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-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1064.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n02i01064ent IS
END c06s04b00x00p03n02i01064ent;
ARCHITECTURE c06s04b00x00p03n02i01064arch OF c06s04b00x00p03n02i01064ent IS
BEGIN
TESTING: PROCESS
type THREE is range 1 to 3;
type ENUM1 is (EN1, EN2, EN3);
type A11 is array (THREE) of BOOLEAN;
type A32 is array (ENUM1, ENUM1) of A11;
variable V1 : BOOLEAN;
variable V32: A32 ;
BEGIN
V1 := V32(EN3)(EN2, 1); -- ONE LESS AND ONE MORE
-- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
-- INDEX POSITIONS IN TYPE DECLARATION
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n02i01064 - The expresion should be the same type as the corresponding index."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n02i01064arch;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.all;
use work.all;
use work.centralRouter_package.all;
--! 8b10b decoder for EPROC_IN2 module
entity EPROC_IN2_DEC8b10b is
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (1 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
busyOut : out std_logic
);
end EPROC_IN2_DEC8b10b;
architecture Behavioral of EPROC_IN2_DEC8b10b is
signal EDATAbitstreamSREG : std_logic_vector (11 downto 0) := (others=>'0'); -- 12 bit (2 x 5 = 10, plus 2 more)
signal word10b_align_array, word10b_align_array_r : word10b_2array_type;
signal word10b : std_logic_vector (9 downto 0) := (others=>'0');
signal comma_valid_bits_or, word10b_align_rdy_r : std_logic;
signal align_select, word10b_rdy : std_logic := '0';
signal comma_valid_bits : std_logic_vector (1 downto 0);
signal alignment_sreg : std_logic_vector (4 downto 0) := (others=>'0');
begin
-------------------------------------------------------------------------------------------
--live bitstream
-- input shift register
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
EDATAbitstreamSREG <= (others => '0');
elsif rising_edge(bitCLK) then
EDATAbitstreamSREG <= edataIN & EDATAbitstreamSREG(11 downto 2);
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock0
-- input shift register mapping into 10 bit registers
-------------------------------------------------------------------------------------------
input_map: for I in 0 to 1 generate -- 1 10bit-word per alignment, 2 possible alignments
--word10b_align_array(I) <= EDATAbitstreamSREG((I+9) downto (I+0)); -- 10 bit word, alligned to bit I
word10b_align_array(I) <= EDATAbitstreamSREG(I+0)&EDATAbitstreamSREG(I+1)&EDATAbitstreamSREG(I+2)&EDATAbitstreamSREG(I+3)&EDATAbitstreamSREG(I+4)&
EDATAbitstreamSREG(I+5)&EDATAbitstreamSREG(I+6)&EDATAbitstreamSREG(I+7)&EDATAbitstreamSREG(I+8)&EDATAbitstreamSREG(I+9); -- 10 bit word, alligned to bit I
end generate input_map;
--
-------------------------------------------------------------------------------------------
--clock0
-- K28.5 comma test
-------------------------------------------------------------------------------------------
comma_test: for I in 0 to 1 generate -- 1 10bit-word per alignment, comma is valid if two first words have comma...
comma_valid_bits(I) <= '1' when (word10b_align_array(I) = COMMAp or word10b_align_array(I) = COMMAn) else '0';
end generate comma_test;
--
comma_valid_bits_or <= comma_valid_bits(1) or comma_valid_bits(0);
--
-------------------------------------------------------------------------------------------
--clock1
-- alignment selector state
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
alignment_sreg <= "00000";
elsif rising_edge(bitCLK) then
if comma_valid_bits_or = '1' then
alignment_sreg <= "10000";
else
alignment_sreg <= alignment_sreg(0) & alignment_sreg(4 downto 1);
end if;
end if;
end process;
--
input_reg1: process(bitCLK)
begin
if rising_edge(bitCLK) then
word10b_align_array_r <= word10b_align_array;
end if;
end process;
--
word10b_align_rdy_r <= alignment_sreg(4);
--
process(bitCLK, rst)
begin
if rst = '1' then
align_select <= '0';
elsif rising_edge(bitCLK) then
if comma_valid_bits_or = '1' then
align_select <= (not comma_valid_bits(0)) and comma_valid_bits(1);
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock2
-- alignment selected
-------------------------------------------------------------------------------------------
--
input_reg2: process(bitCLK)
begin
if rising_edge(bitCLK) then
word10b_rdy <= word10b_align_rdy_r;
end if;
end process;
--
process(bitCLK)
begin
if rising_edge(bitCLK) then
case (align_select) is
when '0' => -- bit0 word got comma => align to bit0
word10b <= word10b_align_array_r(0);
when '1' => -- bit1 word got comma => align to bit1
word10b <= word10b_align_array_r(1);
when others =>
end case;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- at this stage: word10b and word10b_rdy are aligned @ bitCLK
-------------------------------------------------------------------------------------------
EPROC_IN2_ALIGN_BLOCK_inst: entity work.EPROC_IN2_ALIGN_BLOCK
port map(
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst,
bytes => word10b,
bytes_rdy => word10b_rdy,
dataOUT => dataOUT,
dataOUTrdy => dataOUTrdy,
busyOut => busyOut
);
end Behavioral;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:FlagReg:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_FlagReg_1_0 IS
PORT (
IN_FLAG : IN STD_LOGIC;
LD : IN STD_LOGIC;
SET : IN STD_LOGIC;
CLR : IN STD_LOGIC;
CLK : IN STD_LOGIC;
OUT_FLAG : OUT STD_LOGIC
);
END RAT_FlagReg_1_0;
ARCHITECTURE RAT_FlagReg_1_0_arch OF RAT_FlagReg_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_FlagReg_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT FlagReg IS
PORT (
IN_FLAG : IN STD_LOGIC;
LD : IN STD_LOGIC;
SET : IN STD_LOGIC;
CLR : IN STD_LOGIC;
CLK : IN STD_LOGIC;
OUT_FLAG : OUT STD_LOGIC
);
END COMPONENT FlagReg;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_FlagReg_1_0_arch: ARCHITECTURE IS "FlagReg,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_FlagReg_1_0_arch : ARCHITECTURE IS "RAT_FlagReg_1_0,FlagReg,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_FlagReg_1_0_arch: ARCHITECTURE IS "RAT_FlagReg_1_0,FlagReg,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=FlagReg,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : FlagReg
PORT MAP (
IN_FLAG => IN_FLAG,
LD => LD,
SET => SET,
CLR => CLR,
CLK => CLK,
OUT_FLAG => OUT_FLAG
);
END RAT_FlagReg_1_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:FlagReg:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_FlagReg_1_0 IS
PORT (
IN_FLAG : IN STD_LOGIC;
LD : IN STD_LOGIC;
SET : IN STD_LOGIC;
CLR : IN STD_LOGIC;
CLK : IN STD_LOGIC;
OUT_FLAG : OUT STD_LOGIC
);
END RAT_FlagReg_1_0;
ARCHITECTURE RAT_FlagReg_1_0_arch OF RAT_FlagReg_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_FlagReg_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT FlagReg IS
PORT (
IN_FLAG : IN STD_LOGIC;
LD : IN STD_LOGIC;
SET : IN STD_LOGIC;
CLR : IN STD_LOGIC;
CLK : IN STD_LOGIC;
OUT_FLAG : OUT STD_LOGIC
);
END COMPONENT FlagReg;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_FlagReg_1_0_arch: ARCHITECTURE IS "FlagReg,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_FlagReg_1_0_arch : ARCHITECTURE IS "RAT_FlagReg_1_0,FlagReg,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_FlagReg_1_0_arch: ARCHITECTURE IS "RAT_FlagReg_1_0,FlagReg,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=FlagReg,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : FlagReg
PORT MAP (
IN_FLAG => IN_FLAG,
LD => LD,
SET => SET,
CLR => CLR,
CLK => CLK,
OUT_FLAG => OUT_FLAG
);
END RAT_FlagReg_1_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library hwti_common_v1_00_a;
use hwti_common_v1_00_a.common.all;
library plb_hwti_v1_00_a;
use plb_hwti_v1_00_a.all;
library fsl_v20_v2_10_a;
use fsl_v20_v2_10_a.all;
entity plb_hwt_tb is
generic
(
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_MANAG_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_SCHED_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_MUTEX_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_CONDV_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
C_PLB_NUM_MASTERS : integer := 8;
C_PLB_MID_WIDTH : integer := 3;
C_FAMILY : string := "virtex2p"
);
port
(
-- PLB bus interface, do not add or delete
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
Sl_addrAck : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
Sl_MErr : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
Sl_rdBTerm : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdDAck : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rearbitrate : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrDAck : out std_logic;
PLB_abort : in std_logic;
PLB_ABus : in std_logic_vector(0 to C_PLB_AWIDTH-1);
PLB_BE : in std_logic_vector(0 to C_PLB_DWIDTH/8-1);
PLB_busLock : in std_logic;
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_lockErr : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_PLB_MID_WIDTH-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_ordered : in std_logic;
PLB_PAValid : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_pendReq : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdPrim : in std_logic;
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_RNW : in std_logic;
PLB_SAValid : in std_logic;
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrBurst : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_wrPrim : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_compress : out std_logic;
M_guarded : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_ordered : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MErr : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
-- BFM synchronization bus interface
SYNCH_IN : in std_logic_vector(0 to 31) := (others => '0');
SYNCH_OUT : out std_logic_vector(0 to 31) := (others => '0')
);
end entity plb_hwt_tb;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture testbench of plb_hwt_tb is
------------------------------------------
-- Standard constants for bfl/vhdl communication
------------------------------------------
constant NOP : integer := 0;
constant START : integer := 1;
constant STOP : integer := 2;
constant WAIT_IN : integer := 3;
constant WAIT_OUT : integer := 4;
constant ASSERT_IN : integer := 5;
constant ASSERT_OUT : integer := 6;
constant ASSIGN_IN : integer := 7;
constant ASSIGN_OUT : integer := 8;
constant RESET_WDT : integer := 9;
constant INTERRUPT : integer := 31;
------------------------------------------
-- FSL Link Signals To HWTI
------------------------------------------
signal FSL_M_Data : std_logic_vector(0 to 63);
signal FSL_M_Control : std_logic;
signal FSL_M_Write : std_logic;
signal FSL_M_Full : std_logic;
signal FSL_S_Data : std_logic_vector(0 to 63);
signal FSL_S_Control : std_logic;
signal FSL_S_Read : std_logic;
signal FSL_S_Exists : std_logic;
------------------------------------------
-- Signals for the HWTUL
------------------------------------------
signal tid : std_logic_vector(0 to 7);
signal arg : std_logic_vector(0 to 31);
begin
------------------------------------------
-- Instance of the PLB HWTI
------------------------------------------
hwti : entity plb_hwti_v1_00_a.plb_hwti
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
C_MANAG_BASE => C_MANAG_BASEADDR,
C_SCHED_BASE => C_SCHED_BASEADDR,
C_MUTEX_BASE => C_MUTEX_BASEADDR,
C_CONDV_BASE => C_CONDV_BASEADDR,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
C_PLB_NUM_MASTERS => C_PLB_NUM_MASTERS,
C_PLB_MID_WIDTH => C_PLB_MID_WIDTH,
C_FAMILY => C_FAMILY
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
H2ULOW_S_READ => FSL_S_READ,
H2ULOW_S_DATA => FSL_S_DATA(32 to 63),
H2ULOW_S_CONTROL => FSL_S_CONTROL,
H2ULOW_S_EXISTS => FSL_S_EXISTS,
H2UHIGH_S_READ => FSL_S_READ,
H2UHIGH_S_DATA => FSL_S_DATA(0 to 31),
H2UHIGH_S_CONTROL => open,
H2UHIGH_S_EXISTS => open,
U2HLOW_M_WRITE => FSL_M_WRITE,
U2HLOW_M_DATA => FSL_M_DATA(32 to 63),
U2HLOW_M_CONTROL => FSL_M_CONTROL,
U2HLOW_M_FULL => FSL_M_FULL,
U2HHIGH_M_WRITE => FSL_M_WRITE,
U2HHIGH_M_DATA => FSL_M_DATA(0 to 31),
U2HHIGH_M_CONTROL => FSL_M_CONTROL,
U2HHIGH_M_FULL => open,
-- MAP USER PORTS ABOVE THIS LINE ------------------
PLB_Clk => PLB_Clk,
PLB_Rst => PLB_Rst,
Sl_addrAck => Sl_addrAck,
Sl_MBusy => Sl_MBusy,
Sl_MErr => Sl_MErr,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
PLB_abort => PLB_abort,
PLB_ABus => PLB_ABus,
PLB_BE => PLB_BE,
PLB_busLock => PLB_busLock,
PLB_compress => PLB_compress,
PLB_guarded => PLB_guarded,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_ordered => PLB_ordered,
PLB_PAValid => PLB_PAValid,
PLB_pendPri => PLB_pendPri,
PLB_pendReq => PLB_pendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
M_abort => M_abort,
M_ABus => M_ABus,
M_BE => M_BE,
M_busLock => M_busLock,
M_compress => M_compress,
M_guarded => M_guarded,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_ordered => M_ordered,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_RNW => M_RNW,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
PLB_MBusy => PLB_MBusy,
PLB_MErr => PLB_MErr,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MSSize => PLB_MSSize
);
------------------------------------------
-- Zero out the unused synch_out bits
------------------------------------------
SYNCH_OUT(10 to 31) <= (others => '0');
------------------------------------------
-- Test bench code itself
--
-- The test bench itself can be arbitrarily complex and may include
-- hierarchy as the designer sees fit
------------------------------------------
TEST_PROCESS : process
procedure reset is
begin
FSL_M_WRITE <= '0';
FSL_M_CONTROL <= '0';
FSL_M_DATA <= (others => '0');
FSL_S_READ <= '0';
wait for 20 ns;
wait until falling_edge(PLB_Rst);
wait for 20 ns;
assert FALSE report "*** Real simulation starts here ***" severity NOTE;
end procedure;
procedure dostart is
begin
wait until rising_edge(PLB_Clk);
SYNCH_OUT(START) <= '1';
wait until rising_edge(PLB_Clk);
SYNCH_OUT(START) <= '0';
end procedure;
procedure dostop is
begin
wait until rising_edge(SYNCH_IN(STOP));
wait for 1 us;
end procedure;
procedure dowake(signal tid : out std_logic_vector(0 to 7);
signal arg : out std_logic_vector(0 to 31)) is
begin
wait until rising_edge(PLB_Clk) and FSL_S_EXISTS='1';
tid <= FSL_S_DATA(24 to 31);
arg <= FSL_S_DATA(32 to 63);
FSL_S_READ <= '1';
wait until rising_edge(PLB_Clk);
FSL_S_READ <= '0';
end procedure;
procedure dohwti(fsl : std_logic_vector(0 to 63)) is
begin
wait until rising_edge(PLB_Clk) and FSL_M_FULL='0';
FSL_M_WRITE <= '1';
FSL_M_CONTROL <= '0';
FSL_M_DATA <= fsl;
wait until rising_edge(PLB_Clk);
FSL_M_WRITE <= '0';
FSL_M_CONTROL <= '0';
FSL_M_DATA <= (others => '0');
end procedure;
procedure waitres is
begin
wait until rising_edge(PLB_Clk) and FSL_S_EXISTS='1';
FSL_S_READ <= '1';
wait until rising_edge(PLB_Clk);
FSL_S_READ <= '0';
end procedure;
procedure mtx_lock(mtx : in integer) is
begin
dohwti( hwti_mtx_lock(conv_std_logic_vector(mtx,6)) );
end procedure;
procedure mtx_unlock(mtx : in integer) is
begin
dohwti( hwti_mtx_unlock(conv_std_logic_vector(mtx,6)) );
end procedure;
procedure mtx_trylock(mtx : in integer) is
begin
dohwti( hwti_mtx_trylock(conv_std_logic_vector(mtx,6)) );
end procedure;
procedure mtx_owner(mtx : in integer) is
begin
dohwti( hwti_mtx_owner(conv_std_logic_vector(mtx,6)) );
end procedure;
procedure mtx_kind(mtx : in integer) is
begin
dohwti( hwti_mtx_kind(conv_std_logic_vector(mtx,6)) );
end procedure;
procedure mtx_count(mtx : in integer) is
begin
dohwti( hwti_mtx_count(conv_std_logic_vector(mtx,6)) );
end procedure;
procedure cdv_owner(cdv : in integer) is
begin
dohwti( hwti_cdv_owner(conv_std_logic_vector(cdv,6)) );
end procedure;
procedure cdv_wait(cdv : in integer) is
begin
dohwti( hwti_cdv_wait(conv_std_logic_vector(cdv,6)) );
end procedure;
procedure cdv_signal(cdv : in integer) is
begin
dohwti( hwti_cdv_signal(conv_std_logic_vector(cdv,6)) );
end procedure;
procedure cdv_broadcast(cdv : in integer) is
begin
dohwti( hwti_cdv_broadcast(conv_std_logic_vector(cdv,6)) );
end procedure;
procedure man_exit(res : in std_logic_vector(0 to 31)) is
begin
dohwti( hwti_thr_exit(res) );
end procedure;
procedure mem_read(addr : std_logic_vector(0 to 31);
byte : integer) is
begin
dohwti( hwti_mem_read(addr,conv_std_logic_vector(byte,24)) );
end procedure;
procedure mem_write(addr : std_logic_vector(0 to 31);
byte : integer) is
begin
dohwti( hwti_mem_write(addr,conv_std_logic_vector(byte,24)) );
end procedure;
procedure mem_fill( byte : integer ) is
begin
for i in 0 to (byte/8)-1 loop
wait until rising_edge(PLB_Clk) and FSL_M_FULL='0';
FSL_M_WRITE <= '1';
FSL_M_CONTROL <= '0';
FSL_M_DATA <= conv_std_logic_vector(2*i,32) &
conv_std_logic_vector(2*i+1,32);
end loop;
wait until rising_edge(PLB_Clk);
FSL_M_WRITE <= '0';
FSL_M_CONTROL <= '0';
FSL_M_DATA <= (others => '0');
end procedure;
procedure mem_drain( byte : integer ) is
begin
for i in 0 to (byte/8)-1 loop
FSL_S_READ <= '1';
wait until rising_edge(PLB_Clk) and FSL_S_EXISTS='1';
end loop;
wait until rising_edge(PLB_Clk);
FSL_S_READ <= '0';
end procedure;
begin
SYNCH_OUT(NOP) <= '0';
SYNCH_OUT(START) <= '0';
SYNCH_OUT(STOP) <= '0';
SYNCH_OUT(WAIT_IN) <= '0';
SYNCH_OUT(WAIT_OUT) <= '0';
SYNCH_OUT(ASSERT_IN) <= '0';
SYNCH_OUT(ASSERT_OUT) <= '0';
SYNCH_OUT(ASSIGN_IN) <= '0';
SYNCH_OUT(ASSIGN_OUT) <= '0';
SYNCH_OUT(RESET_WDT) <= '0';
------------------------------------------
-- Reset the System
------------------------------------------
reset;
------------------------------------------
-- Setup the memory values
------------------------------------------
assert FALSE report "*** Memory Setup Starting ***" severity NOTE;
dostart;
dostop;
assert FALSE report "*** Memory Setup Finished ***" severity NOTE;
------------------------------------------
-- Setup the Hthreads System
------------------------------------------
assert FALSE report "*** System Setup Starting ***" severity NOTE;
dostart;
dostop;
assert FALSE report "*** System Setup Finished ***" severity NOTE;
------------------------------------------
-- Setup the Hardware Thread
------------------------------------------
assert FALSE report "*** HWT Setup Starting ***" severity NOTE;
dostart;
dostop;
assert FALSE report "*** HWT Setup Finished ***" severity NOTE;
------------------------------------------
-- Wait until we are woken up by the system
------------------------------------------
dowake(tid,arg);
------------------------------------------
-- Attempt to mutex operations
------------------------------------------
assert FALSE report "*** Mutex Operations Starting ***" severity NOTE;
mtx_lock(0); waitres;
mtx_lock(1); waitres;
mtx_lock(2); waitres;
mtx_trylock(2); waitres;
mtx_unlock(2); waitres;
mtx_owner(0); waitres;
mtx_kind(0); waitres;
mtx_count(0); waitres;
assert FALSE report "*** Mutex Operations Finished ***" severity NOTE;
------------------------------------------
-- Attempt condition variable operations
------------------------------------------
assert FALSE report "*** Condition Variables Starting ***" severity NOTE;
cdv_wait(0); wait for 1 us; dostart; dostop; waitres;
cdv_wait(1); wait for 1 us; dostart; dostop; waitres;
cdv_signal(0); waitres;
cdv_signal(1); waitres;
cdv_broadcast(0); waitres;
cdv_broadcast(1); waitres;
assert FALSE report "*** Condition Variables Finished ***" severity NOTE;
------------------------------------------
-- Attempt burst memory read and write
------------------------------------------
mem_read(x"10000000", 256); mem_drain(256);
mem_write(x"20000000", 256); mem_fill(256);
------------------------------------------
-- End the test
------------------------------------------
man_exit(x"CAFEBABE");
wait for 2000 ns;
------------------------------------------
-- Setup the Hthreads System
------------------------------------------
assert FALSE report "*** Starting Results Reading ***" severity NOTE;
dostart;
dostop;
assert FALSE report "*** Finished Results Reading ***" severity NOTE;
wait;
end process TEST_PROCESS;
end architecture testbench;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity univ_bin_counter is
generic(N: natural := 8;
count_max : INTEGER := 8);
port(
clk : in std_logic;
syn_clr, en, up : in std_logic;
clk_en : in std_logic := '1';
qo : out std_logic_vector(N-1 downto 0)
);
end univ_bin_counter;
architecture arch of univ_bin_counter is
signal count : integer := 0;
--signal r_reg : unsigned(N-1 downto 0);
--signal r_next : unsigned(N-1 downto 0);
begin
-- register--
-- process(clk, syn_clr)
-- begin
-- if (syn_clr='1') then
-- r_reg <= (others=>'0');
-- elsif rising_edge(clk) and clk_en = '1' then
-- r_reg <= r_next;
-- end if;
-- end process;
process(clk, en, syn_clr, up, count)
begin
if rising_edge(clk) then
if syn_clr = '1' then
count <= 0;
elsif up = '1' and en = '1' then
count <= count + 1;
elsif up = '0' and en = '1' then
count <= count - 1;
end if;
if up = '1' and count = count_max then
count <= 0;
elsif up = '0' and count = 0 then
count <= count_max;
end if;
end if;
end process;
-- next-state logic--
-- r_next <= (others=>'0') when syn_clr='1' else
-- "00000000" when r_reg = "00001000" and en='1' and up='1' else
-- "00001000" when r_reg = "00000000" and en='1' and up='0' else
-- r_reg + 1 when en ='1' and up='1' else
-- r_reg - 1 when en ='1' and up='0' else
-- r_reg;
-- output logic--
process(count)
begin
case (count) is
when 0 => qo <= X"07";
when 1 => qo <= X"0F";
when 2 => qo <= X"17";
when 3 => qo <= X"1F";
when 4 => qo <= X"27";
when 5 => qo <= X"2F";
when 6 => qo <= X"37";
when 7 => qo <= X"3F";
when 8 => qo <= X"47";
when others => qo <= X"3F";
end case;
end process;
end arch;
|
------------------------------------------------------------------------------
---- ----
---- Tewb_stbench for the ZPU Wishbone bridge ----
---- ----
---- Description: ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Koen Martens, gmc sonologic.nl ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c)
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit:
---- File name:
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA:
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: N/A ----
---- Simulation tools:
---- Text editor:
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library zpu;
use zpu.wishbone.all;
library wb_slaves;
use wb_slaves.tutorial.all;
entity zpu_wishbone_WBOPRT08_tb is
end entity zpu_wishbone_WBOPRT08_tb;
architecture Behave of zpu_wishbone_WBOPRT08_tb is
constant DATA_WIDTH : natural:=8; -- 32 bits data path
constant ADR_MSB : natural:=31;
constant ADR_LSB : natural:=2;
constant D_CARE_VAL : std_logic:='0'; -- Fill value
constant CLK_FREQ : positive:=50; -- 50 MHz clock
constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period
-- tewb_stbench
signal break : std_logic:='0';
signal gpio : std_logic_vector(7 downto 0);
--
signal clk : std_logic;
signal dat_i : std_logic_vector(DATA_WIDTH-1 downto 0);
signal dat_o : std_logic_vector(DATA_WIDTH-1 downto 0);
signal rst : std_logic;
-- data tagging
signal tgd_i : std_logic_vector(DATA_WIDTH-1 downto 0);
signal tgd_o : std_logic_vector(DATA_WIDTH-1 downto 0);
-- MASTER signals
signal wb_ack : std_logic;
signal adr_o : std_logic_vector(ADR_MSB downto ADR_LSB);
signal cyc_o : std_logic;
signal stall_i : std_logic;
signal err_i : std_logic;
signal lock_o : std_logic;
signal rty_i : std_logic;
signal sel_o : std_logic_vector(DATA_WIDTH-1 downto 0);
signal wb_stb : std_logic;
signal tga_o : std_logic_vector(ADR_MSB downto ADR_LSB);
signal tgc_o : std_logic_vector(DATA_WIDTH-1 downto 0); -- size correct?
signal wb_we : std_logic;
begin
wb_br : zpu_wishbone_bridge
generic map(
DATA_WIDTH => DATA_WIDTH,
ADR_MSB => ADR_MSB,
ADR_LSB => ADR_LSB
)
port map(
clk_i => clk,
dat_i => dat_i,
dat_o => dat_o,
rst_i => rst,
tgd_i => tgd_i,
tgd_o => tgd_o,
ack_i => wb_ack,
cyc_o => cyc_o,
stall_i => stall_i,
err_i => err_i,
lock_o => lock_o,
rty_i => rty_i,
sel_o => sel_o,
stb_o => wb_stb,
tga_o => tga_o,
tgc_o => tgc_o,
we_o => wb_we
);
wb_slave : WBOPRT08
port map(
-- wishbone bus
ACK_O => wb_ack,
CLK_I => clk,
DAT_I => dat_i,
DAT_O => dat_o,
RST_I => rst,
STB_I => wb_stb,
WE_I => wb_we,
-- output port
PRT_O => gpio
);
do_clock:
process
begin
clk <= '0';
wait for CLK_S_PER;
clk <= '1';
wait for CLK_S_PER;
if break='1' then
-- print("* Break asserted, end of test");
wait;
end if;
end process do_clock;
do_reset:
process
begin
wait until rising_edge(clk);
rst <= '0';
wait for 9.2345 us;
rst <= '1';
wait for 9.395 us;
rst <= '0';
end process do_reset;
end architecture Behave; -- Entity: zpu_wishbone_WBOPRT08_tb
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000 -- frequency of main clock (used for PLLs)
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
-- Shared bus
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(31 downto 0);
-- SRAM
ramsn : out std_ulogic;
ramoen : out std_ulogic;
rwen : out std_ulogic;
mben : out std_logic_vector(3 downto 0);
-- pragma translate_off
iosn : out std_ulogic;
-- pragma translate_on
-- FLASH
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
byten : out std_ulogic;
wpn : out std_ulogic;
sa : out std_logic_vector(11 downto 0);
sd : inout std_logic_vector(31 downto 0);
sdclk : out std_ulogic;
sdcke : out std_logic; -- sdram clock enable
sdcsn : out std_logic; -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
sdba : out std_logic_vector(1 downto 0); -- sdram bank address
-- debug support unit
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- console UART
rxd1 : in std_ulogic;
txd1 : out std_ulogic;
-- for smsc lan chip
eth_aen : out std_logic;
eth_readn : out std_logic;
eth_writen: out std_logic;
eth_nbe : out std_logic_vector(3 downto 0);
eth_lclk : out std_ulogic;
eth_nads : out std_logic;
eth_ncycle : out std_logic;
eth_wnr : out std_logic;
eth_nvlbus : out std_logic;
eth_nrdyrtn : out std_logic;
eth_ndatacs : out std_logic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0) -- I/O port
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2 : sdctrl_out_type;
--for smc lan chip
signal s_eth_aen : std_logic;
signal s_eth_readn : std_logic;
signal s_eth_writen: std_logic;
signal s_eth_nbe : std_logic_vector(3 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, sdclkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
constant IOAEN : integer := 1;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN ;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
signal dsubre : std_ulogic;
component smc_mctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2;
oepol : integer := 0;
syncrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type;
eth_aen : out std_ulogic; -- for smsc lan chip
eth_readn : out std_ulogic; -- for smsc lan chip
eth_writen: out std_ulogic; -- for smsc lan chip
eth_nbe : out std_logic_vector(3 downto 0) -- for smsc lan chip
);
end component;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => CFG_MCTRL_SDEN,
noclkfb => CFG_CLK_NOFB, freq => freq)
port map (clkin => clk, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => sdclkl, pciclk => open,
cgi => cgi, cgo => cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24) port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 : if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, gnd(0), gnd(0), gnd(0), open, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo2);
apbo(0) <= apb_none;
end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 2, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo,
s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 12) port map (sa, memo.sa(11 downto 0));
sdba_pad : outpadv generic map (width => 2) port map (sdba, memo.sa(14 downto 13));
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>4, tech => padtech)
port map (sddqm, sdo.dqm(3 downto 0));
end generate;
sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, sdo.sdcke(0));
sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, sdo.sdcsn(0));
end generate;
wpn <= '1'; byten <= '0';
nosd0 : if (CFG_MCTRL_LEON2 = 0) generate -- no SDRAM controller
sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, vcc(0));
sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, vcc(0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
mg0 : if not ((CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1)) generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpad generic map (tech => padtech)
port map (ramsn, vcc(0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (address, memo.address(23 downto 0));
memb_pad : outpadv generic map (width => 4, tech => padtech)
port map (mben, memo.mben);
rams_pad : outpad generic map (tech => padtech)
port map (ramsn, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpad generic map (tech => padtech)
port map (rwen, memo.wrn(0));
roen_pad : outpad generic map (tech => padtech)
port map (ramoen, memo.ramoen(0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- pragma translate_on
-- for smc lan chip
eth_aen_pad : outpad generic map (tech => padtech)
port map (eth_aen, s_eth_aen);
eth_readn_pad : outpad generic map (tech => padtech)
port map (eth_readn, s_eth_readn);
eth_writen_pad : outpad generic map (tech => padtech)
port map (eth_writen, s_eth_writen);
eth_nbe_pad : outpadv generic map (width => 4, tech => padtech)
port map (eth_nbe, s_eth_nbe);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-- invert signal for input via a key
dsubre <= not dsubren;
-- for smc lan chip
eth_lclk <= vcc(0);
eth_nads <= gnd(0);
eth_ncycle <= vcc(0);
eth_wnr <= vcc(0);
eth_nvlbus <= vcc(0);
eth_nrdyrtn <= vcc(0);
eth_ndatacs <= vcc(0);
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP2C60 SDR Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (4);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4;
constant CFG_ATBSZ : integer := 4;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020765#;
constant CFG_ETH_ENL : integer := 16#003456#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 0;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (16);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (128);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 1;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 16;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 1;
constant CFG_SVGA_ENABLE : integer := 0;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 1;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#03#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (1);
constant CFG_SPIMCTRL_ASCALER : integer := (8);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (30000);
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY midi_tb IS
END midi_tb;
ARCHITECTURE behavior OF midi_tb IS
-- Component Declaration for the Unit Under Test (UUT)
component midi is
port (
-- clk must be a 31.25Hz clock
clk : in std_logic;
load : in std_logic;
data_in : in std_logic_vector(7 downto 0);
midi_out : out std_logic := '0';
ready : out std_logic := '1'
);
end component;
--Inputs
signal value : std_logic_vector(7 downto 0) := (others => '0');
signal load : std_logic := '0';
signal clk : std_logic := '0';
signal midi_out : std_logic;
signal ready : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: midi port map (
clk => clk,
load => load,
data_in => value,
midi_out => midi_out,
ready => ready
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
variable byte : integer range 0 to 40 := 0;
variable load_value : boolean := false;
begin
wait for clk_period / 2;
loop
wait for clk_period;
if ready = '1' then
if load_value then
load <= '1' after 1ns;
load_value := false;
else
load <= '0' after 1ns;
if byte = 0 then
value <= "10010000" after 1ns;
byte := 1;
load_value := true;
elsif byte = 1 then
value <= "01000101" after 1ns;
byte := 2;
load_value := true;
elsif byte = 2 then
value <= "01000101" after 1ns;
byte := 3;
load_value := true;
elsif byte = 39 then
byte := 0;
else
byte := byte + 1;
end if;
end if;
else
load <= '0' after 1ns;
end if;
end loop;
wait;
end process;
END;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity blinkoflow is
generic (data_bits : integer := 14;
mon_bits : integer := 4;
count_bits : integer := 25);
port (d : in signed(data_bits - 1 downto 0);
good : out std_logic;
bad : out std_logic;
clk : in std_logic);
end blinkoflow;
architecture blinkoflow of blinkoflow is
signal counter : unsigned (count_bits - 1 downto 0);
signal oflow : boolean;
constant twiddle : signed(data_bits - 1 downto 0) := (
data_bits - 1 => '1', others => '0');
begin
process
variable ud : signed(data_bits - 1 downto 0);
begin
wait until rising_edge(clk);
good <= counter(count_bits - 1);
bad <= not counter(count_bits - 1);
ud := d xor twiddle;
oflow <= ud(data_bits - 1 downto data_bits - mon_bits + 1)
= ud(data_bits - 2 downto data_bits - mon_bits);
if oflow then
counter <= (others => '0');
elsif counter(count_bits - 1) = '0' then
counter <= counter + 1;
end if;
end process;
end blinkoflow;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_signed.ALL;
ENTITY quad_bit_alu IS
port(
a: IN SIGNED (3 DOWNTO 0);
b: IN SIGNED (3 DOWNTO 0);
s: IN UNSIGNED (2 DOWNTO 0);
z: OUT std_logic;
r: OUT SIGNED (7 DOWNTO 0)
);
END quad_bit_alu;
ARCHITECTURE alu OF quad_bit_alu IS
SIGNAL a_pad: SIGNED (7 DOWNTO 0);
SIGNAL b_pad: SIGNED (7 DOWNTO 0);
SIGNAL r_buff: SIGNED (7 DOWNTO 0);
BEGIN
-- Pad A
pad_a: PROCESS(a)
VARIABLE sign : std_logic;
BEGIN
sign:= a(3);
IF (sign = '0') THEN
a_pad <= ("0000" & a);
ELSIF (sign = '1') THEN
a_pad <= ("1111" & a);
ELSE
a_pad <= "00000000";
END IF;
END PROCESS pad_a;
-- Pad B
pad_b: PROCESS(b)
VARIABLE sign : std_logic;
BEGIN
sign:= b(3);
IF (sign = '0') THEN
b_pad <= ("0000" & b);
ELSIF (sign = '1') THEN
b_pad <= ("1111" & b);
ELSE
b_pad <= "00000000";
END IF;
END PROCESS pad_b;
-- Main ALU process
op_select: PROCESS(s, a_pad, b_pad, a, b)
BEGIN
CASE s IS
WHEN "000" => r_buff <= (a_pad AND b_pad);
WHEN "001" => r_buff <= (a_pad OR b_pad);
WHEN "010" => r_buff <= (a_pad XOR b_pad);
WHEN "011" => r_buff <= (NOT a_pad);
WHEN "100" => r_buff <= (a_pad + b_pad);
WHEN "101" => r_buff <= (a_pad - b_pad);
WHEN "110" => r_buff <= (a * b);
WHEN "111" => r_buff <= (NOT(a_pad) + "00000001");
WHEN OTHERS => r_buff <= "00000000";
END CASE;
END PROCESS op_select;
-- Handle zero out condition
zero_out:PROCESS (r_buff)
BEGIN
CASE r_buff IS
WHEN "00000000" => z <= '1';
WHEN others => z <= '0';
END CASE;
r <= r_buff;
END PROCESS zero_out;
END alu; |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.types.all; use ocpi.wci.all;
package worker is
type control_in_t is record
clk : std_logic;
reset : bool_t;
control_op : control_op_t; -- what control op is in progress?
state : state_t; -- the current control state
is_operating : bool_t; -- convenience signal for "in operating state in"
is_big_endian : bool_t;
end record control_in_t;
type control_out_t is record
done : bool_t; -- worker indicates completion of control/config
attention : bool_t; -- worker indicates it needs attention
abort_control_op : bool_t;
end record control_out_t;
end package worker;
|
-- created based on http://neil.franklin.ch/Info_Texts/Instruction_Set_8080
-- 20|30: unused in 8080, RIM and SIM only in 8085
-- 40|49|52|5B|64|6D|7F: are all NOPs
-- 76: would be MOV M,M (3 cycle NOP) but used for HLT
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package opcodes is
constant opcNOP : std_logic_vector(7 downto 0) := X"00";
constant opcLXI_B : std_logic_vector(7 downto 0) := X"01"; -- nnnn
constant opcSTAX_B : std_logic_vector(7 downto 0) := X"02";
constant opcINX_B : std_logic_vector(7 downto 0) := X"03";
constant opcINR_B : std_logic_vector(7 downto 0) := X"04";
constant opcDCR_B : std_logic_vector(7 downto 0) := X"05";
constant opcMVI_B : std_logic_vector(7 downto 0) := X"06"; -- nn
constant opcRLC : std_logic_vector(7 downto 0) := X"07";
constant opcDAD_B : std_logic_vector(7 downto 0) := X"09";
constant opcLDAX_B : std_logic_vector(7 downto 0) := X"0A";
constant opcDCX_B : std_logic_vector(7 downto 0) := X"0B";
constant opcINR_C : std_logic_vector(7 downto 0) := X"0C";
constant opcDCR_C : std_logic_vector(7 downto 0) := X"0D";
constant opcMVI_C : std_logic_vector(7 downto 0) := X"0E"; -- nn
constant opcRRC : std_logic_vector(7 downto 0) := X"0F";
constant opcLXI_D : std_logic_vector(7 downto 0) := X"11"; -- nnnn
constant opcSTAX_D : std_logic_vector(7 downto 0) := X"12";
constant opcINX_D : std_logic_vector(7 downto 0) := X"13";
constant opcINR_D : std_logic_vector(7 downto 0) := X"14";
constant opcDCR_D : std_logic_vector(7 downto 0) := X"15";
constant opcMVI_D : std_logic_vector(7 downto 0) := X"16"; -- nn
constant opcRAL : std_logic_vector(7 downto 0) := X"17";
constant opcDAD_D : std_logic_vector(7 downto 0) := X"19";
constant opcLDAX_D : std_logic_vector(7 downto 0) := X"1A";
constant opcDCX_D : std_logic_vector(7 downto 0) := X"1B";
constant opcINR_E : std_logic_vector(7 downto 0) := X"1C";
constant opcDCR_E : std_logic_vector(7 downto 0) := X"1D";
constant opcMVI_E : std_logic_vector(7 downto 0) := X"1E"; -- nn
constant opcRAR : std_logic_vector(7 downto 0) := X"1F";
constant opcRIM : std_logic_vector(7 downto 0) := X"20";
constant opcLXI_H : std_logic_vector(7 downto 0) := X"21"; -- nnnn
constant opcSHLD : std_logic_vector(7 downto 0) := X"22"; -- nnnn
constant opcINX_H : std_logic_vector(7 downto 0) := X"23";
constant opcINR_H : std_logic_vector(7 downto 0) := X"24";
constant opcDCR_H : std_logic_vector(7 downto 0) := X"25";
constant opcMVI_H : std_logic_vector(7 downto 0) := X"26"; -- nn
constant opcDAA : std_logic_vector(7 downto 0) := X"27";
constant opcDAD_H : std_logic_vector(7 downto 0) := X"29";
constant opcLHLD : std_logic_vector(7 downto 0) := X"2A"; -- nnnn
constant opcDCX_H : std_logic_vector(7 downto 0) := X"2B";
constant opcINR_L : std_logic_vector(7 downto 0) := X"2C";
constant opcDCR_L : std_logic_vector(7 downto 0) := X"2D";
constant opcMVI_L : std_logic_vector(7 downto 0) := X"2E"; -- nn
constant opcCMA : std_logic_vector(7 downto 0) := X"2F";
constant opcSIM : std_logic_vector(7 downto 0) := X"30";
constant opcLXI_SP : std_logic_vector(7 downto 0) := X"31"; -- nnnn
constant opcSTA : std_logic_vector(7 downto 0) := X"32"; -- nnnn
constant opcINX_SP : std_logic_vector(7 downto 0) := X"33";
constant opcINR_M : std_logic_vector(7 downto 0) := X"34";
constant opcDCR_M : std_logic_vector(7 downto 0) := X"35";
constant opcMVI_M : std_logic_vector(7 downto 0) := X"36"; -- nn
constant opcSTC : std_logic_vector(7 downto 0) := X"37";
constant opcDAD_SP : std_logic_vector(7 downto 0) := X"39";
constant opcLDA : std_logic_vector(7 downto 0) := X"3A"; -- nnnn
constant opcDCX_SP : std_logic_vector(7 downto 0) := X"3B";
constant opcINR_A : std_logic_vector(7 downto 0) := X"3C";
constant opcDCR_A : std_logic_vector(7 downto 0) := X"3D";
constant opcMVI_A : std_logic_vector(7 downto 0) := X"3E"; -- nn
constant opcCMC : std_logic_vector(7 downto 0) := X"3F";
constant opcMOV_B_B : std_logic_vector(7 downto 0) := X"40";
constant opcMOV_B_C : std_logic_vector(7 downto 0) := X"41";
constant opcMOV_B_D : std_logic_vector(7 downto 0) := X"42";
constant opcMOV_B_E : std_logic_vector(7 downto 0) := X"43";
constant opcMOV_B_H : std_logic_vector(7 downto 0) := X"44";
constant opcMOV_B_L : std_logic_vector(7 downto 0) := X"45";
constant opcMOV_B_M : std_logic_vector(7 downto 0) := X"46";
constant opcMOV_B_A : std_logic_vector(7 downto 0) := X"47";
constant opcMOV_C_B : std_logic_vector(7 downto 0) := X"48";
constant opcMOV_C_C : std_logic_vector(7 downto 0) := X"49";
constant opcMOV_C_D : std_logic_vector(7 downto 0) := X"4A";
constant opcMOV_C_E : std_logic_vector(7 downto 0) := X"4B";
constant opcMOV_C_H : std_logic_vector(7 downto 0) := X"4C";
constant opcMOV_C_L : std_logic_vector(7 downto 0) := X"4D";
constant opcMOV_C_M : std_logic_vector(7 downto 0) := X"4E";
constant opcMOV_C_A : std_logic_vector(7 downto 0) := X"4F";
constant opcMOV_D_B : std_logic_vector(7 downto 0) := X"50";
constant opcMOV_D_C : std_logic_vector(7 downto 0) := X"51";
constant opcMOV_D_D : std_logic_vector(7 downto 0) := X"52";
constant opcMOV_D_E : std_logic_vector(7 downto 0) := X"53";
constant opcMOV_D_H : std_logic_vector(7 downto 0) := X"54";
constant opcMOV_D_L : std_logic_vector(7 downto 0) := X"55";
constant opcMOV_D_M : std_logic_vector(7 downto 0) := X"56";
constant opcMOV_D_A : std_logic_vector(7 downto 0) := X"57";
constant opcMOV_E_B : std_logic_vector(7 downto 0) := X"58";
constant opcMOV_E_C : std_logic_vector(7 downto 0) := X"59";
constant opcMOV_E_D : std_logic_vector(7 downto 0) := X"5A";
constant opcMOV_E_E : std_logic_vector(7 downto 0) := X"5B";
constant opcMOV_E_H : std_logic_vector(7 downto 0) := X"5C";
constant opcMOV_E_L : std_logic_vector(7 downto 0) := X"5D";
constant opcMOV_E_M : std_logic_vector(7 downto 0) := X"5E";
constant opcMOV_E_A : std_logic_vector(7 downto 0) := X"5F";
constant opcMOV_H_B : std_logic_vector(7 downto 0) := X"60";
constant opcMOV_H_C : std_logic_vector(7 downto 0) := X"61";
constant opcMOV_H_D : std_logic_vector(7 downto 0) := X"62";
constant opcMOV_H_E : std_logic_vector(7 downto 0) := X"63";
constant opcMOV_H_H : std_logic_vector(7 downto 0) := X"64";
constant opcMOV_H_L : std_logic_vector(7 downto 0) := X"65";
constant opcMOV_H_M : std_logic_vector(7 downto 0) := X"66";
constant opcMOV_H_A : std_logic_vector(7 downto 0) := X"67";
constant opcMOV_L_B : std_logic_vector(7 downto 0) := X"68";
constant opcMOV_L_C : std_logic_vector(7 downto 0) := X"69";
constant opcMOV_L_D : std_logic_vector(7 downto 0) := X"6A";
constant opcMOV_L_E : std_logic_vector(7 downto 0) := X"6B";
constant opcMOV_L_H : std_logic_vector(7 downto 0) := X"6C";
constant opcMOV_L_L : std_logic_vector(7 downto 0) := X"6D";
constant opcMOV_L_M : std_logic_vector(7 downto 0) := X"6E";
constant opcMOV_L_A : std_logic_vector(7 downto 0) := X"6F";
constant opcMOV_M_B : std_logic_vector(7 downto 0) := X"70";
constant opcMOV_M_C : std_logic_vector(7 downto 0) := X"71";
constant opcMOV_M_D : std_logic_vector(7 downto 0) := X"72";
constant opcMOV_M_E : std_logic_vector(7 downto 0) := X"73";
constant opcMOV_M_H : std_logic_vector(7 downto 0) := X"74";
constant opcMOV_M_L : std_logic_vector(7 downto 0) := X"75";
constant opcHLT : std_logic_vector(7 downto 0) := X"76";
constant opcMOV_M_A : std_logic_vector(7 downto 0) := X"77";
constant opcMOV_A_B : std_logic_vector(7 downto 0) := X"78";
constant opcMOV_A_C : std_logic_vector(7 downto 0) := X"79";
constant opcMOV_A_D : std_logic_vector(7 downto 0) := X"7A";
constant opcMOV_A_E : std_logic_vector(7 downto 0) := X"7B";
constant opcMOV_A_H : std_logic_vector(7 downto 0) := X"7C";
constant opcMOV_A_L : std_logic_vector(7 downto 0) := X"7D";
constant opcMOV_A_M : std_logic_vector(7 downto 0) := X"7E";
constant opcMOV_A_A : std_logic_vector(7 downto 0) := X"7F";
constant opcADD_B : std_logic_vector(7 downto 0) := X"80";
constant opcADD_C : std_logic_vector(7 downto 0) := X"81";
constant opcADD_D : std_logic_vector(7 downto 0) := X"82";
constant opcADD_E : std_logic_vector(7 downto 0) := X"83";
constant opcADD_H : std_logic_vector(7 downto 0) := X"84";
constant opcADD_L : std_logic_vector(7 downto 0) := X"85";
constant opcADD_M : std_logic_vector(7 downto 0) := X"86";
constant opcADD_A : std_logic_vector(7 downto 0) := X"87";
constant opcADC_B : std_logic_vector(7 downto 0) := X"88";
constant opcADC_C : std_logic_vector(7 downto 0) := X"89";
constant opcADC_D : std_logic_vector(7 downto 0) := X"8A";
constant opcADC_E : std_logic_vector(7 downto 0) := X"8B";
constant opcADC_H : std_logic_vector(7 downto 0) := X"8C";
constant opcADC_L : std_logic_vector(7 downto 0) := X"8D";
constant opcADC_M : std_logic_vector(7 downto 0) := X"8E";
constant opcADC_A : std_logic_vector(7 downto 0) := X"8F";
constant opcSUB_B : std_logic_vector(7 downto 0) := X"90";
constant opcSUB_C : std_logic_vector(7 downto 0) := X"91";
constant opcSUB_D : std_logic_vector(7 downto 0) := X"92";
constant opcSUB_E : std_logic_vector(7 downto 0) := X"93";
constant opcSUB_H : std_logic_vector(7 downto 0) := X"94";
constant opcSUB_L : std_logic_vector(7 downto 0) := X"95";
constant opcSUB_M : std_logic_vector(7 downto 0) := X"96";
constant opcSUB_A : std_logic_vector(7 downto 0) := X"97";
constant opcSBB_B : std_logic_vector(7 downto 0) := X"98";
constant opcSBB_C : std_logic_vector(7 downto 0) := X"99";
constant opcSBB_D : std_logic_vector(7 downto 0) := X"9A";
constant opcSBB_E : std_logic_vector(7 downto 0) := X"9B";
constant opcSBB_H : std_logic_vector(7 downto 0) := X"9C";
constant opcSBB_L : std_logic_vector(7 downto 0) := X"9D";
constant opcSBB_M : std_logic_vector(7 downto 0) := X"9E";
constant opcSBB_A : std_logic_vector(7 downto 0) := X"9F";
constant opcANA_B : std_logic_vector(7 downto 0) := X"A0";
constant opcANA_C : std_logic_vector(7 downto 0) := X"A1";
constant opcANA_D : std_logic_vector(7 downto 0) := X"A2";
constant opcANA_E : std_logic_vector(7 downto 0) := X"A3";
constant opcANA_H : std_logic_vector(7 downto 0) := X"A4";
constant opcANA_L : std_logic_vector(7 downto 0) := X"A5";
constant opcANA_M : std_logic_vector(7 downto 0) := X"A6";
constant opcANA_A : std_logic_vector(7 downto 0) := X"A7";
constant opcXRA_B : std_logic_vector(7 downto 0) := X"A8";
constant opcXRA_C : std_logic_vector(7 downto 0) := X"A9";
constant opcXRA_D : std_logic_vector(7 downto 0) := X"AA";
constant opcXRA_E : std_logic_vector(7 downto 0) := X"AB";
constant opcXRA_H : std_logic_vector(7 downto 0) := X"AC";
constant opcXRA_L : std_logic_vector(7 downto 0) := X"AD";
constant opcXRA_M : std_logic_vector(7 downto 0) := X"AE";
constant opcXRA_A : std_logic_vector(7 downto 0) := X"AF";
constant opcORA_B : std_logic_vector(7 downto 0) := X"B0";
constant opcORA_C : std_logic_vector(7 downto 0) := X"B1";
constant opcORA_D : std_logic_vector(7 downto 0) := X"B2";
constant opcORA_E : std_logic_vector(7 downto 0) := X"B3";
constant opcORA_H : std_logic_vector(7 downto 0) := X"B4";
constant opcORA_L : std_logic_vector(7 downto 0) := X"B5";
constant opcORA_M : std_logic_vector(7 downto 0) := X"B6";
constant opcORA_A : std_logic_vector(7 downto 0) := X"B7";
constant opcCMP_B : std_logic_vector(7 downto 0) := X"B8";
constant opcCMP_C : std_logic_vector(7 downto 0) := X"B9";
constant opcCMP_D : std_logic_vector(7 downto 0) := X"BA";
constant opcCMP_E : std_logic_vector(7 downto 0) := X"BB";
constant opcCMP_H : std_logic_vector(7 downto 0) := X"BC";
constant opcCMP_L : std_logic_vector(7 downto 0) := X"BD";
constant opcCMP_M : std_logic_vector(7 downto 0) := X"BE";
constant opcCMP_A : std_logic_vector(7 downto 0) := X"BF";
constant opcRNZ : std_logic_vector(7 downto 0) := X"C0";
constant opcPOP_B : std_logic_vector(7 downto 0) := X"C1";
constant opcJNZ : std_logic_vector(7 downto 0) := X"C2"; -- nnnn
constant opcJMP : std_logic_vector(7 downto 0) := X"C3"; -- nnnn
constant opcCNZ : std_logic_vector(7 downto 0) := X"C4"; -- nnnn
constant opcPUSH_B : std_logic_vector(7 downto 0) := X"C5";
constant opcADI : std_logic_vector(7 downto 0) := X"C6"; -- nn
constant opcRST_0 : std_logic_vector(7 downto 0) := X"C7";
constant opcRZ : std_logic_vector(7 downto 0) := X"C8";
constant opcRET : std_logic_vector(7 downto 0) := X"C9";
constant opcJZ : std_logic_vector(7 downto 0) := X"CA"; -- nnnn
constant opcCZ : std_logic_vector(7 downto 0) := X"CC"; -- nnnn
constant opcCALL : std_logic_vector(7 downto 0) := X"CD"; -- nnnn
constant opcACI : std_logic_vector(7 downto 0) := X"CE"; -- nn
constant opcRST_1 : std_logic_vector(7 downto 0) := X"CF";
constant opcRNC : std_logic_vector(7 downto 0) := X"D0";
constant opcPOP_D : std_logic_vector(7 downto 0) := X"D1";
constant opcJNC : std_logic_vector(7 downto 0) := X"D2"; -- nnnn
constant opcOUT : std_logic_vector(7 downto 0) := X"D3"; -- nn
constant opcCNC : std_logic_vector(7 downto 0) := X"D4"; -- nnnn
constant opcPUSH_D : std_logic_vector(7 downto 0) := X"D5";
constant opcSUI : std_logic_vector(7 downto 0) := X"D6"; -- nn
constant opcRST_2 : std_logic_vector(7 downto 0) := X"D7";
constant opcRC : std_logic_vector(7 downto 0) := X"D8";
constant opcJC : std_logic_vector(7 downto 0) := X"DA"; -- nnnn
constant opcIN : std_logic_vector(7 downto 0) := X"DB"; -- nn
constant opcCC : std_logic_vector(7 downto 0) := X"DC"; -- nnnn
constant opcSBI : std_logic_vector(7 downto 0) := X"DE"; -- nn
constant opcRST_3 : std_logic_vector(7 downto 0) := X"DF";
constant opcRPO : std_logic_vector(7 downto 0) := X"E0";
constant opcPOP_H : std_logic_vector(7 downto 0) := X"E1";
constant opcJPO : std_logic_vector(7 downto 0) := X"E2"; -- nnnn
constant opcXTHL : std_logic_vector(7 downto 0) := X"E3";
constant opcCPO : std_logic_vector(7 downto 0) := X"E4"; -- nnnn
constant opcPUSH_H : std_logic_vector(7 downto 0) := X"E5";
constant opcANI : std_logic_vector(7 downto 0) := X"E6"; -- nn
constant opcRST_4 : std_logic_vector(7 downto 0) := X"E7";
constant opcRPE : std_logic_vector(7 downto 0) := X"E8";
constant opcPCHL : std_logic_vector(7 downto 0) := X"E9";
constant opcJPE : std_logic_vector(7 downto 0) := X"EA"; -- nnnn
constant opcXCHG : std_logic_vector(7 downto 0) := X"EB";
constant opcCPE : std_logic_vector(7 downto 0) := X"EC"; -- nnnn
constant opcXRI : std_logic_vector(7 downto 0) := X"EE"; -- nn
constant opcRST_5 : std_logic_vector(7 downto 0) := X"EF";
constant opcRP : std_logic_vector(7 downto 0) := X"F0";
constant opcPOP_PSW : std_logic_vector(7 downto 0) := X"F1";
constant opcJP : std_logic_vector(7 downto 0) := X"F2"; -- nnnn
constant opcDI : std_logic_vector(7 downto 0) := X"F3";
constant opcCP : std_logic_vector(7 downto 0) := X"F4"; -- nnnn
constant opcPUSH_PSW : std_logic_vector(7 downto 0) := X"F5";
constant opcORI : std_logic_vector(7 downto 0) := X"F6"; -- nn
constant opcRST_6 : std_logic_vector(7 downto 0) := X"F7";
constant opcRM : std_logic_vector(7 downto 0) := X"F8";
constant opcSPHL : std_logic_vector(7 downto 0) := X"F9";
constant opcJM : std_logic_vector(7 downto 0) := X"FA"; -- nnnn
constant opcEI : std_logic_vector(7 downto 0) := X"FB";
constant opcCM : std_logic_vector(7 downto 0) := X"FC"; -- nnnn
constant opcCPI : std_logic_vector(7 downto 0) := X"FE"; -- nn
constant opcRST_7 : std_logic_vector(7 downto 0) := X"FF";
end opcodes;
package body opcodes is
end opcodes; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:51:44 07/06/2016
-- Design Name:
-- Module Name: keyboard-main - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity keyboard_main is
Port ( scancode : out STD_LOGIC_VECTOR(7 downto 0);
ready : out STD_LOGIC;
kbclk : in STD_LOGIC;
kbdata : in STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC);
end keyboard_main;
architecture Behavioral of keyboard_main is
component RF_fetch is port (
kbclk : in STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC;
rf : out STD_LOGIC);
end component;
component scanner is port (
clk : in STD_LOGIC;
rf : in STD_LOGIC;
kbdata : in STD_LOGIC;
reset : in STD_LOGIC;
ready : out STD_LOGIC;
scancode : out STD_LOGIC_VECTOR(7 downto 0));
end component;
signal rf: STD_LOGIC;
begin
rf_fetch0: RF_fetch port map (kbclk, reset, clk, rf);
scanner0 : scanner port map (clk, rf, kbdata, reset, ready, scancode);
end Behavioral;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic;
-- Checker outputs
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info_in,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal : out std_logic
);
end FIFO_credit_based;
architecture behavior of FIFO_credit_based is
component FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic;
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
fake_credit: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
fake_credit_counter_in: in std_logic_vector(1 downto 0);
state_out: in std_logic_vector(4 downto 0);
state_in: in std_logic_vector(4 downto 0);
fault_info: in std_logic;
fault_info_out: in std_logic;
fault_info_in: in std_logic;
health_info: in std_logic;
faulty_packet_out: in std_logic;
faulty_packet_in: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
write_fake_flit: in std_logic;
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info_in,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal : out std_logic
);
end component;
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
constant fake_tail : std_logic_vector := "10000000000000000000000000000001";
-- Packet Dropping FSM states encoded as one-hot (because of checkers for one-bit error detection)
CONSTANT Idle: std_logic_vector (4 downto 0) := "00001";
CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010";
CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100";
CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000";
CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000";
--alias flit_type : std_logic_vector(2 downto 0) is RX(DATA_WIDTH-1 downto DATA_WIDTH-3);
signal fault_info_in, fault_info_out: std_logic;
signal faulty_packet_in, faulty_packet_out: std_logic;
signal xor_all, fault_out: std_logic;
--type state_type is (Idle, Header_flit, Body_flit, Tail_flit, Packet_drop);
--signal state_out, state_in : state_type;
signal state_out, state_in : std_logic_vector(4 downto 0); -- : state_type;
signal fake_credit, credit_in, write_fake_flit: std_logic;
signal fake_credit_counter, fake_credit_counter_in: std_logic_vector(1 downto 0);
-- Signal(s) needed for FIFO control part checkers
signal fault_info_sig, health_info_sig : std_logic;
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
-- Packet drop state machine
-- +---+ No +---+ No
-- | | Flit | | Flit
-- | v | v
-- healthy +--------+ +--------+
-- +---header-->| | | |-------------------+
-- | +->| Header |---Healthy body-->| Body |------------+ |
-- | | +--------+ +--------+ | |
-- | | | ^ | Healthy | ^ Healthy |
-- | | | | | body | | Tail |
-- | | | | | +---+ | |
-- | | | | | v |
-- +--------+ | | | | +--------+ |
-- No +-->| | | | | +-----------------Healthy Tail------>| | |
-- Flit| | IDLE | | | | | Tail |--)--+
-- +---| | | | +-----------Healthy Header--------------| | | |
-- +--------+ | | +--------+ | |
-- ^ | ^ | Faulty No Faulty | |
-- | | | | Flit Flit Flit | |
-- | | | | +------------+ +---+ +---+ | |
-- | | | + --Healthy------+ | | | | | | |
-- | | | header | v | v | v | |
-- | | | +------------------+ | |
-- | | +----Healthy Tail-----| Packet | | |
-- | +-------Faulty Flit----->| Drop |<-----------------------+ |
-- | +------------------+ |
-- +-------------------------------------------------No Flit------------------+
--
------------------------------------------------------------------------------------------------
-- FIFO control part with packet drop and fault classifier support checkers instantiation
FIFO_control_part_checkers: FIFO_credit_based_control_part_checkers
port map (
valid_in => valid_in,
read_en_N => read_en_N,
read_en_E => read_en_E,
read_en_W => read_en_W,
read_en_S => read_en_S,
read_en_L => read_en_L,
read_pointer => read_pointer,
read_pointer_in => read_pointer_in,
write_pointer => write_pointer,
write_pointer_in => write_pointer_in,
credit_out => credit_in, -- correct ?
empty_out => empty,
full_out => full,
read_en_out => read_en,
write_en_out => write_en,
fake_credit => fake_credit,
fake_credit_counter => fake_credit_counter,
fake_credit_counter_in => fake_credit_counter_in,
state_out => state_out,
state_in => state_in,
fault_info => fault_info_sig, -- connected to signal
fault_info_out => fault_info_out,
fault_info_in => fault_info_in,
health_info => health_info_sig, -- connected to signal
faulty_packet_out => faulty_packet_out,
faulty_packet_in => faulty_packet_in,
flit_type => RX(DATA_WIDTH-1 downto DATA_WIDTH-3),
fault_out => fault_out,
write_fake_flit => write_fake_flit,
-- Functional checkers
err_empty_full => err_empty_full,
err_empty_read_en => err_empty_read_en,
err_full_write_en => err_full_write_en,
err_state_in_onehot => err_state_in_onehot,
err_read_pointer_in_onehot => err_read_pointer_in_onehot,
err_write_pointer_in_onehot => err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => err_write_en_write_pointer,
err_not_write_en_write_pointer => err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => err_read_pointer_write_pointer_full,
err_read_pointer_increment => err_read_pointer_increment,
err_read_pointer_not_increment => err_read_pointer_not_increment,
err_write_en => err_write_en,
err_not_write_en => err_not_write_en,
err_not_write_en1 => err_not_write_en1,
err_not_write_en2 => err_not_write_en2,
err_read_en_mismatch => err_read_en_mismatch,
err_read_en_mismatch1 => err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info_in => err_state_out_Packet_drop_not_fault_info_in,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal
);
fault_info <= fault_info_sig; -- Not sure yet ?!
health_info <= health_info_sig;
-- Sequential part
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
FIFO_MEM_3 <= (others=>'0');
FIFO_MEM_4 <= (others=>'0');
fake_credit_counter <= (others=>'0');
faulty_packet_out <= '0';
credit_out <= '0';
state_out <= Idle;
fault_info_out <= '0';
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
state_out <= state_in;
faulty_packet_out <= faulty_packet_in;
credit_out <= credit_in;
fake_credit_counter <= fake_credit_counter_in;
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
FIFO_MEM_3 <= FIFO_MEM_3_in;
FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
fault_info_out <= fault_info_in;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
fault_info_sig <= fault_info_out;
process(fake_credit, read_en, fake_credit_counter) begin
fake_credit_counter_in <= fake_credit_counter;
credit_in <= '0';
if fake_credit = '1' and read_en = '1' then
fake_credit_counter_in <= fake_credit_counter + 1 ;
end if;
if fake_credit = '1' or read_en ='1' then
credit_in <= '1';
end if;
if fake_credit = '0' and read_en = '0' and fake_credit_counter > 0 then
fake_credit_counter_in <= fake_credit_counter - 1 ;
credit_in <= '1';
end if;
end process;
process(valid_in, RX) begin
if valid_in = '1' then
xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
else
xor_all <= '0';
end if;
end process;
process(valid_in, RX, xor_all)begin
fault_out <= '0';
if valid_in = '1' and xor_all /= RX(0) then
fault_out <= '1';
end if;
end process;
process(RX, faulty_packet_out, fault_out, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4, state_out, valid_in) begin
-- this is the default value of the memory!
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
--some defaults
fault_info_in <= '0';
health_info_sig <= '0';
fake_credit <= '0';
state_in <= state_out;
faulty_packet_in <= faulty_packet_out;
write_fake_flit <= '0';
case(state_out) is
when Idle =>
if fault_out = '0' then
if valid_in = '1' then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
when Header_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
state_in <= Body_flit;
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
state_in <= Tail_flit;
else
-- we should not be here!
state_in <= state_out;
end if;
else -- fault_out = '1'
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Body_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
state_in <= state_out;
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
state_in <= Tail_flit;
health_info_sig <= '1';
else
-- we should not be here!
state_in <= state_out;
end if;
else -- fault_out = '1'
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Tail_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else -- fault_out = '1'
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= Idle;
end if;
when Packet_drop =>
if faulty_packet_out = '1' then
if valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" and fault_out = '0' then
faulty_packet_in <= '0';
state_in <= Header_flit;
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
elsif valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" and fault_out = '0' then
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
faulty_packet_in <= '0';
state_in <= Idle;
fake_credit <= '1';
else -- fault_out might have been '1'
if valid_in = '1' then
fake_credit <= '1';
end if;
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= state_out;
end if;
else
-- we should not be here!
state_in <= state_out;
end if;
when others => state_in <= state_out;
end case;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when "1000" => Data_out <= FIFO_MEM_4;
when others => Data_out <= FIFO_MEM_1;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
process(write_en, write_pointer)begin
if write_en = '1' then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, valid_in, write_fake_flit, faulty_packet_out, fault_out) begin
if valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full ='0' then
write_en <= '1';
else
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic;
-- Checker outputs
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info_in,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal : out std_logic
);
end FIFO_credit_based;
architecture behavior of FIFO_credit_based is
component FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic;
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
fake_credit: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
fake_credit_counter_in: in std_logic_vector(1 downto 0);
state_out: in std_logic_vector(4 downto 0);
state_in: in std_logic_vector(4 downto 0);
fault_info: in std_logic;
fault_info_out: in std_logic;
fault_info_in: in std_logic;
health_info: in std_logic;
faulty_packet_out: in std_logic;
faulty_packet_in: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
write_fake_flit: in std_logic;
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info_in,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal : out std_logic
);
end component;
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
constant fake_tail : std_logic_vector := "10000000000000000000000000000001";
-- Packet Dropping FSM states encoded as one-hot (because of checkers for one-bit error detection)
CONSTANT Idle: std_logic_vector (4 downto 0) := "00001";
CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010";
CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100";
CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000";
CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000";
--alias flit_type : std_logic_vector(2 downto 0) is RX(DATA_WIDTH-1 downto DATA_WIDTH-3);
signal fault_info_in, fault_info_out: std_logic;
signal faulty_packet_in, faulty_packet_out: std_logic;
signal xor_all, fault_out: std_logic;
--type state_type is (Idle, Header_flit, Body_flit, Tail_flit, Packet_drop);
--signal state_out, state_in : state_type;
signal state_out, state_in : std_logic_vector(4 downto 0); -- : state_type;
signal fake_credit, credit_in, write_fake_flit: std_logic;
signal fake_credit_counter, fake_credit_counter_in: std_logic_vector(1 downto 0);
-- Signal(s) needed for FIFO control part checkers
signal fault_info_sig, health_info_sig : std_logic;
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
-- Packet drop state machine
-- +---+ No +---+ No
-- | | Flit | | Flit
-- | v | v
-- healthy +--------+ +--------+
-- +---header-->| | | |-------------------+
-- | +->| Header |---Healthy body-->| Body |------------+ |
-- | | +--------+ +--------+ | |
-- | | | ^ | Healthy | ^ Healthy |
-- | | | | | body | | Tail |
-- | | | | | +---+ | |
-- | | | | | v |
-- +--------+ | | | | +--------+ |
-- No +-->| | | | | +-----------------Healthy Tail------>| | |
-- Flit| | IDLE | | | | | Tail |--)--+
-- +---| | | | +-----------Healthy Header--------------| | | |
-- +--------+ | | +--------+ | |
-- ^ | ^ | Faulty No Faulty | |
-- | | | | Flit Flit Flit | |
-- | | | | +------------+ +---+ +---+ | |
-- | | | + --Healthy------+ | | | | | | |
-- | | | header | v | v | v | |
-- | | | +------------------+ | |
-- | | +----Healthy Tail-----| Packet | | |
-- | +-------Faulty Flit----->| Drop |<-----------------------+ |
-- | +------------------+ |
-- +-------------------------------------------------No Flit------------------+
--
------------------------------------------------------------------------------------------------
-- FIFO control part with packet drop and fault classifier support checkers instantiation
FIFO_control_part_checkers: FIFO_credit_based_control_part_checkers
port map (
valid_in => valid_in,
read_en_N => read_en_N,
read_en_E => read_en_E,
read_en_W => read_en_W,
read_en_S => read_en_S,
read_en_L => read_en_L,
read_pointer => read_pointer,
read_pointer_in => read_pointer_in,
write_pointer => write_pointer,
write_pointer_in => write_pointer_in,
credit_out => credit_in, -- correct ?
empty_out => empty,
full_out => full,
read_en_out => read_en,
write_en_out => write_en,
fake_credit => fake_credit,
fake_credit_counter => fake_credit_counter,
fake_credit_counter_in => fake_credit_counter_in,
state_out => state_out,
state_in => state_in,
fault_info => fault_info_sig, -- connected to signal
fault_info_out => fault_info_out,
fault_info_in => fault_info_in,
health_info => health_info_sig, -- connected to signal
faulty_packet_out => faulty_packet_out,
faulty_packet_in => faulty_packet_in,
flit_type => RX(DATA_WIDTH-1 downto DATA_WIDTH-3),
fault_out => fault_out,
write_fake_flit => write_fake_flit,
-- Functional checkers
err_empty_full => err_empty_full,
err_empty_read_en => err_empty_read_en,
err_full_write_en => err_full_write_en,
err_state_in_onehot => err_state_in_onehot,
err_read_pointer_in_onehot => err_read_pointer_in_onehot,
err_write_pointer_in_onehot => err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => err_write_en_write_pointer,
err_not_write_en_write_pointer => err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => err_read_pointer_write_pointer_full,
err_read_pointer_increment => err_read_pointer_increment,
err_read_pointer_not_increment => err_read_pointer_not_increment,
err_write_en => err_write_en,
err_not_write_en => err_not_write_en,
err_not_write_en1 => err_not_write_en1,
err_not_write_en2 => err_not_write_en2,
err_read_en_mismatch => err_read_en_mismatch,
err_read_en_mismatch1 => err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info_in => err_state_out_Packet_drop_not_fault_info_in,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal
);
fault_info <= fault_info_sig; -- Not sure yet ?!
health_info <= health_info_sig;
-- Sequential part
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
FIFO_MEM_3 <= (others=>'0');
FIFO_MEM_4 <= (others=>'0');
fake_credit_counter <= (others=>'0');
faulty_packet_out <= '0';
credit_out <= '0';
state_out <= Idle;
fault_info_out <= '0';
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
state_out <= state_in;
faulty_packet_out <= faulty_packet_in;
credit_out <= credit_in;
fake_credit_counter <= fake_credit_counter_in;
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
FIFO_MEM_3 <= FIFO_MEM_3_in;
FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
fault_info_out <= fault_info_in;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
fault_info_sig <= fault_info_out;
process(fake_credit, read_en, fake_credit_counter) begin
fake_credit_counter_in <= fake_credit_counter;
credit_in <= '0';
if fake_credit = '1' and read_en = '1' then
fake_credit_counter_in <= fake_credit_counter + 1 ;
end if;
if fake_credit = '1' or read_en ='1' then
credit_in <= '1';
end if;
if fake_credit = '0' and read_en = '0' and fake_credit_counter > 0 then
fake_credit_counter_in <= fake_credit_counter - 1 ;
credit_in <= '1';
end if;
end process;
process(valid_in, RX) begin
if valid_in = '1' then
xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
else
xor_all <= '0';
end if;
end process;
process(valid_in, RX, xor_all)begin
fault_out <= '0';
if valid_in = '1' and xor_all /= RX(0) then
fault_out <= '1';
end if;
end process;
process(RX, faulty_packet_out, fault_out, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4, state_out, valid_in) begin
-- this is the default value of the memory!
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
--some defaults
fault_info_in <= '0';
health_info_sig <= '0';
fake_credit <= '0';
state_in <= state_out;
faulty_packet_in <= faulty_packet_out;
write_fake_flit <= '0';
case(state_out) is
when Idle =>
if fault_out = '0' then
if valid_in = '1' then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
when Header_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
state_in <= Body_flit;
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
state_in <= Tail_flit;
else
-- we should not be here!
state_in <= state_out;
end if;
else -- fault_out = '1'
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Body_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
state_in <= state_out;
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
state_in <= Tail_flit;
health_info_sig <= '1';
else
-- we should not be here!
state_in <= state_out;
end if;
else -- fault_out = '1'
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Tail_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else -- fault_out = '1'
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= Idle;
end if;
when Packet_drop =>
if faulty_packet_out = '1' then
if valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" and fault_out = '0' then
faulty_packet_in <= '0';
state_in <= Header_flit;
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
elsif valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" and fault_out = '0' then
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
faulty_packet_in <= '0';
state_in <= Idle;
fake_credit <= '1';
else -- fault_out might have been '1'
if valid_in = '1' then
fake_credit <= '1';
end if;
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= state_out;
end if;
else
-- we should not be here!
state_in <= state_out;
end if;
when others => state_in <= state_out;
end case;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when "1000" => Data_out <= FIFO_MEM_4;
when others => Data_out <= FIFO_MEM_1;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
process(write_en, write_pointer)begin
if write_en = '1' then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, valid_in, write_fake_flit, faulty_packet_out, fault_out) begin
if valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full ='0' then
write_en <= '1';
else
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic;
-- Checker outputs
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info_in,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal : out std_logic
);
end FIFO_credit_based;
architecture behavior of FIFO_credit_based is
component FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic;
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
fake_credit: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
fake_credit_counter_in: in std_logic_vector(1 downto 0);
state_out: in std_logic_vector(4 downto 0);
state_in: in std_logic_vector(4 downto 0);
fault_info: in std_logic;
fault_info_out: in std_logic;
fault_info_in: in std_logic;
health_info: in std_logic;
faulty_packet_out: in std_logic;
faulty_packet_in: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
write_fake_flit: in std_logic;
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info_in,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal : out std_logic
);
end component;
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
constant fake_tail : std_logic_vector := "10000000000000000000000000000001";
-- Packet Dropping FSM states encoded as one-hot (because of checkers for one-bit error detection)
CONSTANT Idle: std_logic_vector (4 downto 0) := "00001";
CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010";
CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100";
CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000";
CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000";
--alias flit_type : std_logic_vector(2 downto 0) is RX(DATA_WIDTH-1 downto DATA_WIDTH-3);
signal fault_info_in, fault_info_out: std_logic;
signal faulty_packet_in, faulty_packet_out: std_logic;
signal xor_all, fault_out: std_logic;
--type state_type is (Idle, Header_flit, Body_flit, Tail_flit, Packet_drop);
--signal state_out, state_in : state_type;
signal state_out, state_in : std_logic_vector(4 downto 0); -- : state_type;
signal fake_credit, credit_in, write_fake_flit: std_logic;
signal fake_credit_counter, fake_credit_counter_in: std_logic_vector(1 downto 0);
-- Signal(s) needed for FIFO control part checkers
signal fault_info_sig, health_info_sig : std_logic;
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
-- Packet drop state machine
-- +---+ No +---+ No
-- | | Flit | | Flit
-- | v | v
-- healthy +--------+ +--------+
-- +---header-->| | | |-------------------+
-- | +->| Header |---Healthy body-->| Body |------------+ |
-- | | +--------+ +--------+ | |
-- | | | ^ | Healthy | ^ Healthy |
-- | | | | | body | | Tail |
-- | | | | | +---+ | |
-- | | | | | v |
-- +--------+ | | | | +--------+ |
-- No +-->| | | | | +-----------------Healthy Tail------>| | |
-- Flit| | IDLE | | | | | Tail |--)--+
-- +---| | | | +-----------Healthy Header--------------| | | |
-- +--------+ | | +--------+ | |
-- ^ | ^ | Faulty No Faulty | |
-- | | | | Flit Flit Flit | |
-- | | | | +------------+ +---+ +---+ | |
-- | | | + --Healthy------+ | | | | | | |
-- | | | header | v | v | v | |
-- | | | +------------------+ | |
-- | | +----Healthy Tail-----| Packet | | |
-- | +-------Faulty Flit----->| Drop |<-----------------------+ |
-- | +------------------+ |
-- +-------------------------------------------------No Flit------------------+
--
------------------------------------------------------------------------------------------------
-- FIFO control part with packet drop and fault classifier support checkers instantiation
FIFO_control_part_checkers: FIFO_credit_based_control_part_checkers
port map (
valid_in => valid_in,
read_en_N => read_en_N,
read_en_E => read_en_E,
read_en_W => read_en_W,
read_en_S => read_en_S,
read_en_L => read_en_L,
read_pointer => read_pointer,
read_pointer_in => read_pointer_in,
write_pointer => write_pointer,
write_pointer_in => write_pointer_in,
credit_out => credit_in, -- correct ?
empty_out => empty,
full_out => full,
read_en_out => read_en,
write_en_out => write_en,
fake_credit => fake_credit,
fake_credit_counter => fake_credit_counter,
fake_credit_counter_in => fake_credit_counter_in,
state_out => state_out,
state_in => state_in,
fault_info => fault_info_sig, -- connected to signal
fault_info_out => fault_info_out,
fault_info_in => fault_info_in,
health_info => health_info_sig, -- connected to signal
faulty_packet_out => faulty_packet_out,
faulty_packet_in => faulty_packet_in,
flit_type => RX(DATA_WIDTH-1 downto DATA_WIDTH-3),
fault_out => fault_out,
write_fake_flit => write_fake_flit,
-- Functional checkers
err_empty_full => err_empty_full,
err_empty_read_en => err_empty_read_en,
err_full_write_en => err_full_write_en,
err_state_in_onehot => err_state_in_onehot,
err_read_pointer_in_onehot => err_read_pointer_in_onehot,
err_write_pointer_in_onehot => err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => err_write_en_write_pointer,
err_not_write_en_write_pointer => err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => err_read_pointer_write_pointer_full,
err_read_pointer_increment => err_read_pointer_increment,
err_read_pointer_not_increment => err_read_pointer_not_increment,
err_write_en => err_write_en,
err_not_write_en => err_not_write_en,
err_not_write_en1 => err_not_write_en1,
err_not_write_en2 => err_not_write_en2,
err_read_en_mismatch => err_read_en_mismatch,
err_read_en_mismatch1 => err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info_in => err_state_out_Packet_drop_not_fault_info_in,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal
);
fault_info <= fault_info_sig; -- Not sure yet ?!
health_info <= health_info_sig;
-- Sequential part
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
FIFO_MEM_3 <= (others=>'0');
FIFO_MEM_4 <= (others=>'0');
fake_credit_counter <= (others=>'0');
faulty_packet_out <= '0';
credit_out <= '0';
state_out <= Idle;
fault_info_out <= '0';
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
state_out <= state_in;
faulty_packet_out <= faulty_packet_in;
credit_out <= credit_in;
fake_credit_counter <= fake_credit_counter_in;
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
FIFO_MEM_3 <= FIFO_MEM_3_in;
FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
fault_info_out <= fault_info_in;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
fault_info_sig <= fault_info_out;
process(fake_credit, read_en, fake_credit_counter) begin
fake_credit_counter_in <= fake_credit_counter;
credit_in <= '0';
if fake_credit = '1' and read_en = '1' then
fake_credit_counter_in <= fake_credit_counter + 1 ;
end if;
if fake_credit = '1' or read_en ='1' then
credit_in <= '1';
end if;
if fake_credit = '0' and read_en = '0' and fake_credit_counter > 0 then
fake_credit_counter_in <= fake_credit_counter - 1 ;
credit_in <= '1';
end if;
end process;
process(valid_in, RX) begin
if valid_in = '1' then
xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
else
xor_all <= '0';
end if;
end process;
process(valid_in, RX, xor_all)begin
fault_out <= '0';
if valid_in = '1' and xor_all /= RX(0) then
fault_out <= '1';
end if;
end process;
process(RX, faulty_packet_out, fault_out, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4, state_out, valid_in) begin
-- this is the default value of the memory!
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
--some defaults
fault_info_in <= '0';
health_info_sig <= '0';
fake_credit <= '0';
state_in <= state_out;
faulty_packet_in <= faulty_packet_out;
write_fake_flit <= '0';
case(state_out) is
when Idle =>
if fault_out = '0' then
if valid_in = '1' then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
when Header_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
state_in <= Body_flit;
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
state_in <= Tail_flit;
else
-- we should not be here!
state_in <= state_out;
end if;
else -- fault_out = '1'
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Body_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
state_in <= state_out;
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
state_in <= Tail_flit;
health_info_sig <= '1';
else
-- we should not be here!
state_in <= state_out;
end if;
else -- fault_out = '1'
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Tail_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else -- fault_out = '1'
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= Idle;
end if;
when Packet_drop =>
if faulty_packet_out = '1' then
if valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" and fault_out = '0' then
faulty_packet_in <= '0';
state_in <= Header_flit;
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
elsif valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" and fault_out = '0' then
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
faulty_packet_in <= '0';
state_in <= Idle;
fake_credit <= '1';
else -- fault_out might have been '1'
if valid_in = '1' then
fake_credit <= '1';
end if;
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= state_out;
end if;
else
-- we should not be here!
state_in <= state_out;
end if;
when others => state_in <= state_out;
end case;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when "1000" => Data_out <= FIFO_MEM_4;
when others => Data_out <= FIFO_MEM_1;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
process(write_en, write_pointer)begin
if write_en = '1' then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, valid_in, write_fake_flit, faulty_packet_out, fault_out) begin
if valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full ='0' then
write_en <= '1';
else
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity square is
Port ( number : in STD_LOGIC_VECTOR (15 downto 0);
clock : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (15 downto 0);
done : out STD_LOGIC);
end square;
architecture Behavioral of square is
type FSM is (INITIAL, OPERATION, FINAL);
signal state : FSM;
signal n, d, r : STD_LOGIC_VECTOR (15 downto 0);
begin
main_process : process (clock)
begin
if clock'event and clock = '1' then
case state is
when INITIAL =>
n <= number;
d <= "000000000000001";
r <= "000000000000000";
done <= '0';
state <= OPERATION;
when OPERATION =>
if (n > 0) then
n <= n - d;
d <= d + 2;
r <= r + 1;
done <= '0';
state <= OPERATION;
else
state <= FINAL;
end if;
when FINAL =>
output <= r;
done <= '1';
state <= INITIAL;
when others =>
done <= '0';
state <= INITIAL;
end case;
end if;
end process;
end Behavioral;
|
--!
--! Generic clock divider
--!
--! Generates an clock enable signal.
--!
--! Example:
--! @code
--! process (clk)
--! begin
--! if rising_edge(clk) then
--! if enable = '1' then
--! ... do something with the period of the divided frequency ...
--! end if;
--! end if;
--! end process;
--! @endcode
--!
--! @author Fabian Greif
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clock_divider is
generic (
DIV : positive := 2);
port (
clk_out_p : out std_logic := '0'; -- Enable output ('1' for one clock cycle)
clk : in std_logic -- System clock
);
end clock_divider;
-- ----------------------------------------------------------------------------
architecture behavior of clock_divider is
begin
process
variable counter : integer range 0 to DIV := 0;
begin
wait until rising_edge(clk);
counter := counter + 1;
if counter = DIV then
counter := 0;
clk_out_p <= '1';
else
clk_out_p <= '0';
end if;
end process;
end behavior;
|
--!
--! Generic clock divider
--!
--! Generates an clock enable signal.
--!
--! Example:
--! @code
--! process (clk)
--! begin
--! if rising_edge(clk) then
--! if enable = '1' then
--! ... do something with the period of the divided frequency ...
--! end if;
--! end if;
--! end process;
--! @endcode
--!
--! @author Fabian Greif
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clock_divider is
generic (
DIV : positive := 2);
port (
clk_out_p : out std_logic := '0'; -- Enable output ('1' for one clock cycle)
clk : in std_logic -- System clock
);
end clock_divider;
-- ----------------------------------------------------------------------------
architecture behavior of clock_divider is
begin
process
variable counter : integer range 0 to DIV := 0;
begin
wait until rising_edge(clk);
counter := counter + 1;
if counter = DIV then
counter := 0;
clk_out_p <= '1';
else
clk_out_p <= '0';
end if;
end process;
end behavior;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: pulse_regen_s6_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity pulse_regen_s6_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end pulse_regen_s6_top;
architecture xilinx of pulse_regen_s6_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component pulse_regen_s6 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : pulse_regen_s6 PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
-- This -*- vhdl -*- file is part of GHDL.
-- IEEE 1076.3 compliant numeric std package.
-- Copyright (C) 2015 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING2. If not see
-- <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package NUMERIC_STD is
type UNSIGNED is array (natural range <>) of STD_LOGIC;
type SIGNED is array (natural range <>) of STD_LOGIC;
function TO_01 (S : SIGNED; XMAP : STD_LOGIC := '0') return SIGNED;
function TO_01 (S : UNSIGNED; XMAP : STD_LOGIC := '0') return UNSIGNED;
-- Convert 'H' and '1' to '1', 'L' and '0' to '0'.
-- If any other value is present, return (others => XMAP)
-- Issue a warning in that case, and if S is a null array.
-- Result index range is S'Length - 1 downto 0.
function std_match (l, r : std_ulogic) return boolean;
function std_match (l, r : std_ulogic_vector) return boolean;
function std_match (l, r : std_logic_vector) return boolean;
function std_match (l, r : UNSIGNED) return boolean;
function std_match (l, r : SIGNED) return boolean;
-- Return True iff L and R matches.
function TO_INTEGER (ARG : UNSIGNED) return NATURAL;
function TO_INTEGER (ARG : SIGNED) return INTEGER;
-- Convert ARG to an integer.
-- Simulation is aborted in case of overflow.
-- Issue a warning in case of non-logical value.
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNSIGNED;
-- Convert ARG to unsigned.
-- Result index range is SIZE - 1 downto 0.
-- Issue a warning if value is truncated.
function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return SIGNED;
-- Convert ARG to signed.
-- Result index range is SIZE - 1 downto 0.
-- Issue a warning if value is truncated.
function resize (ARG : UNSIGNED; NEW_SIZE: natural) return UNSIGNED;
function resize (ARG : SIGNED; NEW_SIZE: natural) return SIGNED;
-- Result index range is NEW_SIZE - 1 downto 0 (unless null array).
-- For SIGNED, the sign of the result is the sign of ARG.
function "=" (L, R : UNSIGNED) return BOOLEAN;
function "=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function "=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function "/=" (L, R : UNSIGNED) return BOOLEAN;
function "/=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function "/=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function "<" (L, R : UNSIGNED) return BOOLEAN;
function "<" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function "<" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function "<=" (L, R : UNSIGNED) return BOOLEAN;
function "<=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function "<=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function ">" (L, R : UNSIGNED) return BOOLEAN;
function ">" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function ">" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function ">=" (L, R : UNSIGNED) return BOOLEAN;
function ">=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function ">=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function "=" (L, R : SIGNED) return BOOLEAN;
function "=" (L : SIGNED; R : INTEGER) return BOOLEAN;
function "=" (L : INTEGER; R : SIGNED) return BOOLEAN;
function "/=" (L, R : SIGNED) return BOOLEAN;
function "/=" (L : SIGNED; R : INTEGER) return BOOLEAN;
function "/=" (L : INTEGER; R : SIGNED) return BOOLEAN;
function "<" (L, R : SIGNED) return BOOLEAN;
function "<" (L : SIGNED; R : INTEGER) return BOOLEAN;
function "<" (L : INTEGER; R : SIGNED) return BOOLEAN;
function "<=" (L, R : SIGNED) return BOOLEAN;
function "<=" (L : SIGNED; R : INTEGER) return BOOLEAN;
function "<=" (L : INTEGER; R : SIGNED) return BOOLEAN;
function ">" (L, R : SIGNED) return BOOLEAN;
function ">" (L : SIGNED; R : INTEGER) return BOOLEAN;
function ">" (L : INTEGER; R : SIGNED) return BOOLEAN;
function ">=" (L, R : SIGNED) return BOOLEAN;
function ">=" (L : SIGNED; R : INTEGER) return BOOLEAN;
function ">=" (L : INTEGER; R : SIGNED) return BOOLEAN;
-- Issue a warning in case of non-logical value.
function "-" (ARG : SIGNED) return SIGNED;
-- Compute -ARG.
-- Result index range is Arg'length - 1 downto 0.
function "abs" (ARG : SIGNED) return SIGNED;
-- Compute abs ARG.
-- Result index range is Arg'length - 1 downto 0.
function "+" (L, R : UNSIGNED) return UNSIGNED;
function "+" (L, R : SIGNED) return SIGNED;
function "-" (L, R : UNSIGNED) return UNSIGNED;
function "-" (L, R : SIGNED) return SIGNED;
-- Compute L +/- R.
-- Result index range is max (L'Length, R'Length) - 1 downto 0.
-- Issue a warning in case of non-logical value.
function "+" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "+" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "+" (L : SIGNED; R : INTEGER) return SIGNED;
function "+" (L : INTEGER; R : SIGNED) return SIGNED;
function "-" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "-" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "-" (L : SIGNED; R : INTEGER) return SIGNED;
function "-" (L : INTEGER; R : SIGNED) return SIGNED;
-- Compute L +/- R.
-- Result index range is V'Length - 1 downto 0, where V is the vector
-- parameter.
-- Issue a warning in case of non-logical value.
-- Issue a warning if value is truncated.
function "*" (L, R : UNSIGNED) return UNSIGNED;
function "*" (L, R : SIGNED) return SIGNED;
-- Compute L * R
-- Result index range is L'Length + R'Length - 1 downto 0.
function "*" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "*" (L : SIGNED; R : INTEGER) return SIGNED;
-- Compute L * R
-- R is converted to a vector of length L'length
function "*" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "*" (L : INTEGER; R : SIGNED) return SIGNED;
-- Compute L * R
-- L is converted to a vector of length R'length
function "/" (L, R : UNSIGNED) return UNSIGNED;
function "/" (L, R : SIGNED) return SIGNED;
function "rem" (L, R : UNSIGNED) return UNSIGNED;
function "rem" (L, R : SIGNED) return SIGNED;
function "mod" (L, R : UNSIGNED) return UNSIGNED;
function "mod" (L, R : SIGNED) return SIGNED;
-- Compute L op R
-- Result index range is L'Length - 1 downto 0.
-- Issue a warning in case of non-logical value.
-- Issue an error if R is 0.
function "/" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "/" (L : SIGNED; R : INTEGER) return SIGNED;
function "rem" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "rem" (L : SIGNED; R : INTEGER) return SIGNED;
function "mod" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "mod" (L : SIGNED; R : INTEGER) return SIGNED;
-- Compute L op R.
-- Result index range is L'Length - 1 downto 0.
-- Issue a warning in case of non-logical value.
-- Issue an error if R is 0.
function "/" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "/" (L : INTEGER; R : SIGNED) return SIGNED;
function "rem" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "rem" (L : INTEGER; R : SIGNED) return SIGNED;
function "mod" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "mod" (L : INTEGER; R : SIGNED) return SIGNED;
-- Compute L op R.
-- Result index range is R'Length - 1 downto 0.
-- Issue a warning in case of non-logical value.
-- Issue an error if R is 0.
-- Result may be truncated.
function "not" (l : UNSIGNED) return UNSIGNED;
function "not" (l : SIGNED) return SIGNED;
function "and" (l, r : UNSIGNED) return UNSIGNED;
function "and" (l, r : SIGNED) return SIGNED;
function "nand" (l, r : UNSIGNED) return UNSIGNED;
function "nand" (l, r : SIGNED) return SIGNED;
function "or" (l, r : UNSIGNED) return UNSIGNED;
function "or" (l, r : SIGNED) return SIGNED;
function "nor" (l, r : UNSIGNED) return UNSIGNED;
function "nor" (l, r : SIGNED) return SIGNED;
function "xor" (l, r : UNSIGNED) return UNSIGNED;
function "xor" (l, r : SIGNED) return SIGNED;
function "xnor" (l, r : UNSIGNED) return UNSIGNED;
function "xnor" (l, r : SIGNED) return SIGNED;
-- Compute L OP R.
-- Result index range is L'Length - 1 downto 0.
-- No specific handling of null array: the index range of the result
-- would be -1 downto 0 (without warning). This it not what is specified
-- in 1076.3, but corresponds to the standard implementation.
-- No specific handling of non-logical values. Behaviour is compatible
-- with std_logic_1164.
function shift_left (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED;
function shift_left (ARG : SIGNED; COUNT: NATURAL) return SIGNED;
function shift_right (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED;
function shift_right (ARG : SIGNED; COUNT: NATURAL) return SIGNED;
-- Result index range is ARG'Length - 1 downto 0.
function rotate_left (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED;
function rotate_left (ARG : SIGNED; COUNT: NATURAL) return SIGNED;
function rotate_right (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED;
function rotate_right (ARG : SIGNED; COUNT: NATURAL) return SIGNED;
-- Result index range is ARG'Length - 1 downto 0.
function "sll" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
function "sll" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
function "srl" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
function "srl" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
-- Result index range is ARG'Length - 1 downto 0.
function "rol" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
function "rol" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
function "ror" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
function "ror" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
-- Result index range is ARG'Length - 1 downto 0.
end NUMERIC_STD;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3104.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p16n02i03104ent IS
port (PT:BOOLEAN);
attribute AT1 : integer;
attribute AT1 of ch0501_P01602_02_ent : entity is 1.2; -- Failure_here
--ERROR: Specification expression is not the same type as attribute declaration
END c05s01b00x00p16n02i03104ent;
ARCHITECTURE c05s01b00x00p16n02i03104arch OF c05s01b00x00p16n02i03104ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s01b00x00p16n02i03104 - Specification expression is not of the same type as attribute specification."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p16n02i03104arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3104.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p16n02i03104ent IS
port (PT:BOOLEAN);
attribute AT1 : integer;
attribute AT1 of ch0501_P01602_02_ent : entity is 1.2; -- Failure_here
--ERROR: Specification expression is not the same type as attribute declaration
END c05s01b00x00p16n02i03104ent;
ARCHITECTURE c05s01b00x00p16n02i03104arch OF c05s01b00x00p16n02i03104ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s01b00x00p16n02i03104 - Specification expression is not of the same type as attribute specification."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p16n02i03104arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3104.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p16n02i03104ent IS
port (PT:BOOLEAN);
attribute AT1 : integer;
attribute AT1 of ch0501_P01602_02_ent : entity is 1.2; -- Failure_here
--ERROR: Specification expression is not the same type as attribute declaration
END c05s01b00x00p16n02i03104ent;
ARCHITECTURE c05s01b00x00p16n02i03104arch OF c05s01b00x00p16n02i03104ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s01b00x00p16n02i03104 - Specification expression is not of the same type as attribute specification."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p16n02i03104arch;
|
--MIT License
--
--Copyright (c) 2017 Danny Savory
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
library ieee, dsaves;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity LUT is
generic(
N : natural
);
port(
clk : in std_logic;
rst : in std_logic;
d : in std_logic_vector((2**N)-1 downto 0);
wen : in std_logic;
s : in std_logic_vector(N-1 downto 0);
o : out std_logic
);
end entity;
architecture POS_EDGE of LUT is
signal mem_bank : std_logic_vector((2**N)-1 downto 0);
begin
MEM_GENERATE:
for i in 0 to ((2**N)-1) generate
FF : entity dsaves.FF(POS_EDGE_HI_EN)
port map(
clk => clk,
d => d(i),
en => wen,
rst => rst,
q => mem_bank(i)
);
end generate;
o <= mem_bank(to_integer(unsigned(s)));
end architecture;
architecture NEG_EDGE of LUT is
signal mem_bank : std_logic_vector((2**N)-1 downto 0);
begin
MEM_GENERATE:
for i in 0 to ((2**N)-1) generate
FF : entity dsaves.FF(NEG_EDGE_HI_EN)
port map(
clk => clk,
d => d(i),
en => wen,
rst => rst,
q => mem_bank(i)
);
end generate;
o <= mem_bank(to_integer(unsigned(s)));
end architecture;
|
-- Title : On Board Programer Package (OBP, WB-debuger simplification)
-- Project : OBP
-------------------------------------------------------------------------------
-- File : obp.vhd
-- Author : Jose Jimenez Montañez, Miguel Jimenez Lopez
-- Company : University of Granada (UGR)
-- Created : 2014-06-12
-- Last update: 2014-06-12
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- OBP is a HDL module implementing a On Board Programer component that allows
-- to program the LM32 inside the WRPC via USB port. In addition, some debug
-- functions have been added (to read/write WB registers, show the SDB structure, etc).
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014, University of Granada (UGR)
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-06-12 1.0 JJimenez,klyone Created and first version
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
package obp_pkg is
function f_xwb_dpram_obp(g_size : natural) return t_sdb_device;
function f_xwb_cram_obp(g_size : natural) return t_sdb_device;
function f_secobp_layout(g_size : natural) return t_sdb_record_array;
component OBP is
generic(
g_dpram_initf : string := "obp.ram";
g_dpram_size : integer := 20480/4;
g_cram_size : integer := 20480/4;
g_bridge_sdb : t_sdb_bridge
);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
enable_obp : in std_logic;
wbs_i : in t_wishbone_slave_in;
wbs_o : out t_wishbone_slave_out;
wbm_i : in t_wishbone_master_in;
wbm_o : out t_wishbone_master_out
);
end component;
constant c_obp_wb_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000000f", -- I think this is overestimated
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000099",
version => x"00000001",
date => x"20000101", -- UNKNOWN
name => "OBP-WBS ")));
constant c_secobp_sdb_address : t_wishbone_address := x"00030000";
end obp_pkg;
package body obp_pkg is
function f_xwb_dpram_obp(g_size : natural) return t_sdb_device
is
variable result : t_sdb_device;
begin
result.abi_class := x"0001"; -- RAM device
result.abi_ver_major := x"01";
result.abi_ver_minor := x"00";
result.wbd_width := x"7"; -- 32/16/8-bit supported
result.wbd_endian := c_sdb_endian_big;
result.sdb_component.addr_first := (others => '0');
result.sdb_component.addr_last := std_logic_vector(to_unsigned(g_size*4-1, 64));
result.sdb_component.product.vendor_id := x"000000000000CE42"; -- CERN
result.sdb_component.product.device_id := x"66554433";
result.sdb_component.product.version := x"00000001";
result.sdb_component.product.date := x"20120305";
result.sdb_component.product.name := "WB4-BlockRAM OBP ";
return result;
end f_xwb_dpram_obp;
function f_xwb_cram_obp(g_size : natural) return t_sdb_device
is
variable result : t_sdb_device;
begin
result.abi_class := x"0001"; -- RAM device
result.abi_ver_major := x"01";
result.abi_ver_minor := x"00";
result.wbd_width := x"7"; -- 32/16/8-bit supported
result.wbd_endian := c_sdb_endian_big;
result.sdb_component.addr_first := (others => '0');
result.sdb_component.addr_last := std_logic_vector(to_unsigned(g_size*4-1, 64));
result.sdb_component.product.vendor_id := x"000000000000CE42"; -- CERN
result.sdb_component.product.device_id := x"66554432";
result.sdb_component.product.version := x"00000001";
result.sdb_component.product.date := x"20120305";
result.sdb_component.product.name := "WB4-BlockRAM OBP C ";
return result;
end f_xwb_cram_obp;
function f_secobp_layout(g_size : natural) return t_sdb_record_array
is
variable result : t_sdb_record_array(1 downto 0);
begin
result(0) := f_sdb_embed_device(f_xwb_cram_obp(g_size), x"00000000");
result(1) := f_sdb_embed_device(c_obp_wb_sdb, x"00020000");
return result;
end f_secobp_layout;
end obp_pkg;
|
--------------------------------------------------------------------------------
-- Engineer: Klimann Wendlin
--
-- Create Date: 07:25:11 11/Okt/2013
-- Design Name: i2s_in_tb
-- Description:
--
-- VHDL Test Bench for module: i2s_in
--
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY i2s_in_tb_vhd IS
END i2s_in_tb_vhd;
ARCHITECTURE behavior OF i2s_in_tb_vhd IS
constant width : integer := 24;
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT i2s_in
generic(width : integer := width);
PORT(
LR_CLK : IN std_logic;
BIT_CLK : IN std_logic;
DIN : IN std_logic;
RESET : IN std_logic;
DATA_L : OUT std_logic_vector(width-1 downto 0);
DATA_R : OUT std_logic_vector(width-1 downto 0);
DATA_RDY_L : OUT std_logic;
DATA_RDY_R : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL LR_CLK : std_logic := '0';
SIGNAL BIT_CLK : std_logic := '0';
SIGNAL DIN : std_logic := '0';
SIGNAL RESET : std_logic := '0';
--Outputs
SIGNAL DATA_L : std_logic_vector(width-1 downto 0);
SIGNAL DATA_R : std_logic_vector(width-1 downto 0);
SIGNAL DATA_RDY_L : std_logic;
SIGNAL DATA_RDY_R : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: i2s_in
PORT MAP(
LR_CLK => LR_CLK,
BIT_CLK => BIT_CLK,
DIN => DIN,
RESET => RESET,
DATA_L => DATA_L,
DATA_R => DATA_R,
DATA_RDY_L => DATA_RDY_L,
DATA_RDY_R => DATA_RDY_R
);
p_reset : process
begin
RESET <= '0';
--LR_CK <= '1';
wait for 640 ns;
RESET <= '1';
-- Reset finished
wait;
end process p_reset;
p_bit_clk : process
begin
BIT_CLK <= '0';
wait for 10 ns;
BIT_CLK <= '1';
wait for 10 ns;
end process p_bit_clk;
p_lr_clk : process
begin
LR_CLK <= '0';
wait for 480 ns;
LR_CLK <= '1';
wait for 480 ns;
end process p_lr_clk;
p_din : process
variable i : POSITIVE :=1;
begin
i := 1;
loop_1: while i <= 24 loop
DIN <= '0';
wait for 20 ns;
DIN <= '1';
wait for 20 ns;
i := i+1;
end loop loop_1;
i := 1;
loop_2: while i <= 12 loop
DIN <= '0';
wait for 40 ns;
DIN <= '1';
wait for 40 ns;
i := i+1;
end loop loop_2;
i := 1;
loop_3: while i <= 6 loop
DIN <= '0';
wait for 80 ns;
DIN <= '1';
wait for 80 ns;
i := i+1;
end loop loop_3;
end process p_din;
END;
|
entity portlisttest is
port (
signal a: in bit;
signal b: out bit
);
end entity;
entity portlisttest is
end entity;
architecture foo of portlisttest is
signal a: bit;
signal b: bit;
begin
DUT:
entity work.portlisttest --(fum)
port map (
a => a,
b => b
);
end architecture;
|
entity e is
port (
x : in bit_vector(8+23+2 downto 0) ); -- Error with prefer-explicit
end entity;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/Complex3Multiply_block3.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Complex3Multiply_block3
-- Source Path: fft_16_bit/FFT HDL Optimized/TWDLMULT_SDNF1_3/Complex3Multiply
-- Hierarchy Level: 3
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Complex3Multiply_block3 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din1_re_dly3 : IN std_logic_vector(19 DOWNTO 0); -- sfix20
din1_im_dly3 : IN std_logic_vector(19 DOWNTO 0); -- sfix20
din1_vld_dly3 : IN std_logic;
twdl_3_7_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_7_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_7_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_7_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin1_vld : OUT std_logic
);
END Complex3Multiply_block3;
ARCHITECTURE rtl OF Complex3Multiply_block3 IS
-- Signals
SIGNAL din1_re_dly3_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_im_dly3_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL din_sum : signed(20 DOWNTO 0); -- sfix21
SIGNAL twdl_3_7_re_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_re_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_7_im_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_im_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL adder_add_cast : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL adder_add_cast_1 : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL twdl_sum : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL Complex3Multiply_din1_re_pipe1 : signed(19 DOWNTO 0); -- sfix20
SIGNAL Complex3Multiply_din1_im_pipe1 : signed(19 DOWNTO 0); -- sfix20
SIGNAL Complex3Multiply_din1_sum_pipe1 : signed(20 DOWNTO 0); -- sfix21
SIGNAL Complex3Multiply_prodOfRe_pipe1 : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Multiply_ProdOfIm_pipe1 : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Multiply_prodOfSum_pipe1 : signed(38 DOWNTO 0); -- sfix39
SIGNAL Complex3Multiply_twiddle_re_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_im_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_sum_pipe1 : signed(17 DOWNTO 0); -- sfix18
SIGNAL prodOfRe : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL prodOfIm : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL prodOfSum : signed(38 DOWNTO 0); -- sfix39_En15
SIGNAL din_vld_dly1 : std_logic;
SIGNAL din_vld_dly2 : std_logic;
SIGNAL din_vld_dly3 : std_logic;
SIGNAL prod_vld : std_logic;
SIGNAL Complex3Add_tmpResult_reg : signed(38 DOWNTO 0); -- sfix39
SIGNAL Complex3Add_multRes_re_reg1 : signed(37 DOWNTO 0); -- sfix38
SIGNAL Complex3Add_multRes_re_reg2 : signed(37 DOWNTO 0); -- sfix38
SIGNAL Complex3Add_multRes_im_reg : signed(39 DOWNTO 0); -- sfix40
SIGNAL Complex3Add_prod_vld_reg1 : std_logic;
SIGNAL Complex3Add_prod_vld_reg2 : std_logic;
SIGNAL Complex3Add_prodOfSum_reg : signed(38 DOWNTO 0); -- sfix39
SIGNAL Complex3Add_tmpResult_reg_next : signed(38 DOWNTO 0); -- sfix39_En15
SIGNAL Complex3Add_multRes_re_reg1_next : signed(37 DOWNTO 0); -- sfix38_En15
SIGNAL Complex3Add_multRes_re_reg2_next : signed(37 DOWNTO 0); -- sfix38_En15
SIGNAL Complex3Add_multRes_im_reg_next : signed(39 DOWNTO 0); -- sfix40_En15
SIGNAL Complex3Add_prod_vld_reg1_next : std_logic;
SIGNAL Complex3Add_prod_vld_reg2_next : std_logic;
SIGNAL Complex3Add_prodOfSum_reg_next : signed(38 DOWNTO 0); -- sfix39_En15
SIGNAL multResFP_re : signed(37 DOWNTO 0); -- sfix38_En15
SIGNAL multResFP_im : signed(39 DOWNTO 0); -- sfix40_En15
SIGNAL twdlXdin_7_re_tmp : signed(19 DOWNTO 0); -- sfix20
SIGNAL twdlXdin_7_im_tmp : signed(19 DOWNTO 0); -- sfix20
BEGIN
din1_re_dly3_signed <= signed(din1_re_dly3);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_re_reg <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_re_reg <= to_signed(16#00000#, 20);
ELSE
din_re_reg <= din1_re_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_process;
din1_im_dly3_signed <= signed(din1_im_dly3);
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_im_reg <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_im_reg <= to_signed(16#00000#, 20);
ELSE
din_im_reg <= din1_im_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_1_process;
din_sum <= resize(din_re_reg, 21) + resize(din_im_reg, 21);
twdl_3_7_re_signed <= signed(twdl_3_7_re);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSE
twdl_re_reg <= twdl_3_7_re_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_2_process;
twdl_3_7_im_signed <= signed(twdl_3_7_im);
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSE
twdl_im_reg <= twdl_3_7_im_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_3_process;
adder_add_cast <= resize(twdl_re_reg, 18);
adder_add_cast_1 <= resize(twdl_im_reg, 18);
twdl_sum <= adder_add_cast + adder_add_cast_1;
-- Complex3Multiply
Complex3Multiply_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prodOfRe <= Complex3Multiply_prodOfRe_pipe1;
prodOfIm <= Complex3Multiply_ProdOfIm_pipe1;
prodOfSum <= Complex3Multiply_prodOfSum_pipe1;
Complex3Multiply_twiddle_re_pipe1 <= twdl_re_reg;
Complex3Multiply_twiddle_im_pipe1 <= twdl_im_reg;
Complex3Multiply_twiddle_sum_pipe1 <= twdl_sum;
Complex3Multiply_din1_re_pipe1 <= din_re_reg;
Complex3Multiply_din1_im_pipe1 <= din_im_reg;
Complex3Multiply_din1_sum_pipe1 <= din_sum;
Complex3Multiply_prodOfRe_pipe1 <= Complex3Multiply_din1_re_pipe1 * Complex3Multiply_twiddle_re_pipe1;
Complex3Multiply_ProdOfIm_pipe1 <= Complex3Multiply_din1_im_pipe1 * Complex3Multiply_twiddle_im_pipe1;
Complex3Multiply_prodOfSum_pipe1 <= Complex3Multiply_din1_sum_pipe1 * Complex3Multiply_twiddle_sum_pipe1;
END IF;
END IF;
END PROCESS Complex3Multiply_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly1 <= din1_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly2 <= din_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly3 <= din_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
prod_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prod_vld <= din_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_7_process;
-- Complex3Add
Complex3Add_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Complex3Add_prodOfSum_reg <= to_signed(0, 39);
Complex3Add_tmpResult_reg <= to_signed(0, 39);
Complex3Add_multRes_re_reg1 <= to_signed(0, 38);
Complex3Add_multRes_re_reg2 <= to_signed(0, 38);
Complex3Add_multRes_im_reg <= to_signed(0, 40);
Complex3Add_prod_vld_reg1 <= '0';
Complex3Add_prod_vld_reg2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Complex3Add_tmpResult_reg <= Complex3Add_tmpResult_reg_next;
Complex3Add_multRes_re_reg1 <= Complex3Add_multRes_re_reg1_next;
Complex3Add_multRes_re_reg2 <= Complex3Add_multRes_re_reg2_next;
Complex3Add_multRes_im_reg <= Complex3Add_multRes_im_reg_next;
Complex3Add_prod_vld_reg1 <= Complex3Add_prod_vld_reg1_next;
Complex3Add_prod_vld_reg2 <= Complex3Add_prod_vld_reg2_next;
Complex3Add_prodOfSum_reg <= Complex3Add_prodOfSum_reg_next;
END IF;
END IF;
END PROCESS Complex3Add_process;
Complex3Add_output : PROCESS (Complex3Add_tmpResult_reg, Complex3Add_multRes_re_reg1,
Complex3Add_multRes_re_reg2, Complex3Add_multRes_im_reg,
Complex3Add_prod_vld_reg1, Complex3Add_prod_vld_reg2,
Complex3Add_prodOfSum_reg, prodOfRe, prodOfIm, prodOfSum, prod_vld)
VARIABLE sub_cast : signed(37 DOWNTO 0);
VARIABLE sub_cast_0 : signed(37 DOWNTO 0);
VARIABLE sub_cast_1 : signed(39 DOWNTO 0);
VARIABLE sub_cast_2 : signed(39 DOWNTO 0);
VARIABLE add_cast : signed(37 DOWNTO 0);
VARIABLE add_cast_0 : signed(37 DOWNTO 0);
VARIABLE add_temp : signed(37 DOWNTO 0);
BEGIN
Complex3Add_tmpResult_reg_next <= Complex3Add_tmpResult_reg;
Complex3Add_multRes_re_reg1_next <= Complex3Add_multRes_re_reg1;
Complex3Add_prodOfSum_reg_next <= Complex3Add_prodOfSum_reg;
Complex3Add_multRes_re_reg2_next <= Complex3Add_multRes_re_reg1;
IF prod_vld = '1' THEN
sub_cast := resize(prodOfRe, 38);
sub_cast_0 := resize(prodOfIm, 38);
Complex3Add_multRes_re_reg1_next <= sub_cast - sub_cast_0;
END IF;
sub_cast_1 := resize(Complex3Add_prodOfSum_reg, 40);
sub_cast_2 := resize(Complex3Add_tmpResult_reg, 40);
Complex3Add_multRes_im_reg_next <= sub_cast_1 - sub_cast_2;
IF prod_vld = '1' THEN
add_cast := resize(prodOfRe, 38);
add_cast_0 := resize(prodOfIm, 38);
add_temp := add_cast + add_cast_0;
Complex3Add_tmpResult_reg_next <= resize(add_temp, 39);
END IF;
IF prod_vld = '1' THEN
Complex3Add_prodOfSum_reg_next <= prodOfSum;
END IF;
Complex3Add_prod_vld_reg2_next <= Complex3Add_prod_vld_reg1;
Complex3Add_prod_vld_reg1_next <= prod_vld;
multResFP_re <= Complex3Add_multRes_re_reg2;
multResFP_im <= Complex3Add_multRes_im_reg;
twdlXdin1_vld <= Complex3Add_prod_vld_reg2;
END PROCESS Complex3Add_output;
twdlXdin_7_re_tmp <= multResFP_re(34 DOWNTO 15);
twdlXdin_7_re <= std_logic_vector(twdlXdin_7_re_tmp);
twdlXdin_7_im_tmp <= multResFP_im(34 DOWNTO 15);
twdlXdin_7_im <= std_logic_vector(twdlXdin_7_im_tmp);
END rtl;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cdcfifo_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE cdcfifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT cdcfifo_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_exdes IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END cdcfifo_pkg;
PACKAGE BODY cdcfifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END cdcfifo_pkg;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cdcfifo_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE cdcfifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT cdcfifo_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_exdes IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END cdcfifo_pkg;
PACKAGE BODY cdcfifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END cdcfifo_pkg;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cdcfifo_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE cdcfifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT cdcfifo_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_exdes IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END cdcfifo_pkg;
PACKAGE BODY cdcfifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END cdcfifo_pkg;
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TernaryInConcatExample IS
PORT(
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
c : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF TernaryInConcatExample IS
BEGIN
assig_process_c: PROCESS(a, b)
VARIABLE tmpBool2std_logic_0 : STD_LOGIC;
VARIABLE tmpBool2std_logic_1 : STD_LOGIC;
VARIABLE tmpBool2std_logic_2 : STD_LOGIC;
VARIABLE tmpBool2std_logic_3 : STD_LOGIC;
VARIABLE tmpBool2std_logic_4 : STD_LOGIC;
VARIABLE tmpBool2std_logic_5 : STD_LOGIC;
BEGIN
IF a > b THEN
tmpBool2std_logic_0 := '1';
ELSE
tmpBool2std_logic_0 := '0';
END IF;
IF a >= b THEN
tmpBool2std_logic_1 := '1';
ELSE
tmpBool2std_logic_1 := '0';
END IF;
IF a = b THEN
tmpBool2std_logic_2 := '1';
ELSE
tmpBool2std_logic_2 := '0';
END IF;
IF a <= b THEN
tmpBool2std_logic_3 := '1';
ELSE
tmpBool2std_logic_3 := '0';
END IF;
IF a < b THEN
tmpBool2std_logic_4 := '1';
ELSE
tmpBool2std_logic_4 := '0';
END IF;
IF a /= b THEN
tmpBool2std_logic_5 := '1';
ELSE
tmpBool2std_logic_5 := '0';
END IF;
c <= X"F" & tmpBool2std_logic_5 & tmpBool2std_logic_4 & tmpBool2std_logic_3 & tmpBool2std_logic_2 & tmpBool2std_logic_1 & tmpBool2std_logic_0 & "0000000000000000000000";
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
S_ACLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_synth IS
CONSTANT AWID_OFFSET : INTEGER := if_then_else(1 = 1,63 - 1,63);
CONSTANT AWADDR_OFFSET : INTEGER := AWID_OFFSET - 32;
CONSTANT AWLEN_OFFSET : INTEGER := if_then_else(1 = 1,AWADDR_OFFSET - 8,AWADDR_OFFSET);
CONSTANT AWSIZE_OFFSET : INTEGER := if_then_else(1 = 1,AWLEN_OFFSET - 3,AWLEN_OFFSET);
CONSTANT AWBURST_OFFSET : INTEGER := if_then_else(1 = 1,AWSIZE_OFFSET - 2,AWSIZE_OFFSET);
CONSTANT AWLOCK_OFFSET : INTEGER := if_then_else(1 = 1,AWBURST_OFFSET - 2,AWBURST_OFFSET);
CONSTANT AWCACHE_OFFSET : INTEGER := if_then_else(1 = 1,AWLOCK_OFFSET - 4,AWLOCK_OFFSET);
CONSTANT AWPROT_OFFSET : INTEGER := AWCACHE_OFFSET - 3;
CONSTANT AWQOS_OFFSET : INTEGER := AWPROT_OFFSET - 4;
CONSTANT AWREGION_OFFSET : INTEGER := AWQOS_OFFSET - 4;
CONSTANT AWUSER_OFFSET : INTEGER := if_then_else(0 = 1,AWREGION_OFFSET-4,AWREGION_OFFSET);
CONSTANT WID_OFFSET : INTEGER := if_then_else(1 = 1,74 - 1,74);
CONSTANT WDATA_OFFSET : INTEGER := WID_OFFSET - 64;
CONSTANT WSTRB_OFFSET : INTEGER := WDATA_OFFSET - 64/8;
CONSTANT WUSER_OFFSET : INTEGER := if_then_else(0 = 1,WSTRB_OFFSET-1,WSTRB_OFFSET);
CONSTANT BID_OFFSET : INTEGER := if_then_else(1 = 1,6 - 1,6);
CONSTANT BRESP_OFFSET : INTEGER := BID_OFFSET - 2;
CONSTANT BUSER_OFFSET : INTEGER := if_then_else(0 = 1,BRESP_OFFSET-1,BRESP_OFFSET);
CONSTANT ARID_OFFSET : INTEGER := if_then_else(1 = 1,63 - 1,63);
CONSTANT ARADDR_OFFSET : INTEGER := ARID_OFFSET - 32;
CONSTANT ARLEN_OFFSET : INTEGER := if_then_else(1 = 1,ARADDR_OFFSET - 8,ARADDR_OFFSET);
CONSTANT ARSIZE_OFFSET : INTEGER := if_then_else(1 = 1,ARLEN_OFFSET - 3,ARLEN_OFFSET);
CONSTANT ARBURST_OFFSET : INTEGER := if_then_else(1 = 1,ARSIZE_OFFSET - 2,ARSIZE_OFFSET);
CONSTANT ARLOCK_OFFSET : INTEGER := if_then_else(1 = 1,ARBURST_OFFSET - 2,ARBURST_OFFSET);
CONSTANT ARCACHE_OFFSET : INTEGER := if_then_else(1 = 1,ARLOCK_OFFSET - 4,ARLOCK_OFFSET);
CONSTANT ARPROT_OFFSET : INTEGER := ARCACHE_OFFSET - 3;
CONSTANT ARQOS_OFFSET : INTEGER := ARPROT_OFFSET - 4;
CONSTANT ARREGION_OFFSET : INTEGER := ARQOS_OFFSET - 4;
CONSTANT ARUSER_OFFSET : INTEGER := if_then_else(0 = 1,ARREGION_OFFSET-4,ARREGION_OFFSET);
CONSTANT RID_OFFSET : INTEGER := if_then_else(1 = 1,68 - 1,68);
CONSTANT RDATA_OFFSET : INTEGER := RID_OFFSET - 64;
CONSTANT RRESP_OFFSET : INTEGER := RDATA_OFFSET - 2;
CONSTANT RUSER_OFFSET : INTEGER := if_then_else(0 = 1,RRESP_OFFSET-1,RRESP_OFFSET);
-- FIFO interface signal declarations
SIGNAL s_aresetn : STD_LOGIC;
SIGNAL m_axi_awid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL m_axi_awaddr : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL m_axi_awlen : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL m_axi_awsize : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL m_axi_awburst : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL m_axi_awlock : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL m_axi_awcache : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL m_axi_awprot : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL m_axi_awqos : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL m_axi_awregion : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL m_axi_awvalid : STD_LOGIC;
SIGNAL m_axi_awready : STD_LOGIC;
SIGNAL m_axi_wid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL m_axi_wdata : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL m_axi_wstrb : STD_LOGIC_VECTOR(64/8-1 DOWNTO 0);
SIGNAL m_axi_wlast : STD_LOGIC;
SIGNAL m_axi_wvalid : STD_LOGIC;
SIGNAL m_axi_wready : STD_LOGIC;
SIGNAL m_axi_bid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL m_axi_bresp : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL m_axi_bvalid : STD_LOGIC;
SIGNAL m_axi_bready : STD_LOGIC;
SIGNAL s_axi_awid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL s_axi_awaddr : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL s_axi_awlen : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL s_axi_awsize : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL s_axi_awburst : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL s_axi_awlock : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL s_axi_awcache : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL s_axi_awprot : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL s_axi_awqos : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL s_axi_awregion : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL s_axi_awvalid : STD_LOGIC;
SIGNAL s_axi_awready : STD_LOGIC;
SIGNAL s_axi_wid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL s_axi_wdata : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL s_axi_wstrb : STD_LOGIC_VECTOR(64/8-1 DOWNTO 0);
SIGNAL s_axi_wlast : STD_LOGIC;
SIGNAL s_axi_wvalid : STD_LOGIC;
SIGNAL s_axi_wready : STD_LOGIC;
SIGNAL s_axi_bid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL s_axi_bresp : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL s_axi_bvalid : STD_LOGIC;
SIGNAL s_axi_bready : STD_LOGIC;
SIGNAL m_axi_arid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL m_axi_araddr : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL m_axi_arlen : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL m_axi_arsize : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL m_axi_arburst : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL m_axi_arlock : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL m_axi_arcache : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL m_axi_arprot : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL m_axi_arqos : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL m_axi_arregion : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL m_axi_arvalid : STD_LOGIC;
SIGNAL m_axi_arready : STD_LOGIC;
SIGNAL m_axi_rid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL m_axi_rdata : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL m_axi_rresp : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL m_axi_rlast : STD_LOGIC;
SIGNAL m_axi_rvalid : STD_LOGIC;
SIGNAL m_axi_rready : STD_LOGIC;
SIGNAL s_axi_arid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL s_axi_araddr : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL s_axi_arlen : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL s_axi_arsize : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL s_axi_arburst : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL s_axi_arlock : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL s_axi_arcache : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL s_axi_arprot : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL s_axi_arqos : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL s_axi_arregion : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL s_axi_arvalid : STD_LOGIC;
SIGNAL s_axi_arready : STD_LOGIC;
SIGNAL s_axi_rid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL s_axi_rdata : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL s_axi_rresp : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL s_axi_rlast : STD_LOGIC;
SIGNAL s_axi_rvalid : STD_LOGIC;
SIGNAL s_axi_rready : STD_LOGIC;
SIGNAL axi_aw_prog_full : STD_LOGIC;
SIGNAL axi_aw_prog_empty : STD_LOGIC;
SIGNAL axi_w_prog_full : STD_LOGIC;
SIGNAL axi_w_prog_empty : STD_LOGIC;
SIGNAL axi_b_prog_full : STD_LOGIC;
SIGNAL axi_b_prog_empty : STD_LOGIC;
SIGNAL axi_ar_prog_full : STD_LOGIC;
SIGNAL axi_ar_prog_empty : STD_LOGIC;
SIGNAL axi_r_prog_full : STD_LOGIC;
SIGNAL axi_r_prog_empty : STD_LOGIC;
SIGNAL s_aclk_i : STD_LOGIC;
-- TB Signals
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL status_wach : STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL status_wdch : STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL status_wrch : STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL sim_done_wach : STD_LOGIC := '0';
SIGNAL sim_done_wdch : STD_LOGIC := '0';
SIGNAL sim_done_wrch : STD_LOGIC := '0';
SIGNAL reset_en_wach : STD_LOGIC := '0';
SIGNAL reset_en_wdch : STD_LOGIC := '0';
SIGNAL reset_en_wrch : STD_LOGIC := '0';
SIGNAL wr_en_wach : STD_LOGIC := '0';
SIGNAL rd_en_wach : STD_LOGIC := '0';
SIGNAL full_wach : STD_LOGIC := '0';
SIGNAL empty_wach : STD_LOGIC := '0';
SIGNAL wr_en_wdch : STD_LOGIC := '0';
SIGNAL rd_en_wdch : STD_LOGIC := '0';
SIGNAL full_wdch : STD_LOGIC := '0';
SIGNAL empty_wdch : STD_LOGIC := '0';
SIGNAL wr_en_wrch : STD_LOGIC := '0';
SIGNAL rd_en_wrch : STD_LOGIC := '0';
SIGNAL full_wrch : STD_LOGIC := '0';
SIGNAL empty_wrch : STD_LOGIC := '0';
SIGNAL prc_we_wach : STD_LOGIC := '0';
SIGNAL prc_we_wdch : STD_LOGIC := '0';
SIGNAL prc_we_wrch : STD_LOGIC := '0';
SIGNAL prc_re_wach : STD_LOGIC := '0';
SIGNAL prc_re_wdch : STD_LOGIC := '0';
SIGNAL prc_re_wrch : STD_LOGIC := '0';
SIGNAL dout_chk_wach : STD_LOGIC := '0';
SIGNAL dout_chk_wdch : STD_LOGIC := '0';
SIGNAL dout_chk_wrch : STD_LOGIC := '0';
SIGNAL status_rach : STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL status_rdch : STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL sim_done_rach : STD_LOGIC := '0';
SIGNAL sim_done_rdch : STD_LOGIC := '0';
SIGNAL reset_en_rach : STD_LOGIC := '0';
SIGNAL reset_en_rdch : STD_LOGIC := '0';
SIGNAL wr_en_rach : STD_LOGIC := '0';
SIGNAL rd_en_rach : STD_LOGIC := '0';
SIGNAL full_rach : STD_LOGIC := '0';
SIGNAL empty_rach : STD_LOGIC := '0';
SIGNAL wr_en_rdch : STD_LOGIC := '0';
SIGNAL rd_en_rdch : STD_LOGIC := '0';
SIGNAL full_rdch : STD_LOGIC := '0';
SIGNAL empty_rdch : STD_LOGIC := '0';
SIGNAL prc_we_rach : STD_LOGIC := '0';
SIGNAL prc_we_rdch : STD_LOGIC := '0';
SIGNAL prc_re_rach : STD_LOGIC := '0';
SIGNAL prc_re_rdch : STD_LOGIC := '0';
SIGNAL dout_chk_rach : STD_LOGIC := '0';
SIGNAL dout_chk_rdch : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL din_wach : STD_LOGIC_VECTOR(63-1 DOWNTO 0);
SIGNAL din_wdch : STD_LOGIC_VECTOR(74-1 DOWNTO 0);
SIGNAL din_wrch : STD_LOGIC_VECTOR(6-1 DOWNTO 0);
SIGNAL dout_wach : STD_LOGIC_VECTOR(63-1 DOWNTO 0);
SIGNAL dout_wdch : STD_LOGIC_VECTOR(74-1 DOWNTO 0);
SIGNAL dout_wrch : STD_LOGIC_VECTOR(6-1 DOWNTO 0);
SIGNAL din_rach : STD_LOGIC_VECTOR(63-1 DOWNTO 0);
SIGNAL din_rdch : STD_LOGIC_VECTOR(68-1 DOWNTO 0);
SIGNAL dout_rach : STD_LOGIC_VECTOR(63-1 DOWNTO 0);
SIGNAL dout_rdch : STD_LOGIC_VECTOR(68-1 DOWNTO 0);
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(s_aclk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(s_aclk_i'event AND s_aclk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(s_aclk_i)
BEGIN
IF(s_aclk_i'event AND s_aclk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
s_aclk_i <= S_ACLK;
------------------
s_aresetn <= NOT (RESET OR rst_s_rd) AFTER 12 ns;
STATUS <= status_wach OR status_wdch OR status_wrch OR status_rach OR status_rdch;
SIM_DONE <= sim_done_wach AND sim_done_wdch AND sim_done_wrch AND sim_done_rach AND sim_done_rdch;
reset_en <= reset_en_wach AND reset_en_wdch AND reset_en_wrch AND reset_en_rach AND reset_en_rdch;
s_axi_awvalid <= wr_en_wach;
m_axi_awready <= rd_en_wach;
full_wach <= NOT s_axi_awready;
empty_wach <= NOT m_axi_awvalid;
s_axi_wvalid <= wr_en_wdch;
m_axi_wready <= rd_en_wdch;
full_wdch <= NOT s_axi_wready;
empty_wdch <= NOT m_axi_wvalid;
m_axi_bvalid <= wr_en_wrch;
s_axi_bready <= rd_en_wrch;
full_wrch <= NOT m_axi_bready;
empty_wrch <= NOT s_axi_bvalid;
--- WACH
fg_dg_wach: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dgen
GENERIC MAP (
C_DIN_WIDTH => 63,
C_DOUT_WIDTH => 63,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET => rst_int_wr,
WR_CLK => s_aclk_i,
PRC_WR_EN => prc_we_wach,
FULL => full_wach,
WR_EN => wr_en_wach,
WR_DATA => din_wach
);
fg_dv_wach: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dverif
GENERIC MAP (
C_DOUT_WIDTH => 63,
C_DIN_WIDTH => 63,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => s_aclk_i,
PRC_RD_EN => prc_re_wach,
RD_EN => rd_en_wach,
EMPTY => empty_wach,
DATA_OUT => dout_wach,
DOUT_CHK => dout_chk_wach
);
fg_pc_wach: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pctrl
GENERIC MAP (
AXI_CHANNEL => "WACH",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 63,
C_DIN_WIDTH => 63,
C_WR_PNTR_WIDTH => 5,
C_RD_PNTR_WIDTH => 5,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_STOP_CNT => TB_STOP_CNT,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en_wach,
WR_CLK => s_aclk_i,
RD_CLK => s_aclk_i,
PRC_WR_EN => prc_we_wach,
PRC_RD_EN => prc_re_wach,
FULL => full_wach,
EMPTY => empty_wach,
ALMOST_FULL => '0',
ALMOST_EMPTY => '0',
DATA_IN => din_wach,
DATA_OUT => dout_wach,
DOUT_CHK => dout_chk_wach,
SIM_DONE => sim_done_wach,
STATUS => status_wach
);
--- WDCH
fg_dg_wdch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dgen
GENERIC MAP (
C_DIN_WIDTH => 74,
C_DOUT_WIDTH => 74,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET => rst_int_wr,
WR_CLK => s_aclk_i,
PRC_WR_EN => prc_we_wdch,
FULL => full_wdch,
WR_EN => wr_en_wdch,
WR_DATA => din_wdch
);
fg_dv_wdch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dverif
GENERIC MAP (
C_DOUT_WIDTH => 74,
C_DIN_WIDTH => 74,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET => rst_int_rd,
RD_CLK => s_aclk_i,
PRC_RD_EN => prc_re_wdch,
RD_EN => rd_en_wdch,
EMPTY => empty_wdch,
DATA_OUT => dout_wdch,
DOUT_CHK => dout_chk_wdch
);
fg_pc_wdch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pctrl
GENERIC MAP (
AXI_CHANNEL => "WDCH",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 74,
C_DIN_WIDTH => 74,
C_WR_PNTR_WIDTH => 1,
C_RD_PNTR_WIDTH => 1,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_STOP_CNT => TB_STOP_CNT,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en_wdch,
WR_CLK => s_aclk_i,
RD_CLK => s_aclk_i,
PRC_WR_EN => prc_we_wdch,
PRC_RD_EN => prc_re_wdch,
FULL => full_wdch,
EMPTY => empty_wdch,
ALMOST_FULL => '0',
ALMOST_EMPTY => '0',
DATA_IN => din_wdch,
DATA_OUT => dout_wdch,
DOUT_CHK => dout_chk_wdch,
SIM_DONE => sim_done_wdch,
STATUS => status_wdch
);
--- WRCH
fg_dg_wrch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dgen
GENERIC MAP (
C_DIN_WIDTH => 6,
C_DOUT_WIDTH => 6,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET => rst_int_rd,
WR_CLK => s_aclk_i,
PRC_WR_EN => prc_we_wrch,
FULL => full_wrch,
WR_EN => wr_en_wrch,
WR_DATA => din_wrch
);
fg_dv_wrch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dverif
GENERIC MAP (
C_DOUT_WIDTH => 6,
C_DIN_WIDTH => 6,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET => rst_int_wr,
RD_CLK => s_aclk_i,
PRC_RD_EN => prc_re_wrch,
RD_EN => rd_en_wrch,
EMPTY => empty_wrch,
DATA_OUT => dout_wrch,
DOUT_CHK => dout_chk_wrch
);
fg_pc_wrch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pctrl
GENERIC MAP (
AXI_CHANNEL => "WRCH",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 6,
C_DIN_WIDTH => 6,
C_WR_PNTR_WIDTH => 4,
C_RD_PNTR_WIDTH => 4,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_STOP_CNT => TB_STOP_CNT,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET_WR => rst_int_rd,
RESET_RD => rst_int_wr,
RESET_EN => reset_en_wrch,
WR_CLK => s_aclk_i,
RD_CLK => s_aclk_i,
PRC_WR_EN => prc_we_wrch,
PRC_RD_EN => prc_re_wrch,
FULL => full_wrch,
EMPTY => empty_wrch,
ALMOST_FULL => '0',
ALMOST_EMPTY => '0',
DATA_IN => din_wrch,
DATA_OUT => dout_wrch,
DOUT_CHK => dout_chk_wrch,
SIM_DONE => sim_done_wrch,
STATUS => status_wrch
);
dout_wach <= m_axi_awid & m_axi_awaddr & m_axi_awlen & m_axi_awsize & m_axi_awburst & m_axi_awlock
& m_axi_awcache & m_axi_awprot & m_axi_awqos & m_axi_awregion;
s_axi_awid <= din_wach(63-1 DOWNTO AWID_OFFSET);
s_axi_awaddr <= din_wach(AWID_OFFSET-1 DOWNTO AWADDR_OFFSET);
s_axi_awlen <= din_wach(AWADDR_OFFSET-1 DOWNTO AWLEN_OFFSET);
s_axi_awsize <= din_wach(AWLEN_OFFSET-1 DOWNTO AWSIZE_OFFSET);
s_axi_awburst <= din_wach(AWSIZE_OFFSET-1 DOWNTO AWBURST_OFFSET);
s_axi_awlock <= din_wach(AWBURST_OFFSET-1 DOWNTO AWLOCK_OFFSET);
s_axi_awcache <= din_wach(AWLOCK_OFFSET-1 DOWNTO AWCACHE_OFFSET);
s_axi_awprot <= din_wach(AWCACHE_OFFSET-1 DOWNTO AWPROT_OFFSET);
s_axi_awqos <= din_wach(AWPROT_OFFSET-1 DOWNTO AWQOS_OFFSET);
s_axi_awregion <= din_wach(AWQOS_OFFSET-1 DOWNTO AWREGION_OFFSET);
dout_wdch <= m_axi_wid & m_axi_wdata & m_axi_wstrb & m_axi_wlast;
s_axi_wid <= din_wdch(74-1 DOWNTO WID_OFFSET);
s_axi_wdata <= din_wdch(WID_OFFSET-1 DOWNTO WDATA_OFFSET);
s_axi_wstrb <= din_wdch(WDATA_OFFSET-1 DOWNTO WSTRB_OFFSET);
s_axi_wlast <= din_wdch(0);
dout_wrch <= s_axi_bid & s_axi_bresp;
m_axi_bid <= din_wrch(6-1 DOWNTO BID_OFFSET);
m_axi_bresp <= din_wrch(BID_OFFSET-1 DOWNTO BRESP_OFFSET);
s_axi_arvalid <= wr_en_rach;
m_axi_arready <= rd_en_rach;
full_rach <= NOT s_axi_arready;
empty_rach <= NOT m_axi_arvalid;
m_axi_rvalid <= wr_en_rdch;
s_axi_rready <= rd_en_rdch;
full_rdch <= NOT m_axi_rready;
empty_rdch <= NOT s_axi_rvalid;
--- RACH
fg_dg_rach: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dgen
GENERIC MAP (
C_DIN_WIDTH => 63,
C_DOUT_WIDTH => 63,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET => rst_int_wr,
WR_CLK => s_aclk_i,
PRC_WR_EN => prc_we_rach,
FULL => full_rach,
WR_EN => wr_en_rach,
WR_DATA => din_rach
);
fg_dv_rach: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dverif
GENERIC MAP (
C_DOUT_WIDTH => 63,
C_DIN_WIDTH => 63,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET => rst_int_rd,
RD_CLK => s_aclk_i,
PRC_RD_EN => prc_re_rach,
RD_EN => rd_en_rach,
EMPTY => empty_rach,
DATA_OUT => dout_rach,
DOUT_CHK => dout_chk_rach
);
fg_pc_rach: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pctrl
GENERIC MAP (
AXI_CHANNEL => "RACH",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 63,
C_DIN_WIDTH => 63,
C_WR_PNTR_WIDTH => 5,
C_RD_PNTR_WIDTH => 5,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_STOP_CNT => TB_STOP_CNT,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en_rach,
WR_CLK => s_aclk_i,
RD_CLK => s_aclk_i,
PRC_WR_EN => prc_we_rach,
PRC_RD_EN => prc_re_rach,
FULL => full_rach,
EMPTY => empty_rach,
ALMOST_FULL => '0',
ALMOST_EMPTY => '0',
DATA_IN => din_rach,
DATA_OUT => dout_rach,
DOUT_CHK => dout_chk_rach,
SIM_DONE => sim_done_rach,
STATUS => status_rach
);
--- RDCH
fg_dg_rdch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dgen
GENERIC MAP (
C_DIN_WIDTH => 68,
C_DOUT_WIDTH => 68,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP (
RESET => rst_int_rd,
WR_CLK => s_aclk_i,
PRC_WR_EN => prc_we_rdch,
FULL => full_rdch,
WR_EN => wr_en_rdch,
WR_DATA => din_rdch
);
fg_dv_rdch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dverif
GENERIC MAP (
C_DOUT_WIDTH => 68,
C_DIN_WIDTH => 68,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP (
RESET => rst_int_wr,
RD_CLK => s_aclk_i,
PRC_RD_EN => prc_re_rdch,
RD_EN => rd_en_rdch,
EMPTY => empty_rdch,
DATA_OUT => dout_rdch,
DOUT_CHK => dout_chk_rdch
);
fg_pc_rdch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pctrl
GENERIC MAP (
AXI_CHANNEL => "RDCH",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 68,
C_DIN_WIDTH => 68,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_STOP_CNT => TB_STOP_CNT,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP (
RESET_WR => rst_int_rd,
RESET_RD => rst_int_wr,
RESET_EN => reset_en_rdch,
WR_CLK => s_aclk_i,
RD_CLK => s_aclk_i,
PRC_WR_EN => prc_we_rdch,
PRC_RD_EN => prc_re_rdch,
FULL => full_rdch,
EMPTY => empty_rdch,
ALMOST_FULL => '0',
ALMOST_EMPTY => '0',
DATA_IN => din_rdch,
DATA_OUT => dout_rdch,
DOUT_CHK => dout_chk_rdch,
SIM_DONE => sim_done_rdch,
STATUS => status_rdch
);
dout_rach <= m_axi_arid & m_axi_araddr & m_axi_arlen & m_axi_arsize & m_axi_arburst & m_axi_arlock & m_axi_arcache & m_axi_arprot
& m_axi_arqos & m_axi_arregion;
s_axi_arid <= din_rach(63-1 DOWNTO ARID_OFFSET);
s_axi_araddr <= din_rach(ARID_OFFSET-1 DOWNTO ARADDR_OFFSET);
s_axi_arlen <= din_rach(ARADDR_OFFSET-1 DOWNTO ARLEN_OFFSET);
s_axi_arsize <= din_rach(ARLEN_OFFSET-1 DOWNTO ARSIZE_OFFSET);
s_axi_arburst <= din_rach(ARSIZE_OFFSET-1 DOWNTO ARBURST_OFFSET);
s_axi_arlock <= din_rach(ARBURST_OFFSET-1 DOWNTO ARLOCK_OFFSET);
s_axi_arcache <= din_rach(ARLOCK_OFFSET-1 DOWNTO ARCACHE_OFFSET);
s_axi_arprot <= din_rach(ARCACHE_OFFSET-1 DOWNTO ARPROT_OFFSET);
s_axi_arqos <= din_rach(ARPROT_OFFSET-1 DOWNTO ARQOS_OFFSET);
s_axi_arregion <= din_rach(ARQOS_OFFSET-1 DOWNTO ARREGION_OFFSET);
dout_rdch <= s_axi_rid & s_axi_rdata & s_axi_rresp & s_axi_rlast;
m_axi_rid <= din_rdch(68-1 DOWNTO RID_OFFSET);
m_axi_rdata <= din_rdch(RID_OFFSET-1 DOWNTO RDATA_OFFSET);
m_axi_rresp <= din_rdch(RDATA_OFFSET-1 DOWNTO RRESP_OFFSET);
m_axi_rlast <= din_rdch(0);
system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_inst : system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_exdes
PORT MAP (
S_ARESETN => s_aresetn,
M_AXI_AWID => m_axi_awid,
M_AXI_AWADDR => m_axi_awaddr,
M_AXI_AWLEN => m_axi_awlen,
M_AXI_AWSIZE => m_axi_awsize,
M_AXI_AWBURST => m_axi_awburst,
M_AXI_AWLOCK => m_axi_awlock,
M_AXI_AWCACHE => m_axi_awcache,
M_AXI_AWPROT => m_axi_awprot,
M_AXI_AWQOS => m_axi_awqos,
M_AXI_AWREGION => m_axi_awregion,
M_AXI_AWVALID => m_axi_awvalid,
M_AXI_AWREADY => m_axi_awready,
M_AXI_WID => m_axi_wid,
M_AXI_WDATA => m_axi_wdata,
M_AXI_WSTRB => m_axi_wstrb,
M_AXI_WLAST => m_axi_wlast,
M_AXI_WVALID => m_axi_wvalid,
M_AXI_WREADY => m_axi_wready,
M_AXI_BID => m_axi_bid,
M_AXI_BRESP => m_axi_bresp,
M_AXI_BVALID => m_axi_bvalid,
M_AXI_BREADY => m_axi_bready,
S_AXI_AWID => s_axi_awid,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWLEN => s_axi_awlen,
S_AXI_AWSIZE => s_axi_awsize,
S_AXI_AWBURST => s_axi_awburst,
S_AXI_AWLOCK => s_axi_awlock,
S_AXI_AWCACHE => s_axi_awcache,
S_AXI_AWPROT => s_axi_awprot,
S_AXI_AWQOS => s_axi_awqos,
S_AXI_AWREGION => s_axi_awregion,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WID => s_axi_wid,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WLAST => s_axi_wlast,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BID => s_axi_bid,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
M_AXI_ARID => m_axi_arid,
M_AXI_ARADDR => m_axi_araddr,
M_AXI_ARLEN => m_axi_arlen,
M_AXI_ARSIZE => m_axi_arsize,
M_AXI_ARBURST => m_axi_arburst,
M_AXI_ARLOCK => m_axi_arlock,
M_AXI_ARCACHE => m_axi_arcache,
M_AXI_ARPROT => m_axi_arprot,
M_AXI_ARQOS => m_axi_arqos,
M_AXI_ARREGION => m_axi_arregion,
M_AXI_ARVALID => m_axi_arvalid,
M_AXI_ARREADY => m_axi_arready,
M_AXI_RID => m_axi_rid,
M_AXI_RDATA => m_axi_rdata,
M_AXI_RRESP => m_axi_rresp,
M_AXI_RLAST => m_axi_rlast,
M_AXI_RVALID => m_axi_rvalid,
M_AXI_RREADY => m_axi_rready,
S_AXI_ARID => s_axi_arid,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARLEN => s_axi_arlen,
S_AXI_ARSIZE => s_axi_arsize,
S_AXI_ARBURST => s_axi_arburst,
S_AXI_ARLOCK => s_axi_arlock,
S_AXI_ARCACHE => s_axi_arcache,
S_AXI_ARPROT => s_axi_arprot,
S_AXI_ARQOS => s_axi_arqos,
S_AXI_ARREGION => s_axi_arregion,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RID => s_axi_rid,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RLAST => s_axi_rlast,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
AXI_AW_PROG_FULL => axi_aw_prog_full,
AXI_AW_PROG_EMPTY => axi_aw_prog_empty,
AXI_W_PROG_FULL => axi_w_prog_full,
AXI_W_PROG_EMPTY => axi_w_prog_empty,
AXI_B_PROG_FULL => axi_b_prog_full,
AXI_B_PROG_EMPTY => axi_b_prog_empty,
AXI_AR_PROG_FULL => axi_ar_prog_full,
AXI_AR_PROG_EMPTY => axi_ar_prog_empty,
AXI_R_PROG_FULL => axi_r_prog_full,
AXI_R_PROG_EMPTY => axi_r_prog_empty,
S_ACLK => s_aclk_i);
END ARCHITECTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc882.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c10s01b00x00p07n01i00882ent_a is
generic (
GS1: INTEGER := 3;
GS2: INTEGER := 9
);
port (
PS1: out INTEGER;
PS2: out INTEGER
);
end c10s01b00x00p07n01i00882ent_a;
architecture c10s01b00x00p07n01i00882arch_a of c10s01b00x00p07n01i00882ent_a is
begin
process
begin
PS1 <= GS1 + 1;
PS2 <= GS2 + 2;
wait; -- forever
end process;
end c10s01b00x00p07n01i00882arch_a;
use WORK.c10s01b00x00p07n01i00882ent_a;
ENTITY c10s01b00x00p07n01i00882ent IS
END c10s01b00x00p07n01i00882ent;
ARCHITECTURE c10s01b00x00p07n01i00882arch OF c10s01b00x00p07n01i00882ent IS
signal G1: INTEGER;
signal G2: INTEGER;
signal A : INTEGER;
signal B : INTEGER;
component c10s01b00x00p07n01i00882ent_a
generic ( G1, G2: INTEGER );
port ( A, B: out INTEGER );
end component;
signal S1: INTEGER;
signal S2: INTEGER;
BEGIN
A1: c10s01b00x00p07n01i00882ent_a generic map ( 3, 9 ) port map ( S1, S2 );
-- verification
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT( S1=4 and S2=11 )
report "***PASSED TEST: c10s01b00x00p07n01i00882"
severity NOTE;
assert ( S1=4 and S2=11 )
report "***FAILED TEST: c10s01b00x00p07n01i00882 - A declarative region is formed by the text of a component declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s01b00x00p07n01i00882arch;
configuration c10s01b00x00p07n01i00882cfg of c10s01b00x00p07n01i00882ent is
for c10s01b00x00p07n01i00882arch
for A1: c10s01b00x00p07n01i00882ent_a
use entity c10s01b00x00p07n01i00882ent_a (c10s01b00x00p07n01i00882arch_a )
generic map ( G1, G2 )
port map ( A, B );
end for;
end for;
end c10s01b00x00p07n01i00882cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc882.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c10s01b00x00p07n01i00882ent_a is
generic (
GS1: INTEGER := 3;
GS2: INTEGER := 9
);
port (
PS1: out INTEGER;
PS2: out INTEGER
);
end c10s01b00x00p07n01i00882ent_a;
architecture c10s01b00x00p07n01i00882arch_a of c10s01b00x00p07n01i00882ent_a is
begin
process
begin
PS1 <= GS1 + 1;
PS2 <= GS2 + 2;
wait; -- forever
end process;
end c10s01b00x00p07n01i00882arch_a;
use WORK.c10s01b00x00p07n01i00882ent_a;
ENTITY c10s01b00x00p07n01i00882ent IS
END c10s01b00x00p07n01i00882ent;
ARCHITECTURE c10s01b00x00p07n01i00882arch OF c10s01b00x00p07n01i00882ent IS
signal G1: INTEGER;
signal G2: INTEGER;
signal A : INTEGER;
signal B : INTEGER;
component c10s01b00x00p07n01i00882ent_a
generic ( G1, G2: INTEGER );
port ( A, B: out INTEGER );
end component;
signal S1: INTEGER;
signal S2: INTEGER;
BEGIN
A1: c10s01b00x00p07n01i00882ent_a generic map ( 3, 9 ) port map ( S1, S2 );
-- verification
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT( S1=4 and S2=11 )
report "***PASSED TEST: c10s01b00x00p07n01i00882"
severity NOTE;
assert ( S1=4 and S2=11 )
report "***FAILED TEST: c10s01b00x00p07n01i00882 - A declarative region is formed by the text of a component declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s01b00x00p07n01i00882arch;
configuration c10s01b00x00p07n01i00882cfg of c10s01b00x00p07n01i00882ent is
for c10s01b00x00p07n01i00882arch
for A1: c10s01b00x00p07n01i00882ent_a
use entity c10s01b00x00p07n01i00882ent_a (c10s01b00x00p07n01i00882arch_a )
generic map ( G1, G2 )
port map ( A, B );
end for;
end for;
end c10s01b00x00p07n01i00882cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc882.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c10s01b00x00p07n01i00882ent_a is
generic (
GS1: INTEGER := 3;
GS2: INTEGER := 9
);
port (
PS1: out INTEGER;
PS2: out INTEGER
);
end c10s01b00x00p07n01i00882ent_a;
architecture c10s01b00x00p07n01i00882arch_a of c10s01b00x00p07n01i00882ent_a is
begin
process
begin
PS1 <= GS1 + 1;
PS2 <= GS2 + 2;
wait; -- forever
end process;
end c10s01b00x00p07n01i00882arch_a;
use WORK.c10s01b00x00p07n01i00882ent_a;
ENTITY c10s01b00x00p07n01i00882ent IS
END c10s01b00x00p07n01i00882ent;
ARCHITECTURE c10s01b00x00p07n01i00882arch OF c10s01b00x00p07n01i00882ent IS
signal G1: INTEGER;
signal G2: INTEGER;
signal A : INTEGER;
signal B : INTEGER;
component c10s01b00x00p07n01i00882ent_a
generic ( G1, G2: INTEGER );
port ( A, B: out INTEGER );
end component;
signal S1: INTEGER;
signal S2: INTEGER;
BEGIN
A1: c10s01b00x00p07n01i00882ent_a generic map ( 3, 9 ) port map ( S1, S2 );
-- verification
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT( S1=4 and S2=11 )
report "***PASSED TEST: c10s01b00x00p07n01i00882"
severity NOTE;
assert ( S1=4 and S2=11 )
report "***FAILED TEST: c10s01b00x00p07n01i00882 - A declarative region is formed by the text of a component declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s01b00x00p07n01i00882arch;
configuration c10s01b00x00p07n01i00882cfg of c10s01b00x00p07n01i00882ent is
for c10s01b00x00p07n01i00882arch
for A1: c10s01b00x00p07n01i00882ent_a
use entity c10s01b00x00p07n01i00882ent_a (c10s01b00x00p07n01i00882arch_a )
generic map ( G1, G2 )
port map ( A, B );
end for;
end for;
end c10s01b00x00p07n01i00882cfg;
|
--------------------------------------------------------------
------------------------------------------------------------
-- FSM_core.vhd
------------------------------------------------------------
--------------------------------------------------------------
--lab3-Part1
--FSM with 0-8 state
entity FSM_core is
port(X:in bit;
CLK:in bit;
reset:in bit;
stateout:out integer range 0 to 8;
Z:out bit);
end entity FSM_core;
architecture Behavior of FSM_core is
signal State,nextState:integer range 0 to 8;
begin
stateout<=state;
process(X,State)
begin
case State is
when 0=>
Z<='0';
if X='0' then nextState<=5;
else nextState<=1;
end if;
when 1=>
Z<='0';
if X='0' then nextState<=5;
else nextState<=2;
end if;
when 2=>
Z<='0';
if X='0' then nextState<=5;
else nextState<=3;
end if;
when 3=>
Z<='0';
if X='0' then nextState<=5;
else nextState<=4;
end if;
when 4=>
Z<='1';
if X='0' then nextState<=5;
else nextState<=4;
end if;
when 5=>
Z<='0';
if X='0' then nextState<=6;
else nextState<=1;
end if;
when 6=>
Z<='0';
if X='0' then nextState<=7;
else nextState<=1;
end if;
when 7=>
Z<='0';
if X='0' then nextState<=8;
else nextState<=1;
end if;
when 8=>
Z<='1';
if X='0' then nextState<=8;
else nextState<=1;
end if;
when others=>null;
end case;
end process;
--nextStateRegister
process(CLK,reset)
begin
if reset='0' then State<=0;
elsif CLK'event and CLK='1' then
State<=nextState;
end if;
end process;
end architecture Behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- View_input.vhd
------------------------------------------------------------
--------------------------------------------------------------
entity View_input is
port (reset:in bit;
w: in bit;
clk:in bit;
z: out bit;
state8_0:out bit_vector(8 downto 0));--LED Red for showing State table
end entity View_input;
architecture match of View_input is
component FSM_core
port(
X: in bit;
CLK: in bit;
reset:in bit;
stateout:out integer range 0 to 8;
Z: out bit);
end component;
signal stateout:integer range 0 to 8;
begin
lable_1:fsm_core port map(w,clk,reset,stateout,z);
with stateout select --mux choice
state8_0 <= "000000001" when 0,
"000000010" when 1,
"000000100" when 2,
"000001000" when 3,
"000010000" when 4,
"000100000" when 5,
"001000000" when 6,
"010000000" when 7,
"100000000" when 8;
end architecture match;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc902.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p05n01i00902ent IS
type work is (foo,bar); -- No_Failure_here
END c10s03b00x00p05n01i00902ent;
ARCHITECTURE c10s03b00x00p05n01i00902arch OF c10s03b00x00p05n01i00902ent IS
BEGIN
TESTING: PROCESS
variable var : work := foo;
BEGIN
wait for 5 ns;
assert NOT( var = foo )
report "***PASSED TEST: c10s03b00x00p05n01i00902"
severity NOTE;
assert ( var = foo )
report "***FAILED TEST: c10s03b00x00p05n01i00902 - The declaration should be visible in the architecture."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p05n01i00902arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc902.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p05n01i00902ent IS
type work is (foo,bar); -- No_Failure_here
END c10s03b00x00p05n01i00902ent;
ARCHITECTURE c10s03b00x00p05n01i00902arch OF c10s03b00x00p05n01i00902ent IS
BEGIN
TESTING: PROCESS
variable var : work := foo;
BEGIN
wait for 5 ns;
assert NOT( var = foo )
report "***PASSED TEST: c10s03b00x00p05n01i00902"
severity NOTE;
assert ( var = foo )
report "***FAILED TEST: c10s03b00x00p05n01i00902 - The declaration should be visible in the architecture."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p05n01i00902arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc902.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p05n01i00902ent IS
type work is (foo,bar); -- No_Failure_here
END c10s03b00x00p05n01i00902ent;
ARCHITECTURE c10s03b00x00p05n01i00902arch OF c10s03b00x00p05n01i00902ent IS
BEGIN
TESTING: PROCESS
variable var : work := foo;
BEGIN
wait for 5 ns;
assert NOT( var = foo )
report "***PASSED TEST: c10s03b00x00p05n01i00902"
severity NOTE;
assert ( var = foo )
report "***FAILED TEST: c10s03b00x00p05n01i00902 - The declaration should be visible in the architecture."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p05n01i00902arch;
|
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`protect begin_protected
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15376)
`protect data_block
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`protect end_protected
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23.05.2016 06:48:08
-- Design Name:
-- Module Name: tb_defragment_and_check_crc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_defragment_and_check_crc is
Port ( a : in STD_LOGIC);
end tb_defragment_and_check_crc;
architecture Behavioral of tb_defragment_and_check_crc is
component defragment_and_check_crc is
Port ( clk : in STD_LOGIC;
input_data_enable : in STD_LOGIC;
input_data : in STD_LOGIC_VECTOR (7 downto 0);
input_data_present : in STD_LOGIC;
input_data_error : in STD_LOGIC;
packet_data_valid : out STD_LOGIC;
packet_data : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal count : unsigned (7 downto 0) := "00000000";
signal clk : std_logic := '0';
signal spaced_out_data_enable : std_logic := '0';
signal spaced_out_data : std_logic_vector(7 downto 0);
signal spaced_out_data_present : std_logic := '0';
signal spaced_out_data_error : std_logic := '0';
signal packet_data_valid : std_logic := '0';
signal packet_data : std_logic_vector(7 downto 0) := (others => '0');
begin
process
begin
wait for 5 ns;
clk <= not clk;
end process;
process(clk)
begin
if rising_edge(clk) then
-- if count(1 downto 0) = "000" then
spaced_out_data <= "000" & std_logic_vector(count(4 downto 0));
spaced_out_data_enable <= '1';
if count(4 downto 0) = "00000" then
spaced_out_data_enable <= '0';
spaced_out_data_present <= '0';
elsif count(4 downto 0) = "11111" then
spaced_out_data_enable <= '1';
spaced_out_data_present <= '0';
else
spaced_out_data_enable <= '1';
spaced_out_data_present <= '1';
end if;
-- else
-- spaced_out_data <= "00000000";
-- spaced_out_data_present <= '0';
-- end if;
count <= count + 1;
end if;
end process;
uut: defragment_and_check_crc port map (
clk => clk,
input_data_enable => spaced_out_data_enable,
input_data => spaced_out_data,
input_data_present => spaced_out_data_present,
input_data_error => spaced_out_data_error,
packet_data_valid => packet_data_valid,
packet_data => packet_data);
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1055.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n02i01055ent IS
END c06s04b00x00p03n02i01055ent;
ARCHITECTURE c06s04b00x00p03n02i01055arch OF c06s04b00x00p03n02i01055ent IS
BEGIN
TESTING: PROCESS
type THREE is range 1 to 3;
type A21 is array (THREE, THREE) of BOOLEAN;
variable V1 : BOOLEAN;
variable V21: A21 ;
BEGIN
V1 := V21(2); -- ONE LESS
-- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
-- INDEX POSITIONS IN TYPE DECLARATION
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n02i01055 - The expresion should be the same type as the corresponding index."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n02i01055arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1055.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n02i01055ent IS
END c06s04b00x00p03n02i01055ent;
ARCHITECTURE c06s04b00x00p03n02i01055arch OF c06s04b00x00p03n02i01055ent IS
BEGIN
TESTING: PROCESS
type THREE is range 1 to 3;
type A21 is array (THREE, THREE) of BOOLEAN;
variable V1 : BOOLEAN;
variable V21: A21 ;
BEGIN
V1 := V21(2); -- ONE LESS
-- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
-- INDEX POSITIONS IN TYPE DECLARATION
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n02i01055 - The expresion should be the same type as the corresponding index."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n02i01055arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1055.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n02i01055ent IS
END c06s04b00x00p03n02i01055ent;
ARCHITECTURE c06s04b00x00p03n02i01055arch OF c06s04b00x00p03n02i01055ent IS
BEGIN
TESTING: PROCESS
type THREE is range 1 to 3;
type A21 is array (THREE, THREE) of BOOLEAN;
variable V1 : BOOLEAN;
variable V21: A21 ;
BEGIN
V1 := V21(2); -- ONE LESS
-- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
-- INDEX POSITIONS IN TYPE DECLARATION
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n02i01055 - The expresion should be the same type as the corresponding index."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n02i01055arch;
|
process(ALUop, a, b)
begin
case ALUop is
when "000" =>
res <= a + b;
when "001" =>
res <= a - b;
when "010" =>
res <= a and b;
when "011" =>
res <= a or b;
when "100" =>
res <= not a;
when others =>
res <= (others => '0');
end case;
end process; |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:35:25 10/04/2013
-- Design Name:
-- Module Name: wishbone_mem - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity wishbone_mem is
generic( mem_size : positive := 3;
wb_size : natural := 16 ; -- Data port size for wishbone
wb_addr_size : natural := 16 -- Data port size for wishbone
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(wb_addr_size-1 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic
);
end wishbone_mem;
architecture Behavioral of wishbone_mem is
component dpram_NxN is
generic(SIZE : natural := 64 ; NBIT : natural := 8; ADDR_WIDTH : natural := 6);
port(
clk : in std_logic;
we : in std_logic;
di : in std_logic_vector(NBIT-1 downto 0 );
a : in std_logic_vector((ADDR_WIDTH - 1) downto 0 );
dpra : in std_logic_vector((ADDR_WIDTH - 1) downto 0 );
spo : out std_logic_vector(NBIT-1 downto 0 );
dpo : out std_logic_vector(NBIT-1 downto 0 )
);
end component;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
signal write_mem : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
write_mem <= wbs_strobe and wbs_write and wbs_cycle ;
ram0 : dpram_NxN
generic map(SIZE => mem_size, NBIT => wb_size, ADDR_WIDTH=> wb_addr_size)
port map(
clk => gls_clk,
we => write_mem ,
di => wbs_writedata,
a => wbs_address ,
dpra => X"0000",
spo => wbs_readdata,
dpo => open
);
end Behavioral;
|
package p is
type ft is file of natural; -- OK
type int_ptr is access integer;
type bad1 is file of int_ptr; -- Error
type bad2 is file of ft; -- Error
file f1 : ft is "foo.txt" ; -- OK
file f2 : integer is "bar.txt"; -- Error
file f3 : ft open READ_MODE is "x.txt"; -- OK
file f4 : ft open 5 is "y.txt"; -- Error
file f5 : ft; -- OK
file f6 : ft is 6; -- Error
type arr_1d is array (natural range <>) of integer;
type arr_2d is array (natural range <>, natural range <>) of integer;
subtype subarr_1d is arr_1d (1 to 2);
subtype subarr_2d is arr_2d (1 to 2, 3 to 4);
type ft2 is file of arr_1d; -- OK
type bad4 is file of arr_2d; -- Error
type ft3 is file of subarr_1d; -- OK
type bad5 is file of subarr_2d; -- Error
type t_ptr_arr is array (natural range <>) of int_ptr;
subtype sub_ptr_arr is t_ptr_arr (1 to 2);
type t_rec is record
a : integer;
b : int_ptr;
end record;
type t_rec2 is record
a : integer;
b : sub_ptr_arr;
c : real;
end record;
type bad6 is file of t_ptr_arr; -- Error
type bad7 is file of sub_ptr_arr; -- Error
type bad8 is file of t_rec; -- Error
type bad9 is file of t_rec2; -- Error
type t_ok_rec is record
a : integer;
b : time;
c : arr_1d(1 to 1);
d : arr_2d(10 to 20, 1 to 3);
end record;
type ft4 is file of t_ok_rec; -- OK
end package;
package body p is
procedure test is
variable status : file_open_status;
variable n : natural;
begin
file_open(f5, "foo.txt", WRITE_MODE); -- OK
file_open(f5, "bar.txt"); -- OK
file_open(status, f5, "x.txt"); -- OK
file_close(f1); -- OK
write(f1, 5); -- OK
read(f1, n); -- OK
read(f1, status); -- Error
assert endfile(f1); -- OK
end procedure;
end package body;
|
package p is
type ft is file of natural; -- OK
type int_ptr is access integer;
type bad1 is file of int_ptr; -- Error
type bad2 is file of ft; -- Error
file f1 : ft is "foo.txt" ; -- OK
file f2 : integer is "bar.txt"; -- Error
file f3 : ft open READ_MODE is "x.txt"; -- OK
file f4 : ft open 5 is "y.txt"; -- Error
file f5 : ft; -- OK
file f6 : ft is 6; -- Error
type arr_1d is array (natural range <>) of integer;
type arr_2d is array (natural range <>, natural range <>) of integer;
subtype subarr_1d is arr_1d (1 to 2);
subtype subarr_2d is arr_2d (1 to 2, 3 to 4);
type ft2 is file of arr_1d; -- OK
type bad4 is file of arr_2d; -- Error
type ft3 is file of subarr_1d; -- OK
type bad5 is file of subarr_2d; -- Error
type t_ptr_arr is array (natural range <>) of int_ptr;
subtype sub_ptr_arr is t_ptr_arr (1 to 2);
type t_rec is record
a : integer;
b : int_ptr;
end record;
type t_rec2 is record
a : integer;
b : sub_ptr_arr;
c : real;
end record;
type bad6 is file of t_ptr_arr; -- Error
type bad7 is file of sub_ptr_arr; -- Error
type bad8 is file of t_rec; -- Error
type bad9 is file of t_rec2; -- Error
type t_ok_rec is record
a : integer;
b : time;
c : arr_1d(1 to 1);
d : arr_2d(10 to 20, 1 to 3);
end record;
type ft4 is file of t_ok_rec; -- OK
end package;
package body p is
procedure test is
variable status : file_open_status;
variable n : natural;
begin
file_open(f5, "foo.txt", WRITE_MODE); -- OK
file_open(f5, "bar.txt"); -- OK
file_open(status, f5, "x.txt"); -- OK
file_close(f1); -- OK
write(f1, 5); -- OK
read(f1, n); -- OK
read(f1, status); -- Error
assert endfile(f1); -- OK
end procedure;
end package body;
|
package p is
type ft is file of natural; -- OK
type int_ptr is access integer;
type bad1 is file of int_ptr; -- Error
type bad2 is file of ft; -- Error
file f1 : ft is "foo.txt" ; -- OK
file f2 : integer is "bar.txt"; -- Error
file f3 : ft open READ_MODE is "x.txt"; -- OK
file f4 : ft open 5 is "y.txt"; -- Error
file f5 : ft; -- OK
file f6 : ft is 6; -- Error
type arr_1d is array (natural range <>) of integer;
type arr_2d is array (natural range <>, natural range <>) of integer;
subtype subarr_1d is arr_1d (1 to 2);
subtype subarr_2d is arr_2d (1 to 2, 3 to 4);
type ft2 is file of arr_1d; -- OK
type bad4 is file of arr_2d; -- Error
type ft3 is file of subarr_1d; -- OK
type bad5 is file of subarr_2d; -- Error
type t_ptr_arr is array (natural range <>) of int_ptr;
subtype sub_ptr_arr is t_ptr_arr (1 to 2);
type t_rec is record
a : integer;
b : int_ptr;
end record;
type t_rec2 is record
a : integer;
b : sub_ptr_arr;
c : real;
end record;
type bad6 is file of t_ptr_arr; -- Error
type bad7 is file of sub_ptr_arr; -- Error
type bad8 is file of t_rec; -- Error
type bad9 is file of t_rec2; -- Error
type t_ok_rec is record
a : integer;
b : time;
c : arr_1d(1 to 1);
d : arr_2d(10 to 20, 1 to 3);
end record;
type ft4 is file of t_ok_rec; -- OK
end package;
package body p is
procedure test is
variable status : file_open_status;
variable n : natural;
begin
file_open(f5, "foo.txt", WRITE_MODE); -- OK
file_open(f5, "bar.txt"); -- OK
file_open(status, f5, "x.txt"); -- OK
file_close(f1); -- OK
write(f1, 5); -- OK
read(f1, n); -- OK
read(f1, status); -- Error
assert endfile(f1); -- OK
end procedure;
end package body;
|
entity tb_dff02 is
end tb_dff02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff02 is
signal clk : std_logic;
signal din : std_logic;
signal dout : std_logic;
signal en : std_logic := '0';
signal rst : std_logic := '0';
begin
dut: entity work.dff02
port map (
q => dout,
d => din,
en => en,
rst => rst,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
din <= '0';
pulse;
assert dout = '1' severity failure;
en <= '1';
pulse;
assert dout = '0' severity failure;
en <= '1';
rst <= '1';
wait for 1 ns;
assert dout = '1' severity failure;
pulse;
assert dout = '1' severity failure;
rst <= '0';
pulse;
assert dout = '0' severity failure;
wait;
end process;
end behav;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:Decrementer:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_Decrementer_0_0 IS
PORT (
I : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
O : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END RAT_Decrementer_0_0;
ARCHITECTURE RAT_Decrementer_0_0_arch OF RAT_Decrementer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_Decrementer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT Decrementer IS
PORT (
I : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
O : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT Decrementer;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_Decrementer_0_0_arch: ARCHITECTURE IS "Decrementer,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_Decrementer_0_0_arch : ARCHITECTURE IS "RAT_Decrementer_0_0,Decrementer,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_Decrementer_0_0_arch: ARCHITECTURE IS "RAT_Decrementer_0_0,Decrementer,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=Decrementer,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : Decrementer
PORT MAP (
I => I,
O => O
);
END RAT_Decrementer_0_0_arch;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Test_sum32b IS
END Test_sum32b;
ARCHITECTURE behavior OF Test_sum32b IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT sum32b
PORT(
Op1 : IN std_logic_vector(31 downto 0);
Op2 : IN std_logic_vector(31 downto 0);
R : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Op1 : std_logic_vector(31 downto 0) := (others => '0');
signal Op2 : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal R : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: sum32b PORT MAP (
Op1 => Op1,
Op2 => Op2,
R => R
);
-- Clock process definitions
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Op1 <= x"00000014";
Op2 <= x"0000000A";
wait for 100 ns;
Op2 <= x"00000014";
-- insert stimulus here
wait;
end process;
END;
|
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`protect end_protected
|
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
--
-- $Id: spi_boot.vhd,v 1.11 2007-08-08 00:39:10 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger ([email protected])
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity spi_boot is
generic (
-- width of bit counter: minimum 6, maximum 12
width_bit_cnt_g : integer := 6;
-- width of image counter: minimum 0, maximum n
width_img_cnt_g : integer := 2;
-- number of bits required to address one image
num_bits_per_img_g : integer := 18;
-- SD specific initialization
sd_init_g : integer := 0;
-- clock divider to reach 400 kHz for MMC compatibility
mmc_compat_clk_div_g : integer := 0;
width_mmc_clk_div_g : integer := 0;
-- active level of reset_i
reset_level_g : integer := 0
);
port (
-- System Interface -------------------------------------------------------
clk_i : in std_logic;
reset_i : in std_logic;
set_sel_i : in std_logic_vector(31-width_img_cnt_g-num_bits_per_img_g
downto 0);
-- Card Interface ---------------------------------------------------------
spi_clk_o : out std_logic;
spi_cs_n_o : out std_logic;
spi_data_in_i : in std_logic;
spi_data_out_o : out std_logic;
spi_en_outs_o : out std_logic;
-- FPGA Configuration Interface -------------------------------------------
start_i : in std_logic;
mode_i : in std_logic;
config_n_o : out std_logic;
detached_o : out std_logic;
cfg_init_n_i : in std_logic;
cfg_done_i : in std_logic;
dat_done_i : in std_logic;
cfg_clk_o : out std_logic;
cfg_dat_o : out std_logic
);
end spi_boot;
library ieee;
use ieee.numeric_std.all;
use work.spi_boot_pack.all;
architecture rtl of spi_boot is
component spi_counter
generic (
cnt_width_g : integer := 4;
cnt_max_g : integer := 15
);
port (
clk_i : in std_logic;
reset_i : in boolean;
cnt_en_i : in boolean;
cnt_o : out std_logic_vector(cnt_width_g-1 downto 0);
cnt_ovfl_o : out boolean
);
end component;
-----------------------------------------------------------------------------
-- States of the controller FSM
--
type ctrl_states_t is (POWER_UP1, POWER_UP2,
CMD0,
CMD1,
CMD55, ACMD41,
CMD16,
WAIT_START,
WAIT_INIT_LOW, WAIT_INIT_HIGH,
CMD18, CMD18_DATA,
CMD12,
INC_IMG_CNT);
--
signal ctrl_fsm_q,
ctrl_fsm_s : ctrl_states_t;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- States of the command FSM
--
type cmd_states_t is (CMD, START, R1, PAUSE);
--
signal cmd_fsm_q,
cmd_fsm_s : cmd_states_t;
--
-----------------------------------------------------------------------------
subtype op_r is integer range 5 downto 0;
type res_bc_t is (NONE, RES_MAX, RES_47, RES_15, RES_7);
signal bit_cnt_q : unsigned(width_bit_cnt_g-1 downto 0);
signal res_bc_s : res_bc_t;
signal upper_bitcnt_zero_s : boolean;
signal cfg_dat_q : std_logic;
signal spi_clk_q : std_logic;
signal spi_clk_rising_q : boolean;
signal spi_clk_falling_q : boolean;
signal spi_dat_q,
spi_dat_s : std_logic;
signal spi_cs_n_q,
spi_cs_n_s : std_logic;
signal cfg_clk_q : std_logic;
signal start_q : std_logic;
signal img_cnt_s : std_logic_vector(width_img_cnt_g downto 0);
signal cnt_en_img_s : boolean;
signal mmc_cnt_ovfl_s : boolean;
signal mmc_compat_s : boolean;
signal cmd_finished_s : boolean;
signal r1_illcmd_q,
r1_idle_q : std_logic;
signal done_q,
send_cmd12_q : boolean;
signal en_outs_s,
en_outs_q : boolean;
signal reset_s : boolean;
signal true_s : boolean;
begin
true_s <= true;
reset_s <= true
when (reset_level_g = 1 and reset_i = '1') or
(reset_level_g = 0 and reset_i = '0') else
false;
-----------------------------------------------------------------------------
-- Process seq
--
-- Purpose:
-- Implements several sequential elements.
--
seq: process (clk_i, reset_s)
variable bit_cnt_v : unsigned(1 downto 0);
begin
if reset_s then
-- reset bit counter to 63 for power up
bit_cnt_q <= (others => '0');
bit_cnt_q(op_r) <= "111111";
spi_dat_q <= '1';
spi_cs_n_q <= '1';
cfg_dat_q <= '1';
start_q <= '0';
done_q <= false;
send_cmd12_q <= false;
ctrl_fsm_q <= POWER_UP1;
cmd_fsm_q <= CMD;
r1_illcmd_q <= '0';
r1_idle_q <= '0';
en_outs_q <= false;
elsif clk_i'event and clk_i = '1' then
-- bit counter control
if spi_clk_rising_q then
case res_bc_s is
when NONE =>
bit_cnt_q <= bit_cnt_q - 1;
when RES_MAX =>
bit_cnt_q <= (others => '1');
when RES_47 =>
bit_cnt_q <= (others => '0');
bit_cnt_q(op_r) <= "101111";
when RES_15 =>
bit_cnt_q <= (others => '0');
bit_cnt_q(op_r) <= "001111";
when RES_7 =>
bit_cnt_q <= (others => '0');
bit_cnt_q(op_r) <= "000111";
when others =>
bit_cnt_q <= (others => '0');
end case;
end if;
-- Card data output register
-- spi_clk_falling_q acts as enable during MMC clock compatibility mode.
-- As soon as this mode is left, the register must start latching.
-- There is no explicit relation to spi_clk_q anymore in normal mode.
-- Instead, spi_dat_s is operated by bit_cnt_q above which changes its
-- value after the rising edge of spi_clk_q.
-- -> spi_dat_q changes upon falling edge of spi_clk_q
if spi_clk_falling_q or not mmc_compat_s then
spi_dat_q <= spi_dat_s;
end if;
-- config data output register
-- a new value is loaded when config clock is high,
-- i.e. input data is sampled with rising spi_clk
-- while output value changes on falling edge of cfg_clk
if cfg_clk_q = '1' and spi_clk_rising_q then
cfg_dat_q <= spi_data_in_i;
end if;
-- Controller FSM state
ctrl_fsm_q <= ctrl_fsm_s;
-- Command FSM state
cmd_fsm_q <= cmd_fsm_s;
-- CS signal for SPI card
if spi_clk_q = '1' then
spi_cs_n_q <= spi_cs_n_s;
end if;
-- Extract flags from R1 response
if cmd_fsm_q = R1 then
bit_cnt_v := bit_cnt_q(1 downto 0);
case bit_cnt_v(1 downto 0) is
when "10" =>
-- save "Illegal Command" flag
r1_illcmd_q <= to_X01(spi_data_in_i);
when "00" =>
-- save "Idle State" flag
r1_idle_q <= to_X01(spi_data_in_i);
when others =>
null;
end case;
end if;
-- Start trigger register for rising edge detection
-- the reset value is '0' thus a rising edge will always be detected
-- after reset even though start_i is tied to '1'
if start_i = '0' then
start_q <= '0';
elsif ctrl_fsm_q = WAIT_START and cmd_finished_s then
start_q <= start_i;
end if;
-- Marker for cfg_done and dat_done
if ctrl_fsm_q = CMD18_DATA then
if cfg_done_i = '1' and dat_done_i = '1' then
done_q <= true;
end if;
if done_q and
(not upper_bitcnt_zero_s or cmd_fsm_q = START) then
-- activate sending of CMD12 when it is safe:
-- * upper bits of bit counter are not zero
-- -> transmission of CMD12 is not running
-- * cmd FSM is in START state
-- -> also no transmission running
send_cmd12_q <= true;
end if;
elsif ctrl_fsm_q = WAIT_START then
-- reset done_q when WAIT_START has been reached
-- this is necessary to let the stop transmission process come to
-- an end without interruption or generation of unwanted cfg_clk_q
done_q <= false;
send_cmd12_q <= false;
end if;
-- output enable
if spi_clk_rising_q then
en_outs_q <= en_outs_s;
end if;
end if;
end process seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process upper_bits
--
-- Purpose:
-- Detects that the upper bits of the bit counter are zero.
-- Upper bits = n downto 6, i.e. the optional part that is not required for
-- commands but for extension of data blocks.
--
upper_bits: process (bit_cnt_q)
variable zero_v : boolean;
begin
zero_v := true;
for i in bit_cnt_q'high downto 6 loop
if bit_cnt_q(i) = '1' then
zero_v := false;
end if;
end loop;
upper_bitcnt_zero_s <= zero_v;
end process upper_bits;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process clk_gen
--
-- Purpose:
-- Generates clocks for card and FPGA configuration.
-- The card clock is free running with a divide by two of clk_i.
-- The clock for FPGA config has an enable and is stopped on high level.
-- There is a phase shift of half a period between spi_clk and cfg_clk.
--
clk_gen: process (clk_i, reset_s)
begin
if reset_s then
spi_clk_q <= '0';
cfg_clk_q <= '1';
elsif clk_i'event and clk_i = '1' then
-- spi_clk_q rises according to the flag
-- it falls with overflow indication
-- the resulting duty cycle is not exactly 50:50,
-- high time is a bit longer
if mmc_compat_s then
-- MMC clock compatibility mode:
-- spi_clk_q rises when flagged by spi_clk_rising_q
if spi_clk_rising_q then
spi_clk_q <= '1';
elsif mmc_cnt_ovfl_s then
-- upon counter overflow spi_clk_q falls in case it does not rise
spi_clk_q <= '0';
end if;
else
-- normal mode
-- spi_clk_q follows spi_clk_rising_q
if spi_clk_rising_q then
spi_clk_q <= '1';
else
spi_clk_q <= '0';
end if;
end if;
-- clock for FPGA config must be enabled and follows spi_clk
if ctrl_fsm_q = CMD18_DATA and cmd_fsm_q = CMD and
not done_q then
cfg_clk_q <= spi_clk_q;
else
cfg_clk_q <= '1';
end if;
end if;
end process clk_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Indication flags for rising and falling spi_clk_q.
-- Essential for MMC clock compatibility mode.
-----------------------------------------------------------------------------
mmc_comap: if mmc_compat_clk_div_g > 0 generate
mmc_compat_sig: process (clk_i, reset_s)
begin
if reset_s then
spi_clk_rising_q <= false;
spi_clk_falling_q <= false;
elsif clk_i'event and clk_i = '1' then
if mmc_compat_s then
-- MMC clock compatibility mode:
-- spi_clk_rising_q is an impulse right before rising edge of spi_clk_q
-- spi_clk_falling_q is an impulse right before falling edge of spi_clk_q
if mmc_cnt_ovfl_s then
spi_clk_rising_q <= spi_clk_q = '0';
spi_clk_falling_q <= spi_clk_q = '1';
else
spi_clk_rising_q <= false;
spi_clk_falling_q <= false;
end if;
else
-- normal mode
spi_clk_rising_q <= not spi_clk_rising_q;
spi_clk_falling_q <= true;
end if;
end if;
end process mmc_compat_sig;
end generate;
no_mmc_compat: if mmc_compat_clk_div_g = 0 generate
-- SPI clock rising whenever spi_clk_q is '0'
spi_clk_rising_q <= spi_clk_q = '0';
-- SPI clock falling whenever spi_clk_q is '1'
spi_clk_falling_q <= spi_clk_q = '1';
end generate;
-----------------------------------------------------------------------------
-- Process ctrl_fsm
--
-- Purpose:
-- Implements the controller FSM.
--
ctrl_fsm: process (ctrl_fsm_q,
cmd_finished_s, r1_illcmd_q, r1_idle_q,
start_i, start_q, mode_i,
cfg_init_n_i)
variable mmc_compat_v : boolean;
begin
-- default assignments
ctrl_fsm_s <= POWER_UP1;
config_n_o <= '1';
cnt_en_img_s <= false;
spi_cs_n_s <= '0';
mmc_compat_v := false;
en_outs_s <= true;
case ctrl_fsm_q is
-- Let card finish power up, step 1 -------------------------------------
when POWER_UP1 =>
mmc_compat_v := true;
spi_cs_n_s <= '1';
if cmd_finished_s then
ctrl_fsm_s <= POWER_UP2;
else
ctrl_fsm_s <= POWER_UP1;
end if;
-- Let card finish power up, step 2 -------------------------------------
when POWER_UP2 =>
mmc_compat_v := true;
if cmd_finished_s then
ctrl_fsm_s <= CMD0;
else
spi_cs_n_s <= '1';
ctrl_fsm_s <= POWER_UP2;
end if;
-- Issue CMD0: GO_IDLE_STATE --------------------------------------------
when CMD0 =>
mmc_compat_v := true;
if cmd_finished_s then
if sd_init_g = 1 then
ctrl_fsm_s <= CMD55;
else
ctrl_fsm_s <= CMD1;
end if;
else
ctrl_fsm_s <= CMD0;
end if;
-- Issue CMD55: APP_CMD -------------------------------------------------
when CMD55 =>
if sd_init_g = 1 then
mmc_compat_v := true;
if cmd_finished_s then
if r1_illcmd_q = '0' then
-- command accepted, continue with ACMD41
ctrl_fsm_s <= ACMD41;
else
-- command rejected, it's an MMC card
ctrl_fsm_s <= CMD1;
end if;
else
ctrl_fsm_s <= CMD55;
end if;
end if;
-- Issue ACMD41: SEND_OP_COND -------------------------------------------
when ACMD41 =>
if sd_init_g = 1 then
mmc_compat_v := true;
if cmd_finished_s then
if r1_illcmd_q = '0' then
-- ok, that's an SD card
if r1_idle_q = '0' then
ctrl_fsm_s <= CMD16;
else
ctrl_fsm_s <= CMD55;
end if;
else
-- command rejected, though it accepted CMD55 -> it's an MMC
ctrl_fsm_s <= CMD1;
end if;
else
ctrl_fsm_s <= ACMD41;
end if;
end if;
-- Issue CMD1: SEND_OP_COND ---------------------------------------------
when CMD1 =>
mmc_compat_v := true;
if cmd_finished_s then
if r1_idle_q = '0' then
ctrl_fsm_s <= CMD16;
else
ctrl_fsm_s <= CMD1;
end if;
else
ctrl_fsm_s <= CMD1;
end if;
-- Issue CMD16: SET_BLOCKLEN --------------------------------------------
when CMD16 =>
if cmd_finished_s then
ctrl_fsm_s <= WAIT_START;
else
ctrl_fsm_s <= CMD16;
end if;
-- Wait for configuration start request ---------------------------------
when WAIT_START =>
spi_cs_n_s <= '1';
-- detect rising edge of start_i
if start_i = '1' and start_q = '0' then
-- decide which mode is requested
if cmd_finished_s then
if mode_i = '0' then
ctrl_fsm_s <= CMD18;
else
ctrl_fsm_s <= WAIT_INIT_LOW;
end if;
else
en_outs_s <= false;
ctrl_fsm_s <= WAIT_START;
end if;
else
en_outs_s <= false;
ctrl_fsm_s <= WAIT_START;
end if;
-- Wait for INIT to become low ------------------------------------------
when WAIT_INIT_LOW =>
spi_cs_n_s <= '1';
-- activate FPGA configuration
config_n_o <= '0';
if cfg_init_n_i = '0' then
ctrl_fsm_s <= WAIT_INIT_HIGH;
else
ctrl_fsm_s <= WAIT_INIT_LOW;
end if;
-- Wait for INIT to become high -----------------------------------------
when WAIT_INIT_HIGH =>
spi_cs_n_s <= '1';
if cfg_init_n_i = '1' and cmd_finished_s then
ctrl_fsm_s <= CMD18;
else
ctrl_fsm_s <= WAIT_INIT_HIGH;
end if;
-- Issue CMD18: READ_MULTIPLE_BLOCKS ------------------------------------
when CMD18 =>
if cmd_finished_s then
ctrl_fsm_s <= CMD18_DATA;
else
ctrl_fsm_s <= CMD18;
end if;
--
-- receive a data block
when CMD18_DATA =>
if cmd_finished_s then
ctrl_fsm_s <= CMD12;
else
ctrl_fsm_s <= CMD18_DATA;
end if;
-- Issued CMD12: STOP_TRANSMISSION -------------------------------------
when CMD12 =>
if cmd_finished_s then
ctrl_fsm_s <= INC_IMG_CNT;
else
ctrl_fsm_s <= CMD12;
end if;
-- Increment Image Counter ----------------------------------------------
when INC_IMG_CNT =>
spi_cs_n_s <= '1';
ctrl_fsm_s <= WAIT_START;
cnt_en_img_s <= true;
when others =>
null;
end case;
-- mmc_compat_s is suppressed if MMC clock compatibility is not required
if mmc_compat_clk_div_g > 0 then
mmc_compat_s <= mmc_compat_v;
else
mmc_compat_s <= false;
end if;
end process ctrl_fsm;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process cmd_fsm
--
-- Purpose:
-- Implements the command FSM.
--
cmd_fsm: process (spi_clk_rising_q,
spi_data_in_i,
bit_cnt_q,
ctrl_fsm_q,
cmd_fsm_q,
send_cmd12_q)
variable cnt_zero_v : boolean;
variable spi_data_low_v : boolean;
variable no_startbit_v : boolean;
begin
-- default assignments
cmd_finished_s <= false;
cmd_fsm_s <= CMD;
res_bc_s <= NONE;
cnt_zero_v := spi_clk_rising_q and bit_cnt_q = 0;
spi_data_low_v := spi_clk_rising_q and spi_data_in_i = '0';
-- these are no real commands thus there will be no startbit
case ctrl_fsm_q is
when POWER_UP1 | POWER_UP2 |
WAIT_START | WAIT_INIT_HIGH | WAIT_INIT_LOW =>
no_startbit_v := true;
when others =>
no_startbit_v := false;
end case;
case cmd_fsm_q is
-- Send the command -----------------------------------------------------
when CMD =>
if cnt_zero_v then
if ctrl_fsm_q /= CMD18_DATA then
-- normal commands including CMD12 require startbit of R1 response
cmd_fsm_s <= START;
else
if not send_cmd12_q then
-- CMD18_DATA needs to read CRC
cmd_fsm_s <= R1;
res_bc_s <= RES_15;
else
-- CMD18_DATA finished, scan for startbit of response
cmd_finished_s <= true;
cmd_fsm_s <= START;
end if;
end if;
else
cmd_fsm_s <= CMD;
end if;
-- Wait for startbit of response ----------------------------------------
when START =>
-- startbit detection or skip of this check
if no_startbit_v and spi_clk_rising_q then
cmd_fsm_s <= R1;
res_bc_s <= RES_7;
elsif spi_data_low_v then
if ctrl_fsm_q /= CMD18_DATA then
cmd_fsm_s <= R1;
else
-- CMD18_DATA startbit detected, read payload
cmd_fsm_s <= CMD;
res_bc_s <= RES_MAX;
end if;
else
cmd_fsm_s <= START;
res_bc_s <= RES_7;
end if;
-- Read R1 response -----------------------------------------------------
when R1 =>
if cnt_zero_v then
res_bc_s <= RES_7;
if not (ctrl_fsm_q = CMD18 or ctrl_fsm_q = CMD18_DATA) then
cmd_fsm_s <= PAUSE;
else
-- CMD18 needs another startbit detection for the data token.
-- CMD18_DATA needs a startbit after having received the CRC, either
-- * next data token
-- * R1 response of CMD12
cmd_fsm_s <= START;
if ctrl_fsm_q = CMD18 then
-- CMD18 response received -> advance to CMD18_DATA
cmd_finished_s <= true;
end if;
end if;
else
cmd_fsm_s <= R1;
end if;
-- PAUSE state -> required for Nrc, card response to host command -------
when PAUSE =>
if cnt_zero_v then
cmd_fsm_s <= CMD;
res_bc_s <= RES_47;
cmd_finished_s <= true;
else
cmd_fsm_s <= PAUSE;
end if;
when others =>
null;
end case;
end process cmd_fsm;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process transmit
--
-- Purpose:
-- Generates the serial data output values based on the current FSM state
--
-- The local variable cmd_v is 64 bits wide in contrast to an SPI command
-- with 48 bits. There are two reasons for this:
-- * During "overlaid" sending of CMD12 in FSM state CMD18_DATA, the bit
-- counter will start from 3F on its lowest 6 bits. Therefore, it is
-- necessary to provide all 64 positions in cmd_v.
-- * Reduces logic.
--
transmit: process (ctrl_fsm_q,
cmd_fsm_q,
bit_cnt_q,
img_cnt_s,
send_cmd12_q,
set_sel_i,
upper_bitcnt_zero_s)
subtype cmd_r is natural range 47 downto 0;
subtype cmd_t is std_logic_vector(cmd_r);
subtype ext_cmd_t is std_logic_vector(63 downto 0);
-- STCCCCCCAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAcccccccS
constant cmd0_c : cmd_t := "010000000000000000000000000000000000000010010101";
constant cmd1_c : cmd_t := "0100000100000000000000000000000000000000-------1";
constant cmd12_c : cmd_t := "0100110000000000000000000000000000000000-------1";
constant cmd16_c : cmd_t := "0101000000000000000000000000000000000000-------1";
constant cmd18_c : cmd_t := "0101001000000000000000000000000000000000-------1";
constant cmd55_c : cmd_t := "0111011100000000000000000000000000000000-------1";
constant acmd41_c : cmd_t := "0110100100000000000000000000000000000000-------1";
variable cmd_v : ext_cmd_t;
variable tx_v : boolean;
begin
-- default assignments
spi_dat_s <= '1';
cmd_v := (others => '1');
tx_v := false;
if cmd_fsm_q = CMD then
case ctrl_fsm_q is
when CMD0 =>
cmd_v(cmd_r) := cmd0_c;
tx_v := true;
when CMD1 =>
cmd_v(cmd_r) := cmd1_c;
tx_v := true;
when CMD16 =>
cmd_v(cmd_r) := cmd16_c;
cmd_v(8 + width_bit_cnt_g-3) := '1';
tx_v := true;
when CMD18 =>
cmd_v(cmd_r) := cmd18_c;
-- insert image counter
cmd_v(8 + num_bits_per_img_g + width_img_cnt_g
downto 8 + num_bits_per_img_g) := img_cnt_s;
-- insert set selection
cmd_v(8 + 31
downto 8 + num_bits_per_img_g + width_img_cnt_g) := set_sel_i;
tx_v := true;
when CMD18_DATA =>
cmd_v(cmd_r) := cmd12_c;
if send_cmd12_q and upper_bitcnt_zero_s then
tx_v := true;
end if;
when CMD55 =>
cmd_v(cmd_r) := cmd55_c;
tx_v := true;
when ACMD41 =>
cmd_v(cmd_r) := acmd41_c;
tx_v := true;
when others =>
null;
end case;
end if;
if tx_v then
spi_dat_s <= cmd_v(to_integer(bit_cnt_q(5 downto 0)));
end if;
end process transmit;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Optional Image Counter
-----------------------------------------------------------------------------
img_cnt: if width_img_cnt_g > 0 generate
img_cnt_b : spi_counter
generic map (
cnt_width_g => width_img_cnt_g,
cnt_max_g => 2**width_img_cnt_g - 1
)
port map (
clk_i => clk_i,
reset_i => reset_s,
cnt_en_i => cnt_en_img_s,
cnt_o => img_cnt_s(width_img_cnt_g-1 downto 0),
cnt_ovfl_o => open
);
img_cnt_s(width_img_cnt_g) <= '0';
end generate;
no_img_cnt: if width_img_cnt_g = 0 generate
img_cnt_s <= (others => '0');
end generate;
-----------------------------------------------------------------------------
-- Optional MMC compatibility counter
-----------------------------------------------------------------------------
mmc_cnt: if mmc_compat_clk_div_g > 0 generate
mmc_cnt_b : spi_counter
generic map (
cnt_width_g => width_mmc_clk_div_g,
cnt_max_g => mmc_compat_clk_div_g
)
port map (
clk_i => clk_i,
reset_i => reset_s,
cnt_en_i => true_s,
cnt_o => open,
cnt_ovfl_o => mmc_cnt_ovfl_s
);
end generate;
no_mmc_cnt: if mmc_compat_clk_div_g = 0 generate
mmc_cnt_ovfl_s <= true;
end generate;
-----------------------------------------------------------------------------
-- Output Mapping
-----------------------------------------------------------------------------
spi_clk_o <= spi_clk_q;
spi_cs_n_o <= spi_cs_n_q;
spi_data_out_o <= spi_dat_q;
spi_en_outs_o <= '1'
when en_outs_q else
'0';
cfg_clk_o <= cfg_clk_q;
cfg_dat_o <= cfg_dat_q;
detached_o <= '0'
when en_outs_q else
'1';
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.10 2007/08/06 23:31:05 arniml
-- enlarge set_sel_i input to fill all upper bits of the 32 bit address vector
--
-- Revision 1.9 2007/02/25 18:24:12 arniml
-- fix type handling of resets
--
-- Revision 1.8 2006/09/11 23:03:36 arniml
-- disable outputs with reset
--
-- Revision 1.7 2005/04/07 20:44:23 arniml
-- add new port detached_o
--
-- Revision 1.6 2005/03/09 19:48:34 arniml
-- invert level of set_sel input
--
-- Revision 1.5 2005/03/08 22:07:12 arniml
-- added set selection
--
-- Revision 1.4 2005/02/18 06:42:08 arniml
-- clarify wording for images
--
-- Revision 1.3 2005/02/16 18:59:10 arniml
-- include output enable control for SPI outputs
--
-- Revision 1.2 2005/02/13 17:25:51 arniml
-- major update to fix several problems
-- configuration/data download of multiple sets works now
--
-- Revision 1.1 2005/02/08 20:41:33 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:34:32)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY arf_nsga2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8: IN unsigned(0 TO 3);
output1, output2: OUT unsigned(0 TO 4));
END arf_nsga2_entity;
ARCHITECTURE arf_nsga2_description OF arf_nsga2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
WHEN "00000010" =>
register1 := register2 + register1;
register2 := input3 * 3;
register3 := input4 * 4;
WHEN "00000011" =>
register2 := register3 + register2;
register3 := input5 * 5;
register4 := input6 * 6;
WHEN "00000100" =>
register3 := register3 + register4;
register2 := register2 + 8;
register4 := input7 * 9;
register1 := register1 + 11;
register5 := input8 * 12;
WHEN "00000101" =>
register4 := register4 + register5;
register5 := register1 * 14;
register6 := register2 * 16;
WHEN "00000110" =>
register1 := register1 * 18;
register2 := register2 * 20;
register5 := register6 + register5;
WHEN "00000111" =>
register1 := register2 + register1;
WHEN "00001000" =>
register2 := register1 * 22;
register6 := register5 * 24;
WHEN "00001001" =>
register1 := register1 * 26;
register5 := register5 * 28;
register2 := register6 + register2;
WHEN "00001010" =>
register1 := register5 + register1;
output1 <= register3 + register2;
WHEN "00001011" =>
output2 <= register4 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END arf_nsga2_description; |
library verilog;
use verilog.vl_types.all;
entity MF_cycloneiiigl_pll is
generic(
operation_mode : string := "normal";
pll_type : string := "auto";
compensate_clock: string := "clock0";
inclk0_input_frequency: integer := 0;
inclk1_input_frequency: integer := 0;
self_reset_on_loss_lock: string := "off";
switch_over_type: string := "auto";
switch_over_counter: integer := 1;
enable_switch_over_counter: string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
test_bypass_lock_detect: string := "off";
clk0_output_frequency: integer := 0;
clk0_multiply_by: integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift: string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency: integer := 0;
clk1_multiply_by: integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift: string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency: integer := 0;
clk2_multiply_by: integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift: string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency: integer := 0;
clk3_multiply_by: integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift: string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency: integer := 0;
clk4_multiply_by: integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift: string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control: string := "auto";
vco_phase_shift_step: integer := 0;
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 1;
charge_pump_current: integer := 10;
loop_filter_r : string := "1.0";
loop_filter_c : integer := 0;
pll_compensation_delay: integer := 0;
simulation_type : string := "functional";
down_spread : string := "0.0";
lock_c : integer := 4;
sim_gate_lock_device_behavior: string := "off";
clk0_phase_shift_num: integer := 0;
clk1_phase_shift_num: integer := 0;
clk2_phase_shift_num: integer := 0;
clk3_phase_shift_num: integer := 0;
clk4_phase_shift_num: integer := 0;
family_name : string := "cycloneiiigl";
clk0_use_even_counter_mode: string := "off";
clk1_use_even_counter_mode: string := "off";
clk2_use_even_counter_mode: string := "off";
clk3_use_even_counter_mode: string := "off";
clk4_use_even_counter_mode: string := "off";
clk0_use_even_counter_value: string := "off";
clk1_use_even_counter_value: string := "off";
clk2_use_even_counter_value: string := "off";
clk3_use_even_counter_value: string := "off";
clk4_use_even_counter_value: string := "off";
init_block_reset_a_count: integer := 1;
init_block_reset_b_count: integer := 1;
phase_counter_select_width: integer := 3;
lock_window : integer := 5000;
inclk0_freq : vl_notype;
inclk1_freq : vl_notype;
charge_pump_current_bits: integer := 0;
lock_window_ui_bits: integer := 0;
loop_filter_c_bits: integer := 0;
loop_filter_r_bits: integer := 0;
test_counter_c0_delay_chain_bits: integer := 0;
test_counter_c1_delay_chain_bits: integer := 0;
test_counter_c2_delay_chain_bits: integer := 0;
test_counter_c3_delay_chain_bits: integer := 0;
test_counter_c4_delay_chain_bits: integer := 0;
test_counter_m_delay_chain_bits: integer := 0;
test_counter_n_delay_chain_bits: integer := 0;
test_feedback_comp_delay_chain_bits: integer := 0;
test_input_comp_delay_chain_bits: integer := 0;
test_volt_reg_output_mode_bits: integer := 0;
test_volt_reg_output_voltage_bits: integer := 0;
test_volt_reg_test_mode: string := "false";
vco_range_detector_high_bits: integer := -1;
vco_range_detector_low_bits: integer := -1;
scan_chain_mif_file: string := "";
auto_settings : string := "true";
SCAN_CHAIN : integer := 144;
GPP_SCAN_CHAIN : integer := 234;
FAST_SCAN_CHAIN : integer := 180;
num_phase_taps : integer := 8
);
port(
inclk : in vl_logic_vector(1 downto 0);
fbin : in vl_logic;
fbout : out vl_logic;
clkswitch : in vl_logic;
areset : in vl_logic;
pfdena : in vl_logic;
scanclk : in vl_logic;
scandata : in vl_logic;
scanclkena : in vl_logic;
configupdate : in vl_logic;
clk : out vl_logic_vector(4 downto 0);
phasecounterselect: in vl_logic_vector;
phaseupdown : in vl_logic;
phasestep : in vl_logic;
clkbad : out vl_logic_vector(1 downto 0);
activeclock : out vl_logic;
locked : out vl_logic;
scandataout : out vl_logic;
scandone : out vl_logic;
phasedone : out vl_logic;
vcooverrange : out vl_logic;
vcounderrange : out vl_logic;
fref : out vl_logic;
icdrclk : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of operation_mode : constant is 1;
attribute mti_svvh_generic_type of pll_type : constant is 1;
attribute mti_svvh_generic_type of compensate_clock : constant is 1;
attribute mti_svvh_generic_type of inclk0_input_frequency : constant is 1;
attribute mti_svvh_generic_type of inclk1_input_frequency : constant is 1;
attribute mti_svvh_generic_type of self_reset_on_loss_lock : constant is 1;
attribute mti_svvh_generic_type of switch_over_type : constant is 1;
attribute mti_svvh_generic_type of switch_over_counter : constant is 1;
attribute mti_svvh_generic_type of enable_switch_over_counter : constant is 1;
attribute mti_svvh_generic_type of bandwidth : constant is 1;
attribute mti_svvh_generic_type of bandwidth_type : constant is 1;
attribute mti_svvh_generic_type of use_dc_coupling : constant is 1;
attribute mti_svvh_generic_type of lock_high : constant is 1;
attribute mti_svvh_generic_type of lock_low : constant is 1;
attribute mti_svvh_generic_type of lock_window_ui : constant is 1;
attribute mti_svvh_generic_type of test_bypass_lock_detect : constant is 1;
attribute mti_svvh_generic_type of clk0_output_frequency : constant is 1;
attribute mti_svvh_generic_type of clk0_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk0_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk0_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk0_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of clk1_output_frequency : constant is 1;
attribute mti_svvh_generic_type of clk1_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk1_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk1_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk1_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of clk2_output_frequency : constant is 1;
attribute mti_svvh_generic_type of clk2_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk2_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk2_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk2_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of clk3_output_frequency : constant is 1;
attribute mti_svvh_generic_type of clk3_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk3_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk3_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk3_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of clk4_output_frequency : constant is 1;
attribute mti_svvh_generic_type of clk4_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk4_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk4_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk4_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of pfd_min : constant is 1;
attribute mti_svvh_generic_type of pfd_max : constant is 1;
attribute mti_svvh_generic_type of vco_min : constant is 1;
attribute mti_svvh_generic_type of vco_max : constant is 1;
attribute mti_svvh_generic_type of vco_center : constant is 1;
attribute mti_svvh_generic_type of m_initial : constant is 1;
attribute mti_svvh_generic_type of m : constant is 1;
attribute mti_svvh_generic_type of n : constant is 1;
attribute mti_svvh_generic_type of c0_high : constant is 1;
attribute mti_svvh_generic_type of c0_low : constant is 1;
attribute mti_svvh_generic_type of c0_initial : constant is 1;
attribute mti_svvh_generic_type of c0_mode : constant is 1;
attribute mti_svvh_generic_type of c0_ph : constant is 1;
attribute mti_svvh_generic_type of c1_high : constant is 1;
attribute mti_svvh_generic_type of c1_low : constant is 1;
attribute mti_svvh_generic_type of c1_initial : constant is 1;
attribute mti_svvh_generic_type of c1_mode : constant is 1;
attribute mti_svvh_generic_type of c1_ph : constant is 1;
attribute mti_svvh_generic_type of c2_high : constant is 1;
attribute mti_svvh_generic_type of c2_low : constant is 1;
attribute mti_svvh_generic_type of c2_initial : constant is 1;
attribute mti_svvh_generic_type of c2_mode : constant is 1;
attribute mti_svvh_generic_type of c2_ph : constant is 1;
attribute mti_svvh_generic_type of c3_high : constant is 1;
attribute mti_svvh_generic_type of c3_low : constant is 1;
attribute mti_svvh_generic_type of c3_initial : constant is 1;
attribute mti_svvh_generic_type of c3_mode : constant is 1;
attribute mti_svvh_generic_type of c3_ph : constant is 1;
attribute mti_svvh_generic_type of c4_high : constant is 1;
attribute mti_svvh_generic_type of c4_low : constant is 1;
attribute mti_svvh_generic_type of c4_initial : constant is 1;
attribute mti_svvh_generic_type of c4_mode : constant is 1;
attribute mti_svvh_generic_type of c4_ph : constant is 1;
attribute mti_svvh_generic_type of m_ph : constant is 1;
attribute mti_svvh_generic_type of clk0_counter : constant is 1;
attribute mti_svvh_generic_type of clk1_counter : constant is 1;
attribute mti_svvh_generic_type of clk2_counter : constant is 1;
attribute mti_svvh_generic_type of clk3_counter : constant is 1;
attribute mti_svvh_generic_type of clk4_counter : constant is 1;
attribute mti_svvh_generic_type of c1_use_casc_in : constant is 1;
attribute mti_svvh_generic_type of c2_use_casc_in : constant is 1;
attribute mti_svvh_generic_type of c3_use_casc_in : constant is 1;
attribute mti_svvh_generic_type of c4_use_casc_in : constant is 1;
attribute mti_svvh_generic_type of m_test_source : constant is 1;
attribute mti_svvh_generic_type of c0_test_source : constant is 1;
attribute mti_svvh_generic_type of c1_test_source : constant is 1;
attribute mti_svvh_generic_type of c2_test_source : constant is 1;
attribute mti_svvh_generic_type of c3_test_source : constant is 1;
attribute mti_svvh_generic_type of c4_test_source : constant is 1;
attribute mti_svvh_generic_type of vco_multiply_by : constant is 1;
attribute mti_svvh_generic_type of vco_divide_by : constant is 1;
attribute mti_svvh_generic_type of vco_post_scale : constant is 1;
attribute mti_svvh_generic_type of vco_frequency_control : constant is 1;
attribute mti_svvh_generic_type of vco_phase_shift_step : constant is 1;
attribute mti_svvh_generic_type of dpa_multiply_by : constant is 1;
attribute mti_svvh_generic_type of dpa_divide_by : constant is 1;
attribute mti_svvh_generic_type of dpa_divider : constant is 1;
attribute mti_svvh_generic_type of charge_pump_current : constant is 1;
attribute mti_svvh_generic_type of loop_filter_r : constant is 1;
attribute mti_svvh_generic_type of loop_filter_c : constant is 1;
attribute mti_svvh_generic_type of pll_compensation_delay : constant is 1;
attribute mti_svvh_generic_type of simulation_type : constant is 1;
attribute mti_svvh_generic_type of down_spread : constant is 1;
attribute mti_svvh_generic_type of lock_c : constant is 1;
attribute mti_svvh_generic_type of sim_gate_lock_device_behavior : constant is 1;
attribute mti_svvh_generic_type of clk0_phase_shift_num : constant is 1;
attribute mti_svvh_generic_type of clk1_phase_shift_num : constant is 1;
attribute mti_svvh_generic_type of clk2_phase_shift_num : constant is 1;
attribute mti_svvh_generic_type of clk3_phase_shift_num : constant is 1;
attribute mti_svvh_generic_type of clk4_phase_shift_num : constant is 1;
attribute mti_svvh_generic_type of family_name : constant is 1;
attribute mti_svvh_generic_type of clk0_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk1_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk2_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk3_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk4_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk0_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of clk1_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of clk2_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of clk3_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of clk4_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of init_block_reset_a_count : constant is 1;
attribute mti_svvh_generic_type of init_block_reset_b_count : constant is 1;
attribute mti_svvh_generic_type of phase_counter_select_width : constant is 1;
attribute mti_svvh_generic_type of lock_window : constant is 1;
attribute mti_svvh_generic_type of inclk0_freq : constant is 3;
attribute mti_svvh_generic_type of inclk1_freq : constant is 3;
attribute mti_svvh_generic_type of charge_pump_current_bits : constant is 1;
attribute mti_svvh_generic_type of lock_window_ui_bits : constant is 1;
attribute mti_svvh_generic_type of loop_filter_c_bits : constant is 1;
attribute mti_svvh_generic_type of loop_filter_r_bits : constant is 1;
attribute mti_svvh_generic_type of test_counter_c0_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_counter_c1_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_counter_c2_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_counter_c3_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_counter_c4_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_counter_m_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_counter_n_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_feedback_comp_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_input_comp_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_volt_reg_output_mode_bits : constant is 1;
attribute mti_svvh_generic_type of test_volt_reg_output_voltage_bits : constant is 1;
attribute mti_svvh_generic_type of test_volt_reg_test_mode : constant is 1;
attribute mti_svvh_generic_type of vco_range_detector_high_bits : constant is 1;
attribute mti_svvh_generic_type of vco_range_detector_low_bits : constant is 1;
attribute mti_svvh_generic_type of scan_chain_mif_file : constant is 1;
attribute mti_svvh_generic_type of auto_settings : constant is 1;
attribute mti_svvh_generic_type of SCAN_CHAIN : constant is 1;
attribute mti_svvh_generic_type of GPP_SCAN_CHAIN : constant is 1;
attribute mti_svvh_generic_type of FAST_SCAN_CHAIN : constant is 1;
attribute mti_svvh_generic_type of num_phase_taps : constant is 1;
end MF_cycloneiiigl_pll;
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`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
entity adder_ctrl is
port (
function_i : in std_logic_vector(2 downto 0);
opa_sign_i : in std_logic;
mx_opa_inv_o : out std_logic;
mx_ci_o : out std_logic_vector(1 downto 0));
end adder_ctrl;
architecture adder_ctrl_rtl of adder_ctrl is
begin -- adder_ctrl_rtl
adder_logic:process(function_i,opa_sign_i)
begin
--ADD instruction
I1: if(function_i= "000") then
mx_opa_inv_o <= '0';
mx_ci_o <= "00";
--ADDC instructionruction
elsif(function_i = "001") then
mx_opa_inv_o <= '0';
mx_ci_o <= "10";
--SUB instruction
elsif(function_i= "010") then
mx_opa_inv_o <= '1';
mx_ci_o <= "01";
--SUBC instruction
elsif(function_i = "011") then
mx_opa_inv_o <= '1';
mx_ci_o <= "10";
--CMP instruction
elsif(function_i = "101") then
mx_opa_inv_o <= '1';
mx_ci_o <= "01";
--ABS instruction
elsif(function_i= "100") then
if(opa_sign_i = '0') then
mx_opa_inv_o <= '0';
mx_ci_o <= "00";
elsif(opa_sign_i= '1') then
mx_opa_inv_o <= '1';
mx_ci_o <= "01";
end if;
--MAX instruciton
elsif(function_i= "110") then
mx_opa_inv_o <= '1';
mx_ci_o <= "01";
--MIN instruciton
elsif(function_i= "111") then
mx_opa_inv_o <= '1';
mx_ci_o <= "01";
end if I1;
end process adder_logic;
end adder_ctrl_rtl;
|
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/04/13 08:30:05
-- Nombre del módulo: clk0_0625Hz - Behavioral
-- Comentarios adicionales:
-- Implementación mediante aproximación, a caso con escala ajustada par (de 800000000 a 800000000).
-- La frecuencia fue ajustada al entero más próximo.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk0_0625Hz is
Port (
clk : in STD_LOGIC; -- Reloj de entrada de 50000000Hz.
reset : in STD_LOGIC;
clk_out : out STD_LOGIC -- Reloj de salida de 0.0625Hz.
);
end clk0_0625Hz;
architecture Behavioral of clk0_0625Hz is
signal temporal: STD_LOGIC;
signal contador: integer range 0 to 399999999 := 0;
begin
divisor_frecuencia: process (clk, reset) begin
if (reset = '1') then
temporal <= '0';
contador <= 0;
elsif rising_edge(clk) then
if (contador = 399999999) then
temporal <= NOT(temporal);
contador <= 0;
else
contador <= contador + 1;
end if;
end if;
end process;
clk_out <= temporal;
end Behavioral; |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/04/13 08:30:05
-- Nombre del módulo: clk0_0625Hz - Behavioral
-- Comentarios adicionales:
-- Implementación mediante aproximación, a caso con escala ajustada par (de 800000000 a 800000000).
-- La frecuencia fue ajustada al entero más próximo.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk0_0625Hz is
Port (
clk : in STD_LOGIC; -- Reloj de entrada de 50000000Hz.
reset : in STD_LOGIC;
clk_out : out STD_LOGIC -- Reloj de salida de 0.0625Hz.
);
end clk0_0625Hz;
architecture Behavioral of clk0_0625Hz is
signal temporal: STD_LOGIC;
signal contador: integer range 0 to 399999999 := 0;
begin
divisor_frecuencia: process (clk, reset) begin
if (reset = '1') then
temporal <= '0';
contador <= 0;
elsif rising_edge(clk) then
if (contador = 399999999) then
temporal <= NOT(temporal);
contador <= 0;
else
contador <= contador + 1;
end if;
end if;
end process;
clk_out <= temporal;
end Behavioral; |
-------------------------------------------------------------------------------
-- $Id: srl_fifo3.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo3 - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo3.vhd
--
-- Description: same as srl_fifo except the Addr port has the correct bit
-- ordering, there is a true FIFO_Empty port, and the C_DEPTH
-- generic actually controlls how many elements the fifo will
-- hold (up to 16). includes an assertion statement to check
-- that C_DEPTH is less than or equal to 16. changed
-- C_DATA_BITS to C_DWIDTH and changed it from natural to
-- positive (the width should be 1 or greater, zero width
-- didn't make sense to me!). Changed C_DEPTH from natural
-- to positive (zero elements doesn't make sense).
-- The Addr port in srl_fifo has the bits reversed which
-- made it more difficult to use. C_DEPTH was not used in
-- srl_fifo. Data_Exists is delayed by one clock so it is
-- not usefull for generating an empty flag. FIFO_Empty is
-- generated directly from the address, the same way that
-- FIFO_Full is generated.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo3.vhd
--
-------------------------------------------------------------------------------
-- Author: jam
--
-- History:
-- JAM 2002-02-02 First Version - modified from original srl_fifo
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
--
-- JAM 2002-04-12 Added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 Added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
--
-- JAM 2002-05-01 Changed FIFO_Empty output from buffer_Empty, which had
-- a clock delay, to the not of data_Exists_I, which
-- doesn't have any delay
--
-- DCW 2004-10-15 Changed unisim.all to unisim.vcomponents.
-- Added C_FAMILY generic.
-- Added C_AWIDTH generic.
--
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.all;
use proc_common_v3_00_a.family.all;
library unisim;
use unisim.vcomponents.all;
entity srl_fifo3 is
generic (
C_FAMILY : string := "virtex4"; -- latest and greatest
C_DWIDTH : positive := 8; -- changed to positive
C_AWIDTH : positive := 4; -- changed to positive
C_DEPTH : positive := 16 -- changed to positive
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to C_AWIDTH-1)
);
end entity srl_fifo3;
architecture imp of srl_fifo3 is
------------------------------------------------------------------------------
-- Architecture BEGIN
------------------------------------------------------------------------------
begin
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- GENERATE FOR C_DEPTH LESS THAN 17
------------------------------------------------------------------------------
------------------------------------------------------------------------------
C_DEPTH_LT_17 : if (C_DEPTH < 17) generate
--------------------------------------------------------------------------
-- Constant Declarations
--------------------------------------------------------------------------
-- convert C_DEPTH to a std_logic_vector so FIFO_Full can be generated
-- based on the selected depth rather than fixed at 16
constant DEPTH : std_logic_vector(0 to 3) :=
conv_std_logic_vector(C_DEPTH-1,4);
--------------------------------------------------------------------------
-- Signal Declarations
--------------------------------------------------------------------------
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
--------------------------------------------------------------------------
-- Component Declarations
--------------------------------------------------------------------------
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic
);
end component SRL16E;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic
);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic
);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic
);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDR;
--------------------------------------------------------------------------
-- Begin for Generate
--------------------------------------------------------------------------
begin
--------------------------------------------------------------------------
-- Depth check and assertion
--------------------------------------------------------------------------
-- C_DEPTH is positive so that ensures the fifo is at least 1 element deep
-- make sure it is not greater than 16 locations deep
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
--------------------------------------------------------------------------
-- Concurrent Signal Assignments
--------------------------------------------------------------------------
-- since srl16 address is 3 downto 0 need to compare individual bits
-- didn't muck with addr_i since the basic addressing works - Addr output
-- is generated correctly below
buffer_Full <= '1' when (addr_i(0) = DEPTH(3) and
addr_i(1) = DEPTH(2) and
addr_i(2) = DEPTH(1) and
addr_i(3) = DEPTH(0) ) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
--------------------------------------------------------------------------
-- Data Exists DFF Instance
--------------------------------------------------------------------------
DATA_EXISTS_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset -- [in std_logic]
);
--------------------------------------------------------------------------
-- GENERATE ADDRESS COUNTERS
--------------------------------------------------------------------------
Addr_Counters : for i in 0 to 3 generate
hsum_A(i) <= (FIFO_Read xor addr_i(i)) and
(FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(i), -- [in std_logic]
CI => addr_cy(i), -- [in std_logic]
S => hsum_A(i), -- [in std_logic]
LO => addr_cy(i+1) -- [out std_logic]
);
XORCY_I : XORCY
port map (
LI => hsum_A(i), -- [in std_logic]
CI => addr_cy(i), -- [in std_logic]
O => sum_A(i) -- [out std_logic]
);
FDRE_I : FDRE
port map (
Q => addr_i(i), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_i, -- [in std_logic]
D => sum_A(i), -- [in std_logic]
R => Reset -- [in std_logic]
);
end generate Addr_Counters;
--------------------------------------------------------------------------
-- GENERATE FIFO RAM
--------------------------------------------------------------------------
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I) -- [out std_logic]
);
end generate FIFO_RAM;
--------------------------------------------------------------------------
-- INT_ADDR_PROCESS
--------------------------------------------------------------------------
-- This process assigns the internal address to the output port
--------------------------------------------------------------------------
-- modified the process to flip the bits since the address bits from
-- the srl16 are 3 downto 0 and Addr needs to be 0 to 3
INT_ADDR_PROCESS:process (addr_i)
begin
for i in Addr'range
loop
Addr(i) <= addr_i(3 - i); -- flip the bits to account
end loop; -- for srl16 addr
end process;
end generate;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- GENERATE FOR C_DEPTH GREATER THAN 16, LESS THAN 32,
-- AND VIRTEX-E AND OLDER FAMILIES
------------------------------------------------------------------------------
------------------------------------------------------------------------------
C_DEPTH_16_32_VE : if ( ( (C_DEPTH > 16) and (C_DEPTH < 33) ) and
( equalIgnoreCase(C_FAMILY,"virtex") or
equalIgnoreCase(C_FAMILY,"virtexe") or
equalIgnoreCase(C_FAMILY,"spartan3e") or
equalIgnoreCase(C_FAMILY,"spartan3") ) )
generate
--------------------------------------------------------------------------
-- Constant Declarations
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Signal Declarations
--------------------------------------------------------------------------
signal addr_i : std_logic_vector(0 to 4);
signal addr_i_1 : std_logic_vector(3 downto 0);
signal buffer_Full_1 : std_logic;
signal next_buffer_Full_1 : std_logic;
signal next_Data_Exists_1 : std_logic;
signal data_Exists_I_1 : std_logic;
signal FIFO_Write_1 : std_logic;
signal Data_In_1 : std_logic_vector(0 to C_DWIDTH-1);
signal FIFO_Read_1 : std_logic;
signal Data_Out_1 : std_logic_vector(0 to C_DWIDTH-1);
signal addr_i_2 : std_logic_vector(3 downto 0);
signal buffer_Full_2 : std_logic;
signal next_buffer_Full_2 : std_logic;
signal next_Data_Exists_2 : std_logic;
signal data_Exists_I_2 : std_logic;
signal FIFO_Write_2 : std_logic;
signal Data_In_2 : std_logic_vector(0 to C_DWIDTH-1);
signal FIFO_Read_2 : std_logic;
signal Data_Out_2 : std_logic_vector(0 to C_DWIDTH-1);
--------------------------------------------------------------------------
-- Component Declarations
--------------------------------------------------------------------------
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic
);
end component SRL16E;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDR;
--------------------------------------------------------------------------
-- Begin for Generate
--------------------------------------------------------------------------
begin
--------------------------------------------------------------------------
-- Concurrent Signal Assignments
--------------------------------------------------------------------------
next_Data_Exists_1 <= ((FIFO_Write and not(FIFO_Read) and not(addr_i_1(0))
and not(addr_i_1(1)) and not(addr_i_1(2))
and not(addr_i_1(3))) or data_Exists_I_1) and not
(FIFO_Read and not(FIFO_Write) and not(addr_i_1(0))
and not(addr_i_1(1)) and not(addr_i_1(2))
and not(addr_i_1(3)));
FIFO_Write_1 <= FIFO_Write;
FIFO_Write_2 <= FIFO_Write;
FIFO_Read_1 <= FIFO_Read;
FIFO_Read_2 <= FIFO_Read;
data_Exists <= data_Exists_I_1;
Data_Out <= Data_Out_2 when (data_Exists_I_2 = '1') else Data_Out_1;
Data_In_2 <= Data_Out_1;
Data_In_1 <= Data_In;
FIFO_Full <= buffer_Full_2;
next_buffer_Full_1 <= '1' when (addr_i_1 = "1111") else '0';
next_Data_Exists_2 <= ((FIFO_Write and not(FIFO_Read) and not(addr_i_2(0))
and not(addr_i_2(1)) and not(addr_i_2(2)) and not
(addr_i_2(3)) and (buffer_Full_1)) or data_Exists_I_2)
and not(FIFO_Read and not(FIFO_Write) and
not(addr_i_2(0)) and not(addr_i_2(1)) and
not(addr_i_2(2)) and not(addr_i_2(3)));
next_buffer_Full_2 <= '1' when (addr_i_2 = "1111") else '0';
FIFO_Empty <= not next_Data_Exists_1 and not next_Data_Exists_2;
-- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
--------------------------------------------------------------------------
-- Address Processes
--------------------------------------------------------------------------
ADDRS_1 : process (Clk)
begin
if (clk'event and clk = '1') then
if (Reset = '1') then
addr_i_1 <= "0000";
elsif ((buffer_Full_1='0') and (FIFO_Write='1') and
(FIFO_Read='0') and (data_Exists_I_1='1')) then
addr_i_1 <= addr_i_1 + 1;
elsif (not(addr_i_1 = "0000") and (FIFO_Read='1') and
(FIFO_Write='0') and (data_Exists_I_2='0')) then
addr_i_1 <= addr_i_1 - 1;
else
null;
end if;
end if;
end process;
ADDRS_2 : process (Clk)
begin
if (clk'event and clk = '1') then
if (Reset = '1') then
addr_i_2 <= "0000";
elsif ((buffer_Full_2='0') and (FIFO_Write = '1') and
(FIFO_Read = '0') and (buffer_Full_1 = '1') and
(data_Exists_I_2='1')) then
addr_i_2 <= addr_i_2 + 1;
elsif (not(addr_i_2 = "0000") and (FIFO_Read = '1') and
(FIFO_Write = '0')) then
addr_i_2 <= addr_i_2 - 1;
else
null;
end if;
end if;
end process;
ADDR_OUT : process (addr_i_1, addr_i_2, data_Exists_I_2)
begin
if (data_Exists_I_2 = '0') then
Addr <= '0' & addr_i_1;
else
Addr <= '1' & addr_i_2;
end if;
end process;
--------------------------------------------------------------------------
-- Data Exists Instances
--------------------------------------------------------------------------
DATA_EXISTS_1_DFF : FDR
port map (
Q => data_Exists_I_1, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists_1, -- [in std_logic]
R => Reset -- [in std_logic]
);
DATA_EXISTS_2_DFF : FDR
port map (
Q => data_Exists_I_2, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists_2, -- [in std_logic]
R => Reset -- [in std_logic]
);
--------------------------------------------------------------------------
-- Buffer Full Instances
--------------------------------------------------------------------------
BUFFER_FULL_1_DFF : FDR
port map (
Q => buffer_Full_1, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_buffer_Full_1, -- [in std_logic]
R => Reset -- [in std_logic]
);
BUFFER_FULL_2_DFF : FDR
port map (
Q => buffer_Full_2, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_buffer_Full_2, -- [in std_logic]
R => Reset -- [in std_logic]
);
--------------------------------------------------------------------------
-- GENERATE FIFO RAMS
--------------------------------------------------------------------------
FIFO_RAM_1 : for i in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => FIFO_Write_1, -- [in std_logic]
D => Data_In_1(i), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i_1(0), -- [in std_logic]
A1 => addr_i_1(1), -- [in std_logic]
A2 => addr_i_1(2), -- [in std_logic]
A3 => addr_i_1(3), -- [in std_logic]
Q => Data_Out_1(i) -- [out std_logic]
);
end generate FIFO_RAM_1;
FIFO_RAM_2 : for i in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => FIFO_Write_2, -- [in std_logic]
D => Data_In_2(i), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i_2(0), -- [in std_logic]
A1 => addr_i_2(1), -- [in std_logic]
A2 => addr_i_2(2), -- [in std_logic]
A3 => addr_i_2(3), -- [in std_logic]
Q => Data_Out_2(i) -- [out std_logic]
);
end generate FIFO_RAM_2;
end generate;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- GENERATE FOR C_DEPTH GREATER THAN 16, LESS THAN 32,
-- AND VIRTEX-2 AND NEWER FAMILIES
------------------------------------------------------------------------------
------------------------------------------------------------------------------
C_DEPTH_16_32_V2 : if ( ( (C_DEPTH > 16) and (C_DEPTH < 33) ) and
( equalIgnoreCase(C_FAMILY,"virtex2") or
equalIgnoreCase(C_FAMILY,"virtex2p") or
equalIgnoreCase(C_FAMILY,"virtex4") ) )
generate
--------------------------------------------------------------------------
-- Constant Declarations
--------------------------------------------------------------------------
constant DEPTH : std_logic_vector(0 to 4) :=
conv_std_logic_vector(C_DEPTH-1,5);
--------------------------------------------------------------------------
-- Signal Declarations
--------------------------------------------------------------------------
signal addr_i : std_logic_vector(0 to 4);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 4);
signal sum_A : std_logic_vector(0 to 4);
signal addr_cy : std_logic_vector(0 to 5);
signal D_Out_ls : std_logic_vector(0 to C_DWIDTH-1);
signal D_Out_ms : std_logic_vector(0 to C_DWIDTH-1);
signal q15 : std_logic_vector(0 to C_DWIDTH-1);
--------------------------------------------------------------------------
-- Component Declarations
--------------------------------------------------------------------------
component SRL16E is
-- pragma translate_off
generic ( INIT : bit_vector := X"0000" );
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic
);
end component SRL16E;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic
);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic
);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDR;
component MUXF5
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
component SRLC16E
-- pragma translate_off
generic ( INIT : bit_vector := X"0000" );
-- pragma translate_on
port (
Q : out std_logic;
Q15 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CE : in std_logic;
CLK : in std_logic;
D : in std_logic
);
end component;
component LUT3
generic( INIT : bit_vector := X"0" );
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic
);
end component;
--------------------------------------------------------------------------
-- Begin for Generate
--------------------------------------------------------------------------
begin
--------------------------------------------------------------------------
-- Concurrent Signal Assignments
--------------------------------------------------------------------------
--buffer_Full <= '1' when (addr_i = "11111") else '0';
buffer_Full <= '1' when (addr_i(0) = DEPTH(4) and
addr_i(1) = DEPTH(3) and
addr_i(2) = DEPTH(2) and
addr_i(3) = DEPTH(1) and
addr_i(4) = DEPTH(0) ) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "00000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
Data_Exists <= data_Exists_I;
addr_cy(0) <= valid_Write;
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
--------------------------------------------------------------------------
-- Data Exists DFF Instance
--------------------------------------------------------------------------
DATA_EXISTS_DFF : FDR
port map (
Q => data_Exists_i, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset -- [in std_logic]
);
--------------------------------------------------------------------------
-- Valid Write LUT Instance
--------------------------------------------------------------------------
-- XST CR183399 WA
-- valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
VALID_WRITE_I : LUT3
generic map ( INIT => X"8A" )
port map (
O => valid_Write,
I0 => FIFO_Write,
I1 => FIFO_Read,
I2 => buffer_Full
);
--END XST WA for CR183399
--------------------------------------------------------------------------
-- GENERATE ADDRESS COUNTERS
--------------------------------------------------------------------------
ADDR_COUNTERS : for i in 0 to 4 generate
hsum_A(I) <= (FIFO_Read xor addr_i(i)) and
(FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(i), -- [in std_logic]
CI => addr_cy(i), -- [in std_logic]
S => hsum_A(i), -- [in std_logic]
LO => addr_cy(i+1) -- [out std_logic]
);
XORCY_I : XORCY
port map (
LI => hsum_A(i), -- [in std_logic]
CI => addr_cy(i), -- [in std_logic]
O => sum_A(i) -- [out std_logic]
);
FDRE_I : FDRE
port map (
Q => addr_i(i), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_i, -- [in std_logic]
D => sum_A(i), -- [in std_logic]
R => Reset -- [in std_logic]
);
end generate Addr_Counters;
--------------------------------------------------------------------------
-- GENERATE FIFO RAMS
--------------------------------------------------------------------------
FIFO_RAM : for i in 0 to C_DWIDTH-1 generate
SRLC16E_LS : SRLC16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
Q => D_Out_ls(i),
Q15 => q15(i),
A0 => addr_i(0),
A1 => addr_i(1),
A2 => addr_i(2),
A3 => addr_i(3),
CE => valid_Write,
CLK => Clk,
D => Data_In(i)
);
SRL16E_MS : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => valid_Write,
D => q15(i),
Clk => Clk,
A0 => addr_i(0),
A1 => addr_i(1),
A2 => addr_i(2),
A3 => addr_i(3),
Q => D_Out_ms(i)
);
MUXF5_I: MUXF5
port map (
O => Data_Out(i), --[out]
I0 => D_Out_ls(i), --[in]
I1 => D_Out_ms(i), --[in]
S => addr_i(4) --[in]
);
end generate FIFO_RAM;
--------------------------------------------------------------------------
-- INT_ADDR_PROCESS
--------------------------------------------------------------------------
-- This process assigns the internal address to the output port
--------------------------------------------------------------------------
INT_ADDR_PROCESS:process (addr_i)
begin -- process
for i in Addr'range
loop
Addr(i) <= addr_i(4 - i); --flip the bits to account for srl16 addr
end loop;
end process;
end generate;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- GENERATE FOR C_DEPTH GREATER THAN 32, LESS THAN 65,
-- AND VIRTEX-E AND OLDER FAMILIES
------------------------------------------------------------------------------
------------------------------------------------------------------------------
C_DEPTH_32_64_VE : if ( (C_DEPTH > 32) and (C_DEPTH < 65) and
( equalIgnoreCase(C_FAMILY,"virtex") or
equalIgnoreCase(C_FAMILY,"virtexe") or
equalIgnoreCase(C_FAMILY,"spartan3e") or
equalIgnoreCase(C_FAMILY,"spartan3") ) )
generate
--------------------------------------------------------------------------
-- Constant Declarations
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Signal Declarations
--------------------------------------------------------------------------
signal addr_i_1 : std_logic_vector(3 downto 0);
signal buffer_Full_1 : std_logic;
signal next_buffer_Full_1 : std_logic;
signal next_Data_Exists_1 : std_logic;
signal data_Exists_I_1 : std_logic;
signal FIFO_Write_1 : std_logic;
signal Data_In_1 : std_logic_vector(0 to C_DWIDTH-1);
signal FIFO_Read_1 : std_logic;
signal Data_Out_1 : std_logic_vector(0 to C_DWIDTH-1);
signal addr_i_2 : std_logic_vector(3 downto 0);
signal buffer_Full_2 : std_logic;
signal next_buffer_Full_2 : std_logic;
signal next_Data_Exists_2 : std_logic;
signal data_Exists_I_2 : std_logic;
signal FIFO_Write_2 : std_logic;
signal Data_In_2 : std_logic_vector(0 to C_DWIDTH-1);
signal FIFO_Read_2 : std_logic;
signal Data_Out_2 : std_logic_vector(0 to C_DWIDTH-1);
signal addr_i_3 : std_logic_vector(3 downto 0);
signal buffer_Full_3 : std_logic;
signal next_buffer_Full_3 : std_logic;
signal next_Data_Exists_3 : std_logic;
signal data_Exists_I_3 : std_logic;
signal FIFO_Write_3 : std_logic;
signal Data_In_3 : std_logic_vector(0 to C_DWIDTH-1);
signal FIFO_Read_3 : std_logic;
signal Data_Out_3 : std_logic_vector(0 to C_DWIDTH-1);
signal addr_i_4 : std_logic_vector(3 downto 0);
signal buffer_Full_4 : std_logic;
signal next_buffer_Full_4 : std_logic;
signal next_Data_Exists_4 : std_logic;
signal data_Exists_I_4 : std_logic;
signal FIFO_Write_4 : std_logic;
signal Data_In_4 : std_logic_vector(0 to C_DWIDTH-1);
signal FIFO_Read_4 : std_logic;
signal Data_Out_4 : std_logic_vector(0 to C_DWIDTH-1);
--------------------------------------------------------------------------
-- Component Declarations
--------------------------------------------------------------------------
component SRL16E is
-- pragma translate_off
generic ( INIT : bit_vector := X"0000" );
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic
);
end component SRL16E;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDR;
--------------------------------------------------------------------------
-- Begin for Generate
--------------------------------------------------------------------------
begin
--------------------------------------------------------------------------
-- Concurrent Signal Assignments
--------------------------------------------------------------------------
FIFO_Write_1 <= FIFO_Write;
FIFO_Read_1 <= FIFO_Read;
FIFO_Write_2 <= FIFO_Write and buffer_Full_1;
FIFO_Read_2 <= FIFO_Read;
FIFO_Write_3 <= FIFO_Write and buffer_Full_2;
FIFO_Read_3 <= FIFO_Read;
FIFO_Write_4 <= FIFO_Write and buffer_Full_3;
FIFO_Read_4 <= FIFO_Read;
Data_In_1 <= Data_In;
Data_In_2 <= Data_Out_1;
Data_In_3 <= Data_Out_2;
Data_In_4 <= Data_Out_3;
FIFO_Full <= buffer_Full_4;
next_buffer_Full_1 <= '1' when (addr_i_1 = "1111") else '0';
next_buffer_Full_2 <= '1' when (addr_i_2 = "1111") else '0';
next_buffer_Full_3 <= '1' when (addr_i_3 = "1111") else '0';
next_buffer_Full_4 <= '1' when (addr_i_4 = "1111") else '0';
next_Data_Exists_1 <= ((FIFO_Write and not(FIFO_Read) and not(addr_i_1(0))
and not(addr_i_1(1)) and not(addr_i_1(2))
and not(addr_i_1(3))) or data_Exists_I_1) and
not(FIFO_Read and not(FIFO_Write)
and not(addr_i_1(0)) and not(addr_i_1(1)) and not
(addr_i_1(2)) and not(addr_i_1(3)));
next_Data_Exists_2 <= ((FIFO_Write and not(FIFO_Read) and not(addr_i_2(0))
and not(addr_i_2(1)) and not(addr_i_2(2))
and not(addr_i_2(3)) and (buffer_Full_1)) or
data_Exists_I_2) and not(FIFO_Read and not(FIFO_Write)
and not(addr_i_2(0)) and not(addr_i_2(1)) and not
(addr_i_2(2)) and not(addr_i_2(3)));
next_Data_Exists_3 <= ((FIFO_Write and not(FIFO_Read) and not(addr_i_3(0))
and not(addr_i_3(1)) and not(addr_i_3(2)) and not
(addr_i_3(3)) and (buffer_Full_2)) or data_Exists_I_3)
and not(FIFO_Read and not(FIFO_Write) and not
(addr_i_3(0)) and not(addr_i_3(1)) and not
(addr_i_3(2)) and not(addr_i_3(3)));
next_Data_Exists_4 <= ((FIFO_Write and not(FIFO_Read) and not(addr_i_4(0))
and not(addr_i_4(1)) and not(addr_i_4(2)) and not
(addr_i_4(3)) and (buffer_Full_3)) or data_Exists_I_4)
and not(FIFO_Read and not(FIFO_Write) and
not(addr_i_4(0)) and not(addr_i_4(1)) and
not(addr_i_4(2)) and not(addr_i_4(3)));
data_Exists <= data_Exists_I_1;
Data_Out <= Data_Out_4 when (data_Exists_I_4 = '1') else
Data_Out_3 when (data_Exists_I_3 = '1') else
Data_Out_2 when (data_Exists_I_2 = '1') else
Data_Out_1;
FIFO_Empty <= not data_Exists_I_1;
--------------------------------------------------------------------------
-- Address Processes
--------------------------------------------------------------------------
ADDRS_1 : process (Clk)
begin
if (clk'event and clk = '1') then
if (Reset = '1') then
addr_i_1 <= "0000";
elsif ((buffer_Full_1='0') and (FIFO_Write='1') and
(FIFO_Read='0') and (data_Exists_I_1='1')) then
addr_i_1 <= addr_i_1 + 1;
elsif (not(addr_i_1 = "0000") and (FIFO_Read='1') and
(FIFO_Write='0') and (data_Exists_I_2='0')) then
addr_i_1 <= addr_i_1 - 1;
else
null;
end if;
end if;
end process;
ADDRS_2 : process (Clk)
begin
if (clk'event and clk = '1') then
if (Reset = '1') then
addr_i_2 <= "0000";
elsif ((buffer_Full_2='0') and (FIFO_Write = '1') and
(FIFO_Read = '0') and (buffer_Full_1 = '1') and
(data_Exists_I_2='1')) then
addr_i_2 <= addr_i_2 + 1;
elsif (not(addr_i_2 = "0000") and (FIFO_Read = '1') and
(FIFO_Write = '0') and (data_Exists_I_3='0')) then
addr_i_2 <= addr_i_2 - 1;
else
null;
end if;
end if;
end process;
ADDRS_3 : process (Clk)
begin
if (clk'event and clk = '1') then
if (Reset = '1') then
addr_i_3 <= "0000";
elsif ((buffer_Full_3='0') and (FIFO_Write = '1') and
(FIFO_Read = '0') and (buffer_Full_2 = '1') and
(data_Exists_I_3='1')) then
addr_i_3 <= addr_i_3 + 1;
elsif (not(addr_i_3 = "0000") and (FIFO_Read = '1') and
(FIFO_Write = '0') and (data_Exists_I_4='0')) then
addr_i_3 <= addr_i_3 - 1;
else
null;
end if;
end if;
end process;
ADDRS_4 : process (Clk)
begin
if (clk'event and clk = '1') then
if (Reset = '1') then
addr_i_4 <= "0000";
elsif ((buffer_Full_4='0') and (FIFO_Write = '1') and
(FIFO_Read = '0') and (buffer_Full_3 = '1') and
(data_Exists_I_4='1')) then
addr_i_4 <= addr_i_4 + 1;
elsif (not(addr_i_4 = "0000") and (FIFO_Read = '1') and
(FIFO_Write = '0')) then
addr_i_4 <= addr_i_4 - 1;
else
null;
end if;
end if;
end process;
ADDR_OUT : process (addr_i_1, addr_i_2, addr_i_3, addr_i_4,
data_Exists_I_2, data_Exists_I_3, data_Exists_I_4)
begin
if ( (data_Exists_I_2 = '0') and
(data_Exists_I_3 = '0') and
(data_Exists_I_4 = '0') )
then
Addr <= "00" & addr_i_1;
elsif ( (data_Exists_I_3 = '0') and
(data_Exists_I_4 = '0') )
then
Addr <= "01" & addr_i_2;
elsif ( (data_Exists_I_4 = '0') )
then
Addr <= "10" & addr_i_3;
else
Addr <= "11" & addr_i_4;
end if;
end process;
--------------------------------------------------------------------------
-- Data Exists Instances
--------------------------------------------------------------------------
DATA_EXISTS_1_DFF : FDR
port map (
Q => data_Exists_I_1, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists_1, -- [in std_logic]
R => Reset -- [in std_logic]
);
DATA_EXISTS_2_DFF : FDR
port map (
Q => data_Exists_I_2, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists_2, -- [in std_logic]
R => Reset -- [in std_logic]
);
DATA_EXISTS_3_DFF : FDR
port map (
Q => data_Exists_I_3, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists_3, -- [in std_logic]
R => Reset -- [in std_logic]
);
DATA_EXISTS_4_DFF : FDR
port map (
Q => data_Exists_I_4, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists_4, -- [in std_logic]
R => Reset -- [in std_logic]
);
--------------------------------------------------------------------------
-- Buffer Full Instances
--------------------------------------------------------------------------
BUFFER_FULL_1_DFF : FDR
port map (
Q => buffer_Full_1, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_buffer_Full_1, -- [in std_logic]
R => Reset -- [in std_logic]
);
BUFFER_FULL_2_DFF : FDR
port map (
Q => buffer_Full_2, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_buffer_Full_2, -- [in std_logic]
R => Reset -- [in std_logic]
);
BUFFER_FULL_3_DFF : FDR
port map (
Q => buffer_Full_3, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_buffer_Full_3, -- [in std_logic]
R => Reset -- [in std_logic]
);
BUFFER_FULL_4_DFF : FDR
port map (
Q => buffer_Full_4, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_buffer_Full_4, -- [in std_logic]
R => Reset -- [in std_logic]
);
--------------------------------------------------------------------------
-- GENERATE FIFO RAMS
--------------------------------------------------------------------------
FIFO_RAM_1 : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => FIFO_Write_1, -- [in std_logic]
D => Data_In_1(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i_1(0), -- [in std_logic]
A1 => addr_i_1(1), -- [in std_logic]
A2 => addr_i_1(2), -- [in std_logic]
A3 => addr_i_1(3), -- [in std_logic]
Q => Data_Out_1(I) -- [out std_logic]
);
end generate FIFO_RAM_1;
FIFO_RAM_2 : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => FIFO_Write_2, -- [in std_logic]
D => Data_In_2(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i_2(0), -- [in std_logic]
A1 => addr_i_2(1), -- [in std_logic]
A2 => addr_i_2(2), -- [in std_logic]
A3 => addr_i_2(3), -- [in std_logic]
Q => Data_Out_2(I) -- [out std_logic]
);
end generate FIFO_RAM_2;
FIFO_RAM_3 : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => FIFO_Write_3, -- [in std_logic]
D => Data_In_3(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i_3(0), -- [in std_logic]
A1 => addr_i_3(1), -- [in std_logic]
A2 => addr_i_3(2), -- [in std_logic]
A3 => addr_i_3(3), -- [in std_logic]
Q => Data_Out_3(I) -- [out std_logic]
);
end generate FIFO_RAM_3;
FIFO_RAM_4 : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => FIFO_Write_4, -- [in std_logic]
D => Data_In_4(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i_4(0), -- [in std_logic]
A1 => addr_i_4(1), -- [in std_logic]
A2 => addr_i_4(2), -- [in std_logic]
A3 => addr_i_4(3), -- [in std_logic]
Q => Data_Out_4(I) -- [out std_logic]
);
end generate FIFO_RAM_4;
end generate;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- GENERATE FOR C_DEPTH GREATER THAN 32, LESS THAN 65,
-- AND VIRTEX-2 AND NEWER FAMILIES
------------------------------------------------------------------------------
------------------------------------------------------------------------------
C_DEPTH_32_64_V2 : if ( (C_DEPTH > 32) and (C_DEPTH < 65) and
( equalIgnoreCase(C_FAMILY,"virtex2") or
equalIgnoreCase(C_FAMILY,"virtex2p") or
equalIgnoreCase(C_FAMILY,"virtex4") ) )
generate
--------------------------------------------------------------------------
-- Constant Declarations
--------------------------------------------------------------------------
constant DEPTH : std_logic_vector(0 to 5) :=
conv_std_logic_vector(C_DEPTH-1,6);
--------------------------------------------------------------------------
-- Signal Declarations
--------------------------------------------------------------------------
signal addr_i : std_logic_vector(0 to 5);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 5);
signal sum_A : std_logic_vector(0 to 5);
signal addr_cy : std_logic_vector(0 to 6);
signal D_Out_ls_1 : std_logic_vector(0 to C_DWIDTH-1);
signal D_Out_ls_2 : std_logic_vector(0 to C_DWIDTH-1);
signal D_Out_ls_3 : std_logic_vector(0 to C_DWIDTH-1);
signal D_Out_ms : std_logic_vector(0 to C_DWIDTH-1);
signal Data_O_ls : std_logic_vector(0 to C_DWIDTH-1);
signal Data_O_ms : std_logic_vector(0 to C_DWIDTH-1);
signal q15_1 : std_logic_vector(0 to C_DWIDTH-1);
signal q15_2 : std_logic_vector(0 to C_DWIDTH-1);
signal q15_3 : std_logic_vector(0 to C_DWIDTH-1);
--------------------------------------------------------------------------
-- Component Declarations
--------------------------------------------------------------------------
component SRL16E is
-- pragma translate_off
generic ( INIT : bit_vector := X"0000" );
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic
);
end component SRL16E;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic
);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic
);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDR;
component MUXF5
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
component MUXF6
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
component SRLC16E
-- pragma translate_off
generic ( INIT : bit_vector := X"0000" );
-- pragma translate_on
port (
Q : out std_logic;
Q15 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CE : in std_logic;
CLK : in std_logic;
D : in std_logic
);
end component;
-- XST WA for CR183399
component LUT3
generic( INIT : bit_vector := X"0" );
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic
);
end component;
--------------------------------------------------------------------------
-- Begin for Generate
--------------------------------------------------------------------------
begin
--------------------------------------------------------------------------
-- Concurrent Signal Assignments
--------------------------------------------------------------------------
-- buffer_Full <= '1' when (addr_i = "11111") else '0';
buffer_Full <= '1' when (addr_i(0) = DEPTH(5) and
addr_i(1) = DEPTH(4) and
addr_i(2) = DEPTH(3) and
addr_i(3) = DEPTH(2) and
addr_i(4) = DEPTH(1) and
addr_i(5) = DEPTH(0)
) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "000000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists <= data_Exists_I;
addr_cy(0) <= valid_Write;
--------------------------------------------------------------------------
-- Data Exists DFF Instance
--------------------------------------------------------------------------
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset -- [in std_logic]
);
--------------------------------------------------------------------------
-- Valid Write LUT Instance
--------------------------------------------------------------------------
-- XST CR183399 WA
-- valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
VALID_WRITE_I : LUT3
generic map ( INIT => X"8A" )
port map (
O => valid_Write, -- [out std_logic]
I0 => FIFO_Write, -- [in std_logic]
I1 => FIFO_Read, -- [in std_logic]
I2 => buffer_Full -- [in std_logic]
);
--END XST WA for CR183399
--------------------------------------------------------------------------
-- GENERATE ADDRESS COUNTERS
--------------------------------------------------------------------------
ADDR_COUNTERS : for i in 0 to 5 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and
(FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(i), -- [in std_logic]
CI => addr_cy(i), -- [in std_logic]
S => hsum_A(i), -- [in std_logic]
LO => addr_cy(i+1) -- [out std_logic]
);
XORCY_I : XORCY
port map (
LI => hsum_A(i), -- [in std_logic]
CI => addr_cy(i), -- [in std_logic]
O => sum_A(i) -- [out std_logic]
);
FDRE_I : FDRE
port map (
Q => addr_i(i), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_i, -- [in std_logic]
D => sum_A(i), -- [in std_logic]
R => Reset -- [in std_logic]
);
end generate ADDR_COUNTERS;
--------------------------------------------------------------------------
-- GENERATE FIFO RAMS
--------------------------------------------------------------------------
FIFO_RAM : for i in 0 to C_DWIDTH-1 generate
SRLC16E_LS1 : SRLC16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
Q => D_Out_ls_1(i), --[out]
Q15 => q15_1(i), --[out]
A0 => addr_i(0), --[in]
A1 => addr_i(1), --[in]
A2 => addr_i(2), --[in]
A3 => addr_i(3), --[in]
CE => valid_Write, --[in]
CLK => Clk, --[in]
D => Data_In(i) --[in]
);
SRLC16E_LS2 : SRLC16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
Q => D_Out_ls_2(i), --[out]
Q15 => q15_2(i), --[out]
A0 => addr_i(0), --[in]
A1 => addr_i(1), --[in]
A2 => addr_i(2), --[in]
A3 => addr_i(3), --[in]
CE => valid_Write, --[in]
CLK => Clk, --[in]
D => q15_1(i) --[in]
);
MUXF5_LS: MUXF5
port map (
O => Data_O_LS(i), --[out]
I0 => D_Out_ls_1(I), --[in]
I1 => D_Out_ls_2(I), --[in]
S => addr_i(4) --[in]
);
SRLC16E_LS3 : SRLC16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
Q => D_Out_ls_3(i), --[out]
Q15 => q15_3(i), --[out]
A0 => addr_i(0), --[in]
A1 => addr_i(1), --[in]
A2 => addr_i(2), --[in]
A3 => addr_i(3), --[in]
CE => valid_Write, --[in]
CLK => Clk, --[in]
D => q15_2(i) --[in]
);
SRL16E_MS : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => valid_Write, --[in]
D => q15_3(i), --[in]
Clk => Clk, --[in]
A0 => addr_i(0), --[in]
A1 => addr_i(1), --[in]
A2 => addr_i(2), --[in]
A3 => addr_i(3), --[in]
Q => D_Out_ms(I) --[out]
);
MUXF5_MS: MUXF5
port map (
O => Data_O_MS(i), --[out]
I0 => D_Out_ls_3(i), --[in]
I1 => D_Out_ms(i), --[in]
S => addr_i(4) --[in]
);
MUXF6_I: MUXF6
port map (
O => Data_out(i), --[out]
I0 => Data_O_ls(i), --[in]
I1 => Data_O_ms(i), --[in]
S => addr_i(5) --[in]
);
end generate FIFO_RAM;
--------------------------------------------------------------------------
-- INT_ADDR_PROCESS
--------------------------------------------------------------------------
-- This process assigns the internal address to the output port
--------------------------------------------------------------------------
INT_ADDR_PROCESS:process (addr_i)
begin
for i in Addr'range
loop
Addr(i) <= addr_i(5 - i); -- flip the bits to account for srl16 addr
end loop;
end process;
end generate;
end architecture imp;
|
architecture RTL of FIFO is
attribute max_delay : time;
attribute max_delay : time;
-- Violations below
attribute max_delay: time;
begin
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
a : inout std_logic;
enable : in std_logic;
d_in : in std_logic;
d_out : out std_logic
);
end;
architecture a of ent is
begin
process(all)
begin
if enable then
a <= d_in;
else
a <= 'Z';
end if;
end process;
d_out <= a;
end;
|
entity tb_func05 is
end tb_func05;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_func05 is
signal r : std_logic_vector(15 downto 0);
signal s : natural;
begin
dut: entity work.func05
port map (s, r);
process
begin
s <= 2;
wait for 1 ns;
assert r = x"1234" severity failure;
s <= 3;
wait for 1 ns;
assert r = x"0000" severity failure;
wait;
end process;
end behav;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY NANDGATE IS
PORT (A,B:IN STD_LOGIC;
C:OUT STD_LOGIC);
END NANDGATE;
ARCHITECTURE NANDG OF NANDGATE IS
BEGIN
C <= A NAND B;
END NANDG;
|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_model_constr_decoder |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_model_constr_decoder.vhd |
-- |
-- Description Generation of the nanoFIP output S_ID and decoding of the inputs C_ID and M_ID. |
-- The output S_ID0 is a clock with period the double of uclk's period and the S_ID1 |
-- is the opposite clock (it is '0' when S_ID0 is '1' and '1' when S_ID0 is '0'). |
-- Each one of the 4 pins of the M_ID and C_ID can be connected to either Vcc, Gnd, |
-- S_ID1 or S_ID0. Like this (after 2 uclk periods) the 8 bits of the Model and |
-- Constructor words take a value, according to the table: Gnd 00 |
-- S_ID0 01 |
-- S_ID1 10 |
-- Vcc 11 |
-- |
-- Authors Pablo Alvarez Sanchez ([email protected]) |
-- Evangelia Gousiou ([email protected]) |
-- Date 21/01/2011 |
-- Version v0.03 |
-- Depends on wf_reset_unit |
---------------- |
-- Last changes |
-- 11/09/2009 v0.01 PAS First version |
-- 20/08/2010 v0.02 EG S_ID corrected so that S_ID0 is always the opposite of S_ID1 |
-- "for" loop replaced with signals concatenation; |
-- Counter is of c_RELOAD_MID_CID bits; Code cleaned-up |
-- 06/10/2010 v0.03 EG generic c_RELOAD_MID_CID removed; |
-- counter unit instantiated |
-- 01/2011 v0.031 EG loading aftern the 2nd cycle (no need for 3) |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_model_constr_decoder
--=================================================================================================
entity wf_model_constr_decoder is port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 Mhz clock
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- nanoFIP WorldFIP Settings (synchronised with uclk_i)
constr_id_i : in std_logic_vector (3 downto 0); -- Constructor identification settings
model_id_i : in std_logic_vector (3 downto 0); -- Model identification settings
-- OUTPUTS
-- nanoFIP WorldFIP Settings output
-- MODIFIED
-- s_id_o : out std_logic_vector (1 downto 0); -- Identification selection
-- Signal to the wf_prod_bytes_retriever unit
constr_id_dec_o : out std_logic_vector (7 downto 0); -- Constructor identification decoded
model_id_dec_o : out std_logic_vector (7 downto 0));-- Model identification decoded
end entity wf_model_constr_decoder;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_model_constr_decoder is
signal s_counter : unsigned (1 downto 0);
signal s_model_stage2, s_model_stage1 : std_logic_vector (3 downto 0);
signal s_constr_stage2, s_constr_stage1 : std_logic_vector (3 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Synchronous process Model_Constructor_Decoder:
-- For M_ID and C_ID to be loaded, 2 uclk periods are needed: on the first uclk tick, the values
-- of all the odd bits of M_ID & C_ID are loaded on the registers s_model_stage1/ s_constr_stage1
-- and on the second uclk tick, the values of the odd bits move to the registers s_model_stage2/
-- s_constr_stage2, giving place to all the even bits to be loaded to the s_model_stage1/
-- s_constr_stage1. The loaded odd and even values are combined after the 2 periods to give the
-- decoded outputs model_id_dec_o & constr_id_dec_o.
Model_Constructor_Decoder: process (uclk_i)
begin
if rising_edge (uclk_i) then -- initializations
if nfip_rst_i = '1' then
model_id_dec_o <= (others => '0');
constr_id_dec_o <= (others => '0');
s_model_stage1 <= (others => '0');
s_model_stage2 <= (others => '0');
s_constr_stage1 <= (others => '0');
s_constr_stage2 <= (others => '0');
else
s_model_stage2 <= s_model_stage1; -- after 2 uclk ticks stage1 keeps the even bits
s_model_stage1 <= model_id_i; -- and stage2 the odd ones
s_constr_stage2 <= s_constr_stage1;
s_constr_stage1 <= constr_id_i; -- same for the constructor
if s_counter = "10" then
model_id_dec_o <= s_model_stage2(3) & s_model_stage1(3) & -- putting together
s_model_stage2(2) & s_model_stage1(2) & -- even and odd bits
s_model_stage2(1) & s_model_stage1(1) &
s_model_stage2(0) & s_model_stage1(0);
constr_id_dec_o <= s_constr_stage2(3) & s_constr_stage1(3) &
s_constr_stage2(2) & s_constr_stage1(2) &
s_constr_stage2(1) & s_constr_stage1(1) &
s_constr_stage2(0) & s_constr_stage1(0);
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Instantiation of a counter wf_incr_counter
Free_Counter: wf_incr_counter
generic map(g_counter_lgth => 2)
port map(
uclk_i => uclk_i,
counter_reinit_i => nfip_rst_i,
counter_incr_i => '1',
counter_is_full_o => open,
-----------------------------------------
counter_o => s_counter);
-----------------------------------------
---------------------------------------------------------------------------------------------------
-- Concurrent signal assignment for the output s_id_o
-- MODIFIED
-- s_id_o <= ((not s_counter(0)) & s_counter(0)); -- 2 opposite clocks generated using
-- the LSB of the counter
-- uclk_i: |-|__|-|__|-|__|-|__|-|__|-|_
-- S_ID0 : |----|____|----|____|----|___
-- S_ID1 : |____|----|____|----|____|---
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity planet_jed is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(18 downto 0)
);
end planet_jed;
architecture behaviour of planet_jed is
constant st0: std_logic_vector(5 downto 0) := "000010";
constant st1: std_logic_vector(5 downto 0) := "110101";
constant st2: std_logic_vector(5 downto 0) := "011101";
constant st3: std_logic_vector(5 downto 0) := "000011";
constant st4: std_logic_vector(5 downto 0) := "010101";
constant st42: std_logic_vector(5 downto 0) := "010100";
constant st5: std_logic_vector(5 downto 0) := "111010";
constant st6: std_logic_vector(5 downto 0) := "010011";
constant st7: std_logic_vector(5 downto 0) := "001111";
constant st41: std_logic_vector(5 downto 0) := "001101";
constant st38: std_logic_vector(5 downto 0) := "011111";
constant st8: std_logic_vector(5 downto 0) := "011100";
constant st10: std_logic_vector(5 downto 0) := "110100";
constant st9: std_logic_vector(5 downto 0) := "110110";
constant st11: std_logic_vector(5 downto 0) := "010110";
constant st12: std_logic_vector(5 downto 0) := "011010";
constant st13: std_logic_vector(5 downto 0) := "110011";
constant st14: std_logic_vector(5 downto 0) := "111111";
constant st15: std_logic_vector(5 downto 0) := "010111";
constant st16: std_logic_vector(5 downto 0) := "111110";
constant st17: std_logic_vector(5 downto 0) := "011000";
constant st18: std_logic_vector(5 downto 0) := "101111";
constant st19: std_logic_vector(5 downto 0) := "000111";
constant st46: std_logic_vector(5 downto 0) := "100101";
constant st24: std_logic_vector(5 downto 0) := "100111";
constant st20: std_logic_vector(5 downto 0) := "000001";
constant st25: std_logic_vector(5 downto 0) := "000000";
constant st21: std_logic_vector(5 downto 0) := "000101";
constant st22: std_logic_vector(5 downto 0) := "000100";
constant st23: std_logic_vector(5 downto 0) := "000110";
constant st26: std_logic_vector(5 downto 0) := "001011";
constant st28: std_logic_vector(5 downto 0) := "100011";
constant st30: std_logic_vector(5 downto 0) := "101011";
constant st27: std_logic_vector(5 downto 0) := "010000";
constant st29: std_logic_vector(5 downto 0) := "110010";
constant st31: std_logic_vector(5 downto 0) := "101101";
constant st32: std_logic_vector(5 downto 0) := "011011";
constant st33: std_logic_vector(5 downto 0) := "001100";
constant st35: std_logic_vector(5 downto 0) := "011110";
constant st34: std_logic_vector(5 downto 0) := "001001";
constant st36: std_logic_vector(5 downto 0) := "101000";
constant st37: std_logic_vector(5 downto 0) := "010010";
constant st39: std_logic_vector(5 downto 0) := "010001";
constant st40: std_logic_vector(5 downto 0) := "110001";
constant st43: std_logic_vector(5 downto 0) := "110000";
constant st44: std_logic_vector(5 downto 0) := "011001";
constant st45: std_logic_vector(5 downto 0) := "101010";
constant st47: std_logic_vector(5 downto 0) := "001000";
signal current_state, next_state: std_logic_vector(5 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------"; output <= "-------------------";
case current_state is
when st0 =>
if std_match(input, "-------") then next_state <= st1; output <= "001011101000000---0";
end if;
when st1 =>
if std_match(input, "----01-") then next_state <= st1; output <= "--------0000000---0";
elsif std_match(input, "----10-") then next_state <= st1; output <= "--------0100000---1";
elsif std_match(input, "----00-") then next_state <= st1; output <= "1000----1000000---1";
elsif std_match(input, "----11-") then next_state <= st2; output <= "1000111110011001000";
end if;
when st2 =>
if std_match(input, "------0") then next_state <= st3; output <= "1010010010000000000";
elsif std_match(input, "---0---") then next_state <= st3; output <= "1010010010000000000";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "1010----1010010---1";
end if;
when st3 =>
if std_match(input, "11-----") then next_state <= st4; output <= "001111101000000-010";
elsif std_match(input, "10-----") then next_state <= st4; output <= "0011111110000000-10";
elsif std_match(input, "0-0-01-") then next_state <= st4; output <= "--------000010000-0";
elsif std_match(input, "0-0-10-") then next_state <= st4; output <= "--------010010000-1";
elsif std_match(input, "0-0-11-") then next_state <= st42; output <= "011011011000100---0";
elsif std_match(input, "0-0-00-") then next_state <= st4; output <= "0110----100000000-1";
elsif std_match(input, "0-1-01-") then next_state <= st4; output <= "--------00011000000";
elsif std_match(input, "0-1-10-") then next_state <= st4; output <= "--------01011000001";
elsif std_match(input, "0-1-11-") then next_state <= st42; output <= "011011011001100--00";
elsif std_match(input, "0-1-00-") then next_state <= st4; output <= "0110----10010000001";
end if;
when st4 =>
if std_match(input, "-------") then next_state <= st5; output <= "1010010010000000000";
end if;
when st5 =>
if std_match(input, "--0----") then next_state <= st6; output <= "1000011110000000001";
elsif std_match(input, "--1----") then next_state <= st6; output <= "1000011110010000001";
end if;
when st6 =>
if std_match(input, "-1----0") then next_state <= st7; output <= "101001001000000-000";
elsif std_match(input, "-110--1") then next_state <= st7; output <= "101001001000000-000";
elsif std_match(input, "-10---1") then next_state <= st41; output <= "101001001000000--00";
elsif std_match(input, "-111--1") then next_state <= st38; output <= "101001001000000--00";
elsif std_match(input, "-0-----") then next_state <= st7; output <= "1010010010000000-00";
end if;
when st7 =>
if std_match(input, "--1----") then next_state <= st8; output <= "0001101010010000000";
elsif std_match(input, "--0----") then next_state <= st8; output <= "0001101010000000000";
end if;
when st8 =>
if std_match(input, "--0----") then next_state <= st10; output <= "1010010010000000000";
elsif std_match(input, "--1----") then next_state <= st9; output <= "1010010010000000000";
end if;
when st9 =>
if std_match(input, "-11----") then next_state <= st11; output <= "001011101001000-000";
elsif std_match(input, "-01----") then next_state <= st11; output <= "0010111110010000-00";
elsif std_match(input, "-10----") then next_state <= st11; output <= "001011101000000-000";
elsif std_match(input, "-00----") then next_state <= st11; output <= "0010111110000000-00";
end if;
when st10 =>
if std_match(input, "--1----") then next_state <= st12; output <= "0010----10010000001";
elsif std_match(input, "--0----") then next_state <= st12; output <= "0010----10000000001";
end if;
when st11 =>
if std_match(input, "-------") then next_state <= st13; output <= "1010010010000000000";
end if;
when st12 =>
if std_match(input, "-------") then next_state <= st14; output <= "1010010010000000000";
end if;
when st13 =>
if std_match(input, "-11----") then next_state <= st15; output <= "010110011001000-000";
elsif std_match(input, "-10----") then next_state <= st15; output <= "010110011000000-000";
elsif std_match(input, "-01----") then next_state <= st15; output <= "0101100010010000-00";
elsif std_match(input, "-00----") then next_state <= st15; output <= "0101100010000000-00";
end if;
when st14 =>
if std_match(input, "--1----") then next_state <= st15; output <= "0101----10010000001";
elsif std_match(input, "--0----") then next_state <= st15; output <= "0101----10000000001";
end if;
when st15 =>
if std_match(input, "-------") then next_state <= st16; output <= "1010010010000000000";
end if;
when st16 =>
if std_match(input, "--1----") then next_state <= st17; output <= "0110010110010000001";
elsif std_match(input, "--0----") then next_state <= st17; output <= "0110010110000000001";
end if;
when st17 =>
if std_match(input, "---0---") then next_state <= st18; output <= "1010010010000000000";
elsif std_match(input, "01-1---") then next_state <= st19; output <= "101001001000001-0-0";
elsif std_match(input, "00-1--0") then next_state <= st19; output <= "1010010010000010--0";
elsif std_match(input, "00-1--1") then next_state <= st46; output <= "101001001000000---0";
elsif std_match(input, "11-1---") then next_state <= st24; output <= "101001001000001-000";
elsif std_match(input, "10-1--0") then next_state <= st24; output <= "1010010010000010-00";
elsif std_match(input, "10-1--1") then next_state <= st18; output <= "1010010010000000-00";
end if;
when st18 =>
if std_match(input, "--1----") then next_state <= st2; output <= "1000111110010000000";
elsif std_match(input, "0-0----") then next_state <= st2; output <= "1000----10000000001";
elsif std_match(input, "1-0----") then next_state <= st2; output <= "1000111110000000000";
end if;
when st19 =>
if std_match(input, "-10----") then next_state <= st20; output <= "100101001000000-0-0";
elsif std_match(input, "-00----") then next_state <= st20; output <= "1001010110000000--0";
elsif std_match(input, "--1----") then next_state <= st25; output <= "100011111001000--00";
end if;
when st20 =>
if std_match(input, "-10----") then next_state <= st19; output <= "101001001000000-0-0";
elsif std_match(input, "-11----") then next_state <= st21; output <= "101001001000000-0-0";
elsif std_match(input, "-01----") then next_state <= st19; output <= "1010010010000000--0";
elsif std_match(input, "-00----") then next_state <= st21; output <= "1010010010000000--0";
end if;
when st21 =>
if std_match(input, "-10----") then next_state <= st22; output <= "001111111000000-0-0";
elsif std_match(input, "-11----") then next_state <= st23; output <= "001111111001000--00";
elsif std_match(input, "-00----") then next_state <= st22; output <= "0011111010000000--0";
elsif std_match(input, "-01----") then next_state <= st23; output <= "001111101001000--00";
end if;
when st22 =>
if std_match(input, "-------") then next_state <= st19; output <= "10100100100000000-0";
end if;
when st23 =>
if std_match(input, "-------") then next_state <= st24; output <= "101001001000000--00";
end if;
when st24 =>
if std_match(input, "-------") then next_state <= st25; output <= "100011111000000--00";
end if;
when st25 =>
if std_match(input, "---0--0") then next_state <= st26; output <= "101001001000000---0";
elsif std_match(input, "---1--0") then next_state <= st28; output <= "101001001000010--00";
elsif std_match(input, "------1") then next_state <= st30; output <= "101001001000000--10";
end if;
when st26 =>
if std_match(input, "--0-01-") then next_state <= st27; output <= "--------0000100---0";
elsif std_match(input, "--0-10-") then next_state <= st27; output <= "--------0100100---1";
elsif std_match(input, "--0-00-") then next_state <= st27; output <= "0110----1000000---1";
elsif std_match(input, "--0-11-") then next_state <= st42; output <= "011011011000100---0";
elsif std_match(input, "--1----") then next_state <= st25; output <= "100011111001000--00";
end if;
when st27 =>
if std_match(input, "-------") then next_state <= st26; output <= "101001001000000---0";
end if;
when st28 =>
if std_match(input, "-------") then next_state <= st29; output <= "011001011000000--01";
end if;
when st29 =>
if std_match(input, "---1---") then next_state <= st26; output <= "101001001000000---0";
elsif std_match(input, "--10---") then next_state <= st3; output <= "1010010010000001000";
elsif std_match(input, "--00---") then next_state <= st3; output <= "1010010010000000100";
end if;
when st30 =>
if std_match(input, "-------") then next_state <= st31; output <= "100001111000000---1";
end if;
when st31 =>
if std_match(input, "---0---") then next_state <= st26; output <= "101001001000000---0";
elsif std_match(input, "---1---") then next_state <= st32; output <= "101001001000000---0";
end if;
when st32 =>
if std_match(input, "--0----") then next_state <= st33; output <= "100101011000000---0";
elsif std_match(input, "--1----") then next_state <= st35; output <= "011011011001000--00";
end if;
when st33 =>
if std_match(input, "--10---") then next_state <= st32; output <= "101001001000000---0";
elsif std_match(input, "--0----") then next_state <= st34; output <= "101001001000000---0";
elsif std_match(input, "---1---") then next_state <= st34; output <= "101001001000000---0";
end if;
when st34 =>
if std_match(input, "--1----") then next_state <= st35; output <= "011011011001000--00";
elsif std_match(input, "--0----") then next_state <= st35; output <= "011011011000000---0";
end if;
when st35 =>
if std_match(input, "-------") then next_state <= st36; output <= "101001001000000--00";
end if;
when st36 =>
if std_match(input, "--0----") then next_state <= st37; output <= "011011101000000--00";
elsif std_match(input, "--1----") then next_state <= st37; output <= "011011101001000--00";
end if;
when st37 =>
if std_match(input, "-------") then next_state <= st9; output <= "1010010010000000100";
end if;
when st38 =>
if std_match(input, "--0-01-") then next_state <= st39; output <= "--------0000100---0";
elsif std_match(input, "--0-10-") then next_state <= st39; output <= "--------0100100---1";
elsif std_match(input, "--0-11-") then next_state <= st42; output <= "011011011000100---0";
elsif std_match(input, "--0-00-") then next_state <= st39; output <= "0110----1000000---1";
elsif std_match(input, "--1----") then next_state <= st40; output <= "100011111001000--00";
end if;
when st39 =>
if std_match(input, "-------") then next_state <= st38; output <= "101001001000000---0";
end if;
when st40 =>
if std_match(input, "-------") then next_state <= st41; output <= "101001001000000--10";
end if;
when st41 =>
if std_match(input, "-------") then next_state <= st42; output <= "011011011000000---0";
end if;
when st42 =>
if std_match(input, "-------") then next_state <= st43; output <= "101001001000000--00";
end if;
when st43 =>
if std_match(input, "--0----") then next_state <= st44; output <= "011011101000000--00";
elsif std_match(input, "--1----") then next_state <= st44; output <= "011011101001000--00";
end if;
when st44 =>
if std_match(input, "-------") then next_state <= st45; output <= "101001001000000--00";
end if;
when st45 =>
if std_match(input, "--0----") then next_state <= st6; output <= "0111001110000000100";
elsif std_match(input, "--1----") then next_state <= st6; output <= "0111001110010000100";
end if;
when st46 =>
if std_match(input, "--0----") then next_state <= st47; output <= "1000----1000000---1";
elsif std_match(input, "--1----") then next_state <= st0; output <= "100011111011010---0";
end if;
when st47 =>
if std_match(input, "-------") then next_state <= st46; output <= "101001001000000---0";
end if;
when others => next_state <= "------"; output <= "-------------------";
end case;
end process;
end behaviour;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: lvds_combo.vhd
-- File: lvds_combo.vhd.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Differential input/output pads with IREF/OREF logic wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allpads.all;
entity lvds_combo is
generic (tech : integer := 0; voltage : integer := 0; width : integer := 1;
oepol : integer := 0; term : integer := 0);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
lvdsref : in std_logic := '1'
);
end ;
architecture rtl of lvds_combo is
signal gnd : std_ulogic;
signal oen : std_logic_vector(0 to width-1);
constant level : integer := lvds;
begin
gnd <= '0';
gen0 : if has_ds_combo(tech) = 0 generate
swloop : for i in 0 to width-1 generate
od0 : outpad_ds generic map (tech, level, voltage, oepol) port map (odpadp(i), odpadn(i), odval(i), en(i));
os0 : outpad_ds generic map (tech, level, voltage, oepol) port map (ospadp(i), ospadn(i), osval(i), en(i));
id0 : inpad_ds generic map (tech, level, voltage) port map (idpadp(i), idpadn(i), idval(i));
is0 : inpad_ds generic map (tech, level, voltage) port map (ispadp(i), ispadn(i), isval(i));
end generate;
end generate;
combo : if has_ds_combo(tech) /= 0 generate
oen <= not en when oepol /= padoen_polarity(tech) else en;
ut025 : if tech = ut25 generate
u0: ut025crh_lvds_combo generic map (voltage, width)
port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen,
idpadp, idpadn, ispadp, ispadn, idval, isval);
end generate;
ut13 : if tech = ut130 generate
u0: ut130hbd_lvds_combo generic map (voltage, width)
port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen,
idpadp, idpadn, ispadp, ispadn, idval, isval);
end generate;
um : if tech = umc generate
u0: umc_lvds_combo generic map (voltage, width)
port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen,
idpadp, idpadn, ispadp, ispadn, idval, isval, lvdsref);
end generate;
rhu : if tech = rhumc generate
u0: rhumc_lvds_combo generic map (voltage, width)
port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen,
idpadp, idpadn, ispadp, ispadn, idval, isval, lvdsref);
end generate;
end generate;
end;
|
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 12.12.2013 10:41:20
-- Design Name:
-- Module Name: switch_output_port_fifo - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description:
-- FIFO interface between switch port on the transmit path and MAC
-- for decoupling clocks and data widths
-- bandwidth on user interface (read) must be higher than mac interface (write)
-- width = error_width + last_width + data_width
-- depth = 32 entries
--
-- see switch_mac_txfifo.svg for further information
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity switch_output_port_fifo is
generic (
GMII_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer
);
port (
-- User-side interface (write)
tx_fifo_in_clk : in std_logic;
tx_fifo_in_reset : in std_logic;
tx_fifo_in_data : in std_logic_vector(TRANSMITTER_DATA_WIDTH-1 downto 0);
tx_fifo_in_valid : in std_logic;
tx_fifo_in_last : in std_logic;
tx_fifo_in_ready : out std_logic;
-- MAC-side interface (read)
tx_fifo_out_clk : in std_logic;
tx_fifo_out_reset : in std_logic;
tx_fifo_out_data : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
tx_fifo_out_valid : out std_logic;
tx_fifo_out_last : out std_logic;
tx_fifo_out_ready : in std_logic;
tx_fifo_out_error : out std_logic
);
end switch_output_port_fifo;
architecture rtl of switch_output_port_fifo is
component fifo_generator_3 is
PORT (
wr_clk : IN std_logic := '0';
rd_clk : IN std_logic := '0';
wr_rst : IN std_logic := '0';
rd_rst : IN std_logic := '0';
wr_en : IN std_logic := '0';
rd_en : IN std_logic := '0';
din : IN std_logic_vector(TRANSMITTER_DATA_WIDTH+2-1 DOWNTO 0) := (OTHERS => '0');
dout : OUT std_logic_vector(GMII_DATA_WIDTH+2-1 DOWNTO 0) := (OTHERS => '0');
full : OUT std_logic := '0';
empty : OUT std_logic := '1'
);
end component;
signal dout_sig : std_logic_vector(GMII_DATA_WIDTH+2-1 DOWNTO 0) := (OTHERS => '0');
signal din_sig : std_logic_vector(TRANSMITTER_DATA_WIDTH+2-1 DOWNTO 0) := (OTHERS => '0');
signal full_sig : std_logic;
signal empty_sig : std_logic;
begin
din_sig <= '0' & tx_fifo_in_last & tx_fifo_in_data;
-- module output ports
tx_fifo_out_error <= dout_sig(GMII_DATA_WIDTH+2-1);
tx_fifo_out_last <= dout_sig(GMII_DATA_WIDTH+1-1);
tx_fifo_out_data <= dout_sig(GMII_DATA_WIDTH-1 downto 0);
tx_fifo_in_ready <= not full_sig;
tx_fifo_out_valid <= not empty_sig;
-- connecting the FIFO inputs and outputs
rx_fifo_ip : fifo_generator_3
PORT MAP (
wr_clk => tx_fifo_in_clk,
wr_rst => tx_fifo_in_reset,
wr_en => tx_fifo_in_valid,
din => din_sig,
full => full_sig,
rd_clk => tx_fifo_out_clk,
rd_rst => tx_fifo_out_reset,
rd_en => tx_fifo_out_ready,
dout => dout_sig,
empty => empty_sig
);
end rtl;
|
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 12.12.2013 10:41:20
-- Design Name:
-- Module Name: switch_output_port_fifo - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description:
-- FIFO interface between switch port on the transmit path and MAC
-- for decoupling clocks and data widths
-- bandwidth on user interface (read) must be higher than mac interface (write)
-- width = error_width + last_width + data_width
-- depth = 32 entries
--
-- see switch_mac_txfifo.svg for further information
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity switch_output_port_fifo is
generic (
GMII_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer
);
port (
-- User-side interface (write)
tx_fifo_in_clk : in std_logic;
tx_fifo_in_reset : in std_logic;
tx_fifo_in_data : in std_logic_vector(TRANSMITTER_DATA_WIDTH-1 downto 0);
tx_fifo_in_valid : in std_logic;
tx_fifo_in_last : in std_logic;
tx_fifo_in_ready : out std_logic;
-- MAC-side interface (read)
tx_fifo_out_clk : in std_logic;
tx_fifo_out_reset : in std_logic;
tx_fifo_out_data : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
tx_fifo_out_valid : out std_logic;
tx_fifo_out_last : out std_logic;
tx_fifo_out_ready : in std_logic;
tx_fifo_out_error : out std_logic
);
end switch_output_port_fifo;
architecture rtl of switch_output_port_fifo is
component fifo_generator_3 is
PORT (
wr_clk : IN std_logic := '0';
rd_clk : IN std_logic := '0';
wr_rst : IN std_logic := '0';
rd_rst : IN std_logic := '0';
wr_en : IN std_logic := '0';
rd_en : IN std_logic := '0';
din : IN std_logic_vector(TRANSMITTER_DATA_WIDTH+2-1 DOWNTO 0) := (OTHERS => '0');
dout : OUT std_logic_vector(GMII_DATA_WIDTH+2-1 DOWNTO 0) := (OTHERS => '0');
full : OUT std_logic := '0';
empty : OUT std_logic := '1'
);
end component;
signal dout_sig : std_logic_vector(GMII_DATA_WIDTH+2-1 DOWNTO 0) := (OTHERS => '0');
signal din_sig : std_logic_vector(TRANSMITTER_DATA_WIDTH+2-1 DOWNTO 0) := (OTHERS => '0');
signal full_sig : std_logic;
signal empty_sig : std_logic;
begin
din_sig <= '0' & tx_fifo_in_last & tx_fifo_in_data;
-- module output ports
tx_fifo_out_error <= dout_sig(GMII_DATA_WIDTH+2-1);
tx_fifo_out_last <= dout_sig(GMII_DATA_WIDTH+1-1);
tx_fifo_out_data <= dout_sig(GMII_DATA_WIDTH-1 downto 0);
tx_fifo_in_ready <= not full_sig;
tx_fifo_out_valid <= not empty_sig;
-- connecting the FIFO inputs and outputs
rx_fifo_ip : fifo_generator_3
PORT MAP (
wr_clk => tx_fifo_in_clk,
wr_rst => tx_fifo_in_reset,
wr_en => tx_fifo_in_valid,
din => din_sig,
full => full_sig,
rd_clk => tx_fifo_out_clk,
rd_rst => tx_fifo_out_reset,
rd_en => tx_fifo_out_ready,
dout => dout_sig,
empty => empty_sig
);
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2675.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p04n01i02675ent IS
END c13s03b01x00p04n01i02675ent;
ARCHITECTURE c13s03b01x00p04n01i02675arch OF c13s03b01x00p04n01i02675ent IS
constant Qwerty_tyur_RT_456T : Integer := 10 ; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( Qwerty_tyur_RT_456T = 10 )
report "***PASSED TEST: c13s03b01x00p04n01i02675"
severity NOTE;
assert ( Qwerty_tyur_RT_456T = 10 )
report "***FAILED TEST: c13s03b01x00p04n01i02675 - Both upper and lower case letter should be able used in an identifier."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p04n01i02675arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2675.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p04n01i02675ent IS
END c13s03b01x00p04n01i02675ent;
ARCHITECTURE c13s03b01x00p04n01i02675arch OF c13s03b01x00p04n01i02675ent IS
constant Qwerty_tyur_RT_456T : Integer := 10 ; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( Qwerty_tyur_RT_456T = 10 )
report "***PASSED TEST: c13s03b01x00p04n01i02675"
severity NOTE;
assert ( Qwerty_tyur_RT_456T = 10 )
report "***FAILED TEST: c13s03b01x00p04n01i02675 - Both upper and lower case letter should be able used in an identifier."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p04n01i02675arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2675.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p04n01i02675ent IS
END c13s03b01x00p04n01i02675ent;
ARCHITECTURE c13s03b01x00p04n01i02675arch OF c13s03b01x00p04n01i02675ent IS
constant Qwerty_tyur_RT_456T : Integer := 10 ; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( Qwerty_tyur_RT_456T = 10 )
report "***PASSED TEST: c13s03b01x00p04n01i02675"
severity NOTE;
assert ( Qwerty_tyur_RT_456T = 10 )
report "***FAILED TEST: c13s03b01x00p04n01i02675 - Both upper and lower case letter should be able used in an identifier."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p04n01i02675arch;
|
-- Without integer boolean operations, the generated code is very ugly
-- (see test_opt.s for the resulting assembly code)
entity test_opt is end test_opt;
architecture test of test_opt is
begin
process
variable a, b, c, d, e, f : integer := 1;
function decalage_droit(a,i : integer) return integer is
begin
return a / (2**i);
end decalage_droit;
function decalage_gauche(a,i : integer) return integer is
begin
return a * (2**i);
end decalage_gauche;
function lsb(a,i : integer) return integer is
begin
return a mod (2**i);
end lsb;
begin
a := b * (2**6);
c := d mod 2;
e := f / (2**7);
report "ok !";
wait;
end process;
end test;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr_ec
-- File: ddr_ec.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Lattice DDR regs
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.ODDRXB;
--pragma translate_on
entity ec_oddr_reg is
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of ec_oddr_reg is
component ODDRXB
port(
DA : in STD_LOGIC;
DB : in STD_LOGIC;
CLK : in STD_LOGIC;
LSR : in STD_LOGIC;
Q : out STD_LOGIC
);
end component;
begin
U0 : ODDRXB port map( DA => D1, DB => D2, CLK => C1, LSR => R, Q => Q);
end;
|
library IEEE;
library IEEE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use WORK.alu_types.all;
entity TREE_PG is
port(
PG0: in std_logic_vector(1 downto 0);
PG1: in std_logic_vector(1 downto 0);
PGO: out std_logic_vector(1 downto 0)
);
end TREE_PG;
architecture BEHAVIORAL of TREE_PG is
begin
PGO(0) <= PG0(0) and PG1(0);--PROPAGATE
PGO(1) <= PG0(1) or ( PG0(0) and PG1(1) );--GENERATE
end BEHAVIORAL;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_ec_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory generators for Lattice XP/EC/ECP RAM blocks
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S1_S1 is
port (
DataInA: in std_logic_vector(0 downto 0);
DataInB: in std_logic_vector(0 downto 0);
AddressA: in std_logic_vector(12 downto 0);
AddressB: in std_logic_vector(12 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(0 downto 0);
QB: out std_logic_vector(0 downto 0));
end;
architecture Structure of EC_RAMB8_S1_S1 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 1)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>gnd, DIA1=>gnd, DIA2=>gnd,
DIA3=>gnd, DIA4=>gnd, DIA5=>gnd,
DIA6=>gnd, DIA7=>gnd, DIA8=>gnd,
DIA9=>gnd, DIA10=>gnd, DIA11=>DataInA(0),
DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
ADA0=>AddressA(0), ADA1=>AddressA(1), ADA2=>AddressA(2),
ADA3=>AddressA(3), ADA4=>AddressA(4), ADA5=>AddressA(5),
ADA6=>AddressA(6), ADA7=>AddressA(7), ADA8=>AddressA(8),
ADA9=>AddressA(9), ADA10=>AddressA(10), ADA11=>AddressA(11),
ADA12=>AddressA(12), DIB0=>gnd, DIB1=>gnd,
DIB2=>gnd, DIB3=>gnd, DIB4=>gnd,
DIB5=>gnd, DIB6=>gnd, DIB7=>gnd,
DIB8=>gnd, DIB9=>gnd, DIB10=>gnd,
DIB11=>DataInB(0), DIB12=>gnd, DIB13=>gnd,
DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
DIB17=>gnd, ADB0=>AddressB(0), ADB1=>AddressB(1),
ADB2=>AddressB(2), ADB3=>AddressB(3), ADB4=>AddressB(4),
ADB5=>AddressB(5), ADB6=>AddressB(6), ADB7=>AddressB(7),
ADB8=>AddressB(8), ADB9=>AddressB(9), ADB10=>AddressB(10),
ADB11=>AddressB(11), ADB12=>AddressB(12), DOA0=>QA(0),
DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
DOA17=>open, DOB0=>QB(0), DOB1=>open, DOB2=>open,
DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S2_S2 is
port (
DataInA: in std_logic_vector(1 downto 0);
DataInB: in std_logic_vector(1 downto 0);
AddressA: in std_logic_vector(11 downto 0);
AddressB: in std_logic_vector(11 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(1 downto 0);
QB: out std_logic_vector(1 downto 0));
end;
architecture Structure of EC_RAMB8_S2_S2 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 2, DATA_WIDTH_A=> 2)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>gnd, DIA1=>DataInA(0), DIA2=>gnd,
DIA3=>gnd, DIA4=>gnd, DIA5=>gnd,
DIA6=>gnd, DIA7=>gnd, DIA8=>gnd,
DIA9=>gnd, DIA10=>gnd, DIA11=>DataInA(1),
DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
ADA0=>vcc, ADA1=>AddressA(0), ADA2=>AddressA(1),
ADA3=>AddressA(2), ADA4=>AddressA(3), ADA5=>AddressA(4),
ADA6=>AddressA(6), ADA7=>AddressA(6), ADA8=>AddressA(7),
ADA9=>AddressA(8), ADA10=>AddressA(9), ADA11=>AddressA(10),
ADA12=>AddressA(11), DIB0=>gnd, DIB1=>DataInB(0),
DIB2=>gnd, DIB3=>gnd, DIB4=>gnd,
DIB5=>gnd, DIB6=>gnd, DIB7=>gnd,
DIB8=>gnd, DIB9=>gnd, DIB10=>gnd,
DIB11=>DataInB(1), DIB12=>gnd, DIB13=>gnd,
DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
DIB17=>gnd, ADB0=>vcc, ADB1=>AddressB(0),
ADB2=>AddressB(1), ADB3=>AddressB(2), ADB4=>AddressB(3),
ADB5=>AddressB(4), ADB6=>AddressB(5), ADB7=>AddressB(6),
ADB8=>AddressB(7), ADB9=>AddressB(8), ADB10=>AddressB(9),
ADB11=>AddressB(10), ADB12=>AddressB(11), DOA0=>QA(1),
DOA1=>QA(0), DOA2=>open, DOA3=>open, DOA4=>open,
DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
DOA17=>open, DOB0=>QB(1), DOB1=>QB(0), DOB2=>open,
DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S4_S4 is
port (
DataInA: in std_logic_vector(3 downto 0);
DataInB: in std_logic_vector(3 downto 0);
AddressA: in std_logic_vector(10 downto 0);
AddressB: in std_logic_vector(10 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(3 downto 0);
QB: out std_logic_vector(3 downto 0));
end;
architecture Structure of EC_RAMB8_S4_S4 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 4, DATA_WIDTH_A=> 4)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
DIA3=>DataInA(3), DIA4=>gnd, DIA5=>gnd,
DIA6=>gnd, DIA7=>gnd, DIA8=>gnd,
DIA9=>gnd, DIA10=>gnd, DIA11=>gnd,
DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
ADA0=>vcc, ADA1=>vcc, ADA2=>AddressA(0),
ADA3=>AddressA(1), ADA4=>AddressA(2), ADA5=>AddressA(3),
ADA6=>AddressA(4), ADA7=>AddressA(5), ADA8=>AddressA(6),
ADA9=>AddressA(7), ADA10=>AddressA(8), ADA11=>AddressA(9),
ADA12=>AddressA(10), DIB0=>DataInB(0), DIB1=>DataInB(1),
DIB2=>DataInB(2), DIB3=>DataInB(3), DIB4=>gnd,
DIB5=>gnd, DIB6=>gnd, DIB7=>gnd,
DIB8=>gnd, DIB9=>gnd, DIB10=>gnd,
DIB11=>gnd, DIB12=>gnd, DIB13=>gnd,
DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
DIB17=>gnd, ADB0=>vcc, ADB1=>vcc,
ADB2=>AddressB(0), ADB3=>AddressB(1), ADB4=>AddressB(2),
ADB5=>AddressB(3), ADB6=>AddressB(4), ADB7=>AddressB(5),
ADB8=>AddressB(6), ADB9=>AddressB(7), ADB10=>AddressB(8),
ADB11=>AddressB(9), ADB12=>AddressB(10), DOA0=>QA(0),
DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>open,
DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
DOA17=>open, DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2),
DOB3=>QB(3), DOB4=>open, DOB5=>open, DOB6=>open,
DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S9_S9 is
port (
DataInA: in std_logic_vector(8 downto 0);
DataInB: in std_logic_vector(8 downto 0);
AddressA: in std_logic_vector(9 downto 0);
AddressB: in std_logic_vector(9 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(8 downto 0);
QB: out std_logic_vector(8 downto 0));
end;
architecture Structure of EC_RAMB8_S9_S9 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5),
DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8),
DIA9=>gnd, DIA10=>gnd, DIA11=>gnd,
DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
ADA0=>vcc, ADA1=>vcc, ADA2=>gnd,
ADA3=>AddressA(0), ADA4=>AddressA(1), ADA5=>AddressA(2),
ADA6=>AddressA(3), ADA7=>AddressA(4), ADA8=>AddressA(5),
ADA9=>AddressA(6), ADA10=>AddressA(7), ADA11=>AddressA(8),
ADA12=>AddressA(9), DIB0=>DataInB(0), DIB1=>DataInB(1),
DIB2=>DataInB(2), DIB3=>DataInB(3), DIB4=>DataInB(4),
DIB5=>DataInB(5), DIB6=>DataInB(6), DIB7=>DataInB(7),
DIB8=>DataInB(8), DIB9=>gnd, DIB10=>gnd,
DIB11=>gnd, DIB12=>gnd, DIB13=>gnd,
DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
DIB17=>gnd, ADB0=>vcc, ADB1=>vcc,
ADB2=>gnd, ADB3=>AddressB(0), ADB4=>AddressB(1),
ADB5=>AddressB(2), ADB6=>AddressB(3), ADB7=>AddressB(4),
ADB8=>AddressB(5), ADB9=>AddressB(6), ADB10=>AddressB(7),
ADB11=>AddressB(8), ADB12=>AddressB(9), DOA0=>QA(0),
DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>QA(4),
DOA5=>QA(5), DOA6=>QA(6), DOA7=>QA(7), DOA8=>QA(8),
DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
DOA17=>open, DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2),
DOB3=>QB(3), DOB4=>QB(4), DOB5=>QB(5), DOB6=>QB(6),
DOB7=>QB(7), DOB8=>QB(8), DOB9=>open, DOB10=>open,
DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S18_S18 is
port (
DataInA: in std_logic_vector(17 downto 0);
DataInB: in std_logic_vector(17 downto 0);
AddressA: in std_logic_vector(8 downto 0);
AddressB: in std_logic_vector(8 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(17 downto 0);
QB: out std_logic_vector(17 downto 0));
end;
architecture Structure of EC_RAMB8_S18_S18 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5),
DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8),
DIA9=>DataInA(9), DIA10=>DataInA(10), DIA11=>DataInA(11),
DIA12=>DataInA(12), DIA13=>DataInA(13), DIA14=>DataInA(14),
DIA15=>DataInA(15), DIA16=>DataInA(16), DIA17=>DataInA(17),
ADA0=>vcc, ADA1=>vcc, ADA2=>gnd,
ADA3=>gnd, ADA4=>AddressA(0), ADA5=>AddressA(1),
ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4),
ADA9=>AddressA(5), ADA10=>AddressA(6), ADA11=>AddressA(7),
ADA12=>AddressA(8), DIB0=>DataInB(0), DIB1=>DataInB(1),
DIB2=>DataInB(2), DIB3=>DataInB(3), DIB4=>DataInB(4),
DIB5=>DataInB(5), DIB6=>DataInB(6), DIB7=>DataInB(7),
DIB8=>DataInB(8), DIB9=>DataInB(9), DIB10=>DataInB(10),
DIB11=>DataInB(11), DIB12=>DataInB(12), DIB13=>DataInB(13),
DIB14=>DataInB(14), DIB15=>DataInB(15), DIB16=>DataInB(16),
DIB17=>DataInB(17), ADB0=>vcc, ADB1=>vcc,
ADB2=>gnd, ADB3=>gnd, ADB4=>AddressB(0),
ADB5=>AddressB(1), ADB6=>AddressB(2), ADB7=>AddressB(3),
ADB8=>AddressB(4), ADB9=>AddressB(5), ADB10=>AddressB(6),
ADB11=>AddressB(7), ADB12=>AddressB(8), DOA0=>QA(0),
DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>QA(4),
DOA5=>QA(5), DOA6=>QA(6), DOA7=>QA(7), DOA8=>QA(8),
DOA9=>QA(9), DOA10=>QA(10), DOA11=>QA(11), DOA12=>QA(12),
DOA13=>QA(13), DOA14=>QA(14), DOA15=>QA(15), DOA16=>QA(16),
DOA17=>QA(17), DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2),
DOB3=>QB(3), DOB4=>QB(4), DOB5=>QB(5), DOB6=>QB(6),
DOB7=>QB(7), DOB8=>QB(8), DOB9=>QB(9), DOB10=>QB(10),
DOB11=>QB(11), DOB12=>QB(12), DOB13=>QB(13), DOB14=>QB(14),
DOB15=>QB(15), DOB16=>QB(16), DOB17=>QB(17));
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S1 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (12 downto 0);
data : in std_logic_vector (0 downto 0);
q : out std_logic_vector (0 downto 0));
end;
architecture behav of EC_RAMB8_S1 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 1)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>gnd,
DI1=>gnd, DI2=>gnd, DI3=>gnd, DI4=>gnd,
DI5=>gnd, DI6=>gnd, DI7=>gnd, DI8=>gnd,
DI9=>gnd, DI10=>gnd, DI11=>Data(0),
DI12=>gnd, DI13=>gnd, DI14=>gnd,
DI15=>gnd, DI16=>gnd, DI17=>gnd,
AD0=>Address(0), AD1=>Address(1), AD2=>Address(2),
AD3=>Address(3), AD4=>Address(4), AD5=>Address(5),
AD6=>Address(6), AD7=>Address(7), AD8=>Address(8),
AD9=>Address(9), AD10=>Address(10), AD11=>Address(11),
AD12=>Address(12), DO0=>Q(0), DO1=>open, DO2=>open, DO3=>open,
DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
DO14=>open, DO15=>open, DO16=>open, DO17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S2 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (11 downto 0);
data : in std_logic_vector (1 downto 0);
q : out std_logic_vector (1 downto 0));
end;
architecture behav of EC_RAMB8_S2 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 2)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>gnd,
DI1=>Data(0), DI2=>gnd, DI3=>gnd, DI4=>gnd,
DI5=>gnd, DI6=>gnd, DI7=>gnd, DI8=>gnd,
DI9=>gnd, DI10=>gnd, DI11=>Data(1),
DI12=>gnd, DI13=>gnd, DI14=>gnd,
DI15=>gnd, DI16=>gnd, DI17=>gnd,
AD0=>gnd, AD1=>Address(0), AD2=>Address(1),
AD3=>Address(2), AD4=>Address(3), AD5=>Address(4),
AD6=>Address(5), AD7=>Address(6), AD8=>Address(7),
AD9=>Address(8), AD10=>Address(9), AD11=>Address(10),
AD12=>Address(11), DO0=>Q(1), DO1=>Q(0), DO2=>open, DO3=>open,
DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
DO14=>open, DO15=>open, DO16=>open, DO17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S4 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (10 downto 0);
data : in std_logic_vector (3 downto 0);
q : out std_logic_vector (3 downto 0));
end;
architecture behav of EC_RAMB8_S4 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 4)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>Data(0),
DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), DI4=>gnd,
DI5=>gnd, DI6=>gnd, DI7=>gnd, DI8=>gnd,
DI9=>gnd, DI10=>gnd, DI11=>gnd,
DI12=>gnd, DI13=>gnd, DI14=>gnd,
DI15=>gnd, DI16=>gnd, DI17=>gnd,
AD0=>gnd, AD1=>gnd, AD2=>Address(0),
AD3=>Address(1), AD4=>Address(2), AD5=>Address(3),
AD6=>Address(4), AD7=>Address(5), AD8=>Address(6),
AD9=>Address(7), AD10=>Address(8), AD11=>Address(9),
AD12=>Address(10), DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3),
DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
DO14=>open, DO15=>open, DO16=>open, DO17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S9 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (9 downto 0);
data : in std_logic_vector (8 downto 0);
q : out std_logic_vector (8 downto 0));
end;
architecture behav of EC_RAMB8_S9 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 9)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>Data(0),
DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), DI4=>Data(4),
DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), DI8=>Data(8),
DI9=>gnd, DI10=>gnd, DI11=>gnd,
DI12=>gnd, DI13=>gnd, DI14=>gnd,
DI15=>gnd, DI16=>gnd, DI17=>gnd,
AD0=>gnd, AD1=>gnd, AD2=>gnd,
AD3=>Address(0), AD4=>Address(1), AD5=>Address(2),
AD6=>Address(3), AD7=>Address(4), AD8=>Address(5),
AD9=>Address(6), AD10=>Address(7), AD11=>Address(8),
AD12=>Address(9), DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3),
DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>Q(8),
DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
DO14=>open, DO15=>open, DO16=>open, DO17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S18 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (8 downto 0);
data : in std_logic_vector (17 downto 0);
q : out std_logic_vector (17 downto 0));
end;
architecture behav of EC_RAMB8_S18 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 18)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>Data(0),
DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), DI4=>Data(4),
DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), DI8=>Data(8),
DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
AD0=>gnd, AD1=>gnd, AD2=>gnd,
AD3=>gnd, AD4=>Address(0), AD5=>Address(1),
AD6=>Address(2), AD7=>Address(3), AD8=>Address(4),
AD9=>Address(5), AD10=>Address(6), AD11=>Address(7),
AD12=>Address(8), DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3),
DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>Q(8),
DO9=>Q(9), DO10=>Q(10), DO11=>Q(11), DO12=>Q(12), DO13=>Q(13),
DO14=>Q(14), DO15=>Q(15), DO16=>Q(16), DO17=>Q(17));
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S36 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (7 downto 0);
data : in std_logic_vector (35 downto 0);
q : out std_logic_vector (35 downto 0));
end;
architecture behav of EC_RAMB8_S36 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL", GSR=>"DISABLED",
RESETMODE=>"ASYNC", REGMODE_B=>"NOREG", REGMODE_A=>"NOREG",
DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18)
port map (CEA => en, CLKA => clk, WEA => we, CSA0 => gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=> gnd, CEB=> en,
CLKB=> clk, WEB=> we, CSB0=>gnd, CSB1=>gnd,
CSB2=>gnd, RSTB=>gnd, DIA0=>Data(0), DIA1=>Data(1),
DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5),
DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9),
DIA10=>Data(10), DIA11=>Data(11), DIA12=>Data(12),
DIA13=>Data(13), DIA14=>Data(14), DIA15=>Data(15),
DIA16=>Data(16), DIA17=>Data(17), ADA0=>vcc,
ADA1=>vcc, ADA2=>vcc, ADA3=>vcc,
ADA4=>Address(0), ADA5=>Address(1), ADA6=>Address(2),
ADA7=>Address(3), ADA8=>Address(4), ADA9=>Address(5),
ADA10=>Address(6), ADA11=>Address(7), ADA12=>gnd,
DIB0=>Data(18), DIB1=>Data(19), DIB2=>Data(20),
DIB3=>Data(21), DIB4=>Data(22), DIB5=>Data(23),
DIB6=>Data(24), DIB7=>Data(25), DIB8=>Data(26),
DIB9=>Data(27), DIB10=>Data(28), DIB11=>Data(29),
DIB12=>Data(30), DIB13=>Data(31), DIB14=>Data(32),
DIB15=>Data(33), DIB16=>Data(34), DIB17=>Data(35),
ADB0=>vcc, ADB1=>vcc, ADB2=>gnd,
ADB3=>gnd, ADB4=>Address(0), ADB5=>Address(1),
ADB6=>Address(2), ADB7=>Address(3), ADB8=>Address(4),
ADB9=>Address(5), ADB10=>Address(6), ADB11=>Address(7),
ADB12=>vcc, DOA0=>Q(0), DOA1=>Q(1), DOA2=>Q(2),
DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5), DOA6=>Q(6), DOA7=>Q(7),
DOA8=>Q(8), DOA9=>Q(9), DOA10=>Q(10), DOA11=>Q(11),
DOA12=>Q(12), DOA13=>Q(13), DOA14=>Q(14), DOA15=>Q(15),
DOA16=>Q(16), DOA17=>Q(17), DOB0=>Q(18), DOB1=>Q(19),
DOB2=>Q(20), DOB3=>Q(21), DOB4=>Q(22), DOB5=>Q(23),
DOB6=>Q(24), DOB7=>Q(25), DOB8=>Q(26), DOB9=>Q(27),
DOB10=>Q(28), DOB11=>Q(29), DOB12=>Q(30), DOB13=>Q(31),
DOB14=>Q(32), DOB15=>Q(33), DOB16=>Q(34), DOB17=>Q(35));
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
entity ec_syncram is
generic (abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of ec_syncram is
component EC_RAMB8_S1 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (12 downto 0);
data : in std_logic_vector (0 downto 0);
q : out std_logic_vector (0 downto 0));
end component;
component EC_RAMB8_S2 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (11 downto 0);
data : in std_logic_vector (1 downto 0);
q : out std_logic_vector (1 downto 0));
end component;
component EC_RAMB8_S4 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (10 downto 0);
data : in std_logic_vector (3 downto 0);
q : out std_logic_vector (3 downto 0));
end component;
component EC_RAMB8_S9 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (9 downto 0);
data : in std_logic_vector (8 downto 0);
q : out std_logic_vector (8 downto 0));
end component;
component EC_RAMB8_S18 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (8 downto 0);
data : in std_logic_vector (17 downto 0);
q : out std_logic_vector (17 downto 0));
end component;
component EC_RAMB8_S36 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (7 downto 0);
data : in std_logic_vector (35 downto 0);
q : out std_logic_vector (35 downto 0));
end component;
constant DMAX : integer := dbits+36;
constant AMAX : integer := 13;
signal gnd : std_ulogic;
signal do, di : std_logic_vector(DMAX downto 0);
signal xa, ya : std_logic_vector(AMAX downto 0);
begin
gnd <= '0'; dataout <= do(dbits-1 downto 0); di(dbits-1 downto 0) <= datain;
di(DMAX downto dbits) <= (others => '0'); xa(abits-1 downto 0) <= address;
xa(AMAX downto abits) <= (others => '0'); ya(abits-1 downto 0) <= address;
ya(AMAX downto abits) <= (others => '1');
a8 : if (abits <= 8) generate
x : for i in 0 to ((dbits-1)/36) generate
r : EC_RAMB8_S36 port map ( clk, enable, write, xa(7 downto 0),
di((i+1)*36-1 downto i*36), do((i+1)*36-1 downto i*36));
end generate;
end generate;
a9 : if (abits = 9) generate
x : for i in 0 to ((dbits-1)/18) generate
r : EC_RAMB8_S18 port map ( clk, enable, write, xa(8 downto 0),
di((i+1)*18-1 downto i*18), do((i+1)*18-1 downto i*18));
end generate;
end generate;
a10 : if (abits = 10) generate
x : for i in 0 to ((dbits-1)/9) generate
r : EC_RAMB8_S9 port map ( clk, enable, write, xa(9 downto 0),
di((i+1)*9-1 downto i*9), do((i+1)*9-1 downto i*9));
end generate;
end generate;
a11 : if (abits = 11) generate
x : for i in 0 to ((dbits-1)/4) generate
r : EC_RAMB8_S4 port map ( clk, enable, write, xa(10 downto 0),
di((i+1)*4-1 downto i*4), do((i+1)*4-1 downto i*4));
end generate;
end generate;
a12 : if (abits = 12) generate
x : for i in 0 to ((dbits-1)/2) generate
r : EC_RAMB8_S2 port map ( clk, enable, write, xa(11 downto 0),
di((i+1)*2-1 downto i*2), do((i+1)*2-1 downto i*2));
end generate;
end generate;
a13 : if (abits = 13) generate
x : for i in 0 to ((dbits-1)/1) generate
r : EC_RAMB8_S1 port map ( clk, enable, write, xa(12 downto 0),
di((i+1)*1-1 downto i*1), do((i+1)*1-1 downto i*1));
end generate;
end generate;
-- pragma translate_off
unsup : if (abits > 13) generate
x : process
begin
assert false
report "Lattice EC syncram mapper: unsupported memory configuration!"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
entity ec_syncram_dp is
generic (
abits : integer := 4; dbits : integer := 32
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of ec_syncram_dp is
component EC_RAMB8_S1_S1 is port (
DataInA, DataInB: in std_logic_vector(0 downto 0);
AddressA, AddressB: in std_logic_vector(12 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(0 downto 0));
end component;
component EC_RAMB8_S2_S2 is port (
DataInA, DataInB: in std_logic_vector(1 downto 0);
AddressA, AddressB: in std_logic_vector(11 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(1 downto 0));
end component;
component EC_RAMB8_S4_S4 is port (
DataInA, DataInB: in std_logic_vector(3 downto 0);
AddressA, AddressB: in std_logic_vector(10 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(3 downto 0));
end component;
component EC_RAMB8_S9_S9 is port (
DataInA, DataInB: in std_logic_vector(8 downto 0);
AddressA, AddressB: in std_logic_vector(9 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(8 downto 0));
end component;
component EC_RAMB8_S18_S18 is port (
DataInA, DataInB: in std_logic_vector(17 downto 0);
AddressA, AddressB: in std_logic_vector(8 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(17 downto 0));
end component;
constant DMAX : integer := dbits+18;
constant AMAX : integer := 13;
signal gnd, vcc : std_ulogic;
signal do1, do2, di1, di2 : std_logic_vector(DMAX downto 0);
signal addr1, addr2 : std_logic_vector(AMAX downto 0);
begin
gnd <= '0'; vcc <= '1';
dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
di1(dbits-1 downto 0) <= datain1; di1(DMAX downto dbits) <= (others => '0');
di2(dbits-1 downto 0) <= datain2; di2(DMAX downto dbits) <= (others => '0');
addr1(abits-1 downto 0) <= address1; addr1(AMAX downto abits) <= (others => '0');
addr2(abits-1 downto 0) <= address2; addr2(AMAX downto abits) <= (others => '0');
a9 : if abits <= 9 generate
x : for i in 0 to ((dbits-1)/18) generate
r0 : EC_RAMB8_S18_S18 port map (
di1((i+1)*18-1 downto i*18), di2((i+1)*18-1 downto i*18),
addr1(8 downto 0), addr2(8 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*18-1 downto i*18), do2((i+1)*18-1 downto i*18));
end generate;
end generate;
a10 : if abits = 10 generate
x : for i in 0 to ((dbits-1)/9) generate
r0 : EC_RAMB8_S9_S9 port map (
di1((i+1)*9-1 downto i*9), di2((i+1)*9-1 downto i*9),
addr1(9 downto 0), addr2(9 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*9-1 downto i*9), do2((i+1)*9-1 downto i*9));
end generate;
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/4) generate
r0 : EC_RAMB8_S4_S4 port map (
di1((i+1)*4-1 downto i*4), di2((i+1)*4-1 downto i*4),
addr1(10 downto 0), addr2(10 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*4-1 downto i*4), do2((i+1)*4-1 downto i*4));
end generate;
end generate;
a12 : if abits = 12 generate
x : for i in 0 to ((dbits-1)/2) generate
r0 : EC_RAMB8_S2_S2 port map (
di1((i+1)*2-1 downto i*2), di2((i+1)*2-1 downto i*2),
addr1(11 downto 0), addr2(11 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*2-1 downto i*2), do2((i+1)*2-1 downto i*2));
end generate;
end generate;
a13 : if abits = 13 generate
x : for i in 0 to ((dbits-1)/1) generate
r0 : EC_RAMB8_S1_S1 port map (
di1((i+1)*1-1 downto i*1), di2((i+1)*1-1 downto i*1),
addr1(12 downto 0), addr2(12 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*1-1 downto i*1), do2((i+1)*1-1 downto i*1));
end generate;
end generate;
-- pragma translate_off
unsup : if (abits > 13) generate
x : process
begin
assert false
report "Lattice EC syncram_dp: unsupported memory configuration!"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: dualBRAM_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 2
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : dualBRAM.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 00
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 256
-- C_READ_DEPTH_A : 256
-- C_ADDRA_WIDTH : 8
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 256
-- C_READ_DEPTH_B : 256
-- C_ADDRB_WIDTH : 8
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 1
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY dualBRAM_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END dualBRAM_prod;
ARCHITECTURE xilinx OF dualBRAM_prod IS
COMPONENT dualBRAM_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : dualBRAM_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
|
architecture RTL of FIFO is
begin
process
begin
SIMPLE_LABEL : x := z;
a := b;
CONDITIONAL_LABEL : x := z when b = 0 else y;
x := z when b = 0 else y;
SELECTED_LABEL : with some_expression select a := b when z = 1;
with some_expression select a := b when z = 1;
end process;
end architecture;
-- Violations below
architecture RTL of FIFO is
begin
process
begin
a :=b;
a := b;
x :=z when b = 0 else y;
x := z when b = 0 else y;
with some_expression select a :=b when z = 1;
with some_expression select a := b when z = 1;
end process;
end architecture;
|
-- Twofish_cbc_encryption_monte_carlo_testbench_128bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file is the testbench for the Encryption Monte Carlo KAT of the twofish cipher with 128 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity cbc_encryption_monte_carlo_testbench128 is
end cbc_encryption_monte_carlo_testbench128;
architecture cbc_encryption128_monte_carlo_testbench_arch of cbc_encryption_monte_carlo_testbench128 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched128
port (
odd_in_tk128,
even_in_tk128 : in std_logic_vector(7 downto 0);
in_key_tk128 : in std_logic_vector(127 downto 0);
out_key_up_tk128,
out_key_down_tk128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched128
port (
in_key_twk128 : in std_logic_vector(127 downto 0);
out_K0_twk128,
out_K1_twk128,
out_K2_twk128,
out_K3_twk128,
out_K4_twk128,
out_K5_twk128,
out_K6_twk128,
out_K7_twk128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_encryption_round128
port (
in1_ter128,
in2_ter128,
in3_ter128,
in4_ter128,
in_Sfirst_ter128,
in_Ssecond_ter128,
in_key_up_ter128,
in_key_down_ter128 : in std_logic_vector(31 downto 0);
out1_ter128,
out2_ter128,
out3_ter128,
out4_ter128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S128
port (
in_key_ts128 : in std_logic_vector(127 downto 0);
out_Sfirst_ts128,
out_Ssecond_ts128 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_cbc_encryption_monte_carlo_testvalues_128bits.txt";
FILE output_file : text is out "twofish_cbc_encryption_monte_carlo_128bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 0 to 9999) return string is
variable our_text : string (1 to 4) := (others => ' ');
variable thousands,
hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100;
thousands := (int_number - (int_number mod 1000)) / 1000;
our_text(1) := digit_to_char(thousands);
our_text(2) := digit_to_char(hundreds);
our_text(3) := digit_to_char(tens);
our_text(4) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
twofish_key,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal key_up,
key_down,
Sfirst,
Ssecond,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched128
port map (
in_key_twk128 => twofish_key,
out_K0_twk128 => K0,
out_K1_twk128 => K1,
out_K2_twk128 => K2,
out_K3_twk128 => K3,
out_K4_twk128 => K4,
out_K5_twk128 => K5,
out_K6_twk128 => K6,
out_K7_twk128 => K7
);
-- performing the input whitening XORs
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched128
port map (
odd_in_tk128 => odd_number,
even_in_tk128 => even_number,
in_key_tk128 => twofish_key,
out_key_up_tk128 => key_up,
out_key_down_tk128 => key_down
);
producing_the_Skeys: twofish_S128
port map (
in_key_ts128 => twofish_key,
out_Sfirst_ts128 => Sfirst,
out_Ssecond_ts128 => Ssecond
);
the_encryption_circuit: twofish_encryption_round128
port map (
in1_ter128 => to_round(127 downto 96),
in2_ter128 => to_round(95 downto 64),
in3_ter128 => to_round(63 downto 32),
in4_ter128 => to_round(31 downto 0),
in_Sfirst_ter128 => Sfirst,
in_Ssecond_ter128 => Ssecond,
in_key_up_ter128 => key_up,
in_key_down_ter128 => key_down,
out1_ter128 => to_encr_reg128(127 downto 96),
out2_ter128 => to_encr_reg128(95 downto 64),
out3_ter128 => to_encr_reg128(63 downto 32),
out4_ter128 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
cbc_emc_proc: process
variable key_f, -- key input from file
pt_f, -- plaintext from file
ct_f,
iv_f : line; -- ciphertext from file
variable key_v, -- key vector input
pt_v , -- plaintext vector
ct_v,
iv_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats
variable round : integer range 0 to 16 := 0; -- holds the rounds
variable PT, CT, CV, CTj_1 : std_logic_vector(127 downto 0) := (others => '0');
begin
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file, iv_f);
readline(input_file, pt_f);
readline(input_file,ct_f);
hread(key_f,key_v);
hread(iv_f, iv_v);
hread(pt_f,pt_v);
hread(ct_f,ct_v);
twofish_key <= key_v;
PT := pt_v;
CV := iv_v;
for counter_10000 in 0 to 9999 loop
input_data <= PT xor CV;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00001000"; -- 8
odd_number <= "00001001"; -- 9
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector(((round*2)+8), 8);
odd_number <= conv_std_logic_vector(((round*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
CTj_1 := CT;
CT := output_data;
if ( counter_10000 = 0 ) then
PT := CV;
else
PT := CTj_1;
end if; -- counter_10000 = 0
CV := CT;
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note;
end loop; -- counter_10000
hwrite(key_f, key_v);
hwrite(iv_f, iv_v);
hwrite(pt_f, pt_v);
hwrite(ct_f,output_data);
writeline(output_file,key_f);
writeline(output_file, iv_f);
writeline(output_file,pt_f);
writeline(output_file,ct_f);
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure;
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter_400) &" OK" severity note;
counter_400 := counter_400 + 1;
end loop;
assert false report "***** CBC Encryption Monte Carlo Test with 128 bits key size ended succesfully! :) *****" severity failure;
end process cbc_emc_proc;
end cbc_encryption128_monte_carlo_testbench_arch;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
bufw_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_EN_A : OUT STD_LOGIC;
bufw_WEN_A : OUT STD_LOGIC_VECTOR (15 downto 0);
bufw_Din_A : OUT STD_LOGIC_VECTOR (127 downto 0);
bufw_Dout_A : IN STD_LOGIC_VECTOR (127 downto 0);
bufw_Clk_A : OUT STD_LOGIC;
bufw_Rst_A : OUT STD_LOGIC;
bufi_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_EN_A : OUT STD_LOGIC;
bufi_WEN_A : OUT STD_LOGIC_VECTOR (15 downto 0);
bufi_Din_A : OUT STD_LOGIC_VECTOR (127 downto 0);
bufi_Dout_A : IN STD_LOGIC_VECTOR (127 downto 0);
bufi_Clk_A : OUT STD_LOGIC;
bufi_Rst_A : OUT STD_LOGIC;
bufo_0_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_0_EN_A : OUT STD_LOGIC;
bufo_0_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_0_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_0_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_0_Clk_A : OUT STD_LOGIC;
bufo_0_Rst_A : OUT STD_LOGIC;
bufo_1_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_1_EN_A : OUT STD_LOGIC;
bufo_1_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_1_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_1_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_1_Clk_A : OUT STD_LOGIC;
bufo_1_Rst_A : OUT STD_LOGIC;
bufo_2_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_2_EN_A : OUT STD_LOGIC;
bufo_2_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_2_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_2_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_2_Clk_A : OUT STD_LOGIC;
bufo_2_Rst_A : OUT STD_LOGIC;
bufo_3_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_3_EN_A : OUT STD_LOGIC;
bufo_3_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_3_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_3_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_3_Clk_A : OUT STD_LOGIC;
bufo_3_Rst_A : OUT STD_LOGIC;
bufo_4_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_4_EN_A : OUT STD_LOGIC;
bufo_4_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_4_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_4_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_4_Clk_A : OUT STD_LOGIC;
bufo_4_Rst_A : OUT STD_LOGIC;
bufo_5_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_5_EN_A : OUT STD_LOGIC;
bufo_5_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_5_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_5_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_5_Clk_A : OUT STD_LOGIC;
bufo_5_Rst_A : OUT STD_LOGIC;
bufo_6_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_6_EN_A : OUT STD_LOGIC;
bufo_6_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_6_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_6_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_6_Clk_A : OUT STD_LOGIC;
bufo_6_Rst_A : OUT STD_LOGIC;
bufo_7_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_7_EN_A : OUT STD_LOGIC;
bufo_7_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_7_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_7_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_7_Clk_A : OUT STD_LOGIC;
bufo_7_Rst_A : OUT STD_LOGIC;
bufo_8_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_8_EN_A : OUT STD_LOGIC;
bufo_8_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_8_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_8_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_8_Clk_A : OUT STD_LOGIC;
bufo_8_Rst_A : OUT STD_LOGIC;
bufo_9_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_9_EN_A : OUT STD_LOGIC;
bufo_9_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_9_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_9_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_9_Clk_A : OUT STD_LOGIC;
bufo_9_Rst_A : OUT STD_LOGIC;
bufo_10_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_10_EN_A : OUT STD_LOGIC;
bufo_10_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_10_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_10_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_10_Clk_A : OUT STD_LOGIC;
bufo_10_Rst_A : OUT STD_LOGIC;
bufo_11_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_11_EN_A : OUT STD_LOGIC;
bufo_11_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_11_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_11_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_11_Clk_A : OUT STD_LOGIC;
bufo_11_Rst_A : OUT STD_LOGIC;
bufo_12_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_12_EN_A : OUT STD_LOGIC;
bufo_12_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_12_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_12_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_12_Clk_A : OUT STD_LOGIC;
bufo_12_Rst_A : OUT STD_LOGIC;
bufo_13_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_13_EN_A : OUT STD_LOGIC;
bufo_13_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_13_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_13_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_13_Clk_A : OUT STD_LOGIC;
bufo_13_Rst_A : OUT STD_LOGIC;
bufo_14_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_14_EN_A : OUT STD_LOGIC;
bufo_14_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_14_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_14_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_14_Clk_A : OUT STD_LOGIC;
bufo_14_Rst_A : OUT STD_LOGIC;
bufo_15_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_15_EN_A : OUT STD_LOGIC;
bufo_15_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_15_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_15_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_15_Clk_A : OUT STD_LOGIC;
bufo_15_Rst_A : OUT STD_LOGIC;
bufo_16_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_16_EN_A : OUT STD_LOGIC;
bufo_16_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_16_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_16_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_16_Clk_A : OUT STD_LOGIC;
bufo_16_Rst_A : OUT STD_LOGIC;
bufo_17_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_17_EN_A : OUT STD_LOGIC;
bufo_17_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_17_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_17_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_17_Clk_A : OUT STD_LOGIC;
bufo_17_Rst_A : OUT STD_LOGIC;
bufo_18_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_18_EN_A : OUT STD_LOGIC;
bufo_18_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_18_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_18_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_18_Clk_A : OUT STD_LOGIC;
bufo_18_Rst_A : OUT STD_LOGIC;
bufo_19_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_19_EN_A : OUT STD_LOGIC;
bufo_19_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_19_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_19_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_19_Clk_A : OUT STD_LOGIC;
bufo_19_Rst_A : OUT STD_LOGIC;
bufo_20_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_20_EN_A : OUT STD_LOGIC;
bufo_20_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_20_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_20_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_20_Clk_A : OUT STD_LOGIC;
bufo_20_Rst_A : OUT STD_LOGIC;
bufo_21_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_21_EN_A : OUT STD_LOGIC;
bufo_21_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_21_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_21_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_21_Clk_A : OUT STD_LOGIC;
bufo_21_Rst_A : OUT STD_LOGIC;
bufo_22_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_22_EN_A : OUT STD_LOGIC;
bufo_22_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_22_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_22_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_22_Clk_A : OUT STD_LOGIC;
bufo_22_Rst_A : OUT STD_LOGIC;
bufo_23_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_23_EN_A : OUT STD_LOGIC;
bufo_23_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_23_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_23_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_23_Clk_A : OUT STD_LOGIC;
bufo_23_Rst_A : OUT STD_LOGIC;
bufo_24_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_24_EN_A : OUT STD_LOGIC;
bufo_24_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_24_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_24_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_24_Clk_A : OUT STD_LOGIC;
bufo_24_Rst_A : OUT STD_LOGIC;
bufo_25_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_25_EN_A : OUT STD_LOGIC;
bufo_25_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_25_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_25_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_25_Clk_A : OUT STD_LOGIC;
bufo_25_Rst_A : OUT STD_LOGIC;
bufo_26_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_26_EN_A : OUT STD_LOGIC;
bufo_26_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_26_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_26_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_26_Clk_A : OUT STD_LOGIC;
bufo_26_Rst_A : OUT STD_LOGIC;
bufo_27_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_27_EN_A : OUT STD_LOGIC;
bufo_27_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_27_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_27_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_27_Clk_A : OUT STD_LOGIC;
bufo_27_Rst_A : OUT STD_LOGIC;
bufo_28_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_28_EN_A : OUT STD_LOGIC;
bufo_28_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_28_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_28_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_28_Clk_A : OUT STD_LOGIC;
bufo_28_Rst_A : OUT STD_LOGIC;
bufo_29_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_29_EN_A : OUT STD_LOGIC;
bufo_29_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_29_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_29_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_29_Clk_A : OUT STD_LOGIC;
bufo_29_Rst_A : OUT STD_LOGIC;
bufo_30_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_30_EN_A : OUT STD_LOGIC;
bufo_30_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_30_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_30_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_30_Clk_A : OUT STD_LOGIC;
bufo_30_Rst_A : OUT STD_LOGIC;
bufo_31_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_31_EN_A : OUT STD_LOGIC;
bufo_31_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_31_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_31_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_31_Clk_A : OUT STD_LOGIC;
bufo_31_Rst_A : OUT STD_LOGIC;
bufo_32_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_32_EN_A : OUT STD_LOGIC;
bufo_32_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_32_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_32_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_32_Clk_A : OUT STD_LOGIC;
bufo_32_Rst_A : OUT STD_LOGIC;
bufo_33_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_33_EN_A : OUT STD_LOGIC;
bufo_33_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_33_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_33_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_33_Clk_A : OUT STD_LOGIC;
bufo_33_Rst_A : OUT STD_LOGIC;
bufo_34_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_34_EN_A : OUT STD_LOGIC;
bufo_34_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_34_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_34_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_34_Clk_A : OUT STD_LOGIC;
bufo_34_Rst_A : OUT STD_LOGIC;
bufo_35_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_35_EN_A : OUT STD_LOGIC;
bufo_35_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_35_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_35_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_35_Clk_A : OUT STD_LOGIC;
bufo_35_Rst_A : OUT STD_LOGIC;
bufo_36_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_36_EN_A : OUT STD_LOGIC;
bufo_36_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_36_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_36_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_36_Clk_A : OUT STD_LOGIC;
bufo_36_Rst_A : OUT STD_LOGIC;
bufo_37_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_37_EN_A : OUT STD_LOGIC;
bufo_37_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_37_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_37_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_37_Clk_A : OUT STD_LOGIC;
bufo_37_Rst_A : OUT STD_LOGIC;
bufo_38_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_38_EN_A : OUT STD_LOGIC;
bufo_38_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_38_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_38_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_38_Clk_A : OUT STD_LOGIC;
bufo_38_Rst_A : OUT STD_LOGIC;
bufo_39_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_39_EN_A : OUT STD_LOGIC;
bufo_39_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_39_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_39_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_39_Clk_A : OUT STD_LOGIC;
bufo_39_Rst_A : OUT STD_LOGIC;
bufo_40_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_40_EN_A : OUT STD_LOGIC;
bufo_40_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_40_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_40_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_40_Clk_A : OUT STD_LOGIC;
bufo_40_Rst_A : OUT STD_LOGIC;
bufo_41_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_41_EN_A : OUT STD_LOGIC;
bufo_41_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_41_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_41_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_41_Clk_A : OUT STD_LOGIC;
bufo_41_Rst_A : OUT STD_LOGIC;
bufo_42_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_42_EN_A : OUT STD_LOGIC;
bufo_42_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_42_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_42_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_42_Clk_A : OUT STD_LOGIC;
bufo_42_Rst_A : OUT STD_LOGIC;
bufo_43_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_43_EN_A : OUT STD_LOGIC;
bufo_43_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_43_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_43_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_43_Clk_A : OUT STD_LOGIC;
bufo_43_Rst_A : OUT STD_LOGIC;
bufo_44_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_44_EN_A : OUT STD_LOGIC;
bufo_44_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_44_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_44_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_44_Clk_A : OUT STD_LOGIC;
bufo_44_Rst_A : OUT STD_LOGIC;
bufo_45_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_45_EN_A : OUT STD_LOGIC;
bufo_45_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_45_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_45_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_45_Clk_A : OUT STD_LOGIC;
bufo_45_Rst_A : OUT STD_LOGIC;
bufo_46_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_46_EN_A : OUT STD_LOGIC;
bufo_46_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_46_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_46_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_46_Clk_A : OUT STD_LOGIC;
bufo_46_Rst_A : OUT STD_LOGIC;
bufo_47_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_47_EN_A : OUT STD_LOGIC;
bufo_47_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_47_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_47_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_47_Clk_A : OUT STD_LOGIC;
bufo_47_Rst_A : OUT STD_LOGIC;
bufo_48_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_48_EN_A : OUT STD_LOGIC;
bufo_48_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_48_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_48_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_48_Clk_A : OUT STD_LOGIC;
bufo_48_Rst_A : OUT STD_LOGIC;
bufo_49_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_49_EN_A : OUT STD_LOGIC;
bufo_49_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_49_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_49_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_49_Clk_A : OUT STD_LOGIC;
bufo_49_Rst_A : OUT STD_LOGIC;
bufo_50_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_50_EN_A : OUT STD_LOGIC;
bufo_50_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_50_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_50_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_50_Clk_A : OUT STD_LOGIC;
bufo_50_Rst_A : OUT STD_LOGIC;
bufo_51_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_51_EN_A : OUT STD_LOGIC;
bufo_51_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_51_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_51_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_51_Clk_A : OUT STD_LOGIC;
bufo_51_Rst_A : OUT STD_LOGIC;
bufo_52_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_52_EN_A : OUT STD_LOGIC;
bufo_52_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_52_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_52_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_52_Clk_A : OUT STD_LOGIC;
bufo_52_Rst_A : OUT STD_LOGIC;
bufo_53_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_53_EN_A : OUT STD_LOGIC;
bufo_53_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_53_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_53_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_53_Clk_A : OUT STD_LOGIC;
bufo_53_Rst_A : OUT STD_LOGIC;
bufo_54_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_54_EN_A : OUT STD_LOGIC;
bufo_54_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_54_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_54_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_54_Clk_A : OUT STD_LOGIC;
bufo_54_Rst_A : OUT STD_LOGIC;
bufo_55_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_55_EN_A : OUT STD_LOGIC;
bufo_55_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_55_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_55_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_55_Clk_A : OUT STD_LOGIC;
bufo_55_Rst_A : OUT STD_LOGIC;
bufo_56_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_56_EN_A : OUT STD_LOGIC;
bufo_56_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_56_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_56_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_56_Clk_A : OUT STD_LOGIC;
bufo_56_Rst_A : OUT STD_LOGIC;
bufo_57_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_57_EN_A : OUT STD_LOGIC;
bufo_57_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_57_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_57_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_57_Clk_A : OUT STD_LOGIC;
bufo_57_Rst_A : OUT STD_LOGIC;
bufo_58_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_58_EN_A : OUT STD_LOGIC;
bufo_58_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_58_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_58_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_58_Clk_A : OUT STD_LOGIC;
bufo_58_Rst_A : OUT STD_LOGIC;
bufo_59_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_59_EN_A : OUT STD_LOGIC;
bufo_59_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_59_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_59_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_59_Clk_A : OUT STD_LOGIC;
bufo_59_Rst_A : OUT STD_LOGIC;
bufo_60_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_60_EN_A : OUT STD_LOGIC;
bufo_60_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_60_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_60_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_60_Clk_A : OUT STD_LOGIC;
bufo_60_Rst_A : OUT STD_LOGIC;
bufo_61_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_61_EN_A : OUT STD_LOGIC;
bufo_61_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_61_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_61_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_61_Clk_A : OUT STD_LOGIC;
bufo_61_Rst_A : OUT STD_LOGIC;
bufo_62_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_62_EN_A : OUT STD_LOGIC;
bufo_62_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_62_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_62_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_62_Clk_A : OUT STD_LOGIC;
bufo_62_Rst_A : OUT STD_LOGIC;
bufo_63_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_63_EN_A : OUT STD_LOGIC;
bufo_63_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_63_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_63_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_63_Clk_A : OUT STD_LOGIC;
bufo_63_Rst_A : OUT STD_LOGIC;
bufo_64_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_64_EN_A : OUT STD_LOGIC;
bufo_64_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_64_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_64_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_64_Clk_A : OUT STD_LOGIC;
bufo_64_Rst_A : OUT STD_LOGIC;
bufo_65_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_65_EN_A : OUT STD_LOGIC;
bufo_65_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_65_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_65_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_65_Clk_A : OUT STD_LOGIC;
bufo_65_Rst_A : OUT STD_LOGIC;
bufo_66_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_66_EN_A : OUT STD_LOGIC;
bufo_66_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_66_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_66_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_66_Clk_A : OUT STD_LOGIC;
bufo_66_Rst_A : OUT STD_LOGIC;
bufo_67_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_67_EN_A : OUT STD_LOGIC;
bufo_67_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_67_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_67_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_67_Clk_A : OUT STD_LOGIC;
bufo_67_Rst_A : OUT STD_LOGIC;
bufo_68_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_68_EN_A : OUT STD_LOGIC;
bufo_68_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_68_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_68_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_68_Clk_A : OUT STD_LOGIC;
bufo_68_Rst_A : OUT STD_LOGIC;
bufo_69_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_69_EN_A : OUT STD_LOGIC;
bufo_69_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_69_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_69_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_69_Clk_A : OUT STD_LOGIC;
bufo_69_Rst_A : OUT STD_LOGIC;
bufo_70_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_70_EN_A : OUT STD_LOGIC;
bufo_70_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_70_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_70_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_70_Clk_A : OUT STD_LOGIC;
bufo_70_Rst_A : OUT STD_LOGIC;
bufo_71_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_71_EN_A : OUT STD_LOGIC;
bufo_71_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_71_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_71_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_71_Clk_A : OUT STD_LOGIC;
bufo_71_Rst_A : OUT STD_LOGIC;
bufo_72_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_72_EN_A : OUT STD_LOGIC;
bufo_72_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_72_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_72_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_72_Clk_A : OUT STD_LOGIC;
bufo_72_Rst_A : OUT STD_LOGIC;
bufo_73_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_73_EN_A : OUT STD_LOGIC;
bufo_73_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_73_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_73_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_73_Clk_A : OUT STD_LOGIC;
bufo_73_Rst_A : OUT STD_LOGIC;
bufo_74_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_74_EN_A : OUT STD_LOGIC;
bufo_74_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_74_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_74_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_74_Clk_A : OUT STD_LOGIC;
bufo_74_Rst_A : OUT STD_LOGIC;
bufo_75_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_75_EN_A : OUT STD_LOGIC;
bufo_75_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_75_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_75_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_75_Clk_A : OUT STD_LOGIC;
bufo_75_Rst_A : OUT STD_LOGIC;
bufo_76_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_76_EN_A : OUT STD_LOGIC;
bufo_76_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_76_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_76_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_76_Clk_A : OUT STD_LOGIC;
bufo_76_Rst_A : OUT STD_LOGIC;
bufo_77_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_77_EN_A : OUT STD_LOGIC;
bufo_77_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_77_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_77_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_77_Clk_A : OUT STD_LOGIC;
bufo_77_Rst_A : OUT STD_LOGIC;
bufo_78_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_78_EN_A : OUT STD_LOGIC;
bufo_78_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_78_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_78_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_78_Clk_A : OUT STD_LOGIC;
bufo_78_Rst_A : OUT STD_LOGIC;
bufo_79_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_79_EN_A : OUT STD_LOGIC;
bufo_79_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_79_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_79_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_79_Clk_A : OUT STD_LOGIC;
bufo_79_Rst_A : OUT STD_LOGIC;
bufo_80_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_80_EN_A : OUT STD_LOGIC;
bufo_80_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_80_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_80_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_80_Clk_A : OUT STD_LOGIC;
bufo_80_Rst_A : OUT STD_LOGIC;
bufo_81_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_81_EN_A : OUT STD_LOGIC;
bufo_81_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_81_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_81_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_81_Clk_A : OUT STD_LOGIC;
bufo_81_Rst_A : OUT STD_LOGIC;
bufo_82_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_82_EN_A : OUT STD_LOGIC;
bufo_82_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_82_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_82_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_82_Clk_A : OUT STD_LOGIC;
bufo_82_Rst_A : OUT STD_LOGIC;
bufo_83_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_83_EN_A : OUT STD_LOGIC;
bufo_83_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_83_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_83_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_83_Clk_A : OUT STD_LOGIC;
bufo_83_Rst_A : OUT STD_LOGIC;
bufo_84_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_84_EN_A : OUT STD_LOGIC;
bufo_84_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_84_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_84_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_84_Clk_A : OUT STD_LOGIC;
bufo_84_Rst_A : OUT STD_LOGIC;
bufo_85_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_85_EN_A : OUT STD_LOGIC;
bufo_85_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_85_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_85_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_85_Clk_A : OUT STD_LOGIC;
bufo_85_Rst_A : OUT STD_LOGIC;
bufo_86_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_86_EN_A : OUT STD_LOGIC;
bufo_86_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_86_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_86_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_86_Clk_A : OUT STD_LOGIC;
bufo_86_Rst_A : OUT STD_LOGIC;
bufo_87_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_87_EN_A : OUT STD_LOGIC;
bufo_87_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_87_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_87_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_87_Clk_A : OUT STD_LOGIC;
bufo_87_Rst_A : OUT STD_LOGIC;
bufo_88_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_88_EN_A : OUT STD_LOGIC;
bufo_88_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_88_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_88_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_88_Clk_A : OUT STD_LOGIC;
bufo_88_Rst_A : OUT STD_LOGIC;
bufo_89_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_89_EN_A : OUT STD_LOGIC;
bufo_89_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_89_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_89_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_89_Clk_A : OUT STD_LOGIC;
bufo_89_Rst_A : OUT STD_LOGIC;
bufo_90_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_90_EN_A : OUT STD_LOGIC;
bufo_90_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_90_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_90_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_90_Clk_A : OUT STD_LOGIC;
bufo_90_Rst_A : OUT STD_LOGIC;
bufo_91_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_91_EN_A : OUT STD_LOGIC;
bufo_91_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_91_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_91_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_91_Clk_A : OUT STD_LOGIC;
bufo_91_Rst_A : OUT STD_LOGIC;
bufo_92_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_92_EN_A : OUT STD_LOGIC;
bufo_92_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_92_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_92_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_92_Clk_A : OUT STD_LOGIC;
bufo_92_Rst_A : OUT STD_LOGIC;
bufo_93_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_93_EN_A : OUT STD_LOGIC;
bufo_93_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_93_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_93_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_93_Clk_A : OUT STD_LOGIC;
bufo_93_Rst_A : OUT STD_LOGIC;
bufo_94_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_94_EN_A : OUT STD_LOGIC;
bufo_94_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_94_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_94_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_94_Clk_A : OUT STD_LOGIC;
bufo_94_Rst_A : OUT STD_LOGIC;
bufo_95_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_95_EN_A : OUT STD_LOGIC;
bufo_95_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_95_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_95_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_95_Clk_A : OUT STD_LOGIC;
bufo_95_Rst_A : OUT STD_LOGIC;
bufo_96_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_96_EN_A : OUT STD_LOGIC;
bufo_96_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_96_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_96_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_96_Clk_A : OUT STD_LOGIC;
bufo_96_Rst_A : OUT STD_LOGIC;
bufo_97_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_97_EN_A : OUT STD_LOGIC;
bufo_97_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_97_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_97_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_97_Clk_A : OUT STD_LOGIC;
bufo_97_Rst_A : OUT STD_LOGIC;
bufo_98_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_98_EN_A : OUT STD_LOGIC;
bufo_98_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_98_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_98_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_98_Clk_A : OUT STD_LOGIC;
bufo_98_Rst_A : OUT STD_LOGIC;
bufo_99_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_99_EN_A : OUT STD_LOGIC;
bufo_99_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_99_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_99_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_99_Clk_A : OUT STD_LOGIC;
bufo_99_Rst_A : OUT STD_LOGIC;
bufo_100_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_100_EN_A : OUT STD_LOGIC;
bufo_100_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_100_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_100_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_100_Clk_A : OUT STD_LOGIC;
bufo_100_Rst_A : OUT STD_LOGIC;
bufo_101_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_101_EN_A : OUT STD_LOGIC;
bufo_101_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_101_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_101_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_101_Clk_A : OUT STD_LOGIC;
bufo_101_Rst_A : OUT STD_LOGIC;
bufo_102_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_102_EN_A : OUT STD_LOGIC;
bufo_102_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_102_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_102_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_102_Clk_A : OUT STD_LOGIC;
bufo_102_Rst_A : OUT STD_LOGIC;
bufo_103_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_103_EN_A : OUT STD_LOGIC;
bufo_103_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_103_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_103_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_103_Clk_A : OUT STD_LOGIC;
bufo_103_Rst_A : OUT STD_LOGIC;
bufo_104_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_104_EN_A : OUT STD_LOGIC;
bufo_104_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_104_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_104_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_104_Clk_A : OUT STD_LOGIC;
bufo_104_Rst_A : OUT STD_LOGIC;
bufo_105_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_105_EN_A : OUT STD_LOGIC;
bufo_105_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_105_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_105_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_105_Clk_A : OUT STD_LOGIC;
bufo_105_Rst_A : OUT STD_LOGIC;
bufo_106_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_106_EN_A : OUT STD_LOGIC;
bufo_106_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_106_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_106_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_106_Clk_A : OUT STD_LOGIC;
bufo_106_Rst_A : OUT STD_LOGIC;
bufo_107_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_107_EN_A : OUT STD_LOGIC;
bufo_107_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_107_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_107_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_107_Clk_A : OUT STD_LOGIC;
bufo_107_Rst_A : OUT STD_LOGIC;
bufo_108_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_108_EN_A : OUT STD_LOGIC;
bufo_108_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_108_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_108_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_108_Clk_A : OUT STD_LOGIC;
bufo_108_Rst_A : OUT STD_LOGIC;
bufo_109_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_109_EN_A : OUT STD_LOGIC;
bufo_109_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_109_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_109_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_109_Clk_A : OUT STD_LOGIC;
bufo_109_Rst_A : OUT STD_LOGIC;
bufo_110_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_110_EN_A : OUT STD_LOGIC;
bufo_110_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_110_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_110_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_110_Clk_A : OUT STD_LOGIC;
bufo_110_Rst_A : OUT STD_LOGIC;
bufo_111_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_111_EN_A : OUT STD_LOGIC;
bufo_111_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_111_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_111_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_111_Clk_A : OUT STD_LOGIC;
bufo_111_Rst_A : OUT STD_LOGIC;
bufo_112_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_112_EN_A : OUT STD_LOGIC;
bufo_112_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_112_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_112_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_112_Clk_A : OUT STD_LOGIC;
bufo_112_Rst_A : OUT STD_LOGIC;
bufo_113_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_113_EN_A : OUT STD_LOGIC;
bufo_113_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_113_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_113_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_113_Clk_A : OUT STD_LOGIC;
bufo_113_Rst_A : OUT STD_LOGIC;
bufo_114_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_114_EN_A : OUT STD_LOGIC;
bufo_114_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_114_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_114_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_114_Clk_A : OUT STD_LOGIC;
bufo_114_Rst_A : OUT STD_LOGIC;
bufo_115_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_115_EN_A : OUT STD_LOGIC;
bufo_115_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_115_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_115_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_115_Clk_A : OUT STD_LOGIC;
bufo_115_Rst_A : OUT STD_LOGIC;
bufo_116_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_116_EN_A : OUT STD_LOGIC;
bufo_116_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_116_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_116_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_116_Clk_A : OUT STD_LOGIC;
bufo_116_Rst_A : OUT STD_LOGIC;
bufo_117_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_117_EN_A : OUT STD_LOGIC;
bufo_117_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_117_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_117_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_117_Clk_A : OUT STD_LOGIC;
bufo_117_Rst_A : OUT STD_LOGIC;
bufo_118_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_118_EN_A : OUT STD_LOGIC;
bufo_118_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_118_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_118_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_118_Clk_A : OUT STD_LOGIC;
bufo_118_Rst_A : OUT STD_LOGIC;
bufo_119_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_119_EN_A : OUT STD_LOGIC;
bufo_119_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_119_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_119_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_119_Clk_A : OUT STD_LOGIC;
bufo_119_Rst_A : OUT STD_LOGIC;
bufo_120_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_120_EN_A : OUT STD_LOGIC;
bufo_120_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_120_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_120_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_120_Clk_A : OUT STD_LOGIC;
bufo_120_Rst_A : OUT STD_LOGIC;
bufo_121_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_121_EN_A : OUT STD_LOGIC;
bufo_121_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_121_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_121_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_121_Clk_A : OUT STD_LOGIC;
bufo_121_Rst_A : OUT STD_LOGIC;
bufo_122_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_122_EN_A : OUT STD_LOGIC;
bufo_122_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_122_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_122_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_122_Clk_A : OUT STD_LOGIC;
bufo_122_Rst_A : OUT STD_LOGIC;
bufo_123_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_123_EN_A : OUT STD_LOGIC;
bufo_123_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_123_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_123_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_123_Clk_A : OUT STD_LOGIC;
bufo_123_Rst_A : OUT STD_LOGIC;
bufo_124_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_124_EN_A : OUT STD_LOGIC;
bufo_124_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_124_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_124_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_124_Clk_A : OUT STD_LOGIC;
bufo_124_Rst_A : OUT STD_LOGIC;
bufo_125_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_125_EN_A : OUT STD_LOGIC;
bufo_125_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_125_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_125_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_125_Clk_A : OUT STD_LOGIC;
bufo_125_Rst_A : OUT STD_LOGIC;
bufo_126_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_126_EN_A : OUT STD_LOGIC;
bufo_126_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_126_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_126_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_126_Clk_A : OUT STD_LOGIC;
bufo_126_Rst_A : OUT STD_LOGIC;
bufo_127_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_127_EN_A : OUT STD_LOGIC;
bufo_127_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_127_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_127_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_127_Clk_A : OUT STD_LOGIC;
bufo_127_Rst_A : OUT STD_LOGIC;
bufo_128_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_128_EN_A : OUT STD_LOGIC;
bufo_128_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_128_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_128_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_128_Clk_A : OUT STD_LOGIC;
bufo_128_Rst_A : OUT STD_LOGIC;
bufo_128_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_128_EN_B : OUT STD_LOGIC;
bufo_128_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_128_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_128_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_128_Clk_B : OUT STD_LOGIC;
bufo_128_Rst_B : OUT STD_LOGIC;
bufo_129_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_129_EN_A : OUT STD_LOGIC;
bufo_129_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_129_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_129_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_129_Clk_A : OUT STD_LOGIC;
bufo_129_Rst_A : OUT STD_LOGIC;
bufo_129_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_129_EN_B : OUT STD_LOGIC;
bufo_129_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_129_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_129_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_129_Clk_B : OUT STD_LOGIC;
bufo_129_Rst_B : OUT STD_LOGIC;
bufo_130_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_130_EN_A : OUT STD_LOGIC;
bufo_130_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_130_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_130_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_130_Clk_A : OUT STD_LOGIC;
bufo_130_Rst_A : OUT STD_LOGIC;
bufo_130_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_130_EN_B : OUT STD_LOGIC;
bufo_130_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_130_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_130_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_130_Clk_B : OUT STD_LOGIC;
bufo_130_Rst_B : OUT STD_LOGIC;
bufo_131_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_131_EN_A : OUT STD_LOGIC;
bufo_131_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_131_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_131_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_131_Clk_A : OUT STD_LOGIC;
bufo_131_Rst_A : OUT STD_LOGIC;
bufo_131_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_131_EN_B : OUT STD_LOGIC;
bufo_131_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_131_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_131_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_131_Clk_B : OUT STD_LOGIC;
bufo_131_Rst_B : OUT STD_LOGIC;
bufo_132_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_132_EN_A : OUT STD_LOGIC;
bufo_132_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_132_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_132_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_132_Clk_A : OUT STD_LOGIC;
bufo_132_Rst_A : OUT STD_LOGIC;
bufo_132_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_132_EN_B : OUT STD_LOGIC;
bufo_132_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_132_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_132_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_132_Clk_B : OUT STD_LOGIC;
bufo_132_Rst_B : OUT STD_LOGIC;
bufo_133_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_133_EN_A : OUT STD_LOGIC;
bufo_133_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_133_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_133_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_133_Clk_A : OUT STD_LOGIC;
bufo_133_Rst_A : OUT STD_LOGIC;
bufo_133_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_133_EN_B : OUT STD_LOGIC;
bufo_133_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_133_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_133_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_133_Clk_B : OUT STD_LOGIC;
bufo_133_Rst_B : OUT STD_LOGIC;
bufo_134_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_134_EN_A : OUT STD_LOGIC;
bufo_134_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_134_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_134_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_134_Clk_A : OUT STD_LOGIC;
bufo_134_Rst_A : OUT STD_LOGIC;
bufo_134_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_134_EN_B : OUT STD_LOGIC;
bufo_134_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_134_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_134_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_134_Clk_B : OUT STD_LOGIC;
bufo_134_Rst_B : OUT STD_LOGIC;
bufo_135_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_135_EN_A : OUT STD_LOGIC;
bufo_135_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_135_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_135_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_135_Clk_A : OUT STD_LOGIC;
bufo_135_Rst_A : OUT STD_LOGIC;
bufo_135_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_135_EN_B : OUT STD_LOGIC;
bufo_135_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_135_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_135_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_135_Clk_B : OUT STD_LOGIC;
bufo_135_Rst_B : OUT STD_LOGIC;
bufo_136_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_136_EN_A : OUT STD_LOGIC;
bufo_136_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_136_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_136_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_136_Clk_A : OUT STD_LOGIC;
bufo_136_Rst_A : OUT STD_LOGIC;
bufo_136_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_136_EN_B : OUT STD_LOGIC;
bufo_136_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_136_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_136_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_136_Clk_B : OUT STD_LOGIC;
bufo_136_Rst_B : OUT STD_LOGIC;
bufo_137_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_137_EN_A : OUT STD_LOGIC;
bufo_137_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_137_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_137_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_137_Clk_A : OUT STD_LOGIC;
bufo_137_Rst_A : OUT STD_LOGIC;
bufo_137_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_137_EN_B : OUT STD_LOGIC;
bufo_137_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_137_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_137_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_137_Clk_B : OUT STD_LOGIC;
bufo_137_Rst_B : OUT STD_LOGIC;
bufo_138_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_138_EN_A : OUT STD_LOGIC;
bufo_138_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_138_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_138_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_138_Clk_A : OUT STD_LOGIC;
bufo_138_Rst_A : OUT STD_LOGIC;
bufo_138_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_138_EN_B : OUT STD_LOGIC;
bufo_138_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_138_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_138_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_138_Clk_B : OUT STD_LOGIC;
bufo_138_Rst_B : OUT STD_LOGIC;
bufo_139_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_139_EN_A : OUT STD_LOGIC;
bufo_139_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_139_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_139_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_139_Clk_A : OUT STD_LOGIC;
bufo_139_Rst_A : OUT STD_LOGIC;
bufo_139_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_139_EN_B : OUT STD_LOGIC;
bufo_139_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_139_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_139_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_139_Clk_B : OUT STD_LOGIC;
bufo_139_Rst_B : OUT STD_LOGIC;
bufo_140_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_140_EN_A : OUT STD_LOGIC;
bufo_140_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_140_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_140_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_140_Clk_A : OUT STD_LOGIC;
bufo_140_Rst_A : OUT STD_LOGIC;
bufo_140_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_140_EN_B : OUT STD_LOGIC;
bufo_140_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_140_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_140_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_140_Clk_B : OUT STD_LOGIC;
bufo_140_Rst_B : OUT STD_LOGIC;
bufo_141_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_141_EN_A : OUT STD_LOGIC;
bufo_141_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_141_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_141_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_141_Clk_A : OUT STD_LOGIC;
bufo_141_Rst_A : OUT STD_LOGIC;
bufo_141_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_141_EN_B : OUT STD_LOGIC;
bufo_141_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_141_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_141_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_141_Clk_B : OUT STD_LOGIC;
bufo_141_Rst_B : OUT STD_LOGIC;
bufo_142_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_142_EN_A : OUT STD_LOGIC;
bufo_142_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_142_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_142_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_142_Clk_A : OUT STD_LOGIC;
bufo_142_Rst_A : OUT STD_LOGIC;
bufo_142_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_142_EN_B : OUT STD_LOGIC;
bufo_142_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_142_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_142_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_142_Clk_B : OUT STD_LOGIC;
bufo_142_Rst_B : OUT STD_LOGIC;
bufo_143_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_143_EN_A : OUT STD_LOGIC;
bufo_143_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_143_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_143_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_143_Clk_A : OUT STD_LOGIC;
bufo_143_Rst_A : OUT STD_LOGIC;
bufo_143_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_143_EN_B : OUT STD_LOGIC;
bufo_143_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_143_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_143_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_143_Clk_B : OUT STD_LOGIC;
bufo_143_Rst_B : OUT STD_LOGIC;
bufo_144_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_144_EN_A : OUT STD_LOGIC;
bufo_144_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_144_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_144_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_144_Clk_A : OUT STD_LOGIC;
bufo_144_Rst_A : OUT STD_LOGIC;
bufo_144_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_144_EN_B : OUT STD_LOGIC;
bufo_144_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_144_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_144_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_144_Clk_B : OUT STD_LOGIC;
bufo_144_Rst_B : OUT STD_LOGIC;
bufo_145_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_145_EN_A : OUT STD_LOGIC;
bufo_145_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_145_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_145_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_145_Clk_A : OUT STD_LOGIC;
bufo_145_Rst_A : OUT STD_LOGIC;
bufo_145_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_145_EN_B : OUT STD_LOGIC;
bufo_145_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_145_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_145_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_145_Clk_B : OUT STD_LOGIC;
bufo_145_Rst_B : OUT STD_LOGIC;
bufo_146_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_146_EN_A : OUT STD_LOGIC;
bufo_146_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_146_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_146_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_146_Clk_A : OUT STD_LOGIC;
bufo_146_Rst_A : OUT STD_LOGIC;
bufo_146_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_146_EN_B : OUT STD_LOGIC;
bufo_146_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_146_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_146_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_146_Clk_B : OUT STD_LOGIC;
bufo_146_Rst_B : OUT STD_LOGIC;
bufo_147_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_147_EN_A : OUT STD_LOGIC;
bufo_147_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_147_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_147_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_147_Clk_A : OUT STD_LOGIC;
bufo_147_Rst_A : OUT STD_LOGIC;
bufo_147_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_147_EN_B : OUT STD_LOGIC;
bufo_147_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_147_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_147_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_147_Clk_B : OUT STD_LOGIC;
bufo_147_Rst_B : OUT STD_LOGIC;
bufo_148_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_148_EN_A : OUT STD_LOGIC;
bufo_148_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_148_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_148_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_148_Clk_A : OUT STD_LOGIC;
bufo_148_Rst_A : OUT STD_LOGIC;
bufo_148_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_148_EN_B : OUT STD_LOGIC;
bufo_148_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_148_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_148_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_148_Clk_B : OUT STD_LOGIC;
bufo_148_Rst_B : OUT STD_LOGIC;
bufo_149_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_149_EN_A : OUT STD_LOGIC;
bufo_149_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_149_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_149_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_149_Clk_A : OUT STD_LOGIC;
bufo_149_Rst_A : OUT STD_LOGIC;
bufo_149_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_149_EN_B : OUT STD_LOGIC;
bufo_149_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_149_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_149_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_149_Clk_B : OUT STD_LOGIC;
bufo_149_Rst_B : OUT STD_LOGIC;
bufo_150_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_150_EN_A : OUT STD_LOGIC;
bufo_150_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_150_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_150_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_150_Clk_A : OUT STD_LOGIC;
bufo_150_Rst_A : OUT STD_LOGIC;
bufo_150_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_150_EN_B : OUT STD_LOGIC;
bufo_150_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_150_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_150_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_150_Clk_B : OUT STD_LOGIC;
bufo_150_Rst_B : OUT STD_LOGIC;
bufo_151_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_151_EN_A : OUT STD_LOGIC;
bufo_151_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_151_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_151_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_151_Clk_A : OUT STD_LOGIC;
bufo_151_Rst_A : OUT STD_LOGIC;
bufo_151_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_151_EN_B : OUT STD_LOGIC;
bufo_151_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_151_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_151_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_151_Clk_B : OUT STD_LOGIC;
bufo_151_Rst_B : OUT STD_LOGIC;
bufo_152_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_152_EN_A : OUT STD_LOGIC;
bufo_152_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_152_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_152_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_152_Clk_A : OUT STD_LOGIC;
bufo_152_Rst_A : OUT STD_LOGIC;
bufo_152_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_152_EN_B : OUT STD_LOGIC;
bufo_152_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_152_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_152_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_152_Clk_B : OUT STD_LOGIC;
bufo_152_Rst_B : OUT STD_LOGIC;
bufo_153_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_153_EN_A : OUT STD_LOGIC;
bufo_153_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_153_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_153_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_153_Clk_A : OUT STD_LOGIC;
bufo_153_Rst_A : OUT STD_LOGIC;
bufo_153_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_153_EN_B : OUT STD_LOGIC;
bufo_153_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_153_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_153_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_153_Clk_B : OUT STD_LOGIC;
bufo_153_Rst_B : OUT STD_LOGIC;
bufo_154_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_154_EN_A : OUT STD_LOGIC;
bufo_154_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_154_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_154_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_154_Clk_A : OUT STD_LOGIC;
bufo_154_Rst_A : OUT STD_LOGIC;
bufo_154_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_154_EN_B : OUT STD_LOGIC;
bufo_154_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_154_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_154_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_154_Clk_B : OUT STD_LOGIC;
bufo_154_Rst_B : OUT STD_LOGIC;
bufo_155_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_155_EN_A : OUT STD_LOGIC;
bufo_155_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_155_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_155_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_155_Clk_A : OUT STD_LOGIC;
bufo_155_Rst_A : OUT STD_LOGIC;
bufo_155_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_155_EN_B : OUT STD_LOGIC;
bufo_155_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_155_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_155_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_155_Clk_B : OUT STD_LOGIC;
bufo_155_Rst_B : OUT STD_LOGIC;
bufo_156_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_156_EN_A : OUT STD_LOGIC;
bufo_156_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_156_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_156_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_156_Clk_A : OUT STD_LOGIC;
bufo_156_Rst_A : OUT STD_LOGIC;
bufo_156_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_156_EN_B : OUT STD_LOGIC;
bufo_156_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_156_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_156_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_156_Clk_B : OUT STD_LOGIC;
bufo_156_Rst_B : OUT STD_LOGIC;
bufo_157_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_157_EN_A : OUT STD_LOGIC;
bufo_157_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_157_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_157_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_157_Clk_A : OUT STD_LOGIC;
bufo_157_Rst_A : OUT STD_LOGIC;
bufo_157_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_157_EN_B : OUT STD_LOGIC;
bufo_157_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_157_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_157_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_157_Clk_B : OUT STD_LOGIC;
bufo_157_Rst_B : OUT STD_LOGIC;
bufo_158_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_158_EN_A : OUT STD_LOGIC;
bufo_158_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_158_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_158_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_158_Clk_A : OUT STD_LOGIC;
bufo_158_Rst_A : OUT STD_LOGIC;
bufo_158_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_158_EN_B : OUT STD_LOGIC;
bufo_158_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_158_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_158_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_158_Clk_B : OUT STD_LOGIC;
bufo_158_Rst_B : OUT STD_LOGIC;
bufo_159_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_159_EN_A : OUT STD_LOGIC;
bufo_159_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_159_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_159_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_159_Clk_A : OUT STD_LOGIC;
bufo_159_Rst_A : OUT STD_LOGIC;
bufo_159_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_159_EN_B : OUT STD_LOGIC;
bufo_159_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_159_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_159_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_159_Clk_B : OUT STD_LOGIC;
bufo_159_Rst_B : OUT STD_LOGIC;
bufo_160_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_160_EN_A : OUT STD_LOGIC;
bufo_160_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_160_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_160_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_160_Clk_A : OUT STD_LOGIC;
bufo_160_Rst_A : OUT STD_LOGIC;
bufo_160_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_160_EN_B : OUT STD_LOGIC;
bufo_160_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_160_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_160_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_160_Clk_B : OUT STD_LOGIC;
bufo_160_Rst_B : OUT STD_LOGIC;
bufo_161_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_161_EN_A : OUT STD_LOGIC;
bufo_161_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_161_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_161_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_161_Clk_A : OUT STD_LOGIC;
bufo_161_Rst_A : OUT STD_LOGIC;
bufo_161_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_161_EN_B : OUT STD_LOGIC;
bufo_161_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_161_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_161_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_161_Clk_B : OUT STD_LOGIC;
bufo_161_Rst_B : OUT STD_LOGIC;
bufo_162_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_162_EN_A : OUT STD_LOGIC;
bufo_162_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_162_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_162_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_162_Clk_A : OUT STD_LOGIC;
bufo_162_Rst_A : OUT STD_LOGIC;
bufo_162_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_162_EN_B : OUT STD_LOGIC;
bufo_162_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_162_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_162_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_162_Clk_B : OUT STD_LOGIC;
bufo_162_Rst_B : OUT STD_LOGIC;
bufo_163_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_163_EN_A : OUT STD_LOGIC;
bufo_163_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_163_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_163_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_163_Clk_A : OUT STD_LOGIC;
bufo_163_Rst_A : OUT STD_LOGIC;
bufo_163_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_163_EN_B : OUT STD_LOGIC;
bufo_163_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_163_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_163_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_163_Clk_B : OUT STD_LOGIC;
bufo_163_Rst_B : OUT STD_LOGIC;
bufo_164_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_164_EN_A : OUT STD_LOGIC;
bufo_164_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_164_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_164_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_164_Clk_A : OUT STD_LOGIC;
bufo_164_Rst_A : OUT STD_LOGIC;
bufo_164_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_164_EN_B : OUT STD_LOGIC;
bufo_164_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_164_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_164_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_164_Clk_B : OUT STD_LOGIC;
bufo_164_Rst_B : OUT STD_LOGIC;
bufo_165_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_165_EN_A : OUT STD_LOGIC;
bufo_165_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_165_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_165_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_165_Clk_A : OUT STD_LOGIC;
bufo_165_Rst_A : OUT STD_LOGIC;
bufo_165_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_165_EN_B : OUT STD_LOGIC;
bufo_165_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_165_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_165_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_165_Clk_B : OUT STD_LOGIC;
bufo_165_Rst_B : OUT STD_LOGIC;
bufo_166_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_166_EN_A : OUT STD_LOGIC;
bufo_166_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_166_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_166_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_166_Clk_A : OUT STD_LOGIC;
bufo_166_Rst_A : OUT STD_LOGIC;
bufo_166_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_166_EN_B : OUT STD_LOGIC;
bufo_166_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_166_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_166_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_166_Clk_B : OUT STD_LOGIC;
bufo_166_Rst_B : OUT STD_LOGIC;
bufo_167_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_167_EN_A : OUT STD_LOGIC;
bufo_167_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_167_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_167_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_167_Clk_A : OUT STD_LOGIC;
bufo_167_Rst_A : OUT STD_LOGIC;
bufo_167_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_167_EN_B : OUT STD_LOGIC;
bufo_167_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_167_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_167_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_167_Clk_B : OUT STD_LOGIC;
bufo_167_Rst_B : OUT STD_LOGIC;
bufo_168_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_168_EN_A : OUT STD_LOGIC;
bufo_168_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_168_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_168_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_168_Clk_A : OUT STD_LOGIC;
bufo_168_Rst_A : OUT STD_LOGIC;
bufo_168_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_168_EN_B : OUT STD_LOGIC;
bufo_168_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_168_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_168_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_168_Clk_B : OUT STD_LOGIC;
bufo_168_Rst_B : OUT STD_LOGIC;
bufo_169_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_169_EN_A : OUT STD_LOGIC;
bufo_169_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_169_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_169_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_169_Clk_A : OUT STD_LOGIC;
bufo_169_Rst_A : OUT STD_LOGIC;
bufo_169_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_169_EN_B : OUT STD_LOGIC;
bufo_169_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_169_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_169_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_169_Clk_B : OUT STD_LOGIC;
bufo_169_Rst_B : OUT STD_LOGIC;
bufo_170_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_170_EN_A : OUT STD_LOGIC;
bufo_170_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_170_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_170_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_170_Clk_A : OUT STD_LOGIC;
bufo_170_Rst_A : OUT STD_LOGIC;
bufo_170_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_170_EN_B : OUT STD_LOGIC;
bufo_170_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_170_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_170_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_170_Clk_B : OUT STD_LOGIC;
bufo_170_Rst_B : OUT STD_LOGIC;
bufo_171_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_171_EN_A : OUT STD_LOGIC;
bufo_171_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_171_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_171_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_171_Clk_A : OUT STD_LOGIC;
bufo_171_Rst_A : OUT STD_LOGIC;
bufo_171_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_171_EN_B : OUT STD_LOGIC;
bufo_171_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_171_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_171_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_171_Clk_B : OUT STD_LOGIC;
bufo_171_Rst_B : OUT STD_LOGIC;
bufo_172_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_172_EN_A : OUT STD_LOGIC;
bufo_172_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_172_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_172_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_172_Clk_A : OUT STD_LOGIC;
bufo_172_Rst_A : OUT STD_LOGIC;
bufo_172_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_172_EN_B : OUT STD_LOGIC;
bufo_172_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_172_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_172_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_172_Clk_B : OUT STD_LOGIC;
bufo_172_Rst_B : OUT STD_LOGIC;
bufo_173_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_173_EN_A : OUT STD_LOGIC;
bufo_173_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_173_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_173_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_173_Clk_A : OUT STD_LOGIC;
bufo_173_Rst_A : OUT STD_LOGIC;
bufo_173_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_173_EN_B : OUT STD_LOGIC;
bufo_173_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_173_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_173_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_173_Clk_B : OUT STD_LOGIC;
bufo_173_Rst_B : OUT STD_LOGIC;
bufo_174_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_174_EN_A : OUT STD_LOGIC;
bufo_174_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_174_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_174_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_174_Clk_A : OUT STD_LOGIC;
bufo_174_Rst_A : OUT STD_LOGIC;
bufo_174_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_174_EN_B : OUT STD_LOGIC;
bufo_174_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_174_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_174_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_174_Clk_B : OUT STD_LOGIC;
bufo_174_Rst_B : OUT STD_LOGIC;
bufo_175_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_175_EN_A : OUT STD_LOGIC;
bufo_175_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_175_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_175_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_175_Clk_A : OUT STD_LOGIC;
bufo_175_Rst_A : OUT STD_LOGIC;
bufo_175_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_175_EN_B : OUT STD_LOGIC;
bufo_175_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_175_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_175_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_175_Clk_B : OUT STD_LOGIC;
bufo_175_Rst_B : OUT STD_LOGIC;
bufo_176_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_176_EN_A : OUT STD_LOGIC;
bufo_176_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_176_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_176_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_176_Clk_A : OUT STD_LOGIC;
bufo_176_Rst_A : OUT STD_LOGIC;
bufo_176_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_176_EN_B : OUT STD_LOGIC;
bufo_176_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_176_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_176_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_176_Clk_B : OUT STD_LOGIC;
bufo_176_Rst_B : OUT STD_LOGIC;
bufo_177_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_177_EN_A : OUT STD_LOGIC;
bufo_177_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_177_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_177_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_177_Clk_A : OUT STD_LOGIC;
bufo_177_Rst_A : OUT STD_LOGIC;
bufo_177_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_177_EN_B : OUT STD_LOGIC;
bufo_177_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_177_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_177_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_177_Clk_B : OUT STD_LOGIC;
bufo_177_Rst_B : OUT STD_LOGIC;
bufo_178_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_178_EN_A : OUT STD_LOGIC;
bufo_178_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_178_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_178_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_178_Clk_A : OUT STD_LOGIC;
bufo_178_Rst_A : OUT STD_LOGIC;
bufo_178_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_178_EN_B : OUT STD_LOGIC;
bufo_178_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_178_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_178_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_178_Clk_B : OUT STD_LOGIC;
bufo_178_Rst_B : OUT STD_LOGIC;
bufo_179_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_179_EN_A : OUT STD_LOGIC;
bufo_179_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_179_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_179_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_179_Clk_A : OUT STD_LOGIC;
bufo_179_Rst_A : OUT STD_LOGIC;
bufo_179_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_179_EN_B : OUT STD_LOGIC;
bufo_179_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_179_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_179_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_179_Clk_B : OUT STD_LOGIC;
bufo_179_Rst_B : OUT STD_LOGIC;
bufo_180_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_180_EN_A : OUT STD_LOGIC;
bufo_180_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_180_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_180_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_180_Clk_A : OUT STD_LOGIC;
bufo_180_Rst_A : OUT STD_LOGIC;
bufo_180_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_180_EN_B : OUT STD_LOGIC;
bufo_180_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_180_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_180_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_180_Clk_B : OUT STD_LOGIC;
bufo_180_Rst_B : OUT STD_LOGIC;
bufo_181_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_181_EN_A : OUT STD_LOGIC;
bufo_181_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_181_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_181_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_181_Clk_A : OUT STD_LOGIC;
bufo_181_Rst_A : OUT STD_LOGIC;
bufo_181_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_181_EN_B : OUT STD_LOGIC;
bufo_181_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_181_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_181_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_181_Clk_B : OUT STD_LOGIC;
bufo_181_Rst_B : OUT STD_LOGIC;
bufo_182_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_182_EN_A : OUT STD_LOGIC;
bufo_182_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_182_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_182_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_182_Clk_A : OUT STD_LOGIC;
bufo_182_Rst_A : OUT STD_LOGIC;
bufo_182_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_182_EN_B : OUT STD_LOGIC;
bufo_182_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_182_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_182_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_182_Clk_B : OUT STD_LOGIC;
bufo_182_Rst_B : OUT STD_LOGIC;
bufo_183_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_183_EN_A : OUT STD_LOGIC;
bufo_183_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_183_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_183_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_183_Clk_A : OUT STD_LOGIC;
bufo_183_Rst_A : OUT STD_LOGIC;
bufo_183_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_183_EN_B : OUT STD_LOGIC;
bufo_183_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_183_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_183_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_183_Clk_B : OUT STD_LOGIC;
bufo_183_Rst_B : OUT STD_LOGIC;
bufo_184_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_184_EN_A : OUT STD_LOGIC;
bufo_184_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_184_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_184_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_184_Clk_A : OUT STD_LOGIC;
bufo_184_Rst_A : OUT STD_LOGIC;
bufo_184_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_184_EN_B : OUT STD_LOGIC;
bufo_184_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_184_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_184_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_184_Clk_B : OUT STD_LOGIC;
bufo_184_Rst_B : OUT STD_LOGIC;
bufo_185_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_185_EN_A : OUT STD_LOGIC;
bufo_185_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_185_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_185_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_185_Clk_A : OUT STD_LOGIC;
bufo_185_Rst_A : OUT STD_LOGIC;
bufo_185_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_185_EN_B : OUT STD_LOGIC;
bufo_185_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_185_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_185_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_185_Clk_B : OUT STD_LOGIC;
bufo_185_Rst_B : OUT STD_LOGIC;
bufo_186_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_186_EN_A : OUT STD_LOGIC;
bufo_186_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_186_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_186_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_186_Clk_A : OUT STD_LOGIC;
bufo_186_Rst_A : OUT STD_LOGIC;
bufo_186_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_186_EN_B : OUT STD_LOGIC;
bufo_186_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_186_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_186_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_186_Clk_B : OUT STD_LOGIC;
bufo_186_Rst_B : OUT STD_LOGIC;
bufo_187_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_187_EN_A : OUT STD_LOGIC;
bufo_187_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_187_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_187_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_187_Clk_A : OUT STD_LOGIC;
bufo_187_Rst_A : OUT STD_LOGIC;
bufo_187_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_187_EN_B : OUT STD_LOGIC;
bufo_187_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_187_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_187_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_187_Clk_B : OUT STD_LOGIC;
bufo_187_Rst_B : OUT STD_LOGIC;
bufo_188_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_188_EN_A : OUT STD_LOGIC;
bufo_188_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_188_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_188_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_188_Clk_A : OUT STD_LOGIC;
bufo_188_Rst_A : OUT STD_LOGIC;
bufo_188_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_188_EN_B : OUT STD_LOGIC;
bufo_188_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_188_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_188_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_188_Clk_B : OUT STD_LOGIC;
bufo_188_Rst_B : OUT STD_LOGIC;
bufo_189_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_189_EN_A : OUT STD_LOGIC;
bufo_189_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_189_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_189_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_189_Clk_A : OUT STD_LOGIC;
bufo_189_Rst_A : OUT STD_LOGIC;
bufo_189_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_189_EN_B : OUT STD_LOGIC;
bufo_189_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_189_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_189_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_189_Clk_B : OUT STD_LOGIC;
bufo_189_Rst_B : OUT STD_LOGIC;
bufo_190_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_190_EN_A : OUT STD_LOGIC;
bufo_190_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_190_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_190_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_190_Clk_A : OUT STD_LOGIC;
bufo_190_Rst_A : OUT STD_LOGIC;
bufo_190_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_190_EN_B : OUT STD_LOGIC;
bufo_190_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_190_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_190_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_190_Clk_B : OUT STD_LOGIC;
bufo_190_Rst_B : OUT STD_LOGIC;
bufo_191_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_191_EN_A : OUT STD_LOGIC;
bufo_191_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_191_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_191_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_191_Clk_A : OUT STD_LOGIC;
bufo_191_Rst_A : OUT STD_LOGIC;
bufo_191_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_191_EN_B : OUT STD_LOGIC;
bufo_191_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_191_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_191_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_191_Clk_B : OUT STD_LOGIC;
bufo_191_Rst_B : OUT STD_LOGIC;
bufo_192_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_192_EN_A : OUT STD_LOGIC;
bufo_192_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_192_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_192_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_192_Clk_A : OUT STD_LOGIC;
bufo_192_Rst_A : OUT STD_LOGIC;
bufo_192_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_192_EN_B : OUT STD_LOGIC;
bufo_192_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_192_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_192_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_192_Clk_B : OUT STD_LOGIC;
bufo_192_Rst_B : OUT STD_LOGIC;
bufo_193_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_193_EN_A : OUT STD_LOGIC;
bufo_193_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_193_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_193_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_193_Clk_A : OUT STD_LOGIC;
bufo_193_Rst_A : OUT STD_LOGIC;
bufo_193_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_193_EN_B : OUT STD_LOGIC;
bufo_193_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_193_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_193_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_193_Clk_B : OUT STD_LOGIC;
bufo_193_Rst_B : OUT STD_LOGIC;
bufo_194_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_194_EN_A : OUT STD_LOGIC;
bufo_194_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_194_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_194_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_194_Clk_A : OUT STD_LOGIC;
bufo_194_Rst_A : OUT STD_LOGIC;
bufo_194_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_194_EN_B : OUT STD_LOGIC;
bufo_194_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_194_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_194_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_194_Clk_B : OUT STD_LOGIC;
bufo_194_Rst_B : OUT STD_LOGIC;
bufo_195_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_195_EN_A : OUT STD_LOGIC;
bufo_195_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_195_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_195_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_195_Clk_A : OUT STD_LOGIC;
bufo_195_Rst_A : OUT STD_LOGIC;
bufo_195_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_195_EN_B : OUT STD_LOGIC;
bufo_195_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_195_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_195_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_195_Clk_B : OUT STD_LOGIC;
bufo_195_Rst_B : OUT STD_LOGIC;
bufo_196_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_196_EN_A : OUT STD_LOGIC;
bufo_196_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_196_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_196_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_196_Clk_A : OUT STD_LOGIC;
bufo_196_Rst_A : OUT STD_LOGIC;
bufo_196_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_196_EN_B : OUT STD_LOGIC;
bufo_196_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_196_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_196_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_196_Clk_B : OUT STD_LOGIC;
bufo_196_Rst_B : OUT STD_LOGIC;
bufo_197_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_197_EN_A : OUT STD_LOGIC;
bufo_197_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_197_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_197_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_197_Clk_A : OUT STD_LOGIC;
bufo_197_Rst_A : OUT STD_LOGIC;
bufo_197_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_197_EN_B : OUT STD_LOGIC;
bufo_197_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_197_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_197_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_197_Clk_B : OUT STD_LOGIC;
bufo_197_Rst_B : OUT STD_LOGIC;
bufo_198_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_198_EN_A : OUT STD_LOGIC;
bufo_198_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_198_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_198_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_198_Clk_A : OUT STD_LOGIC;
bufo_198_Rst_A : OUT STD_LOGIC;
bufo_198_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_198_EN_B : OUT STD_LOGIC;
bufo_198_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_198_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_198_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_198_Clk_B : OUT STD_LOGIC;
bufo_198_Rst_B : OUT STD_LOGIC;
bufo_199_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_199_EN_A : OUT STD_LOGIC;
bufo_199_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_199_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_199_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_199_Clk_A : OUT STD_LOGIC;
bufo_199_Rst_A : OUT STD_LOGIC;
bufo_199_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_199_EN_B : OUT STD_LOGIC;
bufo_199_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_199_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_199_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_199_Clk_B : OUT STD_LOGIC;
bufo_199_Rst_B : OUT STD_LOGIC );
end;
architecture behav of convolve_kernel is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"convolve_kernel,hls_ip_2017_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=5.633800,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=14,HLS_SYN_FF=5893,HLS_SYN_LUT=3947}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000001000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000010000000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000100000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000001000000000";
constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000010000000000";
constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000100000000000";
constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000001000000000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000010000000000000";
constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000100000000000000";
constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000001000000000000000";
constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000010000000000000000";
constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000100000000000000000";
constant ap_ST_fsm_state19 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000001000000000000000000";
constant ap_ST_fsm_state20 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000010000000000000000000";
constant ap_ST_fsm_state21 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000100000000000000000000";
constant ap_ST_fsm_state22 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000001000000000000000000000";
constant ap_ST_fsm_state23 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000010000000000000000000000";
constant ap_ST_fsm_state24 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000100000000000000000000000";
constant ap_ST_fsm_state25 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000001000000000000000000000000";
constant ap_ST_fsm_state26 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000010000000000000000000000000";
constant ap_ST_fsm_state27 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000100000000000000000000000000";
constant ap_ST_fsm_state28 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000001000000000000000000000000000";
constant ap_ST_fsm_state29 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000010000000000000000000000000000";
constant ap_ST_fsm_state30 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000100000000000000000000000000000";
constant ap_ST_fsm_state31 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000001000000000000000000000000000000";
constant ap_ST_fsm_state32 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000010000000000000000000000000000000";
constant ap_ST_fsm_state33 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000100000000000000000000000000000000";
constant ap_ST_fsm_state34 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000001000000000000000000000000000000000";
constant ap_ST_fsm_state35 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000010000000000000000000000000000000000";
constant ap_ST_fsm_state36 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000100000000000000000000000000000000000";
constant ap_ST_fsm_state37 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000001000000000000000000000000000000000000";
constant ap_ST_fsm_state38 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000010000000000000000000000000000000000000";
constant ap_ST_fsm_state39 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000100000000000000000000000000000000000000";
constant ap_ST_fsm_state40 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000001000000000000000000000000000000000000000";
constant ap_ST_fsm_state41 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000010000000000000000000000000000000000000000";
constant ap_ST_fsm_state42 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000100000000000000000000000000000000000000000";
constant ap_ST_fsm_state43 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000001000000000000000000000000000000000000000000";
constant ap_ST_fsm_state44 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000010000000000000000000000000000000000000000000";
constant ap_ST_fsm_state45 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000100000000000000000000000000000000000000000000";
constant ap_ST_fsm_state46 : STD_LOGIC_VECTOR (55 downto 0) := "00000000001000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state47 : STD_LOGIC_VECTOR (55 downto 0) := "00000000010000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state48 : STD_LOGIC_VECTOR (55 downto 0) := "00000000100000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state49 : STD_LOGIC_VECTOR (55 downto 0) := "00000001000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state50 : STD_LOGIC_VECTOR (55 downto 0) := "00000010000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state51 : STD_LOGIC_VECTOR (55 downto 0) := "00000100000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state52 : STD_LOGIC_VECTOR (55 downto 0) := "00001000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state53 : STD_LOGIC_VECTOR (55 downto 0) := "00010000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state54 : STD_LOGIC_VECTOR (55 downto 0) := "00100000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state55 : STD_LOGIC_VECTOR (55 downto 0) := "01000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state56 : STD_LOGIC_VECTOR (55 downto 0) := "10000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_22 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100010";
constant ap_const_lv32_2B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101011";
constant ap_const_lv32_36 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110110";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_2C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101100";
constant ap_const_lv7_7E : STD_LOGIC_VECTOR (6 downto 0) := "1111110";
constant ap_const_lv7_7D : STD_LOGIC_VECTOR (6 downto 0) := "1111101";
constant ap_const_lv7_7C : STD_LOGIC_VECTOR (6 downto 0) := "1111100";
constant ap_const_lv7_7B : STD_LOGIC_VECTOR (6 downto 0) := "1111011";
constant ap_const_lv7_7A : STD_LOGIC_VECTOR (6 downto 0) := "1111010";
constant ap_const_lv7_79 : STD_LOGIC_VECTOR (6 downto 0) := "1111001";
constant ap_const_lv7_78 : STD_LOGIC_VECTOR (6 downto 0) := "1111000";
constant ap_const_lv7_77 : STD_LOGIC_VECTOR (6 downto 0) := "1110111";
constant ap_const_lv7_76 : STD_LOGIC_VECTOR (6 downto 0) := "1110110";
constant ap_const_lv7_75 : STD_LOGIC_VECTOR (6 downto 0) := "1110101";
constant ap_const_lv7_74 : STD_LOGIC_VECTOR (6 downto 0) := "1110100";
constant ap_const_lv7_73 : STD_LOGIC_VECTOR (6 downto 0) := "1110011";
constant ap_const_lv7_72 : STD_LOGIC_VECTOR (6 downto 0) := "1110010";
constant ap_const_lv7_71 : STD_LOGIC_VECTOR (6 downto 0) := "1110001";
constant ap_const_lv7_70 : STD_LOGIC_VECTOR (6 downto 0) := "1110000";
constant ap_const_lv7_6F : STD_LOGIC_VECTOR (6 downto 0) := "1101111";
constant ap_const_lv7_6E : STD_LOGIC_VECTOR (6 downto 0) := "1101110";
constant ap_const_lv7_6D : STD_LOGIC_VECTOR (6 downto 0) := "1101101";
constant ap_const_lv7_6C : STD_LOGIC_VECTOR (6 downto 0) := "1101100";
constant ap_const_lv7_6B : STD_LOGIC_VECTOR (6 downto 0) := "1101011";
constant ap_const_lv7_6A : STD_LOGIC_VECTOR (6 downto 0) := "1101010";
constant ap_const_lv7_69 : STD_LOGIC_VECTOR (6 downto 0) := "1101001";
constant ap_const_lv7_68 : STD_LOGIC_VECTOR (6 downto 0) := "1101000";
constant ap_const_lv7_67 : STD_LOGIC_VECTOR (6 downto 0) := "1100111";
constant ap_const_lv7_66 : STD_LOGIC_VECTOR (6 downto 0) := "1100110";
constant ap_const_lv7_65 : STD_LOGIC_VECTOR (6 downto 0) := "1100101";
constant ap_const_lv7_64 : STD_LOGIC_VECTOR (6 downto 0) := "1100100";
constant ap_const_lv7_63 : STD_LOGIC_VECTOR (6 downto 0) := "1100011";
constant ap_const_lv7_62 : STD_LOGIC_VECTOR (6 downto 0) := "1100010";
constant ap_const_lv7_61 : STD_LOGIC_VECTOR (6 downto 0) := "1100001";
constant ap_const_lv7_60 : STD_LOGIC_VECTOR (6 downto 0) := "1100000";
constant ap_const_lv7_5F : STD_LOGIC_VECTOR (6 downto 0) := "1011111";
constant ap_const_lv7_5E : STD_LOGIC_VECTOR (6 downto 0) := "1011110";
constant ap_const_lv7_5D : STD_LOGIC_VECTOR (6 downto 0) := "1011101";
constant ap_const_lv7_5C : STD_LOGIC_VECTOR (6 downto 0) := "1011100";
constant ap_const_lv7_5B : STD_LOGIC_VECTOR (6 downto 0) := "1011011";
constant ap_const_lv7_5A : STD_LOGIC_VECTOR (6 downto 0) := "1011010";
constant ap_const_lv7_59 : STD_LOGIC_VECTOR (6 downto 0) := "1011001";
constant ap_const_lv7_58 : STD_LOGIC_VECTOR (6 downto 0) := "1011000";
constant ap_const_lv7_57 : STD_LOGIC_VECTOR (6 downto 0) := "1010111";
constant ap_const_lv7_56 : STD_LOGIC_VECTOR (6 downto 0) := "1010110";
constant ap_const_lv7_55 : STD_LOGIC_VECTOR (6 downto 0) := "1010101";
constant ap_const_lv7_54 : STD_LOGIC_VECTOR (6 downto 0) := "1010100";
constant ap_const_lv7_53 : STD_LOGIC_VECTOR (6 downto 0) := "1010011";
constant ap_const_lv7_52 : STD_LOGIC_VECTOR (6 downto 0) := "1010010";
constant ap_const_lv7_51 : STD_LOGIC_VECTOR (6 downto 0) := "1010001";
constant ap_const_lv7_50 : STD_LOGIC_VECTOR (6 downto 0) := "1010000";
constant ap_const_lv7_4F : STD_LOGIC_VECTOR (6 downto 0) := "1001111";
constant ap_const_lv7_4E : STD_LOGIC_VECTOR (6 downto 0) := "1001110";
constant ap_const_lv7_4D : STD_LOGIC_VECTOR (6 downto 0) := "1001101";
constant ap_const_lv7_4C : STD_LOGIC_VECTOR (6 downto 0) := "1001100";
constant ap_const_lv7_4B : STD_LOGIC_VECTOR (6 downto 0) := "1001011";
constant ap_const_lv7_4A : STD_LOGIC_VECTOR (6 downto 0) := "1001010";
constant ap_const_lv7_49 : STD_LOGIC_VECTOR (6 downto 0) := "1001001";
constant ap_const_lv7_48 : STD_LOGIC_VECTOR (6 downto 0) := "1001000";
constant ap_const_lv7_47 : STD_LOGIC_VECTOR (6 downto 0) := "1000111";
constant ap_const_lv7_46 : STD_LOGIC_VECTOR (6 downto 0) := "1000110";
constant ap_const_lv7_45 : STD_LOGIC_VECTOR (6 downto 0) := "1000101";
constant ap_const_lv7_44 : STD_LOGIC_VECTOR (6 downto 0) := "1000100";
constant ap_const_lv7_43 : STD_LOGIC_VECTOR (6 downto 0) := "1000011";
constant ap_const_lv7_42 : STD_LOGIC_VECTOR (6 downto 0) := "1000010";
constant ap_const_lv7_41 : STD_LOGIC_VECTOR (6 downto 0) := "1000001";
constant ap_const_lv7_40 : STD_LOGIC_VECTOR (6 downto 0) := "1000000";
constant ap_const_lv7_3F : STD_LOGIC_VECTOR (6 downto 0) := "0111111";
constant ap_const_lv7_3E : STD_LOGIC_VECTOR (6 downto 0) := "0111110";
constant ap_const_lv7_3D : STD_LOGIC_VECTOR (6 downto 0) := "0111101";
constant ap_const_lv7_3C : STD_LOGIC_VECTOR (6 downto 0) := "0111100";
constant ap_const_lv7_3B : STD_LOGIC_VECTOR (6 downto 0) := "0111011";
constant ap_const_lv7_3A : STD_LOGIC_VECTOR (6 downto 0) := "0111010";
constant ap_const_lv7_39 : STD_LOGIC_VECTOR (6 downto 0) := "0111001";
constant ap_const_lv7_38 : STD_LOGIC_VECTOR (6 downto 0) := "0111000";
constant ap_const_lv7_37 : STD_LOGIC_VECTOR (6 downto 0) := "0110111";
constant ap_const_lv7_36 : STD_LOGIC_VECTOR (6 downto 0) := "0110110";
constant ap_const_lv7_35 : STD_LOGIC_VECTOR (6 downto 0) := "0110101";
constant ap_const_lv7_34 : STD_LOGIC_VECTOR (6 downto 0) := "0110100";
constant ap_const_lv7_33 : STD_LOGIC_VECTOR (6 downto 0) := "0110011";
constant ap_const_lv7_32 : STD_LOGIC_VECTOR (6 downto 0) := "0110010";
constant ap_const_lv7_31 : STD_LOGIC_VECTOR (6 downto 0) := "0110001";
constant ap_const_lv7_30 : STD_LOGIC_VECTOR (6 downto 0) := "0110000";
constant ap_const_lv7_2F : STD_LOGIC_VECTOR (6 downto 0) := "0101111";
constant ap_const_lv7_2E : STD_LOGIC_VECTOR (6 downto 0) := "0101110";
constant ap_const_lv7_2D : STD_LOGIC_VECTOR (6 downto 0) := "0101101";
constant ap_const_lv7_2C : STD_LOGIC_VECTOR (6 downto 0) := "0101100";
constant ap_const_lv7_2B : STD_LOGIC_VECTOR (6 downto 0) := "0101011";
constant ap_const_lv7_2A : STD_LOGIC_VECTOR (6 downto 0) := "0101010";
constant ap_const_lv7_29 : STD_LOGIC_VECTOR (6 downto 0) := "0101001";
constant ap_const_lv7_28 : STD_LOGIC_VECTOR (6 downto 0) := "0101000";
constant ap_const_lv7_27 : STD_LOGIC_VECTOR (6 downto 0) := "0100111";
constant ap_const_lv7_26 : STD_LOGIC_VECTOR (6 downto 0) := "0100110";
constant ap_const_lv7_25 : STD_LOGIC_VECTOR (6 downto 0) := "0100101";
constant ap_const_lv7_24 : STD_LOGIC_VECTOR (6 downto 0) := "0100100";
constant ap_const_lv7_23 : STD_LOGIC_VECTOR (6 downto 0) := "0100011";
constant ap_const_lv7_22 : STD_LOGIC_VECTOR (6 downto 0) := "0100010";
constant ap_const_lv7_21 : STD_LOGIC_VECTOR (6 downto 0) := "0100001";
constant ap_const_lv7_20 : STD_LOGIC_VECTOR (6 downto 0) := "0100000";
constant ap_const_lv7_1F : STD_LOGIC_VECTOR (6 downto 0) := "0011111";
constant ap_const_lv7_1E : STD_LOGIC_VECTOR (6 downto 0) := "0011110";
constant ap_const_lv7_1D : STD_LOGIC_VECTOR (6 downto 0) := "0011101";
constant ap_const_lv7_1C : STD_LOGIC_VECTOR (6 downto 0) := "0011100";
constant ap_const_lv7_1B : STD_LOGIC_VECTOR (6 downto 0) := "0011011";
constant ap_const_lv7_1A : STD_LOGIC_VECTOR (6 downto 0) := "0011010";
constant ap_const_lv7_19 : STD_LOGIC_VECTOR (6 downto 0) := "0011001";
constant ap_const_lv7_18 : STD_LOGIC_VECTOR (6 downto 0) := "0011000";
constant ap_const_lv7_17 : STD_LOGIC_VECTOR (6 downto 0) := "0010111";
constant ap_const_lv7_16 : STD_LOGIC_VECTOR (6 downto 0) := "0010110";
constant ap_const_lv7_15 : STD_LOGIC_VECTOR (6 downto 0) := "0010101";
constant ap_const_lv7_14 : STD_LOGIC_VECTOR (6 downto 0) := "0010100";
constant ap_const_lv7_13 : STD_LOGIC_VECTOR (6 downto 0) := "0010011";
constant ap_const_lv7_12 : STD_LOGIC_VECTOR (6 downto 0) := "0010010";
constant ap_const_lv7_11 : STD_LOGIC_VECTOR (6 downto 0) := "0010001";
constant ap_const_lv7_10 : STD_LOGIC_VECTOR (6 downto 0) := "0010000";
constant ap_const_lv7_F : STD_LOGIC_VECTOR (6 downto 0) := "0001111";
constant ap_const_lv7_E : STD_LOGIC_VECTOR (6 downto 0) := "0001110";
constant ap_const_lv7_D : STD_LOGIC_VECTOR (6 downto 0) := "0001101";
constant ap_const_lv7_C : STD_LOGIC_VECTOR (6 downto 0) := "0001100";
constant ap_const_lv7_B : STD_LOGIC_VECTOR (6 downto 0) := "0001011";
constant ap_const_lv7_A : STD_LOGIC_VECTOR (6 downto 0) := "0001010";
constant ap_const_lv7_9 : STD_LOGIC_VECTOR (6 downto 0) := "0001001";
constant ap_const_lv7_8 : STD_LOGIC_VECTOR (6 downto 0) := "0001000";
constant ap_const_lv7_7 : STD_LOGIC_VECTOR (6 downto 0) := "0000111";
constant ap_const_lv7_6 : STD_LOGIC_VECTOR (6 downto 0) := "0000110";
constant ap_const_lv7_5 : STD_LOGIC_VECTOR (6 downto 0) := "0000101";
constant ap_const_lv7_4 : STD_LOGIC_VECTOR (6 downto 0) := "0000100";
constant ap_const_lv7_3 : STD_LOGIC_VECTOR (6 downto 0) := "0000011";
constant ap_const_lv7_2 : STD_LOGIC_VECTOR (6 downto 0) := "0000010";
constant ap_const_lv7_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_const_lv7_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
constant ap_const_lv7_7F : STD_LOGIC_VECTOR (6 downto 0) := "1111111";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111";
constant ap_const_lv32_2D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101101";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011";
constant ap_const_lv32_2E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101110";
constant ap_const_lv64_19 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011001";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
constant ap_const_lv32_40 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000000";
constant ap_const_lv32_5F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011111";
constant ap_const_lv32_60 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100000";
constant ap_const_lv32_7F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111111";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv128_lc_1 : STD_LOGIC_VECTOR (127 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal grp_fu_2558_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_2580 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state17 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state17 : signal is "none";
signal ap_CS_fsm_state26 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state26 : signal is "none";
signal ap_CS_fsm_state35 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state35 : signal is "none";
signal ap_CS_fsm_state44 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state44 : signal is "none";
signal ap_CS_fsm_state55 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state55 : signal is "none";
signal next_mul_fu_2714_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal next_mul_reg_3471 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal tmp_fu_2720_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_reg_3481 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal tmp_1_fu_2724_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_reg_3486 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_reg_3491 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_reg_3496 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_reg_3501 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_reg_3506 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_13_reg_3511 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_15_reg_3516 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal grp_fu_2564_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_s_reg_3561 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
signal grp_fu_2568_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_1_reg_3566 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_2572_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_2_reg_3571 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_2576_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_3_reg_3576 : STD_LOGIC_VECTOR (31 downto 0);
signal to_b_V_fu_2820_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal to_b_V_reg_3581 : STD_LOGIC_VECTOR (6 downto 0);
signal bufo_126_load_reg_3586 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state45 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state45 : signal is "none";
signal p_s_reg_2284 : STD_LOGIC_VECTOR (6 downto 0);
signal bufo_125_load_reg_3591 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_124_load_reg_3596 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_123_load_reg_3601 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_122_load_reg_3606 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_121_load_reg_3611 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_120_load_reg_3616 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_119_load_reg_3621 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_118_load_reg_3626 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_117_load_reg_3631 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_116_load_reg_3636 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_115_load_reg_3641 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_114_load_reg_3646 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_113_load_reg_3651 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_112_load_reg_3656 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_111_load_reg_3661 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_110_load_reg_3666 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_109_load_reg_3671 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_108_load_reg_3676 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_107_load_reg_3681 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_106_load_reg_3686 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_105_load_reg_3691 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_104_load_reg_3696 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_103_load_reg_3701 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_102_load_reg_3706 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_101_load_reg_3711 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_100_load_reg_3716 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_99_load_reg_3721 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_98_load_reg_3726 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_97_load_reg_3731 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_96_load_reg_3736 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_95_load_reg_3741 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_94_load_reg_3746 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_93_load_reg_3751 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_92_load_reg_3756 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_91_load_reg_3761 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_90_load_reg_3766 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_89_load_reg_3771 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_88_load_reg_3776 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_87_load_reg_3781 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_86_load_reg_3786 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_85_load_reg_3791 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_84_load_reg_3796 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_83_load_reg_3801 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_82_load_reg_3806 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_81_load_reg_3811 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_80_load_reg_3816 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_79_load_reg_3821 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_78_load_reg_3826 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_77_load_reg_3831 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_76_load_reg_3836 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_75_load_reg_3841 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_74_load_reg_3846 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_73_load_reg_3851 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_72_load_reg_3856 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_71_load_reg_3861 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_70_load_reg_3866 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_69_load_reg_3871 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_68_load_reg_3876 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_67_load_reg_3881 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_66_load_reg_3886 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_65_load_reg_3891 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_64_load_reg_3896 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_63_load_reg_3901 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_62_load_reg_3906 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_61_load_reg_3911 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_60_load_reg_3916 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_59_load_reg_3921 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_58_load_reg_3926 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_57_load_reg_3931 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_56_load_reg_3936 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_55_load_reg_3941 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_54_load_reg_3946 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_53_load_reg_3951 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_52_load_reg_3956 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_51_load_reg_3961 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_50_load_reg_3966 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_49_load_reg_3971 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_48_load_reg_3976 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_47_load_reg_3981 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_46_load_reg_3986 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_45_load_reg_3991 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_44_load_reg_3996 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_43_load_reg_4001 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_42_load_reg_4006 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_41_load_reg_4011 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_40_load_reg_4016 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_39_load_reg_4021 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_38_load_reg_4026 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_37_load_reg_4031 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_36_load_reg_4036 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_35_load_reg_4041 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_34_load_reg_4046 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_33_load_reg_4051 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_32_load_reg_4056 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_31_load_reg_4061 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_30_load_reg_4066 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_29_load_reg_4071 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_28_load_reg_4076 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_27_load_reg_4081 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_26_load_reg_4086 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_25_load_reg_4091 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_24_load_reg_4096 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_23_load_reg_4101 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_22_load_reg_4106 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_21_load_reg_4111 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_20_load_reg_4116 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_19_load_reg_4121 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_18_load_reg_4126 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_17_load_reg_4131 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_16_load_reg_4136 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_15_load_reg_4141 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_14_load_reg_4146 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_13_load_reg_4151 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_12_load_reg_4156 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_11_load_reg_4161 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_10_load_reg_4166 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_9_load_reg_4171 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_8_load_reg_4176 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_7_load_reg_4181 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_6_load_reg_4186 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_5_load_reg_4191 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_4_load_reg_4196 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_3_load_reg_4201 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_2_load_reg_4206 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_1_load_reg_4211 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_0_load_reg_4216 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_127_load_reg_4221 : STD_LOGIC_VECTOR (31 downto 0);
signal phi_mul_reg_2272 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state56 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state56 : signal is "none";
signal bufo_load_phi_reg_2296 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state46 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state46 : signal is "none";
signal bufw_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_126_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_125_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_124_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_123_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_122_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_121_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_120_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_119_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_118_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_117_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_116_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_115_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_114_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_113_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_112_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_111_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_110_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_109_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_108_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_107_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_106_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_105_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_104_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_103_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_102_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_101_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_100_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_99_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_98_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_97_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_96_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_95_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_94_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_93_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_92_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_91_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_90_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_89_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_88_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_87_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_86_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_85_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_84_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_83_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_82_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_81_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_80_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_79_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_78_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_77_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_76_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_75_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_74_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_73_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_72_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_71_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_70_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_69_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_68_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_67_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_66_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_65_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_64_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_63_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_62_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_61_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_60_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_59_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_58_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_57_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_56_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_55_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_54_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_53_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_52_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_51_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_50_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_49_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_48_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_47_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_46_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_45_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_44_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_43_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_42_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_41_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_40_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_39_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_38_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_37_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_36_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_35_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_34_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_33_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_32_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_31_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_30_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_29_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_28_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_27_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_26_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_25_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_24_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_23_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_22_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_21_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_20_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_19_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_18_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_17_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_16_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_15_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_14_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_13_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_12_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_11_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_10_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_9_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_8_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_7_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_6_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_5_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_4_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_3_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_2_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_1_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_0_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_127_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_2558_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_2558_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
signal ap_CS_fsm_state18 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state18 : signal is "none";
signal ap_CS_fsm_state27 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state27 : signal is "none";
signal ap_CS_fsm_state36 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state36 : signal is "none";
signal ap_CS_fsm_state47 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state47 : signal is "none";
signal grp_fu_2564_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_2564_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_2568_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_2568_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_2572_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_2572_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_2576_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_2576_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (55 downto 0);
component convolve_kernel_fbkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component convolve_kernel_fcud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
convolve_kernel_fbkb_U1 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_2558_p0,
din1 => grp_fu_2558_p1,
ce => ap_const_logic_1,
dout => grp_fu_2558_p2);
convolve_kernel_fcud_U2 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_2564_p0,
din1 => grp_fu_2564_p1,
ce => ap_const_logic_1,
dout => grp_fu_2564_p2);
convolve_kernel_fcud_U3 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_2568_p0,
din1 => grp_fu_2568_p1,
ce => ap_const_logic_1,
dout => grp_fu_2568_p2);
convolve_kernel_fcud_U4 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_2572_p0,
din1 => grp_fu_2572_p1,
ce => ap_const_logic_1,
dout => grp_fu_2572_p2);
convolve_kernel_fcud_U5 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_2576_p0,
din1 => grp_fu_2576_p1,
ce => ap_const_logic_1,
dout => grp_fu_2576_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
bufo_load_phi_reg_2296_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state46)) then
if ((p_s_reg_2284 = ap_const_lv7_7F)) then
bufo_load_phi_reg_2296 <= bufo_127_load_reg_4221;
elsif ((p_s_reg_2284 = ap_const_lv7_7E)) then
bufo_load_phi_reg_2296 <= bufo_126_load_reg_3586;
elsif ((p_s_reg_2284 = ap_const_lv7_7D)) then
bufo_load_phi_reg_2296 <= bufo_125_load_reg_3591;
elsif ((p_s_reg_2284 = ap_const_lv7_7C)) then
bufo_load_phi_reg_2296 <= bufo_124_load_reg_3596;
elsif ((p_s_reg_2284 = ap_const_lv7_7B)) then
bufo_load_phi_reg_2296 <= bufo_123_load_reg_3601;
elsif ((p_s_reg_2284 = ap_const_lv7_7A)) then
bufo_load_phi_reg_2296 <= bufo_122_load_reg_3606;
elsif ((p_s_reg_2284 = ap_const_lv7_79)) then
bufo_load_phi_reg_2296 <= bufo_121_load_reg_3611;
elsif ((p_s_reg_2284 = ap_const_lv7_78)) then
bufo_load_phi_reg_2296 <= bufo_120_load_reg_3616;
elsif ((p_s_reg_2284 = ap_const_lv7_77)) then
bufo_load_phi_reg_2296 <= bufo_119_load_reg_3621;
elsif ((p_s_reg_2284 = ap_const_lv7_76)) then
bufo_load_phi_reg_2296 <= bufo_118_load_reg_3626;
elsif ((p_s_reg_2284 = ap_const_lv7_75)) then
bufo_load_phi_reg_2296 <= bufo_117_load_reg_3631;
elsif ((p_s_reg_2284 = ap_const_lv7_74)) then
bufo_load_phi_reg_2296 <= bufo_116_load_reg_3636;
elsif ((p_s_reg_2284 = ap_const_lv7_73)) then
bufo_load_phi_reg_2296 <= bufo_115_load_reg_3641;
elsif ((p_s_reg_2284 = ap_const_lv7_72)) then
bufo_load_phi_reg_2296 <= bufo_114_load_reg_3646;
elsif ((p_s_reg_2284 = ap_const_lv7_71)) then
bufo_load_phi_reg_2296 <= bufo_113_load_reg_3651;
elsif ((p_s_reg_2284 = ap_const_lv7_70)) then
bufo_load_phi_reg_2296 <= bufo_112_load_reg_3656;
elsif ((p_s_reg_2284 = ap_const_lv7_6F)) then
bufo_load_phi_reg_2296 <= bufo_111_load_reg_3661;
elsif ((p_s_reg_2284 = ap_const_lv7_6E)) then
bufo_load_phi_reg_2296 <= bufo_110_load_reg_3666;
elsif ((p_s_reg_2284 = ap_const_lv7_6D)) then
bufo_load_phi_reg_2296 <= bufo_109_load_reg_3671;
elsif ((p_s_reg_2284 = ap_const_lv7_6C)) then
bufo_load_phi_reg_2296 <= bufo_108_load_reg_3676;
elsif ((p_s_reg_2284 = ap_const_lv7_6B)) then
bufo_load_phi_reg_2296 <= bufo_107_load_reg_3681;
elsif ((p_s_reg_2284 = ap_const_lv7_6A)) then
bufo_load_phi_reg_2296 <= bufo_106_load_reg_3686;
elsif ((p_s_reg_2284 = ap_const_lv7_69)) then
bufo_load_phi_reg_2296 <= bufo_105_load_reg_3691;
elsif ((p_s_reg_2284 = ap_const_lv7_68)) then
bufo_load_phi_reg_2296 <= bufo_104_load_reg_3696;
elsif ((p_s_reg_2284 = ap_const_lv7_67)) then
bufo_load_phi_reg_2296 <= bufo_103_load_reg_3701;
elsif ((p_s_reg_2284 = ap_const_lv7_66)) then
bufo_load_phi_reg_2296 <= bufo_102_load_reg_3706;
elsif ((p_s_reg_2284 = ap_const_lv7_65)) then
bufo_load_phi_reg_2296 <= bufo_101_load_reg_3711;
elsif ((p_s_reg_2284 = ap_const_lv7_64)) then
bufo_load_phi_reg_2296 <= bufo_100_load_reg_3716;
elsif ((p_s_reg_2284 = ap_const_lv7_63)) then
bufo_load_phi_reg_2296 <= bufo_99_load_reg_3721;
elsif ((p_s_reg_2284 = ap_const_lv7_62)) then
bufo_load_phi_reg_2296 <= bufo_98_load_reg_3726;
elsif ((p_s_reg_2284 = ap_const_lv7_61)) then
bufo_load_phi_reg_2296 <= bufo_97_load_reg_3731;
elsif ((p_s_reg_2284 = ap_const_lv7_60)) then
bufo_load_phi_reg_2296 <= bufo_96_load_reg_3736;
elsif ((p_s_reg_2284 = ap_const_lv7_5F)) then
bufo_load_phi_reg_2296 <= bufo_95_load_reg_3741;
elsif ((p_s_reg_2284 = ap_const_lv7_5E)) then
bufo_load_phi_reg_2296 <= bufo_94_load_reg_3746;
elsif ((p_s_reg_2284 = ap_const_lv7_5D)) then
bufo_load_phi_reg_2296 <= bufo_93_load_reg_3751;
elsif ((p_s_reg_2284 = ap_const_lv7_5C)) then
bufo_load_phi_reg_2296 <= bufo_92_load_reg_3756;
elsif ((p_s_reg_2284 = ap_const_lv7_5B)) then
bufo_load_phi_reg_2296 <= bufo_91_load_reg_3761;
elsif ((p_s_reg_2284 = ap_const_lv7_5A)) then
bufo_load_phi_reg_2296 <= bufo_90_load_reg_3766;
elsif ((p_s_reg_2284 = ap_const_lv7_59)) then
bufo_load_phi_reg_2296 <= bufo_89_load_reg_3771;
elsif ((p_s_reg_2284 = ap_const_lv7_58)) then
bufo_load_phi_reg_2296 <= bufo_88_load_reg_3776;
elsif ((p_s_reg_2284 = ap_const_lv7_57)) then
bufo_load_phi_reg_2296 <= bufo_87_load_reg_3781;
elsif ((p_s_reg_2284 = ap_const_lv7_56)) then
bufo_load_phi_reg_2296 <= bufo_86_load_reg_3786;
elsif ((p_s_reg_2284 = ap_const_lv7_55)) then
bufo_load_phi_reg_2296 <= bufo_85_load_reg_3791;
elsif ((p_s_reg_2284 = ap_const_lv7_54)) then
bufo_load_phi_reg_2296 <= bufo_84_load_reg_3796;
elsif ((p_s_reg_2284 = ap_const_lv7_53)) then
bufo_load_phi_reg_2296 <= bufo_83_load_reg_3801;
elsif ((p_s_reg_2284 = ap_const_lv7_52)) then
bufo_load_phi_reg_2296 <= bufo_82_load_reg_3806;
elsif ((p_s_reg_2284 = ap_const_lv7_51)) then
bufo_load_phi_reg_2296 <= bufo_81_load_reg_3811;
elsif ((p_s_reg_2284 = ap_const_lv7_50)) then
bufo_load_phi_reg_2296 <= bufo_80_load_reg_3816;
elsif ((p_s_reg_2284 = ap_const_lv7_4F)) then
bufo_load_phi_reg_2296 <= bufo_79_load_reg_3821;
elsif ((p_s_reg_2284 = ap_const_lv7_4E)) then
bufo_load_phi_reg_2296 <= bufo_78_load_reg_3826;
elsif ((p_s_reg_2284 = ap_const_lv7_4D)) then
bufo_load_phi_reg_2296 <= bufo_77_load_reg_3831;
elsif ((p_s_reg_2284 = ap_const_lv7_4C)) then
bufo_load_phi_reg_2296 <= bufo_76_load_reg_3836;
elsif ((p_s_reg_2284 = ap_const_lv7_4B)) then
bufo_load_phi_reg_2296 <= bufo_75_load_reg_3841;
elsif ((p_s_reg_2284 = ap_const_lv7_4A)) then
bufo_load_phi_reg_2296 <= bufo_74_load_reg_3846;
elsif ((p_s_reg_2284 = ap_const_lv7_49)) then
bufo_load_phi_reg_2296 <= bufo_73_load_reg_3851;
elsif ((p_s_reg_2284 = ap_const_lv7_48)) then
bufo_load_phi_reg_2296 <= bufo_72_load_reg_3856;
elsif ((p_s_reg_2284 = ap_const_lv7_47)) then
bufo_load_phi_reg_2296 <= bufo_71_load_reg_3861;
elsif ((p_s_reg_2284 = ap_const_lv7_46)) then
bufo_load_phi_reg_2296 <= bufo_70_load_reg_3866;
elsif ((p_s_reg_2284 = ap_const_lv7_45)) then
bufo_load_phi_reg_2296 <= bufo_69_load_reg_3871;
elsif ((p_s_reg_2284 = ap_const_lv7_44)) then
bufo_load_phi_reg_2296 <= bufo_68_load_reg_3876;
elsif ((p_s_reg_2284 = ap_const_lv7_43)) then
bufo_load_phi_reg_2296 <= bufo_67_load_reg_3881;
elsif ((p_s_reg_2284 = ap_const_lv7_42)) then
bufo_load_phi_reg_2296 <= bufo_66_load_reg_3886;
elsif ((p_s_reg_2284 = ap_const_lv7_41)) then
bufo_load_phi_reg_2296 <= bufo_65_load_reg_3891;
elsif ((p_s_reg_2284 = ap_const_lv7_40)) then
bufo_load_phi_reg_2296 <= bufo_64_load_reg_3896;
elsif ((p_s_reg_2284 = ap_const_lv7_3F)) then
bufo_load_phi_reg_2296 <= bufo_63_load_reg_3901;
elsif ((p_s_reg_2284 = ap_const_lv7_3E)) then
bufo_load_phi_reg_2296 <= bufo_62_load_reg_3906;
elsif ((p_s_reg_2284 = ap_const_lv7_3D)) then
bufo_load_phi_reg_2296 <= bufo_61_load_reg_3911;
elsif ((p_s_reg_2284 = ap_const_lv7_3C)) then
bufo_load_phi_reg_2296 <= bufo_60_load_reg_3916;
elsif ((p_s_reg_2284 = ap_const_lv7_3B)) then
bufo_load_phi_reg_2296 <= bufo_59_load_reg_3921;
elsif ((p_s_reg_2284 = ap_const_lv7_3A)) then
bufo_load_phi_reg_2296 <= bufo_58_load_reg_3926;
elsif ((p_s_reg_2284 = ap_const_lv7_39)) then
bufo_load_phi_reg_2296 <= bufo_57_load_reg_3931;
elsif ((p_s_reg_2284 = ap_const_lv7_38)) then
bufo_load_phi_reg_2296 <= bufo_56_load_reg_3936;
elsif ((p_s_reg_2284 = ap_const_lv7_37)) then
bufo_load_phi_reg_2296 <= bufo_55_load_reg_3941;
elsif ((p_s_reg_2284 = ap_const_lv7_36)) then
bufo_load_phi_reg_2296 <= bufo_54_load_reg_3946;
elsif ((p_s_reg_2284 = ap_const_lv7_35)) then
bufo_load_phi_reg_2296 <= bufo_53_load_reg_3951;
elsif ((p_s_reg_2284 = ap_const_lv7_34)) then
bufo_load_phi_reg_2296 <= bufo_52_load_reg_3956;
elsif ((p_s_reg_2284 = ap_const_lv7_33)) then
bufo_load_phi_reg_2296 <= bufo_51_load_reg_3961;
elsif ((p_s_reg_2284 = ap_const_lv7_32)) then
bufo_load_phi_reg_2296 <= bufo_50_load_reg_3966;
elsif ((p_s_reg_2284 = ap_const_lv7_31)) then
bufo_load_phi_reg_2296 <= bufo_49_load_reg_3971;
elsif ((p_s_reg_2284 = ap_const_lv7_30)) then
bufo_load_phi_reg_2296 <= bufo_48_load_reg_3976;
elsif ((p_s_reg_2284 = ap_const_lv7_2F)) then
bufo_load_phi_reg_2296 <= bufo_47_load_reg_3981;
elsif ((p_s_reg_2284 = ap_const_lv7_2E)) then
bufo_load_phi_reg_2296 <= bufo_46_load_reg_3986;
elsif ((p_s_reg_2284 = ap_const_lv7_2D)) then
bufo_load_phi_reg_2296 <= bufo_45_load_reg_3991;
elsif ((p_s_reg_2284 = ap_const_lv7_2C)) then
bufo_load_phi_reg_2296 <= bufo_44_load_reg_3996;
elsif ((p_s_reg_2284 = ap_const_lv7_2B)) then
bufo_load_phi_reg_2296 <= bufo_43_load_reg_4001;
elsif ((p_s_reg_2284 = ap_const_lv7_2A)) then
bufo_load_phi_reg_2296 <= bufo_42_load_reg_4006;
elsif ((p_s_reg_2284 = ap_const_lv7_29)) then
bufo_load_phi_reg_2296 <= bufo_41_load_reg_4011;
elsif ((p_s_reg_2284 = ap_const_lv7_28)) then
bufo_load_phi_reg_2296 <= bufo_40_load_reg_4016;
elsif ((p_s_reg_2284 = ap_const_lv7_27)) then
bufo_load_phi_reg_2296 <= bufo_39_load_reg_4021;
elsif ((p_s_reg_2284 = ap_const_lv7_26)) then
bufo_load_phi_reg_2296 <= bufo_38_load_reg_4026;
elsif ((p_s_reg_2284 = ap_const_lv7_25)) then
bufo_load_phi_reg_2296 <= bufo_37_load_reg_4031;
elsif ((p_s_reg_2284 = ap_const_lv7_24)) then
bufo_load_phi_reg_2296 <= bufo_36_load_reg_4036;
elsif ((p_s_reg_2284 = ap_const_lv7_23)) then
bufo_load_phi_reg_2296 <= bufo_35_load_reg_4041;
elsif ((p_s_reg_2284 = ap_const_lv7_22)) then
bufo_load_phi_reg_2296 <= bufo_34_load_reg_4046;
elsif ((p_s_reg_2284 = ap_const_lv7_21)) then
bufo_load_phi_reg_2296 <= bufo_33_load_reg_4051;
elsif ((p_s_reg_2284 = ap_const_lv7_20)) then
bufo_load_phi_reg_2296 <= bufo_32_load_reg_4056;
elsif ((p_s_reg_2284 = ap_const_lv7_1F)) then
bufo_load_phi_reg_2296 <= bufo_31_load_reg_4061;
elsif ((p_s_reg_2284 = ap_const_lv7_1E)) then
bufo_load_phi_reg_2296 <= bufo_30_load_reg_4066;
elsif ((p_s_reg_2284 = ap_const_lv7_1D)) then
bufo_load_phi_reg_2296 <= bufo_29_load_reg_4071;
elsif ((p_s_reg_2284 = ap_const_lv7_1C)) then
bufo_load_phi_reg_2296 <= bufo_28_load_reg_4076;
elsif ((p_s_reg_2284 = ap_const_lv7_1B)) then
bufo_load_phi_reg_2296 <= bufo_27_load_reg_4081;
elsif ((p_s_reg_2284 = ap_const_lv7_1A)) then
bufo_load_phi_reg_2296 <= bufo_26_load_reg_4086;
elsif ((p_s_reg_2284 = ap_const_lv7_19)) then
bufo_load_phi_reg_2296 <= bufo_25_load_reg_4091;
elsif ((p_s_reg_2284 = ap_const_lv7_18)) then
bufo_load_phi_reg_2296 <= bufo_24_load_reg_4096;
elsif ((p_s_reg_2284 = ap_const_lv7_17)) then
bufo_load_phi_reg_2296 <= bufo_23_load_reg_4101;
elsif ((p_s_reg_2284 = ap_const_lv7_16)) then
bufo_load_phi_reg_2296 <= bufo_22_load_reg_4106;
elsif ((p_s_reg_2284 = ap_const_lv7_15)) then
bufo_load_phi_reg_2296 <= bufo_21_load_reg_4111;
elsif ((p_s_reg_2284 = ap_const_lv7_14)) then
bufo_load_phi_reg_2296 <= bufo_20_load_reg_4116;
elsif ((p_s_reg_2284 = ap_const_lv7_13)) then
bufo_load_phi_reg_2296 <= bufo_19_load_reg_4121;
elsif ((p_s_reg_2284 = ap_const_lv7_12)) then
bufo_load_phi_reg_2296 <= bufo_18_load_reg_4126;
elsif ((p_s_reg_2284 = ap_const_lv7_11)) then
bufo_load_phi_reg_2296 <= bufo_17_load_reg_4131;
elsif ((p_s_reg_2284 = ap_const_lv7_10)) then
bufo_load_phi_reg_2296 <= bufo_16_load_reg_4136;
elsif ((p_s_reg_2284 = ap_const_lv7_F)) then
bufo_load_phi_reg_2296 <= bufo_15_load_reg_4141;
elsif ((p_s_reg_2284 = ap_const_lv7_E)) then
bufo_load_phi_reg_2296 <= bufo_14_load_reg_4146;
elsif ((p_s_reg_2284 = ap_const_lv7_D)) then
bufo_load_phi_reg_2296 <= bufo_13_load_reg_4151;
elsif ((p_s_reg_2284 = ap_const_lv7_C)) then
bufo_load_phi_reg_2296 <= bufo_12_load_reg_4156;
elsif ((p_s_reg_2284 = ap_const_lv7_B)) then
bufo_load_phi_reg_2296 <= bufo_11_load_reg_4161;
elsif ((p_s_reg_2284 = ap_const_lv7_A)) then
bufo_load_phi_reg_2296 <= bufo_10_load_reg_4166;
elsif ((p_s_reg_2284 = ap_const_lv7_9)) then
bufo_load_phi_reg_2296 <= bufo_9_load_reg_4171;
elsif ((p_s_reg_2284 = ap_const_lv7_8)) then
bufo_load_phi_reg_2296 <= bufo_8_load_reg_4176;
elsif ((p_s_reg_2284 = ap_const_lv7_7)) then
bufo_load_phi_reg_2296 <= bufo_7_load_reg_4181;
elsif ((p_s_reg_2284 = ap_const_lv7_6)) then
bufo_load_phi_reg_2296 <= bufo_6_load_reg_4186;
elsif ((p_s_reg_2284 = ap_const_lv7_5)) then
bufo_load_phi_reg_2296 <= bufo_5_load_reg_4191;
elsif ((p_s_reg_2284 = ap_const_lv7_4)) then
bufo_load_phi_reg_2296 <= bufo_4_load_reg_4196;
elsif ((p_s_reg_2284 = ap_const_lv7_3)) then
bufo_load_phi_reg_2296 <= bufo_3_load_reg_4201;
elsif ((p_s_reg_2284 = ap_const_lv7_2)) then
bufo_load_phi_reg_2296 <= bufo_2_load_reg_4206;
elsif ((p_s_reg_2284 = ap_const_lv7_1)) then
bufo_load_phi_reg_2296 <= bufo_1_load_reg_4211;
elsif ((p_s_reg_2284 = ap_const_lv7_0)) then
bufo_load_phi_reg_2296 <= bufo_0_load_reg_4216;
end if;
end if;
end if;
end process;
p_s_reg_2284_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state56)) then
p_s_reg_2284 <= to_b_V_reg_3581;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
p_s_reg_2284 <= ap_const_lv7_0;
end if;
end if;
end process;
phi_mul_reg_2272_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state56)) then
phi_mul_reg_2272 <= next_mul_reg_3471;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
phi_mul_reg_2272 <= ap_const_lv64_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_0))) then
bufo_0_load_reg_4216 <= bufo_0_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_64))) then
bufo_100_load_reg_3716 <= bufo_100_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_65))) then
bufo_101_load_reg_3711 <= bufo_101_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_66))) then
bufo_102_load_reg_3706 <= bufo_102_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_67))) then
bufo_103_load_reg_3701 <= bufo_103_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_68))) then
bufo_104_load_reg_3696 <= bufo_104_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_69))) then
bufo_105_load_reg_3691 <= bufo_105_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_6A))) then
bufo_106_load_reg_3686 <= bufo_106_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_6B))) then
bufo_107_load_reg_3681 <= bufo_107_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_6C))) then
bufo_108_load_reg_3676 <= bufo_108_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_6D))) then
bufo_109_load_reg_3671 <= bufo_109_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_A))) then
bufo_10_load_reg_4166 <= bufo_10_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_6E))) then
bufo_110_load_reg_3666 <= bufo_110_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_6F))) then
bufo_111_load_reg_3661 <= bufo_111_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_70))) then
bufo_112_load_reg_3656 <= bufo_112_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_71))) then
bufo_113_load_reg_3651 <= bufo_113_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_72))) then
bufo_114_load_reg_3646 <= bufo_114_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_73))) then
bufo_115_load_reg_3641 <= bufo_115_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_74))) then
bufo_116_load_reg_3636 <= bufo_116_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_75))) then
bufo_117_load_reg_3631 <= bufo_117_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_76))) then
bufo_118_load_reg_3626 <= bufo_118_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_77))) then
bufo_119_load_reg_3621 <= bufo_119_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_B))) then
bufo_11_load_reg_4161 <= bufo_11_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_78))) then
bufo_120_load_reg_3616 <= bufo_120_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_79))) then
bufo_121_load_reg_3611 <= bufo_121_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_7A))) then
bufo_122_load_reg_3606 <= bufo_122_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_7B))) then
bufo_123_load_reg_3601 <= bufo_123_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_7C))) then
bufo_124_load_reg_3596 <= bufo_124_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_7D))) then
bufo_125_load_reg_3591 <= bufo_125_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_7E))) then
bufo_126_load_reg_3586 <= bufo_126_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_7F))) then
bufo_127_load_reg_4221 <= bufo_127_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_C))) then
bufo_12_load_reg_4156 <= bufo_12_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_D))) then
bufo_13_load_reg_4151 <= bufo_13_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_E))) then
bufo_14_load_reg_4146 <= bufo_14_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_F))) then
bufo_15_load_reg_4141 <= bufo_15_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_10))) then
bufo_16_load_reg_4136 <= bufo_16_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_11))) then
bufo_17_load_reg_4131 <= bufo_17_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_12))) then
bufo_18_load_reg_4126 <= bufo_18_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_13))) then
bufo_19_load_reg_4121 <= bufo_19_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_1))) then
bufo_1_load_reg_4211 <= bufo_1_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_14))) then
bufo_20_load_reg_4116 <= bufo_20_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_15))) then
bufo_21_load_reg_4111 <= bufo_21_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_16))) then
bufo_22_load_reg_4106 <= bufo_22_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_17))) then
bufo_23_load_reg_4101 <= bufo_23_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_18))) then
bufo_24_load_reg_4096 <= bufo_24_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_19))) then
bufo_25_load_reg_4091 <= bufo_25_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_1A))) then
bufo_26_load_reg_4086 <= bufo_26_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_1B))) then
bufo_27_load_reg_4081 <= bufo_27_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_1C))) then
bufo_28_load_reg_4076 <= bufo_28_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_1D))) then
bufo_29_load_reg_4071 <= bufo_29_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_2))) then
bufo_2_load_reg_4206 <= bufo_2_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_1E))) then
bufo_30_load_reg_4066 <= bufo_30_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_1F))) then
bufo_31_load_reg_4061 <= bufo_31_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_20))) then
bufo_32_load_reg_4056 <= bufo_32_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_21))) then
bufo_33_load_reg_4051 <= bufo_33_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_22))) then
bufo_34_load_reg_4046 <= bufo_34_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_23))) then
bufo_35_load_reg_4041 <= bufo_35_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_24))) then
bufo_36_load_reg_4036 <= bufo_36_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_25))) then
bufo_37_load_reg_4031 <= bufo_37_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_26))) then
bufo_38_load_reg_4026 <= bufo_38_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_27))) then
bufo_39_load_reg_4021 <= bufo_39_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_3))) then
bufo_3_load_reg_4201 <= bufo_3_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_28))) then
bufo_40_load_reg_4016 <= bufo_40_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_29))) then
bufo_41_load_reg_4011 <= bufo_41_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_2A))) then
bufo_42_load_reg_4006 <= bufo_42_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_2B))) then
bufo_43_load_reg_4001 <= bufo_43_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_2C))) then
bufo_44_load_reg_3996 <= bufo_44_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_2D))) then
bufo_45_load_reg_3991 <= bufo_45_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_2E))) then
bufo_46_load_reg_3986 <= bufo_46_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_2F))) then
bufo_47_load_reg_3981 <= bufo_47_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_30))) then
bufo_48_load_reg_3976 <= bufo_48_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_31))) then
bufo_49_load_reg_3971 <= bufo_49_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_4))) then
bufo_4_load_reg_4196 <= bufo_4_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_32))) then
bufo_50_load_reg_3966 <= bufo_50_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_33))) then
bufo_51_load_reg_3961 <= bufo_51_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_34))) then
bufo_52_load_reg_3956 <= bufo_52_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_35))) then
bufo_53_load_reg_3951 <= bufo_53_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_36))) then
bufo_54_load_reg_3946 <= bufo_54_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_37))) then
bufo_55_load_reg_3941 <= bufo_55_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_38))) then
bufo_56_load_reg_3936 <= bufo_56_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_39))) then
bufo_57_load_reg_3931 <= bufo_57_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_3A))) then
bufo_58_load_reg_3926 <= bufo_58_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_3B))) then
bufo_59_load_reg_3921 <= bufo_59_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_5))) then
bufo_5_load_reg_4191 <= bufo_5_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_3C))) then
bufo_60_load_reg_3916 <= bufo_60_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_3D))) then
bufo_61_load_reg_3911 <= bufo_61_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_3E))) then
bufo_62_load_reg_3906 <= bufo_62_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_3F))) then
bufo_63_load_reg_3901 <= bufo_63_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_40))) then
bufo_64_load_reg_3896 <= bufo_64_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_41))) then
bufo_65_load_reg_3891 <= bufo_65_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_42))) then
bufo_66_load_reg_3886 <= bufo_66_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_43))) then
bufo_67_load_reg_3881 <= bufo_67_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_44))) then
bufo_68_load_reg_3876 <= bufo_68_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_45))) then
bufo_69_load_reg_3871 <= bufo_69_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_6))) then
bufo_6_load_reg_4186 <= bufo_6_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_46))) then
bufo_70_load_reg_3866 <= bufo_70_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_47))) then
bufo_71_load_reg_3861 <= bufo_71_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_48))) then
bufo_72_load_reg_3856 <= bufo_72_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_49))) then
bufo_73_load_reg_3851 <= bufo_73_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_4A))) then
bufo_74_load_reg_3846 <= bufo_74_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_4B))) then
bufo_75_load_reg_3841 <= bufo_75_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_4C))) then
bufo_76_load_reg_3836 <= bufo_76_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_4D))) then
bufo_77_load_reg_3831 <= bufo_77_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_4E))) then
bufo_78_load_reg_3826 <= bufo_78_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_4F))) then
bufo_79_load_reg_3821 <= bufo_79_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_7))) then
bufo_7_load_reg_4181 <= bufo_7_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_50))) then
bufo_80_load_reg_3816 <= bufo_80_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_51))) then
bufo_81_load_reg_3811 <= bufo_81_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_52))) then
bufo_82_load_reg_3806 <= bufo_82_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_53))) then
bufo_83_load_reg_3801 <= bufo_83_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_54))) then
bufo_84_load_reg_3796 <= bufo_84_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_55))) then
bufo_85_load_reg_3791 <= bufo_85_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_56))) then
bufo_86_load_reg_3786 <= bufo_86_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_57))) then
bufo_87_load_reg_3781 <= bufo_87_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_58))) then
bufo_88_load_reg_3776 <= bufo_88_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_59))) then
bufo_89_load_reg_3771 <= bufo_89_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_8))) then
bufo_8_load_reg_4176 <= bufo_8_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_5A))) then
bufo_90_load_reg_3766 <= bufo_90_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_5B))) then
bufo_91_load_reg_3761 <= bufo_91_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_5C))) then
bufo_92_load_reg_3756 <= bufo_92_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_5D))) then
bufo_93_load_reg_3751 <= bufo_93_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_5E))) then
bufo_94_load_reg_3746 <= bufo_94_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_5F))) then
bufo_95_load_reg_3741 <= bufo_95_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_60))) then
bufo_96_load_reg_3736 <= bufo_96_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_61))) then
bufo_97_load_reg_3731 <= bufo_97_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_62))) then
bufo_98_load_reg_3726 <= bufo_98_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_63))) then
bufo_99_load_reg_3721 <= bufo_99_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_9))) then
bufo_9_load_reg_4171 <= bufo_9_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
next_mul_reg_3471 <= next_mul_fu_2714_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state17) or (ap_const_logic_1 = ap_CS_fsm_state26) or (ap_const_logic_1 = ap_CS_fsm_state35) or (ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state55))) then
reg_2580 <= grp_fu_2558_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
tmp_11_reg_3506 <= bufi_Dout_A(95 downto 64);
tmp_13_reg_3511 <= bufw_Dout_A(127 downto 96);
tmp_15_reg_3516 <= bufi_Dout_A(127 downto 96);
tmp_1_reg_3486 <= tmp_1_fu_2724_p1;
tmp_4_reg_3501 <= bufw_Dout_A(95 downto 64);
tmp_6_reg_3491 <= bufw_Dout_A(63 downto 32);
tmp_8_reg_3496 <= bufi_Dout_A(63 downto 32);
tmp_reg_3481 <= tmp_fu_2720_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
tmp_5_1_reg_3566 <= grp_fu_2568_p2;
tmp_5_2_reg_3571 <= grp_fu_2572_p2;
tmp_5_3_reg_3576 <= grp_fu_2576_p2;
tmp_s_reg_3561 <= grp_fu_2564_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state44)) then
to_b_V_reg_3581 <= to_b_V_fu_2820_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state6;
when ap_ST_fsm_state6 =>
ap_NS_fsm <= ap_ST_fsm_state7;
when ap_ST_fsm_state7 =>
ap_NS_fsm <= ap_ST_fsm_state8;
when ap_ST_fsm_state8 =>
ap_NS_fsm <= ap_ST_fsm_state9;
when ap_ST_fsm_state9 =>
ap_NS_fsm <= ap_ST_fsm_state10;
when ap_ST_fsm_state10 =>
ap_NS_fsm <= ap_ST_fsm_state11;
when ap_ST_fsm_state11 =>
ap_NS_fsm <= ap_ST_fsm_state12;
when ap_ST_fsm_state12 =>
ap_NS_fsm <= ap_ST_fsm_state13;
when ap_ST_fsm_state13 =>
ap_NS_fsm <= ap_ST_fsm_state14;
when ap_ST_fsm_state14 =>
ap_NS_fsm <= ap_ST_fsm_state15;
when ap_ST_fsm_state15 =>
ap_NS_fsm <= ap_ST_fsm_state16;
when ap_ST_fsm_state16 =>
ap_NS_fsm <= ap_ST_fsm_state17;
when ap_ST_fsm_state17 =>
ap_NS_fsm <= ap_ST_fsm_state18;
when ap_ST_fsm_state18 =>
ap_NS_fsm <= ap_ST_fsm_state19;
when ap_ST_fsm_state19 =>
ap_NS_fsm <= ap_ST_fsm_state20;
when ap_ST_fsm_state20 =>
ap_NS_fsm <= ap_ST_fsm_state21;
when ap_ST_fsm_state21 =>
ap_NS_fsm <= ap_ST_fsm_state22;
when ap_ST_fsm_state22 =>
ap_NS_fsm <= ap_ST_fsm_state23;
when ap_ST_fsm_state23 =>
ap_NS_fsm <= ap_ST_fsm_state24;
when ap_ST_fsm_state24 =>
ap_NS_fsm <= ap_ST_fsm_state25;
when ap_ST_fsm_state25 =>
ap_NS_fsm <= ap_ST_fsm_state26;
when ap_ST_fsm_state26 =>
ap_NS_fsm <= ap_ST_fsm_state27;
when ap_ST_fsm_state27 =>
ap_NS_fsm <= ap_ST_fsm_state28;
when ap_ST_fsm_state28 =>
ap_NS_fsm <= ap_ST_fsm_state29;
when ap_ST_fsm_state29 =>
ap_NS_fsm <= ap_ST_fsm_state30;
when ap_ST_fsm_state30 =>
ap_NS_fsm <= ap_ST_fsm_state31;
when ap_ST_fsm_state31 =>
ap_NS_fsm <= ap_ST_fsm_state32;
when ap_ST_fsm_state32 =>
ap_NS_fsm <= ap_ST_fsm_state33;
when ap_ST_fsm_state33 =>
ap_NS_fsm <= ap_ST_fsm_state34;
when ap_ST_fsm_state34 =>
ap_NS_fsm <= ap_ST_fsm_state35;
when ap_ST_fsm_state35 =>
ap_NS_fsm <= ap_ST_fsm_state36;
when ap_ST_fsm_state36 =>
ap_NS_fsm <= ap_ST_fsm_state37;
when ap_ST_fsm_state37 =>
ap_NS_fsm <= ap_ST_fsm_state38;
when ap_ST_fsm_state38 =>
ap_NS_fsm <= ap_ST_fsm_state39;
when ap_ST_fsm_state39 =>
ap_NS_fsm <= ap_ST_fsm_state40;
when ap_ST_fsm_state40 =>
ap_NS_fsm <= ap_ST_fsm_state41;
when ap_ST_fsm_state41 =>
ap_NS_fsm <= ap_ST_fsm_state42;
when ap_ST_fsm_state42 =>
ap_NS_fsm <= ap_ST_fsm_state43;
when ap_ST_fsm_state43 =>
ap_NS_fsm <= ap_ST_fsm_state44;
when ap_ST_fsm_state44 =>
ap_NS_fsm <= ap_ST_fsm_state45;
when ap_ST_fsm_state45 =>
ap_NS_fsm <= ap_ST_fsm_state46;
when ap_ST_fsm_state46 =>
ap_NS_fsm <= ap_ST_fsm_state47;
when ap_ST_fsm_state47 =>
ap_NS_fsm <= ap_ST_fsm_state48;
when ap_ST_fsm_state48 =>
ap_NS_fsm <= ap_ST_fsm_state49;
when ap_ST_fsm_state49 =>
ap_NS_fsm <= ap_ST_fsm_state50;
when ap_ST_fsm_state50 =>
ap_NS_fsm <= ap_ST_fsm_state51;
when ap_ST_fsm_state51 =>
ap_NS_fsm <= ap_ST_fsm_state52;
when ap_ST_fsm_state52 =>
ap_NS_fsm <= ap_ST_fsm_state53;
when ap_ST_fsm_state53 =>
ap_NS_fsm <= ap_ST_fsm_state54;
when ap_ST_fsm_state54 =>
ap_NS_fsm <= ap_ST_fsm_state55;
when ap_ST_fsm_state55 =>
ap_NS_fsm <= ap_ST_fsm_state56;
when ap_ST_fsm_state56 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state17 <= ap_CS_fsm(16);
ap_CS_fsm_state18 <= ap_CS_fsm(17);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state26 <= ap_CS_fsm(25);
ap_CS_fsm_state27 <= ap_CS_fsm(26);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state35 <= ap_CS_fsm(34);
ap_CS_fsm_state36 <= ap_CS_fsm(35);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state44 <= ap_CS_fsm(43);
ap_CS_fsm_state45 <= ap_CS_fsm(44);
ap_CS_fsm_state46 <= ap_CS_fsm(45);
ap_CS_fsm_state47 <= ap_CS_fsm(46);
ap_CS_fsm_state55 <= ap_CS_fsm(54);
ap_CS_fsm_state56 <= ap_CS_fsm(55);
ap_CS_fsm_state8 <= ap_CS_fsm(7);
ap_CS_fsm_state9 <= ap_CS_fsm(8);
ap_done <= ap_const_logic_0;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready <= ap_const_logic_0;
bufi_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_4(31-1 downto 0)))));
bufi_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufi_Clk_A <= ap_clk;
bufi_Din_A <= ap_const_lv128_lc_1;
bufi_EN_A_assign_proc : process(ap_CS_fsm_state2)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
bufi_EN_A <= ap_const_logic_1;
else
bufi_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_Rst_A <= ap_rst;
bufi_WEN_A <= ap_const_lv16_0;
bufo_0_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_0_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_0_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_0_Clk_A <= ap_clk;
bufo_0_Din_A <= reg_2580;
bufo_0_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_0_EN_A <= ap_const_logic_1;
else
bufo_0_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_0_Rst_A <= ap_rst;
bufo_0_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_0) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_0_WEN_A <= ap_const_lv4_F;
else
bufo_0_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_100_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_100_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_100_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_100_Clk_A <= ap_clk;
bufo_100_Din_A <= reg_2580;
bufo_100_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_100_EN_A <= ap_const_logic_1;
else
bufo_100_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_100_Rst_A <= ap_rst;
bufo_100_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_64) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_100_WEN_A <= ap_const_lv4_F;
else
bufo_100_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_101_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_101_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_101_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_101_Clk_A <= ap_clk;
bufo_101_Din_A <= reg_2580;
bufo_101_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_101_EN_A <= ap_const_logic_1;
else
bufo_101_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_101_Rst_A <= ap_rst;
bufo_101_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_65) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_101_WEN_A <= ap_const_lv4_F;
else
bufo_101_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_102_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_102_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_102_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_102_Clk_A <= ap_clk;
bufo_102_Din_A <= reg_2580;
bufo_102_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_102_EN_A <= ap_const_logic_1;
else
bufo_102_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_102_Rst_A <= ap_rst;
bufo_102_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_66) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_102_WEN_A <= ap_const_lv4_F;
else
bufo_102_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_103_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_103_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_103_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_103_Clk_A <= ap_clk;
bufo_103_Din_A <= reg_2580;
bufo_103_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_103_EN_A <= ap_const_logic_1;
else
bufo_103_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_103_Rst_A <= ap_rst;
bufo_103_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_67) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_103_WEN_A <= ap_const_lv4_F;
else
bufo_103_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_104_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_104_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_104_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_104_Clk_A <= ap_clk;
bufo_104_Din_A <= reg_2580;
bufo_104_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_104_EN_A <= ap_const_logic_1;
else
bufo_104_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_104_Rst_A <= ap_rst;
bufo_104_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_68) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_104_WEN_A <= ap_const_lv4_F;
else
bufo_104_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_105_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_105_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_105_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_105_Clk_A <= ap_clk;
bufo_105_Din_A <= reg_2580;
bufo_105_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_105_EN_A <= ap_const_logic_1;
else
bufo_105_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_105_Rst_A <= ap_rst;
bufo_105_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_69) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_105_WEN_A <= ap_const_lv4_F;
else
bufo_105_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_106_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_106_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_106_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_106_Clk_A <= ap_clk;
bufo_106_Din_A <= reg_2580;
bufo_106_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_106_EN_A <= ap_const_logic_1;
else
bufo_106_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_106_Rst_A <= ap_rst;
bufo_106_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_6A) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_106_WEN_A <= ap_const_lv4_F;
else
bufo_106_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_107_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_107_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_107_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_107_Clk_A <= ap_clk;
bufo_107_Din_A <= reg_2580;
bufo_107_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_107_EN_A <= ap_const_logic_1;
else
bufo_107_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_107_Rst_A <= ap_rst;
bufo_107_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_6B) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_107_WEN_A <= ap_const_lv4_F;
else
bufo_107_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_108_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_108_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_108_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_108_Clk_A <= ap_clk;
bufo_108_Din_A <= reg_2580;
bufo_108_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_108_EN_A <= ap_const_logic_1;
else
bufo_108_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_108_Rst_A <= ap_rst;
bufo_108_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_6C) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_108_WEN_A <= ap_const_lv4_F;
else
bufo_108_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_109_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_109_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_109_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_109_Clk_A <= ap_clk;
bufo_109_Din_A <= reg_2580;
bufo_109_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_109_EN_A <= ap_const_logic_1;
else
bufo_109_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_109_Rst_A <= ap_rst;
bufo_109_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_6D) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_109_WEN_A <= ap_const_lv4_F;
else
bufo_109_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_10_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_10_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_10_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_10_Clk_A <= ap_clk;
bufo_10_Din_A <= reg_2580;
bufo_10_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_10_EN_A <= ap_const_logic_1;
else
bufo_10_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_10_Rst_A <= ap_rst;
bufo_10_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_A) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_10_WEN_A <= ap_const_lv4_F;
else
bufo_10_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_110_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_110_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_110_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_110_Clk_A <= ap_clk;
bufo_110_Din_A <= reg_2580;
bufo_110_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_110_EN_A <= ap_const_logic_1;
else
bufo_110_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_110_Rst_A <= ap_rst;
bufo_110_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_6E) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_110_WEN_A <= ap_const_lv4_F;
else
bufo_110_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_111_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_111_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_111_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_111_Clk_A <= ap_clk;
bufo_111_Din_A <= reg_2580;
bufo_111_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_111_EN_A <= ap_const_logic_1;
else
bufo_111_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_111_Rst_A <= ap_rst;
bufo_111_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_6F) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_111_WEN_A <= ap_const_lv4_F;
else
bufo_111_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_112_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_112_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_112_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_112_Clk_A <= ap_clk;
bufo_112_Din_A <= reg_2580;
bufo_112_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_112_EN_A <= ap_const_logic_1;
else
bufo_112_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_112_Rst_A <= ap_rst;
bufo_112_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_70) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_112_WEN_A <= ap_const_lv4_F;
else
bufo_112_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_113_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_113_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_113_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_113_Clk_A <= ap_clk;
bufo_113_Din_A <= reg_2580;
bufo_113_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_113_EN_A <= ap_const_logic_1;
else
bufo_113_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_113_Rst_A <= ap_rst;
bufo_113_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_71) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_113_WEN_A <= ap_const_lv4_F;
else
bufo_113_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_114_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_114_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_114_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_114_Clk_A <= ap_clk;
bufo_114_Din_A <= reg_2580;
bufo_114_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_114_EN_A <= ap_const_logic_1;
else
bufo_114_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_114_Rst_A <= ap_rst;
bufo_114_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_72) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_114_WEN_A <= ap_const_lv4_F;
else
bufo_114_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_115_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_115_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_115_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_115_Clk_A <= ap_clk;
bufo_115_Din_A <= reg_2580;
bufo_115_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_115_EN_A <= ap_const_logic_1;
else
bufo_115_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_115_Rst_A <= ap_rst;
bufo_115_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_73) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_115_WEN_A <= ap_const_lv4_F;
else
bufo_115_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_116_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_116_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_116_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_116_Clk_A <= ap_clk;
bufo_116_Din_A <= reg_2580;
bufo_116_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_116_EN_A <= ap_const_logic_1;
else
bufo_116_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_116_Rst_A <= ap_rst;
bufo_116_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_74) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_116_WEN_A <= ap_const_lv4_F;
else
bufo_116_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_117_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_117_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_117_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_117_Clk_A <= ap_clk;
bufo_117_Din_A <= reg_2580;
bufo_117_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_117_EN_A <= ap_const_logic_1;
else
bufo_117_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_117_Rst_A <= ap_rst;
bufo_117_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_75) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_117_WEN_A <= ap_const_lv4_F;
else
bufo_117_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_118_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_118_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_118_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_118_Clk_A <= ap_clk;
bufo_118_Din_A <= reg_2580;
bufo_118_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_118_EN_A <= ap_const_logic_1;
else
bufo_118_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_118_Rst_A <= ap_rst;
bufo_118_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_76) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_118_WEN_A <= ap_const_lv4_F;
else
bufo_118_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_119_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_119_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_119_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_119_Clk_A <= ap_clk;
bufo_119_Din_A <= reg_2580;
bufo_119_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_119_EN_A <= ap_const_logic_1;
else
bufo_119_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_119_Rst_A <= ap_rst;
bufo_119_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_77) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_119_WEN_A <= ap_const_lv4_F;
else
bufo_119_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_11_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_11_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_11_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_11_Clk_A <= ap_clk;
bufo_11_Din_A <= reg_2580;
bufo_11_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_11_EN_A <= ap_const_logic_1;
else
bufo_11_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_11_Rst_A <= ap_rst;
bufo_11_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_B) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_11_WEN_A <= ap_const_lv4_F;
else
bufo_11_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_120_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_120_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_120_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_120_Clk_A <= ap_clk;
bufo_120_Din_A <= reg_2580;
bufo_120_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_120_EN_A <= ap_const_logic_1;
else
bufo_120_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_120_Rst_A <= ap_rst;
bufo_120_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_78) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_120_WEN_A <= ap_const_lv4_F;
else
bufo_120_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_121_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_121_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_121_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_121_Clk_A <= ap_clk;
bufo_121_Din_A <= reg_2580;
bufo_121_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_121_EN_A <= ap_const_logic_1;
else
bufo_121_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_121_Rst_A <= ap_rst;
bufo_121_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_79) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_121_WEN_A <= ap_const_lv4_F;
else
bufo_121_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_122_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_122_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_122_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_122_Clk_A <= ap_clk;
bufo_122_Din_A <= reg_2580;
bufo_122_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_122_EN_A <= ap_const_logic_1;
else
bufo_122_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_122_Rst_A <= ap_rst;
bufo_122_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_7A) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_122_WEN_A <= ap_const_lv4_F;
else
bufo_122_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_123_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_123_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_123_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_123_Clk_A <= ap_clk;
bufo_123_Din_A <= reg_2580;
bufo_123_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_123_EN_A <= ap_const_logic_1;
else
bufo_123_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_123_Rst_A <= ap_rst;
bufo_123_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_7B) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_123_WEN_A <= ap_const_lv4_F;
else
bufo_123_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_124_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_124_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_124_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_124_Clk_A <= ap_clk;
bufo_124_Din_A <= reg_2580;
bufo_124_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_124_EN_A <= ap_const_logic_1;
else
bufo_124_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_124_Rst_A <= ap_rst;
bufo_124_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_7C) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_124_WEN_A <= ap_const_lv4_F;
else
bufo_124_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_125_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_125_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_125_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_125_Clk_A <= ap_clk;
bufo_125_Din_A <= reg_2580;
bufo_125_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_125_EN_A <= ap_const_logic_1;
else
bufo_125_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_125_Rst_A <= ap_rst;
bufo_125_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_7D) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_125_WEN_A <= ap_const_lv4_F;
else
bufo_125_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_126_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_126_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_126_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_126_Clk_A <= ap_clk;
bufo_126_Din_A <= reg_2580;
bufo_126_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_126_EN_A <= ap_const_logic_1;
else
bufo_126_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_126_Rst_A <= ap_rst;
bufo_126_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_7E) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_126_WEN_A <= ap_const_lv4_F;
else
bufo_126_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_127_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_127_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_127_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_127_Clk_A <= ap_clk;
bufo_127_Din_A <= reg_2580;
bufo_127_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_127_EN_A <= ap_const_logic_1;
else
bufo_127_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_127_Rst_A <= ap_rst;
bufo_127_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_7F) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_127_WEN_A <= ap_const_lv4_F;
else
bufo_127_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_128_Addr_A <= ap_const_lv32_0;
bufo_128_Addr_B <= ap_const_lv32_0;
bufo_128_Clk_A <= ap_clk;
bufo_128_Clk_B <= ap_clk;
bufo_128_Din_A <= ap_const_lv32_0;
bufo_128_Din_B <= ap_const_lv32_0;
bufo_128_EN_A <= ap_const_logic_0;
bufo_128_EN_B <= ap_const_logic_0;
bufo_128_Rst_A <= ap_rst;
bufo_128_Rst_B <= ap_rst;
bufo_128_WEN_A <= ap_const_lv4_0;
bufo_128_WEN_B <= ap_const_lv4_0;
bufo_129_Addr_A <= ap_const_lv32_0;
bufo_129_Addr_B <= ap_const_lv32_0;
bufo_129_Clk_A <= ap_clk;
bufo_129_Clk_B <= ap_clk;
bufo_129_Din_A <= ap_const_lv32_0;
bufo_129_Din_B <= ap_const_lv32_0;
bufo_129_EN_A <= ap_const_logic_0;
bufo_129_EN_B <= ap_const_logic_0;
bufo_129_Rst_A <= ap_rst;
bufo_129_Rst_B <= ap_rst;
bufo_129_WEN_A <= ap_const_lv4_0;
bufo_129_WEN_B <= ap_const_lv4_0;
bufo_12_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_12_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_12_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_12_Clk_A <= ap_clk;
bufo_12_Din_A <= reg_2580;
bufo_12_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_12_EN_A <= ap_const_logic_1;
else
bufo_12_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_12_Rst_A <= ap_rst;
bufo_12_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_C) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_12_WEN_A <= ap_const_lv4_F;
else
bufo_12_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_130_Addr_A <= ap_const_lv32_0;
bufo_130_Addr_B <= ap_const_lv32_0;
bufo_130_Clk_A <= ap_clk;
bufo_130_Clk_B <= ap_clk;
bufo_130_Din_A <= ap_const_lv32_0;
bufo_130_Din_B <= ap_const_lv32_0;
bufo_130_EN_A <= ap_const_logic_0;
bufo_130_EN_B <= ap_const_logic_0;
bufo_130_Rst_A <= ap_rst;
bufo_130_Rst_B <= ap_rst;
bufo_130_WEN_A <= ap_const_lv4_0;
bufo_130_WEN_B <= ap_const_lv4_0;
bufo_131_Addr_A <= ap_const_lv32_0;
bufo_131_Addr_B <= ap_const_lv32_0;
bufo_131_Clk_A <= ap_clk;
bufo_131_Clk_B <= ap_clk;
bufo_131_Din_A <= ap_const_lv32_0;
bufo_131_Din_B <= ap_const_lv32_0;
bufo_131_EN_A <= ap_const_logic_0;
bufo_131_EN_B <= ap_const_logic_0;
bufo_131_Rst_A <= ap_rst;
bufo_131_Rst_B <= ap_rst;
bufo_131_WEN_A <= ap_const_lv4_0;
bufo_131_WEN_B <= ap_const_lv4_0;
bufo_132_Addr_A <= ap_const_lv32_0;
bufo_132_Addr_B <= ap_const_lv32_0;
bufo_132_Clk_A <= ap_clk;
bufo_132_Clk_B <= ap_clk;
bufo_132_Din_A <= ap_const_lv32_0;
bufo_132_Din_B <= ap_const_lv32_0;
bufo_132_EN_A <= ap_const_logic_0;
bufo_132_EN_B <= ap_const_logic_0;
bufo_132_Rst_A <= ap_rst;
bufo_132_Rst_B <= ap_rst;
bufo_132_WEN_A <= ap_const_lv4_0;
bufo_132_WEN_B <= ap_const_lv4_0;
bufo_133_Addr_A <= ap_const_lv32_0;
bufo_133_Addr_B <= ap_const_lv32_0;
bufo_133_Clk_A <= ap_clk;
bufo_133_Clk_B <= ap_clk;
bufo_133_Din_A <= ap_const_lv32_0;
bufo_133_Din_B <= ap_const_lv32_0;
bufo_133_EN_A <= ap_const_logic_0;
bufo_133_EN_B <= ap_const_logic_0;
bufo_133_Rst_A <= ap_rst;
bufo_133_Rst_B <= ap_rst;
bufo_133_WEN_A <= ap_const_lv4_0;
bufo_133_WEN_B <= ap_const_lv4_0;
bufo_134_Addr_A <= ap_const_lv32_0;
bufo_134_Addr_B <= ap_const_lv32_0;
bufo_134_Clk_A <= ap_clk;
bufo_134_Clk_B <= ap_clk;
bufo_134_Din_A <= ap_const_lv32_0;
bufo_134_Din_B <= ap_const_lv32_0;
bufo_134_EN_A <= ap_const_logic_0;
bufo_134_EN_B <= ap_const_logic_0;
bufo_134_Rst_A <= ap_rst;
bufo_134_Rst_B <= ap_rst;
bufo_134_WEN_A <= ap_const_lv4_0;
bufo_134_WEN_B <= ap_const_lv4_0;
bufo_135_Addr_A <= ap_const_lv32_0;
bufo_135_Addr_B <= ap_const_lv32_0;
bufo_135_Clk_A <= ap_clk;
bufo_135_Clk_B <= ap_clk;
bufo_135_Din_A <= ap_const_lv32_0;
bufo_135_Din_B <= ap_const_lv32_0;
bufo_135_EN_A <= ap_const_logic_0;
bufo_135_EN_B <= ap_const_logic_0;
bufo_135_Rst_A <= ap_rst;
bufo_135_Rst_B <= ap_rst;
bufo_135_WEN_A <= ap_const_lv4_0;
bufo_135_WEN_B <= ap_const_lv4_0;
bufo_136_Addr_A <= ap_const_lv32_0;
bufo_136_Addr_B <= ap_const_lv32_0;
bufo_136_Clk_A <= ap_clk;
bufo_136_Clk_B <= ap_clk;
bufo_136_Din_A <= ap_const_lv32_0;
bufo_136_Din_B <= ap_const_lv32_0;
bufo_136_EN_A <= ap_const_logic_0;
bufo_136_EN_B <= ap_const_logic_0;
bufo_136_Rst_A <= ap_rst;
bufo_136_Rst_B <= ap_rst;
bufo_136_WEN_A <= ap_const_lv4_0;
bufo_136_WEN_B <= ap_const_lv4_0;
bufo_137_Addr_A <= ap_const_lv32_0;
bufo_137_Addr_B <= ap_const_lv32_0;
bufo_137_Clk_A <= ap_clk;
bufo_137_Clk_B <= ap_clk;
bufo_137_Din_A <= ap_const_lv32_0;
bufo_137_Din_B <= ap_const_lv32_0;
bufo_137_EN_A <= ap_const_logic_0;
bufo_137_EN_B <= ap_const_logic_0;
bufo_137_Rst_A <= ap_rst;
bufo_137_Rst_B <= ap_rst;
bufo_137_WEN_A <= ap_const_lv4_0;
bufo_137_WEN_B <= ap_const_lv4_0;
bufo_138_Addr_A <= ap_const_lv32_0;
bufo_138_Addr_B <= ap_const_lv32_0;
bufo_138_Clk_A <= ap_clk;
bufo_138_Clk_B <= ap_clk;
bufo_138_Din_A <= ap_const_lv32_0;
bufo_138_Din_B <= ap_const_lv32_0;
bufo_138_EN_A <= ap_const_logic_0;
bufo_138_EN_B <= ap_const_logic_0;
bufo_138_Rst_A <= ap_rst;
bufo_138_Rst_B <= ap_rst;
bufo_138_WEN_A <= ap_const_lv4_0;
bufo_138_WEN_B <= ap_const_lv4_0;
bufo_139_Addr_A <= ap_const_lv32_0;
bufo_139_Addr_B <= ap_const_lv32_0;
bufo_139_Clk_A <= ap_clk;
bufo_139_Clk_B <= ap_clk;
bufo_139_Din_A <= ap_const_lv32_0;
bufo_139_Din_B <= ap_const_lv32_0;
bufo_139_EN_A <= ap_const_logic_0;
bufo_139_EN_B <= ap_const_logic_0;
bufo_139_Rst_A <= ap_rst;
bufo_139_Rst_B <= ap_rst;
bufo_139_WEN_A <= ap_const_lv4_0;
bufo_139_WEN_B <= ap_const_lv4_0;
bufo_13_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_13_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_13_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_13_Clk_A <= ap_clk;
bufo_13_Din_A <= reg_2580;
bufo_13_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_13_EN_A <= ap_const_logic_1;
else
bufo_13_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_13_Rst_A <= ap_rst;
bufo_13_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_D) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_13_WEN_A <= ap_const_lv4_F;
else
bufo_13_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_140_Addr_A <= ap_const_lv32_0;
bufo_140_Addr_B <= ap_const_lv32_0;
bufo_140_Clk_A <= ap_clk;
bufo_140_Clk_B <= ap_clk;
bufo_140_Din_A <= ap_const_lv32_0;
bufo_140_Din_B <= ap_const_lv32_0;
bufo_140_EN_A <= ap_const_logic_0;
bufo_140_EN_B <= ap_const_logic_0;
bufo_140_Rst_A <= ap_rst;
bufo_140_Rst_B <= ap_rst;
bufo_140_WEN_A <= ap_const_lv4_0;
bufo_140_WEN_B <= ap_const_lv4_0;
bufo_141_Addr_A <= ap_const_lv32_0;
bufo_141_Addr_B <= ap_const_lv32_0;
bufo_141_Clk_A <= ap_clk;
bufo_141_Clk_B <= ap_clk;
bufo_141_Din_A <= ap_const_lv32_0;
bufo_141_Din_B <= ap_const_lv32_0;
bufo_141_EN_A <= ap_const_logic_0;
bufo_141_EN_B <= ap_const_logic_0;
bufo_141_Rst_A <= ap_rst;
bufo_141_Rst_B <= ap_rst;
bufo_141_WEN_A <= ap_const_lv4_0;
bufo_141_WEN_B <= ap_const_lv4_0;
bufo_142_Addr_A <= ap_const_lv32_0;
bufo_142_Addr_B <= ap_const_lv32_0;
bufo_142_Clk_A <= ap_clk;
bufo_142_Clk_B <= ap_clk;
bufo_142_Din_A <= ap_const_lv32_0;
bufo_142_Din_B <= ap_const_lv32_0;
bufo_142_EN_A <= ap_const_logic_0;
bufo_142_EN_B <= ap_const_logic_0;
bufo_142_Rst_A <= ap_rst;
bufo_142_Rst_B <= ap_rst;
bufo_142_WEN_A <= ap_const_lv4_0;
bufo_142_WEN_B <= ap_const_lv4_0;
bufo_143_Addr_A <= ap_const_lv32_0;
bufo_143_Addr_B <= ap_const_lv32_0;
bufo_143_Clk_A <= ap_clk;
bufo_143_Clk_B <= ap_clk;
bufo_143_Din_A <= ap_const_lv32_0;
bufo_143_Din_B <= ap_const_lv32_0;
bufo_143_EN_A <= ap_const_logic_0;
bufo_143_EN_B <= ap_const_logic_0;
bufo_143_Rst_A <= ap_rst;
bufo_143_Rst_B <= ap_rst;
bufo_143_WEN_A <= ap_const_lv4_0;
bufo_143_WEN_B <= ap_const_lv4_0;
bufo_144_Addr_A <= ap_const_lv32_0;
bufo_144_Addr_B <= ap_const_lv32_0;
bufo_144_Clk_A <= ap_clk;
bufo_144_Clk_B <= ap_clk;
bufo_144_Din_A <= ap_const_lv32_0;
bufo_144_Din_B <= ap_const_lv32_0;
bufo_144_EN_A <= ap_const_logic_0;
bufo_144_EN_B <= ap_const_logic_0;
bufo_144_Rst_A <= ap_rst;
bufo_144_Rst_B <= ap_rst;
bufo_144_WEN_A <= ap_const_lv4_0;
bufo_144_WEN_B <= ap_const_lv4_0;
bufo_145_Addr_A <= ap_const_lv32_0;
bufo_145_Addr_B <= ap_const_lv32_0;
bufo_145_Clk_A <= ap_clk;
bufo_145_Clk_B <= ap_clk;
bufo_145_Din_A <= ap_const_lv32_0;
bufo_145_Din_B <= ap_const_lv32_0;
bufo_145_EN_A <= ap_const_logic_0;
bufo_145_EN_B <= ap_const_logic_0;
bufo_145_Rst_A <= ap_rst;
bufo_145_Rst_B <= ap_rst;
bufo_145_WEN_A <= ap_const_lv4_0;
bufo_145_WEN_B <= ap_const_lv4_0;
bufo_146_Addr_A <= ap_const_lv32_0;
bufo_146_Addr_B <= ap_const_lv32_0;
bufo_146_Clk_A <= ap_clk;
bufo_146_Clk_B <= ap_clk;
bufo_146_Din_A <= ap_const_lv32_0;
bufo_146_Din_B <= ap_const_lv32_0;
bufo_146_EN_A <= ap_const_logic_0;
bufo_146_EN_B <= ap_const_logic_0;
bufo_146_Rst_A <= ap_rst;
bufo_146_Rst_B <= ap_rst;
bufo_146_WEN_A <= ap_const_lv4_0;
bufo_146_WEN_B <= ap_const_lv4_0;
bufo_147_Addr_A <= ap_const_lv32_0;
bufo_147_Addr_B <= ap_const_lv32_0;
bufo_147_Clk_A <= ap_clk;
bufo_147_Clk_B <= ap_clk;
bufo_147_Din_A <= ap_const_lv32_0;
bufo_147_Din_B <= ap_const_lv32_0;
bufo_147_EN_A <= ap_const_logic_0;
bufo_147_EN_B <= ap_const_logic_0;
bufo_147_Rst_A <= ap_rst;
bufo_147_Rst_B <= ap_rst;
bufo_147_WEN_A <= ap_const_lv4_0;
bufo_147_WEN_B <= ap_const_lv4_0;
bufo_148_Addr_A <= ap_const_lv32_0;
bufo_148_Addr_B <= ap_const_lv32_0;
bufo_148_Clk_A <= ap_clk;
bufo_148_Clk_B <= ap_clk;
bufo_148_Din_A <= ap_const_lv32_0;
bufo_148_Din_B <= ap_const_lv32_0;
bufo_148_EN_A <= ap_const_logic_0;
bufo_148_EN_B <= ap_const_logic_0;
bufo_148_Rst_A <= ap_rst;
bufo_148_Rst_B <= ap_rst;
bufo_148_WEN_A <= ap_const_lv4_0;
bufo_148_WEN_B <= ap_const_lv4_0;
bufo_149_Addr_A <= ap_const_lv32_0;
bufo_149_Addr_B <= ap_const_lv32_0;
bufo_149_Clk_A <= ap_clk;
bufo_149_Clk_B <= ap_clk;
bufo_149_Din_A <= ap_const_lv32_0;
bufo_149_Din_B <= ap_const_lv32_0;
bufo_149_EN_A <= ap_const_logic_0;
bufo_149_EN_B <= ap_const_logic_0;
bufo_149_Rst_A <= ap_rst;
bufo_149_Rst_B <= ap_rst;
bufo_149_WEN_A <= ap_const_lv4_0;
bufo_149_WEN_B <= ap_const_lv4_0;
bufo_14_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_14_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_14_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_14_Clk_A <= ap_clk;
bufo_14_Din_A <= reg_2580;
bufo_14_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_14_EN_A <= ap_const_logic_1;
else
bufo_14_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_14_Rst_A <= ap_rst;
bufo_14_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_E) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_14_WEN_A <= ap_const_lv4_F;
else
bufo_14_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_150_Addr_A <= ap_const_lv32_0;
bufo_150_Addr_B <= ap_const_lv32_0;
bufo_150_Clk_A <= ap_clk;
bufo_150_Clk_B <= ap_clk;
bufo_150_Din_A <= ap_const_lv32_0;
bufo_150_Din_B <= ap_const_lv32_0;
bufo_150_EN_A <= ap_const_logic_0;
bufo_150_EN_B <= ap_const_logic_0;
bufo_150_Rst_A <= ap_rst;
bufo_150_Rst_B <= ap_rst;
bufo_150_WEN_A <= ap_const_lv4_0;
bufo_150_WEN_B <= ap_const_lv4_0;
bufo_151_Addr_A <= ap_const_lv32_0;
bufo_151_Addr_B <= ap_const_lv32_0;
bufo_151_Clk_A <= ap_clk;
bufo_151_Clk_B <= ap_clk;
bufo_151_Din_A <= ap_const_lv32_0;
bufo_151_Din_B <= ap_const_lv32_0;
bufo_151_EN_A <= ap_const_logic_0;
bufo_151_EN_B <= ap_const_logic_0;
bufo_151_Rst_A <= ap_rst;
bufo_151_Rst_B <= ap_rst;
bufo_151_WEN_A <= ap_const_lv4_0;
bufo_151_WEN_B <= ap_const_lv4_0;
bufo_152_Addr_A <= ap_const_lv32_0;
bufo_152_Addr_B <= ap_const_lv32_0;
bufo_152_Clk_A <= ap_clk;
bufo_152_Clk_B <= ap_clk;
bufo_152_Din_A <= ap_const_lv32_0;
bufo_152_Din_B <= ap_const_lv32_0;
bufo_152_EN_A <= ap_const_logic_0;
bufo_152_EN_B <= ap_const_logic_0;
bufo_152_Rst_A <= ap_rst;
bufo_152_Rst_B <= ap_rst;
bufo_152_WEN_A <= ap_const_lv4_0;
bufo_152_WEN_B <= ap_const_lv4_0;
bufo_153_Addr_A <= ap_const_lv32_0;
bufo_153_Addr_B <= ap_const_lv32_0;
bufo_153_Clk_A <= ap_clk;
bufo_153_Clk_B <= ap_clk;
bufo_153_Din_A <= ap_const_lv32_0;
bufo_153_Din_B <= ap_const_lv32_0;
bufo_153_EN_A <= ap_const_logic_0;
bufo_153_EN_B <= ap_const_logic_0;
bufo_153_Rst_A <= ap_rst;
bufo_153_Rst_B <= ap_rst;
bufo_153_WEN_A <= ap_const_lv4_0;
bufo_153_WEN_B <= ap_const_lv4_0;
bufo_154_Addr_A <= ap_const_lv32_0;
bufo_154_Addr_B <= ap_const_lv32_0;
bufo_154_Clk_A <= ap_clk;
bufo_154_Clk_B <= ap_clk;
bufo_154_Din_A <= ap_const_lv32_0;
bufo_154_Din_B <= ap_const_lv32_0;
bufo_154_EN_A <= ap_const_logic_0;
bufo_154_EN_B <= ap_const_logic_0;
bufo_154_Rst_A <= ap_rst;
bufo_154_Rst_B <= ap_rst;
bufo_154_WEN_A <= ap_const_lv4_0;
bufo_154_WEN_B <= ap_const_lv4_0;
bufo_155_Addr_A <= ap_const_lv32_0;
bufo_155_Addr_B <= ap_const_lv32_0;
bufo_155_Clk_A <= ap_clk;
bufo_155_Clk_B <= ap_clk;
bufo_155_Din_A <= ap_const_lv32_0;
bufo_155_Din_B <= ap_const_lv32_0;
bufo_155_EN_A <= ap_const_logic_0;
bufo_155_EN_B <= ap_const_logic_0;
bufo_155_Rst_A <= ap_rst;
bufo_155_Rst_B <= ap_rst;
bufo_155_WEN_A <= ap_const_lv4_0;
bufo_155_WEN_B <= ap_const_lv4_0;
bufo_156_Addr_A <= ap_const_lv32_0;
bufo_156_Addr_B <= ap_const_lv32_0;
bufo_156_Clk_A <= ap_clk;
bufo_156_Clk_B <= ap_clk;
bufo_156_Din_A <= ap_const_lv32_0;
bufo_156_Din_B <= ap_const_lv32_0;
bufo_156_EN_A <= ap_const_logic_0;
bufo_156_EN_B <= ap_const_logic_0;
bufo_156_Rst_A <= ap_rst;
bufo_156_Rst_B <= ap_rst;
bufo_156_WEN_A <= ap_const_lv4_0;
bufo_156_WEN_B <= ap_const_lv4_0;
bufo_157_Addr_A <= ap_const_lv32_0;
bufo_157_Addr_B <= ap_const_lv32_0;
bufo_157_Clk_A <= ap_clk;
bufo_157_Clk_B <= ap_clk;
bufo_157_Din_A <= ap_const_lv32_0;
bufo_157_Din_B <= ap_const_lv32_0;
bufo_157_EN_A <= ap_const_logic_0;
bufo_157_EN_B <= ap_const_logic_0;
bufo_157_Rst_A <= ap_rst;
bufo_157_Rst_B <= ap_rst;
bufo_157_WEN_A <= ap_const_lv4_0;
bufo_157_WEN_B <= ap_const_lv4_0;
bufo_158_Addr_A <= ap_const_lv32_0;
bufo_158_Addr_B <= ap_const_lv32_0;
bufo_158_Clk_A <= ap_clk;
bufo_158_Clk_B <= ap_clk;
bufo_158_Din_A <= ap_const_lv32_0;
bufo_158_Din_B <= ap_const_lv32_0;
bufo_158_EN_A <= ap_const_logic_0;
bufo_158_EN_B <= ap_const_logic_0;
bufo_158_Rst_A <= ap_rst;
bufo_158_Rst_B <= ap_rst;
bufo_158_WEN_A <= ap_const_lv4_0;
bufo_158_WEN_B <= ap_const_lv4_0;
bufo_159_Addr_A <= ap_const_lv32_0;
bufo_159_Addr_B <= ap_const_lv32_0;
bufo_159_Clk_A <= ap_clk;
bufo_159_Clk_B <= ap_clk;
bufo_159_Din_A <= ap_const_lv32_0;
bufo_159_Din_B <= ap_const_lv32_0;
bufo_159_EN_A <= ap_const_logic_0;
bufo_159_EN_B <= ap_const_logic_0;
bufo_159_Rst_A <= ap_rst;
bufo_159_Rst_B <= ap_rst;
bufo_159_WEN_A <= ap_const_lv4_0;
bufo_159_WEN_B <= ap_const_lv4_0;
bufo_15_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_15_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_15_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_15_Clk_A <= ap_clk;
bufo_15_Din_A <= reg_2580;
bufo_15_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_15_EN_A <= ap_const_logic_1;
else
bufo_15_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_15_Rst_A <= ap_rst;
bufo_15_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_F) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_15_WEN_A <= ap_const_lv4_F;
else
bufo_15_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_160_Addr_A <= ap_const_lv32_0;
bufo_160_Addr_B <= ap_const_lv32_0;
bufo_160_Clk_A <= ap_clk;
bufo_160_Clk_B <= ap_clk;
bufo_160_Din_A <= ap_const_lv32_0;
bufo_160_Din_B <= ap_const_lv32_0;
bufo_160_EN_A <= ap_const_logic_0;
bufo_160_EN_B <= ap_const_logic_0;
bufo_160_Rst_A <= ap_rst;
bufo_160_Rst_B <= ap_rst;
bufo_160_WEN_A <= ap_const_lv4_0;
bufo_160_WEN_B <= ap_const_lv4_0;
bufo_161_Addr_A <= ap_const_lv32_0;
bufo_161_Addr_B <= ap_const_lv32_0;
bufo_161_Clk_A <= ap_clk;
bufo_161_Clk_B <= ap_clk;
bufo_161_Din_A <= ap_const_lv32_0;
bufo_161_Din_B <= ap_const_lv32_0;
bufo_161_EN_A <= ap_const_logic_0;
bufo_161_EN_B <= ap_const_logic_0;
bufo_161_Rst_A <= ap_rst;
bufo_161_Rst_B <= ap_rst;
bufo_161_WEN_A <= ap_const_lv4_0;
bufo_161_WEN_B <= ap_const_lv4_0;
bufo_162_Addr_A <= ap_const_lv32_0;
bufo_162_Addr_B <= ap_const_lv32_0;
bufo_162_Clk_A <= ap_clk;
bufo_162_Clk_B <= ap_clk;
bufo_162_Din_A <= ap_const_lv32_0;
bufo_162_Din_B <= ap_const_lv32_0;
bufo_162_EN_A <= ap_const_logic_0;
bufo_162_EN_B <= ap_const_logic_0;
bufo_162_Rst_A <= ap_rst;
bufo_162_Rst_B <= ap_rst;
bufo_162_WEN_A <= ap_const_lv4_0;
bufo_162_WEN_B <= ap_const_lv4_0;
bufo_163_Addr_A <= ap_const_lv32_0;
bufo_163_Addr_B <= ap_const_lv32_0;
bufo_163_Clk_A <= ap_clk;
bufo_163_Clk_B <= ap_clk;
bufo_163_Din_A <= ap_const_lv32_0;
bufo_163_Din_B <= ap_const_lv32_0;
bufo_163_EN_A <= ap_const_logic_0;
bufo_163_EN_B <= ap_const_logic_0;
bufo_163_Rst_A <= ap_rst;
bufo_163_Rst_B <= ap_rst;
bufo_163_WEN_A <= ap_const_lv4_0;
bufo_163_WEN_B <= ap_const_lv4_0;
bufo_164_Addr_A <= ap_const_lv32_0;
bufo_164_Addr_B <= ap_const_lv32_0;
bufo_164_Clk_A <= ap_clk;
bufo_164_Clk_B <= ap_clk;
bufo_164_Din_A <= ap_const_lv32_0;
bufo_164_Din_B <= ap_const_lv32_0;
bufo_164_EN_A <= ap_const_logic_0;
bufo_164_EN_B <= ap_const_logic_0;
bufo_164_Rst_A <= ap_rst;
bufo_164_Rst_B <= ap_rst;
bufo_164_WEN_A <= ap_const_lv4_0;
bufo_164_WEN_B <= ap_const_lv4_0;
bufo_165_Addr_A <= ap_const_lv32_0;
bufo_165_Addr_B <= ap_const_lv32_0;
bufo_165_Clk_A <= ap_clk;
bufo_165_Clk_B <= ap_clk;
bufo_165_Din_A <= ap_const_lv32_0;
bufo_165_Din_B <= ap_const_lv32_0;
bufo_165_EN_A <= ap_const_logic_0;
bufo_165_EN_B <= ap_const_logic_0;
bufo_165_Rst_A <= ap_rst;
bufo_165_Rst_B <= ap_rst;
bufo_165_WEN_A <= ap_const_lv4_0;
bufo_165_WEN_B <= ap_const_lv4_0;
bufo_166_Addr_A <= ap_const_lv32_0;
bufo_166_Addr_B <= ap_const_lv32_0;
bufo_166_Clk_A <= ap_clk;
bufo_166_Clk_B <= ap_clk;
bufo_166_Din_A <= ap_const_lv32_0;
bufo_166_Din_B <= ap_const_lv32_0;
bufo_166_EN_A <= ap_const_logic_0;
bufo_166_EN_B <= ap_const_logic_0;
bufo_166_Rst_A <= ap_rst;
bufo_166_Rst_B <= ap_rst;
bufo_166_WEN_A <= ap_const_lv4_0;
bufo_166_WEN_B <= ap_const_lv4_0;
bufo_167_Addr_A <= ap_const_lv32_0;
bufo_167_Addr_B <= ap_const_lv32_0;
bufo_167_Clk_A <= ap_clk;
bufo_167_Clk_B <= ap_clk;
bufo_167_Din_A <= ap_const_lv32_0;
bufo_167_Din_B <= ap_const_lv32_0;
bufo_167_EN_A <= ap_const_logic_0;
bufo_167_EN_B <= ap_const_logic_0;
bufo_167_Rst_A <= ap_rst;
bufo_167_Rst_B <= ap_rst;
bufo_167_WEN_A <= ap_const_lv4_0;
bufo_167_WEN_B <= ap_const_lv4_0;
bufo_168_Addr_A <= ap_const_lv32_0;
bufo_168_Addr_B <= ap_const_lv32_0;
bufo_168_Clk_A <= ap_clk;
bufo_168_Clk_B <= ap_clk;
bufo_168_Din_A <= ap_const_lv32_0;
bufo_168_Din_B <= ap_const_lv32_0;
bufo_168_EN_A <= ap_const_logic_0;
bufo_168_EN_B <= ap_const_logic_0;
bufo_168_Rst_A <= ap_rst;
bufo_168_Rst_B <= ap_rst;
bufo_168_WEN_A <= ap_const_lv4_0;
bufo_168_WEN_B <= ap_const_lv4_0;
bufo_169_Addr_A <= ap_const_lv32_0;
bufo_169_Addr_B <= ap_const_lv32_0;
bufo_169_Clk_A <= ap_clk;
bufo_169_Clk_B <= ap_clk;
bufo_169_Din_A <= ap_const_lv32_0;
bufo_169_Din_B <= ap_const_lv32_0;
bufo_169_EN_A <= ap_const_logic_0;
bufo_169_EN_B <= ap_const_logic_0;
bufo_169_Rst_A <= ap_rst;
bufo_169_Rst_B <= ap_rst;
bufo_169_WEN_A <= ap_const_lv4_0;
bufo_169_WEN_B <= ap_const_lv4_0;
bufo_16_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_16_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_16_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_16_Clk_A <= ap_clk;
bufo_16_Din_A <= reg_2580;
bufo_16_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_16_EN_A <= ap_const_logic_1;
else
bufo_16_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_16_Rst_A <= ap_rst;
bufo_16_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_10) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_16_WEN_A <= ap_const_lv4_F;
else
bufo_16_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_170_Addr_A <= ap_const_lv32_0;
bufo_170_Addr_B <= ap_const_lv32_0;
bufo_170_Clk_A <= ap_clk;
bufo_170_Clk_B <= ap_clk;
bufo_170_Din_A <= ap_const_lv32_0;
bufo_170_Din_B <= ap_const_lv32_0;
bufo_170_EN_A <= ap_const_logic_0;
bufo_170_EN_B <= ap_const_logic_0;
bufo_170_Rst_A <= ap_rst;
bufo_170_Rst_B <= ap_rst;
bufo_170_WEN_A <= ap_const_lv4_0;
bufo_170_WEN_B <= ap_const_lv4_0;
bufo_171_Addr_A <= ap_const_lv32_0;
bufo_171_Addr_B <= ap_const_lv32_0;
bufo_171_Clk_A <= ap_clk;
bufo_171_Clk_B <= ap_clk;
bufo_171_Din_A <= ap_const_lv32_0;
bufo_171_Din_B <= ap_const_lv32_0;
bufo_171_EN_A <= ap_const_logic_0;
bufo_171_EN_B <= ap_const_logic_0;
bufo_171_Rst_A <= ap_rst;
bufo_171_Rst_B <= ap_rst;
bufo_171_WEN_A <= ap_const_lv4_0;
bufo_171_WEN_B <= ap_const_lv4_0;
bufo_172_Addr_A <= ap_const_lv32_0;
bufo_172_Addr_B <= ap_const_lv32_0;
bufo_172_Clk_A <= ap_clk;
bufo_172_Clk_B <= ap_clk;
bufo_172_Din_A <= ap_const_lv32_0;
bufo_172_Din_B <= ap_const_lv32_0;
bufo_172_EN_A <= ap_const_logic_0;
bufo_172_EN_B <= ap_const_logic_0;
bufo_172_Rst_A <= ap_rst;
bufo_172_Rst_B <= ap_rst;
bufo_172_WEN_A <= ap_const_lv4_0;
bufo_172_WEN_B <= ap_const_lv4_0;
bufo_173_Addr_A <= ap_const_lv32_0;
bufo_173_Addr_B <= ap_const_lv32_0;
bufo_173_Clk_A <= ap_clk;
bufo_173_Clk_B <= ap_clk;
bufo_173_Din_A <= ap_const_lv32_0;
bufo_173_Din_B <= ap_const_lv32_0;
bufo_173_EN_A <= ap_const_logic_0;
bufo_173_EN_B <= ap_const_logic_0;
bufo_173_Rst_A <= ap_rst;
bufo_173_Rst_B <= ap_rst;
bufo_173_WEN_A <= ap_const_lv4_0;
bufo_173_WEN_B <= ap_const_lv4_0;
bufo_174_Addr_A <= ap_const_lv32_0;
bufo_174_Addr_B <= ap_const_lv32_0;
bufo_174_Clk_A <= ap_clk;
bufo_174_Clk_B <= ap_clk;
bufo_174_Din_A <= ap_const_lv32_0;
bufo_174_Din_B <= ap_const_lv32_0;
bufo_174_EN_A <= ap_const_logic_0;
bufo_174_EN_B <= ap_const_logic_0;
bufo_174_Rst_A <= ap_rst;
bufo_174_Rst_B <= ap_rst;
bufo_174_WEN_A <= ap_const_lv4_0;
bufo_174_WEN_B <= ap_const_lv4_0;
bufo_175_Addr_A <= ap_const_lv32_0;
bufo_175_Addr_B <= ap_const_lv32_0;
bufo_175_Clk_A <= ap_clk;
bufo_175_Clk_B <= ap_clk;
bufo_175_Din_A <= ap_const_lv32_0;
bufo_175_Din_B <= ap_const_lv32_0;
bufo_175_EN_A <= ap_const_logic_0;
bufo_175_EN_B <= ap_const_logic_0;
bufo_175_Rst_A <= ap_rst;
bufo_175_Rst_B <= ap_rst;
bufo_175_WEN_A <= ap_const_lv4_0;
bufo_175_WEN_B <= ap_const_lv4_0;
bufo_176_Addr_A <= ap_const_lv32_0;
bufo_176_Addr_B <= ap_const_lv32_0;
bufo_176_Clk_A <= ap_clk;
bufo_176_Clk_B <= ap_clk;
bufo_176_Din_A <= ap_const_lv32_0;
bufo_176_Din_B <= ap_const_lv32_0;
bufo_176_EN_A <= ap_const_logic_0;
bufo_176_EN_B <= ap_const_logic_0;
bufo_176_Rst_A <= ap_rst;
bufo_176_Rst_B <= ap_rst;
bufo_176_WEN_A <= ap_const_lv4_0;
bufo_176_WEN_B <= ap_const_lv4_0;
bufo_177_Addr_A <= ap_const_lv32_0;
bufo_177_Addr_B <= ap_const_lv32_0;
bufo_177_Clk_A <= ap_clk;
bufo_177_Clk_B <= ap_clk;
bufo_177_Din_A <= ap_const_lv32_0;
bufo_177_Din_B <= ap_const_lv32_0;
bufo_177_EN_A <= ap_const_logic_0;
bufo_177_EN_B <= ap_const_logic_0;
bufo_177_Rst_A <= ap_rst;
bufo_177_Rst_B <= ap_rst;
bufo_177_WEN_A <= ap_const_lv4_0;
bufo_177_WEN_B <= ap_const_lv4_0;
bufo_178_Addr_A <= ap_const_lv32_0;
bufo_178_Addr_B <= ap_const_lv32_0;
bufo_178_Clk_A <= ap_clk;
bufo_178_Clk_B <= ap_clk;
bufo_178_Din_A <= ap_const_lv32_0;
bufo_178_Din_B <= ap_const_lv32_0;
bufo_178_EN_A <= ap_const_logic_0;
bufo_178_EN_B <= ap_const_logic_0;
bufo_178_Rst_A <= ap_rst;
bufo_178_Rst_B <= ap_rst;
bufo_178_WEN_A <= ap_const_lv4_0;
bufo_178_WEN_B <= ap_const_lv4_0;
bufo_179_Addr_A <= ap_const_lv32_0;
bufo_179_Addr_B <= ap_const_lv32_0;
bufo_179_Clk_A <= ap_clk;
bufo_179_Clk_B <= ap_clk;
bufo_179_Din_A <= ap_const_lv32_0;
bufo_179_Din_B <= ap_const_lv32_0;
bufo_179_EN_A <= ap_const_logic_0;
bufo_179_EN_B <= ap_const_logic_0;
bufo_179_Rst_A <= ap_rst;
bufo_179_Rst_B <= ap_rst;
bufo_179_WEN_A <= ap_const_lv4_0;
bufo_179_WEN_B <= ap_const_lv4_0;
bufo_17_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_17_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_17_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_17_Clk_A <= ap_clk;
bufo_17_Din_A <= reg_2580;
bufo_17_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_17_EN_A <= ap_const_logic_1;
else
bufo_17_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_17_Rst_A <= ap_rst;
bufo_17_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_11) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_17_WEN_A <= ap_const_lv4_F;
else
bufo_17_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_180_Addr_A <= ap_const_lv32_0;
bufo_180_Addr_B <= ap_const_lv32_0;
bufo_180_Clk_A <= ap_clk;
bufo_180_Clk_B <= ap_clk;
bufo_180_Din_A <= ap_const_lv32_0;
bufo_180_Din_B <= ap_const_lv32_0;
bufo_180_EN_A <= ap_const_logic_0;
bufo_180_EN_B <= ap_const_logic_0;
bufo_180_Rst_A <= ap_rst;
bufo_180_Rst_B <= ap_rst;
bufo_180_WEN_A <= ap_const_lv4_0;
bufo_180_WEN_B <= ap_const_lv4_0;
bufo_181_Addr_A <= ap_const_lv32_0;
bufo_181_Addr_B <= ap_const_lv32_0;
bufo_181_Clk_A <= ap_clk;
bufo_181_Clk_B <= ap_clk;
bufo_181_Din_A <= ap_const_lv32_0;
bufo_181_Din_B <= ap_const_lv32_0;
bufo_181_EN_A <= ap_const_logic_0;
bufo_181_EN_B <= ap_const_logic_0;
bufo_181_Rst_A <= ap_rst;
bufo_181_Rst_B <= ap_rst;
bufo_181_WEN_A <= ap_const_lv4_0;
bufo_181_WEN_B <= ap_const_lv4_0;
bufo_182_Addr_A <= ap_const_lv32_0;
bufo_182_Addr_B <= ap_const_lv32_0;
bufo_182_Clk_A <= ap_clk;
bufo_182_Clk_B <= ap_clk;
bufo_182_Din_A <= ap_const_lv32_0;
bufo_182_Din_B <= ap_const_lv32_0;
bufo_182_EN_A <= ap_const_logic_0;
bufo_182_EN_B <= ap_const_logic_0;
bufo_182_Rst_A <= ap_rst;
bufo_182_Rst_B <= ap_rst;
bufo_182_WEN_A <= ap_const_lv4_0;
bufo_182_WEN_B <= ap_const_lv4_0;
bufo_183_Addr_A <= ap_const_lv32_0;
bufo_183_Addr_B <= ap_const_lv32_0;
bufo_183_Clk_A <= ap_clk;
bufo_183_Clk_B <= ap_clk;
bufo_183_Din_A <= ap_const_lv32_0;
bufo_183_Din_B <= ap_const_lv32_0;
bufo_183_EN_A <= ap_const_logic_0;
bufo_183_EN_B <= ap_const_logic_0;
bufo_183_Rst_A <= ap_rst;
bufo_183_Rst_B <= ap_rst;
bufo_183_WEN_A <= ap_const_lv4_0;
bufo_183_WEN_B <= ap_const_lv4_0;
bufo_184_Addr_A <= ap_const_lv32_0;
bufo_184_Addr_B <= ap_const_lv32_0;
bufo_184_Clk_A <= ap_clk;
bufo_184_Clk_B <= ap_clk;
bufo_184_Din_A <= ap_const_lv32_0;
bufo_184_Din_B <= ap_const_lv32_0;
bufo_184_EN_A <= ap_const_logic_0;
bufo_184_EN_B <= ap_const_logic_0;
bufo_184_Rst_A <= ap_rst;
bufo_184_Rst_B <= ap_rst;
bufo_184_WEN_A <= ap_const_lv4_0;
bufo_184_WEN_B <= ap_const_lv4_0;
bufo_185_Addr_A <= ap_const_lv32_0;
bufo_185_Addr_B <= ap_const_lv32_0;
bufo_185_Clk_A <= ap_clk;
bufo_185_Clk_B <= ap_clk;
bufo_185_Din_A <= ap_const_lv32_0;
bufo_185_Din_B <= ap_const_lv32_0;
bufo_185_EN_A <= ap_const_logic_0;
bufo_185_EN_B <= ap_const_logic_0;
bufo_185_Rst_A <= ap_rst;
bufo_185_Rst_B <= ap_rst;
bufo_185_WEN_A <= ap_const_lv4_0;
bufo_185_WEN_B <= ap_const_lv4_0;
bufo_186_Addr_A <= ap_const_lv32_0;
bufo_186_Addr_B <= ap_const_lv32_0;
bufo_186_Clk_A <= ap_clk;
bufo_186_Clk_B <= ap_clk;
bufo_186_Din_A <= ap_const_lv32_0;
bufo_186_Din_B <= ap_const_lv32_0;
bufo_186_EN_A <= ap_const_logic_0;
bufo_186_EN_B <= ap_const_logic_0;
bufo_186_Rst_A <= ap_rst;
bufo_186_Rst_B <= ap_rst;
bufo_186_WEN_A <= ap_const_lv4_0;
bufo_186_WEN_B <= ap_const_lv4_0;
bufo_187_Addr_A <= ap_const_lv32_0;
bufo_187_Addr_B <= ap_const_lv32_0;
bufo_187_Clk_A <= ap_clk;
bufo_187_Clk_B <= ap_clk;
bufo_187_Din_A <= ap_const_lv32_0;
bufo_187_Din_B <= ap_const_lv32_0;
bufo_187_EN_A <= ap_const_logic_0;
bufo_187_EN_B <= ap_const_logic_0;
bufo_187_Rst_A <= ap_rst;
bufo_187_Rst_B <= ap_rst;
bufo_187_WEN_A <= ap_const_lv4_0;
bufo_187_WEN_B <= ap_const_lv4_0;
bufo_188_Addr_A <= ap_const_lv32_0;
bufo_188_Addr_B <= ap_const_lv32_0;
bufo_188_Clk_A <= ap_clk;
bufo_188_Clk_B <= ap_clk;
bufo_188_Din_A <= ap_const_lv32_0;
bufo_188_Din_B <= ap_const_lv32_0;
bufo_188_EN_A <= ap_const_logic_0;
bufo_188_EN_B <= ap_const_logic_0;
bufo_188_Rst_A <= ap_rst;
bufo_188_Rst_B <= ap_rst;
bufo_188_WEN_A <= ap_const_lv4_0;
bufo_188_WEN_B <= ap_const_lv4_0;
bufo_189_Addr_A <= ap_const_lv32_0;
bufo_189_Addr_B <= ap_const_lv32_0;
bufo_189_Clk_A <= ap_clk;
bufo_189_Clk_B <= ap_clk;
bufo_189_Din_A <= ap_const_lv32_0;
bufo_189_Din_B <= ap_const_lv32_0;
bufo_189_EN_A <= ap_const_logic_0;
bufo_189_EN_B <= ap_const_logic_0;
bufo_189_Rst_A <= ap_rst;
bufo_189_Rst_B <= ap_rst;
bufo_189_WEN_A <= ap_const_lv4_0;
bufo_189_WEN_B <= ap_const_lv4_0;
bufo_18_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_18_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_18_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_18_Clk_A <= ap_clk;
bufo_18_Din_A <= reg_2580;
bufo_18_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_18_EN_A <= ap_const_logic_1;
else
bufo_18_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_18_Rst_A <= ap_rst;
bufo_18_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_12) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_18_WEN_A <= ap_const_lv4_F;
else
bufo_18_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_190_Addr_A <= ap_const_lv32_0;
bufo_190_Addr_B <= ap_const_lv32_0;
bufo_190_Clk_A <= ap_clk;
bufo_190_Clk_B <= ap_clk;
bufo_190_Din_A <= ap_const_lv32_0;
bufo_190_Din_B <= ap_const_lv32_0;
bufo_190_EN_A <= ap_const_logic_0;
bufo_190_EN_B <= ap_const_logic_0;
bufo_190_Rst_A <= ap_rst;
bufo_190_Rst_B <= ap_rst;
bufo_190_WEN_A <= ap_const_lv4_0;
bufo_190_WEN_B <= ap_const_lv4_0;
bufo_191_Addr_A <= ap_const_lv32_0;
bufo_191_Addr_B <= ap_const_lv32_0;
bufo_191_Clk_A <= ap_clk;
bufo_191_Clk_B <= ap_clk;
bufo_191_Din_A <= ap_const_lv32_0;
bufo_191_Din_B <= ap_const_lv32_0;
bufo_191_EN_A <= ap_const_logic_0;
bufo_191_EN_B <= ap_const_logic_0;
bufo_191_Rst_A <= ap_rst;
bufo_191_Rst_B <= ap_rst;
bufo_191_WEN_A <= ap_const_lv4_0;
bufo_191_WEN_B <= ap_const_lv4_0;
bufo_192_Addr_A <= ap_const_lv32_0;
bufo_192_Addr_B <= ap_const_lv32_0;
bufo_192_Clk_A <= ap_clk;
bufo_192_Clk_B <= ap_clk;
bufo_192_Din_A <= ap_const_lv32_0;
bufo_192_Din_B <= ap_const_lv32_0;
bufo_192_EN_A <= ap_const_logic_0;
bufo_192_EN_B <= ap_const_logic_0;
bufo_192_Rst_A <= ap_rst;
bufo_192_Rst_B <= ap_rst;
bufo_192_WEN_A <= ap_const_lv4_0;
bufo_192_WEN_B <= ap_const_lv4_0;
bufo_193_Addr_A <= ap_const_lv32_0;
bufo_193_Addr_B <= ap_const_lv32_0;
bufo_193_Clk_A <= ap_clk;
bufo_193_Clk_B <= ap_clk;
bufo_193_Din_A <= ap_const_lv32_0;
bufo_193_Din_B <= ap_const_lv32_0;
bufo_193_EN_A <= ap_const_logic_0;
bufo_193_EN_B <= ap_const_logic_0;
bufo_193_Rst_A <= ap_rst;
bufo_193_Rst_B <= ap_rst;
bufo_193_WEN_A <= ap_const_lv4_0;
bufo_193_WEN_B <= ap_const_lv4_0;
bufo_194_Addr_A <= ap_const_lv32_0;
bufo_194_Addr_B <= ap_const_lv32_0;
bufo_194_Clk_A <= ap_clk;
bufo_194_Clk_B <= ap_clk;
bufo_194_Din_A <= ap_const_lv32_0;
bufo_194_Din_B <= ap_const_lv32_0;
bufo_194_EN_A <= ap_const_logic_0;
bufo_194_EN_B <= ap_const_logic_0;
bufo_194_Rst_A <= ap_rst;
bufo_194_Rst_B <= ap_rst;
bufo_194_WEN_A <= ap_const_lv4_0;
bufo_194_WEN_B <= ap_const_lv4_0;
bufo_195_Addr_A <= ap_const_lv32_0;
bufo_195_Addr_B <= ap_const_lv32_0;
bufo_195_Clk_A <= ap_clk;
bufo_195_Clk_B <= ap_clk;
bufo_195_Din_A <= ap_const_lv32_0;
bufo_195_Din_B <= ap_const_lv32_0;
bufo_195_EN_A <= ap_const_logic_0;
bufo_195_EN_B <= ap_const_logic_0;
bufo_195_Rst_A <= ap_rst;
bufo_195_Rst_B <= ap_rst;
bufo_195_WEN_A <= ap_const_lv4_0;
bufo_195_WEN_B <= ap_const_lv4_0;
bufo_196_Addr_A <= ap_const_lv32_0;
bufo_196_Addr_B <= ap_const_lv32_0;
bufo_196_Clk_A <= ap_clk;
bufo_196_Clk_B <= ap_clk;
bufo_196_Din_A <= ap_const_lv32_0;
bufo_196_Din_B <= ap_const_lv32_0;
bufo_196_EN_A <= ap_const_logic_0;
bufo_196_EN_B <= ap_const_logic_0;
bufo_196_Rst_A <= ap_rst;
bufo_196_Rst_B <= ap_rst;
bufo_196_WEN_A <= ap_const_lv4_0;
bufo_196_WEN_B <= ap_const_lv4_0;
bufo_197_Addr_A <= ap_const_lv32_0;
bufo_197_Addr_B <= ap_const_lv32_0;
bufo_197_Clk_A <= ap_clk;
bufo_197_Clk_B <= ap_clk;
bufo_197_Din_A <= ap_const_lv32_0;
bufo_197_Din_B <= ap_const_lv32_0;
bufo_197_EN_A <= ap_const_logic_0;
bufo_197_EN_B <= ap_const_logic_0;
bufo_197_Rst_A <= ap_rst;
bufo_197_Rst_B <= ap_rst;
bufo_197_WEN_A <= ap_const_lv4_0;
bufo_197_WEN_B <= ap_const_lv4_0;
bufo_198_Addr_A <= ap_const_lv32_0;
bufo_198_Addr_B <= ap_const_lv32_0;
bufo_198_Clk_A <= ap_clk;
bufo_198_Clk_B <= ap_clk;
bufo_198_Din_A <= ap_const_lv32_0;
bufo_198_Din_B <= ap_const_lv32_0;
bufo_198_EN_A <= ap_const_logic_0;
bufo_198_EN_B <= ap_const_logic_0;
bufo_198_Rst_A <= ap_rst;
bufo_198_Rst_B <= ap_rst;
bufo_198_WEN_A <= ap_const_lv4_0;
bufo_198_WEN_B <= ap_const_lv4_0;
bufo_199_Addr_A <= ap_const_lv32_0;
bufo_199_Addr_B <= ap_const_lv32_0;
bufo_199_Clk_A <= ap_clk;
bufo_199_Clk_B <= ap_clk;
bufo_199_Din_A <= ap_const_lv32_0;
bufo_199_Din_B <= ap_const_lv32_0;
bufo_199_EN_A <= ap_const_logic_0;
bufo_199_EN_B <= ap_const_logic_0;
bufo_199_Rst_A <= ap_rst;
bufo_199_Rst_B <= ap_rst;
bufo_199_WEN_A <= ap_const_lv4_0;
bufo_199_WEN_B <= ap_const_lv4_0;
bufo_19_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_19_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_19_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_19_Clk_A <= ap_clk;
bufo_19_Din_A <= reg_2580;
bufo_19_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_19_EN_A <= ap_const_logic_1;
else
bufo_19_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_19_Rst_A <= ap_rst;
bufo_19_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_13) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_19_WEN_A <= ap_const_lv4_F;
else
bufo_19_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_1_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_1_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_1_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_1_Clk_A <= ap_clk;
bufo_1_Din_A <= reg_2580;
bufo_1_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_1_EN_A <= ap_const_logic_1;
else
bufo_1_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_1_Rst_A <= ap_rst;
bufo_1_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_1) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_1_WEN_A <= ap_const_lv4_F;
else
bufo_1_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_20_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_20_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_20_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_20_Clk_A <= ap_clk;
bufo_20_Din_A <= reg_2580;
bufo_20_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_20_EN_A <= ap_const_logic_1;
else
bufo_20_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_20_Rst_A <= ap_rst;
bufo_20_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_14) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_20_WEN_A <= ap_const_lv4_F;
else
bufo_20_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_21_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_21_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_21_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_21_Clk_A <= ap_clk;
bufo_21_Din_A <= reg_2580;
bufo_21_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_21_EN_A <= ap_const_logic_1;
else
bufo_21_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_21_Rst_A <= ap_rst;
bufo_21_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_15) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_21_WEN_A <= ap_const_lv4_F;
else
bufo_21_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_22_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_22_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_22_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_22_Clk_A <= ap_clk;
bufo_22_Din_A <= reg_2580;
bufo_22_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_22_EN_A <= ap_const_logic_1;
else
bufo_22_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_22_Rst_A <= ap_rst;
bufo_22_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_16) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_22_WEN_A <= ap_const_lv4_F;
else
bufo_22_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_23_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_23_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_23_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_23_Clk_A <= ap_clk;
bufo_23_Din_A <= reg_2580;
bufo_23_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_23_EN_A <= ap_const_logic_1;
else
bufo_23_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_23_Rst_A <= ap_rst;
bufo_23_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_17) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_23_WEN_A <= ap_const_lv4_F;
else
bufo_23_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_24_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_24_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_24_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_24_Clk_A <= ap_clk;
bufo_24_Din_A <= reg_2580;
bufo_24_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_24_EN_A <= ap_const_logic_1;
else
bufo_24_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_24_Rst_A <= ap_rst;
bufo_24_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_18) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_24_WEN_A <= ap_const_lv4_F;
else
bufo_24_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_25_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_25_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_25_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_25_Clk_A <= ap_clk;
bufo_25_Din_A <= reg_2580;
bufo_25_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_25_EN_A <= ap_const_logic_1;
else
bufo_25_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_25_Rst_A <= ap_rst;
bufo_25_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_19) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_25_WEN_A <= ap_const_lv4_F;
else
bufo_25_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_26_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_26_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_26_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_26_Clk_A <= ap_clk;
bufo_26_Din_A <= reg_2580;
bufo_26_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_26_EN_A <= ap_const_logic_1;
else
bufo_26_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_26_Rst_A <= ap_rst;
bufo_26_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_1A) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_26_WEN_A <= ap_const_lv4_F;
else
bufo_26_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_27_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_27_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_27_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_27_Clk_A <= ap_clk;
bufo_27_Din_A <= reg_2580;
bufo_27_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_27_EN_A <= ap_const_logic_1;
else
bufo_27_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_27_Rst_A <= ap_rst;
bufo_27_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_1B) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_27_WEN_A <= ap_const_lv4_F;
else
bufo_27_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_28_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_28_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_28_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_28_Clk_A <= ap_clk;
bufo_28_Din_A <= reg_2580;
bufo_28_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_28_EN_A <= ap_const_logic_1;
else
bufo_28_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_28_Rst_A <= ap_rst;
bufo_28_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_1C) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_28_WEN_A <= ap_const_lv4_F;
else
bufo_28_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_29_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_29_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_29_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_29_Clk_A <= ap_clk;
bufo_29_Din_A <= reg_2580;
bufo_29_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_29_EN_A <= ap_const_logic_1;
else
bufo_29_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_29_Rst_A <= ap_rst;
bufo_29_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_1D) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_29_WEN_A <= ap_const_lv4_F;
else
bufo_29_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_2_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_2_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_2_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_2_Clk_A <= ap_clk;
bufo_2_Din_A <= reg_2580;
bufo_2_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_2_EN_A <= ap_const_logic_1;
else
bufo_2_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_2_Rst_A <= ap_rst;
bufo_2_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_2) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_2_WEN_A <= ap_const_lv4_F;
else
bufo_2_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_30_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_30_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_30_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_30_Clk_A <= ap_clk;
bufo_30_Din_A <= reg_2580;
bufo_30_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_30_EN_A <= ap_const_logic_1;
else
bufo_30_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_30_Rst_A <= ap_rst;
bufo_30_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_1E) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_30_WEN_A <= ap_const_lv4_F;
else
bufo_30_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_31_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_31_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_31_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_31_Clk_A <= ap_clk;
bufo_31_Din_A <= reg_2580;
bufo_31_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_31_EN_A <= ap_const_logic_1;
else
bufo_31_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_31_Rst_A <= ap_rst;
bufo_31_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_1F) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_31_WEN_A <= ap_const_lv4_F;
else
bufo_31_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_32_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_32_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_32_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_32_Clk_A <= ap_clk;
bufo_32_Din_A <= reg_2580;
bufo_32_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_32_EN_A <= ap_const_logic_1;
else
bufo_32_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_32_Rst_A <= ap_rst;
bufo_32_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_20) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_32_WEN_A <= ap_const_lv4_F;
else
bufo_32_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_33_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_33_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_33_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_33_Clk_A <= ap_clk;
bufo_33_Din_A <= reg_2580;
bufo_33_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_33_EN_A <= ap_const_logic_1;
else
bufo_33_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_33_Rst_A <= ap_rst;
bufo_33_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_21) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_33_WEN_A <= ap_const_lv4_F;
else
bufo_33_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_34_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_34_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_34_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_34_Clk_A <= ap_clk;
bufo_34_Din_A <= reg_2580;
bufo_34_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_34_EN_A <= ap_const_logic_1;
else
bufo_34_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_34_Rst_A <= ap_rst;
bufo_34_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_22) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_34_WEN_A <= ap_const_lv4_F;
else
bufo_34_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_35_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_35_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_35_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_35_Clk_A <= ap_clk;
bufo_35_Din_A <= reg_2580;
bufo_35_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_35_EN_A <= ap_const_logic_1;
else
bufo_35_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_35_Rst_A <= ap_rst;
bufo_35_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_23) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_35_WEN_A <= ap_const_lv4_F;
else
bufo_35_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_36_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_36_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_36_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_36_Clk_A <= ap_clk;
bufo_36_Din_A <= reg_2580;
bufo_36_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_36_EN_A <= ap_const_logic_1;
else
bufo_36_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_36_Rst_A <= ap_rst;
bufo_36_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_24) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_36_WEN_A <= ap_const_lv4_F;
else
bufo_36_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_37_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_37_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_37_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_37_Clk_A <= ap_clk;
bufo_37_Din_A <= reg_2580;
bufo_37_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_37_EN_A <= ap_const_logic_1;
else
bufo_37_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_37_Rst_A <= ap_rst;
bufo_37_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_25) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_37_WEN_A <= ap_const_lv4_F;
else
bufo_37_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_38_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_38_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_38_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_38_Clk_A <= ap_clk;
bufo_38_Din_A <= reg_2580;
bufo_38_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_38_EN_A <= ap_const_logic_1;
else
bufo_38_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_38_Rst_A <= ap_rst;
bufo_38_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_26) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_38_WEN_A <= ap_const_lv4_F;
else
bufo_38_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_39_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_39_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_39_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_39_Clk_A <= ap_clk;
bufo_39_Din_A <= reg_2580;
bufo_39_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_39_EN_A <= ap_const_logic_1;
else
bufo_39_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_39_Rst_A <= ap_rst;
bufo_39_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_27) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_39_WEN_A <= ap_const_lv4_F;
else
bufo_39_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_3_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_3_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_3_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_3_Clk_A <= ap_clk;
bufo_3_Din_A <= reg_2580;
bufo_3_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_3_EN_A <= ap_const_logic_1;
else
bufo_3_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_3_Rst_A <= ap_rst;
bufo_3_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_3) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_3_WEN_A <= ap_const_lv4_F;
else
bufo_3_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_40_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_40_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_40_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_40_Clk_A <= ap_clk;
bufo_40_Din_A <= reg_2580;
bufo_40_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_40_EN_A <= ap_const_logic_1;
else
bufo_40_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_40_Rst_A <= ap_rst;
bufo_40_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_28) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_40_WEN_A <= ap_const_lv4_F;
else
bufo_40_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_41_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_41_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_41_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_41_Clk_A <= ap_clk;
bufo_41_Din_A <= reg_2580;
bufo_41_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_41_EN_A <= ap_const_logic_1;
else
bufo_41_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_41_Rst_A <= ap_rst;
bufo_41_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_29) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_41_WEN_A <= ap_const_lv4_F;
else
bufo_41_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_42_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_42_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_42_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_42_Clk_A <= ap_clk;
bufo_42_Din_A <= reg_2580;
bufo_42_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_42_EN_A <= ap_const_logic_1;
else
bufo_42_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_42_Rst_A <= ap_rst;
bufo_42_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_2A) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_42_WEN_A <= ap_const_lv4_F;
else
bufo_42_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_43_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_43_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_43_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_43_Clk_A <= ap_clk;
bufo_43_Din_A <= reg_2580;
bufo_43_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_43_EN_A <= ap_const_logic_1;
else
bufo_43_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_43_Rst_A <= ap_rst;
bufo_43_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_2B) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_43_WEN_A <= ap_const_lv4_F;
else
bufo_43_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_44_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_44_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_44_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_44_Clk_A <= ap_clk;
bufo_44_Din_A <= reg_2580;
bufo_44_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_44_EN_A <= ap_const_logic_1;
else
bufo_44_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_44_Rst_A <= ap_rst;
bufo_44_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_2C) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_44_WEN_A <= ap_const_lv4_F;
else
bufo_44_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_45_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_45_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_45_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_45_Clk_A <= ap_clk;
bufo_45_Din_A <= reg_2580;
bufo_45_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_45_EN_A <= ap_const_logic_1;
else
bufo_45_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_45_Rst_A <= ap_rst;
bufo_45_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_2D) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_45_WEN_A <= ap_const_lv4_F;
else
bufo_45_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_46_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_46_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_46_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_46_Clk_A <= ap_clk;
bufo_46_Din_A <= reg_2580;
bufo_46_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_46_EN_A <= ap_const_logic_1;
else
bufo_46_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_46_Rst_A <= ap_rst;
bufo_46_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_2E) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_46_WEN_A <= ap_const_lv4_F;
else
bufo_46_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_47_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_47_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_47_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_47_Clk_A <= ap_clk;
bufo_47_Din_A <= reg_2580;
bufo_47_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_47_EN_A <= ap_const_logic_1;
else
bufo_47_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_47_Rst_A <= ap_rst;
bufo_47_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_2F) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_47_WEN_A <= ap_const_lv4_F;
else
bufo_47_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_48_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_48_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_48_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_48_Clk_A <= ap_clk;
bufo_48_Din_A <= reg_2580;
bufo_48_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_48_EN_A <= ap_const_logic_1;
else
bufo_48_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_48_Rst_A <= ap_rst;
bufo_48_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_30) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_48_WEN_A <= ap_const_lv4_F;
else
bufo_48_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_49_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_49_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_49_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_49_Clk_A <= ap_clk;
bufo_49_Din_A <= reg_2580;
bufo_49_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_49_EN_A <= ap_const_logic_1;
else
bufo_49_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_49_Rst_A <= ap_rst;
bufo_49_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_31) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_49_WEN_A <= ap_const_lv4_F;
else
bufo_49_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_4_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_4_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_4_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_4_Clk_A <= ap_clk;
bufo_4_Din_A <= reg_2580;
bufo_4_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_4_EN_A <= ap_const_logic_1;
else
bufo_4_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_4_Rst_A <= ap_rst;
bufo_4_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_4) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_4_WEN_A <= ap_const_lv4_F;
else
bufo_4_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_50_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_50_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_50_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_50_Clk_A <= ap_clk;
bufo_50_Din_A <= reg_2580;
bufo_50_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_50_EN_A <= ap_const_logic_1;
else
bufo_50_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_50_Rst_A <= ap_rst;
bufo_50_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_32) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_50_WEN_A <= ap_const_lv4_F;
else
bufo_50_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_51_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_51_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_51_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_51_Clk_A <= ap_clk;
bufo_51_Din_A <= reg_2580;
bufo_51_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_51_EN_A <= ap_const_logic_1;
else
bufo_51_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_51_Rst_A <= ap_rst;
bufo_51_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_33) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_51_WEN_A <= ap_const_lv4_F;
else
bufo_51_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_52_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_52_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_52_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_52_Clk_A <= ap_clk;
bufo_52_Din_A <= reg_2580;
bufo_52_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_52_EN_A <= ap_const_logic_1;
else
bufo_52_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_52_Rst_A <= ap_rst;
bufo_52_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_34) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_52_WEN_A <= ap_const_lv4_F;
else
bufo_52_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_53_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_53_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_53_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_53_Clk_A <= ap_clk;
bufo_53_Din_A <= reg_2580;
bufo_53_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_53_EN_A <= ap_const_logic_1;
else
bufo_53_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_53_Rst_A <= ap_rst;
bufo_53_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_35) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_53_WEN_A <= ap_const_lv4_F;
else
bufo_53_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_54_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_54_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_54_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_54_Clk_A <= ap_clk;
bufo_54_Din_A <= reg_2580;
bufo_54_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_54_EN_A <= ap_const_logic_1;
else
bufo_54_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_54_Rst_A <= ap_rst;
bufo_54_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_36) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_54_WEN_A <= ap_const_lv4_F;
else
bufo_54_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_55_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_55_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_55_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_55_Clk_A <= ap_clk;
bufo_55_Din_A <= reg_2580;
bufo_55_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_55_EN_A <= ap_const_logic_1;
else
bufo_55_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_55_Rst_A <= ap_rst;
bufo_55_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_37) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_55_WEN_A <= ap_const_lv4_F;
else
bufo_55_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_56_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_56_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_56_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_56_Clk_A <= ap_clk;
bufo_56_Din_A <= reg_2580;
bufo_56_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_56_EN_A <= ap_const_logic_1;
else
bufo_56_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_56_Rst_A <= ap_rst;
bufo_56_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_38) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_56_WEN_A <= ap_const_lv4_F;
else
bufo_56_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_57_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_57_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_57_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_57_Clk_A <= ap_clk;
bufo_57_Din_A <= reg_2580;
bufo_57_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_57_EN_A <= ap_const_logic_1;
else
bufo_57_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_57_Rst_A <= ap_rst;
bufo_57_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_39) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_57_WEN_A <= ap_const_lv4_F;
else
bufo_57_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_58_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_58_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_58_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_58_Clk_A <= ap_clk;
bufo_58_Din_A <= reg_2580;
bufo_58_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_58_EN_A <= ap_const_logic_1;
else
bufo_58_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_58_Rst_A <= ap_rst;
bufo_58_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_3A) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_58_WEN_A <= ap_const_lv4_F;
else
bufo_58_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_59_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_59_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_59_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_59_Clk_A <= ap_clk;
bufo_59_Din_A <= reg_2580;
bufo_59_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_59_EN_A <= ap_const_logic_1;
else
bufo_59_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_59_Rst_A <= ap_rst;
bufo_59_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_3B) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_59_WEN_A <= ap_const_lv4_F;
else
bufo_59_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_5_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_5_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_5_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_5_Clk_A <= ap_clk;
bufo_5_Din_A <= reg_2580;
bufo_5_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_5_EN_A <= ap_const_logic_1;
else
bufo_5_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_5_Rst_A <= ap_rst;
bufo_5_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_5) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_5_WEN_A <= ap_const_lv4_F;
else
bufo_5_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_60_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_60_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_60_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_60_Clk_A <= ap_clk;
bufo_60_Din_A <= reg_2580;
bufo_60_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_60_EN_A <= ap_const_logic_1;
else
bufo_60_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_60_Rst_A <= ap_rst;
bufo_60_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_3C) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_60_WEN_A <= ap_const_lv4_F;
else
bufo_60_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_61_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_61_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_61_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_61_Clk_A <= ap_clk;
bufo_61_Din_A <= reg_2580;
bufo_61_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_61_EN_A <= ap_const_logic_1;
else
bufo_61_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_61_Rst_A <= ap_rst;
bufo_61_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_3D) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_61_WEN_A <= ap_const_lv4_F;
else
bufo_61_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_62_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_62_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_62_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_62_Clk_A <= ap_clk;
bufo_62_Din_A <= reg_2580;
bufo_62_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_62_EN_A <= ap_const_logic_1;
else
bufo_62_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_62_Rst_A <= ap_rst;
bufo_62_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_3E) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_62_WEN_A <= ap_const_lv4_F;
else
bufo_62_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_63_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_63_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_63_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_63_Clk_A <= ap_clk;
bufo_63_Din_A <= reg_2580;
bufo_63_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_63_EN_A <= ap_const_logic_1;
else
bufo_63_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_63_Rst_A <= ap_rst;
bufo_63_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_3F) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_63_WEN_A <= ap_const_lv4_F;
else
bufo_63_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_64_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_64_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_64_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_64_Clk_A <= ap_clk;
bufo_64_Din_A <= reg_2580;
bufo_64_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_64_EN_A <= ap_const_logic_1;
else
bufo_64_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_64_Rst_A <= ap_rst;
bufo_64_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_40) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_64_WEN_A <= ap_const_lv4_F;
else
bufo_64_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_65_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_65_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_65_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_65_Clk_A <= ap_clk;
bufo_65_Din_A <= reg_2580;
bufo_65_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_65_EN_A <= ap_const_logic_1;
else
bufo_65_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_65_Rst_A <= ap_rst;
bufo_65_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_41) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_65_WEN_A <= ap_const_lv4_F;
else
bufo_65_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_66_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_66_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_66_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_66_Clk_A <= ap_clk;
bufo_66_Din_A <= reg_2580;
bufo_66_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_66_EN_A <= ap_const_logic_1;
else
bufo_66_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_66_Rst_A <= ap_rst;
bufo_66_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_42) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_66_WEN_A <= ap_const_lv4_F;
else
bufo_66_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_67_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_67_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_67_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_67_Clk_A <= ap_clk;
bufo_67_Din_A <= reg_2580;
bufo_67_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_67_EN_A <= ap_const_logic_1;
else
bufo_67_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_67_Rst_A <= ap_rst;
bufo_67_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_43) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_67_WEN_A <= ap_const_lv4_F;
else
bufo_67_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_68_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_68_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_68_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_68_Clk_A <= ap_clk;
bufo_68_Din_A <= reg_2580;
bufo_68_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_68_EN_A <= ap_const_logic_1;
else
bufo_68_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_68_Rst_A <= ap_rst;
bufo_68_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_44) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_68_WEN_A <= ap_const_lv4_F;
else
bufo_68_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_69_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_69_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_69_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_69_Clk_A <= ap_clk;
bufo_69_Din_A <= reg_2580;
bufo_69_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_69_EN_A <= ap_const_logic_1;
else
bufo_69_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_69_Rst_A <= ap_rst;
bufo_69_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_45) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_69_WEN_A <= ap_const_lv4_F;
else
bufo_69_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_6_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_6_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_6_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_6_Clk_A <= ap_clk;
bufo_6_Din_A <= reg_2580;
bufo_6_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_6_EN_A <= ap_const_logic_1;
else
bufo_6_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_6_Rst_A <= ap_rst;
bufo_6_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_6) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_6_WEN_A <= ap_const_lv4_F;
else
bufo_6_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_70_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_70_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_70_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_70_Clk_A <= ap_clk;
bufo_70_Din_A <= reg_2580;
bufo_70_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_70_EN_A <= ap_const_logic_1;
else
bufo_70_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_70_Rst_A <= ap_rst;
bufo_70_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_46) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_70_WEN_A <= ap_const_lv4_F;
else
bufo_70_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_71_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_71_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_71_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_71_Clk_A <= ap_clk;
bufo_71_Din_A <= reg_2580;
bufo_71_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_71_EN_A <= ap_const_logic_1;
else
bufo_71_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_71_Rst_A <= ap_rst;
bufo_71_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_47) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_71_WEN_A <= ap_const_lv4_F;
else
bufo_71_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_72_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_72_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_72_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_72_Clk_A <= ap_clk;
bufo_72_Din_A <= reg_2580;
bufo_72_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_72_EN_A <= ap_const_logic_1;
else
bufo_72_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_72_Rst_A <= ap_rst;
bufo_72_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_48) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_72_WEN_A <= ap_const_lv4_F;
else
bufo_72_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_73_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_73_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_73_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_73_Clk_A <= ap_clk;
bufo_73_Din_A <= reg_2580;
bufo_73_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_73_EN_A <= ap_const_logic_1;
else
bufo_73_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_73_Rst_A <= ap_rst;
bufo_73_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_49) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_73_WEN_A <= ap_const_lv4_F;
else
bufo_73_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_74_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_74_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_74_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_74_Clk_A <= ap_clk;
bufo_74_Din_A <= reg_2580;
bufo_74_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_74_EN_A <= ap_const_logic_1;
else
bufo_74_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_74_Rst_A <= ap_rst;
bufo_74_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_4A) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_74_WEN_A <= ap_const_lv4_F;
else
bufo_74_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_75_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_75_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_75_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_75_Clk_A <= ap_clk;
bufo_75_Din_A <= reg_2580;
bufo_75_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_75_EN_A <= ap_const_logic_1;
else
bufo_75_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_75_Rst_A <= ap_rst;
bufo_75_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_4B) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_75_WEN_A <= ap_const_lv4_F;
else
bufo_75_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_76_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_76_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_76_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_76_Clk_A <= ap_clk;
bufo_76_Din_A <= reg_2580;
bufo_76_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_76_EN_A <= ap_const_logic_1;
else
bufo_76_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_76_Rst_A <= ap_rst;
bufo_76_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_4C) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_76_WEN_A <= ap_const_lv4_F;
else
bufo_76_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_77_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_77_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_77_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_77_Clk_A <= ap_clk;
bufo_77_Din_A <= reg_2580;
bufo_77_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_77_EN_A <= ap_const_logic_1;
else
bufo_77_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_77_Rst_A <= ap_rst;
bufo_77_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_4D) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_77_WEN_A <= ap_const_lv4_F;
else
bufo_77_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_78_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_78_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_78_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_78_Clk_A <= ap_clk;
bufo_78_Din_A <= reg_2580;
bufo_78_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_78_EN_A <= ap_const_logic_1;
else
bufo_78_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_78_Rst_A <= ap_rst;
bufo_78_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_4E) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_78_WEN_A <= ap_const_lv4_F;
else
bufo_78_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_79_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_79_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_79_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_79_Clk_A <= ap_clk;
bufo_79_Din_A <= reg_2580;
bufo_79_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_79_EN_A <= ap_const_logic_1;
else
bufo_79_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_79_Rst_A <= ap_rst;
bufo_79_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_4F) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_79_WEN_A <= ap_const_lv4_F;
else
bufo_79_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_7_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_7_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_7_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_7_Clk_A <= ap_clk;
bufo_7_Din_A <= reg_2580;
bufo_7_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_7_EN_A <= ap_const_logic_1;
else
bufo_7_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_7_Rst_A <= ap_rst;
bufo_7_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_7) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_7_WEN_A <= ap_const_lv4_F;
else
bufo_7_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_80_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_80_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_80_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_80_Clk_A <= ap_clk;
bufo_80_Din_A <= reg_2580;
bufo_80_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_80_EN_A <= ap_const_logic_1;
else
bufo_80_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_80_Rst_A <= ap_rst;
bufo_80_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_50) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_80_WEN_A <= ap_const_lv4_F;
else
bufo_80_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_81_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_81_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_81_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_81_Clk_A <= ap_clk;
bufo_81_Din_A <= reg_2580;
bufo_81_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_81_EN_A <= ap_const_logic_1;
else
bufo_81_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_81_Rst_A <= ap_rst;
bufo_81_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_51) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_81_WEN_A <= ap_const_lv4_F;
else
bufo_81_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_82_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_82_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_82_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_82_Clk_A <= ap_clk;
bufo_82_Din_A <= reg_2580;
bufo_82_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_82_EN_A <= ap_const_logic_1;
else
bufo_82_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_82_Rst_A <= ap_rst;
bufo_82_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_52) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_82_WEN_A <= ap_const_lv4_F;
else
bufo_82_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_83_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_83_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_83_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_83_Clk_A <= ap_clk;
bufo_83_Din_A <= reg_2580;
bufo_83_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_83_EN_A <= ap_const_logic_1;
else
bufo_83_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_83_Rst_A <= ap_rst;
bufo_83_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_53) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_83_WEN_A <= ap_const_lv4_F;
else
bufo_83_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_84_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_84_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_84_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_84_Clk_A <= ap_clk;
bufo_84_Din_A <= reg_2580;
bufo_84_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_84_EN_A <= ap_const_logic_1;
else
bufo_84_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_84_Rst_A <= ap_rst;
bufo_84_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_54) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_84_WEN_A <= ap_const_lv4_F;
else
bufo_84_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_85_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_85_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_85_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_85_Clk_A <= ap_clk;
bufo_85_Din_A <= reg_2580;
bufo_85_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_85_EN_A <= ap_const_logic_1;
else
bufo_85_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_85_Rst_A <= ap_rst;
bufo_85_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_55) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_85_WEN_A <= ap_const_lv4_F;
else
bufo_85_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_86_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_86_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_86_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_86_Clk_A <= ap_clk;
bufo_86_Din_A <= reg_2580;
bufo_86_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_86_EN_A <= ap_const_logic_1;
else
bufo_86_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_86_Rst_A <= ap_rst;
bufo_86_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_56) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_86_WEN_A <= ap_const_lv4_F;
else
bufo_86_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_87_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_87_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_87_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_87_Clk_A <= ap_clk;
bufo_87_Din_A <= reg_2580;
bufo_87_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_87_EN_A <= ap_const_logic_1;
else
bufo_87_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_87_Rst_A <= ap_rst;
bufo_87_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_57) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_87_WEN_A <= ap_const_lv4_F;
else
bufo_87_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_88_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_88_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_88_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_88_Clk_A <= ap_clk;
bufo_88_Din_A <= reg_2580;
bufo_88_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_88_EN_A <= ap_const_logic_1;
else
bufo_88_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_88_Rst_A <= ap_rst;
bufo_88_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_58) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_88_WEN_A <= ap_const_lv4_F;
else
bufo_88_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_89_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_89_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_89_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_89_Clk_A <= ap_clk;
bufo_89_Din_A <= reg_2580;
bufo_89_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_89_EN_A <= ap_const_logic_1;
else
bufo_89_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_89_Rst_A <= ap_rst;
bufo_89_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_59) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_89_WEN_A <= ap_const_lv4_F;
else
bufo_89_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_8_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_8_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_8_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_8_Clk_A <= ap_clk;
bufo_8_Din_A <= reg_2580;
bufo_8_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_8_EN_A <= ap_const_logic_1;
else
bufo_8_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_8_Rst_A <= ap_rst;
bufo_8_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_8) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_8_WEN_A <= ap_const_lv4_F;
else
bufo_8_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_90_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_90_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_90_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_90_Clk_A <= ap_clk;
bufo_90_Din_A <= reg_2580;
bufo_90_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_90_EN_A <= ap_const_logic_1;
else
bufo_90_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_90_Rst_A <= ap_rst;
bufo_90_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_5A) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_90_WEN_A <= ap_const_lv4_F;
else
bufo_90_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_91_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_91_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_91_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_91_Clk_A <= ap_clk;
bufo_91_Din_A <= reg_2580;
bufo_91_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_91_EN_A <= ap_const_logic_1;
else
bufo_91_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_91_Rst_A <= ap_rst;
bufo_91_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_5B) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_91_WEN_A <= ap_const_lv4_F;
else
bufo_91_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_92_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_92_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_92_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_92_Clk_A <= ap_clk;
bufo_92_Din_A <= reg_2580;
bufo_92_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_92_EN_A <= ap_const_logic_1;
else
bufo_92_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_92_Rst_A <= ap_rst;
bufo_92_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_5C) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_92_WEN_A <= ap_const_lv4_F;
else
bufo_92_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_93_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_93_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_93_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_93_Clk_A <= ap_clk;
bufo_93_Din_A <= reg_2580;
bufo_93_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_93_EN_A <= ap_const_logic_1;
else
bufo_93_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_93_Rst_A <= ap_rst;
bufo_93_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_5D) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_93_WEN_A <= ap_const_lv4_F;
else
bufo_93_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_94_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_94_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_94_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_94_Clk_A <= ap_clk;
bufo_94_Din_A <= reg_2580;
bufo_94_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_94_EN_A <= ap_const_logic_1;
else
bufo_94_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_94_Rst_A <= ap_rst;
bufo_94_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_5E) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_94_WEN_A <= ap_const_lv4_F;
else
bufo_94_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_95_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_95_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_95_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_95_Clk_A <= ap_clk;
bufo_95_Din_A <= reg_2580;
bufo_95_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_95_EN_A <= ap_const_logic_1;
else
bufo_95_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_95_Rst_A <= ap_rst;
bufo_95_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_5F) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_95_WEN_A <= ap_const_lv4_F;
else
bufo_95_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_96_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_96_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_96_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_96_Clk_A <= ap_clk;
bufo_96_Din_A <= reg_2580;
bufo_96_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_96_EN_A <= ap_const_logic_1;
else
bufo_96_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_96_Rst_A <= ap_rst;
bufo_96_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_60) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_96_WEN_A <= ap_const_lv4_F;
else
bufo_96_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_97_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_97_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_97_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_97_Clk_A <= ap_clk;
bufo_97_Din_A <= reg_2580;
bufo_97_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_97_EN_A <= ap_const_logic_1;
else
bufo_97_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_97_Rst_A <= ap_rst;
bufo_97_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_61) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_97_WEN_A <= ap_const_lv4_F;
else
bufo_97_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_98_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_98_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_98_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_98_Clk_A <= ap_clk;
bufo_98_Din_A <= reg_2580;
bufo_98_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_98_EN_A <= ap_const_logic_1;
else
bufo_98_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_98_Rst_A <= ap_rst;
bufo_98_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_62) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_98_WEN_A <= ap_const_lv4_F;
else
bufo_98_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_99_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_99_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_99_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_99_Clk_A <= ap_clk;
bufo_99_Din_A <= reg_2580;
bufo_99_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_99_EN_A <= ap_const_logic_1;
else
bufo_99_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_99_Rst_A <= ap_rst;
bufo_99_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_63) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_99_WEN_A <= ap_const_lv4_F;
else
bufo_99_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_9_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_9_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_9_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_9_Clk_A <= ap_clk;
bufo_9_Din_A <= reg_2580;
bufo_9_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_9_EN_A <= ap_const_logic_1;
else
bufo_9_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_9_Rst_A <= ap_rst;
bufo_9_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_9) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_9_WEN_A <= ap_const_lv4_F;
else
bufo_9_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufw_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_4(31-1 downto 0)))));
bufw_Addr_A_orig <= phi_mul_reg_2272(32 - 1 downto 0);
bufw_Clk_A <= ap_clk;
bufw_Din_A <= ap_const_lv128_lc_1;
bufw_EN_A_assign_proc : process(ap_CS_fsm_state2)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
bufw_EN_A <= ap_const_logic_1;
else
bufw_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_Rst_A <= ap_rst;
bufw_WEN_A <= ap_const_lv16_0;
grp_fu_2558_p0_assign_proc : process(reg_2580, tmp_s_reg_3561, bufo_load_phi_reg_2296, ap_CS_fsm_state9, ap_CS_fsm_state18, ap_CS_fsm_state27, ap_CS_fsm_state36, ap_CS_fsm_state47)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state47)) then
grp_fu_2558_p0 <= bufo_load_phi_reg_2296;
elsif (((ap_const_logic_1 = ap_CS_fsm_state18) or (ap_const_logic_1 = ap_CS_fsm_state27) or (ap_const_logic_1 = ap_CS_fsm_state36))) then
grp_fu_2558_p0 <= reg_2580;
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
grp_fu_2558_p0 <= tmp_s_reg_3561;
else
grp_fu_2558_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_2558_p1_assign_proc : process(reg_2580, tmp_5_1_reg_3566, tmp_5_2_reg_3571, tmp_5_3_reg_3576, ap_CS_fsm_state9, ap_CS_fsm_state18, ap_CS_fsm_state27, ap_CS_fsm_state36, ap_CS_fsm_state47)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state47)) then
grp_fu_2558_p1 <= reg_2580;
elsif ((ap_const_logic_1 = ap_CS_fsm_state36)) then
grp_fu_2558_p1 <= tmp_5_3_reg_3576;
elsif ((ap_const_logic_1 = ap_CS_fsm_state27)) then
grp_fu_2558_p1 <= tmp_5_2_reg_3571;
elsif ((ap_const_logic_1 = ap_CS_fsm_state18)) then
grp_fu_2558_p1 <= tmp_5_1_reg_3566;
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
grp_fu_2558_p1 <= ap_const_lv32_0;
else
grp_fu_2558_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_2564_p0 <= tmp_reg_3481;
grp_fu_2564_p1 <= tmp_1_reg_3486;
grp_fu_2568_p0 <= tmp_6_reg_3491;
grp_fu_2568_p1 <= tmp_8_reg_3496;
grp_fu_2572_p0 <= tmp_4_reg_3501;
grp_fu_2572_p1 <= tmp_11_reg_3506;
grp_fu_2576_p0 <= tmp_13_reg_3511;
grp_fu_2576_p1 <= tmp_15_reg_3516;
next_mul_fu_2714_p2 <= std_logic_vector(unsigned(ap_const_lv64_19) + unsigned(phi_mul_reg_2272));
tmp_1_fu_2724_p1 <= bufi_Dout_A(32 - 1 downto 0);
tmp_fu_2720_p1 <= bufw_Dout_A(32 - 1 downto 0);
to_b_V_fu_2820_p2 <= std_logic_vector(unsigned(ap_const_lv7_1) + unsigned(p_s_reg_2284));
end behav;
|
--
-- Majority voting filter
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_mv_filter is
generic (
WIDTH : natural := 4;
THRESHOLD : natural := 10
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
SAMPLE : in std_logic; -- Clock enable for sample process
CLEAR : in std_logic; -- Reset process
D : in std_logic; -- Signal input
Q : out std_logic -- Signal D was at least THRESHOLD samples high
);
end slib_mv_filter;
architecture rtl of slib_mv_filter is
-- Signals
signal iCounter : unsigned(WIDTH downto 0); -- Sample counter
signal iQ : std_logic; -- Internal Q
begin
-- Main process
MV_PROC: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= (others => '0');
iQ <= '0';
elsif (CLK'event and CLK='1') then
if (iCounter >= THRESHOLD) then -- Compare with threshold
iQ <= '1';
else
if (SAMPLE = '1' and D = '1') then -- Take sample
iCounter <= iCounter + 1;
end if;
end if;
if (CLEAR = '1') then -- Reset logic
iCounter <= (others => '0');
iQ <= '0';
end if;
end if;
end process;
-- Output signals
Q <= iQ;
end rtl;
|
--
-- Majority voting filter
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_mv_filter is
generic (
WIDTH : natural := 4;
THRESHOLD : natural := 10
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
SAMPLE : in std_logic; -- Clock enable for sample process
CLEAR : in std_logic; -- Reset process
D : in std_logic; -- Signal input
Q : out std_logic -- Signal D was at least THRESHOLD samples high
);
end slib_mv_filter;
architecture rtl of slib_mv_filter is
-- Signals
signal iCounter : unsigned(WIDTH downto 0); -- Sample counter
signal iQ : std_logic; -- Internal Q
begin
-- Main process
MV_PROC: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= (others => '0');
iQ <= '0';
elsif (CLK'event and CLK='1') then
if (iCounter >= THRESHOLD) then -- Compare with threshold
iQ <= '1';
else
if (SAMPLE = '1' and D = '1') then -- Take sample
iCounter <= iCounter + 1;
end if;
end if;
if (CLEAR = '1') then -- Reset logic
iCounter <= (others => '0');
iQ <= '0';
end if;
end if;
end process;
-- Output signals
Q <= iQ;
end rtl;
|
--
-- Majority voting filter
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_mv_filter is
generic (
WIDTH : natural := 4;
THRESHOLD : natural := 10
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
SAMPLE : in std_logic; -- Clock enable for sample process
CLEAR : in std_logic; -- Reset process
D : in std_logic; -- Signal input
Q : out std_logic -- Signal D was at least THRESHOLD samples high
);
end slib_mv_filter;
architecture rtl of slib_mv_filter is
-- Signals
signal iCounter : unsigned(WIDTH downto 0); -- Sample counter
signal iQ : std_logic; -- Internal Q
begin
-- Main process
MV_PROC: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= (others => '0');
iQ <= '0';
elsif (CLK'event and CLK='1') then
if (iCounter >= THRESHOLD) then -- Compare with threshold
iQ <= '1';
else
if (SAMPLE = '1' and D = '1') then -- Take sample
iCounter <= iCounter + 1;
end if;
end if;
if (CLEAR = '1') then -- Reset logic
iCounter <= (others => '0');
iQ <= '0';
end if;
end if;
end process;
-- Output signals
Q <= iQ;
end rtl;
|
--
-- Majority voting filter
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_mv_filter is
generic (
WIDTH : natural := 4;
THRESHOLD : natural := 10
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
SAMPLE : in std_logic; -- Clock enable for sample process
CLEAR : in std_logic; -- Reset process
D : in std_logic; -- Signal input
Q : out std_logic -- Signal D was at least THRESHOLD samples high
);
end slib_mv_filter;
architecture rtl of slib_mv_filter is
-- Signals
signal iCounter : unsigned(WIDTH downto 0); -- Sample counter
signal iQ : std_logic; -- Internal Q
begin
-- Main process
MV_PROC: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= (others => '0');
iQ <= '0';
elsif (CLK'event and CLK='1') then
if (iCounter >= THRESHOLD) then -- Compare with threshold
iQ <= '1';
else
if (SAMPLE = '1' and D = '1') then -- Take sample
iCounter <= iCounter + 1;
end if;
end if;
if (CLEAR = '1') then -- Reset logic
iCounter <= (others => '0');
iQ <= '0';
end if;
end if;
end process;
-- Output signals
Q <= iQ;
end rtl;
|
--
-- Majority voting filter
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_mv_filter is
generic (
WIDTH : natural := 4;
THRESHOLD : natural := 10
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
SAMPLE : in std_logic; -- Clock enable for sample process
CLEAR : in std_logic; -- Reset process
D : in std_logic; -- Signal input
Q : out std_logic -- Signal D was at least THRESHOLD samples high
);
end slib_mv_filter;
architecture rtl of slib_mv_filter is
-- Signals
signal iCounter : unsigned(WIDTH downto 0); -- Sample counter
signal iQ : std_logic; -- Internal Q
begin
-- Main process
MV_PROC: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= (others => '0');
iQ <= '0';
elsif (CLK'event and CLK='1') then
if (iCounter >= THRESHOLD) then -- Compare with threshold
iQ <= '1';
else
if (SAMPLE = '1' and D = '1') then -- Take sample
iCounter <= iCounter + 1;
end if;
end if;
if (CLEAR = '1') then -- Reset logic
iCounter <= (others => '0');
iQ <= '0';
end if;
end if;
end process;
-- Output signals
Q <= iQ;
end rtl;
|
-- (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_ila_0_0 IS
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END DemoInterconnect_ila_0_0;
ARCHITECTURE DemoInterconnect_ila_0_0_arch OF DemoInterconnect_ila_0_0 IS
COMPONENT ila_v6_2_4_ila IS
GENERIC (
C_XLNX_HW_PROBE_INFO : STRING;
C_XDEVICEFAMILY : STRING;
C_CORE_TYPE : INTEGER;
C_CORE_INFO1 : INTEGER;
C_CORE_INFO2 : INTEGER;
C_CAPTURE_TYPE : INTEGER;
C_MU_TYPE : INTEGER;
C_TC_TYPE : INTEGER;
C_NUM_OF_PROBES : INTEGER;
C_DATA_DEPTH : INTEGER;
C_MAJOR_VERSION : INTEGER;
C_MINOR_VERSION : INTEGER;
C_BUILD_REVISION : INTEGER;
C_CORE_MAJOR_VER : INTEGER;
C_CORE_MINOR_VER : INTEGER;
C_XSDB_SLAVE_TYPE : INTEGER;
C_NEXT_SLAVE : INTEGER;
C_CSE_DRV_VER : INTEGER;
C_USE_TEST_REG : INTEGER;
C_PIPE_IFACE : INTEGER;
C_RAM_STYLE : STRING;
C_TRIGOUT_EN : INTEGER;
C_TRIGIN_EN : INTEGER;
C_ADV_TRIGGER : INTEGER;
C_EN_DDR_ILA : INTEGER;
C_EN_STRG_QUAL : INTEGER;
C_INPUT_PIPE_STAGES : INTEGER;
C_EN_TIME_TAG : INTEGER;
C_TIME_TAG_WIDTH : INTEGER;
C_ILA_CLK_FREQ : INTEGER;
C_PROBE0_WIDTH : INTEGER;
C_PROBE1_WIDTH : INTEGER;
C_PROBE2_WIDTH : INTEGER;
C_PROBE3_WIDTH : INTEGER;
C_PROBE4_WIDTH : INTEGER;
C_PROBE5_WIDTH : INTEGER;
C_PROBE6_WIDTH : INTEGER;
C_PROBE7_WIDTH : INTEGER;
C_PROBE8_WIDTH : INTEGER;
C_PROBE9_WIDTH : INTEGER;
C_PROBE10_WIDTH : INTEGER;
C_PROBE11_WIDTH : INTEGER;
C_PROBE12_WIDTH : INTEGER;
C_PROBE13_WIDTH : INTEGER;
C_PROBE14_WIDTH : INTEGER;
C_PROBE15_WIDTH : INTEGER;
C_PROBE16_WIDTH : INTEGER;
C_PROBE17_WIDTH : INTEGER;
C_PROBE18_WIDTH : INTEGER;
C_PROBE19_WIDTH : INTEGER;
C_PROBE20_WIDTH : INTEGER;
C_PROBE21_WIDTH : INTEGER;
C_PROBE22_WIDTH : INTEGER;
C_PROBE23_WIDTH : INTEGER;
C_PROBE24_WIDTH : INTEGER;
C_PROBE25_WIDTH : INTEGER;
C_PROBE26_WIDTH : INTEGER;
C_PROBE27_WIDTH : INTEGER;
C_PROBE28_WIDTH : INTEGER;
C_PROBE29_WIDTH : INTEGER;
C_PROBE30_WIDTH : INTEGER;
C_PROBE31_WIDTH : INTEGER;
C_PROBE32_WIDTH : INTEGER;
C_PROBE33_WIDTH : INTEGER;
C_PROBE34_WIDTH : INTEGER;
C_PROBE35_WIDTH : INTEGER;
C_PROBE36_WIDTH : INTEGER;
C_PROBE37_WIDTH : INTEGER;
C_PROBE38_WIDTH : INTEGER;
C_PROBE39_WIDTH : INTEGER;
C_PROBE40_WIDTH : INTEGER;
C_PROBE41_WIDTH : INTEGER;
C_PROBE42_WIDTH : INTEGER;
C_PROBE43_WIDTH : INTEGER;
C_PROBE44_WIDTH : INTEGER;
C_PROBE45_WIDTH : INTEGER;
C_PROBE46_WIDTH : INTEGER;
C_PROBE47_WIDTH : INTEGER;
C_PROBE48_WIDTH : INTEGER;
C_PROBE49_WIDTH : INTEGER;
C_PROBE50_WIDTH : INTEGER;
C_PROBE51_WIDTH : INTEGER;
C_PROBE52_WIDTH : INTEGER;
C_PROBE53_WIDTH : INTEGER;
C_PROBE54_WIDTH : INTEGER;
C_PROBE55_WIDTH : INTEGER;
C_PROBE56_WIDTH : INTEGER;
C_PROBE57_WIDTH : INTEGER;
C_PROBE58_WIDTH : INTEGER;
C_PROBE59_WIDTH : INTEGER;
C_PROBE60_WIDTH : INTEGER;
C_PROBE61_WIDTH : INTEGER;
C_PROBE62_WIDTH : INTEGER;
C_PROBE63_WIDTH : INTEGER;
C_PROBE64_WIDTH : INTEGER;
C_PROBE65_WIDTH : INTEGER;
C_PROBE66_WIDTH : INTEGER;
C_PROBE67_WIDTH : INTEGER;
C_PROBE68_WIDTH : INTEGER;
C_PROBE69_WIDTH : INTEGER;
C_PROBE70_WIDTH : INTEGER;
C_PROBE71_WIDTH : INTEGER;
C_PROBE72_WIDTH : INTEGER;
C_PROBE73_WIDTH : INTEGER;
C_PROBE74_WIDTH : INTEGER;
C_PROBE75_WIDTH : INTEGER;
C_PROBE76_WIDTH : INTEGER;
C_PROBE77_WIDTH : INTEGER;
C_PROBE78_WIDTH : INTEGER;
C_PROBE79_WIDTH : INTEGER;
C_PROBE80_WIDTH : INTEGER;
C_PROBE81_WIDTH : INTEGER;
C_PROBE82_WIDTH : INTEGER;
C_PROBE83_WIDTH : INTEGER;
C_PROBE84_WIDTH : INTEGER;
C_PROBE85_WIDTH : INTEGER;
C_PROBE86_WIDTH : INTEGER;
C_PROBE87_WIDTH : INTEGER;
C_PROBE88_WIDTH : INTEGER;
C_PROBE89_WIDTH : INTEGER;
C_PROBE90_WIDTH : INTEGER;
C_PROBE91_WIDTH : INTEGER;
C_PROBE92_WIDTH : INTEGER;
C_PROBE93_WIDTH : INTEGER;
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C_PROBE359_MU_CNT : INTEGER;
C_PROBE360_MU_CNT : INTEGER;
C_PROBE361_MU_CNT : INTEGER;
C_PROBE362_MU_CNT : INTEGER;
C_PROBE363_MU_CNT : INTEGER;
C_PROBE364_MU_CNT : INTEGER;
C_PROBE365_MU_CNT : INTEGER;
C_PROBE366_MU_CNT : INTEGER;
C_PROBE367_MU_CNT : INTEGER;
C_PROBE368_MU_CNT : INTEGER;
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C_PROBE370_MU_CNT : INTEGER;
C_PROBE371_MU_CNT : INTEGER;
C_PROBE372_MU_CNT : INTEGER;
C_PROBE373_MU_CNT : INTEGER;
C_PROBE374_MU_CNT : INTEGER;
C_PROBE375_MU_CNT : INTEGER;
C_PROBE376_MU_CNT : INTEGER;
C_PROBE377_MU_CNT : INTEGER;
C_PROBE378_MU_CNT : INTEGER;
C_PROBE379_MU_CNT : INTEGER;
C_PROBE380_MU_CNT : INTEGER;
C_PROBE381_MU_CNT : INTEGER;
C_PROBE382_MU_CNT : INTEGER;
C_PROBE383_MU_CNT : INTEGER;
C_PROBE384_MU_CNT : INTEGER;
C_PROBE385_MU_CNT : INTEGER;
C_PROBE386_MU_CNT : INTEGER;
C_PROBE387_MU_CNT : INTEGER;
C_PROBE388_MU_CNT : INTEGER;
C_PROBE389_MU_CNT : INTEGER;
C_PROBE390_MU_CNT : INTEGER;
C_PROBE391_MU_CNT : INTEGER;
C_PROBE392_MU_CNT : INTEGER;
C_PROBE393_MU_CNT : INTEGER;
C_PROBE394_MU_CNT : INTEGER;
C_PROBE395_MU_CNT : INTEGER;
C_PROBE396_MU_CNT : INTEGER;
C_PROBE397_MU_CNT : INTEGER;
C_PROBE398_MU_CNT : INTEGER;
C_PROBE399_MU_CNT : INTEGER;
C_PROBE400_MU_CNT : INTEGER;
C_PROBE401_MU_CNT : INTEGER;
C_PROBE402_MU_CNT : INTEGER;
C_PROBE403_MU_CNT : INTEGER;
C_PROBE404_MU_CNT : INTEGER;
C_PROBE405_MU_CNT : INTEGER;
C_PROBE406_MU_CNT : INTEGER;
C_PROBE407_MU_CNT : INTEGER;
C_PROBE408_MU_CNT : INTEGER;
C_PROBE409_MU_CNT : INTEGER;
C_PROBE410_MU_CNT : INTEGER;
C_PROBE411_MU_CNT : INTEGER;
C_PROBE412_MU_CNT : INTEGER;
C_PROBE413_MU_CNT : INTEGER;
C_PROBE414_MU_CNT : INTEGER;
C_PROBE415_MU_CNT : INTEGER;
C_PROBE416_MU_CNT : INTEGER;
C_PROBE417_MU_CNT : INTEGER;
C_PROBE418_MU_CNT : INTEGER;
C_PROBE419_MU_CNT : INTEGER;
C_PROBE420_MU_CNT : INTEGER;
C_PROBE421_MU_CNT : INTEGER;
C_PROBE422_MU_CNT : INTEGER;
C_PROBE423_MU_CNT : INTEGER;
C_PROBE424_MU_CNT : INTEGER;
C_PROBE425_MU_CNT : INTEGER;
C_PROBE426_MU_CNT : INTEGER;
C_PROBE427_MU_CNT : INTEGER;
C_PROBE428_MU_CNT : INTEGER;
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C_PROBE430_MU_CNT : INTEGER;
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C_PROBE439_MU_CNT : INTEGER;
C_PROBE440_MU_CNT : INTEGER;
C_PROBE441_MU_CNT : INTEGER;
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C_PROBE443_MU_CNT : INTEGER;
C_PROBE444_MU_CNT : INTEGER;
C_PROBE445_MU_CNT : INTEGER;
C_PROBE446_MU_CNT : INTEGER;
C_PROBE447_MU_CNT : INTEGER;
C_PROBE448_MU_CNT : INTEGER;
C_PROBE449_MU_CNT : INTEGER;
C_PROBE450_MU_CNT : INTEGER;
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C_PROBE452_MU_CNT : INTEGER;
C_PROBE453_MU_CNT : INTEGER;
C_PROBE454_MU_CNT : INTEGER;
C_PROBE455_MU_CNT : INTEGER;
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C_PROBE457_MU_CNT : INTEGER;
C_PROBE458_MU_CNT : INTEGER;
C_PROBE459_MU_CNT : INTEGER;
C_PROBE460_MU_CNT : INTEGER;
C_PROBE461_MU_CNT : INTEGER;
C_PROBE462_MU_CNT : INTEGER;
C_PROBE463_MU_CNT : INTEGER;
C_PROBE464_MU_CNT : INTEGER;
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C_PROBE475_MU_CNT : INTEGER;
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C_PROBE478_MU_CNT : INTEGER;
C_PROBE479_MU_CNT : INTEGER;
C_PROBE480_MU_CNT : INTEGER;
C_PROBE481_MU_CNT : INTEGER;
C_PROBE482_MU_CNT : INTEGER;
C_PROBE483_MU_CNT : INTEGER;
C_PROBE484_MU_CNT : INTEGER;
C_PROBE485_MU_CNT : INTEGER;
C_PROBE486_MU_CNT : INTEGER;
C_PROBE487_MU_CNT : INTEGER;
C_PROBE488_MU_CNT : INTEGER;
C_PROBE489_MU_CNT : INTEGER;
C_PROBE490_MU_CNT : INTEGER;
C_PROBE491_MU_CNT : INTEGER;
C_PROBE492_MU_CNT : INTEGER;
C_PROBE493_MU_CNT : INTEGER;
C_PROBE494_MU_CNT : INTEGER;
C_PROBE495_MU_CNT : INTEGER;
C_PROBE496_MU_CNT : INTEGER;
C_PROBE497_MU_CNT : INTEGER;
C_PROBE498_MU_CNT : INTEGER;
C_PROBE499_MU_CNT : INTEGER;
C_PROBE500_MU_CNT : INTEGER;
C_PROBE501_MU_CNT : INTEGER;
C_PROBE502_MU_CNT : INTEGER;
C_PROBE503_MU_CNT : INTEGER;
C_PROBE504_MU_CNT : INTEGER;
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C_PROBE506_MU_CNT : INTEGER;
C_PROBE507_MU_CNT : INTEGER;
C_PROBE508_MU_CNT : INTEGER;
C_PROBE509_MU_CNT : INTEGER;
C_PROBE510_MU_CNT : INTEGER;
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C_PROBE512_MU_CNT : INTEGER;
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C_PROBE514_MU_CNT : INTEGER;
C_PROBE515_MU_CNT : INTEGER;
C_PROBE516_MU_CNT : INTEGER;
C_PROBE517_MU_CNT : INTEGER;
C_PROBE518_MU_CNT : INTEGER;
C_PROBE519_MU_CNT : INTEGER;
C_PROBE520_MU_CNT : INTEGER;
C_PROBE521_MU_CNT : INTEGER;
C_PROBE522_MU_CNT : INTEGER;
C_PROBE523_MU_CNT : INTEGER;
C_PROBE524_MU_CNT : INTEGER;
C_PROBE525_MU_CNT : INTEGER;
C_PROBE526_MU_CNT : INTEGER;
C_PROBE527_MU_CNT : INTEGER;
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C_PROBE530_MU_CNT : INTEGER;
C_PROBE531_MU_CNT : INTEGER;
C_PROBE532_MU_CNT : INTEGER;
C_PROBE533_MU_CNT : INTEGER;
C_PROBE534_MU_CNT : INTEGER;
C_PROBE535_MU_CNT : INTEGER;
C_PROBE536_MU_CNT : INTEGER;
C_PROBE537_MU_CNT : INTEGER;
C_PROBE538_MU_CNT : INTEGER;
C_PROBE539_MU_CNT : INTEGER;
C_PROBE540_MU_CNT : INTEGER;
C_PROBE541_MU_CNT : INTEGER;
C_PROBE542_MU_CNT : INTEGER;
C_PROBE543_MU_CNT : INTEGER;
C_PROBE544_MU_CNT : INTEGER;
C_PROBE545_MU_CNT : INTEGER;
C_PROBE546_MU_CNT : INTEGER;
C_PROBE547_MU_CNT : INTEGER;
C_PROBE548_MU_CNT : INTEGER;
C_PROBE549_MU_CNT : INTEGER;
C_PROBE550_MU_CNT : INTEGER;
C_PROBE551_MU_CNT : INTEGER;
C_PROBE552_MU_CNT : INTEGER;
C_PROBE553_MU_CNT : INTEGER;
C_PROBE554_MU_CNT : INTEGER;
C_PROBE555_MU_CNT : INTEGER;
C_PROBE556_MU_CNT : INTEGER;
C_PROBE557_MU_CNT : INTEGER;
C_PROBE558_MU_CNT : INTEGER;
C_PROBE559_MU_CNT : INTEGER;
C_PROBE560_MU_CNT : INTEGER;
C_PROBE561_MU_CNT : INTEGER;
C_PROBE562_MU_CNT : INTEGER;
C_PROBE563_MU_CNT : INTEGER;
C_PROBE564_MU_CNT : INTEGER;
C_PROBE565_MU_CNT : INTEGER;
C_PROBE566_MU_CNT : INTEGER;
C_PROBE567_MU_CNT : INTEGER;
C_PROBE568_MU_CNT : INTEGER;
C_PROBE569_MU_CNT : INTEGER;
C_PROBE570_MU_CNT : INTEGER;
C_PROBE571_MU_CNT : INTEGER;
C_PROBE572_MU_CNT : INTEGER;
C_PROBE573_MU_CNT : INTEGER;
C_PROBE574_MU_CNT : INTEGER;
C_PROBE575_MU_CNT : INTEGER;
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C_PROBE577_MU_CNT : INTEGER;
C_PROBE578_MU_CNT : INTEGER;
C_PROBE579_MU_CNT : INTEGER;
C_PROBE580_MU_CNT : INTEGER;
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C_PROBE582_MU_CNT : INTEGER;
C_PROBE583_MU_CNT : INTEGER;
C_PROBE584_MU_CNT : INTEGER;
C_PROBE585_MU_CNT : INTEGER;
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C_PROBE587_MU_CNT : INTEGER;
C_PROBE588_MU_CNT : INTEGER;
C_PROBE589_MU_CNT : INTEGER;
C_PROBE590_MU_CNT : INTEGER;
C_PROBE591_MU_CNT : INTEGER;
C_PROBE592_MU_CNT : INTEGER;
C_PROBE593_MU_CNT : INTEGER;
C_PROBE594_MU_CNT : INTEGER;
C_PROBE595_MU_CNT : INTEGER;
C_PROBE596_MU_CNT : INTEGER;
C_PROBE597_MU_CNT : INTEGER;
C_PROBE598_MU_CNT : INTEGER;
C_PROBE599_MU_CNT : INTEGER;
C_PROBE600_MU_CNT : INTEGER;
C_PROBE601_MU_CNT : INTEGER;
C_PROBE602_MU_CNT : INTEGER;
C_PROBE603_MU_CNT : INTEGER;
C_PROBE604_MU_CNT : INTEGER;
C_PROBE605_MU_CNT : INTEGER;
C_PROBE606_MU_CNT : INTEGER;
C_PROBE607_MU_CNT : INTEGER;
C_PROBE608_MU_CNT : INTEGER;
C_PROBE609_MU_CNT : INTEGER;
C_PROBE610_MU_CNT : INTEGER;
C_PROBE611_MU_CNT : INTEGER;
C_PROBE612_MU_CNT : INTEGER;
C_PROBE613_MU_CNT : INTEGER;
C_PROBE614_MU_CNT : INTEGER;
C_PROBE615_MU_CNT : INTEGER;
C_PROBE616_MU_CNT : INTEGER;
C_PROBE617_MU_CNT : INTEGER;
C_PROBE618_MU_CNT : INTEGER;
C_PROBE619_MU_CNT : INTEGER;
C_PROBE620_MU_CNT : INTEGER;
C_PROBE621_MU_CNT : INTEGER;
C_PROBE622_MU_CNT : INTEGER;
C_PROBE623_MU_CNT : INTEGER;
C_PROBE624_MU_CNT : INTEGER;
C_PROBE625_MU_CNT : INTEGER;
C_PROBE626_MU_CNT : INTEGER;
C_PROBE627_MU_CNT : INTEGER;
C_PROBE628_MU_CNT : INTEGER;
C_PROBE629_MU_CNT : INTEGER;
C_PROBE630_MU_CNT : INTEGER;
C_PROBE631_MU_CNT : INTEGER;
C_PROBE632_MU_CNT : INTEGER;
C_PROBE633_MU_CNT : INTEGER;
C_PROBE634_MU_CNT : INTEGER;
C_PROBE635_MU_CNT : INTEGER;
C_PROBE636_MU_CNT : INTEGER;
C_PROBE637_MU_CNT : INTEGER;
C_PROBE638_MU_CNT : INTEGER;
C_PROBE639_MU_CNT : INTEGER;
C_PROBE640_MU_CNT : INTEGER;
C_PROBE641_MU_CNT : INTEGER;
C_PROBE642_MU_CNT : INTEGER;
C_PROBE643_MU_CNT : INTEGER;
C_PROBE644_MU_CNT : INTEGER;
C_PROBE645_MU_CNT : INTEGER;
C_PROBE646_MU_CNT : INTEGER;
C_PROBE647_MU_CNT : INTEGER;
C_PROBE648_MU_CNT : INTEGER;
C_PROBE649_MU_CNT : INTEGER;
C_PROBE650_MU_CNT : INTEGER;
C_PROBE651_MU_CNT : INTEGER;
C_PROBE652_MU_CNT : INTEGER;
C_PROBE653_MU_CNT : INTEGER;
C_PROBE654_MU_CNT : INTEGER;
C_PROBE655_MU_CNT : INTEGER;
C_PROBE656_MU_CNT : INTEGER;
C_PROBE657_MU_CNT : INTEGER;
C_PROBE658_MU_CNT : INTEGER;
C_PROBE659_MU_CNT : INTEGER;
C_PROBE660_MU_CNT : INTEGER;
C_PROBE661_MU_CNT : INTEGER;
C_PROBE662_MU_CNT : INTEGER;
C_PROBE663_MU_CNT : INTEGER;
C_PROBE664_MU_CNT : INTEGER;
C_PROBE665_MU_CNT : INTEGER;
C_PROBE666_MU_CNT : INTEGER;
C_PROBE667_MU_CNT : INTEGER;
C_PROBE668_MU_CNT : INTEGER;
C_PROBE669_MU_CNT : INTEGER;
C_PROBE670_MU_CNT : INTEGER;
C_PROBE671_MU_CNT : INTEGER;
C_PROBE672_MU_CNT : INTEGER;
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C_PROBE675_MU_CNT : INTEGER;
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C_PROBE683_MU_CNT : INTEGER;
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C_PROBE688_MU_CNT : INTEGER;
C_PROBE689_MU_CNT : INTEGER;
C_PROBE690_MU_CNT : INTEGER;
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C_PROBE692_MU_CNT : INTEGER;
C_PROBE693_MU_CNT : INTEGER;
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C_PROBE700_MU_CNT : INTEGER;
C_PROBE701_MU_CNT : INTEGER;
C_PROBE702_MU_CNT : INTEGER;
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C_PROBE709_MU_CNT : INTEGER;
C_PROBE710_MU_CNT : INTEGER;
C_PROBE711_MU_CNT : INTEGER;
C_PROBE712_MU_CNT : INTEGER;
C_PROBE713_MU_CNT : INTEGER;
C_PROBE714_MU_CNT : INTEGER;
C_PROBE715_MU_CNT : INTEGER;
C_PROBE716_MU_CNT : INTEGER;
C_PROBE717_MU_CNT : INTEGER;
C_PROBE718_MU_CNT : INTEGER;
C_PROBE719_MU_CNT : INTEGER;
C_PROBE720_MU_CNT : INTEGER;
C_PROBE721_MU_CNT : INTEGER;
C_PROBE722_MU_CNT : INTEGER;
C_PROBE723_MU_CNT : INTEGER;
C_PROBE724_MU_CNT : INTEGER;
C_PROBE725_MU_CNT : INTEGER;
C_PROBE726_MU_CNT : INTEGER;
C_PROBE727_MU_CNT : INTEGER;
C_PROBE728_MU_CNT : INTEGER;
C_PROBE729_MU_CNT : INTEGER;
C_PROBE730_MU_CNT : INTEGER;
C_PROBE731_MU_CNT : INTEGER;
C_PROBE732_MU_CNT : INTEGER;
C_PROBE733_MU_CNT : INTEGER;
C_PROBE734_MU_CNT : INTEGER;
C_PROBE735_MU_CNT : INTEGER;
C_PROBE736_MU_CNT : INTEGER;
C_PROBE737_MU_CNT : INTEGER;
C_PROBE738_MU_CNT : INTEGER;
C_PROBE739_MU_CNT : INTEGER;
C_PROBE740_MU_CNT : INTEGER;
C_PROBE741_MU_CNT : INTEGER;
C_PROBE742_MU_CNT : INTEGER;
C_PROBE743_MU_CNT : INTEGER;
C_PROBE744_MU_CNT : INTEGER;
C_PROBE745_MU_CNT : INTEGER;
C_PROBE746_MU_CNT : INTEGER;
C_PROBE747_MU_CNT : INTEGER;
C_PROBE748_MU_CNT : INTEGER;
C_PROBE749_MU_CNT : INTEGER;
C_PROBE750_MU_CNT : INTEGER;
C_PROBE751_MU_CNT : INTEGER;
C_PROBE752_MU_CNT : INTEGER;
C_PROBE753_MU_CNT : INTEGER;
C_PROBE754_MU_CNT : INTEGER;
C_PROBE755_MU_CNT : INTEGER;
C_PROBE756_MU_CNT : INTEGER;
C_PROBE757_MU_CNT : INTEGER;
C_PROBE758_MU_CNT : INTEGER;
C_PROBE759_MU_CNT : INTEGER;
C_PROBE760_MU_CNT : INTEGER;
C_PROBE761_MU_CNT : INTEGER;
C_PROBE762_MU_CNT : INTEGER;
C_PROBE763_MU_CNT : INTEGER;
C_PROBE764_MU_CNT : INTEGER;
C_PROBE765_MU_CNT : INTEGER;
C_PROBE766_MU_CNT : INTEGER;
C_PROBE767_MU_CNT : INTEGER;
C_PROBE768_MU_CNT : INTEGER;
C_PROBE769_MU_CNT : INTEGER;
C_PROBE770_MU_CNT : INTEGER;
C_PROBE771_MU_CNT : INTEGER;
C_PROBE772_MU_CNT : INTEGER;
C_PROBE773_MU_CNT : INTEGER;
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C_PROBE775_MU_CNT : INTEGER;
C_PROBE776_MU_CNT : INTEGER;
C_PROBE777_MU_CNT : INTEGER;
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C_PROBE779_MU_CNT : INTEGER;
C_PROBE780_MU_CNT : INTEGER;
C_PROBE781_MU_CNT : INTEGER;
C_PROBE782_MU_CNT : INTEGER;
C_PROBE783_MU_CNT : INTEGER;
C_PROBE784_MU_CNT : INTEGER;
C_PROBE785_MU_CNT : INTEGER;
C_PROBE786_MU_CNT : INTEGER;
C_PROBE787_MU_CNT : INTEGER;
C_PROBE788_MU_CNT : INTEGER;
C_PROBE789_MU_CNT : INTEGER;
C_PROBE790_MU_CNT : INTEGER;
C_PROBE791_MU_CNT : INTEGER;
C_PROBE792_MU_CNT : INTEGER;
C_PROBE793_MU_CNT : INTEGER;
C_PROBE794_MU_CNT : INTEGER;
C_PROBE795_MU_CNT : INTEGER;
C_PROBE796_MU_CNT : INTEGER;
C_PROBE797_MU_CNT : INTEGER;
C_PROBE798_MU_CNT : INTEGER;
C_PROBE799_MU_CNT : INTEGER;
C_PROBE800_MU_CNT : INTEGER;
C_PROBE801_MU_CNT : INTEGER;
C_PROBE802_MU_CNT : INTEGER;
C_PROBE803_MU_CNT : INTEGER;
C_PROBE804_MU_CNT : INTEGER;
C_PROBE805_MU_CNT : INTEGER;
C_PROBE806_MU_CNT : INTEGER;
C_PROBE807_MU_CNT : INTEGER;
C_PROBE808_MU_CNT : INTEGER;
C_PROBE809_MU_CNT : INTEGER;
C_PROBE810_MU_CNT : INTEGER;
C_PROBE811_MU_CNT : INTEGER;
C_PROBE812_MU_CNT : INTEGER;
C_PROBE813_MU_CNT : INTEGER;
C_PROBE814_MU_CNT : INTEGER;
C_PROBE815_MU_CNT : INTEGER;
C_PROBE816_MU_CNT : INTEGER;
C_PROBE817_MU_CNT : INTEGER;
C_PROBE818_MU_CNT : INTEGER;
C_PROBE819_MU_CNT : INTEGER;
C_PROBE820_MU_CNT : INTEGER;
C_PROBE821_MU_CNT : INTEGER;
C_PROBE822_MU_CNT : INTEGER;
C_PROBE823_MU_CNT : INTEGER;
C_PROBE824_MU_CNT : INTEGER;
C_PROBE825_MU_CNT : INTEGER;
C_PROBE826_MU_CNT : INTEGER;
C_PROBE827_MU_CNT : INTEGER;
C_PROBE828_MU_CNT : INTEGER;
C_PROBE829_MU_CNT : INTEGER;
C_PROBE830_MU_CNT : INTEGER;
C_PROBE831_MU_CNT : INTEGER;
C_PROBE832_MU_CNT : INTEGER;
C_PROBE833_MU_CNT : INTEGER;
C_PROBE834_MU_CNT : INTEGER;
C_PROBE835_MU_CNT : INTEGER;
C_PROBE836_MU_CNT : INTEGER;
C_PROBE837_MU_CNT : INTEGER;
C_PROBE838_MU_CNT : INTEGER;
C_PROBE839_MU_CNT : INTEGER;
C_PROBE840_MU_CNT : INTEGER;
C_PROBE841_MU_CNT : INTEGER;
C_PROBE842_MU_CNT : INTEGER;
C_PROBE843_MU_CNT : INTEGER;
C_PROBE844_MU_CNT : INTEGER;
C_PROBE845_MU_CNT : INTEGER;
C_PROBE846_MU_CNT : INTEGER;
C_PROBE847_MU_CNT : INTEGER;
C_PROBE848_MU_CNT : INTEGER;
C_PROBE849_MU_CNT : INTEGER;
C_PROBE850_MU_CNT : INTEGER;
C_PROBE851_MU_CNT : INTEGER;
C_PROBE852_MU_CNT : INTEGER;
C_PROBE853_MU_CNT : INTEGER;
C_PROBE854_MU_CNT : INTEGER;
C_PROBE855_MU_CNT : INTEGER;
C_PROBE856_MU_CNT : INTEGER;
C_PROBE857_MU_CNT : INTEGER;
C_PROBE858_MU_CNT : INTEGER;
C_PROBE859_MU_CNT : INTEGER;
C_PROBE860_MU_CNT : INTEGER;
C_PROBE861_MU_CNT : INTEGER;
C_PROBE862_MU_CNT : INTEGER;
C_PROBE863_MU_CNT : INTEGER;
C_PROBE864_MU_CNT : INTEGER;
C_PROBE865_MU_CNT : INTEGER;
C_PROBE866_MU_CNT : INTEGER;
C_PROBE867_MU_CNT : INTEGER;
C_PROBE868_MU_CNT : INTEGER;
C_PROBE869_MU_CNT : INTEGER;
C_PROBE870_MU_CNT : INTEGER;
C_PROBE871_MU_CNT : INTEGER;
C_PROBE872_MU_CNT : INTEGER;
C_PROBE873_MU_CNT : INTEGER;
C_PROBE874_MU_CNT : INTEGER;
C_PROBE875_MU_CNT : INTEGER;
C_PROBE876_MU_CNT : INTEGER;
C_PROBE877_MU_CNT : INTEGER;
C_PROBE878_MU_CNT : INTEGER;
C_PROBE879_MU_CNT : INTEGER;
C_PROBE880_MU_CNT : INTEGER;
C_PROBE881_MU_CNT : INTEGER;
C_PROBE882_MU_CNT : INTEGER;
C_PROBE883_MU_CNT : INTEGER;
C_PROBE884_MU_CNT : INTEGER;
C_PROBE885_MU_CNT : INTEGER;
C_PROBE886_MU_CNT : INTEGER;
C_PROBE887_MU_CNT : INTEGER;
C_PROBE888_MU_CNT : INTEGER;
C_PROBE889_MU_CNT : INTEGER;
C_PROBE890_MU_CNT : INTEGER;
C_PROBE891_MU_CNT : INTEGER;
C_PROBE892_MU_CNT : INTEGER;
C_PROBE893_MU_CNT : INTEGER;
C_PROBE894_MU_CNT : INTEGER;
C_PROBE895_MU_CNT : INTEGER;
C_PROBE896_MU_CNT : INTEGER;
C_PROBE897_MU_CNT : INTEGER;
C_PROBE898_MU_CNT : INTEGER;
C_PROBE899_MU_CNT : INTEGER;
C_PROBE900_MU_CNT : INTEGER;
C_PROBE901_MU_CNT : INTEGER;
C_PROBE902_MU_CNT : INTEGER;
C_PROBE903_MU_CNT : INTEGER;
C_PROBE904_MU_CNT : INTEGER;
C_PROBE905_MU_CNT : INTEGER;
C_PROBE906_MU_CNT : INTEGER;
C_PROBE907_MU_CNT : INTEGER;
C_PROBE908_MU_CNT : INTEGER;
C_PROBE909_MU_CNT : INTEGER;
C_PROBE910_MU_CNT : INTEGER;
C_PROBE911_MU_CNT : INTEGER;
C_PROBE912_MU_CNT : INTEGER;
C_PROBE913_MU_CNT : INTEGER;
C_PROBE914_MU_CNT : INTEGER;
C_PROBE915_MU_CNT : INTEGER;
C_PROBE916_MU_CNT : INTEGER;
C_PROBE917_MU_CNT : INTEGER;
C_PROBE918_MU_CNT : INTEGER;
C_PROBE919_MU_CNT : INTEGER;
C_PROBE920_MU_CNT : INTEGER;
C_PROBE921_MU_CNT : INTEGER;
C_PROBE922_MU_CNT : INTEGER;
C_PROBE923_MU_CNT : INTEGER;
C_PROBE924_MU_CNT : INTEGER;
C_PROBE925_MU_CNT : INTEGER;
C_PROBE926_MU_CNT : INTEGER;
C_PROBE927_MU_CNT : INTEGER;
C_PROBE928_MU_CNT : INTEGER;
C_PROBE929_MU_CNT : INTEGER;
C_PROBE930_MU_CNT : INTEGER;
C_PROBE931_MU_CNT : INTEGER;
C_PROBE932_MU_CNT : INTEGER;
C_PROBE933_MU_CNT : INTEGER;
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C_PROBE569_TYPE : INTEGER;
C_PROBE570_TYPE : INTEGER;
C_PROBE571_TYPE : INTEGER;
C_PROBE572_TYPE : INTEGER;
C_PROBE573_TYPE : INTEGER;
C_PROBE574_TYPE : INTEGER;
C_PROBE575_TYPE : INTEGER;
C_PROBE576_TYPE : INTEGER;
C_PROBE577_TYPE : INTEGER;
C_PROBE578_TYPE : INTEGER;
C_PROBE579_TYPE : INTEGER;
C_PROBE580_TYPE : INTEGER;
C_PROBE581_TYPE : INTEGER;
C_PROBE582_TYPE : INTEGER;
C_PROBE583_TYPE : INTEGER;
C_PROBE584_TYPE : INTEGER;
C_PROBE585_TYPE : INTEGER;
C_PROBE586_TYPE : INTEGER;
C_PROBE587_TYPE : INTEGER;
C_PROBE588_TYPE : INTEGER;
C_PROBE589_TYPE : INTEGER;
C_PROBE590_TYPE : INTEGER;
C_PROBE591_TYPE : INTEGER;
C_PROBE592_TYPE : INTEGER;
C_PROBE593_TYPE : INTEGER;
C_PROBE594_TYPE : INTEGER;
C_PROBE595_TYPE : INTEGER;
C_PROBE596_TYPE : INTEGER;
C_PROBE597_TYPE : INTEGER;
C_PROBE598_TYPE : INTEGER;
C_PROBE599_TYPE : INTEGER;
C_PROBE600_TYPE : INTEGER;
C_PROBE601_TYPE : INTEGER;
C_PROBE602_TYPE : INTEGER;
C_PROBE603_TYPE : INTEGER;
C_PROBE604_TYPE : INTEGER;
C_PROBE605_TYPE : INTEGER;
C_PROBE606_TYPE : INTEGER;
C_PROBE607_TYPE : INTEGER;
C_PROBE608_TYPE : INTEGER;
C_PROBE609_TYPE : INTEGER;
C_PROBE610_TYPE : INTEGER;
C_PROBE611_TYPE : INTEGER;
C_PROBE612_TYPE : INTEGER;
C_PROBE613_TYPE : INTEGER;
C_PROBE614_TYPE : INTEGER;
C_PROBE615_TYPE : INTEGER;
C_PROBE616_TYPE : INTEGER;
C_PROBE617_TYPE : INTEGER;
C_PROBE618_TYPE : INTEGER;
C_PROBE619_TYPE : INTEGER;
C_PROBE620_TYPE : INTEGER;
C_PROBE621_TYPE : INTEGER;
C_PROBE622_TYPE : INTEGER;
C_PROBE623_TYPE : INTEGER;
C_PROBE624_TYPE : INTEGER;
C_PROBE625_TYPE : INTEGER;
C_PROBE626_TYPE : INTEGER;
C_PROBE627_TYPE : INTEGER;
C_PROBE628_TYPE : INTEGER;
C_PROBE629_TYPE : INTEGER;
C_PROBE630_TYPE : INTEGER;
C_PROBE631_TYPE : INTEGER;
C_PROBE632_TYPE : INTEGER;
C_PROBE633_TYPE : INTEGER;
C_PROBE634_TYPE : INTEGER;
C_PROBE635_TYPE : INTEGER;
C_PROBE636_TYPE : INTEGER;
C_PROBE637_TYPE : INTEGER;
C_PROBE638_TYPE : INTEGER;
C_PROBE639_TYPE : INTEGER;
C_PROBE640_TYPE : INTEGER;
C_PROBE641_TYPE : INTEGER;
C_PROBE642_TYPE : INTEGER;
C_PROBE643_TYPE : INTEGER;
C_PROBE644_TYPE : INTEGER;
C_PROBE645_TYPE : INTEGER;
C_PROBE646_TYPE : INTEGER;
C_PROBE647_TYPE : INTEGER;
C_PROBE648_TYPE : INTEGER;
C_PROBE649_TYPE : INTEGER;
C_PROBE650_TYPE : INTEGER;
C_PROBE651_TYPE : INTEGER;
C_PROBE652_TYPE : INTEGER;
C_PROBE653_TYPE : INTEGER;
C_PROBE654_TYPE : INTEGER;
C_PROBE655_TYPE : INTEGER;
C_PROBE656_TYPE : INTEGER;
C_PROBE657_TYPE : INTEGER;
C_PROBE658_TYPE : INTEGER;
C_PROBE659_TYPE : INTEGER;
C_PROBE660_TYPE : INTEGER;
C_PROBE661_TYPE : INTEGER;
C_PROBE662_TYPE : INTEGER;
C_PROBE663_TYPE : INTEGER;
C_PROBE664_TYPE : INTEGER;
C_PROBE665_TYPE : INTEGER;
C_PROBE666_TYPE : INTEGER;
C_PROBE667_TYPE : INTEGER;
C_PROBE668_TYPE : INTEGER;
C_PROBE669_TYPE : INTEGER;
C_PROBE670_TYPE : INTEGER;
C_PROBE671_TYPE : INTEGER;
C_PROBE672_TYPE : INTEGER;
C_PROBE673_TYPE : INTEGER;
C_PROBE674_TYPE : INTEGER;
C_PROBE675_TYPE : INTEGER;
C_PROBE676_TYPE : INTEGER;
C_PROBE677_TYPE : INTEGER;
C_PROBE678_TYPE : INTEGER;
C_PROBE679_TYPE : INTEGER;
C_PROBE680_TYPE : INTEGER;
C_PROBE681_TYPE : INTEGER;
C_PROBE682_TYPE : INTEGER;
C_PROBE683_TYPE : INTEGER;
C_PROBE684_TYPE : INTEGER;
C_PROBE685_TYPE : INTEGER;
C_PROBE686_TYPE : INTEGER;
C_PROBE687_TYPE : INTEGER;
C_PROBE688_TYPE : INTEGER;
C_PROBE689_TYPE : INTEGER;
C_PROBE690_TYPE : INTEGER;
C_PROBE691_TYPE : INTEGER;
C_PROBE692_TYPE : INTEGER;
C_PROBE693_TYPE : INTEGER;
C_PROBE694_TYPE : INTEGER;
C_PROBE695_TYPE : INTEGER;
C_PROBE696_TYPE : INTEGER;
C_PROBE697_TYPE : INTEGER;
C_PROBE698_TYPE : INTEGER;
C_PROBE699_TYPE : INTEGER;
C_PROBE700_TYPE : INTEGER;
C_PROBE701_TYPE : INTEGER;
C_PROBE702_TYPE : INTEGER;
C_PROBE703_TYPE : INTEGER;
C_PROBE704_TYPE : INTEGER;
C_PROBE705_TYPE : INTEGER;
C_PROBE706_TYPE : INTEGER;
C_PROBE707_TYPE : INTEGER;
C_PROBE708_TYPE : INTEGER;
C_PROBE709_TYPE : INTEGER;
C_PROBE710_TYPE : INTEGER;
C_PROBE711_TYPE : INTEGER;
C_PROBE712_TYPE : INTEGER;
C_PROBE713_TYPE : INTEGER;
C_PROBE714_TYPE : INTEGER;
C_PROBE715_TYPE : INTEGER;
C_PROBE716_TYPE : INTEGER;
C_PROBE717_TYPE : INTEGER;
C_PROBE718_TYPE : INTEGER;
C_PROBE719_TYPE : INTEGER;
C_PROBE720_TYPE : INTEGER;
C_PROBE721_TYPE : INTEGER;
C_PROBE722_TYPE : INTEGER;
C_PROBE723_TYPE : INTEGER;
C_PROBE724_TYPE : INTEGER;
C_PROBE725_TYPE : INTEGER;
C_PROBE726_TYPE : INTEGER;
C_PROBE727_TYPE : INTEGER;
C_PROBE728_TYPE : INTEGER;
C_PROBE729_TYPE : INTEGER;
C_PROBE730_TYPE : INTEGER;
C_PROBE731_TYPE : INTEGER;
C_PROBE732_TYPE : INTEGER;
C_PROBE733_TYPE : INTEGER;
C_PROBE734_TYPE : INTEGER;
C_PROBE735_TYPE : INTEGER;
C_PROBE736_TYPE : INTEGER;
C_PROBE737_TYPE : INTEGER;
C_PROBE738_TYPE : INTEGER;
C_PROBE739_TYPE : INTEGER;
C_PROBE740_TYPE : INTEGER;
C_PROBE741_TYPE : INTEGER;
C_PROBE742_TYPE : INTEGER;
C_PROBE743_TYPE : INTEGER;
C_PROBE744_TYPE : INTEGER;
C_PROBE745_TYPE : INTEGER;
C_PROBE746_TYPE : INTEGER;
C_PROBE747_TYPE : INTEGER;
C_PROBE748_TYPE : INTEGER;
C_PROBE749_TYPE : INTEGER;
C_PROBE750_TYPE : INTEGER;
C_PROBE751_TYPE : INTEGER;
C_PROBE752_TYPE : INTEGER;
C_PROBE753_TYPE : INTEGER;
C_PROBE754_TYPE : INTEGER;
C_PROBE755_TYPE : INTEGER;
C_PROBE756_TYPE : INTEGER;
C_PROBE757_TYPE : INTEGER;
C_PROBE758_TYPE : INTEGER;
C_PROBE759_TYPE : INTEGER;
C_PROBE760_TYPE : INTEGER;
C_PROBE761_TYPE : INTEGER;
C_PROBE762_TYPE : INTEGER;
C_PROBE763_TYPE : INTEGER;
C_PROBE764_TYPE : INTEGER;
C_PROBE765_TYPE : INTEGER;
C_PROBE766_TYPE : INTEGER;
C_PROBE767_TYPE : INTEGER;
C_PROBE768_TYPE : INTEGER;
C_PROBE769_TYPE : INTEGER;
C_PROBE770_TYPE : INTEGER;
C_PROBE771_TYPE : INTEGER;
C_PROBE772_TYPE : INTEGER;
C_PROBE773_TYPE : INTEGER;
C_PROBE774_TYPE : INTEGER;
C_PROBE775_TYPE : INTEGER;
C_PROBE776_TYPE : INTEGER;
C_PROBE777_TYPE : INTEGER;
C_PROBE778_TYPE : INTEGER;
C_PROBE779_TYPE : INTEGER;
C_PROBE780_TYPE : INTEGER;
C_PROBE781_TYPE : INTEGER;
C_PROBE782_TYPE : INTEGER;
C_PROBE783_TYPE : INTEGER;
C_PROBE784_TYPE : INTEGER;
C_PROBE785_TYPE : INTEGER;
C_PROBE786_TYPE : INTEGER;
C_PROBE787_TYPE : INTEGER;
C_PROBE788_TYPE : INTEGER;
C_PROBE789_TYPE : INTEGER;
C_PROBE790_TYPE : INTEGER;
C_PROBE791_TYPE : INTEGER;
C_PROBE792_TYPE : INTEGER;
C_PROBE793_TYPE : INTEGER;
C_PROBE794_TYPE : INTEGER;
C_PROBE795_TYPE : INTEGER;
C_PROBE796_TYPE : INTEGER;
C_PROBE797_TYPE : INTEGER;
C_PROBE798_TYPE : INTEGER;
C_PROBE799_TYPE : INTEGER;
C_PROBE800_TYPE : INTEGER;
C_PROBE801_TYPE : INTEGER;
C_PROBE802_TYPE : INTEGER;
C_PROBE803_TYPE : INTEGER;
C_PROBE804_TYPE : INTEGER;
C_PROBE805_TYPE : INTEGER;
C_PROBE806_TYPE : INTEGER;
C_PROBE807_TYPE : INTEGER;
C_PROBE808_TYPE : INTEGER;
C_PROBE809_TYPE : INTEGER;
C_PROBE810_TYPE : INTEGER;
C_PROBE811_TYPE : INTEGER;
C_PROBE812_TYPE : INTEGER;
C_PROBE813_TYPE : INTEGER;
C_PROBE814_TYPE : INTEGER;
C_PROBE815_TYPE : INTEGER;
C_PROBE816_TYPE : INTEGER;
C_PROBE817_TYPE : INTEGER;
C_PROBE818_TYPE : INTEGER;
C_PROBE819_TYPE : INTEGER;
C_PROBE820_TYPE : INTEGER;
C_PROBE821_TYPE : INTEGER;
C_PROBE822_TYPE : INTEGER;
C_PROBE823_TYPE : INTEGER;
C_PROBE824_TYPE : INTEGER;
C_PROBE825_TYPE : INTEGER;
C_PROBE826_TYPE : INTEGER;
C_PROBE827_TYPE : INTEGER;
C_PROBE828_TYPE : INTEGER;
C_PROBE829_TYPE : INTEGER;
C_PROBE830_TYPE : INTEGER;
C_PROBE831_TYPE : INTEGER;
C_PROBE832_TYPE : INTEGER;
C_PROBE833_TYPE : INTEGER;
C_PROBE834_TYPE : INTEGER;
C_PROBE835_TYPE : INTEGER;
C_PROBE836_TYPE : INTEGER;
C_PROBE837_TYPE : INTEGER;
C_PROBE838_TYPE : INTEGER;
C_PROBE839_TYPE : INTEGER;
C_PROBE840_TYPE : INTEGER;
C_PROBE841_TYPE : INTEGER;
C_PROBE842_TYPE : INTEGER;
C_PROBE843_TYPE : INTEGER;
C_PROBE844_TYPE : INTEGER;
C_PROBE845_TYPE : INTEGER;
C_PROBE846_TYPE : INTEGER;
C_PROBE847_TYPE : INTEGER;
C_PROBE848_TYPE : INTEGER;
C_PROBE849_TYPE : INTEGER;
C_PROBE850_TYPE : INTEGER;
C_PROBE851_TYPE : INTEGER;
C_PROBE852_TYPE : INTEGER;
C_PROBE853_TYPE : INTEGER;
C_PROBE854_TYPE : INTEGER;
C_PROBE855_TYPE : INTEGER;
C_PROBE856_TYPE : INTEGER;
C_PROBE857_TYPE : INTEGER;
C_PROBE858_TYPE : INTEGER;
C_PROBE859_TYPE : INTEGER;
C_PROBE860_TYPE : INTEGER;
C_PROBE861_TYPE : INTEGER;
C_PROBE862_TYPE : INTEGER;
C_PROBE863_TYPE : INTEGER;
C_PROBE864_TYPE : INTEGER;
C_PROBE865_TYPE : INTEGER;
C_PROBE866_TYPE : INTEGER;
C_PROBE867_TYPE : INTEGER;
C_PROBE868_TYPE : INTEGER;
C_PROBE869_TYPE : INTEGER;
C_PROBE870_TYPE : INTEGER;
C_PROBE871_TYPE : INTEGER;
C_PROBE872_TYPE : INTEGER;
C_PROBE873_TYPE : INTEGER;
C_PROBE874_TYPE : INTEGER;
C_PROBE875_TYPE : INTEGER;
C_PROBE876_TYPE : INTEGER;
C_PROBE877_TYPE : INTEGER;
C_PROBE878_TYPE : INTEGER;
C_PROBE879_TYPE : INTEGER;
C_PROBE880_TYPE : INTEGER;
C_PROBE881_TYPE : INTEGER;
C_PROBE882_TYPE : INTEGER;
C_PROBE883_TYPE : INTEGER;
C_PROBE884_TYPE : INTEGER;
C_PROBE885_TYPE : INTEGER;
C_PROBE886_TYPE : INTEGER;
C_PROBE887_TYPE : INTEGER;
C_PROBE888_TYPE : INTEGER;
C_PROBE889_TYPE : INTEGER;
C_PROBE890_TYPE : INTEGER;
C_PROBE891_TYPE : INTEGER;
C_PROBE892_TYPE : INTEGER;
C_PROBE893_TYPE : INTEGER;
C_PROBE894_TYPE : INTEGER;
C_PROBE895_TYPE : INTEGER;
C_PROBE896_TYPE : INTEGER;
C_PROBE897_TYPE : INTEGER;
C_PROBE898_TYPE : INTEGER;
C_PROBE899_TYPE : INTEGER;
C_PROBE900_TYPE : INTEGER;
C_PROBE901_TYPE : INTEGER;
C_PROBE902_TYPE : INTEGER;
C_PROBE903_TYPE : INTEGER;
C_PROBE904_TYPE : INTEGER;
C_PROBE905_TYPE : INTEGER;
C_PROBE906_TYPE : INTEGER;
C_PROBE907_TYPE : INTEGER;
C_PROBE908_TYPE : INTEGER;
C_PROBE909_TYPE : INTEGER;
C_PROBE910_TYPE : INTEGER;
C_PROBE911_TYPE : INTEGER;
C_PROBE912_TYPE : INTEGER;
C_PROBE913_TYPE : INTEGER;
C_PROBE914_TYPE : INTEGER;
C_PROBE915_TYPE : INTEGER;
C_PROBE916_TYPE : INTEGER;
C_PROBE917_TYPE : INTEGER;
C_PROBE918_TYPE : INTEGER;
C_PROBE919_TYPE : INTEGER;
C_PROBE920_TYPE : INTEGER;
C_PROBE921_TYPE : INTEGER;
C_PROBE922_TYPE : INTEGER;
C_PROBE923_TYPE : INTEGER;
C_PROBE924_TYPE : INTEGER;
C_PROBE925_TYPE : INTEGER;
C_PROBE926_TYPE : INTEGER;
C_PROBE927_TYPE : INTEGER;
C_PROBE928_TYPE : INTEGER;
C_PROBE929_TYPE : INTEGER;
C_PROBE930_TYPE : INTEGER;
C_PROBE931_TYPE : INTEGER;
C_PROBE932_TYPE : INTEGER;
C_PROBE933_TYPE : INTEGER;
C_PROBE934_TYPE : INTEGER;
C_PROBE935_TYPE : INTEGER;
C_PROBE936_TYPE : INTEGER;
C_PROBE937_TYPE : INTEGER;
C_PROBE938_TYPE : INTEGER;
C_PROBE939_TYPE : INTEGER;
C_PROBE940_TYPE : INTEGER;
C_PROBE941_TYPE : INTEGER;
C_PROBE942_TYPE : INTEGER;
C_PROBE943_TYPE : INTEGER;
C_PROBE944_TYPE : INTEGER;
C_PROBE945_TYPE : INTEGER;
C_PROBE946_TYPE : INTEGER;
C_PROBE947_TYPE : INTEGER;
C_PROBE948_TYPE : INTEGER;
C_PROBE949_TYPE : INTEGER;
C_PROBE950_TYPE : INTEGER;
C_PROBE951_TYPE : INTEGER;
C_PROBE952_TYPE : INTEGER;
C_PROBE953_TYPE : INTEGER;
C_PROBE954_TYPE : INTEGER;
C_PROBE955_TYPE : INTEGER;
C_PROBE956_TYPE : INTEGER;
C_PROBE957_TYPE : INTEGER;
C_PROBE958_TYPE : INTEGER;
C_PROBE959_TYPE : INTEGER;
C_PROBE960_TYPE : INTEGER;
C_PROBE961_TYPE : INTEGER;
C_PROBE962_TYPE : INTEGER;
C_PROBE963_TYPE : INTEGER;
C_PROBE964_TYPE : INTEGER;
C_PROBE965_TYPE : INTEGER;
C_PROBE966_TYPE : INTEGER;
C_PROBE967_TYPE : INTEGER;
C_PROBE968_TYPE : INTEGER;
C_PROBE969_TYPE : INTEGER;
C_PROBE970_TYPE : INTEGER;
C_PROBE971_TYPE : INTEGER;
C_PROBE972_TYPE : INTEGER;
C_PROBE973_TYPE : INTEGER;
C_PROBE974_TYPE : INTEGER;
C_PROBE975_TYPE : INTEGER;
C_PROBE976_TYPE : INTEGER;
C_PROBE977_TYPE : INTEGER;
C_PROBE978_TYPE : INTEGER;
C_PROBE979_TYPE : INTEGER;
C_PROBE980_TYPE : INTEGER;
C_PROBE981_TYPE : INTEGER;
C_PROBE982_TYPE : INTEGER;
C_PROBE983_TYPE : INTEGER;
C_PROBE984_TYPE : INTEGER;
C_PROBE985_TYPE : INTEGER;
C_PROBE986_TYPE : INTEGER;
C_PROBE987_TYPE : INTEGER;
C_PROBE988_TYPE : INTEGER;
C_PROBE989_TYPE : INTEGER;
C_PROBE990_TYPE : INTEGER;
C_PROBE991_TYPE : INTEGER;
C_PROBE992_TYPE : INTEGER;
C_PROBE993_TYPE : INTEGER;
C_PROBE994_TYPE : INTEGER;
C_PROBE995_TYPE : INTEGER;
C_PROBE996_TYPE : INTEGER;
C_PROBE997_TYPE : INTEGER;
C_PROBE998_TYPE : INTEGER;
C_PROBE999_TYPE : INTEGER;
C_PROBE1000_TYPE : INTEGER;
C_PROBE1001_TYPE : INTEGER;
C_PROBE1002_TYPE : INTEGER;
C_PROBE1003_TYPE : INTEGER;
C_PROBE1004_TYPE : INTEGER;
C_PROBE1005_TYPE : INTEGER;
C_PROBE1006_TYPE : INTEGER;
C_PROBE1007_TYPE : INTEGER;
C_PROBE1008_TYPE : INTEGER;
C_PROBE1009_TYPE : INTEGER;
C_PROBE1010_TYPE : INTEGER;
C_PROBE1011_TYPE : INTEGER;
C_PROBE1012_TYPE : INTEGER;
C_PROBE1013_TYPE : INTEGER;
C_PROBE1014_TYPE : INTEGER;
C_PROBE1015_TYPE : INTEGER;
C_PROBE1016_TYPE : INTEGER;
C_PROBE1017_TYPE : INTEGER;
C_PROBE1018_TYPE : INTEGER;
C_PROBE1019_TYPE : INTEGER;
C_PROBE1020_TYPE : INTEGER;
C_PROBE1021_TYPE : INTEGER;
C_PROBE1022_TYPE : INTEGER;
C_PROBE1023_TYPE : INTEGER
);
PORT (
clk : IN STD_LOGIC;
sl_iport0 : IN STD_LOGIC_VECTOR (36 downto 0);
sl_oport0 : OUT STD_LOGIC_VECTOR (16 downto 0);
trig_in : IN STD_LOGIC;
trig_in_ack : OUT STD_LOGIC;
trig_out : OUT STD_LOGIC;
trig_out_ack : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe21 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe25 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe26 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe27 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe28 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe29 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe30 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe32 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe33 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe34 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe35 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe36 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe37 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe38 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe39 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe40 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe41 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe42 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe43 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe44 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe45 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe46 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe47 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe48 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe49 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe50 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe51 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe52 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe53 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe54 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe55 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe56 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe57 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe58 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe59 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe60 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe61 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe62 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe63 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe64 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe65 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe66 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe67 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe68 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe69 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe70 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe71 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe72 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe73 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe74 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe75 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe76 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe77 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe78 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe79 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe80 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe81 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe82 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe83 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe84 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe85 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe86 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe87 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe88 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe89 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe90 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe91 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe92 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe93 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe94 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe95 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe96 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe97 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe98 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe99 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe100 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe101 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe102 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe103 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe104 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe105 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe106 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe107 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe108 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe109 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe110 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe111 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe112 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe113 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe114 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe115 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe116 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe117 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe118 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe119 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe120 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe121 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe122 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe123 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe124 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe125 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe126 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe127 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe128 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe129 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe130 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe131 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe132 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe133 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe134 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe135 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe136 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe137 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe138 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe139 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe140 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe141 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe142 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe143 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe144 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe145 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe146 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe147 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe148 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe149 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe150 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe151 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe152 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe153 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe154 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe155 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe156 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe157 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe158 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe159 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe160 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe161 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe162 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe163 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe164 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe165 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe166 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe167 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe168 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe169 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe170 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe171 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe172 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe173 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe174 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe175 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe176 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe177 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe178 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe179 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe180 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe181 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe182 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe183 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe184 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe185 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe186 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe187 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe188 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe189 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe190 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe191 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe192 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe193 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe194 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe195 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe196 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe197 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe198 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe199 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe200 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe201 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe202 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe203 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe204 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe205 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe206 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe207 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe208 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe209 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe210 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe211 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe212 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe213 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe214 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe215 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe216 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe217 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe218 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe219 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe220 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe221 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe222 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe223 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe224 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe225 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe226 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe227 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe228 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe229 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe230 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe231 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe232 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe233 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe234 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe235 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe236 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe237 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe238 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe239 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe240 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe241 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe242 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe243 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe244 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe245 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe246 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe247 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe248 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe249 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe250 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe251 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe252 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe253 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe254 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe255 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe256 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe257 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe258 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe259 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe260 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe261 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe262 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe263 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe264 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe265 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe266 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe267 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe268 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe269 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe270 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe271 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe272 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe273 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe274 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe275 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe276 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe277 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe278 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe279 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe280 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe281 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe282 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe283 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe284 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe285 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe286 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe287 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe288 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe289 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe290 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe291 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe292 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe293 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe294 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe295 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe296 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe297 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe298 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe299 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe300 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe301 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe302 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe303 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe304 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe305 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe306 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe307 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe308 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe309 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe310 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe311 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe312 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe313 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe314 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe315 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe316 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe317 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe318 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe319 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe320 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe321 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe322 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe323 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe324 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe325 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe326 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe327 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe328 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe329 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe330 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe331 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe332 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe333 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe334 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe335 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe336 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe337 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe338 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe339 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe340 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe341 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe342 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe343 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe344 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe345 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe346 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe347 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe348 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe349 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe350 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe351 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe352 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe353 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe354 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe355 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe356 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe357 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe358 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe359 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe360 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe361 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe362 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe363 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe364 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe365 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe366 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe367 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe368 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe369 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe370 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe371 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe372 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe373 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe374 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe375 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe376 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe377 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe378 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe379 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe380 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe381 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe382 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe383 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe384 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe385 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe386 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe387 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe388 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe389 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe390 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe391 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe392 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe393 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe394 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe395 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe396 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe397 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe398 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe399 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe400 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe401 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe402 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe403 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe404 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe405 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe406 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe407 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe408 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe409 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe410 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe411 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe412 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe413 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe414 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe415 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe416 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe417 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe418 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe419 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe420 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe421 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe422 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe423 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe424 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe425 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe426 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe427 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe428 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe429 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe430 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe431 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe432 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe433 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe434 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe435 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe436 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe437 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe438 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe439 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe440 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe441 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe442 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe443 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe444 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe445 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe446 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe447 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe448 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe449 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe450 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe451 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe452 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe453 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe454 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe455 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe456 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe457 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe458 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe459 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe460 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe461 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe462 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe463 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe464 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe465 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe466 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe467 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe468 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe469 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe470 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe471 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe472 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe473 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe474 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe475 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe476 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe477 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe478 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe479 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe480 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe481 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe482 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe483 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe484 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe485 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe486 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe487 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe488 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe489 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe490 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe491 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe492 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe493 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe494 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe495 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe496 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe497 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe498 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe499 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe500 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe501 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe502 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe503 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe504 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe505 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe506 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe507 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe508 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe509 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe510 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe511 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe512 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe513 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe514 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe515 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe516 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe517 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe518 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe519 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe520 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe521 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe522 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe523 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe524 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe525 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe526 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe527 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe528 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe529 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe530 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe531 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe532 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe533 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe534 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe535 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe536 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe537 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe538 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe539 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe540 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe541 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe542 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe543 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe544 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe545 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe546 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe547 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe548 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe549 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe550 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe551 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe552 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe553 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe554 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe555 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe556 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe557 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe558 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe559 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe560 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe561 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe562 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe563 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe564 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe565 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe566 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe567 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe568 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe569 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe570 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe571 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe572 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe573 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe574 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe575 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe576 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe577 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe578 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe579 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe580 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe581 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe582 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe583 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe584 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe585 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe586 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe587 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe588 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe589 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe590 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe591 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe592 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe593 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe594 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe595 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe596 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe597 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe598 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe599 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe600 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe601 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe602 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe603 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe604 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe605 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe606 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe607 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe608 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe609 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe610 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe611 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe612 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe613 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe614 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe615 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe616 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe617 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe618 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe619 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe620 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe621 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe622 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe623 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe624 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe625 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe626 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe627 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe628 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe629 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe630 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe631 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe632 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe633 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe634 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe635 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe636 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe637 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe638 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe639 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe640 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe641 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe642 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe643 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe644 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe645 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe646 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe647 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe648 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe649 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe650 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe651 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe652 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe653 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe654 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe655 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe656 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe657 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe658 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe659 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe660 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe661 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe662 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe663 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe664 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe665 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe666 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe667 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe668 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe669 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe670 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe671 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe672 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe673 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe674 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe675 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe676 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe677 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe678 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe679 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe680 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe681 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe682 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe683 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe684 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe685 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe686 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe687 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe688 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe689 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe690 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe691 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe692 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe693 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe694 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe695 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe696 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe697 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe698 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe699 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe700 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe701 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe702 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe703 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe704 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe705 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe706 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe707 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe708 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe709 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe710 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe711 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe712 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe713 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe714 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe715 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe716 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe717 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe718 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe719 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe720 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe721 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe722 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe723 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe724 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe725 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe726 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe727 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe728 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe729 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe730 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe731 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe732 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe733 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe734 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe735 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe736 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe737 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe738 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe739 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe740 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe741 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe742 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe743 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe744 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe745 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe746 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe747 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe748 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe749 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe750 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe751 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe752 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe753 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe754 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe755 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe756 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe757 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe758 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe759 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe760 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe761 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe762 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe763 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe764 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe765 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe766 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe767 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe768 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe769 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe770 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe771 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe772 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe773 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe774 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe775 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe776 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe777 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe778 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe779 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe780 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe781 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe782 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe783 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe784 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe785 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe786 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe787 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe788 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe789 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe790 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe791 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe792 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe793 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe794 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe795 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe796 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe797 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe798 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe799 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe800 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe801 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe802 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe803 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe804 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe805 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe806 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe807 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe808 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe809 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe810 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe811 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe812 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe813 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe814 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe815 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe816 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe817 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe818 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe819 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe820 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe821 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe822 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe823 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe824 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe825 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe826 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe827 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe828 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe829 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe830 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe831 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe832 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe833 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe834 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe835 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe836 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe837 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe838 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe839 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe840 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe841 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe842 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe843 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe844 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe845 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe846 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe847 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe848 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe849 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe850 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe851 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe852 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe853 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe854 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe855 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe856 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe857 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe858 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe859 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe860 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe861 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe862 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe863 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe864 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe865 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe866 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe867 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe868 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe869 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe870 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe871 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe872 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe873 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe874 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe875 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe876 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe877 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe878 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe879 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe880 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe881 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe882 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe883 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe884 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe885 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe886 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe887 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe888 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe889 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe890 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe891 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe892 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe893 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe894 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe895 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe896 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe897 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe898 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe899 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe900 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe901 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe902 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe903 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe904 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe905 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe906 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe907 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe908 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe909 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe910 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe911 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe912 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe913 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe914 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe915 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe916 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe917 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe918 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe919 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe920 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe921 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe922 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe923 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe924 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe925 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe926 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe927 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe928 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe929 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe930 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe931 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe932 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe933 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe934 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe935 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe936 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe937 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe938 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe939 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe940 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe941 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe942 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe943 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe944 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe945 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe946 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe947 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe948 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe949 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe950 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe951 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe952 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe953 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe954 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe955 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe956 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe957 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe958 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe959 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe960 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe961 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe962 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe963 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe964 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe965 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe966 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe967 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe968 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe969 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe970 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe971 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe972 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe973 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe974 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe975 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe976 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe977 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe978 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe979 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe980 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe981 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe982 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe983 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe984 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe985 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe986 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe987 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe988 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe989 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe990 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe991 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe992 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe993 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe994 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe995 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe996 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe997 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe998 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe999 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1000 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1001 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1002 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1003 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1004 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1005 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1006 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1007 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1008 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1009 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1010 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1011 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1012 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1013 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1014 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1015 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1016 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1017 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1018 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1019 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1020 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1021 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1022 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1023 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT ila_v6_2_4_ila;
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_ila_0_0_arch : ARCHITECTURE IS "yes";
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DemoInterconnect_ila_0_0_arch : ARCHITECTURE IS "ila,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DemoInterconnect_ila_0_0_arch : ARCHITECTURE IS "DemoInterconnect_ila_0_0,ila_v6_2_4_ila,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DemoInterconnect_ila_0_0_arch : ARCHITECTURE IS "DemoInterconnect_ila_0_0,ila,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=ila,x_ipVersion=6.2,x_ipLanguage=VHDL,C_XLNX_HW_PROBE_INFO=DEFAULT,C_XDEVICEFAMILY=artix7,C_CORE_TYPE=1,C_CORE_INFO1=0,C_CORE_INFO2=0,C_CAPTURE_TYPE=0,C_MU_TYPE=0,C_TC_TYPE=0,C_NUM_OF_PROBES=4,C_DATA_DEPTH=8192,C_MAJOR_VERSION=2017,C_MINOR_VERSION=3,C_BUILD_REVISION=0,C_CORE_MAJOR_VER=6,C_CORE_MINOR_VER=2,C_XSDB_SLAVE_TYPE=17,C_NEXT_SLAVE=0,C_CSE_DRV_VER=2,C_USE_TEST_REG=1,C_PIPE_IFACE=1,C_RAM_STYLE=SUBCORE,C_TRIGOUT_EN=0,C_TRIGIN_EN=0,C_ADV_TRIGGER=0,C_EN_DDR_ILA=0,C_DDR_CLK_GEN=0,C_CLK_FREQ=200,C_CLK_PERIOD=5.0,C_CLKFBOUT_MULT_F=10,C_DIVCLK_DIVIDE=3,C_CLKOUT0_DIVIDE_F=10,C_EN_STRG_QUAL=1,C_INPUT_PIPE_STAGES=0,ALL_PROBE_SAME_MU=TRUE,ALL_PROBE_SAME_MU_CNT=2,C_EN_TIME_TAG=0,C_TIME_TAG_WIDTH=32,C_ILA_CLK_FREQ=72000000,C_PROBE0_WIDTH=1,C_PROBE1_WIDTH=8,C_PROBE2_WIDTH=1,C_PROBE3_WIDTH=8,C_PROBE4_WIDTH=1,C_PROBE5_WIDTH=1,C_PROBE6_WIDTH=1,C_PROBE7_WIDTH=1,C_PROBE8_WIDTH=1,C_PROBE9_WIDTH=1,C_PROBE10_WIDTH=1,C_PROBE11_WIDTH=1,C_PROBE12_WIDTH=1,C_PROBE13_WIDTH=1,C_PROBE14_WIDTH=1,C_PROBE15_WIDTH=1,C_PROBE16_WIDTH=1,C_PROBE17_WIDTH=1,C_PROBE18_WIDTH=1,C_PROBE19_WIDTH=1,C_PROBE20_WIDTH=1,C_PROBE21_WIDTH=1,C_PROBE22_WIDTH=1,C_PROBE23_WIDTH=1,C_PROBE24_WIDTH=1,C_PROBE25_WIDTH=1,C_PROBE26_WIDTH=1,C_PROBE27_WIDTH=1,C_PROBE28_WIDTH=1,C_PROBE29_WIDTH=1,C_PROBE30_WIDTH=1,C_PROBE31_WIDTH=1,C_PROBE32_WIDTH=1,C_PROBE33_WIDTH=1,C_PROBE34_WIDTH=1,C_PROBE35_WIDTH=1,C_PROBE36_WIDTH=1,C_PROBE37_WIDTH=1,C_PROBE38_WIDTH=1,C_PROBE39_WIDTH=1,C_PROBE40_WIDTH=1,C_PROBE41_WIDTH=1,C_PROBE42_WIDTH=1,C_PROBE43_WIDTH=1,C_PROBE44_WIDTH=1,C_PROBE45_WIDTH=1,C_PROBE46_WIDTH=1,C_PROBE47_WIDTH=1,C_PROBE48_WIDTH=1,C_PROBE49_WIDTH=1,C_PROBE50_WIDTH=1,C_PROBE51_WIDTH=1,C_PROBE52_WIDTH=1,C_PROBE53_WIDTH=1,"&
"C_PROBE54_WIDTH=1,C_PROBE55_WIDTH=1,C_PROBE56_WIDTH=1,C_PROBE57_WIDTH=1,C_PROBE58_WIDTH=1,C_PROBE59_WIDTH=1,C_PROBE60_WIDTH=1,C_PROBE61_WIDTH=1,C_PROBE62_WIDTH=1,C_PROBE63_WIDTH=1,C_PROBE64_WIDTH=1,C_PROBE65_WIDTH=1,C_PROBE66_WIDTH=1,C_PROBE67_WIDTH=1,C_PROBE68_WIDTH=1,C_PROBE69_WIDTH=1,C_PROBE70_WIDTH=1,C_PROBE71_WIDTH=1,C_PROBE72_WIDTH=1,C_PROBE73_WIDTH=1,C_PROBE74_WIDTH=1,C_PROBE75_WIDTH=1,C_PROBE76_WIDTH=1,C_PROBE77_WIDTH=1,C_PROBE78_WIDTH=1,C_PROBE79_WIDTH=1,C_PROBE80_WIDTH=1,C_PROBE81_WIDTH=1,C_PROBE82_WIDTH=1,C_PROBE83_WIDTH=1,C_PROBE84_WIDTH=1,C_PROBE85_WIDTH=1,C_PROBE86_WIDTH=1,C_PROBE87_WIDTH=1,C_PROBE88_WIDTH=1,C_PROBE89_WIDTH=1,C_PROBE90_WIDTH=1,C_PROBE91_WIDTH=1,C_PROBE92_WIDTH=1,C_PROBE93_WIDTH=1,C_PROBE94_WIDTH=1,C_PROBE95_WIDTH=1,C_PROBE96_WIDTH=1,C_PROBE97_WIDTH=1,C_PROBE98_WIDTH=1,C_PROBE99_WIDTH=1,C_PROBE100_WIDTH=1,C_PROBE101_WIDTH=1,C_PROBE102_WIDTH=1,C_PROBE103_WIDTH=1,C_PROBE104_WIDTH=1,C_PROBE105_WIDTH=1,C_PROBE106_WIDTH=1,C_PROBE107_WIDTH=1,C_PROBE108_WIDTH=1,C_PROBE109_WIDTH=1,C_PROBE110_WIDTH=1,C_PROBE111_WIDTH=1,C_PROBE112_WIDTH=1,C_PROBE113_WIDTH=1,C_PROBE114_WIDTH=1,C_PROBE115_WIDTH=1,C_PROBE116_WIDTH=1,C_PROBE117_WIDTH=1,C_PROBE118_WIDTH=1,C_PROBE119_WIDTH=1,C_PROBE120_WIDTH=1,C_PROBE121_WIDTH=1,C_PROBE122_WIDTH=1,C_PROBE123_WIDTH=1,C_PROBE124_WIDTH=1,C_PROBE125_WIDTH=1,C_PROBE126_WIDTH=1,C_PROBE127_WIDTH=1,C_PROBE128_WIDTH=1,C_PROBE129_WIDTH=1,C_PROBE130_WIDTH=1,C_PROBE131_WIDTH=1,C_PROBE132_WIDTH=1,C_PROBE133_WIDTH=1,C_PROBE134_WIDTH=1,C_PROBE135_WIDTH=1,C_PROBE136_WIDTH=1,C_PROBE137_WIDTH=1,C_PROBE138_WIDTH=1,C_PROBE139_WIDTH=1,C_PROBE140_WIDTH=1,C_PROBE141_WIDTH=1,C_PROBE142_WIDTH=1,C_PROBE143_WIDTH=1,C_PROBE144_WIDTH=1,C_PROBE145_WIDTH=1,C_PROBE146_WIDTH=1,C_PROBE147_WIDTH=1,C_PROBE148_WIDTH=1,C_PROBE149_WIDTH=1,C_PROBE150_WIDTH=1,C_PROBE151_WIDTH=1,C_PROBE152_WIDTH=1,C_PROBE153_WIDTH=1,"&
"C_PROBE154_WIDTH=1,C_PROBE155_WIDTH=1,C_PROBE156_WIDTH=1,C_PROBE157_WIDTH=1,C_PROBE158_WIDTH=1,C_PROBE159_WIDTH=1,C_PROBE160_WIDTH=1,C_PROBE161_WIDTH=1,C_PROBE162_WIDTH=1,C_PROBE163_WIDTH=1,C_PROBE164_WIDTH=1,C_PROBE165_WIDTH=1,C_PROBE166_WIDTH=1,C_PROBE167_WIDTH=1,C_PROBE168_WIDTH=1,C_PROBE169_WIDTH=1,C_PROBE170_WIDTH=1,C_PROBE171_WIDTH=1,C_PROBE172_WIDTH=1,C_PROBE173_WIDTH=1,C_PROBE174_WIDTH=1,C_PROBE175_WIDTH=1,C_PROBE176_WIDTH=1,C_PROBE177_WIDTH=1,C_PROBE178_WIDTH=1,C_PROBE179_WIDTH=1,C_PROBE180_WIDTH=1,C_PROBE181_WIDTH=1,C_PROBE182_WIDTH=1,C_PROBE183_WIDTH=1,C_PROBE184_WIDTH=1,C_PROBE185_WIDTH=1,C_PROBE186_WIDTH=1,C_PROBE187_WIDTH=1,C_PROBE188_WIDTH=1,C_PROBE189_WIDTH=1,C_PROBE190_WIDTH=1,C_PROBE191_WIDTH=1,C_PROBE192_WIDTH=1,C_PROBE193_WIDTH=1,C_PROBE194_WIDTH=1,C_PROBE195_WIDTH=1,C_PROBE196_WIDTH=1,C_PROBE197_WIDTH=1,C_PROBE198_WIDTH=1,C_PROBE199_WIDTH=1,C_PROBE200_WIDTH=1,C_PROBE201_WIDTH=1,C_PROBE202_WIDTH=1,C_PROBE203_WIDTH=1,C_PROBE204_WIDTH=1,C_PROBE205_WIDTH=1,C_PROBE206_WIDTH=1,C_PROBE207_WIDTH=1,C_PROBE208_WIDTH=1,C_PROBE209_WIDTH=1,C_PROBE210_WIDTH=1,C_PROBE211_WIDTH=1,C_PROBE212_WIDTH=1,C_PROBE213_WIDTH=1,C_PROBE214_WIDTH=1,C_PROBE215_WIDTH=1,C_PROBE216_WIDTH=1,C_PROBE217_WIDTH=1,C_PROBE218_WIDTH=1,C_PROBE219_WIDTH=1,C_PROBE220_WIDTH=1,C_PROBE221_WIDTH=1,C_PROBE222_WIDTH=1,C_PROBE223_WIDTH=1,C_PROBE224_WIDTH=1,C_PROBE225_WIDTH=1,C_PROBE226_WIDTH=1,C_PROBE227_WIDTH=1,C_PROBE228_WIDTH=1,C_PROBE229_WIDTH=1,C_PROBE230_WIDTH=1,C_PROBE231_WIDTH=1,C_PROBE232_WIDTH=1,C_PROBE233_WIDTH=1,C_PROBE234_WIDTH=1,C_PROBE235_WIDTH=1,C_PROBE236_WIDTH=1,C_PROBE237_WIDTH=1,C_PROBE238_WIDTH=1,C_PROBE239_WIDTH=1,C_PROBE240_WIDTH=1,C_PROBE241_WIDTH=1,C_PROBE242_WIDTH=1,C_PROBE243_WIDTH=1,C_PROBE244_WIDTH=1,C_PROBE245_WIDTH=1,C_PROBE246_WIDTH=1,C_PROBE247_WIDTH=1,C_PROBE248_WIDTH=1,C_PROBE249_WIDTH=1,C_PROBE250_WIDTH=1,C_PROBE251_WIDTH=1,C_PROBE252_WIDTH=1,C_PROBE253_WIDTH=1,"&
"C_PROBE254_WIDTH=1,C_PROBE255_WIDTH=1,C_PROBE256_WIDTH=1,C_PROBE257_WIDTH=1,C_PROBE258_WIDTH=1,C_PROBE259_WIDTH=1,C_PROBE260_WIDTH=1,C_PROBE261_WIDTH=1,C_PROBE262_WIDTH=1,C_PROBE263_WIDTH=1,C_PROBE264_WIDTH=1,C_PROBE265_WIDTH=1,C_PROBE266_WIDTH=1,C_PROBE267_WIDTH=1,C_PROBE268_WIDTH=1,C_PROBE269_WIDTH=1,C_PROBE270_WIDTH=1,C_PROBE271_WIDTH=1,C_PROBE272_WIDTH=1,C_PROBE273_WIDTH=1,C_PROBE274_WIDTH=1,C_PROBE275_WIDTH=1,C_PROBE276_WIDTH=1,C_PROBE277_WIDTH=1,C_PROBE278_WIDTH=1,C_PROBE279_WIDTH=1,C_PROBE280_WIDTH=1,C_PROBE281_WIDTH=1,C_PROBE282_WIDTH=1,C_PROBE283_WIDTH=1,C_PROBE284_WIDTH=1,C_PROBE285_WIDTH=1,C_PROBE286_WIDTH=1,C_PROBE287_WIDTH=1,C_PROBE288_WIDTH=1,C_PROBE289_WIDTH=1,C_PROBE290_WIDTH=1,C_PROBE291_WIDTH=1,C_PROBE292_WIDTH=1,C_PROBE293_WIDTH=1,C_PROBE294_WIDTH=1,C_PROBE295_WIDTH=1,C_PROBE296_WIDTH=1,C_PROBE297_WIDTH=1,C_PROBE298_WIDTH=1,C_PROBE299_WIDTH=1,C_PROBE300_WIDTH=1,C_PROBE301_WIDTH=1,C_PROBE302_WIDTH=1,C_PROBE303_WIDTH=1,C_PROBE304_WIDTH=1,C_PROBE305_WIDTH=1,C_PROBE306_WIDTH=1,C_PROBE307_WIDTH=1,C_PROBE308_WIDTH=1,C_PROBE309_WIDTH=1,C_PROBE310_WIDTH=1,C_PROBE311_WIDTH=1,C_PROBE312_WIDTH=1,C_PROBE313_WIDTH=1,C_PROBE314_WIDTH=1,C_PROBE315_WIDTH=1,C_PROBE316_WIDTH=1,C_PROBE317_WIDTH=1,C_PROBE318_WIDTH=1,C_PROBE319_WIDTH=1,C_PROBE320_WIDTH=1,C_PROBE321_WIDTH=1,C_PROBE322_WIDTH=1,C_PROBE323_WIDTH=1,C_PROBE324_WIDTH=1,C_PROBE325_WIDTH=1,C_PROBE326_WIDTH=1,C_PROBE327_WIDTH=1,C_PROBE328_WIDTH=1,C_PROBE329_WIDTH=1,C_PROBE330_WIDTH=1,C_PROBE331_WIDTH=1,C_PROBE332_WIDTH=1,C_PROBE333_WIDTH=1,C_PROBE334_WIDTH=1,C_PROBE335_WIDTH=1,C_PROBE336_WIDTH=1,C_PROBE337_WIDTH=1,C_PROBE338_WIDTH=1,C_PROBE339_WIDTH=1,C_PROBE340_WIDTH=1,C_PROBE341_WIDTH=1,C_PROBE342_WIDTH=1,C_PROBE343_WIDTH=1,C_PROBE344_WIDTH=1,C_PROBE345_WIDTH=1,C_PROBE346_WIDTH=1,C_PROBE347_WIDTH=1,C_PROBE348_WIDTH=1,C_PROBE349_WIDTH=1,C_PROBE350_WIDTH=1,C_PROBE351_WIDTH=1,C_PROBE352_WIDTH=1,C_PROBE353_WIDTH=1,"&
"C_PROBE354_WIDTH=1,C_PROBE355_WIDTH=1,C_PROBE356_WIDTH=1,C_PROBE357_WIDTH=1,C_PROBE358_WIDTH=1,C_PROBE359_WIDTH=1,C_PROBE360_WIDTH=1,C_PROBE361_WIDTH=1,C_PROBE362_WIDTH=1,C_PROBE363_WIDTH=1,C_PROBE364_WIDTH=1,C_PROBE365_WIDTH=1,C_PROBE366_WIDTH=1,C_PROBE367_WIDTH=1,C_PROBE368_WIDTH=1,C_PROBE369_WIDTH=1,C_PROBE370_WIDTH=1,C_PROBE371_WIDTH=1,C_PROBE372_WIDTH=1,C_PROBE373_WIDTH=1,C_PROBE374_WIDTH=1,C_PROBE375_WIDTH=1,C_PROBE376_WIDTH=1,C_PROBE377_WIDTH=1,C_PROBE378_WIDTH=1,C_PROBE379_WIDTH=1,C_PROBE380_WIDTH=1,C_PROBE381_WIDTH=1,C_PROBE382_WIDTH=1,C_PROBE383_WIDTH=1,C_PROBE384_WIDTH=1,C_PROBE385_WIDTH=1,C_PROBE386_WIDTH=1,C_PROBE387_WIDTH=1,C_PROBE388_WIDTH=1,C_PROBE389_WIDTH=1,C_PROBE390_WIDTH=1,C_PROBE391_WIDTH=1,C_PROBE392_WIDTH=1,C_PROBE393_WIDTH=1,C_PROBE394_WIDTH=1,C_PROBE395_WIDTH=1,C_PROBE396_WIDTH=1,C_PROBE397_WIDTH=1,C_PROBE398_WIDTH=1,C_PROBE399_WIDTH=1,C_PROBE400_WIDTH=1,C_PROBE401_WIDTH=1,C_PROBE402_WIDTH=1,C_PROBE403_WIDTH=1,C_PROBE404_WIDTH=1,C_PROBE405_WIDTH=1,C_PROBE406_WIDTH=1,C_PROBE407_WIDTH=1,C_PROBE408_WIDTH=1,C_PROBE409_WIDTH=1,C_PROBE410_WIDTH=1,C_PROBE411_WIDTH=1,C_PROBE412_WIDTH=1,C_PROBE413_WIDTH=1,C_PROBE414_WIDTH=1,C_PROBE415_WIDTH=1,C_PROBE416_WIDTH=1,C_PROBE417_WIDTH=1,C_PROBE418_WIDTH=1,C_PROBE419_WIDTH=1,C_PROBE420_WIDTH=1,C_PROBE421_WIDTH=1,C_PROBE422_WIDTH=1,C_PROBE423_WIDTH=1,C_PROBE424_WIDTH=1,C_PROBE425_WIDTH=1,C_PROBE426_WIDTH=1,C_PROBE427_WIDTH=1,C_PROBE428_WIDTH=1,C_PROBE429_WIDTH=1,C_PROBE430_WIDTH=1,C_PROBE431_WIDTH=1,C_PROBE432_WIDTH=1,C_PROBE433_WIDTH=1,C_PROBE434_WIDTH=1,C_PROBE435_WIDTH=1,C_PROBE436_WIDTH=1,C_PROBE437_WIDTH=1,C_PROBE438_WIDTH=1,C_PROBE439_WIDTH=1,C_PROBE440_WIDTH=1,C_PROBE441_WIDTH=1,C_PROBE442_WIDTH=1,C_PROBE443_WIDTH=1,C_PROBE444_WIDTH=1,C_PROBE445_WIDTH=1,C_PROBE446_WIDTH=1,C_PROBE447_WIDTH=1,C_PROBE448_WIDTH=1,C_PROBE449_WIDTH=1,C_PROBE450_WIDTH=1,C_PROBE451_WIDTH=1,C_PROBE452_WIDTH=1,C_PROBE453_WIDTH=1,"&
"C_PROBE454_WIDTH=1,C_PROBE455_WIDTH=1,C_PROBE456_WIDTH=1,C_PROBE457_WIDTH=1,C_PROBE458_WIDTH=1,C_PROBE459_WIDTH=1,C_PROBE460_WIDTH=1,C_PROBE461_WIDTH=1,C_PROBE462_WIDTH=1,C_PROBE463_WIDTH=1,C_PROBE464_WIDTH=1,C_PROBE465_WIDTH=1,C_PROBE466_WIDTH=1,C_PROBE467_WIDTH=1,C_PROBE468_WIDTH=1,C_PROBE469_WIDTH=1,C_PROBE470_WIDTH=1,C_PROBE471_WIDTH=1,C_PROBE472_WIDTH=1,C_PROBE473_WIDTH=1,C_PROBE474_WIDTH=1,C_PROBE475_WIDTH=1,C_PROBE476_WIDTH=1,C_PROBE477_WIDTH=1,C_PROBE478_WIDTH=1,C_PROBE479_WIDTH=1,C_PROBE480_WIDTH=1,C_PROBE481_WIDTH=1,C_PROBE482_WIDTH=1,C_PROBE483_WIDTH=1,C_PROBE484_WIDTH=1,C_PROBE485_WIDTH=1,C_PROBE486_WIDTH=1,C_PROBE487_WIDTH=1,C_PROBE488_WIDTH=1,C_PROBE489_WIDTH=1,C_PROBE490_WIDTH=1,C_PROBE491_WIDTH=1,C_PROBE492_WIDTH=1,C_PROBE493_WIDTH=1,C_PROBE494_WIDTH=1,C_PROBE495_WIDTH=1,C_PROBE496_WIDTH=1,C_PROBE497_WIDTH=1,C_PROBE498_WIDTH=1,C_PROBE499_WIDTH=1,C_PROBE500_WIDTH=1,C_PROBE501_WIDTH=1,C_PROBE502_WIDTH=1,C_PROBE503_WIDTH=1,C_PROBE504_WIDTH=1,C_PROBE505_WIDTH=1,C_PROBE506_WIDTH=1,C_PROBE507_WIDTH=1,C_PROBE508_WIDTH=1,C_PROBE509_WIDTH=1,C_PROBE510_WIDTH=1,C_PROBE511_WIDTH=1,C_PROBE512_WIDTH=1,C_PROBE513_WIDTH=1,C_PROBE514_WIDTH=1,C_PROBE515_WIDTH=1,C_PROBE516_WIDTH=1,C_PROBE517_WIDTH=1,C_PROBE518_WIDTH=1,C_PROBE519_WIDTH=1,C_PROBE520_WIDTH=1,C_PROBE521_WIDTH=1,C_PROBE522_WIDTH=1,C_PROBE523_WIDTH=1,C_PROBE524_WIDTH=1,C_PROBE525_WIDTH=1,C_PROBE526_WIDTH=1,C_PROBE527_WIDTH=1,C_PROBE528_WIDTH=1,C_PROBE529_WIDTH=1,C_PROBE530_WIDTH=1,C_PROBE531_WIDTH=1,C_PROBE532_WIDTH=1,C_PROBE533_WIDTH=1,C_PROBE534_WIDTH=1,C_PROBE535_WIDTH=1,C_PROBE536_WIDTH=1,C_PROBE537_WIDTH=1,C_PROBE538_WIDTH=1,C_PROBE539_WIDTH=1,C_PROBE540_WIDTH=1,C_PROBE541_WIDTH=1,C_PROBE542_WIDTH=1,C_PROBE543_WIDTH=1,C_PROBE544_WIDTH=1,C_PROBE545_WIDTH=1,C_PROBE546_WIDTH=1,C_PROBE547_WIDTH=1,C_PROBE548_WIDTH=1,C_PROBE549_WIDTH=1,C_PROBE550_WIDTH=1,C_PROBE551_WIDTH=1,C_PROBE552_WIDTH=1,C_PROBE553_WIDTH=1,"&
"C_PROBE554_WIDTH=1,C_PROBE555_WIDTH=1,C_PROBE556_WIDTH=1,C_PROBE557_WIDTH=1,C_PROBE558_WIDTH=1,C_PROBE559_WIDTH=1,C_PROBE560_WIDTH=1,C_PROBE561_WIDTH=1,C_PROBE562_WIDTH=1,C_PROBE563_WIDTH=1,C_PROBE564_WIDTH=1,C_PROBE565_WIDTH=1,C_PROBE566_WIDTH=1,C_PROBE567_WIDTH=1,C_PROBE568_WIDTH=1,C_PROBE569_WIDTH=1,C_PROBE570_WIDTH=1,C_PROBE571_WIDTH=1,C_PROBE572_WIDTH=1,C_PROBE573_WIDTH=1,C_PROBE574_WIDTH=1,C_PROBE575_WIDTH=1,C_PROBE576_WIDTH=1,C_PROBE577_WIDTH=1,C_PROBE578_WIDTH=1,C_PROBE579_WIDTH=1,C_PROBE580_WIDTH=1,C_PROBE581_WIDTH=1,C_PROBE582_WIDTH=1,C_PROBE583_WIDTH=1,C_PROBE584_WIDTH=1,C_PROBE585_WIDTH=1,C_PROBE586_WIDTH=1,C_PROBE587_WIDTH=1,C_PROBE588_WIDTH=1,C_PROBE589_WIDTH=1,C_PROBE590_WIDTH=1,C_PROBE591_WIDTH=1,C_PROBE592_WIDTH=1,C_PROBE593_WIDTH=1,C_PROBE594_WIDTH=1,C_PROBE595_WIDTH=1,C_PROBE596_WIDTH=1,C_PROBE597_WIDTH=1,C_PROBE598_WIDTH=1,C_PROBE599_WIDTH=1,C_PROBE600_WIDTH=1,C_PROBE601_WIDTH=1,C_PROBE602_WIDTH=1,C_PROBE603_WIDTH=1,C_PROBE604_WIDTH=1,C_PROBE605_WIDTH=1,C_PROBE606_WIDTH=1,C_PROBE607_WIDTH=1,C_PROBE608_WIDTH=1,C_PROBE609_WIDTH=1,C_PROBE610_WIDTH=1,C_PROBE611_WIDTH=1,C_PROBE612_WIDTH=1,C_PROBE613_WIDTH=1,C_PROBE614_WIDTH=1,C_PROBE615_WIDTH=1,C_PROBE616_WIDTH=1,C_PROBE617_WIDTH=1,C_PROBE618_WIDTH=1,C_PROBE619_WIDTH=1,C_PROBE620_WIDTH=1,C_PROBE621_WIDTH=1,C_PROBE622_WIDTH=1,C_PROBE623_WIDTH=1,C_PROBE624_WIDTH=1,C_PROBE625_WIDTH=1,C_PROBE626_WIDTH=1,C_PROBE627_WIDTH=1,C_PROBE628_WIDTH=1,C_PROBE629_WIDTH=1,C_PROBE630_WIDTH=1,C_PROBE631_WIDTH=1,C_PROBE632_WIDTH=1,C_PROBE633_WIDTH=1,C_PROBE634_WIDTH=1,C_PROBE635_WIDTH=1,C_PROBE636_WIDTH=1,C_PROBE637_WIDTH=1,C_PROBE638_WIDTH=1,C_PROBE639_WIDTH=1,C_PROBE640_WIDTH=1,C_PROBE641_WIDTH=1,C_PROBE642_WIDTH=1,C_PROBE643_WIDTH=1,C_PROBE644_WIDTH=1,C_PROBE645_WIDTH=1,C_PROBE646_WIDTH=1,C_PROBE647_WIDTH=1,C_PROBE648_WIDTH=1,C_PROBE649_WIDTH=1,C_PROBE650_WIDTH=1,C_PROBE651_WIDTH=1,C_PROBE652_WIDTH=1,C_PROBE653_WIDTH=1,"&
"C_PROBE654_WIDTH=1,C_PROBE655_WIDTH=1,C_PROBE656_WIDTH=1,C_PROBE657_WIDTH=1,C_PROBE658_WIDTH=1,C_PROBE659_WIDTH=1,C_PROBE660_WIDTH=1,C_PROBE661_WIDTH=1,C_PROBE662_WIDTH=1,C_PROBE663_WIDTH=1,C_PROBE664_WIDTH=1,C_PROBE665_WIDTH=1,C_PROBE666_WIDTH=1,C_PROBE667_WIDTH=1,C_PROBE668_WIDTH=1,C_PROBE669_WIDTH=1,C_PROBE670_WIDTH=1,C_PROBE671_WIDTH=1,C_PROBE672_WIDTH=1,C_PROBE673_WIDTH=1,C_PROBE674_WIDTH=1,C_PROBE675_WIDTH=1,C_PROBE676_WIDTH=1,C_PROBE677_WIDTH=1,C_PROBE678_WIDTH=1,C_PROBE679_WIDTH=1,C_PROBE680_WIDTH=1,C_PROBE681_WIDTH=1,C_PROBE682_WIDTH=1,C_PROBE683_WIDTH=1,C_PROBE684_WIDTH=1,C_PROBE685_WIDTH=1,C_PROBE686_WIDTH=1,C_PROBE687_WIDTH=1,C_PROBE688_WIDTH=1,C_PROBE689_WIDTH=1,C_PROBE690_WIDTH=1,C_PROBE691_WIDTH=1,C_PROBE692_WIDTH=1,C_PROBE693_WIDTH=1,C_PROBE694_WIDTH=1,C_PROBE695_WIDTH=1,C_PROBE696_WIDTH=1,C_PROBE697_WIDTH=1,C_PROBE698_WIDTH=1,C_PROBE699_WIDTH=1,C_PROBE700_WIDTH=1,C_PROBE701_WIDTH=1,C_PROBE702_WIDTH=1,C_PROBE703_WIDTH=1,C_PROBE704_WIDTH=1,C_PROBE705_WIDTH=1,C_PROBE706_WIDTH=1,C_PROBE707_WIDTH=1,C_PROBE708_WIDTH=1,C_PROBE709_WIDTH=1,C_PROBE710_WIDTH=1,C_PROBE711_WIDTH=1,C_PROBE712_WIDTH=1,C_PROBE713_WIDTH=1,C_PROBE714_WIDTH=1,C_PROBE715_WIDTH=1,C_PROBE716_WIDTH=1,C_PROBE717_WIDTH=1,C_PROBE718_WIDTH=1,C_PROBE719_WIDTH=1,C_PROBE720_WIDTH=1,C_PROBE721_WIDTH=1,C_PROBE722_WIDTH=1,C_PROBE723_WIDTH=1,C_PROBE724_WIDTH=1,C_PROBE725_WIDTH=1,C_PROBE726_WIDTH=1,C_PROBE727_WIDTH=1,C_PROBE728_WIDTH=1,C_PROBE729_WIDTH=1,C_PROBE730_WIDTH=1,C_PROBE731_WIDTH=1,C_PROBE732_WIDTH=1,C_PROBE733_WIDTH=1,C_PROBE734_WIDTH=1,C_PROBE735_WIDTH=1,C_PROBE736_WIDTH=1,C_PROBE737_WIDTH=1,C_PROBE738_WIDTH=1,C_PROBE739_WIDTH=1,C_PROBE740_WIDTH=1,C_PROBE741_WIDTH=1,C_PROBE742_WIDTH=1,C_PROBE743_WIDTH=1,C_PROBE744_WIDTH=1,C_PROBE745_WIDTH=1,C_PROBE746_WIDTH=1,C_PROBE747_WIDTH=1,C_PROBE748_WIDTH=1,C_PROBE749_WIDTH=1,C_PROBE750_WIDTH=1,C_PROBE751_WIDTH=1,C_PROBE752_WIDTH=1,C_PROBE753_WIDTH=1,"&
"C_PROBE754_WIDTH=1,C_PROBE755_WIDTH=1,C_PROBE756_WIDTH=1,C_PROBE757_WIDTH=1,C_PROBE758_WIDTH=1,C_PROBE759_WIDTH=1,C_PROBE760_WIDTH=1,C_PROBE761_WIDTH=1,C_PROBE762_WIDTH=1,C_PROBE763_WIDTH=1,C_PROBE764_WIDTH=1,C_PROBE765_WIDTH=1,C_PROBE766_WIDTH=1,C_PROBE767_WIDTH=1,C_PROBE768_WIDTH=1,C_PROBE769_WIDTH=1,C_PROBE770_WIDTH=1,C_PROBE771_WIDTH=1,C_PROBE772_WIDTH=1,C_PROBE773_WIDTH=1,C_PROBE774_WIDTH=1,C_PROBE775_WIDTH=1,C_PROBE776_WIDTH=1,C_PROBE777_WIDTH=1,C_PROBE778_WIDTH=1,C_PROBE779_WIDTH=1,C_PROBE780_WIDTH=1,C_PROBE781_WIDTH=1,C_PROBE782_WIDTH=1,C_PROBE783_WIDTH=1,C_PROBE784_WIDTH=1,C_PROBE785_WIDTH=1,C_PROBE786_WIDTH=1,C_PROBE787_WIDTH=1,C_PROBE788_WIDTH=1,C_PROBE789_WIDTH=1,C_PROBE790_WIDTH=1,C_PROBE791_WIDTH=1,C_PROBE792_WIDTH=1,C_PROBE793_WIDTH=1,C_PROBE794_WIDTH=1,C_PROBE795_WIDTH=1,C_PROBE796_WIDTH=1,C_PROBE797_WIDTH=1,C_PROBE798_WIDTH=1,C_PROBE799_WIDTH=1,C_PROBE800_WIDTH=1,C_PROBE801_WIDTH=1,C_PROBE802_WIDTH=1,C_PROBE803_WIDTH=1,C_PROBE804_WIDTH=1,C_PROBE805_WIDTH=1,C_PROBE806_WIDTH=1,C_PROBE807_WIDTH=1,C_PROBE808_WIDTH=1,C_PROBE809_WIDTH=1,C_PROBE810_WIDTH=1,C_PROBE811_WIDTH=1,C_PROBE812_WIDTH=1,C_PROBE813_WIDTH=1,C_PROBE814_WIDTH=1,C_PROBE815_WIDTH=1,C_PROBE816_WIDTH=1,C_PROBE817_WIDTH=1,C_PROBE818_WIDTH=1,C_PROBE819_WIDTH=1,C_PROBE820_WIDTH=1,C_PROBE821_WIDTH=1,C_PROBE822_WIDTH=1,C_PROBE823_WIDTH=1,C_PROBE824_WIDTH=1,C_PROBE825_WIDTH=1,C_PROBE826_WIDTH=1,C_PROBE827_WIDTH=1,C_PROBE828_WIDTH=1,C_PROBE829_WIDTH=1,C_PROBE830_WIDTH=1,C_PROBE831_WIDTH=1,C_PROBE832_WIDTH=1,C_PROBE833_WIDTH=1,C_PROBE834_WIDTH=1,C_PROBE835_WIDTH=1,C_PROBE836_WIDTH=1,C_PROBE837_WIDTH=1,C_PROBE838_WIDTH=1,C_PROBE839_WIDTH=1,C_PROBE840_WIDTH=1,C_PROBE841_WIDTH=1,C_PROBE842_WIDTH=1,C_PROBE843_WIDTH=1,C_PROBE844_WIDTH=1,C_PROBE845_WIDTH=1,C_PROBE846_WIDTH=1,C_PROBE847_WIDTH=1,C_PROBE848_WIDTH=1,C_PROBE849_WIDTH=1,C_PROBE850_WIDTH=1,C_PROBE851_WIDTH=1,C_PROBE852_WIDTH=1,C_PROBE853_WIDTH=1,"&
"C_PROBE854_WIDTH=1,C_PROBE855_WIDTH=1,C_PROBE856_WIDTH=1,C_PROBE857_WIDTH=1,C_PROBE858_WIDTH=1,C_PROBE859_WIDTH=1,C_PROBE860_WIDTH=1,C_PROBE861_WIDTH=1,C_PROBE862_WIDTH=1,C_PROBE863_WIDTH=1,C_PROBE864_WIDTH=1,C_PROBE865_WIDTH=1,C_PROBE866_WIDTH=1,C_PROBE867_WIDTH=1,C_PROBE868_WIDTH=1,C_PROBE869_WIDTH=1,C_PROBE870_WIDTH=1,C_PROBE871_WIDTH=1,C_PROBE872_WIDTH=1,C_PROBE873_WIDTH=1,C_PROBE874_WIDTH=1,C_PROBE875_WIDTH=1,C_PROBE876_WIDTH=1,C_PROBE877_WIDTH=1,C_PROBE878_WIDTH=1,C_PROBE879_WIDTH=1,C_PROBE880_WIDTH=1,C_PROBE881_WIDTH=1,C_PROBE882_WIDTH=1,C_PROBE883_WIDTH=1,C_PROBE884_WIDTH=1,C_PROBE885_WIDTH=1,C_PROBE886_WIDTH=1,C_PROBE887_WIDTH=1,C_PROBE888_WIDTH=1,C_PROBE889_WIDTH=1,C_PROBE890_WIDTH=1,C_PROBE891_WIDTH=1,C_PROBE892_WIDTH=1,C_PROBE893_WIDTH=1,C_PROBE894_WIDTH=1,C_PROBE895_WIDTH=1,C_PROBE896_WIDTH=1,C_PROBE897_WIDTH=1,C_PROBE898_WIDTH=1,C_PROBE899_WIDTH=1,C_PROBE900_WIDTH=1,C_PROBE901_WIDTH=1,C_PROBE902_WIDTH=1,C_PROBE903_WIDTH=1,C_PROBE904_WIDTH=1,C_PROBE905_WIDTH=1,C_PROBE906_WIDTH=1,C_PROBE907_WIDTH=1,C_PROBE908_WIDTH=1,C_PROBE909_WIDTH=1,C_PROBE910_WIDTH=1,C_PROBE911_WIDTH=1,C_PROBE912_WIDTH=1,C_PROBE913_WIDTH=1,C_PROBE914_WIDTH=1,C_PROBE915_WIDTH=1,C_PROBE916_WIDTH=1,C_PROBE917_WIDTH=1,C_PROBE918_WIDTH=1,C_PROBE919_WIDTH=1,C_PROBE920_WIDTH=1,C_PROBE921_WIDTH=1,C_PROBE922_WIDTH=1,C_PROBE923_WIDTH=1,C_PROBE924_WIDTH=1,C_PROBE925_WIDTH=1,C_PROBE926_WIDTH=1,C_PROBE927_WIDTH=1,C_PROBE928_WIDTH=1,C_PROBE929_WIDTH=1,C_PROBE930_WIDTH=1,C_PROBE931_WIDTH=1,C_PROBE932_WIDTH=1,C_PROBE933_WIDTH=1,C_PROBE934_WIDTH=1,C_PROBE935_WIDTH=1,C_PROBE936_WIDTH=1,C_PROBE937_WIDTH=1,C_PROBE938_WIDTH=1,C_PROBE939_WIDTH=1,C_PROBE940_WIDTH=1,C_PROBE941_WIDTH=1,C_PROBE942_WIDTH=1,C_PROBE943_WIDTH=1,C_PROBE944_WIDTH=1,C_PROBE945_WIDTH=1,C_PROBE946_WIDTH=1,C_PROBE947_WIDTH=1,C_PROBE948_WIDTH=1,C_PROBE949_WIDTH=1,C_PROBE950_WIDTH=1,C_PROBE951_WIDTH=1,C_PROBE952_WIDTH=1,C_PROBE953_WIDTH=1,"&
"C_PROBE954_WIDTH=1,C_PROBE955_WIDTH=1,C_PROBE956_WIDTH=1,C_PROBE957_WIDTH=1,C_PROBE958_WIDTH=1,C_PROBE959_WIDTH=1,C_PROBE960_WIDTH=1,C_PROBE961_WIDTH=1,C_PROBE962_WIDTH=1,C_PROBE963_WIDTH=1,C_PROBE964_WIDTH=1,C_PROBE965_WIDTH=1,C_PROBE966_WIDTH=1,C_PROBE967_WIDTH=1,C_PROBE968_WIDTH=1,C_PROBE969_WIDTH=1,C_PROBE970_WIDTH=1,C_PROBE971_WIDTH=1,C_PROBE972_WIDTH=1,C_PROBE973_WIDTH=1,C_PROBE974_WIDTH=1,C_PROBE975_WIDTH=1,C_PROBE976_WIDTH=1,C_PROBE977_WIDTH=1,C_PROBE978_WIDTH=1,C_PROBE979_WIDTH=1,C_PROBE980_WIDTH=1,C_PROBE981_WIDTH=1,C_PROBE982_WIDTH=1,C_PROBE983_WIDTH=1,C_PROBE984_WIDTH=1,C_PROBE985_WIDTH=1,C_PROBE986_WIDTH=1,C_PROBE987_WIDTH=1,C_PROBE988_WIDTH=1,C_PROBE989_WIDTH=1,C_PROBE990_WIDTH=1,C_PROBE991_WIDTH=1,C_PROBE992_WIDTH=1,C_PROBE993_WIDTH=1,C_PROBE994_WIDTH=1,C_PROBE995_WIDTH=1,C_PROBE996_WIDTH=1,C_PROBE997_WIDTH=1,C_PROBE998_WIDTH=1,C_PROBE999_WIDTH=1,C_PROBE1000_WIDTH=1,C_PROBE1001_WIDTH=1,C_PROBE1002_WIDTH=1,C_PROBE1003_WIDTH=1,C_PROBE1004_WIDTH=1,C_PROBE1005_WIDTH=1,C_PROBE1006_WIDTH=1,C_PROBE1007_WIDTH=1,C_PROBE1008_WIDTH=1,C_PROBE1009_WIDTH=1,C_PROBE1010_WIDTH=1,C_PROBE1011_WIDTH=1,C_PROBE1012_WIDTH=1,C_PROBE1013_WIDTH=1,C_PROBE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=2,C_PROBE1_MU_CNT=2,C_PROBE2_MU_CNT=2,C_PROBE3_MU_CNT=2,C_PROBE4_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,"&
"C_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,"&
"C_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,"&
"C_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,"&
"C_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,"&
"C_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,"&
"C_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,"&
"C_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,"&
"C_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,"&
"C_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,"&
"C_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1008_MU_CNT=1,C_PROBE1009_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1023_MU_CNT=1,C_PROBE0_TYPE=0,C_PROBE1_TYPE=1,C_PROBE2_TYPE=0,C_PROBE3_TYPE=1,C_PROBE4_TYPE=1,C_PROBE5_TYPE=1,"&
"C_PROBE6_TYPE=1,C_PROBE7_TYPE=1,C_PROBE8_TYPE=1,C_PROBE9_TYPE=1,C_PROBE10_TYPE=1,C_PROBE11_TYPE=1,C_PROBE12_TYPE=1,C_PROBE13_TYPE=1,C_PROBE14_TYPE=1,C_PROBE15_TYPE=1,C_PROBE16_TYPE=1,C_PROBE17_TYPE=1,C_PROBE18_TYPE=1,C_PROBE19_TYPE=1,C_PROBE20_TYPE=1,C_PROBE21_TYPE=1,C_PROBE22_TYPE=1,C_PROBE23_TYPE=1,C_PROBE24_TYPE=1,C_PROBE25_TYPE=1,C_PROBE26_TYPE=1,C_PROBE27_TYPE=1,C_PROBE28_TYPE=1,C_PROBE29_TYPE=1,C_PROBE30_TYPE=1,C_PROBE31_TYPE=1,C_PROBE32_TYPE=1,C_PROBE33_TYPE=1,C_PROBE34_TYPE=1,C_PROBE35_TYPE=1,C_PROBE36_TYPE=1,C_PROBE37_TYPE=1,C_PROBE38_TYPE=1,C_PROBE39_TYPE=1,C_PROBE40_TYPE=1,C_PROBE41_TYPE=1,C_PROBE42_TYPE=1,C_PROBE43_TYPE=1,C_PROBE44_TYPE=1,C_PROBE45_TYPE=1,C_PROBE46_TYPE=1,C_PROBE47_TYPE=1,C_PROBE48_TYPE=1,C_PROBE49_TYPE=1,C_PROBE50_TYPE=1,C_PROBE51_TYPE=1,C_PROBE52_TYPE=1,C_PROBE53_TYPE=1,C_PROBE54_TYPE=1,C_PROBE55_TYPE=1,C_PROBE56_TYPE=1,C_PROBE57_TYPE=1,C_PROBE58_TYPE=1,C_PROBE59_TYPE=1,C_PROBE60_TYPE=1,C_PROBE61_TYPE=1,C_PROBE62_TYPE=1,C_PROBE63_TYPE=1,C_PROBE64_TYPE=1,C_PROBE65_TYPE=1,C_PROBE66_TYPE=1,C_PROBE67_TYPE=1,C_PROBE68_TYPE=1,C_PROBE69_TYPE=1,C_PROBE70_TYPE=1,C_PROBE71_TYPE=1,C_PROBE72_TYPE=1,C_PROBE73_TYPE=1,C_PROBE74_TYPE=1,C_PROBE75_TYPE=1,C_PROBE76_TYPE=1,C_PROBE77_TYPE=1,C_PROBE78_TYPE=1,C_PROBE79_TYPE=1,C_PROBE80_TYPE=1,C_PROBE81_TYPE=1,C_PROBE82_TYPE=1,C_PROBE83_TYPE=1,C_PROBE84_TYPE=1,C_PROBE85_TYPE=1,C_PROBE86_TYPE=1,C_PROBE87_TYPE=1,C_PROBE88_TYPE=1,C_PROBE89_TYPE=1,C_PROBE90_TYPE=1,C_PROBE91_TYPE=1,C_PROBE92_TYPE=1,C_PROBE93_TYPE=1,C_PROBE94_TYPE=1,C_PROBE95_TYPE=1,C_PROBE96_TYPE=1,C_PROBE97_TYPE=1,C_PROBE98_TYPE=1,C_PROBE99_TYPE=1,C_PROBE100_TYPE=1,C_PROBE101_TYPE=1,C_PROBE102_TYPE=1,C_PROBE103_TYPE=1,C_PROBE104_TYPE=1,C_PROBE105_TYPE=1,"&
"C_PROBE106_TYPE=1,C_PROBE107_TYPE=1,C_PROBE108_TYPE=1,C_PROBE109_TYPE=1,C_PROBE110_TYPE=1,C_PROBE111_TYPE=1,C_PROBE112_TYPE=1,C_PROBE113_TYPE=1,C_PROBE114_TYPE=1,C_PROBE115_TYPE=1,C_PROBE116_TYPE=1,C_PROBE117_TYPE=1,C_PROBE118_TYPE=1,C_PROBE119_TYPE=1,C_PROBE120_TYPE=1,C_PROBE121_TYPE=1,C_PROBE122_TYPE=1,C_PROBE123_TYPE=1,C_PROBE124_TYPE=1,C_PROBE125_TYPE=1,C_PROBE126_TYPE=1,C_PROBE127_TYPE=1,C_PROBE128_TYPE=1,C_PROBE129_TYPE=1,C_PROBE130_TYPE=1,C_PROBE131_TYPE=1,C_PROBE132_TYPE=1,C_PROBE133_TYPE=1,C_PROBE134_TYPE=1,C_PROBE135_TYPE=1,C_PROBE136_TYPE=1,C_PROBE137_TYPE=1,C_PROBE138_TYPE=1,C_PROBE139_TYPE=1,C_PROBE140_TYPE=1,C_PROBE141_TYPE=1,C_PROBE142_TYPE=1,C_PROBE143_TYPE=1,C_PROBE144_TYPE=1,C_PROBE145_TYPE=1,C_PROBE146_TYPE=1,C_PROBE147_TYPE=1,C_PROBE148_TYPE=1,C_PROBE149_TYPE=1,C_PROBE150_TYPE=1,C_PROBE151_TYPE=1,C_PROBE152_TYPE=1,C_PROBE153_TYPE=1,C_PROBE154_TYPE=1,C_PROBE155_TYPE=1,C_PROBE156_TYPE=1,C_PROBE157_TYPE=1,C_PROBE158_TYPE=1,C_PROBE159_TYPE=1,C_PROBE160_TYPE=1,C_PROBE161_TYPE=1,C_PROBE162_TYPE=1,C_PROBE163_TYPE=1,C_PROBE164_TYPE=1,C_PROBE165_TYPE=1,C_PROBE166_TYPE=1,C_PROBE167_TYPE=1,C_PROBE168_TYPE=1,C_PROBE169_TYPE=1,C_PROBE170_TYPE=1,C_PROBE171_TYPE=1,C_PROBE172_TYPE=1,C_PROBE173_TYPE=1,C_PROBE174_TYPE=1,C_PROBE175_TYPE=1,C_PROBE176_TYPE=1,C_PROBE177_TYPE=1,C_PROBE178_TYPE=1,C_PROBE179_TYPE=1,C_PROBE180_TYPE=1,C_PROBE181_TYPE=1,C_PROBE182_TYPE=1,C_PROBE183_TYPE=1,C_PROBE184_TYPE=1,C_PROBE185_TYPE=1,C_PROBE186_TYPE=1,C_PROBE187_TYPE=1,C_PROBE188_TYPE=1,C_PROBE189_TYPE=1,C_PROBE190_TYPE=1,C_PROBE191_TYPE=1,C_PROBE192_TYPE=1,C_PROBE193_TYPE=1,C_PROBE194_TYPE=1,C_PROBE195_TYPE=1,C_PROBE196_TYPE=1,C_PROBE197_TYPE=1,C_PROBE198_TYPE=1,C_PROBE199_TYPE=1,C_PROBE200_TYPE=1,C_PROBE201_TYPE=1,C_PROBE202_TYPE=1,C_PROBE203_TYPE=1,C_PROBE204_TYPE=1,C_PROBE205_TYPE=1,"&
"C_PROBE206_TYPE=1,C_PROBE207_TYPE=1,C_PROBE208_TYPE=1,C_PROBE209_TYPE=1,C_PROBE210_TYPE=1,C_PROBE211_TYPE=1,C_PROBE212_TYPE=1,C_PROBE213_TYPE=1,C_PROBE214_TYPE=1,C_PROBE215_TYPE=1,C_PROBE216_TYPE=1,C_PROBE217_TYPE=1,C_PROBE218_TYPE=1,C_PROBE219_TYPE=1,C_PROBE220_TYPE=1,C_PROBE221_TYPE=1,C_PROBE222_TYPE=1,C_PROBE223_TYPE=1,C_PROBE224_TYPE=1,C_PROBE225_TYPE=1,C_PROBE226_TYPE=1,C_PROBE227_TYPE=1,C_PROBE228_TYPE=1,C_PROBE229_TYPE=1,C_PROBE230_TYPE=1,C_PROBE231_TYPE=1,C_PROBE232_TYPE=1,C_PROBE233_TYPE=1,C_PROBE234_TYPE=1,C_PROBE235_TYPE=1,C_PROBE236_TYPE=1,C_PROBE237_TYPE=1,C_PROBE238_TYPE=1,C_PROBE239_TYPE=1,C_PROBE240_TYPE=1,C_PROBE241_TYPE=1,C_PROBE242_TYPE=1,C_PROBE243_TYPE=1,C_PROBE244_TYPE=1,C_PROBE245_TYPE=1,C_PROBE246_TYPE=1,C_PROBE247_TYPE=1,C_PROBE248_TYPE=1,C_PROBE249_TYPE=1,C_PROBE250_TYPE=1,C_PROBE251_TYPE=1,C_PROBE252_TYPE=1,C_PROBE253_TYPE=1,C_PROBE254_TYPE=1,C_PROBE255_TYPE=1,C_PROBE256_TYPE=1,C_PROBE257_TYPE=1,C_PROBE258_TYPE=1,C_PROBE259_TYPE=1,C_PROBE260_TYPE=1,C_PROBE261_TYPE=1,C_PROBE262_TYPE=1,C_PROBE263_TYPE=1,C_PROBE264_TYPE=1,C_PROBE265_TYPE=1,C_PROBE266_TYPE=1,C_PROBE267_TYPE=1,C_PROBE268_TYPE=1,C_PROBE269_TYPE=1,C_PROBE270_TYPE=1,C_PROBE271_TYPE=1,C_PROBE272_TYPE=1,C_PROBE273_TYPE=1,C_PROBE274_TYPE=1,C_PROBE275_TYPE=1,C_PROBE276_TYPE=1,C_PROBE277_TYPE=1,C_PROBE278_TYPE=1,C_PROBE279_TYPE=1,C_PROBE280_TYPE=1,C_PROBE281_TYPE=1,C_PROBE282_TYPE=1,C_PROBE283_TYPE=1,C_PROBE284_TYPE=1,C_PROBE285_TYPE=1,C_PROBE286_TYPE=1,C_PROBE287_TYPE=1,C_PROBE288_TYPE=1,C_PROBE289_TYPE=1,C_PROBE290_TYPE=1,C_PROBE291_TYPE=1,C_PROBE292_TYPE=1,C_PROBE293_TYPE=1,C_PROBE294_TYPE=1,C_PROBE295_TYPE=1,C_PROBE296_TYPE=1,C_PROBE297_TYPE=1,C_PROBE298_TYPE=1,C_PROBE299_TYPE=1,C_PROBE300_TYPE=1,C_PROBE301_TYPE=1,C_PROBE302_TYPE=1,C_PROBE303_TYPE=1,C_PROBE304_TYPE=1,C_PROBE305_TYPE=1,"&
"C_PROBE306_TYPE=1,C_PROBE307_TYPE=1,C_PROBE308_TYPE=1,C_PROBE309_TYPE=1,C_PROBE310_TYPE=1,C_PROBE311_TYPE=1,C_PROBE312_TYPE=1,C_PROBE313_TYPE=1,C_PROBE314_TYPE=1,C_PROBE315_TYPE=1,C_PROBE316_TYPE=1,C_PROBE317_TYPE=1,C_PROBE318_TYPE=1,C_PROBE319_TYPE=1,C_PROBE320_TYPE=1,C_PROBE321_TYPE=1,C_PROBE322_TYPE=1,C_PROBE323_TYPE=1,C_PROBE324_TYPE=1,C_PROBE325_TYPE=1,C_PROBE326_TYPE=1,C_PROBE327_TYPE=1,C_PROBE328_TYPE=1,C_PROBE329_TYPE=1,C_PROBE330_TYPE=1,C_PROBE331_TYPE=1,C_PROBE332_TYPE=1,C_PROBE333_TYPE=1,C_PROBE334_TYPE=1,C_PROBE335_TYPE=1,C_PROBE336_TYPE=1,C_PROBE337_TYPE=1,C_PROBE338_TYPE=1,C_PROBE339_TYPE=1,C_PROBE340_TYPE=1,C_PROBE341_TYPE=1,C_PROBE342_TYPE=1,C_PROBE343_TYPE=1,C_PROBE344_TYPE=1,C_PROBE345_TYPE=1,C_PROBE346_TYPE=1,C_PROBE347_TYPE=1,C_PROBE348_TYPE=1,C_PROBE349_TYPE=1,C_PROBE350_TYPE=1,C_PROBE351_TYPE=1,C_PROBE352_TYPE=1,C_PROBE353_TYPE=1,C_PROBE354_TYPE=1,C_PROBE355_TYPE=1,C_PROBE356_TYPE=1,C_PROBE357_TYPE=1,C_PROBE358_TYPE=1,C_PROBE359_TYPE=1,C_PROBE360_TYPE=1,C_PROBE361_TYPE=1,C_PROBE362_TYPE=1,C_PROBE363_TYPE=1,C_PROBE364_TYPE=1,C_PROBE365_TYPE=1,C_PROBE366_TYPE=1,C_PROBE367_TYPE=1,C_PROBE368_TYPE=1,C_PROBE369_TYPE=1,C_PROBE370_TYPE=1,C_PROBE371_TYPE=1,C_PROBE372_TYPE=1,C_PROBE373_TYPE=1,C_PROBE374_TYPE=1,C_PROBE375_TYPE=1,C_PROBE376_TYPE=1,C_PROBE377_TYPE=1,C_PROBE378_TYPE=1,C_PROBE379_TYPE=1,C_PROBE380_TYPE=1,C_PROBE381_TYPE=1,C_PROBE382_TYPE=1,C_PROBE383_TYPE=1,C_PROBE384_TYPE=1,C_PROBE385_TYPE=1,C_PROBE386_TYPE=1,C_PROBE387_TYPE=1,C_PROBE388_TYPE=1,C_PROBE389_TYPE=1,C_PROBE390_TYPE=1,C_PROBE391_TYPE=1,C_PROBE392_TYPE=1,C_PROBE393_TYPE=1,C_PROBE394_TYPE=1,C_PROBE395_TYPE=1,C_PROBE396_TYPE=1,C_PROBE397_TYPE=1,C_PROBE398_TYPE=1,C_PROBE399_TYPE=1,C_PROBE400_TYPE=1,C_PROBE401_TYPE=1,C_PROBE402_TYPE=1,C_PROBE403_TYPE=1,C_PROBE404_TYPE=1,C_PROBE405_TYPE=1,"&
"C_PROBE406_TYPE=1,C_PROBE407_TYPE=1,C_PROBE408_TYPE=1,C_PROBE409_TYPE=1,C_PROBE410_TYPE=1,C_PROBE411_TYPE=1,C_PROBE412_TYPE=1,C_PROBE413_TYPE=1,C_PROBE414_TYPE=1,C_PROBE415_TYPE=1,C_PROBE416_TYPE=1,C_PROBE417_TYPE=1,C_PROBE418_TYPE=1,C_PROBE419_TYPE=1,C_PROBE420_TYPE=1,C_PROBE421_TYPE=1,C_PROBE422_TYPE=1,C_PROBE423_TYPE=1,C_PROBE424_TYPE=1,C_PROBE425_TYPE=1,C_PROBE426_TYPE=1,C_PROBE427_TYPE=1,C_PROBE428_TYPE=1,C_PROBE429_TYPE=1,C_PROBE430_TYPE=1,C_PROBE431_TYPE=1,C_PROBE432_TYPE=1,C_PROBE433_TYPE=1,C_PROBE434_TYPE=1,C_PROBE435_TYPE=1,C_PROBE436_TYPE=1,C_PROBE437_TYPE=1,C_PROBE438_TYPE=1,C_PROBE439_TYPE=1,C_PROBE440_TYPE=1,C_PROBE441_TYPE=1,C_PROBE442_TYPE=1,C_PROBE443_TYPE=1,C_PROBE444_TYPE=1,C_PROBE445_TYPE=1,C_PROBE446_TYPE=1,C_PROBE447_TYPE=1,C_PROBE448_TYPE=1,C_PROBE449_TYPE=1,C_PROBE450_TYPE=1,C_PROBE451_TYPE=1,C_PROBE452_TYPE=1,C_PROBE453_TYPE=1,C_PROBE454_TYPE=1,C_PROBE455_TYPE=1,C_PROBE456_TYPE=1,C_PROBE457_TYPE=1,C_PROBE458_TYPE=1,C_PROBE459_TYPE=1,C_PROBE460_TYPE=1,C_PROBE461_TYPE=1,C_PROBE462_TYPE=1,C_PROBE463_TYPE=1,C_PROBE464_TYPE=1,C_PROBE465_TYPE=1,C_PROBE466_TYPE=1,C_PROBE467_TYPE=1,C_PROBE468_TYPE=1,C_PROBE469_TYPE=1,C_PROBE470_TYPE=1,C_PROBE471_TYPE=1,C_PROBE472_TYPE=1,C_PROBE473_TYPE=1,C_PROBE474_TYPE=1,C_PROBE475_TYPE=1,C_PROBE476_TYPE=1,C_PROBE477_TYPE=1,C_PROBE478_TYPE=1,C_PROBE479_TYPE=1,C_PROBE480_TYPE=1,C_PROBE481_TYPE=1,C_PROBE482_TYPE=1,C_PROBE483_TYPE=1,C_PROBE484_TYPE=1,C_PROBE485_TYPE=1,C_PROBE486_TYPE=1,C_PROBE487_TYPE=1,C_PROBE488_TYPE=1,C_PROBE489_TYPE=1,C_PROBE490_TYPE=1,C_PROBE491_TYPE=1,C_PROBE492_TYPE=1,C_PROBE493_TYPE=1,C_PROBE494_TYPE=1,C_PROBE495_TYPE=1,C_PROBE496_TYPE=1,C_PROBE497_TYPE=1,C_PROBE498_TYPE=1,C_PROBE499_TYPE=1,C_PROBE500_TYPE=1,C_PROBE501_TYPE=1,C_PROBE502_TYPE=1,C_PROBE503_TYPE=1,C_PROBE504_TYPE=1,C_PROBE505_TYPE=1,"&
"C_PROBE506_TYPE=1,C_PROBE507_TYPE=1,C_PROBE508_TYPE=1,C_PROBE509_TYPE=1,C_PROBE510_TYPE=1,C_PROBE511_TYPE=1,C_PROBE512_TYPE=1,C_PROBE513_TYPE=1,C_PROBE514_TYPE=1,C_PROBE515_TYPE=1,C_PROBE516_TYPE=1,C_PROBE517_TYPE=1,C_PROBE518_TYPE=1,C_PROBE519_TYPE=1,C_PROBE520_TYPE=1,C_PROBE521_TYPE=1,C_PROBE522_TYPE=1,C_PROBE523_TYPE=1,C_PROBE524_TYPE=1,C_PROBE525_TYPE=1,C_PROBE526_TYPE=1,C_PROBE527_TYPE=1,C_PROBE528_TYPE=1,C_PROBE529_TYPE=1,C_PROBE530_TYPE=1,C_PROBE531_TYPE=1,C_PROBE532_TYPE=1,C_PROBE533_TYPE=1,C_PROBE534_TYPE=1,C_PROBE535_TYPE=1,C_PROBE536_TYPE=1,C_PROBE537_TYPE=1,C_PROBE538_TYPE=1,C_PROBE539_TYPE=1,C_PROBE540_TYPE=1,C_PROBE541_TYPE=1,C_PROBE542_TYPE=1,C_PROBE543_TYPE=1,C_PROBE544_TYPE=1,C_PROBE545_TYPE=1,C_PROBE546_TYPE=1,C_PROBE547_TYPE=1,C_PROBE548_TYPE=1,C_PROBE549_TYPE=1,C_PROBE550_TYPE=1,C_PROBE551_TYPE=1,C_PROBE552_TYPE=1,C_PROBE553_TYPE=1,C_PROBE554_TYPE=1,C_PROBE555_TYPE=1,C_PROBE556_TYPE=1,C_PROBE557_TYPE=1,C_PROBE558_TYPE=1,C_PROBE559_TYPE=1,C_PROBE560_TYPE=1,C_PROBE561_TYPE=1,C_PROBE562_TYPE=1,C_PROBE563_TYPE=1,C_PROBE564_TYPE=1,C_PROBE565_TYPE=1,C_PROBE566_TYPE=1,C_PROBE567_TYPE=1,C_PROBE568_TYPE=1,C_PROBE569_TYPE=1,C_PROBE570_TYPE=1,C_PROBE571_TYPE=1,C_PROBE572_TYPE=1,C_PROBE573_TYPE=1,C_PROBE574_TYPE=1,C_PROBE575_TYPE=1,C_PROBE576_TYPE=1,C_PROBE577_TYPE=1,C_PROBE578_TYPE=1,C_PROBE579_TYPE=1,C_PROBE580_TYPE=1,C_PROBE581_TYPE=1,C_PROBE582_TYPE=1,C_PROBE583_TYPE=1,C_PROBE584_TYPE=1,C_PROBE585_TYPE=1,C_PROBE586_TYPE=1,C_PROBE587_TYPE=1,C_PROBE588_TYPE=1,C_PROBE589_TYPE=1,C_PROBE590_TYPE=1,C_PROBE591_TYPE=1,C_PROBE592_TYPE=1,C_PROBE593_TYPE=1,C_PROBE594_TYPE=1,C_PROBE595_TYPE=1,C_PROBE596_TYPE=1,C_PROBE597_TYPE=1,C_PROBE598_TYPE=1,C_PROBE599_TYPE=1,C_PROBE600_TYPE=1,C_PROBE601_TYPE=1,C_PROBE602_TYPE=1,C_PROBE603_TYPE=1,C_PROBE604_TYPE=1,C_PROBE605_TYPE=1,"&
"C_PROBE606_TYPE=1,C_PROBE607_TYPE=1,C_PROBE608_TYPE=1,C_PROBE609_TYPE=1,C_PROBE610_TYPE=1,C_PROBE611_TYPE=1,C_PROBE612_TYPE=1,C_PROBE613_TYPE=1,C_PROBE614_TYPE=1,C_PROBE615_TYPE=1,C_PROBE616_TYPE=1,C_PROBE617_TYPE=1,C_PROBE618_TYPE=1,C_PROBE619_TYPE=1,C_PROBE620_TYPE=1,C_PROBE621_TYPE=1,C_PROBE622_TYPE=1,C_PROBE623_TYPE=1,C_PROBE624_TYPE=1,C_PROBE625_TYPE=1,C_PROBE626_TYPE=1,C_PROBE627_TYPE=1,C_PROBE628_TYPE=1,C_PROBE629_TYPE=1,C_PROBE630_TYPE=1,C_PROBE631_TYPE=1,C_PROBE632_TYPE=1,C_PROBE633_TYPE=1,C_PROBE634_TYPE=1,C_PROBE635_TYPE=1,C_PROBE636_TYPE=1,C_PROBE637_TYPE=1,C_PROBE638_TYPE=1,C_PROBE639_TYPE=1,C_PROBE640_TYPE=1,C_PROBE641_TYPE=1,C_PROBE642_TYPE=1,C_PROBE643_TYPE=1,C_PROBE644_TYPE=1,C_PROBE645_TYPE=1,C_PROBE646_TYPE=1,C_PROBE647_TYPE=1,C_PROBE648_TYPE=1,C_PROBE649_TYPE=1,C_PROBE650_TYPE=1,C_PROBE651_TYPE=1,C_PROBE652_TYPE=1,C_PROBE653_TYPE=1,C_PROBE654_TYPE=1,C_PROBE655_TYPE=1,C_PROBE656_TYPE=1,C_PROBE657_TYPE=1,C_PROBE658_TYPE=1,C_PROBE659_TYPE=1,C_PROBE660_TYPE=1,C_PROBE661_TYPE=1,C_PROBE662_TYPE=1,C_PROBE663_TYPE=1,C_PROBE664_TYPE=1,C_PROBE665_TYPE=1,C_PROBE666_TYPE=1,C_PROBE667_TYPE=1,C_PROBE668_TYPE=1,C_PROBE669_TYPE=1,C_PROBE670_TYPE=1,C_PROBE671_TYPE=1,C_PROBE672_TYPE=1,C_PROBE673_TYPE=1,C_PROBE674_TYPE=1,C_PROBE675_TYPE=1,C_PROBE676_TYPE=1,C_PROBE677_TYPE=1,C_PROBE678_TYPE=1,C_PROBE679_TYPE=1,C_PROBE680_TYPE=1,C_PROBE681_TYPE=1,C_PROBE682_TYPE=1,C_PROBE683_TYPE=1,C_PROBE684_TYPE=1,C_PROBE685_TYPE=1,C_PROBE686_TYPE=1,C_PROBE687_TYPE=1,C_PROBE688_TYPE=1,C_PROBE689_TYPE=1,C_PROBE690_TYPE=1,C_PROBE691_TYPE=1,C_PROBE692_TYPE=1,C_PROBE693_TYPE=1,C_PROBE694_TYPE=1,C_PROBE695_TYPE=1,C_PROBE696_TYPE=1,C_PROBE697_TYPE=1,C_PROBE698_TYPE=1,C_PROBE699_TYPE=1,C_PROBE700_TYPE=1,C_PROBE701_TYPE=1,C_PROBE702_TYPE=1,C_PROBE703_TYPE=1,C_PROBE704_TYPE=1,C_PROBE705_TYPE=1,"&
"C_PROBE706_TYPE=1,C_PROBE707_TYPE=1,C_PROBE708_TYPE=1,C_PROBE709_TYPE=1,C_PROBE710_TYPE=1,C_PROBE711_TYPE=1,C_PROBE712_TYPE=1,C_PROBE713_TYPE=1,C_PROBE714_TYPE=1,C_PROBE715_TYPE=1,C_PROBE716_TYPE=1,C_PROBE717_TYPE=1,C_PROBE718_TYPE=1,C_PROBE719_TYPE=1,C_PROBE720_TYPE=1,C_PROBE721_TYPE=1,C_PROBE722_TYPE=1,C_PROBE723_TYPE=1,C_PROBE724_TYPE=1,C_PROBE725_TYPE=1,C_PROBE726_TYPE=1,C_PROBE727_TYPE=1,C_PROBE728_TYPE=1,C_PROBE729_TYPE=1,C_PROBE730_TYPE=1,C_PROBE731_TYPE=1,C_PROBE732_TYPE=1,C_PROBE733_TYPE=1,C_PROBE734_TYPE=1,C_PROBE735_TYPE=1,C_PROBE736_TYPE=1,C_PROBE737_TYPE=1,C_PROBE738_TYPE=1,C_PROBE739_TYPE=1,C_PROBE740_TYPE=1,C_PROBE741_TYPE=1,C_PROBE742_TYPE=1,C_PROBE743_TYPE=1,C_PROBE744_TYPE=1,C_PROBE745_TYPE=1,C_PROBE746_TYPE=1,C_PROBE747_TYPE=1,C_PROBE748_TYPE=1,C_PROBE749_TYPE=1,C_PROBE750_TYPE=1,C_PROBE751_TYPE=1,C_PROBE752_TYPE=1,C_PROBE753_TYPE=1,C_PROBE754_TYPE=1,C_PROBE755_TYPE=1,C_PROBE756_TYPE=1,C_PROBE757_TYPE=1,C_PROBE758_TYPE=1,C_PROBE759_TYPE=1,C_PROBE760_TYPE=1,C_PROBE761_TYPE=1,C_PROBE762_TYPE=1,C_PROBE763_TYPE=1,C_PROBE764_TYPE=1,C_PROBE765_TYPE=1,C_PROBE766_TYPE=1,C_PROBE767_TYPE=1,C_PROBE768_TYPE=1,C_PROBE769_TYPE=1,C_PROBE770_TYPE=1,C_PROBE771_TYPE=1,C_PROBE772_TYPE=1,C_PROBE773_TYPE=1,C_PROBE774_TYPE=1,C_PROBE775_TYPE=1,C_PROBE776_TYPE=1,C_PROBE777_TYPE=1,C_PROBE778_TYPE=1,C_PROBE779_TYPE=1,C_PROBE780_TYPE=1,C_PROBE781_TYPE=1,C_PROBE782_TYPE=1,C_PROBE783_TYPE=1,C_PROBE784_TYPE=1,C_PROBE785_TYPE=1,C_PROBE786_TYPE=1,C_PROBE787_TYPE=1,C_PROBE788_TYPE=1,C_PROBE789_TYPE=1,C_PROBE790_TYPE=1,C_PROBE791_TYPE=1,C_PROBE792_TYPE=1,C_PROBE793_TYPE=1,C_PROBE794_TYPE=1,C_PROBE795_TYPE=1,C_PROBE796_TYPE=1,C_PROBE797_TYPE=1,C_PROBE798_TYPE=1,C_PROBE799_TYPE=1,C_PROBE800_TYPE=1,C_PROBE801_TYPE=1,C_PROBE802_TYPE=1,C_PROBE803_TYPE=1,C_PROBE804_TYPE=1,C_PROBE805_TYPE=1,"&
"C_PROBE806_TYPE=1,C_PROBE807_TYPE=1,C_PROBE808_TYPE=1,C_PROBE809_TYPE=1,C_PROBE810_TYPE=1,C_PROBE811_TYPE=1,C_PROBE812_TYPE=1,C_PROBE813_TYPE=1,C_PROBE814_TYPE=1,C_PROBE815_TYPE=1,C_PROBE816_TYPE=1,C_PROBE817_TYPE=1,C_PROBE818_TYPE=1,C_PROBE819_TYPE=1,C_PROBE820_TYPE=1,C_PROBE821_TYPE=1,C_PROBE822_TYPE=1,C_PROBE823_TYPE=1,C_PROBE824_TYPE=1,C_PROBE825_TYPE=1,C_PROBE826_TYPE=1,C_PROBE827_TYPE=1,C_PROBE828_TYPE=1,C_PROBE829_TYPE=1,C_PROBE830_TYPE=1,C_PROBE831_TYPE=1,C_PROBE832_TYPE=1,C_PROBE833_TYPE=1,C_PROBE834_TYPE=1,C_PROBE835_TYPE=1,C_PROBE836_TYPE=1,C_PROBE837_TYPE=1,C_PROBE838_TYPE=1,C_PROBE839_TYPE=1,C_PROBE840_TYPE=1,C_PROBE841_TYPE=1,C_PROBE842_TYPE=1,C_PROBE843_TYPE=1,C_PROBE844_TYPE=1,C_PROBE845_TYPE=1,C_PROBE846_TYPE=1,C_PROBE847_TYPE=1,C_PROBE848_TYPE=1,C_PROBE849_TYPE=1,C_PROBE850_TYPE=1,C_PROBE851_TYPE=1,C_PROBE852_TYPE=1,C_PROBE853_TYPE=1,C_PROBE854_TYPE=1,C_PROBE855_TYPE=1,C_PROBE856_TYPE=1,C_PROBE857_TYPE=1,C_PROBE858_TYPE=1,C_PROBE859_TYPE=1,C_PROBE860_TYPE=1,C_PROBE861_TYPE=1,C_PROBE862_TYPE=1,C_PROBE863_TYPE=1,C_PROBE864_TYPE=1,C_PROBE865_TYPE=1,C_PROBE866_TYPE=1,C_PROBE867_TYPE=1,C_PROBE868_TYPE=1,C_PROBE869_TYPE=1,C_PROBE870_TYPE=1,C_PROBE871_TYPE=1,C_PROBE872_TYPE=1,C_PROBE873_TYPE=1,C_PROBE874_TYPE=1,C_PROBE875_TYPE=1,C_PROBE876_TYPE=1,C_PROBE877_TYPE=1,C_PROBE878_TYPE=1,C_PROBE879_TYPE=1,C_PROBE880_TYPE=1,C_PROBE881_TYPE=1,C_PROBE882_TYPE=1,C_PROBE883_TYPE=1,C_PROBE884_TYPE=1,C_PROBE885_TYPE=1,C_PROBE886_TYPE=1,C_PROBE887_TYPE=1,C_PROBE888_TYPE=1,C_PROBE889_TYPE=1,C_PROBE890_TYPE=1,C_PROBE891_TYPE=1,C_PROBE892_TYPE=1,C_PROBE893_TYPE=1,C_PROBE894_TYPE=1,C_PROBE895_TYPE=1,C_PROBE896_TYPE=1,C_PROBE897_TYPE=1,C_PROBE898_TYPE=1,C_PROBE899_TYPE=1,C_PROBE900_TYPE=1,C_PROBE901_TYPE=1,C_PROBE902_TYPE=1,C_PROBE903_TYPE=1,C_PROBE904_TYPE=1,C_PROBE905_TYPE=1,"&
"C_PROBE906_TYPE=1,C_PROBE907_TYPE=1,C_PROBE908_TYPE=1,C_PROBE909_TYPE=1,C_PROBE910_TYPE=1,C_PROBE911_TYPE=1,C_PROBE912_TYPE=1,C_PROBE913_TYPE=1,C_PROBE914_TYPE=1,C_PROBE915_TYPE=1,C_PROBE916_TYPE=1,C_PROBE917_TYPE=1,C_PROBE918_TYPE=1,C_PROBE919_TYPE=1,C_PROBE920_TYPE=1,C_PROBE921_TYPE=1,C_PROBE922_TYPE=1,C_PROBE923_TYPE=1,C_PROBE924_TYPE=1,C_PROBE925_TYPE=1,C_PROBE926_TYPE=1,C_PROBE927_TYPE=1,C_PROBE928_TYPE=1,C_PROBE929_TYPE=1,C_PROBE930_TYPE=1,C_PROBE931_TYPE=1,C_PROBE932_TYPE=1,C_PROBE933_TYPE=1,C_PROBE934_TYPE=1,C_PROBE935_TYPE=1,C_PROBE936_TYPE=1,C_PROBE937_TYPE=1,C_PROBE938_TYPE=1,C_PROBE939_TYPE=1,C_PROBE940_TYPE=1,C_PROBE941_TYPE=1,C_PROBE942_TYPE=1,C_PROBE943_TYPE=1,C_PROBE944_TYPE=1,C_PROBE945_TYPE=1,C_PROBE946_TYPE=1,C_PROBE947_TYPE=1,C_PROBE948_TYPE=1,C_PROBE949_TYPE=1,C_PROBE950_TYPE=1,C_PROBE951_TYPE=1,C_PROBE952_TYPE=1,C_PROBE953_TYPE=1,C_PROBE954_TYPE=1,C_PROBE955_TYPE=1,C_PROBE956_TYPE=1,C_PROBE957_TYPE=1,C_PROBE958_TYPE=1,C_PROBE959_TYPE=1,C_PROBE960_TYPE=1,C_PROBE961_TYPE=1,C_PROBE962_TYPE=1,C_PROBE963_TYPE=1,C_PROBE964_TYPE=1,C_PROBE965_TYPE=1,C_PROBE966_TYPE=1,C_PROBE967_TYPE=1,C_PROBE968_TYPE=1,C_PROBE969_TYPE=1,C_PROBE970_TYPE=1,C_PROBE971_TYPE=1,C_PROBE972_TYPE=1,C_PROBE973_TYPE=1,C_PROBE974_TYPE=1,C_PROBE975_TYPE=1,C_PROBE976_TYPE=1,C_PROBE977_TYPE=1,C_PROBE978_TYPE=1,C_PROBE979_TYPE=1,C_PROBE980_TYPE=1,C_PROBE981_TYPE=1,C_PROBE982_TYPE=1,C_PROBE983_TYPE=1,C_PROBE984_TYPE=1,C_PROBE985_TYPE=1,C_PROBE986_TYPE=1,C_PROBE987_TYPE=1,C_PROBE988_TYPE=1,C_PROBE989_TYPE=1,C_PROBE990_TYPE=1,C_PROBE991_TYPE=1,C_PROBE992_TYPE=1,C_PROBE993_TYPE=1,C_PROBE994_TYPE=1,C_PROBE995_TYPE=1,C_PROBE996_TYPE=1,C_PROBE997_TYPE=1,C_PROBE998_TYPE=1,C_PROBE999_TYPE=1,C_PROBE1000_TYPE=1,C_PROBE1001_TYPE=1,C_PROBE1002_TYPE=1,C_PROBE1003_TYPE=1,C_PROBE1004_TYPE=1,C_PROBE1005_TYPE=1,"&
"C_PROBE1006_TYPE=1,C_PROBE1007_TYPE=1,C_PROBE1008_TYPE=1,C_PROBE1009_TYPE=1,C_PROBE1010_TYPE=1,C_PROBE1011_TYPE=1,C_PROBE1012_TYPE=1,C_PROBE1013_TYPE=1,C_PROBE1014_TYPE=1,C_PROBE1015_TYPE=1,C_PROBE1016_TYPE=1,C_PROBE1017_TYPE=1,C_PROBE1018_TYPE=1,C_PROBE1019_TYPE=1,C_PROBE1020_TYPE=1,C_PROBE1021_TYPE=1,C_PROBE1022_TYPE=1,C_PROBE1023_TYPE=1},";
attribute syn_noprune : boolean;
attribute syn_noprune of U0 : label is true;
SIGNAL sl_iport0 : STD_LOGIC_VECTOR (36 downto 0);
SIGNAL sl_oport0 : STD_LOGIC_VECTOR (16 downto 0);
BEGIN
U0 : ila_v6_2_4_ila
GENERIC MAP (
C_XLNX_HW_PROBE_INFO => "DEFAULT",
C_XDEVICEFAMILY => "artix7",
C_CORE_TYPE => 1,
C_CORE_INFO1 => 0,
C_CORE_INFO2 => 0,
C_CAPTURE_TYPE => 0,
C_MU_TYPE => 0,
C_TC_TYPE => 0,
C_NUM_OF_PROBES => 4,
C_DATA_DEPTH => 8192,
C_MAJOR_VERSION => 2017,
C_MINOR_VERSION => 3,
C_BUILD_REVISION => 0,
C_CORE_MAJOR_VER => 6,
C_CORE_MINOR_VER => 2,
C_XSDB_SLAVE_TYPE => 17,
C_NEXT_SLAVE => 0,
C_CSE_DRV_VER => 2,
C_USE_TEST_REG => 1,
C_PIPE_IFACE => 1,
C_RAM_STYLE => "SUBCORE",
C_TRIGOUT_EN => 0,
C_TRIGIN_EN => 0,
C_ADV_TRIGGER => 0,
C_EN_DDR_ILA => 0,
C_EN_STRG_QUAL => 1,
C_INPUT_PIPE_STAGES => 0,
C_EN_TIME_TAG => 0,
C_TIME_TAG_WIDTH => 32,
C_ILA_CLK_FREQ => 72000000,
C_PROBE0_WIDTH => 1,
C_PROBE1_WIDTH => 8,
C_PROBE2_WIDTH => 1,
C_PROBE3_WIDTH => 8,
C_PROBE4_WIDTH => 1,
C_PROBE5_WIDTH => 1,
C_PROBE6_WIDTH => 1,
C_PROBE7_WIDTH => 1,
C_PROBE8_WIDTH => 1,
C_PROBE9_WIDTH => 1,
C_PROBE10_WIDTH => 1,
C_PROBE11_WIDTH => 1,
C_PROBE12_WIDTH => 1,
C_PROBE13_WIDTH => 1,
C_PROBE14_WIDTH => 1,
C_PROBE15_WIDTH => 1,
C_PROBE16_WIDTH => 1,
C_PROBE17_WIDTH => 1,
C_PROBE18_WIDTH => 1,
C_PROBE19_WIDTH => 1,
C_PROBE20_WIDTH => 1,
C_PROBE21_WIDTH => 1,
C_PROBE22_WIDTH => 1,
C_PROBE23_WIDTH => 1,
C_PROBE24_WIDTH => 1,
C_PROBE25_WIDTH => 1,
C_PROBE26_WIDTH => 1,
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C_PROBE708_WIDTH => 1,
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C_PROBE796_WIDTH => 1,
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C_PROBE813_WIDTH => 1,
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C_PROBE816_WIDTH => 1,
C_PROBE817_WIDTH => 1,
C_PROBE818_WIDTH => 1,
C_PROBE819_WIDTH => 1,
C_PROBE820_WIDTH => 1,
C_PROBE821_WIDTH => 1,
C_PROBE822_WIDTH => 1,
C_PROBE823_WIDTH => 1,
C_PROBE824_WIDTH => 1,
C_PROBE825_WIDTH => 1,
C_PROBE826_WIDTH => 1,
C_PROBE827_WIDTH => 1,
C_PROBE828_WIDTH => 1,
C_PROBE829_WIDTH => 1,
C_PROBE830_WIDTH => 1,
C_PROBE831_WIDTH => 1,
C_PROBE832_WIDTH => 1,
C_PROBE833_WIDTH => 1,
C_PROBE834_WIDTH => 1,
C_PROBE835_WIDTH => 1,
C_PROBE836_WIDTH => 1,
C_PROBE837_WIDTH => 1,
C_PROBE838_WIDTH => 1,
C_PROBE839_WIDTH => 1,
C_PROBE840_WIDTH => 1,
C_PROBE841_WIDTH => 1,
C_PROBE842_WIDTH => 1,
C_PROBE843_WIDTH => 1,
C_PROBE844_WIDTH => 1,
C_PROBE845_WIDTH => 1,
C_PROBE846_WIDTH => 1,
C_PROBE847_WIDTH => 1,
C_PROBE848_WIDTH => 1,
C_PROBE849_WIDTH => 1,
C_PROBE850_WIDTH => 1,
C_PROBE851_WIDTH => 1,
C_PROBE852_WIDTH => 1,
C_PROBE853_WIDTH => 1,
C_PROBE854_WIDTH => 1,
C_PROBE855_WIDTH => 1,
C_PROBE856_WIDTH => 1,
C_PROBE857_WIDTH => 1,
C_PROBE858_WIDTH => 1,
C_PROBE859_WIDTH => 1,
C_PROBE860_WIDTH => 1,
C_PROBE861_WIDTH => 1,
C_PROBE862_WIDTH => 1,
C_PROBE863_WIDTH => 1,
C_PROBE864_WIDTH => 1,
C_PROBE865_WIDTH => 1,
C_PROBE866_WIDTH => 1,
C_PROBE867_WIDTH => 1,
C_PROBE868_WIDTH => 1,
C_PROBE869_WIDTH => 1,
C_PROBE870_WIDTH => 1,
C_PROBE871_WIDTH => 1,
C_PROBE872_WIDTH => 1,
C_PROBE873_WIDTH => 1,
C_PROBE874_WIDTH => 1,
C_PROBE875_WIDTH => 1,
C_PROBE876_WIDTH => 1,
C_PROBE877_WIDTH => 1,
C_PROBE878_WIDTH => 1,
C_PROBE879_WIDTH => 1,
C_PROBE880_WIDTH => 1,
C_PROBE881_WIDTH => 1,
C_PROBE882_WIDTH => 1,
C_PROBE883_WIDTH => 1,
C_PROBE884_WIDTH => 1,
C_PROBE885_WIDTH => 1,
C_PROBE886_WIDTH => 1,
C_PROBE887_WIDTH => 1,
C_PROBE888_WIDTH => 1,
C_PROBE889_WIDTH => 1,
C_PROBE890_WIDTH => 1,
C_PROBE891_WIDTH => 1,
C_PROBE892_WIDTH => 1,
C_PROBE893_WIDTH => 1,
C_PROBE894_WIDTH => 1,
C_PROBE895_WIDTH => 1,
C_PROBE896_WIDTH => 1,
C_PROBE897_WIDTH => 1,
C_PROBE898_WIDTH => 1,
C_PROBE899_WIDTH => 1,
C_PROBE900_WIDTH => 1,
C_PROBE901_WIDTH => 1,
C_PROBE902_WIDTH => 1,
C_PROBE903_WIDTH => 1,
C_PROBE904_WIDTH => 1,
C_PROBE905_WIDTH => 1,
C_PROBE906_WIDTH => 1,
C_PROBE907_WIDTH => 1,
C_PROBE908_WIDTH => 1,
C_PROBE909_WIDTH => 1,
C_PROBE910_WIDTH => 1,
C_PROBE911_WIDTH => 1,
C_PROBE912_WIDTH => 1,
C_PROBE913_WIDTH => 1,
C_PROBE914_WIDTH => 1,
C_PROBE915_WIDTH => 1,
C_PROBE916_WIDTH => 1,
C_PROBE917_WIDTH => 1,
C_PROBE918_WIDTH => 1,
C_PROBE919_WIDTH => 1,
C_PROBE920_WIDTH => 1,
C_PROBE921_WIDTH => 1,
C_PROBE922_WIDTH => 1,
C_PROBE923_WIDTH => 1,
C_PROBE924_WIDTH => 1,
C_PROBE925_WIDTH => 1,
C_PROBE926_WIDTH => 1,
C_PROBE927_WIDTH => 1,
C_PROBE928_WIDTH => 1,
C_PROBE929_WIDTH => 1,
C_PROBE930_WIDTH => 1,
C_PROBE931_WIDTH => 1,
C_PROBE932_WIDTH => 1,
C_PROBE933_WIDTH => 1,
C_PROBE934_WIDTH => 1,
C_PROBE935_WIDTH => 1,
C_PROBE936_WIDTH => 1,
C_PROBE937_WIDTH => 1,
C_PROBE938_WIDTH => 1,
C_PROBE939_WIDTH => 1,
C_PROBE940_WIDTH => 1,
C_PROBE941_WIDTH => 1,
C_PROBE942_WIDTH => 1,
C_PROBE943_WIDTH => 1,
C_PROBE944_WIDTH => 1,
C_PROBE945_WIDTH => 1,
C_PROBE946_WIDTH => 1,
C_PROBE947_WIDTH => 1,
C_PROBE948_WIDTH => 1,
C_PROBE949_WIDTH => 1,
C_PROBE950_WIDTH => 1,
C_PROBE951_WIDTH => 1,
C_PROBE952_WIDTH => 1,
C_PROBE953_WIDTH => 1,
C_PROBE954_WIDTH => 1,
C_PROBE955_WIDTH => 1,
C_PROBE956_WIDTH => 1,
C_PROBE957_WIDTH => 1,
C_PROBE958_WIDTH => 1,
C_PROBE959_WIDTH => 1,
C_PROBE960_WIDTH => 1,
C_PROBE961_WIDTH => 1,
C_PROBE962_WIDTH => 1,
C_PROBE963_WIDTH => 1,
C_PROBE964_WIDTH => 1,
C_PROBE965_WIDTH => 1,
C_PROBE966_WIDTH => 1,
C_PROBE967_WIDTH => 1,
C_PROBE968_WIDTH => 1,
C_PROBE969_WIDTH => 1,
C_PROBE970_WIDTH => 1,
C_PROBE971_WIDTH => 1,
C_PROBE972_WIDTH => 1,
C_PROBE973_WIDTH => 1,
C_PROBE974_WIDTH => 1,
C_PROBE975_WIDTH => 1,
C_PROBE976_WIDTH => 1,
C_PROBE977_WIDTH => 1,
C_PROBE978_WIDTH => 1,
C_PROBE979_WIDTH => 1,
C_PROBE980_WIDTH => 1,
C_PROBE981_WIDTH => 1,
C_PROBE982_WIDTH => 1,
C_PROBE983_WIDTH => 1,
C_PROBE984_WIDTH => 1,
C_PROBE985_WIDTH => 1,
C_PROBE986_WIDTH => 1,
C_PROBE987_WIDTH => 1,
C_PROBE988_WIDTH => 1,
C_PROBE989_WIDTH => 1,
C_PROBE990_WIDTH => 1,
C_PROBE991_WIDTH => 1,
C_PROBE992_WIDTH => 1,
C_PROBE993_WIDTH => 1,
C_PROBE994_WIDTH => 1,
C_PROBE995_WIDTH => 1,
C_PROBE996_WIDTH => 1,
C_PROBE997_WIDTH => 1,
C_PROBE998_WIDTH => 1,
C_PROBE999_WIDTH => 1,
C_PROBE1000_WIDTH => 1,
C_PROBE1001_WIDTH => 1,
C_PROBE1002_WIDTH => 1,
C_PROBE1003_WIDTH => 1,
C_PROBE1004_WIDTH => 1,
C_PROBE1005_WIDTH => 1,
C_PROBE1006_WIDTH => 1,
C_PROBE1007_WIDTH => 1,
C_PROBE1008_WIDTH => 1,
C_PROBE1009_WIDTH => 1,
C_PROBE1010_WIDTH => 1,
C_PROBE1011_WIDTH => 1,
C_PROBE1012_WIDTH => 1,
C_PROBE1013_WIDTH => 1,
C_PROBE1014_WIDTH => 1,
C_PROBE1015_WIDTH => 1,
C_PROBE1016_WIDTH => 1,
C_PROBE1017_WIDTH => 1,
C_PROBE1018_WIDTH => 1,
C_PROBE1019_WIDTH => 1,
C_PROBE1020_WIDTH => 1,
C_PROBE1021_WIDTH => 1,
C_PROBE1022_WIDTH => 1,
C_PROBE1023_WIDTH => 1,
C_PROBE0_MU_CNT => 2,
C_PROBE1_MU_CNT => 2,
C_PROBE2_MU_CNT => 2,
C_PROBE3_MU_CNT => 2,
C_PROBE4_MU_CNT => 1,
C_PROBE5_MU_CNT => 1,
C_PROBE6_MU_CNT => 1,
C_PROBE7_MU_CNT => 1,
C_PROBE8_MU_CNT => 1,
C_PROBE9_MU_CNT => 1,
C_PROBE10_MU_CNT => 1,
C_PROBE11_MU_CNT => 1,
C_PROBE12_MU_CNT => 1,
C_PROBE13_MU_CNT => 1,
C_PROBE14_MU_CNT => 1,
C_PROBE15_MU_CNT => 1,
C_PROBE16_MU_CNT => 1,
C_PROBE17_MU_CNT => 1,
C_PROBE18_MU_CNT => 1,
C_PROBE19_MU_CNT => 1,
C_PROBE20_MU_CNT => 1,
C_PROBE21_MU_CNT => 1,
C_PROBE22_MU_CNT => 1,
C_PROBE23_MU_CNT => 1,
C_PROBE24_MU_CNT => 1,
C_PROBE25_MU_CNT => 1,
C_PROBE26_MU_CNT => 1,
C_PROBE27_MU_CNT => 1,
C_PROBE28_MU_CNT => 1,
C_PROBE29_MU_CNT => 1,
C_PROBE30_MU_CNT => 1,
C_PROBE31_MU_CNT => 1,
C_PROBE32_MU_CNT => 1,
C_PROBE33_MU_CNT => 1,
C_PROBE34_MU_CNT => 1,
C_PROBE35_MU_CNT => 1,
C_PROBE36_MU_CNT => 1,
C_PROBE37_MU_CNT => 1,
C_PROBE38_MU_CNT => 1,
C_PROBE39_MU_CNT => 1,
C_PROBE40_MU_CNT => 1,
C_PROBE41_MU_CNT => 1,
C_PROBE42_MU_CNT => 1,
C_PROBE43_MU_CNT => 1,
C_PROBE44_MU_CNT => 1,
C_PROBE45_MU_CNT => 1,
C_PROBE46_MU_CNT => 1,
C_PROBE47_MU_CNT => 1,
C_PROBE48_MU_CNT => 1,
C_PROBE49_MU_CNT => 1,
C_PROBE50_MU_CNT => 1,
C_PROBE51_MU_CNT => 1,
C_PROBE52_MU_CNT => 1,
C_PROBE53_MU_CNT => 1,
C_PROBE54_MU_CNT => 1,
C_PROBE55_MU_CNT => 1,
C_PROBE56_MU_CNT => 1,
C_PROBE57_MU_CNT => 1,
C_PROBE58_MU_CNT => 1,
C_PROBE59_MU_CNT => 1,
C_PROBE60_MU_CNT => 1,
C_PROBE61_MU_CNT => 1,
C_PROBE62_MU_CNT => 1,
C_PROBE63_MU_CNT => 1,
C_PROBE64_MU_CNT => 1,
C_PROBE65_MU_CNT => 1,
C_PROBE66_MU_CNT => 1,
C_PROBE67_MU_CNT => 1,
C_PROBE68_MU_CNT => 1,
C_PROBE69_MU_CNT => 1,
C_PROBE70_MU_CNT => 1,
C_PROBE71_MU_CNT => 1,
C_PROBE72_MU_CNT => 1,
C_PROBE73_MU_CNT => 1,
C_PROBE74_MU_CNT => 1,
C_PROBE75_MU_CNT => 1,
C_PROBE76_MU_CNT => 1,
C_PROBE77_MU_CNT => 1,
C_PROBE78_MU_CNT => 1,
C_PROBE79_MU_CNT => 1,
C_PROBE80_MU_CNT => 1,
C_PROBE81_MU_CNT => 1,
C_PROBE82_MU_CNT => 1,
C_PROBE83_MU_CNT => 1,
C_PROBE84_MU_CNT => 1,
C_PROBE85_MU_CNT => 1,
C_PROBE86_MU_CNT => 1,
C_PROBE87_MU_CNT => 1,
C_PROBE88_MU_CNT => 1,
C_PROBE89_MU_CNT => 1,
C_PROBE90_MU_CNT => 1,
C_PROBE91_MU_CNT => 1,
C_PROBE92_MU_CNT => 1,
C_PROBE93_MU_CNT => 1,
C_PROBE94_MU_CNT => 1,
C_PROBE95_MU_CNT => 1,
C_PROBE96_MU_CNT => 1,
C_PROBE97_MU_CNT => 1,
C_PROBE98_MU_CNT => 1,
C_PROBE99_MU_CNT => 1,
C_PROBE100_MU_CNT => 1,
C_PROBE101_MU_CNT => 1,
C_PROBE102_MU_CNT => 1,
C_PROBE103_MU_CNT => 1,
C_PROBE104_MU_CNT => 1,
C_PROBE105_MU_CNT => 1,
C_PROBE106_MU_CNT => 1,
C_PROBE107_MU_CNT => 1,
C_PROBE108_MU_CNT => 1,
C_PROBE109_MU_CNT => 1,
C_PROBE110_MU_CNT => 1,
C_PROBE111_MU_CNT => 1,
C_PROBE112_MU_CNT => 1,
C_PROBE113_MU_CNT => 1,
C_PROBE114_MU_CNT => 1,
C_PROBE115_MU_CNT => 1,
C_PROBE116_MU_CNT => 1,
C_PROBE117_MU_CNT => 1,
C_PROBE118_MU_CNT => 1,
C_PROBE119_MU_CNT => 1,
C_PROBE120_MU_CNT => 1,
C_PROBE121_MU_CNT => 1,
C_PROBE122_MU_CNT => 1,
C_PROBE123_MU_CNT => 1,
C_PROBE124_MU_CNT => 1,
C_PROBE125_MU_CNT => 1,
C_PROBE126_MU_CNT => 1,
C_PROBE127_MU_CNT => 1,
C_PROBE128_MU_CNT => 1,
C_PROBE129_MU_CNT => 1,
C_PROBE130_MU_CNT => 1,
C_PROBE131_MU_CNT => 1,
C_PROBE132_MU_CNT => 1,
C_PROBE133_MU_CNT => 1,
C_PROBE134_MU_CNT => 1,
C_PROBE135_MU_CNT => 1,
C_PROBE136_MU_CNT => 1,
C_PROBE137_MU_CNT => 1,
C_PROBE138_MU_CNT => 1,
C_PROBE139_MU_CNT => 1,
C_PROBE140_MU_CNT => 1,
C_PROBE141_MU_CNT => 1,
C_PROBE142_MU_CNT => 1,
C_PROBE143_MU_CNT => 1,
C_PROBE144_MU_CNT => 1,
C_PROBE145_MU_CNT => 1,
C_PROBE146_MU_CNT => 1,
C_PROBE147_MU_CNT => 1,
C_PROBE148_MU_CNT => 1,
C_PROBE149_MU_CNT => 1,
C_PROBE150_MU_CNT => 1,
C_PROBE151_MU_CNT => 1,
C_PROBE152_MU_CNT => 1,
C_PROBE153_MU_CNT => 1,
C_PROBE154_MU_CNT => 1,
C_PROBE155_MU_CNT => 1,
C_PROBE156_MU_CNT => 1,
C_PROBE157_MU_CNT => 1,
C_PROBE158_MU_CNT => 1,
C_PROBE159_MU_CNT => 1,
C_PROBE160_MU_CNT => 1,
C_PROBE161_MU_CNT => 1,
C_PROBE162_MU_CNT => 1,
C_PROBE163_MU_CNT => 1,
C_PROBE164_MU_CNT => 1,
C_PROBE165_MU_CNT => 1,
C_PROBE166_MU_CNT => 1,
C_PROBE167_MU_CNT => 1,
C_PROBE168_MU_CNT => 1,
C_PROBE169_MU_CNT => 1,
C_PROBE170_MU_CNT => 1,
C_PROBE171_MU_CNT => 1,
C_PROBE172_MU_CNT => 1,
C_PROBE173_MU_CNT => 1,
C_PROBE174_MU_CNT => 1,
C_PROBE175_MU_CNT => 1,
C_PROBE176_MU_CNT => 1,
C_PROBE177_MU_CNT => 1,
C_PROBE178_MU_CNT => 1,
C_PROBE179_MU_CNT => 1,
C_PROBE180_MU_CNT => 1,
C_PROBE181_MU_CNT => 1,
C_PROBE182_MU_CNT => 1,
C_PROBE183_MU_CNT => 1,
C_PROBE184_MU_CNT => 1,
C_PROBE185_MU_CNT => 1,
C_PROBE186_MU_CNT => 1,
C_PROBE187_MU_CNT => 1,
C_PROBE188_MU_CNT => 1,
C_PROBE189_MU_CNT => 1,
C_PROBE190_MU_CNT => 1,
C_PROBE191_MU_CNT => 1,
C_PROBE192_MU_CNT => 1,
C_PROBE193_MU_CNT => 1,
C_PROBE194_MU_CNT => 1,
C_PROBE195_MU_CNT => 1,
C_PROBE196_MU_CNT => 1,
C_PROBE197_MU_CNT => 1,
C_PROBE198_MU_CNT => 1,
C_PROBE199_MU_CNT => 1,
C_PROBE200_MU_CNT => 1,
C_PROBE201_MU_CNT => 1,
C_PROBE202_MU_CNT => 1,
C_PROBE203_MU_CNT => 1,
C_PROBE204_MU_CNT => 1,
C_PROBE205_MU_CNT => 1,
C_PROBE206_MU_CNT => 1,
C_PROBE207_MU_CNT => 1,
C_PROBE208_MU_CNT => 1,
C_PROBE209_MU_CNT => 1,
C_PROBE210_MU_CNT => 1,
C_PROBE211_MU_CNT => 1,
C_PROBE212_MU_CNT => 1,
C_PROBE213_MU_CNT => 1,
C_PROBE214_MU_CNT => 1,
C_PROBE215_MU_CNT => 1,
C_PROBE216_MU_CNT => 1,
C_PROBE217_MU_CNT => 1,
C_PROBE218_MU_CNT => 1,
C_PROBE219_MU_CNT => 1,
C_PROBE220_MU_CNT => 1,
C_PROBE221_MU_CNT => 1,
C_PROBE222_MU_CNT => 1,
C_PROBE223_MU_CNT => 1,
C_PROBE224_MU_CNT => 1,
C_PROBE225_MU_CNT => 1,
C_PROBE226_MU_CNT => 1,
C_PROBE227_MU_CNT => 1,
C_PROBE228_MU_CNT => 1,
C_PROBE229_MU_CNT => 1,
C_PROBE230_MU_CNT => 1,
C_PROBE231_MU_CNT => 1,
C_PROBE232_MU_CNT => 1,
C_PROBE233_MU_CNT => 1,
C_PROBE234_MU_CNT => 1,
C_PROBE235_MU_CNT => 1,
C_PROBE236_MU_CNT => 1,
C_PROBE237_MU_CNT => 1,
C_PROBE238_MU_CNT => 1,
C_PROBE239_MU_CNT => 1,
C_PROBE240_MU_CNT => 1,
C_PROBE241_MU_CNT => 1,
C_PROBE242_MU_CNT => 1,
C_PROBE243_MU_CNT => 1,
C_PROBE244_MU_CNT => 1,
C_PROBE245_MU_CNT => 1,
C_PROBE246_MU_CNT => 1,
C_PROBE247_MU_CNT => 1,
C_PROBE248_MU_CNT => 1,
C_PROBE249_MU_CNT => 1,
C_PROBE250_MU_CNT => 1,
C_PROBE251_MU_CNT => 1,
C_PROBE252_MU_CNT => 1,
C_PROBE253_MU_CNT => 1,
C_PROBE254_MU_CNT => 1,
C_PROBE255_MU_CNT => 1,
C_PROBE256_MU_CNT => 1,
C_PROBE257_MU_CNT => 1,
C_PROBE258_MU_CNT => 1,
C_PROBE259_MU_CNT => 1,
C_PROBE260_MU_CNT => 1,
C_PROBE261_MU_CNT => 1,
C_PROBE262_MU_CNT => 1,
C_PROBE263_MU_CNT => 1,
C_PROBE264_MU_CNT => 1,
C_PROBE265_MU_CNT => 1,
C_PROBE266_MU_CNT => 1,
C_PROBE267_MU_CNT => 1,
C_PROBE268_MU_CNT => 1,
C_PROBE269_MU_CNT => 1,
C_PROBE270_MU_CNT => 1,
C_PROBE271_MU_CNT => 1,
C_PROBE272_MU_CNT => 1,
C_PROBE273_MU_CNT => 1,
C_PROBE274_MU_CNT => 1,
C_PROBE275_MU_CNT => 1,
C_PROBE276_MU_CNT => 1,
C_PROBE277_MU_CNT => 1,
C_PROBE278_MU_CNT => 1,
C_PROBE279_MU_CNT => 1,
C_PROBE280_MU_CNT => 1,
C_PROBE281_MU_CNT => 1,
C_PROBE282_MU_CNT => 1,
C_PROBE283_MU_CNT => 1,
C_PROBE284_MU_CNT => 1,
C_PROBE285_MU_CNT => 1,
C_PROBE286_MU_CNT => 1,
C_PROBE287_MU_CNT => 1,
C_PROBE288_MU_CNT => 1,
C_PROBE289_MU_CNT => 1,
C_PROBE290_MU_CNT => 1,
C_PROBE291_MU_CNT => 1,
C_PROBE292_MU_CNT => 1,
C_PROBE293_MU_CNT => 1,
C_PROBE294_MU_CNT => 1,
C_PROBE295_MU_CNT => 1,
C_PROBE296_MU_CNT => 1,
C_PROBE297_MU_CNT => 1,
C_PROBE298_MU_CNT => 1,
C_PROBE299_MU_CNT => 1,
C_PROBE300_MU_CNT => 1,
C_PROBE301_MU_CNT => 1,
C_PROBE302_MU_CNT => 1,
C_PROBE303_MU_CNT => 1,
C_PROBE304_MU_CNT => 1,
C_PROBE305_MU_CNT => 1,
C_PROBE306_MU_CNT => 1,
C_PROBE307_MU_CNT => 1,
C_PROBE308_MU_CNT => 1,
C_PROBE309_MU_CNT => 1,
C_PROBE310_MU_CNT => 1,
C_PROBE311_MU_CNT => 1,
C_PROBE312_MU_CNT => 1,
C_PROBE313_MU_CNT => 1,
C_PROBE314_MU_CNT => 1,
C_PROBE315_MU_CNT => 1,
C_PROBE316_MU_CNT => 1,
C_PROBE317_MU_CNT => 1,
C_PROBE318_MU_CNT => 1,
C_PROBE319_MU_CNT => 1,
C_PROBE320_MU_CNT => 1,
C_PROBE321_MU_CNT => 1,
C_PROBE322_MU_CNT => 1,
C_PROBE323_MU_CNT => 1,
C_PROBE324_MU_CNT => 1,
C_PROBE325_MU_CNT => 1,
C_PROBE326_MU_CNT => 1,
C_PROBE327_MU_CNT => 1,
C_PROBE328_MU_CNT => 1,
C_PROBE329_MU_CNT => 1,
C_PROBE330_MU_CNT => 1,
C_PROBE331_MU_CNT => 1,
C_PROBE332_MU_CNT => 1,
C_PROBE333_MU_CNT => 1,
C_PROBE334_MU_CNT => 1,
C_PROBE335_MU_CNT => 1,
C_PROBE336_MU_CNT => 1,
C_PROBE337_MU_CNT => 1,
C_PROBE338_MU_CNT => 1,
C_PROBE339_MU_CNT => 1,
C_PROBE340_MU_CNT => 1,
C_PROBE341_MU_CNT => 1,
C_PROBE342_MU_CNT => 1,
C_PROBE343_MU_CNT => 1,
C_PROBE344_MU_CNT => 1,
C_PROBE345_MU_CNT => 1,
C_PROBE346_MU_CNT => 1,
C_PROBE347_MU_CNT => 1,
C_PROBE348_MU_CNT => 1,
C_PROBE349_MU_CNT => 1,
C_PROBE350_MU_CNT => 1,
C_PROBE351_MU_CNT => 1,
C_PROBE352_MU_CNT => 1,
C_PROBE353_MU_CNT => 1,
C_PROBE354_MU_CNT => 1,
C_PROBE355_MU_CNT => 1,
C_PROBE356_MU_CNT => 1,
C_PROBE357_MU_CNT => 1,
C_PROBE358_MU_CNT => 1,
C_PROBE359_MU_CNT => 1,
C_PROBE360_MU_CNT => 1,
C_PROBE361_MU_CNT => 1,
C_PROBE362_MU_CNT => 1,
C_PROBE363_MU_CNT => 1,
C_PROBE364_MU_CNT => 1,
C_PROBE365_MU_CNT => 1,
C_PROBE366_MU_CNT => 1,
C_PROBE367_MU_CNT => 1,
C_PROBE368_MU_CNT => 1,
C_PROBE369_MU_CNT => 1,
C_PROBE370_MU_CNT => 1,
C_PROBE371_MU_CNT => 1,
C_PROBE372_MU_CNT => 1,
C_PROBE373_MU_CNT => 1,
C_PROBE374_MU_CNT => 1,
C_PROBE375_MU_CNT => 1,
C_PROBE376_MU_CNT => 1,
C_PROBE377_MU_CNT => 1,
C_PROBE378_MU_CNT => 1,
C_PROBE379_MU_CNT => 1,
C_PROBE380_MU_CNT => 1,
C_PROBE381_MU_CNT => 1,
C_PROBE382_MU_CNT => 1,
C_PROBE383_MU_CNT => 1,
C_PROBE384_MU_CNT => 1,
C_PROBE385_MU_CNT => 1,
C_PROBE386_MU_CNT => 1,
C_PROBE387_MU_CNT => 1,
C_PROBE388_MU_CNT => 1,
C_PROBE389_MU_CNT => 1,
C_PROBE390_MU_CNT => 1,
C_PROBE391_MU_CNT => 1,
C_PROBE392_MU_CNT => 1,
C_PROBE393_MU_CNT => 1,
C_PROBE394_MU_CNT => 1,
C_PROBE395_MU_CNT => 1,
C_PROBE396_MU_CNT => 1,
C_PROBE397_MU_CNT => 1,
C_PROBE398_MU_CNT => 1,
C_PROBE399_MU_CNT => 1,
C_PROBE400_MU_CNT => 1,
C_PROBE401_MU_CNT => 1,
C_PROBE402_MU_CNT => 1,
C_PROBE403_MU_CNT => 1,
C_PROBE404_MU_CNT => 1,
C_PROBE405_MU_CNT => 1,
C_PROBE406_MU_CNT => 1,
C_PROBE407_MU_CNT => 1,
C_PROBE408_MU_CNT => 1,
C_PROBE409_MU_CNT => 1,
C_PROBE410_MU_CNT => 1,
C_PROBE411_MU_CNT => 1,
C_PROBE412_MU_CNT => 1,
C_PROBE413_MU_CNT => 1,
C_PROBE414_MU_CNT => 1,
C_PROBE415_MU_CNT => 1,
C_PROBE416_MU_CNT => 1,
C_PROBE417_MU_CNT => 1,
C_PROBE418_MU_CNT => 1,
C_PROBE419_MU_CNT => 1,
C_PROBE420_MU_CNT => 1,
C_PROBE421_MU_CNT => 1,
C_PROBE422_MU_CNT => 1,
C_PROBE423_MU_CNT => 1,
C_PROBE424_MU_CNT => 1,
C_PROBE425_MU_CNT => 1,
C_PROBE426_MU_CNT => 1,
C_PROBE427_MU_CNT => 1,
C_PROBE428_MU_CNT => 1,
C_PROBE429_MU_CNT => 1,
C_PROBE430_MU_CNT => 1,
C_PROBE431_MU_CNT => 1,
C_PROBE432_MU_CNT => 1,
C_PROBE433_MU_CNT => 1,
C_PROBE434_MU_CNT => 1,
C_PROBE435_MU_CNT => 1,
C_PROBE436_MU_CNT => 1,
C_PROBE437_MU_CNT => 1,
C_PROBE438_MU_CNT => 1,
C_PROBE439_MU_CNT => 1,
C_PROBE440_MU_CNT => 1,
C_PROBE441_MU_CNT => 1,
C_PROBE442_MU_CNT => 1,
C_PROBE443_MU_CNT => 1,
C_PROBE444_MU_CNT => 1,
C_PROBE445_MU_CNT => 1,
C_PROBE446_MU_CNT => 1,
C_PROBE447_MU_CNT => 1,
C_PROBE448_MU_CNT => 1,
C_PROBE449_MU_CNT => 1,
C_PROBE450_MU_CNT => 1,
C_PROBE451_MU_CNT => 1,
C_PROBE452_MU_CNT => 1,
C_PROBE453_MU_CNT => 1,
C_PROBE454_MU_CNT => 1,
C_PROBE455_MU_CNT => 1,
C_PROBE456_MU_CNT => 1,
C_PROBE457_MU_CNT => 1,
C_PROBE458_MU_CNT => 1,
C_PROBE459_MU_CNT => 1,
C_PROBE460_MU_CNT => 1,
C_PROBE461_MU_CNT => 1,
C_PROBE462_MU_CNT => 1,
C_PROBE463_MU_CNT => 1,
C_PROBE464_MU_CNT => 1,
C_PROBE465_MU_CNT => 1,
C_PROBE466_MU_CNT => 1,
C_PROBE467_MU_CNT => 1,
C_PROBE468_MU_CNT => 1,
C_PROBE469_MU_CNT => 1,
C_PROBE470_MU_CNT => 1,
C_PROBE471_MU_CNT => 1,
C_PROBE472_MU_CNT => 1,
C_PROBE473_MU_CNT => 1,
C_PROBE474_MU_CNT => 1,
C_PROBE475_MU_CNT => 1,
C_PROBE476_MU_CNT => 1,
C_PROBE477_MU_CNT => 1,
C_PROBE478_MU_CNT => 1,
C_PROBE479_MU_CNT => 1,
C_PROBE480_MU_CNT => 1,
C_PROBE481_MU_CNT => 1,
C_PROBE482_MU_CNT => 1,
C_PROBE483_MU_CNT => 1,
C_PROBE484_MU_CNT => 1,
C_PROBE485_MU_CNT => 1,
C_PROBE486_MU_CNT => 1,
C_PROBE487_MU_CNT => 1,
C_PROBE488_MU_CNT => 1,
C_PROBE489_MU_CNT => 1,
C_PROBE490_MU_CNT => 1,
C_PROBE491_MU_CNT => 1,
C_PROBE492_MU_CNT => 1,
C_PROBE493_MU_CNT => 1,
C_PROBE494_MU_CNT => 1,
C_PROBE495_MU_CNT => 1,
C_PROBE496_MU_CNT => 1,
C_PROBE497_MU_CNT => 1,
C_PROBE498_MU_CNT => 1,
C_PROBE499_MU_CNT => 1,
C_PROBE500_MU_CNT => 1,
C_PROBE501_MU_CNT => 1,
C_PROBE502_MU_CNT => 1,
C_PROBE503_MU_CNT => 1,
C_PROBE504_MU_CNT => 1,
C_PROBE505_MU_CNT => 1,
C_PROBE506_MU_CNT => 1,
C_PROBE507_MU_CNT => 1,
C_PROBE508_MU_CNT => 1,
C_PROBE509_MU_CNT => 1,
C_PROBE510_MU_CNT => 1,
C_PROBE511_MU_CNT => 1,
C_PROBE512_MU_CNT => 1,
C_PROBE513_MU_CNT => 1,
C_PROBE514_MU_CNT => 1,
C_PROBE515_MU_CNT => 1,
C_PROBE516_MU_CNT => 1,
C_PROBE517_MU_CNT => 1,
C_PROBE518_MU_CNT => 1,
C_PROBE519_MU_CNT => 1,
C_PROBE520_MU_CNT => 1,
C_PROBE521_MU_CNT => 1,
C_PROBE522_MU_CNT => 1,
C_PROBE523_MU_CNT => 1,
C_PROBE524_MU_CNT => 1,
C_PROBE525_MU_CNT => 1,
C_PROBE526_MU_CNT => 1,
C_PROBE527_MU_CNT => 1,
C_PROBE528_MU_CNT => 1,
C_PROBE529_MU_CNT => 1,
C_PROBE530_MU_CNT => 1,
C_PROBE531_MU_CNT => 1,
C_PROBE532_MU_CNT => 1,
C_PROBE533_MU_CNT => 1,
C_PROBE534_MU_CNT => 1,
C_PROBE535_MU_CNT => 1,
C_PROBE536_MU_CNT => 1,
C_PROBE537_MU_CNT => 1,
C_PROBE538_MU_CNT => 1,
C_PROBE539_MU_CNT => 1,
C_PROBE540_MU_CNT => 1,
C_PROBE541_MU_CNT => 1,
C_PROBE542_MU_CNT => 1,
C_PROBE543_MU_CNT => 1,
C_PROBE544_MU_CNT => 1,
C_PROBE545_MU_CNT => 1,
C_PROBE546_MU_CNT => 1,
C_PROBE547_MU_CNT => 1,
C_PROBE548_MU_CNT => 1,
C_PROBE549_MU_CNT => 1,
C_PROBE550_MU_CNT => 1,
C_PROBE551_MU_CNT => 1,
C_PROBE552_MU_CNT => 1,
C_PROBE553_MU_CNT => 1,
C_PROBE554_MU_CNT => 1,
C_PROBE555_MU_CNT => 1,
C_PROBE556_MU_CNT => 1,
C_PROBE557_MU_CNT => 1,
C_PROBE558_MU_CNT => 1,
C_PROBE559_MU_CNT => 1,
C_PROBE560_MU_CNT => 1,
C_PROBE561_MU_CNT => 1,
C_PROBE562_MU_CNT => 1,
C_PROBE563_MU_CNT => 1,
C_PROBE564_MU_CNT => 1,
C_PROBE565_MU_CNT => 1,
C_PROBE566_MU_CNT => 1,
C_PROBE567_MU_CNT => 1,
C_PROBE568_MU_CNT => 1,
C_PROBE569_MU_CNT => 1,
C_PROBE570_MU_CNT => 1,
C_PROBE571_MU_CNT => 1,
C_PROBE572_MU_CNT => 1,
C_PROBE573_MU_CNT => 1,
C_PROBE574_MU_CNT => 1,
C_PROBE575_MU_CNT => 1,
C_PROBE576_MU_CNT => 1,
C_PROBE577_MU_CNT => 1,
C_PROBE578_MU_CNT => 1,
C_PROBE579_MU_CNT => 1,
C_PROBE580_MU_CNT => 1,
C_PROBE581_MU_CNT => 1,
C_PROBE582_MU_CNT => 1,
C_PROBE583_MU_CNT => 1,
C_PROBE584_MU_CNT => 1,
C_PROBE585_MU_CNT => 1,
C_PROBE586_MU_CNT => 1,
C_PROBE587_MU_CNT => 1,
C_PROBE588_MU_CNT => 1,
C_PROBE589_MU_CNT => 1,
C_PROBE590_MU_CNT => 1,
C_PROBE591_MU_CNT => 1,
C_PROBE592_MU_CNT => 1,
C_PROBE593_MU_CNT => 1,
C_PROBE594_MU_CNT => 1,
C_PROBE595_MU_CNT => 1,
C_PROBE596_MU_CNT => 1,
C_PROBE597_MU_CNT => 1,
C_PROBE598_MU_CNT => 1,
C_PROBE599_MU_CNT => 1,
C_PROBE600_MU_CNT => 1,
C_PROBE601_MU_CNT => 1,
C_PROBE602_MU_CNT => 1,
C_PROBE603_MU_CNT => 1,
C_PROBE604_MU_CNT => 1,
C_PROBE605_MU_CNT => 1,
C_PROBE606_MU_CNT => 1,
C_PROBE607_MU_CNT => 1,
C_PROBE608_MU_CNT => 1,
C_PROBE609_MU_CNT => 1,
C_PROBE610_MU_CNT => 1,
C_PROBE611_MU_CNT => 1,
C_PROBE612_MU_CNT => 1,
C_PROBE613_MU_CNT => 1,
C_PROBE614_MU_CNT => 1,
C_PROBE615_MU_CNT => 1,
C_PROBE616_MU_CNT => 1,
C_PROBE617_MU_CNT => 1,
C_PROBE618_MU_CNT => 1,
C_PROBE619_MU_CNT => 1,
C_PROBE620_MU_CNT => 1,
C_PROBE621_MU_CNT => 1,
C_PROBE622_MU_CNT => 1,
C_PROBE623_MU_CNT => 1,
C_PROBE624_MU_CNT => 1,
C_PROBE625_MU_CNT => 1,
C_PROBE626_MU_CNT => 1,
C_PROBE627_MU_CNT => 1,
C_PROBE628_MU_CNT => 1,
C_PROBE629_MU_CNT => 1,
C_PROBE630_MU_CNT => 1,
C_PROBE631_MU_CNT => 1,
C_PROBE632_MU_CNT => 1,
C_PROBE633_MU_CNT => 1,
C_PROBE634_MU_CNT => 1,
C_PROBE635_MU_CNT => 1,
C_PROBE636_MU_CNT => 1,
C_PROBE637_MU_CNT => 1,
C_PROBE638_MU_CNT => 1,
C_PROBE639_MU_CNT => 1,
C_PROBE640_MU_CNT => 1,
C_PROBE641_MU_CNT => 1,
C_PROBE642_MU_CNT => 1,
C_PROBE643_MU_CNT => 1,
C_PROBE644_MU_CNT => 1,
C_PROBE645_MU_CNT => 1,
C_PROBE646_MU_CNT => 1,
C_PROBE647_MU_CNT => 1,
C_PROBE648_MU_CNT => 1,
C_PROBE649_MU_CNT => 1,
C_PROBE650_MU_CNT => 1,
C_PROBE651_MU_CNT => 1,
C_PROBE652_MU_CNT => 1,
C_PROBE653_MU_CNT => 1,
C_PROBE654_MU_CNT => 1,
C_PROBE655_MU_CNT => 1,
C_PROBE656_MU_CNT => 1,
C_PROBE657_MU_CNT => 1,
C_PROBE658_MU_CNT => 1,
C_PROBE659_MU_CNT => 1,
C_PROBE660_MU_CNT => 1,
C_PROBE661_MU_CNT => 1,
C_PROBE662_MU_CNT => 1,
C_PROBE663_MU_CNT => 1,
C_PROBE664_MU_CNT => 1,
C_PROBE665_MU_CNT => 1,
C_PROBE666_MU_CNT => 1,
C_PROBE667_MU_CNT => 1,
C_PROBE668_MU_CNT => 1,
C_PROBE669_MU_CNT => 1,
C_PROBE670_MU_CNT => 1,
C_PROBE671_MU_CNT => 1,
C_PROBE672_MU_CNT => 1,
C_PROBE673_MU_CNT => 1,
C_PROBE674_MU_CNT => 1,
C_PROBE675_MU_CNT => 1,
C_PROBE676_MU_CNT => 1,
C_PROBE677_MU_CNT => 1,
C_PROBE678_MU_CNT => 1,
C_PROBE679_MU_CNT => 1,
C_PROBE680_MU_CNT => 1,
C_PROBE681_MU_CNT => 1,
C_PROBE682_MU_CNT => 1,
C_PROBE683_MU_CNT => 1,
C_PROBE684_MU_CNT => 1,
C_PROBE685_MU_CNT => 1,
C_PROBE686_MU_CNT => 1,
C_PROBE687_MU_CNT => 1,
C_PROBE688_MU_CNT => 1,
C_PROBE689_MU_CNT => 1,
C_PROBE690_MU_CNT => 1,
C_PROBE691_MU_CNT => 1,
C_PROBE692_MU_CNT => 1,
C_PROBE693_MU_CNT => 1,
C_PROBE694_MU_CNT => 1,
C_PROBE695_MU_CNT => 1,
C_PROBE696_MU_CNT => 1,
C_PROBE697_MU_CNT => 1,
C_PROBE698_MU_CNT => 1,
C_PROBE699_MU_CNT => 1,
C_PROBE700_MU_CNT => 1,
C_PROBE701_MU_CNT => 1,
C_PROBE702_MU_CNT => 1,
C_PROBE703_MU_CNT => 1,
C_PROBE704_MU_CNT => 1,
C_PROBE705_MU_CNT => 1,
C_PROBE706_MU_CNT => 1,
C_PROBE707_MU_CNT => 1,
C_PROBE708_MU_CNT => 1,
C_PROBE709_MU_CNT => 1,
C_PROBE710_MU_CNT => 1,
C_PROBE711_MU_CNT => 1,
C_PROBE712_MU_CNT => 1,
C_PROBE713_MU_CNT => 1,
C_PROBE714_MU_CNT => 1,
C_PROBE715_MU_CNT => 1,
C_PROBE716_MU_CNT => 1,
C_PROBE717_MU_CNT => 1,
C_PROBE718_MU_CNT => 1,
C_PROBE719_MU_CNT => 1,
C_PROBE720_MU_CNT => 1,
C_PROBE721_MU_CNT => 1,
C_PROBE722_MU_CNT => 1,
C_PROBE723_MU_CNT => 1,
C_PROBE724_MU_CNT => 1,
C_PROBE725_MU_CNT => 1,
C_PROBE726_MU_CNT => 1,
C_PROBE727_MU_CNT => 1,
C_PROBE728_MU_CNT => 1,
C_PROBE729_MU_CNT => 1,
C_PROBE730_MU_CNT => 1,
C_PROBE731_MU_CNT => 1,
C_PROBE732_MU_CNT => 1,
C_PROBE733_MU_CNT => 1,
C_PROBE734_MU_CNT => 1,
C_PROBE735_MU_CNT => 1,
C_PROBE736_MU_CNT => 1,
C_PROBE737_MU_CNT => 1,
C_PROBE738_MU_CNT => 1,
C_PROBE739_MU_CNT => 1,
C_PROBE740_MU_CNT => 1,
C_PROBE741_MU_CNT => 1,
C_PROBE742_MU_CNT => 1,
C_PROBE743_MU_CNT => 1,
C_PROBE744_MU_CNT => 1,
C_PROBE745_MU_CNT => 1,
C_PROBE746_MU_CNT => 1,
C_PROBE747_MU_CNT => 1,
C_PROBE748_MU_CNT => 1,
C_PROBE749_MU_CNT => 1,
C_PROBE750_MU_CNT => 1,
C_PROBE751_MU_CNT => 1,
C_PROBE752_MU_CNT => 1,
C_PROBE753_MU_CNT => 1,
C_PROBE754_MU_CNT => 1,
C_PROBE755_MU_CNT => 1,
C_PROBE756_MU_CNT => 1,
C_PROBE757_MU_CNT => 1,
C_PROBE758_MU_CNT => 1,
C_PROBE759_MU_CNT => 1,
C_PROBE760_MU_CNT => 1,
C_PROBE761_MU_CNT => 1,
C_PROBE762_MU_CNT => 1,
C_PROBE763_MU_CNT => 1,
C_PROBE764_MU_CNT => 1,
C_PROBE765_MU_CNT => 1,
C_PROBE766_MU_CNT => 1,
C_PROBE767_MU_CNT => 1,
C_PROBE768_MU_CNT => 1,
C_PROBE769_MU_CNT => 1,
C_PROBE770_MU_CNT => 1,
C_PROBE771_MU_CNT => 1,
C_PROBE772_MU_CNT => 1,
C_PROBE773_MU_CNT => 1,
C_PROBE774_MU_CNT => 1,
C_PROBE775_MU_CNT => 1,
C_PROBE776_MU_CNT => 1,
C_PROBE777_MU_CNT => 1,
C_PROBE778_MU_CNT => 1,
C_PROBE779_MU_CNT => 1,
C_PROBE780_MU_CNT => 1,
C_PROBE781_MU_CNT => 1,
C_PROBE782_MU_CNT => 1,
C_PROBE783_MU_CNT => 1,
C_PROBE784_MU_CNT => 1,
C_PROBE785_MU_CNT => 1,
C_PROBE786_MU_CNT => 1,
C_PROBE787_MU_CNT => 1,
C_PROBE788_MU_CNT => 1,
C_PROBE789_MU_CNT => 1,
C_PROBE790_MU_CNT => 1,
C_PROBE791_MU_CNT => 1,
C_PROBE792_MU_CNT => 1,
C_PROBE793_MU_CNT => 1,
C_PROBE794_MU_CNT => 1,
C_PROBE795_MU_CNT => 1,
C_PROBE796_MU_CNT => 1,
C_PROBE797_MU_CNT => 1,
C_PROBE798_MU_CNT => 1,
C_PROBE799_MU_CNT => 1,
C_PROBE800_MU_CNT => 1,
C_PROBE801_MU_CNT => 1,
C_PROBE802_MU_CNT => 1,
C_PROBE803_MU_CNT => 1,
C_PROBE804_MU_CNT => 1,
C_PROBE805_MU_CNT => 1,
C_PROBE806_MU_CNT => 1,
C_PROBE807_MU_CNT => 1,
C_PROBE808_MU_CNT => 1,
C_PROBE809_MU_CNT => 1,
C_PROBE810_MU_CNT => 1,
C_PROBE811_MU_CNT => 1,
C_PROBE812_MU_CNT => 1,
C_PROBE813_MU_CNT => 1,
C_PROBE814_MU_CNT => 1,
C_PROBE815_MU_CNT => 1,
C_PROBE816_MU_CNT => 1,
C_PROBE817_MU_CNT => 1,
C_PROBE818_MU_CNT => 1,
C_PROBE819_MU_CNT => 1,
C_PROBE820_MU_CNT => 1,
C_PROBE821_MU_CNT => 1,
C_PROBE822_MU_CNT => 1,
C_PROBE823_MU_CNT => 1,
C_PROBE824_MU_CNT => 1,
C_PROBE825_MU_CNT => 1,
C_PROBE826_MU_CNT => 1,
C_PROBE827_MU_CNT => 1,
C_PROBE828_MU_CNT => 1,
C_PROBE829_MU_CNT => 1,
C_PROBE830_MU_CNT => 1,
C_PROBE831_MU_CNT => 1,
C_PROBE832_MU_CNT => 1,
C_PROBE833_MU_CNT => 1,
C_PROBE834_MU_CNT => 1,
C_PROBE835_MU_CNT => 1,
C_PROBE836_MU_CNT => 1,
C_PROBE837_MU_CNT => 1,
C_PROBE838_MU_CNT => 1,
C_PROBE839_MU_CNT => 1,
C_PROBE840_MU_CNT => 1,
C_PROBE841_MU_CNT => 1,
C_PROBE842_MU_CNT => 1,
C_PROBE843_MU_CNT => 1,
C_PROBE844_MU_CNT => 1,
C_PROBE845_MU_CNT => 1,
C_PROBE846_MU_CNT => 1,
C_PROBE847_MU_CNT => 1,
C_PROBE848_MU_CNT => 1,
C_PROBE849_MU_CNT => 1,
C_PROBE850_MU_CNT => 1,
C_PROBE851_MU_CNT => 1,
C_PROBE852_MU_CNT => 1,
C_PROBE853_MU_CNT => 1,
C_PROBE854_MU_CNT => 1,
C_PROBE855_MU_CNT => 1,
C_PROBE856_MU_CNT => 1,
C_PROBE857_MU_CNT => 1,
C_PROBE858_MU_CNT => 1,
C_PROBE859_MU_CNT => 1,
C_PROBE860_MU_CNT => 1,
C_PROBE861_MU_CNT => 1,
C_PROBE862_MU_CNT => 1,
C_PROBE863_MU_CNT => 1,
C_PROBE864_MU_CNT => 1,
C_PROBE865_MU_CNT => 1,
C_PROBE866_MU_CNT => 1,
C_PROBE867_MU_CNT => 1,
C_PROBE868_MU_CNT => 1,
C_PROBE869_MU_CNT => 1,
C_PROBE870_MU_CNT => 1,
C_PROBE871_MU_CNT => 1,
C_PROBE872_MU_CNT => 1,
C_PROBE873_MU_CNT => 1,
C_PROBE874_MU_CNT => 1,
C_PROBE875_MU_CNT => 1,
C_PROBE876_MU_CNT => 1,
C_PROBE877_MU_CNT => 1,
C_PROBE878_MU_CNT => 1,
C_PROBE879_MU_CNT => 1,
C_PROBE880_MU_CNT => 1,
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C_PROBE507_TYPE => 1,
C_PROBE508_TYPE => 1,
C_PROBE509_TYPE => 1,
C_PROBE510_TYPE => 1,
C_PROBE511_TYPE => 1,
C_PROBE512_TYPE => 1,
C_PROBE513_TYPE => 1,
C_PROBE514_TYPE => 1,
C_PROBE515_TYPE => 1,
C_PROBE516_TYPE => 1,
C_PROBE517_TYPE => 1,
C_PROBE518_TYPE => 1,
C_PROBE519_TYPE => 1,
C_PROBE520_TYPE => 1,
C_PROBE521_TYPE => 1,
C_PROBE522_TYPE => 1,
C_PROBE523_TYPE => 1,
C_PROBE524_TYPE => 1,
C_PROBE525_TYPE => 1,
C_PROBE526_TYPE => 1,
C_PROBE527_TYPE => 1,
C_PROBE528_TYPE => 1,
C_PROBE529_TYPE => 1,
C_PROBE530_TYPE => 1,
C_PROBE531_TYPE => 1,
C_PROBE532_TYPE => 1,
C_PROBE533_TYPE => 1,
C_PROBE534_TYPE => 1,
C_PROBE535_TYPE => 1,
C_PROBE536_TYPE => 1,
C_PROBE537_TYPE => 1,
C_PROBE538_TYPE => 1,
C_PROBE539_TYPE => 1,
C_PROBE540_TYPE => 1,
C_PROBE541_TYPE => 1,
C_PROBE542_TYPE => 1,
C_PROBE543_TYPE => 1,
C_PROBE544_TYPE => 1,
C_PROBE545_TYPE => 1,
C_PROBE546_TYPE => 1,
C_PROBE547_TYPE => 1,
C_PROBE548_TYPE => 1,
C_PROBE549_TYPE => 1,
C_PROBE550_TYPE => 1,
C_PROBE551_TYPE => 1,
C_PROBE552_TYPE => 1,
C_PROBE553_TYPE => 1,
C_PROBE554_TYPE => 1,
C_PROBE555_TYPE => 1,
C_PROBE556_TYPE => 1,
C_PROBE557_TYPE => 1,
C_PROBE558_TYPE => 1,
C_PROBE559_TYPE => 1,
C_PROBE560_TYPE => 1,
C_PROBE561_TYPE => 1,
C_PROBE562_TYPE => 1,
C_PROBE563_TYPE => 1,
C_PROBE564_TYPE => 1,
C_PROBE565_TYPE => 1,
C_PROBE566_TYPE => 1,
C_PROBE567_TYPE => 1,
C_PROBE568_TYPE => 1,
C_PROBE569_TYPE => 1,
C_PROBE570_TYPE => 1,
C_PROBE571_TYPE => 1,
C_PROBE572_TYPE => 1,
C_PROBE573_TYPE => 1,
C_PROBE574_TYPE => 1,
C_PROBE575_TYPE => 1,
C_PROBE576_TYPE => 1,
C_PROBE577_TYPE => 1,
C_PROBE578_TYPE => 1,
C_PROBE579_TYPE => 1,
C_PROBE580_TYPE => 1,
C_PROBE581_TYPE => 1,
C_PROBE582_TYPE => 1,
C_PROBE583_TYPE => 1,
C_PROBE584_TYPE => 1,
C_PROBE585_TYPE => 1,
C_PROBE586_TYPE => 1,
C_PROBE587_TYPE => 1,
C_PROBE588_TYPE => 1,
C_PROBE589_TYPE => 1,
C_PROBE590_TYPE => 1,
C_PROBE591_TYPE => 1,
C_PROBE592_TYPE => 1,
C_PROBE593_TYPE => 1,
C_PROBE594_TYPE => 1,
C_PROBE595_TYPE => 1,
C_PROBE596_TYPE => 1,
C_PROBE597_TYPE => 1,
C_PROBE598_TYPE => 1,
C_PROBE599_TYPE => 1,
C_PROBE600_TYPE => 1,
C_PROBE601_TYPE => 1,
C_PROBE602_TYPE => 1,
C_PROBE603_TYPE => 1,
C_PROBE604_TYPE => 1,
C_PROBE605_TYPE => 1,
C_PROBE606_TYPE => 1,
C_PROBE607_TYPE => 1,
C_PROBE608_TYPE => 1,
C_PROBE609_TYPE => 1,
C_PROBE610_TYPE => 1,
C_PROBE611_TYPE => 1,
C_PROBE612_TYPE => 1,
C_PROBE613_TYPE => 1,
C_PROBE614_TYPE => 1,
C_PROBE615_TYPE => 1,
C_PROBE616_TYPE => 1,
C_PROBE617_TYPE => 1,
C_PROBE618_TYPE => 1,
C_PROBE619_TYPE => 1,
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C_PROBE621_TYPE => 1,
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C_PROBE623_TYPE => 1,
C_PROBE624_TYPE => 1,
C_PROBE625_TYPE => 1,
C_PROBE626_TYPE => 1,
C_PROBE627_TYPE => 1,
C_PROBE628_TYPE => 1,
C_PROBE629_TYPE => 1,
C_PROBE630_TYPE => 1,
C_PROBE631_TYPE => 1,
C_PROBE632_TYPE => 1,
C_PROBE633_TYPE => 1,
C_PROBE634_TYPE => 1,
C_PROBE635_TYPE => 1,
C_PROBE636_TYPE => 1,
C_PROBE637_TYPE => 1,
C_PROBE638_TYPE => 1,
C_PROBE639_TYPE => 1,
C_PROBE640_TYPE => 1,
C_PROBE641_TYPE => 1,
C_PROBE642_TYPE => 1,
C_PROBE643_TYPE => 1,
C_PROBE644_TYPE => 1,
C_PROBE645_TYPE => 1,
C_PROBE646_TYPE => 1,
C_PROBE647_TYPE => 1,
C_PROBE648_TYPE => 1,
C_PROBE649_TYPE => 1,
C_PROBE650_TYPE => 1,
C_PROBE651_TYPE => 1,
C_PROBE652_TYPE => 1,
C_PROBE653_TYPE => 1,
C_PROBE654_TYPE => 1,
C_PROBE655_TYPE => 1,
C_PROBE656_TYPE => 1,
C_PROBE657_TYPE => 1,
C_PROBE658_TYPE => 1,
C_PROBE659_TYPE => 1,
C_PROBE660_TYPE => 1,
C_PROBE661_TYPE => 1,
C_PROBE662_TYPE => 1,
C_PROBE663_TYPE => 1,
C_PROBE664_TYPE => 1,
C_PROBE665_TYPE => 1,
C_PROBE666_TYPE => 1,
C_PROBE667_TYPE => 1,
C_PROBE668_TYPE => 1,
C_PROBE669_TYPE => 1,
C_PROBE670_TYPE => 1,
C_PROBE671_TYPE => 1,
C_PROBE672_TYPE => 1,
C_PROBE673_TYPE => 1,
C_PROBE674_TYPE => 1,
C_PROBE675_TYPE => 1,
C_PROBE676_TYPE => 1,
C_PROBE677_TYPE => 1,
C_PROBE678_TYPE => 1,
C_PROBE679_TYPE => 1,
C_PROBE680_TYPE => 1,
C_PROBE681_TYPE => 1,
C_PROBE682_TYPE => 1,
C_PROBE683_TYPE => 1,
C_PROBE684_TYPE => 1,
C_PROBE685_TYPE => 1,
C_PROBE686_TYPE => 1,
C_PROBE687_TYPE => 1,
C_PROBE688_TYPE => 1,
C_PROBE689_TYPE => 1,
C_PROBE690_TYPE => 1,
C_PROBE691_TYPE => 1,
C_PROBE692_TYPE => 1,
C_PROBE693_TYPE => 1,
C_PROBE694_TYPE => 1,
C_PROBE695_TYPE => 1,
C_PROBE696_TYPE => 1,
C_PROBE697_TYPE => 1,
C_PROBE698_TYPE => 1,
C_PROBE699_TYPE => 1,
C_PROBE700_TYPE => 1,
C_PROBE701_TYPE => 1,
C_PROBE702_TYPE => 1,
C_PROBE703_TYPE => 1,
C_PROBE704_TYPE => 1,
C_PROBE705_TYPE => 1,
C_PROBE706_TYPE => 1,
C_PROBE707_TYPE => 1,
C_PROBE708_TYPE => 1,
C_PROBE709_TYPE => 1,
C_PROBE710_TYPE => 1,
C_PROBE711_TYPE => 1,
C_PROBE712_TYPE => 1,
C_PROBE713_TYPE => 1,
C_PROBE714_TYPE => 1,
C_PROBE715_TYPE => 1,
C_PROBE716_TYPE => 1,
C_PROBE717_TYPE => 1,
C_PROBE718_TYPE => 1,
C_PROBE719_TYPE => 1,
C_PROBE720_TYPE => 1,
C_PROBE721_TYPE => 1,
C_PROBE722_TYPE => 1,
C_PROBE723_TYPE => 1,
C_PROBE724_TYPE => 1,
C_PROBE725_TYPE => 1,
C_PROBE726_TYPE => 1,
C_PROBE727_TYPE => 1,
C_PROBE728_TYPE => 1,
C_PROBE729_TYPE => 1,
C_PROBE730_TYPE => 1,
C_PROBE731_TYPE => 1,
C_PROBE732_TYPE => 1,
C_PROBE733_TYPE => 1,
C_PROBE734_TYPE => 1,
C_PROBE735_TYPE => 1,
C_PROBE736_TYPE => 1,
C_PROBE737_TYPE => 1,
C_PROBE738_TYPE => 1,
C_PROBE739_TYPE => 1,
C_PROBE740_TYPE => 1,
C_PROBE741_TYPE => 1,
C_PROBE742_TYPE => 1,
C_PROBE743_TYPE => 1,
C_PROBE744_TYPE => 1,
C_PROBE745_TYPE => 1,
C_PROBE746_TYPE => 1,
C_PROBE747_TYPE => 1,
C_PROBE748_TYPE => 1,
C_PROBE749_TYPE => 1,
C_PROBE750_TYPE => 1,
C_PROBE751_TYPE => 1,
C_PROBE752_TYPE => 1,
C_PROBE753_TYPE => 1,
C_PROBE754_TYPE => 1,
C_PROBE755_TYPE => 1,
C_PROBE756_TYPE => 1,
C_PROBE757_TYPE => 1,
C_PROBE758_TYPE => 1,
C_PROBE759_TYPE => 1,
C_PROBE760_TYPE => 1,
C_PROBE761_TYPE => 1,
C_PROBE762_TYPE => 1,
C_PROBE763_TYPE => 1,
C_PROBE764_TYPE => 1,
C_PROBE765_TYPE => 1,
C_PROBE766_TYPE => 1,
C_PROBE767_TYPE => 1,
C_PROBE768_TYPE => 1,
C_PROBE769_TYPE => 1,
C_PROBE770_TYPE => 1,
C_PROBE771_TYPE => 1,
C_PROBE772_TYPE => 1,
C_PROBE773_TYPE => 1,
C_PROBE774_TYPE => 1,
C_PROBE775_TYPE => 1,
C_PROBE776_TYPE => 1,
C_PROBE777_TYPE => 1,
C_PROBE778_TYPE => 1,
C_PROBE779_TYPE => 1,
C_PROBE780_TYPE => 1,
C_PROBE781_TYPE => 1,
C_PROBE782_TYPE => 1,
C_PROBE783_TYPE => 1,
C_PROBE784_TYPE => 1,
C_PROBE785_TYPE => 1,
C_PROBE786_TYPE => 1,
C_PROBE787_TYPE => 1,
C_PROBE788_TYPE => 1,
C_PROBE789_TYPE => 1,
C_PROBE790_TYPE => 1,
C_PROBE791_TYPE => 1,
C_PROBE792_TYPE => 1,
C_PROBE793_TYPE => 1,
C_PROBE794_TYPE => 1,
C_PROBE795_TYPE => 1,
C_PROBE796_TYPE => 1,
C_PROBE797_TYPE => 1,
C_PROBE798_TYPE => 1,
C_PROBE799_TYPE => 1,
C_PROBE800_TYPE => 1,
C_PROBE801_TYPE => 1,
C_PROBE802_TYPE => 1,
C_PROBE803_TYPE => 1,
C_PROBE804_TYPE => 1,
C_PROBE805_TYPE => 1,
C_PROBE806_TYPE => 1,
C_PROBE807_TYPE => 1,
C_PROBE808_TYPE => 1,
C_PROBE809_TYPE => 1,
C_PROBE810_TYPE => 1,
C_PROBE811_TYPE => 1,
C_PROBE812_TYPE => 1,
C_PROBE813_TYPE => 1,
C_PROBE814_TYPE => 1,
C_PROBE815_TYPE => 1,
C_PROBE816_TYPE => 1,
C_PROBE817_TYPE => 1,
C_PROBE818_TYPE => 1,
C_PROBE819_TYPE => 1,
C_PROBE820_TYPE => 1,
C_PROBE821_TYPE => 1,
C_PROBE822_TYPE => 1,
C_PROBE823_TYPE => 1,
C_PROBE824_TYPE => 1,
C_PROBE825_TYPE => 1,
C_PROBE826_TYPE => 1,
C_PROBE827_TYPE => 1,
C_PROBE828_TYPE => 1,
C_PROBE829_TYPE => 1,
C_PROBE830_TYPE => 1,
C_PROBE831_TYPE => 1,
C_PROBE832_TYPE => 1,
C_PROBE833_TYPE => 1,
C_PROBE834_TYPE => 1,
C_PROBE835_TYPE => 1,
C_PROBE836_TYPE => 1,
C_PROBE837_TYPE => 1,
C_PROBE838_TYPE => 1,
C_PROBE839_TYPE => 1,
C_PROBE840_TYPE => 1,
C_PROBE841_TYPE => 1,
C_PROBE842_TYPE => 1,
C_PROBE843_TYPE => 1,
C_PROBE844_TYPE => 1,
C_PROBE845_TYPE => 1,
C_PROBE846_TYPE => 1,
C_PROBE847_TYPE => 1,
C_PROBE848_TYPE => 1,
C_PROBE849_TYPE => 1,
C_PROBE850_TYPE => 1,
C_PROBE851_TYPE => 1,
C_PROBE852_TYPE => 1,
C_PROBE853_TYPE => 1,
C_PROBE854_TYPE => 1,
C_PROBE855_TYPE => 1,
C_PROBE856_TYPE => 1,
C_PROBE857_TYPE => 1,
C_PROBE858_TYPE => 1,
C_PROBE859_TYPE => 1,
C_PROBE860_TYPE => 1,
C_PROBE861_TYPE => 1,
C_PROBE862_TYPE => 1,
C_PROBE863_TYPE => 1,
C_PROBE864_TYPE => 1,
C_PROBE865_TYPE => 1,
C_PROBE866_TYPE => 1,
C_PROBE867_TYPE => 1,
C_PROBE868_TYPE => 1,
C_PROBE869_TYPE => 1,
C_PROBE870_TYPE => 1,
C_PROBE871_TYPE => 1,
C_PROBE872_TYPE => 1,
C_PROBE873_TYPE => 1,
C_PROBE874_TYPE => 1,
C_PROBE875_TYPE => 1,
C_PROBE876_TYPE => 1,
C_PROBE877_TYPE => 1,
C_PROBE878_TYPE => 1,
C_PROBE879_TYPE => 1,
C_PROBE880_TYPE => 1,
C_PROBE881_TYPE => 1,
C_PROBE882_TYPE => 1,
C_PROBE883_TYPE => 1,
C_PROBE884_TYPE => 1,
C_PROBE885_TYPE => 1,
C_PROBE886_TYPE => 1,
C_PROBE887_TYPE => 1,
C_PROBE888_TYPE => 1,
C_PROBE889_TYPE => 1,
C_PROBE890_TYPE => 1,
C_PROBE891_TYPE => 1,
C_PROBE892_TYPE => 1,
C_PROBE893_TYPE => 1,
C_PROBE894_TYPE => 1,
C_PROBE895_TYPE => 1,
C_PROBE896_TYPE => 1,
C_PROBE897_TYPE => 1,
C_PROBE898_TYPE => 1,
C_PROBE899_TYPE => 1,
C_PROBE900_TYPE => 1,
C_PROBE901_TYPE => 1,
C_PROBE902_TYPE => 1,
C_PROBE903_TYPE => 1,
C_PROBE904_TYPE => 1,
C_PROBE905_TYPE => 1,
C_PROBE906_TYPE => 1,
C_PROBE907_TYPE => 1,
C_PROBE908_TYPE => 1,
C_PROBE909_TYPE => 1,
C_PROBE910_TYPE => 1,
C_PROBE911_TYPE => 1,
C_PROBE912_TYPE => 1,
C_PROBE913_TYPE => 1,
C_PROBE914_TYPE => 1,
C_PROBE915_TYPE => 1,
C_PROBE916_TYPE => 1,
C_PROBE917_TYPE => 1,
C_PROBE918_TYPE => 1,
C_PROBE919_TYPE => 1,
C_PROBE920_TYPE => 1,
C_PROBE921_TYPE => 1,
C_PROBE922_TYPE => 1,
C_PROBE923_TYPE => 1,
C_PROBE924_TYPE => 1,
C_PROBE925_TYPE => 1,
C_PROBE926_TYPE => 1,
C_PROBE927_TYPE => 1,
C_PROBE928_TYPE => 1,
C_PROBE929_TYPE => 1,
C_PROBE930_TYPE => 1,
C_PROBE931_TYPE => 1,
C_PROBE932_TYPE => 1,
C_PROBE933_TYPE => 1,
C_PROBE934_TYPE => 1,
C_PROBE935_TYPE => 1,
C_PROBE936_TYPE => 1,
C_PROBE937_TYPE => 1,
C_PROBE938_TYPE => 1,
C_PROBE939_TYPE => 1,
C_PROBE940_TYPE => 1,
C_PROBE941_TYPE => 1,
C_PROBE942_TYPE => 1,
C_PROBE943_TYPE => 1,
C_PROBE944_TYPE => 1,
C_PROBE945_TYPE => 1,
C_PROBE946_TYPE => 1,
C_PROBE947_TYPE => 1,
C_PROBE948_TYPE => 1,
C_PROBE949_TYPE => 1,
C_PROBE950_TYPE => 1,
C_PROBE951_TYPE => 1,
C_PROBE952_TYPE => 1,
C_PROBE953_TYPE => 1,
C_PROBE954_TYPE => 1,
C_PROBE955_TYPE => 1,
C_PROBE956_TYPE => 1,
C_PROBE957_TYPE => 1,
C_PROBE958_TYPE => 1,
C_PROBE959_TYPE => 1,
C_PROBE960_TYPE => 1,
C_PROBE961_TYPE => 1,
C_PROBE962_TYPE => 1,
C_PROBE963_TYPE => 1,
C_PROBE964_TYPE => 1,
C_PROBE965_TYPE => 1,
C_PROBE966_TYPE => 1,
C_PROBE967_TYPE => 1,
C_PROBE968_TYPE => 1,
C_PROBE969_TYPE => 1,
C_PROBE970_TYPE => 1,
C_PROBE971_TYPE => 1,
C_PROBE972_TYPE => 1,
C_PROBE973_TYPE => 1,
C_PROBE974_TYPE => 1,
C_PROBE975_TYPE => 1,
C_PROBE976_TYPE => 1,
C_PROBE977_TYPE => 1,
C_PROBE978_TYPE => 1,
C_PROBE979_TYPE => 1,
C_PROBE980_TYPE => 1,
C_PROBE981_TYPE => 1,
C_PROBE982_TYPE => 1,
C_PROBE983_TYPE => 1,
C_PROBE984_TYPE => 1,
C_PROBE985_TYPE => 1,
C_PROBE986_TYPE => 1,
C_PROBE987_TYPE => 1,
C_PROBE988_TYPE => 1,
C_PROBE989_TYPE => 1,
C_PROBE990_TYPE => 1,
C_PROBE991_TYPE => 1,
C_PROBE992_TYPE => 1,
C_PROBE993_TYPE => 1,
C_PROBE994_TYPE => 1,
C_PROBE995_TYPE => 1,
C_PROBE996_TYPE => 1,
C_PROBE997_TYPE => 1,
C_PROBE998_TYPE => 1,
C_PROBE999_TYPE => 1,
C_PROBE1000_TYPE => 1,
C_PROBE1001_TYPE => 1,
C_PROBE1002_TYPE => 1,
C_PROBE1003_TYPE => 1,
C_PROBE1004_TYPE => 1,
C_PROBE1005_TYPE => 1,
C_PROBE1006_TYPE => 1,
C_PROBE1007_TYPE => 1,
C_PROBE1008_TYPE => 1,
C_PROBE1009_TYPE => 1,
C_PROBE1010_TYPE => 1,
C_PROBE1011_TYPE => 1,
C_PROBE1012_TYPE => 1,
C_PROBE1013_TYPE => 1,
C_PROBE1014_TYPE => 1,
C_PROBE1015_TYPE => 1,
C_PROBE1016_TYPE => 1,
C_PROBE1017_TYPE => 1,
C_PROBE1018_TYPE => 1,
C_PROBE1019_TYPE => 1,
C_PROBE1020_TYPE => 1,
C_PROBE1021_TYPE => 1,
C_PROBE1022_TYPE => 1,
C_PROBE1023_TYPE => 1
)
PORT MAP (
clk => clk,
sl_iport0 => sl_iport0,
sl_oport0 => sl_oport0,
trig_out => open,
trig_out_ack => '0',
trig_in => '0',
trig_in_ack => open,
probe0 => probe0,
probe1 => probe1,
probe2 => probe2,
probe3 => probe3,
probe4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe32 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe33 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe34 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe35 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe36 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe37 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe38 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe39 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe40 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe41 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe42 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe43 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe44 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe45 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe46 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe47 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe48 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe49 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe50 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe51 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe52 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe53 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe54 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe55 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe56 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe57 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe58 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe59 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe60 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe61 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe62 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe63 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe64 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe65 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe66 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe67 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe68 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe69 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe70 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe71 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe72 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe73 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe74 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe75 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe76 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe77 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe78 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe79 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe80 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe81 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe82 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe83 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe84 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe85 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe86 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe87 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe88 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe89 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe90 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe91 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe92 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe93 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe94 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe95 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe96 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe97 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe98 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe99 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe100 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe101 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe102 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe103 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe104 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe105 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe106 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe107 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe108 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe109 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe110 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe111 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe112 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe113 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe114 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe115 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe116 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe117 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe118 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe119 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe120 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe121 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe122 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe123 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe124 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe125 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe126 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe127 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe128 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe129 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe130 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe131 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe132 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe133 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe134 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe135 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe136 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe137 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe138 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe139 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe140 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe141 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe142 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe143 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe144 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe145 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe146 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe147 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe148 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe149 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe150 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe151 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe152 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe153 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe154 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe155 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe156 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe157 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe158 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe159 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe160 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe161 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe162 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe163 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe164 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe165 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe166 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe167 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe168 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe169 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe170 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe171 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe172 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe173 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe174 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe175 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe176 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe177 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe178 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe179 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe180 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe181 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe182 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe183 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe184 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe185 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe186 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe187 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe188 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe189 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe190 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe191 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe192 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe193 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe194 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe195 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe196 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe197 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe198 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe199 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe200 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe201 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe202 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe203 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe204 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe205 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe206 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe207 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe208 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe209 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe210 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe211 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe212 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe213 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe214 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe215 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe216 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe217 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe218 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe219 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe220 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe221 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe222 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe223 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe224 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe225 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe226 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe227 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe228 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe229 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe230 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe231 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe232 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe233 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe234 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe235 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe236 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe237 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe238 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe239 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe240 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe241 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe242 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe243 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe244 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe245 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe246 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe247 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe248 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe249 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe250 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe251 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe252 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe253 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe254 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe255 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe256 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe257 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe258 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe259 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe260 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe261 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe262 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe263 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe264 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe265 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe266 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe267 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe268 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe269 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe270 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe271 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe272 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe273 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe274 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe275 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe276 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe277 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe278 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe279 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe280 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe281 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe282 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe283 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe284 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe285 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe286 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe287 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe288 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe289 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe290 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe291 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe292 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe293 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe294 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe295 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe296 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe297 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe298 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe299 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe300 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe301 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe302 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe303 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe304 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe305 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe306 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe307 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe308 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe309 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe310 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe311 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe312 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe313 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe314 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe315 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe316 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe317 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe318 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe319 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe320 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe321 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe322 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe323 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe324 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe325 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe326 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe327 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe328 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe329 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe330 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe331 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe332 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe333 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe334 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe335 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe336 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe337 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe338 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe339 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe340 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe341 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe342 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe343 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe344 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe345 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe346 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe347 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe348 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe349 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe350 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe351 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe352 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe353 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe354 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe355 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe356 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe357 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe358 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe359 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe360 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe361 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe362 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe363 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe364 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe365 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe366 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe367 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe368 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe369 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe370 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe371 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe372 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe373 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe374 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe375 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe376 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe377 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe378 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe379 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe380 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe381 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe382 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe383 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe384 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe385 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe386 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe387 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe388 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe389 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe390 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe391 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe392 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe393 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe394 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe395 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe396 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe397 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe398 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe399 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe400 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe401 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe402 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe403 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe404 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe405 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe406 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe407 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe408 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe409 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe410 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe411 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe412 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe413 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe414 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe415 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe416 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe417 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe418 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe419 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe420 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe421 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe422 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe423 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe424 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe425 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe426 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe427 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe428 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe429 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe430 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe431 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe432 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe433 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe434 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe435 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe436 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe437 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe438 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe439 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe440 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe441 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe442 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe443 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe444 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe445 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe446 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe447 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe448 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe449 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe450 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe451 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe452 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe453 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe454 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe455 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe456 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe457 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe458 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe459 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe460 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe461 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe462 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe463 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe464 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe465 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe466 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe467 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe468 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe469 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe470 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe471 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe472 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe473 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe474 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe475 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe476 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe477 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe478 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe479 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe480 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe481 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe482 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe483 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe484 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe485 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe486 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe487 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe488 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe489 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe490 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe491 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe492 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe493 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe494 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe495 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe496 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe497 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe498 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe499 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe500 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe501 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe502 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe503 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe504 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe505 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe506 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe507 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe508 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe509 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe510 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe511 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe512 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe513 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe514 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe515 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe516 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe517 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe518 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe519 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe520 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe521 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe522 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe523 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe524 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe525 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe526 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe527 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe528 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe529 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe530 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe531 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe532 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe533 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe534 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe535 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe536 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe537 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe538 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe539 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe540 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe541 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe542 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe543 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe544 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe545 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe546 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe547 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe548 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe549 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe550 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe551 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe552 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe553 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe554 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe555 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe556 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe557 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe558 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe559 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe560 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe561 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe562 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe563 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe564 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe565 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe566 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe567 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe568 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe569 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe570 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe571 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe572 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe573 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe574 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe575 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe576 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe577 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe578 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe579 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe580 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe581 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe582 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe583 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe584 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe585 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe586 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe587 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe588 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe589 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe590 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe591 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe592 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe593 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe594 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe595 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe596 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe597 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe598 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe599 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe600 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe601 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe602 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe603 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe604 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe605 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe606 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe607 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe608 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe609 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe610 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe611 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe612 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe613 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe614 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe615 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe616 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe617 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe618 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe619 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe620 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe621 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe622 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe623 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe624 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe625 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe626 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe627 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe628 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe629 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe630 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe631 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe632 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe633 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe634 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe635 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe636 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe637 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe638 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe639 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe640 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe641 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe642 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe643 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe644 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe645 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe646 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe647 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe648 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe649 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe650 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe651 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe652 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe653 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe654 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe655 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe656 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe657 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe658 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe659 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe660 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe661 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe662 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe663 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe664 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe665 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe666 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe667 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe668 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe669 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe670 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe671 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe672 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe673 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe674 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe675 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe676 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe677 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe678 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe679 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe680 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe681 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe682 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe683 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe684 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe685 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe686 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe687 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe688 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe689 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe690 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe691 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe692 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe693 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe694 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe695 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe696 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe697 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe698 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe699 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe700 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe701 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe702 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe703 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe704 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe705 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe706 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe707 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe708 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe709 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe710 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe711 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe712 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe713 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe714 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe715 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe716 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe717 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe718 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe719 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe720 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe721 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe722 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe723 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe724 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe725 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe726 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe727 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe728 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe729 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe730 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe731 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe732 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe733 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe734 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe735 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe736 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe737 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe738 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe739 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe740 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe741 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe742 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe743 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe744 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe745 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe746 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe747 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe748 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe749 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe750 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe751 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe752 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe753 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe754 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe755 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe756 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe757 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe758 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe759 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe760 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe761 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe762 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe763 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe764 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe765 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe766 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe767 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe768 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe769 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe770 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe771 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe772 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe773 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe774 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe775 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe776 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe777 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe778 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe779 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe780 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe781 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe782 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe783 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe784 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe785 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe786 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe787 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe788 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe789 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe790 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe791 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe792 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe793 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe794 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe795 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe796 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe797 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe798 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe799 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe800 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe801 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe802 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe803 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe804 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe805 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe806 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe807 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe808 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe809 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe810 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe811 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe812 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe813 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe814 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe815 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe816 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe817 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe818 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe819 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe820 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe821 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe822 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe823 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe824 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe825 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe826 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe827 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe828 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe829 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe830 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe831 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe832 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe833 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe834 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe835 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe836 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe837 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe838 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe839 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe840 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe841 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe842 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe843 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe844 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe845 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe846 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe847 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe848 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe849 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe850 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe851 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe852 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe853 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe854 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe855 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe856 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe857 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe858 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe859 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe860 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe861 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe862 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe863 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe864 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe865 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe866 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe867 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe868 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe869 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe870 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe871 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe872 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe873 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe874 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe875 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe876 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe877 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe878 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe879 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe880 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe881 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe882 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe883 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe884 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe885 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe886 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe887 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe888 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe889 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe890 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe891 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe892 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe893 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe894 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe895 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe896 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe897 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe898 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe899 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe900 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe901 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe902 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe903 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe904 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe905 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe906 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe907 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe908 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe909 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe910 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe911 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe912 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe913 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe914 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe915 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe916 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe917 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe918 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe919 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe920 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe921 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe922 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe923 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe924 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe925 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe926 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe927 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe928 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe929 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe930 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe931 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe932 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe933 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe934 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe935 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe936 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe937 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe938 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe939 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe940 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe941 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe942 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe943 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe944 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe945 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe946 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe947 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe948 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe949 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe950 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe951 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe952 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe953 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe954 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe955 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe956 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe957 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe958 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe959 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe960 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe961 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe962 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe963 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe964 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe965 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe966 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe967 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe968 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe969 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe970 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe971 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe972 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe973 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe974 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe975 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe976 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe977 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe978 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe979 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe980 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe981 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe982 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe983 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe984 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe985 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe986 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe987 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe988 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe989 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe990 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe991 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe992 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe993 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe994 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe995 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe996 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe997 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe998 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe999 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1000 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1001 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1002 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1003 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1004 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1005 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1006 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1007 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1008 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1009 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1010 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1011 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1012 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1013 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1014 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1015 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1016 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1017 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1018 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1019 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1020 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1021 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1022 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1023 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1))
);
END DemoInterconnect_ila_0_0_arch;
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
ROM_form.vhd
Production template for a 0.125K program (128 instructions) for KCPSM6 in a Spartan-6,
Virtex-6 or 7-Series device using 9 Slices.
Ken Chapman (Xilinx Ltd)
14th March 2013 - First Release
This is a VHDL template file for the KCPSM6 assembler.
This VHDL file is not valid as input directly into a synthesis or a simulation tool.
The assembler will read this template and insert the information required to complete
the definition of program ROM and write it out to a new '.vhd' file that is ready for
synthesis and simulation.
This template can be modified to define alternative memory definitions. However, you are
responsible for ensuring the template is correct as the assembler does not perform any
checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
The next line is used to determine where the template actually starts.
{begin template}
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- Production template for a 0.125K program (128 instructions) for KCPSM6 in a Spartan-6,
-- Virtex-6 or 7-Series device using 9 Slices.
--
-- Note: The full 12-bit KCPSM6 address is connected but only the lower 7-bits will be
-- employed. Likewise the 'bram_enable' should still be connected to 'enable'.
-- This minimises the changes required to the hardware description of a design
-- when moving between different memory types and selecting different sizes.
--
-- program_rom: your_program
-- port map( address => address,
-- instruction => instruction,
-- enable => bram_enable,
-- clk => clk);
--
--
-- Program defined by '{psmname}.psm'.
--
-- Generated by KCPSM6 Assembler: {timestamp}.
--
-- Assembler used ROM_form template: ROM_form_128_14March13.vhd
--
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
signal rom_value : std_logic_vector(17 downto 0);
--
begin
--
instruction_bit: for i in 0 to 17 generate
begin
--
kcpsm6_rom_flop: FDRE
port map ( D => rom_value(i),
Q => instruction(i),
CE => enable,
R => address(7+(i/4)),
C => clk);
--
end generate instruction_bit;
--
--
kcpsm6_rom0: ROM128X1
generic map( INIT => X"{INIT128_0}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(0));
--
kcpsm6_rom1: ROM128X1
generic map( INIT => X"{INIT128_1}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(1));
--
kcpsm6_rom2: ROM128X1
generic map( INIT => X"{INIT128_2}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(2));
--
kcpsm6_rom3: ROM128X1
generic map( INIT => X"{INIT128_3}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(3));
--
kcpsm6_rom4: ROM128X1
generic map( INIT => X"{INIT128_4}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(4));
--
kcpsm6_rom5: ROM128X1
generic map( INIT => X"{INIT128_5}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(5));
--
kcpsm6_rom6: ROM128X1
generic map( INIT => X"{INIT128_6}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(6));
--
kcpsm6_rom7: ROM128X1
generic map( INIT => X"{INIT128_7}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(7));
--
kcpsm6_rom8: ROM128X1
generic map( INIT => X"{INIT128_8}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(8));
--
kcpsm6_rom9: ROM128X1
generic map( INIT => X"{INIT128_9}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(9));
--
kcpsm6_rom10: ROM128X1
generic map( INIT => X"{INIT128_10}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(10));
--
kcpsm6_rom11: ROM128X1
generic map( INIT => X"{INIT128_11}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(11));
--
kcpsm6_rom12: ROM128X1
generic map( INIT => X"{INIT128_12}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(12));
--
kcpsm6_rom13: ROM128X1
generic map( INIT => X"{INIT128_13}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(13));
--
kcpsm6_rom14: ROM128X1
generic map( INIT => X"{INIT128_14}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(14));
--
kcpsm6_rom15: ROM128X1
generic map( INIT => X"{INIT128_15}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(15));
--
kcpsm6_rom16: ROM128X1
generic map( INIT => X"{INIT128_16}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(16));
--
kcpsm6_rom17: ROM128X1
generic map( INIT => X"{INIT128_17}")
port map( A0 => address(0),
A1 => address(1),
A2 => address(2),
A3 => address(3),
A4 => address(4),
A5 => address(5),
A6 => address(6),
O => rom_value(17));
--
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
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