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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [3:0] l_stop = crc[3:0];
wire [3:0] l_break = crc[7:4];
wire [3:0] l_continue = crc[11:8];
/*AUTOWIRE*/
wire [15:0] out0 = Test0(l_stop, l_break, l_continue);
wire [15:0] out1 = Test1(l_stop, l_break, l_continue);
wire [15:0] out2 = Test2(l_stop, l_break, l_continue);
wire [15:0] out3 = Test3(l_stop, l_break, l_continue);
// Aggregate outputs into a single result vector
wire [63:0] result = {out3,out2,out1,out0};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
if (out0!==out1) $stop;
if (out0!==out2) $stop;
if (out0!==out3) $stop;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h293e9f9798e97da0
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
function [15:0] Test0;
input [3:0] loop_stop;
input [3:0] loop_break;
input [3:0] loop_continue;
integer i;
reg broken;
Test0 = 0;
broken = 0;
begin
for (i=1; i<20; i=i+1) begin
if (!broken) begin
Test0 = Test0 + 1;
if (i[3:0] != loop_continue) begin // continue
if (i[3:0] == loop_break) begin
broken = 1'b1;
end
if (!broken) begin
Test0 = Test0 + i[15:0];
end
end
end
end
end
endfunction
function [15:0] Test1;
input [3:0] loop_stop;
input [3:0] loop_break;
input [3:0] loop_continue;
integer i;
Test1 = 0;
begin : outer_block
for (i=1; i<20; i=i+1) begin : inner_block
Test1 = Test1 + 1;
// continue, IE jump to end-of-inner_block. Must be inside inner_block.
if (i[3:0] == loop_continue) disable inner_block;
// break, IE jump to end-of-outer_block. Must be inside outer_block.
if (i[3:0] == loop_break) disable outer_block;
Test1 = Test1 + i[15:0];
end : inner_block
end : outer_block
endfunction
function [15:0] Test2;
input [3:0] loop_stop;
input [3:0] loop_break;
input [3:0] loop_continue;
integer i;
Test2 = 0;
begin
for (i=1; i<20; i=i+1) begin
Test2 = Test2 + 1;
if (i[3:0] == loop_continue) continue;
if (i[3:0] == loop_break) break;
Test2 = Test2 + i[15:0];
end
end
endfunction
function [15:0] Test3;
input [3:0] loop_stop;
input [3:0] loop_break;
input [3:0] loop_continue;
integer i;
Test3 = 0;
begin
for (i=1; i<20; i=i+1) begin
Test3 = Test3 + 1;
if (i[3:0] == loop_continue) continue;
// return, IE jump to end-of-function optionally setting return value
if (i[3:0] == loop_break) return Test3;
Test3 = Test3 + i[15:0];
end
end
endfunction
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// verilator lint_off WIDTH
// verilator lint_off VARHIDDEN
module t (
clk
);
input clk;
integer cyc=0;
reg [63:0] crc; initial crc = 64'h1;
chk chk (.clk (clk),
.rst_l (1'b1),
.expr (|crc)
);
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module chk (input clk, input rst_l, input expr);
integer errors; initial errors = 0;
task printerr;
input [8*64:1] msg;
begin
errors = errors + 1;
$write("%%Error: %0s\n", msg);
$stop;
end
endtask
always @(posedge clk) begin
if (rst_l) begin
if (expr == 1'b0) begin
printerr("expr not asserted");
end
end
end
wire noxs = ((expr ^ expr) == 1'b0);
reg hasx;
always @ (noxs) begin
if (noxs) begin
hasx = 1'b0;
end
else begin
hasx = 1'b1;
end
end
always @(posedge clk) begin
if (rst_l) begin
if (hasx) begin
printerr("expr has unknowns");
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// verilator lint_off WIDTH
// verilator lint_off VARHIDDEN
module t (
clk
);
input clk;
integer cyc=0;
reg [63:0] crc; initial crc = 64'h1;
chk chk (.clk (clk),
.rst_l (1'b1),
.expr (|crc)
);
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module chk (input clk, input rst_l, input expr);
integer errors; initial errors = 0;
task printerr;
input [8*64:1] msg;
begin
errors = errors + 1;
$write("%%Error: %0s\n", msg);
$stop;
end
endtask
always @(posedge clk) begin
if (rst_l) begin
if (expr == 1'b0) begin
printerr("expr not asserted");
end
end
end
wire noxs = ((expr ^ expr) == 1'b0);
reg hasx;
always @ (noxs) begin
if (noxs) begin
hasx = 1'b0;
end
else begin
hasx = 1'b1;
end
end
always @(posedge clk) begin
if (rst_l) begin
if (hasx) begin
printerr("expr has unknowns");
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// verilator lint_off WIDTH
// verilator lint_off VARHIDDEN
module t (
clk
);
input clk;
integer cyc=0;
reg [63:0] crc; initial crc = 64'h1;
chk chk (.clk (clk),
.rst_l (1'b1),
.expr (|crc)
);
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module chk (input clk, input rst_l, input expr);
integer errors; initial errors = 0;
task printerr;
input [8*64:1] msg;
begin
errors = errors + 1;
$write("%%Error: %0s\n", msg);
$stop;
end
endtask
always @(posedge clk) begin
if (rst_l) begin
if (expr == 1'b0) begin
printerr("expr not asserted");
end
end
end
wire noxs = ((expr ^ expr) == 1'b0);
reg hasx;
always @ (noxs) begin
if (noxs) begin
hasx = 1'b0;
end
else begin
hasx = 1'b1;
end
end
always @(posedge clk) begin
if (rst_l) begin
if (hasx) begin
printerr("expr has unknowns");
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// simplistic example, should choose 1st conditional generate and assign straight through
// the tool also compiles the special case and determines an error (replication value is 0)
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
`timescale 1ns / 1ps
module t(data_i, data_o, single);
parameter op_bits = 32;
input [op_bits -1:0] data_i;
output [31:0] data_o;
input single;
//simplistic example, should choose 1st conditional generate and assign straight through
//the tool also compiles the special case and determines an error (replication value is 0
generate
if (op_bits == 32) begin : general_case
assign data_o = data_i;
// Test implicit signals
/* verilator lint_off IMPLICIT */
assign imp = single;
/* verilator lint_on IMPLICIT */
end
else begin : special_case
assign data_o = {{(32 -op_bits){1'b0}},data_i};
/* verilator lint_off IMPLICIT */
assign imp = single;
/* verilator lint_on IMPLICIT */
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [71:0] muxed; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.muxed (muxed[71:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {muxed[63:0]};
wire [5:0] width_check = cyc[5:0] + 1;
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h20050a66e7b253d1
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
muxed,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [71:0] muxed;
wire [71:0] a = {in[7:0],~in[31:0],in[31:0]};
wire [71:0] b = {~in[7:0],in[31:0],~in[31:0]};
/*AUTOWIRE*/
Muxer muxer (
.sa (0),
.sb (in[0]),
/*AUTOINST*/
// Outputs
.muxed (muxed[71:0]),
// Inputs
.a (a[71:0]),
.b (b[71:0]));
endmodule
module Muxer (/*AUTOARG*/
// Outputs
muxed,
// Inputs
sa, sb, a, b
);
input sa;
input sb;
output wire [71:0] muxed;
input [71:0] a;
input [71:0] b;
// Constification wasn't sizing with inlining and gave
// unsized error on below
// v
assign muxed = (({72{sa}} & a)
| ({72{sb}} & b));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [71:0] muxed; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.muxed (muxed[71:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {muxed[63:0]};
wire [5:0] width_check = cyc[5:0] + 1;
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h20050a66e7b253d1
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
muxed,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [71:0] muxed;
wire [71:0] a = {in[7:0],~in[31:0],in[31:0]};
wire [71:0] b = {~in[7:0],in[31:0],~in[31:0]};
/*AUTOWIRE*/
Muxer muxer (
.sa (0),
.sb (in[0]),
/*AUTOINST*/
// Outputs
.muxed (muxed[71:0]),
// Inputs
.a (a[71:0]),
.b (b[71:0]));
endmodule
module Muxer (/*AUTOARG*/
// Outputs
muxed,
// Inputs
sa, sb, a, b
);
input sa;
input sb;
output wire [71:0] muxed;
input [71:0] a;
input [71:0] b;
// Constification wasn't sizing with inlining and gave
// unsized error on below
// v
assign muxed = (({72{sa}} & a)
| ({72{sb}} & b));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [1:0] clkvec = crc[1:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] count; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.count (count[1:0]),
// Inputs
.clkvec (clkvec[1:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {62'h0, count};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'hfe8bac0bb1a0e53b
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
`ifdef T_TEST1
module Test
(
input wire [1:0] clkvec,
// verilator lint_off MULTIDRIVEN
output reg [1:0] count
// verilator lint_on MULTIDRIVEN
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
initial count[igen] = 1'b0;
always @ (posedge clkvec[igen])
count[igen] <= count[igen] + 1;
end
endgenerate
always @ (count) begin
$write("hi\n");
end
endmodule
`endif
`ifdef T_TEST2
module Test
(
input wire [1:0] clkvec,
// verilator lint_off MULTIDRIVEN
output reg [1:0] count
// verilator lint_on MULTIDRIVEN
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
wire clk_tmp = clkvec[igen];
// Unsupported: Count is multidriven, though if we did better analysis it wouldn't
// need to be.
initial count[igen] = 1'b0;
always @ (posedge clk_tmp)
count[igen] <= count[igen] + 1;
end
endgenerate
endmodule
`endif
`ifdef T_TEST3
module Test
(
input wire [1:0] clkvec,
output wire [1:0] count
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
wire clk_tmp = clkvec[igen];
reg tmp_count = 1'b0;
always @ (posedge clk_tmp) begin
tmp_count <= tmp_count + 1;
end
assign count[igen] = tmp_count;
end
endgenerate
endmodule
`endif
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [7:0] sel = crc[7:0];
wire [255+3:0] in = {crc[2:0],crc,crc,crc,crc};
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] out; // From test of Test.v
// End of automatics
/* Test AUTO_TEMPLATE (
.i\([0-9]+\) (in[\1 +:4]),
); */
Test test (/*AUTOINST*/
// Outputs
.out (out[3:0]),
// Inputs
.sel (sel[7:0]),
.i0 (in[0 +:4]), // Templated
.i1 (in[1 +:4]), // Templated
.i2 (in[2 +:4]), // Templated
.i3 (in[3 +:4]), // Templated
.i4 (in[4 +:4]), // Templated
.i5 (in[5 +:4]), // Templated
.i6 (in[6 +:4]), // Templated
.i7 (in[7 +:4]), // Templated
.i8 (in[8 +:4]), // Templated
.i9 (in[9 +:4]), // Templated
.i10 (in[10 +:4]), // Templated
.i11 (in[11 +:4]), // Templated
.i12 (in[12 +:4]), // Templated
.i13 (in[13 +:4]), // Templated
.i14 (in[14 +:4]), // Templated
.i15 (in[15 +:4]), // Templated
.i16 (in[16 +:4]), // Templated
.i17 (in[17 +:4]), // Templated
.i18 (in[18 +:4]), // Templated
.i19 (in[19 +:4]), // Templated
.i20 (in[20 +:4]), // Templated
.i21 (in[21 +:4]), // Templated
.i22 (in[22 +:4]), // Templated
.i23 (in[23 +:4]), // Templated
.i24 (in[24 +:4]), // Templated
.i25 (in[25 +:4]), // Templated
.i26 (in[26 +:4]), // Templated
.i27 (in[27 +:4]), // Templated
.i28 (in[28 +:4]), // Templated
.i29 (in[29 +:4]), // Templated
.i30 (in[30 +:4]), // Templated
.i31 (in[31 +:4]), // Templated
.i32 (in[32 +:4]), // Templated
.i33 (in[33 +:4]), // Templated
.i34 (in[34 +:4]), // Templated
.i35 (in[35 +:4]), // Templated
.i36 (in[36 +:4]), // Templated
.i37 (in[37 +:4]), // Templated
.i38 (in[38 +:4]), // Templated
.i39 (in[39 +:4]), // Templated
.i40 (in[40 +:4]), // Templated
.i41 (in[41 +:4]), // Templated
.i42 (in[42 +:4]), // Templated
.i43 (in[43 +:4]), // Templated
.i44 (in[44 +:4]), // Templated
.i45 (in[45 +:4]), // Templated
.i46 (in[46 +:4]), // Templated
.i47 (in[47 +:4]), // Templated
.i48 (in[48 +:4]), // Templated
.i49 (in[49 +:4]), // Templated
.i50 (in[50 +:4]), // Templated
.i51 (in[51 +:4]), // Templated
.i52 (in[52 +:4]), // Templated
.i53 (in[53 +:4]), // Templated
.i54 (in[54 +:4]), // Templated
.i55 (in[55 +:4]), // Templated
.i56 (in[56 +:4]), // Templated
.i57 (in[57 +:4]), // Templated
.i58 (in[58 +:4]), // Templated
.i59 (in[59 +:4]), // Templated
.i60 (in[60 +:4]), // Templated
.i61 (in[61 +:4]), // Templated
.i62 (in[62 +:4]), // Templated
.i63 (in[63 +:4]), // Templated
.i64 (in[64 +:4]), // Templated
.i65 (in[65 +:4]), // Templated
.i66 (in[66 +:4]), // Templated
.i67 (in[67 +:4]), // Templated
.i68 (in[68 +:4]), // Templated
.i69 (in[69 +:4]), // Templated
.i70 (in[70 +:4]), // Templated
.i71 (in[71 +:4]), // Templated
.i72 (in[72 +:4]), // Templated
.i73 (in[73 +:4]), // Templated
.i74 (in[74 +:4]), // Templated
.i75 (in[75 +:4]), // Templated
.i76 (in[76 +:4]), // Templated
.i77 (in[77 +:4]), // Templated
.i78 (in[78 +:4]), // Templated
.i79 (in[79 +:4]), // Templated
.i80 (in[80 +:4]), // Templated
.i81 (in[81 +:4]), // Templated
.i82 (in[82 +:4]), // Templated
.i83 (in[83 +:4]), // Templated
.i84 (in[84 +:4]), // Templated
.i85 (in[85 +:4]), // Templated
.i86 (in[86 +:4]), // Templated
.i87 (in[87 +:4]), // Templated
.i88 (in[88 +:4]), // Templated
.i89 (in[89 +:4]), // Templated
.i90 (in[90 +:4]), // Templated
.i91 (in[91 +:4]), // Templated
.i92 (in[92 +:4]), // Templated
.i93 (in[93 +:4]), // Templated
.i94 (in[94 +:4]), // Templated
.i95 (in[95 +:4]), // Templated
.i96 (in[96 +:4]), // Templated
.i97 (in[97 +:4]), // Templated
.i98 (in[98 +:4]), // Templated
.i99 (in[99 +:4]), // Templated
.i100 (in[100 +:4]), // Templated
.i101 (in[101 +:4]), // Templated
.i102 (in[102 +:4]), // Templated
.i103 (in[103 +:4]), // Templated
.i104 (in[104 +:4]), // Templated
.i105 (in[105 +:4]), // Templated
.i106 (in[106 +:4]), // Templated
.i107 (in[107 +:4]), // Templated
.i108 (in[108 +:4]), // Templated
.i109 (in[109 +:4]), // Templated
.i110 (in[110 +:4]), // Templated
.i111 (in[111 +:4]), // Templated
.i112 (in[112 +:4]), // Templated
.i113 (in[113 +:4]), // Templated
.i114 (in[114 +:4]), // Templated
.i115 (in[115 +:4]), // Templated
.i116 (in[116 +:4]), // Templated
.i117 (in[117 +:4]), // Templated
.i118 (in[118 +:4]), // Templated
.i119 (in[119 +:4]), // Templated
.i120 (in[120 +:4]), // Templated
.i121 (in[121 +:4]), // Templated
.i122 (in[122 +:4]), // Templated
.i123 (in[123 +:4]), // Templated
.i124 (in[124 +:4]), // Templated
.i125 (in[125 +:4]), // Templated
.i126 (in[126 +:4]), // Templated
.i127 (in[127 +:4]), // Templated
.i128 (in[128 +:4]), // Templated
.i129 (in[129 +:4]), // Templated
.i130 (in[130 +:4]), // Templated
.i131 (in[131 +:4]), // Templated
.i132 (in[132 +:4]), // Templated
.i133 (in[133 +:4]), // Templated
.i134 (in[134 +:4]), // Templated
.i135 (in[135 +:4]), // Templated
.i136 (in[136 +:4]), // Templated
.i137 (in[137 +:4]), // Templated
.i138 (in[138 +:4]), // Templated
.i139 (in[139 +:4]), // Templated
.i140 (in[140 +:4]), // Templated
.i141 (in[141 +:4]), // Templated
.i142 (in[142 +:4]), // Templated
.i143 (in[143 +:4]), // Templated
.i144 (in[144 +:4]), // Templated
.i145 (in[145 +:4]), // Templated
.i146 (in[146 +:4]), // Templated
.i147 (in[147 +:4]), // Templated
.i148 (in[148 +:4]), // Templated
.i149 (in[149 +:4]), // Templated
.i150 (in[150 +:4]), // Templated
.i151 (in[151 +:4]), // Templated
.i152 (in[152 +:4]), // Templated
.i153 (in[153 +:4]), // Templated
.i154 (in[154 +:4]), // Templated
.i155 (in[155 +:4]), // Templated
.i156 (in[156 +:4]), // Templated
.i157 (in[157 +:4]), // Templated
.i158 (in[158 +:4]), // Templated
.i159 (in[159 +:4]), // Templated
.i160 (in[160 +:4]), // Templated
.i161 (in[161 +:4]), // Templated
.i162 (in[162 +:4]), // Templated
.i163 (in[163 +:4]), // Templated
.i164 (in[164 +:4]), // Templated
.i165 (in[165 +:4]), // Templated
.i166 (in[166 +:4]), // Templated
.i167 (in[167 +:4]), // Templated
.i168 (in[168 +:4]), // Templated
.i169 (in[169 +:4]), // Templated
.i170 (in[170 +:4]), // Templated
.i171 (in[171 +:4]), // Templated
.i172 (in[172 +:4]), // Templated
.i173 (in[173 +:4]), // Templated
.i174 (in[174 +:4]), // Templated
.i175 (in[175 +:4]), // Templated
.i176 (in[176 +:4]), // Templated
.i177 (in[177 +:4]), // Templated
.i178 (in[178 +:4]), // Templated
.i179 (in[179 +:4]), // Templated
.i180 (in[180 +:4]), // Templated
.i181 (in[181 +:4]), // Templated
.i182 (in[182 +:4]), // Templated
.i183 (in[183 +:4]), // Templated
.i184 (in[184 +:4]), // Templated
.i185 (in[185 +:4]), // Templated
.i186 (in[186 +:4]), // Templated
.i187 (in[187 +:4]), // Templated
.i188 (in[188 +:4]), // Templated
.i189 (in[189 +:4]), // Templated
.i190 (in[190 +:4]), // Templated
.i191 (in[191 +:4]), // Templated
.i192 (in[192 +:4]), // Templated
.i193 (in[193 +:4]), // Templated
.i194 (in[194 +:4]), // Templated
.i195 (in[195 +:4]), // Templated
.i196 (in[196 +:4]), // Templated
.i197 (in[197 +:4]), // Templated
.i198 (in[198 +:4]), // Templated
.i199 (in[199 +:4]), // Templated
.i200 (in[200 +:4]), // Templated
.i201 (in[201 +:4]), // Templated
.i202 (in[202 +:4]), // Templated
.i203 (in[203 +:4]), // Templated
.i204 (in[204 +:4]), // Templated
.i205 (in[205 +:4]), // Templated
.i206 (in[206 +:4]), // Templated
.i207 (in[207 +:4]), // Templated
.i208 (in[208 +:4]), // Templated
.i209 (in[209 +:4]), // Templated
.i210 (in[210 +:4]), // Templated
.i211 (in[211 +:4]), // Templated
.i212 (in[212 +:4]), // Templated
.i213 (in[213 +:4]), // Templated
.i214 (in[214 +:4]), // Templated
.i215 (in[215 +:4]), // Templated
.i216 (in[216 +:4]), // Templated
.i217 (in[217 +:4]), // Templated
.i218 (in[218 +:4]), // Templated
.i219 (in[219 +:4]), // Templated
.i220 (in[220 +:4]), // Templated
.i221 (in[221 +:4]), // Templated
.i222 (in[222 +:4]), // Templated
.i223 (in[223 +:4]), // Templated
.i224 (in[224 +:4]), // Templated
.i225 (in[225 +:4]), // Templated
.i226 (in[226 +:4]), // Templated
.i227 (in[227 +:4]), // Templated
.i228 (in[228 +:4]), // Templated
.i229 (in[229 +:4]), // Templated
.i230 (in[230 +:4]), // Templated
.i231 (in[231 +:4]), // Templated
.i232 (in[232 +:4]), // Templated
.i233 (in[233 +:4]), // Templated
.i234 (in[234 +:4]), // Templated
.i235 (in[235 +:4]), // Templated
.i236 (in[236 +:4]), // Templated
.i237 (in[237 +:4]), // Templated
.i238 (in[238 +:4]), // Templated
.i239 (in[239 +:4]), // Templated
.i240 (in[240 +:4]), // Templated
.i241 (in[241 +:4]), // Templated
.i242 (in[242 +:4]), // Templated
.i243 (in[243 +:4]), // Templated
.i244 (in[244 +:4]), // Templated
.i245 (in[245 +:4]), // Templated
.i246 (in[246 +:4]), // Templated
.i247 (in[247 +:4]), // Templated
.i248 (in[248 +:4]), // Templated
.i249 (in[249 +:4]), // Templated
.i250 (in[250 +:4]), // Templated
.i251 (in[251 +:4]), // Templated
.i252 (in[252 +:4]), // Templated
.i253 (in[253 +:4]), // Templated
.i254 (in[254 +:4]), // Templated
.i255 (in[255 +:4])); // Templated
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, out};
// What checksum will we end up with
`define EXPECTED_SUM 64'h36f3051d15caf07a
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test
( output wire [3:0] out,
input [7:0] sel,
input [3:0] i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16,
i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i27, i28, i29, i30, i31, i32, i33,
i34, i35, i36, i37, i38, i39, i40, i41, i42, i43, i44, i45, i46, i47, i48, i49, i50,
i51, i52, i53, i54, i55, i56, i57, i58, i59, i60, i61, i62, i63, i64, i65, i66, i67,
i68, i69, i70, i71, i72, i73, i74, i75, i76, i77, i78, i79, i80, i81, i82, i83, i84,
i85, i86, i87, i88, i89, i90, i91, i92, i93, i94, i95, i96, i97, i98, i99, i100, i101,
i102, i103, i104, i105, i106, i107, i108, i109, i110, i111, i112, i113, i114, i115,
i116, i117, i118, i119, i120, i121, i122, i123, i124, i125, i126, i127, i128, i129,
i130, i131, i132, i133, i134, i135, i136, i137, i138, i139, i140, i141, i142, i143,
i144, i145, i146, i147, i148, i149, i150, i151, i152, i153, i154, i155, i156, i157,
i158, i159, i160, i161, i162, i163, i164, i165, i166, i167, i168, i169, i170, i171,
i172, i173, i174, i175, i176, i177, i178, i179, i180, i181, i182, i183, i184, i185,
i186, i187, i188, i189, i190, i191, i192, i193, i194, i195, i196, i197, i198, i199,
i200, i201, i202, i203, i204, i205, i206, i207, i208, i209, i210, i211, i212, i213,
i214, i215, i216, i217, i218, i219, i220, i221, i222, i223, i224, i225, i226, i227,
i228, i229, i230, i231, i232, i233, i234, i235, i236, i237, i238, i239, i240, i241,
i242, i243, i244, i245, i246, i247, i248, i249, i250, i251, i252, i253, i254, i255
);
assign out
= (sel==8'h00) ? i0 : (sel==8'h01) ? i1 : (sel==8'h02) ? i2 : (sel==8'h03) ? i3
: (sel==8'h04) ? i4 : (sel==8'h05) ? i5 : (sel==8'h06) ? i6 : (sel==8'h07) ? i7
: (sel==8'h08) ? i8 : (sel==8'h09) ? i9 : (sel==8'h0a) ? i10 : (sel==8'h0b) ? i11
: (sel==8'h0c) ? i12 : (sel==8'h0d) ? i13 : (sel==8'h0e) ? i14 : (sel==8'h0f) ? i15
: (sel==8'h10) ? i16 : (sel==8'h11) ? i17 : (sel==8'h12) ? i18 : (sel==8'h13) ? i19
: (sel==8'h14) ? i20 : (sel==8'h15) ? i21 : (sel==8'h16) ? i22 : (sel==8'h17) ? i23
: (sel==8'h18) ? i24 : (sel==8'h19) ? i25 : (sel==8'h1a) ? i26 : (sel==8'h1b) ? i27
: (sel==8'h1c) ? i28 : (sel==8'h1d) ? i29 : (sel==8'h1e) ? i30 : (sel==8'h1f) ? i31
: (sel==8'h20) ? i32 : (sel==8'h21) ? i33 : (sel==8'h22) ? i34 : (sel==8'h23) ? i35
: (sel==8'h24) ? i36 : (sel==8'h25) ? i37 : (sel==8'h26) ? i38 : (sel==8'h27) ? i39
: (sel==8'h28) ? i40 : (sel==8'h29) ? i41 : (sel==8'h2a) ? i42 : (sel==8'h2b) ? i43
: (sel==8'h2c) ? i44 : (sel==8'h2d) ? i45 : (sel==8'h2e) ? i46 : (sel==8'h2f) ? i47
: (sel==8'h30) ? i48 : (sel==8'h31) ? i49 : (sel==8'h32) ? i50 : (sel==8'h33) ? i51
: (sel==8'h34) ? i52 : (sel==8'h35) ? i53 : (sel==8'h36) ? i54 : (sel==8'h37) ? i55
: (sel==8'h38) ? i56 : (sel==8'h39) ? i57 : (sel==8'h3a) ? i58 : (sel==8'h3b) ? i59
: (sel==8'h3c) ? i60 : (sel==8'h3d) ? i61 : (sel==8'h3e) ? i62 : (sel==8'h3f) ? i63
: (sel==8'h40) ? i64 : (sel==8'h41) ? i65 : (sel==8'h42) ? i66 : (sel==8'h43) ? i67
: (sel==8'h44) ? i68 : (sel==8'h45) ? i69 : (sel==8'h46) ? i70 : (sel==8'h47) ? i71
: (sel==8'h48) ? i72 : (sel==8'h49) ? i73 : (sel==8'h4a) ? i74 : (sel==8'h4b) ? i75
: (sel==8'h4c) ? i76 : (sel==8'h4d) ? i77 : (sel==8'h4e) ? i78 : (sel==8'h4f) ? i79
: (sel==8'h50) ? i80 : (sel==8'h51) ? i81 : (sel==8'h52) ? i82 : (sel==8'h53) ? i83
: (sel==8'h54) ? i84 : (sel==8'h55) ? i85 : (sel==8'h56) ? i86 : (sel==8'h57) ? i87
: (sel==8'h58) ? i88 : (sel==8'h59) ? i89 : (sel==8'h5a) ? i90 : (sel==8'h5b) ? i91
: (sel==8'h5c) ? i92 : (sel==8'h5d) ? i93 : (sel==8'h5e) ? i94 : (sel==8'h5f) ? i95
: (sel==8'h60) ? i96 : (sel==8'h61) ? i97 : (sel==8'h62) ? i98 : (sel==8'h63) ? i99
: (sel==8'h64) ? i100 : (sel==8'h65) ? i101 : (sel==8'h66) ? i102 : (sel==8'h67) ? i103
: (sel==8'h68) ? i104 : (sel==8'h69) ? i105 : (sel==8'h6a) ? i106 : (sel==8'h6b) ? i107
: (sel==8'h6c) ? i108 : (sel==8'h6d) ? i109 : (sel==8'h6e) ? i110 : (sel==8'h6f) ? i111
: (sel==8'h70) ? i112 : (sel==8'h71) ? i113 : (sel==8'h72) ? i114 : (sel==8'h73) ? i115
: (sel==8'h74) ? i116 : (sel==8'h75) ? i117 : (sel==8'h76) ? i118 : (sel==8'h77) ? i119
: (sel==8'h78) ? i120 : (sel==8'h79) ? i121 : (sel==8'h7a) ? i122 : (sel==8'h7b) ? i123
: (sel==8'h7c) ? i124 : (sel==8'h7d) ? i125 : (sel==8'h7e) ? i126 : (sel==8'h7f) ? i127
: (sel==8'h80) ? i128 : (sel==8'h81) ? i129 : (sel==8'h82) ? i130 : (sel==8'h83) ? i131
: (sel==8'h84) ? i132 : (sel==8'h85) ? i133 : (sel==8'h86) ? i134 : (sel==8'h87) ? i135
: (sel==8'h88) ? i136 : (sel==8'h89) ? i137 : (sel==8'h8a) ? i138 : (sel==8'h8b) ? i139
: (sel==8'h8c) ? i140 : (sel==8'h8d) ? i141 : (sel==8'h8e) ? i142 : (sel==8'h8f) ? i143
: (sel==8'h90) ? i144 : (sel==8'h91) ? i145 : (sel==8'h92) ? i146 : (sel==8'h93) ? i147
: (sel==8'h94) ? i148 : (sel==8'h95) ? i149 : (sel==8'h96) ? i150 : (sel==8'h98) ? i151
: (sel==8'h99) ? i152 : (sel==8'h9a) ? i153 : (sel==8'h9b) ? i154 : (sel==8'h9c) ? i155
: (sel==8'h9d) ? i156 : (sel==8'h9e) ? i157 : (sel==8'h9f) ? i158 : (sel==8'ha0) ? i159
: (sel==8'ha1) ? i160 : (sel==8'ha2) ? i161 : (sel==8'ha3) ? i162 : (sel==8'ha4) ? i163
: (sel==8'ha5) ? i164 : (sel==8'ha6) ? i165 : (sel==8'ha7) ? i166 : (sel==8'ha8) ? i167
: (sel==8'ha9) ? i168 : (sel==8'haa) ? i169 : (sel==8'hab) ? i170 : (sel==8'hac) ? i171
: (sel==8'had) ? i172 : (sel==8'hae) ? i173 : (sel==8'haf) ? i174 : (sel==8'hb0) ? i175
: (sel==8'hb1) ? i176 : (sel==8'hb2) ? i177 : (sel==8'hb3) ? i178 : (sel==8'hb4) ? i179
: (sel==8'hb5) ? i180 : (sel==8'hb6) ? i181 : (sel==8'hb7) ? i182 : (sel==8'hb8) ? i183
: (sel==8'hb9) ? i184 : (sel==8'hba) ? i185 : (sel==8'hbb) ? i186 : (sel==8'hbc) ? i187
: (sel==8'hbd) ? i188 : (sel==8'hbe) ? i189 : (sel==8'hbf) ? i190 : (sel==8'hc0) ? i191
: (sel==8'hc1) ? i192 : (sel==8'hc2) ? i193 : (sel==8'hc3) ? i194 : (sel==8'hc4) ? i195
: (sel==8'hc5) ? i196 : (sel==8'hc6) ? i197 : (sel==8'hc7) ? i198 : (sel==8'hc8) ? i199
: (sel==8'hc9) ? i200 : (sel==8'hca) ? i201 : (sel==8'hcb) ? i202 : (sel==8'hcc) ? i203
: (sel==8'hcd) ? i204 : (sel==8'hce) ? i205 : (sel==8'hcf) ? i206 : (sel==8'hd0) ? i207
: (sel==8'hd1) ? i208 : (sel==8'hd2) ? i209 : (sel==8'hd3) ? i210 : (sel==8'hd4) ? i211
: (sel==8'hd5) ? i212 : (sel==8'hd6) ? i213 : (sel==8'hd7) ? i214 : (sel==8'hd8) ? i215
: (sel==8'hd9) ? i216 : (sel==8'hda) ? i217 : (sel==8'hdb) ? i218 : (sel==8'hdc) ? i219
: (sel==8'hdd) ? i220 : (sel==8'hde) ? i221 : (sel==8'hdf) ? i222 : (sel==8'he0) ? i223
: (sel==8'he1) ? i224 : (sel==8'he2) ? i225 : (sel==8'he3) ? i226 : (sel==8'he4) ? i227
: (sel==8'he5) ? i228 : (sel==8'he6) ? i229 : (sel==8'he7) ? i230 : (sel==8'he8) ? i231
: (sel==8'he9) ? i232 : (sel==8'hea) ? i233 : (sel==8'heb) ? i234 : (sel==8'hec) ? i235
: (sel==8'hed) ? i236 : (sel==8'hee) ? i237 : (sel==8'hef) ? i238 : (sel==8'hf0) ? i239
: (sel==8'hf1) ? i240 : (sel==8'hf2) ? i241 : (sel==8'hf3) ? i242 : (sel==8'hf4) ? i243
: (sel==8'hf5) ? i244 : (sel==8'hf6) ? i245 : (sel==8'hf7) ? i246 : (sel==8'hf8) ? i247
: (sel==8'hf9) ? i248 : (sel==8'hfa) ? i249 : (sel==8'hfb) ? i250 : (sel==8'hfc) ? i251
: (sel==8'hfd) ? i252 : (sel==8'hfe) ? i253 : (sel==8'hff) ? i254 : i255;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [7:0] sel = crc[7:0];
wire [255+3:0] in = {crc[2:0],crc,crc,crc,crc};
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] out; // From test of Test.v
// End of automatics
/* Test AUTO_TEMPLATE (
.i\([0-9]+\) (in[\1 +:4]),
); */
Test test (/*AUTOINST*/
// Outputs
.out (out[3:0]),
// Inputs
.sel (sel[7:0]),
.i0 (in[0 +:4]), // Templated
.i1 (in[1 +:4]), // Templated
.i2 (in[2 +:4]), // Templated
.i3 (in[3 +:4]), // Templated
.i4 (in[4 +:4]), // Templated
.i5 (in[5 +:4]), // Templated
.i6 (in[6 +:4]), // Templated
.i7 (in[7 +:4]), // Templated
.i8 (in[8 +:4]), // Templated
.i9 (in[9 +:4]), // Templated
.i10 (in[10 +:4]), // Templated
.i11 (in[11 +:4]), // Templated
.i12 (in[12 +:4]), // Templated
.i13 (in[13 +:4]), // Templated
.i14 (in[14 +:4]), // Templated
.i15 (in[15 +:4]), // Templated
.i16 (in[16 +:4]), // Templated
.i17 (in[17 +:4]), // Templated
.i18 (in[18 +:4]), // Templated
.i19 (in[19 +:4]), // Templated
.i20 (in[20 +:4]), // Templated
.i21 (in[21 +:4]), // Templated
.i22 (in[22 +:4]), // Templated
.i23 (in[23 +:4]), // Templated
.i24 (in[24 +:4]), // Templated
.i25 (in[25 +:4]), // Templated
.i26 (in[26 +:4]), // Templated
.i27 (in[27 +:4]), // Templated
.i28 (in[28 +:4]), // Templated
.i29 (in[29 +:4]), // Templated
.i30 (in[30 +:4]), // Templated
.i31 (in[31 +:4]), // Templated
.i32 (in[32 +:4]), // Templated
.i33 (in[33 +:4]), // Templated
.i34 (in[34 +:4]), // Templated
.i35 (in[35 +:4]), // Templated
.i36 (in[36 +:4]), // Templated
.i37 (in[37 +:4]), // Templated
.i38 (in[38 +:4]), // Templated
.i39 (in[39 +:4]), // Templated
.i40 (in[40 +:4]), // Templated
.i41 (in[41 +:4]), // Templated
.i42 (in[42 +:4]), // Templated
.i43 (in[43 +:4]), // Templated
.i44 (in[44 +:4]), // Templated
.i45 (in[45 +:4]), // Templated
.i46 (in[46 +:4]), // Templated
.i47 (in[47 +:4]), // Templated
.i48 (in[48 +:4]), // Templated
.i49 (in[49 +:4]), // Templated
.i50 (in[50 +:4]), // Templated
.i51 (in[51 +:4]), // Templated
.i52 (in[52 +:4]), // Templated
.i53 (in[53 +:4]), // Templated
.i54 (in[54 +:4]), // Templated
.i55 (in[55 +:4]), // Templated
.i56 (in[56 +:4]), // Templated
.i57 (in[57 +:4]), // Templated
.i58 (in[58 +:4]), // Templated
.i59 (in[59 +:4]), // Templated
.i60 (in[60 +:4]), // Templated
.i61 (in[61 +:4]), // Templated
.i62 (in[62 +:4]), // Templated
.i63 (in[63 +:4]), // Templated
.i64 (in[64 +:4]), // Templated
.i65 (in[65 +:4]), // Templated
.i66 (in[66 +:4]), // Templated
.i67 (in[67 +:4]), // Templated
.i68 (in[68 +:4]), // Templated
.i69 (in[69 +:4]), // Templated
.i70 (in[70 +:4]), // Templated
.i71 (in[71 +:4]), // Templated
.i72 (in[72 +:4]), // Templated
.i73 (in[73 +:4]), // Templated
.i74 (in[74 +:4]), // Templated
.i75 (in[75 +:4]), // Templated
.i76 (in[76 +:4]), // Templated
.i77 (in[77 +:4]), // Templated
.i78 (in[78 +:4]), // Templated
.i79 (in[79 +:4]), // Templated
.i80 (in[80 +:4]), // Templated
.i81 (in[81 +:4]), // Templated
.i82 (in[82 +:4]), // Templated
.i83 (in[83 +:4]), // Templated
.i84 (in[84 +:4]), // Templated
.i85 (in[85 +:4]), // Templated
.i86 (in[86 +:4]), // Templated
.i87 (in[87 +:4]), // Templated
.i88 (in[88 +:4]), // Templated
.i89 (in[89 +:4]), // Templated
.i90 (in[90 +:4]), // Templated
.i91 (in[91 +:4]), // Templated
.i92 (in[92 +:4]), // Templated
.i93 (in[93 +:4]), // Templated
.i94 (in[94 +:4]), // Templated
.i95 (in[95 +:4]), // Templated
.i96 (in[96 +:4]), // Templated
.i97 (in[97 +:4]), // Templated
.i98 (in[98 +:4]), // Templated
.i99 (in[99 +:4]), // Templated
.i100 (in[100 +:4]), // Templated
.i101 (in[101 +:4]), // Templated
.i102 (in[102 +:4]), // Templated
.i103 (in[103 +:4]), // Templated
.i104 (in[104 +:4]), // Templated
.i105 (in[105 +:4]), // Templated
.i106 (in[106 +:4]), // Templated
.i107 (in[107 +:4]), // Templated
.i108 (in[108 +:4]), // Templated
.i109 (in[109 +:4]), // Templated
.i110 (in[110 +:4]), // Templated
.i111 (in[111 +:4]), // Templated
.i112 (in[112 +:4]), // Templated
.i113 (in[113 +:4]), // Templated
.i114 (in[114 +:4]), // Templated
.i115 (in[115 +:4]), // Templated
.i116 (in[116 +:4]), // Templated
.i117 (in[117 +:4]), // Templated
.i118 (in[118 +:4]), // Templated
.i119 (in[119 +:4]), // Templated
.i120 (in[120 +:4]), // Templated
.i121 (in[121 +:4]), // Templated
.i122 (in[122 +:4]), // Templated
.i123 (in[123 +:4]), // Templated
.i124 (in[124 +:4]), // Templated
.i125 (in[125 +:4]), // Templated
.i126 (in[126 +:4]), // Templated
.i127 (in[127 +:4]), // Templated
.i128 (in[128 +:4]), // Templated
.i129 (in[129 +:4]), // Templated
.i130 (in[130 +:4]), // Templated
.i131 (in[131 +:4]), // Templated
.i132 (in[132 +:4]), // Templated
.i133 (in[133 +:4]), // Templated
.i134 (in[134 +:4]), // Templated
.i135 (in[135 +:4]), // Templated
.i136 (in[136 +:4]), // Templated
.i137 (in[137 +:4]), // Templated
.i138 (in[138 +:4]), // Templated
.i139 (in[139 +:4]), // Templated
.i140 (in[140 +:4]), // Templated
.i141 (in[141 +:4]), // Templated
.i142 (in[142 +:4]), // Templated
.i143 (in[143 +:4]), // Templated
.i144 (in[144 +:4]), // Templated
.i145 (in[145 +:4]), // Templated
.i146 (in[146 +:4]), // Templated
.i147 (in[147 +:4]), // Templated
.i148 (in[148 +:4]), // Templated
.i149 (in[149 +:4]), // Templated
.i150 (in[150 +:4]), // Templated
.i151 (in[151 +:4]), // Templated
.i152 (in[152 +:4]), // Templated
.i153 (in[153 +:4]), // Templated
.i154 (in[154 +:4]), // Templated
.i155 (in[155 +:4]), // Templated
.i156 (in[156 +:4]), // Templated
.i157 (in[157 +:4]), // Templated
.i158 (in[158 +:4]), // Templated
.i159 (in[159 +:4]), // Templated
.i160 (in[160 +:4]), // Templated
.i161 (in[161 +:4]), // Templated
.i162 (in[162 +:4]), // Templated
.i163 (in[163 +:4]), // Templated
.i164 (in[164 +:4]), // Templated
.i165 (in[165 +:4]), // Templated
.i166 (in[166 +:4]), // Templated
.i167 (in[167 +:4]), // Templated
.i168 (in[168 +:4]), // Templated
.i169 (in[169 +:4]), // Templated
.i170 (in[170 +:4]), // Templated
.i171 (in[171 +:4]), // Templated
.i172 (in[172 +:4]), // Templated
.i173 (in[173 +:4]), // Templated
.i174 (in[174 +:4]), // Templated
.i175 (in[175 +:4]), // Templated
.i176 (in[176 +:4]), // Templated
.i177 (in[177 +:4]), // Templated
.i178 (in[178 +:4]), // Templated
.i179 (in[179 +:4]), // Templated
.i180 (in[180 +:4]), // Templated
.i181 (in[181 +:4]), // Templated
.i182 (in[182 +:4]), // Templated
.i183 (in[183 +:4]), // Templated
.i184 (in[184 +:4]), // Templated
.i185 (in[185 +:4]), // Templated
.i186 (in[186 +:4]), // Templated
.i187 (in[187 +:4]), // Templated
.i188 (in[188 +:4]), // Templated
.i189 (in[189 +:4]), // Templated
.i190 (in[190 +:4]), // Templated
.i191 (in[191 +:4]), // Templated
.i192 (in[192 +:4]), // Templated
.i193 (in[193 +:4]), // Templated
.i194 (in[194 +:4]), // Templated
.i195 (in[195 +:4]), // Templated
.i196 (in[196 +:4]), // Templated
.i197 (in[197 +:4]), // Templated
.i198 (in[198 +:4]), // Templated
.i199 (in[199 +:4]), // Templated
.i200 (in[200 +:4]), // Templated
.i201 (in[201 +:4]), // Templated
.i202 (in[202 +:4]), // Templated
.i203 (in[203 +:4]), // Templated
.i204 (in[204 +:4]), // Templated
.i205 (in[205 +:4]), // Templated
.i206 (in[206 +:4]), // Templated
.i207 (in[207 +:4]), // Templated
.i208 (in[208 +:4]), // Templated
.i209 (in[209 +:4]), // Templated
.i210 (in[210 +:4]), // Templated
.i211 (in[211 +:4]), // Templated
.i212 (in[212 +:4]), // Templated
.i213 (in[213 +:4]), // Templated
.i214 (in[214 +:4]), // Templated
.i215 (in[215 +:4]), // Templated
.i216 (in[216 +:4]), // Templated
.i217 (in[217 +:4]), // Templated
.i218 (in[218 +:4]), // Templated
.i219 (in[219 +:4]), // Templated
.i220 (in[220 +:4]), // Templated
.i221 (in[221 +:4]), // Templated
.i222 (in[222 +:4]), // Templated
.i223 (in[223 +:4]), // Templated
.i224 (in[224 +:4]), // Templated
.i225 (in[225 +:4]), // Templated
.i226 (in[226 +:4]), // Templated
.i227 (in[227 +:4]), // Templated
.i228 (in[228 +:4]), // Templated
.i229 (in[229 +:4]), // Templated
.i230 (in[230 +:4]), // Templated
.i231 (in[231 +:4]), // Templated
.i232 (in[232 +:4]), // Templated
.i233 (in[233 +:4]), // Templated
.i234 (in[234 +:4]), // Templated
.i235 (in[235 +:4]), // Templated
.i236 (in[236 +:4]), // Templated
.i237 (in[237 +:4]), // Templated
.i238 (in[238 +:4]), // Templated
.i239 (in[239 +:4]), // Templated
.i240 (in[240 +:4]), // Templated
.i241 (in[241 +:4]), // Templated
.i242 (in[242 +:4]), // Templated
.i243 (in[243 +:4]), // Templated
.i244 (in[244 +:4]), // Templated
.i245 (in[245 +:4]), // Templated
.i246 (in[246 +:4]), // Templated
.i247 (in[247 +:4]), // Templated
.i248 (in[248 +:4]), // Templated
.i249 (in[249 +:4]), // Templated
.i250 (in[250 +:4]), // Templated
.i251 (in[251 +:4]), // Templated
.i252 (in[252 +:4]), // Templated
.i253 (in[253 +:4]), // Templated
.i254 (in[254 +:4]), // Templated
.i255 (in[255 +:4])); // Templated
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, out};
// What checksum will we end up with
`define EXPECTED_SUM 64'h36f3051d15caf07a
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test
( output wire [3:0] out,
input [7:0] sel,
input [3:0] i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16,
i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i27, i28, i29, i30, i31, i32, i33,
i34, i35, i36, i37, i38, i39, i40, i41, i42, i43, i44, i45, i46, i47, i48, i49, i50,
i51, i52, i53, i54, i55, i56, i57, i58, i59, i60, i61, i62, i63, i64, i65, i66, i67,
i68, i69, i70, i71, i72, i73, i74, i75, i76, i77, i78, i79, i80, i81, i82, i83, i84,
i85, i86, i87, i88, i89, i90, i91, i92, i93, i94, i95, i96, i97, i98, i99, i100, i101,
i102, i103, i104, i105, i106, i107, i108, i109, i110, i111, i112, i113, i114, i115,
i116, i117, i118, i119, i120, i121, i122, i123, i124, i125, i126, i127, i128, i129,
i130, i131, i132, i133, i134, i135, i136, i137, i138, i139, i140, i141, i142, i143,
i144, i145, i146, i147, i148, i149, i150, i151, i152, i153, i154, i155, i156, i157,
i158, i159, i160, i161, i162, i163, i164, i165, i166, i167, i168, i169, i170, i171,
i172, i173, i174, i175, i176, i177, i178, i179, i180, i181, i182, i183, i184, i185,
i186, i187, i188, i189, i190, i191, i192, i193, i194, i195, i196, i197, i198, i199,
i200, i201, i202, i203, i204, i205, i206, i207, i208, i209, i210, i211, i212, i213,
i214, i215, i216, i217, i218, i219, i220, i221, i222, i223, i224, i225, i226, i227,
i228, i229, i230, i231, i232, i233, i234, i235, i236, i237, i238, i239, i240, i241,
i242, i243, i244, i245, i246, i247, i248, i249, i250, i251, i252, i253, i254, i255
);
assign out
= (sel==8'h00) ? i0 : (sel==8'h01) ? i1 : (sel==8'h02) ? i2 : (sel==8'h03) ? i3
: (sel==8'h04) ? i4 : (sel==8'h05) ? i5 : (sel==8'h06) ? i6 : (sel==8'h07) ? i7
: (sel==8'h08) ? i8 : (sel==8'h09) ? i9 : (sel==8'h0a) ? i10 : (sel==8'h0b) ? i11
: (sel==8'h0c) ? i12 : (sel==8'h0d) ? i13 : (sel==8'h0e) ? i14 : (sel==8'h0f) ? i15
: (sel==8'h10) ? i16 : (sel==8'h11) ? i17 : (sel==8'h12) ? i18 : (sel==8'h13) ? i19
: (sel==8'h14) ? i20 : (sel==8'h15) ? i21 : (sel==8'h16) ? i22 : (sel==8'h17) ? i23
: (sel==8'h18) ? i24 : (sel==8'h19) ? i25 : (sel==8'h1a) ? i26 : (sel==8'h1b) ? i27
: (sel==8'h1c) ? i28 : (sel==8'h1d) ? i29 : (sel==8'h1e) ? i30 : (sel==8'h1f) ? i31
: (sel==8'h20) ? i32 : (sel==8'h21) ? i33 : (sel==8'h22) ? i34 : (sel==8'h23) ? i35
: (sel==8'h24) ? i36 : (sel==8'h25) ? i37 : (sel==8'h26) ? i38 : (sel==8'h27) ? i39
: (sel==8'h28) ? i40 : (sel==8'h29) ? i41 : (sel==8'h2a) ? i42 : (sel==8'h2b) ? i43
: (sel==8'h2c) ? i44 : (sel==8'h2d) ? i45 : (sel==8'h2e) ? i46 : (sel==8'h2f) ? i47
: (sel==8'h30) ? i48 : (sel==8'h31) ? i49 : (sel==8'h32) ? i50 : (sel==8'h33) ? i51
: (sel==8'h34) ? i52 : (sel==8'h35) ? i53 : (sel==8'h36) ? i54 : (sel==8'h37) ? i55
: (sel==8'h38) ? i56 : (sel==8'h39) ? i57 : (sel==8'h3a) ? i58 : (sel==8'h3b) ? i59
: (sel==8'h3c) ? i60 : (sel==8'h3d) ? i61 : (sel==8'h3e) ? i62 : (sel==8'h3f) ? i63
: (sel==8'h40) ? i64 : (sel==8'h41) ? i65 : (sel==8'h42) ? i66 : (sel==8'h43) ? i67
: (sel==8'h44) ? i68 : (sel==8'h45) ? i69 : (sel==8'h46) ? i70 : (sel==8'h47) ? i71
: (sel==8'h48) ? i72 : (sel==8'h49) ? i73 : (sel==8'h4a) ? i74 : (sel==8'h4b) ? i75
: (sel==8'h4c) ? i76 : (sel==8'h4d) ? i77 : (sel==8'h4e) ? i78 : (sel==8'h4f) ? i79
: (sel==8'h50) ? i80 : (sel==8'h51) ? i81 : (sel==8'h52) ? i82 : (sel==8'h53) ? i83
: (sel==8'h54) ? i84 : (sel==8'h55) ? i85 : (sel==8'h56) ? i86 : (sel==8'h57) ? i87
: (sel==8'h58) ? i88 : (sel==8'h59) ? i89 : (sel==8'h5a) ? i90 : (sel==8'h5b) ? i91
: (sel==8'h5c) ? i92 : (sel==8'h5d) ? i93 : (sel==8'h5e) ? i94 : (sel==8'h5f) ? i95
: (sel==8'h60) ? i96 : (sel==8'h61) ? i97 : (sel==8'h62) ? i98 : (sel==8'h63) ? i99
: (sel==8'h64) ? i100 : (sel==8'h65) ? i101 : (sel==8'h66) ? i102 : (sel==8'h67) ? i103
: (sel==8'h68) ? i104 : (sel==8'h69) ? i105 : (sel==8'h6a) ? i106 : (sel==8'h6b) ? i107
: (sel==8'h6c) ? i108 : (sel==8'h6d) ? i109 : (sel==8'h6e) ? i110 : (sel==8'h6f) ? i111
: (sel==8'h70) ? i112 : (sel==8'h71) ? i113 : (sel==8'h72) ? i114 : (sel==8'h73) ? i115
: (sel==8'h74) ? i116 : (sel==8'h75) ? i117 : (sel==8'h76) ? i118 : (sel==8'h77) ? i119
: (sel==8'h78) ? i120 : (sel==8'h79) ? i121 : (sel==8'h7a) ? i122 : (sel==8'h7b) ? i123
: (sel==8'h7c) ? i124 : (sel==8'h7d) ? i125 : (sel==8'h7e) ? i126 : (sel==8'h7f) ? i127
: (sel==8'h80) ? i128 : (sel==8'h81) ? i129 : (sel==8'h82) ? i130 : (sel==8'h83) ? i131
: (sel==8'h84) ? i132 : (sel==8'h85) ? i133 : (sel==8'h86) ? i134 : (sel==8'h87) ? i135
: (sel==8'h88) ? i136 : (sel==8'h89) ? i137 : (sel==8'h8a) ? i138 : (sel==8'h8b) ? i139
: (sel==8'h8c) ? i140 : (sel==8'h8d) ? i141 : (sel==8'h8e) ? i142 : (sel==8'h8f) ? i143
: (sel==8'h90) ? i144 : (sel==8'h91) ? i145 : (sel==8'h92) ? i146 : (sel==8'h93) ? i147
: (sel==8'h94) ? i148 : (sel==8'h95) ? i149 : (sel==8'h96) ? i150 : (sel==8'h98) ? i151
: (sel==8'h99) ? i152 : (sel==8'h9a) ? i153 : (sel==8'h9b) ? i154 : (sel==8'h9c) ? i155
: (sel==8'h9d) ? i156 : (sel==8'h9e) ? i157 : (sel==8'h9f) ? i158 : (sel==8'ha0) ? i159
: (sel==8'ha1) ? i160 : (sel==8'ha2) ? i161 : (sel==8'ha3) ? i162 : (sel==8'ha4) ? i163
: (sel==8'ha5) ? i164 : (sel==8'ha6) ? i165 : (sel==8'ha7) ? i166 : (sel==8'ha8) ? i167
: (sel==8'ha9) ? i168 : (sel==8'haa) ? i169 : (sel==8'hab) ? i170 : (sel==8'hac) ? i171
: (sel==8'had) ? i172 : (sel==8'hae) ? i173 : (sel==8'haf) ? i174 : (sel==8'hb0) ? i175
: (sel==8'hb1) ? i176 : (sel==8'hb2) ? i177 : (sel==8'hb3) ? i178 : (sel==8'hb4) ? i179
: (sel==8'hb5) ? i180 : (sel==8'hb6) ? i181 : (sel==8'hb7) ? i182 : (sel==8'hb8) ? i183
: (sel==8'hb9) ? i184 : (sel==8'hba) ? i185 : (sel==8'hbb) ? i186 : (sel==8'hbc) ? i187
: (sel==8'hbd) ? i188 : (sel==8'hbe) ? i189 : (sel==8'hbf) ? i190 : (sel==8'hc0) ? i191
: (sel==8'hc1) ? i192 : (sel==8'hc2) ? i193 : (sel==8'hc3) ? i194 : (sel==8'hc4) ? i195
: (sel==8'hc5) ? i196 : (sel==8'hc6) ? i197 : (sel==8'hc7) ? i198 : (sel==8'hc8) ? i199
: (sel==8'hc9) ? i200 : (sel==8'hca) ? i201 : (sel==8'hcb) ? i202 : (sel==8'hcc) ? i203
: (sel==8'hcd) ? i204 : (sel==8'hce) ? i205 : (sel==8'hcf) ? i206 : (sel==8'hd0) ? i207
: (sel==8'hd1) ? i208 : (sel==8'hd2) ? i209 : (sel==8'hd3) ? i210 : (sel==8'hd4) ? i211
: (sel==8'hd5) ? i212 : (sel==8'hd6) ? i213 : (sel==8'hd7) ? i214 : (sel==8'hd8) ? i215
: (sel==8'hd9) ? i216 : (sel==8'hda) ? i217 : (sel==8'hdb) ? i218 : (sel==8'hdc) ? i219
: (sel==8'hdd) ? i220 : (sel==8'hde) ? i221 : (sel==8'hdf) ? i222 : (sel==8'he0) ? i223
: (sel==8'he1) ? i224 : (sel==8'he2) ? i225 : (sel==8'he3) ? i226 : (sel==8'he4) ? i227
: (sel==8'he5) ? i228 : (sel==8'he6) ? i229 : (sel==8'he7) ? i230 : (sel==8'he8) ? i231
: (sel==8'he9) ? i232 : (sel==8'hea) ? i233 : (sel==8'heb) ? i234 : (sel==8'hec) ? i235
: (sel==8'hed) ? i236 : (sel==8'hee) ? i237 : (sel==8'hef) ? i238 : (sel==8'hf0) ? i239
: (sel==8'hf1) ? i240 : (sel==8'hf2) ? i241 : (sel==8'hf3) ? i242 : (sel==8'hf4) ? i243
: (sel==8'hf5) ? i244 : (sel==8'hf6) ? i245 : (sel==8'hf7) ? i246 : (sel==8'hf8) ? i247
: (sel==8'hf9) ? i248 : (sel==8'hfa) ? i249 : (sel==8'hfb) ? i250 : (sel==8'hfc) ? i251
: (sel==8'hfd) ? i252 : (sel==8'hfe) ? i253 : (sel==8'hff) ? i254 : i255;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t_case_huge_sub (/*AUTOARG*/
// Outputs
outa, outb, outc,
// Inputs
index
);
input [7:0] index;
output [9:0] outa;
output [1:0] outb;
output outc;
// =============================
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [9:0] outa;
reg [1:0] outb;
reg outc;
// End of automatics
// =============================
// Created from perl
// for $i (0..1023) { printf "\t10'h%03x: begin outa = 10'h%03x; outb = 2'b%02b; outc = 1'b%d; end\n", $i, rand(1024),rand(4),rand(2); };
always @(/*AS*/index) begin
case (index)
8'h00: begin outa = 10'h152; outb = 2'b00; outc = 1'b1; end
8'h01: begin outa = 10'h318; outb = 2'b11; outc = 1'b1; end
8'h02: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end
8'h03: begin outa = 10'h392; outb = 2'b01; outc = 1'b1; end
8'h04: begin outa = 10'h1ef; outb = 2'b00; outc = 1'b0; end
8'h05: begin outa = 10'h06c; outb = 2'b10; outc = 1'b1; end
8'h06: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end
8'h07: begin outa = 10'h29a; outb = 2'b10; outc = 1'b0; end
8'h08: begin outa = 10'h3ce; outb = 2'b01; outc = 1'b0; end
8'h09: begin outa = 10'h37c; outb = 2'b01; outc = 1'b0; end
8'h0a: begin outa = 10'h058; outb = 2'b10; outc = 1'b0; end
8'h0b: begin outa = 10'h3b2; outb = 2'b01; outc = 1'b1; end
8'h0c: begin outa = 10'h36f; outb = 2'b11; outc = 1'b0; end
8'h0d: begin outa = 10'h2c5; outb = 2'b11; outc = 1'b0; end
8'h0e: begin outa = 10'h23a; outb = 2'b00; outc = 1'b0; end
8'h0f: begin outa = 10'h222; outb = 2'b01; outc = 1'b1; end
8'h10: begin outa = 10'h328; outb = 2'b00; outc = 1'b1; end
8'h11: begin outa = 10'h3c3; outb = 2'b00; outc = 1'b1; end
8'h12: begin outa = 10'h12c; outb = 2'b01; outc = 1'b0; end
8'h13: begin outa = 10'h1d0; outb = 2'b00; outc = 1'b1; end
8'h14: begin outa = 10'h3ff; outb = 2'b01; outc = 1'b1; end
8'h15: begin outa = 10'h115; outb = 2'b11; outc = 1'b1; end
8'h16: begin outa = 10'h3ba; outb = 2'b10; outc = 1'b0; end
8'h17: begin outa = 10'h3ba; outb = 2'b00; outc = 1'b0; end
8'h18: begin outa = 10'h10d; outb = 2'b00; outc = 1'b1; end
8'h19: begin outa = 10'h13b; outb = 2'b01; outc = 1'b1; end
8'h1a: begin outa = 10'h0a0; outb = 2'b10; outc = 1'b1; end
8'h1b: begin outa = 10'h264; outb = 2'b11; outc = 1'b0; end
8'h1c: begin outa = 10'h3a2; outb = 2'b10; outc = 1'b0; end
8'h1d: begin outa = 10'h07c; outb = 2'b00; outc = 1'b1; end
8'h1e: begin outa = 10'h291; outb = 2'b00; outc = 1'b0; end
8'h1f: begin outa = 10'h1d1; outb = 2'b10; outc = 1'b0; end
8'h20: begin outa = 10'h354; outb = 2'b11; outc = 1'b1; end
8'h21: begin outa = 10'h0c0; outb = 2'b00; outc = 1'b1; end
8'h22: begin outa = 10'h191; outb = 2'b00; outc = 1'b0; end
8'h23: begin outa = 10'h379; outb = 2'b01; outc = 1'b0; end
8'h24: begin outa = 10'h073; outb = 2'b00; outc = 1'b0; end
8'h25: begin outa = 10'h2fd; outb = 2'b11; outc = 1'b1; end
8'h26: begin outa = 10'h2e0; outb = 2'b11; outc = 1'b1; end
8'h27: begin outa = 10'h337; outb = 2'b01; outc = 1'b1; end
8'h28: begin outa = 10'h2c7; outb = 2'b11; outc = 1'b1; end
8'h29: begin outa = 10'h19e; outb = 2'b11; outc = 1'b0; end
8'h2a: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end
8'h2b: begin outa = 10'h06a; outb = 2'b01; outc = 1'b1; end
8'h2c: begin outa = 10'h1c7; outb = 2'b01; outc = 1'b1; end
8'h2d: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end
8'h2e: begin outa = 10'h0cf; outb = 2'b01; outc = 1'b1; end
8'h2f: begin outa = 10'h009; outb = 2'b11; outc = 1'b1; end
8'h30: begin outa = 10'h09d; outb = 2'b00; outc = 1'b1; end
8'h31: begin outa = 10'h28e; outb = 2'b00; outc = 1'b0; end
8'h32: begin outa = 10'h010; outb = 2'b01; outc = 1'b0; end
8'h33: begin outa = 10'h1e0; outb = 2'b10; outc = 1'b0; end
8'h34: begin outa = 10'h079; outb = 2'b01; outc = 1'b1; end
8'h35: begin outa = 10'h13e; outb = 2'b10; outc = 1'b1; end
8'h36: begin outa = 10'h282; outb = 2'b11; outc = 1'b0; end
8'h37: begin outa = 10'h21c; outb = 2'b11; outc = 1'b1; end
8'h38: begin outa = 10'h148; outb = 2'b00; outc = 1'b1; end
8'h39: begin outa = 10'h3c0; outb = 2'b10; outc = 1'b0; end
8'h3a: begin outa = 10'h176; outb = 2'b01; outc = 1'b1; end
8'h3b: begin outa = 10'h3fc; outb = 2'b10; outc = 1'b1; end
8'h3c: begin outa = 10'h295; outb = 2'b11; outc = 1'b1; end
8'h3d: begin outa = 10'h113; outb = 2'b10; outc = 1'b1; end
8'h3e: begin outa = 10'h354; outb = 2'b01; outc = 1'b1; end
8'h3f: begin outa = 10'h0db; outb = 2'b11; outc = 1'b0; end
8'h40: begin outa = 10'h238; outb = 2'b01; outc = 1'b0; end
8'h41: begin outa = 10'h12b; outb = 2'b01; outc = 1'b1; end
8'h42: begin outa = 10'h1dc; outb = 2'b10; outc = 1'b0; end
8'h43: begin outa = 10'h137; outb = 2'b01; outc = 1'b1; end
8'h44: begin outa = 10'h1e2; outb = 2'b01; outc = 1'b1; end
8'h45: begin outa = 10'h3d5; outb = 2'b11; outc = 1'b1; end
8'h46: begin outa = 10'h30c; outb = 2'b11; outc = 1'b0; end
8'h47: begin outa = 10'h298; outb = 2'b11; outc = 1'b0; end
8'h48: begin outa = 10'h080; outb = 2'b00; outc = 1'b1; end
8'h49: begin outa = 10'h35a; outb = 2'b11; outc = 1'b1; end
8'h4a: begin outa = 10'h01b; outb = 2'b00; outc = 1'b0; end
8'h4b: begin outa = 10'h0a3; outb = 2'b11; outc = 1'b0; end
8'h4c: begin outa = 10'h0b3; outb = 2'b11; outc = 1'b1; end
8'h4d: begin outa = 10'h17a; outb = 2'b00; outc = 1'b0; end
8'h4e: begin outa = 10'h3ae; outb = 2'b11; outc = 1'b0; end
8'h4f: begin outa = 10'h078; outb = 2'b11; outc = 1'b0; end
8'h50: begin outa = 10'h322; outb = 2'b00; outc = 1'b1; end
8'h51: begin outa = 10'h213; outb = 2'b11; outc = 1'b0; end
8'h52: begin outa = 10'h11a; outb = 2'b11; outc = 1'b0; end
8'h53: begin outa = 10'h1a7; outb = 2'b00; outc = 1'b0; end
8'h54: begin outa = 10'h35a; outb = 2'b00; outc = 1'b1; end
8'h55: begin outa = 10'h233; outb = 2'b00; outc = 1'b0; end
8'h56: begin outa = 10'h01d; outb = 2'b01; outc = 1'b1; end
8'h57: begin outa = 10'h2d5; outb = 2'b00; outc = 1'b0; end
8'h58: begin outa = 10'h1a0; outb = 2'b00; outc = 1'b1; end
8'h59: begin outa = 10'h3d0; outb = 2'b00; outc = 1'b1; end
8'h5a: begin outa = 10'h181; outb = 2'b01; outc = 1'b1; end
8'h5b: begin outa = 10'h219; outb = 2'b01; outc = 1'b1; end
8'h5c: begin outa = 10'h26a; outb = 2'b01; outc = 1'b1; end
8'h5d: begin outa = 10'h050; outb = 2'b10; outc = 1'b0; end
8'h5e: begin outa = 10'h189; outb = 2'b10; outc = 1'b0; end
8'h5f: begin outa = 10'h1eb; outb = 2'b01; outc = 1'b1; end
8'h60: begin outa = 10'h224; outb = 2'b00; outc = 1'b1; end
8'h61: begin outa = 10'h2fe; outb = 2'b00; outc = 1'b0; end
8'h62: begin outa = 10'h0ae; outb = 2'b00; outc = 1'b1; end
8'h63: begin outa = 10'h1cd; outb = 2'b00; outc = 1'b0; end
8'h64: begin outa = 10'h273; outb = 2'b10; outc = 1'b1; end
8'h65: begin outa = 10'h268; outb = 2'b10; outc = 1'b0; end
8'h66: begin outa = 10'h111; outb = 2'b01; outc = 1'b0; end
8'h67: begin outa = 10'h1f9; outb = 2'b00; outc = 1'b0; end
8'h68: begin outa = 10'h232; outb = 2'b00; outc = 1'b1; end
8'h69: begin outa = 10'h255; outb = 2'b11; outc = 1'b0; end
8'h6a: begin outa = 10'h34c; outb = 2'b01; outc = 1'b1; end
8'h6b: begin outa = 10'h049; outb = 2'b01; outc = 1'b1; end
8'h6c: begin outa = 10'h197; outb = 2'b11; outc = 1'b0; end
8'h6d: begin outa = 10'h0fe; outb = 2'b11; outc = 1'b0; end
8'h6e: begin outa = 10'h253; outb = 2'b01; outc = 1'b1; end
8'h6f: begin outa = 10'h2de; outb = 2'b11; outc = 1'b0; end
8'h70: begin outa = 10'h13b; outb = 2'b10; outc = 1'b1; end
8'h71: begin outa = 10'h040; outb = 2'b10; outc = 1'b0; end
8'h72: begin outa = 10'h0b4; outb = 2'b00; outc = 1'b1; end
8'h73: begin outa = 10'h233; outb = 2'b11; outc = 1'b1; end
8'h74: begin outa = 10'h198; outb = 2'b00; outc = 1'b1; end
8'h75: begin outa = 10'h018; outb = 2'b00; outc = 1'b1; end
8'h76: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end
8'h77: begin outa = 10'h134; outb = 2'b11; outc = 1'b0; end
8'h78: begin outa = 10'h1ca; outb = 2'b10; outc = 1'b0; end
8'h79: begin outa = 10'h286; outb = 2'b10; outc = 1'b1; end
8'h7a: begin outa = 10'h0e6; outb = 2'b11; outc = 1'b1; end
8'h7b: begin outa = 10'h064; outb = 2'b10; outc = 1'b1; end
8'h7c: begin outa = 10'h257; outb = 2'b00; outc = 1'b1; end
8'h7d: begin outa = 10'h31a; outb = 2'b10; outc = 1'b1; end
8'h7e: begin outa = 10'h247; outb = 2'b01; outc = 1'b0; end
8'h7f: begin outa = 10'h299; outb = 2'b00; outc = 1'b0; end
8'h80: begin outa = 10'h02c; outb = 2'b00; outc = 1'b0; end
8'h81: begin outa = 10'h2bb; outb = 2'b11; outc = 1'b0; end
8'h82: begin outa = 10'h180; outb = 2'b10; outc = 1'b0; end
8'h83: begin outa = 10'h245; outb = 2'b01; outc = 1'b1; end
8'h84: begin outa = 10'h0da; outb = 2'b10; outc = 1'b0; end
8'h85: begin outa = 10'h367; outb = 2'b10; outc = 1'b0; end
8'h86: begin outa = 10'h304; outb = 2'b01; outc = 1'b0; end
8'h87: begin outa = 10'h38b; outb = 2'b11; outc = 1'b0; end
8'h88: begin outa = 10'h09f; outb = 2'b01; outc = 1'b0; end
8'h89: begin outa = 10'h1f0; outb = 2'b10; outc = 1'b1; end
8'h8a: begin outa = 10'h281; outb = 2'b10; outc = 1'b1; end
8'h8b: begin outa = 10'h019; outb = 2'b00; outc = 1'b0; end
8'h8c: begin outa = 10'h1f2; outb = 2'b10; outc = 1'b0; end
8'h8d: begin outa = 10'h0b1; outb = 2'b01; outc = 1'b1; end
8'h8e: begin outa = 10'h058; outb = 2'b01; outc = 1'b1; end
8'h8f: begin outa = 10'h39b; outb = 2'b00; outc = 1'b1; end
8'h90: begin outa = 10'h2ec; outb = 2'b10; outc = 1'b1; end
8'h91: begin outa = 10'h250; outb = 2'b00; outc = 1'b1; end
8'h92: begin outa = 10'h3f4; outb = 2'b10; outc = 1'b1; end
8'h93: begin outa = 10'h057; outb = 2'b10; outc = 1'b1; end
8'h94: begin outa = 10'h18f; outb = 2'b01; outc = 1'b1; end
8'h95: begin outa = 10'h105; outb = 2'b01; outc = 1'b1; end
8'h96: begin outa = 10'h1ae; outb = 2'b00; outc = 1'b1; end
8'h97: begin outa = 10'h04e; outb = 2'b10; outc = 1'b0; end
8'h98: begin outa = 10'h240; outb = 2'b11; outc = 1'b0; end
8'h99: begin outa = 10'h3e4; outb = 2'b01; outc = 1'b0; end
8'h9a: begin outa = 10'h3c6; outb = 2'b01; outc = 1'b0; end
8'h9b: begin outa = 10'h109; outb = 2'b00; outc = 1'b1; end
8'h9c: begin outa = 10'h073; outb = 2'b10; outc = 1'b1; end
8'h9d: begin outa = 10'h19f; outb = 2'b01; outc = 1'b0; end
8'h9e: begin outa = 10'h3b8; outb = 2'b01; outc = 1'b0; end
8'h9f: begin outa = 10'h00e; outb = 2'b00; outc = 1'b1; end
8'ha0: begin outa = 10'h1b3; outb = 2'b11; outc = 1'b1; end
8'ha1: begin outa = 10'h2bd; outb = 2'b11; outc = 1'b0; end
8'ha2: begin outa = 10'h324; outb = 2'b00; outc = 1'b1; end
8'ha3: begin outa = 10'h343; outb = 2'b10; outc = 1'b0; end
8'ha4: begin outa = 10'h1c9; outb = 2'b01; outc = 1'b0; end
8'ha5: begin outa = 10'h185; outb = 2'b00; outc = 1'b1; end
8'ha6: begin outa = 10'h37a; outb = 2'b00; outc = 1'b1; end
8'ha7: begin outa = 10'h0e0; outb = 2'b01; outc = 1'b1; end
8'ha8: begin outa = 10'h0a3; outb = 2'b10; outc = 1'b0; end
8'ha9: begin outa = 10'h019; outb = 2'b11; outc = 1'b0; end
8'haa: begin outa = 10'h099; outb = 2'b00; outc = 1'b1; end
8'hab: begin outa = 10'h376; outb = 2'b01; outc = 1'b1; end
8'hac: begin outa = 10'h077; outb = 2'b00; outc = 1'b1; end
8'had: begin outa = 10'h2b1; outb = 2'b11; outc = 1'b1; end
8'hae: begin outa = 10'h27f; outb = 2'b00; outc = 1'b0; end
8'haf: begin outa = 10'h265; outb = 2'b11; outc = 1'b0; end
8'hb0: begin outa = 10'h156; outb = 2'b10; outc = 1'b1; end
8'hb1: begin outa = 10'h1ce; outb = 2'b00; outc = 1'b0; end
8'hb2: begin outa = 10'h008; outb = 2'b01; outc = 1'b0; end
8'hb3: begin outa = 10'h12e; outb = 2'b11; outc = 1'b1; end
8'hb4: begin outa = 10'h199; outb = 2'b11; outc = 1'b0; end
8'hb5: begin outa = 10'h330; outb = 2'b10; outc = 1'b0; end
8'hb6: begin outa = 10'h1ab; outb = 2'b01; outc = 1'b1; end
8'hb7: begin outa = 10'h3bd; outb = 2'b00; outc = 1'b0; end
8'hb8: begin outa = 10'h0ca; outb = 2'b10; outc = 1'b0; end
8'hb9: begin outa = 10'h367; outb = 2'b00; outc = 1'b0; end
8'hba: begin outa = 10'h334; outb = 2'b00; outc = 1'b0; end
8'hbb: begin outa = 10'h040; outb = 2'b00; outc = 1'b1; end
8'hbc: begin outa = 10'h1a7; outb = 2'b10; outc = 1'b1; end
8'hbd: begin outa = 10'h036; outb = 2'b11; outc = 1'b1; end
8'hbe: begin outa = 10'h223; outb = 2'b11; outc = 1'b1; end
8'hbf: begin outa = 10'h075; outb = 2'b01; outc = 1'b0; end
8'hc0: begin outa = 10'h3c4; outb = 2'b00; outc = 1'b1; end
8'hc1: begin outa = 10'h2cc; outb = 2'b01; outc = 1'b0; end
8'hc2: begin outa = 10'h123; outb = 2'b01; outc = 1'b0; end
8'hc3: begin outa = 10'h3fd; outb = 2'b01; outc = 1'b1; end
8'hc4: begin outa = 10'h11e; outb = 2'b00; outc = 1'b0; end
8'hc5: begin outa = 10'h27c; outb = 2'b11; outc = 1'b1; end
8'hc6: begin outa = 10'h1e2; outb = 2'b11; outc = 1'b0; end
8'hc7: begin outa = 10'h377; outb = 2'b11; outc = 1'b0; end
8'hc8: begin outa = 10'h33a; outb = 2'b11; outc = 1'b0; end
8'hc9: begin outa = 10'h32d; outb = 2'b11; outc = 1'b1; end
8'hca: begin outa = 10'h014; outb = 2'b11; outc = 1'b0; end
8'hcb: begin outa = 10'h332; outb = 2'b10; outc = 1'b0; end
8'hcc: begin outa = 10'h359; outb = 2'b00; outc = 1'b0; end
8'hcd: begin outa = 10'h0a4; outb = 2'b10; outc = 1'b1; end
8'hce: begin outa = 10'h348; outb = 2'b00; outc = 1'b1; end
8'hcf: begin outa = 10'h04b; outb = 2'b11; outc = 1'b1; end
8'hd0: begin outa = 10'h147; outb = 2'b10; outc = 1'b1; end
8'hd1: begin outa = 10'h026; outb = 2'b00; outc = 1'b1; end
8'hd2: begin outa = 10'h103; outb = 2'b00; outc = 1'b0; end
8'hd3: begin outa = 10'h106; outb = 2'b00; outc = 1'b1; end
8'hd4: begin outa = 10'h35a; outb = 2'b00; outc = 1'b0; end
8'hd5: begin outa = 10'h254; outb = 2'b01; outc = 1'b0; end
8'hd6: begin outa = 10'h0cd; outb = 2'b01; outc = 1'b0; end
8'hd7: begin outa = 10'h17c; outb = 2'b11; outc = 1'b1; end
8'hd8: begin outa = 10'h37e; outb = 2'b10; outc = 1'b1; end
8'hd9: begin outa = 10'h0a9; outb = 2'b11; outc = 1'b1; end
8'hda: begin outa = 10'h0fe; outb = 2'b01; outc = 1'b0; end
8'hdb: begin outa = 10'h3c0; outb = 2'b11; outc = 1'b1; end
8'hdc: begin outa = 10'h1d9; outb = 2'b10; outc = 1'b1; end
8'hdd: begin outa = 10'h10e; outb = 2'b00; outc = 1'b1; end
8'hde: begin outa = 10'h394; outb = 2'b01; outc = 1'b0; end
8'hdf: begin outa = 10'h316; outb = 2'b01; outc = 1'b0; end
8'he0: begin outa = 10'h05b; outb = 2'b11; outc = 1'b0; end
8'he1: begin outa = 10'h126; outb = 2'b01; outc = 1'b1; end
8'he2: begin outa = 10'h369; outb = 2'b11; outc = 1'b0; end
8'he3: begin outa = 10'h291; outb = 2'b10; outc = 1'b1; end
8'he4: begin outa = 10'h2ca; outb = 2'b00; outc = 1'b1; end
8'he5: begin outa = 10'h25b; outb = 2'b01; outc = 1'b1; end
8'he6: begin outa = 10'h106; outb = 2'b00; outc = 1'b0; end
8'he7: begin outa = 10'h172; outb = 2'b11; outc = 1'b1; end
8'he8: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end
8'he9: begin outa = 10'h2d3; outb = 2'b11; outc = 1'b1; end
8'hea: begin outa = 10'h182; outb = 2'b00; outc = 1'b0; end
8'heb: begin outa = 10'h327; outb = 2'b00; outc = 1'b1; end
8'hec: begin outa = 10'h1d0; outb = 2'b10; outc = 1'b0; end
8'hed: begin outa = 10'h204; outb = 2'b00; outc = 1'b1; end
8'hee: begin outa = 10'h11f; outb = 2'b00; outc = 1'b1; end
8'hef: begin outa = 10'h365; outb = 2'b11; outc = 1'b1; end
8'hf0: begin outa = 10'h2c2; outb = 2'b01; outc = 1'b1; end
8'hf1: begin outa = 10'h2b5; outb = 2'b10; outc = 1'b0; end
8'hf2: begin outa = 10'h1f8; outb = 2'b10; outc = 1'b1; end
8'hf3: begin outa = 10'h2a7; outb = 2'b01; outc = 1'b1; end
8'hf4: begin outa = 10'h1be; outb = 2'b10; outc = 1'b1; end
8'hf5: begin outa = 10'h25e; outb = 2'b10; outc = 1'b1; end
8'hf6: begin outa = 10'h032; outb = 2'b10; outc = 1'b0; end
8'hf7: begin outa = 10'h2ef; outb = 2'b00; outc = 1'b0; end
8'hf8: begin outa = 10'h02f; outb = 2'b00; outc = 1'b1; end
8'hf9: begin outa = 10'h201; outb = 2'b10; outc = 1'b0; end
8'hfa: begin outa = 10'h054; outb = 2'b01; outc = 1'b1; end
8'hfb: begin outa = 10'h013; outb = 2'b10; outc = 1'b0; end
8'hfc: begin outa = 10'h249; outb = 2'b01; outc = 1'b0; end
8'hfd: begin outa = 10'h09a; outb = 2'b10; outc = 1'b0; end
8'hfe: begin outa = 10'h012; outb = 2'b00; outc = 1'b0; end
8'hff: begin outa = 10'h114; outb = 2'b10; outc = 1'b1; end
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t_case_huge_sub (/*AUTOARG*/
// Outputs
outa, outb, outc,
// Inputs
index
);
input [7:0] index;
output [9:0] outa;
output [1:0] outb;
output outc;
// =============================
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [9:0] outa;
reg [1:0] outb;
reg outc;
// End of automatics
// =============================
// Created from perl
// for $i (0..1023) { printf "\t10'h%03x: begin outa = 10'h%03x; outb = 2'b%02b; outc = 1'b%d; end\n", $i, rand(1024),rand(4),rand(2); };
always @(/*AS*/index) begin
case (index)
8'h00: begin outa = 10'h152; outb = 2'b00; outc = 1'b1; end
8'h01: begin outa = 10'h318; outb = 2'b11; outc = 1'b1; end
8'h02: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end
8'h03: begin outa = 10'h392; outb = 2'b01; outc = 1'b1; end
8'h04: begin outa = 10'h1ef; outb = 2'b00; outc = 1'b0; end
8'h05: begin outa = 10'h06c; outb = 2'b10; outc = 1'b1; end
8'h06: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end
8'h07: begin outa = 10'h29a; outb = 2'b10; outc = 1'b0; end
8'h08: begin outa = 10'h3ce; outb = 2'b01; outc = 1'b0; end
8'h09: begin outa = 10'h37c; outb = 2'b01; outc = 1'b0; end
8'h0a: begin outa = 10'h058; outb = 2'b10; outc = 1'b0; end
8'h0b: begin outa = 10'h3b2; outb = 2'b01; outc = 1'b1; end
8'h0c: begin outa = 10'h36f; outb = 2'b11; outc = 1'b0; end
8'h0d: begin outa = 10'h2c5; outb = 2'b11; outc = 1'b0; end
8'h0e: begin outa = 10'h23a; outb = 2'b00; outc = 1'b0; end
8'h0f: begin outa = 10'h222; outb = 2'b01; outc = 1'b1; end
8'h10: begin outa = 10'h328; outb = 2'b00; outc = 1'b1; end
8'h11: begin outa = 10'h3c3; outb = 2'b00; outc = 1'b1; end
8'h12: begin outa = 10'h12c; outb = 2'b01; outc = 1'b0; end
8'h13: begin outa = 10'h1d0; outb = 2'b00; outc = 1'b1; end
8'h14: begin outa = 10'h3ff; outb = 2'b01; outc = 1'b1; end
8'h15: begin outa = 10'h115; outb = 2'b11; outc = 1'b1; end
8'h16: begin outa = 10'h3ba; outb = 2'b10; outc = 1'b0; end
8'h17: begin outa = 10'h3ba; outb = 2'b00; outc = 1'b0; end
8'h18: begin outa = 10'h10d; outb = 2'b00; outc = 1'b1; end
8'h19: begin outa = 10'h13b; outb = 2'b01; outc = 1'b1; end
8'h1a: begin outa = 10'h0a0; outb = 2'b10; outc = 1'b1; end
8'h1b: begin outa = 10'h264; outb = 2'b11; outc = 1'b0; end
8'h1c: begin outa = 10'h3a2; outb = 2'b10; outc = 1'b0; end
8'h1d: begin outa = 10'h07c; outb = 2'b00; outc = 1'b1; end
8'h1e: begin outa = 10'h291; outb = 2'b00; outc = 1'b0; end
8'h1f: begin outa = 10'h1d1; outb = 2'b10; outc = 1'b0; end
8'h20: begin outa = 10'h354; outb = 2'b11; outc = 1'b1; end
8'h21: begin outa = 10'h0c0; outb = 2'b00; outc = 1'b1; end
8'h22: begin outa = 10'h191; outb = 2'b00; outc = 1'b0; end
8'h23: begin outa = 10'h379; outb = 2'b01; outc = 1'b0; end
8'h24: begin outa = 10'h073; outb = 2'b00; outc = 1'b0; end
8'h25: begin outa = 10'h2fd; outb = 2'b11; outc = 1'b1; end
8'h26: begin outa = 10'h2e0; outb = 2'b11; outc = 1'b1; end
8'h27: begin outa = 10'h337; outb = 2'b01; outc = 1'b1; end
8'h28: begin outa = 10'h2c7; outb = 2'b11; outc = 1'b1; end
8'h29: begin outa = 10'h19e; outb = 2'b11; outc = 1'b0; end
8'h2a: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end
8'h2b: begin outa = 10'h06a; outb = 2'b01; outc = 1'b1; end
8'h2c: begin outa = 10'h1c7; outb = 2'b01; outc = 1'b1; end
8'h2d: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end
8'h2e: begin outa = 10'h0cf; outb = 2'b01; outc = 1'b1; end
8'h2f: begin outa = 10'h009; outb = 2'b11; outc = 1'b1; end
8'h30: begin outa = 10'h09d; outb = 2'b00; outc = 1'b1; end
8'h31: begin outa = 10'h28e; outb = 2'b00; outc = 1'b0; end
8'h32: begin outa = 10'h010; outb = 2'b01; outc = 1'b0; end
8'h33: begin outa = 10'h1e0; outb = 2'b10; outc = 1'b0; end
8'h34: begin outa = 10'h079; outb = 2'b01; outc = 1'b1; end
8'h35: begin outa = 10'h13e; outb = 2'b10; outc = 1'b1; end
8'h36: begin outa = 10'h282; outb = 2'b11; outc = 1'b0; end
8'h37: begin outa = 10'h21c; outb = 2'b11; outc = 1'b1; end
8'h38: begin outa = 10'h148; outb = 2'b00; outc = 1'b1; end
8'h39: begin outa = 10'h3c0; outb = 2'b10; outc = 1'b0; end
8'h3a: begin outa = 10'h176; outb = 2'b01; outc = 1'b1; end
8'h3b: begin outa = 10'h3fc; outb = 2'b10; outc = 1'b1; end
8'h3c: begin outa = 10'h295; outb = 2'b11; outc = 1'b1; end
8'h3d: begin outa = 10'h113; outb = 2'b10; outc = 1'b1; end
8'h3e: begin outa = 10'h354; outb = 2'b01; outc = 1'b1; end
8'h3f: begin outa = 10'h0db; outb = 2'b11; outc = 1'b0; end
8'h40: begin outa = 10'h238; outb = 2'b01; outc = 1'b0; end
8'h41: begin outa = 10'h12b; outb = 2'b01; outc = 1'b1; end
8'h42: begin outa = 10'h1dc; outb = 2'b10; outc = 1'b0; end
8'h43: begin outa = 10'h137; outb = 2'b01; outc = 1'b1; end
8'h44: begin outa = 10'h1e2; outb = 2'b01; outc = 1'b1; end
8'h45: begin outa = 10'h3d5; outb = 2'b11; outc = 1'b1; end
8'h46: begin outa = 10'h30c; outb = 2'b11; outc = 1'b0; end
8'h47: begin outa = 10'h298; outb = 2'b11; outc = 1'b0; end
8'h48: begin outa = 10'h080; outb = 2'b00; outc = 1'b1; end
8'h49: begin outa = 10'h35a; outb = 2'b11; outc = 1'b1; end
8'h4a: begin outa = 10'h01b; outb = 2'b00; outc = 1'b0; end
8'h4b: begin outa = 10'h0a3; outb = 2'b11; outc = 1'b0; end
8'h4c: begin outa = 10'h0b3; outb = 2'b11; outc = 1'b1; end
8'h4d: begin outa = 10'h17a; outb = 2'b00; outc = 1'b0; end
8'h4e: begin outa = 10'h3ae; outb = 2'b11; outc = 1'b0; end
8'h4f: begin outa = 10'h078; outb = 2'b11; outc = 1'b0; end
8'h50: begin outa = 10'h322; outb = 2'b00; outc = 1'b1; end
8'h51: begin outa = 10'h213; outb = 2'b11; outc = 1'b0; end
8'h52: begin outa = 10'h11a; outb = 2'b11; outc = 1'b0; end
8'h53: begin outa = 10'h1a7; outb = 2'b00; outc = 1'b0; end
8'h54: begin outa = 10'h35a; outb = 2'b00; outc = 1'b1; end
8'h55: begin outa = 10'h233; outb = 2'b00; outc = 1'b0; end
8'h56: begin outa = 10'h01d; outb = 2'b01; outc = 1'b1; end
8'h57: begin outa = 10'h2d5; outb = 2'b00; outc = 1'b0; end
8'h58: begin outa = 10'h1a0; outb = 2'b00; outc = 1'b1; end
8'h59: begin outa = 10'h3d0; outb = 2'b00; outc = 1'b1; end
8'h5a: begin outa = 10'h181; outb = 2'b01; outc = 1'b1; end
8'h5b: begin outa = 10'h219; outb = 2'b01; outc = 1'b1; end
8'h5c: begin outa = 10'h26a; outb = 2'b01; outc = 1'b1; end
8'h5d: begin outa = 10'h050; outb = 2'b10; outc = 1'b0; end
8'h5e: begin outa = 10'h189; outb = 2'b10; outc = 1'b0; end
8'h5f: begin outa = 10'h1eb; outb = 2'b01; outc = 1'b1; end
8'h60: begin outa = 10'h224; outb = 2'b00; outc = 1'b1; end
8'h61: begin outa = 10'h2fe; outb = 2'b00; outc = 1'b0; end
8'h62: begin outa = 10'h0ae; outb = 2'b00; outc = 1'b1; end
8'h63: begin outa = 10'h1cd; outb = 2'b00; outc = 1'b0; end
8'h64: begin outa = 10'h273; outb = 2'b10; outc = 1'b1; end
8'h65: begin outa = 10'h268; outb = 2'b10; outc = 1'b0; end
8'h66: begin outa = 10'h111; outb = 2'b01; outc = 1'b0; end
8'h67: begin outa = 10'h1f9; outb = 2'b00; outc = 1'b0; end
8'h68: begin outa = 10'h232; outb = 2'b00; outc = 1'b1; end
8'h69: begin outa = 10'h255; outb = 2'b11; outc = 1'b0; end
8'h6a: begin outa = 10'h34c; outb = 2'b01; outc = 1'b1; end
8'h6b: begin outa = 10'h049; outb = 2'b01; outc = 1'b1; end
8'h6c: begin outa = 10'h197; outb = 2'b11; outc = 1'b0; end
8'h6d: begin outa = 10'h0fe; outb = 2'b11; outc = 1'b0; end
8'h6e: begin outa = 10'h253; outb = 2'b01; outc = 1'b1; end
8'h6f: begin outa = 10'h2de; outb = 2'b11; outc = 1'b0; end
8'h70: begin outa = 10'h13b; outb = 2'b10; outc = 1'b1; end
8'h71: begin outa = 10'h040; outb = 2'b10; outc = 1'b0; end
8'h72: begin outa = 10'h0b4; outb = 2'b00; outc = 1'b1; end
8'h73: begin outa = 10'h233; outb = 2'b11; outc = 1'b1; end
8'h74: begin outa = 10'h198; outb = 2'b00; outc = 1'b1; end
8'h75: begin outa = 10'h018; outb = 2'b00; outc = 1'b1; end
8'h76: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end
8'h77: begin outa = 10'h134; outb = 2'b11; outc = 1'b0; end
8'h78: begin outa = 10'h1ca; outb = 2'b10; outc = 1'b0; end
8'h79: begin outa = 10'h286; outb = 2'b10; outc = 1'b1; end
8'h7a: begin outa = 10'h0e6; outb = 2'b11; outc = 1'b1; end
8'h7b: begin outa = 10'h064; outb = 2'b10; outc = 1'b1; end
8'h7c: begin outa = 10'h257; outb = 2'b00; outc = 1'b1; end
8'h7d: begin outa = 10'h31a; outb = 2'b10; outc = 1'b1; end
8'h7e: begin outa = 10'h247; outb = 2'b01; outc = 1'b0; end
8'h7f: begin outa = 10'h299; outb = 2'b00; outc = 1'b0; end
8'h80: begin outa = 10'h02c; outb = 2'b00; outc = 1'b0; end
8'h81: begin outa = 10'h2bb; outb = 2'b11; outc = 1'b0; end
8'h82: begin outa = 10'h180; outb = 2'b10; outc = 1'b0; end
8'h83: begin outa = 10'h245; outb = 2'b01; outc = 1'b1; end
8'h84: begin outa = 10'h0da; outb = 2'b10; outc = 1'b0; end
8'h85: begin outa = 10'h367; outb = 2'b10; outc = 1'b0; end
8'h86: begin outa = 10'h304; outb = 2'b01; outc = 1'b0; end
8'h87: begin outa = 10'h38b; outb = 2'b11; outc = 1'b0; end
8'h88: begin outa = 10'h09f; outb = 2'b01; outc = 1'b0; end
8'h89: begin outa = 10'h1f0; outb = 2'b10; outc = 1'b1; end
8'h8a: begin outa = 10'h281; outb = 2'b10; outc = 1'b1; end
8'h8b: begin outa = 10'h019; outb = 2'b00; outc = 1'b0; end
8'h8c: begin outa = 10'h1f2; outb = 2'b10; outc = 1'b0; end
8'h8d: begin outa = 10'h0b1; outb = 2'b01; outc = 1'b1; end
8'h8e: begin outa = 10'h058; outb = 2'b01; outc = 1'b1; end
8'h8f: begin outa = 10'h39b; outb = 2'b00; outc = 1'b1; end
8'h90: begin outa = 10'h2ec; outb = 2'b10; outc = 1'b1; end
8'h91: begin outa = 10'h250; outb = 2'b00; outc = 1'b1; end
8'h92: begin outa = 10'h3f4; outb = 2'b10; outc = 1'b1; end
8'h93: begin outa = 10'h057; outb = 2'b10; outc = 1'b1; end
8'h94: begin outa = 10'h18f; outb = 2'b01; outc = 1'b1; end
8'h95: begin outa = 10'h105; outb = 2'b01; outc = 1'b1; end
8'h96: begin outa = 10'h1ae; outb = 2'b00; outc = 1'b1; end
8'h97: begin outa = 10'h04e; outb = 2'b10; outc = 1'b0; end
8'h98: begin outa = 10'h240; outb = 2'b11; outc = 1'b0; end
8'h99: begin outa = 10'h3e4; outb = 2'b01; outc = 1'b0; end
8'h9a: begin outa = 10'h3c6; outb = 2'b01; outc = 1'b0; end
8'h9b: begin outa = 10'h109; outb = 2'b00; outc = 1'b1; end
8'h9c: begin outa = 10'h073; outb = 2'b10; outc = 1'b1; end
8'h9d: begin outa = 10'h19f; outb = 2'b01; outc = 1'b0; end
8'h9e: begin outa = 10'h3b8; outb = 2'b01; outc = 1'b0; end
8'h9f: begin outa = 10'h00e; outb = 2'b00; outc = 1'b1; end
8'ha0: begin outa = 10'h1b3; outb = 2'b11; outc = 1'b1; end
8'ha1: begin outa = 10'h2bd; outb = 2'b11; outc = 1'b0; end
8'ha2: begin outa = 10'h324; outb = 2'b00; outc = 1'b1; end
8'ha3: begin outa = 10'h343; outb = 2'b10; outc = 1'b0; end
8'ha4: begin outa = 10'h1c9; outb = 2'b01; outc = 1'b0; end
8'ha5: begin outa = 10'h185; outb = 2'b00; outc = 1'b1; end
8'ha6: begin outa = 10'h37a; outb = 2'b00; outc = 1'b1; end
8'ha7: begin outa = 10'h0e0; outb = 2'b01; outc = 1'b1; end
8'ha8: begin outa = 10'h0a3; outb = 2'b10; outc = 1'b0; end
8'ha9: begin outa = 10'h019; outb = 2'b11; outc = 1'b0; end
8'haa: begin outa = 10'h099; outb = 2'b00; outc = 1'b1; end
8'hab: begin outa = 10'h376; outb = 2'b01; outc = 1'b1; end
8'hac: begin outa = 10'h077; outb = 2'b00; outc = 1'b1; end
8'had: begin outa = 10'h2b1; outb = 2'b11; outc = 1'b1; end
8'hae: begin outa = 10'h27f; outb = 2'b00; outc = 1'b0; end
8'haf: begin outa = 10'h265; outb = 2'b11; outc = 1'b0; end
8'hb0: begin outa = 10'h156; outb = 2'b10; outc = 1'b1; end
8'hb1: begin outa = 10'h1ce; outb = 2'b00; outc = 1'b0; end
8'hb2: begin outa = 10'h008; outb = 2'b01; outc = 1'b0; end
8'hb3: begin outa = 10'h12e; outb = 2'b11; outc = 1'b1; end
8'hb4: begin outa = 10'h199; outb = 2'b11; outc = 1'b0; end
8'hb5: begin outa = 10'h330; outb = 2'b10; outc = 1'b0; end
8'hb6: begin outa = 10'h1ab; outb = 2'b01; outc = 1'b1; end
8'hb7: begin outa = 10'h3bd; outb = 2'b00; outc = 1'b0; end
8'hb8: begin outa = 10'h0ca; outb = 2'b10; outc = 1'b0; end
8'hb9: begin outa = 10'h367; outb = 2'b00; outc = 1'b0; end
8'hba: begin outa = 10'h334; outb = 2'b00; outc = 1'b0; end
8'hbb: begin outa = 10'h040; outb = 2'b00; outc = 1'b1; end
8'hbc: begin outa = 10'h1a7; outb = 2'b10; outc = 1'b1; end
8'hbd: begin outa = 10'h036; outb = 2'b11; outc = 1'b1; end
8'hbe: begin outa = 10'h223; outb = 2'b11; outc = 1'b1; end
8'hbf: begin outa = 10'h075; outb = 2'b01; outc = 1'b0; end
8'hc0: begin outa = 10'h3c4; outb = 2'b00; outc = 1'b1; end
8'hc1: begin outa = 10'h2cc; outb = 2'b01; outc = 1'b0; end
8'hc2: begin outa = 10'h123; outb = 2'b01; outc = 1'b0; end
8'hc3: begin outa = 10'h3fd; outb = 2'b01; outc = 1'b1; end
8'hc4: begin outa = 10'h11e; outb = 2'b00; outc = 1'b0; end
8'hc5: begin outa = 10'h27c; outb = 2'b11; outc = 1'b1; end
8'hc6: begin outa = 10'h1e2; outb = 2'b11; outc = 1'b0; end
8'hc7: begin outa = 10'h377; outb = 2'b11; outc = 1'b0; end
8'hc8: begin outa = 10'h33a; outb = 2'b11; outc = 1'b0; end
8'hc9: begin outa = 10'h32d; outb = 2'b11; outc = 1'b1; end
8'hca: begin outa = 10'h014; outb = 2'b11; outc = 1'b0; end
8'hcb: begin outa = 10'h332; outb = 2'b10; outc = 1'b0; end
8'hcc: begin outa = 10'h359; outb = 2'b00; outc = 1'b0; end
8'hcd: begin outa = 10'h0a4; outb = 2'b10; outc = 1'b1; end
8'hce: begin outa = 10'h348; outb = 2'b00; outc = 1'b1; end
8'hcf: begin outa = 10'h04b; outb = 2'b11; outc = 1'b1; end
8'hd0: begin outa = 10'h147; outb = 2'b10; outc = 1'b1; end
8'hd1: begin outa = 10'h026; outb = 2'b00; outc = 1'b1; end
8'hd2: begin outa = 10'h103; outb = 2'b00; outc = 1'b0; end
8'hd3: begin outa = 10'h106; outb = 2'b00; outc = 1'b1; end
8'hd4: begin outa = 10'h35a; outb = 2'b00; outc = 1'b0; end
8'hd5: begin outa = 10'h254; outb = 2'b01; outc = 1'b0; end
8'hd6: begin outa = 10'h0cd; outb = 2'b01; outc = 1'b0; end
8'hd7: begin outa = 10'h17c; outb = 2'b11; outc = 1'b1; end
8'hd8: begin outa = 10'h37e; outb = 2'b10; outc = 1'b1; end
8'hd9: begin outa = 10'h0a9; outb = 2'b11; outc = 1'b1; end
8'hda: begin outa = 10'h0fe; outb = 2'b01; outc = 1'b0; end
8'hdb: begin outa = 10'h3c0; outb = 2'b11; outc = 1'b1; end
8'hdc: begin outa = 10'h1d9; outb = 2'b10; outc = 1'b1; end
8'hdd: begin outa = 10'h10e; outb = 2'b00; outc = 1'b1; end
8'hde: begin outa = 10'h394; outb = 2'b01; outc = 1'b0; end
8'hdf: begin outa = 10'h316; outb = 2'b01; outc = 1'b0; end
8'he0: begin outa = 10'h05b; outb = 2'b11; outc = 1'b0; end
8'he1: begin outa = 10'h126; outb = 2'b01; outc = 1'b1; end
8'he2: begin outa = 10'h369; outb = 2'b11; outc = 1'b0; end
8'he3: begin outa = 10'h291; outb = 2'b10; outc = 1'b1; end
8'he4: begin outa = 10'h2ca; outb = 2'b00; outc = 1'b1; end
8'he5: begin outa = 10'h25b; outb = 2'b01; outc = 1'b1; end
8'he6: begin outa = 10'h106; outb = 2'b00; outc = 1'b0; end
8'he7: begin outa = 10'h172; outb = 2'b11; outc = 1'b1; end
8'he8: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end
8'he9: begin outa = 10'h2d3; outb = 2'b11; outc = 1'b1; end
8'hea: begin outa = 10'h182; outb = 2'b00; outc = 1'b0; end
8'heb: begin outa = 10'h327; outb = 2'b00; outc = 1'b1; end
8'hec: begin outa = 10'h1d0; outb = 2'b10; outc = 1'b0; end
8'hed: begin outa = 10'h204; outb = 2'b00; outc = 1'b1; end
8'hee: begin outa = 10'h11f; outb = 2'b00; outc = 1'b1; end
8'hef: begin outa = 10'h365; outb = 2'b11; outc = 1'b1; end
8'hf0: begin outa = 10'h2c2; outb = 2'b01; outc = 1'b1; end
8'hf1: begin outa = 10'h2b5; outb = 2'b10; outc = 1'b0; end
8'hf2: begin outa = 10'h1f8; outb = 2'b10; outc = 1'b1; end
8'hf3: begin outa = 10'h2a7; outb = 2'b01; outc = 1'b1; end
8'hf4: begin outa = 10'h1be; outb = 2'b10; outc = 1'b1; end
8'hf5: begin outa = 10'h25e; outb = 2'b10; outc = 1'b1; end
8'hf6: begin outa = 10'h032; outb = 2'b10; outc = 1'b0; end
8'hf7: begin outa = 10'h2ef; outb = 2'b00; outc = 1'b0; end
8'hf8: begin outa = 10'h02f; outb = 2'b00; outc = 1'b1; end
8'hf9: begin outa = 10'h201; outb = 2'b10; outc = 1'b0; end
8'hfa: begin outa = 10'h054; outb = 2'b01; outc = 1'b1; end
8'hfb: begin outa = 10'h013; outb = 2'b10; outc = 1'b0; end
8'hfc: begin outa = 10'h249; outb = 2'b01; outc = 1'b0; end
8'hfd: begin outa = 10'h09a; outb = 2'b10; outc = 1'b0; end
8'hfe: begin outa = 10'h012; outb = 2'b00; outc = 1'b0; end
8'hff: begin outa = 10'h114; outb = 2'b10; outc = 1'b1; end
endcase
end
endmodule
|
module mem_window (
clk,
reset,
// Memory slave port
s1_address,
s1_read,
s1_readdata,
s1_readdatavalid,
s1_write,
s1_writedata,
s1_burstcount,
s1_byteenable,
s1_waitrequest,
// Configuration register slave port
cra_write,
cra_writedata,
cra_byteenable,
// Bridged master port to memory
m1_address,
m1_read,
m1_readdata,
m1_readdatavalid,
m1_write,
m1_writedata,
m1_burstcount,
m1_byteenable,
m1_waitrequest
);
parameter PAGE_ADDRESS_WIDTH = 20;
parameter MEM_ADDRESS_WIDTH = 32;
parameter NUM_BYTES = 32;
parameter BURSTCOUNT_WIDTH = 1;
parameter CRA_BITWIDTH = 32;
localparam ADDRESS_SHIFT = $clog2(NUM_BYTES);
localparam PAGE_ID_WIDTH = MEM_ADDRESS_WIDTH - PAGE_ADDRESS_WIDTH - ADDRESS_SHIFT;
localparam DATA_WIDTH = NUM_BYTES * 8;
input clk;
input reset;
// Memory slave port
input [PAGE_ADDRESS_WIDTH-1:0] s1_address;
input s1_read;
output [DATA_WIDTH-1:0] s1_readdata;
output s1_readdatavalid;
input s1_write;
input [DATA_WIDTH-1:0] s1_writedata;
input [BURSTCOUNT_WIDTH-1:0] s1_burstcount;
input [NUM_BYTES-1:0] s1_byteenable;
output s1_waitrequest;
// Bridged master port to memory
output [MEM_ADDRESS_WIDTH-1:0] m1_address;
output m1_read;
input [DATA_WIDTH-1:0] m1_readdata;
input m1_readdatavalid;
output m1_write;
output [DATA_WIDTH-1:0] m1_writedata;
output [BURSTCOUNT_WIDTH-1:0] m1_burstcount;
output [NUM_BYTES-1:0] m1_byteenable;
input m1_waitrequest;
// CRA slave
input cra_write;
input [CRA_BITWIDTH-1:0] cra_writedata;
input [CRA_BITWIDTH/8-1:0] cra_byteenable;
// Architecture
// CRA slave allows the master to change the active page
reg [PAGE_ID_WIDTH-1:0] page_id;
reg [CRA_BITWIDTH-1:0] cra_writemask;
integer i;
always@*
for (i=0; i<CRA_BITWIDTH; i=i+1)
cra_writemask[i] = cra_byteenable[i/8] & cra_write;
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
page_id <= {PAGE_ID_WIDTH{1'b0}};
else
page_id <= (cra_writedata & cra_writemask) | (page_id & ~cra_writemask);
end
// The s1 port bridges to the m1 port - with the page ID tacked on to the address
assign m1_address = {page_id, s1_address, {ADDRESS_SHIFT{1'b0}}};
assign m1_read = s1_read;
assign s1_readdata = m1_readdata;
assign s1_readdatavalid = m1_readdatavalid;
assign m1_write = s1_write;
assign m1_writedata = s1_writedata;
assign m1_burstcount = s1_burstcount;
assign m1_byteenable = s1_byteenable;
assign s1_waitrequest = m1_waitrequest;
endmodule
|
module mem_window (
clk,
reset,
// Memory slave port
s1_address,
s1_read,
s1_readdata,
s1_readdatavalid,
s1_write,
s1_writedata,
s1_burstcount,
s1_byteenable,
s1_waitrequest,
// Configuration register slave port
cra_write,
cra_writedata,
cra_byteenable,
// Bridged master port to memory
m1_address,
m1_read,
m1_readdata,
m1_readdatavalid,
m1_write,
m1_writedata,
m1_burstcount,
m1_byteenable,
m1_waitrequest
);
parameter PAGE_ADDRESS_WIDTH = 20;
parameter MEM_ADDRESS_WIDTH = 32;
parameter NUM_BYTES = 32;
parameter BURSTCOUNT_WIDTH = 1;
parameter CRA_BITWIDTH = 32;
localparam ADDRESS_SHIFT = $clog2(NUM_BYTES);
localparam PAGE_ID_WIDTH = MEM_ADDRESS_WIDTH - PAGE_ADDRESS_WIDTH - ADDRESS_SHIFT;
localparam DATA_WIDTH = NUM_BYTES * 8;
input clk;
input reset;
// Memory slave port
input [PAGE_ADDRESS_WIDTH-1:0] s1_address;
input s1_read;
output [DATA_WIDTH-1:0] s1_readdata;
output s1_readdatavalid;
input s1_write;
input [DATA_WIDTH-1:0] s1_writedata;
input [BURSTCOUNT_WIDTH-1:0] s1_burstcount;
input [NUM_BYTES-1:0] s1_byteenable;
output s1_waitrequest;
// Bridged master port to memory
output [MEM_ADDRESS_WIDTH-1:0] m1_address;
output m1_read;
input [DATA_WIDTH-1:0] m1_readdata;
input m1_readdatavalid;
output m1_write;
output [DATA_WIDTH-1:0] m1_writedata;
output [BURSTCOUNT_WIDTH-1:0] m1_burstcount;
output [NUM_BYTES-1:0] m1_byteenable;
input m1_waitrequest;
// CRA slave
input cra_write;
input [CRA_BITWIDTH-1:0] cra_writedata;
input [CRA_BITWIDTH/8-1:0] cra_byteenable;
// Architecture
// CRA slave allows the master to change the active page
reg [PAGE_ID_WIDTH-1:0] page_id;
reg [CRA_BITWIDTH-1:0] cra_writemask;
integer i;
always@*
for (i=0; i<CRA_BITWIDTH; i=i+1)
cra_writemask[i] = cra_byteenable[i/8] & cra_write;
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
page_id <= {PAGE_ID_WIDTH{1'b0}};
else
page_id <= (cra_writedata & cra_writemask) | (page_id & ~cra_writemask);
end
// The s1 port bridges to the m1 port - with the page ID tacked on to the address
assign m1_address = {page_id, s1_address, {ADDRESS_SHIFT{1'b0}}};
assign m1_read = s1_read;
assign s1_readdata = m1_readdata;
assign s1_readdatavalid = m1_readdatavalid;
assign m1_write = s1_write;
assign m1_writedata = s1_writedata;
assign m1_burstcount = s1_burstcount;
assign m1_byteenable = s1_byteenable;
assign s1_waitrequest = m1_waitrequest;
endmodule
|
module export_master (
clk,
reset,
address,
read,
readdata,
readdatavalid,
write,
writedata,
burstcount,
byteenable,
waitrequest,
burstbegin,
export_address,
export_read,
export_readdata,
export_readdatavalid,
export_write,
export_writedata,
export_burstcount,
export_burstbegin,
export_byteenable,
export_waitrequest,
interrupt,
export_interrupt
);
parameter NUM_BYTES = 4;
parameter BYTE_ADDRESS_WIDTH = 32;
parameter WORD_ADDRESS_WIDTH = 32;
parameter BURSTCOUNT_WIDTH = 1;
localparam DATA_WIDTH = NUM_BYTES * 8;
localparam ADDRESS_SHIFT = BYTE_ADDRESS_WIDTH - WORD_ADDRESS_WIDTH;
input clk;
input reset;
input [WORD_ADDRESS_WIDTH-1:0] address;
input read;
output [DATA_WIDTH-1:0] readdata;
output readdatavalid;
input write;
input [DATA_WIDTH-1:0] writedata;
input [BURSTCOUNT_WIDTH-1:0] burstcount;
input burstbegin;
input [NUM_BYTES-1:0] byteenable;
output waitrequest;
output interrupt;
output [BYTE_ADDRESS_WIDTH-1:0] export_address;
output export_read;
input [DATA_WIDTH-1:0] export_readdata;
input export_readdatavalid;
output export_write;
output [DATA_WIDTH-1:0] export_writedata;
output [BURSTCOUNT_WIDTH-1:0] export_burstcount;
output export_burstbegin;
output [NUM_BYTES-1:0] export_byteenable;
input export_waitrequest;
input export_interrupt;
assign export_address = address << ADDRESS_SHIFT;
assign export_read = read;
assign readdata = export_readdata;
assign readdatavalid = export_readdatavalid;
assign export_write = write;
assign export_writedata = writedata;
assign export_burstcount = burstcount;
assign export_burstbegin = burstbegin;
assign export_byteenable = byteenable;
assign interrupt = export_interrupt;
assign waitrequest = export_waitrequest;
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 08/25/2009
Version 1.0
This block takes the length and forms the appropriate burst count.
Whenever one of the short access enables are asserted this block
will post a burst of one. Posting a burst of one isn't necessary
but it will make it possible to add byte enable support to the
read master at a later date.
Revision History:
1.0 First version
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module read_burst_control (
address,
length,
maximum_burst_count,
short_first_access_enable,
short_last_access_enable,
short_first_and_last_access_enable,
burst_count
);
parameter BURST_ENABLE = 1; // set to 0 to hardwire the address and write signals straight out
parameter BURST_COUNT_WIDTH = 3;
parameter WORD_SIZE_LOG2 = 2; // log2(DATA WIDTH/8)
parameter ADDRESS_WIDTH = 32;
parameter LENGTH_WIDTH = 32;
parameter BURST_WRAPPING_SUPPORT = 1; // set 1 for on, set 0 for off. This parameter can't be enabled when hte master supports programmable burst.
localparam BURST_OFFSET_WIDTH = (BURST_COUNT_WIDTH == 1)? 1: (BURST_COUNT_WIDTH-1);
input [ADDRESS_WIDTH-1:0] address;
input [LENGTH_WIDTH-1:0] length;
input [BURST_COUNT_WIDTH-1:0] maximum_burst_count; // will be either a hardcoded input or programmable
input short_first_access_enable;
input short_last_access_enable;
input short_first_and_last_access_enable;
output wire [BURST_COUNT_WIDTH-1:0] burst_count;
wire [BURST_COUNT_WIDTH-1:0] posted_burst; // when the burst statemachine is used this will be the burst count posted to the fabric
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count; // muxes posted_burst, posted_burst_d1, and '1' since we need to be able to post bursts of '1' for short accesses
wire burst_of_one_enable; // asserted when partial word accesses are occuring
wire short_burst_enable;
wire [BURST_OFFSET_WIDTH-1:0] burst_offset;
assign burst_offset = address[BURST_OFFSET_WIDTH+WORD_SIZE_LOG2-1:WORD_SIZE_LOG2];
// for unaligned or partial transfers we must use a burst length of 1 so that
assign burst_of_one_enable = (short_first_access_enable == 1) | (short_last_access_enable == 1) | (short_first_and_last_access_enable == 1) | // when performing partial accesses use a burst length of 1
((BURST_WRAPPING_SUPPORT == 1) & (burst_offset != 0)); // when the burst boundary offset is non-zero then the master isn't in burst alignment yet as so a burst of 1 needs to be posted
assign short_burst_enable = ((length >> WORD_SIZE_LOG2) < maximum_burst_count);
always @ (maximum_burst_count or length or short_burst_enable or burst_of_one_enable)
begin
case ({short_burst_enable, burst_of_one_enable})
2'b00 : internal_burst_count = maximum_burst_count;
2'b01 : internal_burst_count = 1; // this is when the master starts unaligned
2'b10 : internal_burst_count = ((length >> WORD_SIZE_LOG2) & {(BURST_COUNT_WIDTH-1){1'b1}}); // this could be followed by a burst of 1 if there are a few bytes leftover
2'b11 : internal_burst_count = 1; // burst of 1 needs to win, this is when the master starts with very little data to transfer
endcase
end
generate
if (BURST_ENABLE == 1)
begin
assign burst_count = internal_burst_count;
end
else
begin
assign burst_count = 1; // this will be stubbed at the top level but will be used for the address and pending reads incrementing
end
endgenerate
endmodule
|
module channel_demux
#(parameter NUM_CHAN = 2) ( //usb Side
input [31:0]usbdata_final,
input WR_final,
// TX Side
input reset,
input txclk,
output reg [NUM_CHAN:0] WR_channel,
output reg [31:0] ram_data,
output reg [NUM_CHAN:0] WR_done_channel );
/* Parse header and forward to ram */
reg [2:0]reader_state;
reg [4:0]channel ;
reg [6:0]read_length ;
// States
parameter IDLE = 3'd0;
parameter HEADER = 3'd1;
parameter WAIT = 3'd2;
parameter FORWARD = 3'd3;
`define CHANNEL 20:16
`define PKT_SIZE 127
wire [4:0] true_channel;
assign true_channel = (usbdata_final[`CHANNEL] == 5'h1f) ?
NUM_CHAN : (usbdata_final[`CHANNEL]);
always @(posedge txclk)
begin
if (reset)
begin
reader_state <= IDLE;
WR_channel <= 0;
WR_done_channel <= 0;
end
else
case (reader_state)
IDLE: begin
if (WR_final)
reader_state <= HEADER;
end
// Store channel and forware header
HEADER: begin
channel <= true_channel;
WR_channel[true_channel] <= 1;
ram_data <= usbdata_final;
read_length <= 7'd0 ;
reader_state <= WAIT;
end
WAIT: begin
WR_channel[channel] <= 0;
if (read_length == `PKT_SIZE)
reader_state <= IDLE;
else if (WR_final)
reader_state <= FORWARD;
end
FORWARD: begin
WR_channel[channel] <= 1;
ram_data <= usbdata_final;
read_length <= read_length + 7'd1;
reader_state <= WAIT;
end
default:
begin
//error handling
reader_state <= IDLE;
end
endcase
end
endmodule
|
module channel_demux
#(parameter NUM_CHAN = 2) ( //usb Side
input [31:0]usbdata_final,
input WR_final,
// TX Side
input reset,
input txclk,
output reg [NUM_CHAN:0] WR_channel,
output reg [31:0] ram_data,
output reg [NUM_CHAN:0] WR_done_channel );
/* Parse header and forward to ram */
reg [2:0]reader_state;
reg [4:0]channel ;
reg [6:0]read_length ;
// States
parameter IDLE = 3'd0;
parameter HEADER = 3'd1;
parameter WAIT = 3'd2;
parameter FORWARD = 3'd3;
`define CHANNEL 20:16
`define PKT_SIZE 127
wire [4:0] true_channel;
assign true_channel = (usbdata_final[`CHANNEL] == 5'h1f) ?
NUM_CHAN : (usbdata_final[`CHANNEL]);
always @(posedge txclk)
begin
if (reset)
begin
reader_state <= IDLE;
WR_channel <= 0;
WR_done_channel <= 0;
end
else
case (reader_state)
IDLE: begin
if (WR_final)
reader_state <= HEADER;
end
// Store channel and forware header
HEADER: begin
channel <= true_channel;
WR_channel[true_channel] <= 1;
ram_data <= usbdata_final;
read_length <= 7'd0 ;
reader_state <= WAIT;
end
WAIT: begin
WR_channel[channel] <= 0;
if (read_length == `PKT_SIZE)
reader_state <= IDLE;
else if (WR_final)
reader_state <= FORWARD;
end
FORWARD: begin
WR_channel[channel] <= 1;
ram_data <= usbdata_final;
read_length <= read_length + 7'd1;
reader_state <= WAIT;
end
default:
begin
//error handling
reader_state <= IDLE;
end
endcase
end
endmodule
|
module channel_demux
#(parameter NUM_CHAN = 2) ( //usb Side
input [31:0]usbdata_final,
input WR_final,
// TX Side
input reset,
input txclk,
output reg [NUM_CHAN:0] WR_channel,
output reg [31:0] ram_data,
output reg [NUM_CHAN:0] WR_done_channel );
/* Parse header and forward to ram */
reg [2:0]reader_state;
reg [4:0]channel ;
reg [6:0]read_length ;
// States
parameter IDLE = 3'd0;
parameter HEADER = 3'd1;
parameter WAIT = 3'd2;
parameter FORWARD = 3'd3;
`define CHANNEL 20:16
`define PKT_SIZE 127
wire [4:0] true_channel;
assign true_channel = (usbdata_final[`CHANNEL] == 5'h1f) ?
NUM_CHAN : (usbdata_final[`CHANNEL]);
always @(posedge txclk)
begin
if (reset)
begin
reader_state <= IDLE;
WR_channel <= 0;
WR_done_channel <= 0;
end
else
case (reader_state)
IDLE: begin
if (WR_final)
reader_state <= HEADER;
end
// Store channel and forware header
HEADER: begin
channel <= true_channel;
WR_channel[true_channel] <= 1;
ram_data <= usbdata_final;
read_length <= 7'd0 ;
reader_state <= WAIT;
end
WAIT: begin
WR_channel[channel] <= 0;
if (read_length == `PKT_SIZE)
reader_state <= IDLE;
else if (WR_final)
reader_state <= FORWARD;
end
FORWARD: begin
WR_channel[channel] <= 1;
ram_data <= usbdata_final;
read_length <= read_length + 7'd1;
reader_state <= WAIT;
end
default:
begin
//error handling
reader_state <= IDLE;
end
endcase
end
endmodule
|
module channel_demux
#(parameter NUM_CHAN = 2) ( //usb Side
input [31:0]usbdata_final,
input WR_final,
// TX Side
input reset,
input txclk,
output reg [NUM_CHAN:0] WR_channel,
output reg [31:0] ram_data,
output reg [NUM_CHAN:0] WR_done_channel );
/* Parse header and forward to ram */
reg [2:0]reader_state;
reg [4:0]channel ;
reg [6:0]read_length ;
// States
parameter IDLE = 3'd0;
parameter HEADER = 3'd1;
parameter WAIT = 3'd2;
parameter FORWARD = 3'd3;
`define CHANNEL 20:16
`define PKT_SIZE 127
wire [4:0] true_channel;
assign true_channel = (usbdata_final[`CHANNEL] == 5'h1f) ?
NUM_CHAN : (usbdata_final[`CHANNEL]);
always @(posedge txclk)
begin
if (reset)
begin
reader_state <= IDLE;
WR_channel <= 0;
WR_done_channel <= 0;
end
else
case (reader_state)
IDLE: begin
if (WR_final)
reader_state <= HEADER;
end
// Store channel and forware header
HEADER: begin
channel <= true_channel;
WR_channel[true_channel] <= 1;
ram_data <= usbdata_final;
read_length <= 7'd0 ;
reader_state <= WAIT;
end
WAIT: begin
WR_channel[channel] <= 0;
if (read_length == `PKT_SIZE)
reader_state <= IDLE;
else if (WR_final)
reader_state <= FORWARD;
end
FORWARD: begin
WR_channel[channel] <= 1;
ram_data <= usbdata_final;
read_length <= read_length + 7'd1;
reader_state <= WAIT;
end
default:
begin
//error handling
reader_state <= IDLE;
end
endcase
end
endmodule
|
// Model of FIFO in Altera
module fifo_1c_1k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 32;
parameter depth = 1024;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [31:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [31:0] q;
output rdfull;
output rdempty;
output [9:0] rdusedw;
output wrfull;
output wrempty;
output [9:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [7:0] rdptr;
reg [7:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
reg [9:0] rdusedw;
reg [9:0] wrusedw;
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
assign wrempty = (wrusedw == 0);
assign wrfull = (wrusedw == depth-1);
assign rdempty = (rdusedw == 0);
assign rdfull = (rdusedw == depth-1);
endmodule // fifo_1c_1k
|
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module pll (
inclk0,
c0);
input inclk0;
output c0;
endmodule
|
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module pll (
inclk0,
c0);
input inclk0;
output c0;
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module rx_chain_dual
(input clock,
input clock_2x,
input reset,
input enable,
input wire [7:0] decim_rate,
input sample_strobe,
input decimator_strobe,
input wire [31:0] freq0,
input wire [15:0] i_in0,
input wire [15:0] q_in0,
output wire [15:0] i_out0,
output wire [15:0] q_out0,
input wire [31:0] freq1,
input wire [15:0] i_in1,
input wire [15:0] q_in1,
output wire [15:0] i_out1,
output wire [15:0] q_out1
);
wire [15:0] phase;
wire [15:0] bb_i, bb_q;
wire [15:0] i_in, q_in;
wire [31:0] phase0;
wire [31:0] phase1;
reg [15:0] bb_i0, bb_q0;
reg [15:0] bb_i1, bb_q1;
// We want to time-share the CORDIC by double-clocking it
phase_acc rx_phase_acc_0
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq0),.phase(phase0) );
phase_acc rx_phase_acc_1
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq1),.phase(phase1) );
assign phase = clock ? phase0[31:16] : phase1[31:16];
assign i_in = clock ? i_in0 : i_in1;
assign q_in = clock ? q_in0 : q_in1;
// This appears reversed because of the number of CORDIC stages
always @(posedge clock_2x)
if(clock)
begin
bb_i1 <= #1 bb_i;
bb_q1 <= #1 bb_q;
end
else
begin
bb_i0 <= #1 bb_i;
bb_q0 <= #1 bb_q;
end
cordic rx_cordic
( .clock(clock_2x),.reset(reset),.enable(enable),
.xi(i_in),.yi(q_in),.zi(phase),
.xo(bb_i),.yo(bb_q),.zo() );
cic_decim cic_decim_i_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i0),.signal_out(i_out0) );
cic_decim cic_decim_q_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q0),.signal_out(q_out0) );
cic_decim cic_decim_i_1
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i1),.signal_out(i_out1) );
cic_decim cic_decim_q_1
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q1),.signal_out(q_out1) );
endmodule // rx_chain
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Basic Phase accumulator for DDS
module phase_acc (clk,reset,enable,strobe,serial_addr,serial_data,serial_strobe,phase);
parameter FREQADDR = 0;
parameter PHASEADDR = 0;
parameter resolution = 32;
input clk, reset, enable, strobe;
input [6:0] serial_addr;
input [31:0] serial_data;
input serial_strobe;
output reg [resolution-1:0] phase;
wire [resolution-1:0] freq;
setting_reg #(FREQADDR) sr_rxfreq0(.clock(clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(freq));
always @(posedge clk)
if(reset)
phase <= #1 32'b0;
else if(serial_strobe & (serial_addr == PHASEADDR))
phase <= #1 serial_data;
else if(enable & strobe)
phase <= #1 phase + freq;
endmodule // phase_acc
|
// megafunction wizard: %LPM_BUSTRI%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_bustri
// ============================================================
// File Name: bustri.v
// Megafunction Name(s):
// lpm_bustri
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module bustri (
data,
enabledt,
tridata);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
lpm_bustri lpm_bustri_component (
.tridata (tridata),
.enabledt (enabledt),
.data (data));
defparam
lpm_bustri_component.lpm_width = 16,
lpm_bustri_component.lpm_type = "LPM_BUSTRI";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: BiDir NUMERIC "0"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
// Retrieval info: USED_PORT: tridata 0 0 16 0 BIDIR NODEFVAL tridata[15..0]
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
// Retrieval info: CONNECT: tridata 0 0 16 0 @tridata 0 0 16 0
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
// megafunction wizard: %LPM_BUSTRI%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_bustri
// ============================================================
// File Name: bustri.v
// Megafunction Name(s):
// lpm_bustri
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module bustri (
data,
enabledt,
tridata);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
lpm_bustri lpm_bustri_component (
.tridata (tridata),
.enabledt (enabledt),
.data (data));
defparam
lpm_bustri_component.lpm_width = 16,
lpm_bustri_component.lpm_type = "LPM_BUSTRI";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: BiDir NUMERIC "0"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
// Retrieval info: USED_PORT: tridata 0 0 16 0 BIDIR NODEFVAL tridata[15..0]
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
// Retrieval info: CONNECT: tridata 0 0 16 0 @tridata 0 0 16 0
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
// megafunction wizard: %LPM_ADD_SUB%CBX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_add_sub
// ============================================================
// File Name: sub32.v
// Megafunction Name(s):
// lpm_add_sub
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_DIRECTION=SUB LPM_PIPELINE=1 LPM_WIDTH=32 aclr clken clock dataa datab result
//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END
//synthesis_resources = lut 32
module sub32_add_sub_cqa
(
aclr,
clken,
clock,
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clken;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
wire [0:0] wire_add_sub_cella_0cout;
wire [0:0] wire_add_sub_cella_1cout;
wire [0:0] wire_add_sub_cella_2cout;
wire [0:0] wire_add_sub_cella_3cout;
wire [0:0] wire_add_sub_cella_4cout;
wire [0:0] wire_add_sub_cella_5cout;
wire [0:0] wire_add_sub_cella_6cout;
wire [0:0] wire_add_sub_cella_7cout;
wire [0:0] wire_add_sub_cella_8cout;
wire [0:0] wire_add_sub_cella_9cout;
wire [0:0] wire_add_sub_cella_10cout;
wire [0:0] wire_add_sub_cella_11cout;
wire [0:0] wire_add_sub_cella_12cout;
wire [0:0] wire_add_sub_cella_13cout;
wire [0:0] wire_add_sub_cella_14cout;
wire [0:0] wire_add_sub_cella_15cout;
wire [0:0] wire_add_sub_cella_16cout;
wire [0:0] wire_add_sub_cella_17cout;
wire [0:0] wire_add_sub_cella_18cout;
wire [0:0] wire_add_sub_cella_19cout;
wire [0:0] wire_add_sub_cella_20cout;
wire [0:0] wire_add_sub_cella_21cout;
wire [0:0] wire_add_sub_cella_22cout;
wire [0:0] wire_add_sub_cella_23cout;
wire [0:0] wire_add_sub_cella_24cout;
wire [0:0] wire_add_sub_cella_25cout;
wire [0:0] wire_add_sub_cella_26cout;
wire [0:0] wire_add_sub_cella_27cout;
wire [0:0] wire_add_sub_cella_28cout;
wire [0:0] wire_add_sub_cella_29cout;
wire [0:0] wire_add_sub_cella_30cout;
wire [31:0] wire_add_sub_cella_dataa;
wire [31:0] wire_add_sub_cella_datab;
wire [31:0] wire_add_sub_cella_regout;
stratix_lcell add_sub_cella_0
(
.aclr(aclr),
.cin(1'b1),
.clk(clock),
.cout(wire_add_sub_cella_0cout[0:0]),
.dataa(wire_add_sub_cella_dataa[0:0]),
.datab(wire_add_sub_cella_datab[0:0]),
.ena(clken),
.regout(wire_add_sub_cella_regout[0:0]));
defparam
add_sub_cella_0.cin_used = "true",
add_sub_cella_0.lut_mask = "69b2",
add_sub_cella_0.operation_mode = "arithmetic",
add_sub_cella_0.sum_lutc_input = "cin",
add_sub_cella_0.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_1
(
.aclr(aclr),
.cin(wire_add_sub_cella_0cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_1cout[0:0]),
.dataa(wire_add_sub_cella_dataa[1:1]),
.datab(wire_add_sub_cella_datab[1:1]),
.ena(clken),
.regout(wire_add_sub_cella_regout[1:1]));
defparam
add_sub_cella_1.cin_used = "true",
add_sub_cella_1.lut_mask = "69b2",
add_sub_cella_1.operation_mode = "arithmetic",
add_sub_cella_1.sum_lutc_input = "cin",
add_sub_cella_1.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_2
(
.aclr(aclr),
.cin(wire_add_sub_cella_1cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_2cout[0:0]),
.dataa(wire_add_sub_cella_dataa[2:2]),
.datab(wire_add_sub_cella_datab[2:2]),
.ena(clken),
.regout(wire_add_sub_cella_regout[2:2]));
defparam
add_sub_cella_2.cin_used = "true",
add_sub_cella_2.lut_mask = "69b2",
add_sub_cella_2.operation_mode = "arithmetic",
add_sub_cella_2.sum_lutc_input = "cin",
add_sub_cella_2.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_3
(
.aclr(aclr),
.cin(wire_add_sub_cella_2cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_3cout[0:0]),
.dataa(wire_add_sub_cella_dataa[3:3]),
.datab(wire_add_sub_cella_datab[3:3]),
.ena(clken),
.regout(wire_add_sub_cella_regout[3:3]));
defparam
add_sub_cella_3.cin_used = "true",
add_sub_cella_3.lut_mask = "69b2",
add_sub_cella_3.operation_mode = "arithmetic",
add_sub_cella_3.sum_lutc_input = "cin",
add_sub_cella_3.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_4
(
.aclr(aclr),
.cin(wire_add_sub_cella_3cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_4cout[0:0]),
.dataa(wire_add_sub_cella_dataa[4:4]),
.datab(wire_add_sub_cella_datab[4:4]),
.ena(clken),
.regout(wire_add_sub_cella_regout[4:4]));
defparam
add_sub_cella_4.cin_used = "true",
add_sub_cella_4.lut_mask = "69b2",
add_sub_cella_4.operation_mode = "arithmetic",
add_sub_cella_4.sum_lutc_input = "cin",
add_sub_cella_4.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_5
(
.aclr(aclr),
.cin(wire_add_sub_cella_4cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_5cout[0:0]),
.dataa(wire_add_sub_cella_dataa[5:5]),
.datab(wire_add_sub_cella_datab[5:5]),
.ena(clken),
.regout(wire_add_sub_cella_regout[5:5]));
defparam
add_sub_cella_5.cin_used = "true",
add_sub_cella_5.lut_mask = "69b2",
add_sub_cella_5.operation_mode = "arithmetic",
add_sub_cella_5.sum_lutc_input = "cin",
add_sub_cella_5.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_6
(
.aclr(aclr),
.cin(wire_add_sub_cella_5cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_6cout[0:0]),
.dataa(wire_add_sub_cella_dataa[6:6]),
.datab(wire_add_sub_cella_datab[6:6]),
.ena(clken),
.regout(wire_add_sub_cella_regout[6:6]));
defparam
add_sub_cella_6.cin_used = "true",
add_sub_cella_6.lut_mask = "69b2",
add_sub_cella_6.operation_mode = "arithmetic",
add_sub_cella_6.sum_lutc_input = "cin",
add_sub_cella_6.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_7
(
.aclr(aclr),
.cin(wire_add_sub_cella_6cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_7cout[0:0]),
.dataa(wire_add_sub_cella_dataa[7:7]),
.datab(wire_add_sub_cella_datab[7:7]),
.ena(clken),
.regout(wire_add_sub_cella_regout[7:7]));
defparam
add_sub_cella_7.cin_used = "true",
add_sub_cella_7.lut_mask = "69b2",
add_sub_cella_7.operation_mode = "arithmetic",
add_sub_cella_7.sum_lutc_input = "cin",
add_sub_cella_7.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_8
(
.aclr(aclr),
.cin(wire_add_sub_cella_7cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_8cout[0:0]),
.dataa(wire_add_sub_cella_dataa[8:8]),
.datab(wire_add_sub_cella_datab[8:8]),
.ena(clken),
.regout(wire_add_sub_cella_regout[8:8]));
defparam
add_sub_cella_8.cin_used = "true",
add_sub_cella_8.lut_mask = "69b2",
add_sub_cella_8.operation_mode = "arithmetic",
add_sub_cella_8.sum_lutc_input = "cin",
add_sub_cella_8.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_9
(
.aclr(aclr),
.cin(wire_add_sub_cella_8cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_9cout[0:0]),
.dataa(wire_add_sub_cella_dataa[9:9]),
.datab(wire_add_sub_cella_datab[9:9]),
.ena(clken),
.regout(wire_add_sub_cella_regout[9:9]));
defparam
add_sub_cella_9.cin_used = "true",
add_sub_cella_9.lut_mask = "69b2",
add_sub_cella_9.operation_mode = "arithmetic",
add_sub_cella_9.sum_lutc_input = "cin",
add_sub_cella_9.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_10
(
.aclr(aclr),
.cin(wire_add_sub_cella_9cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_10cout[0:0]),
.dataa(wire_add_sub_cella_dataa[10:10]),
.datab(wire_add_sub_cella_datab[10:10]),
.ena(clken),
.regout(wire_add_sub_cella_regout[10:10]));
defparam
add_sub_cella_10.cin_used = "true",
add_sub_cella_10.lut_mask = "69b2",
add_sub_cella_10.operation_mode = "arithmetic",
add_sub_cella_10.sum_lutc_input = "cin",
add_sub_cella_10.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_11
(
.aclr(aclr),
.cin(wire_add_sub_cella_10cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_11cout[0:0]),
.dataa(wire_add_sub_cella_dataa[11:11]),
.datab(wire_add_sub_cella_datab[11:11]),
.ena(clken),
.regout(wire_add_sub_cella_regout[11:11]));
defparam
add_sub_cella_11.cin_used = "true",
add_sub_cella_11.lut_mask = "69b2",
add_sub_cella_11.operation_mode = "arithmetic",
add_sub_cella_11.sum_lutc_input = "cin",
add_sub_cella_11.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_12
(
.aclr(aclr),
.cin(wire_add_sub_cella_11cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_12cout[0:0]),
.dataa(wire_add_sub_cella_dataa[12:12]),
.datab(wire_add_sub_cella_datab[12:12]),
.ena(clken),
.regout(wire_add_sub_cella_regout[12:12]));
defparam
add_sub_cella_12.cin_used = "true",
add_sub_cella_12.lut_mask = "69b2",
add_sub_cella_12.operation_mode = "arithmetic",
add_sub_cella_12.sum_lutc_input = "cin",
add_sub_cella_12.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_13
(
.aclr(aclr),
.cin(wire_add_sub_cella_12cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_13cout[0:0]),
.dataa(wire_add_sub_cella_dataa[13:13]),
.datab(wire_add_sub_cella_datab[13:13]),
.ena(clken),
.regout(wire_add_sub_cella_regout[13:13]));
defparam
add_sub_cella_13.cin_used = "true",
add_sub_cella_13.lut_mask = "69b2",
add_sub_cella_13.operation_mode = "arithmetic",
add_sub_cella_13.sum_lutc_input = "cin",
add_sub_cella_13.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_14
(
.aclr(aclr),
.cin(wire_add_sub_cella_13cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_14cout[0:0]),
.dataa(wire_add_sub_cella_dataa[14:14]),
.datab(wire_add_sub_cella_datab[14:14]),
.ena(clken),
.regout(wire_add_sub_cella_regout[14:14]));
defparam
add_sub_cella_14.cin_used = "true",
add_sub_cella_14.lut_mask = "69b2",
add_sub_cella_14.operation_mode = "arithmetic",
add_sub_cella_14.sum_lutc_input = "cin",
add_sub_cella_14.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_15
(
.aclr(aclr),
.cin(wire_add_sub_cella_14cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_15cout[0:0]),
.dataa(wire_add_sub_cella_dataa[15:15]),
.datab(wire_add_sub_cella_datab[15:15]),
.ena(clken),
.regout(wire_add_sub_cella_regout[15:15]));
defparam
add_sub_cella_15.cin_used = "true",
add_sub_cella_15.lut_mask = "69b2",
add_sub_cella_15.operation_mode = "arithmetic",
add_sub_cella_15.sum_lutc_input = "cin",
add_sub_cella_15.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_16
(
.aclr(aclr),
.cin(wire_add_sub_cella_15cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_16cout[0:0]),
.dataa(wire_add_sub_cella_dataa[16:16]),
.datab(wire_add_sub_cella_datab[16:16]),
.ena(clken),
.regout(wire_add_sub_cella_regout[16:16]));
defparam
add_sub_cella_16.cin_used = "true",
add_sub_cella_16.lut_mask = "69b2",
add_sub_cella_16.operation_mode = "arithmetic",
add_sub_cella_16.sum_lutc_input = "cin",
add_sub_cella_16.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_17
(
.aclr(aclr),
.cin(wire_add_sub_cella_16cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_17cout[0:0]),
.dataa(wire_add_sub_cella_dataa[17:17]),
.datab(wire_add_sub_cella_datab[17:17]),
.ena(clken),
.regout(wire_add_sub_cella_regout[17:17]));
defparam
add_sub_cella_17.cin_used = "true",
add_sub_cella_17.lut_mask = "69b2",
add_sub_cella_17.operation_mode = "arithmetic",
add_sub_cella_17.sum_lutc_input = "cin",
add_sub_cella_17.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_18
(
.aclr(aclr),
.cin(wire_add_sub_cella_17cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_18cout[0:0]),
.dataa(wire_add_sub_cella_dataa[18:18]),
.datab(wire_add_sub_cella_datab[18:18]),
.ena(clken),
.regout(wire_add_sub_cella_regout[18:18]));
defparam
add_sub_cella_18.cin_used = "true",
add_sub_cella_18.lut_mask = "69b2",
add_sub_cella_18.operation_mode = "arithmetic",
add_sub_cella_18.sum_lutc_input = "cin",
add_sub_cella_18.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_19
(
.aclr(aclr),
.cin(wire_add_sub_cella_18cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_19cout[0:0]),
.dataa(wire_add_sub_cella_dataa[19:19]),
.datab(wire_add_sub_cella_datab[19:19]),
.ena(clken),
.regout(wire_add_sub_cella_regout[19:19]));
defparam
add_sub_cella_19.cin_used = "true",
add_sub_cella_19.lut_mask = "69b2",
add_sub_cella_19.operation_mode = "arithmetic",
add_sub_cella_19.sum_lutc_input = "cin",
add_sub_cella_19.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_20
(
.aclr(aclr),
.cin(wire_add_sub_cella_19cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_20cout[0:0]),
.dataa(wire_add_sub_cella_dataa[20:20]),
.datab(wire_add_sub_cella_datab[20:20]),
.ena(clken),
.regout(wire_add_sub_cella_regout[20:20]));
defparam
add_sub_cella_20.cin_used = "true",
add_sub_cella_20.lut_mask = "69b2",
add_sub_cella_20.operation_mode = "arithmetic",
add_sub_cella_20.sum_lutc_input = "cin",
add_sub_cella_20.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_21
(
.aclr(aclr),
.cin(wire_add_sub_cella_20cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_21cout[0:0]),
.dataa(wire_add_sub_cella_dataa[21:21]),
.datab(wire_add_sub_cella_datab[21:21]),
.ena(clken),
.regout(wire_add_sub_cella_regout[21:21]));
defparam
add_sub_cella_21.cin_used = "true",
add_sub_cella_21.lut_mask = "69b2",
add_sub_cella_21.operation_mode = "arithmetic",
add_sub_cella_21.sum_lutc_input = "cin",
add_sub_cella_21.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_22
(
.aclr(aclr),
.cin(wire_add_sub_cella_21cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_22cout[0:0]),
.dataa(wire_add_sub_cella_dataa[22:22]),
.datab(wire_add_sub_cella_datab[22:22]),
.ena(clken),
.regout(wire_add_sub_cella_regout[22:22]));
defparam
add_sub_cella_22.cin_used = "true",
add_sub_cella_22.lut_mask = "69b2",
add_sub_cella_22.operation_mode = "arithmetic",
add_sub_cella_22.sum_lutc_input = "cin",
add_sub_cella_22.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_23
(
.aclr(aclr),
.cin(wire_add_sub_cella_22cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_23cout[0:0]),
.dataa(wire_add_sub_cella_dataa[23:23]),
.datab(wire_add_sub_cella_datab[23:23]),
.ena(clken),
.regout(wire_add_sub_cella_regout[23:23]));
defparam
add_sub_cella_23.cin_used = "true",
add_sub_cella_23.lut_mask = "69b2",
add_sub_cella_23.operation_mode = "arithmetic",
add_sub_cella_23.sum_lutc_input = "cin",
add_sub_cella_23.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_24
(
.aclr(aclr),
.cin(wire_add_sub_cella_23cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_24cout[0:0]),
.dataa(wire_add_sub_cella_dataa[24:24]),
.datab(wire_add_sub_cella_datab[24:24]),
.ena(clken),
.regout(wire_add_sub_cella_regout[24:24]));
defparam
add_sub_cella_24.cin_used = "true",
add_sub_cella_24.lut_mask = "69b2",
add_sub_cella_24.operation_mode = "arithmetic",
add_sub_cella_24.sum_lutc_input = "cin",
add_sub_cella_24.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_25
(
.aclr(aclr),
.cin(wire_add_sub_cella_24cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_25cout[0:0]),
.dataa(wire_add_sub_cella_dataa[25:25]),
.datab(wire_add_sub_cella_datab[25:25]),
.ena(clken),
.regout(wire_add_sub_cella_regout[25:25]));
defparam
add_sub_cella_25.cin_used = "true",
add_sub_cella_25.lut_mask = "69b2",
add_sub_cella_25.operation_mode = "arithmetic",
add_sub_cella_25.sum_lutc_input = "cin",
add_sub_cella_25.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_26
(
.aclr(aclr),
.cin(wire_add_sub_cella_25cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_26cout[0:0]),
.dataa(wire_add_sub_cella_dataa[26:26]),
.datab(wire_add_sub_cella_datab[26:26]),
.ena(clken),
.regout(wire_add_sub_cella_regout[26:26]));
defparam
add_sub_cella_26.cin_used = "true",
add_sub_cella_26.lut_mask = "69b2",
add_sub_cella_26.operation_mode = "arithmetic",
add_sub_cella_26.sum_lutc_input = "cin",
add_sub_cella_26.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_27
(
.aclr(aclr),
.cin(wire_add_sub_cella_26cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_27cout[0:0]),
.dataa(wire_add_sub_cella_dataa[27:27]),
.datab(wire_add_sub_cella_datab[27:27]),
.ena(clken),
.regout(wire_add_sub_cella_regout[27:27]));
defparam
add_sub_cella_27.cin_used = "true",
add_sub_cella_27.lut_mask = "69b2",
add_sub_cella_27.operation_mode = "arithmetic",
add_sub_cella_27.sum_lutc_input = "cin",
add_sub_cella_27.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_28
(
.aclr(aclr),
.cin(wire_add_sub_cella_27cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_28cout[0:0]),
.dataa(wire_add_sub_cella_dataa[28:28]),
.datab(wire_add_sub_cella_datab[28:28]),
.ena(clken),
.regout(wire_add_sub_cella_regout[28:28]));
defparam
add_sub_cella_28.cin_used = "true",
add_sub_cella_28.lut_mask = "69b2",
add_sub_cella_28.operation_mode = "arithmetic",
add_sub_cella_28.sum_lutc_input = "cin",
add_sub_cella_28.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_29
(
.aclr(aclr),
.cin(wire_add_sub_cella_28cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_29cout[0:0]),
.dataa(wire_add_sub_cella_dataa[29:29]),
.datab(wire_add_sub_cella_datab[29:29]),
.ena(clken),
.regout(wire_add_sub_cella_regout[29:29]));
defparam
add_sub_cella_29.cin_used = "true",
add_sub_cella_29.lut_mask = "69b2",
add_sub_cella_29.operation_mode = "arithmetic",
add_sub_cella_29.sum_lutc_input = "cin",
add_sub_cella_29.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_30
(
.aclr(aclr),
.cin(wire_add_sub_cella_29cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_30cout[0:0]),
.dataa(wire_add_sub_cella_dataa[30:30]),
.datab(wire_add_sub_cella_datab[30:30]),
.ena(clken),
.regout(wire_add_sub_cella_regout[30:30]));
defparam
add_sub_cella_30.cin_used = "true",
add_sub_cella_30.lut_mask = "69b2",
add_sub_cella_30.operation_mode = "arithmetic",
add_sub_cella_30.sum_lutc_input = "cin",
add_sub_cella_30.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_31
(
.aclr(aclr),
.cin(wire_add_sub_cella_30cout[0:0]),
.clk(clock),
.dataa(wire_add_sub_cella_dataa[31:31]),
.datab(wire_add_sub_cella_datab[31:31]),
.ena(clken),
.regout(wire_add_sub_cella_regout[31:31]));
defparam
add_sub_cella_31.cin_used = "true",
add_sub_cella_31.lut_mask = "6969",
add_sub_cella_31.operation_mode = "normal",
add_sub_cella_31.sum_lutc_input = "cin",
add_sub_cella_31.lpm_type = "stratix_lcell";
assign
wire_add_sub_cella_dataa = dataa,
wire_add_sub_cella_datab = datab;
assign
result = wire_add_sub_cella_regout;
endmodule //sub32_add_sub_cqa
//VALID FILE
module sub32 (
dataa,
datab,
clock,
aclr,
clken,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] dataa;
input [31:0] datab;
input clock;
input aclr;
input clken;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
sub32_add_sub_cqa sub32_add_sub_cqa_component (
.dataa (dataa),
.datab (datab),
.clken (clken),
.aclr (aclr),
.clock (clock),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: nBit NUMERIC "32"
// Retrieval info: PRIVATE: Function NUMERIC "1"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: aclr NUMERIC "1"
// Retrieval info: PRIVATE: clken NUMERIC "1"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "SUB"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL dataa[31..0]
// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL datab[31..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module sub32 (
dataa,
datab,
clock,
aclr,
clken,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] dataa;
input [31:0] datab;
input clock;
input aclr;
input clken;
output [31:0] result;
endmodule
|
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module sub32 (
dataa,
datab,
clock,
aclr,
clken,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] dataa;
input [31:0] datab;
input clock;
input aclr;
input clken;
output [31:0] result;
endmodule
|
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module sub32 (
dataa,
datab,
clock,
aclr,
clken,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] dataa;
input [31:0] datab;
input clock;
input aclr;
input clken;
output [31:0] result;
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Following defines conditionally include RX path circuitry
`include "config.vh" // resolved relative to project root
module rx_chain
(input clock,
input reset,
input enable,
input wire [7:0] decim_rate,
input sample_strobe,
input decimator_strobe,
output wire hb_strobe,
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out,
output wire [15:0] debugdata,output wire [15:0] debugctrl
);
parameter FREQADDR = 0;
parameter PHASEADDR = 0;
wire [31:0] phase;
wire [15:0] bb_i, bb_q;
wire [15:0] hb_in_i, hb_in_q;
assign debugdata = hb_in_i;
`ifdef RX_NCO_ON
phase_acc #(FREQADDR,PHASEADDR,32) rx_phase_acc
(.clk(clock),.reset(reset),.enable(enable),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.strobe(sample_strobe),.phase(phase) );
cordic rx_cordic
( .clock(clock),.reset(reset),.enable(enable),
.xi(i_in),.yi(q_in),.zi(phase[31:16]),
.xo(bb_i),.yo(bb_q),.zo() );
`else
assign bb_i = i_in;
assign bb_q = q_in;
assign sample_strobe = 1;
`endif // !`ifdef RX_NCO_ON
`ifdef RX_CIC_ON
cic_decim cic_decim_i_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i),.signal_out(hb_in_i) );
`else
assign hb_in_i = bb_i;
assign decimator_strobe = sample_strobe;
`endif
`ifdef RX_HB_ON
halfband_decim hbd_i_0
( .clock(clock),.reset(reset),.enable(enable),
.strobe_in(decimator_strobe),.strobe_out(hb_strobe),
.data_in(hb_in_i),.data_out(i_out),.debugctrl(debugctrl) );
`else
assign i_out = hb_in_i;
assign hb_strobe = decimator_strobe;
`endif
`ifdef RX_CIC_ON
cic_decim cic_decim_q_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q),.signal_out(hb_in_q) );
`else
assign hb_in_q = bb_q;
`endif
`ifdef RX_HB_ON
halfband_decim hbd_q_0
( .clock(clock),.reset(reset),.enable(enable),
.strobe_in(decimator_strobe),.strobe_out(),
.data_in(hb_in_q),.data_out(q_out) );
`else
assign q_out = hb_in_q;
`endif
endmodule // rx_chain
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:06:52 06/28/2009
// Design Name:
// Module Name: dcm
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module my_dcm (
input CLKIN,
output CLKFX,
output LOCKED,
input RST,
output[7:0] STATUS
);
// DCM: Digital Clock Manager Circuit
// Spartan-3
// Xilinx HDL Language Template, version 11.1
DCM #(
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(41.667), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hFFFF), // FACTORY JF values
// .LOC("DCM_X0Y0"),
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_inst (
.CLK0(CLK0), // 0 degree DCM CLK output
.CLK180(CLK180), // 180 degree DCM CLK output
.CLK270(CLK270), // 270 degree DCM CLK output
.CLK2X(CLK2X), // 2X DCM CLK output
.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
.CLK90(CLK90), // 90 degree DCM CLK output
.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
.LOCKED(LOCKED), // DCM LOCK status output
.PSDONE(PSDONE), // Dynamic phase adjust done output
.STATUS(STATUS), // 8-bit DCM status bits output
.CLKFB(CLKFB), // DCM clock feedback
.CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(PSCLK), // Dynamic phase adjust clock input
.PSEN(PSEN), // Dynamic phase adjust enable input
.PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
.RST(RST) // DCM asynchronous reset input
);
endmodule
|
module halfband_interp
(input clock, input reset, input enable,
input strobe_in, input strobe_out,
input [15:0] signal_in_i, input [15:0] signal_in_q,
output reg [15:0] signal_out_i, output reg [15:0] signal_out_q,
output wire [12:0] debug);
wire [15:0] coeff_ram_out;
wire [15:0] data_ram_out_i;
wire [15:0] data_ram_out_q;
wire [3:0] data_rd_addr;
reg [3:0] data_wr_addr;
reg [2:0] coeff_rd_addr;
wire filt_done;
wire [15:0] mac_out_i;
wire [15:0] mac_out_q;
reg [15:0] delayed_middle_i, delayed_middle_q;
wire [7:0] shift = 8'd9;
reg stb_out_happened;
wire [15:0] data_ram_out_i_b;
always @(posedge clock)
if(strobe_in)
stb_out_happened <= #1 1'b0;
else if(strobe_out)
stb_out_happened <= #1 1'b1;
assign debug = {filt_done,data_rd_addr,data_wr_addr,coeff_rd_addr};
wire [15:0] signal_out_i = stb_out_happened ? mac_out_i : delayed_middle_i;
wire [15:0] signal_out_q = stb_out_happened ? mac_out_q : delayed_middle_q;
/* always @(posedge clock)
if(reset)
begin
signal_out_i <= #1 16'd0;
signal_out_q <= #1 16'd0;
end
else if(strobe_in)
begin
signal_out_i <= #1 delayed_middle_i; // Multiply by 1 for middle coeff
signal_out_q <= #1 delayed_middle_q;
end
//else if(filt_done&stb_out_happened)
else if(stb_out_happened)
begin
signal_out_i <= #1 mac_out_i;
signal_out_q <= #1 mac_out_q;
end
*/
always @(posedge clock)
if(reset)
coeff_rd_addr <= #1 3'd0;
else if(coeff_rd_addr != 3'd0)
coeff_rd_addr <= #1 coeff_rd_addr + 3'd1;
else if(strobe_in)
coeff_rd_addr <= #1 3'd1;
reg filt_done_d1;
always@(posedge clock)
filt_done_d1 <= #1 filt_done;
always @(posedge clock)
if(reset)
data_wr_addr <= #1 4'd0;
//else if(strobe_in)
else if(filt_done & ~filt_done_d1)
data_wr_addr <= #1 data_wr_addr + 4'd1;
always @(posedge clock)
if(coeff_rd_addr == 3'd7)
begin
delayed_middle_i <= #1 data_ram_out_i_b;
// delayed_middle_q <= #1 data_ram_out_q_b;
end
// always @(posedge clock)
// if(reset)
// data_rd_addr <= #1 4'd0;
// else if(strobe_in)
// data_rd_addr <= #1 data_wr_addr + 4'd1;
// else if(!filt_done)
// data_rd_addr <= #1 data_rd_addr + 4'd1;
// else
// data_rd_addr <= #1 data_wr_addr;
wire [3:0] data_rd_addr1 = data_wr_addr + {1'b0,coeff_rd_addr};
wire [3:0] data_rd_addr2 = data_wr_addr + 15 - {1'b0,coeff_rd_addr};
// always @(posedge clock)
// if(reset)
// filt_done <= #1 1'b1;
// else if(strobe_in)
// filt_done <= #1 1'b0;
// else if(coeff_rd_addr == 4'd0)
// filt_done <= #1 1'b1;
assign filt_done = (coeff_rd_addr == 3'd0);
coeff_ram coeff_ram ( .clock(clock),.rd_addr({1'b0,coeff_rd_addr}),.rd_data(coeff_ram_out) );
ram16_2sum data_ram_i ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_i),
.rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_i_b),.sum(data_ram_out_i));
ram16_2sum data_ram_q ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_q),
.rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_q));
mac mac_i (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in),
.x(data_ram_out_i),.y(coeff_ram_out),.shift(shift),.z(mac_out_i) );
mac mac_q (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in),
.x(data_ram_out_q),.y(coeff_ram_out),.shift(shift),.z(mac_out_q) );
endmodule // halfband_interp
|
// megafunction wizard: %LPM_ADD_SUB%CBX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_add_sub
// ============================================================
// File Name: add32.v
// Megafunction Name(s):
// lpm_add_sub
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_DIRECTION=ADD LPM_WIDTH=8 dataa datab result
//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END
//synthesis_resources = lut 8
module add32_add_sub_nq7
(
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
wire [7:0] wire_add_sub_cella_combout;
wire [0:0] wire_add_sub_cella_0cout;
wire [0:0] wire_add_sub_cella_1cout;
wire [0:0] wire_add_sub_cella_2cout;
wire [0:0] wire_add_sub_cella_3cout;
wire [0:0] wire_add_sub_cella_4cout;
wire [0:0] wire_add_sub_cella_5cout;
wire [0:0] wire_add_sub_cella_6cout;
wire [7:0] wire_add_sub_cella_dataa;
wire [7:0] wire_add_sub_cella_datab;
stratix_lcell add_sub_cella_0
(
.cin(1'b0),
.combout(wire_add_sub_cella_combout[0:0]),
.cout(wire_add_sub_cella_0cout[0:0]),
.dataa(wire_add_sub_cella_dataa[0:0]),
.datab(wire_add_sub_cella_datab[0:0]));
defparam
add_sub_cella_0.cin_used = "true",
add_sub_cella_0.lut_mask = "96e8",
add_sub_cella_0.operation_mode = "arithmetic",
add_sub_cella_0.sum_lutc_input = "cin",
add_sub_cella_0.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_1
(
.cin(wire_add_sub_cella_0cout[0:0]),
.combout(wire_add_sub_cella_combout[1:1]),
.cout(wire_add_sub_cella_1cout[0:0]),
.dataa(wire_add_sub_cella_dataa[1:1]),
.datab(wire_add_sub_cella_datab[1:1]));
defparam
add_sub_cella_1.cin_used = "true",
add_sub_cella_1.lut_mask = "96e8",
add_sub_cella_1.operation_mode = "arithmetic",
add_sub_cella_1.sum_lutc_input = "cin",
add_sub_cella_1.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_2
(
.cin(wire_add_sub_cella_1cout[0:0]),
.combout(wire_add_sub_cella_combout[2:2]),
.cout(wire_add_sub_cella_2cout[0:0]),
.dataa(wire_add_sub_cella_dataa[2:2]),
.datab(wire_add_sub_cella_datab[2:2]));
defparam
add_sub_cella_2.cin_used = "true",
add_sub_cella_2.lut_mask = "96e8",
add_sub_cella_2.operation_mode = "arithmetic",
add_sub_cella_2.sum_lutc_input = "cin",
add_sub_cella_2.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_3
(
.cin(wire_add_sub_cella_2cout[0:0]),
.combout(wire_add_sub_cella_combout[3:3]),
.cout(wire_add_sub_cella_3cout[0:0]),
.dataa(wire_add_sub_cella_dataa[3:3]),
.datab(wire_add_sub_cella_datab[3:3]));
defparam
add_sub_cella_3.cin_used = "true",
add_sub_cella_3.lut_mask = "96e8",
add_sub_cella_3.operation_mode = "arithmetic",
add_sub_cella_3.sum_lutc_input = "cin",
add_sub_cella_3.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_4
(
.cin(wire_add_sub_cella_3cout[0:0]),
.combout(wire_add_sub_cella_combout[4:4]),
.cout(wire_add_sub_cella_4cout[0:0]),
.dataa(wire_add_sub_cella_dataa[4:4]),
.datab(wire_add_sub_cella_datab[4:4]));
defparam
add_sub_cella_4.cin_used = "true",
add_sub_cella_4.lut_mask = "96e8",
add_sub_cella_4.operation_mode = "arithmetic",
add_sub_cella_4.sum_lutc_input = "cin",
add_sub_cella_4.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_5
(
.cin(wire_add_sub_cella_4cout[0:0]),
.combout(wire_add_sub_cella_combout[5:5]),
.cout(wire_add_sub_cella_5cout[0:0]),
.dataa(wire_add_sub_cella_dataa[5:5]),
.datab(wire_add_sub_cella_datab[5:5]));
defparam
add_sub_cella_5.cin_used = "true",
add_sub_cella_5.lut_mask = "96e8",
add_sub_cella_5.operation_mode = "arithmetic",
add_sub_cella_5.sum_lutc_input = "cin",
add_sub_cella_5.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_6
(
.cin(wire_add_sub_cella_5cout[0:0]),
.combout(wire_add_sub_cella_combout[6:6]),
.cout(wire_add_sub_cella_6cout[0:0]),
.dataa(wire_add_sub_cella_dataa[6:6]),
.datab(wire_add_sub_cella_datab[6:6]));
defparam
add_sub_cella_6.cin_used = "true",
add_sub_cella_6.lut_mask = "96e8",
add_sub_cella_6.operation_mode = "arithmetic",
add_sub_cella_6.sum_lutc_input = "cin",
add_sub_cella_6.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_7
(
.cin(wire_add_sub_cella_6cout[0:0]),
.combout(wire_add_sub_cella_combout[7:7]),
.dataa(wire_add_sub_cella_dataa[7:7]),
.datab(wire_add_sub_cella_datab[7:7]));
defparam
add_sub_cella_7.cin_used = "true",
add_sub_cella_7.lut_mask = "9696",
add_sub_cella_7.operation_mode = "normal",
add_sub_cella_7.sum_lutc_input = "cin",
add_sub_cella_7.lpm_type = "stratix_lcell";
assign
wire_add_sub_cella_dataa = dataa,
wire_add_sub_cella_datab = datab;
assign
result = wire_add_sub_cella_combout;
endmodule //add32_add_sub_nq7
//VALID FILE
module add32 (
dataa,
datab,
result)/* synthesis synthesis_clearbox = 1 */;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
wire [7:0] sub_wire0;
wire [7:0] result = sub_wire0[7:0];
add32_add_sub_nq7 add32_add_sub_nq7_component (
.dataa (dataa),
.datab (datab),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: nBit NUMERIC "8"
// Retrieval info: PRIVATE: Function NUMERIC "0"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0]
// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL dataa[7..0]
// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL datab[7..0]
// Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module tx_chain
(input clock,
input reset,
input enable,
input wire [7:0] interp_rate,
input sample_strobe,
input interpolator_strobe,
input wire [31:0] freq,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out
);
wire [15:0] bb_i, bb_q;
cic_interp cic_interp_i
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
.signal_in(i_in),.signal_out(bb_i) );
cic_interp cic_interp_q
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
.signal_in(q_in),.signal_out(bb_q) );
`define NOCORDIC_TX
`ifdef NOCORDIC_TX
assign i_out = bb_i;
assign q_out = bb_q;
`else
wire [31:0] phase;
phase_acc phase_acc_tx
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq),.phase(phase) );
cordic tx_cordic_0
( .clock(clock),.reset(reset),.enable(sample_strobe),
.xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
.xo(i_out),.yo(q_out),.zo() );
`endif
endmodule // tx_chain
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module tx_chain
(input clock,
input reset,
input enable,
input wire [7:0] interp_rate,
input sample_strobe,
input interpolator_strobe,
input wire [31:0] freq,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out
);
wire [15:0] bb_i, bb_q;
cic_interp cic_interp_i
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
.signal_in(i_in),.signal_out(bb_i) );
cic_interp cic_interp_q
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
.signal_in(q_in),.signal_out(bb_q) );
`define NOCORDIC_TX
`ifdef NOCORDIC_TX
assign i_out = bb_i;
assign q_out = bb_q;
`else
wire [31:0] phase;
phase_acc phase_acc_tx
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq),.phase(phase) );
cordic tx_cordic_0
( .clock(clock),.reset(reset),.enable(sample_strobe),
.xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
.xo(i_out),.yo(q_out),.zo() );
`endif
endmodule // tx_chain
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module tx_chain
(input clock,
input reset,
input enable,
input wire [7:0] interp_rate,
input sample_strobe,
input interpolator_strobe,
input wire [31:0] freq,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out
);
wire [15:0] bb_i, bb_q;
cic_interp cic_interp_i
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
.signal_in(i_in),.signal_out(bb_i) );
cic_interp cic_interp_q
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
.signal_in(q_in),.signal_out(bb_q) );
`define NOCORDIC_TX
`ifdef NOCORDIC_TX
assign i_out = bb_i;
assign q_out = bb_q;
`else
wire [31:0] phase;
phase_acc phase_acc_tx
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq),.phase(phase) );
cordic tx_cordic_0
( .clock(clock),.reset(reset),.enable(sample_strobe),
.xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
.xo(i_out),.yo(q_out),.zo() );
`endif
endmodule // tx_chain
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0);
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0)
// synopsys translate_off
,
.fbin (),
.pllena (),
.clkswitch (),
.areset (),
.pfdena (),
.clkena (),
.extclkena (),
.scanclk (),
.scanaclr (),
.scandata (),
.scanread (),
.scanwrite (),
.extclk (),
.clkbad (),
.activeclock (),
.locked (),
.clkloss (),
.scandataout (),
.scandone (),
.sclkout1 (),
.sclkout0 (),
.enable0 (),
.enable1 ()
// synopsys translate_on
);
defparam
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 1,
altpll_component.inclk0_input_frequency = 20833,
altpll_component.clk0_divide_by = 1,
altpll_component.pll_type = "AUTO",
altpll_component.clk0_time_delay = "0",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk0_phase_shift = "-3000";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-3.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;fbin;pllena;clkswitch;areset"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "pfdena;clkena;extclkena;scanclk;scanaclr"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "scandata;scanread;scanwrite;clk;extclk"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "528.000"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "clkbad;activeclock;locked;clkloss;scandataout"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "scandone;sclkout1;sclkout0;enable0;enable1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-3000"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE FALSE
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0);
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0)
// synopsys translate_off
,
.fbin (),
.pllena (),
.clkswitch (),
.areset (),
.pfdena (),
.clkena (),
.extclkena (),
.scanclk (),
.scanaclr (),
.scandata (),
.scanread (),
.scanwrite (),
.extclk (),
.clkbad (),
.activeclock (),
.locked (),
.clkloss (),
.scandataout (),
.scandone (),
.sclkout1 (),
.sclkout0 (),
.enable0 (),
.enable1 ()
// synopsys translate_on
);
defparam
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 1,
altpll_component.inclk0_input_frequency = 20833,
altpll_component.clk0_divide_by = 1,
altpll_component.pll_type = "AUTO",
altpll_component.clk0_time_delay = "0",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk0_phase_shift = "-3000";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-3.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;fbin;pllena;clkswitch;areset"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "pfdena;clkena;extclkena;scanclk;scanaclr"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "scandata;scanread;scanwrite;clk;extclk"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "528.000"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "clkbad;activeclock;locked;clkloss;scandataout"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "scandone;sclkout1;sclkout0;enable0;enable1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-3000"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE FALSE
|
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module bustri (
data,
enabledt,
tridata);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
endmodule
|
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module bustri (
data,
enabledt,
tridata);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
endmodule
|
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module bustri (
data,
enabledt,
tridata);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
endmodule
|
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module bustri (
data,
enabledt,
tridata);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
endmodule
|
// $Id: //acds/main/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#8 $
// $Revision: #8 $
// $Date: 2009/02/18 $
// $Author: pscheidt $
//-----------------------------------------------------------------------------
//
// File: altera_std_synchronizer_nocut.v
//
// Abstract: Single bit clock domain crossing synchronizer. Exactly the same
// as altera_std_synchronizer.v, except that the embedded false
// path constraint is removed in this module. If you use this
// module, you will have to apply the appropriate timing
// constraints.
//
// We expect to make this a standard Quartus atom eventually.
//
// Composed of two or more flip flops connected in series.
// Random metastable condition is simulated when the
// __ALTERA_STD__METASTABLE_SIM macro is defined.
// Use +define+__ALTERA_STD__METASTABLE_SIM argument
// on the Verilog simulator compiler command line to
// enable this mode. In addition, define the macro
// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output
// with every metastable event generated in the synchronizer.
//
// Copyright (C) Altera Corporation 2009, All Rights Reserved
//-----------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_std_synchronizer_nocut (
clk,
reset_n,
din,
dout
);
parameter depth = 3; // This value must be >= 2 !
input clk;
input reset_n;
input din;
output dout;
// QuartusII synthesis directives:
// 1. Preserve all registers ie. do not touch them.
// 2. Do not merge other flip-flops with synchronizer flip-flops.
// QuartusII TimeQuest directives:
// 1. Identify all flip-flops in this module as members of the synchronizer
// to enable automatic metastability MTBF analysis.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
//synthesis translate_off
initial begin
if (depth <2) begin
$display("%m: Error: synchronizer length: %0d less than 2.", depth);
end
end
// the first synchronizer register is either a simple D flop for synthesis
// and non-metastable simulation or a D flop with a method to inject random
// metastable events resulting in random delay of [0,1] cycles
`ifdef __ALTERA_STD__METASTABLE_SIM
reg[31:0] RANDOM_SEED = 123456;
wire next_din_s1;
wire dout;
reg din_last;
reg random;
event metastable_event; // hook for debug monitoring
initial begin
$display("%m: Info: Metastable event injection simulation mode enabled");
end
always @(posedge clk) begin
if (reset_n == 0)
random <= $random(RANDOM_SEED);
else
random <= $random;
end
assign next_din_s1 = (din_last ^ din) ? random : din;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_last <= 1'b0;
else
din_last <= din;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= next_din_s1;
end
`else
//synthesis translate_on
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= din;
end
//synthesis translate_off
`endif
`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
always @(*) begin
if (reset_n && (din_last != din) && (random != din)) begin
$display("%m: Verbose Info: metastable event @ time %t", $time);
->metastable_event;
end
end
`endif
//synthesis translate_on
// the remaining synchronizer registers form a simple shift register
// of length depth-1
generate
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate
assign dout = dreg[depth-2];
endmodule
|
// megafunction wizard: %ALTACCUMULATE%CBX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altaccumulate
// ============================================================
// File Name: accum32.v
// Megafunction Name(s):
// altaccumulate
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
//altaccumulate DEVICE_FAMILY=Cyclone LPM_REPRESENTATION=SIGNED WIDTH_IN=32 WIDTH_OUT=32 aclr clken clock data result
//VERSION_BEGIN 3.0 cbx_altaccumulate 2003:04:08:16:04:48:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END
//synthesis_resources = lut 32
module accum32_accum_nta
(
aclr,
clken,
clock,
data,
result) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clken;
input clock;
input [31:0] data;
output [31:0] result;
wire [0:0] wire_acc_cella_0cout;
wire [0:0] wire_acc_cella_1cout;
wire [0:0] wire_acc_cella_2cout;
wire [0:0] wire_acc_cella_3cout;
wire [0:0] wire_acc_cella_4cout;
wire [0:0] wire_acc_cella_5cout;
wire [0:0] wire_acc_cella_6cout;
wire [0:0] wire_acc_cella_7cout;
wire [0:0] wire_acc_cella_8cout;
wire [0:0] wire_acc_cella_9cout;
wire [0:0] wire_acc_cella_10cout;
wire [0:0] wire_acc_cella_11cout;
wire [0:0] wire_acc_cella_12cout;
wire [0:0] wire_acc_cella_13cout;
wire [0:0] wire_acc_cella_14cout;
wire [0:0] wire_acc_cella_15cout;
wire [0:0] wire_acc_cella_16cout;
wire [0:0] wire_acc_cella_17cout;
wire [0:0] wire_acc_cella_18cout;
wire [0:0] wire_acc_cella_19cout;
wire [0:0] wire_acc_cella_20cout;
wire [0:0] wire_acc_cella_21cout;
wire [0:0] wire_acc_cella_22cout;
wire [0:0] wire_acc_cella_23cout;
wire [0:0] wire_acc_cella_24cout;
wire [0:0] wire_acc_cella_25cout;
wire [0:0] wire_acc_cella_26cout;
wire [0:0] wire_acc_cella_27cout;
wire [0:0] wire_acc_cella_28cout;
wire [0:0] wire_acc_cella_29cout;
wire [0:0] wire_acc_cella_30cout;
wire [31:0] wire_acc_cella_dataa;
wire [31:0] wire_acc_cella_datab;
wire [31:0] wire_acc_cella_datac;
wire [31:0] wire_acc_cella_regout;
wire sload;
stratix_lcell acc_cella_0
(
.aclr(aclr),
.cin(1'b0),
.clk(clock),
.cout(wire_acc_cella_0cout[0:0]),
.dataa(wire_acc_cella_dataa[0:0]),
.datab(wire_acc_cella_datab[0:0]),
.datac(wire_acc_cella_datac[0:0]),
.ena(clken),
.regout(wire_acc_cella_regout[0:0]),
.sload(sload));
defparam
acc_cella_0.cin_used = "true",
acc_cella_0.lut_mask = "96e8",
acc_cella_0.operation_mode = "arithmetic",
acc_cella_0.sum_lutc_input = "cin",
acc_cella_0.synch_mode = "on",
acc_cella_0.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_1
(
.aclr(aclr),
.cin(wire_acc_cella_0cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_1cout[0:0]),
.dataa(wire_acc_cella_dataa[1:1]),
.datab(wire_acc_cella_datab[1:1]),
.datac(wire_acc_cella_datac[1:1]),
.ena(clken),
.regout(wire_acc_cella_regout[1:1]),
.sload(sload));
defparam
acc_cella_1.cin_used = "true",
acc_cella_1.lut_mask = "96e8",
acc_cella_1.operation_mode = "arithmetic",
acc_cella_1.sum_lutc_input = "cin",
acc_cella_1.synch_mode = "on",
acc_cella_1.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_2
(
.aclr(aclr),
.cin(wire_acc_cella_1cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_2cout[0:0]),
.dataa(wire_acc_cella_dataa[2:2]),
.datab(wire_acc_cella_datab[2:2]),
.datac(wire_acc_cella_datac[2:2]),
.ena(clken),
.regout(wire_acc_cella_regout[2:2]),
.sload(sload));
defparam
acc_cella_2.cin_used = "true",
acc_cella_2.lut_mask = "96e8",
acc_cella_2.operation_mode = "arithmetic",
acc_cella_2.sum_lutc_input = "cin",
acc_cella_2.synch_mode = "on",
acc_cella_2.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_3
(
.aclr(aclr),
.cin(wire_acc_cella_2cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_3cout[0:0]),
.dataa(wire_acc_cella_dataa[3:3]),
.datab(wire_acc_cella_datab[3:3]),
.datac(wire_acc_cella_datac[3:3]),
.ena(clken),
.regout(wire_acc_cella_regout[3:3]),
.sload(sload));
defparam
acc_cella_3.cin_used = "true",
acc_cella_3.lut_mask = "96e8",
acc_cella_3.operation_mode = "arithmetic",
acc_cella_3.sum_lutc_input = "cin",
acc_cella_3.synch_mode = "on",
acc_cella_3.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_4
(
.aclr(aclr),
.cin(wire_acc_cella_3cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_4cout[0:0]),
.dataa(wire_acc_cella_dataa[4:4]),
.datab(wire_acc_cella_datab[4:4]),
.datac(wire_acc_cella_datac[4:4]),
.ena(clken),
.regout(wire_acc_cella_regout[4:4]),
.sload(sload));
defparam
acc_cella_4.cin_used = "true",
acc_cella_4.lut_mask = "96e8",
acc_cella_4.operation_mode = "arithmetic",
acc_cella_4.sum_lutc_input = "cin",
acc_cella_4.synch_mode = "on",
acc_cella_4.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_5
(
.aclr(aclr),
.cin(wire_acc_cella_4cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_5cout[0:0]),
.dataa(wire_acc_cella_dataa[5:5]),
.datab(wire_acc_cella_datab[5:5]),
.datac(wire_acc_cella_datac[5:5]),
.ena(clken),
.regout(wire_acc_cella_regout[5:5]),
.sload(sload));
defparam
acc_cella_5.cin_used = "true",
acc_cella_5.lut_mask = "96e8",
acc_cella_5.operation_mode = "arithmetic",
acc_cella_5.sum_lutc_input = "cin",
acc_cella_5.synch_mode = "on",
acc_cella_5.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_6
(
.aclr(aclr),
.cin(wire_acc_cella_5cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_6cout[0:0]),
.dataa(wire_acc_cella_dataa[6:6]),
.datab(wire_acc_cella_datab[6:6]),
.datac(wire_acc_cella_datac[6:6]),
.ena(clken),
.regout(wire_acc_cella_regout[6:6]),
.sload(sload));
defparam
acc_cella_6.cin_used = "true",
acc_cella_6.lut_mask = "96e8",
acc_cella_6.operation_mode = "arithmetic",
acc_cella_6.sum_lutc_input = "cin",
acc_cella_6.synch_mode = "on",
acc_cella_6.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_7
(
.aclr(aclr),
.cin(wire_acc_cella_6cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_7cout[0:0]),
.dataa(wire_acc_cella_dataa[7:7]),
.datab(wire_acc_cella_datab[7:7]),
.datac(wire_acc_cella_datac[7:7]),
.ena(clken),
.regout(wire_acc_cella_regout[7:7]),
.sload(sload));
defparam
acc_cella_7.cin_used = "true",
acc_cella_7.lut_mask = "96e8",
acc_cella_7.operation_mode = "arithmetic",
acc_cella_7.sum_lutc_input = "cin",
acc_cella_7.synch_mode = "on",
acc_cella_7.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_8
(
.aclr(aclr),
.cin(wire_acc_cella_7cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_8cout[0:0]),
.dataa(wire_acc_cella_dataa[8:8]),
.datab(wire_acc_cella_datab[8:8]),
.datac(wire_acc_cella_datac[8:8]),
.ena(clken),
.regout(wire_acc_cella_regout[8:8]),
.sload(sload));
defparam
acc_cella_8.cin_used = "true",
acc_cella_8.lut_mask = "96e8",
acc_cella_8.operation_mode = "arithmetic",
acc_cella_8.sum_lutc_input = "cin",
acc_cella_8.synch_mode = "on",
acc_cella_8.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_9
(
.aclr(aclr),
.cin(wire_acc_cella_8cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_9cout[0:0]),
.dataa(wire_acc_cella_dataa[9:9]),
.datab(wire_acc_cella_datab[9:9]),
.datac(wire_acc_cella_datac[9:9]),
.ena(clken),
.regout(wire_acc_cella_regout[9:9]),
.sload(sload));
defparam
acc_cella_9.cin_used = "true",
acc_cella_9.lut_mask = "96e8",
acc_cella_9.operation_mode = "arithmetic",
acc_cella_9.sum_lutc_input = "cin",
acc_cella_9.synch_mode = "on",
acc_cella_9.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_10
(
.aclr(aclr),
.cin(wire_acc_cella_9cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_10cout[0:0]),
.dataa(wire_acc_cella_dataa[10:10]),
.datab(wire_acc_cella_datab[10:10]),
.datac(wire_acc_cella_datac[10:10]),
.ena(clken),
.regout(wire_acc_cella_regout[10:10]),
.sload(sload));
defparam
acc_cella_10.cin_used = "true",
acc_cella_10.lut_mask = "96e8",
acc_cella_10.operation_mode = "arithmetic",
acc_cella_10.sum_lutc_input = "cin",
acc_cella_10.synch_mode = "on",
acc_cella_10.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_11
(
.aclr(aclr),
.cin(wire_acc_cella_10cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_11cout[0:0]),
.dataa(wire_acc_cella_dataa[11:11]),
.datab(wire_acc_cella_datab[11:11]),
.datac(wire_acc_cella_datac[11:11]),
.ena(clken),
.regout(wire_acc_cella_regout[11:11]),
.sload(sload));
defparam
acc_cella_11.cin_used = "true",
acc_cella_11.lut_mask = "96e8",
acc_cella_11.operation_mode = "arithmetic",
acc_cella_11.sum_lutc_input = "cin",
acc_cella_11.synch_mode = "on",
acc_cella_11.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_12
(
.aclr(aclr),
.cin(wire_acc_cella_11cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_12cout[0:0]),
.dataa(wire_acc_cella_dataa[12:12]),
.datab(wire_acc_cella_datab[12:12]),
.datac(wire_acc_cella_datac[12:12]),
.ena(clken),
.regout(wire_acc_cella_regout[12:12]),
.sload(sload));
defparam
acc_cella_12.cin_used = "true",
acc_cella_12.lut_mask = "96e8",
acc_cella_12.operation_mode = "arithmetic",
acc_cella_12.sum_lutc_input = "cin",
acc_cella_12.synch_mode = "on",
acc_cella_12.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_13
(
.aclr(aclr),
.cin(wire_acc_cella_12cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_13cout[0:0]),
.dataa(wire_acc_cella_dataa[13:13]),
.datab(wire_acc_cella_datab[13:13]),
.datac(wire_acc_cella_datac[13:13]),
.ena(clken),
.regout(wire_acc_cella_regout[13:13]),
.sload(sload));
defparam
acc_cella_13.cin_used = "true",
acc_cella_13.lut_mask = "96e8",
acc_cella_13.operation_mode = "arithmetic",
acc_cella_13.sum_lutc_input = "cin",
acc_cella_13.synch_mode = "on",
acc_cella_13.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_14
(
.aclr(aclr),
.cin(wire_acc_cella_13cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_14cout[0:0]),
.dataa(wire_acc_cella_dataa[14:14]),
.datab(wire_acc_cella_datab[14:14]),
.datac(wire_acc_cella_datac[14:14]),
.ena(clken),
.regout(wire_acc_cella_regout[14:14]),
.sload(sload));
defparam
acc_cella_14.cin_used = "true",
acc_cella_14.lut_mask = "96e8",
acc_cella_14.operation_mode = "arithmetic",
acc_cella_14.sum_lutc_input = "cin",
acc_cella_14.synch_mode = "on",
acc_cella_14.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_15
(
.aclr(aclr),
.cin(wire_acc_cella_14cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_15cout[0:0]),
.dataa(wire_acc_cella_dataa[15:15]),
.datab(wire_acc_cella_datab[15:15]),
.datac(wire_acc_cella_datac[15:15]),
.ena(clken),
.regout(wire_acc_cella_regout[15:15]),
.sload(sload));
defparam
acc_cella_15.cin_used = "true",
acc_cella_15.lut_mask = "96e8",
acc_cella_15.operation_mode = "arithmetic",
acc_cella_15.sum_lutc_input = "cin",
acc_cella_15.synch_mode = "on",
acc_cella_15.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_16
(
.aclr(aclr),
.cin(wire_acc_cella_15cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_16cout[0:0]),
.dataa(wire_acc_cella_dataa[16:16]),
.datab(wire_acc_cella_datab[16:16]),
.datac(wire_acc_cella_datac[16:16]),
.ena(clken),
.regout(wire_acc_cella_regout[16:16]),
.sload(sload));
defparam
acc_cella_16.cin_used = "true",
acc_cella_16.lut_mask = "96e8",
acc_cella_16.operation_mode = "arithmetic",
acc_cella_16.sum_lutc_input = "cin",
acc_cella_16.synch_mode = "on",
acc_cella_16.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_17
(
.aclr(aclr),
.cin(wire_acc_cella_16cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_17cout[0:0]),
.dataa(wire_acc_cella_dataa[17:17]),
.datab(wire_acc_cella_datab[17:17]),
.datac(wire_acc_cella_datac[17:17]),
.ena(clken),
.regout(wire_acc_cella_regout[17:17]),
.sload(sload));
defparam
acc_cella_17.cin_used = "true",
acc_cella_17.lut_mask = "96e8",
acc_cella_17.operation_mode = "arithmetic",
acc_cella_17.sum_lutc_input = "cin",
acc_cella_17.synch_mode = "on",
acc_cella_17.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_18
(
.aclr(aclr),
.cin(wire_acc_cella_17cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_18cout[0:0]),
.dataa(wire_acc_cella_dataa[18:18]),
.datab(wire_acc_cella_datab[18:18]),
.datac(wire_acc_cella_datac[18:18]),
.ena(clken),
.regout(wire_acc_cella_regout[18:18]),
.sload(sload));
defparam
acc_cella_18.cin_used = "true",
acc_cella_18.lut_mask = "96e8",
acc_cella_18.operation_mode = "arithmetic",
acc_cella_18.sum_lutc_input = "cin",
acc_cella_18.synch_mode = "on",
acc_cella_18.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_19
(
.aclr(aclr),
.cin(wire_acc_cella_18cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_19cout[0:0]),
.dataa(wire_acc_cella_dataa[19:19]),
.datab(wire_acc_cella_datab[19:19]),
.datac(wire_acc_cella_datac[19:19]),
.ena(clken),
.regout(wire_acc_cella_regout[19:19]),
.sload(sload));
defparam
acc_cella_19.cin_used = "true",
acc_cella_19.lut_mask = "96e8",
acc_cella_19.operation_mode = "arithmetic",
acc_cella_19.sum_lutc_input = "cin",
acc_cella_19.synch_mode = "on",
acc_cella_19.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_20
(
.aclr(aclr),
.cin(wire_acc_cella_19cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_20cout[0:0]),
.dataa(wire_acc_cella_dataa[20:20]),
.datab(wire_acc_cella_datab[20:20]),
.datac(wire_acc_cella_datac[20:20]),
.ena(clken),
.regout(wire_acc_cella_regout[20:20]),
.sload(sload));
defparam
acc_cella_20.cin_used = "true",
acc_cella_20.lut_mask = "96e8",
acc_cella_20.operation_mode = "arithmetic",
acc_cella_20.sum_lutc_input = "cin",
acc_cella_20.synch_mode = "on",
acc_cella_20.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_21
(
.aclr(aclr),
.cin(wire_acc_cella_20cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_21cout[0:0]),
.dataa(wire_acc_cella_dataa[21:21]),
.datab(wire_acc_cella_datab[21:21]),
.datac(wire_acc_cella_datac[21:21]),
.ena(clken),
.regout(wire_acc_cella_regout[21:21]),
.sload(sload));
defparam
acc_cella_21.cin_used = "true",
acc_cella_21.lut_mask = "96e8",
acc_cella_21.operation_mode = "arithmetic",
acc_cella_21.sum_lutc_input = "cin",
acc_cella_21.synch_mode = "on",
acc_cella_21.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_22
(
.aclr(aclr),
.cin(wire_acc_cella_21cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_22cout[0:0]),
.dataa(wire_acc_cella_dataa[22:22]),
.datab(wire_acc_cella_datab[22:22]),
.datac(wire_acc_cella_datac[22:22]),
.ena(clken),
.regout(wire_acc_cella_regout[22:22]),
.sload(sload));
defparam
acc_cella_22.cin_used = "true",
acc_cella_22.lut_mask = "96e8",
acc_cella_22.operation_mode = "arithmetic",
acc_cella_22.sum_lutc_input = "cin",
acc_cella_22.synch_mode = "on",
acc_cella_22.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_23
(
.aclr(aclr),
.cin(wire_acc_cella_22cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_23cout[0:0]),
.dataa(wire_acc_cella_dataa[23:23]),
.datab(wire_acc_cella_datab[23:23]),
.datac(wire_acc_cella_datac[23:23]),
.ena(clken),
.regout(wire_acc_cella_regout[23:23]),
.sload(sload));
defparam
acc_cella_23.cin_used = "true",
acc_cella_23.lut_mask = "96e8",
acc_cella_23.operation_mode = "arithmetic",
acc_cella_23.sum_lutc_input = "cin",
acc_cella_23.synch_mode = "on",
acc_cella_23.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_24
(
.aclr(aclr),
.cin(wire_acc_cella_23cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_24cout[0:0]),
.dataa(wire_acc_cella_dataa[24:24]),
.datab(wire_acc_cella_datab[24:24]),
.datac(wire_acc_cella_datac[24:24]),
.ena(clken),
.regout(wire_acc_cella_regout[24:24]),
.sload(sload));
defparam
acc_cella_24.cin_used = "true",
acc_cella_24.lut_mask = "96e8",
acc_cella_24.operation_mode = "arithmetic",
acc_cella_24.sum_lutc_input = "cin",
acc_cella_24.synch_mode = "on",
acc_cella_24.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_25
(
.aclr(aclr),
.cin(wire_acc_cella_24cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_25cout[0:0]),
.dataa(wire_acc_cella_dataa[25:25]),
.datab(wire_acc_cella_datab[25:25]),
.datac(wire_acc_cella_datac[25:25]),
.ena(clken),
.regout(wire_acc_cella_regout[25:25]),
.sload(sload));
defparam
acc_cella_25.cin_used = "true",
acc_cella_25.lut_mask = "96e8",
acc_cella_25.operation_mode = "arithmetic",
acc_cella_25.sum_lutc_input = "cin",
acc_cella_25.synch_mode = "on",
acc_cella_25.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_26
(
.aclr(aclr),
.cin(wire_acc_cella_25cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_26cout[0:0]),
.dataa(wire_acc_cella_dataa[26:26]),
.datab(wire_acc_cella_datab[26:26]),
.datac(wire_acc_cella_datac[26:26]),
.ena(clken),
.regout(wire_acc_cella_regout[26:26]),
.sload(sload));
defparam
acc_cella_26.cin_used = "true",
acc_cella_26.lut_mask = "96e8",
acc_cella_26.operation_mode = "arithmetic",
acc_cella_26.sum_lutc_input = "cin",
acc_cella_26.synch_mode = "on",
acc_cella_26.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_27
(
.aclr(aclr),
.cin(wire_acc_cella_26cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_27cout[0:0]),
.dataa(wire_acc_cella_dataa[27:27]),
.datab(wire_acc_cella_datab[27:27]),
.datac(wire_acc_cella_datac[27:27]),
.ena(clken),
.regout(wire_acc_cella_regout[27:27]),
.sload(sload));
defparam
acc_cella_27.cin_used = "true",
acc_cella_27.lut_mask = "96e8",
acc_cella_27.operation_mode = "arithmetic",
acc_cella_27.sum_lutc_input = "cin",
acc_cella_27.synch_mode = "on",
acc_cella_27.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_28
(
.aclr(aclr),
.cin(wire_acc_cella_27cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_28cout[0:0]),
.dataa(wire_acc_cella_dataa[28:28]),
.datab(wire_acc_cella_datab[28:28]),
.datac(wire_acc_cella_datac[28:28]),
.ena(clken),
.regout(wire_acc_cella_regout[28:28]),
.sload(sload));
defparam
acc_cella_28.cin_used = "true",
acc_cella_28.lut_mask = "96e8",
acc_cella_28.operation_mode = "arithmetic",
acc_cella_28.sum_lutc_input = "cin",
acc_cella_28.synch_mode = "on",
acc_cella_28.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_29
(
.aclr(aclr),
.cin(wire_acc_cella_28cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_29cout[0:0]),
.dataa(wire_acc_cella_dataa[29:29]),
.datab(wire_acc_cella_datab[29:29]),
.datac(wire_acc_cella_datac[29:29]),
.ena(clken),
.regout(wire_acc_cella_regout[29:29]),
.sload(sload));
defparam
acc_cella_29.cin_used = "true",
acc_cella_29.lut_mask = "96e8",
acc_cella_29.operation_mode = "arithmetic",
acc_cella_29.sum_lutc_input = "cin",
acc_cella_29.synch_mode = "on",
acc_cella_29.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_30
(
.aclr(aclr),
.cin(wire_acc_cella_29cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_30cout[0:0]),
.dataa(wire_acc_cella_dataa[30:30]),
.datab(wire_acc_cella_datab[30:30]),
.datac(wire_acc_cella_datac[30:30]),
.ena(clken),
.regout(wire_acc_cella_regout[30:30]),
.sload(sload));
defparam
acc_cella_30.cin_used = "true",
acc_cella_30.lut_mask = "96e8",
acc_cella_30.operation_mode = "arithmetic",
acc_cella_30.sum_lutc_input = "cin",
acc_cella_30.synch_mode = "on",
acc_cella_30.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_31
(
.aclr(aclr),
.cin(wire_acc_cella_30cout[0:0]),
.clk(clock),
.dataa(wire_acc_cella_dataa[31:31]),
.datab(wire_acc_cella_datab[31:31]),
.datac(wire_acc_cella_datac[31:31]),
.ena(clken),
.regout(wire_acc_cella_regout[31:31]),
.sload(sload));
defparam
acc_cella_31.cin_used = "true",
acc_cella_31.lut_mask = "9696",
acc_cella_31.operation_mode = "normal",
acc_cella_31.sum_lutc_input = "cin",
acc_cella_31.synch_mode = "on",
acc_cella_31.lpm_type = "stratix_lcell";
assign
wire_acc_cella_dataa = data,
wire_acc_cella_datab = wire_acc_cella_regout,
wire_acc_cella_datac = data;
assign
result = wire_acc_cella_regout,
sload = 1'b0;
endmodule //accum32_accum_nta
//VALID FILE
module accum32 (
data,
clock,
clken,
aclr,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] data;
input clock;
input clken;
input aclr;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
accum32_accum_nta accum32_accum_nta_component (
.clken (clken),
.aclr (aclr),
.clock (clock),
.data (data),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: WIDTH_IN NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "32"
// Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: ADD_SUB NUMERIC "0"
// Retrieval info: PRIVATE: CIN NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
// Retrieval info: PRIVATE: COUT NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW NUMERIC "0"
// Retrieval info: PRIVATE: LATENCY NUMERIC "0"
// Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: WIDTH_IN NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "32"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:16:09 07/10/2009
// Design Name:
// Module Name: spi
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spi(
input clk,
input SCK,
input MOSI,
inout MISO,
input SSEL,
output cmd_ready,
output param_ready,
output [7:0] cmd_data,
output [7:0] param_data,
output endmessage,
output startmessage,
input [7:0] input_data,
output [31:0] byte_cnt,
output [2:0] bit_cnt
);
reg [7:0] cmd_data_r;
reg [7:0] param_data_r;
reg [2:0] SSELr;
reg [2:0] SSELSCKr;
always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
always @(posedge SCK) SSELSCKr <= {SSELSCKr[1:0], SSEL};
wire SSEL_inactive = SSELr[1];
wire SSEL_active = ~SSELr[1]; // SSEL is active low
wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge
assign endmessage = SSEL_endmessage;
assign startmessage = SSEL_startmessage;
// bit count for one SPI byte + byte count for the message
reg [2:0] bitcnt;
initial bitcnt = 3'b000;
wire bitcnt_msb = bitcnt[2];
reg [2:0] bitcnt_wrap_r;
always @(posedge clk) bitcnt_wrap_r <= {bitcnt_wrap_r[1:0], bitcnt_msb};
wire byte_received_sync = (bitcnt_wrap_r[2:1] == 2'b10);
reg [31:0] byte_cnt_r;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
assign bit_cnt = bitcnt;
always @(posedge SCK) begin
if(SSELSCKr[1]) bitcnt <= 3'b000;
else bitcnt <= bitcnt + 3'b001;
end
always @(posedge SCK) begin
if(~SSELSCKr[1])
byte_data_received <= {byte_data_received[6:0], MOSI};
if(~SSELSCKr[1] && bitcnt==3'b111)
byte_received <= 1'b1;
else byte_received <= 1'b0;
end
//reg [2:0] byte_received_r;
//always @(posedge clk) byte_received_r <= {byte_received_r[1:0], byte_received};
//wire byte_received_sync = (byte_received_r[2:1] == 2'b01);
always @(posedge clk) begin
if(SSEL_inactive)
byte_cnt_r <= 16'h0000;
else if(byte_received_sync)
byte_cnt_r <= byte_cnt_r + 16'h0001;
end
reg [7:0] byte_data_sent;
assign MISO = ~SSEL ? input_data[7-bitcnt] : 1'bZ; // send MSB first
reg cmd_ready_r;
reg param_ready_r;
reg cmd_ready_r2;
reg param_ready_r2;
assign cmd_ready = cmd_ready_r;
assign param_ready = param_ready_r;
assign cmd_data = cmd_data_r;
assign param_data = param_data_r;
assign byte_cnt = byte_cnt_r;
always @(posedge clk) cmd_ready_r2 = byte_received_sync && byte_cnt_r == 32'h0;
always @(posedge clk) param_ready_r2 = byte_received_sync && byte_cnt_r > 32'h0;
// fill registers
always @(posedge clk) begin
if (SSEL_startmessage)
cmd_data_r <= 8'h00;
else if(cmd_ready_r2)
cmd_data_r <= byte_data_received;
else if(param_ready_r2)
param_data_r <= byte_data_received;
end
// delay ready signals by one clock
always @(posedge clk) begin
cmd_ready_r <= cmd_ready_r2;
param_ready_r <= param_ready_r2;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:16:09 07/10/2009
// Design Name:
// Module Name: spi
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spi(
input clk,
input SCK,
input MOSI,
inout MISO,
input SSEL,
output cmd_ready,
output param_ready,
output [7:0] cmd_data,
output [7:0] param_data,
output endmessage,
output startmessage,
input [7:0] input_data,
output [31:0] byte_cnt,
output [2:0] bit_cnt
);
reg [7:0] cmd_data_r;
reg [7:0] param_data_r;
reg [2:0] SSELr;
reg [2:0] SSELSCKr;
always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
always @(posedge SCK) SSELSCKr <= {SSELSCKr[1:0], SSEL};
wire SSEL_inactive = SSELr[1];
wire SSEL_active = ~SSELr[1]; // SSEL is active low
wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge
assign endmessage = SSEL_endmessage;
assign startmessage = SSEL_startmessage;
// bit count for one SPI byte + byte count for the message
reg [2:0] bitcnt;
initial bitcnt = 3'b000;
wire bitcnt_msb = bitcnt[2];
reg [2:0] bitcnt_wrap_r;
always @(posedge clk) bitcnt_wrap_r <= {bitcnt_wrap_r[1:0], bitcnt_msb};
wire byte_received_sync = (bitcnt_wrap_r[2:1] == 2'b10);
reg [31:0] byte_cnt_r;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
assign bit_cnt = bitcnt;
always @(posedge SCK) begin
if(SSELSCKr[1]) bitcnt <= 3'b000;
else bitcnt <= bitcnt + 3'b001;
end
always @(posedge SCK) begin
if(~SSELSCKr[1])
byte_data_received <= {byte_data_received[6:0], MOSI};
if(~SSELSCKr[1] && bitcnt==3'b111)
byte_received <= 1'b1;
else byte_received <= 1'b0;
end
//reg [2:0] byte_received_r;
//always @(posedge clk) byte_received_r <= {byte_received_r[1:0], byte_received};
//wire byte_received_sync = (byte_received_r[2:1] == 2'b01);
always @(posedge clk) begin
if(SSEL_inactive)
byte_cnt_r <= 16'h0000;
else if(byte_received_sync)
byte_cnt_r <= byte_cnt_r + 16'h0001;
end
reg [7:0] byte_data_sent;
assign MISO = ~SSEL ? input_data[7-bitcnt] : 1'bZ; // send MSB first
reg cmd_ready_r;
reg param_ready_r;
reg cmd_ready_r2;
reg param_ready_r2;
assign cmd_ready = cmd_ready_r;
assign param_ready = param_ready_r;
assign cmd_data = cmd_data_r;
assign param_data = param_data_r;
assign byte_cnt = byte_cnt_r;
always @(posedge clk) cmd_ready_r2 = byte_received_sync && byte_cnt_r == 32'h0;
always @(posedge clk) param_ready_r2 = byte_received_sync && byte_cnt_r > 32'h0;
// fill registers
always @(posedge clk) begin
if (SSEL_startmessage)
cmd_data_r <= 8'h00;
else if(cmd_ready_r2)
cmd_data_r <= byte_data_received;
else if(param_ready_r2)
param_data_r <= byte_data_received;
end
// delay ready signals by one clock
always @(posedge clk) begin
cmd_ready_r <= cmd_ready_r2;
param_ready_r <= param_ready_r2;
end
endmodule
|
// Model of FIFO in Altera
module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 16;
parameter depth = 1024;
parameter addr_bits = 10;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [width-1:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [width-1:0] q;
output rdfull;
output rdempty;
output reg [addr_bits-1:0] rdusedw;
output wrfull;
output wrempty;
output reg [addr_bits-1:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [addr_bits-1:0] rdptr;
reg [addr_bits-1:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
assign wrempty = (wrusedw == 0);
assign wrfull = (wrusedw == depth-1);
assign rdempty = (rdusedw == 0);
assign rdfull = (rdusedw == depth-1);
endmodule // fifo
|
// Model of FIFO in Altera
module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 16;
parameter depth = 1024;
parameter addr_bits = 10;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [width-1:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [width-1:0] q;
output rdfull;
output rdempty;
output reg [addr_bits-1:0] rdusedw;
output wrfull;
output wrempty;
output reg [addr_bits-1:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [addr_bits-1:0] rdptr;
reg [addr_bits-1:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
assign wrempty = (wrusedw == 0);
assign wrfull = (wrusedw == depth-1);
assign rdempty = (rdusedw == 0);
assign rdfull = (rdusedw == depth-1);
endmodule // fifo
|
// Model of FIFO in Altera
module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 16;
parameter depth = 1024;
parameter addr_bits = 10;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [width-1:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [width-1:0] q;
output rdfull;
output rdempty;
output reg [addr_bits-1:0] rdusedw;
output wrfull;
output wrempty;
output reg [addr_bits-1:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [addr_bits-1:0] rdptr;
reg [addr_bits-1:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
assign wrempty = (wrusedw == 0);
assign wrfull = (wrusedw == depth-1);
assign rdempty = (rdusedw == 0);
assign rdfull = (rdusedw == depth-1);
endmodule // fifo
|
// Bidirectional registers
module bidir_reg
( inout wire [15:0] tristate,
input wire [15:0] oe,
input wire [15:0] reg_val );
// This would be much cleaner if all the tools
// supported "for generate"........
assign tristate[0] = oe[0] ? reg_val[0] : 1'bz;
assign tristate[1] = oe[1] ? reg_val[1] : 1'bz;
assign tristate[2] = oe[2] ? reg_val[2] : 1'bz;
assign tristate[3] = oe[3] ? reg_val[3] : 1'bz;
assign tristate[4] = oe[4] ? reg_val[4] : 1'bz;
assign tristate[5] = oe[5] ? reg_val[5] : 1'bz;
assign tristate[6] = oe[6] ? reg_val[6] : 1'bz;
assign tristate[7] = oe[7] ? reg_val[7] : 1'bz;
assign tristate[8] = oe[8] ? reg_val[8] : 1'bz;
assign tristate[9] = oe[9] ? reg_val[9] : 1'bz;
assign tristate[10] = oe[10] ? reg_val[10] : 1'bz;
assign tristate[11] = oe[11] ? reg_val[11] : 1'bz;
assign tristate[12] = oe[12] ? reg_val[12] : 1'bz;
assign tristate[13] = oe[13] ? reg_val[13] : 1'bz;
assign tristate[14] = oe[14] ? reg_val[14] : 1'bz;
assign tristate[15] = oe[15] ? reg_val[15] : 1'bz;
endmodule // bidir_reg
|
// Bidirectional registers
module bidir_reg
( inout wire [15:0] tristate,
input wire [15:0] oe,
input wire [15:0] reg_val );
// This would be much cleaner if all the tools
// supported "for generate"........
assign tristate[0] = oe[0] ? reg_val[0] : 1'bz;
assign tristate[1] = oe[1] ? reg_val[1] : 1'bz;
assign tristate[2] = oe[2] ? reg_val[2] : 1'bz;
assign tristate[3] = oe[3] ? reg_val[3] : 1'bz;
assign tristate[4] = oe[4] ? reg_val[4] : 1'bz;
assign tristate[5] = oe[5] ? reg_val[5] : 1'bz;
assign tristate[6] = oe[6] ? reg_val[6] : 1'bz;
assign tristate[7] = oe[7] ? reg_val[7] : 1'bz;
assign tristate[8] = oe[8] ? reg_val[8] : 1'bz;
assign tristate[9] = oe[9] ? reg_val[9] : 1'bz;
assign tristate[10] = oe[10] ? reg_val[10] : 1'bz;
assign tristate[11] = oe[11] ? reg_val[11] : 1'bz;
assign tristate[12] = oe[12] ? reg_val[12] : 1'bz;
assign tristate[13] = oe[13] ? reg_val[13] : 1'bz;
assign tristate[14] = oe[14] ? reg_val[14] : 1'bz;
assign tristate[15] = oe[15] ? reg_val[15] : 1'bz;
endmodule // bidir_reg
|
// megafunction wizard: %LPM_ADD_SUB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_add_sub
// ============================================================
// File Name: mylpm_addsub.v
// Megafunction Name(s):
// lpm_add_sub
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module mylpm_addsub (
add_sub,
dataa,
datab,
clock,
result);
input add_sub;
input [15:0] dataa;
input [15:0] datab;
input clock;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
lpm_add_sub lpm_add_sub_component (
.dataa (dataa),
.add_sub (add_sub),
.datab (datab),
.clock (clock),
.result (sub_wire0));
defparam
lpm_add_sub_component.lpm_width = 16,
lpm_add_sub_component.lpm_direction = "UNUSED",
lpm_add_sub_component.lpm_type = "LPM_ADD_SUB",
lpm_add_sub_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO",
lpm_add_sub_component.lpm_pipeline = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: Function NUMERIC "2"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0]
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
// megafunction wizard: %LPM_ADD_SUB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_add_sub
// ============================================================
// File Name: mylpm_addsub.v
// Megafunction Name(s):
// lpm_add_sub
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module mylpm_addsub (
add_sub,
dataa,
datab,
clock,
result);
input add_sub;
input [15:0] dataa;
input [15:0] datab;
input clock;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
lpm_add_sub lpm_add_sub_component (
.dataa (dataa),
.add_sub (add_sub),
.datab (datab),
.clock (clock),
.result (sub_wire0));
defparam
lpm_add_sub_component.lpm_width = 16,
lpm_add_sub_component.lpm_direction = "UNUSED",
lpm_add_sub_component.lpm_type = "LPM_ADD_SUB",
lpm_add_sub_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO",
lpm_add_sub_component.lpm_pipeline = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: Function NUMERIC "2"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0]
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module atr_delay(clk_i,rst_i,ena_i,tx_empty_i,tx_delay_i,rx_delay_i,atr_tx_o);
input clk_i;
input rst_i;
input ena_i;
input tx_empty_i;
input [11:0] tx_delay_i;
input [11:0] rx_delay_i;
output atr_tx_o;
reg [3:0] state;
reg [11:0] count;
`define ST_RX_DELAY 4'b0001
`define ST_RX 4'b0010
`define ST_TX_DELAY 4'b0100
`define ST_TX 4'b1000
always @(posedge clk_i)
if (rst_i | ~ena_i)
begin
state <= `ST_RX;
count <= 12'b0;
end
else
case (state)
`ST_RX:
if (!tx_empty_i)
begin
state <= `ST_TX_DELAY;
count <= tx_delay_i;
end
`ST_TX_DELAY:
if (count == 0)
state <= `ST_TX;
else
count <= count - 1;
`ST_TX:
if (tx_empty_i)
begin
state <= `ST_RX_DELAY;
count <= rx_delay_i;
end
`ST_RX_DELAY:
if (count == 0)
state <= `ST_RX;
else
count <= count - 1;
default: // Error
begin
state <= `ST_RX;
count <= 0;
end
endcase
assign atr_tx_o = (state == `ST_TX) | (state == `ST_RX_DELAY);
endmodule // atr_delay
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module atr_delay(clk_i,rst_i,ena_i,tx_empty_i,tx_delay_i,rx_delay_i,atr_tx_o);
input clk_i;
input rst_i;
input ena_i;
input tx_empty_i;
input [11:0] tx_delay_i;
input [11:0] rx_delay_i;
output atr_tx_o;
reg [3:0] state;
reg [11:0] count;
`define ST_RX_DELAY 4'b0001
`define ST_RX 4'b0010
`define ST_TX_DELAY 4'b0100
`define ST_TX 4'b1000
always @(posedge clk_i)
if (rst_i | ~ena_i)
begin
state <= `ST_RX;
count <= 12'b0;
end
else
case (state)
`ST_RX:
if (!tx_empty_i)
begin
state <= `ST_TX_DELAY;
count <= tx_delay_i;
end
`ST_TX_DELAY:
if (count == 0)
state <= `ST_TX;
else
count <= count - 1;
`ST_TX:
if (tx_empty_i)
begin
state <= `ST_RX_DELAY;
count <= rx_delay_i;
end
`ST_RX_DELAY:
if (count == 0)
state <= `ST_RX;
else
count <= count - 1;
default: // Error
begin
state <= `ST_RX;
count <= 0;
end
endcase
assign atr_tx_o = (state == `ST_TX) | (state == `ST_RX_DELAY);
endmodule // atr_delay
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module atr_delay(clk_i,rst_i,ena_i,tx_empty_i,tx_delay_i,rx_delay_i,atr_tx_o);
input clk_i;
input rst_i;
input ena_i;
input tx_empty_i;
input [11:0] tx_delay_i;
input [11:0] rx_delay_i;
output atr_tx_o;
reg [3:0] state;
reg [11:0] count;
`define ST_RX_DELAY 4'b0001
`define ST_RX 4'b0010
`define ST_TX_DELAY 4'b0100
`define ST_TX 4'b1000
always @(posedge clk_i)
if (rst_i | ~ena_i)
begin
state <= `ST_RX;
count <= 12'b0;
end
else
case (state)
`ST_RX:
if (!tx_empty_i)
begin
state <= `ST_TX_DELAY;
count <= tx_delay_i;
end
`ST_TX_DELAY:
if (count == 0)
state <= `ST_TX;
else
count <= count - 1;
`ST_TX:
if (tx_empty_i)
begin
state <= `ST_RX_DELAY;
count <= rx_delay_i;
end
`ST_RX_DELAY:
if (count == 0)
state <= `ST_RX;
else
count <= count - 1;
default: // Error
begin
state <= `ST_RX;
count <= 0;
end
endcase
assign atr_tx_o = (state == `ST_TX) | (state == `ST_RX_DELAY);
endmodule // atr_delay
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module atr_delay(clk_i,rst_i,ena_i,tx_empty_i,tx_delay_i,rx_delay_i,atr_tx_o);
input clk_i;
input rst_i;
input ena_i;
input tx_empty_i;
input [11:0] tx_delay_i;
input [11:0] rx_delay_i;
output atr_tx_o;
reg [3:0] state;
reg [11:0] count;
`define ST_RX_DELAY 4'b0001
`define ST_RX 4'b0010
`define ST_TX_DELAY 4'b0100
`define ST_TX 4'b1000
always @(posedge clk_i)
if (rst_i | ~ena_i)
begin
state <= `ST_RX;
count <= 12'b0;
end
else
case (state)
`ST_RX:
if (!tx_empty_i)
begin
state <= `ST_TX_DELAY;
count <= tx_delay_i;
end
`ST_TX_DELAY:
if (count == 0)
state <= `ST_TX;
else
count <= count - 1;
`ST_TX:
if (tx_empty_i)
begin
state <= `ST_RX_DELAY;
count <= rx_delay_i;
end
`ST_RX_DELAY:
if (count == 0)
state <= `ST_RX;
else
count <= count - 1;
default: // Error
begin
state <= `ST_RX;
count <= 0;
end
endcase
assign atr_tx_o = (state == `ST_TX) | (state == `ST_RX_DELAY);
endmodule // atr_delay
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module strobe_gen
( input clock,
input reset,
input enable,
input [7:0] rate, // Rate should be 1 LESS THAN your desired divide ratio
input strobe_in,
output wire strobe );
// parameter width = 8;
reg [7:0] counter;
assign strobe = ~|counter && enable && strobe_in;
always @(posedge clock)
if(reset | ~enable)
counter <= #1 8'd0;
else if(strobe_in)
if(counter == 0)
counter <= #1 rate;
else
counter <= #1 counter - 8'd1;
endmodule // strobe_gen
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cordic(clock, reset, enable, xi, yi, zi, xo, yo, zo );
parameter bitwidth = 16;
parameter zwidth = 16;
input clock;
input reset;
input enable;
input [bitwidth-1:0] xi, yi;
output [bitwidth-1:0] xo, yo;
input [zwidth-1:0] zi;
output [zwidth-1:0] zo;
reg [bitwidth+1:0] x0,y0;
reg [zwidth-2:0] z0;
wire [bitwidth+1:0] x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12;
wire [bitwidth+1:0] y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12;
wire [zwidth-2:0] z1,z2,z3,z4,z5,z6,z7,z8,z9,z10,z11,z12;
wire [bitwidth+1:0] xi_ext = {{2{xi[bitwidth-1]}},xi};
wire [bitwidth+1:0] yi_ext = {{2{yi[bitwidth-1]}},yi};
// Compute consts. Would be easier if vlog had atan...
// see gen_cordic_consts.py
`define c00 16'd8192
`define c01 16'd4836
`define c02 16'd2555
`define c03 16'd1297
`define c04 16'd651
`define c05 16'd326
`define c06 16'd163
`define c07 16'd81
`define c08 16'd41
`define c09 16'd20
`define c10 16'd10
`define c11 16'd5
`define c12 16'd3
`define c13 16'd1
`define c14 16'd1
`define c15 16'd0
`define c16 16'd0
always @(posedge clock)
if(reset)
begin
x0 <= #1 0; y0 <= #1 0; z0 <= #1 0;
end
else if(enable)
begin
z0 <= #1 zi[zwidth-2:0];
case (zi[zwidth-1:zwidth-2])
2'b00, 2'b11 :
begin
x0 <= #1 xi_ext;
y0 <= #1 yi_ext;
end
2'b01, 2'b10 :
begin
x0 <= #1 -xi_ext;
y0 <= #1 -yi_ext;
end
endcase // case(zi[zwidth-1:zwidth-2])
end // else: !if(reset)
// FIXME need to handle variable number of stages
// FIXME should be able to narrow zwidth but quartus makes it bigger...
// This would be easier if arrays worked better in vlog...
cordic_stage #(bitwidth+2,zwidth-1,0) cordic_stage0 (clock,reset,enable,x0,y0,z0,`c00,x1,y1,z1);
cordic_stage #(bitwidth+2,zwidth-1,1) cordic_stage1 (clock,reset,enable,x1,y1,z1,`c01,x2,y2,z2);
cordic_stage #(bitwidth+2,zwidth-1,2) cordic_stage2 (clock,reset,enable,x2,y2,z2,`c02,x3,y3,z3);
cordic_stage #(bitwidth+2,zwidth-1,3) cordic_stage3 (clock,reset,enable,x3,y3,z3,`c03,x4,y4,z4);
cordic_stage #(bitwidth+2,zwidth-1,4) cordic_stage4 (clock,reset,enable,x4,y4,z4,`c04,x5,y5,z5);
cordic_stage #(bitwidth+2,zwidth-1,5) cordic_stage5 (clock,reset,enable,x5,y5,z5,`c05,x6,y6,z6);
cordic_stage #(bitwidth+2,zwidth-1,6) cordic_stage6 (clock,reset,enable,x6,y6,z6,`c06,x7,y7,z7);
cordic_stage #(bitwidth+2,zwidth-1,7) cordic_stage7 (clock,reset,enable,x7,y7,z7,`c07,x8,y8,z8);
cordic_stage #(bitwidth+2,zwidth-1,8) cordic_stage8 (clock,reset,enable,x8,y8,z8,`c08,x9,y9,z9);
cordic_stage #(bitwidth+2,zwidth-1,9) cordic_stage9 (clock,reset,enable,x9,y9,z9,`c09,x10,y10,z10);
cordic_stage #(bitwidth+2,zwidth-1,10) cordic_stage10 (clock,reset,enable,x10,y10,z10,`c10,x11,y11,z11);
cordic_stage #(bitwidth+2,zwidth-1,11) cordic_stage11 (clock,reset,enable,x11,y11,z11,`c11,x12,y12,z12);
assign xo = x12[bitwidth:1];
assign yo = y12[bitwidth:1];
//assign xo = x12[bitwidth+1:2]; // CORDIC gain is ~1.6, plus gain from rotating vectors
//assign yo = y12[bitwidth+1:2];
assign zo = z12;
endmodule // cordic
|
// megafunction wizard: %FIFO%CBX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_4k.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=4096 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTHU=12 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//a_gray2bin device_family="Cyclone" WIDTH=12 bin gray
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_a_gray2bin_9m4
(
bin,
gray) /* synthesis synthesis_clearbox=1 */;
output [11:0] bin;
input [11:0] gray;
wire xor0;
wire xor1;
wire xor10;
wire xor2;
wire xor3;
wire xor4;
wire xor5;
wire xor6;
wire xor7;
wire xor8;
wire xor9;
assign
bin = {gray[11], xor10, xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0},
xor0 = (gray[0] ^ xor1),
xor1 = (gray[1] ^ xor2),
xor10 = (gray[11] ^ gray[10]),
xor2 = (gray[2] ^ xor3),
xor3 = (gray[3] ^ xor4),
xor4 = (gray[4] ^ xor5),
xor5 = (gray[5] ^ xor6),
xor6 = (gray[6] ^ xor7),
xor7 = (gray[7] ^ xor8),
xor8 = (gray[8] ^ xor9),
xor9 = (gray[9] ^ xor10);
endmodule //fifo_4k_a_gray2bin_9m4
//a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=12 aclr clock cnt_en q
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = lut 13
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_a_graycounter_826
(
aclr,
clock,
cnt_en,
q) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clock;
input cnt_en;
output [11:0] q;
wire [0:0] wire_countera_0cout;
wire [0:0] wire_countera_1cout;
wire [0:0] wire_countera_2cout;
wire [0:0] wire_countera_3cout;
wire [0:0] wire_countera_4cout;
wire [0:0] wire_countera_5cout;
wire [0:0] wire_countera_6cout;
wire [0:0] wire_countera_7cout;
wire [0:0] wire_countera_8cout;
wire [0:0] wire_countera_9cout;
wire [0:0] wire_countera_10cout;
wire [11:0] wire_countera_regout;
wire wire_parity_cout;
wire wire_parity_regout;
wire [11:0] power_modified_counter_values;
wire sclr;
wire updown;
cyclone_lcell countera_0
(
.aclr(aclr),
.cin(wire_parity_cout),
.clk(clock),
.combout(),
.cout(wire_countera_0cout[0:0]),
.dataa(cnt_en),
.datab(wire_countera_regout[0:0]),
.ena(1'b1),
.regout(wire_countera_regout[0:0]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_0.cin_used = "true",
countera_0.lut_mask = "c6a0",
countera_0.operation_mode = "arithmetic",
countera_0.sum_lutc_input = "cin",
countera_0.synch_mode = "on",
countera_0.lpm_type = "cyclone_lcell";
cyclone_lcell countera_1
(
.aclr(aclr),
.cin(wire_countera_0cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_1cout[0:0]),
.dataa(power_modified_counter_values[0]),
.datab(power_modified_counter_values[1]),
.ena(1'b1),
.regout(wire_countera_regout[1:1]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_1.cin_used = "true",
countera_1.lut_mask = "6c50",
countera_1.operation_mode = "arithmetic",
countera_1.sum_lutc_input = "cin",
countera_1.synch_mode = "on",
countera_1.lpm_type = "cyclone_lcell";
cyclone_lcell countera_2
(
.aclr(aclr),
.cin(wire_countera_1cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_2cout[0:0]),
.dataa(power_modified_counter_values[1]),
.datab(power_modified_counter_values[2]),
.ena(1'b1),
.regout(wire_countera_regout[2:2]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_2.cin_used = "true",
countera_2.lut_mask = "6c50",
countera_2.operation_mode = "arithmetic",
countera_2.sum_lutc_input = "cin",
countera_2.synch_mode = "on",
countera_2.lpm_type = "cyclone_lcell";
cyclone_lcell countera_3
(
.aclr(aclr),
.cin(wire_countera_2cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_3cout[0:0]),
.dataa(power_modified_counter_values[2]),
.datab(power_modified_counter_values[3]),
.ena(1'b1),
.regout(wire_countera_regout[3:3]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_3.cin_used = "true",
countera_3.lut_mask = "6c50",
countera_3.operation_mode = "arithmetic",
countera_3.sum_lutc_input = "cin",
countera_3.synch_mode = "on",
countera_3.lpm_type = "cyclone_lcell";
cyclone_lcell countera_4
(
.aclr(aclr),
.cin(wire_countera_3cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_4cout[0:0]),
.dataa(power_modified_counter_values[3]),
.datab(power_modified_counter_values[4]),
.ena(1'b1),
.regout(wire_countera_regout[4:4]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_4.cin_used = "true",
countera_4.lut_mask = "6c50",
countera_4.operation_mode = "arithmetic",
countera_4.sum_lutc_input = "cin",
countera_4.synch_mode = "on",
countera_4.lpm_type = "cyclone_lcell";
cyclone_lcell countera_5
(
.aclr(aclr),
.cin(wire_countera_4cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_5cout[0:0]),
.dataa(power_modified_counter_values[4]),
.datab(power_modified_counter_values[5]),
.ena(1'b1),
.regout(wire_countera_regout[5:5]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_5.cin_used = "true",
countera_5.lut_mask = "6c50",
countera_5.operation_mode = "arithmetic",
countera_5.sum_lutc_input = "cin",
countera_5.synch_mode = "on",
countera_5.lpm_type = "cyclone_lcell";
cyclone_lcell countera_6
(
.aclr(aclr),
.cin(wire_countera_5cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_6cout[0:0]),
.dataa(power_modified_counter_values[5]),
.datab(power_modified_counter_values[6]),
.ena(1'b1),
.regout(wire_countera_regout[6:6]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_6.cin_used = "true",
countera_6.lut_mask = "6c50",
countera_6.operation_mode = "arithmetic",
countera_6.sum_lutc_input = "cin",
countera_6.synch_mode = "on",
countera_6.lpm_type = "cyclone_lcell";
cyclone_lcell countera_7
(
.aclr(aclr),
.cin(wire_countera_6cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_7cout[0:0]),
.dataa(power_modified_counter_values[6]),
.datab(power_modified_counter_values[7]),
.ena(1'b1),
.regout(wire_countera_regout[7:7]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_7.cin_used = "true",
countera_7.lut_mask = "6c50",
countera_7.operation_mode = "arithmetic",
countera_7.sum_lutc_input = "cin",
countera_7.synch_mode = "on",
countera_7.lpm_type = "cyclone_lcell";
cyclone_lcell countera_8
(
.aclr(aclr),
.cin(wire_countera_7cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_8cout[0:0]),
.dataa(power_modified_counter_values[7]),
.datab(power_modified_counter_values[8]),
.ena(1'b1),
.regout(wire_countera_regout[8:8]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_8.cin_used = "true",
countera_8.lut_mask = "6c50",
countera_8.operation_mode = "arithmetic",
countera_8.sum_lutc_input = "cin",
countera_8.synch_mode = "on",
countera_8.lpm_type = "cyclone_lcell";
cyclone_lcell countera_9
(
.aclr(aclr),
.cin(wire_countera_8cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_9cout[0:0]),
.dataa(power_modified_counter_values[8]),
.datab(power_modified_counter_values[9]),
.ena(1'b1),
.regout(wire_countera_regout[9:9]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_9.cin_used = "true",
countera_9.lut_mask = "6c50",
countera_9.operation_mode = "arithmetic",
countera_9.sum_lutc_input = "cin",
countera_9.synch_mode = "on",
countera_9.lpm_type = "cyclone_lcell";
cyclone_lcell countera_10
(
.aclr(aclr),
.cin(wire_countera_9cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_10cout[0:0]),
.dataa(power_modified_counter_values[9]),
.datab(power_modified_counter_values[10]),
.ena(1'b1),
.regout(wire_countera_regout[10:10]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_10.cin_used = "true",
countera_10.lut_mask = "6c50",
countera_10.operation_mode = "arithmetic",
countera_10.sum_lutc_input = "cin",
countera_10.synch_mode = "on",
countera_10.lpm_type = "cyclone_lcell";
cyclone_lcell countera_11
(
.aclr(aclr),
.cin(wire_countera_10cout[0:0]),
.clk(clock),
.combout(),
.cout(),
.dataa(power_modified_counter_values[11]),
.ena(1'b1),
.regout(wire_countera_regout[11:11]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datab(1'b1),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_11.cin_used = "true",
countera_11.lut_mask = "5a5a",
countera_11.operation_mode = "normal",
countera_11.sum_lutc_input = "cin",
countera_11.synch_mode = "on",
countera_11.lpm_type = "cyclone_lcell";
cyclone_lcell parity
(
.aclr(aclr),
.cin(updown),
.clk(clock),
.combout(),
.cout(wire_parity_cout),
.dataa(cnt_en),
.datab(wire_parity_regout),
.ena(1'b1),
.regout(wire_parity_regout),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
parity.cin_used = "true",
parity.lut_mask = "6682",
parity.operation_mode = "arithmetic",
parity.synch_mode = "on",
parity.lpm_type = "cyclone_lcell";
assign
power_modified_counter_values = {wire_countera_regout[11:0]},
q = power_modified_counter_values,
sclr = 1'b0,
updown = 1'b1;
endmodule //fifo_4k_a_graycounter_826
//a_graycounter DEVICE_FAMILY="Cyclone" PVALUE=1 WIDTH=12 aclr clock cnt_en q
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = lut 13
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_a_graycounter_3r6
(
aclr,
clock,
cnt_en,
q) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clock;
input cnt_en;
output [11:0] q;
wire [0:0] wire_countera_0cout;
wire [0:0] wire_countera_1cout;
wire [0:0] wire_countera_2cout;
wire [0:0] wire_countera_3cout;
wire [0:0] wire_countera_4cout;
wire [0:0] wire_countera_5cout;
wire [0:0] wire_countera_6cout;
wire [0:0] wire_countera_7cout;
wire [0:0] wire_countera_8cout;
wire [0:0] wire_countera_9cout;
wire [0:0] wire_countera_10cout;
wire [11:0] wire_countera_regout;
wire wire_parity_cout;
wire wire_parity_regout;
wire [11:0] power_modified_counter_values;
wire sclr;
wire updown;
cyclone_lcell countera_0
(
.aclr(aclr),
.cin(wire_parity_cout),
.clk(clock),
.combout(),
.cout(wire_countera_0cout[0:0]),
.dataa(cnt_en),
.datab(wire_countera_regout[0:0]),
.ena(1'b1),
.regout(wire_countera_regout[0:0]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_0.cin_used = "true",
countera_0.lut_mask = "c6a0",
countera_0.operation_mode = "arithmetic",
countera_0.sum_lutc_input = "cin",
countera_0.synch_mode = "on",
countera_0.lpm_type = "cyclone_lcell";
cyclone_lcell countera_1
(
.aclr(aclr),
.cin(wire_countera_0cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_1cout[0:0]),
.dataa(power_modified_counter_values[0]),
.datab(power_modified_counter_values[1]),
.ena(1'b1),
.regout(wire_countera_regout[1:1]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_1.cin_used = "true",
countera_1.lut_mask = "6c50",
countera_1.operation_mode = "arithmetic",
countera_1.sum_lutc_input = "cin",
countera_1.synch_mode = "on",
countera_1.lpm_type = "cyclone_lcell";
cyclone_lcell countera_2
(
.aclr(aclr),
.cin(wire_countera_1cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_2cout[0:0]),
.dataa(power_modified_counter_values[1]),
.datab(power_modified_counter_values[2]),
.ena(1'b1),
.regout(wire_countera_regout[2:2]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_2.cin_used = "true",
countera_2.lut_mask = "6c50",
countera_2.operation_mode = "arithmetic",
countera_2.sum_lutc_input = "cin",
countera_2.synch_mode = "on",
countera_2.lpm_type = "cyclone_lcell";
cyclone_lcell countera_3
(
.aclr(aclr),
.cin(wire_countera_2cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_3cout[0:0]),
.dataa(power_modified_counter_values[2]),
.datab(power_modified_counter_values[3]),
.ena(1'b1),
.regout(wire_countera_regout[3:3]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_3.cin_used = "true",
countera_3.lut_mask = "6c50",
countera_3.operation_mode = "arithmetic",
countera_3.sum_lutc_input = "cin",
countera_3.synch_mode = "on",
countera_3.lpm_type = "cyclone_lcell";
cyclone_lcell countera_4
(
.aclr(aclr),
.cin(wire_countera_3cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_4cout[0:0]),
.dataa(power_modified_counter_values[3]),
.datab(power_modified_counter_values[4]),
.ena(1'b1),
.regout(wire_countera_regout[4:4]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_4.cin_used = "true",
countera_4.lut_mask = "6c50",
countera_4.operation_mode = "arithmetic",
countera_4.sum_lutc_input = "cin",
countera_4.synch_mode = "on",
countera_4.lpm_type = "cyclone_lcell";
cyclone_lcell countera_5
(
.aclr(aclr),
.cin(wire_countera_4cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_5cout[0:0]),
.dataa(power_modified_counter_values[4]),
.datab(power_modified_counter_values[5]),
.ena(1'b1),
.regout(wire_countera_regout[5:5]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_5.cin_used = "true",
countera_5.lut_mask = "6c50",
countera_5.operation_mode = "arithmetic",
countera_5.sum_lutc_input = "cin",
countera_5.synch_mode = "on",
countera_5.lpm_type = "cyclone_lcell";
cyclone_lcell countera_6
(
.aclr(aclr),
.cin(wire_countera_5cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_6cout[0:0]),
.dataa(power_modified_counter_values[5]),
.datab(power_modified_counter_values[6]),
.ena(1'b1),
.regout(wire_countera_regout[6:6]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_6.cin_used = "true",
countera_6.lut_mask = "6c50",
countera_6.operation_mode = "arithmetic",
countera_6.sum_lutc_input = "cin",
countera_6.synch_mode = "on",
countera_6.lpm_type = "cyclone_lcell";
cyclone_lcell countera_7
(
.aclr(aclr),
.cin(wire_countera_6cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_7cout[0:0]),
.dataa(power_modified_counter_values[6]),
.datab(power_modified_counter_values[7]),
.ena(1'b1),
.regout(wire_countera_regout[7:7]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_7.cin_used = "true",
countera_7.lut_mask = "6c50",
countera_7.operation_mode = "arithmetic",
countera_7.sum_lutc_input = "cin",
countera_7.synch_mode = "on",
countera_7.lpm_type = "cyclone_lcell";
cyclone_lcell countera_8
(
.aclr(aclr),
.cin(wire_countera_7cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_8cout[0:0]),
.dataa(power_modified_counter_values[7]),
.datab(power_modified_counter_values[8]),
.ena(1'b1),
.regout(wire_countera_regout[8:8]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_8.cin_used = "true",
countera_8.lut_mask = "6c50",
countera_8.operation_mode = "arithmetic",
countera_8.sum_lutc_input = "cin",
countera_8.synch_mode = "on",
countera_8.lpm_type = "cyclone_lcell";
cyclone_lcell countera_9
(
.aclr(aclr),
.cin(wire_countera_8cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_9cout[0:0]),
.dataa(power_modified_counter_values[8]),
.datab(power_modified_counter_values[9]),
.ena(1'b1),
.regout(wire_countera_regout[9:9]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_9.cin_used = "true",
countera_9.lut_mask = "6c50",
countera_9.operation_mode = "arithmetic",
countera_9.sum_lutc_input = "cin",
countera_9.synch_mode = "on",
countera_9.lpm_type = "cyclone_lcell";
cyclone_lcell countera_10
(
.aclr(aclr),
.cin(wire_countera_9cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_10cout[0:0]),
.dataa(power_modified_counter_values[9]),
.datab(power_modified_counter_values[10]),
.ena(1'b1),
.regout(wire_countera_regout[10:10]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_10.cin_used = "true",
countera_10.lut_mask = "6c50",
countera_10.operation_mode = "arithmetic",
countera_10.sum_lutc_input = "cin",
countera_10.synch_mode = "on",
countera_10.lpm_type = "cyclone_lcell";
cyclone_lcell countera_11
(
.aclr(aclr),
.cin(wire_countera_10cout[0:0]),
.clk(clock),
.combout(),
.cout(),
.dataa(power_modified_counter_values[11]),
.ena(1'b1),
.regout(wire_countera_regout[11:11]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datab(1'b1),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_11.cin_used = "true",
countera_11.lut_mask = "5a5a",
countera_11.operation_mode = "normal",
countera_11.sum_lutc_input = "cin",
countera_11.synch_mode = "on",
countera_11.lpm_type = "cyclone_lcell";
cyclone_lcell parity
(
.aclr(aclr),
.cin(updown),
.clk(clock),
.combout(),
.cout(wire_parity_cout),
.dataa(cnt_en),
.datab((~ wire_parity_regout)),
.ena(1'b1),
.regout(wire_parity_regout),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
parity.cin_used = "true",
parity.lut_mask = "9982",
parity.operation_mode = "arithmetic",
parity.synch_mode = "on",
parity.lpm_type = "cyclone_lcell";
assign
power_modified_counter_values = {wire_countera_regout[11:1], (~ wire_countera_regout[0])},
q = power_modified_counter_values,
sclr = 1'b0,
updown = 1'b1;
endmodule //fifo_4k_a_graycounter_3r6
//altsyncram ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=12 WIDTHAD_B=12 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a
//VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//synthesis_resources = M4K 16
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_altsyncram_8pl
(
address_a,
address_b,
clock0,
clock1,
clocken1,
data_a,
q_b,
wren_a) /* synthesis synthesis_clearbox=1 */;
input [11:0] address_a;
input [11:0] address_b;
input clock0;
input clock1;
input clocken1;
input [15:0] data_a;
output [15:0] q_b;
input wren_a;
wire [0:0] wire_ram_block3a_0portbdataout;
wire [0:0] wire_ram_block3a_1portbdataout;
wire [0:0] wire_ram_block3a_2portbdataout;
wire [0:0] wire_ram_block3a_3portbdataout;
wire [0:0] wire_ram_block3a_4portbdataout;
wire [0:0] wire_ram_block3a_5portbdataout;
wire [0:0] wire_ram_block3a_6portbdataout;
wire [0:0] wire_ram_block3a_7portbdataout;
wire [0:0] wire_ram_block3a_8portbdataout;
wire [0:0] wire_ram_block3a_9portbdataout;
wire [0:0] wire_ram_block3a_10portbdataout;
wire [0:0] wire_ram_block3a_11portbdataout;
wire [0:0] wire_ram_block3a_12portbdataout;
wire [0:0] wire_ram_block3a_13portbdataout;
wire [0:0] wire_ram_block3a_14portbdataout;
wire [0:0] wire_ram_block3a_15portbdataout;
wire [11:0] address_a_wire;
wire [11:0] address_b_wire;
cyclone_ram_block ram_block3a_0
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[0]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_0portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_0.connectivity_checking = "OFF",
ram_block3a_0.logical_ram_name = "ALTSYNCRAM",
ram_block3a_0.mixed_port_feed_through_mode = "dont_care",
ram_block3a_0.operation_mode = "dual_port",
ram_block3a_0.port_a_address_width = 12,
ram_block3a_0.port_a_data_width = 1,
ram_block3a_0.port_a_first_address = 0,
ram_block3a_0.port_a_first_bit_number = 0,
ram_block3a_0.port_a_last_address = 4095,
ram_block3a_0.port_a_logical_ram_depth = 4096,
ram_block3a_0.port_a_logical_ram_width = 16,
ram_block3a_0.port_b_address_clear = "none",
ram_block3a_0.port_b_address_clock = "clock1",
ram_block3a_0.port_b_address_width = 12,
ram_block3a_0.port_b_data_out_clear = "none",
ram_block3a_0.port_b_data_out_clock = "none",
ram_block3a_0.port_b_data_width = 1,
ram_block3a_0.port_b_first_address = 0,
ram_block3a_0.port_b_first_bit_number = 0,
ram_block3a_0.port_b_last_address = 4095,
ram_block3a_0.port_b_logical_ram_depth = 4096,
ram_block3a_0.port_b_logical_ram_width = 16,
ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_0.ram_block_type = "auto",
ram_block3a_0.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_1
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[1]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_1portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_1.connectivity_checking = "OFF",
ram_block3a_1.logical_ram_name = "ALTSYNCRAM",
ram_block3a_1.mixed_port_feed_through_mode = "dont_care",
ram_block3a_1.operation_mode = "dual_port",
ram_block3a_1.port_a_address_width = 12,
ram_block3a_1.port_a_data_width = 1,
ram_block3a_1.port_a_first_address = 0,
ram_block3a_1.port_a_first_bit_number = 1,
ram_block3a_1.port_a_last_address = 4095,
ram_block3a_1.port_a_logical_ram_depth = 4096,
ram_block3a_1.port_a_logical_ram_width = 16,
ram_block3a_1.port_b_address_clear = "none",
ram_block3a_1.port_b_address_clock = "clock1",
ram_block3a_1.port_b_address_width = 12,
ram_block3a_1.port_b_data_out_clear = "none",
ram_block3a_1.port_b_data_out_clock = "none",
ram_block3a_1.port_b_data_width = 1,
ram_block3a_1.port_b_first_address = 0,
ram_block3a_1.port_b_first_bit_number = 1,
ram_block3a_1.port_b_last_address = 4095,
ram_block3a_1.port_b_logical_ram_depth = 4096,
ram_block3a_1.port_b_logical_ram_width = 16,
ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_1.ram_block_type = "auto",
ram_block3a_1.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_2
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[2]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_2portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_2.connectivity_checking = "OFF",
ram_block3a_2.logical_ram_name = "ALTSYNCRAM",
ram_block3a_2.mixed_port_feed_through_mode = "dont_care",
ram_block3a_2.operation_mode = "dual_port",
ram_block3a_2.port_a_address_width = 12,
ram_block3a_2.port_a_data_width = 1,
ram_block3a_2.port_a_first_address = 0,
ram_block3a_2.port_a_first_bit_number = 2,
ram_block3a_2.port_a_last_address = 4095,
ram_block3a_2.port_a_logical_ram_depth = 4096,
ram_block3a_2.port_a_logical_ram_width = 16,
ram_block3a_2.port_b_address_clear = "none",
ram_block3a_2.port_b_address_clock = "clock1",
ram_block3a_2.port_b_address_width = 12,
ram_block3a_2.port_b_data_out_clear = "none",
ram_block3a_2.port_b_data_out_clock = "none",
ram_block3a_2.port_b_data_width = 1,
ram_block3a_2.port_b_first_address = 0,
ram_block3a_2.port_b_first_bit_number = 2,
ram_block3a_2.port_b_last_address = 4095,
ram_block3a_2.port_b_logical_ram_depth = 4096,
ram_block3a_2.port_b_logical_ram_width = 16,
ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_2.ram_block_type = "auto",
ram_block3a_2.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_3
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[3]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_3portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_3.connectivity_checking = "OFF",
ram_block3a_3.logical_ram_name = "ALTSYNCRAM",
ram_block3a_3.mixed_port_feed_through_mode = "dont_care",
ram_block3a_3.operation_mode = "dual_port",
ram_block3a_3.port_a_address_width = 12,
ram_block3a_3.port_a_data_width = 1,
ram_block3a_3.port_a_first_address = 0,
ram_block3a_3.port_a_first_bit_number = 3,
ram_block3a_3.port_a_last_address = 4095,
ram_block3a_3.port_a_logical_ram_depth = 4096,
ram_block3a_3.port_a_logical_ram_width = 16,
ram_block3a_3.port_b_address_clear = "none",
ram_block3a_3.port_b_address_clock = "clock1",
ram_block3a_3.port_b_address_width = 12,
ram_block3a_3.port_b_data_out_clear = "none",
ram_block3a_3.port_b_data_out_clock = "none",
ram_block3a_3.port_b_data_width = 1,
ram_block3a_3.port_b_first_address = 0,
ram_block3a_3.port_b_first_bit_number = 3,
ram_block3a_3.port_b_last_address = 4095,
ram_block3a_3.port_b_logical_ram_depth = 4096,
ram_block3a_3.port_b_logical_ram_width = 16,
ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_3.ram_block_type = "auto",
ram_block3a_3.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_4
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[4]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_4portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_4.connectivity_checking = "OFF",
ram_block3a_4.logical_ram_name = "ALTSYNCRAM",
ram_block3a_4.mixed_port_feed_through_mode = "dont_care",
ram_block3a_4.operation_mode = "dual_port",
ram_block3a_4.port_a_address_width = 12,
ram_block3a_4.port_a_data_width = 1,
ram_block3a_4.port_a_first_address = 0,
ram_block3a_4.port_a_first_bit_number = 4,
ram_block3a_4.port_a_last_address = 4095,
ram_block3a_4.port_a_logical_ram_depth = 4096,
ram_block3a_4.port_a_logical_ram_width = 16,
ram_block3a_4.port_b_address_clear = "none",
ram_block3a_4.port_b_address_clock = "clock1",
ram_block3a_4.port_b_address_width = 12,
ram_block3a_4.port_b_data_out_clear = "none",
ram_block3a_4.port_b_data_out_clock = "none",
ram_block3a_4.port_b_data_width = 1,
ram_block3a_4.port_b_first_address = 0,
ram_block3a_4.port_b_first_bit_number = 4,
ram_block3a_4.port_b_last_address = 4095,
ram_block3a_4.port_b_logical_ram_depth = 4096,
ram_block3a_4.port_b_logical_ram_width = 16,
ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_4.ram_block_type = "auto",
ram_block3a_4.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_5
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[5]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_5portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_5.connectivity_checking = "OFF",
ram_block3a_5.logical_ram_name = "ALTSYNCRAM",
ram_block3a_5.mixed_port_feed_through_mode = "dont_care",
ram_block3a_5.operation_mode = "dual_port",
ram_block3a_5.port_a_address_width = 12,
ram_block3a_5.port_a_data_width = 1,
ram_block3a_5.port_a_first_address = 0,
ram_block3a_5.port_a_first_bit_number = 5,
ram_block3a_5.port_a_last_address = 4095,
ram_block3a_5.port_a_logical_ram_depth = 4096,
ram_block3a_5.port_a_logical_ram_width = 16,
ram_block3a_5.port_b_address_clear = "none",
ram_block3a_5.port_b_address_clock = "clock1",
ram_block3a_5.port_b_address_width = 12,
ram_block3a_5.port_b_data_out_clear = "none",
ram_block3a_5.port_b_data_out_clock = "none",
ram_block3a_5.port_b_data_width = 1,
ram_block3a_5.port_b_first_address = 0,
ram_block3a_5.port_b_first_bit_number = 5,
ram_block3a_5.port_b_last_address = 4095,
ram_block3a_5.port_b_logical_ram_depth = 4096,
ram_block3a_5.port_b_logical_ram_width = 16,
ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_5.ram_block_type = "auto",
ram_block3a_5.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_6
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[6]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_6portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_6.connectivity_checking = "OFF",
ram_block3a_6.logical_ram_name = "ALTSYNCRAM",
ram_block3a_6.mixed_port_feed_through_mode = "dont_care",
ram_block3a_6.operation_mode = "dual_port",
ram_block3a_6.port_a_address_width = 12,
ram_block3a_6.port_a_data_width = 1,
ram_block3a_6.port_a_first_address = 0,
ram_block3a_6.port_a_first_bit_number = 6,
ram_block3a_6.port_a_last_address = 4095,
ram_block3a_6.port_a_logical_ram_depth = 4096,
ram_block3a_6.port_a_logical_ram_width = 16,
ram_block3a_6.port_b_address_clear = "none",
ram_block3a_6.port_b_address_clock = "clock1",
ram_block3a_6.port_b_address_width = 12,
ram_block3a_6.port_b_data_out_clear = "none",
ram_block3a_6.port_b_data_out_clock = "none",
ram_block3a_6.port_b_data_width = 1,
ram_block3a_6.port_b_first_address = 0,
ram_block3a_6.port_b_first_bit_number = 6,
ram_block3a_6.port_b_last_address = 4095,
ram_block3a_6.port_b_logical_ram_depth = 4096,
ram_block3a_6.port_b_logical_ram_width = 16,
ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_6.ram_block_type = "auto",
ram_block3a_6.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_7
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[7]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_7portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_7.connectivity_checking = "OFF",
ram_block3a_7.logical_ram_name = "ALTSYNCRAM",
ram_block3a_7.mixed_port_feed_through_mode = "dont_care",
ram_block3a_7.operation_mode = "dual_port",
ram_block3a_7.port_a_address_width = 12,
ram_block3a_7.port_a_data_width = 1,
ram_block3a_7.port_a_first_address = 0,
ram_block3a_7.port_a_first_bit_number = 7,
ram_block3a_7.port_a_last_address = 4095,
ram_block3a_7.port_a_logical_ram_depth = 4096,
ram_block3a_7.port_a_logical_ram_width = 16,
ram_block3a_7.port_b_address_clear = "none",
ram_block3a_7.port_b_address_clock = "clock1",
ram_block3a_7.port_b_address_width = 12,
ram_block3a_7.port_b_data_out_clear = "none",
ram_block3a_7.port_b_data_out_clock = "none",
ram_block3a_7.port_b_data_width = 1,
ram_block3a_7.port_b_first_address = 0,
ram_block3a_7.port_b_first_bit_number = 7,
ram_block3a_7.port_b_last_address = 4095,
ram_block3a_7.port_b_logical_ram_depth = 4096,
ram_block3a_7.port_b_logical_ram_width = 16,
ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_7.ram_block_type = "auto",
ram_block3a_7.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_8
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[8]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_8portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_8.connectivity_checking = "OFF",
ram_block3a_8.logical_ram_name = "ALTSYNCRAM",
ram_block3a_8.mixed_port_feed_through_mode = "dont_care",
ram_block3a_8.operation_mode = "dual_port",
ram_block3a_8.port_a_address_width = 12,
ram_block3a_8.port_a_data_width = 1,
ram_block3a_8.port_a_first_address = 0,
ram_block3a_8.port_a_first_bit_number = 8,
ram_block3a_8.port_a_last_address = 4095,
ram_block3a_8.port_a_logical_ram_depth = 4096,
ram_block3a_8.port_a_logical_ram_width = 16,
ram_block3a_8.port_b_address_clear = "none",
ram_block3a_8.port_b_address_clock = "clock1",
ram_block3a_8.port_b_address_width = 12,
ram_block3a_8.port_b_data_out_clear = "none",
ram_block3a_8.port_b_data_out_clock = "none",
ram_block3a_8.port_b_data_width = 1,
ram_block3a_8.port_b_first_address = 0,
ram_block3a_8.port_b_first_bit_number = 8,
ram_block3a_8.port_b_last_address = 4095,
ram_block3a_8.port_b_logical_ram_depth = 4096,
ram_block3a_8.port_b_logical_ram_width = 16,
ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_8.ram_block_type = "auto",
ram_block3a_8.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_9
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[9]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_9portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_9.connectivity_checking = "OFF",
ram_block3a_9.logical_ram_name = "ALTSYNCRAM",
ram_block3a_9.mixed_port_feed_through_mode = "dont_care",
ram_block3a_9.operation_mode = "dual_port",
ram_block3a_9.port_a_address_width = 12,
ram_block3a_9.port_a_data_width = 1,
ram_block3a_9.port_a_first_address = 0,
ram_block3a_9.port_a_first_bit_number = 9,
ram_block3a_9.port_a_last_address = 4095,
ram_block3a_9.port_a_logical_ram_depth = 4096,
ram_block3a_9.port_a_logical_ram_width = 16,
ram_block3a_9.port_b_address_clear = "none",
ram_block3a_9.port_b_address_clock = "clock1",
ram_block3a_9.port_b_address_width = 12,
ram_block3a_9.port_b_data_out_clear = "none",
ram_block3a_9.port_b_data_out_clock = "none",
ram_block3a_9.port_b_data_width = 1,
ram_block3a_9.port_b_first_address = 0,
ram_block3a_9.port_b_first_bit_number = 9,
ram_block3a_9.port_b_last_address = 4095,
ram_block3a_9.port_b_logical_ram_depth = 4096,
ram_block3a_9.port_b_logical_ram_width = 16,
ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_9.ram_block_type = "auto",
ram_block3a_9.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_10
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[10]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_10portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_10.connectivity_checking = "OFF",
ram_block3a_10.logical_ram_name = "ALTSYNCRAM",
ram_block3a_10.mixed_port_feed_through_mode = "dont_care",
ram_block3a_10.operation_mode = "dual_port",
ram_block3a_10.port_a_address_width = 12,
ram_block3a_10.port_a_data_width = 1,
ram_block3a_10.port_a_first_address = 0,
ram_block3a_10.port_a_first_bit_number = 10,
ram_block3a_10.port_a_last_address = 4095,
ram_block3a_10.port_a_logical_ram_depth = 4096,
ram_block3a_10.port_a_logical_ram_width = 16,
ram_block3a_10.port_b_address_clear = "none",
ram_block3a_10.port_b_address_clock = "clock1",
ram_block3a_10.port_b_address_width = 12,
ram_block3a_10.port_b_data_out_clear = "none",
ram_block3a_10.port_b_data_out_clock = "none",
ram_block3a_10.port_b_data_width = 1,
ram_block3a_10.port_b_first_address = 0,
ram_block3a_10.port_b_first_bit_number = 10,
ram_block3a_10.port_b_last_address = 4095,
ram_block3a_10.port_b_logical_ram_depth = 4096,
ram_block3a_10.port_b_logical_ram_width = 16,
ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_10.ram_block_type = "auto",
ram_block3a_10.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_11
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[11]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_11portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_11.connectivity_checking = "OFF",
ram_block3a_11.logical_ram_name = "ALTSYNCRAM",
ram_block3a_11.mixed_port_feed_through_mode = "dont_care",
ram_block3a_11.operation_mode = "dual_port",
ram_block3a_11.port_a_address_width = 12,
ram_block3a_11.port_a_data_width = 1,
ram_block3a_11.port_a_first_address = 0,
ram_block3a_11.port_a_first_bit_number = 11,
ram_block3a_11.port_a_last_address = 4095,
ram_block3a_11.port_a_logical_ram_depth = 4096,
ram_block3a_11.port_a_logical_ram_width = 16,
ram_block3a_11.port_b_address_clear = "none",
ram_block3a_11.port_b_address_clock = "clock1",
ram_block3a_11.port_b_address_width = 12,
ram_block3a_11.port_b_data_out_clear = "none",
ram_block3a_11.port_b_data_out_clock = "none",
ram_block3a_11.port_b_data_width = 1,
ram_block3a_11.port_b_first_address = 0,
ram_block3a_11.port_b_first_bit_number = 11,
ram_block3a_11.port_b_last_address = 4095,
ram_block3a_11.port_b_logical_ram_depth = 4096,
ram_block3a_11.port_b_logical_ram_width = 16,
ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_11.ram_block_type = "auto",
ram_block3a_11.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_12
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[12]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_12portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_12.connectivity_checking = "OFF",
ram_block3a_12.logical_ram_name = "ALTSYNCRAM",
ram_block3a_12.mixed_port_feed_through_mode = "dont_care",
ram_block3a_12.operation_mode = "dual_port",
ram_block3a_12.port_a_address_width = 12,
ram_block3a_12.port_a_data_width = 1,
ram_block3a_12.port_a_first_address = 0,
ram_block3a_12.port_a_first_bit_number = 12,
ram_block3a_12.port_a_last_address = 4095,
ram_block3a_12.port_a_logical_ram_depth = 4096,
ram_block3a_12.port_a_logical_ram_width = 16,
ram_block3a_12.port_b_address_clear = "none",
ram_block3a_12.port_b_address_clock = "clock1",
ram_block3a_12.port_b_address_width = 12,
ram_block3a_12.port_b_data_out_clear = "none",
ram_block3a_12.port_b_data_out_clock = "none",
ram_block3a_12.port_b_data_width = 1,
ram_block3a_12.port_b_first_address = 0,
ram_block3a_12.port_b_first_bit_number = 12,
ram_block3a_12.port_b_last_address = 4095,
ram_block3a_12.port_b_logical_ram_depth = 4096,
ram_block3a_12.port_b_logical_ram_width = 16,
ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_12.ram_block_type = "auto",
ram_block3a_12.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_13
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[13]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_13portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_13.connectivity_checking = "OFF",
ram_block3a_13.logical_ram_name = "ALTSYNCRAM",
ram_block3a_13.mixed_port_feed_through_mode = "dont_care",
ram_block3a_13.operation_mode = "dual_port",
ram_block3a_13.port_a_address_width = 12,
ram_block3a_13.port_a_data_width = 1,
ram_block3a_13.port_a_first_address = 0,
ram_block3a_13.port_a_first_bit_number = 13,
ram_block3a_13.port_a_last_address = 4095,
ram_block3a_13.port_a_logical_ram_depth = 4096,
ram_block3a_13.port_a_logical_ram_width = 16,
ram_block3a_13.port_b_address_clear = "none",
ram_block3a_13.port_b_address_clock = "clock1",
ram_block3a_13.port_b_address_width = 12,
ram_block3a_13.port_b_data_out_clear = "none",
ram_block3a_13.port_b_data_out_clock = "none",
ram_block3a_13.port_b_data_width = 1,
ram_block3a_13.port_b_first_address = 0,
ram_block3a_13.port_b_first_bit_number = 13,
ram_block3a_13.port_b_last_address = 4095,
ram_block3a_13.port_b_logical_ram_depth = 4096,
ram_block3a_13.port_b_logical_ram_width = 16,
ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_13.ram_block_type = "auto",
ram_block3a_13.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_14
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[14]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_14portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_14.connectivity_checking = "OFF",
ram_block3a_14.logical_ram_name = "ALTSYNCRAM",
ram_block3a_14.mixed_port_feed_through_mode = "dont_care",
ram_block3a_14.operation_mode = "dual_port",
ram_block3a_14.port_a_address_width = 12,
ram_block3a_14.port_a_data_width = 1,
ram_block3a_14.port_a_first_address = 0,
ram_block3a_14.port_a_first_bit_number = 14,
ram_block3a_14.port_a_last_address = 4095,
ram_block3a_14.port_a_logical_ram_depth = 4096,
ram_block3a_14.port_a_logical_ram_width = 16,
ram_block3a_14.port_b_address_clear = "none",
ram_block3a_14.port_b_address_clock = "clock1",
ram_block3a_14.port_b_address_width = 12,
ram_block3a_14.port_b_data_out_clear = "none",
ram_block3a_14.port_b_data_out_clock = "none",
ram_block3a_14.port_b_data_width = 1,
ram_block3a_14.port_b_first_address = 0,
ram_block3a_14.port_b_first_bit_number = 14,
ram_block3a_14.port_b_last_address = 4095,
ram_block3a_14.port_b_logical_ram_depth = 4096,
ram_block3a_14.port_b_logical_ram_width = 16,
ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_14.ram_block_type = "auto",
ram_block3a_14.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_15
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[15]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_15portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_15.connectivity_checking = "OFF",
ram_block3a_15.logical_ram_name = "ALTSYNCRAM",
ram_block3a_15.mixed_port_feed_through_mode = "dont_care",
ram_block3a_15.operation_mode = "dual_port",
ram_block3a_15.port_a_address_width = 12,
ram_block3a_15.port_a_data_width = 1,
ram_block3a_15.port_a_first_address = 0,
ram_block3a_15.port_a_first_bit_number = 15,
ram_block3a_15.port_a_last_address = 4095,
ram_block3a_15.port_a_logical_ram_depth = 4096,
ram_block3a_15.port_a_logical_ram_width = 16,
ram_block3a_15.port_b_address_clear = "none",
ram_block3a_15.port_b_address_clock = "clock1",
ram_block3a_15.port_b_address_width = 12,
ram_block3a_15.port_b_data_out_clear = "none",
ram_block3a_15.port_b_data_out_clock = "none",
ram_block3a_15.port_b_data_width = 1,
ram_block3a_15.port_b_first_address = 0,
ram_block3a_15.port_b_first_bit_number = 15,
ram_block3a_15.port_b_last_address = 4095,
ram_block3a_15.port_b_logical_ram_depth = 4096,
ram_block3a_15.port_b_logical_ram_width = 16,
ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_15.ram_block_type = "auto",
ram_block3a_15.lpm_type = "cyclone_ram_block";
assign
address_a_wire = address_a,
address_b_wire = address_b,
q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]};
endmodule //fifo_4k_altsyncram_8pl
//dffpipe DELAY=1 WIDTH=12 clock clrn d q
//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//synthesis_resources = lut 12
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_dffpipe_bb3
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
input clock;
input clrn;
input [11:0] d;
output [11:0] q;
wire [11:0] wire_dffe4a_D;
reg [11:0] dffe4a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe4a[0:0] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[0:0] <= 1'b1;
else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0;
else if (ena == 1'b1) dffe4a[0:0] <= wire_dffe4a_D[0:0];
// synopsys translate_off
initial
dffe4a[1:1] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[1:1] <= 1'b1;
else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0;
else if (ena == 1'b1) dffe4a[1:1] <= wire_dffe4a_D[1:1];
// synopsys translate_off
initial
dffe4a[2:2] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[2:2] <= 1'b1;
else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0;
else if (ena == 1'b1) dffe4a[2:2] <= wire_dffe4a_D[2:2];
// synopsys translate_off
initial
dffe4a[3:3] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[3:3] <= 1'b1;
else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0;
else if (ena == 1'b1) dffe4a[3:3] <= wire_dffe4a_D[3:3];
// synopsys translate_off
initial
dffe4a[4:4] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[4:4] <= 1'b1;
else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0;
else if (ena == 1'b1) dffe4a[4:4] <= wire_dffe4a_D[4:4];
// synopsys translate_off
initial
dffe4a[5:5] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[5:5] <= 1'b1;
else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0;
else if (ena == 1'b1) dffe4a[5:5] <= wire_dffe4a_D[5:5];
// synopsys translate_off
initial
dffe4a[6:6] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[6:6] <= 1'b1;
else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0;
else if (ena == 1'b1) dffe4a[6:6] <= wire_dffe4a_D[6:6];
// synopsys translate_off
initial
dffe4a[7:7] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[7:7] <= 1'b1;
else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0;
else if (ena == 1'b1) dffe4a[7:7] <= wire_dffe4a_D[7:7];
// synopsys translate_off
initial
dffe4a[8:8] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[8:8] <= 1'b1;
else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0;
else if (ena == 1'b1) dffe4a[8:8] <= wire_dffe4a_D[8:8];
// synopsys translate_off
initial
dffe4a[9:9] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[9:9] <= 1'b1;
else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0;
else if (ena == 1'b1) dffe4a[9:9] <= wire_dffe4a_D[9:9];
// synopsys translate_off
initial
dffe4a[10:10] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[10:10] <= 1'b1;
else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0;
else if (ena == 1'b1) dffe4a[10:10] <= wire_dffe4a_D[10:10];
// synopsys translate_off
initial
dffe4a[11:11] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[11:11] <= 1'b1;
else if (clrn == 1'b0) dffe4a[11:11] <= 1'b0;
else if (ena == 1'b1) dffe4a[11:11] <= wire_dffe4a_D[11:11];
assign
wire_dffe4a_D = (d & {12{(~ sclr)}});
assign
ena = 1'b1,
prn = 1'b1,
q = dffe4a,
sclr = 1'b0;
endmodule //fifo_4k_dffpipe_bb3
//dffpipe WIDTH=12 clock clrn d q
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//dffpipe WIDTH=12 clock clrn d q
//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//synthesis_resources = lut 12
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_dffpipe_em2
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
input clock;
input clrn;
input [11:0] d;
output [11:0] q;
wire [11:0] wire_dffe6a_D;
reg [11:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe6a[0:0] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[0:0] <= 1'b1;
else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0;
else if (ena == 1'b1) dffe6a[0:0] <= wire_dffe6a_D[0:0];
// synopsys translate_off
initial
dffe6a[1:1] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[1:1] <= 1'b1;
else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0;
else if (ena == 1'b1) dffe6a[1:1] <= wire_dffe6a_D[1:1];
// synopsys translate_off
initial
dffe6a[2:2] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[2:2] <= 1'b1;
else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0;
else if (ena == 1'b1) dffe6a[2:2] <= wire_dffe6a_D[2:2];
// synopsys translate_off
initial
dffe6a[3:3] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[3:3] <= 1'b1;
else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0;
else if (ena == 1'b1) dffe6a[3:3] <= wire_dffe6a_D[3:3];
// synopsys translate_off
initial
dffe6a[4:4] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[4:4] <= 1'b1;
else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0;
else if (ena == 1'b1) dffe6a[4:4] <= wire_dffe6a_D[4:4];
// synopsys translate_off
initial
dffe6a[5:5] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[5:5] <= 1'b1;
else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0;
else if (ena == 1'b1) dffe6a[5:5] <= wire_dffe6a_D[5:5];
// synopsys translate_off
initial
dffe6a[6:6] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[6:6] <= 1'b1;
else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0;
else if (ena == 1'b1) dffe6a[6:6] <= wire_dffe6a_D[6:6];
// synopsys translate_off
initial
dffe6a[7:7] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[7:7] <= 1'b1;
else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0;
else if (ena == 1'b1) dffe6a[7:7] <= wire_dffe6a_D[7:7];
// synopsys translate_off
initial
dffe6a[8:8] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[8:8] <= 1'b1;
else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0;
else if (ena == 1'b1) dffe6a[8:8] <= wire_dffe6a_D[8:8];
// synopsys translate_off
initial
dffe6a[9:9] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[9:9] <= 1'b1;
else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0;
else if (ena == 1'b1) dffe6a[9:9] <= wire_dffe6a_D[9:9];
// synopsys translate_off
initial
dffe6a[10:10] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[10:10] <= 1'b1;
else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0;
else if (ena == 1'b1) dffe6a[10:10] <= wire_dffe6a_D[10:10];
// synopsys translate_off
initial
dffe6a[11:11] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[11:11] <= 1'b1;
else if (clrn == 1'b0) dffe6a[11:11] <= 1'b0;
else if (ena == 1'b1) dffe6a[11:11] <= wire_dffe6a_D[11:11];
assign
wire_dffe6a_D = (d & {12{(~ sclr)}});
assign
ena = 1'b1,
prn = 1'b1,
q = dffe6a,
sclr = 1'b0;
endmodule //fifo_4k_dffpipe_em2
//synthesis_resources = lut 12
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_alt_synch_pipe_em2
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */;
input clock;
input clrn;
input [11:0] d;
output [11:0] q;
wire [11:0] wire_dffpipe5_q;
fifo_4k_dffpipe_em2 dffpipe5
(
.clock(clock),
.clrn(clrn),
.d(d),
.q(wire_dffpipe5_q));
assign
q = wire_dffpipe5_q;
endmodule //fifo_4k_alt_synch_pipe_em2
//lpm_add_sub DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=12 dataa datab result
//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = lut 12
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_add_sub_b18
(
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input [11:0] dataa;
input [11:0] datab;
output [11:0] result;
wire [11:0] wire_add_sub_cella_combout;
wire [0:0] wire_add_sub_cella_0cout;
wire [0:0] wire_add_sub_cella_1cout;
wire [0:0] wire_add_sub_cella_2cout;
wire [0:0] wire_add_sub_cella_3cout;
wire [0:0] wire_add_sub_cella_4cout;
wire [0:0] wire_add_sub_cella_5cout;
wire [0:0] wire_add_sub_cella_6cout;
wire [0:0] wire_add_sub_cella_7cout;
wire [0:0] wire_add_sub_cella_8cout;
wire [0:0] wire_add_sub_cella_9cout;
wire [0:0] wire_add_sub_cella_10cout;
wire [11:0] wire_add_sub_cella_dataa;
wire [11:0] wire_add_sub_cella_datab;
cyclone_lcell add_sub_cella_0
(
.cin(1'b1),
.combout(wire_add_sub_cella_combout[0:0]),
.cout(wire_add_sub_cella_0cout[0:0]),
.dataa(wire_add_sub_cella_dataa[0:0]),
.datab(wire_add_sub_cella_datab[0:0]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_0.cin_used = "true",
add_sub_cella_0.lut_mask = "69b2",
add_sub_cella_0.operation_mode = "arithmetic",
add_sub_cella_0.sum_lutc_input = "cin",
add_sub_cella_0.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_1
(
.cin(wire_add_sub_cella_0cout[0:0]),
.combout(wire_add_sub_cella_combout[1:1]),
.cout(wire_add_sub_cella_1cout[0:0]),
.dataa(wire_add_sub_cella_dataa[1:1]),
.datab(wire_add_sub_cella_datab[1:1]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_1.cin_used = "true",
add_sub_cella_1.lut_mask = "69b2",
add_sub_cella_1.operation_mode = "arithmetic",
add_sub_cella_1.sum_lutc_input = "cin",
add_sub_cella_1.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_2
(
.cin(wire_add_sub_cella_1cout[0:0]),
.combout(wire_add_sub_cella_combout[2:2]),
.cout(wire_add_sub_cella_2cout[0:0]),
.dataa(wire_add_sub_cella_dataa[2:2]),
.datab(wire_add_sub_cella_datab[2:2]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_2.cin_used = "true",
add_sub_cella_2.lut_mask = "69b2",
add_sub_cella_2.operation_mode = "arithmetic",
add_sub_cella_2.sum_lutc_input = "cin",
add_sub_cella_2.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_3
(
.cin(wire_add_sub_cella_2cout[0:0]),
.combout(wire_add_sub_cella_combout[3:3]),
.cout(wire_add_sub_cella_3cout[0:0]),
.dataa(wire_add_sub_cella_dataa[3:3]),
.datab(wire_add_sub_cella_datab[3:3]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_3.cin_used = "true",
add_sub_cella_3.lut_mask = "69b2",
add_sub_cella_3.operation_mode = "arithmetic",
add_sub_cella_3.sum_lutc_input = "cin",
add_sub_cella_3.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_4
(
.cin(wire_add_sub_cella_3cout[0:0]),
.combout(wire_add_sub_cella_combout[4:4]),
.cout(wire_add_sub_cella_4cout[0:0]),
.dataa(wire_add_sub_cella_dataa[4:4]),
.datab(wire_add_sub_cella_datab[4:4]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_4.cin_used = "true",
add_sub_cella_4.lut_mask = "69b2",
add_sub_cella_4.operation_mode = "arithmetic",
add_sub_cella_4.sum_lutc_input = "cin",
add_sub_cella_4.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_5
(
.cin(wire_add_sub_cella_4cout[0:0]),
.combout(wire_add_sub_cella_combout[5:5]),
.cout(wire_add_sub_cella_5cout[0:0]),
.dataa(wire_add_sub_cella_dataa[5:5]),
.datab(wire_add_sub_cella_datab[5:5]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_5.cin_used = "true",
add_sub_cella_5.lut_mask = "69b2",
add_sub_cella_5.operation_mode = "arithmetic",
add_sub_cella_5.sum_lutc_input = "cin",
add_sub_cella_5.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_6
(
.cin(wire_add_sub_cella_5cout[0:0]),
.combout(wire_add_sub_cella_combout[6:6]),
.cout(wire_add_sub_cella_6cout[0:0]),
.dataa(wire_add_sub_cella_dataa[6:6]),
.datab(wire_add_sub_cella_datab[6:6]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_6.cin_used = "true",
add_sub_cella_6.lut_mask = "69b2",
add_sub_cella_6.operation_mode = "arithmetic",
add_sub_cella_6.sum_lutc_input = "cin",
add_sub_cella_6.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_7
(
.cin(wire_add_sub_cella_6cout[0:0]),
.combout(wire_add_sub_cella_combout[7:7]),
.cout(wire_add_sub_cella_7cout[0:0]),
.dataa(wire_add_sub_cella_dataa[7:7]),
.datab(wire_add_sub_cella_datab[7:7]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_7.cin_used = "true",
add_sub_cella_7.lut_mask = "69b2",
add_sub_cella_7.operation_mode = "arithmetic",
add_sub_cella_7.sum_lutc_input = "cin",
add_sub_cella_7.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_8
(
.cin(wire_add_sub_cella_7cout[0:0]),
.combout(wire_add_sub_cella_combout[8:8]),
.cout(wire_add_sub_cella_8cout[0:0]),
.dataa(wire_add_sub_cella_dataa[8:8]),
.datab(wire_add_sub_cella_datab[8:8]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_8.cin_used = "true",
add_sub_cella_8.lut_mask = "69b2",
add_sub_cella_8.operation_mode = "arithmetic",
add_sub_cella_8.sum_lutc_input = "cin",
add_sub_cella_8.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_9
(
.cin(wire_add_sub_cella_8cout[0:0]),
.combout(wire_add_sub_cella_combout[9:9]),
.cout(wire_add_sub_cella_9cout[0:0]),
.dataa(wire_add_sub_cella_dataa[9:9]),
.datab(wire_add_sub_cella_datab[9:9]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_9.cin_used = "true",
add_sub_cella_9.lut_mask = "69b2",
add_sub_cella_9.operation_mode = "arithmetic",
add_sub_cella_9.sum_lutc_input = "cin",
add_sub_cella_9.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_10
(
.cin(wire_add_sub_cella_9cout[0:0]),
.combout(wire_add_sub_cella_combout[10:10]),
.cout(wire_add_sub_cella_10cout[0:0]),
.dataa(wire_add_sub_cella_dataa[10:10]),
.datab(wire_add_sub_cella_datab[10:10]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_10.cin_used = "true",
add_sub_cella_10.lut_mask = "69b2",
add_sub_cella_10.operation_mode = "arithmetic",
add_sub_cella_10.sum_lutc_input = "cin",
add_sub_cella_10.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_11
(
.cin(wire_add_sub_cella_10cout[0:0]),
.combout(wire_add_sub_cella_combout[11:11]),
.cout(),
.dataa(wire_add_sub_cella_dataa[11:11]),
.datab(wire_add_sub_cella_datab[11:11]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_11.cin_used = "true",
add_sub_cella_11.lut_mask = "6969",
add_sub_cella_11.operation_mode = "normal",
add_sub_cella_11.sum_lutc_input = "cin",
add_sub_cella_11.lpm_type = "cyclone_lcell";
assign
wire_add_sub_cella_dataa = dataa,
wire_add_sub_cella_datab = datab;
assign
result = wire_add_sub_cella_combout;
endmodule //fifo_4k_add_sub_b18
//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=12 aeb dataa datab
//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=12 aeb dataa datab
//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = lut 104 M4K 16
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_dcfifo_6cq
(
aclr,
data,
q,
rdclk,
rdempty,
rdreq,
rdusedw,
wrclk,
wrfull,
wrreq,
wrusedw) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g|power_modified_counter_values\" -to \"ws_dgrp|dffpipe5|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp|dffpipe5|dffe6a\" }CUT=ON" */;
input aclr;
input [15:0] data;
output [15:0] q;
input rdclk;
output rdempty;
input rdreq;
output [11:0] rdusedw;
input wrclk;
output wrfull;
input wrreq;
output [11:0] wrusedw;
wire [11:0] wire_rdptr_g_gray2bin_bin;
wire [11:0] wire_rs_dgwp_gray2bin_bin;
wire [11:0] wire_wrptr_g_gray2bin_bin;
wire [11:0] wire_ws_dgrp_gray2bin_bin;
wire [11:0] wire_rdptr_g_q;
wire [11:0] wire_rdptr_g1p_q;
wire [11:0] wire_wrptr_g1p_q;
wire [15:0] wire_fifo_ram_q_b;
reg [11:0] delayed_wrptr_g;
reg [11:0] wrptr_g;
wire [11:0] wire_rs_brp_q;
wire [11:0] wire_rs_bwp_q;
wire [11:0] wire_rs_dgwp_q;
wire [11:0] wire_ws_brp_q;
wire [11:0] wire_ws_bwp_q;
wire [11:0] wire_ws_dgrp_q;
wire [11:0] wire_rdusedw_sub_result;
wire [11:0] wire_wrusedw_sub_result;
reg wire_rdempty_eq_comp_aeb_int;
wire wire_rdempty_eq_comp_aeb;
wire [11:0] wire_rdempty_eq_comp_dataa;
wire [11:0] wire_rdempty_eq_comp_datab;
reg wire_wrfull_eq_comp_aeb_int;
wire wire_wrfull_eq_comp_aeb;
wire [11:0] wire_wrfull_eq_comp_dataa;
wire [11:0] wire_wrfull_eq_comp_datab;
wire int_rdempty;
wire int_wrfull;
wire valid_rdreq;
wire valid_wrreq;
fifo_4k_a_gray2bin_9m4 rdptr_g_gray2bin
(
.bin(wire_rdptr_g_gray2bin_bin),
.gray(wire_rdptr_g_q));
fifo_4k_a_gray2bin_9m4 rs_dgwp_gray2bin
(
.bin(wire_rs_dgwp_gray2bin_bin),
.gray(wire_rs_dgwp_q));
fifo_4k_a_gray2bin_9m4 wrptr_g_gray2bin
(
.bin(wire_wrptr_g_gray2bin_bin),
.gray(wrptr_g));
fifo_4k_a_gray2bin_9m4 ws_dgrp_gray2bin
(
.bin(wire_ws_dgrp_gray2bin_bin),
.gray(wire_ws_dgrp_q));
fifo_4k_a_graycounter_826 rdptr_g
(
.aclr(aclr),
.clock(rdclk),
.cnt_en(valid_rdreq),
.q(wire_rdptr_g_q));
fifo_4k_a_graycounter_3r6 rdptr_g1p
(
.aclr(aclr),
.clock(rdclk),
.cnt_en(valid_rdreq),
.q(wire_rdptr_g1p_q));
fifo_4k_a_graycounter_3r6 wrptr_g1p
(
.aclr(aclr),
.clock(wrclk),
.cnt_en(valid_wrreq),
.q(wire_wrptr_g1p_q));
fifo_4k_altsyncram_8pl fifo_ram
(
.address_a(wrptr_g),
.address_b(((wire_rdptr_g_q & {12{int_rdempty}}) | (wire_rdptr_g1p_q & {12{(~ int_rdempty)}}))),
.clock0(wrclk),
.clock1(rdclk),
.clocken1((valid_rdreq | int_rdempty)),
.data_a(data),
.q_b(wire_fifo_ram_q_b),
.wren_a(valid_wrreq));
// synopsys translate_off
initial
delayed_wrptr_g = 0;
// synopsys translate_on
always @ ( posedge wrclk or posedge aclr)
if (aclr == 1'b1) delayed_wrptr_g <= 12'b0;
else delayed_wrptr_g <= wrptr_g;
// synopsys translate_off
initial
wrptr_g = 0;
// synopsys translate_on
always @ ( posedge wrclk or posedge aclr)
if (aclr == 1'b1) wrptr_g <= 12'b0;
else if (valid_wrreq == 1'b1) wrptr_g <= wire_wrptr_g1p_q;
fifo_4k_dffpipe_bb3 rs_brp
(
.clock(rdclk),
.clrn((~ aclr)),
.d(wire_rdptr_g_gray2bin_bin),
.q(wire_rs_brp_q));
fifo_4k_dffpipe_bb3 rs_bwp
(
.clock(rdclk),
.clrn((~ aclr)),
.d(wire_rs_dgwp_gray2bin_bin),
.q(wire_rs_bwp_q));
fifo_4k_alt_synch_pipe_em2 rs_dgwp
(
.clock(rdclk),
.clrn((~ aclr)),
.d(delayed_wrptr_g),
.q(wire_rs_dgwp_q));
fifo_4k_dffpipe_bb3 ws_brp
(
.clock(wrclk),
.clrn((~ aclr)),
.d(wire_ws_dgrp_gray2bin_bin),
.q(wire_ws_brp_q));
fifo_4k_dffpipe_bb3 ws_bwp
(
.clock(wrclk),
.clrn((~ aclr)),
.d(wire_wrptr_g_gray2bin_bin),
.q(wire_ws_bwp_q));
fifo_4k_alt_synch_pipe_em2 ws_dgrp
(
.clock(wrclk),
.clrn((~ aclr)),
.d(wire_rdptr_g_q),
.q(wire_ws_dgrp_q));
fifo_4k_add_sub_b18 rdusedw_sub
(
.dataa(wire_rs_bwp_q),
.datab(wire_rs_brp_q),
.result(wire_rdusedw_sub_result));
fifo_4k_add_sub_b18 wrusedw_sub
(
.dataa(wire_ws_bwp_q),
.datab(wire_ws_brp_q),
.result(wire_wrusedw_sub_result));
always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab)
if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab)
begin
wire_rdempty_eq_comp_aeb_int = 1'b1;
end
else
begin
wire_rdempty_eq_comp_aeb_int = 1'b0;
end
assign
wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int;
assign
wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q,
wire_rdempty_eq_comp_datab = wire_rdptr_g_q;
always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab)
if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab)
begin
wire_wrfull_eq_comp_aeb_int = 1'b1;
end
else
begin
wire_wrfull_eq_comp_aeb_int = 1'b0;
end
assign
wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int;
assign
wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q,
wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q;
assign
int_rdempty = wire_rdempty_eq_comp_aeb,
int_wrfull = wire_wrfull_eq_comp_aeb,
q = wire_fifo_ram_q_b,
rdempty = int_rdempty,
rdusedw = wire_rdusedw_sub_result,
valid_rdreq = rdreq,
valid_wrreq = wrreq,
wrfull = int_wrfull,
wrusedw = wire_wrusedw_sub_result;
endmodule //fifo_4k_dcfifo_6cq
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_4k (
data,
wrreq,
rdreq,
rdclk,
wrclk,
aclr,
q,
rdempty,
rdusedw,
wrfull,
wrusedw)/* synthesis synthesis_clearbox = 1 */;
input [15:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
wire sub_wire0;
wire [11:0] sub_wire1;
wire sub_wire2;
wire [15:0] sub_wire3;
wire [11:0] sub_wire4;
wire rdempty = sub_wire0;
wire [11:0] wrusedw = sub_wire1[11:0];
wire wrfull = sub_wire2;
wire [15:0] q = sub_wire3[15:0];
wire [11:0] rdusedw = sub_wire4[11:0];
fifo_4k_dcfifo_6cq fifo_4k_dcfifo_6cq_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.q (sub_wire3),
.rdusedw (sub_wire4));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE
|
// megafunction wizard: %FIFO%CBX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_4k.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=4096 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTHU=12 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//a_gray2bin device_family="Cyclone" WIDTH=12 bin gray
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_a_gray2bin_9m4
(
bin,
gray) /* synthesis synthesis_clearbox=1 */;
output [11:0] bin;
input [11:0] gray;
wire xor0;
wire xor1;
wire xor10;
wire xor2;
wire xor3;
wire xor4;
wire xor5;
wire xor6;
wire xor7;
wire xor8;
wire xor9;
assign
bin = {gray[11], xor10, xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0},
xor0 = (gray[0] ^ xor1),
xor1 = (gray[1] ^ xor2),
xor10 = (gray[11] ^ gray[10]),
xor2 = (gray[2] ^ xor3),
xor3 = (gray[3] ^ xor4),
xor4 = (gray[4] ^ xor5),
xor5 = (gray[5] ^ xor6),
xor6 = (gray[6] ^ xor7),
xor7 = (gray[7] ^ xor8),
xor8 = (gray[8] ^ xor9),
xor9 = (gray[9] ^ xor10);
endmodule //fifo_4k_a_gray2bin_9m4
//a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=12 aclr clock cnt_en q
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = lut 13
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_a_graycounter_826
(
aclr,
clock,
cnt_en,
q) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clock;
input cnt_en;
output [11:0] q;
wire [0:0] wire_countera_0cout;
wire [0:0] wire_countera_1cout;
wire [0:0] wire_countera_2cout;
wire [0:0] wire_countera_3cout;
wire [0:0] wire_countera_4cout;
wire [0:0] wire_countera_5cout;
wire [0:0] wire_countera_6cout;
wire [0:0] wire_countera_7cout;
wire [0:0] wire_countera_8cout;
wire [0:0] wire_countera_9cout;
wire [0:0] wire_countera_10cout;
wire [11:0] wire_countera_regout;
wire wire_parity_cout;
wire wire_parity_regout;
wire [11:0] power_modified_counter_values;
wire sclr;
wire updown;
cyclone_lcell countera_0
(
.aclr(aclr),
.cin(wire_parity_cout),
.clk(clock),
.combout(),
.cout(wire_countera_0cout[0:0]),
.dataa(cnt_en),
.datab(wire_countera_regout[0:0]),
.ena(1'b1),
.regout(wire_countera_regout[0:0]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_0.cin_used = "true",
countera_0.lut_mask = "c6a0",
countera_0.operation_mode = "arithmetic",
countera_0.sum_lutc_input = "cin",
countera_0.synch_mode = "on",
countera_0.lpm_type = "cyclone_lcell";
cyclone_lcell countera_1
(
.aclr(aclr),
.cin(wire_countera_0cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_1cout[0:0]),
.dataa(power_modified_counter_values[0]),
.datab(power_modified_counter_values[1]),
.ena(1'b1),
.regout(wire_countera_regout[1:1]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_1.cin_used = "true",
countera_1.lut_mask = "6c50",
countera_1.operation_mode = "arithmetic",
countera_1.sum_lutc_input = "cin",
countera_1.synch_mode = "on",
countera_1.lpm_type = "cyclone_lcell";
cyclone_lcell countera_2
(
.aclr(aclr),
.cin(wire_countera_1cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_2cout[0:0]),
.dataa(power_modified_counter_values[1]),
.datab(power_modified_counter_values[2]),
.ena(1'b1),
.regout(wire_countera_regout[2:2]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_2.cin_used = "true",
countera_2.lut_mask = "6c50",
countera_2.operation_mode = "arithmetic",
countera_2.sum_lutc_input = "cin",
countera_2.synch_mode = "on",
countera_2.lpm_type = "cyclone_lcell";
cyclone_lcell countera_3
(
.aclr(aclr),
.cin(wire_countera_2cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_3cout[0:0]),
.dataa(power_modified_counter_values[2]),
.datab(power_modified_counter_values[3]),
.ena(1'b1),
.regout(wire_countera_regout[3:3]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_3.cin_used = "true",
countera_3.lut_mask = "6c50",
countera_3.operation_mode = "arithmetic",
countera_3.sum_lutc_input = "cin",
countera_3.synch_mode = "on",
countera_3.lpm_type = "cyclone_lcell";
cyclone_lcell countera_4
(
.aclr(aclr),
.cin(wire_countera_3cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_4cout[0:0]),
.dataa(power_modified_counter_values[3]),
.datab(power_modified_counter_values[4]),
.ena(1'b1),
.regout(wire_countera_regout[4:4]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_4.cin_used = "true",
countera_4.lut_mask = "6c50",
countera_4.operation_mode = "arithmetic",
countera_4.sum_lutc_input = "cin",
countera_4.synch_mode = "on",
countera_4.lpm_type = "cyclone_lcell";
cyclone_lcell countera_5
(
.aclr(aclr),
.cin(wire_countera_4cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_5cout[0:0]),
.dataa(power_modified_counter_values[4]),
.datab(power_modified_counter_values[5]),
.ena(1'b1),
.regout(wire_countera_regout[5:5]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_5.cin_used = "true",
countera_5.lut_mask = "6c50",
countera_5.operation_mode = "arithmetic",
countera_5.sum_lutc_input = "cin",
countera_5.synch_mode = "on",
countera_5.lpm_type = "cyclone_lcell";
cyclone_lcell countera_6
(
.aclr(aclr),
.cin(wire_countera_5cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_6cout[0:0]),
.dataa(power_modified_counter_values[5]),
.datab(power_modified_counter_values[6]),
.ena(1'b1),
.regout(wire_countera_regout[6:6]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_6.cin_used = "true",
countera_6.lut_mask = "6c50",
countera_6.operation_mode = "arithmetic",
countera_6.sum_lutc_input = "cin",
countera_6.synch_mode = "on",
countera_6.lpm_type = "cyclone_lcell";
cyclone_lcell countera_7
(
.aclr(aclr),
.cin(wire_countera_6cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_7cout[0:0]),
.dataa(power_modified_counter_values[6]),
.datab(power_modified_counter_values[7]),
.ena(1'b1),
.regout(wire_countera_regout[7:7]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_7.cin_used = "true",
countera_7.lut_mask = "6c50",
countera_7.operation_mode = "arithmetic",
countera_7.sum_lutc_input = "cin",
countera_7.synch_mode = "on",
countera_7.lpm_type = "cyclone_lcell";
cyclone_lcell countera_8
(
.aclr(aclr),
.cin(wire_countera_7cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_8cout[0:0]),
.dataa(power_modified_counter_values[7]),
.datab(power_modified_counter_values[8]),
.ena(1'b1),
.regout(wire_countera_regout[8:8]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_8.cin_used = "true",
countera_8.lut_mask = "6c50",
countera_8.operation_mode = "arithmetic",
countera_8.sum_lutc_input = "cin",
countera_8.synch_mode = "on",
countera_8.lpm_type = "cyclone_lcell";
cyclone_lcell countera_9
(
.aclr(aclr),
.cin(wire_countera_8cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_9cout[0:0]),
.dataa(power_modified_counter_values[8]),
.datab(power_modified_counter_values[9]),
.ena(1'b1),
.regout(wire_countera_regout[9:9]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_9.cin_used = "true",
countera_9.lut_mask = "6c50",
countera_9.operation_mode = "arithmetic",
countera_9.sum_lutc_input = "cin",
countera_9.synch_mode = "on",
countera_9.lpm_type = "cyclone_lcell";
cyclone_lcell countera_10
(
.aclr(aclr),
.cin(wire_countera_9cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_10cout[0:0]),
.dataa(power_modified_counter_values[9]),
.datab(power_modified_counter_values[10]),
.ena(1'b1),
.regout(wire_countera_regout[10:10]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_10.cin_used = "true",
countera_10.lut_mask = "6c50",
countera_10.operation_mode = "arithmetic",
countera_10.sum_lutc_input = "cin",
countera_10.synch_mode = "on",
countera_10.lpm_type = "cyclone_lcell";
cyclone_lcell countera_11
(
.aclr(aclr),
.cin(wire_countera_10cout[0:0]),
.clk(clock),
.combout(),
.cout(),
.dataa(power_modified_counter_values[11]),
.ena(1'b1),
.regout(wire_countera_regout[11:11]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datab(1'b1),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_11.cin_used = "true",
countera_11.lut_mask = "5a5a",
countera_11.operation_mode = "normal",
countera_11.sum_lutc_input = "cin",
countera_11.synch_mode = "on",
countera_11.lpm_type = "cyclone_lcell";
cyclone_lcell parity
(
.aclr(aclr),
.cin(updown),
.clk(clock),
.combout(),
.cout(wire_parity_cout),
.dataa(cnt_en),
.datab(wire_parity_regout),
.ena(1'b1),
.regout(wire_parity_regout),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
parity.cin_used = "true",
parity.lut_mask = "6682",
parity.operation_mode = "arithmetic",
parity.synch_mode = "on",
parity.lpm_type = "cyclone_lcell";
assign
power_modified_counter_values = {wire_countera_regout[11:0]},
q = power_modified_counter_values,
sclr = 1'b0,
updown = 1'b1;
endmodule //fifo_4k_a_graycounter_826
//a_graycounter DEVICE_FAMILY="Cyclone" PVALUE=1 WIDTH=12 aclr clock cnt_en q
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = lut 13
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_a_graycounter_3r6
(
aclr,
clock,
cnt_en,
q) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clock;
input cnt_en;
output [11:0] q;
wire [0:0] wire_countera_0cout;
wire [0:0] wire_countera_1cout;
wire [0:0] wire_countera_2cout;
wire [0:0] wire_countera_3cout;
wire [0:0] wire_countera_4cout;
wire [0:0] wire_countera_5cout;
wire [0:0] wire_countera_6cout;
wire [0:0] wire_countera_7cout;
wire [0:0] wire_countera_8cout;
wire [0:0] wire_countera_9cout;
wire [0:0] wire_countera_10cout;
wire [11:0] wire_countera_regout;
wire wire_parity_cout;
wire wire_parity_regout;
wire [11:0] power_modified_counter_values;
wire sclr;
wire updown;
cyclone_lcell countera_0
(
.aclr(aclr),
.cin(wire_parity_cout),
.clk(clock),
.combout(),
.cout(wire_countera_0cout[0:0]),
.dataa(cnt_en),
.datab(wire_countera_regout[0:0]),
.ena(1'b1),
.regout(wire_countera_regout[0:0]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_0.cin_used = "true",
countera_0.lut_mask = "c6a0",
countera_0.operation_mode = "arithmetic",
countera_0.sum_lutc_input = "cin",
countera_0.synch_mode = "on",
countera_0.lpm_type = "cyclone_lcell";
cyclone_lcell countera_1
(
.aclr(aclr),
.cin(wire_countera_0cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_1cout[0:0]),
.dataa(power_modified_counter_values[0]),
.datab(power_modified_counter_values[1]),
.ena(1'b1),
.regout(wire_countera_regout[1:1]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_1.cin_used = "true",
countera_1.lut_mask = "6c50",
countera_1.operation_mode = "arithmetic",
countera_1.sum_lutc_input = "cin",
countera_1.synch_mode = "on",
countera_1.lpm_type = "cyclone_lcell";
cyclone_lcell countera_2
(
.aclr(aclr),
.cin(wire_countera_1cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_2cout[0:0]),
.dataa(power_modified_counter_values[1]),
.datab(power_modified_counter_values[2]),
.ena(1'b1),
.regout(wire_countera_regout[2:2]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_2.cin_used = "true",
countera_2.lut_mask = "6c50",
countera_2.operation_mode = "arithmetic",
countera_2.sum_lutc_input = "cin",
countera_2.synch_mode = "on",
countera_2.lpm_type = "cyclone_lcell";
cyclone_lcell countera_3
(
.aclr(aclr),
.cin(wire_countera_2cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_3cout[0:0]),
.dataa(power_modified_counter_values[2]),
.datab(power_modified_counter_values[3]),
.ena(1'b1),
.regout(wire_countera_regout[3:3]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_3.cin_used = "true",
countera_3.lut_mask = "6c50",
countera_3.operation_mode = "arithmetic",
countera_3.sum_lutc_input = "cin",
countera_3.synch_mode = "on",
countera_3.lpm_type = "cyclone_lcell";
cyclone_lcell countera_4
(
.aclr(aclr),
.cin(wire_countera_3cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_4cout[0:0]),
.dataa(power_modified_counter_values[3]),
.datab(power_modified_counter_values[4]),
.ena(1'b1),
.regout(wire_countera_regout[4:4]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_4.cin_used = "true",
countera_4.lut_mask = "6c50",
countera_4.operation_mode = "arithmetic",
countera_4.sum_lutc_input = "cin",
countera_4.synch_mode = "on",
countera_4.lpm_type = "cyclone_lcell";
cyclone_lcell countera_5
(
.aclr(aclr),
.cin(wire_countera_4cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_5cout[0:0]),
.dataa(power_modified_counter_values[4]),
.datab(power_modified_counter_values[5]),
.ena(1'b1),
.regout(wire_countera_regout[5:5]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_5.cin_used = "true",
countera_5.lut_mask = "6c50",
countera_5.operation_mode = "arithmetic",
countera_5.sum_lutc_input = "cin",
countera_5.synch_mode = "on",
countera_5.lpm_type = "cyclone_lcell";
cyclone_lcell countera_6
(
.aclr(aclr),
.cin(wire_countera_5cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_6cout[0:0]),
.dataa(power_modified_counter_values[5]),
.datab(power_modified_counter_values[6]),
.ena(1'b1),
.regout(wire_countera_regout[6:6]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_6.cin_used = "true",
countera_6.lut_mask = "6c50",
countera_6.operation_mode = "arithmetic",
countera_6.sum_lutc_input = "cin",
countera_6.synch_mode = "on",
countera_6.lpm_type = "cyclone_lcell";
cyclone_lcell countera_7
(
.aclr(aclr),
.cin(wire_countera_6cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_7cout[0:0]),
.dataa(power_modified_counter_values[6]),
.datab(power_modified_counter_values[7]),
.ena(1'b1),
.regout(wire_countera_regout[7:7]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_7.cin_used = "true",
countera_7.lut_mask = "6c50",
countera_7.operation_mode = "arithmetic",
countera_7.sum_lutc_input = "cin",
countera_7.synch_mode = "on",
countera_7.lpm_type = "cyclone_lcell";
cyclone_lcell countera_8
(
.aclr(aclr),
.cin(wire_countera_7cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_8cout[0:0]),
.dataa(power_modified_counter_values[7]),
.datab(power_modified_counter_values[8]),
.ena(1'b1),
.regout(wire_countera_regout[8:8]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_8.cin_used = "true",
countera_8.lut_mask = "6c50",
countera_8.operation_mode = "arithmetic",
countera_8.sum_lutc_input = "cin",
countera_8.synch_mode = "on",
countera_8.lpm_type = "cyclone_lcell";
cyclone_lcell countera_9
(
.aclr(aclr),
.cin(wire_countera_8cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_9cout[0:0]),
.dataa(power_modified_counter_values[8]),
.datab(power_modified_counter_values[9]),
.ena(1'b1),
.regout(wire_countera_regout[9:9]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_9.cin_used = "true",
countera_9.lut_mask = "6c50",
countera_9.operation_mode = "arithmetic",
countera_9.sum_lutc_input = "cin",
countera_9.synch_mode = "on",
countera_9.lpm_type = "cyclone_lcell";
cyclone_lcell countera_10
(
.aclr(aclr),
.cin(wire_countera_9cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_10cout[0:0]),
.dataa(power_modified_counter_values[9]),
.datab(power_modified_counter_values[10]),
.ena(1'b1),
.regout(wire_countera_regout[10:10]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_10.cin_used = "true",
countera_10.lut_mask = "6c50",
countera_10.operation_mode = "arithmetic",
countera_10.sum_lutc_input = "cin",
countera_10.synch_mode = "on",
countera_10.lpm_type = "cyclone_lcell";
cyclone_lcell countera_11
(
.aclr(aclr),
.cin(wire_countera_10cout[0:0]),
.clk(clock),
.combout(),
.cout(),
.dataa(power_modified_counter_values[11]),
.ena(1'b1),
.regout(wire_countera_regout[11:11]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datab(1'b1),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_11.cin_used = "true",
countera_11.lut_mask = "5a5a",
countera_11.operation_mode = "normal",
countera_11.sum_lutc_input = "cin",
countera_11.synch_mode = "on",
countera_11.lpm_type = "cyclone_lcell";
cyclone_lcell parity
(
.aclr(aclr),
.cin(updown),
.clk(clock),
.combout(),
.cout(wire_parity_cout),
.dataa(cnt_en),
.datab((~ wire_parity_regout)),
.ena(1'b1),
.regout(wire_parity_regout),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
parity.cin_used = "true",
parity.lut_mask = "9982",
parity.operation_mode = "arithmetic",
parity.synch_mode = "on",
parity.lpm_type = "cyclone_lcell";
assign
power_modified_counter_values = {wire_countera_regout[11:1], (~ wire_countera_regout[0])},
q = power_modified_counter_values,
sclr = 1'b0,
updown = 1'b1;
endmodule //fifo_4k_a_graycounter_3r6
//altsyncram ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=12 WIDTHAD_B=12 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a
//VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//synthesis_resources = M4K 16
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_altsyncram_8pl
(
address_a,
address_b,
clock0,
clock1,
clocken1,
data_a,
q_b,
wren_a) /* synthesis synthesis_clearbox=1 */;
input [11:0] address_a;
input [11:0] address_b;
input clock0;
input clock1;
input clocken1;
input [15:0] data_a;
output [15:0] q_b;
input wren_a;
wire [0:0] wire_ram_block3a_0portbdataout;
wire [0:0] wire_ram_block3a_1portbdataout;
wire [0:0] wire_ram_block3a_2portbdataout;
wire [0:0] wire_ram_block3a_3portbdataout;
wire [0:0] wire_ram_block3a_4portbdataout;
wire [0:0] wire_ram_block3a_5portbdataout;
wire [0:0] wire_ram_block3a_6portbdataout;
wire [0:0] wire_ram_block3a_7portbdataout;
wire [0:0] wire_ram_block3a_8portbdataout;
wire [0:0] wire_ram_block3a_9portbdataout;
wire [0:0] wire_ram_block3a_10portbdataout;
wire [0:0] wire_ram_block3a_11portbdataout;
wire [0:0] wire_ram_block3a_12portbdataout;
wire [0:0] wire_ram_block3a_13portbdataout;
wire [0:0] wire_ram_block3a_14portbdataout;
wire [0:0] wire_ram_block3a_15portbdataout;
wire [11:0] address_a_wire;
wire [11:0] address_b_wire;
cyclone_ram_block ram_block3a_0
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[0]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_0portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_0.connectivity_checking = "OFF",
ram_block3a_0.logical_ram_name = "ALTSYNCRAM",
ram_block3a_0.mixed_port_feed_through_mode = "dont_care",
ram_block3a_0.operation_mode = "dual_port",
ram_block3a_0.port_a_address_width = 12,
ram_block3a_0.port_a_data_width = 1,
ram_block3a_0.port_a_first_address = 0,
ram_block3a_0.port_a_first_bit_number = 0,
ram_block3a_0.port_a_last_address = 4095,
ram_block3a_0.port_a_logical_ram_depth = 4096,
ram_block3a_0.port_a_logical_ram_width = 16,
ram_block3a_0.port_b_address_clear = "none",
ram_block3a_0.port_b_address_clock = "clock1",
ram_block3a_0.port_b_address_width = 12,
ram_block3a_0.port_b_data_out_clear = "none",
ram_block3a_0.port_b_data_out_clock = "none",
ram_block3a_0.port_b_data_width = 1,
ram_block3a_0.port_b_first_address = 0,
ram_block3a_0.port_b_first_bit_number = 0,
ram_block3a_0.port_b_last_address = 4095,
ram_block3a_0.port_b_logical_ram_depth = 4096,
ram_block3a_0.port_b_logical_ram_width = 16,
ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_0.ram_block_type = "auto",
ram_block3a_0.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_1
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[1]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_1portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_1.connectivity_checking = "OFF",
ram_block3a_1.logical_ram_name = "ALTSYNCRAM",
ram_block3a_1.mixed_port_feed_through_mode = "dont_care",
ram_block3a_1.operation_mode = "dual_port",
ram_block3a_1.port_a_address_width = 12,
ram_block3a_1.port_a_data_width = 1,
ram_block3a_1.port_a_first_address = 0,
ram_block3a_1.port_a_first_bit_number = 1,
ram_block3a_1.port_a_last_address = 4095,
ram_block3a_1.port_a_logical_ram_depth = 4096,
ram_block3a_1.port_a_logical_ram_width = 16,
ram_block3a_1.port_b_address_clear = "none",
ram_block3a_1.port_b_address_clock = "clock1",
ram_block3a_1.port_b_address_width = 12,
ram_block3a_1.port_b_data_out_clear = "none",
ram_block3a_1.port_b_data_out_clock = "none",
ram_block3a_1.port_b_data_width = 1,
ram_block3a_1.port_b_first_address = 0,
ram_block3a_1.port_b_first_bit_number = 1,
ram_block3a_1.port_b_last_address = 4095,
ram_block3a_1.port_b_logical_ram_depth = 4096,
ram_block3a_1.port_b_logical_ram_width = 16,
ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_1.ram_block_type = "auto",
ram_block3a_1.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_2
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[2]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_2portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_2.connectivity_checking = "OFF",
ram_block3a_2.logical_ram_name = "ALTSYNCRAM",
ram_block3a_2.mixed_port_feed_through_mode = "dont_care",
ram_block3a_2.operation_mode = "dual_port",
ram_block3a_2.port_a_address_width = 12,
ram_block3a_2.port_a_data_width = 1,
ram_block3a_2.port_a_first_address = 0,
ram_block3a_2.port_a_first_bit_number = 2,
ram_block3a_2.port_a_last_address = 4095,
ram_block3a_2.port_a_logical_ram_depth = 4096,
ram_block3a_2.port_a_logical_ram_width = 16,
ram_block3a_2.port_b_address_clear = "none",
ram_block3a_2.port_b_address_clock = "clock1",
ram_block3a_2.port_b_address_width = 12,
ram_block3a_2.port_b_data_out_clear = "none",
ram_block3a_2.port_b_data_out_clock = "none",
ram_block3a_2.port_b_data_width = 1,
ram_block3a_2.port_b_first_address = 0,
ram_block3a_2.port_b_first_bit_number = 2,
ram_block3a_2.port_b_last_address = 4095,
ram_block3a_2.port_b_logical_ram_depth = 4096,
ram_block3a_2.port_b_logical_ram_width = 16,
ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_2.ram_block_type = "auto",
ram_block3a_2.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_3
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[3]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_3portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_3.connectivity_checking = "OFF",
ram_block3a_3.logical_ram_name = "ALTSYNCRAM",
ram_block3a_3.mixed_port_feed_through_mode = "dont_care",
ram_block3a_3.operation_mode = "dual_port",
ram_block3a_3.port_a_address_width = 12,
ram_block3a_3.port_a_data_width = 1,
ram_block3a_3.port_a_first_address = 0,
ram_block3a_3.port_a_first_bit_number = 3,
ram_block3a_3.port_a_last_address = 4095,
ram_block3a_3.port_a_logical_ram_depth = 4096,
ram_block3a_3.port_a_logical_ram_width = 16,
ram_block3a_3.port_b_address_clear = "none",
ram_block3a_3.port_b_address_clock = "clock1",
ram_block3a_3.port_b_address_width = 12,
ram_block3a_3.port_b_data_out_clear = "none",
ram_block3a_3.port_b_data_out_clock = "none",
ram_block3a_3.port_b_data_width = 1,
ram_block3a_3.port_b_first_address = 0,
ram_block3a_3.port_b_first_bit_number = 3,
ram_block3a_3.port_b_last_address = 4095,
ram_block3a_3.port_b_logical_ram_depth = 4096,
ram_block3a_3.port_b_logical_ram_width = 16,
ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_3.ram_block_type = "auto",
ram_block3a_3.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_4
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[4]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_4portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_4.connectivity_checking = "OFF",
ram_block3a_4.logical_ram_name = "ALTSYNCRAM",
ram_block3a_4.mixed_port_feed_through_mode = "dont_care",
ram_block3a_4.operation_mode = "dual_port",
ram_block3a_4.port_a_address_width = 12,
ram_block3a_4.port_a_data_width = 1,
ram_block3a_4.port_a_first_address = 0,
ram_block3a_4.port_a_first_bit_number = 4,
ram_block3a_4.port_a_last_address = 4095,
ram_block3a_4.port_a_logical_ram_depth = 4096,
ram_block3a_4.port_a_logical_ram_width = 16,
ram_block3a_4.port_b_address_clear = "none",
ram_block3a_4.port_b_address_clock = "clock1",
ram_block3a_4.port_b_address_width = 12,
ram_block3a_4.port_b_data_out_clear = "none",
ram_block3a_4.port_b_data_out_clock = "none",
ram_block3a_4.port_b_data_width = 1,
ram_block3a_4.port_b_first_address = 0,
ram_block3a_4.port_b_first_bit_number = 4,
ram_block3a_4.port_b_last_address = 4095,
ram_block3a_4.port_b_logical_ram_depth = 4096,
ram_block3a_4.port_b_logical_ram_width = 16,
ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_4.ram_block_type = "auto",
ram_block3a_4.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_5
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[5]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_5portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_5.connectivity_checking = "OFF",
ram_block3a_5.logical_ram_name = "ALTSYNCRAM",
ram_block3a_5.mixed_port_feed_through_mode = "dont_care",
ram_block3a_5.operation_mode = "dual_port",
ram_block3a_5.port_a_address_width = 12,
ram_block3a_5.port_a_data_width = 1,
ram_block3a_5.port_a_first_address = 0,
ram_block3a_5.port_a_first_bit_number = 5,
ram_block3a_5.port_a_last_address = 4095,
ram_block3a_5.port_a_logical_ram_depth = 4096,
ram_block3a_5.port_a_logical_ram_width = 16,
ram_block3a_5.port_b_address_clear = "none",
ram_block3a_5.port_b_address_clock = "clock1",
ram_block3a_5.port_b_address_width = 12,
ram_block3a_5.port_b_data_out_clear = "none",
ram_block3a_5.port_b_data_out_clock = "none",
ram_block3a_5.port_b_data_width = 1,
ram_block3a_5.port_b_first_address = 0,
ram_block3a_5.port_b_first_bit_number = 5,
ram_block3a_5.port_b_last_address = 4095,
ram_block3a_5.port_b_logical_ram_depth = 4096,
ram_block3a_5.port_b_logical_ram_width = 16,
ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_5.ram_block_type = "auto",
ram_block3a_5.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_6
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[6]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_6portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_6.connectivity_checking = "OFF",
ram_block3a_6.logical_ram_name = "ALTSYNCRAM",
ram_block3a_6.mixed_port_feed_through_mode = "dont_care",
ram_block3a_6.operation_mode = "dual_port",
ram_block3a_6.port_a_address_width = 12,
ram_block3a_6.port_a_data_width = 1,
ram_block3a_6.port_a_first_address = 0,
ram_block3a_6.port_a_first_bit_number = 6,
ram_block3a_6.port_a_last_address = 4095,
ram_block3a_6.port_a_logical_ram_depth = 4096,
ram_block3a_6.port_a_logical_ram_width = 16,
ram_block3a_6.port_b_address_clear = "none",
ram_block3a_6.port_b_address_clock = "clock1",
ram_block3a_6.port_b_address_width = 12,
ram_block3a_6.port_b_data_out_clear = "none",
ram_block3a_6.port_b_data_out_clock = "none",
ram_block3a_6.port_b_data_width = 1,
ram_block3a_6.port_b_first_address = 0,
ram_block3a_6.port_b_first_bit_number = 6,
ram_block3a_6.port_b_last_address = 4095,
ram_block3a_6.port_b_logical_ram_depth = 4096,
ram_block3a_6.port_b_logical_ram_width = 16,
ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_6.ram_block_type = "auto",
ram_block3a_6.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_7
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[7]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_7portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_7.connectivity_checking = "OFF",
ram_block3a_7.logical_ram_name = "ALTSYNCRAM",
ram_block3a_7.mixed_port_feed_through_mode = "dont_care",
ram_block3a_7.operation_mode = "dual_port",
ram_block3a_7.port_a_address_width = 12,
ram_block3a_7.port_a_data_width = 1,
ram_block3a_7.port_a_first_address = 0,
ram_block3a_7.port_a_first_bit_number = 7,
ram_block3a_7.port_a_last_address = 4095,
ram_block3a_7.port_a_logical_ram_depth = 4096,
ram_block3a_7.port_a_logical_ram_width = 16,
ram_block3a_7.port_b_address_clear = "none",
ram_block3a_7.port_b_address_clock = "clock1",
ram_block3a_7.port_b_address_width = 12,
ram_block3a_7.port_b_data_out_clear = "none",
ram_block3a_7.port_b_data_out_clock = "none",
ram_block3a_7.port_b_data_width = 1,
ram_block3a_7.port_b_first_address = 0,
ram_block3a_7.port_b_first_bit_number = 7,
ram_block3a_7.port_b_last_address = 4095,
ram_block3a_7.port_b_logical_ram_depth = 4096,
ram_block3a_7.port_b_logical_ram_width = 16,
ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_7.ram_block_type = "auto",
ram_block3a_7.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_8
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[8]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_8portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_8.connectivity_checking = "OFF",
ram_block3a_8.logical_ram_name = "ALTSYNCRAM",
ram_block3a_8.mixed_port_feed_through_mode = "dont_care",
ram_block3a_8.operation_mode = "dual_port",
ram_block3a_8.port_a_address_width = 12,
ram_block3a_8.port_a_data_width = 1,
ram_block3a_8.port_a_first_address = 0,
ram_block3a_8.port_a_first_bit_number = 8,
ram_block3a_8.port_a_last_address = 4095,
ram_block3a_8.port_a_logical_ram_depth = 4096,
ram_block3a_8.port_a_logical_ram_width = 16,
ram_block3a_8.port_b_address_clear = "none",
ram_block3a_8.port_b_address_clock = "clock1",
ram_block3a_8.port_b_address_width = 12,
ram_block3a_8.port_b_data_out_clear = "none",
ram_block3a_8.port_b_data_out_clock = "none",
ram_block3a_8.port_b_data_width = 1,
ram_block3a_8.port_b_first_address = 0,
ram_block3a_8.port_b_first_bit_number = 8,
ram_block3a_8.port_b_last_address = 4095,
ram_block3a_8.port_b_logical_ram_depth = 4096,
ram_block3a_8.port_b_logical_ram_width = 16,
ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_8.ram_block_type = "auto",
ram_block3a_8.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_9
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[9]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_9portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_9.connectivity_checking = "OFF",
ram_block3a_9.logical_ram_name = "ALTSYNCRAM",
ram_block3a_9.mixed_port_feed_through_mode = "dont_care",
ram_block3a_9.operation_mode = "dual_port",
ram_block3a_9.port_a_address_width = 12,
ram_block3a_9.port_a_data_width = 1,
ram_block3a_9.port_a_first_address = 0,
ram_block3a_9.port_a_first_bit_number = 9,
ram_block3a_9.port_a_last_address = 4095,
ram_block3a_9.port_a_logical_ram_depth = 4096,
ram_block3a_9.port_a_logical_ram_width = 16,
ram_block3a_9.port_b_address_clear = "none",
ram_block3a_9.port_b_address_clock = "clock1",
ram_block3a_9.port_b_address_width = 12,
ram_block3a_9.port_b_data_out_clear = "none",
ram_block3a_9.port_b_data_out_clock = "none",
ram_block3a_9.port_b_data_width = 1,
ram_block3a_9.port_b_first_address = 0,
ram_block3a_9.port_b_first_bit_number = 9,
ram_block3a_9.port_b_last_address = 4095,
ram_block3a_9.port_b_logical_ram_depth = 4096,
ram_block3a_9.port_b_logical_ram_width = 16,
ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_9.ram_block_type = "auto",
ram_block3a_9.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_10
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[10]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_10portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_10.connectivity_checking = "OFF",
ram_block3a_10.logical_ram_name = "ALTSYNCRAM",
ram_block3a_10.mixed_port_feed_through_mode = "dont_care",
ram_block3a_10.operation_mode = "dual_port",
ram_block3a_10.port_a_address_width = 12,
ram_block3a_10.port_a_data_width = 1,
ram_block3a_10.port_a_first_address = 0,
ram_block3a_10.port_a_first_bit_number = 10,
ram_block3a_10.port_a_last_address = 4095,
ram_block3a_10.port_a_logical_ram_depth = 4096,
ram_block3a_10.port_a_logical_ram_width = 16,
ram_block3a_10.port_b_address_clear = "none",
ram_block3a_10.port_b_address_clock = "clock1",
ram_block3a_10.port_b_address_width = 12,
ram_block3a_10.port_b_data_out_clear = "none",
ram_block3a_10.port_b_data_out_clock = "none",
ram_block3a_10.port_b_data_width = 1,
ram_block3a_10.port_b_first_address = 0,
ram_block3a_10.port_b_first_bit_number = 10,
ram_block3a_10.port_b_last_address = 4095,
ram_block3a_10.port_b_logical_ram_depth = 4096,
ram_block3a_10.port_b_logical_ram_width = 16,
ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_10.ram_block_type = "auto",
ram_block3a_10.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_11
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[11]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_11portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_11.connectivity_checking = "OFF",
ram_block3a_11.logical_ram_name = "ALTSYNCRAM",
ram_block3a_11.mixed_port_feed_through_mode = "dont_care",
ram_block3a_11.operation_mode = "dual_port",
ram_block3a_11.port_a_address_width = 12,
ram_block3a_11.port_a_data_width = 1,
ram_block3a_11.port_a_first_address = 0,
ram_block3a_11.port_a_first_bit_number = 11,
ram_block3a_11.port_a_last_address = 4095,
ram_block3a_11.port_a_logical_ram_depth = 4096,
ram_block3a_11.port_a_logical_ram_width = 16,
ram_block3a_11.port_b_address_clear = "none",
ram_block3a_11.port_b_address_clock = "clock1",
ram_block3a_11.port_b_address_width = 12,
ram_block3a_11.port_b_data_out_clear = "none",
ram_block3a_11.port_b_data_out_clock = "none",
ram_block3a_11.port_b_data_width = 1,
ram_block3a_11.port_b_first_address = 0,
ram_block3a_11.port_b_first_bit_number = 11,
ram_block3a_11.port_b_last_address = 4095,
ram_block3a_11.port_b_logical_ram_depth = 4096,
ram_block3a_11.port_b_logical_ram_width = 16,
ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_11.ram_block_type = "auto",
ram_block3a_11.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_12
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[12]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_12portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_12.connectivity_checking = "OFF",
ram_block3a_12.logical_ram_name = "ALTSYNCRAM",
ram_block3a_12.mixed_port_feed_through_mode = "dont_care",
ram_block3a_12.operation_mode = "dual_port",
ram_block3a_12.port_a_address_width = 12,
ram_block3a_12.port_a_data_width = 1,
ram_block3a_12.port_a_first_address = 0,
ram_block3a_12.port_a_first_bit_number = 12,
ram_block3a_12.port_a_last_address = 4095,
ram_block3a_12.port_a_logical_ram_depth = 4096,
ram_block3a_12.port_a_logical_ram_width = 16,
ram_block3a_12.port_b_address_clear = "none",
ram_block3a_12.port_b_address_clock = "clock1",
ram_block3a_12.port_b_address_width = 12,
ram_block3a_12.port_b_data_out_clear = "none",
ram_block3a_12.port_b_data_out_clock = "none",
ram_block3a_12.port_b_data_width = 1,
ram_block3a_12.port_b_first_address = 0,
ram_block3a_12.port_b_first_bit_number = 12,
ram_block3a_12.port_b_last_address = 4095,
ram_block3a_12.port_b_logical_ram_depth = 4096,
ram_block3a_12.port_b_logical_ram_width = 16,
ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_12.ram_block_type = "auto",
ram_block3a_12.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_13
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[13]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_13portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_13.connectivity_checking = "OFF",
ram_block3a_13.logical_ram_name = "ALTSYNCRAM",
ram_block3a_13.mixed_port_feed_through_mode = "dont_care",
ram_block3a_13.operation_mode = "dual_port",
ram_block3a_13.port_a_address_width = 12,
ram_block3a_13.port_a_data_width = 1,
ram_block3a_13.port_a_first_address = 0,
ram_block3a_13.port_a_first_bit_number = 13,
ram_block3a_13.port_a_last_address = 4095,
ram_block3a_13.port_a_logical_ram_depth = 4096,
ram_block3a_13.port_a_logical_ram_width = 16,
ram_block3a_13.port_b_address_clear = "none",
ram_block3a_13.port_b_address_clock = "clock1",
ram_block3a_13.port_b_address_width = 12,
ram_block3a_13.port_b_data_out_clear = "none",
ram_block3a_13.port_b_data_out_clock = "none",
ram_block3a_13.port_b_data_width = 1,
ram_block3a_13.port_b_first_address = 0,
ram_block3a_13.port_b_first_bit_number = 13,
ram_block3a_13.port_b_last_address = 4095,
ram_block3a_13.port_b_logical_ram_depth = 4096,
ram_block3a_13.port_b_logical_ram_width = 16,
ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_13.ram_block_type = "auto",
ram_block3a_13.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_14
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[14]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_14portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_14.connectivity_checking = "OFF",
ram_block3a_14.logical_ram_name = "ALTSYNCRAM",
ram_block3a_14.mixed_port_feed_through_mode = "dont_care",
ram_block3a_14.operation_mode = "dual_port",
ram_block3a_14.port_a_address_width = 12,
ram_block3a_14.port_a_data_width = 1,
ram_block3a_14.port_a_first_address = 0,
ram_block3a_14.port_a_first_bit_number = 14,
ram_block3a_14.port_a_last_address = 4095,
ram_block3a_14.port_a_logical_ram_depth = 4096,
ram_block3a_14.port_a_logical_ram_width = 16,
ram_block3a_14.port_b_address_clear = "none",
ram_block3a_14.port_b_address_clock = "clock1",
ram_block3a_14.port_b_address_width = 12,
ram_block3a_14.port_b_data_out_clear = "none",
ram_block3a_14.port_b_data_out_clock = "none",
ram_block3a_14.port_b_data_width = 1,
ram_block3a_14.port_b_first_address = 0,
ram_block3a_14.port_b_first_bit_number = 14,
ram_block3a_14.port_b_last_address = 4095,
ram_block3a_14.port_b_logical_ram_depth = 4096,
ram_block3a_14.port_b_logical_ram_width = 16,
ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_14.ram_block_type = "auto",
ram_block3a_14.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_15
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[15]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_15portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_15.connectivity_checking = "OFF",
ram_block3a_15.logical_ram_name = "ALTSYNCRAM",
ram_block3a_15.mixed_port_feed_through_mode = "dont_care",
ram_block3a_15.operation_mode = "dual_port",
ram_block3a_15.port_a_address_width = 12,
ram_block3a_15.port_a_data_width = 1,
ram_block3a_15.port_a_first_address = 0,
ram_block3a_15.port_a_first_bit_number = 15,
ram_block3a_15.port_a_last_address = 4095,
ram_block3a_15.port_a_logical_ram_depth = 4096,
ram_block3a_15.port_a_logical_ram_width = 16,
ram_block3a_15.port_b_address_clear = "none",
ram_block3a_15.port_b_address_clock = "clock1",
ram_block3a_15.port_b_address_width = 12,
ram_block3a_15.port_b_data_out_clear = "none",
ram_block3a_15.port_b_data_out_clock = "none",
ram_block3a_15.port_b_data_width = 1,
ram_block3a_15.port_b_first_address = 0,
ram_block3a_15.port_b_first_bit_number = 15,
ram_block3a_15.port_b_last_address = 4095,
ram_block3a_15.port_b_logical_ram_depth = 4096,
ram_block3a_15.port_b_logical_ram_width = 16,
ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_15.ram_block_type = "auto",
ram_block3a_15.lpm_type = "cyclone_ram_block";
assign
address_a_wire = address_a,
address_b_wire = address_b,
q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]};
endmodule //fifo_4k_altsyncram_8pl
//dffpipe DELAY=1 WIDTH=12 clock clrn d q
//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//synthesis_resources = lut 12
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_dffpipe_bb3
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
input clock;
input clrn;
input [11:0] d;
output [11:0] q;
wire [11:0] wire_dffe4a_D;
reg [11:0] dffe4a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe4a[0:0] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[0:0] <= 1'b1;
else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0;
else if (ena == 1'b1) dffe4a[0:0] <= wire_dffe4a_D[0:0];
// synopsys translate_off
initial
dffe4a[1:1] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[1:1] <= 1'b1;
else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0;
else if (ena == 1'b1) dffe4a[1:1] <= wire_dffe4a_D[1:1];
// synopsys translate_off
initial
dffe4a[2:2] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[2:2] <= 1'b1;
else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0;
else if (ena == 1'b1) dffe4a[2:2] <= wire_dffe4a_D[2:2];
// synopsys translate_off
initial
dffe4a[3:3] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[3:3] <= 1'b1;
else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0;
else if (ena == 1'b1) dffe4a[3:3] <= wire_dffe4a_D[3:3];
// synopsys translate_off
initial
dffe4a[4:4] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[4:4] <= 1'b1;
else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0;
else if (ena == 1'b1) dffe4a[4:4] <= wire_dffe4a_D[4:4];
// synopsys translate_off
initial
dffe4a[5:5] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[5:5] <= 1'b1;
else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0;
else if (ena == 1'b1) dffe4a[5:5] <= wire_dffe4a_D[5:5];
// synopsys translate_off
initial
dffe4a[6:6] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[6:6] <= 1'b1;
else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0;
else if (ena == 1'b1) dffe4a[6:6] <= wire_dffe4a_D[6:6];
// synopsys translate_off
initial
dffe4a[7:7] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[7:7] <= 1'b1;
else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0;
else if (ena == 1'b1) dffe4a[7:7] <= wire_dffe4a_D[7:7];
// synopsys translate_off
initial
dffe4a[8:8] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[8:8] <= 1'b1;
else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0;
else if (ena == 1'b1) dffe4a[8:8] <= wire_dffe4a_D[8:8];
// synopsys translate_off
initial
dffe4a[9:9] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[9:9] <= 1'b1;
else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0;
else if (ena == 1'b1) dffe4a[9:9] <= wire_dffe4a_D[9:9];
// synopsys translate_off
initial
dffe4a[10:10] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[10:10] <= 1'b1;
else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0;
else if (ena == 1'b1) dffe4a[10:10] <= wire_dffe4a_D[10:10];
// synopsys translate_off
initial
dffe4a[11:11] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[11:11] <= 1'b1;
else if (clrn == 1'b0) dffe4a[11:11] <= 1'b0;
else if (ena == 1'b1) dffe4a[11:11] <= wire_dffe4a_D[11:11];
assign
wire_dffe4a_D = (d & {12{(~ sclr)}});
assign
ena = 1'b1,
prn = 1'b1,
q = dffe4a,
sclr = 1'b0;
endmodule //fifo_4k_dffpipe_bb3
//dffpipe WIDTH=12 clock clrn d q
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//dffpipe WIDTH=12 clock clrn d q
//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//synthesis_resources = lut 12
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_dffpipe_em2
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
input clock;
input clrn;
input [11:0] d;
output [11:0] q;
wire [11:0] wire_dffe6a_D;
reg [11:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe6a[0:0] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[0:0] <= 1'b1;
else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0;
else if (ena == 1'b1) dffe6a[0:0] <= wire_dffe6a_D[0:0];
// synopsys translate_off
initial
dffe6a[1:1] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[1:1] <= 1'b1;
else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0;
else if (ena == 1'b1) dffe6a[1:1] <= wire_dffe6a_D[1:1];
// synopsys translate_off
initial
dffe6a[2:2] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[2:2] <= 1'b1;
else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0;
else if (ena == 1'b1) dffe6a[2:2] <= wire_dffe6a_D[2:2];
// synopsys translate_off
initial
dffe6a[3:3] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[3:3] <= 1'b1;
else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0;
else if (ena == 1'b1) dffe6a[3:3] <= wire_dffe6a_D[3:3];
// synopsys translate_off
initial
dffe6a[4:4] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[4:4] <= 1'b1;
else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0;
else if (ena == 1'b1) dffe6a[4:4] <= wire_dffe6a_D[4:4];
// synopsys translate_off
initial
dffe6a[5:5] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[5:5] <= 1'b1;
else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0;
else if (ena == 1'b1) dffe6a[5:5] <= wire_dffe6a_D[5:5];
// synopsys translate_off
initial
dffe6a[6:6] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[6:6] <= 1'b1;
else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0;
else if (ena == 1'b1) dffe6a[6:6] <= wire_dffe6a_D[6:6];
// synopsys translate_off
initial
dffe6a[7:7] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[7:7] <= 1'b1;
else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0;
else if (ena == 1'b1) dffe6a[7:7] <= wire_dffe6a_D[7:7];
// synopsys translate_off
initial
dffe6a[8:8] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[8:8] <= 1'b1;
else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0;
else if (ena == 1'b1) dffe6a[8:8] <= wire_dffe6a_D[8:8];
// synopsys translate_off
initial
dffe6a[9:9] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[9:9] <= 1'b1;
else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0;
else if (ena == 1'b1) dffe6a[9:9] <= wire_dffe6a_D[9:9];
// synopsys translate_off
initial
dffe6a[10:10] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[10:10] <= 1'b1;
else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0;
else if (ena == 1'b1) dffe6a[10:10] <= wire_dffe6a_D[10:10];
// synopsys translate_off
initial
dffe6a[11:11] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[11:11] <= 1'b1;
else if (clrn == 1'b0) dffe6a[11:11] <= 1'b0;
else if (ena == 1'b1) dffe6a[11:11] <= wire_dffe6a_D[11:11];
assign
wire_dffe6a_D = (d & {12{(~ sclr)}});
assign
ena = 1'b1,
prn = 1'b1,
q = dffe6a,
sclr = 1'b0;
endmodule //fifo_4k_dffpipe_em2
//synthesis_resources = lut 12
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_alt_synch_pipe_em2
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */;
input clock;
input clrn;
input [11:0] d;
output [11:0] q;
wire [11:0] wire_dffpipe5_q;
fifo_4k_dffpipe_em2 dffpipe5
(
.clock(clock),
.clrn(clrn),
.d(d),
.q(wire_dffpipe5_q));
assign
q = wire_dffpipe5_q;
endmodule //fifo_4k_alt_synch_pipe_em2
//lpm_add_sub DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=12 dataa datab result
//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = lut 12
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_add_sub_b18
(
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input [11:0] dataa;
input [11:0] datab;
output [11:0] result;
wire [11:0] wire_add_sub_cella_combout;
wire [0:0] wire_add_sub_cella_0cout;
wire [0:0] wire_add_sub_cella_1cout;
wire [0:0] wire_add_sub_cella_2cout;
wire [0:0] wire_add_sub_cella_3cout;
wire [0:0] wire_add_sub_cella_4cout;
wire [0:0] wire_add_sub_cella_5cout;
wire [0:0] wire_add_sub_cella_6cout;
wire [0:0] wire_add_sub_cella_7cout;
wire [0:0] wire_add_sub_cella_8cout;
wire [0:0] wire_add_sub_cella_9cout;
wire [0:0] wire_add_sub_cella_10cout;
wire [11:0] wire_add_sub_cella_dataa;
wire [11:0] wire_add_sub_cella_datab;
cyclone_lcell add_sub_cella_0
(
.cin(1'b1),
.combout(wire_add_sub_cella_combout[0:0]),
.cout(wire_add_sub_cella_0cout[0:0]),
.dataa(wire_add_sub_cella_dataa[0:0]),
.datab(wire_add_sub_cella_datab[0:0]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_0.cin_used = "true",
add_sub_cella_0.lut_mask = "69b2",
add_sub_cella_0.operation_mode = "arithmetic",
add_sub_cella_0.sum_lutc_input = "cin",
add_sub_cella_0.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_1
(
.cin(wire_add_sub_cella_0cout[0:0]),
.combout(wire_add_sub_cella_combout[1:1]),
.cout(wire_add_sub_cella_1cout[0:0]),
.dataa(wire_add_sub_cella_dataa[1:1]),
.datab(wire_add_sub_cella_datab[1:1]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_1.cin_used = "true",
add_sub_cella_1.lut_mask = "69b2",
add_sub_cella_1.operation_mode = "arithmetic",
add_sub_cella_1.sum_lutc_input = "cin",
add_sub_cella_1.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_2
(
.cin(wire_add_sub_cella_1cout[0:0]),
.combout(wire_add_sub_cella_combout[2:2]),
.cout(wire_add_sub_cella_2cout[0:0]),
.dataa(wire_add_sub_cella_dataa[2:2]),
.datab(wire_add_sub_cella_datab[2:2]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_2.cin_used = "true",
add_sub_cella_2.lut_mask = "69b2",
add_sub_cella_2.operation_mode = "arithmetic",
add_sub_cella_2.sum_lutc_input = "cin",
add_sub_cella_2.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_3
(
.cin(wire_add_sub_cella_2cout[0:0]),
.combout(wire_add_sub_cella_combout[3:3]),
.cout(wire_add_sub_cella_3cout[0:0]),
.dataa(wire_add_sub_cella_dataa[3:3]),
.datab(wire_add_sub_cella_datab[3:3]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_3.cin_used = "true",
add_sub_cella_3.lut_mask = "69b2",
add_sub_cella_3.operation_mode = "arithmetic",
add_sub_cella_3.sum_lutc_input = "cin",
add_sub_cella_3.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_4
(
.cin(wire_add_sub_cella_3cout[0:0]),
.combout(wire_add_sub_cella_combout[4:4]),
.cout(wire_add_sub_cella_4cout[0:0]),
.dataa(wire_add_sub_cella_dataa[4:4]),
.datab(wire_add_sub_cella_datab[4:4]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_4.cin_used = "true",
add_sub_cella_4.lut_mask = "69b2",
add_sub_cella_4.operation_mode = "arithmetic",
add_sub_cella_4.sum_lutc_input = "cin",
add_sub_cella_4.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_5
(
.cin(wire_add_sub_cella_4cout[0:0]),
.combout(wire_add_sub_cella_combout[5:5]),
.cout(wire_add_sub_cella_5cout[0:0]),
.dataa(wire_add_sub_cella_dataa[5:5]),
.datab(wire_add_sub_cella_datab[5:5]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_5.cin_used = "true",
add_sub_cella_5.lut_mask = "69b2",
add_sub_cella_5.operation_mode = "arithmetic",
add_sub_cella_5.sum_lutc_input = "cin",
add_sub_cella_5.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_6
(
.cin(wire_add_sub_cella_5cout[0:0]),
.combout(wire_add_sub_cella_combout[6:6]),
.cout(wire_add_sub_cella_6cout[0:0]),
.dataa(wire_add_sub_cella_dataa[6:6]),
.datab(wire_add_sub_cella_datab[6:6]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_6.cin_used = "true",
add_sub_cella_6.lut_mask = "69b2",
add_sub_cella_6.operation_mode = "arithmetic",
add_sub_cella_6.sum_lutc_input = "cin",
add_sub_cella_6.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_7
(
.cin(wire_add_sub_cella_6cout[0:0]),
.combout(wire_add_sub_cella_combout[7:7]),
.cout(wire_add_sub_cella_7cout[0:0]),
.dataa(wire_add_sub_cella_dataa[7:7]),
.datab(wire_add_sub_cella_datab[7:7]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_7.cin_used = "true",
add_sub_cella_7.lut_mask = "69b2",
add_sub_cella_7.operation_mode = "arithmetic",
add_sub_cella_7.sum_lutc_input = "cin",
add_sub_cella_7.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_8
(
.cin(wire_add_sub_cella_7cout[0:0]),
.combout(wire_add_sub_cella_combout[8:8]),
.cout(wire_add_sub_cella_8cout[0:0]),
.dataa(wire_add_sub_cella_dataa[8:8]),
.datab(wire_add_sub_cella_datab[8:8]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_8.cin_used = "true",
add_sub_cella_8.lut_mask = "69b2",
add_sub_cella_8.operation_mode = "arithmetic",
add_sub_cella_8.sum_lutc_input = "cin",
add_sub_cella_8.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_9
(
.cin(wire_add_sub_cella_8cout[0:0]),
.combout(wire_add_sub_cella_combout[9:9]),
.cout(wire_add_sub_cella_9cout[0:0]),
.dataa(wire_add_sub_cella_dataa[9:9]),
.datab(wire_add_sub_cella_datab[9:9]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_9.cin_used = "true",
add_sub_cella_9.lut_mask = "69b2",
add_sub_cella_9.operation_mode = "arithmetic",
add_sub_cella_9.sum_lutc_input = "cin",
add_sub_cella_9.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_10
(
.cin(wire_add_sub_cella_9cout[0:0]),
.combout(wire_add_sub_cella_combout[10:10]),
.cout(wire_add_sub_cella_10cout[0:0]),
.dataa(wire_add_sub_cella_dataa[10:10]),
.datab(wire_add_sub_cella_datab[10:10]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_10.cin_used = "true",
add_sub_cella_10.lut_mask = "69b2",
add_sub_cella_10.operation_mode = "arithmetic",
add_sub_cella_10.sum_lutc_input = "cin",
add_sub_cella_10.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_11
(
.cin(wire_add_sub_cella_10cout[0:0]),
.combout(wire_add_sub_cella_combout[11:11]),
.cout(),
.dataa(wire_add_sub_cella_dataa[11:11]),
.datab(wire_add_sub_cella_datab[11:11]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_11.cin_used = "true",
add_sub_cella_11.lut_mask = "6969",
add_sub_cella_11.operation_mode = "normal",
add_sub_cella_11.sum_lutc_input = "cin",
add_sub_cella_11.lpm_type = "cyclone_lcell";
assign
wire_add_sub_cella_dataa = dataa,
wire_add_sub_cella_datab = datab;
assign
result = wire_add_sub_cella_combout;
endmodule //fifo_4k_add_sub_b18
//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=12 aeb dataa datab
//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=12 aeb dataa datab
//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = lut 104 M4K 16
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_dcfifo_6cq
(
aclr,
data,
q,
rdclk,
rdempty,
rdreq,
rdusedw,
wrclk,
wrfull,
wrreq,
wrusedw) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g|power_modified_counter_values\" -to \"ws_dgrp|dffpipe5|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp|dffpipe5|dffe6a\" }CUT=ON" */;
input aclr;
input [15:0] data;
output [15:0] q;
input rdclk;
output rdempty;
input rdreq;
output [11:0] rdusedw;
input wrclk;
output wrfull;
input wrreq;
output [11:0] wrusedw;
wire [11:0] wire_rdptr_g_gray2bin_bin;
wire [11:0] wire_rs_dgwp_gray2bin_bin;
wire [11:0] wire_wrptr_g_gray2bin_bin;
wire [11:0] wire_ws_dgrp_gray2bin_bin;
wire [11:0] wire_rdptr_g_q;
wire [11:0] wire_rdptr_g1p_q;
wire [11:0] wire_wrptr_g1p_q;
wire [15:0] wire_fifo_ram_q_b;
reg [11:0] delayed_wrptr_g;
reg [11:0] wrptr_g;
wire [11:0] wire_rs_brp_q;
wire [11:0] wire_rs_bwp_q;
wire [11:0] wire_rs_dgwp_q;
wire [11:0] wire_ws_brp_q;
wire [11:0] wire_ws_bwp_q;
wire [11:0] wire_ws_dgrp_q;
wire [11:0] wire_rdusedw_sub_result;
wire [11:0] wire_wrusedw_sub_result;
reg wire_rdempty_eq_comp_aeb_int;
wire wire_rdempty_eq_comp_aeb;
wire [11:0] wire_rdempty_eq_comp_dataa;
wire [11:0] wire_rdempty_eq_comp_datab;
reg wire_wrfull_eq_comp_aeb_int;
wire wire_wrfull_eq_comp_aeb;
wire [11:0] wire_wrfull_eq_comp_dataa;
wire [11:0] wire_wrfull_eq_comp_datab;
wire int_rdempty;
wire int_wrfull;
wire valid_rdreq;
wire valid_wrreq;
fifo_4k_a_gray2bin_9m4 rdptr_g_gray2bin
(
.bin(wire_rdptr_g_gray2bin_bin),
.gray(wire_rdptr_g_q));
fifo_4k_a_gray2bin_9m4 rs_dgwp_gray2bin
(
.bin(wire_rs_dgwp_gray2bin_bin),
.gray(wire_rs_dgwp_q));
fifo_4k_a_gray2bin_9m4 wrptr_g_gray2bin
(
.bin(wire_wrptr_g_gray2bin_bin),
.gray(wrptr_g));
fifo_4k_a_gray2bin_9m4 ws_dgrp_gray2bin
(
.bin(wire_ws_dgrp_gray2bin_bin),
.gray(wire_ws_dgrp_q));
fifo_4k_a_graycounter_826 rdptr_g
(
.aclr(aclr),
.clock(rdclk),
.cnt_en(valid_rdreq),
.q(wire_rdptr_g_q));
fifo_4k_a_graycounter_3r6 rdptr_g1p
(
.aclr(aclr),
.clock(rdclk),
.cnt_en(valid_rdreq),
.q(wire_rdptr_g1p_q));
fifo_4k_a_graycounter_3r6 wrptr_g1p
(
.aclr(aclr),
.clock(wrclk),
.cnt_en(valid_wrreq),
.q(wire_wrptr_g1p_q));
fifo_4k_altsyncram_8pl fifo_ram
(
.address_a(wrptr_g),
.address_b(((wire_rdptr_g_q & {12{int_rdempty}}) | (wire_rdptr_g1p_q & {12{(~ int_rdempty)}}))),
.clock0(wrclk),
.clock1(rdclk),
.clocken1((valid_rdreq | int_rdempty)),
.data_a(data),
.q_b(wire_fifo_ram_q_b),
.wren_a(valid_wrreq));
// synopsys translate_off
initial
delayed_wrptr_g = 0;
// synopsys translate_on
always @ ( posedge wrclk or posedge aclr)
if (aclr == 1'b1) delayed_wrptr_g <= 12'b0;
else delayed_wrptr_g <= wrptr_g;
// synopsys translate_off
initial
wrptr_g = 0;
// synopsys translate_on
always @ ( posedge wrclk or posedge aclr)
if (aclr == 1'b1) wrptr_g <= 12'b0;
else if (valid_wrreq == 1'b1) wrptr_g <= wire_wrptr_g1p_q;
fifo_4k_dffpipe_bb3 rs_brp
(
.clock(rdclk),
.clrn((~ aclr)),
.d(wire_rdptr_g_gray2bin_bin),
.q(wire_rs_brp_q));
fifo_4k_dffpipe_bb3 rs_bwp
(
.clock(rdclk),
.clrn((~ aclr)),
.d(wire_rs_dgwp_gray2bin_bin),
.q(wire_rs_bwp_q));
fifo_4k_alt_synch_pipe_em2 rs_dgwp
(
.clock(rdclk),
.clrn((~ aclr)),
.d(delayed_wrptr_g),
.q(wire_rs_dgwp_q));
fifo_4k_dffpipe_bb3 ws_brp
(
.clock(wrclk),
.clrn((~ aclr)),
.d(wire_ws_dgrp_gray2bin_bin),
.q(wire_ws_brp_q));
fifo_4k_dffpipe_bb3 ws_bwp
(
.clock(wrclk),
.clrn((~ aclr)),
.d(wire_wrptr_g_gray2bin_bin),
.q(wire_ws_bwp_q));
fifo_4k_alt_synch_pipe_em2 ws_dgrp
(
.clock(wrclk),
.clrn((~ aclr)),
.d(wire_rdptr_g_q),
.q(wire_ws_dgrp_q));
fifo_4k_add_sub_b18 rdusedw_sub
(
.dataa(wire_rs_bwp_q),
.datab(wire_rs_brp_q),
.result(wire_rdusedw_sub_result));
fifo_4k_add_sub_b18 wrusedw_sub
(
.dataa(wire_ws_bwp_q),
.datab(wire_ws_brp_q),
.result(wire_wrusedw_sub_result));
always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab)
if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab)
begin
wire_rdempty_eq_comp_aeb_int = 1'b1;
end
else
begin
wire_rdempty_eq_comp_aeb_int = 1'b0;
end
assign
wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int;
assign
wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q,
wire_rdempty_eq_comp_datab = wire_rdptr_g_q;
always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab)
if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab)
begin
wire_wrfull_eq_comp_aeb_int = 1'b1;
end
else
begin
wire_wrfull_eq_comp_aeb_int = 1'b0;
end
assign
wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int;
assign
wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q,
wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q;
assign
int_rdempty = wire_rdempty_eq_comp_aeb,
int_wrfull = wire_wrfull_eq_comp_aeb,
q = wire_fifo_ram_q_b,
rdempty = int_rdempty,
rdusedw = wire_rdusedw_sub_result,
valid_rdreq = rdreq,
valid_wrreq = wrreq,
wrfull = int_wrfull,
wrusedw = wire_wrusedw_sub_result;
endmodule //fifo_4k_dcfifo_6cq
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_4k (
data,
wrreq,
rdreq,
rdclk,
wrclk,
aclr,
q,
rdempty,
rdusedw,
wrfull,
wrusedw)/* synthesis synthesis_clearbox = 1 */;
input [15:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
wire sub_wire0;
wire [11:0] sub_wire1;
wire sub_wire2;
wire [15:0] sub_wire3;
wire [11:0] sub_wire4;
wire rdempty = sub_wire0;
wire [11:0] wrusedw = sub_wire1[11:0];
wire wrfull = sub_wire2;
wire [15:0] q = sub_wire3[15:0];
wire [11:0] rdusedw = sub_wire4[11:0];
fifo_4k_dcfifo_6cq fifo_4k_dcfifo_6cq_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.q (sub_wire3),
.rdusedw (sub_wire4));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE
|
// megafunction wizard: %FIFO%CBX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_4k.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=4096 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTHU=12 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//a_gray2bin device_family="Cyclone" WIDTH=12 bin gray
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_a_gray2bin_9m4
(
bin,
gray) /* synthesis synthesis_clearbox=1 */;
output [11:0] bin;
input [11:0] gray;
wire xor0;
wire xor1;
wire xor10;
wire xor2;
wire xor3;
wire xor4;
wire xor5;
wire xor6;
wire xor7;
wire xor8;
wire xor9;
assign
bin = {gray[11], xor10, xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0},
xor0 = (gray[0] ^ xor1),
xor1 = (gray[1] ^ xor2),
xor10 = (gray[11] ^ gray[10]),
xor2 = (gray[2] ^ xor3),
xor3 = (gray[3] ^ xor4),
xor4 = (gray[4] ^ xor5),
xor5 = (gray[5] ^ xor6),
xor6 = (gray[6] ^ xor7),
xor7 = (gray[7] ^ xor8),
xor8 = (gray[8] ^ xor9),
xor9 = (gray[9] ^ xor10);
endmodule //fifo_4k_a_gray2bin_9m4
//a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=12 aclr clock cnt_en q
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = lut 13
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_a_graycounter_826
(
aclr,
clock,
cnt_en,
q) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clock;
input cnt_en;
output [11:0] q;
wire [0:0] wire_countera_0cout;
wire [0:0] wire_countera_1cout;
wire [0:0] wire_countera_2cout;
wire [0:0] wire_countera_3cout;
wire [0:0] wire_countera_4cout;
wire [0:0] wire_countera_5cout;
wire [0:0] wire_countera_6cout;
wire [0:0] wire_countera_7cout;
wire [0:0] wire_countera_8cout;
wire [0:0] wire_countera_9cout;
wire [0:0] wire_countera_10cout;
wire [11:0] wire_countera_regout;
wire wire_parity_cout;
wire wire_parity_regout;
wire [11:0] power_modified_counter_values;
wire sclr;
wire updown;
cyclone_lcell countera_0
(
.aclr(aclr),
.cin(wire_parity_cout),
.clk(clock),
.combout(),
.cout(wire_countera_0cout[0:0]),
.dataa(cnt_en),
.datab(wire_countera_regout[0:0]),
.ena(1'b1),
.regout(wire_countera_regout[0:0]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_0.cin_used = "true",
countera_0.lut_mask = "c6a0",
countera_0.operation_mode = "arithmetic",
countera_0.sum_lutc_input = "cin",
countera_0.synch_mode = "on",
countera_0.lpm_type = "cyclone_lcell";
cyclone_lcell countera_1
(
.aclr(aclr),
.cin(wire_countera_0cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_1cout[0:0]),
.dataa(power_modified_counter_values[0]),
.datab(power_modified_counter_values[1]),
.ena(1'b1),
.regout(wire_countera_regout[1:1]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_1.cin_used = "true",
countera_1.lut_mask = "6c50",
countera_1.operation_mode = "arithmetic",
countera_1.sum_lutc_input = "cin",
countera_1.synch_mode = "on",
countera_1.lpm_type = "cyclone_lcell";
cyclone_lcell countera_2
(
.aclr(aclr),
.cin(wire_countera_1cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_2cout[0:0]),
.dataa(power_modified_counter_values[1]),
.datab(power_modified_counter_values[2]),
.ena(1'b1),
.regout(wire_countera_regout[2:2]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_2.cin_used = "true",
countera_2.lut_mask = "6c50",
countera_2.operation_mode = "arithmetic",
countera_2.sum_lutc_input = "cin",
countera_2.synch_mode = "on",
countera_2.lpm_type = "cyclone_lcell";
cyclone_lcell countera_3
(
.aclr(aclr),
.cin(wire_countera_2cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_3cout[0:0]),
.dataa(power_modified_counter_values[2]),
.datab(power_modified_counter_values[3]),
.ena(1'b1),
.regout(wire_countera_regout[3:3]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_3.cin_used = "true",
countera_3.lut_mask = "6c50",
countera_3.operation_mode = "arithmetic",
countera_3.sum_lutc_input = "cin",
countera_3.synch_mode = "on",
countera_3.lpm_type = "cyclone_lcell";
cyclone_lcell countera_4
(
.aclr(aclr),
.cin(wire_countera_3cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_4cout[0:0]),
.dataa(power_modified_counter_values[3]),
.datab(power_modified_counter_values[4]),
.ena(1'b1),
.regout(wire_countera_regout[4:4]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_4.cin_used = "true",
countera_4.lut_mask = "6c50",
countera_4.operation_mode = "arithmetic",
countera_4.sum_lutc_input = "cin",
countera_4.synch_mode = "on",
countera_4.lpm_type = "cyclone_lcell";
cyclone_lcell countera_5
(
.aclr(aclr),
.cin(wire_countera_4cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_5cout[0:0]),
.dataa(power_modified_counter_values[4]),
.datab(power_modified_counter_values[5]),
.ena(1'b1),
.regout(wire_countera_regout[5:5]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_5.cin_used = "true",
countera_5.lut_mask = "6c50",
countera_5.operation_mode = "arithmetic",
countera_5.sum_lutc_input = "cin",
countera_5.synch_mode = "on",
countera_5.lpm_type = "cyclone_lcell";
cyclone_lcell countera_6
(
.aclr(aclr),
.cin(wire_countera_5cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_6cout[0:0]),
.dataa(power_modified_counter_values[5]),
.datab(power_modified_counter_values[6]),
.ena(1'b1),
.regout(wire_countera_regout[6:6]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_6.cin_used = "true",
countera_6.lut_mask = "6c50",
countera_6.operation_mode = "arithmetic",
countera_6.sum_lutc_input = "cin",
countera_6.synch_mode = "on",
countera_6.lpm_type = "cyclone_lcell";
cyclone_lcell countera_7
(
.aclr(aclr),
.cin(wire_countera_6cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_7cout[0:0]),
.dataa(power_modified_counter_values[6]),
.datab(power_modified_counter_values[7]),
.ena(1'b1),
.regout(wire_countera_regout[7:7]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_7.cin_used = "true",
countera_7.lut_mask = "6c50",
countera_7.operation_mode = "arithmetic",
countera_7.sum_lutc_input = "cin",
countera_7.synch_mode = "on",
countera_7.lpm_type = "cyclone_lcell";
cyclone_lcell countera_8
(
.aclr(aclr),
.cin(wire_countera_7cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_8cout[0:0]),
.dataa(power_modified_counter_values[7]),
.datab(power_modified_counter_values[8]),
.ena(1'b1),
.regout(wire_countera_regout[8:8]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_8.cin_used = "true",
countera_8.lut_mask = "6c50",
countera_8.operation_mode = "arithmetic",
countera_8.sum_lutc_input = "cin",
countera_8.synch_mode = "on",
countera_8.lpm_type = "cyclone_lcell";
cyclone_lcell countera_9
(
.aclr(aclr),
.cin(wire_countera_8cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_9cout[0:0]),
.dataa(power_modified_counter_values[8]),
.datab(power_modified_counter_values[9]),
.ena(1'b1),
.regout(wire_countera_regout[9:9]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_9.cin_used = "true",
countera_9.lut_mask = "6c50",
countera_9.operation_mode = "arithmetic",
countera_9.sum_lutc_input = "cin",
countera_9.synch_mode = "on",
countera_9.lpm_type = "cyclone_lcell";
cyclone_lcell countera_10
(
.aclr(aclr),
.cin(wire_countera_9cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_10cout[0:0]),
.dataa(power_modified_counter_values[9]),
.datab(power_modified_counter_values[10]),
.ena(1'b1),
.regout(wire_countera_regout[10:10]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_10.cin_used = "true",
countera_10.lut_mask = "6c50",
countera_10.operation_mode = "arithmetic",
countera_10.sum_lutc_input = "cin",
countera_10.synch_mode = "on",
countera_10.lpm_type = "cyclone_lcell";
cyclone_lcell countera_11
(
.aclr(aclr),
.cin(wire_countera_10cout[0:0]),
.clk(clock),
.combout(),
.cout(),
.dataa(power_modified_counter_values[11]),
.ena(1'b1),
.regout(wire_countera_regout[11:11]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datab(1'b1),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_11.cin_used = "true",
countera_11.lut_mask = "5a5a",
countera_11.operation_mode = "normal",
countera_11.sum_lutc_input = "cin",
countera_11.synch_mode = "on",
countera_11.lpm_type = "cyclone_lcell";
cyclone_lcell parity
(
.aclr(aclr),
.cin(updown),
.clk(clock),
.combout(),
.cout(wire_parity_cout),
.dataa(cnt_en),
.datab(wire_parity_regout),
.ena(1'b1),
.regout(wire_parity_regout),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
parity.cin_used = "true",
parity.lut_mask = "6682",
parity.operation_mode = "arithmetic",
parity.synch_mode = "on",
parity.lpm_type = "cyclone_lcell";
assign
power_modified_counter_values = {wire_countera_regout[11:0]},
q = power_modified_counter_values,
sclr = 1'b0,
updown = 1'b1;
endmodule //fifo_4k_a_graycounter_826
//a_graycounter DEVICE_FAMILY="Cyclone" PVALUE=1 WIDTH=12 aclr clock cnt_en q
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = lut 13
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_a_graycounter_3r6
(
aclr,
clock,
cnt_en,
q) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clock;
input cnt_en;
output [11:0] q;
wire [0:0] wire_countera_0cout;
wire [0:0] wire_countera_1cout;
wire [0:0] wire_countera_2cout;
wire [0:0] wire_countera_3cout;
wire [0:0] wire_countera_4cout;
wire [0:0] wire_countera_5cout;
wire [0:0] wire_countera_6cout;
wire [0:0] wire_countera_7cout;
wire [0:0] wire_countera_8cout;
wire [0:0] wire_countera_9cout;
wire [0:0] wire_countera_10cout;
wire [11:0] wire_countera_regout;
wire wire_parity_cout;
wire wire_parity_regout;
wire [11:0] power_modified_counter_values;
wire sclr;
wire updown;
cyclone_lcell countera_0
(
.aclr(aclr),
.cin(wire_parity_cout),
.clk(clock),
.combout(),
.cout(wire_countera_0cout[0:0]),
.dataa(cnt_en),
.datab(wire_countera_regout[0:0]),
.ena(1'b1),
.regout(wire_countera_regout[0:0]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_0.cin_used = "true",
countera_0.lut_mask = "c6a0",
countera_0.operation_mode = "arithmetic",
countera_0.sum_lutc_input = "cin",
countera_0.synch_mode = "on",
countera_0.lpm_type = "cyclone_lcell";
cyclone_lcell countera_1
(
.aclr(aclr),
.cin(wire_countera_0cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_1cout[0:0]),
.dataa(power_modified_counter_values[0]),
.datab(power_modified_counter_values[1]),
.ena(1'b1),
.regout(wire_countera_regout[1:1]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_1.cin_used = "true",
countera_1.lut_mask = "6c50",
countera_1.operation_mode = "arithmetic",
countera_1.sum_lutc_input = "cin",
countera_1.synch_mode = "on",
countera_1.lpm_type = "cyclone_lcell";
cyclone_lcell countera_2
(
.aclr(aclr),
.cin(wire_countera_1cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_2cout[0:0]),
.dataa(power_modified_counter_values[1]),
.datab(power_modified_counter_values[2]),
.ena(1'b1),
.regout(wire_countera_regout[2:2]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_2.cin_used = "true",
countera_2.lut_mask = "6c50",
countera_2.operation_mode = "arithmetic",
countera_2.sum_lutc_input = "cin",
countera_2.synch_mode = "on",
countera_2.lpm_type = "cyclone_lcell";
cyclone_lcell countera_3
(
.aclr(aclr),
.cin(wire_countera_2cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_3cout[0:0]),
.dataa(power_modified_counter_values[2]),
.datab(power_modified_counter_values[3]),
.ena(1'b1),
.regout(wire_countera_regout[3:3]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_3.cin_used = "true",
countera_3.lut_mask = "6c50",
countera_3.operation_mode = "arithmetic",
countera_3.sum_lutc_input = "cin",
countera_3.synch_mode = "on",
countera_3.lpm_type = "cyclone_lcell";
cyclone_lcell countera_4
(
.aclr(aclr),
.cin(wire_countera_3cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_4cout[0:0]),
.dataa(power_modified_counter_values[3]),
.datab(power_modified_counter_values[4]),
.ena(1'b1),
.regout(wire_countera_regout[4:4]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_4.cin_used = "true",
countera_4.lut_mask = "6c50",
countera_4.operation_mode = "arithmetic",
countera_4.sum_lutc_input = "cin",
countera_4.synch_mode = "on",
countera_4.lpm_type = "cyclone_lcell";
cyclone_lcell countera_5
(
.aclr(aclr),
.cin(wire_countera_4cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_5cout[0:0]),
.dataa(power_modified_counter_values[4]),
.datab(power_modified_counter_values[5]),
.ena(1'b1),
.regout(wire_countera_regout[5:5]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_5.cin_used = "true",
countera_5.lut_mask = "6c50",
countera_5.operation_mode = "arithmetic",
countera_5.sum_lutc_input = "cin",
countera_5.synch_mode = "on",
countera_5.lpm_type = "cyclone_lcell";
cyclone_lcell countera_6
(
.aclr(aclr),
.cin(wire_countera_5cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_6cout[0:0]),
.dataa(power_modified_counter_values[5]),
.datab(power_modified_counter_values[6]),
.ena(1'b1),
.regout(wire_countera_regout[6:6]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_6.cin_used = "true",
countera_6.lut_mask = "6c50",
countera_6.operation_mode = "arithmetic",
countera_6.sum_lutc_input = "cin",
countera_6.synch_mode = "on",
countera_6.lpm_type = "cyclone_lcell";
cyclone_lcell countera_7
(
.aclr(aclr),
.cin(wire_countera_6cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_7cout[0:0]),
.dataa(power_modified_counter_values[6]),
.datab(power_modified_counter_values[7]),
.ena(1'b1),
.regout(wire_countera_regout[7:7]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_7.cin_used = "true",
countera_7.lut_mask = "6c50",
countera_7.operation_mode = "arithmetic",
countera_7.sum_lutc_input = "cin",
countera_7.synch_mode = "on",
countera_7.lpm_type = "cyclone_lcell";
cyclone_lcell countera_8
(
.aclr(aclr),
.cin(wire_countera_7cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_8cout[0:0]),
.dataa(power_modified_counter_values[7]),
.datab(power_modified_counter_values[8]),
.ena(1'b1),
.regout(wire_countera_regout[8:8]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_8.cin_used = "true",
countera_8.lut_mask = "6c50",
countera_8.operation_mode = "arithmetic",
countera_8.sum_lutc_input = "cin",
countera_8.synch_mode = "on",
countera_8.lpm_type = "cyclone_lcell";
cyclone_lcell countera_9
(
.aclr(aclr),
.cin(wire_countera_8cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_9cout[0:0]),
.dataa(power_modified_counter_values[8]),
.datab(power_modified_counter_values[9]),
.ena(1'b1),
.regout(wire_countera_regout[9:9]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_9.cin_used = "true",
countera_9.lut_mask = "6c50",
countera_9.operation_mode = "arithmetic",
countera_9.sum_lutc_input = "cin",
countera_9.synch_mode = "on",
countera_9.lpm_type = "cyclone_lcell";
cyclone_lcell countera_10
(
.aclr(aclr),
.cin(wire_countera_9cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_10cout[0:0]),
.dataa(power_modified_counter_values[9]),
.datab(power_modified_counter_values[10]),
.ena(1'b1),
.regout(wire_countera_regout[10:10]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_10.cin_used = "true",
countera_10.lut_mask = "6c50",
countera_10.operation_mode = "arithmetic",
countera_10.sum_lutc_input = "cin",
countera_10.synch_mode = "on",
countera_10.lpm_type = "cyclone_lcell";
cyclone_lcell countera_11
(
.aclr(aclr),
.cin(wire_countera_10cout[0:0]),
.clk(clock),
.combout(),
.cout(),
.dataa(power_modified_counter_values[11]),
.ena(1'b1),
.regout(wire_countera_regout[11:11]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datab(1'b1),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_11.cin_used = "true",
countera_11.lut_mask = "5a5a",
countera_11.operation_mode = "normal",
countera_11.sum_lutc_input = "cin",
countera_11.synch_mode = "on",
countera_11.lpm_type = "cyclone_lcell";
cyclone_lcell parity
(
.aclr(aclr),
.cin(updown),
.clk(clock),
.combout(),
.cout(wire_parity_cout),
.dataa(cnt_en),
.datab((~ wire_parity_regout)),
.ena(1'b1),
.regout(wire_parity_regout),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
parity.cin_used = "true",
parity.lut_mask = "9982",
parity.operation_mode = "arithmetic",
parity.synch_mode = "on",
parity.lpm_type = "cyclone_lcell";
assign
power_modified_counter_values = {wire_countera_regout[11:1], (~ wire_countera_regout[0])},
q = power_modified_counter_values,
sclr = 1'b0,
updown = 1'b1;
endmodule //fifo_4k_a_graycounter_3r6
//altsyncram ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=12 WIDTHAD_B=12 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a
//VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//synthesis_resources = M4K 16
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_altsyncram_8pl
(
address_a,
address_b,
clock0,
clock1,
clocken1,
data_a,
q_b,
wren_a) /* synthesis synthesis_clearbox=1 */;
input [11:0] address_a;
input [11:0] address_b;
input clock0;
input clock1;
input clocken1;
input [15:0] data_a;
output [15:0] q_b;
input wren_a;
wire [0:0] wire_ram_block3a_0portbdataout;
wire [0:0] wire_ram_block3a_1portbdataout;
wire [0:0] wire_ram_block3a_2portbdataout;
wire [0:0] wire_ram_block3a_3portbdataout;
wire [0:0] wire_ram_block3a_4portbdataout;
wire [0:0] wire_ram_block3a_5portbdataout;
wire [0:0] wire_ram_block3a_6portbdataout;
wire [0:0] wire_ram_block3a_7portbdataout;
wire [0:0] wire_ram_block3a_8portbdataout;
wire [0:0] wire_ram_block3a_9portbdataout;
wire [0:0] wire_ram_block3a_10portbdataout;
wire [0:0] wire_ram_block3a_11portbdataout;
wire [0:0] wire_ram_block3a_12portbdataout;
wire [0:0] wire_ram_block3a_13portbdataout;
wire [0:0] wire_ram_block3a_14portbdataout;
wire [0:0] wire_ram_block3a_15portbdataout;
wire [11:0] address_a_wire;
wire [11:0] address_b_wire;
cyclone_ram_block ram_block3a_0
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[0]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_0portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_0.connectivity_checking = "OFF",
ram_block3a_0.logical_ram_name = "ALTSYNCRAM",
ram_block3a_0.mixed_port_feed_through_mode = "dont_care",
ram_block3a_0.operation_mode = "dual_port",
ram_block3a_0.port_a_address_width = 12,
ram_block3a_0.port_a_data_width = 1,
ram_block3a_0.port_a_first_address = 0,
ram_block3a_0.port_a_first_bit_number = 0,
ram_block3a_0.port_a_last_address = 4095,
ram_block3a_0.port_a_logical_ram_depth = 4096,
ram_block3a_0.port_a_logical_ram_width = 16,
ram_block3a_0.port_b_address_clear = "none",
ram_block3a_0.port_b_address_clock = "clock1",
ram_block3a_0.port_b_address_width = 12,
ram_block3a_0.port_b_data_out_clear = "none",
ram_block3a_0.port_b_data_out_clock = "none",
ram_block3a_0.port_b_data_width = 1,
ram_block3a_0.port_b_first_address = 0,
ram_block3a_0.port_b_first_bit_number = 0,
ram_block3a_0.port_b_last_address = 4095,
ram_block3a_0.port_b_logical_ram_depth = 4096,
ram_block3a_0.port_b_logical_ram_width = 16,
ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_0.ram_block_type = "auto",
ram_block3a_0.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_1
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[1]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_1portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_1.connectivity_checking = "OFF",
ram_block3a_1.logical_ram_name = "ALTSYNCRAM",
ram_block3a_1.mixed_port_feed_through_mode = "dont_care",
ram_block3a_1.operation_mode = "dual_port",
ram_block3a_1.port_a_address_width = 12,
ram_block3a_1.port_a_data_width = 1,
ram_block3a_1.port_a_first_address = 0,
ram_block3a_1.port_a_first_bit_number = 1,
ram_block3a_1.port_a_last_address = 4095,
ram_block3a_1.port_a_logical_ram_depth = 4096,
ram_block3a_1.port_a_logical_ram_width = 16,
ram_block3a_1.port_b_address_clear = "none",
ram_block3a_1.port_b_address_clock = "clock1",
ram_block3a_1.port_b_address_width = 12,
ram_block3a_1.port_b_data_out_clear = "none",
ram_block3a_1.port_b_data_out_clock = "none",
ram_block3a_1.port_b_data_width = 1,
ram_block3a_1.port_b_first_address = 0,
ram_block3a_1.port_b_first_bit_number = 1,
ram_block3a_1.port_b_last_address = 4095,
ram_block3a_1.port_b_logical_ram_depth = 4096,
ram_block3a_1.port_b_logical_ram_width = 16,
ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_1.ram_block_type = "auto",
ram_block3a_1.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_2
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[2]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_2portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_2.connectivity_checking = "OFF",
ram_block3a_2.logical_ram_name = "ALTSYNCRAM",
ram_block3a_2.mixed_port_feed_through_mode = "dont_care",
ram_block3a_2.operation_mode = "dual_port",
ram_block3a_2.port_a_address_width = 12,
ram_block3a_2.port_a_data_width = 1,
ram_block3a_2.port_a_first_address = 0,
ram_block3a_2.port_a_first_bit_number = 2,
ram_block3a_2.port_a_last_address = 4095,
ram_block3a_2.port_a_logical_ram_depth = 4096,
ram_block3a_2.port_a_logical_ram_width = 16,
ram_block3a_2.port_b_address_clear = "none",
ram_block3a_2.port_b_address_clock = "clock1",
ram_block3a_2.port_b_address_width = 12,
ram_block3a_2.port_b_data_out_clear = "none",
ram_block3a_2.port_b_data_out_clock = "none",
ram_block3a_2.port_b_data_width = 1,
ram_block3a_2.port_b_first_address = 0,
ram_block3a_2.port_b_first_bit_number = 2,
ram_block3a_2.port_b_last_address = 4095,
ram_block3a_2.port_b_logical_ram_depth = 4096,
ram_block3a_2.port_b_logical_ram_width = 16,
ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_2.ram_block_type = "auto",
ram_block3a_2.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_3
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[3]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_3portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_3.connectivity_checking = "OFF",
ram_block3a_3.logical_ram_name = "ALTSYNCRAM",
ram_block3a_3.mixed_port_feed_through_mode = "dont_care",
ram_block3a_3.operation_mode = "dual_port",
ram_block3a_3.port_a_address_width = 12,
ram_block3a_3.port_a_data_width = 1,
ram_block3a_3.port_a_first_address = 0,
ram_block3a_3.port_a_first_bit_number = 3,
ram_block3a_3.port_a_last_address = 4095,
ram_block3a_3.port_a_logical_ram_depth = 4096,
ram_block3a_3.port_a_logical_ram_width = 16,
ram_block3a_3.port_b_address_clear = "none",
ram_block3a_3.port_b_address_clock = "clock1",
ram_block3a_3.port_b_address_width = 12,
ram_block3a_3.port_b_data_out_clear = "none",
ram_block3a_3.port_b_data_out_clock = "none",
ram_block3a_3.port_b_data_width = 1,
ram_block3a_3.port_b_first_address = 0,
ram_block3a_3.port_b_first_bit_number = 3,
ram_block3a_3.port_b_last_address = 4095,
ram_block3a_3.port_b_logical_ram_depth = 4096,
ram_block3a_3.port_b_logical_ram_width = 16,
ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_3.ram_block_type = "auto",
ram_block3a_3.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_4
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[4]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_4portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_4.connectivity_checking = "OFF",
ram_block3a_4.logical_ram_name = "ALTSYNCRAM",
ram_block3a_4.mixed_port_feed_through_mode = "dont_care",
ram_block3a_4.operation_mode = "dual_port",
ram_block3a_4.port_a_address_width = 12,
ram_block3a_4.port_a_data_width = 1,
ram_block3a_4.port_a_first_address = 0,
ram_block3a_4.port_a_first_bit_number = 4,
ram_block3a_4.port_a_last_address = 4095,
ram_block3a_4.port_a_logical_ram_depth = 4096,
ram_block3a_4.port_a_logical_ram_width = 16,
ram_block3a_4.port_b_address_clear = "none",
ram_block3a_4.port_b_address_clock = "clock1",
ram_block3a_4.port_b_address_width = 12,
ram_block3a_4.port_b_data_out_clear = "none",
ram_block3a_4.port_b_data_out_clock = "none",
ram_block3a_4.port_b_data_width = 1,
ram_block3a_4.port_b_first_address = 0,
ram_block3a_4.port_b_first_bit_number = 4,
ram_block3a_4.port_b_last_address = 4095,
ram_block3a_4.port_b_logical_ram_depth = 4096,
ram_block3a_4.port_b_logical_ram_width = 16,
ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_4.ram_block_type = "auto",
ram_block3a_4.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_5
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[5]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_5portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_5.connectivity_checking = "OFF",
ram_block3a_5.logical_ram_name = "ALTSYNCRAM",
ram_block3a_5.mixed_port_feed_through_mode = "dont_care",
ram_block3a_5.operation_mode = "dual_port",
ram_block3a_5.port_a_address_width = 12,
ram_block3a_5.port_a_data_width = 1,
ram_block3a_5.port_a_first_address = 0,
ram_block3a_5.port_a_first_bit_number = 5,
ram_block3a_5.port_a_last_address = 4095,
ram_block3a_5.port_a_logical_ram_depth = 4096,
ram_block3a_5.port_a_logical_ram_width = 16,
ram_block3a_5.port_b_address_clear = "none",
ram_block3a_5.port_b_address_clock = "clock1",
ram_block3a_5.port_b_address_width = 12,
ram_block3a_5.port_b_data_out_clear = "none",
ram_block3a_5.port_b_data_out_clock = "none",
ram_block3a_5.port_b_data_width = 1,
ram_block3a_5.port_b_first_address = 0,
ram_block3a_5.port_b_first_bit_number = 5,
ram_block3a_5.port_b_last_address = 4095,
ram_block3a_5.port_b_logical_ram_depth = 4096,
ram_block3a_5.port_b_logical_ram_width = 16,
ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_5.ram_block_type = "auto",
ram_block3a_5.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_6
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[6]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_6portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_6.connectivity_checking = "OFF",
ram_block3a_6.logical_ram_name = "ALTSYNCRAM",
ram_block3a_6.mixed_port_feed_through_mode = "dont_care",
ram_block3a_6.operation_mode = "dual_port",
ram_block3a_6.port_a_address_width = 12,
ram_block3a_6.port_a_data_width = 1,
ram_block3a_6.port_a_first_address = 0,
ram_block3a_6.port_a_first_bit_number = 6,
ram_block3a_6.port_a_last_address = 4095,
ram_block3a_6.port_a_logical_ram_depth = 4096,
ram_block3a_6.port_a_logical_ram_width = 16,
ram_block3a_6.port_b_address_clear = "none",
ram_block3a_6.port_b_address_clock = "clock1",
ram_block3a_6.port_b_address_width = 12,
ram_block3a_6.port_b_data_out_clear = "none",
ram_block3a_6.port_b_data_out_clock = "none",
ram_block3a_6.port_b_data_width = 1,
ram_block3a_6.port_b_first_address = 0,
ram_block3a_6.port_b_first_bit_number = 6,
ram_block3a_6.port_b_last_address = 4095,
ram_block3a_6.port_b_logical_ram_depth = 4096,
ram_block3a_6.port_b_logical_ram_width = 16,
ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_6.ram_block_type = "auto",
ram_block3a_6.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_7
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[7]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_7portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_7.connectivity_checking = "OFF",
ram_block3a_7.logical_ram_name = "ALTSYNCRAM",
ram_block3a_7.mixed_port_feed_through_mode = "dont_care",
ram_block3a_7.operation_mode = "dual_port",
ram_block3a_7.port_a_address_width = 12,
ram_block3a_7.port_a_data_width = 1,
ram_block3a_7.port_a_first_address = 0,
ram_block3a_7.port_a_first_bit_number = 7,
ram_block3a_7.port_a_last_address = 4095,
ram_block3a_7.port_a_logical_ram_depth = 4096,
ram_block3a_7.port_a_logical_ram_width = 16,
ram_block3a_7.port_b_address_clear = "none",
ram_block3a_7.port_b_address_clock = "clock1",
ram_block3a_7.port_b_address_width = 12,
ram_block3a_7.port_b_data_out_clear = "none",
ram_block3a_7.port_b_data_out_clock = "none",
ram_block3a_7.port_b_data_width = 1,
ram_block3a_7.port_b_first_address = 0,
ram_block3a_7.port_b_first_bit_number = 7,
ram_block3a_7.port_b_last_address = 4095,
ram_block3a_7.port_b_logical_ram_depth = 4096,
ram_block3a_7.port_b_logical_ram_width = 16,
ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_7.ram_block_type = "auto",
ram_block3a_7.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_8
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[8]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_8portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_8.connectivity_checking = "OFF",
ram_block3a_8.logical_ram_name = "ALTSYNCRAM",
ram_block3a_8.mixed_port_feed_through_mode = "dont_care",
ram_block3a_8.operation_mode = "dual_port",
ram_block3a_8.port_a_address_width = 12,
ram_block3a_8.port_a_data_width = 1,
ram_block3a_8.port_a_first_address = 0,
ram_block3a_8.port_a_first_bit_number = 8,
ram_block3a_8.port_a_last_address = 4095,
ram_block3a_8.port_a_logical_ram_depth = 4096,
ram_block3a_8.port_a_logical_ram_width = 16,
ram_block3a_8.port_b_address_clear = "none",
ram_block3a_8.port_b_address_clock = "clock1",
ram_block3a_8.port_b_address_width = 12,
ram_block3a_8.port_b_data_out_clear = "none",
ram_block3a_8.port_b_data_out_clock = "none",
ram_block3a_8.port_b_data_width = 1,
ram_block3a_8.port_b_first_address = 0,
ram_block3a_8.port_b_first_bit_number = 8,
ram_block3a_8.port_b_last_address = 4095,
ram_block3a_8.port_b_logical_ram_depth = 4096,
ram_block3a_8.port_b_logical_ram_width = 16,
ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_8.ram_block_type = "auto",
ram_block3a_8.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_9
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[9]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_9portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_9.connectivity_checking = "OFF",
ram_block3a_9.logical_ram_name = "ALTSYNCRAM",
ram_block3a_9.mixed_port_feed_through_mode = "dont_care",
ram_block3a_9.operation_mode = "dual_port",
ram_block3a_9.port_a_address_width = 12,
ram_block3a_9.port_a_data_width = 1,
ram_block3a_9.port_a_first_address = 0,
ram_block3a_9.port_a_first_bit_number = 9,
ram_block3a_9.port_a_last_address = 4095,
ram_block3a_9.port_a_logical_ram_depth = 4096,
ram_block3a_9.port_a_logical_ram_width = 16,
ram_block3a_9.port_b_address_clear = "none",
ram_block3a_9.port_b_address_clock = "clock1",
ram_block3a_9.port_b_address_width = 12,
ram_block3a_9.port_b_data_out_clear = "none",
ram_block3a_9.port_b_data_out_clock = "none",
ram_block3a_9.port_b_data_width = 1,
ram_block3a_9.port_b_first_address = 0,
ram_block3a_9.port_b_first_bit_number = 9,
ram_block3a_9.port_b_last_address = 4095,
ram_block3a_9.port_b_logical_ram_depth = 4096,
ram_block3a_9.port_b_logical_ram_width = 16,
ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_9.ram_block_type = "auto",
ram_block3a_9.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_10
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[10]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_10portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_10.connectivity_checking = "OFF",
ram_block3a_10.logical_ram_name = "ALTSYNCRAM",
ram_block3a_10.mixed_port_feed_through_mode = "dont_care",
ram_block3a_10.operation_mode = "dual_port",
ram_block3a_10.port_a_address_width = 12,
ram_block3a_10.port_a_data_width = 1,
ram_block3a_10.port_a_first_address = 0,
ram_block3a_10.port_a_first_bit_number = 10,
ram_block3a_10.port_a_last_address = 4095,
ram_block3a_10.port_a_logical_ram_depth = 4096,
ram_block3a_10.port_a_logical_ram_width = 16,
ram_block3a_10.port_b_address_clear = "none",
ram_block3a_10.port_b_address_clock = "clock1",
ram_block3a_10.port_b_address_width = 12,
ram_block3a_10.port_b_data_out_clear = "none",
ram_block3a_10.port_b_data_out_clock = "none",
ram_block3a_10.port_b_data_width = 1,
ram_block3a_10.port_b_first_address = 0,
ram_block3a_10.port_b_first_bit_number = 10,
ram_block3a_10.port_b_last_address = 4095,
ram_block3a_10.port_b_logical_ram_depth = 4096,
ram_block3a_10.port_b_logical_ram_width = 16,
ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_10.ram_block_type = "auto",
ram_block3a_10.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_11
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[11]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_11portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_11.connectivity_checking = "OFF",
ram_block3a_11.logical_ram_name = "ALTSYNCRAM",
ram_block3a_11.mixed_port_feed_through_mode = "dont_care",
ram_block3a_11.operation_mode = "dual_port",
ram_block3a_11.port_a_address_width = 12,
ram_block3a_11.port_a_data_width = 1,
ram_block3a_11.port_a_first_address = 0,
ram_block3a_11.port_a_first_bit_number = 11,
ram_block3a_11.port_a_last_address = 4095,
ram_block3a_11.port_a_logical_ram_depth = 4096,
ram_block3a_11.port_a_logical_ram_width = 16,
ram_block3a_11.port_b_address_clear = "none",
ram_block3a_11.port_b_address_clock = "clock1",
ram_block3a_11.port_b_address_width = 12,
ram_block3a_11.port_b_data_out_clear = "none",
ram_block3a_11.port_b_data_out_clock = "none",
ram_block3a_11.port_b_data_width = 1,
ram_block3a_11.port_b_first_address = 0,
ram_block3a_11.port_b_first_bit_number = 11,
ram_block3a_11.port_b_last_address = 4095,
ram_block3a_11.port_b_logical_ram_depth = 4096,
ram_block3a_11.port_b_logical_ram_width = 16,
ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_11.ram_block_type = "auto",
ram_block3a_11.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_12
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[12]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_12portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_12.connectivity_checking = "OFF",
ram_block3a_12.logical_ram_name = "ALTSYNCRAM",
ram_block3a_12.mixed_port_feed_through_mode = "dont_care",
ram_block3a_12.operation_mode = "dual_port",
ram_block3a_12.port_a_address_width = 12,
ram_block3a_12.port_a_data_width = 1,
ram_block3a_12.port_a_first_address = 0,
ram_block3a_12.port_a_first_bit_number = 12,
ram_block3a_12.port_a_last_address = 4095,
ram_block3a_12.port_a_logical_ram_depth = 4096,
ram_block3a_12.port_a_logical_ram_width = 16,
ram_block3a_12.port_b_address_clear = "none",
ram_block3a_12.port_b_address_clock = "clock1",
ram_block3a_12.port_b_address_width = 12,
ram_block3a_12.port_b_data_out_clear = "none",
ram_block3a_12.port_b_data_out_clock = "none",
ram_block3a_12.port_b_data_width = 1,
ram_block3a_12.port_b_first_address = 0,
ram_block3a_12.port_b_first_bit_number = 12,
ram_block3a_12.port_b_last_address = 4095,
ram_block3a_12.port_b_logical_ram_depth = 4096,
ram_block3a_12.port_b_logical_ram_width = 16,
ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_12.ram_block_type = "auto",
ram_block3a_12.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_13
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[13]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_13portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_13.connectivity_checking = "OFF",
ram_block3a_13.logical_ram_name = "ALTSYNCRAM",
ram_block3a_13.mixed_port_feed_through_mode = "dont_care",
ram_block3a_13.operation_mode = "dual_port",
ram_block3a_13.port_a_address_width = 12,
ram_block3a_13.port_a_data_width = 1,
ram_block3a_13.port_a_first_address = 0,
ram_block3a_13.port_a_first_bit_number = 13,
ram_block3a_13.port_a_last_address = 4095,
ram_block3a_13.port_a_logical_ram_depth = 4096,
ram_block3a_13.port_a_logical_ram_width = 16,
ram_block3a_13.port_b_address_clear = "none",
ram_block3a_13.port_b_address_clock = "clock1",
ram_block3a_13.port_b_address_width = 12,
ram_block3a_13.port_b_data_out_clear = "none",
ram_block3a_13.port_b_data_out_clock = "none",
ram_block3a_13.port_b_data_width = 1,
ram_block3a_13.port_b_first_address = 0,
ram_block3a_13.port_b_first_bit_number = 13,
ram_block3a_13.port_b_last_address = 4095,
ram_block3a_13.port_b_logical_ram_depth = 4096,
ram_block3a_13.port_b_logical_ram_width = 16,
ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_13.ram_block_type = "auto",
ram_block3a_13.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_14
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[14]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_14portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_14.connectivity_checking = "OFF",
ram_block3a_14.logical_ram_name = "ALTSYNCRAM",
ram_block3a_14.mixed_port_feed_through_mode = "dont_care",
ram_block3a_14.operation_mode = "dual_port",
ram_block3a_14.port_a_address_width = 12,
ram_block3a_14.port_a_data_width = 1,
ram_block3a_14.port_a_first_address = 0,
ram_block3a_14.port_a_first_bit_number = 14,
ram_block3a_14.port_a_last_address = 4095,
ram_block3a_14.port_a_logical_ram_depth = 4096,
ram_block3a_14.port_a_logical_ram_width = 16,
ram_block3a_14.port_b_address_clear = "none",
ram_block3a_14.port_b_address_clock = "clock1",
ram_block3a_14.port_b_address_width = 12,
ram_block3a_14.port_b_data_out_clear = "none",
ram_block3a_14.port_b_data_out_clock = "none",
ram_block3a_14.port_b_data_width = 1,
ram_block3a_14.port_b_first_address = 0,
ram_block3a_14.port_b_first_bit_number = 14,
ram_block3a_14.port_b_last_address = 4095,
ram_block3a_14.port_b_logical_ram_depth = 4096,
ram_block3a_14.port_b_logical_ram_width = 16,
ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_14.ram_block_type = "auto",
ram_block3a_14.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_15
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[15]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_15portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_15.connectivity_checking = "OFF",
ram_block3a_15.logical_ram_name = "ALTSYNCRAM",
ram_block3a_15.mixed_port_feed_through_mode = "dont_care",
ram_block3a_15.operation_mode = "dual_port",
ram_block3a_15.port_a_address_width = 12,
ram_block3a_15.port_a_data_width = 1,
ram_block3a_15.port_a_first_address = 0,
ram_block3a_15.port_a_first_bit_number = 15,
ram_block3a_15.port_a_last_address = 4095,
ram_block3a_15.port_a_logical_ram_depth = 4096,
ram_block3a_15.port_a_logical_ram_width = 16,
ram_block3a_15.port_b_address_clear = "none",
ram_block3a_15.port_b_address_clock = "clock1",
ram_block3a_15.port_b_address_width = 12,
ram_block3a_15.port_b_data_out_clear = "none",
ram_block3a_15.port_b_data_out_clock = "none",
ram_block3a_15.port_b_data_width = 1,
ram_block3a_15.port_b_first_address = 0,
ram_block3a_15.port_b_first_bit_number = 15,
ram_block3a_15.port_b_last_address = 4095,
ram_block3a_15.port_b_logical_ram_depth = 4096,
ram_block3a_15.port_b_logical_ram_width = 16,
ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_15.ram_block_type = "auto",
ram_block3a_15.lpm_type = "cyclone_ram_block";
assign
address_a_wire = address_a,
address_b_wire = address_b,
q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]};
endmodule //fifo_4k_altsyncram_8pl
//dffpipe DELAY=1 WIDTH=12 clock clrn d q
//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//synthesis_resources = lut 12
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_dffpipe_bb3
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
input clock;
input clrn;
input [11:0] d;
output [11:0] q;
wire [11:0] wire_dffe4a_D;
reg [11:0] dffe4a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe4a[0:0] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[0:0] <= 1'b1;
else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0;
else if (ena == 1'b1) dffe4a[0:0] <= wire_dffe4a_D[0:0];
// synopsys translate_off
initial
dffe4a[1:1] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[1:1] <= 1'b1;
else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0;
else if (ena == 1'b1) dffe4a[1:1] <= wire_dffe4a_D[1:1];
// synopsys translate_off
initial
dffe4a[2:2] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[2:2] <= 1'b1;
else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0;
else if (ena == 1'b1) dffe4a[2:2] <= wire_dffe4a_D[2:2];
// synopsys translate_off
initial
dffe4a[3:3] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[3:3] <= 1'b1;
else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0;
else if (ena == 1'b1) dffe4a[3:3] <= wire_dffe4a_D[3:3];
// synopsys translate_off
initial
dffe4a[4:4] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[4:4] <= 1'b1;
else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0;
else if (ena == 1'b1) dffe4a[4:4] <= wire_dffe4a_D[4:4];
// synopsys translate_off
initial
dffe4a[5:5] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[5:5] <= 1'b1;
else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0;
else if (ena == 1'b1) dffe4a[5:5] <= wire_dffe4a_D[5:5];
// synopsys translate_off
initial
dffe4a[6:6] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[6:6] <= 1'b1;
else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0;
else if (ena == 1'b1) dffe4a[6:6] <= wire_dffe4a_D[6:6];
// synopsys translate_off
initial
dffe4a[7:7] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[7:7] <= 1'b1;
else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0;
else if (ena == 1'b1) dffe4a[7:7] <= wire_dffe4a_D[7:7];
// synopsys translate_off
initial
dffe4a[8:8] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[8:8] <= 1'b1;
else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0;
else if (ena == 1'b1) dffe4a[8:8] <= wire_dffe4a_D[8:8];
// synopsys translate_off
initial
dffe4a[9:9] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[9:9] <= 1'b1;
else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0;
else if (ena == 1'b1) dffe4a[9:9] <= wire_dffe4a_D[9:9];
// synopsys translate_off
initial
dffe4a[10:10] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[10:10] <= 1'b1;
else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0;
else if (ena == 1'b1) dffe4a[10:10] <= wire_dffe4a_D[10:10];
// synopsys translate_off
initial
dffe4a[11:11] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[11:11] <= 1'b1;
else if (clrn == 1'b0) dffe4a[11:11] <= 1'b0;
else if (ena == 1'b1) dffe4a[11:11] <= wire_dffe4a_D[11:11];
assign
wire_dffe4a_D = (d & {12{(~ sclr)}});
assign
ena = 1'b1,
prn = 1'b1,
q = dffe4a,
sclr = 1'b0;
endmodule //fifo_4k_dffpipe_bb3
//dffpipe WIDTH=12 clock clrn d q
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//dffpipe WIDTH=12 clock clrn d q
//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//synthesis_resources = lut 12
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_dffpipe_em2
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
input clock;
input clrn;
input [11:0] d;
output [11:0] q;
wire [11:0] wire_dffe6a_D;
reg [11:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe6a[0:0] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[0:0] <= 1'b1;
else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0;
else if (ena == 1'b1) dffe6a[0:0] <= wire_dffe6a_D[0:0];
// synopsys translate_off
initial
dffe6a[1:1] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[1:1] <= 1'b1;
else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0;
else if (ena == 1'b1) dffe6a[1:1] <= wire_dffe6a_D[1:1];
// synopsys translate_off
initial
dffe6a[2:2] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[2:2] <= 1'b1;
else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0;
else if (ena == 1'b1) dffe6a[2:2] <= wire_dffe6a_D[2:2];
// synopsys translate_off
initial
dffe6a[3:3] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[3:3] <= 1'b1;
else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0;
else if (ena == 1'b1) dffe6a[3:3] <= wire_dffe6a_D[3:3];
// synopsys translate_off
initial
dffe6a[4:4] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[4:4] <= 1'b1;
else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0;
else if (ena == 1'b1) dffe6a[4:4] <= wire_dffe6a_D[4:4];
// synopsys translate_off
initial
dffe6a[5:5] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[5:5] <= 1'b1;
else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0;
else if (ena == 1'b1) dffe6a[5:5] <= wire_dffe6a_D[5:5];
// synopsys translate_off
initial
dffe6a[6:6] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[6:6] <= 1'b1;
else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0;
else if (ena == 1'b1) dffe6a[6:6] <= wire_dffe6a_D[6:6];
// synopsys translate_off
initial
dffe6a[7:7] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[7:7] <= 1'b1;
else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0;
else if (ena == 1'b1) dffe6a[7:7] <= wire_dffe6a_D[7:7];
// synopsys translate_off
initial
dffe6a[8:8] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[8:8] <= 1'b1;
else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0;
else if (ena == 1'b1) dffe6a[8:8] <= wire_dffe6a_D[8:8];
// synopsys translate_off
initial
dffe6a[9:9] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[9:9] <= 1'b1;
else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0;
else if (ena == 1'b1) dffe6a[9:9] <= wire_dffe6a_D[9:9];
// synopsys translate_off
initial
dffe6a[10:10] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[10:10] <= 1'b1;
else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0;
else if (ena == 1'b1) dffe6a[10:10] <= wire_dffe6a_D[10:10];
// synopsys translate_off
initial
dffe6a[11:11] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[11:11] <= 1'b1;
else if (clrn == 1'b0) dffe6a[11:11] <= 1'b0;
else if (ena == 1'b1) dffe6a[11:11] <= wire_dffe6a_D[11:11];
assign
wire_dffe6a_D = (d & {12{(~ sclr)}});
assign
ena = 1'b1,
prn = 1'b1,
q = dffe6a,
sclr = 1'b0;
endmodule //fifo_4k_dffpipe_em2
//synthesis_resources = lut 12
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_alt_synch_pipe_em2
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */;
input clock;
input clrn;
input [11:0] d;
output [11:0] q;
wire [11:0] wire_dffpipe5_q;
fifo_4k_dffpipe_em2 dffpipe5
(
.clock(clock),
.clrn(clrn),
.d(d),
.q(wire_dffpipe5_q));
assign
q = wire_dffpipe5_q;
endmodule //fifo_4k_alt_synch_pipe_em2
//lpm_add_sub DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=12 dataa datab result
//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = lut 12
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_add_sub_b18
(
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input [11:0] dataa;
input [11:0] datab;
output [11:0] result;
wire [11:0] wire_add_sub_cella_combout;
wire [0:0] wire_add_sub_cella_0cout;
wire [0:0] wire_add_sub_cella_1cout;
wire [0:0] wire_add_sub_cella_2cout;
wire [0:0] wire_add_sub_cella_3cout;
wire [0:0] wire_add_sub_cella_4cout;
wire [0:0] wire_add_sub_cella_5cout;
wire [0:0] wire_add_sub_cella_6cout;
wire [0:0] wire_add_sub_cella_7cout;
wire [0:0] wire_add_sub_cella_8cout;
wire [0:0] wire_add_sub_cella_9cout;
wire [0:0] wire_add_sub_cella_10cout;
wire [11:0] wire_add_sub_cella_dataa;
wire [11:0] wire_add_sub_cella_datab;
cyclone_lcell add_sub_cella_0
(
.cin(1'b1),
.combout(wire_add_sub_cella_combout[0:0]),
.cout(wire_add_sub_cella_0cout[0:0]),
.dataa(wire_add_sub_cella_dataa[0:0]),
.datab(wire_add_sub_cella_datab[0:0]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_0.cin_used = "true",
add_sub_cella_0.lut_mask = "69b2",
add_sub_cella_0.operation_mode = "arithmetic",
add_sub_cella_0.sum_lutc_input = "cin",
add_sub_cella_0.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_1
(
.cin(wire_add_sub_cella_0cout[0:0]),
.combout(wire_add_sub_cella_combout[1:1]),
.cout(wire_add_sub_cella_1cout[0:0]),
.dataa(wire_add_sub_cella_dataa[1:1]),
.datab(wire_add_sub_cella_datab[1:1]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_1.cin_used = "true",
add_sub_cella_1.lut_mask = "69b2",
add_sub_cella_1.operation_mode = "arithmetic",
add_sub_cella_1.sum_lutc_input = "cin",
add_sub_cella_1.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_2
(
.cin(wire_add_sub_cella_1cout[0:0]),
.combout(wire_add_sub_cella_combout[2:2]),
.cout(wire_add_sub_cella_2cout[0:0]),
.dataa(wire_add_sub_cella_dataa[2:2]),
.datab(wire_add_sub_cella_datab[2:2]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_2.cin_used = "true",
add_sub_cella_2.lut_mask = "69b2",
add_sub_cella_2.operation_mode = "arithmetic",
add_sub_cella_2.sum_lutc_input = "cin",
add_sub_cella_2.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_3
(
.cin(wire_add_sub_cella_2cout[0:0]),
.combout(wire_add_sub_cella_combout[3:3]),
.cout(wire_add_sub_cella_3cout[0:0]),
.dataa(wire_add_sub_cella_dataa[3:3]),
.datab(wire_add_sub_cella_datab[3:3]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_3.cin_used = "true",
add_sub_cella_3.lut_mask = "69b2",
add_sub_cella_3.operation_mode = "arithmetic",
add_sub_cella_3.sum_lutc_input = "cin",
add_sub_cella_3.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_4
(
.cin(wire_add_sub_cella_3cout[0:0]),
.combout(wire_add_sub_cella_combout[4:4]),
.cout(wire_add_sub_cella_4cout[0:0]),
.dataa(wire_add_sub_cella_dataa[4:4]),
.datab(wire_add_sub_cella_datab[4:4]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_4.cin_used = "true",
add_sub_cella_4.lut_mask = "69b2",
add_sub_cella_4.operation_mode = "arithmetic",
add_sub_cella_4.sum_lutc_input = "cin",
add_sub_cella_4.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_5
(
.cin(wire_add_sub_cella_4cout[0:0]),
.combout(wire_add_sub_cella_combout[5:5]),
.cout(wire_add_sub_cella_5cout[0:0]),
.dataa(wire_add_sub_cella_dataa[5:5]),
.datab(wire_add_sub_cella_datab[5:5]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_5.cin_used = "true",
add_sub_cella_5.lut_mask = "69b2",
add_sub_cella_5.operation_mode = "arithmetic",
add_sub_cella_5.sum_lutc_input = "cin",
add_sub_cella_5.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_6
(
.cin(wire_add_sub_cella_5cout[0:0]),
.combout(wire_add_sub_cella_combout[6:6]),
.cout(wire_add_sub_cella_6cout[0:0]),
.dataa(wire_add_sub_cella_dataa[6:6]),
.datab(wire_add_sub_cella_datab[6:6]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_6.cin_used = "true",
add_sub_cella_6.lut_mask = "69b2",
add_sub_cella_6.operation_mode = "arithmetic",
add_sub_cella_6.sum_lutc_input = "cin",
add_sub_cella_6.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_7
(
.cin(wire_add_sub_cella_6cout[0:0]),
.combout(wire_add_sub_cella_combout[7:7]),
.cout(wire_add_sub_cella_7cout[0:0]),
.dataa(wire_add_sub_cella_dataa[7:7]),
.datab(wire_add_sub_cella_datab[7:7]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_7.cin_used = "true",
add_sub_cella_7.lut_mask = "69b2",
add_sub_cella_7.operation_mode = "arithmetic",
add_sub_cella_7.sum_lutc_input = "cin",
add_sub_cella_7.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_8
(
.cin(wire_add_sub_cella_7cout[0:0]),
.combout(wire_add_sub_cella_combout[8:8]),
.cout(wire_add_sub_cella_8cout[0:0]),
.dataa(wire_add_sub_cella_dataa[8:8]),
.datab(wire_add_sub_cella_datab[8:8]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_8.cin_used = "true",
add_sub_cella_8.lut_mask = "69b2",
add_sub_cella_8.operation_mode = "arithmetic",
add_sub_cella_8.sum_lutc_input = "cin",
add_sub_cella_8.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_9
(
.cin(wire_add_sub_cella_8cout[0:0]),
.combout(wire_add_sub_cella_combout[9:9]),
.cout(wire_add_sub_cella_9cout[0:0]),
.dataa(wire_add_sub_cella_dataa[9:9]),
.datab(wire_add_sub_cella_datab[9:9]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_9.cin_used = "true",
add_sub_cella_9.lut_mask = "69b2",
add_sub_cella_9.operation_mode = "arithmetic",
add_sub_cella_9.sum_lutc_input = "cin",
add_sub_cella_9.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_10
(
.cin(wire_add_sub_cella_9cout[0:0]),
.combout(wire_add_sub_cella_combout[10:10]),
.cout(wire_add_sub_cella_10cout[0:0]),
.dataa(wire_add_sub_cella_dataa[10:10]),
.datab(wire_add_sub_cella_datab[10:10]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_10.cin_used = "true",
add_sub_cella_10.lut_mask = "69b2",
add_sub_cella_10.operation_mode = "arithmetic",
add_sub_cella_10.sum_lutc_input = "cin",
add_sub_cella_10.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_11
(
.cin(wire_add_sub_cella_10cout[0:0]),
.combout(wire_add_sub_cella_combout[11:11]),
.cout(),
.dataa(wire_add_sub_cella_dataa[11:11]),
.datab(wire_add_sub_cella_datab[11:11]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_11.cin_used = "true",
add_sub_cella_11.lut_mask = "6969",
add_sub_cella_11.operation_mode = "normal",
add_sub_cella_11.sum_lutc_input = "cin",
add_sub_cella_11.lpm_type = "cyclone_lcell";
assign
wire_add_sub_cella_dataa = dataa,
wire_add_sub_cella_datab = datab;
assign
result = wire_add_sub_cella_combout;
endmodule //fifo_4k_add_sub_b18
//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=12 aeb dataa datab
//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=12 aeb dataa datab
//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = lut 104 M4K 16
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_4k_dcfifo_6cq
(
aclr,
data,
q,
rdclk,
rdempty,
rdreq,
rdusedw,
wrclk,
wrfull,
wrreq,
wrusedw) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g|power_modified_counter_values\" -to \"ws_dgrp|dffpipe5|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp|dffpipe5|dffe6a\" }CUT=ON" */;
input aclr;
input [15:0] data;
output [15:0] q;
input rdclk;
output rdempty;
input rdreq;
output [11:0] rdusedw;
input wrclk;
output wrfull;
input wrreq;
output [11:0] wrusedw;
wire [11:0] wire_rdptr_g_gray2bin_bin;
wire [11:0] wire_rs_dgwp_gray2bin_bin;
wire [11:0] wire_wrptr_g_gray2bin_bin;
wire [11:0] wire_ws_dgrp_gray2bin_bin;
wire [11:0] wire_rdptr_g_q;
wire [11:0] wire_rdptr_g1p_q;
wire [11:0] wire_wrptr_g1p_q;
wire [15:0] wire_fifo_ram_q_b;
reg [11:0] delayed_wrptr_g;
reg [11:0] wrptr_g;
wire [11:0] wire_rs_brp_q;
wire [11:0] wire_rs_bwp_q;
wire [11:0] wire_rs_dgwp_q;
wire [11:0] wire_ws_brp_q;
wire [11:0] wire_ws_bwp_q;
wire [11:0] wire_ws_dgrp_q;
wire [11:0] wire_rdusedw_sub_result;
wire [11:0] wire_wrusedw_sub_result;
reg wire_rdempty_eq_comp_aeb_int;
wire wire_rdempty_eq_comp_aeb;
wire [11:0] wire_rdempty_eq_comp_dataa;
wire [11:0] wire_rdempty_eq_comp_datab;
reg wire_wrfull_eq_comp_aeb_int;
wire wire_wrfull_eq_comp_aeb;
wire [11:0] wire_wrfull_eq_comp_dataa;
wire [11:0] wire_wrfull_eq_comp_datab;
wire int_rdempty;
wire int_wrfull;
wire valid_rdreq;
wire valid_wrreq;
fifo_4k_a_gray2bin_9m4 rdptr_g_gray2bin
(
.bin(wire_rdptr_g_gray2bin_bin),
.gray(wire_rdptr_g_q));
fifo_4k_a_gray2bin_9m4 rs_dgwp_gray2bin
(
.bin(wire_rs_dgwp_gray2bin_bin),
.gray(wire_rs_dgwp_q));
fifo_4k_a_gray2bin_9m4 wrptr_g_gray2bin
(
.bin(wire_wrptr_g_gray2bin_bin),
.gray(wrptr_g));
fifo_4k_a_gray2bin_9m4 ws_dgrp_gray2bin
(
.bin(wire_ws_dgrp_gray2bin_bin),
.gray(wire_ws_dgrp_q));
fifo_4k_a_graycounter_826 rdptr_g
(
.aclr(aclr),
.clock(rdclk),
.cnt_en(valid_rdreq),
.q(wire_rdptr_g_q));
fifo_4k_a_graycounter_3r6 rdptr_g1p
(
.aclr(aclr),
.clock(rdclk),
.cnt_en(valid_rdreq),
.q(wire_rdptr_g1p_q));
fifo_4k_a_graycounter_3r6 wrptr_g1p
(
.aclr(aclr),
.clock(wrclk),
.cnt_en(valid_wrreq),
.q(wire_wrptr_g1p_q));
fifo_4k_altsyncram_8pl fifo_ram
(
.address_a(wrptr_g),
.address_b(((wire_rdptr_g_q & {12{int_rdempty}}) | (wire_rdptr_g1p_q & {12{(~ int_rdempty)}}))),
.clock0(wrclk),
.clock1(rdclk),
.clocken1((valid_rdreq | int_rdempty)),
.data_a(data),
.q_b(wire_fifo_ram_q_b),
.wren_a(valid_wrreq));
// synopsys translate_off
initial
delayed_wrptr_g = 0;
// synopsys translate_on
always @ ( posedge wrclk or posedge aclr)
if (aclr == 1'b1) delayed_wrptr_g <= 12'b0;
else delayed_wrptr_g <= wrptr_g;
// synopsys translate_off
initial
wrptr_g = 0;
// synopsys translate_on
always @ ( posedge wrclk or posedge aclr)
if (aclr == 1'b1) wrptr_g <= 12'b0;
else if (valid_wrreq == 1'b1) wrptr_g <= wire_wrptr_g1p_q;
fifo_4k_dffpipe_bb3 rs_brp
(
.clock(rdclk),
.clrn((~ aclr)),
.d(wire_rdptr_g_gray2bin_bin),
.q(wire_rs_brp_q));
fifo_4k_dffpipe_bb3 rs_bwp
(
.clock(rdclk),
.clrn((~ aclr)),
.d(wire_rs_dgwp_gray2bin_bin),
.q(wire_rs_bwp_q));
fifo_4k_alt_synch_pipe_em2 rs_dgwp
(
.clock(rdclk),
.clrn((~ aclr)),
.d(delayed_wrptr_g),
.q(wire_rs_dgwp_q));
fifo_4k_dffpipe_bb3 ws_brp
(
.clock(wrclk),
.clrn((~ aclr)),
.d(wire_ws_dgrp_gray2bin_bin),
.q(wire_ws_brp_q));
fifo_4k_dffpipe_bb3 ws_bwp
(
.clock(wrclk),
.clrn((~ aclr)),
.d(wire_wrptr_g_gray2bin_bin),
.q(wire_ws_bwp_q));
fifo_4k_alt_synch_pipe_em2 ws_dgrp
(
.clock(wrclk),
.clrn((~ aclr)),
.d(wire_rdptr_g_q),
.q(wire_ws_dgrp_q));
fifo_4k_add_sub_b18 rdusedw_sub
(
.dataa(wire_rs_bwp_q),
.datab(wire_rs_brp_q),
.result(wire_rdusedw_sub_result));
fifo_4k_add_sub_b18 wrusedw_sub
(
.dataa(wire_ws_bwp_q),
.datab(wire_ws_brp_q),
.result(wire_wrusedw_sub_result));
always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab)
if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab)
begin
wire_rdempty_eq_comp_aeb_int = 1'b1;
end
else
begin
wire_rdempty_eq_comp_aeb_int = 1'b0;
end
assign
wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int;
assign
wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q,
wire_rdempty_eq_comp_datab = wire_rdptr_g_q;
always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab)
if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab)
begin
wire_wrfull_eq_comp_aeb_int = 1'b1;
end
else
begin
wire_wrfull_eq_comp_aeb_int = 1'b0;
end
assign
wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int;
assign
wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q,
wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q;
assign
int_rdempty = wire_rdempty_eq_comp_aeb,
int_wrfull = wire_wrfull_eq_comp_aeb,
q = wire_fifo_ram_q_b,
rdempty = int_rdempty,
rdusedw = wire_rdusedw_sub_result,
valid_rdreq = rdreq,
valid_wrreq = wrreq,
wrfull = int_wrfull,
wrusedw = wire_wrusedw_sub_result;
endmodule //fifo_4k_dcfifo_6cq
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_4k (
data,
wrreq,
rdreq,
rdclk,
wrclk,
aclr,
q,
rdempty,
rdusedw,
wrfull,
wrusedw)/* synthesis synthesis_clearbox = 1 */;
input [15:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
wire sub_wire0;
wire [11:0] sub_wire1;
wire sub_wire2;
wire [15:0] sub_wire3;
wire [11:0] sub_wire4;
wire rdempty = sub_wire0;
wire [11:0] wrusedw = sub_wire1[11:0];
wire wrfull = sub_wire2;
wire [15:0] q = sub_wire3[15:0];
wire [11:0] rdusedw = sub_wire4[11:0];
fifo_4k_dcfifo_6cq fifo_4k_dcfifo_6cq_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.q (sub_wire3),
.rdusedw (sub_wire4));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: wdata_mux.v
//
// Description:
// Contains MI-side write command queue.
// SI-slot index selected by AW arbiter is pushed onto queue when S_AVALID transfer is received.
// Queue is popped when WLAST data beat is transferred.
// W-channel input from SI-slot selected by queue output is transferred to MI-side output .
//--------------------------------------------------------------------------
//
// Structure:
// wdata_mux
// axic_reg_srl_fifo
// mux_enc
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_wdata_mux #
(
parameter C_FAMILY = "none", // FPGA Family.
parameter integer C_WMESG_WIDTH = 1, // Width of W-channel payload.
parameter integer C_NUM_SLAVE_SLOTS = 1, // Number of S_* ports.
parameter integer C_SELECT_WIDTH = 1, // Width of ASELECT.
parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2**C_FIFO_DEPTH_LOG.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave Data Ports
input wire [C_NUM_SLAVE_SLOTS*C_WMESG_WIDTH-1:0] S_WMESG,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_WLAST,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_WVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_WREADY,
// Master Data Ports
output wire [C_WMESG_WIDTH-1:0] M_WMESG,
output wire M_WLAST,
output wire M_WVALID,
input wire M_WREADY,
// Write Command Ports
input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // SI-slot index from AW arbiter
input wire S_AVALID,
output wire S_AREADY
);
localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5; // Max depth = 32
// Decode select input to 1-hot
function [C_NUM_SLAVE_SLOTS-1:0] f_decoder (
input [C_SELECT_WIDTH-1:0] sel
);
integer i;
begin
for (i=0; i<C_NUM_SLAVE_SLOTS; i=i+1) begin
f_decoder[i] = (sel == i);
end
end
endfunction
wire m_valid_i;
wire m_last_i;
wire [C_NUM_SLAVE_SLOTS-1:0] m_select_hot;
wire [C_SELECT_WIDTH-1:0] m_select_enc;
wire m_avalid;
wire m_aready;
generate
if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux
// SI-side write command queue
axi_data_fifo_v2_1_axic_reg_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (C_SELECT_WIDTH),
.C_FIFO_DEPTH_LOG (P_FIFO_DEPTH_LOG),
.C_USE_FULL (0)
)
wmux_aw_fifo
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (S_ASELECT),
.S_VALID (S_AVALID),
.S_READY (S_AREADY),
.M_MESG (m_select_enc),
.M_VALID (m_avalid),
.M_READY (m_aready)
);
assign m_select_hot = f_decoder(m_select_enc);
// Instantiate MUX
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_SLAVE_SLOTS),
.C_SEL_WIDTH (C_SELECT_WIDTH),
.C_DATA_WIDTH (C_WMESG_WIDTH)
) mux_w
(
.S (m_select_enc),
.A (S_WMESG),
.O (M_WMESG),
.OE (1'b1)
);
assign m_last_i = |(S_WLAST & m_select_hot);
assign m_valid_i = |(S_WVALID & m_select_hot);
assign m_aready = m_valid_i & m_avalid & m_last_i & M_WREADY;
assign M_WLAST = m_last_i;
assign M_WVALID = m_valid_i & m_avalid;
assign S_WREADY = m_select_hot & {C_NUM_SLAVE_SLOTS{m_avalid & M_WREADY}};
end else begin : gen_no_wmux
assign S_AREADY = 1'b1;
assign M_WVALID = S_WVALID;
assign S_WREADY = M_WREADY;
assign M_WLAST = S_WLAST;
assign M_WMESG = S_WMESG;
end
endgenerate
endmodule
`default_nettype wire
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: wdata_mux.v
//
// Description:
// Contains MI-side write command queue.
// SI-slot index selected by AW arbiter is pushed onto queue when S_AVALID transfer is received.
// Queue is popped when WLAST data beat is transferred.
// W-channel input from SI-slot selected by queue output is transferred to MI-side output .
//--------------------------------------------------------------------------
//
// Structure:
// wdata_mux
// axic_reg_srl_fifo
// mux_enc
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_wdata_mux #
(
parameter C_FAMILY = "none", // FPGA Family.
parameter integer C_WMESG_WIDTH = 1, // Width of W-channel payload.
parameter integer C_NUM_SLAVE_SLOTS = 1, // Number of S_* ports.
parameter integer C_SELECT_WIDTH = 1, // Width of ASELECT.
parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2**C_FIFO_DEPTH_LOG.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave Data Ports
input wire [C_NUM_SLAVE_SLOTS*C_WMESG_WIDTH-1:0] S_WMESG,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_WLAST,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_WVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_WREADY,
// Master Data Ports
output wire [C_WMESG_WIDTH-1:0] M_WMESG,
output wire M_WLAST,
output wire M_WVALID,
input wire M_WREADY,
// Write Command Ports
input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // SI-slot index from AW arbiter
input wire S_AVALID,
output wire S_AREADY
);
localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5; // Max depth = 32
// Decode select input to 1-hot
function [C_NUM_SLAVE_SLOTS-1:0] f_decoder (
input [C_SELECT_WIDTH-1:0] sel
);
integer i;
begin
for (i=0; i<C_NUM_SLAVE_SLOTS; i=i+1) begin
f_decoder[i] = (sel == i);
end
end
endfunction
wire m_valid_i;
wire m_last_i;
wire [C_NUM_SLAVE_SLOTS-1:0] m_select_hot;
wire [C_SELECT_WIDTH-1:0] m_select_enc;
wire m_avalid;
wire m_aready;
generate
if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux
// SI-side write command queue
axi_data_fifo_v2_1_axic_reg_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (C_SELECT_WIDTH),
.C_FIFO_DEPTH_LOG (P_FIFO_DEPTH_LOG),
.C_USE_FULL (0)
)
wmux_aw_fifo
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (S_ASELECT),
.S_VALID (S_AVALID),
.S_READY (S_AREADY),
.M_MESG (m_select_enc),
.M_VALID (m_avalid),
.M_READY (m_aready)
);
assign m_select_hot = f_decoder(m_select_enc);
// Instantiate MUX
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_SLAVE_SLOTS),
.C_SEL_WIDTH (C_SELECT_WIDTH),
.C_DATA_WIDTH (C_WMESG_WIDTH)
) mux_w
(
.S (m_select_enc),
.A (S_WMESG),
.O (M_WMESG),
.OE (1'b1)
);
assign m_last_i = |(S_WLAST & m_select_hot);
assign m_valid_i = |(S_WVALID & m_select_hot);
assign m_aready = m_valid_i & m_avalid & m_last_i & M_WREADY;
assign M_WLAST = m_last_i;
assign M_WVALID = m_valid_i & m_avalid;
assign S_WREADY = m_select_hot & {C_NUM_SLAVE_SLOTS{m_avalid & M_WREADY}};
end else begin : gen_no_wmux
assign S_AREADY = 1'b1;
assign M_WVALID = S_WVALID;
assign S_WREADY = M_WREADY;
assign M_WLAST = S_WLAST;
assign M_WMESG = S_WMESG;
end
endgenerate
endmodule
`default_nettype wire
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2004 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Serial Control Bus from Cypress chip
module serial_io
( input master_clk,
input serial_clock,
input serial_data_in,
input enable,
input reset,
inout wire serial_data_out,
output reg [6:0] serial_addr,
output reg [31:0] serial_data,
output wire serial_strobe,
input wire [31:0] readback_0,
input wire [31:0] readback_1,
input wire [31:0] readback_2,
input wire [31:0] readback_3,
input wire [31:0] readback_4,
input wire [31:0] readback_5,
input wire [31:0] readback_6,
input wire [31:0] readback_7
);
reg is_read;
reg [7:0] ser_ctr;
reg write_done;
assign serial_data_out = is_read ? serial_data[31] : 1'bz;
always @(posedge serial_clock, posedge reset, negedge enable)
if(reset)
ser_ctr <= #1 8'd0;
else if(~enable)
ser_ctr <= #1 8'd0;
else if(ser_ctr == 39)
ser_ctr <= #1 8'd0;
else
ser_ctr <= #1 ser_ctr + 8'd1;
always @(posedge serial_clock, posedge reset, negedge enable)
if(reset)
is_read <= #1 1'b0;
else if(~enable)
is_read <= #1 1'b0;
else if((ser_ctr == 7)&&(serial_addr[6]==1))
is_read <= #1 1'b1;
always @(posedge serial_clock, posedge reset)
if(reset)
begin
serial_addr <= #1 7'b0;
serial_data <= #1 32'b0;
write_done <= #1 1'b0;
end
else if(~enable)
begin
//serial_addr <= #1 7'b0;
//serial_data <= #1 32'b0;
write_done <= #1 1'b0;
end
else
begin
if(~is_read && (ser_ctr == 39))
write_done <= #1 1'b1;
else
write_done <= #1 1'b0;
if(is_read & (ser_ctr==8))
case (serial_addr)
7'd1: serial_data <= #1 readback_0;
7'd2: serial_data <= #1 readback_1;
7'd3: serial_data <= #1 readback_2;
7'd4: serial_data <= #1 readback_3;
7'd5: serial_data <= #1 readback_4;
7'd6: serial_data <= #1 readback_5;
7'd7: serial_data <= #1 readback_6;
7'd8: serial_data <= #1 readback_7;
default: serial_data <= #1 32'd0;
endcase // case(serial_addr)
else if(ser_ctr >= 8)
serial_data <= #1 {serial_data[30:0],serial_data_in};
else if(ser_ctr < 8)
serial_addr <= #1 {serial_addr[5:0],serial_data_in};
end // else: !if(~enable)
reg enable_d1, enable_d2;
always @(posedge master_clk)
begin
enable_d1 <= #1 enable;
enable_d2 <= #1 enable_d1;
end
assign serial_strobe = enable_d2 & ~enable_d1;
endmodule // serial_io
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2004 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Serial Control Bus from Cypress chip
module serial_io
( input master_clk,
input serial_clock,
input serial_data_in,
input enable,
input reset,
inout wire serial_data_out,
output reg [6:0] serial_addr,
output reg [31:0] serial_data,
output wire serial_strobe,
input wire [31:0] readback_0,
input wire [31:0] readback_1,
input wire [31:0] readback_2,
input wire [31:0] readback_3,
input wire [31:0] readback_4,
input wire [31:0] readback_5,
input wire [31:0] readback_6,
input wire [31:0] readback_7
);
reg is_read;
reg [7:0] ser_ctr;
reg write_done;
assign serial_data_out = is_read ? serial_data[31] : 1'bz;
always @(posedge serial_clock, posedge reset, negedge enable)
if(reset)
ser_ctr <= #1 8'd0;
else if(~enable)
ser_ctr <= #1 8'd0;
else if(ser_ctr == 39)
ser_ctr <= #1 8'd0;
else
ser_ctr <= #1 ser_ctr + 8'd1;
always @(posedge serial_clock, posedge reset, negedge enable)
if(reset)
is_read <= #1 1'b0;
else if(~enable)
is_read <= #1 1'b0;
else if((ser_ctr == 7)&&(serial_addr[6]==1))
is_read <= #1 1'b1;
always @(posedge serial_clock, posedge reset)
if(reset)
begin
serial_addr <= #1 7'b0;
serial_data <= #1 32'b0;
write_done <= #1 1'b0;
end
else if(~enable)
begin
//serial_addr <= #1 7'b0;
//serial_data <= #1 32'b0;
write_done <= #1 1'b0;
end
else
begin
if(~is_read && (ser_ctr == 39))
write_done <= #1 1'b1;
else
write_done <= #1 1'b0;
if(is_read & (ser_ctr==8))
case (serial_addr)
7'd1: serial_data <= #1 readback_0;
7'd2: serial_data <= #1 readback_1;
7'd3: serial_data <= #1 readback_2;
7'd4: serial_data <= #1 readback_3;
7'd5: serial_data <= #1 readback_4;
7'd6: serial_data <= #1 readback_5;
7'd7: serial_data <= #1 readback_6;
7'd8: serial_data <= #1 readback_7;
default: serial_data <= #1 32'd0;
endcase // case(serial_addr)
else if(ser_ctr >= 8)
serial_data <= #1 {serial_data[30:0],serial_data_in};
else if(ser_ctr < 8)
serial_addr <= #1 {serial_addr[5:0],serial_data_in};
end // else: !if(~enable)
reg enable_d1, enable_d2;
always @(posedge master_clk)
begin
enable_d1 <= #1 enable;
enable_d2 <= #1 enable_d1;
end
assign serial_strobe = enable_d2 & ~enable_d1;
endmodule // serial_io
|
// -- (c) Copyright 2011-2014 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: axi_crossbar.v
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_axi_crossbar # (
parameter C_FAMILY = "rtl",
// FPGA Base Family. Current version: virtex6 or spartan6.
parameter integer C_NUM_SLAVE_SLOTS = 1,
// Number of Slave Interface (SI) slots for connecting
// to master IP. Range: 1-16.
parameter integer C_NUM_MASTER_SLOTS = 2,
// Number of Master Interface (MI) slots for connecting
// to slave IP. Range: 1-16.
parameter integer C_AXI_ID_WIDTH = 1,
// Width of ID signals propagated by the Interconnect.
// Width of ID signals produced on all MI slots.
// Range: 1-32.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and
// m_axi_araddr for all SI/MI slots.
// Range: 1-64.
parameter integer C_AXI_DATA_WIDTH = 32,
// Data width of the internal interconnect write and read
// data paths.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_AXI_PROTOCOL = 0,
// 0 = "AXI4",
// 1 = "AXI3",
// 2 = "AXI4LITE"
// Propagate WID only when C_AXI_PROTOCOL = 1.
parameter integer C_NUM_ADDR_RANGES = 1,
// Number of BASE/HIGH_ADDR pairs per MI slot.
// Range: 1-16.
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = 128'h00000000001000000000000000000000,
// Base address of each range of each MI slot.
// For unused ranges, set C_M_AXI_BASE_ADDR[mm*aa*64 +: C_AXI_ADDR_WIDTH] = {C_AXI_ADDR_WIDTH{1'b1}}.
// (Bit positions above C_AXI_ADDR_WIDTH are ignored.)
// Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit64}}.
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*32-1:0] C_M_AXI_ADDR_WIDTH = 64'H0000000c0000000c,
// Number of low-order address bits that are used to select locations within each address range of each MI slot.
// The High address of each range is derived as BASE_ADDR + 2**C_M_AXI_ADDR_WIDTH -1.
// For used address ranges, C_M_AXI_ADDR_WIDTH must be > 0.
// For unused ranges, set C_M_AXI_ADDR_WIDTH to 32'h00000000.
// Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit32}}.
// Range: 0 - C_AXI_ADDR_WIDTH.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_BASE_ID = 32'h00000000,
// Base ID of each SI slot.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0 to 2**C_AXI_ID_WIDTH-1.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_THREAD_ID_WIDTH = 32'h00000000,
// Number of low-order ID bits a connected master may vary to select a transaction thread.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0 - C_AXI_ID_WIDTH.
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
// 1 = Propagate all USER signals, 0 = Dont propagate.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of BUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF,
// Multi-pathway write connectivity from each SI slot (N) to each
// MI slot (M):
// 0 = no pathway required; 1 = pathway required. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF,
// Multi-pathway read connectivity from each SI slot (N) to each
// MI slot (M):
// 0 = no pathway required; 1 = pathway required. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
parameter integer C_R_REGISTER = 0,
// Insert register slice on R channel in the crossbar. (Valid only for SASD)
// Range: Reg-slice type (0-8).
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_SINGLE_THREAD = 32'h00000000,
// 0 = Implement separate command queues per ID thread.
// 1 = Force corresponding SI slot to be single-threaded. (Valid only for SAMD)
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0, 1
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_WRITE_ACCEPTANCE = 32'H00000002,
// Maximum number of active write transactions that each SI
// slot can accept. (Valid only for SAMD)
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_READ_ACCEPTANCE = 32'H00000002,
// Maximum number of active read transactions that each SI
// slot can accept. (Valid only for SAMD)
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_ISSUING = 64'H0000000400000004,
// Maximum number of data-active write transactions that
// each MI slot can generate at any one time. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_ISSUING = 64'H0000000400000004,
// Maximum number of active read transactions that
// each MI slot can generate at any one time. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY = 32'h00000000,
// Arbitration priority among each SI slot.
// Higher values indicate higher priority.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0-15.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE = 32'h00000000,
// Indicates whether each MI slot connects to a secure slave
// (allows only TrustZone secure access).
// Format: C_NUM_MASTER_SLOTS{Bit32}.
// Range: 0, 1
parameter integer C_CONNECTIVITY_MODE = 1
// 0 = Shared-Address Shared-Data (SASD).
// 1 = Shared-Address Multi-Data (SAMD).
// Default 1 (on) for simulation; default 0 (off) for implementation.
)
(
// Global Signals
input wire aclk,
input wire aresetn,
// Slave Interface Write Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_awsize,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_awburst,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awcache,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_awprot,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awregion,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awqos,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awvalid,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wlast,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wvalid,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_bresp,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bvalid,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_arsize,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_arburst,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arcache,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_arprot,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arregion,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arqos,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arvalid,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_rresp,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rlast,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rvalid,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rready,
// Master Interface Write Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_awsize,
output wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_awburst,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awcache,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_awprot,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awregion,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awqos,
output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awvalid,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awready,
// Master Interface Write Data Ports
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wlast,
output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wvalid,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wready,
// Master Interface Write Response Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_bresp,
input wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bvalid,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bready,
// Master Interface Read Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_arsize,
output wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_arburst,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arcache,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_arprot,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arregion,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arqos,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arvalid,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arready,
// Master Interface Read Data Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_rresp,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rlast,
input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rvalid,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rready
);
localparam [64:0] P_ONES = {65{1'b1}};
localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_BASE_ID = f_base_id(0);
localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_HIGH_ID = f_high_id(0);
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
localparam [2:0] P_AXILITE_SIZE = 3'b010;
localparam [1:0] P_INCR = 2'b01;
localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_WRITE = f_m_supports_write(0);
localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_READ = f_m_supports_read(0);
localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_WRITE = f_s_supports_write(0);
localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_READ = f_s_supports_read(0);
localparam integer C_DEBUG = 1;
localparam integer P_RANGE_CHECK = 1;
// 1 (non-zero) = Detect and issue DECERR on the following conditions:
// a. address range mismatch (no valid MI slot)
// b. Burst or >32-bit transfer to AxiLite slave
// c. TrustZone access violation
// d. R/W direction unsupported by target
// 0 = Pass all transactions (no DECERR):
// a. Omit DECERR detection and response logic
// b. Omit address decoder and propagate s_axi_a*REGION to m_axi_a*REGION
// when C_NUM_MASTER_SLOTS=1 and C_NUM_ADDR_RANGES=1.
// c. Unpredictable target MI-slot if address mismatch and >1 MI-slot
// d. Transaction corruption if any burst or >32-bit transfer to AxiLite slave
// Illegal combination: P_RANGE_CHECK = 0 && C_M_AXI_SECURE != 0.
localparam integer P_ADDR_DECODE = ((P_RANGE_CHECK == 1) || (C_NUM_MASTER_SLOTS > 1) || (C_NUM_ADDR_RANGES > 1)) ? 1 : 0; // Always 1
localparam [C_NUM_MASTER_SLOTS*32-1:0] P_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32'h00000000}};
// Transaction error detection (per MI-slot)
// 0 = None; 1 = AXI4Lite burst violation
// Format: C_NUM_MASTER_SLOTS{Bit32};
localparam integer P_LEN = (C_AXI_PROTOCOL == P_AXI3) ? 4 : 8;
localparam integer P_LOCK = (C_AXI_PROTOCOL == P_AXI3) ? 2 : 1;
localparam P_FAMILY = ((C_FAMILY == "virtex7") || (C_FAMILY == "kintex7") || (C_FAMILY == "artix7") || (C_FAMILY == "zynq")) ? C_FAMILY : "rtl";
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// Widths of all write issuance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit)
function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_write_issue_width_vec
(input null_arg);
integer mi;
reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result;
begin
result = 0;
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result[mi*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_WRITE_ISSUING[mi*32+:32]);
end
result[C_NUM_MASTER_SLOTS*32+:32] = 32'h0;
f_write_issue_width_vec = result;
end
endfunction
// Widths of all read issuance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit)
function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_read_issue_width_vec
(input null_arg);
integer mi;
reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result;
begin
result = 0;
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result[mi*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_READ_ISSUING[mi*32+:32]);
end
result[C_NUM_MASTER_SLOTS*32+:32] = 32'h0;
f_read_issue_width_vec = result;
end
endfunction
// Widths of all write acceptance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit)
function [C_NUM_SLAVE_SLOTS*32-1:0] f_write_accept_width_vec
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*32-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_WRITE_ACCEPTANCE[si*32+:32]);
end
f_write_accept_width_vec = result;
end
endfunction
// Widths of all read acceptance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit)
function [C_NUM_SLAVE_SLOTS*32-1:0] f_read_accept_width_vec
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*32-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_READ_ACCEPTANCE[si*32+:32]);
end
f_read_accept_width_vec = result;
end
endfunction
// Convert C_S_AXI_BASE_ID vector from Bit32 to Bit64 format
function [C_NUM_SLAVE_SLOTS*64-1:0] f_base_id
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*64-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*64+:C_AXI_ID_WIDTH] = C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH];
end
f_base_id = result;
end
endfunction
// Construct P_S_HIGH_ID vector
function [C_NUM_SLAVE_SLOTS*64-1:0] f_high_id
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*64-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*64+:C_AXI_ID_WIDTH] = (C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] :
({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} :
(C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]}));
end
f_high_id = result;
end
endfunction
// Construct P_M_HIGH_ADDR vector
function [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] f_high_addr
(input null_arg);
integer ar;
reg [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] result;
begin
result = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}};
for (ar=0; ar<C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES; ar=ar+1) begin
result[ar*64+:C_AXI_ADDR_WIDTH] = (C_M_AXI_ADDR_WIDTH[ar*32+:32] == 0) ? 64'h00000000_00000000 :
({1'b0, C_M_AXI_ADDR_WIDTH[ar*32+:31]} >= C_AXI_ADDR_WIDTH) ? {C_AXI_ADDR_WIDTH{1'b1}} :
(C_M_AXI_BASE_ADDR[ar*64+:C_AXI_ADDR_WIDTH] | ~(P_ONES << {1'b0, C_M_AXI_ADDR_WIDTH[ar*32+:7]}));
end
f_high_addr = result;
end
endfunction
// Generate a mask of valid ID bits for a given SI slot.
function [C_AXI_ID_WIDTH-1:0] f_thread_id_mask
(input integer si);
begin
f_thread_id_mask =
(C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? {C_AXI_ID_WIDTH{1'b0}} :
({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} :
({C_AXI_ID_WIDTH{1'b0}} | ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]}));
end
endfunction
// Isolate thread bits of input S_ID and add to BASE_ID to form MI-side ID value
// only for end-point SI-slots
function [C_AXI_ID_WIDTH-1:0] f_extend_ID (
input [C_AXI_ID_WIDTH-1:0] s_id,
input integer si
);
begin
f_extend_ID =
(C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] :
({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? s_id :
(C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | (s_id & ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]})));
end
endfunction
// Bit vector of SI slots with at least one write connection.
function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_write
(input null_arg);
integer mi;
reg [C_NUM_SLAVE_SLOTS-1:0] result;
begin
result = {C_NUM_SLAVE_SLOTS{1'b0}};
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result = result | C_M_AXI_WRITE_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS];
end
f_s_supports_write = result;
end
endfunction
// Bit vector of SI slots with at least one read connection.
function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_read
(input null_arg);
integer mi;
reg [C_NUM_SLAVE_SLOTS-1:0] result;
begin
result = {C_NUM_SLAVE_SLOTS{1'b0}};
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result = result | C_M_AXI_READ_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS];
end
f_s_supports_read = result;
end
endfunction
// Bit vector of MI slots with at least one write connection.
function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_write
(input null_arg);
integer mi;
begin
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
f_m_supports_write[mi] = (|C_M_AXI_WRITE_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]);
end
end
endfunction
// Bit vector of MI slots with at least one read connection.
function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_read
(input null_arg);
integer mi;
begin
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
f_m_supports_read[mi] = (|C_M_AXI_READ_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]);
end
end
endfunction
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_awid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] si_cb_awaddr ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] si_cb_awlen ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_awsize ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_awburst ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_awlock ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_awcache ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_awprot ;
// wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_awregion ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_awqos ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] si_cb_awuser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_awvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_awready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_wid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] si_cb_wdata ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] si_cb_wstrb ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wlast ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] si_cb_wuser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_bid ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_bresp ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] si_cb_buser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_bvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_bready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_arid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] si_cb_araddr ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] si_cb_arlen ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_arsize ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_arburst ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_arlock ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_arcache ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_arprot ;
// wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_arregion ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_arqos ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] si_cb_aruser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_arvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_arready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_rid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] si_cb_rdata ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_rresp ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rlast ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] si_cb_ruser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_awid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] cb_mi_awaddr ;
wire [C_NUM_MASTER_SLOTS*8-1:0] cb_mi_awlen ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_awsize ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_awburst ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_awlock ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_awcache ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_awprot ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_awregion ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_awqos ;
wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] cb_mi_awuser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_awvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_awready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_wid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] cb_mi_wdata ;
wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] cb_mi_wstrb ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wlast ;
wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] cb_mi_wuser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_bid ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_bresp ;
wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] cb_mi_buser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_bvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_bready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_arid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] cb_mi_araddr ;
wire [C_NUM_MASTER_SLOTS*8-1:0] cb_mi_arlen ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_arsize ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_arburst ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_arlock ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_arcache ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_arprot ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_arregion ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_arqos ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] cb_mi_aruser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_arvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_arready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_rid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] cb_mi_rdata ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_rresp ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rlast ;
wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] cb_mi_ruser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rready ;
genvar slot;
generate
for (slot=0;slot<C_NUM_SLAVE_SLOTS;slot=slot+1) begin : gen_si_tieoff
assign si_cb_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (s_axi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign si_cb_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign si_cb_awlen[slot*8+:8] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awlen[slot*P_LEN+:P_LEN] : 0 ;
assign si_cb_awsize[slot*3+:3] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awsize[slot*3+:3] : P_AXILITE_SIZE ;
assign si_cb_awburst[slot*2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awburst[slot*2+:2] : P_INCR ;
assign si_cb_awlock[slot*2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? {1'b0, s_axi_awlock[slot*P_LOCK+:1]} : 0 ;
assign si_cb_awcache[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awcache[slot*4+:4] : 0 ;
assign si_cb_awprot[slot*3+:3] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awprot[slot*3+:3] : 0 ;
assign si_cb_awqos[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awqos[slot*4+:4] : 0 ;
// assign si_cb_awregion[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_awregion[slot*4+:4] : 0 ;
assign si_cb_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] : 0 ;
assign si_cb_awvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awvalid[slot*1+:1] : 0 ;
assign si_cb_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI3) ) ? (s_axi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign si_cb_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign si_cb_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ;
assign si_cb_wlast[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_wlast[slot*1+:1] : 1'b1 ;
assign si_cb_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] : 0 ;
assign si_cb_wvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wvalid[slot*1+:1] : 0 ;
assign si_cb_bready[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_bready[slot*1+:1] : 0 ;
assign si_cb_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (s_axi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign si_cb_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign si_cb_arlen[slot*8+:8] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arlen[slot*P_LEN+:P_LEN] : 0 ;
assign si_cb_arsize[slot*3+:3] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arsize[slot*3+:3] : P_AXILITE_SIZE ;
assign si_cb_arburst[slot*2+:2] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arburst[slot*2+:2] : P_INCR ;
assign si_cb_arlock[slot*2+:2] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? {1'b0, s_axi_arlock[slot*P_LOCK+:1]} : 0 ;
assign si_cb_arcache[slot*4+:4] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arcache[slot*4+:4] : 0 ;
assign si_cb_arprot[slot*3+:3] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_arprot[slot*3+:3] : 0 ;
assign si_cb_arqos[slot*4+:4] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arqos[slot*4+:4] : 0 ;
// assign si_cb_arregion[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_arregion[slot*4+:4] : 0 ;
assign si_cb_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] : 0 ;
assign si_cb_arvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_arvalid[slot*1+:1] : 0 ;
assign si_cb_rready[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_rready[slot*1+:1] : 0 ;
assign s_axi_awready[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_awready[slot*1+:1] : 0 ;
assign s_axi_wready[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_wready[slot*1+:1] : 0 ;
assign s_axi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (si_cb_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign s_axi_bresp[slot*2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_bresp[slot*2+:2] : 0 ;
assign s_axi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] : 0 ;
assign s_axi_bvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_bvalid[slot*1+:1] : 0 ;
assign s_axi_arready[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_arready[slot*1+:1] : 0 ;
assign s_axi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (si_cb_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign s_axi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign s_axi_rresp[slot*2+:2] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rresp[slot*2+:2] : 0 ;
assign s_axi_rlast[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cb_rlast[slot*1+:1] : 0 ;
assign s_axi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] : 0 ;
assign s_axi_rvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rvalid[slot*1+:1] : 0 ;
end // gen_si_tieoff
for (slot=0;slot<C_NUM_MASTER_SLOTS;slot=slot+1) begin : gen_mi_tieoff
assign m_axi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign m_axi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign m_axi_awlen[slot*P_LEN+:P_LEN] = (~P_M_AXI_SUPPORTS_WRITE[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4 ) ? cb_mi_awlen[slot*8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_awlen[slot*8+:4] : 0 ;
assign m_axi_awsize[slot*3+:3] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awsize[slot*3+:3] : 0 ;
assign m_axi_awburst[slot*2+:2] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awburst[slot*2+:2] : 0 ;
assign m_axi_awlock[slot*P_LOCK+:P_LOCK] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awlock[slot*2+:1] : 0 ;
assign m_axi_awcache[slot*4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awcache[slot*4+:4] : 0 ;
assign m_axi_awprot[slot*3+:3] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awprot[slot*3+:3] : 0 ;
assign m_axi_awregion[slot*4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? cb_mi_awregion[slot*4+:4] : 0 ;
assign m_axi_awqos[slot*4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awqos[slot*4+:4] : 0 ;
assign m_axi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] : 0 ;
assign m_axi_awvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awvalid[slot*1+:1] : 0 ;
assign m_axi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign m_axi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign m_axi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ;
assign m_axi_wlast[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_wlast[slot*1+:1] : 0 ;
assign m_axi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] : 0 ;
assign m_axi_wvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wvalid[slot*1+:1] : 0 ;
assign m_axi_bready[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_bready[slot*1+:1] : 0 ;
assign m_axi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign m_axi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign m_axi_arlen[slot*P_LEN+:P_LEN] = (~P_M_AXI_SUPPORTS_READ[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4 ) ? cb_mi_arlen[slot*8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_arlen[slot*8+:4] : 0 ;
assign m_axi_arsize[slot*3+:3] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arsize[slot*3+:3] : 0 ;
assign m_axi_arburst[slot*2+:2] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arburst[slot*2+:2] : 0 ;
assign m_axi_arlock[slot*P_LOCK+:P_LOCK] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arlock[slot*2+:1] : 0 ;
assign m_axi_arcache[slot*4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arcache[slot*4+:4] : 0 ;
assign m_axi_arprot[slot*3+:3] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_arprot[slot*3+:3] : 0 ;
assign m_axi_arregion[slot*4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? cb_mi_arregion[slot*4+:4] : 0 ;
assign m_axi_arqos[slot*4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arqos[slot*4+:4] : 0 ;
assign m_axi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] : 0 ;
assign m_axi_arvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_arvalid[slot*1+:1] : 0 ;
assign m_axi_rready[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_rready[slot*1+:1] : 0 ;
assign cb_mi_awready[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_awready[slot*1+:1] : 0 ;
assign cb_mi_wready[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_wready[slot*1+:1] : 0 ;
assign cb_mi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign cb_mi_bresp[slot*2+:2] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_bresp[slot*2+:2] : 0 ;
assign cb_mi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] : 0 ;
assign cb_mi_bvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_bvalid[slot*1+:1] : 0 ;
assign cb_mi_arready[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_arready[slot*1+:1] : 0 ;
assign cb_mi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign cb_mi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign cb_mi_rresp[slot*2+:2] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rresp[slot*2+:2] : 0 ;
assign cb_mi_rlast[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rlast[slot*1+:1] : 1'b1 ;
assign cb_mi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] : 0 ;
assign cb_mi_rvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rvalid[slot*1+:1] : 0 ;
end // gen_mi_tieoff
if ((C_CONNECTIVITY_MODE==0) || (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_sasd
axi_crossbar_v2_1_crossbar_sasd #
(
.C_FAMILY (P_FAMILY),
.C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS),
.C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS),
.C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_M_AXI_BASE_ADDR (C_M_AXI_BASE_ADDR),
.C_M_AXI_HIGH_ADDR (f_high_addr(0)),
.C_S_AXI_BASE_ID (P_S_AXI_BASE_ID),
.C_S_AXI_HIGH_ID (P_S_AXI_HIGH_ID),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_S_AXI_SUPPORTS_WRITE (P_S_AXI_SUPPORTS_WRITE),
.C_S_AXI_SUPPORTS_READ (P_S_AXI_SUPPORTS_READ),
.C_M_AXI_SUPPORTS_WRITE (P_M_AXI_SUPPORTS_WRITE),
.C_M_AXI_SUPPORTS_READ (P_M_AXI_SUPPORTS_READ),
.C_S_AXI_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY),
.C_M_AXI_SECURE (C_M_AXI_SECURE),
.C_R_REGISTER (C_R_REGISTER),
.C_RANGE_CHECK (P_RANGE_CHECK),
.C_ADDR_DECODE (P_ADDR_DECODE),
.C_M_AXI_ERR_MODE (P_M_AXI_ERR_MODE),
.C_DEBUG (C_DEBUG)
)
crossbar_sasd_0
(
.ACLK (aclk),
.ARESETN (aresetn),
.S_AXI_AWID (si_cb_awid ),
.S_AXI_AWADDR (si_cb_awaddr ),
.S_AXI_AWLEN (si_cb_awlen ),
.S_AXI_AWSIZE (si_cb_awsize ),
.S_AXI_AWBURST (si_cb_awburst ),
.S_AXI_AWLOCK (si_cb_awlock ),
.S_AXI_AWCACHE (si_cb_awcache ),
.S_AXI_AWPROT (si_cb_awprot ),
// .S_AXI_AWREGION (si_cb_awregion ),
.S_AXI_AWQOS (si_cb_awqos ),
.S_AXI_AWUSER (si_cb_awuser ),
.S_AXI_AWVALID (si_cb_awvalid ),
.S_AXI_AWREADY (si_cb_awready ),
.S_AXI_WID (si_cb_wid ),
.S_AXI_WDATA (si_cb_wdata ),
.S_AXI_WSTRB (si_cb_wstrb ),
.S_AXI_WLAST (si_cb_wlast ),
.S_AXI_WUSER (si_cb_wuser ),
.S_AXI_WVALID (si_cb_wvalid ),
.S_AXI_WREADY (si_cb_wready ),
.S_AXI_BID (si_cb_bid ),
.S_AXI_BRESP (si_cb_bresp ),
.S_AXI_BUSER (si_cb_buser ),
.S_AXI_BVALID (si_cb_bvalid ),
.S_AXI_BREADY (si_cb_bready ),
.S_AXI_ARID (si_cb_arid ),
.S_AXI_ARADDR (si_cb_araddr ),
.S_AXI_ARLEN (si_cb_arlen ),
.S_AXI_ARSIZE (si_cb_arsize ),
.S_AXI_ARBURST (si_cb_arburst ),
.S_AXI_ARLOCK (si_cb_arlock ),
.S_AXI_ARCACHE (si_cb_arcache ),
.S_AXI_ARPROT (si_cb_arprot ),
// .S_AXI_ARREGION (si_cb_arregion ),
.S_AXI_ARQOS (si_cb_arqos ),
.S_AXI_ARUSER (si_cb_aruser ),
.S_AXI_ARVALID (si_cb_arvalid ),
.S_AXI_ARREADY (si_cb_arready ),
.S_AXI_RID (si_cb_rid ),
.S_AXI_RDATA (si_cb_rdata ),
.S_AXI_RRESP (si_cb_rresp ),
.S_AXI_RLAST (si_cb_rlast ),
.S_AXI_RUSER (si_cb_ruser ),
.S_AXI_RVALID (si_cb_rvalid ),
.S_AXI_RREADY (si_cb_rready ),
.M_AXI_AWID (cb_mi_awid ),
.M_AXI_AWADDR (cb_mi_awaddr ),
.M_AXI_AWLEN (cb_mi_awlen ),
.M_AXI_AWSIZE (cb_mi_awsize ),
.M_AXI_AWBURST (cb_mi_awburst ),
.M_AXI_AWLOCK (cb_mi_awlock ),
.M_AXI_AWCACHE (cb_mi_awcache ),
.M_AXI_AWPROT (cb_mi_awprot ),
.M_AXI_AWREGION (cb_mi_awregion ),
.M_AXI_AWQOS (cb_mi_awqos ),
.M_AXI_AWUSER (cb_mi_awuser ),
.M_AXI_AWVALID (cb_mi_awvalid ),
.M_AXI_AWREADY (cb_mi_awready ),
.M_AXI_WID (cb_mi_wid ),
.M_AXI_WDATA (cb_mi_wdata ),
.M_AXI_WSTRB (cb_mi_wstrb ),
.M_AXI_WLAST (cb_mi_wlast ),
.M_AXI_WUSER (cb_mi_wuser ),
.M_AXI_WVALID (cb_mi_wvalid ),
.M_AXI_WREADY (cb_mi_wready ),
.M_AXI_BID (cb_mi_bid ),
.M_AXI_BRESP (cb_mi_bresp ),
.M_AXI_BUSER (cb_mi_buser ),
.M_AXI_BVALID (cb_mi_bvalid ),
.M_AXI_BREADY (cb_mi_bready ),
.M_AXI_ARID (cb_mi_arid ),
.M_AXI_ARADDR (cb_mi_araddr ),
.M_AXI_ARLEN (cb_mi_arlen ),
.M_AXI_ARSIZE (cb_mi_arsize ),
.M_AXI_ARBURST (cb_mi_arburst ),
.M_AXI_ARLOCK (cb_mi_arlock ),
.M_AXI_ARCACHE (cb_mi_arcache ),
.M_AXI_ARPROT (cb_mi_arprot ),
.M_AXI_ARREGION (cb_mi_arregion ),
.M_AXI_ARQOS (cb_mi_arqos ),
.M_AXI_ARUSER (cb_mi_aruser ),
.M_AXI_ARVALID (cb_mi_arvalid ),
.M_AXI_ARREADY (cb_mi_arready ),
.M_AXI_RID (cb_mi_rid ),
.M_AXI_RDATA (cb_mi_rdata ),
.M_AXI_RRESP (cb_mi_rresp ),
.M_AXI_RLAST (cb_mi_rlast ),
.M_AXI_RUSER (cb_mi_ruser ),
.M_AXI_RVALID (cb_mi_rvalid ),
.M_AXI_RREADY (cb_mi_rready )
);
end else begin : gen_samd
axi_crossbar_v2_1_crossbar #
(
.C_FAMILY (P_FAMILY),
.C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS),
.C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS),
.C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_S_AXI_THREAD_ID_WIDTH (C_S_AXI_THREAD_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_M_AXI_BASE_ADDR (C_M_AXI_BASE_ADDR),
.C_M_AXI_HIGH_ADDR (f_high_addr(0)),
.C_S_AXI_BASE_ID (P_S_AXI_BASE_ID),
.C_S_AXI_HIGH_ID (P_S_AXI_HIGH_ID),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_S_AXI_SUPPORTS_WRITE (P_S_AXI_SUPPORTS_WRITE),
.C_S_AXI_SUPPORTS_READ (P_S_AXI_SUPPORTS_READ),
.C_M_AXI_SUPPORTS_WRITE (P_M_AXI_SUPPORTS_WRITE),
.C_M_AXI_SUPPORTS_READ (P_M_AXI_SUPPORTS_READ),
.C_M_AXI_WRITE_CONNECTIVITY (C_M_AXI_WRITE_CONNECTIVITY),
.C_M_AXI_READ_CONNECTIVITY (C_M_AXI_READ_CONNECTIVITY),
.C_S_AXI_SINGLE_THREAD (C_S_AXI_SINGLE_THREAD),
.C_S_AXI_WRITE_ACCEPTANCE (C_S_AXI_WRITE_ACCEPTANCE),
.C_S_AXI_READ_ACCEPTANCE (C_S_AXI_READ_ACCEPTANCE),
.C_M_AXI_WRITE_ISSUING (C_M_AXI_WRITE_ISSUING),
.C_M_AXI_READ_ISSUING (C_M_AXI_READ_ISSUING),
.C_S_AXI_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY),
.C_M_AXI_SECURE (C_M_AXI_SECURE),
.C_RANGE_CHECK (P_RANGE_CHECK),
.C_ADDR_DECODE (P_ADDR_DECODE),
.C_W_ISSUE_WIDTH (f_write_issue_width_vec(0) ),
.C_R_ISSUE_WIDTH (f_read_issue_width_vec(0) ),
.C_W_ACCEPT_WIDTH (f_write_accept_width_vec(0)),
.C_R_ACCEPT_WIDTH (f_read_accept_width_vec(0)),
.C_M_AXI_ERR_MODE (P_M_AXI_ERR_MODE),
.C_DEBUG (C_DEBUG)
)
crossbar_samd
(
.ACLK (aclk),
.ARESETN (aresetn),
.S_AXI_AWID (si_cb_awid ),
.S_AXI_AWADDR (si_cb_awaddr ),
.S_AXI_AWLEN (si_cb_awlen ),
.S_AXI_AWSIZE (si_cb_awsize ),
.S_AXI_AWBURST (si_cb_awburst ),
.S_AXI_AWLOCK (si_cb_awlock ),
.S_AXI_AWCACHE (si_cb_awcache ),
.S_AXI_AWPROT (si_cb_awprot ),
// .S_AXI_AWREGION (si_cb_awregion ),
.S_AXI_AWQOS (si_cb_awqos ),
.S_AXI_AWUSER (si_cb_awuser ),
.S_AXI_AWVALID (si_cb_awvalid ),
.S_AXI_AWREADY (si_cb_awready ),
.S_AXI_WID (si_cb_wid ),
.S_AXI_WDATA (si_cb_wdata ),
.S_AXI_WSTRB (si_cb_wstrb ),
.S_AXI_WLAST (si_cb_wlast ),
.S_AXI_WUSER (si_cb_wuser ),
.S_AXI_WVALID (si_cb_wvalid ),
.S_AXI_WREADY (si_cb_wready ),
.S_AXI_BID (si_cb_bid ),
.S_AXI_BRESP (si_cb_bresp ),
.S_AXI_BUSER (si_cb_buser ),
.S_AXI_BVALID (si_cb_bvalid ),
.S_AXI_BREADY (si_cb_bready ),
.S_AXI_ARID (si_cb_arid ),
.S_AXI_ARADDR (si_cb_araddr ),
.S_AXI_ARLEN (si_cb_arlen ),
.S_AXI_ARSIZE (si_cb_arsize ),
.S_AXI_ARBURST (si_cb_arburst ),
.S_AXI_ARLOCK (si_cb_arlock ),
.S_AXI_ARCACHE (si_cb_arcache ),
.S_AXI_ARPROT (si_cb_arprot ),
// .S_AXI_ARREGION (si_cb_arregion ),
.S_AXI_ARQOS (si_cb_arqos ),
.S_AXI_ARUSER (si_cb_aruser ),
.S_AXI_ARVALID (si_cb_arvalid ),
.S_AXI_ARREADY (si_cb_arready ),
.S_AXI_RID (si_cb_rid ),
.S_AXI_RDATA (si_cb_rdata ),
.S_AXI_RRESP (si_cb_rresp ),
.S_AXI_RLAST (si_cb_rlast ),
.S_AXI_RUSER (si_cb_ruser ),
.S_AXI_RVALID (si_cb_rvalid ),
.S_AXI_RREADY (si_cb_rready ),
.M_AXI_AWID (cb_mi_awid ),
.M_AXI_AWADDR (cb_mi_awaddr ),
.M_AXI_AWLEN (cb_mi_awlen ),
.M_AXI_AWSIZE (cb_mi_awsize ),
.M_AXI_AWBURST (cb_mi_awburst ),
.M_AXI_AWLOCK (cb_mi_awlock ),
.M_AXI_AWCACHE (cb_mi_awcache ),
.M_AXI_AWPROT (cb_mi_awprot ),
.M_AXI_AWREGION (cb_mi_awregion ),
.M_AXI_AWQOS (cb_mi_awqos ),
.M_AXI_AWUSER (cb_mi_awuser ),
.M_AXI_AWVALID (cb_mi_awvalid ),
.M_AXI_AWREADY (cb_mi_awready ),
.M_AXI_WID (cb_mi_wid ),
.M_AXI_WDATA (cb_mi_wdata ),
.M_AXI_WSTRB (cb_mi_wstrb ),
.M_AXI_WLAST (cb_mi_wlast ),
.M_AXI_WUSER (cb_mi_wuser ),
.M_AXI_WVALID (cb_mi_wvalid ),
.M_AXI_WREADY (cb_mi_wready ),
.M_AXI_BID (cb_mi_bid ),
.M_AXI_BRESP (cb_mi_bresp ),
.M_AXI_BUSER (cb_mi_buser ),
.M_AXI_BVALID (cb_mi_bvalid ),
.M_AXI_BREADY (cb_mi_bready ),
.M_AXI_ARID (cb_mi_arid ),
.M_AXI_ARADDR (cb_mi_araddr ),
.M_AXI_ARLEN (cb_mi_arlen ),
.M_AXI_ARSIZE (cb_mi_arsize ),
.M_AXI_ARBURST (cb_mi_arburst ),
.M_AXI_ARLOCK (cb_mi_arlock ),
.M_AXI_ARCACHE (cb_mi_arcache ),
.M_AXI_ARPROT (cb_mi_arprot ),
.M_AXI_ARREGION (cb_mi_arregion ),
.M_AXI_ARQOS (cb_mi_arqos ),
.M_AXI_ARUSER (cb_mi_aruser ),
.M_AXI_ARVALID (cb_mi_arvalid ),
.M_AXI_ARREADY (cb_mi_arready ),
.M_AXI_RID (cb_mi_rid ),
.M_AXI_RDATA (cb_mi_rdata ),
.M_AXI_RRESP (cb_mi_rresp ),
.M_AXI_RLAST (cb_mi_rlast ),
.M_AXI_RUSER (cb_mi_ruser ),
.M_AXI_RVALID (cb_mi_rvalid ),
.M_AXI_RREADY (cb_mi_rready )
);
end // gen_samd
// end // gen_crossbar
endgenerate
endmodule
`default_nettype wire
|
// -- (c) Copyright 2011-2014 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
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// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
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// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: axi_crossbar.v
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_axi_crossbar # (
parameter C_FAMILY = "rtl",
// FPGA Base Family. Current version: virtex6 or spartan6.
parameter integer C_NUM_SLAVE_SLOTS = 1,
// Number of Slave Interface (SI) slots for connecting
// to master IP. Range: 1-16.
parameter integer C_NUM_MASTER_SLOTS = 2,
// Number of Master Interface (MI) slots for connecting
// to slave IP. Range: 1-16.
parameter integer C_AXI_ID_WIDTH = 1,
// Width of ID signals propagated by the Interconnect.
// Width of ID signals produced on all MI slots.
// Range: 1-32.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and
// m_axi_araddr for all SI/MI slots.
// Range: 1-64.
parameter integer C_AXI_DATA_WIDTH = 32,
// Data width of the internal interconnect write and read
// data paths.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_AXI_PROTOCOL = 0,
// 0 = "AXI4",
// 1 = "AXI3",
// 2 = "AXI4LITE"
// Propagate WID only when C_AXI_PROTOCOL = 1.
parameter integer C_NUM_ADDR_RANGES = 1,
// Number of BASE/HIGH_ADDR pairs per MI slot.
// Range: 1-16.
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = 128'h00000000001000000000000000000000,
// Base address of each range of each MI slot.
// For unused ranges, set C_M_AXI_BASE_ADDR[mm*aa*64 +: C_AXI_ADDR_WIDTH] = {C_AXI_ADDR_WIDTH{1'b1}}.
// (Bit positions above C_AXI_ADDR_WIDTH are ignored.)
// Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit64}}.
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*32-1:0] C_M_AXI_ADDR_WIDTH = 64'H0000000c0000000c,
// Number of low-order address bits that are used to select locations within each address range of each MI slot.
// The High address of each range is derived as BASE_ADDR + 2**C_M_AXI_ADDR_WIDTH -1.
// For used address ranges, C_M_AXI_ADDR_WIDTH must be > 0.
// For unused ranges, set C_M_AXI_ADDR_WIDTH to 32'h00000000.
// Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit32}}.
// Range: 0 - C_AXI_ADDR_WIDTH.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_BASE_ID = 32'h00000000,
// Base ID of each SI slot.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0 to 2**C_AXI_ID_WIDTH-1.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_THREAD_ID_WIDTH = 32'h00000000,
// Number of low-order ID bits a connected master may vary to select a transaction thread.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0 - C_AXI_ID_WIDTH.
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
// 1 = Propagate all USER signals, 0 = Dont propagate.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of BUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF,
// Multi-pathway write connectivity from each SI slot (N) to each
// MI slot (M):
// 0 = no pathway required; 1 = pathway required. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF,
// Multi-pathway read connectivity from each SI slot (N) to each
// MI slot (M):
// 0 = no pathway required; 1 = pathway required. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
parameter integer C_R_REGISTER = 0,
// Insert register slice on R channel in the crossbar. (Valid only for SASD)
// Range: Reg-slice type (0-8).
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_SINGLE_THREAD = 32'h00000000,
// 0 = Implement separate command queues per ID thread.
// 1 = Force corresponding SI slot to be single-threaded. (Valid only for SAMD)
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0, 1
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_WRITE_ACCEPTANCE = 32'H00000002,
// Maximum number of active write transactions that each SI
// slot can accept. (Valid only for SAMD)
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_READ_ACCEPTANCE = 32'H00000002,
// Maximum number of active read transactions that each SI
// slot can accept. (Valid only for SAMD)
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_ISSUING = 64'H0000000400000004,
// Maximum number of data-active write transactions that
// each MI slot can generate at any one time. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_ISSUING = 64'H0000000400000004,
// Maximum number of active read transactions that
// each MI slot can generate at any one time. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY = 32'h00000000,
// Arbitration priority among each SI slot.
// Higher values indicate higher priority.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0-15.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE = 32'h00000000,
// Indicates whether each MI slot connects to a secure slave
// (allows only TrustZone secure access).
// Format: C_NUM_MASTER_SLOTS{Bit32}.
// Range: 0, 1
parameter integer C_CONNECTIVITY_MODE = 1
// 0 = Shared-Address Shared-Data (SASD).
// 1 = Shared-Address Multi-Data (SAMD).
// Default 1 (on) for simulation; default 0 (off) for implementation.
)
(
// Global Signals
input wire aclk,
input wire aresetn,
// Slave Interface Write Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_awsize,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_awburst,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awcache,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_awprot,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awregion,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awqos,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awvalid,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wlast,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wvalid,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_bresp,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bvalid,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_arsize,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_arburst,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arcache,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_arprot,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arregion,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arqos,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arvalid,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_rresp,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rlast,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rvalid,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rready,
// Master Interface Write Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_awsize,
output wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_awburst,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awcache,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_awprot,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awregion,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awqos,
output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awvalid,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awready,
// Master Interface Write Data Ports
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wlast,
output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wvalid,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wready,
// Master Interface Write Response Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_bresp,
input wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bvalid,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bready,
// Master Interface Read Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_arsize,
output wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_arburst,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arcache,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_arprot,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arregion,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arqos,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arvalid,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arready,
// Master Interface Read Data Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_rresp,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rlast,
input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rvalid,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rready
);
localparam [64:0] P_ONES = {65{1'b1}};
localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_BASE_ID = f_base_id(0);
localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_HIGH_ID = f_high_id(0);
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
localparam [2:0] P_AXILITE_SIZE = 3'b010;
localparam [1:0] P_INCR = 2'b01;
localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_WRITE = f_m_supports_write(0);
localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_READ = f_m_supports_read(0);
localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_WRITE = f_s_supports_write(0);
localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_READ = f_s_supports_read(0);
localparam integer C_DEBUG = 1;
localparam integer P_RANGE_CHECK = 1;
// 1 (non-zero) = Detect and issue DECERR on the following conditions:
// a. address range mismatch (no valid MI slot)
// b. Burst or >32-bit transfer to AxiLite slave
// c. TrustZone access violation
// d. R/W direction unsupported by target
// 0 = Pass all transactions (no DECERR):
// a. Omit DECERR detection and response logic
// b. Omit address decoder and propagate s_axi_a*REGION to m_axi_a*REGION
// when C_NUM_MASTER_SLOTS=1 and C_NUM_ADDR_RANGES=1.
// c. Unpredictable target MI-slot if address mismatch and >1 MI-slot
// d. Transaction corruption if any burst or >32-bit transfer to AxiLite slave
// Illegal combination: P_RANGE_CHECK = 0 && C_M_AXI_SECURE != 0.
localparam integer P_ADDR_DECODE = ((P_RANGE_CHECK == 1) || (C_NUM_MASTER_SLOTS > 1) || (C_NUM_ADDR_RANGES > 1)) ? 1 : 0; // Always 1
localparam [C_NUM_MASTER_SLOTS*32-1:0] P_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32'h00000000}};
// Transaction error detection (per MI-slot)
// 0 = None; 1 = AXI4Lite burst violation
// Format: C_NUM_MASTER_SLOTS{Bit32};
localparam integer P_LEN = (C_AXI_PROTOCOL == P_AXI3) ? 4 : 8;
localparam integer P_LOCK = (C_AXI_PROTOCOL == P_AXI3) ? 2 : 1;
localparam P_FAMILY = ((C_FAMILY == "virtex7") || (C_FAMILY == "kintex7") || (C_FAMILY == "artix7") || (C_FAMILY == "zynq")) ? C_FAMILY : "rtl";
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// Widths of all write issuance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit)
function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_write_issue_width_vec
(input null_arg);
integer mi;
reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result;
begin
result = 0;
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result[mi*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_WRITE_ISSUING[mi*32+:32]);
end
result[C_NUM_MASTER_SLOTS*32+:32] = 32'h0;
f_write_issue_width_vec = result;
end
endfunction
// Widths of all read issuance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit)
function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_read_issue_width_vec
(input null_arg);
integer mi;
reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result;
begin
result = 0;
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result[mi*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_READ_ISSUING[mi*32+:32]);
end
result[C_NUM_MASTER_SLOTS*32+:32] = 32'h0;
f_read_issue_width_vec = result;
end
endfunction
// Widths of all write acceptance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit)
function [C_NUM_SLAVE_SLOTS*32-1:0] f_write_accept_width_vec
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*32-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_WRITE_ACCEPTANCE[si*32+:32]);
end
f_write_accept_width_vec = result;
end
endfunction
// Widths of all read acceptance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit)
function [C_NUM_SLAVE_SLOTS*32-1:0] f_read_accept_width_vec
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*32-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_READ_ACCEPTANCE[si*32+:32]);
end
f_read_accept_width_vec = result;
end
endfunction
// Convert C_S_AXI_BASE_ID vector from Bit32 to Bit64 format
function [C_NUM_SLAVE_SLOTS*64-1:0] f_base_id
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*64-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*64+:C_AXI_ID_WIDTH] = C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH];
end
f_base_id = result;
end
endfunction
// Construct P_S_HIGH_ID vector
function [C_NUM_SLAVE_SLOTS*64-1:0] f_high_id
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*64-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*64+:C_AXI_ID_WIDTH] = (C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] :
({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} :
(C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]}));
end
f_high_id = result;
end
endfunction
// Construct P_M_HIGH_ADDR vector
function [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] f_high_addr
(input null_arg);
integer ar;
reg [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] result;
begin
result = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}};
for (ar=0; ar<C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES; ar=ar+1) begin
result[ar*64+:C_AXI_ADDR_WIDTH] = (C_M_AXI_ADDR_WIDTH[ar*32+:32] == 0) ? 64'h00000000_00000000 :
({1'b0, C_M_AXI_ADDR_WIDTH[ar*32+:31]} >= C_AXI_ADDR_WIDTH) ? {C_AXI_ADDR_WIDTH{1'b1}} :
(C_M_AXI_BASE_ADDR[ar*64+:C_AXI_ADDR_WIDTH] | ~(P_ONES << {1'b0, C_M_AXI_ADDR_WIDTH[ar*32+:7]}));
end
f_high_addr = result;
end
endfunction
// Generate a mask of valid ID bits for a given SI slot.
function [C_AXI_ID_WIDTH-1:0] f_thread_id_mask
(input integer si);
begin
f_thread_id_mask =
(C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? {C_AXI_ID_WIDTH{1'b0}} :
({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} :
({C_AXI_ID_WIDTH{1'b0}} | ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]}));
end
endfunction
// Isolate thread bits of input S_ID and add to BASE_ID to form MI-side ID value
// only for end-point SI-slots
function [C_AXI_ID_WIDTH-1:0] f_extend_ID (
input [C_AXI_ID_WIDTH-1:0] s_id,
input integer si
);
begin
f_extend_ID =
(C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] :
({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? s_id :
(C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | (s_id & ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]})));
end
endfunction
// Bit vector of SI slots with at least one write connection.
function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_write
(input null_arg);
integer mi;
reg [C_NUM_SLAVE_SLOTS-1:0] result;
begin
result = {C_NUM_SLAVE_SLOTS{1'b0}};
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result = result | C_M_AXI_WRITE_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS];
end
f_s_supports_write = result;
end
endfunction
// Bit vector of SI slots with at least one read connection.
function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_read
(input null_arg);
integer mi;
reg [C_NUM_SLAVE_SLOTS-1:0] result;
begin
result = {C_NUM_SLAVE_SLOTS{1'b0}};
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result = result | C_M_AXI_READ_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS];
end
f_s_supports_read = result;
end
endfunction
// Bit vector of MI slots with at least one write connection.
function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_write
(input null_arg);
integer mi;
begin
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
f_m_supports_write[mi] = (|C_M_AXI_WRITE_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]);
end
end
endfunction
// Bit vector of MI slots with at least one read connection.
function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_read
(input null_arg);
integer mi;
begin
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
f_m_supports_read[mi] = (|C_M_AXI_READ_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]);
end
end
endfunction
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_awid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] si_cb_awaddr ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] si_cb_awlen ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_awsize ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_awburst ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_awlock ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_awcache ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_awprot ;
// wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_awregion ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_awqos ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] si_cb_awuser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_awvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_awready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_wid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] si_cb_wdata ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] si_cb_wstrb ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wlast ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] si_cb_wuser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_bid ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_bresp ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] si_cb_buser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_bvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_bready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_arid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] si_cb_araddr ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] si_cb_arlen ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_arsize ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_arburst ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_arlock ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_arcache ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_arprot ;
// wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_arregion ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_arqos ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] si_cb_aruser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_arvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_arready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_rid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] si_cb_rdata ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_rresp ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rlast ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] si_cb_ruser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_awid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] cb_mi_awaddr ;
wire [C_NUM_MASTER_SLOTS*8-1:0] cb_mi_awlen ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_awsize ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_awburst ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_awlock ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_awcache ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_awprot ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_awregion ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_awqos ;
wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] cb_mi_awuser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_awvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_awready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_wid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] cb_mi_wdata ;
wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] cb_mi_wstrb ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wlast ;
wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] cb_mi_wuser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_bid ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_bresp ;
wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] cb_mi_buser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_bvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_bready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_arid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] cb_mi_araddr ;
wire [C_NUM_MASTER_SLOTS*8-1:0] cb_mi_arlen ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_arsize ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_arburst ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_arlock ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_arcache ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_arprot ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_arregion ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_arqos ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] cb_mi_aruser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_arvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_arready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_rid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] cb_mi_rdata ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_rresp ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rlast ;
wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] cb_mi_ruser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rready ;
genvar slot;
generate
for (slot=0;slot<C_NUM_SLAVE_SLOTS;slot=slot+1) begin : gen_si_tieoff
assign si_cb_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (s_axi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign si_cb_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign si_cb_awlen[slot*8+:8] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awlen[slot*P_LEN+:P_LEN] : 0 ;
assign si_cb_awsize[slot*3+:3] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awsize[slot*3+:3] : P_AXILITE_SIZE ;
assign si_cb_awburst[slot*2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awburst[slot*2+:2] : P_INCR ;
assign si_cb_awlock[slot*2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? {1'b0, s_axi_awlock[slot*P_LOCK+:1]} : 0 ;
assign si_cb_awcache[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awcache[slot*4+:4] : 0 ;
assign si_cb_awprot[slot*3+:3] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awprot[slot*3+:3] : 0 ;
assign si_cb_awqos[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awqos[slot*4+:4] : 0 ;
// assign si_cb_awregion[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_awregion[slot*4+:4] : 0 ;
assign si_cb_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] : 0 ;
assign si_cb_awvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awvalid[slot*1+:1] : 0 ;
assign si_cb_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI3) ) ? (s_axi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign si_cb_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign si_cb_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ;
assign si_cb_wlast[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_wlast[slot*1+:1] : 1'b1 ;
assign si_cb_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] : 0 ;
assign si_cb_wvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wvalid[slot*1+:1] : 0 ;
assign si_cb_bready[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_bready[slot*1+:1] : 0 ;
assign si_cb_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (s_axi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign si_cb_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign si_cb_arlen[slot*8+:8] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arlen[slot*P_LEN+:P_LEN] : 0 ;
assign si_cb_arsize[slot*3+:3] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arsize[slot*3+:3] : P_AXILITE_SIZE ;
assign si_cb_arburst[slot*2+:2] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arburst[slot*2+:2] : P_INCR ;
assign si_cb_arlock[slot*2+:2] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? {1'b0, s_axi_arlock[slot*P_LOCK+:1]} : 0 ;
assign si_cb_arcache[slot*4+:4] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arcache[slot*4+:4] : 0 ;
assign si_cb_arprot[slot*3+:3] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_arprot[slot*3+:3] : 0 ;
assign si_cb_arqos[slot*4+:4] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arqos[slot*4+:4] : 0 ;
// assign si_cb_arregion[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_arregion[slot*4+:4] : 0 ;
assign si_cb_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] : 0 ;
assign si_cb_arvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_arvalid[slot*1+:1] : 0 ;
assign si_cb_rready[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_rready[slot*1+:1] : 0 ;
assign s_axi_awready[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_awready[slot*1+:1] : 0 ;
assign s_axi_wready[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_wready[slot*1+:1] : 0 ;
assign s_axi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (si_cb_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign s_axi_bresp[slot*2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_bresp[slot*2+:2] : 0 ;
assign s_axi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] : 0 ;
assign s_axi_bvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_bvalid[slot*1+:1] : 0 ;
assign s_axi_arready[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_arready[slot*1+:1] : 0 ;
assign s_axi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (si_cb_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign s_axi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign s_axi_rresp[slot*2+:2] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rresp[slot*2+:2] : 0 ;
assign s_axi_rlast[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cb_rlast[slot*1+:1] : 0 ;
assign s_axi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] : 0 ;
assign s_axi_rvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rvalid[slot*1+:1] : 0 ;
end // gen_si_tieoff
for (slot=0;slot<C_NUM_MASTER_SLOTS;slot=slot+1) begin : gen_mi_tieoff
assign m_axi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign m_axi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign m_axi_awlen[slot*P_LEN+:P_LEN] = (~P_M_AXI_SUPPORTS_WRITE[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4 ) ? cb_mi_awlen[slot*8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_awlen[slot*8+:4] : 0 ;
assign m_axi_awsize[slot*3+:3] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awsize[slot*3+:3] : 0 ;
assign m_axi_awburst[slot*2+:2] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awburst[slot*2+:2] : 0 ;
assign m_axi_awlock[slot*P_LOCK+:P_LOCK] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awlock[slot*2+:1] : 0 ;
assign m_axi_awcache[slot*4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awcache[slot*4+:4] : 0 ;
assign m_axi_awprot[slot*3+:3] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awprot[slot*3+:3] : 0 ;
assign m_axi_awregion[slot*4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? cb_mi_awregion[slot*4+:4] : 0 ;
assign m_axi_awqos[slot*4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awqos[slot*4+:4] : 0 ;
assign m_axi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] : 0 ;
assign m_axi_awvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awvalid[slot*1+:1] : 0 ;
assign m_axi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign m_axi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign m_axi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ;
assign m_axi_wlast[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_wlast[slot*1+:1] : 0 ;
assign m_axi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] : 0 ;
assign m_axi_wvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wvalid[slot*1+:1] : 0 ;
assign m_axi_bready[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_bready[slot*1+:1] : 0 ;
assign m_axi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign m_axi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign m_axi_arlen[slot*P_LEN+:P_LEN] = (~P_M_AXI_SUPPORTS_READ[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4 ) ? cb_mi_arlen[slot*8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_arlen[slot*8+:4] : 0 ;
assign m_axi_arsize[slot*3+:3] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arsize[slot*3+:3] : 0 ;
assign m_axi_arburst[slot*2+:2] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arburst[slot*2+:2] : 0 ;
assign m_axi_arlock[slot*P_LOCK+:P_LOCK] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arlock[slot*2+:1] : 0 ;
assign m_axi_arcache[slot*4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arcache[slot*4+:4] : 0 ;
assign m_axi_arprot[slot*3+:3] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_arprot[slot*3+:3] : 0 ;
assign m_axi_arregion[slot*4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? cb_mi_arregion[slot*4+:4] : 0 ;
assign m_axi_arqos[slot*4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arqos[slot*4+:4] : 0 ;
assign m_axi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] : 0 ;
assign m_axi_arvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_arvalid[slot*1+:1] : 0 ;
assign m_axi_rready[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_rready[slot*1+:1] : 0 ;
assign cb_mi_awready[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_awready[slot*1+:1] : 0 ;
assign cb_mi_wready[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_wready[slot*1+:1] : 0 ;
assign cb_mi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign cb_mi_bresp[slot*2+:2] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_bresp[slot*2+:2] : 0 ;
assign cb_mi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] : 0 ;
assign cb_mi_bvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_bvalid[slot*1+:1] : 0 ;
assign cb_mi_arready[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_arready[slot*1+:1] : 0 ;
assign cb_mi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign cb_mi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign cb_mi_rresp[slot*2+:2] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rresp[slot*2+:2] : 0 ;
assign cb_mi_rlast[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rlast[slot*1+:1] : 1'b1 ;
assign cb_mi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] : 0 ;
assign cb_mi_rvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rvalid[slot*1+:1] : 0 ;
end // gen_mi_tieoff
if ((C_CONNECTIVITY_MODE==0) || (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_sasd
axi_crossbar_v2_1_crossbar_sasd #
(
.C_FAMILY (P_FAMILY),
.C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS),
.C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS),
.C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_M_AXI_BASE_ADDR (C_M_AXI_BASE_ADDR),
.C_M_AXI_HIGH_ADDR (f_high_addr(0)),
.C_S_AXI_BASE_ID (P_S_AXI_BASE_ID),
.C_S_AXI_HIGH_ID (P_S_AXI_HIGH_ID),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_S_AXI_SUPPORTS_WRITE (P_S_AXI_SUPPORTS_WRITE),
.C_S_AXI_SUPPORTS_READ (P_S_AXI_SUPPORTS_READ),
.C_M_AXI_SUPPORTS_WRITE (P_M_AXI_SUPPORTS_WRITE),
.C_M_AXI_SUPPORTS_READ (P_M_AXI_SUPPORTS_READ),
.C_S_AXI_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY),
.C_M_AXI_SECURE (C_M_AXI_SECURE),
.C_R_REGISTER (C_R_REGISTER),
.C_RANGE_CHECK (P_RANGE_CHECK),
.C_ADDR_DECODE (P_ADDR_DECODE),
.C_M_AXI_ERR_MODE (P_M_AXI_ERR_MODE),
.C_DEBUG (C_DEBUG)
)
crossbar_sasd_0
(
.ACLK (aclk),
.ARESETN (aresetn),
.S_AXI_AWID (si_cb_awid ),
.S_AXI_AWADDR (si_cb_awaddr ),
.S_AXI_AWLEN (si_cb_awlen ),
.S_AXI_AWSIZE (si_cb_awsize ),
.S_AXI_AWBURST (si_cb_awburst ),
.S_AXI_AWLOCK (si_cb_awlock ),
.S_AXI_AWCACHE (si_cb_awcache ),
.S_AXI_AWPROT (si_cb_awprot ),
// .S_AXI_AWREGION (si_cb_awregion ),
.S_AXI_AWQOS (si_cb_awqos ),
.S_AXI_AWUSER (si_cb_awuser ),
.S_AXI_AWVALID (si_cb_awvalid ),
.S_AXI_AWREADY (si_cb_awready ),
.S_AXI_WID (si_cb_wid ),
.S_AXI_WDATA (si_cb_wdata ),
.S_AXI_WSTRB (si_cb_wstrb ),
.S_AXI_WLAST (si_cb_wlast ),
.S_AXI_WUSER (si_cb_wuser ),
.S_AXI_WVALID (si_cb_wvalid ),
.S_AXI_WREADY (si_cb_wready ),
.S_AXI_BID (si_cb_bid ),
.S_AXI_BRESP (si_cb_bresp ),
.S_AXI_BUSER (si_cb_buser ),
.S_AXI_BVALID (si_cb_bvalid ),
.S_AXI_BREADY (si_cb_bready ),
.S_AXI_ARID (si_cb_arid ),
.S_AXI_ARADDR (si_cb_araddr ),
.S_AXI_ARLEN (si_cb_arlen ),
.S_AXI_ARSIZE (si_cb_arsize ),
.S_AXI_ARBURST (si_cb_arburst ),
.S_AXI_ARLOCK (si_cb_arlock ),
.S_AXI_ARCACHE (si_cb_arcache ),
.S_AXI_ARPROT (si_cb_arprot ),
// .S_AXI_ARREGION (si_cb_arregion ),
.S_AXI_ARQOS (si_cb_arqos ),
.S_AXI_ARUSER (si_cb_aruser ),
.S_AXI_ARVALID (si_cb_arvalid ),
.S_AXI_ARREADY (si_cb_arready ),
.S_AXI_RID (si_cb_rid ),
.S_AXI_RDATA (si_cb_rdata ),
.S_AXI_RRESP (si_cb_rresp ),
.S_AXI_RLAST (si_cb_rlast ),
.S_AXI_RUSER (si_cb_ruser ),
.S_AXI_RVALID (si_cb_rvalid ),
.S_AXI_RREADY (si_cb_rready ),
.M_AXI_AWID (cb_mi_awid ),
.M_AXI_AWADDR (cb_mi_awaddr ),
.M_AXI_AWLEN (cb_mi_awlen ),
.M_AXI_AWSIZE (cb_mi_awsize ),
.M_AXI_AWBURST (cb_mi_awburst ),
.M_AXI_AWLOCK (cb_mi_awlock ),
.M_AXI_AWCACHE (cb_mi_awcache ),
.M_AXI_AWPROT (cb_mi_awprot ),
.M_AXI_AWREGION (cb_mi_awregion ),
.M_AXI_AWQOS (cb_mi_awqos ),
.M_AXI_AWUSER (cb_mi_awuser ),
.M_AXI_AWVALID (cb_mi_awvalid ),
.M_AXI_AWREADY (cb_mi_awready ),
.M_AXI_WID (cb_mi_wid ),
.M_AXI_WDATA (cb_mi_wdata ),
.M_AXI_WSTRB (cb_mi_wstrb ),
.M_AXI_WLAST (cb_mi_wlast ),
.M_AXI_WUSER (cb_mi_wuser ),
.M_AXI_WVALID (cb_mi_wvalid ),
.M_AXI_WREADY (cb_mi_wready ),
.M_AXI_BID (cb_mi_bid ),
.M_AXI_BRESP (cb_mi_bresp ),
.M_AXI_BUSER (cb_mi_buser ),
.M_AXI_BVALID (cb_mi_bvalid ),
.M_AXI_BREADY (cb_mi_bready ),
.M_AXI_ARID (cb_mi_arid ),
.M_AXI_ARADDR (cb_mi_araddr ),
.M_AXI_ARLEN (cb_mi_arlen ),
.M_AXI_ARSIZE (cb_mi_arsize ),
.M_AXI_ARBURST (cb_mi_arburst ),
.M_AXI_ARLOCK (cb_mi_arlock ),
.M_AXI_ARCACHE (cb_mi_arcache ),
.M_AXI_ARPROT (cb_mi_arprot ),
.M_AXI_ARREGION (cb_mi_arregion ),
.M_AXI_ARQOS (cb_mi_arqos ),
.M_AXI_ARUSER (cb_mi_aruser ),
.M_AXI_ARVALID (cb_mi_arvalid ),
.M_AXI_ARREADY (cb_mi_arready ),
.M_AXI_RID (cb_mi_rid ),
.M_AXI_RDATA (cb_mi_rdata ),
.M_AXI_RRESP (cb_mi_rresp ),
.M_AXI_RLAST (cb_mi_rlast ),
.M_AXI_RUSER (cb_mi_ruser ),
.M_AXI_RVALID (cb_mi_rvalid ),
.M_AXI_RREADY (cb_mi_rready )
);
end else begin : gen_samd
axi_crossbar_v2_1_crossbar #
(
.C_FAMILY (P_FAMILY),
.C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS),
.C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS),
.C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_S_AXI_THREAD_ID_WIDTH (C_S_AXI_THREAD_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_M_AXI_BASE_ADDR (C_M_AXI_BASE_ADDR),
.C_M_AXI_HIGH_ADDR (f_high_addr(0)),
.C_S_AXI_BASE_ID (P_S_AXI_BASE_ID),
.C_S_AXI_HIGH_ID (P_S_AXI_HIGH_ID),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_S_AXI_SUPPORTS_WRITE (P_S_AXI_SUPPORTS_WRITE),
.C_S_AXI_SUPPORTS_READ (P_S_AXI_SUPPORTS_READ),
.C_M_AXI_SUPPORTS_WRITE (P_M_AXI_SUPPORTS_WRITE),
.C_M_AXI_SUPPORTS_READ (P_M_AXI_SUPPORTS_READ),
.C_M_AXI_WRITE_CONNECTIVITY (C_M_AXI_WRITE_CONNECTIVITY),
.C_M_AXI_READ_CONNECTIVITY (C_M_AXI_READ_CONNECTIVITY),
.C_S_AXI_SINGLE_THREAD (C_S_AXI_SINGLE_THREAD),
.C_S_AXI_WRITE_ACCEPTANCE (C_S_AXI_WRITE_ACCEPTANCE),
.C_S_AXI_READ_ACCEPTANCE (C_S_AXI_READ_ACCEPTANCE),
.C_M_AXI_WRITE_ISSUING (C_M_AXI_WRITE_ISSUING),
.C_M_AXI_READ_ISSUING (C_M_AXI_READ_ISSUING),
.C_S_AXI_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY),
.C_M_AXI_SECURE (C_M_AXI_SECURE),
.C_RANGE_CHECK (P_RANGE_CHECK),
.C_ADDR_DECODE (P_ADDR_DECODE),
.C_W_ISSUE_WIDTH (f_write_issue_width_vec(0) ),
.C_R_ISSUE_WIDTH (f_read_issue_width_vec(0) ),
.C_W_ACCEPT_WIDTH (f_write_accept_width_vec(0)),
.C_R_ACCEPT_WIDTH (f_read_accept_width_vec(0)),
.C_M_AXI_ERR_MODE (P_M_AXI_ERR_MODE),
.C_DEBUG (C_DEBUG)
)
crossbar_samd
(
.ACLK (aclk),
.ARESETN (aresetn),
.S_AXI_AWID (si_cb_awid ),
.S_AXI_AWADDR (si_cb_awaddr ),
.S_AXI_AWLEN (si_cb_awlen ),
.S_AXI_AWSIZE (si_cb_awsize ),
.S_AXI_AWBURST (si_cb_awburst ),
.S_AXI_AWLOCK (si_cb_awlock ),
.S_AXI_AWCACHE (si_cb_awcache ),
.S_AXI_AWPROT (si_cb_awprot ),
// .S_AXI_AWREGION (si_cb_awregion ),
.S_AXI_AWQOS (si_cb_awqos ),
.S_AXI_AWUSER (si_cb_awuser ),
.S_AXI_AWVALID (si_cb_awvalid ),
.S_AXI_AWREADY (si_cb_awready ),
.S_AXI_WID (si_cb_wid ),
.S_AXI_WDATA (si_cb_wdata ),
.S_AXI_WSTRB (si_cb_wstrb ),
.S_AXI_WLAST (si_cb_wlast ),
.S_AXI_WUSER (si_cb_wuser ),
.S_AXI_WVALID (si_cb_wvalid ),
.S_AXI_WREADY (si_cb_wready ),
.S_AXI_BID (si_cb_bid ),
.S_AXI_BRESP (si_cb_bresp ),
.S_AXI_BUSER (si_cb_buser ),
.S_AXI_BVALID (si_cb_bvalid ),
.S_AXI_BREADY (si_cb_bready ),
.S_AXI_ARID (si_cb_arid ),
.S_AXI_ARADDR (si_cb_araddr ),
.S_AXI_ARLEN (si_cb_arlen ),
.S_AXI_ARSIZE (si_cb_arsize ),
.S_AXI_ARBURST (si_cb_arburst ),
.S_AXI_ARLOCK (si_cb_arlock ),
.S_AXI_ARCACHE (si_cb_arcache ),
.S_AXI_ARPROT (si_cb_arprot ),
// .S_AXI_ARREGION (si_cb_arregion ),
.S_AXI_ARQOS (si_cb_arqos ),
.S_AXI_ARUSER (si_cb_aruser ),
.S_AXI_ARVALID (si_cb_arvalid ),
.S_AXI_ARREADY (si_cb_arready ),
.S_AXI_RID (si_cb_rid ),
.S_AXI_RDATA (si_cb_rdata ),
.S_AXI_RRESP (si_cb_rresp ),
.S_AXI_RLAST (si_cb_rlast ),
.S_AXI_RUSER (si_cb_ruser ),
.S_AXI_RVALID (si_cb_rvalid ),
.S_AXI_RREADY (si_cb_rready ),
.M_AXI_AWID (cb_mi_awid ),
.M_AXI_AWADDR (cb_mi_awaddr ),
.M_AXI_AWLEN (cb_mi_awlen ),
.M_AXI_AWSIZE (cb_mi_awsize ),
.M_AXI_AWBURST (cb_mi_awburst ),
.M_AXI_AWLOCK (cb_mi_awlock ),
.M_AXI_AWCACHE (cb_mi_awcache ),
.M_AXI_AWPROT (cb_mi_awprot ),
.M_AXI_AWREGION (cb_mi_awregion ),
.M_AXI_AWQOS (cb_mi_awqos ),
.M_AXI_AWUSER (cb_mi_awuser ),
.M_AXI_AWVALID (cb_mi_awvalid ),
.M_AXI_AWREADY (cb_mi_awready ),
.M_AXI_WID (cb_mi_wid ),
.M_AXI_WDATA (cb_mi_wdata ),
.M_AXI_WSTRB (cb_mi_wstrb ),
.M_AXI_WLAST (cb_mi_wlast ),
.M_AXI_WUSER (cb_mi_wuser ),
.M_AXI_WVALID (cb_mi_wvalid ),
.M_AXI_WREADY (cb_mi_wready ),
.M_AXI_BID (cb_mi_bid ),
.M_AXI_BRESP (cb_mi_bresp ),
.M_AXI_BUSER (cb_mi_buser ),
.M_AXI_BVALID (cb_mi_bvalid ),
.M_AXI_BREADY (cb_mi_bready ),
.M_AXI_ARID (cb_mi_arid ),
.M_AXI_ARADDR (cb_mi_araddr ),
.M_AXI_ARLEN (cb_mi_arlen ),
.M_AXI_ARSIZE (cb_mi_arsize ),
.M_AXI_ARBURST (cb_mi_arburst ),
.M_AXI_ARLOCK (cb_mi_arlock ),
.M_AXI_ARCACHE (cb_mi_arcache ),
.M_AXI_ARPROT (cb_mi_arprot ),
.M_AXI_ARREGION (cb_mi_arregion ),
.M_AXI_ARQOS (cb_mi_arqos ),
.M_AXI_ARUSER (cb_mi_aruser ),
.M_AXI_ARVALID (cb_mi_arvalid ),
.M_AXI_ARREADY (cb_mi_arready ),
.M_AXI_RID (cb_mi_rid ),
.M_AXI_RDATA (cb_mi_rdata ),
.M_AXI_RRESP (cb_mi_rresp ),
.M_AXI_RLAST (cb_mi_rlast ),
.M_AXI_RUSER (cb_mi_ruser ),
.M_AXI_RVALID (cb_mi_rvalid ),
.M_AXI_RREADY (cb_mi_rready )
);
end // gen_samd
// end // gen_crossbar
endgenerate
endmodule
`default_nettype wire
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo);
parameter bitwidth = 16;
parameter zwidth = 16;
parameter shift = 1;
input clock;
input reset;
input enable;
input [bitwidth-1:0] xi,yi;
input [zwidth-1:0] zi;
input [zwidth-1:0] constant;
output [bitwidth-1:0] xo,yo;
output [zwidth-1:0] zo;
wire z_is_pos = ~zi[zwidth-1];
reg [bitwidth-1:0] xo,yo;
reg [zwidth-1:0] zo;
always @(posedge clock)
if(reset)
begin
xo <= #1 0;
yo <= #1 0;
zo <= #1 0;
end
else if(enable)
begin
xo <= #1 z_is_pos ?
xi - {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]} :
xi + {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]};
yo <= #1 z_is_pos ?
yi + {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]} :
yi - {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]};
zo <= #1 z_is_pos ?
zi - constant :
zi + constant;
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo);
parameter bitwidth = 16;
parameter zwidth = 16;
parameter shift = 1;
input clock;
input reset;
input enable;
input [bitwidth-1:0] xi,yi;
input [zwidth-1:0] zi;
input [zwidth-1:0] constant;
output [bitwidth-1:0] xo,yo;
output [zwidth-1:0] zo;
wire z_is_pos = ~zi[zwidth-1];
reg [bitwidth-1:0] xo,yo;
reg [zwidth-1:0] zo;
always @(posedge clock)
if(reset)
begin
xo <= #1 0;
yo <= #1 0;
zo <= #1 0;
end
else if(enable)
begin
xo <= #1 z_is_pos ?
xi - {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]} :
xi + {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]};
yo <= #1 z_is_pos ?
yi + {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]} :
yi - {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]};
zo <= #1 z_is_pos ?
zi - constant :
zi + constant;
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo);
parameter bitwidth = 16;
parameter zwidth = 16;
parameter shift = 1;
input clock;
input reset;
input enable;
input [bitwidth-1:0] xi,yi;
input [zwidth-1:0] zi;
input [zwidth-1:0] constant;
output [bitwidth-1:0] xo,yo;
output [zwidth-1:0] zo;
wire z_is_pos = ~zi[zwidth-1];
reg [bitwidth-1:0] xo,yo;
reg [zwidth-1:0] zo;
always @(posedge clock)
if(reset)
begin
xo <= #1 0;
yo <= #1 0;
zo <= #1 0;
end
else if(enable)
begin
xo <= #1 z_is_pos ?
xi - {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]} :
xi + {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]};
yo <= #1 z_is_pos ?
yi + {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]} :
yi - {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]};
zo <= #1 z_is_pos ?
zi - constant :
zi + constant;
end
endmodule
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: wdata_router.v
//
// Description:
// Contains SI-side write command queue.
// Target MI-slot index is pushed onto queue when S_AVALID transfer is received.
// Queue is popped when WLAST data beat is transferred.
// W-channel input is transferred to MI-slot output selected by queue output.
//--------------------------------------------------------------------------
//
// Structure:
// wdata_router
// axic_reg_srl_fifo
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_wdata_router #
(
parameter C_FAMILY = "none", // FPGA Family.
parameter integer C_WMESG_WIDTH = 1, // Width of all data signals
parameter integer C_NUM_MASTER_SLOTS = 1, // Number of M_* ports.
parameter integer C_SELECT_WIDTH = 1, // Width of S_ASELECT.
parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2**C_FIFO_DEPTH_LOG.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave Data Ports
input wire [C_WMESG_WIDTH-1:0] S_WMESG,
input wire S_WLAST,
input wire S_WVALID,
output wire S_WREADY,
// Master Data Ports
output wire [C_WMESG_WIDTH-1:0] M_WMESG, // Broadcast to all MI-slots
output wire M_WLAST, // Broadcast to all MI-slots
output wire [C_NUM_MASTER_SLOTS-1:0] M_WVALID, // Per MI-slot
input wire [C_NUM_MASTER_SLOTS-1:0] M_WREADY, // Per MI-slot
// Address Arbiter Ports
input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // Target MI-slot index from SI-side AW command
input wire S_AVALID,
output wire S_AREADY
);
localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5; // Max depth = 32
// Decode select input to 1-hot
function [C_NUM_MASTER_SLOTS-1:0] f_decoder (
input [C_SELECT_WIDTH-1:0] sel
);
integer i;
begin
for (i=0; i<C_NUM_MASTER_SLOTS; i=i+1) begin
f_decoder[i] = (sel == i);
end
end
endfunction
//---------------------------------------------------------------------------
// Internal signal declarations
//---------------------------------------------------------------------------
wire [C_NUM_MASTER_SLOTS-1:0] m_select_hot;
wire [C_SELECT_WIDTH-1:0] m_select_enc;
wire m_avalid;
wire m_aready;
//---------------------------------------------------------------------------
// Router
//---------------------------------------------------------------------------
// SI-side write command queue
axi_data_fifo_v2_1_axic_reg_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (C_SELECT_WIDTH),
.C_FIFO_DEPTH_LOG (P_FIFO_DEPTH_LOG),
.C_USE_FULL (1)
)
wrouter_aw_fifo
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (S_ASELECT),
.S_VALID (S_AVALID),
.S_READY (S_AREADY),
.M_MESG (m_select_enc),
.M_VALID (m_avalid),
.M_READY (m_aready)
);
assign m_select_hot = f_decoder(m_select_enc);
// W-channel payload and LAST are broadcast to all MI-slot's W-mux
assign M_WMESG = S_WMESG;
assign M_WLAST = S_WLAST;
// Assert m_aready when last beat acknowledged by slave
assign m_aready = m_avalid & S_WVALID & S_WLAST & (|(M_WREADY & m_select_hot));
// M_WVALID is generated per MI-slot (including error handler at slot C_NUM_MASTER_SLOTS).
// The slot selected by the head of the queue (m_select_enc) is enabled.
assign M_WVALID = {C_NUM_MASTER_SLOTS{S_WVALID & m_avalid}} & m_select_hot;
// S_WREADY is muxed from the MI slot selected by the head of the queue (m_select_enc).
assign S_WREADY = m_avalid & (|(M_WREADY & m_select_hot));
endmodule
`default_nettype wire
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: wdata_router.v
//
// Description:
// Contains SI-side write command queue.
// Target MI-slot index is pushed onto queue when S_AVALID transfer is received.
// Queue is popped when WLAST data beat is transferred.
// W-channel input is transferred to MI-slot output selected by queue output.
//--------------------------------------------------------------------------
//
// Structure:
// wdata_router
// axic_reg_srl_fifo
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_wdata_router #
(
parameter C_FAMILY = "none", // FPGA Family.
parameter integer C_WMESG_WIDTH = 1, // Width of all data signals
parameter integer C_NUM_MASTER_SLOTS = 1, // Number of M_* ports.
parameter integer C_SELECT_WIDTH = 1, // Width of S_ASELECT.
parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2**C_FIFO_DEPTH_LOG.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave Data Ports
input wire [C_WMESG_WIDTH-1:0] S_WMESG,
input wire S_WLAST,
input wire S_WVALID,
output wire S_WREADY,
// Master Data Ports
output wire [C_WMESG_WIDTH-1:0] M_WMESG, // Broadcast to all MI-slots
output wire M_WLAST, // Broadcast to all MI-slots
output wire [C_NUM_MASTER_SLOTS-1:0] M_WVALID, // Per MI-slot
input wire [C_NUM_MASTER_SLOTS-1:0] M_WREADY, // Per MI-slot
// Address Arbiter Ports
input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // Target MI-slot index from SI-side AW command
input wire S_AVALID,
output wire S_AREADY
);
localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5; // Max depth = 32
// Decode select input to 1-hot
function [C_NUM_MASTER_SLOTS-1:0] f_decoder (
input [C_SELECT_WIDTH-1:0] sel
);
integer i;
begin
for (i=0; i<C_NUM_MASTER_SLOTS; i=i+1) begin
f_decoder[i] = (sel == i);
end
end
endfunction
//---------------------------------------------------------------------------
// Internal signal declarations
//---------------------------------------------------------------------------
wire [C_NUM_MASTER_SLOTS-1:0] m_select_hot;
wire [C_SELECT_WIDTH-1:0] m_select_enc;
wire m_avalid;
wire m_aready;
//---------------------------------------------------------------------------
// Router
//---------------------------------------------------------------------------
// SI-side write command queue
axi_data_fifo_v2_1_axic_reg_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (C_SELECT_WIDTH),
.C_FIFO_DEPTH_LOG (P_FIFO_DEPTH_LOG),
.C_USE_FULL (1)
)
wrouter_aw_fifo
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (S_ASELECT),
.S_VALID (S_AVALID),
.S_READY (S_AREADY),
.M_MESG (m_select_enc),
.M_VALID (m_avalid),
.M_READY (m_aready)
);
assign m_select_hot = f_decoder(m_select_enc);
// W-channel payload and LAST are broadcast to all MI-slot's W-mux
assign M_WMESG = S_WMESG;
assign M_WLAST = S_WLAST;
// Assert m_aready when last beat acknowledged by slave
assign m_aready = m_avalid & S_WVALID & S_WLAST & (|(M_WREADY & m_select_hot));
// M_WVALID is generated per MI-slot (including error handler at slot C_NUM_MASTER_SLOTS).
// The slot selected by the head of the queue (m_select_enc) is enabled.
assign M_WVALID = {C_NUM_MASTER_SLOTS{S_WVALID & m_avalid}} & m_select_hot;
// S_WREADY is muxed from the MI slot selected by the head of the queue (m_select_enc).
assign S_WREADY = m_avalid & (|(M_WREADY & m_select_hot));
endmodule
`default_nettype wire
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// NOTE This only works for N=4, max decim rate of 128
// NOTE signal "rate" is ONE LESS THAN the actual rate
module cic_dec_shifter(rate,signal_in,signal_out);
parameter bw = 16;
parameter maxbitgain = 28;
input [7:0] rate;
input wire [bw+maxbitgain-1:0] signal_in;
output reg [bw-1:0] signal_out;
function [4:0] bitgain;
input [7:0] rate;
case(rate)
// Exact Cases -- N*log2(rate)
8'd4 : bitgain = 8;
8'd8 : bitgain = 12;
8'd16 : bitgain = 16;
8'd32 : bitgain = 20;
8'd64 : bitgain = 24;
8'd128 : bitgain = 28;
// Nearest without overflow -- ceil(N*log2(rate))
8'd5 : bitgain = 10;
8'd6 : bitgain = 11;
8'd7 : bitgain = 12;
8'd9 : bitgain = 13;
8'd10,8'd11 : bitgain = 14;
8'd12,8'd13 : bitgain = 15;
8'd14,8'd15 : bitgain = 16;
8'd17,8'd18,8'd19 : bitgain = 17;
8'd20,8'd21,8'd22 : bitgain = 18;
8'd23,8'd24,8'd25,8'd26 : bitgain = 19;
8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 20;
8'd33,8'd34,8'd35,8'd36,8'd37,8'd38 : bitgain = 21;
8'd39,8'd40,8'd41,8'd42,8'd43,8'd44,8'd45 : bitgain = 22;
8'd46,8'd47,8'd48,8'd49,8'd50,8'd51,8'd52,8'd53 : bitgain = 23;
8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 24;
8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76 : bitgain = 25;
8'd77,8'd78,8'd79,8'd80,8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90 : bitgain = 26;
8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101,8'd102,8'd103,8'd104,8'd105,8'd106,8'd107 : bitgain = 27;
default : bitgain = 28;
endcase // case(rate)
endfunction // bitgain
wire [4:0] shift = bitgain(rate+1);
// We should be able to do this, but can't ....
// assign signal_out = signal_in[shift+bw-1:shift];
always @*
case(shift)
5'd8 : signal_out = signal_in[8+bw-1:8];
5'd10 : signal_out = signal_in[10+bw-1:10];
5'd11 : signal_out = signal_in[11+bw-1:11];
5'd12 : signal_out = signal_in[12+bw-1:12];
5'd13 : signal_out = signal_in[13+bw-1:13];
5'd14 : signal_out = signal_in[14+bw-1:14];
5'd15 : signal_out = signal_in[15+bw-1:15];
5'd16 : signal_out = signal_in[16+bw-1:16];
5'd17 : signal_out = signal_in[17+bw-1:17];
5'd18 : signal_out = signal_in[18+bw-1:18];
5'd19 : signal_out = signal_in[19+bw-1:19];
5'd20 : signal_out = signal_in[20+bw-1:20];
5'd21 : signal_out = signal_in[21+bw-1:21];
5'd22 : signal_out = signal_in[22+bw-1:22];
5'd23 : signal_out = signal_in[23+bw-1:23];
5'd24 : signal_out = signal_in[24+bw-1:24];
5'd25 : signal_out = signal_in[25+bw-1:25];
5'd26 : signal_out = signal_in[26+bw-1:26];
5'd27 : signal_out = signal_in[27+bw-1:27];
5'd28 : signal_out = signal_in[28+bw-1:28];
default : signal_out = signal_in[28+bw-1:28];
endcase // case(shift)
endmodule // cic_dec_shifter
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// NOTE This only works for N=4, max decim rate of 128
// NOTE signal "rate" is ONE LESS THAN the actual rate
module cic_dec_shifter(rate,signal_in,signal_out);
parameter bw = 16;
parameter maxbitgain = 28;
input [7:0] rate;
input wire [bw+maxbitgain-1:0] signal_in;
output reg [bw-1:0] signal_out;
function [4:0] bitgain;
input [7:0] rate;
case(rate)
// Exact Cases -- N*log2(rate)
8'd4 : bitgain = 8;
8'd8 : bitgain = 12;
8'd16 : bitgain = 16;
8'd32 : bitgain = 20;
8'd64 : bitgain = 24;
8'd128 : bitgain = 28;
// Nearest without overflow -- ceil(N*log2(rate))
8'd5 : bitgain = 10;
8'd6 : bitgain = 11;
8'd7 : bitgain = 12;
8'd9 : bitgain = 13;
8'd10,8'd11 : bitgain = 14;
8'd12,8'd13 : bitgain = 15;
8'd14,8'd15 : bitgain = 16;
8'd17,8'd18,8'd19 : bitgain = 17;
8'd20,8'd21,8'd22 : bitgain = 18;
8'd23,8'd24,8'd25,8'd26 : bitgain = 19;
8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 20;
8'd33,8'd34,8'd35,8'd36,8'd37,8'd38 : bitgain = 21;
8'd39,8'd40,8'd41,8'd42,8'd43,8'd44,8'd45 : bitgain = 22;
8'd46,8'd47,8'd48,8'd49,8'd50,8'd51,8'd52,8'd53 : bitgain = 23;
8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 24;
8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76 : bitgain = 25;
8'd77,8'd78,8'd79,8'd80,8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90 : bitgain = 26;
8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101,8'd102,8'd103,8'd104,8'd105,8'd106,8'd107 : bitgain = 27;
default : bitgain = 28;
endcase // case(rate)
endfunction // bitgain
wire [4:0] shift = bitgain(rate+1);
// We should be able to do this, but can't ....
// assign signal_out = signal_in[shift+bw-1:shift];
always @*
case(shift)
5'd8 : signal_out = signal_in[8+bw-1:8];
5'd10 : signal_out = signal_in[10+bw-1:10];
5'd11 : signal_out = signal_in[11+bw-1:11];
5'd12 : signal_out = signal_in[12+bw-1:12];
5'd13 : signal_out = signal_in[13+bw-1:13];
5'd14 : signal_out = signal_in[14+bw-1:14];
5'd15 : signal_out = signal_in[15+bw-1:15];
5'd16 : signal_out = signal_in[16+bw-1:16];
5'd17 : signal_out = signal_in[17+bw-1:17];
5'd18 : signal_out = signal_in[18+bw-1:18];
5'd19 : signal_out = signal_in[19+bw-1:19];
5'd20 : signal_out = signal_in[20+bw-1:20];
5'd21 : signal_out = signal_in[21+bw-1:21];
5'd22 : signal_out = signal_in[22+bw-1:22];
5'd23 : signal_out = signal_in[23+bw-1:23];
5'd24 : signal_out = signal_in[24+bw-1:24];
5'd25 : signal_out = signal_in[25+bw-1:25];
5'd26 : signal_out = signal_in[26+bw-1:26];
5'd27 : signal_out = signal_in[27+bw-1:27];
5'd28 : signal_out = signal_in[28+bw-1:28];
default : signal_out = signal_in[28+bw-1:28];
endcase // case(shift)
endmodule // cic_dec_shifter
|
module mac (input clock, input reset, input enable, input clear,
input signed [15:0] x, input signed [15:0] y,
input [7:0] shift, output [15:0] z );
reg signed [30:0] product;
reg signed [39:0] z_int;
reg signed [15:0] z_shift;
reg enable_d1;
always @(posedge clock)
enable_d1 <= #1 enable;
always @(posedge clock)
if(reset | clear)
z_int <= #1 40'd0;
else if(enable_d1)
z_int <= #1 z_int + {{9{product[30]}},product};
always @(posedge clock)
product <= #1 x*y;
always @* // FIXME full case? parallel case?
case(shift)
//8'd0 : z_shift <= z_int[39:24];
//8'd1 : z_shift <= z_int[38:23];
//8'd2 : z_shift <= z_int[37:22];
//8'd3 : z_shift <= z_int[36:21];
//8'd4 : z_shift <= z_int[35:20];
//8'd5 : z_shift <= z_int[34:19];
8'd6 : z_shift <= z_int[33:18];
8'd7 : z_shift <= z_int[32:17];
8'd8 : z_shift <= z_int[31:16];
8'd9 : z_shift <= z_int[30:15];
8'd10 : z_shift <= z_int[29:14];
8'd11 : z_shift <= z_int[28:13];
//8'd12 : z_shift <= z_int[27:12];
//8'd13 : z_shift <= z_int[26:11];
//8'd14 : z_shift <= z_int[25:10];
//8'd15 : z_shift <= z_int[24:9];
//8'd16 : z_shift <= z_int[23:8];
//8'd17 : z_shift <= z_int[22:7];
//8'd18 : z_shift <= z_int[21:6];
//8'd19 : z_shift <= z_int[20:5];
//8'd20 : z_shift <= z_int[19:4];
//8'd21 : z_shift <= z_int[18:3];
//8'd22 : z_shift <= z_int[17:2];
//8'd23 : z_shift <= z_int[16:1];
//8'd24 : z_shift <= z_int[15:0];
default : z_shift <= z_int[15:0];
endcase // case(shift)
// FIXME do we need to saturate?
//assign z = z_shift;
assign z = z_int[15:0];
endmodule // mac
|
module mac (input clock, input reset, input enable, input clear,
input signed [15:0] x, input signed [15:0] y,
input [7:0] shift, output [15:0] z );
reg signed [30:0] product;
reg signed [39:0] z_int;
reg signed [15:0] z_shift;
reg enable_d1;
always @(posedge clock)
enable_d1 <= #1 enable;
always @(posedge clock)
if(reset | clear)
z_int <= #1 40'd0;
else if(enable_d1)
z_int <= #1 z_int + {{9{product[30]}},product};
always @(posedge clock)
product <= #1 x*y;
always @* // FIXME full case? parallel case?
case(shift)
//8'd0 : z_shift <= z_int[39:24];
//8'd1 : z_shift <= z_int[38:23];
//8'd2 : z_shift <= z_int[37:22];
//8'd3 : z_shift <= z_int[36:21];
//8'd4 : z_shift <= z_int[35:20];
//8'd5 : z_shift <= z_int[34:19];
8'd6 : z_shift <= z_int[33:18];
8'd7 : z_shift <= z_int[32:17];
8'd8 : z_shift <= z_int[31:16];
8'd9 : z_shift <= z_int[30:15];
8'd10 : z_shift <= z_int[29:14];
8'd11 : z_shift <= z_int[28:13];
//8'd12 : z_shift <= z_int[27:12];
//8'd13 : z_shift <= z_int[26:11];
//8'd14 : z_shift <= z_int[25:10];
//8'd15 : z_shift <= z_int[24:9];
//8'd16 : z_shift <= z_int[23:8];
//8'd17 : z_shift <= z_int[22:7];
//8'd18 : z_shift <= z_int[21:6];
//8'd19 : z_shift <= z_int[20:5];
//8'd20 : z_shift <= z_int[19:4];
//8'd21 : z_shift <= z_int[18:3];
//8'd22 : z_shift <= z_int[17:2];
//8'd23 : z_shift <= z_int[16:1];
//8'd24 : z_shift <= z_int[15:0];
default : z_shift <= z_int[15:0];
endcase // case(shift)
// FIXME do we need to saturate?
//assign z = z_shift;
assign z = z_int[15:0];
endmodule // mac
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module dpram(wclk,wdata,waddr,wen,rclk,rdata,raddr);
parameter depth = 4;
parameter width = 16;
parameter size = 16;
input wclk;
input [width-1:0] wdata;
input [depth-1:0] waddr;
input wen;
input rclk;
output reg [width-1:0] rdata;
input [depth-1:0] raddr;
reg [width-1:0] ram [0:size-1];
always @(posedge wclk)
if(wen)
ram[waddr] <= #1 wdata;
always @(posedge rclk)
rdata <= #1 ram[raddr];
endmodule // dpram
|
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module mylpm_addsub (
add_sub,
dataa,
datab,
clock,
result);
input add_sub;
input [15:0] dataa;
input [15:0] datab;
input clock;
output [15:0] result;
endmodule
|
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module mylpm_addsub (
add_sub,
dataa,
datab,
clock,
result);
input add_sub;
input [15:0] dataa;
input [15:0] datab;
input clock;
output [15:0] result;
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clk_doubler.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 156 11/29/2004 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module clk_doubler (
inclk0,
c0);
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0)
// synopsys translate_off
,
.activeclock (),
.areset (),
.clkbad (),
.clkena (),
.clkloss (),
.clkswitch (),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena (),
.fbin (),
.locked (),
.pfdena (),
.pllena (),
.scanaclr (),
.scanclk (),
.scandata (),
.scandataout (),
.scandone (),
.scanread (),
.scanwrite (),
.sclkout0 (),
.sclkout1 ()
// synopsys translate_on
);
defparam
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 2,
altpll_component.inclk0_input_frequency = 15625,
altpll_component.clk0_divide_by = 1,
altpll_component.pll_type = "AUTO",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk0_phase_shift = "0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clk_doubler.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 156 11/29/2004 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module clk_doubler (
inclk0,
c0);
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0)
// synopsys translate_off
,
.activeclock (),
.areset (),
.clkbad (),
.clkena (),
.clkloss (),
.clkswitch (),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena (),
.fbin (),
.locked (),
.pfdena (),
.pllena (),
.scanaclr (),
.scanclk (),
.scandata (),
.scandataout (),
.scandone (),
.scanread (),
.scanwrite (),
.sclkout0 (),
.sclkout1 ()
// synopsys translate_on
);
defparam
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 2,
altpll_component.inclk0_input_frequency = 15625,
altpll_component.clk0_divide_by = 1,
altpll_component.pll_type = "AUTO",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk0_phase_shift = "0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_2k.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_2k (
data,
wrreq,
rdreq,
rdclk,
wrclk,
aclr,
q,
rdempty,
rdusedw,
wrfull,
wrusedw)/* synthesis synthesis_clearbox = 1 */;
input [15:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [15:0] q;
output rdempty;
output [10:0] rdusedw;
output wrfull;
output [10:0] wrusedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: Depth NUMERIC "2048"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL rdusedw[10..0]
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0]
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_wave*.jpg FALSE
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_2k.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_2k (
data,
wrreq,
rdreq,
rdclk,
wrclk,
aclr,
q,
rdempty,
rdusedw,
wrfull,
wrusedw)/* synthesis synthesis_clearbox = 1 */;
input [15:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [15:0] q;
output rdempty;
output [10:0] rdusedw;
output wrfull;
output [10:0] wrusedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: Depth NUMERIC "2048"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL rdusedw[10..0]
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0]
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_wave*.jpg FALSE
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_2k.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_2k (
data,
wrreq,
rdreq,
rdclk,
wrclk,
aclr,
q,
rdempty,
rdusedw,
wrfull,
wrusedw)/* synthesis synthesis_clearbox = 1 */;
input [15:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [15:0] q;
output rdempty;
output [10:0] rdusedw;
output wrfull;
output [10:0] wrusedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: Depth NUMERIC "2048"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL rdusedw[10..0]
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0]
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_wave*.jpg FALSE
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_4k.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_4k (
data,
wrreq,
rdreq,
rdclk,
wrclk,
aclr,
q,
rdempty,
rdusedw,
wrfull,
wrusedw)/* synthesis synthesis_clearbox = 1 */;
input [15:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module tx_chain_hb
(input clock,
input reset,
input enable,
input wire [7:0] interp_rate,
input sample_strobe,
input interpolator_strobe,
input hb_strobe,
input wire [31:0] freq,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out,
output wire [15:0] debug, output [15:0] hb_i_out
);
assign debug[15:13] = {sample_strobe,hb_strobe,interpolator_strobe};
wire [15:0] bb_i, bb_q;
wire [15:0] hb_i_out, hb_q_out;
halfband_interp hb
(.clock(clock),.reset(reset),.enable(enable),
.strobe_in(interpolator_strobe),.strobe_out(hb_strobe),
.signal_in_i(i_in),.signal_in_q(q_in),
.signal_out_i(hb_i_out),.signal_out_q(hb_q_out),
.debug(debug[12:0]));
cic_interp cic_interp_i
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
.signal_in(hb_i_out),.signal_out(bb_i) );
cic_interp cic_interp_q
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
.signal_in(hb_q_out),.signal_out(bb_q) );
`define NOCORDIC_TX
`ifdef NOCORDIC_TX
assign i_out = bb_i;
assign q_out = bb_q;
`else
wire [31:0] phase;
phase_acc phase_acc_tx
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq),.phase(phase) );
cordic tx_cordic_0
( .clock(clock),.reset(reset),.enable(sample_strobe),
.xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
.xo(i_out),.yo(q_out),.zo() );
`endif
endmodule // tx_chain
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module tx_chain_hb
(input clock,
input reset,
input enable,
input wire [7:0] interp_rate,
input sample_strobe,
input interpolator_strobe,
input hb_strobe,
input wire [31:0] freq,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out,
output wire [15:0] debug, output [15:0] hb_i_out
);
assign debug[15:13] = {sample_strobe,hb_strobe,interpolator_strobe};
wire [15:0] bb_i, bb_q;
wire [15:0] hb_i_out, hb_q_out;
halfband_interp hb
(.clock(clock),.reset(reset),.enable(enable),
.strobe_in(interpolator_strobe),.strobe_out(hb_strobe),
.signal_in_i(i_in),.signal_in_q(q_in),
.signal_out_i(hb_i_out),.signal_out_q(hb_q_out),
.debug(debug[12:0]));
cic_interp cic_interp_i
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
.signal_in(hb_i_out),.signal_out(bb_i) );
cic_interp cic_interp_q
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
.signal_in(hb_q_out),.signal_out(bb_q) );
`define NOCORDIC_TX
`ifdef NOCORDIC_TX
assign i_out = bb_i;
assign q_out = bb_q;
`else
wire [31:0] phase;
phase_acc phase_acc_tx
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq),.phase(phase) );
cordic tx_cordic_0
( .clock(clock),.reset(reset),.enable(sample_strobe),
.xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
.xo(i_out),.yo(q_out),.zo() );
`endif
endmodule // tx_chain
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module clk_divider(input reset, input wire in_clk,output reg out_clk, input [7:0] ratio);
reg [7:0] counter;
// FIXME maybe should use PLL or switch to double edge version
always @(posedge in_clk or posedge reset)
if(reset)
counter <= #1 8'd0;
else if(counter == 0)
counter <= #1 ratio[7:1] + (ratio[0] & out_clk) - 8'b1;
else
counter <= #1 counter-8'd1;
always @(posedge in_clk or posedge reset)
if(reset)
out_clk <= #1 1'b0;
else if(counter == 0)
out_clk <= #1 ~out_clk;
endmodule // clk_divider
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module clk_divider(input reset, input wire in_clk,output reg out_clk, input [7:0] ratio);
reg [7:0] counter;
// FIXME maybe should use PLL or switch to double edge version
always @(posedge in_clk or posedge reset)
if(reset)
counter <= #1 8'd0;
else if(counter == 0)
counter <= #1 ratio[7:1] + (ratio[0] & out_clk) - 8'b1;
else
counter <= #1 counter-8'd1;
always @(posedge in_clk or posedge reset)
if(reset)
out_clk <= #1 1'b0;
else if(counter == 0)
out_clk <= #1 ~out_clk;
endmodule // clk_divider
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module clk_divider(input reset, input wire in_clk,output reg out_clk, input [7:0] ratio);
reg [7:0] counter;
// FIXME maybe should use PLL or switch to double edge version
always @(posedge in_clk or posedge reset)
if(reset)
counter <= #1 8'd0;
else if(counter == 0)
counter <= #1 ratio[7:1] + (ratio[0] & out_clk) - 8'b1;
else
counter <= #1 counter-8'd1;
always @(posedge in_clk or posedge reset)
if(reset)
out_clk <= #1 1'b0;
else if(counter == 0)
out_clk <= #1 ~out_clk;
endmodule // clk_divider
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module clk_divider(input reset, input wire in_clk,output reg out_clk, input [7:0] ratio);
reg [7:0] counter;
// FIXME maybe should use PLL or switch to double edge version
always @(posedge in_clk or posedge reset)
if(reset)
counter <= #1 8'd0;
else if(counter == 0)
counter <= #1 ratio[7:1] + (ratio[0] & out_clk) - 8'b1;
else
counter <= #1 counter-8'd1;
always @(posedge in_clk or posedge reset)
if(reset)
out_clk <= #1 1'b0;
else if(counter == 0)
out_clk <= #1 ~out_clk;
endmodule // clk_divider
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module clk_divider(input reset, input wire in_clk,output reg out_clk, input [7:0] ratio);
reg [7:0] counter;
// FIXME maybe should use PLL or switch to double edge version
always @(posedge in_clk or posedge reset)
if(reset)
counter <= #1 8'd0;
else if(counter == 0)
counter <= #1 ratio[7:1] + (ratio[0] & out_clk) - 8'b1;
else
counter <= #1 counter-8'd1;
always @(posedge in_clk or posedge reset)
if(reset)
out_clk <= #1 1'b0;
else if(counter == 0)
out_clk <= #1 ~out_clk;
endmodule // clk_divider
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clk_doubler.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 156 11/29/2004 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module clk_doubler (
inclk0,
c0);
input inclk0;
output c0;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE
|
// Model of FIFO in Altera
module fifo_1c_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 32;
parameter depth = 4096;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [31:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [31:0] q;
output rdfull;
output rdempty;
output [7:0] rdusedw;
output wrfull;
output wrempty;
output [7:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [7:0] rdptr;
reg [7:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
reg [7:0] rdusedw;
reg [7:0] wrusedw;
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
endmodule // fifo_1c_4k
|
// Model of FIFO in Altera
module fifo_1c_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 32;
parameter depth = 4096;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [31:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [31:0] q;
output rdfull;
output rdempty;
output [7:0] rdusedw;
output wrfull;
output wrempty;
output [7:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [7:0] rdptr;
reg [7:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
reg [7:0] rdusedw;
reg [7:0] wrusedw;
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
endmodule // fifo_1c_4k
|
// Model of FIFO in Altera
module fifo_1c_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 32;
parameter depth = 4096;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [31:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [31:0] q;
output rdfull;
output rdempty;
output [7:0] rdusedw;
output wrfull;
output wrempty;
output [7:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [7:0] rdptr;
reg [7:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
reg [7:0] rdusedw;
reg [7:0] wrusedw;
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
endmodule // fifo_1c_4k
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module gen_sync
( input clock,
input reset,
input enable,
input [7:0] rate,
output wire sync );
// parameter width = 8;
reg [7:0] counter;
assign sync = |(((rate+1)>>1)& counter);
always @(posedge clock)
if(reset || ~enable)
counter <= #1 0;
else if(counter == rate)
counter <= #1 0;
else
counter <= #1 counter + 8'd1;
endmodule // gen_sync
|
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