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// file: ClockDivider.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
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// liability) for any loss or damage of any kind or nature
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// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
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// (individually and collectively, "Critical
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___108.000______0.000______50.0______221.150____300.991
// CLK_OUT2_____9.000______0.000______50.0______327.887____300.991
// CLK_OUT3____18.000______0.000______50.0______295.409____300.991
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "ClockDivider,clk_wiz_v5_2_1,{component_name=ClockDivider,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=3,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module ClockDivider
(
// Clock in ports
input clk,
// Clock out ports
output clk_vga,
output clk_cpu,
output clk_2cpu
);
ClockDivider_clk_wiz inst
(
// Clock in ports
.clk(clk),
// Clock out ports
.clk_vga(clk_vga),
.clk_cpu(clk_cpu),
.clk_2cpu(clk_2cpu)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_PP_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__xnor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y , A, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, xnor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_BEHAVIORAL_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_BEHAVIORAL_V
/**
* lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
* keep-alive power rail.
*
* X = (!A | SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
X ,
SLEEP,
A
);
// Module ports
output X ;
input SLEEP;
input A ;
// Module supplies
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , SLEEP );
and and0 (and0_out_X, not0_out, A );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_BEHAVIORAL_V |
(** * MoreLogic: More on Logic in Coq *)
Require Export "Prop".
(* ############################################################ *)
(** * Existential Quantification *)
(** Another critical logical connective is _existential
quantification_. We can express it with the following
definition: *)
Inductive ex (X:Type) (P : X->Prop) : Prop :=
ex_intro : forall (witness:X), P witness -> ex X P.
(** That is, [ex] is a family of propositions indexed by a type [X]
and a property [P] over [X]. In order to give evidence for the
assertion "there exists an [x] for which the property [P] holds"
we must actually name a _witness_ -- a specific value [x] -- and
then give evidence for [P x], i.e., evidence that [x] has the
property [P].
*)
(** *** *)
(** Coq's [Notation] facility can be used to introduce more
familiar notation for writing existentially quantified
propositions, exactly parallel to the built-in syntax for
universally quantified propositions. Instead of writing [ex nat
ev] to express the proposition that there exists some number that
is even, for example, we can write [exists x:nat, ev x]. (It is
not necessary to understand exactly how the [Notation] definition
works.) *)
Notation "'exists' x , p" := (ex _ (fun x => p))
(at level 200, x ident, right associativity) : type_scope.
Notation "'exists' x : X , p" := (ex _ (fun x:X => p))
(at level 200, x ident, right associativity) : type_scope.
(** *** *)
(** We can use the usual set of tactics for
manipulating existentials. For example, to prove an
existential, we can [apply] the constructor [ex_intro]. Since the
premise of [ex_intro] involves a variable ([witness]) that does
not appear in its conclusion, we need to explicitly give its value
when we use [apply]. *)
Example exists_example_1 : exists n, n + (n * n) = 6.
Proof.
apply ex_intro with (witness:=2).
reflexivity. Qed.
(** Note that we have to explicitly give the witness. *)
(** *** *)
(** Or, instead of writing [apply ex_intro with (witness:=e)] all the
time, we can use the convenient shorthand [exists e], which means
the same thing. *)
Example exists_example_1' : exists n, n + (n * n) = 6.
Proof.
exists 2.
reflexivity. Qed.
(** *** *)
(** Conversely, if we have an existential hypothesis in the
context, we can eliminate it with [inversion]. Note the use
of the [as...] pattern to name the variable that Coq
introduces to name the witness value and get evidence that
the hypothesis holds for the witness. (If we don't
explicitly choose one, Coq will just call it [witness], which
makes proofs confusing.) *)
Theorem exists_example_2 : forall n,
(exists m, n = 4 + m) ->
(exists o, n = 2 + o).
Proof.
intros n H.
inversion H as [m Hm].
exists (2 + m).
apply Hm. Qed.
Check beautiful.
Print beautiful.
Print b_sum.
(** Here is another example of how to work with existentials. *)
Lemma exists_example_3 :
exists (n:nat), even n /\ beautiful n.
Proof.
(* WORKED IN CLASS *)
exists 8.
split.
unfold even. simpl. reflexivity.
apply b_sum with (n:=3) (m:=5).
apply b_3. apply b_5.
Qed.
(** **** Exercise: 1 star, optional (english_exists) *)
(** In English, what does the proposition
ex nat (fun n => beautiful (S n))
]]
mean? *)
(* There exists some n of type nat such that the successor
is beautiful
*)
(*
*)
(** **** Exercise: 1 star (dist_not_exists) *)
(** Prove that "[P] holds for all [x]" implies "there is no [x] for
which [P] does not hold." *)
Theorem dist_not_exists : forall (X:Type) (P : X -> Prop),
(forall x, P x) -> ~ (exists x, ~ P x).
Proof.
intros.
unfold not.
intro.
destruct H0 as [L].
apply H0.
apply (H L).
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (not_exists_dist) *)
(** (The other direction of this theorem requires the classical "law
of the excluded middle".) *)
Theorem not_exists_dist :
excluded_middle ->
forall (X:Type) (P : X -> Prop),
~ (exists x, ~ P x) -> (forall x, P x).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (dist_exists_or) *)
(** Prove that existential quantification distributes over
disjunction. *)
Theorem dist_exists_or : forall (X:Type) (P Q : X -> Prop),
(exists x, P x \/ Q x) <-> (exists x, P x) \/ (exists x, Q x).
Proof.
split.
Case "->". intros. destruct H as [x' Hx].
destruct Hx as [HL | HR].
left. exists x'. apply HL.
right. exists x'. apply HR.
Case "<-". intros. destruct H.
destruct H as [x' Hx].
apply (or_introl (P x') (Q x')) in Hx.
exists x'.
apply Hx.
destruct H as [x' Hx].
apply (or_intror (P x') (Q x')) in Hx.
exists x'.
auto.
Qed.
(** [] *)
(* ###################################################### *)
(** * Evidence-Carrying Booleans *)
(** So far we've seen two different forms of equality predicates:
[eq], which produces a [Prop], and the type-specific forms, like
[beq_nat], that produce [boolean] values. The former are more
convenient to reason about, but we've relied on the latter to let
us use equality tests in _computations_. While it is
straightforward to write lemmas (e.g. [beq_nat_true] and
[beq_nat_false]) that connect the two forms, using these lemmas
quickly gets tedious. *)
(** *** *)
(** It turns out that we can get the benefits of both forms at once by
using a construct called [sumbool]. *)
Inductive sumbool (A B : Prop) : Set :=
| left : A -> sumbool A B
| right : B -> sumbool A B.
Notation "{ A } + { B }" := (sumbool A B) : type_scope.
(** Think of [sumbool] as being like the [boolean] type, but instead
of its values being just [true] and [false], they carry _evidence_
of truth or falsity. This means that when we [destruct] them, we
are left with the relevant evidence as a hypothesis -- just as
with [or]. (In fact, the definition of [sumbool] is almost the
same as for [or]. The only difference is that values of [sumbool]
are declared to be in [Set] rather than in [Prop]; this is a
technical distinction that allows us to compute with them.) *)
(** *** *)
(** Here's how we can define a [sumbool] for equality on [nat]s *)
Theorem eq_nat_dec : forall n m : nat, {n = m} + {n <> m}.
Proof.
(* WORKED IN CLASS *)
intros n.
induction n as [|n'].
Case "n = 0".
intros m.
destruct m as [|m'].
SCase "m = 0".
left. reflexivity.
SCase "m = S m'".
right. intros contra. inversion contra.
Case "n = S n'".
intros m.
destruct m as [|m'].
SCase "m = 0".
right. intros contra. inversion contra.
SCase "m = S m'".
destruct IHn' with (m := m') as [eq | neq].
left. apply f_equal. apply eq.
right. intros Heq. inversion Heq as [Heq']. apply neq. apply Heq'.
Defined.
(** Read as a theorem, this says that equality on [nat]s is decidable:
that is, given two [nat] values, we can always produce either
evidence that they are equal or evidence that they are not. Read
computationally, [eq_nat_dec] takes two [nat] values and returns a
[sumbool] constructed with [left] if they are equal and [right] if
they are not; this result can be tested with a [match] or, better,
with an [if-then-else], just like a regular [boolean]. (Notice
that we ended this proof with [Defined] rather than [Qed]. The
only difference this makes is that the proof becomes
_transparent_, meaning that its definition is available when Coq
tries to do reductions, which is important for the computational
interpretation.) *)
(** *** *)
(** Here's a simple example illustrating the advantages of the
[sumbool] form. *)
Definition override' {X: Type} (f: nat->X) (k:nat) (x:X) : nat->X:=
fun (k':nat) => if eq_nat_dec k k' then x else f k'.
Theorem override_same' : forall (X:Type) x1 k1 k2 (f : nat->X),
f k1 = x1 ->
(override' f k1 x1) k2 = f k2.
Proof.
intros X x1 k1 k2 f. intros Hx1.
unfold override'.
destruct (eq_nat_dec k1 k2). (* observe what appears as a hypothesis *)
Case "k1 = k2".
rewrite <- e.
symmetry. apply Hx1.
Case "k1 <> k2".
reflexivity. Qed.
(** Compare this to the more laborious proof (in MoreCoq.v) for the
version of [override] defined using [beq_nat], where we had to use
the auxiliary lemma [beq_nat_true] to convert a fact about
booleans to a Prop. *)
(** **** Exercise: 1 star (override_shadow') *)
Theorem override_shadow' : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
(override' (override' f k1 x2) k1 x1) k2 = (override' f k1 x1) k2.
Proof.
intros.
unfold override'.
destruct (eq_nat_dec k1 k2).
reflexivity.
reflexivity.
Qed.
(** [] *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (all_forallb) *)
(** Inductively define a property [all] of lists, parameterized by a
type [X] and a property [P : X -> Prop], such that [all X P l]
asserts that [P] is true for every element of the list [l]. *)
Inductive all (X : Type) (P : X -> Prop) : list X -> Prop :=
(* FILL IN HERE *)
.
(** Recall the function [forallb], from the exercise
[forall_exists_challenge] in chapter [Poly]: *)
Fixpoint forallb {X : Type} (test : X -> bool) (l : list X) : bool :=
match l with
| [] => true
| x :: l' => andb (test x) (forallb test l')
end.
(** Using the property [all], write down a specification for [forallb],
and prove that it satisfies the specification. Try to make your
specification as precise as possible.
Are there any important properties of the function [forallb] which
are not captured by your specification? *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 4 stars, advanced (filter_challenge) *)
(** One of the main purposes of Coq is to prove that programs match
their specifications. To this end, let's prove that our
definition of [filter] matches a specification. Here is the
specification, written out informally in English.
Suppose we have a set [X], a function [test: X->bool], and a list
[l] of type [list X]. Suppose further that [l] is an "in-order
merge" of two lists, [l1] and [l2], such that every item in [l1]
satisfies [test] and no item in [l2] satisfies test. Then [filter
test l = l1].
A list [l] is an "in-order merge" of [l1] and [l2] if it contains
all the same elements as [l1] and [l2], in the same order as [l1]
and [l2], but possibly interleaved. For example,
[1,4,6,2,3]
is an in-order merge of
[1,6,2]
and
[4,3].
Your job is to translate this specification into a Coq theorem and
prove it. (Hint: You'll need to begin by defining what it means
for one list to be a merge of two others. Do this with an
inductive relation, not a [Fixpoint].) *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 5 stars, advanced, optional (filter_challenge_2) *)
(** A different way to formally characterize the behavior of [filter]
goes like this: Among all subsequences of [l] with the property
that [test] evaluates to [true] on all their members, [filter test
l] is the longest. Express this claim formally and prove it. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 4 stars, advanced (no_repeats) *)
(** The following inductively defined proposition... *)
Inductive appears_in {X:Type} (a:X) : list X -> Prop :=
| ai_here : forall l, appears_in a (a::l)
| ai_later : forall b l, appears_in a l -> appears_in a (b::l).
(** ...gives us a precise way of saying that a value [a] appears at
least once as a member of a list [l].
Here's a pair of warm-ups about [appears_in].
*)
Lemma appears_in_app : forall (X:Type) (xs ys : list X) (x:X),
appears_in x (xs ++ ys) -> appears_in x xs \/ appears_in x ys.
Proof.
(* FILL IN HERE *) Admitted.
Lemma app_appears_in : forall (X:Type) (xs ys : list X) (x:X),
appears_in x xs \/ appears_in x ys -> appears_in x (xs ++ ys).
Proof.
(* FILL IN HERE *) Admitted.
(** Now use [appears_in] to define a proposition [disjoint X l1 l2],
which should be provable exactly when [l1] and [l2] are
lists (with elements of type X) that have no elements in common. *)
(* FILL IN HERE *)
(** Next, use [appears_in] to define an inductive proposition
[no_repeats X l], which should be provable exactly when [l] is a
list (with elements of type [X]) where every member is different
from every other. For example, [no_repeats nat [1,2,3,4]] and
[no_repeats bool []] should be provable, while [no_repeats nat
[1,2,1]] and [no_repeats bool [true,true]] should not be. *)
(* FILL IN HERE *)
(** Finally, state and prove one or more interesting theorems relating
[disjoint], [no_repeats] and [++] (list append). *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars (nostutter) *)
(** Formulating inductive definitions of predicates is an important
skill you'll need in this course. Try to solve this exercise
without any help at all.
We say that a list of numbers "stutters" if it repeats the same
number consecutively. The predicate "[nostutter mylist]" means
that [mylist] does not stutter. Formulate an inductive definition
for [nostutter]. (This is different from the [no_repeats]
predicate in the exercise above; the sequence [1;4;1] repeats but
does not stutter.) *)
Inductive nostutter: list nat -> Prop :=
(* FILL IN HERE *)
.
(** Make sure each of these tests succeeds, but you are free
to change the proof if the given one doesn't work for you.
Your definition might be different from mine and still correct,
in which case the examples might need a different proof.
The suggested proofs for the examples (in comments) use a number
of tactics we haven't talked about, to try to make them robust
with respect to different possible ways of defining [nostutter].
You should be able to just uncomment and use them as-is, but if
you prefer you can also prove each example with more basic
tactics. *)
Example test_nostutter_1: nostutter [3;1;4;1;5;6].
(* FILL IN HERE *) Admitted.
(*
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
*)
Example test_nostutter_2: nostutter [].
(* FILL IN HERE *) Admitted.
(*
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
*)
Example test_nostutter_3: nostutter [5].
(* FILL IN HERE *) Admitted.
(*
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
*)
Example test_nostutter_4: not (nostutter [3;1;1;4]).
(* FILL IN HERE *) Admitted.
(*
Proof. intro.
repeat match goal with
h: nostutter _ |- _ => inversion h; clear h; subst
end.
contradiction H1; auto. Qed.
*)
(** [] *)
(** **** Exercise: 4 stars, advanced (pigeonhole principle) *)
(** The "pigeonhole principle" states a basic fact about counting:
if you distribute more than [n] items into [n] pigeonholes, some
pigeonhole must contain at least two items. As is often the case,
this apparently trivial fact about numbers requires non-trivial
machinery to prove, but we now have enough... *)
(** First a pair of useful lemmas (we already proved these for lists
of naturals, but not for arbitrary lists). *)
Lemma app_length : forall (X:Type) (l1 l2 : list X),
length (l1 ++ l2) = length l1 + length l2.
Proof.
(* FILL IN HERE *) Admitted.
Lemma appears_in_app_split : forall (X:Type) (x:X) (l:list X),
appears_in x l ->
exists l1, exists l2, l = l1 ++ (x::l2).
Proof.
(* FILL IN HERE *) Admitted.
(** Now define a predicate [repeats] (analogous to [no_repeats] in the
exercise above), such that [repeats X l] asserts that [l] contains
at least one repeated element (of type [X]). *)
Inductive repeats {X:Type} : list X -> Prop :=
(* FILL IN HERE *)
.
(** Now here's a way to formalize the pigeonhole principle. List [l2]
represents a list of pigeonhole labels, and list [l1] represents
the labels assigned to a list of items: if there are more items
than labels, at least two items must have the same label. This
proof is much easier if you use the [excluded_middle] hypothesis
to show that [appears_in] is decidable, i.e. [forall x
l, (appears_in x l) \/ ~ (appears_in x l)]. However, it is also
possible to make the proof go through _without_ assuming that
[appears_in] is decidable; if you can manage to do this, you will
not need the [excluded_middle] hypothesis. *)
Theorem pigeonhole_principle: forall (X:Type) (l1 l2:list X),
excluded_middle ->
(forall x, appears_in x l1 -> appears_in x l2) ->
length l2 < length l1 ->
repeats l1.
Proof.
intros X l1. induction l1 as [|x l1'].
(* FILL IN HERE *) Admitted.
(** [] *)
(* FILL IN HERE *)
(** $Date: 2014-12-31 16:01:37 -0500 (Wed, 31 Dec 2014) $ *)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DFXTP_BEHAVIORAL_PP_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_lp__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXTP_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAHCIN_BLACKBOX_V
`define SKY130_FD_SC_LP__FAHCIN_BLACKBOX_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__fahcin (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAHCIN_BLACKBOX_V
|
module wait_time_module (reset, work, clk, wait_time);
//counting the wait_time
input clk,work,reset;
output [11:0] wait_time;
reg [11:0] wait_time;
reg [5:0] i;
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
wait_time <= 0;
i <= 0;
end
else if (work == 0)
begin
//if(i >= 59)
if(i >= 4)
begin
wait_time <= wait_time +1;
i <= 0;
end
else i <= i+1;
end
end
/*always @ (posedge clk)
begin
if(!reset&!work)
begin
if(i >= 1)
//if(i >= 59)
begin
wait_time <= BCD_counter(wait_time);
i <= 0;
end
else i <= i+1;
end
else
begin
wait_time <= 0;
i <= 0;
end
end*/
/*
assign rw = reset||work;
always @ (posedge clk or negedge rw)begin
if(!rw)begin
wait_time <= 0;
i <= 0;
end
else
begin
case({reset,work})
2'b00:begin
//if(i >= 59)
if(i >= 1)
begin
wait_time <= BCD_counter(wait_time);
i <= 0;
end
else
i <= i+1;
end
default:
begin
wait_time <= 0;
i <= 0;
end
endcase
end
end
*/
/*
assign rw = reset||work;
always @ (posedge clk or posedge rw)
begin
if(rw)
begin
wait_time <= 0;
i <= 0;
end
else
begin
case({reset,work})
2'b00:begin
//if(i >= 59)
if(i >= 1)
begin
wait_time <= BCD_counter(wait_time);
i <= 0;
end
else i <= i+1;
end
default:
begin
wait_time <= 0;
i <= 0;
end
endcase
end
end*/
endmodule
|
`include "../define.v"
`include "../regfile.v"
module regfile_tb;
reg clk, rst;
reg[`RegAddrWidth-1:0] waddr;
reg[`RegDataWidth-1:0] wdata;
reg we;
// read port1
reg re1;
reg[`RegAddrWidth-1:0] raddr_1;
wire[`RegDataWidth-1:0] rdata_1;
// read port2
reg re2;
reg[`RegAddrWidth-1:0] raddr_2;
wire[`RegDataWidth-1:0] rdata_2;
regfile regs(clk, rst, waddr, wdata, we, re1, raddr_1, rdata_1, re2, raddr_2, rdata_2);
initial begin
clk = 1;
forever #1 clk = ~clk;
end
initial begin : test
integer i;
$dumpfile("vcd/regfile_tb.vcd");
$dumpvars;
$readmemb("testData/data.data", regs.regs);
rst = ~`RstEnable;
re1 = `ReadEnable;
for (i = 0; i < `RegNum; i = i + 1) begin
#1 raddr_1 = i;
#1 $display("now reading from read port 1: %32b", rdata_1);
end
re1 = ~`ReadEnable;
$display("==============================================================");
// for (i = 0; i < `RegNum; i = i + 1) begin
// #1 raddr_2 = i;
// #1 $display("now reading from read port 2: %32b", rdata_2);
// end
// $display("==============================================================");
for (i = 0; i < `RegNum; i = i + 1) begin
@(posedge clk) begin
we = `WriteEnable;
waddr = i;
wdata = i;
#1.5 we = ~`WriteEnable;
end
$display("now writting: %32b", wdata);
end
$display("==============================================================");
re2 = `ReadEnable;
for (i = 0; i < `RegNum; i = i + 1) begin
#1 raddr_2 = i;
#1 $display("now reading %2d", i, " from read port 2: %32b", rdata_2);
end
re2 = ~`ReadEnable;
$display("==============================================================");
rst = ~rst;
re1 = `ReadEnable;
for (i = 0; i < `RegNum; i = i + 1) begin
#1 raddr_1 = i;
#1 $display("now reading from read port 1: %32b", rdata_1);
end
re1 = ~`ReadEnable;
$finish;
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__NOR4B_FUNCTIONAL_PP_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__nor4b (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y , A, B, C, not0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4B_FUNCTIONAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/05 22:54:09
// Design Name:
// Module Name: flow_led_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module flow_led_tb(
);
parameter COUNT = 1000; // number of T
parameter DELAY = 5; // T = 10ns, f = 100MHz
reg clk_src, reset, M;
reg [4:0] clk_sel;
wire [3:0] state;
integer i;
flow_led DUT (.clk_src(clk_src), .reset(reset), .clk_sel(clk_sel), .M(M), .state(state));
initial begin
#(COUNT*DELAY) $finish;
end
initial begin
clk_src = 0;
for(i = 0; i < COUNT; i = i + 1) begin
#DELAY clk_src = ~clk_src;
end
end
initial begin
M = 1;
#(COUNT*DELAY/2) M = 0;
end
initial begin
reset = 0;
#DELAY reset = 1;
#DELAY reset = 0;
#((COUNT-5)*DELAY/2) reset = 0;
#DELAY reset = 1;
#DELAY reset = 0;
end
initial begin
clk_sel = 5'b0000;
#(COUNT*DELAY/5) clk_sel = clk_sel + 1;
#(COUNT*DELAY/5) clk_sel = clk_sel + 1;
#(COUNT*DELAY/5) clk_sel = clk_sel + 1;
#(COUNT*DELAY/5) clk_sel = clk_sel + 1;
#(COUNT*DELAY/5) clk_sel = clk_sel + 1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKINV_2_V
`define SKY130_FD_SC_MS__CLKINV_2_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkinv_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkinv_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKINV_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DLATCH_P_TB_V
`define SKY130_FD_SC_HVL__UDP_DLATCH_P_TB_V
/**
* udp_dlatch$P: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__udp_dlatch_p.v"
module top();
// Inputs are registered
reg D;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
#20 D = 1'b0;
#40 D = 1'b1;
#60 D = 1'b0;
#80 D = 1'b1;
#100 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hvl__udp_dlatch$P dut (.D(D), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DLATCH_P_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD1_BEHAVIORAL_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD1_BEHAVIORAL_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv5sd1 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD1_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21AI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__O21AI_BEHAVIORAL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o21ai (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21AI_BEHAVIORAL_V |
module mojo_top(
// 50MHz clock input
input clk,
// Input from reset button (active low)
input rst_n,
input inin,
// Outputs to the 8 onboard LEDs
output[7:0]data,
output[7:0]led
// cclk input from AVR, high when AVR is ready
/*input cclk,
// AVR SPI connections
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
// AVR ADC channel select
output [3:0] spi_channel,
// Serial connections
input avr_tx, // AVR Tx => FPGA Rx
output avr_rx, // AVR Rx => FPGA Tx
input avr_rx_busy // AVR Rx buffer full
*/ );
wire rst = ~rst_n; // make reset active high
/*
// these signals should be high-z when not used
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
*/
wire I_STA;
wire SETWRITE;
wire CLRWRITE;
wire WRITE;
wire [15:0] MD_OUT;
wire [15:0] AC_OUT;
wire [15:0] MMO;
assign led = MMO[7:0];
dunc16 myDunc16 (
.CLK(clk),
.ININ(inin),
.I_STA( I_STA ),
.SETWRITE( SETWRITE ),
.CLRWRITE( CLRWRITE ),
.WRITE(WRITE),
.MD_OUT( MD_OUT ),
.AC_OUT( AC_OUT ),
.MMO( MMO ),
.RESET(rst)
);
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUX2I_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__MUX2I_PP_SYMBOL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__mux2i (
//# {{data|Data Signals}}
input A0 ,
input A1 ,
output Y ,
//# {{control|Control Signals}}
input S ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUX2I_PP_SYMBOL_V
|
//
// Written by Synplify
// Product Version "H-2013.03-SP1-1 "
// Program "Synplify Premier", Mapper "map201303sp1_1rc, Build 007R"
// Thu Feb 5 15:49:20 2015
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\/opt/tools/synopsys/fpga/H-2013.03-SP1/lib/xilinx/unisim_m10i.v "
// file 2 "\/opt/tools/synopsys/fpga/H-2013.03-SP1/lib/xilinx/unisim.v "
// file 3 "\/opt/tools/synopsys/fpga/H-2013.03-SP1/lib/vlog/umr_capim.v "
// file 4 "\/opt/tools/synopsys/fpga/H-2013.03-SP1/lib/vlog/scemi_objects.v "
// file 5 "\/opt/tools/synopsys/fpga/H-2013.03-SP1/lib/vlog/scemi_pipes.svh "
// file 6 "\/opt/tools/synopsys/fpga/H-2013.03-SP1/lib/vlog/hypermods.v "
// file 7 "\/home/david/projects/faultify_github/faultify/hardware/testcases/DCT4/src/dct4.v "
// file 8 "\/home/david/projects/faultify_github/faultify/hardware/testcases/DCT4/src/dct_coefs.v "
// file 9 "\/home/david/projects/faultify_github/faultify/hardware/testcases/DCT4/fpga_syn/rev_1/syntmp/multadd.v "
// file 10 "\/home/david/projects/faultify_github/faultify/hardware/testcases/DCT4/fpga_syn/rev_1/syntmp/unisim.v "
`timescale 100 ps/100 ps
module dct4 (
CK,
inp,
outp,
outi
)
;
/* Synopsys
.origName=dct4
.langParams="in out csize"
in=8
out=20
csize=12
*/
input CK ;
input [63:0] inp ;
output [19:0] outp ;
output [2:0] outi ;
wire CK ;
wire [2:0] i;
wire [6:3] t5_2;
wire [8:7] t5_1;
wire [9:0] t5_5;
wire [9:0] t5_3;
wire [10:3] t5_4;
wire [19:0] \_l3.un17_t1 ;
wire [19:0] un16_t1_1_1;
wire [19:0] un16_t1_1_0_2;
wire [47:20] P_uc;
wire [29:0] ACOUT;
wire [17:0] BCOUT;
wire [3:0] CARRYOUT;
wire [47:20] P_uc_0;
wire [29:0] ACOUT_0;
wire [17:0] BCOUT_0;
wire [3:0] CARRYOUT_0;
wire [47:20] P_uc_1;
wire [29:0] ACOUT_1;
wire [17:0] BCOUT_1;
wire [3:0] CARRYOUT_1;
wire [47:0] PCOUT_1;
wire [47:20] P_uc_2;
wire [29:0] ACOUT_2;
wire [17:0] BCOUT_2;
wire [3:0] CARRYOUT_2;
wire [19:0] \_l3.un17_t1_0 ;
wire [47:20] P_uc_2_0;
wire [19:0] un16_t1_1_0_2_0;
wire [47:20] P_uc_3;
wire [19:0] un16_t1_1_1_0;
wire [47:20] P_uc_0_0;
wire [8:7] t5_1_i;
wire [0:0] i_i;
wire [0:0] t5_3_i;
wire [2:0] i_fast;
wire VCC ;
wire GND ;
wire un1_i_8_0 ;
wire CARRYCASCOUT ;
wire OVERFLOW ;
wire MULTSIGNOUT ;
wire PATTERNBDETECT ;
wire PATTERNDETECT ;
wire UNDERFLOW ;
wire CARRYCASCOUT_0 ;
wire OVERFLOW_0 ;
wire MULTSIGNOUT_0 ;
wire PATTERNBDETECT_0 ;
wire PATTERNDETECT_0 ;
wire UNDERFLOW_0 ;
wire CARRYCASCOUT_1 ;
wire OVERFLOW_1 ;
wire MULTSIGNOUT_1 ;
wire PATTERNBDETECT_1 ;
wire PATTERNDETECT_1 ;
wire UNDERFLOW_1 ;
wire CARRYCASCOUT_2 ;
wire OVERFLOW_2 ;
wire MULTSIGNOUT_2 ;
wire PATTERNBDETECT_2 ;
wire PATTERNDETECT_2 ;
wire UNDERFLOW_2 ;
wire N_101_i ;
wire N_57_i ;
wire N_60_i ;
wire N_62_i ;
wire N_73_i ;
wire un1_i_8_1_i ;
wire \t5_4_6_0_.N_4_i ;
wire \t5_4_6_0_.N_5_i ;
wire \t5_4_6_0_.N_7_i ;
wire \t5_4_6_0_.N_10_i ;
wire \t5_5_9_.N_5_i ;
wire \t5_4_10_8_.N_3_i ;
wire \t5_4_10_8_.N_7_mux_i ;
wire \t5_3_10_0_.N_9_i ;
wire N_71_i_i ;
wire \t5_3_10_0_.N_14_i ;
wire \t5_3_10_0_.N_17_i ;
wire \t5_5_3_2_.N_4_i ;
wire un1_i_1_i ;
wire N_87_i ;
wire i_1_rep1 ;
wire i_1_rep2 ;
wire i_2_rep1 ;
wire i_0_rep1 ;
wire \t5_4_6_0_.SUM2 ;
wire \t5_4_6_0_.SUM2_fast ;
wire \t5_4_6_0_.SUM2_rep1 ;
wire \t5_4_6_0_.SUM1 ;
wire \t5_4_6_0_.SUM1_fast ;
wire \t5_4_6_0_.SUM1_rep1 ;
wire \t5_4_6_0_.SUM1_rep2 ;
GND GND_cZ (
.G(GND)
);
VCC VCC_cZ (
.P(VCC)
);
// @7:43
FD \i_Z[2] (
.Q(i[2]),
.D(\t5_4_6_0_.SUM2 ),
.C(CK)
);
// @7:43
FD \i_Z[1] (
.Q(i[1]),
.D(\t5_4_6_0_.SUM1 ),
.C(CK)
);
// @7:43
FD \i_fast_Z[1] (
.Q(i_fast[1]),
.D(\t5_4_6_0_.SUM1_fast ),
.C(CK)
);
// @7:43
FD i_1_rep1_Z (
.Q(i_1_rep1),
.D(\t5_4_6_0_.SUM1_rep1 ),
.C(CK)
);
// @7:43
FD i_1_rep2_Z (
.Q(i_1_rep2),
.D(\t5_4_6_0_.SUM1_rep2 ),
.C(CK)
);
// @7:43
FD \i_fast_Z[2] (
.Q(i_fast[2]),
.D(\t5_4_6_0_.SUM2_fast ),
.C(CK)
);
// @7:43
FD i_2_rep1_Z (
.Q(i_2_rep1),
.D(\t5_4_6_0_.SUM2_rep1 ),
.C(CK)
);
// @7:86
LUT2 \t5_4_6_0_.SUM1_rep2_cZ (
.I0(i_1_rep2),
.I1(i[0]),
.O(\t5_4_6_0_.SUM1_rep2 )
);
defparam \t5_4_6_0_.SUM1_rep2_cZ .INIT=4'h6;
// @7:86
LUT2 \t5_4_6_0_.SUM1_rep1_cZ (
.I0(i_1_rep1),
.I1(i[0]),
.O(\t5_4_6_0_.SUM1_rep1 )
);
defparam \t5_4_6_0_.SUM1_rep1_cZ .INIT=4'h6;
// @7:86
LUT2 \t5_4_6_0_.SUM1_fast_cZ (
.I0(i_fast[1]),
.I1(i[0]),
.O(\t5_4_6_0_.SUM1_fast )
);
defparam \t5_4_6_0_.SUM1_fast_cZ .INIT=4'h6;
// @7:86
LUT2 \t5_4_6_0_.SUM1_cZ (
.I0(i[1]),
.I1(i[0]),
.O(\t5_4_6_0_.SUM1 )
);
defparam \t5_4_6_0_.SUM1_cZ .INIT=4'h6;
// @7:79
INV \i_RNIHB76[0] (
.I(i[0]),
.O(i_i[0])
);
// @7:43
FD \outi_Z[0] (
.Q(outi[0]),
.D(i[0]),
.C(CK)
);
// @7:43
FD \outi_Z[1] (
.Q(outi[1]),
.D(i[1]),
.C(CK)
);
// @7:43
FD \outi_Z[2] (
.Q(outi[2]),
.D(i[2]),
.C(CK)
);
// @7:43
FD \i_Z[0] (
.Q(i[0]),
.D(i_i[0]),
.C(CK)
);
// @7:43
FD \i_fast_Z[0] (
.Q(i_fast[0]),
.D(i_i[0]),
.C(CK)
);
// @7:43
FD i_0_rep1_Z (
.Q(i_0_rep1),
.D(i_i[0]),
.C(CK)
);
// @7:75
LUT3 un1_i_8 (
.I0(i_0_rep1),
.I1(i_1_rep1),
.I2(i_2_rep1),
.O(un1_i_8_0)
);
defparam un1_i_8.INIT=8'h40;
// @7:75
LUT3 \t5_5_0_.m2 (
.I0(i_fast[0]),
.I1(i_fast[1]),
.I2(i_fast[2]),
.O(t5_5[0])
);
defparam \t5_5_0_.m2 .INIT=8'h62;
// @7:75
LUT3 \t5_5_3_2_.m4 (
.I0(i_0_rep1),
.I1(i_1_rep1),
.I2(i_2_rep1),
.O(t5_5[3])
);
defparam \t5_5_3_2_.m4 .INIT=8'h4C;
// @7:75
LUT3 \t5_2_i_a2[7] (
.I0(i_fast[0]),
.I1(i_fast[1]),
.I2(i_fast[2]),
.O(t5_1[7])
);
defparam \t5_2_i_a2[7] .INIT=8'h28;
// @7:80
LUT3 \i_fast_RNITRJI_0[0] (
.I0(i_fast[0]),
.I1(i_fast[1]),
.I2(i_fast[2]),
.O(N_87_i)
);
defparam \i_fast_RNITRJI_0[0] .INIT=8'h1B;
// @7:75
LUT3 \t5_5_9_.m3 (
.I0(i_0_rep1),
.I1(i_1_rep1),
.I2(i_2_rep1),
.O(t5_5[9])
);
defparam \t5_5_9_.m3 .INIT=8'h71;
// @7:79
LUT3 \i_fast_RNITRJI[0] (
.I0(i_fast[0]),
.I1(i_fast[1]),
.I2(i_fast[2]),
.O(N_62_i)
);
defparam \i_fast_RNITRJI[0] .INIT=8'h26;
// @7:80
LUT3 \t5_4_10_8_.N_7_mux_i_cZ (
.I0(i[2]),
.I1(i[1]),
.I2(i[0]),
.O(\t5_4_10_8_.N_7_mux_i )
);
defparam \t5_4_10_8_.N_7_mux_i_cZ .INIT=8'h9D;
// @7:80
LUT3 i_1_rep1_RNIGHRL (
.I0(i_0_rep1),
.I1(i_1_rep1),
.I2(i_2_rep1),
.O(un1_i_1_i)
);
defparam i_1_rep1_RNIGHRL.INIT=8'h7F;
// @7:80
LUT3 \t5_3_10_0_.t5_3_i[0] (
.I0(i_fast[0]),
.I1(i_fast[1]),
.I2(i_fast[2]),
.O(t5_3_i[0])
);
defparam \t5_3_10_0_.t5_3_i[0] .INIT=8'hF1;
// @7:80
LUT3 \t5_5_3_2_.N_4_i_cZ (
.I0(i_0_rep1),
.I1(i_1_rep1),
.I2(i_2_rep1),
.O(\t5_5_3_2_.N_4_i )
);
defparam \t5_5_3_2_.N_4_i_cZ .INIT=8'h97;
// @7:79
DSP48E1 \un16_t1_1_0_0[19:0] (
.ACOUT(ACOUT[29:0]),
.BCOUT(BCOUT[17:0]),
.CARRYCASCOUT(CARRYCASCOUT),
.CARRYOUT(CARRYOUT[3:0]),
.MULTSIGNOUT(MULTSIGNOUT),
.OVERFLOW(OVERFLOW),
.P({P_uc[47:20], un16_t1_1_0_2[19:0]}),
.PATTERNBDETECT(PATTERNBDETECT),
.PATTERNDETECT(PATTERNDETECT),
.PCOUT({P_uc_3[47:20], un16_t1_1_0_2_0[19:0]}),
.UNDERFLOW(UNDERFLOW),
.A({inp[7], inp[7], inp[7], inp[7], inp[7], inp[7], inp[7], inp[7], inp[7], inp[7], inp[7], inp[7], inp[7], inp[7], inp[7], inp[7], inp[7], inp[7], inp[7], inp[7], inp[7], inp[7], inp[7:0]}),
.ACIN({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.ALUMODE({GND, GND, GND, GND}),
.B({GND, GND, GND, GND, GND, GND, GND, GND, un1_i_8_1_i, N_73_i, t5_1_i[7], t5_2[6], N_62_i, N_60_i, t5_2[3], N_57_i, i[1], N_101_i}),
.BCIN({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.C({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.CARRYCASCIN(GND),
.CARRYIN(GND),
.CARRYINSEL({GND, GND, GND}),
.CEA1(GND),
.CEA2(GND),
.CEAD(GND),
.CEALUMODE(GND),
.CEB1(GND),
.CEB2(GND),
.CEC(GND),
.CECARRYIN(GND),
.CECTRL(GND),
.CED(GND),
.CEINMODE(VCC),
.CEM(GND),
.CEP(GND),
.CLK(CK),
.D({inp[63], inp[63], inp[63], inp[63], inp[63], inp[63], inp[63], inp[63], inp[63], inp[63], inp[63], inp[63], inp[63], inp[63], inp[63], inp[63], inp[63], inp[63:56]}),
.INMODE({GND, i_i[0], VCC, GND, GND}),
.MULTSIGNIN(GND),
.OPMODE({GND, GND, VCC, GND, VCC, GND, VCC}),
.PCIN({P_uc_2_0[47:20], \_l3.un17_t1_0 [19:0]}),
.RSTA(GND),
.RSTALLCARRYIN(GND),
.RSTALUMODE(GND),
.RSTB(GND),
.RSTC(GND),
.RSTCTRL(GND),
.RSTD(GND),
.RSTINMODE(GND),
.RSTM(GND),
.RSTP(GND)
);
defparam \un16_t1_1_0_0[19:0] .ACASCREG=0;
defparam \un16_t1_1_0_0[19:0] .ADREG=0;
defparam \un16_t1_1_0_0[19:0] .ALUMODEREG=0;
defparam \un16_t1_1_0_0[19:0] .AREG=0;
defparam \un16_t1_1_0_0[19:0] .AUTORESET_PATDET="NO_RESET";
defparam \un16_t1_1_0_0[19:0] .A_INPUT="DIRECT";
defparam \un16_t1_1_0_0[19:0] .BCASCREG=0;
defparam \un16_t1_1_0_0[19:0] .BREG=0;
defparam \un16_t1_1_0_0[19:0] .B_INPUT="DIRECT";
defparam \un16_t1_1_0_0[19:0] .CARRYINREG=0;
defparam \un16_t1_1_0_0[19:0] .CARRYINSELREG=0;
defparam \un16_t1_1_0_0[19:0] .CREG=1;
defparam \un16_t1_1_0_0[19:0] .DREG=0;
defparam \un16_t1_1_0_0[19:0] .INMODEREG=1;
defparam \un16_t1_1_0_0[19:0] .MREG=0;
defparam \un16_t1_1_0_0[19:0] .OPMODEREG=0;
defparam \un16_t1_1_0_0[19:0] .PREG=0;
defparam \un16_t1_1_0_0[19:0] .USE_DPORT="TRUE";
defparam \un16_t1_1_0_0[19:0] .USE_MULT="MULTIPLY";
defparam \un16_t1_1_0_0[19:0] .USE_SIMD="ONE48";
// @7:80
DSP48E1 \un16_t1_1_0_2[19:0] (
.ACOUT(ACOUT_0[29:0]),
.BCOUT(BCOUT_0[17:0]),
.CARRYCASCOUT(CARRYCASCOUT_0),
.CARRYOUT(CARRYOUT_0[3:0]),
.MULTSIGNOUT(MULTSIGNOUT_0),
.OVERFLOW(OVERFLOW_0),
.P({P_uc_0[47:20], un16_t1_1_1[19:0]}),
.PATTERNBDETECT(PATTERNBDETECT_0),
.PATTERNDETECT(PATTERNDETECT_0),
.PCOUT({P_uc_0_0[47:20], un16_t1_1_1_0[19:0]}),
.UNDERFLOW(UNDERFLOW_0),
.A({inp[23], inp[23], inp[23], inp[23], inp[23], inp[23], inp[23], inp[23], inp[23], inp[23], inp[23], inp[23], inp[23], inp[23], inp[23], inp[23], inp[23], inp[23], inp[23], inp[23], inp[23], inp[23], inp[23:16]}),
.ACIN({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.ALUMODE({GND, GND, GND, GND}),
.B({t5_4[10], t5_4[10], t5_4[10], t5_4[10], t5_4[10], t5_4[10], t5_4[10], t5_4[10], \t5_4_10_8_.N_7_mux_i , \t5_4_10_8_.N_3_i , t5_1[8], \t5_5_9_.N_5_i , t5_4[5], \t5_4_6_0_.N_10_i , t5_4[3], \t5_4_6_0_.N_7_i , \t5_4_6_0_.N_5_i , \t5_4_6_0_.N_4_i }),
.BCIN({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.C({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.CARRYCASCIN(GND),
.CARRYIN(GND),
.CARRYINSEL({GND, GND, GND}),
.CEA1(GND),
.CEA2(GND),
.CEAD(GND),
.CEALUMODE(GND),
.CEB1(GND),
.CEB2(GND),
.CEC(GND),
.CECARRYIN(GND),
.CECTRL(GND),
.CED(GND),
.CEINMODE(VCC),
.CEM(GND),
.CEP(GND),
.CLK(CK),
.D({inp[47], inp[47], inp[47], inp[47], inp[47], inp[47], inp[47], inp[47], inp[47], inp[47], inp[47], inp[47], inp[47], inp[47], inp[47], inp[47], inp[47], inp[47:40]}),
.INMODE({GND, i_i[0], VCC, GND, GND}),
.MULTSIGNIN(GND),
.OPMODE({GND, GND, VCC, GND, VCC, GND, VCC}),
.PCIN({P_uc_3[47:20], un16_t1_1_0_2_0[19:0]}),
.RSTA(GND),
.RSTALLCARRYIN(GND),
.RSTALUMODE(GND),
.RSTB(GND),
.RSTC(GND),
.RSTCTRL(GND),
.RSTD(GND),
.RSTINMODE(GND),
.RSTM(GND),
.RSTP(GND)
);
defparam \un16_t1_1_0_2[19:0] .ACASCREG=0;
defparam \un16_t1_1_0_2[19:0] .ADREG=0;
defparam \un16_t1_1_0_2[19:0] .ALUMODEREG=0;
defparam \un16_t1_1_0_2[19:0] .AREG=0;
defparam \un16_t1_1_0_2[19:0] .AUTORESET_PATDET="NO_RESET";
defparam \un16_t1_1_0_2[19:0] .A_INPUT="DIRECT";
defparam \un16_t1_1_0_2[19:0] .BCASCREG=0;
defparam \un16_t1_1_0_2[19:0] .BREG=0;
defparam \un16_t1_1_0_2[19:0] .B_INPUT="DIRECT";
defparam \un16_t1_1_0_2[19:0] .CARRYINREG=0;
defparam \un16_t1_1_0_2[19:0] .CARRYINSELREG=0;
defparam \un16_t1_1_0_2[19:0] .CREG=1;
defparam \un16_t1_1_0_2[19:0] .DREG=0;
defparam \un16_t1_1_0_2[19:0] .INMODEREG=1;
defparam \un16_t1_1_0_2[19:0] .MREG=0;
defparam \un16_t1_1_0_2[19:0] .OPMODEREG=0;
defparam \un16_t1_1_0_2[19:0] .PREG=0;
defparam \un16_t1_1_0_2[19:0] .USE_DPORT="TRUE";
defparam \un16_t1_1_0_2[19:0] .USE_MULT="MULTIPLY";
defparam \un16_t1_1_0_2[19:0] .USE_SIMD="ONE48";
// @7:80
DSP48E1 \un16_t1_1_1[19:0] (
.ACOUT(ACOUT_1[29:0]),
.BCOUT(BCOUT_1[17:0]),
.CARRYCASCOUT(CARRYCASCOUT_1),
.CARRYOUT(CARRYOUT_1[3:0]),
.MULTSIGNOUT(MULTSIGNOUT_1),
.OVERFLOW(OVERFLOW_1),
.P({P_uc_1[47:20], outp[19:0]}),
.PATTERNBDETECT(PATTERNBDETECT_1),
.PATTERNDETECT(PATTERNDETECT_1),
.PCOUT(PCOUT_1[47:0]),
.UNDERFLOW(UNDERFLOW_1),
.A({inp[15], inp[15], inp[15], inp[15], inp[15], inp[15], inp[15], inp[15], inp[15], inp[15], inp[15], inp[15], inp[15], inp[15], inp[15], inp[15], inp[15], inp[15], inp[15], inp[15], inp[15], inp[15], inp[15:8]}),
.ACIN({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.ALUMODE({GND, GND, GND, GND}),
.B({\t5_3_10_0_.N_17_i , \t5_3_10_0_.N_17_i , \t5_3_10_0_.N_17_i , \t5_3_10_0_.N_17_i , \t5_3_10_0_.N_17_i , \t5_3_10_0_.N_17_i , \t5_3_10_0_.N_17_i , \t5_3_10_0_.N_17_i , t5_3[9], t5_1_i[8], \t5_3_10_0_.N_14_i , N_71_i_i, t5_3[5:4], \t5_3_10_0_.N_9_i , t5_3[2:0]}),
.BCIN({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.C({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.CARRYCASCIN(GND),
.CARRYIN(GND),
.CARRYINSEL({GND, GND, GND}),
.CEA1(GND),
.CEA2(GND),
.CEAD(GND),
.CEALUMODE(GND),
.CEB1(GND),
.CEB2(GND),
.CEC(GND),
.CECARRYIN(GND),
.CECTRL(GND),
.CED(GND),
.CEINMODE(VCC),
.CEM(GND),
.CEP(VCC),
.CLK(CK),
.D({inp[55], inp[55], inp[55], inp[55], inp[55], inp[55], inp[55], inp[55], inp[55], inp[55], inp[55], inp[55], inp[55], inp[55], inp[55], inp[55], inp[55], inp[55:48]}),
.INMODE({GND, i_i[0], VCC, GND, GND}),
.MULTSIGNIN(GND),
.OPMODE({GND, GND, VCC, GND, VCC, GND, VCC}),
.PCIN({P_uc_0_0[47:20], un16_t1_1_1_0[19:0]}),
.RSTA(GND),
.RSTALLCARRYIN(GND),
.RSTALUMODE(GND),
.RSTB(GND),
.RSTC(GND),
.RSTCTRL(GND),
.RSTD(GND),
.RSTINMODE(GND),
.RSTM(GND),
.RSTP(GND)
);
defparam \un16_t1_1_1[19:0] .ACASCREG=0;
defparam \un16_t1_1_1[19:0] .ADREG=0;
defparam \un16_t1_1_1[19:0] .ALUMODEREG=0;
defparam \un16_t1_1_1[19:0] .AREG=0;
defparam \un16_t1_1_1[19:0] .AUTORESET_PATDET="NO_RESET";
defparam \un16_t1_1_1[19:0] .A_INPUT="DIRECT";
defparam \un16_t1_1_1[19:0] .BCASCREG=0;
defparam \un16_t1_1_1[19:0] .BREG=0;
defparam \un16_t1_1_1[19:0] .B_INPUT="DIRECT";
defparam \un16_t1_1_1[19:0] .CARRYINREG=0;
defparam \un16_t1_1_1[19:0] .CARRYINSELREG=0;
defparam \un16_t1_1_1[19:0] .CREG=1;
defparam \un16_t1_1_1[19:0] .DREG=0;
defparam \un16_t1_1_1[19:0] .INMODEREG=1;
defparam \un16_t1_1_1[19:0] .MREG=0;
defparam \un16_t1_1_1[19:0] .OPMODEREG=0;
defparam \un16_t1_1_1[19:0] .PREG=1;
defparam \un16_t1_1_1[19:0] .USE_DPORT="TRUE";
defparam \un16_t1_1_1[19:0] .USE_MULT="MULTIPLY";
defparam \un16_t1_1_1[19:0] .USE_SIMD="ONE48";
// @7:80
DSP48E1 \_l3.un17_t1[19:0] (
.ACOUT(ACOUT_2[29:0]),
.BCOUT(BCOUT_2[17:0]),
.CARRYCASCOUT(CARRYCASCOUT_2),
.CARRYOUT(CARRYOUT_2[3:0]),
.MULTSIGNOUT(MULTSIGNOUT_2),
.OVERFLOW(OVERFLOW_2),
.P({P_uc_2[47:20], \_l3.un17_t1 [19:0]}),
.PATTERNBDETECT(PATTERNBDETECT_2),
.PATTERNDETECT(PATTERNDETECT_2),
.PCOUT({P_uc_2_0[47:20], \_l3.un17_t1_0 [19:0]}),
.UNDERFLOW(UNDERFLOW_2),
.A({inp[31], inp[31], inp[31], inp[31], inp[31], inp[31], inp[31], inp[31], inp[31], inp[31], inp[31], inp[31], inp[31], inp[31], inp[31], inp[31], inp[31], inp[31], inp[31], inp[31], inp[31], inp[31], inp[31:24]}),
.ACIN({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.ALUMODE({GND, GND, GND, GND}),
.B({i_1_rep2, i_1_rep2, i_1_rep2, i_1_rep2, i_1_rep2, i_1_rep2, i_1_rep2, i_1_rep2, t5_5[9], t5_1[7], N_87_i, un1_i_1_i, un1_i_8_0, t5_3_i[0], t5_5[3], \t5_5_3_2_.N_4_i , N_62_i, t5_5[0]}),
.BCIN({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.C({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
.CARRYCASCIN(GND),
.CARRYIN(GND),
.CARRYINSEL({GND, GND, GND}),
.CEA1(GND),
.CEA2(GND),
.CEAD(GND),
.CEALUMODE(GND),
.CEB1(GND),
.CEB2(GND),
.CEC(GND),
.CECARRYIN(GND),
.CECTRL(GND),
.CED(GND),
.CEINMODE(VCC),
.CEM(GND),
.CEP(GND),
.CLK(CK),
.D({inp[39], inp[39], inp[39], inp[39], inp[39], inp[39], inp[39], inp[39], inp[39], inp[39], inp[39], inp[39], inp[39], inp[39], inp[39], inp[39], inp[39], inp[39:32]}),
.INMODE({GND, i_i[0], VCC, GND, GND}),
.MULTSIGNIN(GND),
.OPMODE({GND, GND, GND, GND, VCC, GND, VCC}),
.PCIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
.RSTA(GND),
.RSTALLCARRYIN(GND),
.RSTALUMODE(GND),
.RSTB(GND),
.RSTC(GND),
.RSTCTRL(GND),
.RSTD(GND),
.RSTINMODE(GND),
.RSTM(GND),
.RSTP(GND)
);
defparam \_l3.un17_t1[19:0] .ACASCREG=0;
defparam \_l3.un17_t1[19:0] .ADREG=0;
defparam \_l3.un17_t1[19:0] .ALUMODEREG=0;
defparam \_l3.un17_t1[19:0] .AREG=0;
defparam \_l3.un17_t1[19:0] .AUTORESET_PATDET="NO_RESET";
defparam \_l3.un17_t1[19:0] .A_INPUT="DIRECT";
defparam \_l3.un17_t1[19:0] .BCASCREG=0;
defparam \_l3.un17_t1[19:0] .BREG=0;
defparam \_l3.un17_t1[19:0] .B_INPUT="DIRECT";
defparam \_l3.un17_t1[19:0] .CARRYINREG=0;
defparam \_l3.un17_t1[19:0] .CARRYINSELREG=0;
defparam \_l3.un17_t1[19:0] .CREG=1;
defparam \_l3.un17_t1[19:0] .DREG=0;
defparam \_l3.un17_t1[19:0] .INMODEREG=1;
defparam \_l3.un17_t1[19:0] .MREG=0;
defparam \_l3.un17_t1[19:0] .OPMODEREG=0;
defparam \_l3.un17_t1[19:0] .PREG=0;
defparam \_l3.un17_t1[19:0] .USE_DPORT="TRUE";
defparam \_l3.un17_t1[19:0] .USE_MULT="MULTIPLY";
defparam \_l3.un17_t1[19:0] .USE_SIMD="ONE48";
// @7:86
LUT3 \t5_4_6_0_.SUM2_lut6_2_o6 (
.I0(i[0]),
.I1(i[2]),
.I2(i[1]),
.O(\t5_4_6_0_.SUM2 )
);
defparam \t5_4_6_0_.SUM2_lut6_2_o6 .INIT=8'h6C;
// @7:86
LUT3 \t5_4_6_0_.SUM2_lut6_2_o5 (
.I0(i[0]),
.I1(i[1]),
.I2(i_2_rep1),
.O(\t5_4_6_0_.SUM2_rep1 )
);
defparam \t5_4_6_0_.SUM2_lut6_2_o5 .INIT=8'h78;
// @7:75
LUT2 \t5_2_0_a4_lut6_2_o6[3] (
.I0(i[1]),
.I1(i[0]),
.O(t5_2[3])
);
defparam \t5_2_0_a4_lut6_2_o6[3] .INIT=4'h4;
// @7:75
LUT2 \t5_2_0_a4_lut6_2_o5[3] (
.I0(i[2]),
.I1(i[0]),
.O(\t5_5_9_.N_5_i )
);
defparam \t5_2_0_a4_lut6_2_o5[3] .INIT=4'h9;
// @7:79
LUT2 \i_RNI5QEC_o6[2] (
.I0(i[2]),
.I1(i[1]),
.O(un1_i_8_1_i)
);
defparam \i_RNI5QEC_o6[2] .INIT=4'h7;
// @7:79
LUT2 \i_RNI5QEC_o5[2] (
.I0(i[2]),
.I1(i[1]),
.O(\t5_4_6_0_.N_10_i )
);
defparam \i_RNI5QEC_o5[2] .INIT=4'hD;
// @7:80
LUT2 \t5_4_6_0_.N_71_i_i_lut6_2_o6 (
.I0(i[2]),
.I1(i[1]),
.O(N_71_i_i)
);
defparam \t5_4_6_0_.N_71_i_i_lut6_2_o6 .INIT=4'h9;
// @7:80
LUT3 \t5_4_6_0_.N_71_i_i_lut6_2_o5 (
.I0(i[2]),
.I1(i[1]),
.I2(i[0]),
.O(t5_1_i[8])
);
defparam \t5_4_6_0_.N_71_i_i_lut6_2_o5 .INIT=8'hD6;
// @7:75
LUT3 \t5_4_6_0_.m11_lut6_2_o6 (
.I0(i[2]),
.I1(i[1]),
.I2(i[0]),
.O(t5_4[5])
);
defparam \t5_4_6_0_.m11_lut6_2_o6 .INIT=8'h1E;
// @7:75
LUT3 \t5_4_6_0_.m11_lut6_2_o5 (
.I0(i[2]),
.I1(i[1]),
.I2(i[0]),
.O(t5_3[4])
);
defparam \t5_4_6_0_.m11_lut6_2_o5 .INIT=8'h71;
// @7:75
LUT3 \t5_4_10_8_.m5_lut6_2_o6 (
.I0(i[2]),
.I1(i[1]),
.I2(i[0]),
.O(t5_4[10])
);
defparam \t5_4_10_8_.m5_lut6_2_o6 .INIT=8'h46;
// @7:75
LUT3 \t5_4_10_8_.m5_lut6_2_o5 (
.I0(i[2]),
.I1(i[1]),
.I2(i[0]),
.O(t5_3[2])
);
defparam \t5_4_10_8_.m5_lut6_2_o5 .INIT=8'h2F;
// @7:79
LUT3 i_0_rep1_RNI5HAQ_o6 (
.I0(i[2]),
.I1(i[1]),
.I2(i[0]),
.O(t5_1_i[7])
);
defparam i_0_rep1_RNI5HAQ_o6.INIT=8'h9F;
// @7:79
LUT3 i_0_rep1_RNI5HAQ_o5 (
.I0(i[2]),
.I1(i[1]),
.I2(i_0_rep1),
.O(N_73_i)
);
defparam i_0_rep1_RNI5HAQ_o5.INIT=8'h5C;
// @7:79
LUT3 \i_fast_RNIMQSO_o6[2] (
.I0(i[2]),
.I1(i[1]),
.I2(i[0]),
.O(N_101_i)
);
defparam \i_fast_RNIMQSO_o6[2] .INIT=8'hC8;
// @7:79
LUT3 \i_fast_RNIMQSO_o5[2] (
.I0(i[1]),
.I1(i_fast[2]),
.I2(i[0]),
.O(\t5_4_6_0_.SUM2_fast )
);
defparam \i_fast_RNIMQSO_o5[2] .INIT=8'h6C;
// @7:80
LUT3 \t5_4_6_0_.N_7_i_lut6_2_o6 (
.I0(i[2]),
.I1(i[1]),
.I2(i[0]),
.O(\t5_4_6_0_.N_7_i )
);
defparam \t5_4_6_0_.N_7_i_lut6_2_o6 .INIT=8'h63;
// @7:80
LUT3 \t5_4_6_0_.N_7_i_lut6_2_o5 (
.I0(i[2]),
.I1(i[1]),
.I2(i[0]),
.O(t5_3[0])
);
defparam \t5_4_6_0_.N_7_i_lut6_2_o5 .INIT=8'h54;
// @7:80
LUT3 \t5_4_6_0_.N_5_i_lut6_2_o6 (
.I0(i[2]),
.I1(i[1]),
.I2(i[0]),
.O(\t5_4_6_0_.N_5_i )
);
defparam \t5_4_6_0_.N_5_i_lut6_2_o6 .INIT=8'hA8;
// @7:80
LUT3 \t5_4_6_0_.N_5_i_lut6_2_o5 (
.I0(i[2]),
.I1(i[1]),
.I2(i[0]),
.O(t5_3[5])
);
defparam \t5_4_6_0_.N_5_i_lut6_2_o5 .INIT=8'h42;
// @7:80
LUT3 \t5_4_6_0_.N_4_i_lut6_2_o6 (
.I0(i[2]),
.I1(i[1]),
.I2(i[0]),
.O(\t5_4_6_0_.N_4_i )
);
defparam \t5_4_6_0_.N_4_i_lut6_2_o6 .INIT=8'hA4;
// @7:80
LUT3 \t5_4_6_0_.N_4_i_lut6_2_o5 (
.I0(i[2]),
.I1(i[1]),
.I2(i[0]),
.O(t5_1[8])
);
defparam \t5_4_6_0_.N_4_i_lut6_2_o5 .INIT=8'h29;
// @7:80
LUT3 \t5_3_10_0_.N_17_i_lut6_2_o6 (
.I0(i[2]),
.I1(i[1]),
.I2(i[0]),
.O(\t5_3_10_0_.N_17_i )
);
defparam \t5_3_10_0_.N_17_i_lut6_2_o6 .INIT=8'hEA;
// @7:80
LUT3 \t5_3_10_0_.N_17_i_lut6_2_o5 (
.I0(i[2]),
.I1(i[1]),
.I2(i[0]),
.O(t5_3[9])
);
defparam \t5_3_10_0_.N_17_i_lut6_2_o5 .INIT=8'h51;
// @7:80
LUT3 \t5_3_10_0_.N_14_i_lut6_2_o6 (
.I0(i[2]),
.I1(i[1]),
.I2(i[0]),
.O(\t5_3_10_0_.N_14_i )
);
defparam \t5_3_10_0_.N_14_i_lut6_2_o6 .INIT=8'h85;
// @7:80
LUT3 \t5_3_10_0_.N_14_i_lut6_2_o5 (
.I0(i[2]),
.I1(i[1]),
.I2(i[0]),
.O(t5_3[1])
);
defparam \t5_3_10_0_.N_14_i_lut6_2_o5 .INIT=8'h1C;
// @7:75
LUT3 \t5_4_6_0_.m8_lut6_2_o6 (
.I0(i[2]),
.I1(i[1]),
.I2(i[0]),
.O(t5_4[3])
);
defparam \t5_4_6_0_.m8_lut6_2_o6 .INIT=8'h16;
// @7:75
LUT3 \t5_4_6_0_.m8_lut6_2_o5 (
.I0(i[2]),
.I1(i[1]),
.I2(i[0]),
.O(\t5_3_10_0_.N_9_i )
);
defparam \t5_4_6_0_.m8_lut6_2_o5 .INIT=8'hCA;
// @7:79
LUT3 i_1_rep2_RNI7MKK_0_o6 (
.I0(i_1_rep2),
.I1(i[2]),
.I2(i[0]),
.O(N_60_i)
);
defparam i_1_rep2_RNI7MKK_0_o6.INIT=8'h67;
// @7:79
LUT3 i_1_rep2_RNI7MKK_0_o5 (
.I0(i[2]),
.I1(i[1]),
.I2(i[0]),
.O(t5_2[6])
);
defparam i_1_rep2_RNI7MKK_0_o5.INIT=8'hD3;
// @7:79
LUT3 i_1_rep2_RNI7MKK_o6 (
.I0(i_1_rep2),
.I1(i[2]),
.I2(i[0]),
.O(N_57_i)
);
defparam i_1_rep2_RNI7MKK_o6.INIT=8'h9D;
// @7:79
LUT3 i_1_rep2_RNI7MKK_o5 (
.I0(i[2]),
.I1(i[1]),
.I2(i[0]),
.O(\t5_4_10_8_.N_3_i )
);
defparam i_1_rep2_RNI7MKK_o5.INIT=8'h8A;
endmodule /* dct4 */
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_uart.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 243 01/31/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_uart (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [7:0] sub_wire1;
wire sub_wire2;
wire wrfull = sub_wire0;
wire [7:0] q = sub_wire1[7:0];
wire rdempty = sub_wire2;
dcfifo dcfifo_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.wrfull (sub_wire0),
.q (sub_wire1),
.rdempty (sub_wire2),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Cyclone IV E",
dcfifo_component.lpm_numwords = 4096,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 8,
dcfifo_component.lpm_widthu = 12,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "8"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "8"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_uart.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_uart.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_uart.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_uart.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_uart_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_uart_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_transmitter.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core transmitter logic ////
//// ////
//// Known problems (limits): ////
//// None known ////
//// ////
//// To Do: ////
//// Thourough testing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// Modified for use in the ZAP project by Revanth Kamaraj ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.18 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16 2002/01/08 11:29:40 mohor
// tf_pop was too wide. Now it is only 1 clk cycle width.
//
// Revision 1.15 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.14 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.13 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.12 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.11 2001/10/29 17:00:46 gorban
// fixed parity sending and tx_fifo resets over- and underrun
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.6 2001/06/23 11:21:48 gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.5 2001/06/02 14:28:14 gorban
// Fixed receiver and transmitter. Major bug fixed.
//
// Revision 1.4 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:49 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
//
// Revision 1.1 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
`include "uart_defines.v"
module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);
input clk;
input wb_rst_i;
input [7:0] lcr;
input tf_push;
input [7:0] wb_dat_i;
input enable;
input tx_reset;
input lsr_mask; //reset of fifo
output stx_pad_o;
output [2:0] tstate;
output [`UART_FIFO_COUNTER_W-1:0] tf_count;
reg [2:0] tstate;
reg [4:0] counter;
reg [2:0] bit_counter; // counts the bits to be sent
reg [6:0] shift_out; // output shift register
reg stx_o_tmp;
reg parity_xor; // parity of the word
reg tf_pop;
reg bit_out;
// TX FIFO instance
//
// Transmitter FIFO signals
wire [`UART_FIFO_WIDTH-1:0] tf_data_in;
wire [`UART_FIFO_WIDTH-1:0] tf_data_out;
wire tf_push;
wire tf_overrun;
wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
assign tf_data_in = wb_dat_i;
uart_tfifo fifo_tx( // error bit signal is not used in transmitter FIFO
.clk( clk ),
.wb_rst_i( wb_rst_i ),
.data_in( tf_data_in ),
.data_out( tf_data_out ),
.push( tf_push ),
.pop( tf_pop ),
.overrun( tf_overrun ),
.count( tf_count ),
.fifo_reset( tx_reset ),
.reset_status(lsr_mask)
);
// TRANSMITTER FINAL STATE MACHINE
parameter s_idle = 3'd0;
parameter s_send_start = 3'd1;
parameter s_send_byte = 3'd2;
parameter s_send_parity = 3'd3;
parameter s_send_stop = 3'd4;
parameter s_pop_byte = 3'd5;
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
begin
tstate <= s_idle;
stx_o_tmp <= 1'b1;
counter <= 5'b0;
shift_out <= 7'b0;
bit_out <= 1'b0;
parity_xor <= 1'b0;
tf_pop <= 1'b0;
bit_counter <= 3'b0;
end
else
if (enable)
begin
case (tstate)
s_idle : if (~|tf_count) // if tf_count==0
begin
tstate <= s_idle;
stx_o_tmp <= 1'b1;
end
else
begin
tf_pop <= 1'b0;
stx_o_tmp <= 1'b1;
tstate <= s_pop_byte;
end
s_pop_byte : begin
tf_pop <= 1'b1;
case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
2'b00 : begin
bit_counter <= 3'b100;
parity_xor <= ^tf_data_out[4:0];
end
2'b01 : begin
bit_counter <= 3'b101;
parity_xor <= ^tf_data_out[5:0];
end
2'b10 : begin
bit_counter <= 3'b110;
parity_xor <= ^tf_data_out[6:0];
end
2'b11 : begin
bit_counter <= 3'b111;
parity_xor <= ^tf_data_out[7:0];
end
endcase
{shift_out[6:0], bit_out} <= tf_data_out;
tstate <= s_send_start;
end
s_send_start : begin
tf_pop <= 1'b0;
if (~|counter)
counter <= 5'b01111;
else
if (counter == 5'b00001)
begin
counter <= 0;
tstate <= s_send_byte;
end
else
counter <= counter - 1'b1;
stx_o_tmp <= 1'b0;
end
s_send_byte : begin
if (~|counter)
counter <= 5'b01111;
else
if (counter == 5'b00001)
begin
if (bit_counter > 3'b0)
begin
bit_counter <= bit_counter - 1'b1;
{shift_out[5:0],bit_out } <= {shift_out[6:1], shift_out[0]};
tstate <= s_send_byte;
end
else // end of byte
if (~lcr[`UART_LC_PE])
begin
tstate <= s_send_stop;
end
else
begin
case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
2'b00: bit_out <= ~parity_xor;
2'b01: bit_out <= 1'b1;
2'b10: bit_out <= parity_xor;
2'b11: bit_out <= 1'b0;
endcase
tstate <= s_send_parity;
end
counter <= 0;
end
else
counter <= counter - 1'b1;
stx_o_tmp <= bit_out; // set output pin
end
s_send_parity : begin
if (~|counter)
counter <= 5'b01111;
else
if (counter == 5'b00001)
begin
counter <= 4'b0;
tstate <= s_send_stop;
end
else
counter <= counter - 1'b1;
stx_o_tmp <= bit_out;
end
s_send_stop : begin
if (~|counter)
begin
casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
3'b0xx: counter <= 5'b01101; // 1 stop bit ok igor
3'b100: counter <= 5'b10101; // 1.5 stop bit
default: counter <= 5'b11101; // 2 stop bits
endcase
end
else
if (counter == 5'b00001)
begin
counter <= 0;
tstate <= s_idle;
end
else
counter <= counter - 1'b1;
stx_o_tmp <= 1'b1;
end
default : // should never get here
tstate <= s_idle;
endcase
end // end if enable
else
tf_pop <= 1'b0; // tf_pop must be 1 cycle width
end // transmitter logic
assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; // Break condition
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O22AI_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__O22AI_PP_SYMBOL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o22ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O22AI_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXBP_BLACKBOX_V
`define SKY130_FD_SC_HS__DLXBP_BLACKBOX_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlxbp (
Q ,
Q_N ,
D ,
GATE
);
output Q ;
output Q_N ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXBP_BLACKBOX_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`include "firmware/src/mmc3_eth_core.v"
`include "gpio/gpio_core.v"
`include "gpio/gpio.v"
`include "bram_fifo/bram_fifo.v"
`include "bram_fifo/bram_fifo_core.v"
`include "utils/reset_gen.v"
`include "utils/fifo_32_to_8.v"
`include "utils/generic_fifo.v"
`include "utils/clock_multiplier.v"
`include "utils/clock_divider.v"
`include "utils/rbcp_to_bus.v"
`include "utils/bus_to_ip.v"
module tb (
input wire BUS_CLK,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
inout wire [31:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire BUS_BYTE_ACCESS
);
localparam FIFO_BASEADDR = 32'h8000;
localparam FIFO_HIGHADDR = 32'h9000-1;
localparam FIFO_BASEADDR_DATA = 32'h8000_0000;
localparam FIFO_HIGHADDR_DATA = 32'h9000_0000;
localparam ABUSWIDTH = 32;
assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
localparam RESET_DELAY = 5000;
/*
localparam CLOCKPERIOD_CLKIN1 = 10*1000;
reg CLKIN1;
initial CLKIN1 = 1'b0;
always #(CLOCKPERIOD_CLKIN1 / 2) CLKIN1 = !CLKIN1;
*/
// ----- Clock (mimics a PLL) -----
localparam PLL_MUL = 5;
localparam PLL_DIV_BUS_CLK = 7;
localparam PLL_DIV_CLK250 = 4;
localparam PLL_DIV_CLK125TX = 8;
localparam PLL_DIV_CLK125TX90 = 8;
localparam PLL_DIV_CLK125RX = 8;
localparam PLL_LOCK_DELAY = 1000*1000;
wire PLL_VCO, CLK250, CLK125TX, CLK125TX90, CLK125RX;
clock_multiplier #(
.MULTIPLIER(PLL_MUL)
) i_clock_multiplier(
.CLK(BUS_CLK),
.CLOCK(PLL_VCO)
);
// clock_divider #(
// .DIVISOR(PLL_DIV_BUS_CLK)
// ) i_clock_divisor_1 (
// .CLK(PLL_VCO),
// .RESET(1'b0),
// .CE(),
// .CLOCK(BUS_CLK)
// );
clock_divider #(
.DIVISOR(PLL_DIV_CLK250)
) i_clock_divisor_2 (
.CLK(PLL_VCO),
.RESET(1'b0),
.CE(),
.CLOCK(CLK250)
);
clock_divider #(
.DIVISOR(PLL_DIV_CLK125TX)
) i_clock_divisor_3 (
.CLK(PLL_VCO),
.RESET(1'b0),
.CE(),
.CLOCK(CLK125TX)
);
clock_divider #(
.DIVISOR(PLL_DIV_CLK125RX)
) i_clock_divisor_4 (
.CLK(PLL_VCO),
.RESET(1'b0),
.CE(),
.CLOCK(CLK125RX)
);
reg LOCKED;
initial begin
LOCKED = 1'b0;
#(PLL_LOCK_DELAY) LOCKED = 1'b1;
end
// -------------------------
// ------- RESET/CLOCK ------- //
// wire BUS_RST;
// reset_gen ireset_gen (
// .CLK(BUS_CLK),
// .RST(BUS_RST)
// );
reg RESET_N;
initial begin
RESET_N = 1'b0;
#(RESET_DELAY) RESET_N = 1'b1;
end
// ------- USER MODULES ------- //
wire FIFO_FULL, FIFO_READ, FIFO_NOT_EMPTY, FIFO_WRITE;
wire [31:0] FIFO_DATA;
bram_fifo #(
.BASEADDR(FIFO_BASEADDR),
.HIGHADDR(FIFO_HIGHADDR),
.BASEADDR_DATA(FIFO_BASEADDR_DATA),
.HIGHADDR_DATA(FIFO_HIGHADDR_DATA),
.ABUSWIDTH(32)
) i_out_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.FIFO_READ_NEXT_OUT(FIFO_READ),
.FIFO_EMPTY_IN(!FIFO_WRITE),
.FIFO_DATA(FIFO_DATA),
.FIFO_NOT_EMPTY(FIFO_NOT_EMPTY),
.FIFO_FULL(FIFO_FULL),
.FIFO_NEAR_FULL(),
.FIFO_READ_ERROR()
);
wire [7:0] GPIO;
wire ENABLE;
assign ENABLE = GPIO[0];
mmc3_eth_core i_mmc3_eth_core (
.RESET_N(RESET_N),
// clocks from PLL
.BUS_CLK(BUS_CLK),
.CLK125TX(CLK125TX),
.CLK125TX90(CLK125TX90),
.CLK125RX(CLK125RX),
.PLL_LOCKED(LOCKED),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_BYTE_ACCESS(BUS_BYTE_ACCESS),
.fifo_empty(!FIFO_NOT_EMPTY),
.fifo_full(FIFO_FULL),
.FIFO_NEXT(!FIFO_FULL && ENABLE),
.FIFO_DATA(FIFO_DATA),
.FIFO_WRITE(FIFO_WRITE),
.GPIO(GPIO)
);
initial begin
$dumpfile("/tmp/mmc3_eth.vcd");
$dumpvars(0);
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:24:57 03/11/2015
// Design Name: delay_line
// Module Name: C:/Users/omicronns/Workspaces/webpack-ise/lab2/delay_line/tb_delay_line.v
// Project Name: delay_line
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: delay_line
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_delay_line #(
parameter WIDTH = 8,
parameter DELAY = 4
);
wire clk;
wire [WIDTH - 1:0] data_in;
wire [WIDTH - 1:0] data_out;
delay_line_gen_test #(
.WIDTH(WIDTH),
.DELAY(DELAY)
)
generator (
.out(data_in),
.clk(clk)
);
// Instantiate the Unit Under Test (UUT)
delay_line #(
.WIDTH(WIDTH),
.DELAY(DELAY)
)
uut (
.ce(1'b1),
.rst(1'b0),
.clk(clk),
.in(data_in),
.out(data_out)
);
delay_line_check_test #(
.WIDTH(WIDTH),
.DELAY(DELAY)
)
checker (
.in(data_out)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's ALU ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/project,or1k ////
//// ////
//// Description ////
//// ALU ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_alu.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Defines added, flags are corrected.
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_alu(
a, b, mult_mac_result, macrc_op,
alu_op, alu_op2, comp_op,
cust5_op, cust5_limm,
result, flagforw, flag_we,
ovforw, ov_we,
cyforw, cy_we, carry, flag
);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
input [width-1:0] a;
input [width-1:0] b;
input [width-1:0] mult_mac_result;
input macrc_op;
input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
input [`OR1200_ALUOP2_WIDTH-1:0] alu_op2;
input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
input [4:0] cust5_op;
input [5:0] cust5_limm;
output [width-1:0] result;
output flagforw;
output flag_we;
output cyforw;
output cy_we;
output ovforw;
output ov_we;
input carry;
input flag;
//
// Internal wires and regs
//
reg [width-1:0] result;
reg [width-1:0] shifted_rotated;
reg [width-1:0] extended;
`ifdef OR1200_IMPL_ALU_CUST5
reg [width-1:0] result_cust5;
`endif
reg flagforw;
reg flagcomp;
reg flag_we;
reg cyforw;
reg cy_we;
reg ovforw;
reg ov_we;
wire [width-1:0] comp_a;
wire [width-1:0] comp_b;
wire a_eq_b;
wire a_lt_b;
wire [width-1:0] result_sum;
wire [width-1:0] result_and;
wire cy_sum;
`ifdef OR1200_IMPL_SUB
wire cy_sub;
`endif
wire ov_sum;
wire [width-1:0] carry_in;
wire [width-1:0] b_mux;
//
// Combinatorial logic
//
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
`ifdef OR1200_IMPL_ALU_COMP1
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
`endif
`ifdef OR1200_IMPL_ALU_COMP3
assign a_eq_b = !(|result_sum);
// signed compare when comp_op[3] is set
assign a_lt_b = comp_op[3] ? ((a[width-1] & !b[width-1]) |
(!a[width-1] & !b[width-1] & result_sum[width-1])|
(a[width-1] & b[width-1] & result_sum[width-1])):
(a < b);
`endif
`ifdef OR1200_IMPL_SUB
`ifdef OR1200_IMPL_ALU_COMP3
assign cy_sub = a_lt_b;
`else
assign cy_sub = (comp_a < comp_b);
`endif
`endif
`ifdef OR1200_IMPL_ADDC
assign carry_in = (alu_op==`OR1200_ALUOP_ADDC) ?
{{width-1{1'b0}},carry} : {width{1'b0}};
`else
assign carry_in = {width-1{1'b0}};
`endif
`ifdef OR1200_IMPL_ALU_COMP3
`ifdef OR1200_IMPL_SUB
assign b_mux = ((alu_op==`OR1200_ALUOP_SUB) | (alu_op==`OR1200_ALUOP_COMP)) ?
(~b)+1 : b;
`else
assign b_mux = (alu_op==`OR1200_ALUOP_COMP) ? (~b)+1 : b;
`endif
`else // ! `ifdef OR1200_IMPL_ALU_COMP3
`ifdef OR1200_IMPL_SUB
assign b_mux = (alu_op==`OR1200_ALUOP_SUB) ? (~b)+1 : b;
`else
assign b_mux = b;
`endif
`endif
assign {cy_sum, result_sum} = (a + b_mux) + carry_in;
// Numbers either both +ve and bit 31 of result set
assign ov_sum = ((!a[width-1] & !b_mux[width-1]) & result_sum[width-1]) |
`ifdef OR1200_IMPL_SUB
// Subtract larger negative from smaller positive
((!a[width-1] & b_mux[width-1]) & result_sum[width-1] &
alu_op==`OR1200_ALUOP_SUB) |
`endif
// or both -ve and bit 31 of result clear
((a[width-1] & b_mux[width-1]) & !result_sum[width-1]);
assign result_and = a & b;
//
// Simulation check for bad ALU behavior
//
`ifdef OR1200_WARNINGS
// synopsys translate_off
always @(result) begin
if (result === 32'bx)
$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
end
// synopsys translate_on
`endif
//
// Central part of the ALU
//
always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op
or shifted_rotated or mult_mac_result or flag or carry
`ifdef OR1200_IMPL_ALU_EXT
or extended
`endif
`ifdef OR1200_IMPL_ALU_CUST5
or result_cust5
`endif
) begin
`ifdef OR1200_CASE_DEFAULT
casez (alu_op) // synopsys parallel_case
`else
casez (alu_op) // synopsys full_case parallel_case
`endif
`ifdef OR1200_IMPL_ALU_FFL1
`OR1200_ALUOP_FFL1: begin
`ifdef OR1200_CASE_DEFAULT
casez (alu_op2) // synopsys parallel_case
`else
casez (alu_op2) // synopsys full_case parallel_case
`endif
0: begin // FF1
result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;
end
default: begin // FL1
result = a[31] ? 32 : a[30] ? 31 : a[29] ? 30 : a[28] ? 29 : a[27] ? 28 : a[26] ? 27 : a[25] ? 26 : a[24] ? 25 : a[23] ? 24 : a[22] ? 23 : a[21] ? 22 : a[20] ? 21 : a[19] ? 20 : a[18] ? 19 : a[17] ? 18 : a[16] ? 17 : a[15] ? 16 : a[14] ? 15 : a[13] ? 14 : a[12] ? 13 : a[11] ? 12 : a[10] ? 11 : a[9] ? 10 : a[8] ? 9 : a[7] ? 8 : a[6] ? 7 : a[5] ? 6 : a[4] ? 5 : a[3] ? 4 : a[2] ? 3 : a[1] ? 2 : a[0] ? 1 : 0 ;
end
endcase // casez (alu_op2)
end // case: `OR1200_ALUOP_FFL1
`endif // `ifdef OR1200_IMPL_ALU_FFL1
`ifdef OR1200_IMPL_ALU_CUST5
`OR1200_ALUOP_CUST5 : begin
result = result_cust5;
end
`endif
`OR1200_ALUOP_SHROT : begin
result = shifted_rotated;
end
`ifdef OR1200_IMPL_ADDC
`OR1200_ALUOP_ADDC,
`endif
`ifdef OR1200_IMPL_SUB
`OR1200_ALUOP_SUB,
`endif
`OR1200_ALUOP_ADD : begin
result = result_sum;
end
`OR1200_ALUOP_XOR : begin
result = a ^ b;
end
`OR1200_ALUOP_OR : begin
result = a | b;
end
`ifdef OR1200_IMPL_ALU_EXT
`OR1200_ALUOP_EXTHB : begin
result = extended;
end
`OR1200_ALUOP_EXTW : begin
result = a;
end
`endif
`OR1200_ALUOP_MOVHI : begin
if (macrc_op) begin
result = mult_mac_result;
end
else begin
result = b << 16;
end
end
`ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_DIV_IMPLEMENTED
`OR1200_ALUOP_DIV,
`OR1200_ALUOP_DIVU,
`endif
`OR1200_ALUOP_MUL,
`OR1200_ALUOP_MULU : begin
result = mult_mac_result;
end
`endif
`OR1200_ALUOP_CMOV: begin
result = flag ? a : b;
end
`ifdef OR1200_CASE_DEFAULT
default: begin
`else
`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin
`endif
result=result_and;
end
endcase
end
//
// Generate flag and flag write enable
//
always @(alu_op or result_sum or result_and or flagcomp
) begin
casez (alu_op) // synopsys parallel_case
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
`ifdef OR1200_IMPL_ADDC
`OR1200_ALUOP_ADDC,
`endif
`OR1200_ALUOP_ADD : begin
flagforw = (result_sum == 32'h0000_0000);
flag_we = 1'b1;
end
`OR1200_ALUOP_AND: begin
flagforw = (result_and == 32'h0000_0000);
flag_we = 1'b1;
end
`endif
`OR1200_ALUOP_COMP: begin
flagforw = flagcomp;
flag_we = 1'b1;
end
default: begin
flagforw = flagcomp;
flag_we = 1'b0;
end
endcase
end
//
// Generate SR[CY] write enable
//
always @(alu_op or cy_sum
`ifdef OR1200_IMPL_CY
`ifdef OR1200_IMPL_SUB
or cy_sub
`endif
`endif
) begin
casez (alu_op) // synopsys parallel_case
`ifdef OR1200_IMPL_CY
`ifdef OR1200_IMPL_ADDC
`OR1200_ALUOP_ADDC,
`endif
`OR1200_ALUOP_ADD : begin
cyforw = cy_sum;
cy_we = 1'b1;
end
`ifdef OR1200_IMPL_SUB
`OR1200_ALUOP_SUB: begin
cyforw = cy_sub;
cy_we = 1'b1;
end
`endif
`endif
default: begin
cyforw = 1'b0;
cy_we = 1'b0;
end
endcase
end
//
// Generate SR[OV] write enable
//
always @(alu_op or ov_sum) begin
casez (alu_op) // synopsys parallel_case
`ifdef OR1200_IMPL_OV
`ifdef OR1200_IMPL_ADDC
`OR1200_ALUOP_ADDC,
`endif
`ifdef OR1200_IMPL_SUB
`OR1200_ALUOP_SUB,
`endif
`OR1200_ALUOP_ADD : begin
ovforw = ov_sum;
ov_we = 1'b1;
end
`endif
default: begin
ovforw = 1'b0;
ov_we = 1'b0;
end
endcase
end
//
// Shifts and rotation
//
always @(alu_op2 or a or b) begin
case (alu_op2) // synopsys parallel_case
`OR1200_SHROTOP_SLL :
shifted_rotated = (a << b[4:0]);
`OR1200_SHROTOP_SRL :
shifted_rotated = (a >> b[4:0]);
`ifdef OR1200_IMPL_ALU_ROTATE
`OR1200_SHROTOP_ROR :
shifted_rotated = (a << (6'd32-{1'b0,b[4:0]})) |
(a >> b[4:0]);
`endif
default:
shifted_rotated = ({32{a[31]}} <<
(6'd32-{1'b0, b[4:0]})) |
a >> b[4:0];
endcase
end
//
// First type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP1
always @(comp_op or a_eq_b or a_lt_b) begin
case(comp_op[2:0]) // synopsys parallel_case
`OR1200_COP_SFEQ:
flagcomp = a_eq_b;
`OR1200_COP_SFNE:
flagcomp = ~a_eq_b;
`OR1200_COP_SFGT:
flagcomp = ~(a_eq_b | a_lt_b);
`OR1200_COP_SFGE:
flagcomp = ~a_lt_b;
`OR1200_COP_SFLT:
flagcomp = a_lt_b;
`OR1200_COP_SFLE:
flagcomp = a_eq_b | a_lt_b;
default:
flagcomp = 1'b0;
endcase
end
`endif
//
// Second type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP2
always @(comp_op or comp_a or comp_b) begin
case(comp_op[2:0]) // synopsys parallel_case
`OR1200_COP_SFEQ:
flagcomp = (comp_a == comp_b);
`OR1200_COP_SFNE:
flagcomp = (comp_a != comp_b);
`OR1200_COP_SFGT:
flagcomp = (comp_a > comp_b);
`OR1200_COP_SFGE:
flagcomp = (comp_a >= comp_b);
`OR1200_COP_SFLT:
flagcomp = (comp_a < comp_b);
`OR1200_COP_SFLE:
flagcomp = (comp_a <= comp_b);
default:
flagcomp = 1'b0;
endcase
end
`endif // `ifdef OR1200_IMPL_ALU_COMP2
`ifdef OR1200_IMPL_ALU_COMP3
always @(comp_op or a_eq_b or a_lt_b) begin
case(comp_op[2:0]) // synopsys parallel_case
`OR1200_COP_SFEQ:
flagcomp = a_eq_b;
`OR1200_COP_SFNE:
flagcomp = ~a_eq_b;
`OR1200_COP_SFGT:
flagcomp = ~(a_eq_b | a_lt_b);
`OR1200_COP_SFGE:
flagcomp = ~a_lt_b;
`OR1200_COP_SFLT:
flagcomp = a_lt_b;
`OR1200_COP_SFLE:
flagcomp = a_eq_b | a_lt_b;
default:
flagcomp = 1'b0;
endcase
end
`endif
`ifdef OR1200_IMPL_ALU_EXT
always @(alu_op or alu_op2 or a) begin
casez (alu_op2)
`OR1200_EXTHBOP_HS : extended = {{16{a[15]}},a[15:0]};
`OR1200_EXTHBOP_BS : extended = {{24{a[7]}},a[7:0]};
`OR1200_EXTHBOP_HZ : extended = {16'd0,a[15:0]};
`OR1200_EXTHBOP_BZ : extended = {24'd0,a[7:0]};
default: extended = a; // Used for l.extw instructions
endcase // casez (alu_op2)
end
`endif
//
// l.cust5 custom instructions
//
`ifdef OR1200_IMPL_ALU_CUST5
// Examples for move byte, set bit and clear bit
//
always @(cust5_op or cust5_limm or a or b) begin
casez (cust5_op) // synopsys parallel_case
5'h1 : begin
casez (cust5_limm[1:0])
2'h0: result_cust5 = {a[31:8], b[7:0]};
2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
2'h3: result_cust5 = {b[7:0], a[23:0]};
endcase
end
5'h2 :
result_cust5 = a | (1 << cust5_limm);
5'h3 :
result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
//
// *** Put here new l.cust5 custom instructions ***
//
default: begin
result_cust5 = a;
end
endcase
end // always @ (cust5_op or cust5_limm or a or b)
`endif
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:37:28 07/09/2015
// Design Name:
// Module Name: DVI_OUT
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DVI_OUT
( input PixelClk,
input PixelClk2,
input PixelClk10,
input SerDesStrobe,
input [7:0] Red,
input [7:0] Green,
input [7:0] Blue,
input HSync,
input VSync,
input VideoEnable,
output [3:0] TMDS_out_P,
output [3:0] TMDS_out_N
);
wire [9:0] EncRed;
wire [9:0] EncGreen;
wire [9:0] EncBlue;
wire SerOutRed;
wire SerOutGreen;
wire SerOutBlue;
wire SerOutClock;
Component_encoder CE_Red(.Data(Red), .C0(1'b0), .C1(1'b0), .DE(VideoEnable), .PixClk(PixelClk), .OutEncoded(EncRed));
Component_encoder CE_Green(.Data(Green), .C0(1'b0), .C1(1'b0), .DE(VideoEnable), .PixClk(PixelClk), .OutEncoded(EncGreen));
Component_encoder CE_Blue(.Data(Blue), .C0(HSync), .C1(VSync), .DE(VideoEnable), .PixClk(PixelClk), .OutEncoded(EncBlue));
Serializer_10_1 SER_Red(.Data(EncRed), .Clk_10(PixelClk10), .Clk_2(PixelClk2), .Strobe(SerDesStrobe), .Out(SerOutRed));
Serializer_10_1 SER_Green(.Data(EncGreen), .Clk_10(PixelClk10), .Clk_2(PixelClk2), .Strobe(SerDesStrobe), .Out(SerOutGreen));
Serializer_10_1 SER_Blue(.Data(EncBlue), .Clk_10(PixelClk10), .Clk_2(PixelClk2), .Strobe(SerDesStrobe), .Out(SerOutBlue));
Serializer_10_1 SER_Clock(.Data(10'b0000011111), .Clk_10(PixelClk10), .Clk_2(PixelClk2), .Strobe(SerDesStrobe), .Out(SerOutClock));
OBUFDS OutBufDif_B(.I(SerOutBlue), .O(TMDS_out_P[0]), .OB(TMDS_out_N[0]));
OBUFDS OutBufDif_G(.I(SerOutGreen), .O(TMDS_out_P[1]), .OB(TMDS_out_N[1]));
OBUFDS OutBufDif_R(.I(SerOutRed), .O(TMDS_out_P[2]), .OB(TMDS_out_N[2]));
OBUFDS OutBufDif_C(.I(SerOutClock), .O(TMDS_out_P[3]), .OB(TMDS_out_N[3]));
endmodule
|
// soc_system.v
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module soc_system (
input wire clk_clk, // clk.clk
input wire hps_0_f2h_cold_reset_req_reset_n, // hps_0_f2h_cold_reset_req.reset_n
input wire hps_0_f2h_debug_reset_req_reset_n, // hps_0_f2h_debug_reset_req.reset_n
input wire [27:0] hps_0_f2h_stm_hw_events_stm_hwevents, // hps_0_f2h_stm_hw_events.stm_hwevents
input wire hps_0_f2h_warm_reset_req_reset_n, // hps_0_f2h_warm_reset_req.reset_n
output wire hps_0_h2f_reset_reset_n, // hps_0_h2f_reset.reset_n
output wire hps_0_hps_io_hps_io_emac1_inst_TX_CLK, // hps_0_hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_0_hps_io_hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_0_hps_io_hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_0_hps_io_hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_0_hps_io_hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_0_hps_io_hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_0_hps_io_hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_0_hps_io_hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_0_hps_io_hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_0_hps_io_hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_0_hps_io_hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_0_hps_io_hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_0_hps_io_hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_0_hps_io_hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_0_hps_io_hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_0_hps_io_hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_0_hps_io_hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_0_hps_io_hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_0_hps_io_hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_0_hps_io_hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_0_hps_io_hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_0_hps_io_hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_0_hps_io_hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_0_hps_io_hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_0_hps_io_hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_0_hps_io_hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_0_hps_io_hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_0_hps_io_hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_0_hps_io_hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_0_hps_io_hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_0_hps_io_hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_0_hps_io_hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_0_hps_io_hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_0_hps_io_hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_0_hps_io_hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_0_hps_io_hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_0_hps_io_hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_0_hps_io_hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_0_hps_io_hps_io_i2c0_inst_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_0_hps_io_hps_io_i2c0_inst_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_0_hps_io_hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_0_hps_io_hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO09, // .hps_io_gpio_inst_GPIO09
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO61, // .hps_io_gpio_inst_GPIO61
output wire [14:0] memory_mem_a, // memory.mem_a
output wire [2:0] memory_mem_ba, // .mem_ba
output wire memory_mem_ck, // .mem_ck
output wire memory_mem_ck_n, // .mem_ck_n
output wire memory_mem_cke, // .mem_cke
output wire memory_mem_cs_n, // .mem_cs_n
output wire memory_mem_ras_n, // .mem_ras_n
output wire memory_mem_cas_n, // .mem_cas_n
output wire memory_mem_we_n, // .mem_we_n
output wire memory_mem_reset_n, // .mem_reset_n
inout wire [31:0] memory_mem_dq, // .mem_dq
inout wire [3:0] memory_mem_dqs, // .mem_dqs
inout wire [3:0] memory_mem_dqs_n, // .mem_dqs_n
output wire memory_mem_odt, // .mem_odt
output wire [3:0] memory_mem_dm, // .mem_dm
input wire memory_oct_rzqin, // .oct_rzqin
input wire reset_reset_n // reset.reset_n
);
wire [1:0] hps_0_h2f_axi_master_awburst; // hps_0:h2f_AWBURST -> mm_interconnect_0:hps_0_h2f_axi_master_awburst
wire [3:0] hps_0_h2f_axi_master_arlen; // hps_0:h2f_ARLEN -> mm_interconnect_0:hps_0_h2f_axi_master_arlen
wire [7:0] hps_0_h2f_axi_master_wstrb; // hps_0:h2f_WSTRB -> mm_interconnect_0:hps_0_h2f_axi_master_wstrb
wire hps_0_h2f_axi_master_wready; // mm_interconnect_0:hps_0_h2f_axi_master_wready -> hps_0:h2f_WREADY
wire [11:0] hps_0_h2f_axi_master_rid; // mm_interconnect_0:hps_0_h2f_axi_master_rid -> hps_0:h2f_RID
wire hps_0_h2f_axi_master_rready; // hps_0:h2f_RREADY -> mm_interconnect_0:hps_0_h2f_axi_master_rready
wire [3:0] hps_0_h2f_axi_master_awlen; // hps_0:h2f_AWLEN -> mm_interconnect_0:hps_0_h2f_axi_master_awlen
wire [11:0] hps_0_h2f_axi_master_wid; // hps_0:h2f_WID -> mm_interconnect_0:hps_0_h2f_axi_master_wid
wire [3:0] hps_0_h2f_axi_master_arcache; // hps_0:h2f_ARCACHE -> mm_interconnect_0:hps_0_h2f_axi_master_arcache
wire hps_0_h2f_axi_master_wvalid; // hps_0:h2f_WVALID -> mm_interconnect_0:hps_0_h2f_axi_master_wvalid
wire [29:0] hps_0_h2f_axi_master_araddr; // hps_0:h2f_ARADDR -> mm_interconnect_0:hps_0_h2f_axi_master_araddr
wire [2:0] hps_0_h2f_axi_master_arprot; // hps_0:h2f_ARPROT -> mm_interconnect_0:hps_0_h2f_axi_master_arprot
wire [2:0] hps_0_h2f_axi_master_awprot; // hps_0:h2f_AWPROT -> mm_interconnect_0:hps_0_h2f_axi_master_awprot
wire [63:0] hps_0_h2f_axi_master_wdata; // hps_0:h2f_WDATA -> mm_interconnect_0:hps_0_h2f_axi_master_wdata
wire hps_0_h2f_axi_master_arvalid; // hps_0:h2f_ARVALID -> mm_interconnect_0:hps_0_h2f_axi_master_arvalid
wire [3:0] hps_0_h2f_axi_master_awcache; // hps_0:h2f_AWCACHE -> mm_interconnect_0:hps_0_h2f_axi_master_awcache
wire [11:0] hps_0_h2f_axi_master_arid; // hps_0:h2f_ARID -> mm_interconnect_0:hps_0_h2f_axi_master_arid
wire [1:0] hps_0_h2f_axi_master_arlock; // hps_0:h2f_ARLOCK -> mm_interconnect_0:hps_0_h2f_axi_master_arlock
wire [1:0] hps_0_h2f_axi_master_awlock; // hps_0:h2f_AWLOCK -> mm_interconnect_0:hps_0_h2f_axi_master_awlock
wire [29:0] hps_0_h2f_axi_master_awaddr; // hps_0:h2f_AWADDR -> mm_interconnect_0:hps_0_h2f_axi_master_awaddr
wire [1:0] hps_0_h2f_axi_master_bresp; // mm_interconnect_0:hps_0_h2f_axi_master_bresp -> hps_0:h2f_BRESP
wire hps_0_h2f_axi_master_arready; // mm_interconnect_0:hps_0_h2f_axi_master_arready -> hps_0:h2f_ARREADY
wire [63:0] hps_0_h2f_axi_master_rdata; // mm_interconnect_0:hps_0_h2f_axi_master_rdata -> hps_0:h2f_RDATA
wire hps_0_h2f_axi_master_awready; // mm_interconnect_0:hps_0_h2f_axi_master_awready -> hps_0:h2f_AWREADY
wire [1:0] hps_0_h2f_axi_master_arburst; // hps_0:h2f_ARBURST -> mm_interconnect_0:hps_0_h2f_axi_master_arburst
wire [2:0] hps_0_h2f_axi_master_arsize; // hps_0:h2f_ARSIZE -> mm_interconnect_0:hps_0_h2f_axi_master_arsize
wire hps_0_h2f_axi_master_bready; // hps_0:h2f_BREADY -> mm_interconnect_0:hps_0_h2f_axi_master_bready
wire hps_0_h2f_axi_master_rlast; // mm_interconnect_0:hps_0_h2f_axi_master_rlast -> hps_0:h2f_RLAST
wire hps_0_h2f_axi_master_wlast; // hps_0:h2f_WLAST -> mm_interconnect_0:hps_0_h2f_axi_master_wlast
wire [1:0] hps_0_h2f_axi_master_rresp; // mm_interconnect_0:hps_0_h2f_axi_master_rresp -> hps_0:h2f_RRESP
wire [11:0] hps_0_h2f_axi_master_awid; // hps_0:h2f_AWID -> mm_interconnect_0:hps_0_h2f_axi_master_awid
wire [11:0] hps_0_h2f_axi_master_bid; // mm_interconnect_0:hps_0_h2f_axi_master_bid -> hps_0:h2f_BID
wire hps_0_h2f_axi_master_bvalid; // mm_interconnect_0:hps_0_h2f_axi_master_bvalid -> hps_0:h2f_BVALID
wire [2:0] hps_0_h2f_axi_master_awsize; // hps_0:h2f_AWSIZE -> mm_interconnect_0:hps_0_h2f_axi_master_awsize
wire hps_0_h2f_axi_master_awvalid; // hps_0:h2f_AWVALID -> mm_interconnect_0:hps_0_h2f_axi_master_awvalid
wire hps_0_h2f_axi_master_rvalid; // mm_interconnect_0:hps_0_h2f_axi_master_rvalid -> hps_0:h2f_RVALID
wire [31:0] fpga_only_master_master_readdata; // mm_interconnect_0:fpga_only_master_master_readdata -> fpga_only_master:master_readdata
wire fpga_only_master_master_waitrequest; // mm_interconnect_0:fpga_only_master_master_waitrequest -> fpga_only_master:master_waitrequest
wire [31:0] fpga_only_master_master_address; // fpga_only_master:master_address -> mm_interconnect_0:fpga_only_master_master_address
wire fpga_only_master_master_read; // fpga_only_master:master_read -> mm_interconnect_0:fpga_only_master_master_read
wire [3:0] fpga_only_master_master_byteenable; // fpga_only_master:master_byteenable -> mm_interconnect_0:fpga_only_master_master_byteenable
wire fpga_only_master_master_readdatavalid; // mm_interconnect_0:fpga_only_master_master_readdatavalid -> fpga_only_master:master_readdatavalid
wire fpga_only_master_master_write; // fpga_only_master:master_write -> mm_interconnect_0:fpga_only_master_master_write
wire [31:0] fpga_only_master_master_writedata; // fpga_only_master:master_writedata -> mm_interconnect_0:fpga_only_master_master_writedata
wire [1:0] hps_0_h2f_lw_axi_master_awburst; // hps_0:h2f_lw_AWBURST -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awburst
wire [3:0] hps_0_h2f_lw_axi_master_arlen; // hps_0:h2f_lw_ARLEN -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arlen
wire [3:0] hps_0_h2f_lw_axi_master_wstrb; // hps_0:h2f_lw_WSTRB -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wstrb
wire hps_0_h2f_lw_axi_master_wready; // mm_interconnect_0:hps_0_h2f_lw_axi_master_wready -> hps_0:h2f_lw_WREADY
wire [11:0] hps_0_h2f_lw_axi_master_rid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rid -> hps_0:h2f_lw_RID
wire hps_0_h2f_lw_axi_master_rready; // hps_0:h2f_lw_RREADY -> mm_interconnect_0:hps_0_h2f_lw_axi_master_rready
wire [3:0] hps_0_h2f_lw_axi_master_awlen; // hps_0:h2f_lw_AWLEN -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awlen
wire [11:0] hps_0_h2f_lw_axi_master_wid; // hps_0:h2f_lw_WID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wid
wire [3:0] hps_0_h2f_lw_axi_master_arcache; // hps_0:h2f_lw_ARCACHE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arcache
wire hps_0_h2f_lw_axi_master_wvalid; // hps_0:h2f_lw_WVALID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wvalid
wire [20:0] hps_0_h2f_lw_axi_master_araddr; // hps_0:h2f_lw_ARADDR -> mm_interconnect_0:hps_0_h2f_lw_axi_master_araddr
wire [2:0] hps_0_h2f_lw_axi_master_arprot; // hps_0:h2f_lw_ARPROT -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arprot
wire [2:0] hps_0_h2f_lw_axi_master_awprot; // hps_0:h2f_lw_AWPROT -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awprot
wire [31:0] hps_0_h2f_lw_axi_master_wdata; // hps_0:h2f_lw_WDATA -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wdata
wire hps_0_h2f_lw_axi_master_arvalid; // hps_0:h2f_lw_ARVALID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arvalid
wire [3:0] hps_0_h2f_lw_axi_master_awcache; // hps_0:h2f_lw_AWCACHE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awcache
wire [11:0] hps_0_h2f_lw_axi_master_arid; // hps_0:h2f_lw_ARID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arid
wire [1:0] hps_0_h2f_lw_axi_master_arlock; // hps_0:h2f_lw_ARLOCK -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arlock
wire [1:0] hps_0_h2f_lw_axi_master_awlock; // hps_0:h2f_lw_AWLOCK -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awlock
wire [20:0] hps_0_h2f_lw_axi_master_awaddr; // hps_0:h2f_lw_AWADDR -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awaddr
wire [1:0] hps_0_h2f_lw_axi_master_bresp; // mm_interconnect_0:hps_0_h2f_lw_axi_master_bresp -> hps_0:h2f_lw_BRESP
wire hps_0_h2f_lw_axi_master_arready; // mm_interconnect_0:hps_0_h2f_lw_axi_master_arready -> hps_0:h2f_lw_ARREADY
wire [31:0] hps_0_h2f_lw_axi_master_rdata; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rdata -> hps_0:h2f_lw_RDATA
wire hps_0_h2f_lw_axi_master_awready; // mm_interconnect_0:hps_0_h2f_lw_axi_master_awready -> hps_0:h2f_lw_AWREADY
wire [1:0] hps_0_h2f_lw_axi_master_arburst; // hps_0:h2f_lw_ARBURST -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arburst
wire [2:0] hps_0_h2f_lw_axi_master_arsize; // hps_0:h2f_lw_ARSIZE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arsize
wire hps_0_h2f_lw_axi_master_bready; // hps_0:h2f_lw_BREADY -> mm_interconnect_0:hps_0_h2f_lw_axi_master_bready
wire hps_0_h2f_lw_axi_master_rlast; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rlast -> hps_0:h2f_lw_RLAST
wire hps_0_h2f_lw_axi_master_wlast; // hps_0:h2f_lw_WLAST -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wlast
wire [1:0] hps_0_h2f_lw_axi_master_rresp; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rresp -> hps_0:h2f_lw_RRESP
wire [11:0] hps_0_h2f_lw_axi_master_awid; // hps_0:h2f_lw_AWID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awid
wire [11:0] hps_0_h2f_lw_axi_master_bid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_bid -> hps_0:h2f_lw_BID
wire hps_0_h2f_lw_axi_master_bvalid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_bvalid -> hps_0:h2f_lw_BVALID
wire [2:0] hps_0_h2f_lw_axi_master_awsize; // hps_0:h2f_lw_AWSIZE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awsize
wire hps_0_h2f_lw_axi_master_awvalid; // hps_0:h2f_lw_AWVALID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awvalid
wire hps_0_h2f_lw_axi_master_rvalid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rvalid -> hps_0:h2f_lw_RVALID
wire mm_interconnect_0_onchip_memory2_0_s1_chipselect; // mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
wire [63:0] mm_interconnect_0_onchip_memory2_0_s1_readdata; // onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
wire [12:0] mm_interconnect_0_onchip_memory2_0_s1_address; // mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
wire [7:0] mm_interconnect_0_onchip_memory2_0_s1_byteenable; // mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
wire mm_interconnect_0_onchip_memory2_0_s1_write; // mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
wire [63:0] mm_interconnect_0_onchip_memory2_0_s1_writedata; // mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
wire mm_interconnect_0_onchip_memory2_0_s1_clken; // mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata; // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest; // jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest
wire [0:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
wire [31:0] mm_interconnect_0_intr_capturer_0_avalon_slave_0_readdata; // intr_capturer_0:rddata -> mm_interconnect_0:intr_capturer_0_avalon_slave_0_readdata
wire [0:0] mm_interconnect_0_intr_capturer_0_avalon_slave_0_address; // mm_interconnect_0:intr_capturer_0_avalon_slave_0_address -> intr_capturer_0:addr
wire mm_interconnect_0_intr_capturer_0_avalon_slave_0_read; // mm_interconnect_0:intr_capturer_0_avalon_slave_0_read -> intr_capturer_0:read
wire [31:0] mm_interconnect_0_sysid_qsys_control_slave_readdata; // sysid_qsys:readdata -> mm_interconnect_0:sysid_qsys_control_slave_readdata
wire [0:0] mm_interconnect_0_sysid_qsys_control_slave_address; // mm_interconnect_0:sysid_qsys_control_slave_address -> sysid_qsys:address
wire mm_interconnect_0_reg32_avalon_interface_0_avalon_slave_0_chipselect; // mm_interconnect_0:reg32_avalon_interface_0_avalon_slave_0_chipselect -> reg32_avalon_interface_0:chipselect
wire [31:0] mm_interconnect_0_reg32_avalon_interface_0_avalon_slave_0_readdata; // reg32_avalon_interface_0:readdata -> mm_interconnect_0:reg32_avalon_interface_0_avalon_slave_0_readdata
wire mm_interconnect_0_reg32_avalon_interface_0_avalon_slave_0_read; // mm_interconnect_0:reg32_avalon_interface_0_avalon_slave_0_read -> reg32_avalon_interface_0:read
wire [3:0] mm_interconnect_0_reg32_avalon_interface_0_avalon_slave_0_byteenable; // mm_interconnect_0:reg32_avalon_interface_0_avalon_slave_0_byteenable -> reg32_avalon_interface_0:byteenable
wire mm_interconnect_0_reg32_avalon_interface_0_avalon_slave_0_write; // mm_interconnect_0:reg32_avalon_interface_0_avalon_slave_0_write -> reg32_avalon_interface_0:write
wire [31:0] mm_interconnect_0_reg32_avalon_interface_0_avalon_slave_0_writedata; // mm_interconnect_0:reg32_avalon_interface_0_avalon_slave_0_writedata -> reg32_avalon_interface_0:writedata
wire mm_interconnect_0_rc4_avalon_interface_0_avalon_slave_0_chipselect; // mm_interconnect_0:rc4_avalon_interface_0_avalon_slave_0_chipselect -> rc4_avalon_interface_0:chipselect
wire [31:0] mm_interconnect_0_rc4_avalon_interface_0_avalon_slave_0_readdata; // rc4_avalon_interface_0:readdata -> mm_interconnect_0:rc4_avalon_interface_0_avalon_slave_0_readdata
wire mm_interconnect_0_rc4_avalon_interface_0_avalon_slave_0_read; // mm_interconnect_0:rc4_avalon_interface_0_avalon_slave_0_read -> rc4_avalon_interface_0:read
wire [3:0] mm_interconnect_0_rc4_avalon_interface_0_avalon_slave_0_byteenable; // mm_interconnect_0:rc4_avalon_interface_0_avalon_slave_0_byteenable -> rc4_avalon_interface_0:byteenable
wire mm_interconnect_0_rc4_avalon_interface_0_avalon_slave_0_write; // mm_interconnect_0:rc4_avalon_interface_0_avalon_slave_0_write -> rc4_avalon_interface_0:write
wire [31:0] mm_interconnect_0_rc4_avalon_interface_0_avalon_slave_0_writedata; // mm_interconnect_0:rc4_avalon_interface_0_avalon_slave_0_writedata -> rc4_avalon_interface_0:writedata
wire [31:0] hps_only_master_master_readdata; // mm_interconnect_1:hps_only_master_master_readdata -> hps_only_master:master_readdata
wire hps_only_master_master_waitrequest; // mm_interconnect_1:hps_only_master_master_waitrequest -> hps_only_master:master_waitrequest
wire [31:0] hps_only_master_master_address; // hps_only_master:master_address -> mm_interconnect_1:hps_only_master_master_address
wire hps_only_master_master_read; // hps_only_master:master_read -> mm_interconnect_1:hps_only_master_master_read
wire [3:0] hps_only_master_master_byteenable; // hps_only_master:master_byteenable -> mm_interconnect_1:hps_only_master_master_byteenable
wire hps_only_master_master_readdatavalid; // mm_interconnect_1:hps_only_master_master_readdatavalid -> hps_only_master:master_readdatavalid
wire hps_only_master_master_write; // hps_only_master:master_write -> mm_interconnect_1:hps_only_master_master_write
wire [31:0] hps_only_master_master_writedata; // hps_only_master:master_writedata -> mm_interconnect_1:hps_only_master_master_writedata
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_awburst; // mm_interconnect_1:hps_0_f2h_axi_slave_awburst -> hps_0:f2h_AWBURST
wire [4:0] mm_interconnect_1_hps_0_f2h_axi_slave_awuser; // mm_interconnect_1:hps_0_f2h_axi_slave_awuser -> hps_0:f2h_AWUSER
wire [3:0] mm_interconnect_1_hps_0_f2h_axi_slave_arlen; // mm_interconnect_1:hps_0_f2h_axi_slave_arlen -> hps_0:f2h_ARLEN
wire [15:0] mm_interconnect_1_hps_0_f2h_axi_slave_wstrb; // mm_interconnect_1:hps_0_f2h_axi_slave_wstrb -> hps_0:f2h_WSTRB
wire mm_interconnect_1_hps_0_f2h_axi_slave_wready; // hps_0:f2h_WREADY -> mm_interconnect_1:hps_0_f2h_axi_slave_wready
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_rid; // hps_0:f2h_RID -> mm_interconnect_1:hps_0_f2h_axi_slave_rid
wire mm_interconnect_1_hps_0_f2h_axi_slave_rready; // mm_interconnect_1:hps_0_f2h_axi_slave_rready -> hps_0:f2h_RREADY
wire [3:0] mm_interconnect_1_hps_0_f2h_axi_slave_awlen; // mm_interconnect_1:hps_0_f2h_axi_slave_awlen -> hps_0:f2h_AWLEN
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_wid; // mm_interconnect_1:hps_0_f2h_axi_slave_wid -> hps_0:f2h_WID
wire [3:0] mm_interconnect_1_hps_0_f2h_axi_slave_arcache; // mm_interconnect_1:hps_0_f2h_axi_slave_arcache -> hps_0:f2h_ARCACHE
wire mm_interconnect_1_hps_0_f2h_axi_slave_wvalid; // mm_interconnect_1:hps_0_f2h_axi_slave_wvalid -> hps_0:f2h_WVALID
wire [31:0] mm_interconnect_1_hps_0_f2h_axi_slave_araddr; // mm_interconnect_1:hps_0_f2h_axi_slave_araddr -> hps_0:f2h_ARADDR
wire [2:0] mm_interconnect_1_hps_0_f2h_axi_slave_arprot; // mm_interconnect_1:hps_0_f2h_axi_slave_arprot -> hps_0:f2h_ARPROT
wire [2:0] mm_interconnect_1_hps_0_f2h_axi_slave_awprot; // mm_interconnect_1:hps_0_f2h_axi_slave_awprot -> hps_0:f2h_AWPROT
wire [127:0] mm_interconnect_1_hps_0_f2h_axi_slave_wdata; // mm_interconnect_1:hps_0_f2h_axi_slave_wdata -> hps_0:f2h_WDATA
wire mm_interconnect_1_hps_0_f2h_axi_slave_arvalid; // mm_interconnect_1:hps_0_f2h_axi_slave_arvalid -> hps_0:f2h_ARVALID
wire [3:0] mm_interconnect_1_hps_0_f2h_axi_slave_awcache; // mm_interconnect_1:hps_0_f2h_axi_slave_awcache -> hps_0:f2h_AWCACHE
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_arid; // mm_interconnect_1:hps_0_f2h_axi_slave_arid -> hps_0:f2h_ARID
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_arlock; // mm_interconnect_1:hps_0_f2h_axi_slave_arlock -> hps_0:f2h_ARLOCK
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_awlock; // mm_interconnect_1:hps_0_f2h_axi_slave_awlock -> hps_0:f2h_AWLOCK
wire [31:0] mm_interconnect_1_hps_0_f2h_axi_slave_awaddr; // mm_interconnect_1:hps_0_f2h_axi_slave_awaddr -> hps_0:f2h_AWADDR
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_bresp; // hps_0:f2h_BRESP -> mm_interconnect_1:hps_0_f2h_axi_slave_bresp
wire mm_interconnect_1_hps_0_f2h_axi_slave_arready; // hps_0:f2h_ARREADY -> mm_interconnect_1:hps_0_f2h_axi_slave_arready
wire [127:0] mm_interconnect_1_hps_0_f2h_axi_slave_rdata; // hps_0:f2h_RDATA -> mm_interconnect_1:hps_0_f2h_axi_slave_rdata
wire mm_interconnect_1_hps_0_f2h_axi_slave_awready; // hps_0:f2h_AWREADY -> mm_interconnect_1:hps_0_f2h_axi_slave_awready
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_arburst; // mm_interconnect_1:hps_0_f2h_axi_slave_arburst -> hps_0:f2h_ARBURST
wire [2:0] mm_interconnect_1_hps_0_f2h_axi_slave_arsize; // mm_interconnect_1:hps_0_f2h_axi_slave_arsize -> hps_0:f2h_ARSIZE
wire mm_interconnect_1_hps_0_f2h_axi_slave_bready; // mm_interconnect_1:hps_0_f2h_axi_slave_bready -> hps_0:f2h_BREADY
wire mm_interconnect_1_hps_0_f2h_axi_slave_rlast; // hps_0:f2h_RLAST -> mm_interconnect_1:hps_0_f2h_axi_slave_rlast
wire mm_interconnect_1_hps_0_f2h_axi_slave_wlast; // mm_interconnect_1:hps_0_f2h_axi_slave_wlast -> hps_0:f2h_WLAST
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_rresp; // hps_0:f2h_RRESP -> mm_interconnect_1:hps_0_f2h_axi_slave_rresp
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_awid; // mm_interconnect_1:hps_0_f2h_axi_slave_awid -> hps_0:f2h_AWID
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_bid; // hps_0:f2h_BID -> mm_interconnect_1:hps_0_f2h_axi_slave_bid
wire mm_interconnect_1_hps_0_f2h_axi_slave_bvalid; // hps_0:f2h_BVALID -> mm_interconnect_1:hps_0_f2h_axi_slave_bvalid
wire [2:0] mm_interconnect_1_hps_0_f2h_axi_slave_awsize; // mm_interconnect_1:hps_0_f2h_axi_slave_awsize -> hps_0:f2h_AWSIZE
wire mm_interconnect_1_hps_0_f2h_axi_slave_awvalid; // mm_interconnect_1:hps_0_f2h_axi_slave_awvalid -> hps_0:f2h_AWVALID
wire [4:0] mm_interconnect_1_hps_0_f2h_axi_slave_aruser; // mm_interconnect_1:hps_0_f2h_axi_slave_aruser -> hps_0:f2h_ARUSER
wire mm_interconnect_1_hps_0_f2h_axi_slave_rvalid; // hps_0:f2h_RVALID -> mm_interconnect_1:hps_0_f2h_axi_slave_rvalid
wire [31:0] hps_0_f2h_irq0_irq; // irq_mapper:sender_irq -> hps_0:f2h_irq_p0
wire [31:0] hps_0_f2h_irq1_irq; // irq_mapper_001:sender_irq -> hps_0:f2h_irq_p1
wire [31:0] intr_capturer_0_interrupt_receiver_irq; // irq_mapper_002:sender_irq -> intr_capturer_0:interrupt_in
wire irq_mapper_receiver0_irq; // jtag_uart:av_irq -> [irq_mapper:receiver0_irq, irq_mapper_002:receiver0_irq]
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [intr_capturer_0:rst_n, irq_mapper_002:reset, jtag_uart:rst_n, mm_interconnect_0:fpga_only_master_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_0:onchip_memory2_0_reset1_reset_bridge_in_reset_reset, mm_interconnect_1:hps_only_master_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_1:hps_only_master_master_translator_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rc4_avalon_interface_0:reset_n, reg32_avalon_interface_0:reset_n, rst_translator:in_reset, sysid_qsys:reset_n]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [onchip_memory2_0:reset_req, rst_translator:reset_req_in]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [mm_interconnect_0:hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_1:hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset]
soc_system_fpga_only_master #(
.USE_PLI (0),
.PLI_PORT (50000),
.FIFO_DEPTHS (2)
) fpga_only_master (
.clk_clk (clk_clk), // clk.clk
.clk_reset_reset (~reset_reset_n), // clk_reset.reset
.master_address (fpga_only_master_master_address), // master.address
.master_readdata (fpga_only_master_master_readdata), // .readdata
.master_read (fpga_only_master_master_read), // .read
.master_write (fpga_only_master_master_write), // .write
.master_writedata (fpga_only_master_master_writedata), // .writedata
.master_waitrequest (fpga_only_master_master_waitrequest), // .waitrequest
.master_readdatavalid (fpga_only_master_master_readdatavalid), // .readdatavalid
.master_byteenable (fpga_only_master_master_byteenable), // .byteenable
.master_reset_reset () // master_reset.reset
);
soc_system_hps_0 #(
.F2S_Width (3),
.S2F_Width (2)
) hps_0 (
.f2h_cold_rst_req_n (hps_0_f2h_cold_reset_req_reset_n), // f2h_cold_reset_req.reset_n
.f2h_dbg_rst_req_n (hps_0_f2h_debug_reset_req_reset_n), // f2h_debug_reset_req.reset_n
.f2h_warm_rst_req_n (hps_0_f2h_warm_reset_req_reset_n), // f2h_warm_reset_req.reset_n
.f2h_stm_hwevents (hps_0_f2h_stm_hw_events_stm_hwevents), // f2h_stm_hw_events.stm_hwevents
.mem_a (memory_mem_a), // memory.mem_a
.mem_ba (memory_mem_ba), // .mem_ba
.mem_ck (memory_mem_ck), // .mem_ck
.mem_ck_n (memory_mem_ck_n), // .mem_ck_n
.mem_cke (memory_mem_cke), // .mem_cke
.mem_cs_n (memory_mem_cs_n), // .mem_cs_n
.mem_ras_n (memory_mem_ras_n), // .mem_ras_n
.mem_cas_n (memory_mem_cas_n), // .mem_cas_n
.mem_we_n (memory_mem_we_n), // .mem_we_n
.mem_reset_n (memory_mem_reset_n), // .mem_reset_n
.mem_dq (memory_mem_dq), // .mem_dq
.mem_dqs (memory_mem_dqs), // .mem_dqs
.mem_dqs_n (memory_mem_dqs_n), // .mem_dqs_n
.mem_odt (memory_mem_odt), // .mem_odt
.mem_dm (memory_mem_dm), // .mem_dm
.oct_rzqin (memory_oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_0_hps_io_hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_0_hps_io_hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_0_hps_io_hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_0_hps_io_hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_0_hps_io_hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_0_hps_io_hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_0_hps_io_hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_0_hps_io_hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_0_hps_io_hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_0_hps_io_hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_0_hps_io_hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_0_hps_io_hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_0_hps_io_hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_0_hps_io_hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_sdio_inst_CMD (hps_0_hps_io_hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_0_hps_io_hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_0_hps_io_hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_0_hps_io_hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_0_hps_io_hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_0_hps_io_hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_0_hps_io_hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_0_hps_io_hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_0_hps_io_hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_0_hps_io_hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_0_hps_io_hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_0_hps_io_hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_0_hps_io_hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_0_hps_io_hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_0_hps_io_hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_0_hps_io_hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_0_hps_io_hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_0_hps_io_hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim1_inst_CLK (hps_0_hps_io_hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_0_hps_io_hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_0_hps_io_hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_0_hps_io_hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_0_hps_io_hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_0_hps_io_hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c0_inst_SDA (hps_0_hps_io_hps_io_i2c0_inst_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_i2c0_inst_SCL (hps_0_hps_io_hps_io_i2c0_inst_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_i2c1_inst_SDA (hps_0_hps_io_hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_0_hps_io_hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO09 (hps_0_hps_io_hps_io_gpio_inst_GPIO09), // .hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_0_hps_io_hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_0_hps_io_hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO53 (hps_0_hps_io_hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_0_hps_io_hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_0_hps_io_hps_io_gpio_inst_GPIO61), // .hps_io_gpio_inst_GPIO61
.h2f_rst_n (hps_0_h2f_reset_reset_n), // h2f_reset.reset_n
.h2f_axi_clk (clk_clk), // h2f_axi_clock.clk
.h2f_AWID (hps_0_h2f_axi_master_awid), // h2f_axi_master.awid
.h2f_AWADDR (hps_0_h2f_axi_master_awaddr), // .awaddr
.h2f_AWLEN (hps_0_h2f_axi_master_awlen), // .awlen
.h2f_AWSIZE (hps_0_h2f_axi_master_awsize), // .awsize
.h2f_AWBURST (hps_0_h2f_axi_master_awburst), // .awburst
.h2f_AWLOCK (hps_0_h2f_axi_master_awlock), // .awlock
.h2f_AWCACHE (hps_0_h2f_axi_master_awcache), // .awcache
.h2f_AWPROT (hps_0_h2f_axi_master_awprot), // .awprot
.h2f_AWVALID (hps_0_h2f_axi_master_awvalid), // .awvalid
.h2f_AWREADY (hps_0_h2f_axi_master_awready), // .awready
.h2f_WID (hps_0_h2f_axi_master_wid), // .wid
.h2f_WDATA (hps_0_h2f_axi_master_wdata), // .wdata
.h2f_WSTRB (hps_0_h2f_axi_master_wstrb), // .wstrb
.h2f_WLAST (hps_0_h2f_axi_master_wlast), // .wlast
.h2f_WVALID (hps_0_h2f_axi_master_wvalid), // .wvalid
.h2f_WREADY (hps_0_h2f_axi_master_wready), // .wready
.h2f_BID (hps_0_h2f_axi_master_bid), // .bid
.h2f_BRESP (hps_0_h2f_axi_master_bresp), // .bresp
.h2f_BVALID (hps_0_h2f_axi_master_bvalid), // .bvalid
.h2f_BREADY (hps_0_h2f_axi_master_bready), // .bready
.h2f_ARID (hps_0_h2f_axi_master_arid), // .arid
.h2f_ARADDR (hps_0_h2f_axi_master_araddr), // .araddr
.h2f_ARLEN (hps_0_h2f_axi_master_arlen), // .arlen
.h2f_ARSIZE (hps_0_h2f_axi_master_arsize), // .arsize
.h2f_ARBURST (hps_0_h2f_axi_master_arburst), // .arburst
.h2f_ARLOCK (hps_0_h2f_axi_master_arlock), // .arlock
.h2f_ARCACHE (hps_0_h2f_axi_master_arcache), // .arcache
.h2f_ARPROT (hps_0_h2f_axi_master_arprot), // .arprot
.h2f_ARVALID (hps_0_h2f_axi_master_arvalid), // .arvalid
.h2f_ARREADY (hps_0_h2f_axi_master_arready), // .arready
.h2f_RID (hps_0_h2f_axi_master_rid), // .rid
.h2f_RDATA (hps_0_h2f_axi_master_rdata), // .rdata
.h2f_RRESP (hps_0_h2f_axi_master_rresp), // .rresp
.h2f_RLAST (hps_0_h2f_axi_master_rlast), // .rlast
.h2f_RVALID (hps_0_h2f_axi_master_rvalid), // .rvalid
.h2f_RREADY (hps_0_h2f_axi_master_rready), // .rready
.f2h_axi_clk (clk_clk), // f2h_axi_clock.clk
.f2h_AWID (mm_interconnect_1_hps_0_f2h_axi_slave_awid), // f2h_axi_slave.awid
.f2h_AWADDR (mm_interconnect_1_hps_0_f2h_axi_slave_awaddr), // .awaddr
.f2h_AWLEN (mm_interconnect_1_hps_0_f2h_axi_slave_awlen), // .awlen
.f2h_AWSIZE (mm_interconnect_1_hps_0_f2h_axi_slave_awsize), // .awsize
.f2h_AWBURST (mm_interconnect_1_hps_0_f2h_axi_slave_awburst), // .awburst
.f2h_AWLOCK (mm_interconnect_1_hps_0_f2h_axi_slave_awlock), // .awlock
.f2h_AWCACHE (mm_interconnect_1_hps_0_f2h_axi_slave_awcache), // .awcache
.f2h_AWPROT (mm_interconnect_1_hps_0_f2h_axi_slave_awprot), // .awprot
.f2h_AWVALID (mm_interconnect_1_hps_0_f2h_axi_slave_awvalid), // .awvalid
.f2h_AWREADY (mm_interconnect_1_hps_0_f2h_axi_slave_awready), // .awready
.f2h_AWUSER (mm_interconnect_1_hps_0_f2h_axi_slave_awuser), // .awuser
.f2h_WID (mm_interconnect_1_hps_0_f2h_axi_slave_wid), // .wid
.f2h_WDATA (mm_interconnect_1_hps_0_f2h_axi_slave_wdata), // .wdata
.f2h_WSTRB (mm_interconnect_1_hps_0_f2h_axi_slave_wstrb), // .wstrb
.f2h_WLAST (mm_interconnect_1_hps_0_f2h_axi_slave_wlast), // .wlast
.f2h_WVALID (mm_interconnect_1_hps_0_f2h_axi_slave_wvalid), // .wvalid
.f2h_WREADY (mm_interconnect_1_hps_0_f2h_axi_slave_wready), // .wready
.f2h_BID (mm_interconnect_1_hps_0_f2h_axi_slave_bid), // .bid
.f2h_BRESP (mm_interconnect_1_hps_0_f2h_axi_slave_bresp), // .bresp
.f2h_BVALID (mm_interconnect_1_hps_0_f2h_axi_slave_bvalid), // .bvalid
.f2h_BREADY (mm_interconnect_1_hps_0_f2h_axi_slave_bready), // .bready
.f2h_ARID (mm_interconnect_1_hps_0_f2h_axi_slave_arid), // .arid
.f2h_ARADDR (mm_interconnect_1_hps_0_f2h_axi_slave_araddr), // .araddr
.f2h_ARLEN (mm_interconnect_1_hps_0_f2h_axi_slave_arlen), // .arlen
.f2h_ARSIZE (mm_interconnect_1_hps_0_f2h_axi_slave_arsize), // .arsize
.f2h_ARBURST (mm_interconnect_1_hps_0_f2h_axi_slave_arburst), // .arburst
.f2h_ARLOCK (mm_interconnect_1_hps_0_f2h_axi_slave_arlock), // .arlock
.f2h_ARCACHE (mm_interconnect_1_hps_0_f2h_axi_slave_arcache), // .arcache
.f2h_ARPROT (mm_interconnect_1_hps_0_f2h_axi_slave_arprot), // .arprot
.f2h_ARVALID (mm_interconnect_1_hps_0_f2h_axi_slave_arvalid), // .arvalid
.f2h_ARREADY (mm_interconnect_1_hps_0_f2h_axi_slave_arready), // .arready
.f2h_ARUSER (mm_interconnect_1_hps_0_f2h_axi_slave_aruser), // .aruser
.f2h_RID (mm_interconnect_1_hps_0_f2h_axi_slave_rid), // .rid
.f2h_RDATA (mm_interconnect_1_hps_0_f2h_axi_slave_rdata), // .rdata
.f2h_RRESP (mm_interconnect_1_hps_0_f2h_axi_slave_rresp), // .rresp
.f2h_RLAST (mm_interconnect_1_hps_0_f2h_axi_slave_rlast), // .rlast
.f2h_RVALID (mm_interconnect_1_hps_0_f2h_axi_slave_rvalid), // .rvalid
.f2h_RREADY (mm_interconnect_1_hps_0_f2h_axi_slave_rready), // .rready
.h2f_lw_axi_clk (clk_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (hps_0_h2f_lw_axi_master_awid), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.h2f_lw_AWLEN (hps_0_h2f_lw_axi_master_awlen), // .awlen
.h2f_lw_AWSIZE (hps_0_h2f_lw_axi_master_awsize), // .awsize
.h2f_lw_AWBURST (hps_0_h2f_lw_axi_master_awburst), // .awburst
.h2f_lw_AWLOCK (hps_0_h2f_lw_axi_master_awlock), // .awlock
.h2f_lw_AWCACHE (hps_0_h2f_lw_axi_master_awcache), // .awcache
.h2f_lw_AWPROT (hps_0_h2f_lw_axi_master_awprot), // .awprot
.h2f_lw_AWVALID (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.h2f_lw_AWREADY (hps_0_h2f_lw_axi_master_awready), // .awready
.h2f_lw_WID (hps_0_h2f_lw_axi_master_wid), // .wid
.h2f_lw_WDATA (hps_0_h2f_lw_axi_master_wdata), // .wdata
.h2f_lw_WSTRB (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.h2f_lw_WLAST (hps_0_h2f_lw_axi_master_wlast), // .wlast
.h2f_lw_WVALID (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.h2f_lw_WREADY (hps_0_h2f_lw_axi_master_wready), // .wready
.h2f_lw_BID (hps_0_h2f_lw_axi_master_bid), // .bid
.h2f_lw_BRESP (hps_0_h2f_lw_axi_master_bresp), // .bresp
.h2f_lw_BVALID (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.h2f_lw_BREADY (hps_0_h2f_lw_axi_master_bready), // .bready
.h2f_lw_ARID (hps_0_h2f_lw_axi_master_arid), // .arid
.h2f_lw_ARADDR (hps_0_h2f_lw_axi_master_araddr), // .araddr
.h2f_lw_ARLEN (hps_0_h2f_lw_axi_master_arlen), // .arlen
.h2f_lw_ARSIZE (hps_0_h2f_lw_axi_master_arsize), // .arsize
.h2f_lw_ARBURST (hps_0_h2f_lw_axi_master_arburst), // .arburst
.h2f_lw_ARLOCK (hps_0_h2f_lw_axi_master_arlock), // .arlock
.h2f_lw_ARCACHE (hps_0_h2f_lw_axi_master_arcache), // .arcache
.h2f_lw_ARPROT (hps_0_h2f_lw_axi_master_arprot), // .arprot
.h2f_lw_ARVALID (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.h2f_lw_ARREADY (hps_0_h2f_lw_axi_master_arready), // .arready
.h2f_lw_RID (hps_0_h2f_lw_axi_master_rid), // .rid
.h2f_lw_RDATA (hps_0_h2f_lw_axi_master_rdata), // .rdata
.h2f_lw_RRESP (hps_0_h2f_lw_axi_master_rresp), // .rresp
.h2f_lw_RLAST (hps_0_h2f_lw_axi_master_rlast), // .rlast
.h2f_lw_RVALID (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.h2f_lw_RREADY (hps_0_h2f_lw_axi_master_rready), // .rready
.f2h_irq_p0 (hps_0_f2h_irq0_irq), // f2h_irq0.irq
.f2h_irq_p1 (hps_0_f2h_irq1_irq) // f2h_irq1.irq
);
soc_system_fpga_only_master #(
.USE_PLI (0),
.PLI_PORT (50000),
.FIFO_DEPTHS (2)
) hps_only_master (
.clk_clk (clk_clk), // clk.clk
.clk_reset_reset (~reset_reset_n), // clk_reset.reset
.master_address (hps_only_master_master_address), // master.address
.master_readdata (hps_only_master_master_readdata), // .readdata
.master_read (hps_only_master_master_read), // .read
.master_write (hps_only_master_master_write), // .write
.master_writedata (hps_only_master_master_writedata), // .writedata
.master_waitrequest (hps_only_master_master_waitrequest), // .waitrequest
.master_readdatavalid (hps_only_master_master_readdatavalid), // .readdatavalid
.master_byteenable (hps_only_master_master_byteenable), // .byteenable
.master_reset_reset () // master_reset.reset
);
intr_capturer #(
.NUM_INTR (32)
) intr_capturer_0 (
.clk (clk_clk), // clock.clk
.rst_n (~rst_controller_reset_out_reset), // reset_sink.reset_n
.addr (mm_interconnect_0_intr_capturer_0_avalon_slave_0_address), // avalon_slave_0.address
.read (mm_interconnect_0_intr_capturer_0_avalon_slave_0_read), // .read
.rddata (mm_interconnect_0_intr_capturer_0_avalon_slave_0_readdata), // .readdata
.interrupt_in (intr_capturer_0_interrupt_receiver_irq) // interrupt_receiver.irq
);
soc_system_jtag_uart jtag_uart (
.clk (clk_clk), // clk.clk
.rst_n (~rst_controller_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver0_irq) // irq.irq
);
soc_system_onchip_memory2_0 onchip_memory2_0 (
.clk (clk_clk), // clk1.clk
.address (mm_interconnect_0_onchip_memory2_0_s1_address), // s1.address
.clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.freeze (1'b0) // (terminated)
);
rc4_avalon_interface rc4_avalon_interface_0 (
.readdata (mm_interconnect_0_rc4_avalon_interface_0_avalon_slave_0_readdata), // avalon_slave_0.readdata
.read (mm_interconnect_0_rc4_avalon_interface_0_avalon_slave_0_read), // .read
.write (mm_interconnect_0_rc4_avalon_interface_0_avalon_slave_0_write), // .write
.writedata (mm_interconnect_0_rc4_avalon_interface_0_avalon_slave_0_writedata), // .writedata
.chipselect (mm_interconnect_0_rc4_avalon_interface_0_avalon_slave_0_chipselect), // .chipselect
.byteenable (mm_interconnect_0_rc4_avalon_interface_0_avalon_slave_0_byteenable), // .byteenable
.clk (clk_clk), // clock.clk
.reset_n (~rst_controller_reset_out_reset) // reset.reset_n
);
reg32_avalon_interface reg32_avalon_interface_0 (
.clk (clk_clk), // clock.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.writedata (mm_interconnect_0_reg32_avalon_interface_0_avalon_slave_0_writedata), // avalon_slave_0.writedata
.readdata (mm_interconnect_0_reg32_avalon_interface_0_avalon_slave_0_readdata), // .readdata
.write (mm_interconnect_0_reg32_avalon_interface_0_avalon_slave_0_write), // .write
.read (mm_interconnect_0_reg32_avalon_interface_0_avalon_slave_0_read), // .read
.chipselect (mm_interconnect_0_reg32_avalon_interface_0_avalon_slave_0_chipselect), // .chipselect
.byteenable (mm_interconnect_0_reg32_avalon_interface_0_avalon_slave_0_byteenable) // .byteenable
);
soc_system_sysid_qsys sysid_qsys (
.clock (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.readdata (mm_interconnect_0_sysid_qsys_control_slave_readdata), // control_slave.readdata
.address (mm_interconnect_0_sysid_qsys_control_slave_address) // .address
);
soc_system_mm_interconnect_0 mm_interconnect_0 (
.hps_0_h2f_axi_master_awid (hps_0_h2f_axi_master_awid), // hps_0_h2f_axi_master.awid
.hps_0_h2f_axi_master_awaddr (hps_0_h2f_axi_master_awaddr), // .awaddr
.hps_0_h2f_axi_master_awlen (hps_0_h2f_axi_master_awlen), // .awlen
.hps_0_h2f_axi_master_awsize (hps_0_h2f_axi_master_awsize), // .awsize
.hps_0_h2f_axi_master_awburst (hps_0_h2f_axi_master_awburst), // .awburst
.hps_0_h2f_axi_master_awlock (hps_0_h2f_axi_master_awlock), // .awlock
.hps_0_h2f_axi_master_awcache (hps_0_h2f_axi_master_awcache), // .awcache
.hps_0_h2f_axi_master_awprot (hps_0_h2f_axi_master_awprot), // .awprot
.hps_0_h2f_axi_master_awvalid (hps_0_h2f_axi_master_awvalid), // .awvalid
.hps_0_h2f_axi_master_awready (hps_0_h2f_axi_master_awready), // .awready
.hps_0_h2f_axi_master_wid (hps_0_h2f_axi_master_wid), // .wid
.hps_0_h2f_axi_master_wdata (hps_0_h2f_axi_master_wdata), // .wdata
.hps_0_h2f_axi_master_wstrb (hps_0_h2f_axi_master_wstrb), // .wstrb
.hps_0_h2f_axi_master_wlast (hps_0_h2f_axi_master_wlast), // .wlast
.hps_0_h2f_axi_master_wvalid (hps_0_h2f_axi_master_wvalid), // .wvalid
.hps_0_h2f_axi_master_wready (hps_0_h2f_axi_master_wready), // .wready
.hps_0_h2f_axi_master_bid (hps_0_h2f_axi_master_bid), // .bid
.hps_0_h2f_axi_master_bresp (hps_0_h2f_axi_master_bresp), // .bresp
.hps_0_h2f_axi_master_bvalid (hps_0_h2f_axi_master_bvalid), // .bvalid
.hps_0_h2f_axi_master_bready (hps_0_h2f_axi_master_bready), // .bready
.hps_0_h2f_axi_master_arid (hps_0_h2f_axi_master_arid), // .arid
.hps_0_h2f_axi_master_araddr (hps_0_h2f_axi_master_araddr), // .araddr
.hps_0_h2f_axi_master_arlen (hps_0_h2f_axi_master_arlen), // .arlen
.hps_0_h2f_axi_master_arsize (hps_0_h2f_axi_master_arsize), // .arsize
.hps_0_h2f_axi_master_arburst (hps_0_h2f_axi_master_arburst), // .arburst
.hps_0_h2f_axi_master_arlock (hps_0_h2f_axi_master_arlock), // .arlock
.hps_0_h2f_axi_master_arcache (hps_0_h2f_axi_master_arcache), // .arcache
.hps_0_h2f_axi_master_arprot (hps_0_h2f_axi_master_arprot), // .arprot
.hps_0_h2f_axi_master_arvalid (hps_0_h2f_axi_master_arvalid), // .arvalid
.hps_0_h2f_axi_master_arready (hps_0_h2f_axi_master_arready), // .arready
.hps_0_h2f_axi_master_rid (hps_0_h2f_axi_master_rid), // .rid
.hps_0_h2f_axi_master_rdata (hps_0_h2f_axi_master_rdata), // .rdata
.hps_0_h2f_axi_master_rresp (hps_0_h2f_axi_master_rresp), // .rresp
.hps_0_h2f_axi_master_rlast (hps_0_h2f_axi_master_rlast), // .rlast
.hps_0_h2f_axi_master_rvalid (hps_0_h2f_axi_master_rvalid), // .rvalid
.hps_0_h2f_axi_master_rready (hps_0_h2f_axi_master_rready), // .rready
.hps_0_h2f_lw_axi_master_awid (hps_0_h2f_lw_axi_master_awid), // hps_0_h2f_lw_axi_master.awid
.hps_0_h2f_lw_axi_master_awaddr (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.hps_0_h2f_lw_axi_master_awlen (hps_0_h2f_lw_axi_master_awlen), // .awlen
.hps_0_h2f_lw_axi_master_awsize (hps_0_h2f_lw_axi_master_awsize), // .awsize
.hps_0_h2f_lw_axi_master_awburst (hps_0_h2f_lw_axi_master_awburst), // .awburst
.hps_0_h2f_lw_axi_master_awlock (hps_0_h2f_lw_axi_master_awlock), // .awlock
.hps_0_h2f_lw_axi_master_awcache (hps_0_h2f_lw_axi_master_awcache), // .awcache
.hps_0_h2f_lw_axi_master_awprot (hps_0_h2f_lw_axi_master_awprot), // .awprot
.hps_0_h2f_lw_axi_master_awvalid (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.hps_0_h2f_lw_axi_master_awready (hps_0_h2f_lw_axi_master_awready), // .awready
.hps_0_h2f_lw_axi_master_wid (hps_0_h2f_lw_axi_master_wid), // .wid
.hps_0_h2f_lw_axi_master_wdata (hps_0_h2f_lw_axi_master_wdata), // .wdata
.hps_0_h2f_lw_axi_master_wstrb (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.hps_0_h2f_lw_axi_master_wlast (hps_0_h2f_lw_axi_master_wlast), // .wlast
.hps_0_h2f_lw_axi_master_wvalid (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.hps_0_h2f_lw_axi_master_wready (hps_0_h2f_lw_axi_master_wready), // .wready
.hps_0_h2f_lw_axi_master_bid (hps_0_h2f_lw_axi_master_bid), // .bid
.hps_0_h2f_lw_axi_master_bresp (hps_0_h2f_lw_axi_master_bresp), // .bresp
.hps_0_h2f_lw_axi_master_bvalid (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.hps_0_h2f_lw_axi_master_bready (hps_0_h2f_lw_axi_master_bready), // .bready
.hps_0_h2f_lw_axi_master_arid (hps_0_h2f_lw_axi_master_arid), // .arid
.hps_0_h2f_lw_axi_master_araddr (hps_0_h2f_lw_axi_master_araddr), // .araddr
.hps_0_h2f_lw_axi_master_arlen (hps_0_h2f_lw_axi_master_arlen), // .arlen
.hps_0_h2f_lw_axi_master_arsize (hps_0_h2f_lw_axi_master_arsize), // .arsize
.hps_0_h2f_lw_axi_master_arburst (hps_0_h2f_lw_axi_master_arburst), // .arburst
.hps_0_h2f_lw_axi_master_arlock (hps_0_h2f_lw_axi_master_arlock), // .arlock
.hps_0_h2f_lw_axi_master_arcache (hps_0_h2f_lw_axi_master_arcache), // .arcache
.hps_0_h2f_lw_axi_master_arprot (hps_0_h2f_lw_axi_master_arprot), // .arprot
.hps_0_h2f_lw_axi_master_arvalid (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.hps_0_h2f_lw_axi_master_arready (hps_0_h2f_lw_axi_master_arready), // .arready
.hps_0_h2f_lw_axi_master_rid (hps_0_h2f_lw_axi_master_rid), // .rid
.hps_0_h2f_lw_axi_master_rdata (hps_0_h2f_lw_axi_master_rdata), // .rdata
.hps_0_h2f_lw_axi_master_rresp (hps_0_h2f_lw_axi_master_rresp), // .rresp
.hps_0_h2f_lw_axi_master_rlast (hps_0_h2f_lw_axi_master_rlast), // .rlast
.hps_0_h2f_lw_axi_master_rvalid (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.hps_0_h2f_lw_axi_master_rready (hps_0_h2f_lw_axi_master_rready), // .rready
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.fpga_only_master_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // fpga_only_master_clk_reset_reset_bridge_in_reset.reset
.hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
.onchip_memory2_0_reset1_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // onchip_memory2_0_reset1_reset_bridge_in_reset.reset
.fpga_only_master_master_address (fpga_only_master_master_address), // fpga_only_master_master.address
.fpga_only_master_master_waitrequest (fpga_only_master_master_waitrequest), // .waitrequest
.fpga_only_master_master_byteenable (fpga_only_master_master_byteenable), // .byteenable
.fpga_only_master_master_read (fpga_only_master_master_read), // .read
.fpga_only_master_master_readdata (fpga_only_master_master_readdata), // .readdata
.fpga_only_master_master_readdatavalid (fpga_only_master_master_readdatavalid), // .readdatavalid
.fpga_only_master_master_write (fpga_only_master_master_write), // .write
.fpga_only_master_master_writedata (fpga_only_master_master_writedata), // .writedata
.intr_capturer_0_avalon_slave_0_address (mm_interconnect_0_intr_capturer_0_avalon_slave_0_address), // intr_capturer_0_avalon_slave_0.address
.intr_capturer_0_avalon_slave_0_read (mm_interconnect_0_intr_capturer_0_avalon_slave_0_read), // .read
.intr_capturer_0_avalon_slave_0_readdata (mm_interconnect_0_intr_capturer_0_avalon_slave_0_readdata), // .readdata
.jtag_uart_avalon_jtag_slave_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // jtag_uart_avalon_jtag_slave.address
.jtag_uart_avalon_jtag_slave_write (mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write
.jtag_uart_avalon_jtag_slave_read (mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read
.jtag_uart_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.jtag_uart_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.jtag_uart_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.jtag_uart_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
.onchip_memory2_0_s1_address (mm_interconnect_0_onchip_memory2_0_s1_address), // onchip_memory2_0_s1.address
.onchip_memory2_0_s1_write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.onchip_memory2_0_s1_readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.onchip_memory2_0_s1_writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.onchip_memory2_0_s1_byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.onchip_memory2_0_s1_chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.onchip_memory2_0_s1_clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.rc4_avalon_interface_0_avalon_slave_0_write (mm_interconnect_0_rc4_avalon_interface_0_avalon_slave_0_write), // rc4_avalon_interface_0_avalon_slave_0.write
.rc4_avalon_interface_0_avalon_slave_0_read (mm_interconnect_0_rc4_avalon_interface_0_avalon_slave_0_read), // .read
.rc4_avalon_interface_0_avalon_slave_0_readdata (mm_interconnect_0_rc4_avalon_interface_0_avalon_slave_0_readdata), // .readdata
.rc4_avalon_interface_0_avalon_slave_0_writedata (mm_interconnect_0_rc4_avalon_interface_0_avalon_slave_0_writedata), // .writedata
.rc4_avalon_interface_0_avalon_slave_0_byteenable (mm_interconnect_0_rc4_avalon_interface_0_avalon_slave_0_byteenable), // .byteenable
.rc4_avalon_interface_0_avalon_slave_0_chipselect (mm_interconnect_0_rc4_avalon_interface_0_avalon_slave_0_chipselect), // .chipselect
.reg32_avalon_interface_0_avalon_slave_0_write (mm_interconnect_0_reg32_avalon_interface_0_avalon_slave_0_write), // reg32_avalon_interface_0_avalon_slave_0.write
.reg32_avalon_interface_0_avalon_slave_0_read (mm_interconnect_0_reg32_avalon_interface_0_avalon_slave_0_read), // .read
.reg32_avalon_interface_0_avalon_slave_0_readdata (mm_interconnect_0_reg32_avalon_interface_0_avalon_slave_0_readdata), // .readdata
.reg32_avalon_interface_0_avalon_slave_0_writedata (mm_interconnect_0_reg32_avalon_interface_0_avalon_slave_0_writedata), // .writedata
.reg32_avalon_interface_0_avalon_slave_0_byteenable (mm_interconnect_0_reg32_avalon_interface_0_avalon_slave_0_byteenable), // .byteenable
.reg32_avalon_interface_0_avalon_slave_0_chipselect (mm_interconnect_0_reg32_avalon_interface_0_avalon_slave_0_chipselect), // .chipselect
.sysid_qsys_control_slave_address (mm_interconnect_0_sysid_qsys_control_slave_address), // sysid_qsys_control_slave.address
.sysid_qsys_control_slave_readdata (mm_interconnect_0_sysid_qsys_control_slave_readdata) // .readdata
);
soc_system_mm_interconnect_1 mm_interconnect_1 (
.hps_0_f2h_axi_slave_awid (mm_interconnect_1_hps_0_f2h_axi_slave_awid), // hps_0_f2h_axi_slave.awid
.hps_0_f2h_axi_slave_awaddr (mm_interconnect_1_hps_0_f2h_axi_slave_awaddr), // .awaddr
.hps_0_f2h_axi_slave_awlen (mm_interconnect_1_hps_0_f2h_axi_slave_awlen), // .awlen
.hps_0_f2h_axi_slave_awsize (mm_interconnect_1_hps_0_f2h_axi_slave_awsize), // .awsize
.hps_0_f2h_axi_slave_awburst (mm_interconnect_1_hps_0_f2h_axi_slave_awburst), // .awburst
.hps_0_f2h_axi_slave_awlock (mm_interconnect_1_hps_0_f2h_axi_slave_awlock), // .awlock
.hps_0_f2h_axi_slave_awcache (mm_interconnect_1_hps_0_f2h_axi_slave_awcache), // .awcache
.hps_0_f2h_axi_slave_awprot (mm_interconnect_1_hps_0_f2h_axi_slave_awprot), // .awprot
.hps_0_f2h_axi_slave_awuser (mm_interconnect_1_hps_0_f2h_axi_slave_awuser), // .awuser
.hps_0_f2h_axi_slave_awvalid (mm_interconnect_1_hps_0_f2h_axi_slave_awvalid), // .awvalid
.hps_0_f2h_axi_slave_awready (mm_interconnect_1_hps_0_f2h_axi_slave_awready), // .awready
.hps_0_f2h_axi_slave_wid (mm_interconnect_1_hps_0_f2h_axi_slave_wid), // .wid
.hps_0_f2h_axi_slave_wdata (mm_interconnect_1_hps_0_f2h_axi_slave_wdata), // .wdata
.hps_0_f2h_axi_slave_wstrb (mm_interconnect_1_hps_0_f2h_axi_slave_wstrb), // .wstrb
.hps_0_f2h_axi_slave_wlast (mm_interconnect_1_hps_0_f2h_axi_slave_wlast), // .wlast
.hps_0_f2h_axi_slave_wvalid (mm_interconnect_1_hps_0_f2h_axi_slave_wvalid), // .wvalid
.hps_0_f2h_axi_slave_wready (mm_interconnect_1_hps_0_f2h_axi_slave_wready), // .wready
.hps_0_f2h_axi_slave_bid (mm_interconnect_1_hps_0_f2h_axi_slave_bid), // .bid
.hps_0_f2h_axi_slave_bresp (mm_interconnect_1_hps_0_f2h_axi_slave_bresp), // .bresp
.hps_0_f2h_axi_slave_bvalid (mm_interconnect_1_hps_0_f2h_axi_slave_bvalid), // .bvalid
.hps_0_f2h_axi_slave_bready (mm_interconnect_1_hps_0_f2h_axi_slave_bready), // .bready
.hps_0_f2h_axi_slave_arid (mm_interconnect_1_hps_0_f2h_axi_slave_arid), // .arid
.hps_0_f2h_axi_slave_araddr (mm_interconnect_1_hps_0_f2h_axi_slave_araddr), // .araddr
.hps_0_f2h_axi_slave_arlen (mm_interconnect_1_hps_0_f2h_axi_slave_arlen), // .arlen
.hps_0_f2h_axi_slave_arsize (mm_interconnect_1_hps_0_f2h_axi_slave_arsize), // .arsize
.hps_0_f2h_axi_slave_arburst (mm_interconnect_1_hps_0_f2h_axi_slave_arburst), // .arburst
.hps_0_f2h_axi_slave_arlock (mm_interconnect_1_hps_0_f2h_axi_slave_arlock), // .arlock
.hps_0_f2h_axi_slave_arcache (mm_interconnect_1_hps_0_f2h_axi_slave_arcache), // .arcache
.hps_0_f2h_axi_slave_arprot (mm_interconnect_1_hps_0_f2h_axi_slave_arprot), // .arprot
.hps_0_f2h_axi_slave_aruser (mm_interconnect_1_hps_0_f2h_axi_slave_aruser), // .aruser
.hps_0_f2h_axi_slave_arvalid (mm_interconnect_1_hps_0_f2h_axi_slave_arvalid), // .arvalid
.hps_0_f2h_axi_slave_arready (mm_interconnect_1_hps_0_f2h_axi_slave_arready), // .arready
.hps_0_f2h_axi_slave_rid (mm_interconnect_1_hps_0_f2h_axi_slave_rid), // .rid
.hps_0_f2h_axi_slave_rdata (mm_interconnect_1_hps_0_f2h_axi_slave_rdata), // .rdata
.hps_0_f2h_axi_slave_rresp (mm_interconnect_1_hps_0_f2h_axi_slave_rresp), // .rresp
.hps_0_f2h_axi_slave_rlast (mm_interconnect_1_hps_0_f2h_axi_slave_rlast), // .rlast
.hps_0_f2h_axi_slave_rvalid (mm_interconnect_1_hps_0_f2h_axi_slave_rvalid), // .rvalid
.hps_0_f2h_axi_slave_rready (mm_interconnect_1_hps_0_f2h_axi_slave_rready), // .rready
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset.reset
.hps_only_master_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // hps_only_master_clk_reset_reset_bridge_in_reset.reset
.hps_only_master_master_translator_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // hps_only_master_master_translator_reset_reset_bridge_in_reset.reset
.hps_only_master_master_address (hps_only_master_master_address), // hps_only_master_master.address
.hps_only_master_master_waitrequest (hps_only_master_master_waitrequest), // .waitrequest
.hps_only_master_master_byteenable (hps_only_master_master_byteenable), // .byteenable
.hps_only_master_master_read (hps_only_master_master_read), // .read
.hps_only_master_master_readdata (hps_only_master_master_readdata), // .readdata
.hps_only_master_master_readdatavalid (hps_only_master_master_readdatavalid), // .readdatavalid
.hps_only_master_master_write (hps_only_master_master_write), // .write
.hps_only_master_master_writedata (hps_only_master_master_writedata) // .writedata
);
soc_system_irq_mapper irq_mapper (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (hps_0_f2h_irq0_irq) // sender.irq
);
soc_system_irq_mapper_001 irq_mapper_001 (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.sender_irq (hps_0_f2h_irq1_irq) // sender.irq
);
soc_system_irq_mapper irq_mapper_002 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (intr_capturer_0_interrupt_receiver_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~hps_0_h2f_reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A311O_SYMBOL_V
`define SKY130_FD_SC_LS__A311O_SYMBOL_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a311o (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A311O_SYMBOL_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIEBus_qpll_reset.v
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : qpll_reset.v
// Description : QPLL Reset Module for 7 Series Transceiver
// Version : 11.4
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- QPLL Reset Module --------------------------------------------------
module PCIEBus_qpll_reset #
(
//---------- Global ------------------------------------
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
parameter PCIE_LANE = 1, // PCIe number of lanes
parameter BYPASS_COARSE_OVRD = 1 // Bypass coarse frequency override
)
(
//---------- Input -------------------------------------
input QRST_CLK,
input QRST_RST_N,
input QRST_MMCM_LOCK,
input [PCIE_LANE-1:0] QRST_CPLLLOCK,
input [(PCIE_LANE-1)>>2:0]QRST_DRP_DONE,
input [(PCIE_LANE-1)>>2:0]QRST_QPLLLOCK,
input [ 1:0] QRST_RATE,
input [PCIE_LANE-1:0] QRST_QPLLRESET_IN,
input [PCIE_LANE-1:0] QRST_QPLLPD_IN,
//---------- Output ------------------------------------
output QRST_OVRD,
output QRST_DRP_START,
output QRST_QPLLRESET_OUT,
output QRST_QPLLPD_OUT,
output QRST_IDLE,
output [ 3:0] QRST_FSM
);
//---------- Input Register ----------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]drp_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]qplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllreset_in_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllpd_in_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]drp_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]qplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllreset_in_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllpd_in_reg2;
//---------- Output Register --------------------------
reg ovrd = 1'd0;
reg qpllreset = 1'd1;
reg qpllpd = 1'd0;
reg [ 3:0] fsm = 2;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 1;
localparam FSM_WAIT_LOCK = 2;
localparam FSM_MMCM_LOCK = 3;
localparam FSM_DRP_START_NOM = 4;
localparam FSM_DRP_DONE_NOM = 5;
localparam FSM_QPLLLOCK = 6;
localparam FSM_DRP_START_OPT = 7;
localparam FSM_DRP_DONE_OPT = 8;
localparam FSM_QPLL_RESET = 9;
localparam FSM_QPLLLOCK2 = 10;
localparam FSM_QPLL_PDRESET = 11;
localparam FSM_QPLL_PD = 12;
//---------- Input FF ----------------------------------------------------------
always @ (posedge QRST_CLK)
begin
if (!QRST_RST_N)
begin
//---------- 1st Stage FF --------------------------
mmcm_lock_reg1 <= 1'd0;
cplllock_reg1 <= {PCIE_LANE{1'd1}};
drp_done_reg1 <= {(((PCIE_LANE-1)>>2)+1){1'd0}};
qplllock_reg1 <= {(((PCIE_LANE-1)>>2)+1){1'd0}};
rate_reg1 <= 2'd0;
qpllreset_in_reg1 <= {PCIE_LANE{1'd1}};
qpllpd_in_reg1 <= {PCIE_LANE{1'd0}};
//---------- 2nd Stage FF --------------------------
mmcm_lock_reg2 <= 1'd0;
cplllock_reg2 <= {PCIE_LANE{1'd1}};
drp_done_reg2 <= {(((PCIE_LANE-1)>>2)+1){1'd0}};
qplllock_reg2 <= {(((PCIE_LANE-1)>>2)+1){1'd0}};
rate_reg2 <= 2'd0;
qpllreset_in_reg2 <= {PCIE_LANE{1'd1}};
qpllpd_in_reg2 <= {PCIE_LANE{1'd0}};
end
else
begin
//---------- 1st Stage FF --------------------------
mmcm_lock_reg1 <= QRST_MMCM_LOCK;
cplllock_reg1 <= QRST_CPLLLOCK;
drp_done_reg1 <= QRST_DRP_DONE;
qplllock_reg1 <= QRST_QPLLLOCK;
rate_reg1 <= QRST_RATE;
qpllreset_in_reg1 <= QRST_QPLLRESET_IN;
qpllpd_in_reg1 <= QRST_QPLLPD_IN;
//---------- 2nd Stage FF --------------------------
mmcm_lock_reg2 <= mmcm_lock_reg1;
cplllock_reg2 <= cplllock_reg1;
drp_done_reg2 <= drp_done_reg1;
qplllock_reg2 <= qplllock_reg1;
rate_reg2 <= rate_reg1;
qpllreset_in_reg2 <= qpllreset_in_reg1;
qpllpd_in_reg2 <= qpllpd_in_reg1;
end
end
//---------- QPLL Reset FSM ----------------------------------------------------
always @ (posedge QRST_CLK)
begin
if (!QRST_RST_N)
begin
fsm <= FSM_WAIT_LOCK;
ovrd <= 1'd0;
qpllreset <= 1'd1;
qpllpd <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
if (!QRST_RST_N)
begin
fsm <= FSM_WAIT_LOCK;
ovrd <= 1'd0;
qpllreset <= 1'd1;
qpllpd <= 1'd0;
end
else
begin
fsm <= FSM_IDLE;
ovrd <= ovrd;
qpllreset <= &qpllreset_in_reg2;
qpllpd <= &qpllpd_in_reg2;
end
end
//---------- Wait for CPLL and QPLL to Lose Lock ---
FSM_WAIT_LOCK :
begin
fsm <= ((&(~cplllock_reg2)) && (&(~qplllock_reg2)) ? FSM_MMCM_LOCK : FSM_WAIT_LOCK);
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Wait for MMCM and CPLL Lock -----------
FSM_MMCM_LOCK :
begin
fsm <= ((mmcm_lock_reg2 && (&cplllock_reg2)) ? FSM_DRP_START_NOM : FSM_MMCM_LOCK);
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Start QPLL DRP for Normal QPLL Lock Mode
FSM_DRP_START_NOM:
begin
fsm <= (&(~drp_done_reg2) ? FSM_DRP_DONE_NOM : FSM_DRP_START_NOM);
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Wait for QPLL DRP Done ----------------
FSM_DRP_DONE_NOM :
begin
fsm <= (&drp_done_reg2 ? FSM_QPLLLOCK : FSM_DRP_DONE_NOM);
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Wait for QPLL Lock --------------------
FSM_QPLLLOCK :
begin
fsm <= (&qplllock_reg2 ? ((BYPASS_COARSE_OVRD == 1) ? FSM_QPLL_PDRESET : FSM_DRP_START_OPT) : FSM_QPLLLOCK);
ovrd <= ovrd;
qpllreset <= 1'd0;
qpllpd <= qpllpd;
end
//---------- Start QPLL DRP for Optimized QPLL Lock Mode
FSM_DRP_START_OPT:
begin
fsm <= (&(~drp_done_reg2) ? FSM_DRP_DONE_OPT : FSM_DRP_START_OPT);
ovrd <= 1'd1;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Wait for QPLL DRP Done ----------------
FSM_DRP_DONE_OPT :
begin
if (&drp_done_reg2)
begin
fsm <= ((PCIE_PLL_SEL == "QPLL") ? FSM_QPLL_RESET : FSM_QPLL_PDRESET);
ovrd <= ovrd;
qpllreset <= (PCIE_PLL_SEL == "QPLL");
qpllpd <= qpllpd;
end
else
begin
fsm <= FSM_DRP_DONE_OPT;
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
end
//---------- Reset QPLL ----------------------------
FSM_QPLL_RESET :
begin
fsm <= (&(~qplllock_reg2) ? FSM_QPLLLOCK2 : FSM_QPLL_RESET);
ovrd <= ovrd;
qpllreset <= 1'd1;
qpllpd <= 1'd0;
end
//---------- Wait for QPLL Lock --------------------
FSM_QPLLLOCK2 :
begin
fsm <= (&qplllock_reg2 ? FSM_IDLE : FSM_QPLLLOCK2);
ovrd <= ovrd;
qpllreset <= 1'd0;
qpllpd <= 1'd0;
end
//---------- Hold QPLL in Reset --------------------
FSM_QPLL_PDRESET :
begin
fsm <= FSM_QPLL_PD;
ovrd <= ovrd;
qpllreset <= (PCIE_PLL_SEL == "CPLL") ? (rate_reg2 != 2'd2) : 1'd0;
qpllpd <= qpllpd;
end
//---------- Power-down QPLL -----------------------
FSM_QPLL_PD :
begin
fsm <= FSM_IDLE;
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= (PCIE_PLL_SEL == "CPLL") ? (rate_reg2 != 2'd2) : 1'd0;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_WAIT_LOCK;
ovrd <= 1'd0;
qpllreset <= 1'd0;
qpllpd <= 1'd0;
end
endcase
end
end
//---------- QPLL Lock Output --------------------------------------------------
assign QRST_OVRD = ovrd;
assign QRST_DRP_START = (fsm == FSM_DRP_START_NOM) || (fsm == FSM_DRP_START_OPT);
assign QRST_QPLLRESET_OUT = qpllreset;
assign QRST_QPLLPD_OUT = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllpd);
assign QRST_IDLE = (fsm == FSM_IDLE);
assign QRST_FSM = fsm;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
///////////////////////////////////////////////////////////////////////////////
// Title : Synchronous FIFO model
// File : sfifo.v
// Author : Frank Bruno
// Created : 14-May-2009
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module generates a Synchronous FIFO
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
// The file below this point is mdifiable by the licensee:
`timescale 1ns / 10ps
module ssi_sfifo
#
(
parameter WIDTH = 32,
parameter DEPTH = 8,
parameter DLOG2 = 3,
parameter AFULL = 3
)
(
input [WIDTH-1:0] data,
input wrreq,
input rdreq,
input clock,
input aclr,
output reg [WIDTH-1:0] q,
output full,
output empty,
output reg [DLOG2-1:0] usedw,
output almost_full
);
reg [WIDTH-1:0] ram[DEPTH-1:0];
reg [DLOG2-1:0] wr_addr;
reg [DLOG2-1:0] rd_addr;
always @(posedge clock, posedge aclr)
if (aclr) begin
usedw <= 'b0;
wr_addr <= 'b0;
rd_addr <= 'b0;
q <= 'b0;
end else begin
case ({wrreq, rdreq})
2'b10: usedw <= usedw + 8'h1;
2'b01: usedw <= usedw - 8'h1;
endcase // case ({wrreq, rdreq})
if (wrreq) ram[wr_addr] <= data;
if (wrreq) wr_addr <= wr_addr + 8'h1;
if (rdreq) begin
rd_addr <= rd_addr + 8'h1;
q <= ram[rd_addr];
end
//q <= ram[rd_addr];
end // else: !if(aclr)
//assign q = ram[rd_addr];
assign full = &usedw;
assign empty = ~|usedw;
assign almost_full = usedw > AFULL;
endmodule // sfifo
|
//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// A settings and readback bus controlled via fifo36 interface
module settings_fifo_ctrl
#(
parameter XPORT_HDR = 1, //extra transport hdr line
parameter PROT_DEST = 0, //protocol framer destination
parameter PROT_HDR = 1, //needs a protocol header?
parameter ACK_SID = 0 //stream ID for packet ACK
)
(
//clock and synchronous reset for all interfaces
input clock, input reset, input clear,
//current system time
input [63:0] vita_time,
//ready signal for multiple peripherals
input perfs_ready,
//input fifo36 interface control
input [35:0] in_data, input in_valid, output in_ready,
//output fifo36 interface status
output [35:0] out_data, output out_valid, input out_ready,
//32-bit settings bus outputs
output strobe, output [7:0] addr, output [31:0] data,
//16X 32-bit inputs for readback
input [31:0] word00,
input [31:0] word01,
input [31:0] word02,
input [31:0] word03,
input [31:0] word04,
input [31:0] word05,
input [31:0] word06,
input [31:0] word07,
input [31:0] word08,
input [31:0] word09,
input [31:0] word10,
input [31:0] word11,
input [31:0] word12,
input [31:0] word13,
input [31:0] word14,
input [31:0] word15,
//debug output
output [31:0] debug
);
wire reading = in_valid && in_ready;
wire writing = out_valid && out_ready;
//------------------------------------------------------------------
//-- The command fifo:
//-- Stores an individual register access command per line.
//------------------------------------------------------------------
wire [63:0] in_command_ticks, out_command_ticks;
wire [31:0] in_command_hdr, out_command_hdr;
wire [31:0] in_command_data, out_command_data;
wire in_command_has_time, out_command_has_time;
wire command_fifo_full, command_fifo_empty;
wire command_fifo_read, command_fifo_write;
shortfifo #(.WIDTH(129)) command_fifo (
.clk(clock), .rst(reset), .clear(clear),
.datain({in_command_ticks, in_command_hdr, in_command_data, in_command_has_time}),
.dataout({out_command_ticks, out_command_hdr, out_command_data, out_command_has_time}),
.write(command_fifo_write), .full(command_fifo_full), //input interface
.empty(command_fifo_empty), .read(command_fifo_read) //output interface
);
//------------------------------------------------------------------
//-- The result fifo:
//-- Stores an individual result of a command per line.
//------------------------------------------------------------------
wire [31:0] in_result_hdr, out_result_hdr;
wire [31:0] in_result_data, out_result_data;
wire result_fifo_full, result_fifo_empty;
wire result_fifo_read, result_fifo_write;
shortfifo #(.WIDTH(64)) result_fifo (
.clk(clock), .rst(reset), .clear(clear),
.datain({in_result_hdr, in_result_data}),
.dataout({out_result_hdr, out_result_data}),
.write(result_fifo_write), .full(result_fifo_full), //input interface
.empty(result_fifo_empty), .read(result_fifo_read) //output interface
);
//------------------------------------------------------------------
//-- Input state machine:
//-- Read input packet and fill a command fifo entry.
//------------------------------------------------------------------
localparam READ_LINE0 = 0;
localparam VITA_HDR = 1;
localparam VITA_SID = 2;
localparam VITA_CID0 = 3;
localparam VITA_CID1 = 4;
localparam VITA_TSI = 5;
localparam VITA_TSF0 = 6;
localparam VITA_TSF1 = 7;
localparam READ_HDR = 8;
localparam READ_DATA = 9;
localparam WAIT_EOF = 10;
localparam STORE_CMD = 11;
localparam START_STATE = (XPORT_HDR)? READ_LINE0 : VITA_HDR;
reg [4:0] in_state;
//holdover from current read inputs
reg [31:0] in_data_reg, in_hdr_reg;
reg [63:0] in_ticks_reg;
wire has_sid = in_data[28];
wire has_cid = in_data[27];
wire has_tsi = in_data[23:22] != 0;
wire has_tsf = in_data[21:20] != 0;
reg has_sid_reg, has_cid_reg, has_tsi_reg, has_tsf_reg;
assign in_ready = (in_state < STORE_CMD);
assign command_fifo_write = (in_state == STORE_CMD);
assign in_command_ticks = in_ticks_reg;
assign in_command_data = in_data_reg;
assign in_command_hdr = in_hdr_reg;
assign in_command_has_time = has_tsf_reg;
always @(posedge clock) begin
if (reset) begin
in_state <= START_STATE;
end
else begin
case (in_state)
READ_LINE0: begin
if (reading) in_state <= VITA_HDR;
end
VITA_HDR: begin
if (reading) begin
if (has_sid) in_state <= VITA_SID;
else if (has_cid) in_state <= VITA_CID0;
else if (has_tsi) in_state <= VITA_TSI;
else if (has_tsf) in_state <= VITA_TSF0;
else in_state <= READ_HDR;
end
has_sid_reg <= has_sid;
has_cid_reg <= has_cid;
has_tsi_reg <= has_tsi;
has_tsf_reg <= has_tsf;
end
VITA_SID: begin
if (reading) begin
if (has_cid_reg) in_state <= VITA_CID0;
else if (has_tsi_reg) in_state <= VITA_TSI;
else if (has_tsf_reg) in_state <= VITA_TSF0;
else in_state <= READ_HDR;
end
end
VITA_CID0: begin
if (reading) in_state <= VITA_CID1;
end
VITA_CID1: begin
if (reading) begin
if (has_tsi_reg) in_state <= VITA_TSI;
else if (has_tsf_reg) in_state <= VITA_TSF0;
else in_state <= READ_HDR;
end
end
VITA_TSI: begin
if (reading) begin
if (has_tsf_reg) in_state <= VITA_TSF0;
else in_state <= READ_HDR;
end
end
VITA_TSF0: begin
if (reading) in_state <= VITA_TSF1;
in_ticks_reg[63:32] <= in_data;
end
VITA_TSF1: begin
if (reading) in_state <= READ_HDR;
in_ticks_reg[31:0] <= in_data;
end
READ_HDR: begin
if (reading) in_state <= READ_DATA;
in_hdr_reg <= in_data[31:0];
end
READ_DATA: begin
if (reading) in_state <= (in_data[33])? STORE_CMD : WAIT_EOF;
in_data_reg <= in_data[31:0];
end
WAIT_EOF: begin
if (reading && in_data[33]) in_state <= STORE_CMD;
end
STORE_CMD: begin
if (~command_fifo_full) in_state <= START_STATE;
end
endcase //in_state
end
end
//------------------------------------------------------------------
//-- Command state machine:
//-- Read a command fifo entry, act on it, produce result.
//------------------------------------------------------------------
localparam LOAD_CMD = 0;
localparam EVENT_CMD = 1;
reg cmd_state;
reg [31:0] rb_data;
reg [63:0] command_ticks_reg;
reg [31:0] command_hdr_reg;
reg [31:0] command_data_reg;
reg [63:0] vita_time_reg;
always @(posedge clock)
vita_time_reg <= vita_time;
wire late;
`ifndef FIFO_CTRL_NO_TIME
time_compare time_compare(
.time_now(vita_time_reg), .trigger_time(command_ticks_reg), .late(late));
`else
assign late = 1;
`endif
//action occurs in the event state and when there is fifo space (should always be true)
//the third condition is that all peripherals in the perfs signal are ready/active high
//the fourth condition is that is an event time has been set, action is delayed until that time
wire time_ready = (out_command_has_time)? late : 1;
wire action = (cmd_state == EVENT_CMD) && ~result_fifo_full && perfs_ready && time_ready;
assign command_fifo_read = action;
assign result_fifo_write = action;
assign in_result_hdr = command_hdr_reg;
assign in_result_data = rb_data;
always @(posedge clock) begin
if (reset) begin
cmd_state <= LOAD_CMD;
end
else begin
case (cmd_state)
LOAD_CMD: begin
if (~command_fifo_empty) cmd_state <= EVENT_CMD;
command_ticks_reg <= out_command_ticks;
command_hdr_reg <= out_command_hdr;
command_data_reg <= out_command_data;
end
EVENT_CMD: begin // poking and peeking happens here!
if (action || clear) cmd_state <= LOAD_CMD;
end
endcase //cmd_state
end
end
//------------------------------------------------------------------
//-- assign to settings bus interface
//------------------------------------------------------------------
reg strobe_reg;
assign strobe = strobe_reg;
assign data = command_data_reg;
assign addr = command_hdr_reg[7:0];
wire poke = command_hdr_reg[8];
always @(posedge clock) begin
if (reset || clear) strobe_reg <= 0;
else strobe_reg <= action && poke;
end
//------------------------------------------------------------------
//-- readback mux
//------------------------------------------------------------------
always @(posedge clock) begin
case (out_command_hdr[3:0])
0 : rb_data <= word00;
1 : rb_data <= word01;
2 : rb_data <= word02;
3 : rb_data <= word03;
4 : rb_data <= word04;
5 : rb_data <= word05;
6 : rb_data <= word06;
7 : rb_data <= word07;
8 : rb_data <= word08;
9 : rb_data <= word09;
10: rb_data <= word10;
11: rb_data <= word11;
12: rb_data <= word12;
13: rb_data <= word13;
14: rb_data <= word14;
15: rb_data <= word15;
endcase // case(addr_reg[3:0])
end
//------------------------------------------------------------------
//-- Output state machine:
//-- Read a command fifo entry, act on it, produce ack packet.
//------------------------------------------------------------------
localparam WRITE_PROT_HDR = 0;
localparam WRITE_VRT_HDR = 1;
localparam WRITE_VRT_SID = 2;
localparam WRITE_RB_HDR = 3;
localparam WRITE_RB_DATA = 4;
//the state for the start of packet condition
localparam WRITE_PKT_HDR = (PROT_HDR)? WRITE_PROT_HDR : WRITE_VRT_HDR;
reg [2:0] out_state;
assign out_valid = ~result_fifo_empty;
assign result_fifo_read = out_data[33] && writing;
always @(posedge clock) begin
if (reset) begin
out_state <= WRITE_PKT_HDR;
end
else if (writing && out_data[33]) begin
out_state <= WRITE_PKT_HDR;
end
else if (writing) begin
out_state <= out_state + 1;
end
end
//------------------------------------------------------------------
//-- assign to output fifo interface
//------------------------------------------------------------------
wire [31:0] prot_hdr;
assign prot_hdr[15:0] = 16; //bytes in proceeding vita packet
assign prot_hdr[16] = 1; //yes frame
assign prot_hdr[18:17] = PROT_DEST;
assign prot_hdr[31:19] = 0; //nothing
reg [31:0] out_data_int;
always @* begin
case (out_state)
WRITE_PROT_HDR: out_data_int <= prot_hdr;
WRITE_VRT_HDR: out_data_int <= {12'b010100000000, out_result_hdr[19:16], 2'b0, prot_hdr[15:2]};
WRITE_VRT_SID: out_data_int <= ACK_SID;
WRITE_RB_HDR: out_data_int <= out_result_hdr;
WRITE_RB_DATA: out_data_int <= out_result_data;
default: out_data_int <= 0;
endcase //state
end
assign out_data[35:34] = 2'b0;
assign out_data[33] = (out_state == WRITE_RB_DATA);
assign out_data[32] = (out_state == WRITE_PKT_HDR);
assign out_data[31:0] = out_data_int;
//------------------------------------------------------------------
//-- debug outputs
//------------------------------------------------------------------
assign debug = {
in_state, out_state, //8
in_valid, in_ready, in_data[33:32], //4
out_valid, out_ready, out_data[33:32], //4
command_fifo_empty, command_fifo_full, //2
command_fifo_read, command_fifo_write, //2
addr, //8
strobe_reg, strobe, poke, out_command_has_time //4
};
endmodule //settings_fifo_ctrl
|
(***********************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA-Rocquencourt & LRI-CNRS-Orsay *)
(* \VV/ *************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(***********************************************************************)
(* $Id$ *)
(**************************************************************)
(* FSetDecide.v *)
(* *)
(* Author: Aaron Bohannon *)
(**************************************************************)
(** This file implements a decision procedure for a certain
class of propositions involving finite sets. *)
Require Import Decidable DecidableTypeEx FSetFacts.
(** First, a version for Weak Sets *)
Module WDecide (E : DecidableType)(Import M : WSfun E).
Module F := FSetFacts.WFacts E M.
(** * Overview
This functor defines the tactic [fsetdec], which will
solve any valid goal of the form
<<
forall s1 ... sn,
forall x1 ... xm,
P1 -> ... -> Pk -> P
>>
where [P]'s are defined by the grammar:
<<
P ::=
| Q
| Empty F
| Subset F F'
| Equal F F'
Q ::=
| E.eq X X'
| In X F
| Q /\ Q'
| Q \/ Q'
| Q -> Q'
| Q <-> Q'
| ~ Q
| True
| False
F ::=
| S
| empty
| singleton X
| add X F
| remove X F
| union F F'
| inter F F'
| diff F F'
X ::= x1 | ... | xm
S ::= s1 | ... | sn
>>
The tactic will also work on some goals that vary slightly from
the above form:
- The variables and hypotheses may be mixed in any order and may
have already been introduced into the context. Moreover,
there may be additional, unrelated hypotheses mixed in (these
will be ignored).
- A conjunction of hypotheses will be handled as easily as
separate hypotheses, i.e., [P1 /\ P2 -> P] can be solved iff
[P1 -> P2 -> P] can be solved.
- [fsetdec] should solve any goal if the FSet-related hypotheses
are contradictory.
- [fsetdec] will first perform any necessary zeta and beta
reductions and will invoke [subst] to eliminate any Coq
equalities between finite sets or their elements.
- If [E.eq] is convertible with Coq's equality, it will not
matter which one is used in the hypotheses or conclusion.
- The tactic can solve goals where the finite sets or set
elements are expressed by Coq terms that are more complicated
than variables. However, non-local definitions are not
expanded, and Coq equalities between non-variable terms are
not used. For example, this goal will be solved:
<<
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g (g x2)) ->
In x1 s1 ->
In (g (g x2)) (f s2)
>>
This one will not be solved:
<<
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g x2) ->
In x1 s1 ->
g x2 = g (g x2) ->
In (g (g x2)) (f s2)
>>
*)
(** * Facts and Tactics for Propositional Logic
These lemmas and tactics are in a module so that they do
not affect the namespace if you import the enclosing
module [Decide]. *)
Module FSetLogicalFacts.
Require Export Decidable.
Require Export Setoid.
(** ** Lemmas and Tactics About Decidable Propositions *)
(** ** Propositional Equivalences Involving Negation
These are all written with the unfolded form of
negation, since I am not sure if setoid rewriting will
always perform conversion. *)
(** ** Tactics for Negations *)
Tactic Notation "fold" "any" "not" :=
repeat (
match goal with
| H: context [?P -> False] |- _ =>
fold (~ P) in H
| |- context [?P -> False] =>
fold (~ P)
end).
(** [push not using db] will pushes all negations to the
leaves of propositions in the goal, using the lemmas in
[db] to assist in checking the decidability of the
propositions involved. If [using db] is omitted, then
[core] will be used. Additional versions are provided
to manipulate the hypotheses or the hypotheses and goal
together.
XXX: This tactic and the similar subsequent ones should
have been defined using [autorewrite]. However, dealing
with multiples rewrite sites and side-conditions is
done more cleverly with the following explicit
analysis of goals. *)
Ltac or_not_l_iff P Q tac :=
(rewrite (or_not_l_iff_1 P Q) by tac) ||
(rewrite (or_not_l_iff_2 P Q) by tac).
Ltac or_not_r_iff P Q tac :=
(rewrite (or_not_r_iff_1 P Q) by tac) ||
(rewrite (or_not_r_iff_2 P Q) by tac).
Ltac or_not_l_iff_in P Q H tac :=
(rewrite (or_not_l_iff_1 P Q) in H by tac) ||
(rewrite (or_not_l_iff_2 P Q) in H by tac).
Ltac or_not_r_iff_in P Q H tac :=
(rewrite (or_not_r_iff_1 P Q) in H by tac) ||
(rewrite (or_not_r_iff_2 P Q) in H by tac).
Tactic Notation "push" "not" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff;
repeat (
match goal with
| |- context [True -> False] => rewrite not_true_iff
| |- context [False -> False] => rewrite not_false_iff
| |- context [(?P -> False) -> False] => rewrite (not_not_iff P) by dec
| |- context [(?P -> False) -> (?Q -> False)] =>
rewrite (contrapositive P Q) by dec
| |- context [(?P -> False) \/ ?Q] => or_not_l_iff P Q dec
| |- context [?P \/ (?Q -> False)] => or_not_r_iff P Q dec
| |- context [(?P -> False) -> ?Q] => rewrite (imp_not_l P Q) by dec
| |- context [?P \/ ?Q -> False] => rewrite (not_or_iff P Q)
| |- context [?P /\ ?Q -> False] => rewrite (not_and_iff P Q)
| |- context [(?P -> ?Q) -> False] => rewrite (not_imp_iff P Q) by dec
end);
fold any not.
Tactic Notation "push" "not" :=
push not using core.
Tactic Notation
"push" "not" "in" "*" "|-" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff in * |-;
repeat (
match goal with
| H: context [True -> False] |- _ => rewrite not_true_iff in H
| H: context [False -> False] |- _ => rewrite not_false_iff in H
| H: context [(?P -> False) -> False] |- _ =>
rewrite (not_not_iff P) in H by dec
| H: context [(?P -> False) -> (?Q -> False)] |- _ =>
rewrite (contrapositive P Q) in H by dec
| H: context [(?P -> False) \/ ?Q] |- _ => or_not_l_iff_in P Q H dec
| H: context [?P \/ (?Q -> False)] |- _ => or_not_r_iff_in P Q H dec
| H: context [(?P -> False) -> ?Q] |- _ =>
rewrite (imp_not_l P Q) in H by dec
| H: context [?P \/ ?Q -> False] |- _ => rewrite (not_or_iff P Q) in H
| H: context [?P /\ ?Q -> False] |- _ => rewrite (not_and_iff P Q) in H
| H: context [(?P -> ?Q) -> False] |- _ =>
rewrite (not_imp_iff P Q) in H by dec
end);
fold any not.
Tactic Notation "push" "not" "in" "*" "|-" :=
push not in * |- using core.
Tactic Notation "push" "not" "in" "*" "using" ident(db) :=
push not using db; push not in * |- using db.
Tactic Notation "push" "not" "in" "*" :=
push not in * using core.
(** A simple test case to see how this works. *)
Lemma test_push : forall P Q R : Prop,
decidable P ->
decidable Q ->
(~ True) ->
(~ False) ->
(~ ~ P) ->
(~ (P /\ Q) -> ~ R) ->
((P /\ Q) \/ ~ R) ->
(~ (P /\ Q) \/ R) ->
(R \/ ~ (P /\ Q)) ->
(~ R \/ (P /\ Q)) ->
(~ P -> R) ->
(~ ((R -> P) \/ (Q -> R))) ->
(~ (P /\ R)) ->
(~ (P -> R)) ->
True.
Proof.
intros. push not in *.
(* note that ~(R->P) remains (since R isnt decidable) *)
tauto.
Qed.
(** [pull not using db] will pull as many negations as
possible toward the top of the propositions in the goal,
using the lemmas in [db] to assist in checking the
decidability of the propositions involved. If [using
db] is omitted, then [core] will be used. Additional
versions are provided to manipulate the hypotheses or
the hypotheses and goal together. *)
Tactic Notation "pull" "not" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff;
repeat (
match goal with
| |- context [True -> False] => rewrite not_true_iff
| |- context [False -> False] => rewrite not_false_iff
| |- context [(?P -> False) -> False] => rewrite (not_not_iff P) by dec
| |- context [(?P -> False) -> (?Q -> False)] =>
rewrite (contrapositive P Q) by dec
| |- context [(?P -> False) \/ ?Q] => or_not_l_iff P Q dec
| |- context [?P \/ (?Q -> False)] => or_not_r_iff P Q dec
| |- context [(?P -> False) -> ?Q] => rewrite (imp_not_l P Q) by dec
| |- context [(?P -> False) /\ (?Q -> False)] =>
rewrite <- (not_or_iff P Q)
| |- context [?P -> ?Q -> False] => rewrite <- (not_and_iff P Q)
| |- context [?P /\ (?Q -> False)] => rewrite <- (not_imp_iff P Q) by dec
| |- context [(?Q -> False) /\ ?P] =>
rewrite <- (not_imp_rev_iff P Q) by dec
end);
fold any not.
Tactic Notation "pull" "not" :=
pull not using core.
Tactic Notation
"pull" "not" "in" "*" "|-" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff in * |-;
repeat (
match goal with
| H: context [True -> False] |- _ => rewrite not_true_iff in H
| H: context [False -> False] |- _ => rewrite not_false_iff in H
| H: context [(?P -> False) -> False] |- _ =>
rewrite (not_not_iff P) in H by dec
| H: context [(?P -> False) -> (?Q -> False)] |- _ =>
rewrite (contrapositive P Q) in H by dec
| H: context [(?P -> False) \/ ?Q] |- _ => or_not_l_iff_in P Q H dec
| H: context [?P \/ (?Q -> False)] |- _ => or_not_r_iff_in P Q H dec
| H: context [(?P -> False) -> ?Q] |- _ =>
rewrite (imp_not_l P Q) in H by dec
| H: context [(?P -> False) /\ (?Q -> False)] |- _ =>
rewrite <- (not_or_iff P Q) in H
| H: context [?P -> ?Q -> False] |- _ =>
rewrite <- (not_and_iff P Q) in H
| H: context [?P /\ (?Q -> False)] |- _ =>
rewrite <- (not_imp_iff P Q) in H by dec
| H: context [(?Q -> False) /\ ?P] |- _ =>
rewrite <- (not_imp_rev_iff P Q) in H by dec
end);
fold any not.
Tactic Notation "pull" "not" "in" "*" "|-" :=
pull not in * |- using core.
Tactic Notation "pull" "not" "in" "*" "using" ident(db) :=
pull not using db; pull not in * |- using db.
Tactic Notation "pull" "not" "in" "*" :=
pull not in * using core.
(** A simple test case to see how this works. *)
Lemma test_pull : forall P Q R : Prop,
decidable P ->
decidable Q ->
(~ True) ->
(~ False) ->
(~ ~ P) ->
(~ (P /\ Q) -> ~ R) ->
((P /\ Q) \/ ~ R) ->
(~ (P /\ Q) \/ R) ->
(R \/ ~ (P /\ Q)) ->
(~ R \/ (P /\ Q)) ->
(~ P -> R) ->
(~ (R -> P) /\ ~ (Q -> R)) ->
(~ P \/ ~ R) ->
(P /\ ~ R) ->
(~ R /\ P) ->
True.
Proof.
intros. pull not in *. tauto.
Qed.
End FSetLogicalFacts.
Import FSetLogicalFacts.
(** * Auxiliary Tactics
Again, these lemmas and tactics are in a module so that
they do not affect the namespace if you import the
enclosing module [Decide]. *)
Module FSetDecideAuxiliary.
(** ** Generic Tactics
We begin by defining a few generic, useful tactics. *)
(** [if t then t1 else t2] executes [t] and, if it does not
fail, then [t1] will be applied to all subgoals
produced. If [t] fails, then [t2] is executed. *)
Tactic Notation
"if" tactic(t)
"then" tactic(t1)
"else" tactic(t2) :=
first [ t; first [ t1 | fail 2 ] | t2 ].
(** [prop P holds by t] succeeds (but does not modify the
goal or context) if the proposition [P] can be proved by
[t] in the current context. Otherwise, the tactic
fails. *)
Tactic Notation "prop" constr(P) "holds" "by" tactic(t) :=
let H := fresh in
assert P as H by t;
clear H.
(** This tactic acts just like [assert ... by ...] but will
fail if the context already contains the proposition. *)
Tactic Notation "assert" "new" constr(e) "by" tactic(t) :=
match goal with
| H: e |- _ => fail 1
| _ => assert e by t
end.
(** [subst++] is similar to [subst] except that
- it never fails (as [subst] does on recursive
equations),
- it substitutes locally defined variable for their
definitions,
- it performs beta reductions everywhere, which may
arise after substituting a locally defined function
for its definition.
*)
Tactic Notation "subst" "++" :=
repeat (
match goal with
| x : _ |- _ => subst x
end);
cbv zeta beta in *.
(** [decompose records] calls [decompose record H] on every
relevant hypothesis [H]. *)
Tactic Notation "decompose" "records" :=
repeat (
match goal with
| H: _ |- _ => progress (decompose record H); clear H
end).
(** ** Discarding Irrelevant Hypotheses
We will want to clear the context of any
non-FSet-related hypotheses in order to increase the
speed of the tactic. To do this, we will need to be
able to decide which are relevant. We do this by making
a simple inductive definition classifying the
propositions of interest. *)
Inductive FSet_elt_Prop : Prop -> Prop :=
| eq_Prop : forall (S : Set) (x y : S),
FSet_elt_Prop (x = y)
| eq_elt_prop : forall x y,
FSet_elt_Prop (E.eq x y)
| In_elt_prop : forall x s,
FSet_elt_Prop (In x s)
| True_elt_prop :
FSet_elt_Prop True
| False_elt_prop :
FSet_elt_Prop False
| conj_elt_prop : forall P Q,
FSet_elt_Prop P ->
FSet_elt_Prop Q ->
FSet_elt_Prop (P /\ Q)
| disj_elt_prop : forall P Q,
FSet_elt_Prop P ->
FSet_elt_Prop Q ->
FSet_elt_Prop (P \/ Q)
| impl_elt_prop : forall P Q,
FSet_elt_Prop P ->
FSet_elt_Prop Q ->
FSet_elt_Prop (P -> Q)
| not_elt_prop : forall P,
FSet_elt_Prop P ->
FSet_elt_Prop (~ P).
Inductive FSet_Prop : Prop -> Prop :=
| elt_FSet_Prop : forall P,
FSet_elt_Prop P ->
FSet_Prop P
| Empty_FSet_Prop : forall s,
FSet_Prop (Empty s)
| Subset_FSet_Prop : forall s1 s2,
FSet_Prop (Subset s1 s2)
| Equal_FSet_Prop : forall s1 s2,
FSet_Prop (Equal s1 s2).
(** Here is the tactic that will throw away hypotheses that
are not useful (for the intended scope of the [fsetdec]
tactic). *)
Hint Constructors FSet_elt_Prop FSet_Prop : FSet_Prop.
Ltac discard_nonFSet :=
decompose records;
repeat (
match goal with
| H : ?P |- _ =>
if prop (FSet_Prop P) holds by
(auto 100 with FSet_Prop)
then fail
else clear H
end).
(** ** Turning Set Operators into Propositional Connectives
The lemmas from [FSetFacts] will be used to break down
set operations into propositional formulas built over
the predicates [In] and [E.eq] applied only to
variables. We are going to use them with [autorewrite].
*)
Hint Rewrite
F.empty_iff F.singleton_iff F.add_iff F.remove_iff
F.union_iff F.inter_iff F.diff_iff
: set_simpl.
(** ** Decidability of FSet Propositions *)
(** [In] is decidable. *)
Lemma dec_In : forall x s,
decidable (In x s).
Proof.
red; intros; generalize (F.mem_iff s x); case (mem x s); intuition.
Qed.
(** [E.eq] is decidable. *)
Lemma dec_eq : forall (x y : E.t),
decidable (E.eq x y).
Proof.
red; intros x y; destruct (E.eq_dec x y); auto.
Qed.
(** The hint database [FSet_decidability] will be given to
the [push_neg] tactic from the module [Negation]. *)
Hint Resolve dec_In dec_eq : FSet_decidability.
(** ** Normalizing Propositions About Equality
We have to deal with the fact that [E.eq] may be
convertible with Coq's equality. Thus, we will find the
following tactics useful to replace one form with the
other everywhere. *)
(** The next tactic, [Logic_eq_to_E_eq], mentions the term
[E.t]; thus, we must ensure that [E.t] is used in favor
of any other convertible but syntactically distinct
term. *)
Ltac change_to_E_t :=
repeat (
match goal with
| H : ?T |- _ =>
progress (change T with E.t in H);
repeat (
match goal with
| J : _ |- _ => progress (change T with E.t in J)
| |- _ => progress (change T with E.t)
end )
end).
(** These two tactics take us from Coq's built-in equality
to [E.eq] (and vice versa) when possible. *)
Ltac Logic_eq_to_E_eq :=
repeat (
match goal with
| H: _ |- _ =>
progress (change (@Logic.eq E.t) with E.eq in H)
| |- _ =>
progress (change (@Logic.eq E.t) with E.eq)
end).
Ltac E_eq_to_Logic_eq :=
repeat (
match goal with
| H: _ |- _ =>
progress (change E.eq with (@Logic.eq E.t) in H)
| |- _ =>
progress (change E.eq with (@Logic.eq E.t))
end).
(** This tactic works like the built-in tactic [subst], but
at the level of set element equality (which may not be
the convertible with Coq's equality). *)
Ltac substFSet :=
repeat (
match goal with
| H: E.eq ?x ?y |- _ => rewrite H in *; clear H
end).
(** ** Considering Decidability of Base Propositions
This tactic adds assertions about the decidability of
[E.eq] and [In] to the context. This is necessary for
the completeness of the [fsetdec] tactic. However, in
order to minimize the cost of proof search, we should be
careful to not add more than we need. Once negations
have been pushed to the leaves of the propositions, we
only need to worry about decidability for those base
propositions that appear in a negated form. *)
Ltac assert_decidability :=
(** We actually don't want these rules to fire if the
syntactic context in the patterns below is trivially
empty, but we'll just do some clean-up at the
afterward. *)
repeat (
match goal with
| H: context [~ E.eq ?x ?y] |- _ =>
assert new (E.eq x y \/ ~ E.eq x y) by (apply dec_eq)
| H: context [~ In ?x ?s] |- _ =>
assert new (In x s \/ ~ In x s) by (apply dec_In)
| |- context [~ E.eq ?x ?y] =>
assert new (E.eq x y \/ ~ E.eq x y) by (apply dec_eq)
| |- context [~ In ?x ?s] =>
assert new (In x s \/ ~ In x s) by (apply dec_In)
end);
(** Now we eliminate the useless facts we added (because
they would likely be very harmful to performance). *)
repeat (
match goal with
| _: ~ ?P, H : ?P \/ ~ ?P |- _ => clear H
end).
(** ** Handling [Empty], [Subset], and [Equal]
This tactic instantiates universally quantified
hypotheses (which arise from the unfolding of [Empty],
[Subset], and [Equal]) for each of the set element
expressions that is involved in some membership or
equality fact. Then it throws away those hypotheses,
which should no longer be needed. *)
Ltac inst_FSet_hypotheses :=
repeat (
match goal with
| H : forall a : E.t, _,
_ : context [ In ?x _ ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ In ?x _ ] =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _,
_ : context [ E.eq ?x _ ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ E.eq ?x _ ] =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _,
_ : context [ E.eq _ ?x ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ E.eq _ ?x ] =>
let P := type of (H x) in
assert new P by (exact (H x))
end);
repeat (
match goal with
| H : forall a : E.t, _ |- _ =>
clear H
end).
(** ** The Core [fsetdec] Auxiliary Tactics *)
(** Here is the crux of the proof search. Recursion through
[intuition]! (This will terminate if I correctly
understand the behavior of [intuition].) *)
Ltac fsetdec_rec :=
try (match goal with
| H: E.eq ?x ?x -> False |- _ => destruct H
end);
(reflexivity ||
contradiction ||
(progress substFSet; intuition fsetdec_rec)).
(** If we add [unfold Empty, Subset, Equal in *; intros;] to
the beginning of this tactic, it will satisfy the same
specification as the [fsetdec] tactic; however, it will
be much slower than necessary without the pre-processing
done by the wrapper tactic [fsetdec]. *)
Ltac fsetdec_body :=
inst_FSet_hypotheses;
autorewrite with set_simpl in *;
push not in * using FSet_decidability;
substFSet;
assert_decidability;
auto using E.eq_refl;
(intuition fsetdec_rec) ||
fail 1
"because the goal is beyond the scope of this tactic".
End FSetDecideAuxiliary.
Import FSetDecideAuxiliary.
(** * The [fsetdec] Tactic
Here is the top-level tactic (the only one intended for
clients of this library). It's specification is given at
the top of the file. *)
Ltac fsetdec :=
(** We first unfold any occurrences of [iff]. *)
unfold iff in *;
(** We fold occurrences of [not] because it is better for
[intros] to leave us with a goal of [~ P] than a goal of
[False]. *)
fold any not; intros;
(** Now we decompose conjunctions, which will allow the
[discard_nonFSet] and [assert_decidability] tactics to
do a much better job. *)
decompose records;
discard_nonFSet;
(** We unfold these defined propositions on finite sets. If
our goal was one of them, then have one more item to
introduce now. *)
unfold Empty, Subset, Equal in *; intros;
(** We now want to get rid of all uses of [=] in favor of
[E.eq]. However, the best way to eliminate a [=] is in
the context is with [subst], so we will try that first.
In fact, we may as well convert uses of [E.eq] into [=]
when possible before we do [subst] so that we can even
more mileage out of it. Then we will convert all
remaining uses of [=] back to [E.eq] when possible. We
use [change_to_E_t] to ensure that we have a canonical
name for set elements, so that [Logic_eq_to_E_eq] will
work properly. *)
change_to_E_t; E_eq_to_Logic_eq; subst++; Logic_eq_to_E_eq;
(** The next optimization is to swap a negated goal with a
negated hypothesis when possible. Any swap will improve
performance by eliminating the total number of
negations, but we will get the maximum benefit if we
swap the goal with a hypotheses mentioning the same set
element, so we try that first. If we reach the fourth
branch below, we attempt any swap. However, to maintain
completeness of this tactic, we can only perform such a
swap with a decidable proposition; hence, we first test
whether the hypothesis is an [FSet_elt_Prop], noting
that any [FSet_elt_Prop] is decidable. *)
pull not using FSet_decidability;
unfold not in *;
match goal with
| H: (In ?x ?r) -> False |- (In ?x ?s) -> False =>
contradict H; fsetdec_body
| H: (In ?x ?r) -> False |- (E.eq ?x ?y) -> False =>
contradict H; fsetdec_body
| H: (In ?x ?r) -> False |- (E.eq ?y ?x) -> False =>
contradict H; fsetdec_body
| H: ?P -> False |- ?Q -> False =>
if prop (FSet_elt_Prop P) holds by
(auto 100 with FSet_Prop)
then (contradict H; fsetdec_body)
else fsetdec_body
| |- _ =>
fsetdec_body
end.
(** * Examples *)
Module FSetDecideTestCases.
Lemma test_eq_trans_1 : forall x y z s,
E.eq x y ->
~ ~ E.eq z y ->
In x s ->
In z s.
Proof. fsetdec. Qed.
Lemma test_eq_trans_2 : forall x y z r s,
In x (singleton y) ->
~ In z r ->
~ ~ In z (add y r) ->
In x s ->
In z s.
Proof. fsetdec. Qed.
Lemma test_eq_neq_trans_1 : forall w x y z s,
E.eq x w ->
~ ~ E.eq x y ->
~ E.eq y z ->
In w s ->
In w (remove z s).
Proof. fsetdec. Qed.
Lemma test_eq_neq_trans_2 : forall w x y z r1 r2 s,
In x (singleton w) ->
~ In x r1 ->
In x (add y r1) ->
In y r2 ->
In y (remove z r2) ->
In w s ->
In w (remove z s).
Proof. fsetdec. Qed.
Lemma test_In_singleton : forall x,
In x (singleton x).
Proof. fsetdec. Qed.
Lemma test_Subset_add_remove : forall x s,
s [<=] (add x (remove x s)).
Proof. fsetdec. Qed.
Lemma test_eq_disjunction : forall w x y z,
In w (add x (add y (singleton z))) ->
E.eq w x \/ E.eq w y \/ E.eq w z.
Proof. fsetdec. Qed.
Lemma test_not_In_disj : forall x y s1 s2 s3 s4,
~ In x (union s1 (union s2 (union s3 (add y s4)))) ->
~ (In x s1 \/ In x s4 \/ E.eq y x).
Proof. fsetdec. Qed.
Lemma test_not_In_conj : forall x y s1 s2 s3 s4,
~ In x (union s1 (union s2 (union s3 (add y s4)))) ->
~ In x s1 /\ ~ In x s4 /\ ~ E.eq y x.
Proof. fsetdec. Qed.
Lemma test_iff_conj : forall a x s s',
(In a s' <-> E.eq x a \/ In a s) ->
(In a s' <-> In a (add x s)).
Proof. fsetdec. Qed.
Lemma test_set_ops_1 : forall x q r s,
(singleton x) [<=] s ->
Empty (union q r) ->
Empty (inter (diff s q) (diff s r)) ->
~ In x s.
Proof. fsetdec. Qed.
Lemma eq_chain_test : forall x1 x2 x3 x4 s1 s2 s3 s4,
Empty s1 ->
In x2 (add x1 s1) ->
In x3 s2 ->
~ In x3 (remove x2 s2) ->
~ In x4 s3 ->
In x4 (add x3 s3) ->
In x1 s4 ->
Subset (add x4 s4) s4.
Proof. fsetdec. Qed.
Lemma test_too_complex : forall x y z r s,
E.eq x y ->
(In x (singleton y) -> r [<=] s) ->
In z r ->
In z s.
Proof.
(** [fsetdec] is not intended to solve this directly. *)
intros until s; intros Heq H Hr; lapply H; fsetdec.
Qed.
Lemma function_test_1 :
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g (g x2)) ->
In x1 s1 ->
In (g (g x2)) (f s2).
Proof. fsetdec. Qed.
Lemma function_test_2 :
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g x2) ->
In x1 s1 ->
g x2 = g (g x2) ->
In (g (g x2)) (f s2).
Proof.
(** [fsetdec] is not intended to solve this directly. *)
intros until 3. intros g_eq. rewrite <- g_eq. fsetdec.
Qed.
End FSetDecideTestCases.
End WDecide.
Require Import FSetInterface.
(** Now comes a special version dedicated to full sets. For this
one, only one argument [(M:S)] is necessary. *)
Module Decide (M : S).
Module D:=OT_as_DT M.E.
Module WD := WDecide D M.
Ltac fsetdec := WD.fsetdec.
End Decide. |
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
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// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 5
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_top,Vivado 2015.1" *)
(* CHECK_LICENSE_TYPE = "design_1_auto_us_2,axi_dwidth_converter_v2_1_top,{}" *)
(* CORE_GENERATION_INFO = "design_1_auto_us_2,axi_dwidth_converter_v2_1_top,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=0,C_S_AXI_ID_WIDTH=1,C_SUPPORTS_ID=0,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_M_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=0,C_FIFO_MODE=0,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_BEATS=16,C_PACKING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_auto_us_2 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
axi_dwidth_converter_v2_1_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(0),
.C_FIFO_MODE(0),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(32'H00000000),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(3'H0),
.s_axi_arregion(4'H0),
.s_axi_arqos(4'H0),
.s_axi_arvalid(1'H0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'H0),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_arvalid(),
.m_axi_arready(1'H0),
.m_axi_rdata(64'H0000000000000000),
.m_axi_rresp(2'H0),
.m_axi_rlast(1'H1),
.m_axi_rvalid(1'H0),
.m_axi_rready()
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRBN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DLRBN_FUNCTIONAL_PP_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_ls__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRBN_FUNCTIONAL_PP_V |
(* * IndPrinciples: Induction Principles *)
(** * 帰納法の原理 *)
(* With the Curry-Howard correspondence and its realization in Coq in
mind, we can now take a deeper look at induction principles. *)
(** Coqにおけるカーリーハワード対応とその実現について、帰納法の原理をより深く探って行きましょう。 *)
Require Export "ProofObjects".
(* ##################################################### *)
(** * Basics *)
(** Every time we declare a new [Inductive] datatype, Coq
automatically generates an _induction principle_ for this type.
This induction principle is a theorem like any other: If [t] is
defined inductively, the corresponding induction principle is
called [t_ind]. Here is the one for natural numbers: *)
(** 新たに[Inductive]なデータ型を宣言するときはいつでも、Coqは自動的にこの型の帰納法の原理 (_induction principle_)を生成します。 型[t]に対応する帰納法の原理は[t_ind]という名前になります。 ここでは自然数に対するものを示します。 *)
Check nat_ind.
(* ===> nat_ind :
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n *)
(* The [induction] tactic is a straightforward wrapper that, at its
core, simply performs [apply t_ind]. To see this more clearly,
let's experiment with directly using [apply nat_ind], instead of
the [induction] tactic, to carry out some proofs. Here, for
example, is an alternate proof of a theorem that we saw in the
[Basics] chapter. *)
(** [induction] タクティックは、基本的には [apply t_ind] の単純なラッパーです。
もっとわかりやすくするために、[induction] タクティックのかわりに [apply nat_ind] を使っていくつかの証明をしてみる実験をしてみましょう。
例えば、[Basics_J] の章で見た定理の別の証明を見てみましょう。 *)
Theorem mult_0_r' : forall n:nat,
n * 0 = 0.
Proof.
apply nat_ind.
- (* n = O *) reflexivity.
- (* n = S n' *) simpl. intros n' IHn'. rewrite -> IHn'.
reflexivity. Qed.
(* This proof is basically the same as the earlier one, but a
few minor differences are worth noting.
First, in the induction step of the proof (the ["S"] case), we
have to do a little bookkeeping manually (the [intros]) that
[induction] does automatically.
Second, we do not introduce [n] into the context before applying
[nat_ind] -- the conclusion of [nat_ind] is a quantified formula,
and [apply] needs this conclusion to exactly match the shape of
the goal state, including the quantifier. The [induction] tactic
works either with a variable in the context or a quantified
variable in the goal.
Third, the [apply] tactic automatically chooses variable names for
us (in the second subgoal, here), whereas [induction] lets us
specify (with the [as...] clause) what names should be used. The
automatic choice is actually a little unfortunate, since it
re-uses the name [n] for a variable that is different from the [n]
in the original theorem. This is why the [Case] annotation is
just [S] -- if we tried to write it out in the more explicit form
that we've been using for most proofs, we'd have to write [n = S
n], which doesn't make a lot of sense! All of these conveniences
make [induction] nicer to use in practice than applying induction
principles like [nat_ind] directly. But it is important to
realize that, modulo this little bit of bookkeeping, applying
[nat_ind] is what we are really doing. *)
(** この証明は基本的には前述のものと同じですが、細かい点で特筆すべき違いがあります。
1つめは、帰納段階の証明(["S"] の場合)において、[induction] が自動でやってくれること([intros])を手作業で行なう必要があることです。
2つめは、[nat_ind] を適用する前にコンテキストに [n] を導入していないことです。
[nat_ind] の結論は限量子を含む式であり、[apply] で使うためにはこの結論と限量子を含んだゴールの形とぴったりと一致する必要があります。
[induction] タクティックはコンテキストにある変数にもゴール内の量子化された変数のどちらにでも使えます。
3つめは、[apply] タクティックは変数名(この場合はサブゴール内で使われる変数名)を自動で選びますが、[induction] は([as ...] 節によって)使う名前を指定できることです。
実際には、この自動選択にはちょっと不都合な点があります。元の定理の [n] とは別の変数として [n] を再利用してしまいます。
これは [Case] 注釈がただの [S] だからです。
ほかの証明で使ってきたように省略しない形で書くと、これは [n = S n] という意味のなさない形になってしまいます。
このようなことがあるため、実際には [nat_ind] のような帰納法の原理を直接適用するよりも、素直に [induction] を使ったほうがよいでしょう。
しかし、ちょっとした例外を除けば実際にやりたいのは [nat_ind] の適用であるということを知っておくことは重要です。 *)
(* **** Exercise: 2 stars (plus_one_r') *)
(** **** 練習問題: ★★ (plus_one_r') *)
(* Complete this proof without using the [induction] tactic. *)
(** [induction] タクティックを使わずに、下記の証明を完成させなさい。 *)
Theorem plus_one_r' : forall n:nat,
n + 1 = S n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Coq generates induction principles for every datatype defined with
[Inductive], including those that aren't recursive. Although of
course we don't need induction to prove properties of
non-recursive datatypes, the idea of an induction principle still
makes sense for them: it gives a way to prove that a property
holds for all values of the type.
These generated principles follow a similar pattern. If we define
a type [t] with constructors [c1] ... [cn], Coq generates a
theorem with this shape:
t_ind : forall P : t -> Prop,
... case for c1 ... ->
... case for c2 ... -> ...
... case for cn ... ->
forall n : t, P n
The specific shape of each case depends on the arguments to the
corresponding constructor. Before trying to write down a general
rule, let's look at some more examples. First, an example where
the constructors take no arguments: *)
(** Coqは[Inductive]によって定義されたあらゆるデータ型に対して帰納法の原理を生成します。その中には、帰納的でないものも含まれます。
(帰納的でないデータ型の性質を証明するために帰納法はもちろん必要ないのですが、帰納法の原理のアイデアは帰納的でないデータ型にたいしても問題なく適用できます。)
このように生成された原理は、似たようなパターンに対しても適用できます。
コンストラクタ [c1] ... [cn] を持った型 [t] を定義すると、Coqは次の形の定理を生成します。
t_ind :
forall P : t -> Prop,
... c1の場合 ... ->
... c2の場合 ... ->
... ->
... cnの場合 ... ->
forall n : t, P n
各場合分けの形は、対応するコンストラクタの引数の数によって決まります。
一般的な規則を紹介する前に、もっと例を見てみましょう。
最初は、コンストラクタが引数を取らない場合です。
*)
Inductive yesno : Type :=
| yes : yesno
| no : yesno.
Check yesno_ind.
(* ===> yesno_ind : forall P : yesno -> Prop,
P yes ->
P no ->
forall y : yesno, P y *)
(* **** Exercise: 1 star, optional (rgb) *)
(** **** 練習問題: ★ , optional (rgb) *)
(** Write out the induction principle that Coq will generate for the
following datatype. Write down your answer on paper or type it
into a comment, and then compare it with what Coq prints. *)
(** 次のデータ型に対してCoqが生成する帰納法の原理を予測しなさい。
紙かまたはコメント中に答えを書いたのち、Coqの出力と比較しなさい。 *)
Inductive rgb : Type :=
| red : rgb
| green : rgb
| blue : rgb.
Check rgb_ind.
(** [] *)
(* Here's another example, this time with one of the constructors
taking some arguments. *)
(** 別の例を見てみましょう。引数を受け取るコンストラクタがある場合です。 *)
Inductive natlist : Type :=
| nnil : natlist
| ncons : nat -> natlist -> natlist.
Check natlist_ind.
(* ===> (modulo a little variable renaming)
natlist_ind :
forall P : natlist -> Prop,
P nnil ->
(forall (n : nat) (l : natlist),
P l -> P (ncons n l)) ->
forall n : natlist, P n *)
(* **** Exercise: 1 star, optional (natlist1) *)
(** **** 練習問題: ★, optional (natlist1) *)
(** Suppose we had written the above definition a little
differently: *)
(** 上記の定義をすこし変えたとしましょう。 *)
Inductive natlist1 : Type :=
| nnil1 : natlist1
| nsnoc1 : natlist1 -> nat -> natlist1.
(* Now what will the induction principle look like? *)
(** このとき、帰納法の原理はどのようになるでしょうか? *)
(** [] *)
(* From these examples, we can extract this general rule:
- The type declaration gives several constructors; each
corresponds to one clause of the induction principle.
- Each constructor [c] takes argument types [a1] ... [an].
- Each [ai] can be either [t] (the datatype we are defining) or
some other type [s].
- The corresponding case of the induction principle says:
- "For all values [x1]...[xn] of types [a1]...[an], if [P]
holds for each of the inductive arguments (each [xi] of type
[t]), then [P] holds for [c x1 ... xn]".
*)
(** これらの例より、一般的な規則を導くことができます。
- 型宣言は複数のコンストラクタを持ち、各コンストラクタが帰納法の原理の各節に対応する。
- 各コンストラクタ [c] は引数 [a1]..[an] を取る。
- [ai] は [t](定義しようとしているデータ型)、もしくは別の型 [s] かのどちらかである。
- 帰納法の原理において各節は以下のことを述べている。
- "型 [a1]...[an] のすべての値 [x1]...[xn] について、各 [x] について [P] が成り立つならば、[c x1 ... xn] についても [P] が成り立つ"
*)
(* **** Exercise: 1 star, optional (byntree_ind) *)
(** **** 練習問題: ★, optional (byntree_ind) *)
(** Write out the induction principle that Coq will generate for the
following datatype. (Again, write down your answer on paper or
type it into a comment, and then compare it with what Coq
prints.) *)
(** 次のデータ型に対してCoqが生成する帰納法の原理を予測しなさい。
もう一度、紙かまたはコメント中に答えを書いたのち、Coqの出力と比較しなさい。 *)
Inductive byntree : Type :=
| bempty : byntree
| bleaf : yesno -> byntree
| nbranch : yesno -> byntree -> byntree -> byntree.
(** [] *)
(* **** Exercise: 1 star, optional (ex_set) *)
(** **** 練習問題: ★, optional (ex_set) *)
(* Here is an induction principle for an inductively defined
set.
ExSet_ind :
forall P : ExSet -> Prop,
(forall b : bool, P (con1 b)) ->
(forall (n : nat) (e : ExSet), P e -> P (con2 n e)) ->
forall e : ExSet, P e
Give an [Inductive] definition of [ExSet]: *)
(** ここに帰納的に定義された集合(set)の定義に対する帰納法の原理があります
ExSet_ind :
forall P : ExSet -> Prop,
(forall b : bool, P (con1 b)) ->
(forall (n : nat) (e : ExSet), P e -> P (con2 n e)) ->
forall e : ExSet, P e
[ExSet]の[Inductive]による帰納的な定義を書きなさい *)
Inductive ExSet : Type :=
(* FILL IN HERE *)
.
(** [] *)
(* * Polymorphism *)
(** * 多相性 *)
(* Next, what about polymorphic datatypes?
The inductive definition of polymorphic lists
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
is very similar to that of [natlist]. The main difference is
that, here, the whole definition is _parameterized_ on a set [X]:
that is, we are defining a _family_ of inductive types [list X],
one for each [X]. (Note that, wherever [list] appears in the body
of the declaration, it is always applied to the parameter [X].)
The induction principle is likewise parameterized on [X]:
list_ind :
forall (X : Type) (P : list X -> Prop),
P [] ->
(forall (x : X) (l : list X), P l -> P (x :: l)) ->
forall l : list X, P l
Note that the _whole_ induction principle is parameterized on
[X]. That is, [list_ind] can be thought of as a polymorphic
function that, when applied to a type [X], gives us back an
induction principle specialized to the type [list X]. *)
(** 次に、多相的なデータ型ではどのようになるでしょうか?
多相的なリストの帰納的定義は [natlist] によく似ています。
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
ここでの主な違いは、定義全体が集合 [X] によってパラメータ化されていることです。
つまり、それぞれの [X] ごとに帰納型 [list X] を定義していることになります。
(定義本体で [list] が登場するときは、常にパラメータ [X] に適用されていることに
注意してください。)
帰納法の原理も同様に [X] によってパラメータ化されます。
list_ind :
forall (X : Type) (P : list X -> Prop),
P [] ->
(forall (x : X) (l : list X), P l -> P (x :: l)) ->
forall l : list X, P l
この全体的な帰納法の原理の形に注目してください。帰納法の原理全体が
[X] によってパラメータ化されています。
別の見方をすると、[list_ind] は多相関数と考えることができます。この関数は、型 [X] が適用されると、[list X] に特化した帰納法の原理を返します。
*)
(* **** Exercise: 1 star (tree) *)
(** **** 練習問題: ★ (tree) *)
(* Write out the induction principle that Coq will generate for
the following datatype. Compare your answer with what Coq
prints. *)
(** 次のデータ型に対してCoqが生成する帰納法の原理を予測しなさい。
答えが書けたら、それをCoqの出力と比較しなさい。 *)
Inductive tree (X:Type) : Type :=
| leaf : X -> tree X
| node : tree X -> tree X -> tree X.
Check tree_ind.
(** [] *)
(* **** Exercise: 1 star, optional (mytype) *)
(** **** 練習問題: ★, optional (mytype) *)
(** Find an inductive definition that gives rise to the
following induction principle: *)
(** 以下の帰納法の原理を生成する帰納的定義を探しなさい。
mytype_ind :
forall (X : Type) (P : mytype X -> Prop),
(forall x : X, P (constr1 X x)) ->
(forall n : nat, P (constr2 X n)) ->
(forall m : mytype X, P m ->
forall n : nat, P (constr3 X m n)) ->
forall m : mytype X, P m
*)
(** [] *)
(* **** Exercise: 1 star, optional (foo) *)
(** **** 練習問題: ★, optional (foo) *)
(* Find an inductive definition that gives rise to the
following induction principle:
(** 以下の帰納法の原理を生成する帰納的定義を探しなさい。
foo_ind :
forall (X Y : Type) (P : foo X Y -> Prop),
(forall x : X, P (bar X Y x)) ->
(forall y : Y, P (baz X Y y)) ->
(forall f1 : nat -> foo X Y,
(forall n : nat, P (f1 n)) -> P (quux X Y f1)) ->
forall f2 : foo X Y, P f2
*)
(** [] *)
(** **** Exercise: 1 star, optional (foo') *)
(** **** 練習問題: ★, optional (foo') *)
(* Consider the following inductive definition: *)
(** 次のような帰納的定義があるとします。 *)
Inductive foo' (X:Type) : Type :=
| C1 : list X -> foo' X -> foo' X
| C2 : foo' X.
(* What induction principle will Coq generate for [foo']? Fill
in the blanks, then check your answer with Coq.)
foo'_ind :
forall (X : Type) (P : foo' X -> Prop),
(forall (l : list X) (f : foo' X),
_______________________ ->
_______________________ ) ->
___________________________________________ ->
forall f : foo' X, ________________________
*)
(** [foo'] に対してCoqはどのような帰納法の原理を生成するでしょうか?
空欄を埋め、Coqの結果と比較しなさい
foo'_ind :
forall (X : Type) (P : foo' X -> Prop),
(forall (l : list X) (f : foo' X),
_______________________ ->
_______________________ ) ->
___________________________________________ ->
forall f : foo' X, ________________________
*)
(** [] *)
(* ##################################################### *)
(* ** Induction Hypotheses *)
(** ** 帰納法の仮定 *)
(* Where does the phrase "induction hypothesis" fit into this story?
The induction principle for numbers
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n
is a generic statement that holds for all propositions
[P] (or rather, strictly speaking, for all families of
propositions [P] indexed by a number [n]). Each time we
use this principle, we are choosing [P] to be a particular
expression of type [nat->Prop].
We can make proofs by induction more explicit by giving
this expression a name. For example, instead of stating
the theorem [mult_0_r] as "[forall n, n * 0 = 0]," we can
write it as "[forall n, P_m0r n]", where [P_m0r] is defined
as... *)
(** この概念において"帰納法の仮定"はどこにあてはまるでしょうか?
数に関する帰納法の原理
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n
は、すべての命題 [P](より正確には数値 n を引数にとる命題 [P] )について成り立つ一般的な文です。
この原理を使うときはいつも、[nat->Prop] という型を持つ式を [P] として選びます。
この式に名前を与えることで、証明をもっと明確にできます。
例えば、[mult_0_r] を"[forall n, n * 0 = 0]"と宣言するかわりに、"[forall n, P_m0r n]"と宣言します。
なお、ここで [P_m0r] は次のように定義されています。
*)
Definition P_m0r (n:nat) : Prop :=
n * 0 = 0.
(* ... or equivalently... *)
(** あるいは・・・ *)
Definition P_m0r' : nat->Prop :=
fun n => n * 0 = 0.
(** でも同じ意味です。 *)
(* Now when we do the proof it is easier to see where [P_m0r]
appears. *)
(** これで、証明する際に [P_m0r] がどこに現れるかが分かりやすくなります。 *)
Theorem mult_0_r'' : forall n:nat,
P_m0r n.
Proof.
apply nat_ind.
- (* n = O *) reflexivity.
- (* n = S n' *)
(* Note the proof state at this point! *)
intros n IHn.
unfold P_m0r in IHn. unfold P_m0r. simpl. apply IHn. Qed.
(* This extra naming step isn't something that we do in
normal proofs, but it is useful to do it explicitly for an example
or two, because it allows us to see exactly what the induction
hypothesis is. If we prove [forall n, P_m0r n] by induction on
[n] (using either [induction] or [apply nat_ind]), we see that the
first subgoal requires us to prove [P_m0r 0] ("[P] holds for
zero"), while the second subgoal requires us to prove [forall n',
P_m0r n' -> P_m0r n' (S n')] (that is "[P] holds of [S n'] if it
holds of [n']" or, more elegantly, "[P] is preserved by [S]").
The _induction hypothesis_ is the premise of this latter
implication -- the assumption that [P] holds of [n'], which we are
allowed to use in proving that [P] holds for [S n']. *)
(** このように名前をつける手順は通常の証明では不要です。
しかし、1つ2つ試してみると、帰納法の仮定がどのようなものなのかが分かりやすくなります。
[forall n, P_m0r n] を [n] による帰納法([induction] か [apply nat_ind] を使う)によって証明しようとすると、最初のサブゴールでは [P_m0r 0]("[P] が0に対して成り立つ")を証明しなければならず、2つめのサブゴールでは [forall n', P_m0r n' -> P_m0r (S n')]("[P] が [n'] について成り立つならば、[P] が [S n'] についても成り立つ"あるいは" [P] が [S] によって保存される")を証明しなければなりません。
帰納法の仮定(_induction hypothesis_)は、2つめの推論の基礎になっています -- [P] が [n'] について成り立つことを仮定することにより、それによって [P] が [S n'] について成り立つことを示すことができます。
*)
(* ##################################################### *)
(* ** More on the [induction] Tactic *)
(** ** [induction] タクティックについてもう少し *)
(** The [induction] tactic actually does even more low-level
bookkeeping for us than we discussed above.
Recall the informal statement of the induction principle for
natural numbers:
- If [P n] is some proposition involving a natural number n, and
we want to show that P holds for _all_ numbers n, we can
reason like this:
- show that [P O] holds
- show that, if [P n'] holds, then so does [P (S n')]
- conclude that [P n] holds for all n.
So, when we begin a proof with [intros n] and then [induction n],
we are first telling Coq to consider a _particular_ [n] (by
introducing it into the context) and then telling it to prove
something about _all_ numbers (by using induction).
What Coq actually does in this situation, internally, is to
"re-generalize" the variable we perform induction on. For
example, in our original proof that [plus] is associative... *)
(** [induction] タクティックは、実はこれまで見てきたような、いささか
低レベルな作業をこなすだけのものではありません。
自然数に関する帰納的な公理の非形式的な記述を思い出してみてください。:
- もし [P n] が数値 n を意味する何かの命題だとして、命題 P が全ての数値 n に
ついて成り立つことを示したい場合は、このような推論を
することができます。:
- [P O] が成り立つことを示す
- もし [P n'] が成り立つなら, [P (S n')] が成り立つことを示す。
- 任意の n について [P n] が成り立つと結論する。
我々が証明を [intros n] で始め、次に [induction n] とすると、
これはCoqに「特定の」 [n] について(それを仮定取り込むことで)考えて
から、その後でそれを帰納法を使って任意の数値にまで推し進めるよう
示していることになります。
このようなときに Coq が内部的に行っていることは、帰納法を適用した変数を
「再一般化( _re-generalize_ )」することです。
例えば、[plus] の結合則を証明するケースでは... *)
Theorem plus_assoc' : forall n m p : nat,
n + (m + p) = (n + m) + p.
Proof.
(* ...we first introduce all 3 variables into the context,
which amounts to saying "Consider an arbitrary [n], [m], and
[p]..." *)
(** ...最初に 3個の変数を全てコンテキストに導入しています。
これはつまり"任意の [n], [m], [p] について考える"という
意味になっています... *)
intros n m p.
(* ...We now use the [induction] tactic to prove [P n] (that
is, [n + (m + p) = (n + m) + p]) for _all_ [n],
and hence also for the particular [n] that is in the context
at the moment. *)
(** ...ここで、[induction] タクティックを使い [P n] (任意の [n] に
ついて [n + (m + p) = (n + m) + p])を証明し、すぐに、
コンテキストにある特定の [n] についても証明します。 *)
induction n as [| n'].
- (* n = O *) reflexivity.
- (* n = S n' *)
(* In the second subgoal generated by [induction] -- the
"inductive step" -- we must prove that [P n'] implies
[P (S n')] for all [n']. The [induction] tactic
automatically introduces [n'] and [P n'] into the context
for us, leaving just [P (S n')] as the goal. *)
(** [induction] が作成した(帰納法の手順とも言うべき)二つ目の
ゴールでは、 [P n'] ならば任意の [n'] で [P (S n')] が成り立つ
ことを証明する必要があります。 この時に [induction] タクティックは
[P (S n')] をゴールにしたまま、自動的に [n'] と [P n'] を
コンテキストに導入してくれます。
*)
simpl. rewrite -> IHn'. reflexivity. Qed.
(* It also works to apply [induction] to a variable that is
quantified in the goal. *)
(** [induction] をゴールにある量化された変数に適用してもかまいません。 *)
Theorem plus_comm' : forall n m : nat,
n + m = m + n.
Proof.
induction n as [| n'].
- (* n = O *) intros m. rewrite <- plus_n_O. reflexivity.
- (* n = S n' *) intros m. simpl. rewrite -> IHn'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(* Note that [induction n] leaves [m] still bound in the goal --
i.e., what we are proving inductively is a statement beginning
with [forall m].
If we do [induction] on a variable that is quantified in the goal
_after_ some other quantifiers, the [induction] tactic will
automatically introduce the variables bound by these quantifiers
into the context. *)
(** [induction n] が [m] をゴールに残したままにしていることに注目してください。
つまり、今証明しようとしている帰納的な性質は、[forall m] で表されて
いるということです。
もし [induction] をゴールにおいて量化された変数に対して他の量化子の後に
適用すると、[induction] タクティックは自動的に変数をその量化子に基づいて
コンテキストに導入します。 *)
Theorem plus_comm'' : forall n m : nat,
n + m = m + n.
Proof.
(* Let's do induction on [m] this time, instead of [n]... *)
(** ここで [n] の代わりに [m] を induction しましょう。... *)
induction m as [| m'].
- (* m = O *) simpl. rewrite <- plus_n_O. reflexivity.
- (* m = S m' *) simpl. rewrite <- IHm'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(** **** Exercise: 1 star, optional (plus_explicit_prop) *)
(** **** 練習問題: ★, optional (plus_explicit_prop) *)
(* Rewrite both [plus_assoc'] and [plus_comm'] and their proofs in
the same style as [mult_0_r''] above -- that is, for each theorem,
give an explicit [Definition] of the proposition being proved by
induction, and state the theorem and proof in terms of this
defined proposition. *)
(** [plus_assoc'] と [plus_comm'] を、その証明とともに上の [mult_0_r''] と
同じスタイルになるよう書き直しなさい。このことは、それぞれの定理が
帰納法で証明された命題に明確な定義を与え、この定義された命題から定理と
証明を示しています。 *)
(* FILL IN HERE *)
(** [] *)
(* ##################################################### *)
(* * Induction Principles in [Prop] *)
(** * 命題に対する帰納法の原理 *)
(** Earlier, we looked in detail at the induction principles that Coq
generates for inductively defined _sets_. The induction
principles for inductively defined _propositions_ like [ev] are a
tiny bit more complicated. As with all induction principles, we
want to use the induction principle on [ev] to prove things by
inductively considering the possible shapes that something in [ev]
can have. Intuitively speaking, however, what we want to prove
are not statements about _evidence_ but statements about
_numbers_: accordingly, we want an induction principle that lets
us prove properties of numbers by induction on evidence.
For example, from what we've said so far, you might expect the
inductive definition of [ev]...
Inductive ev : nat -> Prop :=
| ev_0 : ev 0
| ev_SS : forall n : nat, ev n -> ev (S (S n)).
...to give rise to an induction principle that looks like this...
ev_ind_max : forall P : (forall n : nat, ev n -> Prop),
P O ev_0 ->
(forall (m : nat) (E : ev m),
P m E ->
P (S (S m)) (ev_SS m E)) ->
forall (n : nat) (E : gorgeous n),
P n E
... because:
- Since [ev] is indexed by a number [n] (every [ev] object [E] is
a piece of evidence that some particular number [n] is even),
the proposition [P] is parameterized by both [n] and [E] --
that is, the induction principle can be used to prove
assertions involving both an even number and the evidence that
it is even.
- Since there are two ways of giving evidence of evenness ([ev]
has two constructors), applying the induction principle
generates two subgoals:
- We must prove that [P] holds for [O] and [ev_0].
- We must prove that, whenever [n] is an even number and [E]
is an evidence of its evenness, if [P] holds of [n] and
[E], then it also holds of [S (S n)] and [ev_SS n E].
- If these subgoals can be proved, then the induction principle
tells us that [P] is true for _all_ even numbers [n] and
evidence [E] of their evenness.
This is more flexibility than we normally need or want: it is
giving us a way to prove logical assertions where the assertion
involves properties of some piece of _evidence_ of evenness, while
all we really care about is proving properties of _numbers_ that
are even -- we are interested in assertions about numbers, not
about evidence. It would therefore be more convenient to have an
induction principle for proving propositions [P] that are
parameterized just by [n] and whose conclusion establishes [P] for
all even numbers [n]:
forall P : nat -> Prop,
... ->
forall n : nat,
even n -> P n
For this reason, Coq actually generates the following simplified
induction principle for [ev]: *)
(** TODO!!
*)
Check ev_ind.
(* ===> ev_ind
: forall P : nat -> Prop,
P 0 ->
(forall n : nat, ev n -> P n -> P (S (S n))) ->
forall n : nat,
ev n -> P n *)
(** In particular, Coq has dropped the evidence term [E] as a
parameter of the the proposition [P]. *)
(** In English, [ev_ind] says:
- Suppose, [P] is a property of natural numbers (that is, [P n] is
a [Prop] for every [n]). To show that [P n] holds whenever [n]
is even, it suffices to show:
- [P] holds for [0],
- for any [n], if [n] is even and [P] holds for [n], then [P]
holds for [S (S n)]. *)
(** As expected, we can apply [ev_ind] directly instead of using
[induction]. *)
Theorem ev_ev' : forall n, ev n -> ev' n.
Proof.
apply ev_ind.
- (* ev_0 *)
apply ev'_0.
- (* ev_SS *)
intros m Hm IH.
apply (ev'_sum 2 m).
+ apply ev'_2.
+ apply IH.
Qed.
(** The precise form of an [Inductive] definition can affect the
induction principle Coq generates.
For example, in chapter [IndProp], we defined [<=] as: *)
(* Inductive le : nat -> nat -> Prop :=
| le_n : forall n, le n n
| le_S : forall n m, (le n m) -> (le n (S m)). *)
(** This definition can be streamlined a little by observing that the
left-hand argument [n] is the same everywhere in the definition,
so we can actually make it a "general parameter" to the whole
definition, rather than an argument to each constructor. *)
Inductive le (n:nat) : nat -> Prop :=
| le_n : le n n
| le_S : forall m, (le n m) -> (le n (S m)).
Notation "m <= n" := (le m n).
(** The second one is better, even though it looks less symmetric.
Why? Because it gives us a simpler induction principle. *)
Check le_ind.
(* ===> forall (n : nat) (P : nat -> Prop),
P n ->
(forall m : nat, n <= m -> P m -> P (S m)) ->
forall n0 : nat, n <= n0 -> P n0 *)
(* ####################################################### *)
(* * Formal vs. Informal Proofs by Induction *)
(** 帰納法による、形式的証明 vs 非形式的な証明 *)
(* Question: What is the relation between a formal proof of a
proposition [P] and an informal proof of the same proposition [P]?
Answer: The latter should _teach_ the reader how to produce the
former.
Question: How much detail is needed??
Unfortunately, there is no single right answer; rather, there is a
range of choices.
At one end of the spectrum, we can essentially give the reader the
whole formal proof (i.e., the informal proof amounts to just
transcribing the formal one into words). This gives the reader
the ability to reproduce the formal one for themselves, but it
probably doesn't _teach_ them anything much.
At the other end of the spectrum, we can say "The theorem is true
and you can figure out why for yourself if you think about it hard
enough." This is also not a good teaching strategy, because often
writing the proof requires one or more significant insights into
the thing we're proving, and most readers will give up before they
rediscover all the same insights as we did.
In the middle is the golden mean -- a proof that includes all of
the essential insights (saving the reader the hard part of work
that we went through to find the proof in the first place) and
clear high-level suggestions for the more routine parts to save the
reader from spending too much time reconstructing these
parts (e.g., what the IH says and what must be shown in each case
of an inductive proof), but not so much detail that the main ideas
are obscured.
Another key point: if we're comparing a formal proof of a
proposition [P] and an informal proof of [P], the proposition [P]
doesn't change. That is, formal and informal proofs are _talking
about the same world_ and they _must play by the same rules_. *)
TODO
(** Q: 命題 [P] の形式的な証明と、同じ命題 [P] の非形式的な証明の間にはどのような関係があるのでしょうか?
A: 後者は、読む人に「どのように形式的な証明を導くか」を示すようなものとなっているべきです。
Q: どの程度細かく書く必要があるのですか?
A: この問いに唯一と言えるような解答はありません。回答には選択の幅があります。
その範囲の片方の端は、読み手にただ形式的な証明全体を与えればよいという考えです。つまり非形式的な証明は、形式的な証明をただ単に普通の言葉で書き換えただけ 、ということです。この方法は、読み手に形式的な証明を書かせるための能力を与えることはできますが、それについて何かも「教えてくれる」訳ではありません。
これに対しもう一方の端は、「その定理は真で、頑張ればできるはず」ような記述です。この方法も、「教える」ということに関してはあまりいいやり方とはいえません。なぜなら、証明を記述するときはいつも、今証明しようとしているものの奥深くにまで目を向け考えることが必要とされますが、細かく書きすぎると証明を読む側の人の多くは自分自身の力で同じ思考にたどり着くことなく、あきらめて証明の記述に頼ってしまうでしょう。
一番の答えはその中間にあります。全ての要点をかいつまんだ証明というのは、「かつてあなたが証明をしたときに非常に苦労した部分について、読む人が同じ苦労をしなくて済むようになっている」ようなものです。そしてまた、読み手が同じような苦労を何時間もかけてする必要がないよう、証明の中で使える部品などを高度に示唆するものでなければなりません(例えば、仮定 IH が何を言っているかや、帰納的な証明のどの部分に現れるかなど)。しかし、詳細が少なすぎると、証明の主要なアイデアがうまく伝わりません。
もう一つのキーポイント:もし我々が命題 P の形式的な証明と非形式的な証明について話しているならば、命題 P 自体は何も変わりません。このことは、形式的な証明も非形式的な証明も、同じ「世界」について話をしていて、同じルール(_rule_)に基づいていなければならない、と言うことを意味しています。
*)
(* *** Induction Over an Inductively Defined Set *)
(** *** 帰納的に定義された集合についての帰納法 *)
(* _Template_:
- _Theorem_: <Universally quantified proposition of the form
"For all [n:S], [P(n)]," where [S] is some inductively defined
set.>
_Proof_: By induction on [n].
<one case for each constructor [c] of [S]...>
- Suppose [n = c a1 ... ak], where <...and here we state
the IH for each of the [a]'s that has type [S], if any>.
We must show <...and here we restate [P(c a1 ... ak)]>.
<go on and prove [P(n)] to finish the case...>
- <other cases similarly...> []
_Example_:
- _Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index (S n) l = None].
_Proof_: By induction on [l].
- Suppose [l = []]. We must show, for all numbers [n],
that, if [length [] = n], then [index (S n) [] =
None].
This follows immediately from the definition of [index].
- Suppose [l = x :: l'] for some [x] and [l'], where
[length l' = n'] implies [index (S n') l' = None], for
any number [n']. We must show, for all [n], that, if
[length (x::l') = n] then [index (S n) (x::l') =
None].
Let [n] be a number with [length l = n]. Since
length l = length (x::l') = S (length l'),
it suffices to show that
index (S (length l')) l' = None.
]]
But this follows directly from the induction hypothesis,
picking [n'] to be length [l']. [] *)
(** _Template_:
- 定理: < "For all [n:S], [P(n)],"の形で全量子化された命題。ただし [S] は帰納的に定義された集合。>
証明: [n] についての帰納法で証明する。
<集合 [S] の各コンストラクタ [c] について...>
- [n = c a1 ... ak] と仮定して、<...もし必要なら [S] のそれぞれの要素 [a] についてIHであることをを示す。>ならば
<...ここで再び [P(c a1 ... ak)] を示す> である。
< [P(n)] を証明してこのケースを終わらせる...>
- <他のケースも同様に記述する...> []
_Example_:
- _Theorem_: 任意の集合 [X] 、リスト [l : list X]、 自然数 [n] について、
もし [length l = n] が成り立つなら、[index (S n) l = None] も成り立つ。
_Proof_: [l] についての帰納法で証明する。
- まず、[l = []] と仮定して、任意の [n] でこれが成り立つことを示す。もし length [[] = n] ならば [index (S n) [] = None] 。
これは index の定義から直接導かれる 。
- 次に、 [x] と [l'] において [l = x :: l'] と仮定して、任意の [n'] について
[length l' = n'] ならば [index (S n') l' = None] である時、任意の [n] について、
もし [length (x::l') = n] ならば [index (S n) (x::l') = None] を示す。
[n] を [length l = n] となるような数とすると、
length l = length (x::l') = S (length l'),
これは以下の十分条件である。
index (S (length l')) l' = None.
しかしこれは仮定法の仮定から直接導かれる。
[l'] の length となるような [n'] を選択すればよい。 [] *)
(* *** Induction Over an Inductively Defined Proposition *)
(** *** 帰納的に定義された命題についての帰納法 *)
(** Since inductively defined proof objects are often called
"derivation trees," this form of proof is also known as _induction
on derivations_.
_Template_:
- _Theorem_: <Proposition of the form "[Q -> P]," where [Q] is
some inductively defined proposition (more generally,
"For all [x] [y] [z], [Q x y z -> P x y z]")>
_Proof_: By induction on a derivation of [Q]. <Or, more
generally, "Suppose we are given [x], [y], and [z]. We
show that [Q x y z] implies [P x y z], by induction on a
derivation of [Q x y z]"...>
<one case for each constructor [c] of [Q]...>
- Suppose the final rule used to show [Q] is [c]. Then
<...and here we state the types of all of the [a]'s
together with any equalities that follow from the
definition of the constructor and the IH for each of
the [a]'s that has type [Q], if there are any>. We must
show <...and here we restate [P]>.
<go on and prove [P] to finish the case...>
- <other cases similarly...> []
_Example_
- _Theorem_: The [<=] relation is transitive -- i.e., for all
numbers [n], [m], and [o], if [n <= m] and [m <= o], then
[n <= o].
_Proof_: By induction on a derivation of [m <= o].
- Suppose the final rule used to show [m <= o] is
[le_n]. Then [m = o] and we must show that [n <= m],
which is immediate by hypothesis.
- Suppose the final rule used to show [m <= o] is
[le_S]. Then [o = S o'] for some [o'] with [m <= o'].
We must show that [n <= S o'].
By induction hypothesis, [n <= o'].
But then, by [le_S], [n <= S o']. [] *)
(** 帰納的に定義された証明オブジェクトは、しばしば”導出木”と呼ばれるため、この形の証明は「導出による帰納法( _induction on derivations_ )」として知られています。
_Template_ :
- _Theorem_ : <"[Q -> P]," という形を持った命題。ただし [Q] は帰納的に定義された命題(さらに一般的には、"For all [x] [y] [z], [Q x y z -> P x y z]" という形の命題)>
_Proof_ : [Q] の導出による帰納法で証明する。 <もしくは、さらに一般化して、" [x], [y], [z]を仮定して、[Q x y z] ならば [P x y z] を示す。[Q x y z]の導出による帰納法によって"...>
<各コンストラクタ [c] による値 [Q] について...>
- [Q] が [c] であることを示した最後のルールを仮定して、
<...ここで [a] の全ての型をコンストラクタの定義にある等式と
共に示し、型 [Q] を持つ [a] がIHであることをそれぞれ示す。>
ならば <...ここで再び [P] を示す> である。
<がんばって [P] を証明し、このケースを閉じる...>
- <他のケースも同様に...> []
_Example_
- _Theorem_ : [<=] という関係は推移的である -- すなわち、任意の
数値 [n], [m], [o] について、もし [n <= m] と [m <= o] が成り立つ
ならば [n <= o] である。
_Proof_ : [m <= o] についての帰納法で証明する。
- [m <= o] が [le_n] であることを示した最後のルールであると仮定しましょう。
それにより [m = o] であることとその結果が直接導かれます。
- [m <= o] が [le_S] であることを示した最後のルールであると仮定しましょう。
それにより [m <= o'] を満たす [o'] について [o = S o'] が成り立つ。
帰納法の仮定法より [n <= o'] である。
従って[le_S] より [n <= o] である。 [] *)
(** $Date: 2016-05-26 16:17:19 -0400 (Thu, 26 May 2016) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DFF_P_PP_PG_N_TB_V
`define SKY130_FD_SC_HD__UDP_DFF_P_PP_PG_N_TB_V
/**
* udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__udp_dff_p_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 NOTIFIER = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 NOTIFIER = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 NOTIFIER = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 NOTIFIER = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dut (.D(D), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DFF_P_PP_PG_N_TB_V
|
module ememory # (parameter AW = 32, // address width
parameter PW = 104, // packet width
parameter IDW = 12, // ID width
parameter DEPTH = 65536, // memory depth
parameter NAME = "emem", // instance name
parameter WAIT = 0, // enable random wait
parameter MON = 0 // enable monitor monitor
)
(// clk,reset
input clk,
input nreset,
input [IDW-1:0] coreid,
// incoming read/write
input access_in,
input [PW-1:0] packet_in,
output ready_out, //pushback
// back to mesh (readback data)
output reg access_out,
output [PW-1:0] packet_out,
input ready_in //pushback
);
//derived parameters
localparam DW = AW; //always the same
parameter MAW = $clog2(DEPTH);
//###############
//# LOCAL WIRES
//##############
wire [MAW-1:0] addr;
wire [63:0] din;
wire [63:0] dout;
wire en;
wire mem_rd;
reg [7:0] wen;
reg write_out;
reg [1:0] datamode_out;
reg [4:0] ctrlmode_out;
reg [AW-1:0] dstaddr_out;
wire [AW-1:0] srcaddr_out;
wire [AW-1:0] data_out;
reg [2:0] align_addr;
wire [DW-1:0] din_aligned;
wire [63:0] dout_aligned;
wire ready_random; //TODO: make random
wire ready_all;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [4:0] ctrlmode_in; // From p2e of packet2emesh.v
wire [AW-1:0] data_in; // From p2e of packet2emesh.v
wire [1:0] datamode_in; // From p2e of packet2emesh.v
wire [AW-1:0] dstaddr_in; // From p2e of packet2emesh.v
wire [AW-1:0] srcaddr_in; // From p2e of packet2emesh.v
wire write_in; // From p2e of packet2emesh.v
// End of automatics
packet2emesh #(.AW(AW),
.PW(PW))
p2e (/*AUTOINST*/
// Outputs
.write_in (write_in),
.datamode_in (datamode_in[1:0]),
.ctrlmode_in (ctrlmode_in[4:0]),
.dstaddr_in (dstaddr_in[AW-1:0]),
.srcaddr_in (srcaddr_in[AW-1:0]),
.data_in (data_in[AW-1:0]),
// Inputs
.packet_in (packet_in[PW-1:0]));
//Access-in
assign en = access_in & ready_all & ready_all;
assign mem_rd = (access_in & ~write_in & ready_all);
//Pushback Circuit (pass through problems?)
assign ready_all = (ready_random | ready_in);
assign readt_out = ready_all;// & access_in
//Address-in (shifted by three bits, 64 bit wide memory)
assign addr[MAW-1:0] = dstaddr_in[MAW+2:3];
//Shift up
assign din_aligned[DW-1:0] = (datamode_in[1:0]==2'b00) ? {(4){data_in[7:0]}} :
(datamode_in[1:0]==2'b01) ? {(2){data_in[15:0]}} :
data_in[31:0];
//Data-in (hardoded width)
assign din[63:0] =(datamode_in[1:0]==2'b11) ? {srcaddr_in[31:0],din_aligned[31:0]}:
{din_aligned[31:0],din_aligned[31:0]};
//Write mask
//TODO: make module
always@*
casez({write_in, datamode_in[1:0],dstaddr_in[2:0]})
//Byte
6'b100000 : wen[7:0] = 8'b00000001;
6'b100001 : wen[7:0] = 8'b00000010;
6'b100010 : wen[7:0] = 8'b00000100;
6'b100011 : wen[7:0] = 8'b00001000;
6'b100100 : wen[7:0] = 8'b00010000;
6'b100101 : wen[7:0] = 8'b00100000;
6'b100110 : wen[7:0] = 8'b01000000;
6'b100111 : wen[7:0] = 8'b10000000;
//Short
6'b10100? : wen[7:0] = 8'b00000011;
6'b10101? : wen[7:0] = 8'b00001100;
6'b10110? : wen[7:0] = 8'b00110000;
6'b10111? : wen[7:0] = 8'b11000000;
//Word
6'b1100?? : wen[7:0] = 8'b00001111;
6'b1101?? : wen[7:0] = 8'b11110000;
//Double
6'b111??? : wen[7:0] = 8'b11111111;
default : wen[7:0] = 8'b00000000;
endcase // casez ({write, datamode_in[1:0],addr_in[2:0]})
//Single ported memory
defparam mem.DW=64;
defparam mem.DEPTH=DEPTH;
oh_memory_sp mem(
// Inputs
.clk (clk),
.en (en),
.we (write_in),
.wem ({
{(8){wen[7]}},
{(8){wen[6]}},
{(8){wen[5]}},
{(8){wen[4]}},
{(8){wen[3]}},
{(8){wen[2]}},
{(8){wen[1]}},
{(8){wen[0]}}
}
),
.addr (addr[MAW-1:0]),
.din (din[63:0]),
.dout (dout[63:0]),
.vdd (1'b1),
.vddm (1'b1),
.memrepair(8'b0),
.memconfig(8'b0),
.bist_en (1'b0),
.bist_we (1'b0),
.bist_wem (64'b0),
.bist_addr({(MAW){1'b0}}),
.bist_din (64'b0)
);
//Outgoing transaction
always @ (posedge clk or negedge nreset)
if(!nreset)
access_out <=1'b0;
else
begin
access_out <= mem_rd;
write_out <= 1'b1;
align_addr[2:0] <= dstaddr_in[2:0];
datamode_out[1:0] <= datamode_in[1:0];
ctrlmode_out[4:0] <= ctrlmode_in[4:0];
dstaddr_out[AW-1:0] <= srcaddr_in[AW-1:0];
end
//Data alignment for readback
emesh_rdalign emesh_rdalign (// Outputs
.data_out (dout_aligned[63:0]),
// Inputs
.datamode (datamode_out[1:0]),
.addr (align_addr[2:0]),
.data_in (dout[63:0]));
assign srcaddr_out[AW-1:0] = (datamode_out[1:0]==2'b11) ? dout[63:32] : 32'b0;
assign data_out[31:0] = dout_aligned[31:0];
//Concatenate
emesh2packet #(.AW(AW),
.PW(PW))
e2p (
/*AUTOINST*/
// Outputs
.packet_out (packet_out[PW-1:0]),
// Inputs
.write_out (write_out),
.datamode_out (datamode_out[1:0]),
.ctrlmode_out (ctrlmode_out[4:0]),
.dstaddr_out (dstaddr_out[AW-1:0]),
.data_out (data_out[AW-1:0]),
.srcaddr_out (srcaddr_out[AW-1:0]));
`ifdef TARGET_SIM
generate
if(MON)
begin
emesh_monitor #(.PW(PW),
.INDEX(1),
.NAME(NAME),
.IDW(IDW)
)
emesh_monitor (.dut_access (access_in & write_in),
.dut_packet (packet_in[PW-1:0]),
.ready_in (ready_random),
/*AUTOINST*/
// Inputs
.clk (clk),
.nreset (nreset),
.coreid (coreid[IDW-1:0]));
end // if (MON)
endgenerate
`endif
//Random wait generator //TODO: make this a module
generate
if(WAIT)
begin
reg [8:0] ready_counter;
always @ (posedge clk or negedge nreset)
if(!nreset)
ready_counter[8:0] <= 'b0;
else
ready_counter[8:0] <= ready_counter+1'b1;
assign ready_random = (|ready_counter[5:0]);//(|ready_counter[3:0]);//1'b0;
end
else
begin
assign ready_random = 1'b0;
end // else: !if(WAIT)
endgenerate
endmodule // emesh_memory
// Local Variables:
// verilog-library-directories:("." "../dv" )
// End:
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// dpram_be.v: Dual-ported RAM with byte-enable //
// //
// Author: Ameer M.S. Abdelhadi ([email protected], [email protected]) //
// SRAM-based 2D BCAM; The University of British Columbia (UBC), April 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module dpram_be
#( parameter MEMD = 8*1024, // memory depth
parameter DATAW = 90 , // data width; a multiply of BYTEW
parameter BYTEW = 9 , // byte (segment) width
parameter IZERO = 0 , // binary / Initial RAM with zeros (has priority over IFILE)
parameter IFILE = "" ) // initialization hex file (don't pass extension), optional
( input clk , // clock
input rst , // global registers reset
// Port A - True port; write with byte-enable or full width read
input wEnbA , // write enable for port A
input [DATAW/BYTEW-1:0] bEnbA , // byte-enable for port A (one-hot) / [DATAW/BYTEW-1:0]
input [`log2(MEMD)-1:0] addrA , // read/write addresses / [`log2(MEMD)-1:0]
input [BYTEW -1:0] wDataA, // write data / [DATAW -1:0]
output [DATAW -1:0] rDataA, // read data / [DATAW -1:0]
// Port B - read only
input [`log2(MEMD)-1:0] rAddrB , // read address / [`log2(MEMD)-1:0]
output [DATAW -1:0] rDataB); // read data / [DATAW -1:0]
localparam nBYTE = DATAW/BYTEW; // number of byte slices
localparam ADDRW = `log2(MEMD); // address width
// outputs for M20K bytes
wire [nBYTE*10-1:0] rDataA10;
wire [nBYTE*10-1:0] rDataB10;
// generate and instantiate true dual-ported RAM
genvar bi;
generate
// M20K byte width is 8 or 10 bits; if BYTEW>10, use the entire M20K block, otherwise use internal M20K byte enables
if ( (BYTEW>10) || (MEMD>1024) )
for (bi=0 ; bi<nBYTE ; bi=bi+1) begin: M20K1Ebi
tdpram #( .MEMD ( MEMD ), // memory depth
.DATAW ( BYTEW ), // data width
.IZERO ( IZERO ), // binary / Initial RAM with zeros (has priority over IFILE)
.IFILE ( IFILE )) // initialization hex file (don't pass extension), optional
tdprami ( .clk ( clk ), // clock
.wEnbA ( wEnbA && bEnbA[bi] ), // write enable for port A
.wEnbB ( 1'b0 ), // write enable for port B
.addrA ( addrA ), // write addresses - packed from nWPORTS write ports / [`log2(MEMD)-1:0]
.addrB ( rAddrB ), // write addresses - packed from nWPORTS write ports / [`log2(MEMD)-1:0]
.wDataA( wDataA ), // write data - packed from nRPORTS read ports / [DATAW -1:0]
.wDataB( {BYTEW{1'b1}} ), // write data - packed from nRPORTS read ports / [DATAW -1:0]
.rDataA( rDataA[bi*BYTEW +: BYTEW] ), // read data - packed from nRPORTS read ports / [DATAW -1:0]
.rDataB( rDataB[bi*BYTEW +: BYTEW] )); // read data - packed from nRPORTS read ports / [DATAW -1:0]
end
else // BYTEW<=10 && MEMD<=1024
for (bi=0 ; bi<(nBYTE/2) ; bi=bi+1) begin: M20K2Ebi
altsyncram #( .address_reg_b ( "CLOCK0" ),
.byte_size ( 10 ),
.clock_enable_input_a ( "BYPASS" ),
.clock_enable_input_b ( "BYPASS" ),
.clock_enable_output_a ( "BYPASS" ),
.clock_enable_output_b ( "BYPASS" ),
.indata_reg_b ( "CLOCK0" ),
.intended_device_family ( "Stratix V" ),
.lpm_type ( "altsyncram" ),
.numwords_a ( 1024 ),
.numwords_b ( 1024 ),
.operation_mode ( "BIDIR_DUAL_PORT" ),
.outdata_aclr_a ( "CLEAR0" ),
.outdata_aclr_b ( "CLEAR0" ),
.outdata_reg_a ( "UNREGISTERED" ),
.outdata_reg_b ( "UNREGISTERED" ),
.power_up_uninitialized ( "FALSE" ),
.ram_block_type ( "M20K" ),
.read_during_write_mode_mixed_ports ( "OLD_DATA" ),
.read_during_write_mode_port_a ( "NEW_DATA_NO_NBE_READ" ),
.read_during_write_mode_port_b ( "NEW_DATA_NO_NBE_READ" ),
.widthad_a ( 10 ),
.widthad_b ( 10 ),
.width_a ( 20 ),
.width_b ( 20 ),
.width_byteena_a ( 2 ),
.width_byteena_b ( 1 ),
.wrcontrol_wraddress_reg_b ( "CLOCK0" ))
altsyncram_be ( .byteena_a ( bEnbA[bi*2 +: 2] ),
.clock0 ( clk ),
.wren_a ( wEnbA ),
.address_b ( `ZPAD(rAddrB,10) ),
.data_b ( 20'b1 ),
.wren_b ( 1'b0 ),
.aclr0 ( rst ),
.address_a ( `ZPAD(addrA,10) ),
.data_a ( {2{`ZPAD(wDataA,10)}} ),
.q_a ( rDataA10[bi*20 +: 20] ),
.q_b ( rDataB10[bi*20 +: 20] ),
.aclr1 ( 1'b0 ),
.addressstall_a ( 1'b0 ),
.addressstall_b ( 1'b0 ),
.byteena_b ( 1'b1 ),
.clock1 ( 1'b1 ),
.clocken0 ( 1'b1 ),
.clocken1 ( 1'b1 ),
.clocken2 ( 1'b1 ),
.clocken3 ( 1'b1 ),
.eccstatus ( ),
.rden_a ( 1'b1 ),
.rden_b ( 1'b1 ));
assign rDataA[bi*BYTEW*2+BYTEW +: BYTEW] = rDataA10[bi*20+10 +: BYTEW];
assign rDataA[bi*BYTEW*2 +: BYTEW] = rDataA10[bi*20 +: BYTEW];
assign rDataB[bi*BYTEW*2+BYTEW +: BYTEW] = rDataB10[bi*20+10 +: BYTEW];
assign rDataB[bi*BYTEW*2 +: BYTEW] = rDataB10[bi*20 +: BYTEW];
end
endgenerate
endmodule
|
`default_nettype none
module module_scope_Example(o1, o2);
parameter [31:0] v1 = 10;
parameter [31:0] v2 = 20;
output [31:0] o1, o2;
assign module_scope_Example.o1 = module_scope_Example.v1;
assign module_scope_Example.o2 = module_scope_Example.v2;
endmodule
module module_scope_ExampleLong(o1, o2);
parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1 = 10;
parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2 = 20;
output [31:0] o1, o2;
assign module_scope_ExampleLong.o1 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1;
assign module_scope_ExampleLong.o2 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2;
endmodule
module module_scope_top(
output [31:0] a1, a2, b1, b2, c1, c2,
output [31:0] d1, d2, e1, e2, f1, f2
);
module_scope_Example a(a1, a2);
module_scope_Example #(1) b(b1, b2);
module_scope_Example #(1, 2) c(c1, c2);
module_scope_ExampleLong d(d1, d2);
module_scope_ExampleLong #(1) e(e1, e2);
module_scope_ExampleLong #(1, 2) f(f1, f2);
endmodule
|
/*
File: e_tx_io.v
This file is part of the Parallella Project .
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module e_tx_io (/*AUTOARG*/
// Outputs
tx_lclk_p, tx_lclk_n, tx_frame_p, tx_frame_n, tx_data_p, tx_data_n,
tx_wr_wait, tx_rd_wait,
// Inputs
reset, ioreset, tx_wr_wait_p, tx_wr_wait_n, tx_rd_wait_p,
tx_rd_wait_n, txlclk_p, txlclk_s, txlclk_out, txframe_p, txdata_p,
ecfg_tx_enable, ecfg_tx_gpio_mode, ecfg_tx_clkdiv, ecfg_dataout
);
parameter IOSTD_ELINK = "LVDS_25";
//###########
//# eLink pins
//###########
output tx_lclk_p, tx_lclk_n; // Differential clock from PLL to eLink
input reset;
input ioreset;
output tx_frame_p, tx_frame_n; // Outputs to eLink
output [7:0] tx_data_p, tx_data_n;
input tx_wr_wait_p, tx_wr_wait_n;
input tx_rd_wait_p, tx_rd_wait_n;
//#############
//# Fabric interface, 1/8 bit rate of eLink
//#############
input txlclk_p; // Parallel clock in (bit rate / 8)
input txlclk_s; // Serial clock in (bit rate / 2)
input txlclk_out; // "LCLK" source in, 90deg from lclk_s
input [7:0] txframe_p;
input [63:0] txdata_p;
output tx_wr_wait;
output tx_rd_wait;
//#############
//# Configuration bits
//#############
input ecfg_tx_enable; //enable signal for rx
input ecfg_tx_gpio_mode; //forces rx wait pins to constants
input [3:0] ecfg_tx_clkdiv; // TODO: Implement this
input [10:0] ecfg_dataout; // frame & data for GPIO mode
//############
//# WIRES
//############
wire [7:0] tx_data; // High-speed serial data outputs
wire [7:0] tx_data_t; // Tristate signal to OBUF's
wire tx_frame; // serial frame signal
wire tx_lclk;
//#############################
//# Serializer instantiations
//#############################
reg [63:0] pdata;
reg [7:0] pframe;
reg [1:0] txenb_sync;
wire txenb = txenb_sync[0];
reg [1:0] txgpio_sync;
wire txgpio = txgpio_sync[0];
integer n;
// Sync these control bits into our domain
always @ (posedge txlclk_p) begin
txenb_sync <= {ecfg_tx_enable, txenb_sync[1]};
txgpio_sync <= {ecfg_tx_gpio_mode, txgpio_sync[1]};
if(txgpio) begin
pframe <= {8{ecfg_dataout[8]}};
for(n=0; n<8; n=n+1)
pdata[n*8+7 -: 8] <= ecfg_dataout[7:0];
end else if(txenb) begin
pframe <= txframe_p;
pdata <= txdata_p;
end else begin
pframe <= 8'd0;
pdata <= 64'd0;
end // else: !if(txgpio)
end // always @ (posedge txlclk_p)
genvar i;
generate for(i=0; i<8; i=i+1)
begin : gen_serdes
OSERDESE2
#(
.DATA_RATE_OQ("DDR"), // DDR, SDR
.DATA_RATE_TQ("BUF"), // DDR, BUF, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
.INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
.INIT_TQ(1'b1), // Initial value of TQ output (1'b0,1'b1)
.SERDES_MODE("MASTER"), // MASTER, SLAVE
.SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
.SRVAL_TQ(1'b1), // TQ output value when SR is used (1'b0,1'b1)
.TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
.TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
.TRISTATE_WIDTH(1) // 3-state converter width (1,4)
) OSERDESE2_txdata
(
.OFB(), // 1-bit output: Feedback path for data
.OQ(tx_data[i]), // 1-bit output: Data path output
// SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
.SHIFTOUT1(),
.SHIFTOUT2(),
.TBYTEOUT(), // 1-bit output: Byte group tristate
.TFB(), // 1-bit output: 3-state control
.TQ(tx_data_t[i]), // 1-bit output: 3-state control
.CLK(txlclk_s), // 1-bit input: High speed clock
.CLKDIV(txlclk_p), // 1-bit input: Divided clock
// D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
.D1(pdata[i+56]), // First data out
.D2(pdata[i+48]),
.D3(pdata[i+40]),
.D4(pdata[i+32]),
.D5(pdata[i+24]),
.D6(pdata[i+16]),
.D7(pdata[i+8]),
.D8(pdata[i]), // Last data out
.OCE(1'b1), // 1-bit input: Output data clock enable
.RST(ioreset), // 1-bit input: Reset
// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0),
// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
.T1(~ecfg_tx_enable),
.T2(1'b0),
.T3(1'b0),
.T4(1'b0),
.TBYTEIN(1'b0), // 1-bit input: Byte group tristate
.TCE(1'b1) // 1-bit input: 3-state clock enable
);
end // block: gen_serdes
endgenerate
OSERDESE2
#(
.DATA_RATE_OQ("DDR"), // DDR, SDR
.DATA_RATE_TQ("SDR"), // DDR, BUF, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
.INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
.INIT_TQ(1'b0), // Initial value of TQ output (1'b0,1'b1)
.SERDES_MODE("MASTER"), // MASTER, SLAVE
.SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
.SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)
.TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
.TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
.TRISTATE_WIDTH(1) // 3-state converter width (1,4)
) OSERDESE2_tframe
(
.OFB(), // 1-bit output: Feedback path for data
.OQ(tx_frame), // 1-bit output: Data path output
// SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
.SHIFTOUT1(),
.SHIFTOUT2(),
.TBYTEOUT(), // 1-bit output: Byte group tristate
.TFB(), // 1-bit output: 3-state control
.TQ(), // 1-bit output: 3-state control
.CLK(txlclk_s), // 1-bit input: High speed clock
.CLKDIV(txlclk_p), // 1-bit input: Divided clock
// D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
.D1(pframe[7]), // first data out
.D2(pframe[6]),
.D3(pframe[5]),
.D4(pframe[4]),
.D5(pframe[3]),
.D6(pframe[2]),
.D7(pframe[1]),
.D8(pframe[0]), // last data out
.OCE(1'b1), // 1-bit input: Output data clock enable
.RST(ioreset), // 1-bit input: Reset
// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0),
// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
.T1(1'b0),
.T2(1'b0),
.T3(1'b0),
.T4(1'b0),
.TBYTEIN(1'b0), // 1-bit input: Byte group tristate
.TCE(1'b0) // 1-bit input: 3-state clock enable
);
//################################
//# LClock Creation
//################################
ODDR
#(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
oddr_lclk_inst
(
.Q (tx_lclk),
.C (txlclk_out),
.CE (1'b1),
.D1 (txenb),
.D2 (1'b0),
.R (1'b0),
.S (1'b0));
//################################
//# Output Buffers
//################################
OBUFTDS
#(
.IOSTANDARD(IOSTD_ELINK),
.SLEW("FAST")
) OBUFTDS_txdata [7:0]
(
.O (tx_data_p),
.OB (tx_data_n),
.I (tx_data),
.T (tx_data_t)
);
OBUFDS
#(
.IOSTANDARD(IOSTD_ELINK),
.SLEW("FAST")
) OBUFDS_txframe
(
.O (tx_frame_p),
.OB (tx_frame_n),
.I (tx_frame_n)
);
OBUFDS
#(
.IOSTANDARD(IOSTD_ELINK),
.SLEW("FAST")
) OBUFDS_lclk
(
.O (tx_lclk_p),
.OB (tx_lclk_n),
.I (tx_lclk)
);
//################################
//# Wait Input Buffers
//################################
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_txwrwait
(.I (tx_wr_wait_p),
.IB (tx_wr_wait_n),
.O (tx_wr_wait));
// On Parallella this signal comes in single-ended
// TODO: should add a
assign tx_rd_wait = tx_rd_wait_p;
endmodule // e_tx_io
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DFF_NRS_SYMBOL_V
`define SKY130_FD_SC_LS__UDP_DFF_NRS_SYMBOL_V
/**
* udp_dff$NRS: Negative edge triggered D flip-flop (Q output UDP)
* with both active high reset and set (reset dominate).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_dff$NRS (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET,
input SET ,
//# {{clocks|Clocking}}
input CLK_N
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DFF_NRS_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21BA_BLACKBOX_V
`define SKY130_FD_SC_HS__O21BA_BLACKBOX_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o21ba (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21BA_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLXTN_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__DLXTN_PP_SYMBOL_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dlxtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE_N,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLXTN_PP_SYMBOL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Mon Sep 18 12:32:27 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_0_stub.v
// Design : vio_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "vio,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_in1, probe_in2, probe_in3)
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_in1[0:0],probe_in2[0:0],probe_in3[0:0]" */;
input clk;
input [0:0]probe_in0;
input [0:0]probe_in1;
input [0:0]probe_in2;
input [0:0]probe_in3;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVN_BLACKBOX_V
`define SKY130_FD_SC_HD__EINVN_BLACKBOX_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__einvn (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVN_BLACKBOX_V
|
// Testbench for Embedded Interrupt Controller (EIC) wbgen2 functionatlity
`timescale 1ns/1ps
`include "../common/wishbone_test_master.v"
`include "output/vlog_constants.v"
module main;
function [4:0] decode_irq;
input[31:0] isr_val;
begin:decode_irq_body
integer i;
integer irqn;
irqn=-1;
for(i=0; i<32; i=i+1) if(isr_val[i])
begin
if(irqn < 0) irqn = i;
end
decode_irq = irqn;
end
endfunction
WB_TEST_MASTER WB();
wire clk = WB.wb_clk;
wire rst = WB.wb_rst;
wire wb_irq;
reg irq_rising_edge = 0;
reg irq_falling_edge = 1;
reg irq_level_hi = 0;
reg irq_level_lo = 1;
integer irqn;
reg [31:0] rval;
wb_test_interrupts
dut(
.rst_n_i (WB.wb_rst),
.wb_clk_i (WB.wb_clk),
.wb_addr_i (WB.wb_addr[1:0]),
.wb_data_i (WB.wb_data_o),
.wb_data_o (WB.wb_data_i),
.wb_cyc_i (WB.wb_cyc),
.wb_sel_i (WB.wb_bwsel),
.wb_stb_i (WB.wb_stb),
.wb_we_i (WB.wb_we),
.wb_ack_o (WB.wb_ack),
.wb_irq_o (wb_irq),
.irq_ipe_i (irq_rising_edge),
.irq_ine_i (irq_falling_edge),
.irq_il0_i (irq_level_lo ),
.irq_il1_i (irq_level_hi )
);
initial begin
wait (WB.ready);
$display("Configure the interrupt controller - enable all interrupts");
WB.write32(`ADDR_TESTIRQ_EIC_IER, 'hf);
// generate some irqs
#8000; irq_rising_edge = 1;
#8000; irq_falling_edge = 0;
#8000; irq_level_lo = 0;
#8000; irq_level_hi = 1;
$display("Mask all interrupts");
#8000; WB.write32(`ADDR_TESTIRQ_EIC_IDR, 'hf);
#8000; irq_level_lo = 0;
#8000; irq_level_hi = 1;
$display("Test done.");
end
// irq responder
always@(wb_irq) begin
if(wb_irq == 1) begin
WB.read32(`ADDR_TESTIRQ_EIC_ISR, rval);
irqn = decode_irq(rval);
$display("Got interrupt: %d", irqn);
if(irqn == 2) begin
$display("Clearing the 0-level-sensitive interrupt source");
irq_level_lo = 1;
end
if(irqn == 3) begin
$display("Clearing the 1-level-sensitive interrupt source");
irq_level_hi = 0;
end
// acknowledge the interrupts
WB.write32(`ADDR_TESTIRQ_EIC_ISR, (1<<irqn));
$display("Acknowledged IRQ: %d", irqn);
end
end
endmodule
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_7_paramram_wrap.v
// Version : v1.0
// Description: manage address/data generation to paramram module.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
`include "axi_traffic_gen_v2_0_7_defines.v"
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_7_paramram_wrap #
(
parameter C_FAMILY = "virtex7",
parameter C_RAMINIT_PARAMRAM0_F = "NONE" ,
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_M_AXI_DATA_WIDTH = 32,
parameter C_M_AXI_ADDR_WIDTH = 32,
parameter C_REPEAT_COUNT = 254,
parameter C_ATG_BASIC_AXI4 = 0
) (
input Clk ,
input rst_l ,
//s
input awfifo_valid ,
input [71:0] awfifo_out ,
input wfifo_valid ,
input [C_S_AXI_DATA_WIDTH*9/8+1-1:0] wfifo_out ,
//axi_traffic_gen_v2_0_7_cmdram
input [127:0] cmd_out_mr_regslice ,
input [127:0] cmd_out_mr_regslice_ff ,
input [127:0] cmd_out_mw_regslice ,
input [127:0] cmd_out_mw_regslice_ff ,
output reg [23:0] param_cmdw_submitcnt_ff ,
output reg [23:0] param_cmdr_submitcnt_ff ,
//mr
output reg [127:0] cmd_out_mr ,
input mar_fifo_push_ff ,
input [9:0] mar_ptr_new_ff ,
input [9:0] mar_ptr_new_2ff ,
output param_cmdr_delayop_valid ,
output [23:0] param_cmdr_count ,
output param_cmdr_repeatfixedop_valid,
output reg param_cmdr_disable_submitincr ,
//mw
output reg [127:0] cmd_out_mw ,
input maw_fifo_push_ff ,
input [9:0] maw_ptr_new_ff ,
input [9:0] maw_ptr_new_2ff ,
output param_cmdw_delayop_valid ,
output [23:0] param_cmdw_count ,
output param_cmdw_repeatfixedop_valid,
output reg param_cmdw_disable_submitincr
//debug-capture
);
wire [127:0] cmd_out_mr_postmux;
wire [127:0] cmd_out_mw_postmux;
//generate if(C_ATG_BASIC_AXI4 == 1 ) begin : PARAMRAM_OFF
// always @(posedge Clk) begin
// param_cmdw_submitcnt_ff <= 20'h0;
// param_cmdr_submitcnt_ff <= 20'h0;
// end
// assign cmd_out_mr_postmux[31:0] = cmd_out_mr_regslice_ff[31:0];
// assign cmd_out_mr_postmux[127:32] = cmd_out_mr_regslice[127:32];
// always @(posedge Clk) begin
// cmd_out_mr <= cmd_out_mr_postmux;
// end
// assign param_cmdr_delayop_valid = 1'b0;
// assign param_cmdr_count = 1'b0;
// assign param_cmdr_repeatfixedop_valid= 1'b0;
// always @(posedge Clk) begin
// param_cmdr_disable_submitincr <= 1'b0;
// end
//
// assign cmd_out_mw_postmux[31:0] = cmd_out_mw_regslice_ff[31:0];
// assign cmd_out_mw_postmux[127:32] = cmd_out_mw_regslice[127:32];
// always @(posedge Clk) begin
// cmd_out_mw <= cmd_out_mw_postmux;
// end
// assign param_cmdw_delayop_valid = 1'b0;
// assign param_cmdw_count = 1'b0;
// assign param_cmdw_repeatfixedop_valid = 1'b0;
// always @(posedge Clk) begin
// param_cmdw_disable_submitincr <= 1'b0;
// end
//end
//endgenerate
generate if(C_ATG_BASIC_AXI4 == 0 ) begin : PARAMRAM_ON
/*
*
* grahams : adding parameterized FSM + registers
*
*
*
*/
// PORT A : AXI SLV writes, CMDR read
// PORT B : CMDW read
//wire param_ram_we = awfifo_valid && (awfifo_out[23:12] == 12'h001);
wire param_ram_we = awfifo_valid && (awfifo_out[15:12] == 4'h1);
reg param_ram_we_ff;
reg [8:0] param_ram_addr_ff;
always @(posedge Clk) begin
param_ram_we_ff <= (rst_l) ? ((param_ram_we) ? 1'h1 : ((wfifo_valid) ? 1'h0 : param_ram_we_ff)) : 1'h0 ;
param_ram_addr_ff <= (rst_l) ? ((param_ram_we) ? awfifo_out[10:2] : param_ram_addr_ff) : 9'h0 ;
end
wire [3:0] paramram_we_a = (wfifo_valid && param_ram_we_ff) ? 4'hf : 4'h0 ;
//wire [9:0] paramram_addr_a = (param_ram_we_ff) ? {1'b0,awfifo_out[10:2]} : {2'b0,mar_ptr_new_ff[7:0]} ;
wire [8:0] paramram_addr_a = (wfifo_valid && param_ram_we_ff) ? param_ram_addr_ff : {1'b0,mar_ptr_new_ff[7:0]} ;
wire [31:0] paramram_wr_data_a;
if(C_S_AXI_DATA_WIDTH == 64) begin: ADDR_64_GEN
assign paramram_wr_data_a = (param_ram_addr_ff[0]) ? wfifo_out[63:32]: wfifo_out[31:0];
end
if(C_S_AXI_DATA_WIDTH == 32) begin: ADDR_32_GEN
assign paramram_wr_data_a = wfifo_out[31:0];
end
wire [31:0] paramram_rd_data_a;
wire [3:0] paramram_we_b = 4'b0 ;
wire [8:0] paramram_addr_b = {1'b1,maw_ptr_new_ff[7:0]};
wire [31:0] paramram_wr_data_b = 32'h0;
wire [31:0] paramram_rd_data_b;
axi_traffic_gen_v2_0_7_slvram_v7 #(
.C_FAMILY (C_FAMILY ),
.C_DATAWIDTH (32 ),
.C_SIZE (512 ),
.C_ADDR_WIDTH(9 ),
//.C_INITRAM_F ("/home/kpolise/prm.mif")
.C_INITRAM_F (C_RAMINIT_PARAMRAM0_F)
) paramram (
.clk_a (Clk ),
.we_a (paramram_we_a ),
.addr_a (paramram_addr_a ),
.wr_data_a(paramram_wr_data_a),
.rd_data_a(paramram_rd_data_a),
.clk_b (Clk ),
.we_b (paramram_we_b ),
.addr_b (paramram_addr_b ),
.wr_data_b(paramram_wr_data_b),
.rd_data_b(paramram_rd_data_b)
);
wire [31:0] paramram_mr_regslice;
wire [31:0] paramram_mw_regslice;
axi_traffic_gen_v2_0_7_regslice
#(
.DWIDTH(32),
.IDWIDTH(1),
.DATADEPTH(`REGSLICE_PARAMRAM_DATA),
.IDDEPTH(1)
)
paramram_r_regslice
(
.din (paramram_rd_data_a ),
.dout (paramram_mr_regslice),
.dout_early ( ),
.idin (1'b0 ),
.idout ( ),
.id_stable ( ),
.id_stable_ff ( ),
.data_stable ( ),
.clk (Clk ),
.reset (~rst_l )
);
axi_traffic_gen_v2_0_7_regslice
#(
.DWIDTH (32 ),
.IDWIDTH (1 ),
.DATADEPTH(`REGSLICE_PARAMRAM_DATA),
.IDDEPTH (1 )
)
paramram_w_regslice
(
.din (paramram_rd_data_b ),
.dout (paramram_mw_regslice),
.dout_early ( ),
.idin (1'b0 ),
.idout ( ),
.id_stable ( ),
.id_stable_ff ( ),
.data_stable ( ),
.clk (Clk ),
.reset (~rst_l )
);
/*
* CMDR PARAM FSM / CONTROL
*
*/
reg [2:0] param_cmdr_op_ff ;
reg [1:0] param_cmdr_addrmode_ff ;
reg [1:0] param_cmdr_intervalmode_ff;
reg param_cmdr_idmode_ff ;
wire [23:0] cmdr_rnum;
wire [15:0] r_randnum;
assign cmdr_rnum = {r_randnum[7:0],r_randnum[15:0]};
axi_traffic_gen_v2_0_7_randgen
cmdr_rand(
.seed (16'h5A5A ),
.randnum (r_randnum),
.generate_next(1'b1 ),
.reset (~rst_l ),
.clk (Clk )
);
reg [23:0] param_cmdr_count_minus1_ff ;
wire [23:0] paramram_mr_regslice_minus1 = paramram_mr_regslice[23:0]-1;
wire [23:0] param_cmdr_count_int = (paramram_mr_regslice[23:0] <= 24'd6) ? 24'b0 : paramram_mr_regslice[23:0]-24'h6;
wire [11:0] param_cmdr_dint = (paramram_mr_regslice[19:8] <= 12'd6) ? 12'b0 : paramram_mr_regslice[19:8]-12'h6;
wire [23:0] param_cmdr_count_dint = {paramram_mr_regslice[23:20],param_cmdr_dint,paramram_mr_regslice[7:0]};
assign param_cmdr_count = (param_cmdr_repeatfixedop_valid == 1'b1) ? param_cmdr_count_dint : param_cmdr_count_int;
//assign param_cmdr_count = param_cmdr_count_int;
always @(posedge Clk) begin
param_cmdr_count_minus1_ff <= paramram_mr_regslice_minus1 ;
param_cmdr_addrmode_ff <= paramram_mr_regslice[25:24] ;
param_cmdr_intervalmode_ff <= paramram_mr_regslice[27:26] ;
param_cmdr_idmode_ff <= paramram_mr_regslice[28] ;
param_cmdr_op_ff <= paramram_mr_regslice[31:29] ;
end
// opcntrl signals here, will be validated by opcode field
reg [3:0] param_cmdr_addrrandrange_encoded;
always @(posedge Clk) begin
param_cmdr_addrrandrange_encoded <= paramram_mr_regslice[23:20] ;
end
reg [3:0] param_cmdr_state_ff;
reg [3:0] param_cmdr_state_nxt;
reg [23:0] param_cmdr_submitcnt_nxt;
// control for incrementing counters during special op
reg [31:0] param_cmdr_addr_ff;
reg [31:0] param_cmdr_add_1;
reg [31:0] param_cmdr_addr_nxt;
reg [31:0] param_cmdr_addr_tmp;
reg [31:0] four_k_bound_chk;
reg [31:0] four_k_bound_chk_ff;
reg param_cmdr_addrmux;
wire [31:0] cmd_out_mr_addr_align = cmd_out_mr_regslice[31:0] & 32'hFFFFF000;
reg [31:0] cmd_out_mr_addr_align_four;
reg [31:0] cmd_out_mr_addr_align_eight;
reg [31:0] cmd_out_mr_comp;
wire [3:0] param_incr_shift = (C_M_AXI_DATA_WIDTH == 32) ? 4'h2 : (C_M_AXI_DATA_WIDTH == 64) ? 4'h3 : (C_M_AXI_DATA_WIDTH == 128) ? 4'h4 : (C_M_AXI_DATA_WIDTH == 256) ? 4'h5: 4'h6;
//wire [31:0] param_maxburstbytes = (C_M_AXI_DATA_WIDTH == 32) ? `SQOP_ADDRMODE_RAND_MAXBURSTBYTES_32 : `SQOP_ADDRMODE_RAND_MAXBURSTBYTES_64;
//wire [31:0] param_maxburstbytes = (C_M_AXI_DATA_WIDTH == 32) ? `SQOP_ADDRMODE_RAND_MAXBURSTBYTES_32 : (C_M_AXI_DATA_WIDTH == 64) ? `SQOP_ADDRMODE_RAND_MAXBURSTBYTES_64 : (C_M_AXI_DATA_WIDTH == 128) ? `SQOP_ADDRMODE_RAND_MAXBURSTBYTES_128 : (C_M_AXI_DATA_WIDTH == 256) ? `SQOP_ADDRMODE_RAND_MAXBURSTBYTES_256 : `SQOP_ADDRMODE_RAND_MAXBURSTBYTES_512;
wire [31:0] param_maxburstbytes = (C_M_AXI_DATA_WIDTH == 32) ? `SQOP_ADDRMODE_RAND_MAXBURSTBYTES_32 : (C_M_AXI_DATA_WIDTH == 64) ? `SQOP_ADDRMODE_RAND_MAXBURSTBYTES_64 : `SQOP_ADDRMODE_RAND_MAXBURSTBYTES_128;
wire [12:0] param_cmdr_addrincr = (cmd_out_mr_regslice[39:32]+1) << param_incr_shift;
wire [12:0] param_cmdr_addrrandc = (cmd_out_mr_regslice[39:32]+1) << param_incr_shift;
reg [12:0] param_cmdr_addrincr_ff;
reg mar_fifo_push_2ff;
reg [31:0] rand_addr_n;
reg [31:0] rand_addr_n_ff;
reg [31:0] rand_addr_n_tmp;
reg [31:0] rand_addr_n_tmpc;
reg [31:0] param_cmdr_addrrand_i;
reg [31:0] param_cmdr_addrrand_i_ff;
always @(posedge Clk) begin
param_cmdr_addrincr_ff <= (rst_l) ? param_cmdr_addrincr : 13'h0;
param_cmdr_state_ff <= (rst_l) ? param_cmdr_state_nxt : `SQOP_ST_IDLE;
param_cmdr_submitcnt_ff <= (rst_l) ? param_cmdr_submitcnt_nxt : 24'h0;
param_cmdr_addr_ff <= (rst_l) ? param_cmdr_addr_nxt : 32'h0;
param_cmdr_add_1 <= (rst_l) ? param_cmdr_addr_ff+param_cmdr_addrincr : 32'h0;
param_cmdr_addr_tmp <= (rst_l) ? param_cmdr_add_1+param_cmdr_addrincr : 32'h0;
four_k_bound_chk_ff <= (rst_l) ? four_k_bound_chk : 32'h0;
mar_fifo_push_2ff <= (rst_l) ? mar_fifo_push_ff : 1'b0;
param_cmdr_addrrand_i_ff <= (rst_l) ? param_cmdr_addrrand_i : 1'b0;
end
/*
*
* ADDR RANGE Encoding w/ needed bits to meet range
*
0 4096 12 10
1 8192 13 11
2 16384 14 12
3 32768 15 13
4 65536 16 14
5 131072 17 15
6 262144 18 16
7 524288 19 17
8 1048576 20 18
9 2097152 21 19
10 4194304 22 20
11 8388608 23 21
12 16777216 24 22
13 33554432 25 23
14 67108864 26 24
15 134217728 27 25
*/
if(C_M_AXI_DATA_WIDTH == 512) begin: RAND_R_ADDR_512_GEN
always @(*)
begin
case (param_cmdr_addrrandrange_encoded)
4'd0: param_cmdr_addrrand_i = {cmdr_rnum[10-5:0],6'b0};
4'd1: param_cmdr_addrrand_i = {cmdr_rnum[11-5:0],6'b0};
4'd2: param_cmdr_addrrand_i = {cmdr_rnum[12-5:0],6'b0};
4'd3: param_cmdr_addrrand_i = {cmdr_rnum[13-5:0],6'b0};
4'd4: param_cmdr_addrrand_i = {cmdr_rnum[14-5:0],6'b0};
4'd5: param_cmdr_addrrand_i = {cmdr_rnum[15-5:0],6'b0};
4'd6: param_cmdr_addrrand_i = {cmdr_rnum[16-5:0],6'b0};
4'd7: param_cmdr_addrrand_i = {cmdr_rnum[17-5:0],6'b0};
4'd8: param_cmdr_addrrand_i = {cmdr_rnum[18-5:0],6'b0};
4'd9: param_cmdr_addrrand_i = {cmdr_rnum[19-5:0],6'b0};
4'd10: param_cmdr_addrrand_i = {cmdr_rnum[20-5:0],6'b0};
4'd11: param_cmdr_addrrand_i = {cmdr_rnum[21-5:0],6'b0};
4'd12: param_cmdr_addrrand_i = {cmdr_rnum[22-5:0],6'b0};
4'd13: param_cmdr_addrrand_i = {cmdr_rnum[23-5:0],6'b0};
4'd14: param_cmdr_addrrand_i = {cmdr_rnum[23-5:0],6'b0};
4'd15: param_cmdr_addrrand_i = {cmdr_rnum[23-5:0],6'b0}; // redundant
endcase
end // always @ begin
end
if(C_M_AXI_DATA_WIDTH == 256) begin: RAND_R_ADDR_256_GEN
always @(*)
begin
case (param_cmdr_addrrandrange_encoded)
4'd0: param_cmdr_addrrand_i = {cmdr_rnum[10-4:0],5'b0};
4'd1: param_cmdr_addrrand_i = {cmdr_rnum[11-4:0],5'b0};
4'd2: param_cmdr_addrrand_i = {cmdr_rnum[12-4:0],5'b0};
4'd3: param_cmdr_addrrand_i = {cmdr_rnum[13-4:0],5'b0};
4'd4: param_cmdr_addrrand_i = {cmdr_rnum[14-4:0],5'b0};
4'd5: param_cmdr_addrrand_i = {cmdr_rnum[15-4:0],5'b0};
4'd6: param_cmdr_addrrand_i = {cmdr_rnum[16-4:0],5'b0};
4'd7: param_cmdr_addrrand_i = {cmdr_rnum[17-4:0],5'b0};
4'd8: param_cmdr_addrrand_i = {cmdr_rnum[18-4:0],5'b0};
4'd9: param_cmdr_addrrand_i = {cmdr_rnum[19-4:0],5'b0};
4'd10: param_cmdr_addrrand_i = {cmdr_rnum[20-4:0],5'b0};
4'd11: param_cmdr_addrrand_i = {cmdr_rnum[21-4:0],5'b0};
4'd12: param_cmdr_addrrand_i = {cmdr_rnum[22-4:0],5'b0};
4'd13: param_cmdr_addrrand_i = {cmdr_rnum[23-4:0],5'b0};
4'd14: param_cmdr_addrrand_i = {cmdr_rnum[23-4:0],5'b0};
4'd15: param_cmdr_addrrand_i = {cmdr_rnum[23-4:0],5'b0}; // redundant
endcase
end // always @ begin
end
if(C_M_AXI_DATA_WIDTH == 128) begin: RAND_R_ADDR_128_GEN
always @(*)
begin
case (param_cmdr_addrrandrange_encoded)
4'd0: param_cmdr_addrrand_i = {cmdr_rnum[10-3:0],4'b0};
4'd1: param_cmdr_addrrand_i = {cmdr_rnum[11-3:0],4'b0};
4'd2: param_cmdr_addrrand_i = {cmdr_rnum[12-3:0],4'b0};
4'd3: param_cmdr_addrrand_i = {cmdr_rnum[13-3:0],4'b0};
4'd4: param_cmdr_addrrand_i = {cmdr_rnum[14-3:0],4'b0};
4'd5: param_cmdr_addrrand_i = {cmdr_rnum[15-3:0],4'b0};
4'd6: param_cmdr_addrrand_i = {cmdr_rnum[16-3:0],4'b0};
4'd7: param_cmdr_addrrand_i = {cmdr_rnum[17-3:0],4'b0};
4'd8: param_cmdr_addrrand_i = {cmdr_rnum[18-3:0],4'b0};
4'd9: param_cmdr_addrrand_i = {cmdr_rnum[19-3:0],4'b0};
4'd10: param_cmdr_addrrand_i = {cmdr_rnum[20-3:0],4'b0};
4'd11: param_cmdr_addrrand_i = {cmdr_rnum[21-3:0],4'b0};
4'd12: param_cmdr_addrrand_i = {cmdr_rnum[22-3:0],4'b0};
4'd13: param_cmdr_addrrand_i = {cmdr_rnum[23-3:0],4'b0};
4'd14: param_cmdr_addrrand_i = {cmdr_rnum[23-3:0],4'b0};
4'd15: param_cmdr_addrrand_i = {cmdr_rnum[23-3:0],4'b0}; // redundant
endcase
end // always @ begin
end
if(C_M_AXI_DATA_WIDTH == 64) begin: RAND_R_ADDR_64_GEN
always @(*)
begin
case (param_cmdr_addrrandrange_encoded)
4'd0: param_cmdr_addrrand_i = {cmdr_rnum[10-2:0],3'b0};
4'd1: param_cmdr_addrrand_i = {cmdr_rnum[11-2:0],3'b0};
4'd2: param_cmdr_addrrand_i = {cmdr_rnum[12-2:0],3'b0};
4'd3: param_cmdr_addrrand_i = {cmdr_rnum[13-2:0],3'b0};
4'd4: param_cmdr_addrrand_i = {cmdr_rnum[14-2:0],3'b0};
4'd5: param_cmdr_addrrand_i = {cmdr_rnum[15-2:0],3'b0};
4'd6: param_cmdr_addrrand_i = {cmdr_rnum[16-2:0],3'b0};
4'd7: param_cmdr_addrrand_i = {cmdr_rnum[17-2:0],3'b0};
4'd8: param_cmdr_addrrand_i = {cmdr_rnum[18-2:0],3'b0};
4'd9: param_cmdr_addrrand_i = {cmdr_rnum[19-2:0],3'b0};
4'd10: param_cmdr_addrrand_i = {cmdr_rnum[20-2:0],3'b0};
4'd11: param_cmdr_addrrand_i = {cmdr_rnum[21-2:0],3'b0};
4'd12: param_cmdr_addrrand_i = {cmdr_rnum[22-2:0],3'b0};
4'd13: param_cmdr_addrrand_i = {cmdr_rnum[23-2:0],3'b0};
4'd14: param_cmdr_addrrand_i = {cmdr_rnum[23-2:0],3'b0};
4'd15: param_cmdr_addrrand_i = {cmdr_rnum[23-2:0],3'b0}; // redundant
endcase
end // always @ begin
end
if(C_M_AXI_DATA_WIDTH == 32) begin: RAND_R_ADDR_32_GEN
always @(*)
begin
case (param_cmdr_addrrandrange_encoded)
4'd0: param_cmdr_addrrand_i = {cmdr_rnum[10-1:0],2'b0};
4'd1: param_cmdr_addrrand_i = {cmdr_rnum[11-1:0],2'b0};
4'd2: param_cmdr_addrrand_i = {cmdr_rnum[12-1:0],2'b0};
4'd3: param_cmdr_addrrand_i = {cmdr_rnum[13-1:0],2'b0};
4'd4: param_cmdr_addrrand_i = {cmdr_rnum[14-1:0],2'b0};
4'd5: param_cmdr_addrrand_i = {cmdr_rnum[15-1:0],2'b0};
4'd6: param_cmdr_addrrand_i = {cmdr_rnum[16-1:0],2'b0};
4'd7: param_cmdr_addrrand_i = {cmdr_rnum[17-1:0],2'b0};
4'd8: param_cmdr_addrrand_i = {cmdr_rnum[18-1:0],2'b0};
4'd9: param_cmdr_addrrand_i = {cmdr_rnum[19-1:0],2'b0};
4'd10: param_cmdr_addrrand_i = {cmdr_rnum[20-1:0],2'b0};
4'd11: param_cmdr_addrrand_i = {cmdr_rnum[21-1:0],2'b0};
4'd12: param_cmdr_addrrand_i = {cmdr_rnum[22-1:0],2'b0};
4'd13: param_cmdr_addrrand_i = {cmdr_rnum[23-1:0],2'b0};
4'd14: param_cmdr_addrrand_i = {cmdr_rnum[23-1:0],2'b0};
4'd15: param_cmdr_addrrand_i = {cmdr_rnum[23-1:0],2'b0}; // redundant
endcase
end // always @ begin
end
// checking address to gaurantee does not exceed range
reg param_cmdr_maxaddr_check_32b,param_cmdr_maxaddr_check_64b,param_cmdr_maxaddr_check_128b,param_cmdr_maxaddr_check_256b,param_cmdr_maxaddr_check_512b ;
if(C_M_AXI_DATA_WIDTH == 32) begin: RAND_R_ADDR_32_CHK
always @(*)
begin
//Set all other checks to 0
param_cmdr_maxaddr_check_64b = 1'b0;
param_cmdr_maxaddr_check_128b = 1'b0;
param_cmdr_maxaddr_check_256b = 1'b0;
param_cmdr_maxaddr_check_512b = 1'b0;
case (param_cmdr_addrrandrange_encoded)
4'd0: param_cmdr_maxaddr_check_32b = (cmdr_rnum[9:8] == 2'h3) && (C_M_AXI_DATA_WIDTH == 32);
4'd1: param_cmdr_maxaddr_check_32b = (cmdr_rnum[10:8]== 3'h7) && (C_M_AXI_DATA_WIDTH == 32);
4'd2: param_cmdr_maxaddr_check_32b = (cmdr_rnum[11:8]== 4'hf) && (C_M_AXI_DATA_WIDTH == 32);
4'd3: param_cmdr_maxaddr_check_32b = (cmdr_rnum[12:8]== 5'h1f) && (C_M_AXI_DATA_WIDTH == 32);
4'd4: param_cmdr_maxaddr_check_32b = (cmdr_rnum[13:8]== 6'h3f) && (C_M_AXI_DATA_WIDTH == 32);
4'd5: param_cmdr_maxaddr_check_32b = (cmdr_rnum[14:8]== 7'h7f) && (C_M_AXI_DATA_WIDTH == 32);
4'd6: param_cmdr_maxaddr_check_32b = (cmdr_rnum[15:8]== 8'hff) && (C_M_AXI_DATA_WIDTH == 32);
4'd7: param_cmdr_maxaddr_check_32b = (cmdr_rnum[16:8]== 9'h1ff) && (C_M_AXI_DATA_WIDTH == 32);
4'd8: param_cmdr_maxaddr_check_32b = (cmdr_rnum[17:8]== 10'h3ff) && (C_M_AXI_DATA_WIDTH == 32);
4'd9: param_cmdr_maxaddr_check_32b = (cmdr_rnum[18:8]== 11'h7ff) && (C_M_AXI_DATA_WIDTH == 32);
4'd10: param_cmdr_maxaddr_check_32b = (cmdr_rnum[19:8]== 12'hfff) && (C_M_AXI_DATA_WIDTH == 32);
4'd11: param_cmdr_maxaddr_check_32b = (cmdr_rnum[20:8]== 13'h1fff) && (C_M_AXI_DATA_WIDTH == 32);
4'd12: param_cmdr_maxaddr_check_32b = (cmdr_rnum[21:8]== 14'h3fff) && (C_M_AXI_DATA_WIDTH == 32);
4'd13: param_cmdr_maxaddr_check_32b = (cmdr_rnum[22:8]== 15'h7fff) && (C_M_AXI_DATA_WIDTH == 32);
4'd14: param_cmdr_maxaddr_check_32b = (cmdr_rnum[23:8]== 16'hffff) && (C_M_AXI_DATA_WIDTH == 32);
4'd15: param_cmdr_maxaddr_check_32b = (cmdr_rnum[23:8]== 16'hffff) && (C_M_AXI_DATA_WIDTH == 32); // redundant
endcase
end // always @ begin
end
if(C_M_AXI_DATA_WIDTH == 64) begin: RAND_R_ADDR_64_CHK
always @(*)
begin
//Set all other checks to 0
param_cmdr_maxaddr_check_32b = 1'b0;
param_cmdr_maxaddr_check_128b = 1'b0;
param_cmdr_maxaddr_check_256b = 1'b0;
param_cmdr_maxaddr_check_512b = 1'b0;
case (param_cmdr_addrrandrange_encoded)
4'd0: param_cmdr_maxaddr_check_64b = (cmdr_rnum[9:9] == 1'h1) && (C_M_AXI_DATA_WIDTH == 64);
4'd1: param_cmdr_maxaddr_check_64b = (cmdr_rnum[10:9]== 2'h3) && (C_M_AXI_DATA_WIDTH == 64);
4'd2: param_cmdr_maxaddr_check_64b = (cmdr_rnum[11:9]== 3'h7) && (C_M_AXI_DATA_WIDTH == 64);
4'd3: param_cmdr_maxaddr_check_64b = (cmdr_rnum[12:9]== 4'hf) && (C_M_AXI_DATA_WIDTH == 64);
4'd4: param_cmdr_maxaddr_check_64b = (cmdr_rnum[13:9]== 5'h1f) && (C_M_AXI_DATA_WIDTH == 64);
4'd5: param_cmdr_maxaddr_check_64b = (cmdr_rnum[14:9]== 6'h3f) && (C_M_AXI_DATA_WIDTH == 64);
4'd6: param_cmdr_maxaddr_check_64b = (cmdr_rnum[15:9]== 7'h7f) && (C_M_AXI_DATA_WIDTH == 64);
4'd7: param_cmdr_maxaddr_check_64b = (cmdr_rnum[16:9]== 8'hff) && (C_M_AXI_DATA_WIDTH == 64);
4'd8: param_cmdr_maxaddr_check_64b = (cmdr_rnum[17:9]== 9'h1ff) && (C_M_AXI_DATA_WIDTH == 64);
4'd9: param_cmdr_maxaddr_check_64b = (cmdr_rnum[18:9]== 10'h3ff) && (C_M_AXI_DATA_WIDTH == 64);
4'd10: param_cmdr_maxaddr_check_64b = (cmdr_rnum[19:9]== 11'h7ff) && (C_M_AXI_DATA_WIDTH == 64);
4'd11: param_cmdr_maxaddr_check_64b = (cmdr_rnum[20:9]== 12'hfff) && (C_M_AXI_DATA_WIDTH == 64);
4'd12: param_cmdr_maxaddr_check_64b = (cmdr_rnum[21:9]== 13'h1fff) && (C_M_AXI_DATA_WIDTH == 64);
4'd13: param_cmdr_maxaddr_check_64b = (cmdr_rnum[22:9]== 14'h3fff) && (C_M_AXI_DATA_WIDTH == 64);
4'd14: param_cmdr_maxaddr_check_64b = (cmdr_rnum[23:9]== 15'h7fff) && (C_M_AXI_DATA_WIDTH == 64);
4'd15: param_cmdr_maxaddr_check_64b = (cmdr_rnum[23:9]== 15'h7fff) && (C_M_AXI_DATA_WIDTH == 64);
endcase
end // always @ begin
end
if(C_M_AXI_DATA_WIDTH == 128) begin: RAND_R_ADDR_128_CHK
always @(*)
begin
//Set all other checks to 0
param_cmdr_maxaddr_check_32b = 1'b0;
param_cmdr_maxaddr_check_64b = 1'b0;
param_cmdr_maxaddr_check_256b = 1'b0;
param_cmdr_maxaddr_check_512b = 1'b0;
case (param_cmdr_addrrandrange_encoded)
//4'd0: param_cmdr_maxaddr_check_128b = (cmdr_rnum[10:10] == 1'h1) && (C_M_AXI_DATA_WIDTH >= 128);
4'd0: param_cmdr_maxaddr_check_128b = (cmdr_rnum[8:8]== 1'h1) && (C_M_AXI_DATA_WIDTH == 128);
4'd1: param_cmdr_maxaddr_check_128b = (cmdr_rnum[9:8]== 2'h3) && (C_M_AXI_DATA_WIDTH == 128);
4'd2: param_cmdr_maxaddr_check_128b = (cmdr_rnum[10:8]== 3'h7) && (C_M_AXI_DATA_WIDTH == 128);
4'd3: param_cmdr_maxaddr_check_128b = (cmdr_rnum[11:8]== 4'hf) && (C_M_AXI_DATA_WIDTH == 128);
4'd4: param_cmdr_maxaddr_check_128b = (cmdr_rnum[12:8]== 5'h1f) && (C_M_AXI_DATA_WIDTH == 128);
4'd5: param_cmdr_maxaddr_check_128b = (cmdr_rnum[13:8]== 6'h3f) && (C_M_AXI_DATA_WIDTH == 128);
4'd6: param_cmdr_maxaddr_check_128b = (cmdr_rnum[14:8]== 7'h7f) && (C_M_AXI_DATA_WIDTH == 128);
4'd7: param_cmdr_maxaddr_check_128b = (cmdr_rnum[15:8]== 8'hff) && (C_M_AXI_DATA_WIDTH == 128);
4'd8: param_cmdr_maxaddr_check_128b = (cmdr_rnum[16:8]== 9'h1ff) && (C_M_AXI_DATA_WIDTH == 128);
4'd9: param_cmdr_maxaddr_check_128b = (cmdr_rnum[17:8]== 10'h3ff) && (C_M_AXI_DATA_WIDTH == 128);
4'd10: param_cmdr_maxaddr_check_128b = (cmdr_rnum[18:8]== 11'h7ff) && (C_M_AXI_DATA_WIDTH == 128);
4'd11: param_cmdr_maxaddr_check_128b = (cmdr_rnum[19:8]== 12'hfff) && (C_M_AXI_DATA_WIDTH == 128);
4'd12: param_cmdr_maxaddr_check_128b = (cmdr_rnum[20:8]== 13'h1fff) && (C_M_AXI_DATA_WIDTH == 128);
4'd13: param_cmdr_maxaddr_check_128b = (cmdr_rnum[21:8]== 14'h3fff) && (C_M_AXI_DATA_WIDTH == 128);
4'd14: param_cmdr_maxaddr_check_128b = (cmdr_rnum[22:8]== 15'h7fff) && (C_M_AXI_DATA_WIDTH == 128);
4'd15: param_cmdr_maxaddr_check_128b = (cmdr_rnum[22:8]== 15'h7fff) && (C_M_AXI_DATA_WIDTH == 128);
endcase
end // always @ begin
end
if(C_M_AXI_DATA_WIDTH == 256) begin: RAND_R_ADDR_256_CHK
always @(*)
begin
//Set all other checks to 0
param_cmdr_maxaddr_check_32b = 1'b0;
param_cmdr_maxaddr_check_64b = 1'b0;
param_cmdr_maxaddr_check_128b = 1'b0;
param_cmdr_maxaddr_check_512b = 1'b0;
case (param_cmdr_addrrandrange_encoded)
//4'd0: param_cmdr_maxaddr_check_256b = (cmdr_rnum[10:10] == 1'h1) && (C_M_AXI_DATA_WIDTH >= 256);
4'd0: param_cmdr_maxaddr_check_256b = (cmdr_rnum[7:7]== 1'h1) && (C_M_AXI_DATA_WIDTH == 256);
4'd1: param_cmdr_maxaddr_check_256b = (cmdr_rnum[8:7]== 2'h3) && (C_M_AXI_DATA_WIDTH == 256);
4'd2: param_cmdr_maxaddr_check_256b = (cmdr_rnum[9:7]== 3'h7) && (C_M_AXI_DATA_WIDTH == 256);
4'd3: param_cmdr_maxaddr_check_256b = (cmdr_rnum[10:7]== 4'hf) && (C_M_AXI_DATA_WIDTH == 256);
4'd4: param_cmdr_maxaddr_check_256b = (cmdr_rnum[11:7]== 5'h1f) && (C_M_AXI_DATA_WIDTH == 256);
4'd5: param_cmdr_maxaddr_check_256b = (cmdr_rnum[12:7]== 6'h2f) && (C_M_AXI_DATA_WIDTH == 256);
4'd6: param_cmdr_maxaddr_check_256b = (cmdr_rnum[13:7]== 7'h7f) && (C_M_AXI_DATA_WIDTH == 256);
4'd7: param_cmdr_maxaddr_check_256b = (cmdr_rnum[14:7]== 8'hff) && (C_M_AXI_DATA_WIDTH == 256);
4'd8: param_cmdr_maxaddr_check_256b = (cmdr_rnum[15:7]== 9'h1ff) && (C_M_AXI_DATA_WIDTH == 256);
4'd9: param_cmdr_maxaddr_check_256b = (cmdr_rnum[16:7]== 10'h3ff) && (C_M_AXI_DATA_WIDTH == 256);
4'd10: param_cmdr_maxaddr_check_256b = (cmdr_rnum[17:7]== 11'h7ff) && (C_M_AXI_DATA_WIDTH == 256);
4'd11: param_cmdr_maxaddr_check_256b = (cmdr_rnum[18:7]== 12'hfff) && (C_M_AXI_DATA_WIDTH == 256);
4'd12: param_cmdr_maxaddr_check_256b = (cmdr_rnum[19:7]== 13'h1fff) && (C_M_AXI_DATA_WIDTH == 256);
4'd13: param_cmdr_maxaddr_check_256b = (cmdr_rnum[20:7]== 14'h3fff) && (C_M_AXI_DATA_WIDTH == 256);
4'd14: param_cmdr_maxaddr_check_256b = (cmdr_rnum[21:7]== 15'h7fff) && (C_M_AXI_DATA_WIDTH == 256);
4'd15: param_cmdr_maxaddr_check_256b = (cmdr_rnum[21:7]== 15'h7fff) && (C_M_AXI_DATA_WIDTH == 256);
endcase
end // always @ begin
end
if(C_M_AXI_DATA_WIDTH == 512) begin: RAND_R_ADDR_512_CHK
always @(*)
begin
//Set all other checks to 0
param_cmdr_maxaddr_check_32b = 1'b0;
param_cmdr_maxaddr_check_64b = 1'b0;
param_cmdr_maxaddr_check_128b = 1'b0;
param_cmdr_maxaddr_check_256b = 1'b0;
case (param_cmdr_addrrandrange_encoded)
//4'd0: param_cmdr_maxaddr_check_512b = (cmdr_rnum[10:10] == 1'h1) && (C_M_AXI_DATA_WIDTH >= 512);
4'd0: param_cmdr_maxaddr_check_512b = (cmdr_rnum[6:6]== 1'h1) && (C_M_AXI_DATA_WIDTH == 512);
4'd1: param_cmdr_maxaddr_check_512b = (cmdr_rnum[7:6]== 2'h3) && (C_M_AXI_DATA_WIDTH == 512);
4'd2: param_cmdr_maxaddr_check_512b = (cmdr_rnum[8:6]== 3'h7) && (C_M_AXI_DATA_WIDTH == 512);
4'd3: param_cmdr_maxaddr_check_512b = (cmdr_rnum[9:6]== 4'hf) && (C_M_AXI_DATA_WIDTH == 512);
4'd4: param_cmdr_maxaddr_check_512b = (cmdr_rnum[10:6]== 5'h1f) && (C_M_AXI_DATA_WIDTH == 512);
4'd5: param_cmdr_maxaddr_check_512b = (cmdr_rnum[11:6]== 6'h2f) && (C_M_AXI_DATA_WIDTH == 512);
4'd6: param_cmdr_maxaddr_check_512b = (cmdr_rnum[12:6]== 7'h7f) && (C_M_AXI_DATA_WIDTH == 512);
4'd7: param_cmdr_maxaddr_check_512b = (cmdr_rnum[13:6]== 8'hff) && (C_M_AXI_DATA_WIDTH == 512);
4'd8: param_cmdr_maxaddr_check_512b = (cmdr_rnum[14:6]== 9'h1ff) && (C_M_AXI_DATA_WIDTH == 512);
4'd9: param_cmdr_maxaddr_check_512b = (cmdr_rnum[15:6]== 10'h3ff) && (C_M_AXI_DATA_WIDTH == 512);
4'd10: param_cmdr_maxaddr_check_512b = (cmdr_rnum[16:6]== 11'h7ff) && (C_M_AXI_DATA_WIDTH == 512);
4'd11: param_cmdr_maxaddr_check_512b = (cmdr_rnum[17:6]== 12'hfff) && (C_M_AXI_DATA_WIDTH == 512);
4'd12: param_cmdr_maxaddr_check_512b = (cmdr_rnum[18:6]== 13'h1fff) && (C_M_AXI_DATA_WIDTH == 512);
4'd13: param_cmdr_maxaddr_check_512b = (cmdr_rnum[19:6]== 14'h3fff) && (C_M_AXI_DATA_WIDTH == 512);
4'd14: param_cmdr_maxaddr_check_512b = (cmdr_rnum[20:6]== 15'h7fff) && (C_M_AXI_DATA_WIDTH == 512);
4'd15: param_cmdr_maxaddr_check_512b = (cmdr_rnum[20:6]== 15'h7fff) && (C_M_AXI_DATA_WIDTH == 512);
endcase
end // always @ begin
end
reg [31:0] param_cmdr_addrrand_ff;
reg [31:0] param_cmdr_addrrand_2ff;
reg [31:0] rand_base_chkr_t_ff;
reg [31:0] rand_base_chkr_ff;
wire [31:0] rand_base_chkr_t = cmd_out_mr_regslice[31:0] + param_cmdr_addrrand_i_ff;
wire [31:0] rand_base_chkr = rand_base_chkr_t_ff - param_maxburstbytes;
wire [31:0] param_cmdr_addrrand = (param_cmdr_maxaddr_check_512b | param_cmdr_maxaddr_check_256b | param_cmdr_maxaddr_check_128b | param_cmdr_maxaddr_check_64b | param_cmdr_maxaddr_check_32b) ?
(cmd_out_mr_regslice[31:0] > rand_base_chkr_ff) ? cmd_out_mr_regslice[31:0] : rand_base_chkr_ff :
(cmd_out_mr_regslice[31:0] + param_cmdr_addrrand_i_ff);
assign param_cmdr_addrrand_valid = ( param_cmdr_addrmode_ff == `SQOP_ADDRMODE_RAND );
assign param_cmdr_addrincr_valid = ( param_cmdr_addrmode_ff == `SQOP_ADDRMODE_INCR );
//Currently NOT IN USE
assign param_cmdr_intervalrand_valid = ( param_cmdr_intervalmode_ff == `SQOP_INTERVALMODE_RAND );
always @(posedge Clk) begin
rand_base_chkr_ff <= rand_base_chkr;
rand_base_chkr_t_ff <= rand_base_chkr_t;
rand_addr_n_ff <= rand_addr_n;
rand_addr_n <= param_cmdr_addrrand + param_cmdr_addrrandc;
end
always @(posedge Clk) begin
param_cmdr_addrrand_ff <= param_cmdr_addrrand;
param_cmdr_addrrand_2ff <= param_cmdr_addrrand_ff;
rand_addr_n_tmpc <= rand_addr_n - (param_cmdr_addrrand_ff & 32'hFFFFF000);
rand_addr_n_tmp <= param_cmdr_addrrand_2ff - rand_addr_n_tmpc;
end
wire newcmdr_param_valid = cmd_out_mr[63];
wire param_cmdr_repeatop_valid = newcmdr_param_valid &&
paramram_mr_regslice[23:1] != 23'h0 && // need value >1
paramram_mr_regslice[31:29] == `SQOP_REPEATOP;
assign param_cmdr_repeatfixedop_valid = newcmdr_param_valid &&
paramram_mr_regslice[31:29] == `SQOP_FIXEDREPEATOP;
assign param_cmdr_delayop_valid = newcmdr_param_valid &&
paramram_mr_regslice[31:29] == `SQOP_DELAYOP;
always @(*)
begin
param_cmdr_state_nxt = param_cmdr_state_ff;
param_cmdr_submitcnt_nxt = param_cmdr_submitcnt_ff;
param_cmdr_addr_nxt = param_cmdr_addr_ff;
param_cmdr_disable_submitincr = 1'b0;
param_cmdr_addrmux = 1'b0;
four_k_bound_chk = four_k_bound_chk_ff;
case (param_cmdr_state_ff)
`SQOP_ST_IDLE :
begin
param_cmdr_submitcnt_nxt = 0 ;
param_cmdr_addr_nxt = 0;
four_k_bound_chk = cmd_out_mr_addr_align_four;
if ( param_cmdr_repeatop_valid || param_cmdr_repeatfixedop_valid )
begin
param_cmdr_disable_submitincr = 1'b1;
if (param_cmdr_addrrand_valid & ~param_cmdr_addrrand[11])
begin
param_cmdr_addr_nxt = param_cmdr_addrrand;
end
else
begin
param_cmdr_addr_nxt = cmd_out_mr[31:0];
end
param_cmdr_state_nxt = `SQOP_ST_ACTIVE;
end
else
begin
param_cmdr_state_nxt = `SQOP_ST_IDLE;
end
end
`SQOP_ST_ACTIVE :
begin
if ( mar_ptr_new_ff != mar_ptr_new_2ff )
param_cmdr_submitcnt_nxt = 8'h0;
else if (mar_fifo_push_ff)
param_cmdr_submitcnt_nxt = param_cmdr_submitcnt_ff+1;
if (param_cmdr_repeatop_valid && (param_cmdr_submitcnt_ff != param_cmdr_count_minus1_ff))
param_cmdr_disable_submitincr = 1'b1;
else if (param_cmdr_repeatfixedop_valid && (param_cmdr_submitcnt_ff != C_REPEAT_COUNT))
param_cmdr_disable_submitincr = 1'b1;
if (param_cmdr_submitcnt_ff > 0 && (param_cmdr_addrrand_valid | param_cmdr_addrincr_valid))
param_cmdr_addrmux = 1'b1;
if (param_cmdr_addrrand_valid & ~param_cmdr_addrrand[11])
begin
if (param_cmdr_addrrand_2ff[31:12] != rand_addr_n_ff[31:12]) begin
if (rand_addr_n_tmp < cmd_out_mr_regslice[31:0])
param_cmdr_addr_nxt = cmd_out_mr_regslice[31:0];
else
param_cmdr_addr_nxt = rand_addr_n_tmp;
end
else begin
param_cmdr_addr_nxt = param_cmdr_addrrand_2ff;
end
end
else
begin
// special case for ix:0, which has x's on cmd_mr_out initially...
if (param_cmdr_submitcnt_ff == 0) begin
if (cmd_out_mr_comp > cmd_out_mr_addr_align_four) begin
param_cmdr_addr_nxt = cmd_out_mr_addr_align_four;
four_k_bound_chk = cmd_out_mr_addr_align_eight;
end
else begin
param_cmdr_addr_nxt = cmd_out_mr_regslice[31:0]+param_cmdr_addrincr;
four_k_bound_chk = cmd_out_mr_addr_align_four;
end
end
else if ( mar_fifo_push_ff && ~mar_fifo_push_2ff && param_cmdr_addrincr_valid) begin
//else if ( mar_fifo_push_ff && param_cmdr_addrincr_valid) begin
if (param_cmdr_addr_tmp > four_k_bound_chk_ff) begin
param_cmdr_addr_nxt = four_k_bound_chk_ff;
four_k_bound_chk = four_k_bound_chk_ff + 32'd4096;
end
else begin
param_cmdr_addr_nxt = param_cmdr_add_1;
four_k_bound_chk = four_k_bound_chk_ff;
end
end
end
if ( mar_ptr_new_ff != mar_ptr_new_2ff )
param_cmdr_state_nxt = `SQOP_ST_IDLE ;
else
param_cmdr_state_nxt = `SQOP_ST_ACTIVE ;
end
default : param_cmdr_state_nxt = param_cmdr_state_ff;
endcase
end
always @(posedge Clk) begin
cmd_out_mr_addr_align_four <= cmd_out_mr_addr_align + 32'd4096;
cmd_out_mr_addr_align_eight <= cmd_out_mr_addr_align + 32'd8192;
cmd_out_mr_comp <= cmd_out_mr_regslice[31:0]+param_cmdr_addrincr+param_cmdr_addrincr;
end
// address mode incrementing...
wire [127:0] param_cmdr_cmd_out_mr_data;
assign param_cmdr_cmd_out_mr_data[127:32] = cmd_out_mr_regslice[127:32];
assign param_cmdr_cmd_out_mr_data[31:0] = param_cmdr_addr_ff;
assign cmd_out_mr_postmux[31:0] = (param_cmdr_addrmux) ? param_cmdr_cmd_out_mr_data[31:0] : cmd_out_mr_regslice_ff[31:0];
assign cmd_out_mr_postmux[127:32] = cmd_out_mr_regslice[127:32];
// retiming for timing closure
always @(posedge Clk) begin
cmd_out_mr <= cmd_out_mr_postmux;
end
/*
* CMDW PARAM FSM / CONTROL
*
*/
reg [23:0] param_cmdw_count_ff ;
reg [2:0] param_cmdw_op_ff ;
reg [1:0] param_cmdw_addrmode_ff ;
reg [1:0] param_cmdw_intervalmode_ff;
reg param_cmdw_idmode_ff ;
wire [23:0] cmdw_rnum;
wire [15:0] w_randnum;
assign cmdw_rnum = {w_randnum[7:0],w_randnum[15:0]};
axi_traffic_gen_v2_0_7_randgen
cmdw_rand(
.seed (16'h7C9B ),
.randnum (w_randnum),
.generate_next(1'b1 ),
.reset (~rst_l ),
.clk (Clk )
);
reg [23:0] param_cmdw_count_minus1_ff ;
wire [23:0] paramram_mw_regslice_minus1 = paramram_mw_regslice[23:0]-1;
wire [23:0] param_cmdw_count_int = (paramram_mw_regslice[23:0] <= 24'd6) ? 24'b0 : paramram_mw_regslice[23:0]-24'h6;
wire [11:0] param_cmdw_dint = (paramram_mw_regslice[19:8] <= 12'd6) ? 12'b0 : paramram_mw_regslice[19:8]-12'h6;
wire [23:0] param_cmdw_count_dint = {paramram_mw_regslice[23:20],param_cmdw_dint,paramram_mw_regslice[7:0]};
assign param_cmdw_count = (param_cmdw_repeatfixedop_valid == 1'b1) ? param_cmdw_count_dint : param_cmdw_count_int;
always @(posedge Clk) begin
param_cmdw_count_ff <= paramram_mw_regslice[23:0] ;
param_cmdw_count_minus1_ff <= paramram_mw_regslice_minus1 ;
param_cmdw_addrmode_ff <= paramram_mw_regslice[25:24] ;
param_cmdw_intervalmode_ff <= paramram_mw_regslice[27:26] ;
param_cmdw_idmode_ff <= paramram_mw_regslice[28] ;
param_cmdw_op_ff <= paramram_mw_regslice[31:29] ;
end
// opcntrl signals here, will be validated by opcode field
reg [3:0] param_cmdw_addrrandrange_encoded;
always @(posedge Clk) begin
param_cmdw_addrrandrange_encoded <= paramram_mw_regslice[23:20] ;
end
reg [3:0] param_cmdw_state_nxt;
reg [23:0] param_cmdw_submitcnt_nxt;
// control for incrementing counters during special op
reg [31:0] param_cmdw_addr_ff;
reg [31:0] param_cmdw_add_1;
reg [31:0] param_cmdw_addr_nxt;
reg [31:0] param_cmdw_addr_tmp;
reg [31:0] four_k_bound_chkw;
reg [31:0] four_k_bound_chk_ffw;
reg param_cmdw_addrmux;
wire [31:0] cmd_out_mw_addr_align = cmd_out_mw_regslice[31:0] & 32'hFFFFF000;
reg [31:0] cmd_out_mw_addr_align_four;
reg [31:0] cmd_out_mw_addr_align_eight;
reg [31:0] cmd_out_mw_comp;
wire [12:0] param_cmdw_addrincr = (cmd_out_mw_regslice[39:32]+1) << param_incr_shift;
wire [12:0] param_cmdw_addrrandc = (cmd_out_mw_regslice[39:32]+1) << param_incr_shift;
reg [12:0] param_cmdw_addrincr_ff;
reg maw_fifo_push_2ff;
reg [31:0] rand_addw_n;
reg [31:0] rand_addw_n_ff;
reg [31:0] rand_addw_n_tmp;
reg [31:0] rand_addw_n_tmpc;
reg [31:0] param_cmdw_addrrand_i;
reg [31:0] param_cmdw_addrrand_i_ff;
reg [3:0] param_cmdw_state_ff;
always @(posedge Clk) begin
param_cmdw_addrincr_ff <= (rst_l) ? param_cmdw_addrincr : 13'h0;
param_cmdw_state_ff <= (rst_l) ? param_cmdw_state_nxt : `SQOP_ST_IDLE;
param_cmdw_submitcnt_ff <= (rst_l) ? param_cmdw_submitcnt_nxt : 24'h0;
param_cmdw_addr_ff <= (rst_l) ? param_cmdw_addr_nxt : 32'h0;
param_cmdw_add_1 <= (rst_l) ? param_cmdw_addr_ff+param_cmdw_addrincr_ff : 32'h0;
param_cmdw_addr_tmp <= (rst_l) ? param_cmdw_add_1+param_cmdw_addrincr_ff : 32'h0;
four_k_bound_chk_ffw <= (rst_l) ? four_k_bound_chkw : 32'h0;
maw_fifo_push_2ff <= (rst_l) ? maw_fifo_push_ff : 1'b0;
param_cmdw_addrrand_i_ff <= (rst_l) ? param_cmdw_addrrand_i : 1'b0;
end
if(C_M_AXI_DATA_WIDTH == 512) begin: RAND_W_ADDR_512_GEN
always @(*)
begin
case (param_cmdw_addrrandrange_encoded)
4'd0: param_cmdw_addrrand_i = {cmdw_rnum[10-5:0],6'b0};
4'd1: param_cmdw_addrrand_i = {cmdw_rnum[11-5:0],6'b0};
4'd2: param_cmdw_addrrand_i = {cmdw_rnum[12-5:0],6'b0};
4'd3: param_cmdw_addrrand_i = {cmdw_rnum[13-5:0],6'b0};
4'd4: param_cmdw_addrrand_i = {cmdw_rnum[14-5:0],6'b0};
4'd5: param_cmdw_addrrand_i = {cmdw_rnum[15-5:0],6'b0};
4'd6: param_cmdw_addrrand_i = {cmdw_rnum[16-5:0],6'b0};
4'd7: param_cmdw_addrrand_i = {cmdw_rnum[17-5:0],6'b0};
4'd8: param_cmdw_addrrand_i = {cmdw_rnum[18-5:0],6'b0};
4'd9: param_cmdw_addrrand_i = {cmdw_rnum[19-5:0],6'b0};
4'd10: param_cmdw_addrrand_i = {cmdw_rnum[20-5:0],6'b0};
4'd11: param_cmdw_addrrand_i = {cmdw_rnum[21-5:0],6'b0};
4'd12: param_cmdw_addrrand_i = {cmdw_rnum[22-5:0],6'b0};
4'd13: param_cmdw_addrrand_i = {cmdw_rnum[23-5:0],6'b0};
4'd14: param_cmdw_addrrand_i = {cmdw_rnum[23-5:0],6'b0};
4'd15: param_cmdw_addrrand_i = {cmdw_rnum[23-5:0],6'b0};
endcase
end
end
if(C_M_AXI_DATA_WIDTH == 256) begin: RAND_W_ADDR_256_GEN
always @(*)
begin
case (param_cmdw_addrrandrange_encoded)
4'd0: param_cmdw_addrrand_i = {cmdw_rnum[10-4:0],5'b0};
4'd1: param_cmdw_addrrand_i = {cmdw_rnum[11-4:0],5'b0};
4'd2: param_cmdw_addrrand_i = {cmdw_rnum[12-4:0],5'b0};
4'd3: param_cmdw_addrrand_i = {cmdw_rnum[13-4:0],5'b0};
4'd4: param_cmdw_addrrand_i = {cmdw_rnum[14-4:0],5'b0};
4'd5: param_cmdw_addrrand_i = {cmdw_rnum[15-4:0],5'b0};
4'd6: param_cmdw_addrrand_i = {cmdw_rnum[16-4:0],5'b0};
4'd7: param_cmdw_addrrand_i = {cmdw_rnum[17-4:0],5'b0};
4'd8: param_cmdw_addrrand_i = {cmdw_rnum[18-4:0],5'b0};
4'd9: param_cmdw_addrrand_i = {cmdw_rnum[19-4:0],5'b0};
4'd10: param_cmdw_addrrand_i = {cmdw_rnum[20-4:0],5'b0};
4'd11: param_cmdw_addrrand_i = {cmdw_rnum[21-4:0],5'b0};
4'd12: param_cmdw_addrrand_i = {cmdw_rnum[22-4:0],5'b0};
4'd13: param_cmdw_addrrand_i = {cmdw_rnum[23-4:0],5'b0};
4'd14: param_cmdw_addrrand_i = {cmdw_rnum[23-4:0],5'b0};
4'd15: param_cmdw_addrrand_i = {cmdw_rnum[23-4:0],5'b0};
endcase
end
end
if(C_M_AXI_DATA_WIDTH == 128) begin: RAND_W_ADDR_128_GEN
always @(*)
begin
case (param_cmdw_addrrandrange_encoded)
4'd0: param_cmdw_addrrand_i = {cmdw_rnum[10-3:0],4'b0};
4'd1: param_cmdw_addrrand_i = {cmdw_rnum[11-3:0],4'b0};
4'd2: param_cmdw_addrrand_i = {cmdw_rnum[12-3:0],4'b0};
4'd3: param_cmdw_addrrand_i = {cmdw_rnum[13-3:0],4'b0};
4'd4: param_cmdw_addrrand_i = {cmdw_rnum[14-3:0],4'b0};
4'd5: param_cmdw_addrrand_i = {cmdw_rnum[15-3:0],4'b0};
4'd6: param_cmdw_addrrand_i = {cmdw_rnum[16-3:0],4'b0};
4'd7: param_cmdw_addrrand_i = {cmdw_rnum[17-3:0],4'b0};
4'd8: param_cmdw_addrrand_i = {cmdw_rnum[18-3:0],4'b0};
4'd9: param_cmdw_addrrand_i = {cmdw_rnum[19-3:0],4'b0};
4'd10: param_cmdw_addrrand_i = {cmdw_rnum[20-3:0],4'b0};
4'd11: param_cmdw_addrrand_i = {cmdw_rnum[21-3:0],4'b0};
4'd12: param_cmdw_addrrand_i = {cmdw_rnum[22-3:0],4'b0};
4'd13: param_cmdw_addrrand_i = {cmdw_rnum[23-3:0],4'b0};
4'd14: param_cmdw_addrrand_i = {cmdw_rnum[23-3:0],4'b0};
4'd15: param_cmdw_addrrand_i = {cmdw_rnum[23-3:0],4'b0};
endcase
end
end
if(C_M_AXI_DATA_WIDTH == 64) begin: RAND_W_ADDR_64_GEN
always @(*)
begin
case (param_cmdw_addrrandrange_encoded)
4'd0: param_cmdw_addrrand_i = {cmdw_rnum[10-2:0],3'b0};
4'd1: param_cmdw_addrrand_i = {cmdw_rnum[11-2:0],3'b0};
4'd2: param_cmdw_addrrand_i = {cmdw_rnum[12-2:0],3'b0};
4'd3: param_cmdw_addrrand_i = {cmdw_rnum[13-2:0],3'b0};
4'd4: param_cmdw_addrrand_i = {cmdw_rnum[14-2:0],3'b0};
4'd5: param_cmdw_addrrand_i = {cmdw_rnum[15-2:0],3'b0};
4'd6: param_cmdw_addrrand_i = {cmdw_rnum[16-2:0],3'b0};
4'd7: param_cmdw_addrrand_i = {cmdw_rnum[17-2:0],3'b0};
4'd8: param_cmdw_addrrand_i = {cmdw_rnum[18-2:0],3'b0};
4'd9: param_cmdw_addrrand_i = {cmdw_rnum[19-2:0],3'b0};
4'd10: param_cmdw_addrrand_i = {cmdw_rnum[20-2:0],3'b0};
4'd11: param_cmdw_addrrand_i = {cmdw_rnum[21-2:0],3'b0};
4'd12: param_cmdw_addrrand_i = {cmdw_rnum[22-2:0],3'b0};
4'd13: param_cmdw_addrrand_i = {cmdw_rnum[23-2:0],3'b0};
4'd14: param_cmdw_addrrand_i = {cmdw_rnum[23-2:0],3'b0};
4'd15: param_cmdw_addrrand_i = {cmdw_rnum[23-2:0],3'b0};
endcase
end
end
if(C_M_AXI_DATA_WIDTH == 32) begin: RAND_W_ADDR_32_GEN
always @(*)
begin
case (param_cmdw_addrrandrange_encoded)
4'd0: param_cmdw_addrrand_i = {cmdw_rnum[10-1:0],2'b0};
4'd1: param_cmdw_addrrand_i = {cmdw_rnum[11-1:0],2'b0};
4'd2: param_cmdw_addrrand_i = {cmdw_rnum[12-1:0],2'b0};
4'd3: param_cmdw_addrrand_i = {cmdw_rnum[13-1:0],2'b0};
4'd4: param_cmdw_addrrand_i = {cmdw_rnum[14-1:0],2'b0};
4'd5: param_cmdw_addrrand_i = {cmdw_rnum[15-1:0],2'b0};
4'd6: param_cmdw_addrrand_i = {cmdw_rnum[16-1:0],2'b0};
4'd7: param_cmdw_addrrand_i = {cmdw_rnum[17-1:0],2'b0};
4'd8: param_cmdw_addrrand_i = {cmdw_rnum[18-1:0],2'b0};
4'd9: param_cmdw_addrrand_i = {cmdw_rnum[19-1:0],2'b0};
4'd10: param_cmdw_addrrand_i = {cmdw_rnum[20-1:0],2'b0};
4'd11: param_cmdw_addrrand_i = {cmdw_rnum[21-1:0],2'b0};
4'd12: param_cmdw_addrrand_i = {cmdw_rnum[22-1:0],2'b0};
4'd13: param_cmdw_addrrand_i = {cmdw_rnum[23-1:0],2'b0};
4'd14: param_cmdw_addrrand_i = {cmdw_rnum[23-1:0],2'b0};
4'd15: param_cmdw_addrrand_i = {cmdw_rnum[23-1:0],2'b0};
endcase
end
end
reg param_cmdw_maxaddr_check_32b,param_cmdw_maxaddr_check_64b,param_cmdw_maxaddr_check_128b,param_cmdw_maxaddr_check_256b,param_cmdw_maxaddr_check_512b;
if(C_M_AXI_DATA_WIDTH == 32) begin: RAND_W_ADDR_32_CHK
always @(*)
begin
//Set all other checks to 0
param_cmdw_maxaddr_check_64b = 1'b0;
param_cmdw_maxaddr_check_128b = 1'b0;
param_cmdw_maxaddr_check_256b = 1'b0;
param_cmdw_maxaddr_check_512b = 1'b0;
case (param_cmdw_addrrandrange_encoded)
4'd0: param_cmdw_maxaddr_check_32b = (cmdw_rnum[9:8] == 2'h3) && (C_M_AXI_DATA_WIDTH == 32);
4'd1: param_cmdw_maxaddr_check_32b = (cmdw_rnum[10:8]== 3'h7) && (C_M_AXI_DATA_WIDTH == 32);
4'd2: param_cmdw_maxaddr_check_32b = (cmdw_rnum[11:8]== 4'hf) && (C_M_AXI_DATA_WIDTH == 32);
4'd3: param_cmdw_maxaddr_check_32b = (cmdw_rnum[12:8]== 5'h1f) && (C_M_AXI_DATA_WIDTH == 32);
4'd4: param_cmdw_maxaddr_check_32b = (cmdw_rnum[13:8]== 6'h3f) && (C_M_AXI_DATA_WIDTH == 32);
4'd5: param_cmdw_maxaddr_check_32b = (cmdw_rnum[14:8]== 7'h7f) && (C_M_AXI_DATA_WIDTH == 32);
4'd6: param_cmdw_maxaddr_check_32b = (cmdw_rnum[15:8]== 8'hff) && (C_M_AXI_DATA_WIDTH == 32);
4'd7: param_cmdw_maxaddr_check_32b = (cmdw_rnum[16:8]== 9'h1ff) && (C_M_AXI_DATA_WIDTH == 32);
4'd8: param_cmdw_maxaddr_check_32b = (cmdw_rnum[17:8]== 10'h3ff) && (C_M_AXI_DATA_WIDTH == 32);
4'd9: param_cmdw_maxaddr_check_32b = (cmdw_rnum[18:8]== 11'h7ff) && (C_M_AXI_DATA_WIDTH == 32);
4'd10: param_cmdw_maxaddr_check_32b = (cmdw_rnum[19:8]== 12'hfff) && (C_M_AXI_DATA_WIDTH == 32);
4'd11: param_cmdw_maxaddr_check_32b = (cmdw_rnum[20:8]== 13'h1fff) && (C_M_AXI_DATA_WIDTH == 32);
4'd12: param_cmdw_maxaddr_check_32b = (cmdw_rnum[21:8]== 14'h3fff) && (C_M_AXI_DATA_WIDTH == 32);
4'd13: param_cmdw_maxaddr_check_32b = (cmdw_rnum[22:8]== 15'h7fff) && (C_M_AXI_DATA_WIDTH == 32);
4'd14: param_cmdw_maxaddr_check_32b = (cmdw_rnum[23:8]== 16'hffff) && (C_M_AXI_DATA_WIDTH == 32);
4'd15: param_cmdw_maxaddr_check_32b = (cmdw_rnum[23:8]== 16'hffff) && (C_M_AXI_DATA_WIDTH == 32);
endcase
end // always @ begin
end
if(C_M_AXI_DATA_WIDTH == 64) begin: RAND_W_ADDR_64_CHK
always @(*)
begin
//Set all other checks to 0
param_cmdw_maxaddr_check_32b = 1'b0;
param_cmdw_maxaddr_check_128b = 1'b0;
param_cmdw_maxaddr_check_256b = 1'b0;
param_cmdw_maxaddr_check_512b = 1'b0;
case (param_cmdw_addrrandrange_encoded)
4'd0: param_cmdw_maxaddr_check_64b = (cmdw_rnum[9:9] == 1'h1) && (C_M_AXI_DATA_WIDTH == 64);
4'd1: param_cmdw_maxaddr_check_64b = (cmdw_rnum[10:9]== 2'h3) && (C_M_AXI_DATA_WIDTH == 64);
4'd2: param_cmdw_maxaddr_check_64b = (cmdw_rnum[11:9]== 3'h7) && (C_M_AXI_DATA_WIDTH == 64);
4'd3: param_cmdw_maxaddr_check_64b = (cmdw_rnum[12:9]== 4'hf) && (C_M_AXI_DATA_WIDTH == 64);
4'd4: param_cmdw_maxaddr_check_64b = (cmdw_rnum[13:9]== 5'h1f) && (C_M_AXI_DATA_WIDTH == 64);
4'd5: param_cmdw_maxaddr_check_64b = (cmdw_rnum[14:9]== 6'h3f) && (C_M_AXI_DATA_WIDTH == 64);
4'd6: param_cmdw_maxaddr_check_64b = (cmdw_rnum[15:9]== 7'h7f) && (C_M_AXI_DATA_WIDTH == 64);
4'd7: param_cmdw_maxaddr_check_64b = (cmdw_rnum[16:9]== 8'hff) && (C_M_AXI_DATA_WIDTH == 64);
4'd8: param_cmdw_maxaddr_check_64b = (cmdw_rnum[17:9]== 9'h1ff) && (C_M_AXI_DATA_WIDTH == 64);
4'd9: param_cmdw_maxaddr_check_64b = (cmdw_rnum[18:9]== 10'h3ff) && (C_M_AXI_DATA_WIDTH == 64);
4'd10: param_cmdw_maxaddr_check_64b = (cmdw_rnum[19:9]== 11'h7ff) && (C_M_AXI_DATA_WIDTH == 64);
4'd11: param_cmdw_maxaddr_check_64b = (cmdw_rnum[20:9]== 12'hfff) && (C_M_AXI_DATA_WIDTH == 64);
4'd12: param_cmdw_maxaddr_check_64b = (cmdw_rnum[21:9]== 13'h1fff) && (C_M_AXI_DATA_WIDTH == 64);
4'd13: param_cmdw_maxaddr_check_64b = (cmdw_rnum[22:9]== 14'h3fff) && (C_M_AXI_DATA_WIDTH == 64);
4'd14: param_cmdw_maxaddr_check_64b = (cmdw_rnum[23:9]== 15'h7fff) && (C_M_AXI_DATA_WIDTH == 64);
4'd15: param_cmdw_maxaddr_check_64b = (cmdw_rnum[23:9]== 15'h7fff) && (C_M_AXI_DATA_WIDTH == 64);
endcase
end // always @ begin
end
if(C_M_AXI_DATA_WIDTH == 128) begin: RAND_W_ADDR_128_CHK
always @(*)
begin
//Set all other checks to 0
param_cmdw_maxaddr_check_32b = 1'b0;
param_cmdw_maxaddr_check_64b = 1'b0;
param_cmdw_maxaddr_check_256b = 1'b0;
param_cmdw_maxaddr_check_512b = 1'b0;
case (param_cmdw_addrrandrange_encoded)
//4'd0: param_cmdw_maxaddr_check_128b = (cmdw_rnum[10:10] == 1'h1) && (C_M_AXI_DATA_WIDTH >= 128);
4'd0: param_cmdw_maxaddr_check_128b = (cmdw_rnum[8:8]== 1'h1) && (C_M_AXI_DATA_WIDTH == 128);
4'd1: param_cmdw_maxaddr_check_128b = (cmdw_rnum[9:8]== 2'h3) && (C_M_AXI_DATA_WIDTH == 128);
4'd2: param_cmdw_maxaddr_check_128b = (cmdw_rnum[10:8]== 3'h7) && (C_M_AXI_DATA_WIDTH == 128);
4'd3: param_cmdw_maxaddr_check_128b = (cmdw_rnum[11:8]== 4'hf) && (C_M_AXI_DATA_WIDTH == 128);
4'd4: param_cmdw_maxaddr_check_128b = (cmdw_rnum[12:8]== 5'h1f) && (C_M_AXI_DATA_WIDTH == 128);
4'd5: param_cmdw_maxaddr_check_128b = (cmdw_rnum[13:8]== 6'h3f) && (C_M_AXI_DATA_WIDTH == 128);
4'd6: param_cmdw_maxaddr_check_128b = (cmdw_rnum[14:8]== 7'h7f) && (C_M_AXI_DATA_WIDTH == 128);
4'd7: param_cmdw_maxaddr_check_128b = (cmdw_rnum[15:8]== 8'hff) && (C_M_AXI_DATA_WIDTH == 128);
4'd8: param_cmdw_maxaddr_check_128b = (cmdw_rnum[16:8]== 9'h1ff) && (C_M_AXI_DATA_WIDTH == 128);
4'd9: param_cmdw_maxaddr_check_128b = (cmdw_rnum[17:8]== 10'h3ff) && (C_M_AXI_DATA_WIDTH == 128);
4'd10: param_cmdw_maxaddr_check_128b = (cmdw_rnum[18:8]== 11'h7ff) && (C_M_AXI_DATA_WIDTH == 128);
4'd11: param_cmdw_maxaddr_check_128b = (cmdw_rnum[19:8]== 12'hfff) && (C_M_AXI_DATA_WIDTH == 128);
4'd12: param_cmdw_maxaddr_check_128b = (cmdw_rnum[20:8]== 13'h1fff) && (C_M_AXI_DATA_WIDTH == 128);
4'd13: param_cmdw_maxaddr_check_128b = (cmdw_rnum[21:8]== 14'h3fff) && (C_M_AXI_DATA_WIDTH == 128);
4'd14: param_cmdw_maxaddr_check_128b = (cmdw_rnum[22:8]== 15'h7fff) && (C_M_AXI_DATA_WIDTH == 128);
4'd15: param_cmdw_maxaddr_check_128b = (cmdw_rnum[22:8]== 15'h7fff) && (C_M_AXI_DATA_WIDTH == 128);
endcase
end // always @ begin
end
if(C_M_AXI_DATA_WIDTH == 256) begin: RAND_W_ADDR_256_CHK
always @(*)
begin
//Set all other checks to 0
param_cmdw_maxaddr_check_32b = 1'b0;
param_cmdw_maxaddr_check_64b = 1'b0;
param_cmdw_maxaddr_check_128b = 1'b0;
param_cmdw_maxaddr_check_512b = 1'b0;
case (param_cmdw_addrrandrange_encoded)
//4'd0: param_cmdw_maxaddr_check_256b = (cmdw_rnum[10:10] == 1'h1) && (C_M_AXI_DATA_WIDTH >= 256);
4'd0: param_cmdw_maxaddr_check_256b = (cmdw_rnum[7:7]== 1'h1) && (C_M_AXI_DATA_WIDTH == 256);
4'd1: param_cmdw_maxaddr_check_256b = (cmdw_rnum[8:7]== 2'h3) && (C_M_AXI_DATA_WIDTH == 256);
4'd2: param_cmdw_maxaddr_check_256b = (cmdw_rnum[9:7]== 3'h7) && (C_M_AXI_DATA_WIDTH == 256);
4'd3: param_cmdw_maxaddr_check_256b = (cmdw_rnum[10:7]== 4'hf) && (C_M_AXI_DATA_WIDTH == 256);
4'd4: param_cmdw_maxaddr_check_256b = (cmdw_rnum[11:7]== 5'h1f) && (C_M_AXI_DATA_WIDTH == 256);
4'd5: param_cmdw_maxaddr_check_256b = (cmdw_rnum[12:7]== 6'h2f) && (C_M_AXI_DATA_WIDTH == 256);
4'd6: param_cmdw_maxaddr_check_256b = (cmdw_rnum[13:7]== 7'h7f) && (C_M_AXI_DATA_WIDTH == 256);
4'd7: param_cmdw_maxaddr_check_256b = (cmdw_rnum[14:7]== 8'hff) && (C_M_AXI_DATA_WIDTH == 256);
4'd8: param_cmdw_maxaddr_check_256b = (cmdw_rnum[15:7]== 9'h1ff) && (C_M_AXI_DATA_WIDTH == 256);
4'd9: param_cmdw_maxaddr_check_256b = (cmdw_rnum[16:7]== 10'h3ff) && (C_M_AXI_DATA_WIDTH == 256);
4'd10: param_cmdw_maxaddr_check_256b = (cmdw_rnum[17:7]== 11'h7ff) && (C_M_AXI_DATA_WIDTH == 256);
4'd11: param_cmdw_maxaddr_check_256b = (cmdw_rnum[18:7]== 12'hfff) && (C_M_AXI_DATA_WIDTH == 256);
4'd12: param_cmdw_maxaddr_check_256b = (cmdw_rnum[19:7]== 13'h1fff) && (C_M_AXI_DATA_WIDTH == 256);
4'd13: param_cmdw_maxaddr_check_256b = (cmdw_rnum[20:7]== 14'h3fff) && (C_M_AXI_DATA_WIDTH == 256);
4'd14: param_cmdw_maxaddr_check_256b = (cmdw_rnum[21:7]== 15'h7fff) && (C_M_AXI_DATA_WIDTH == 256);
4'd15: param_cmdw_maxaddr_check_256b = (cmdw_rnum[21:7]== 15'h7fff) && (C_M_AXI_DATA_WIDTH == 256);
endcase
end // always @ begin
end
if(C_M_AXI_DATA_WIDTH == 512) begin: RAND_W_ADDR_512_CHK
always @(*)
begin
//Set all other checks to 0
param_cmdw_maxaddr_check_32b = 1'b0;
param_cmdw_maxaddr_check_64b = 1'b0;
param_cmdw_maxaddr_check_128b = 1'b0;
param_cmdw_maxaddr_check_256b = 1'b0;
case (param_cmdw_addrrandrange_encoded)
//4'd0: param_cmdw_maxaddr_check_512b = (cmdw_rnum[10:10] == 1'h1) && (C_M_AXI_DATA_WIDTH >= 512);
4'd0: param_cmdw_maxaddr_check_512b = (cmdw_rnum[6:6]== 1'h1) && (C_M_AXI_DATA_WIDTH == 512);
4'd1: param_cmdw_maxaddr_check_512b = (cmdw_rnum[7:6]== 2'h3) && (C_M_AXI_DATA_WIDTH == 512);
4'd2: param_cmdw_maxaddr_check_512b = (cmdw_rnum[8:6]== 3'h7) && (C_M_AXI_DATA_WIDTH == 512);
4'd3: param_cmdw_maxaddr_check_512b = (cmdw_rnum[9:6]== 4'hf) && (C_M_AXI_DATA_WIDTH == 512);
4'd4: param_cmdw_maxaddr_check_512b = (cmdw_rnum[10:6]== 5'h1f) && (C_M_AXI_DATA_WIDTH == 512);
4'd5: param_cmdw_maxaddr_check_512b = (cmdw_rnum[11:6]== 6'h2f) && (C_M_AXI_DATA_WIDTH == 512);
4'd6: param_cmdw_maxaddr_check_512b = (cmdw_rnum[12:6]== 7'h7f) && (C_M_AXI_DATA_WIDTH == 512);
4'd7: param_cmdw_maxaddr_check_512b = (cmdw_rnum[13:6]== 8'hff) && (C_M_AXI_DATA_WIDTH == 512);
4'd8: param_cmdw_maxaddr_check_512b = (cmdw_rnum[14:6]== 9'h1ff) && (C_M_AXI_DATA_WIDTH == 512);
4'd9: param_cmdw_maxaddr_check_512b = (cmdw_rnum[15:6]== 10'h3ff) && (C_M_AXI_DATA_WIDTH == 512);
4'd10: param_cmdw_maxaddr_check_512b = (cmdw_rnum[16:6]== 11'h7ff) && (C_M_AXI_DATA_WIDTH == 512);
4'd11: param_cmdw_maxaddr_check_512b = (cmdw_rnum[17:6]== 12'hfff) && (C_M_AXI_DATA_WIDTH == 512);
4'd12: param_cmdw_maxaddr_check_512b = (cmdw_rnum[18:6]== 13'h1fff) && (C_M_AXI_DATA_WIDTH == 512);
4'd13: param_cmdw_maxaddr_check_512b = (cmdw_rnum[19:6]== 14'h3fff) && (C_M_AXI_DATA_WIDTH == 512);
4'd14: param_cmdw_maxaddr_check_512b = (cmdw_rnum[20:6]== 15'h7fff) && (C_M_AXI_DATA_WIDTH == 512);
4'd15: param_cmdw_maxaddr_check_512b = (cmdw_rnum[20:6]== 15'h7fff) && (C_M_AXI_DATA_WIDTH == 512);
endcase
end // always @ begin
end
reg [31:0] param_cmdw_addrrand_ff;
reg [31:0] param_cmdw_addrrand_2ff;
reg [31:0] rand_base_chkw_t_ff;
reg [31:0] rand_base_chkw_ff;
wire [31:0] rand_base_chkw_t = cmd_out_mw_regslice[31:0] + param_cmdw_addrrand_i_ff;
wire [31:0] rand_base_chkw = rand_base_chkw_t_ff - param_maxburstbytes;
wire [31:0] param_cmdw_addrrand = (param_cmdw_maxaddr_check_512b | param_cmdw_maxaddr_check_256b | param_cmdw_maxaddr_check_128b | param_cmdw_maxaddr_check_64b | param_cmdw_maxaddr_check_32b) ?
(cmd_out_mw_regslice[31:0] > rand_base_chkw_ff) ? cmd_out_mw_regslice[31:0] : rand_base_chkw_ff :
(cmd_out_mw_regslice[31:0] + param_cmdw_addrrand_i_ff);
assign param_cmdw_addrrand_valid = ( param_cmdw_addrmode_ff == `SQOP_ADDRMODE_RAND );
assign param_cmdw_addrincr_valid = ( param_cmdw_addrmode_ff == `SQOP_ADDRMODE_INCR );
assign param_cmdw_intervalrand_valid = ( param_cmdw_intervalmode_ff == `SQOP_INTERVALMODE_RAND );
always @(posedge Clk) begin
rand_base_chkw_ff <= rand_base_chkw;
rand_base_chkw_t_ff <= rand_base_chkw_t;
rand_addw_n_ff <= rand_addw_n;
rand_addw_n <= param_cmdw_addrrand + param_cmdw_addrrandc;
end
always @(posedge Clk) begin
param_cmdw_addrrand_ff <= param_cmdw_addrrand;
param_cmdw_addrrand_2ff <= param_cmdw_addrrand_ff;
rand_addw_n_tmpc <= rand_addw_n - (param_cmdw_addrrand_ff & 32'hFFFFF000);
rand_addw_n_tmp <= param_cmdw_addrrand_2ff - rand_addw_n_tmpc;
end
wire newcmdw_param_valid = cmd_out_mw[63];
wire param_cmdw_repeatop_valid = newcmdw_param_valid &&
paramram_mw_regslice[23:1] != 23'h0 && // need value >1
paramram_mw_regslice[31:29] == `SQOP_REPEATOP;
assign param_cmdw_repeatfixedop_valid = newcmdw_param_valid &&
paramram_mw_regslice[31:29] == `SQOP_FIXEDREPEATOP;
assign param_cmdw_delayop_valid = newcmdw_param_valid &&
paramram_mw_regslice[31:29] == `SQOP_DELAYOP;
always @(*)
begin
param_cmdw_state_nxt = param_cmdw_state_ff;
param_cmdw_submitcnt_nxt = param_cmdw_submitcnt_ff;
param_cmdw_addr_nxt = param_cmdw_addr_ff;
param_cmdw_disable_submitincr = 1'b0;
param_cmdw_addrmux = 1'b0;
four_k_bound_chkw = four_k_bound_chk_ffw;
case (param_cmdw_state_ff)
`SQOP_ST_IDLE :
begin
param_cmdw_submitcnt_nxt = 0;
param_cmdw_addr_nxt = 0;
four_k_bound_chkw = cmd_out_mw_addr_align+32'd4096;
if ( param_cmdw_repeatop_valid || param_cmdw_repeatfixedop_valid )
begin
param_cmdw_disable_submitincr = 1'b1;
if (param_cmdw_addrrand_valid & ~param_cmdw_addrrand[11])
begin
param_cmdw_addr_nxt = param_cmdw_addrrand;
end
else
begin
param_cmdw_addr_nxt = cmd_out_mw[31:0];
end
param_cmdw_state_nxt = `SQOP_ST_ACTIVE;
end
else
begin
param_cmdw_state_nxt = `SQOP_ST_IDLE;
end
end
`SQOP_ST_ACTIVE :
begin
//rand_addw_n = param_cmdw_addrrand+param_cmdw_addrrandc;
//rand_addw_n_tmp = param_cmdw_addrrand - (rand_addw_n - (param_cmdw_addrrand & 32'hFFFFF000));
if ( maw_ptr_new_ff != maw_ptr_new_2ff )
param_cmdw_submitcnt_nxt = 8'h0;
else if (maw_fifo_push_ff)
param_cmdw_submitcnt_nxt = param_cmdw_submitcnt_ff+1;
if (param_cmdw_repeatop_valid && (param_cmdw_submitcnt_ff != param_cmdw_count_minus1_ff))
param_cmdw_disable_submitincr = 1'b1;
else if (param_cmdw_repeatfixedop_valid && (param_cmdw_submitcnt_ff != C_REPEAT_COUNT))
param_cmdw_disable_submitincr = 1'b1;
if (param_cmdw_submitcnt_ff > 0 && (param_cmdw_addrrand_valid | param_cmdw_addrincr_valid))
param_cmdw_addrmux = 1'b1;
if (param_cmdw_addrrand_valid & ~param_cmdw_addrrand[11])
begin
if (param_cmdw_addrrand_2ff[31:12] != rand_addw_n_ff[31:12]) begin
if (rand_addw_n_tmp < cmd_out_mw_regslice[31:0])
param_cmdw_addr_nxt = cmd_out_mw_regslice[31:0];
else
param_cmdw_addr_nxt = rand_addw_n_tmp;
end
else begin
param_cmdw_addr_nxt = param_cmdw_addrrand_2ff;
end
end
else
begin
// special case for ix:0, which has x's on cmd_mr_out initially...
if (param_cmdw_submitcnt_ff == 0) begin
if (cmd_out_mw_comp > cmd_out_mw_addr_align_four) begin
param_cmdw_addr_nxt = cmd_out_mw_addr_align_four;
four_k_bound_chkw = cmd_out_mw_addr_align_eight;
end
else begin
param_cmdw_addr_nxt = cmd_out_mw_regslice[31:0]+param_cmdw_addrincr;
four_k_bound_chkw = cmd_out_mw_addr_align_four;
end
end
else if ( maw_fifo_push_ff && ~maw_fifo_push_2ff && param_cmdw_addrincr_valid) begin
//else if ( maw_fifo_push_ff && param_cmdw_addrincr_valid) begin
if (param_cmdw_addr_tmp > four_k_bound_chk_ffw) begin
param_cmdw_addr_nxt = four_k_bound_chk_ffw;
four_k_bound_chkw = four_k_bound_chk_ffw + 32'd4096;
end
else begin
param_cmdw_addr_nxt = param_cmdw_add_1;
four_k_bound_chkw = four_k_bound_chk_ffw;
end
end
end
if ( maw_ptr_new_ff != maw_ptr_new_2ff )
param_cmdw_state_nxt = `SQOP_ST_IDLE ;
else
param_cmdw_state_nxt = `SQOP_ST_ACTIVE ;
end
default : param_cmdw_state_nxt <= param_cmdw_state_ff;
endcase
end
always @(posedge Clk) begin
cmd_out_mw_addr_align_four <= cmd_out_mw_addr_align + 32'd4096;
cmd_out_mw_addr_align_eight <= cmd_out_mw_addr_align + 32'd8192;
cmd_out_mw_comp <= cmd_out_mw_regslice[31:0]+param_cmdw_addrincr+param_cmdw_addrincr;
end
// address mode incrementing...
wire [127:0] param_cmdw_cmd_out_mw_data;
assign param_cmdw_cmd_out_mw_data[127:32] = cmd_out_mw_regslice[127:32];
assign param_cmdw_cmd_out_mw_data[31:0] = param_cmdw_addr_ff;
assign cmd_out_mw_postmux[31:0] = (param_cmdw_addrmux) ? param_cmdw_cmd_out_mw_data[31:0] : cmd_out_mw_regslice_ff[31:0];
assign cmd_out_mw_postmux[127:32] = cmd_out_mw_regslice[127:32];
always @(posedge Clk) begin
cmd_out_mw <= cmd_out_mw_postmux;
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A222O_PP_SYMBOL_V
`define SKY130_FD_SC_MS__A222O_PP_SYMBOL_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a222o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
input C2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A222O_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__ISOBUFSRC_16_V
`define SKY130_FD_SC_HDLL__ISOBUFSRC_16_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog wrapper for isobufsrc with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__isobufsrc.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__isobufsrc_16 (
X ,
SLEEP,
A ,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input SLEEP;
input A ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__isobufsrc_16 (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__ISOBUFSRC_16_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcieCore_pcie_bram_top_7x.v
// Version : 1.11
// Description : bram wrapper for Tx and Rx
// given the pcie block attributes calculate the number of brams
// and pipeline stages and instantiate the brams
//
// Hierarchy:
// pcie_bram_top top level
// pcie_brams pcie_bram instantiations,
// pipeline stages (if any),
// address decode logic (if any),
// datapath muxing (if any)
// pcie_bram bram library cell wrapper
// the pcie_bram module can have a paramter that
// specifies the family (V6, V5, V4)
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
module pcieCore_pcie_bram_top_7x
#(
parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT
parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 0, // MPS Supported : 0 - 128 B, 1 - 256 B, 2 - 512 B, 3 - 1024 B
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8
parameter VC0_TX_LASTPACKET = 31, // Number of Packets in Transmit
parameter TLM_TX_OVERHEAD = 24, // Overhead Bytes for Packets (Transmit)
parameter TL_TX_RAM_RADDR_LATENCY = 1, // BRAM Read Address Latency (Transmit)
parameter TL_TX_RAM_RDATA_LATENCY = 2, // BRAM Read Data Latency (Transmit)
parameter TL_TX_RAM_WRITE_LATENCY = 1, // BRAM Write Latency (Transmit)
parameter VC0_RX_RAM_LIMIT = 'h1FFF, // RAM Size (Receive)
parameter TL_RX_RAM_RADDR_LATENCY = 1, // BRAM Read Address Latency (Receive)
parameter TL_RX_RAM_RDATA_LATENCY = 2, // BRAM Read Data Latency (Receive)
parameter TL_RX_RAM_WRITE_LATENCY = 1 // BRAM Write Latency (Receive)
)
(
input user_clk_i, // Clock input
input reset_i, // Reset input
input mim_tx_wen, // Write Enable for Transmit path BRAM
input [12:0] mim_tx_waddr, // Write Address for Transmit path BRAM
input [71:0] mim_tx_wdata, // Write Data for Transmit path BRAM
input mim_tx_ren, // Read Enable for Transmit path BRAM
input mim_tx_rce, // Read Output Register Clock Enable for Transmit path BRAM
input [12:0] mim_tx_raddr, // Read Address for Transmit path BRAM
output [71:0] mim_tx_rdata, // Read Data for Transmit path BRAM
input mim_rx_wen, // Write Enable for Receive path BRAM
input [12:0] mim_rx_waddr, // Write Enable for Receive path BRAM
input [71:0] mim_rx_wdata, // Write Enable for Receive path BRAM
input mim_rx_ren, // Read Enable for Receive path BRAM
input mim_rx_rce, // Read Output Register Clock Enable for Receive path BRAM
input [12:0] mim_rx_raddr, // Read Address for Receive path BRAM
output [71:0] mim_rx_rdata // Read Data for Receive path BRAM
);
// TX calculations
localparam MPS_BYTES = ((DEV_CAP_MAX_PAYLOAD_SUPPORTED == 0) ? 128 :
(DEV_CAP_MAX_PAYLOAD_SUPPORTED == 1) ? 256 :
(DEV_CAP_MAX_PAYLOAD_SUPPORTED == 2) ? 512 :
1024 );
localparam BYTES_TX = (VC0_TX_LASTPACKET + 1) * (MPS_BYTES + TLM_TX_OVERHEAD);
localparam ROWS_TX = 1;
localparam COLS_TX = ((BYTES_TX <= 4096) ? 1 :
(BYTES_TX <= 8192) ? 2 :
(BYTES_TX <= 16384) ? 4 :
(BYTES_TX <= 32768) ? 8 :
18
);
// RX calculations
localparam ROWS_RX = 1;
localparam COLS_RX = ((VC0_RX_RAM_LIMIT < 'h0200) ? 1 :
(VC0_RX_RAM_LIMIT < 'h0400) ? 2 :
(VC0_RX_RAM_LIMIT < 'h0800) ? 4 :
(VC0_RX_RAM_LIMIT < 'h1000) ? 8 :
18
);
initial begin
$display("[%t] %m ROWS_TX %0d COLS_TX %0d", $time, ROWS_TX, COLS_TX);
$display("[%t] %m ROWS_RX %0d COLS_RX %0d", $time, ROWS_RX, COLS_RX);
end
pcieCore_pcie_brams_7x #(
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.IMPL_TARGET ( IMPL_TARGET ),
.NUM_BRAMS ( COLS_TX ),
.RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY )
)
pcie_brams_tx (
.user_clk_i ( user_clk_i ),
.reset_i ( reset_i ),
.waddr ( mim_tx_waddr ),
.wen ( mim_tx_wen ),
.ren ( mim_tx_ren ),
.rce ( mim_tx_rce ),
.wdata ( mim_tx_wdata ),
.raddr ( mim_tx_raddr ),
.rdata ( mim_tx_rdata )
);
pcieCore_pcie_brams_7x #(
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.IMPL_TARGET ( IMPL_TARGET ),
.NUM_BRAMS ( COLS_RX ),
.RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY )
) pcie_brams_rx (
.user_clk_i ( user_clk_i ),
.reset_i ( reset_i ),
.waddr ( mim_rx_waddr ),
.wen ( mim_rx_wen ),
.ren ( mim_rx_ren ),
.rce ( mim_rx_rce ),
.wdata ( mim_rx_wdata ),
.raddr ( mim_rx_raddr ),
.rdata ( mim_rx_rdata )
);
endmodule // pcie_bram_top
|
////////////////////////////////////////////////////////////////////////////////////////////////////
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
// 02111-1307, USA.
//
// ©2013 - Roman Ovseitsev <[email protected]>
// Based on code ©2011 - X Engineering Software Systems Corp. (www.xess.com)
////////////////////////////////////////////////////////////////////////////////////////////////////
//##################################################################################################
//
// Single Port SDRAM controller for XuLA-200.
//
//##################################################################################################
`timescale 1ns / 1ps
module SdramCtrl (clk_i, lock_i, rst_i, rd_i, wr_i, earlyOpBegun_o, opBegun_o, rdPending_o, done_o,
rdDone_o, addr_i, data_i, data_o, status_o, sdCke_o, sdCe_bo, sdRas_bo, sdCas_bo,
sdWe_bo, sdBs_o, sdAddr_o, sdData_io, sdDqmh_o, sdDqml_o);
`include "Math.v"
parameter real FREQ = 12.0; // Operating frequency in MHz.
parameter PIPE_EN = 0; // If true, enable pipelined read operations.
//`define MULTIPLE_ACTIVE_ROWS_D // If defined allow an active row in each bank.
localparam IN_PHASE = 1; // SDRAM and controller work on same or opposite clock edge.
localparam MAX_NOPS = 10000; // Number of NOPs before entering self-refresh.
localparam ENABLE_REFRESH = 1; // If true, row refreshes are automatically inserted.
`ifdef MULTIPLE_ACTIVE_ROWS_D
localparam MULTIPLE_ACTIVE_ROWS = 1; // If true, allow an active row in each bank.
`else
localparam MULTIPLE_ACTIVE_ROWS = 0;
`endif
localparam DATA_WIDTH = 16; // Host & SDRAM data width.
// Parameters for Winbond W9812G6JH-6 (all times are in nanoseconds).
localparam NROWS = 4096; // Number of rows in SDRAM array.
localparam NCOLS = 512; // Number of columns in SDRAM array.
localparam HADDR_WIDTH = 23; // Host-side address width.
localparam SADDR_WIDTH = 12; // SDRAM-side address width.
localparam BANK_ADDR_WIDTH = 2; // Width of the bank address. Requires additional changes
// of logic related to activeRow_r if modified.
localparam real T_INIT = 200000.0; // min initialization interval (ns).
localparam real T_RAS = 42.0; // min interval between active to precharge commands (ns).
localparam real T_RCD = 15.0; // min interval between active and R/W commands (ns).
localparam real T_REF = 64000000.0; // maximum refresh interval (ns).
localparam real T_RFC = 60.0; // duration of refresh operation (ns).
localparam real T_RP = 15.0; // min precharge command duration (ns).
localparam real T_XSR = 72.0; // exit self-refresh time (ns).
// Host side.
input wire clk_i; // Master clock.
input wire lock_i; // True if clock is stable.
input wire rst_i; // Reset.
input wire rd_i; // Initiate read operation.
input wire wr_i; // Initiate write operation.
output reg earlyOpBegun_o; // Read/write/self-refresh op has begun (async).
output wire opBegun_o; // Read/write/self-refresh op has begun (clocked).
output reg rdPending_o; // True if read operation(s) are still in the pipeline.
output reg done_o; // Read or write operation is done_o.
output reg rdDone_o; // Read operation is done_o and data is available.
input wire [HADDR_WIDTH-1:0] addr_i; // Address from host to SDRAM.
input wire [DATA_WIDTH-1:0] data_i; // Data from host to SDRAM.
output wire [DATA_WIDTH-1:0] data_o; // Data from SDRAM to host.
output reg [3:0] status_o; // Diagnostic status of the FSM .
// SDRAM side.
output sdCke_o; // Clock-enable to SDRAM.
output sdCe_bo; // Chip-select to SDRAM.
output sdRas_bo; // SDRAM row address strobe.
output sdCas_bo; // SDRAM column address strobe.
output sdWe_bo; // SDRAM write enable.
output [BANK_ADDR_WIDTH-1:0] sdBs_o; // SDRAM bank address.
output [SADDR_WIDTH-1:0] sdAddr_o; // SDRAM row/column address.
inout [DATA_WIDTH-1:0] sdData_io; // Data to/from SDRAM.
output sdDqmh_o; // Enable upper-byte of SDRAM databus if true.
output sdDqml_o; // Enable lower-byte of SDRAM databus if true.
localparam [0:0] OUTPUT_C = 1; // direction of dataflow w.r.t. this controller.
localparam [0:0] INPUT_C = 0;
localparam [0:0] NOP_C = 0; // no operation.
localparam [0:0] READ_C = 1; // read operation.
localparam [0:0] WRITE_C = 1; // write operation.
// SDRAM timing parameters converted into clock cycles (based on FREQ).
localparam INIT_CYCLES = ceil(T_INIT*FREQ/1000.0); // SDRAM power-on initialization interval.
localparam RAS_CYCLES = ceil(T_RAS*FREQ/1000.0); // active-to-precharge interval.
localparam RCD_CYCLES = pfx(ceil(T_RCD*FREQ/1000.0)); // active-to-R/W interval.
localparam REF_CYCLES = ceil(T_REF*FREQ/1000.0/NROWS);// interval between row refreshes.
localparam RFC_CYCLES = ceil(T_RFC*FREQ/1000.0); // refresh operation interval.
localparam RP_CYCLES = ceil(T_RP*FREQ/1000.0); // precharge operation interval.
localparam WR_CYCLES = 2; // write recovery time.
localparam XSR_CYCLES = ceil(T_XSR*FREQ/1000.0); // exit self-refresh time.
localparam MODE_CYCLES = 2; // mode register setup time.
localparam CAS_CYCLES = 3; // CAS latency.
localparam RFSH_OPS_C = 8; // number of refresh operations needed to init SDRAM.
// timer registers that count down times for various SDRAM operations.
reg [clog2(INIT_CYCLES):0] timer_r = 0; // current SDRAM op time.
reg [clog2(INIT_CYCLES):0] timer_x = 0;
reg [clog2(RAS_CYCLES):0] rasTimer_r = 0; // active-to-precharge time.
reg [clog2(RAS_CYCLES):0] rasTimer_x = 0;
reg [clog2(WR_CYCLES):0] wrTimer_r = 0; // write-to-precharge time.
reg [clog2(WR_CYCLES):0] wrTimer_x = 0;
reg [clog2(REF_CYCLES):0] refTimer_r = REF_CYCLES;// time between row refreshes.
reg [clog2(REF_CYCLES):0] refTimer_x = REF_CYCLES;
reg [clog2(RFSH_OPS_C):0] rfshCntr_r = 0; // counts refreshes that are needed.
reg [clog2(RFSH_OPS_C):0] rfshCntr_x = 0;
reg [clog2(MAX_NOPS):0] nopCntr_r = 0; // counts consecutive NOP_C operations.
reg [clog2(MAX_NOPS):0] nopCntr_x = 0;
reg doSelfRfsh_s; // active when the NOP counter hits zero and self-refresh can start.
// states of the SDRAM controller state machine.
localparam [2:0] INITWAIT = 3'b000; // initialization - waiting for power-on initialization to complete.
localparam [2:0] INITPCHG = 3'b001; // initialization - initial precharge of SDRAM banks.
localparam [2:0] INITSETMODE = 3'b010; // initialization - set SDRAM mode.
localparam [2:0] INITRFSH = 3'b011; // initialization - do initial refreshes.
localparam [2:0] RW = 3'b100; // read/write/refresh the SDRAM.
localparam [2:0] ACTIVATE = 3'b101; // open a row of the SDRAM for reading/writing.
localparam [2:0] REFRESHROW = 3'b110; // refresh a row of the SDRAM.
localparam [2:0] SELFREFRESH = 3'b111; // keep SDRAM in self-refresh mode with CKE low.
reg [2:0] state_r = INITWAIT; // state register and next state.
reg [2:0] state_x = INITWAIT; // state register and next state.
// commands that are sent to the SDRAM to make it perform certain operations.
// commands use these SDRAM input pins (ce_bo,ras_bo,cas_bo,we_bo,dqmh_o,dqml_o).
localparam [5:0] NOP_CMD_C = 'b011100;
localparam [5:0] ACTIVE_CMD_C = 'b001100;
localparam [5:0] READ_CMD_C = 'b010100;
localparam [5:0] WRITE_CMD_C = 'b010000;
localparam [5:0] PCHG_CMD_C = 'b001000;
localparam [5:0] MODE_CMD_C = 'b000000;
localparam [5:0] RFSH_CMD_C = 'b000100;
// SDRAM mode register.
// the SDRAM is placed in a non-burst mode (burst length = 1) with a 3-cycle CAS.
localparam [11:0] MODE_C = 'b00_0_00_011_0_000;
// the host address is decomposed into these sets of SDRAM address components.
localparam ROW_LEN_C = clog2(NROWS); // number of row address bits.
localparam COL_LEN_C = clog2(NCOLS); // number of column address bits.
reg [BANK_ADDR_WIDTH-1:0] bank_s; // bank address bits.
reg [ROW_LEN_C-1:0] row_s; // row address within bank.
reg [COL_LEN_C-1:0] col_s; // column address within row.
// registers that store the currently active row in each bank of the SDRAM.
localparam NUM_ACTIVE_ROWS = (MULTIPLE_ACTIVE_ROWS == 0 ? 1 : 2**BANK_ADDR_WIDTH);
localparam NUM_ACTIVE_ROWS_WIDTH = (MULTIPLE_ACTIVE_ROWS == 0 ? 1 : BANK_ADDR_WIDTH);
reg [ROW_LEN_C-1:0] activeRow_r [NUM_ACTIVE_ROWS_WIDTH-1:0];
reg [ROW_LEN_C-1:0] activeRow_x [NUM_ACTIVE_ROWS_WIDTH-1:0];
reg [NUM_ACTIVE_ROWS-1:0] activeFlag_r = 0; // indicates that some row in a bank is active.
reg [NUM_ACTIVE_ROWS-1:0] activeFlag_x = 0;
reg [NUM_ACTIVE_ROWS_WIDTH-1:0] bankIndex_s; // bank address bits.
reg [BANK_ADDR_WIDTH-1:0] activeBank_r; // indicates the bank with the active row.
reg [BANK_ADDR_WIDTH-1:0] activeBank_x;
reg doActivate_s; // indicates when a new row in a bank needs to be activated.
// there is a command bit embedded within the SDRAM column address.
localparam CMDBIT_POS_C = 10; // position of command bit.
localparam [0:0] AUTO_PCHG_ON_C = 1; // CMDBIT value to auto-precharge the bank.
localparam [0:0] AUTO_PCHG_OFF_C = 0; // CMDBIT value to disable auto-precharge.
localparam ONE_BANK_C = 0; // CMDBIT value to select one bank.
localparam ALL_BANKS_C = 1; // CMDBIT value to select all banks.
// status signals that indicate when certain operations are in progress.
reg wrInProgress_s; // write operation in progress.
reg rdInProgress_s; // read operation in progress.
reg activateInProgress_s; // row activation is in progress.
// these registers track the progress of read and write operations.
reg [CAS_CYCLES+1:0] rdPipeline_r = 0;
reg [CAS_CYCLES+1:0] rdPipeline_x = 0; // pipeline of read ops in progress.
reg wrPipeline_r = 0;
reg wrPipeline_x = 0; // pipeline of write ops (only need 1 cycle).
// registered outputs to host.
reg opBegun_r = 0;
reg opBegun_x = 0; // true when SDRAM read or write operation is started.
reg [DATA_WIDTH-1:0] sdramData_r = 0;
reg [DATA_WIDTH-1:0] sdramData_x = 0; // holds data read from SDRAM and sent to the host.
reg [DATA_WIDTH-1:0] sdramDataOppPhase_r;
reg [DATA_WIDTH-1:0] sdramDataOppPhase_x; // holds data read from SDRAM on opposite clock edge.
// registered outputs to SDRAM.
reg cke_r = 0;
reg cke_x = 0; // Clock-enable bit.
reg [5:0] cmd_r = NOP_CMD_C;
reg [5:0] cmd_x = NOP_CMD_C; // SDRAM command bits.
reg [BANK_ADDR_WIDTH-1:0] ba_r;
reg [BANK_ADDR_WIDTH-1:0] ba_x; // SDRAM bank address bits.
reg [SADDR_WIDTH-1:0] sAddr_r = 0;
reg [SADDR_WIDTH-1:0] sAddr_x = 0; // SDRAM row/column address.
reg [DATA_WIDTH-1:0] sData_r = 0;
reg [DATA_WIDTH-1:0] sData_x = 0; // SDRAM out databus.
reg sDataDir_r = INPUT_C;
reg sDataDir_x = INPUT_C; // SDRAM databus direction control bit.
// attach registered SDRAM control signals to SDRAM input pins
assign {sdCe_bo, sdRas_bo, sdCas_bo, sdWe_bo, sdDqmh_o, sdDqml_o} = cmd_r; // SDRAM operation control bits
assign sdCke_o = cke_r; // SDRAM clock enable
assign sdBs_o = ba_r; // SDRAM bank address
assign sdAddr_o = sAddr_r; // SDRAM address
assign sdData_io = (sDataDir_r == OUTPUT_C) ? sData_r : 16'bz; // SDRAM output data bus
// attach some port signals
assign data_o = sdramData_r; // data back to host
assign opBegun_o = opBegun_r; // true if requested operation has begun
//*********************************************************************
// compute the next state and outputs
//*********************************************************************
always @(rd_i, wr_i, addr_i, data_i, sdramData_r, sdData_io, state_r, opBegun_x, activeFlag_r,
activeBank_r, rdPipeline_r, wrPipeline_r, sdramDataOppPhase_r, nopCntr_r,
lock_i, rfshCntr_r, timer_r, rasTimer_r, wrTimer_r, refTimer_r, cmd_r, col_s, ba_r, cke_r,
rdInProgress_s, activateInProgress_s, wrInProgress_s, doActivate_s, doSelfRfsh_s,
`ifdef MULTIPLE_ACTIVE_ROWS_D
activeRow_r[1], activeRow_r[0]
`else
activeRow_r[0]
`endif
) begin
//*********************************************************************
// setup default values for signals
//*********************************************************************
opBegun_x = 0; // no operations have begun
earlyOpBegun_o = opBegun_x;
cke_x = 1; // enable SDRAM clock
cmd_x = NOP_CMD_C; // set SDRAM command to no-operation
sDataDir_x = INPUT_C; // accept data from the SDRAM
sData_x = data_i; // output data from host to SDRAM
state_x = state_r; // reload these registers and flags
activeFlag_x = activeFlag_r; // with their existing values
`ifdef MULTIPLE_ACTIVE_ROWS_D
activeRow_x[0] = activeRow_r[0];
activeRow_x[1] = activeRow_r[1];
`else
activeRow_x[0] = activeRow_r[0];
`endif
activeBank_x = activeBank_r;
rfshCntr_x = rfshCntr_r;
//*********************************************************************
// setup default value for the SDRAM address
//*********************************************************************
// extract bank field from host address
ba_x = addr_i[BANK_ADDR_WIDTH + ROW_LEN_C + COL_LEN_C - 1 : ROW_LEN_C + COL_LEN_C];
if (MULTIPLE_ACTIVE_ROWS == 1) begin
bank_s = 0;
bankIndex_s = ba_x;
end else begin
bank_s = ba_x;
bankIndex_s = 0;
end
// extract row, column fields from host address
row_s = addr_i[ROW_LEN_C + COL_LEN_C - 1 : COL_LEN_C];
col_s[COL_LEN_C-1 : 0] = addr_i[COL_LEN_C-1 : 0];
// by default, set SDRAM address to the column address with interspersed
// command bit set to disable auto-precharge
sAddr_x = {1'b0, AUTO_PCHG_OFF_C, col_s[COL_LEN_C-1 : 0]};
//*********************************************************************
// manage the read and write operation pipelines
//*********************************************************************
// determine if read operations are in progress by the presence of
// READ flags in the read pipeline
if (rdPipeline_r[CAS_CYCLES+1 : 1] != 0) begin
rdInProgress_s = 1;
end else begin
rdInProgress_s = 0;
end
rdPending_o = rdInProgress_s; // tell the host if read operations are in progress
// enter NOPs into the read and write pipeline shift registers by default
rdPipeline_x = {NOP_C, rdPipeline_r[CAS_CYCLES+1 : 1]};
wrPipeline_x = NOP_C;
// transfer data from SDRAM to the host data register if a read flag has exited the pipeline
// (the transfer occurs 1 cycle before we tell the host the read operation is done)
if (rdPipeline_r[1] == READ_C) begin
sdramDataOppPhase_x = sdData_io[DATA_WIDTH-1:0]; // gets value on the SDRAM databus on the opposite phase
if (IN_PHASE == 1) begin
// get the SDRAM data for the host directly from the SDRAM if the controller and SDRAM are in-phase
sdramData_x = sdData_io[DATA_WIDTH-1:0];
end else begin
// otherwise get the SDRAM data that was gathered on the previous opposite clock edge
sdramData_x = sdramDataOppPhase_r[DATA_WIDTH-1:0];
end
end else begin
// retain contents of host data registers if no data from the SDRAM has arrived yet
sdramDataOppPhase_x = sdramDataOppPhase_r;
sdramData_x = sdramData_r;
end
done_o = rdPipeline_r[0] | wrPipeline_r; // a read or write operation is done
rdDone_o = rdPipeline_r[0]; // SDRAM data available when a READ flag exits the pipeline
//*********************************************************************
// manage row activation
//*********************************************************************
// request a row activation operation if the row of the current address
// does not match the currently active row in the bank, or if no row
// in the bank is currently active
if ((bank_s != activeBank_r) || (row_s != activeRow_r[bankIndex_s]) || (activeFlag_r[bankIndex_s] == 0)) begin
doActivate_s = 1;
end else begin
doActivate_s = 0;
end
//*********************************************************************
// manage self-refresh
//*********************************************************************
// enter self-refresh if neither a read or write is requested for MAX_NOP consecutive cycles.
if (rd_i == 1 || wr_i == 1) begin
// any read or write resets NOP counter and exits self-refresh state
nopCntr_x = 0;
doSelfRfsh_s = 0;
end else if (nopCntr_r != MAX_NOPS) begin
// increment NOP counter whenever there is no read or write operation
nopCntr_x = nopCntr_r + 1;
doSelfRfsh_s = 0;
end else begin
// start self-refresh when counter hits maximum NOP count and leave counter unchanged
nopCntr_x = nopCntr_r;
doSelfRfsh_s = 1;
end
//*********************************************************************
// update the timers
//*********************************************************************
// row activation timer
if (rasTimer_r != 0) begin
// decrement a non-zero timer and set the flag
// to indicate the row activation is still inprogress
rasTimer_x = rasTimer_r - 1;
activateInProgress_s = 1;
end else begin
// on timeout, keep the timer at zero and reset the flag
// to indicate the row activation operation is done
rasTimer_x = rasTimer_r;
activateInProgress_s = 0;
end
// write operation timer
if (wrTimer_r != 0) begin
// decrement a non-zero timer and set the flag
// to indicate the write operation is still inprogress
wrTimer_x = wrTimer_r - 1;
wrInProgress_s = 1;
end else begin
// on timeout, keep the timer at zero and reset the flag that
// indicates a write operation is in progress
wrTimer_x = wrTimer_r;
wrInProgress_s = 0;
end
// refresh timer
if (refTimer_r != 0) begin
refTimer_x = refTimer_r - 1;
end else begin
// on timeout, reload the timer with the interval between row refreshes
// and increment the counter for the number of row refreshes that are needed
refTimer_x = REF_CYCLES;
if (ENABLE_REFRESH == 1) begin
rfshCntr_x = rfshCntr_r + 1;
end else begin
rfshCntr_x = 0; // refresh never occurs if this counter never gets above zero
end
end
// main timer for sequencing SDRAM operations
if (timer_r != 0) begin
// decrement the timer and do nothing else since the previous operation has not completed yet.
timer_x = timer_r - 1;
status_o = 'b0000;
end else begin
// the previous operation has completed once the timer hits zero
timer_x = timer_r; // by default, leave the timer at zero
//*********************************************************************
// compute the next state and outputs
//*********************************************************************
(* parallel_case *) case (state_r)
//*********************************************************************
// let clock stabilize and then wait for the SDRAM to initialize
//*********************************************************************
INITWAIT: begin
if (lock_i == 1) begin
// wait for SDRAM power-on initialization once the clock is stable
timer_x = INIT_CYCLES; // set timer for initialization duration
state_x = INITPCHG;
end else begin
// disable SDRAM clock and return to this state if the clock is not stable
// this insures the clock is stable before enabling the SDRAM
// it also insures a clean startup if the SDRAM is currently in self-refresh mode
cke_x = 0;
end
status_o = 'b0001;
end
//*********************************************************************
// precharge all SDRAM banks after power-on initialization
//*********************************************************************
INITPCHG: begin
cmd_x = PCHG_CMD_C;
sAddr_x[CMDBIT_POS_C] = ALL_BANKS_C; // precharge all banks
timer_x = RP_CYCLES; // set timer for precharge operation duration
rfshCntr_x = RFSH_OPS_C; // set counter for refresh ops needed after precharge
state_x = INITRFSH;
status_o = 'b0010;
end
//*********************************************************************
// refresh the SDRAM a number of times after initial precharge
//*********************************************************************
INITRFSH: begin
cmd_x = RFSH_CMD_C;
timer_x = RFC_CYCLES; // set timer to refresh operation duration
rfshCntr_x = rfshCntr_r - 1; // decrement refresh operation counter
if (rfshCntr_r == 1) begin
state_x = INITSETMODE; // set the SDRAM mode once all refresh ops are done
end
status_o = 'b0011;
end
//*********************************************************************
// set the mode register of the SDRAM
//*********************************************************************
INITSETMODE: begin
cmd_x = MODE_CMD_C;
sAddr_x[11:0] = MODE_C; // output mode register bits on the SDRAM address bits
timer_x = MODE_CYCLES; // set timer for mode setting operation duration
state_x = RW;
status_o = 'b0100;
end
//*********************************************************************
// process read/write/refresh operations after initialization is done
//*********************************************************************
RW: begin
//*********************************************************************
// highest priority operation: row refresh
// do a refresh operation if the refresh counter is non-zero
//*********************************************************************
if (rfshCntr_r != 0) begin
// wait for any row activations, writes or reads to finish before doing a precharge
if (activateInProgress_s == 0 && wrInProgress_s == 0 && rdInProgress_s == 0) begin
cmd_x = PCHG_CMD_C; // initiate precharge of the SDRAM
sAddr_x[CMDBIT_POS_C] = ALL_BANKS_C; // precharge all banks
timer_x = RP_CYCLES; // set timer for this operation
activeFlag_x = 0; // all rows are inactive after a precharge operation
state_x = REFRESHROW; // refresh the SDRAM after the precharge
end
status_o = 'b0101;
//*********************************************************************
// do a host-initiated read operation
//*********************************************************************
end else if (rd_i == 1) begin
// Wait one clock cycle if the bank address has just changed and each bank has its own active row.
// This gives extra time for the row activation circuitry.
if (ba_x == ba_r || MULTIPLE_ACTIVE_ROWS == 0) begin
// activate a new row if the current read is outside the active row or bank
if (doActivate_s == 1) begin
// activate new row only if all previous activations, writes, reads are done
if (activateInProgress_s == 0 && wrInProgress_s == 0 && rdInProgress_s == 0) begin
cmd_x = PCHG_CMD_C; // initiate precharge of the SDRAM
sAddr_x[CMDBIT_POS_C] = ONE_BANK_C; // precharge this bank
timer_x = RP_CYCLES; // set timer for this operation
activeFlag_x[bankIndex_s] = 0; // rows in this bank are inactive after a precharge operation
state_x = ACTIVATE; // activate the new row after the precharge is done
end
// read from the currently active row if no previous read operation
// is in progress or if pipeline reads are enabled
// we can always initiate a read even if a write is already in progress
end else if (rdInProgress_s == 0 || PIPE_EN == 1) begin
cmd_x = READ_CMD_C; // initiate a read of the SDRAM
// insert a flag into the pipeline shift register that will exit the end
// of the shift register when the data from the SDRAM is available
rdPipeline_x = {READ_C, rdPipeline_r[CAS_CYCLES+1 : 1]};
opBegun_x = 1; // tell the host the requested operation has begun
end
end
status_o = 'b0110;
//*********************************************************************
// do a host-initiated write operation
//*********************************************************************
end else if (wr_i == 1) begin
// Wait one clock cycle if the bank address has just changed and each bank has its own active row.
// This gives extra time for the row activation circuitry.
if ((ba_x == ba_r) || (MULTIPLE_ACTIVE_ROWS == 0)) begin
// activate a new row if the current write is outside the active row or bank
if (doActivate_s == 1) begin
// activate new row only if all previous activations, writes, reads are done
if ((activateInProgress_s == 0) && (wrInProgress_s == 0) && (rdInProgress_s == 0)) begin
cmd_x = PCHG_CMD_C; // initiate precharge of the SDRAM
sAddr_x[CMDBIT_POS_C] = ONE_BANK_C; // precharge this bank
timer_x = RP_CYCLES; // set timer for this operation
activeFlag_x[bankIndex_s] = 0; // rows in this bank are inactive after a precharge operation
state_x = ACTIVATE; // activate the new row after the precharge is done
end
// write to the currently active row if no previous read operations are in progress
end else if (rdInProgress_s == 0) begin
cmd_x = WRITE_CMD_C; // initiate the write operation
sDataDir_x = OUTPUT_C; // turn on drivers to send data to SDRAM
// set timer so precharge doesn't occur too soon after write operation
wrTimer_x = WR_CYCLES;
// insert a flag into the 1-bit pipeline shift register that will exit on the
// next cycle. The write into SDRAM is not actually done by that time, but
// this doesn't matter to the host
wrPipeline_x = WRITE_C;
opBegun_x = 1; // tell the host the requested operation has begun
end
end
status_o = 'b0111;
//*********************************************************************
// do a host-initiated self-refresh operation
//*********************************************************************
end else if (doSelfRfsh_s == 1) begin
// wait until all previous activations, writes, reads are done
if ((activateInProgress_s == 0) && (wrInProgress_s == 0) && (rdInProgress_s == 0)) begin
cmd_x = PCHG_CMD_C; // initiate precharge of the SDRAM
sAddr_x[CMDBIT_POS_C] = ALL_BANKS_C; // precharge all banks
timer_x = RP_CYCLES; // set timer for this operation
activeFlag_x = 0; // all rows are inactive after a precharge operation
state_x = SELFREFRESH; // self-refresh the SDRAM after the precharge
end
status_o = 'b1000;
//*********************************************************************
// no operation
//*********************************************************************
end else begin
state_x = RW; // continue to look for SDRAM operations to execute
status_o = 'b1001;
end
end
//*********************************************************************
// activate a row of the SDRAM
//*********************************************************************
ACTIVATE: begin
cmd_x = ACTIVE_CMD_C;
sAddr_x = 0; // output the address for the row to be activated
sAddr_x[ROW_LEN_C - 1:0] = row_s;
activeBank_x = bank_s;
activeRow_x[bankIndex_s] = row_s; // store the new active SDRAM row address
activeFlag_x[bankIndex_s] = 1; // the SDRAM is now active
rasTimer_x = RAS_CYCLES; // minimum time before another precharge can occur
timer_x = RCD_CYCLES; // minimum time before a read/write operation can occur
state_x = RW; // return to do read/write operation that initiated this activation
status_o = 'b1010;
end
//*********************************************************************
// refresh a row of the SDRAM
//*********************************************************************
REFRESHROW: begin
cmd_x = RFSH_CMD_C;
timer_x = RFC_CYCLES; // refresh operation interval
rfshCntr_x = rfshCntr_r - 1; // decrement the number of needed row refreshes
state_x = RW; // process more SDRAM operations after refresh is done
status_o = 'b1011;
end
//*********************************************************************
// place the SDRAM into self-refresh and keep it there until further notice
//*********************************************************************
SELFREFRESH: begin
if (doSelfRfsh_s == 1 || lock_i == 0) begin
// keep the SDRAM in self-refresh mode as long as requested and until there is a stable clock
cmd_x = RFSH_CMD_C;// output the refresh command; this is only needed on the first clock cycle
cke_x = 0; // disable the SDRAM clock
end else begin
// else exit self-refresh mode and start processing read and write operations
cke_x = 1; // restart the SDRAM clock
rfshCntr_x = 0; // no refreshes are needed immediately after leaving self-refresh
activeFlag_x = 0; // self-refresh deactivates all rows
timer_x = XSR_CYCLES; // wait this long until read and write operations can resume
state_x = RW;
end
status_o = 'b1100;
end
//*********************************************************************
// unknown state
//*********************************************************************
default: begin
state_x = INITWAIT; // reset state if in erroneous state
status_o = 'b1101;
end
endcase
end // else
end // always
//*********************************************************************
// update registers on the appropriate clock edge
//*********************************************************************
always @(posedge clk_i or posedge rst_i) begin
if (rst_i == 1) begin
// asynchronous reset
state_r <= INITWAIT;
activeFlag_r <= 0;
rfshCntr_r <= 0;
timer_r <= 0;
refTimer_r <= REF_CYCLES;
rasTimer_r <= 0;
wrTimer_r <= 0;
nopCntr_r <= 0;
opBegun_r <= 0;
rdPipeline_r <= 0;
wrPipeline_r <= 0;
cke_r <= 0;
cmd_r <= NOP_CMD_C;
ba_r <= 0;
sAddr_r <= 0;
sData_r <= 0;
sDataDir_r <= INPUT_C;
sdramData_r <= 0;
end else begin
state_r <= state_x;
activeBank_r <= activeBank_x;
`ifdef MULTIPLE_ACTIVE_ROWS_D
activeRow_r[0] = activeRow_x[0];
activeRow_r[1] = activeRow_x[1];
`else
activeRow_r[0] = activeRow_x[0];
`endif
activeFlag_r <= activeFlag_x;
rfshCntr_r <= rfshCntr_x;
timer_r <= timer_x;
refTimer_r <= refTimer_x;
rasTimer_r <= rasTimer_x;
wrTimer_r <= wrTimer_x;
nopCntr_r <= nopCntr_x;
opBegun_r <= opBegun_x;
rdPipeline_r <= rdPipeline_x;
wrPipeline_r <= wrPipeline_x;
cke_r <= cke_x;
cmd_r <= cmd_x;
ba_r <= ba_x;
sAddr_r <= sAddr_x;
sData_r <= sData_x;
sDataDir_r <= sDataDir_x;
sdramData_r <= sdramData_x;
end
end
// The register that gets data from the SDRAM and holds it for the host
// is clocked on the opposite edge. We don't use this register if IN_PHASE=TRUE.
always @(negedge clk_i or posedge rst_i) begin
if (rst_i == 1) begin
// asynchronous reset
sdramDataOppPhase_r <= 0;
end else begin
sdramDataOppPhase_r <= sdramDataOppPhase_x;
end
end
endmodule |
/*
* Copyright 2013, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* if "ack" is 1, then current input has been used. */
module f_permutation(clk, reset, in, in_ready, ack, out, out_ready);
input clk, reset;
input [575:0] in;
input in_ready;
output ack;
output reg [1599:0] out;
output reg out_ready;
reg [22:0] i; /* select round constant */
wire [1599:0] round_in, round_out;
wire [63:0] rc; /* round constant */
wire update;
wire accept;
reg calc; /* == 1: calculating rounds */
assign accept = in_ready & (~ calc); // in_ready & (i == 0)
always @ (posedge clk)
if (reset) i <= 0;
else i <= {i[21:0], accept};
always @ (posedge clk)
if (reset) calc <= 0;
else calc <= (calc & (~ i[22])) | accept;
assign update = calc | accept;
assign ack = accept;
always @ (posedge clk)
if (reset)
out_ready <= 0;
else if (accept)
out_ready <= 0;
else if (i[22]) // only change at the last round
out_ready <= 1;
assign round_in = accept ? {in ^ out[1599:1599-575], out[1599-576:0]} : out;
rconst
rconst_ ({i, accept}, rc);
round
round_ (round_in, rc, round_out);
always @ (posedge clk)
if (reset)
out <= 0;
else if (update)
out <= round_out;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O211A_FUNCTIONAL_V
`define SKY130_FD_SC_LS__O211A_FUNCTIONAL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o211a (
X ,
A1,
A2,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O211A_FUNCTIONAL_V |
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Complex_Multiply.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Complex_Multiply
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Sin_Cos/Complex_Multiply
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Complex_Multiply
(
In1_re,
In1_im,
In2_re,
In2_im,
Re,
Im
);
input signed [17:0] In1_re; // sfix18_En16
input signed [17:0] In1_im; // sfix18_En16
input signed [17:0] In2_re; // sfix18_En16
input signed [17:0] In2_im; // sfix18_En16
output signed [35:0] Re; // sfix36_En32
output signed [35:0] Im; // sfix36_En32
wire signed [35:0] Product_out1; // sfix36_En32
wire signed [35:0] Product1_out1; // sfix36_En32
wire signed [35:0] Add1_out1; // sfix36_En32
wire signed [35:0] Product2_out1; // sfix36_En32
wire signed [35:0] Product3_out1; // sfix36_En32
wire signed [35:0] Add2_out1; // sfix36_En32
// <S33>/Product
//
// <S33>/Complex to Real-Imag1
//
// <S33>/Complex to Real-Imag2
assign Product_out1 = In1_re * In2_re;
// <S33>/Product1
assign Product1_out1 = In1_im * In2_im;
// <S33>/Add1
assign Add1_out1 = Product_out1 - Product1_out1;
assign Re = Add1_out1;
// <S33>/Product2
assign Product2_out1 = In1_re * In2_im;
// <S33>/Product3
assign Product3_out1 = In1_im * In2_re;
// <S33>/Add2
assign Add2_out1 = Product2_out1 + Product3_out1;
assign Im = Add2_out1;
endmodule // controllerHdl_Complex_Multiply
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4_BLACKBOX_V
`define SKY130_FD_SC_LS__NAND4_BLACKBOX_V
/**
* nand4: 4-input NAND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4_BLACKBOX_V
|
`timescale 1ns / 1ps
module CORDIC_Arch2 #(parameter W = 32, parameter EW = 8, parameter SW = 23, parameter SWR=26, parameter EWR = 5)//*/
/*#(parameter W = 64, parameter EW = 11, parameter SW = 52, parameter SWR = 55, parameter EWR = 6) //-- Double Precision */
(
//Input Signals
input wire clk, // Reloj del sistema.
input wire rst, // Señal de reset del sistema.
input wire beg_fsm_cordic, // Señal de inicio de la maquina de estados del módulo CORDIC.
input wire ack_cordic, // Señal de acknowledge proveniente de otro módulo que indica que ha recibido el resultado del modulo CORDIC.
input wire operation, // Señal que indica si se realiza la operacion seno(1'b1) o coseno(1'b0).
input wire [W-1:0] data_in, // Dato de entrada, contiene el angulo que se desea calcular en radianes.
input wire [1:0] shift_region_flag, // Señal que indica si el ángulo a calcular esta fuera del rango de calculo del algoritmo CORDIC.
//Output Signals
output wire ready_cordic, // Señal de salida que indica que se ha completado el calculo del seno/coseno.
output wire overflow_flag, // Bandera de overflow de la operacion.
output wire underflow_flag, // Bandera de underflow de la operacion.
output wire [W-1:0] data_output // Bus de datos con el valor final del angulo calculado.
);
localparam d_var = 0; // Valor por defecto que se le carga al contador de variables.
localparam d_iter = 0; // Valor por defecto que se le carga al contador de iteraciones.
localparam mode = 1'b0;
localparam r_mode = 2'b00;
localparam iter_bits = 4; //Modificar valor para obtener diferente cantidad de iteraciones; ejem= 3=8iter, 4=16iter. etc
wire [W-1:0] x0,y0;
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
generate
case(W)
32:
begin
assign x0 = 32'h3f1b74ee; // x0 = 0.607252935008881, valor inicial de la variable X.
assign y0 = 32'h00000000; // y0 = 0, valor inicial de la variable Y.
end
64:
begin
assign x0 = 64'h3fe36e9db5086bc9; // x0 = 0.607252935008881, valor inicial de la variable X.
assign y0 = 64'h0000000000000000; // y0 = 0, valor inicial de la variable Y.
end
default:
begin
assign x0 = 32'h3f1b74ee; // x0 = 0.607252935008881, valor inicial de la variable X.
assign y0 = 32'h00000000; // y0 = 0, valor inicial de la variable Y.
end
endcase
endgenerate
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
//Signal declaration
wire reset_reg_cordic;
//ENABLE
wire enab_d_ff_RB1; // Enable de la primera linea de registros.
wire enab_d_ff2_RB2; // Enable de la segunda linea de registros.
wire enab_RB3; // Enable del registro que guarda el valor del signo, dependiendo del modo del algoritmo.
wire enab_d_ff4_Xn, enab_d_ff4_Yn, enab_d_ff4_Zn; // Enable de los registros que guardan los datos provenientes del modulo de suma/resta.
wire enab_d_ff5_data_out; // Enable del registo que guarda el valor de salida final, listo para enviarse al procesador.
wire enab_cont_iter, enab_cont_var; // Enable de los contadores de variable e iteracion
wire load_cont_iter, load_cont_var; // Señal de carga de un valor en los contadores de variable e iteraciones.
wire enab_dff_5;
//SELECTION
wire sel_mux_1, sel_mux_3; // Señales de seleccion provenientes de la maquina de estados.
wire [1:0] sel_mux_2; // Señal de seleccion que se activa dependiendo de la variable que se este calculando.
wire sel_mux_1_reg, sel_mux_3_reg; // Señales de seleccion provenientes de la maquina de estados.
wire [1:0] sel_mux_2_reg; // Señal de seleccion que se activa dependiendo de la variable que se este calculando.
//DATA WIRES
wire d_ff1_operation_out; // Salida del registro que guarda el dato de entrada de la operacion a realizar, coseno(1'b0) o seno(1'b1)
wire [1:0] d_ff1_shift_region_flag_out; // Salida del registro que guarda el dato de entrada que indica si el ángulo a calcular esta fuera del rango de calculo del algoritmo CORDIC.
wire [W-1:0] d_ff1_Z; // Salidas de los registros que guardan los valores iniciales de las variables X, Y y Z.
wire [W-1:0] d_ff_Xn, d_ff_Yn, d_ff_Zn; // Salidas de los registros que guardan los valores de las variables X, Y y Z despues de cada iteracion.
wire [W-1:0] first_mux_X, first_mux_Y, first_mux_Z; // Salidas de los mux que escogen entre un valor inicial y el valor obtenido en una iteracion.
wire [W-1:0] d_ff2_X, d_ff2_Y, d_ff2_Z; // Salidas de los registros que guardan los valores provenientes de la primera linea de mux.
wire sign; // Salida del mux que escoge entre el signo de Y o Z, dependiendo del modo, ya sea rotacion o vectorizacion.
wire [W-1:0] data_out_LUT; // Salida del modulo generate que genera la LUT necesaria dependiendo del ancho de palabra.
wire [iter_bits-1:0] cont_iter_out; // Salida del contador que cuenta las iteraciones realizadas.
wire [EW-1:0] sh_exp_x, sh_exp_y; // Salidas de los sumadores de punto fijo que realizan los desplazamientos.
wire [W-1:0] d_ff3_sh_x_out, d_ff3_sh_y_out; // Salida del registro que guarda el valor de X y Y luego de realizar los desplazamientos.
wire [W-1:0] d_ff3_LUT_out; // Salida del registro que guarda el valor de la LUT.
wire d_ff3_sign_out; // Salida del registro que guarda el valor del signo.
wire [1:0] cont_var_out; // Salida del contador que cuenta las variables calculadas.
wire [W-1:0] mux_sal; // Salida del mux final para colocar en la salida el valor deseado.
wire [W-1:0] data_output2; // Salida del registro antes del cambio de signo.
wire [W-1:0] sign_inv_out; // Salida del modulo de inversion de signo, dependiendo de si se el angulo de entrada estaba fuera del rango de calculo del algoritmo CORDIC.
wire min_tick_iter,max_tick_iter; // Señales que indican cuando se ha alcanzado el valor mas bajo y masalto de cuenta, correspondientemente en el contador de iteraciones.
wire min_tick_var,max_tick_var; // Señales que indican cuando se ha alcanzado el valor mas bajo y masalto de cuenta, correspondientemente en el contador de variables.
wire enab_reg_sel_mux1,enab_reg_sel_mux2,enab_reg_sel_mux3;
wire ready_add_subt; // Señal que indica que se ha realizado la operacion de suma/resta en punto flotante.
wire [W-1:0] result_add_subt; // Dato de entrada, contiene el resultado del módulo de suma/resta.
wire beg_add_subt; // Señal de salida que indica que se debe de iniciar el modulo de suma/resta.
wire ack_add_subt; // Señal que le indica al modulo de suma/resta que se recibio el resultado de este modulo correctamente.
wire op_add_subt; // Señal hacia el módulo de suma/resta que indica si se va a realizar una suma(1'b0) o una resta(1'b1).
wire [W-1:0] add_subt_dataA; // Bus de datos hacia el modulo de suma/resta con el valor al que se le desea aplicar dicha operacion.
wire [W-1:0] add_subt_dataB; // Bus de datos hacia el modulo de suma/resta con el valor al que se le desea aplicar dicha operacion.
//Instanciación
//------------------------------------------------------------------------------------------------------------------------
//FSM
CORDIC_FSM_v2 cordic_FSM
(
.clk(clk), // Reloj del sitema.
.reset(rst), // Reset del sitema.
.beg_FSM_CORDIC(beg_fsm_cordic), // Señal de inicio de la maquina de estados.
.ACK_FSM_CORDIC(ack_cordic), // Señal proveniente del modulo que recibe el resultado, indicado que el dato ha sido recibido.
.operation(d_ff1_operation_out), // Señal que determina si lo que se requiere es realizar un coseno(1´b0) o seno (1'b1).
.exception(1'b0),
.shift_region_flag(d_ff1_shift_region_flag_out), // Señal que indica si el angulo a calcular se encuentra fuera del rango de calculo del algoritmo CORDIC.
.cont_var(cont_var_out), // Señal que indica cual varible se va a calcular. Proveniente del contador de variables.
.ready_add_subt(ready_add_subt), // Señal proveniente del módulo de suma/resta, indica que se ha terminado la operacion y que se puede disponer del resultado de dicho modulo.
.max_tick_iter(max_tick_iter),
.min_tick_iter(min_tick_iter), // Señales que indican la maxima y minima cuenta, respectivamente, en el contador de iteraciones.
.max_tick_var(max_tick_var),
.min_tick_var(min_tick_var), // Señales que indican la maxima y minima cuenta, respectivamente, en el contador de variables.
//Output Signals
.reset_reg_cordic(reset_reg_cordic),
.ready_CORDIC(ready_cordic), // Señal que indica que el calculo CORDIC se ha terminado.
.beg_add_subt(beg_add_subt), // Señal que indica al modulo de suma/resta que inicie su operacion.
.ack_add_subt(ack_add_subt), // Señal que le indica al modulo de suma/resta que se ha recibido exitosamente el resultado que este entrega.
.sel_mux_1(sel_mux_1),
.sel_mux_3(sel_mux_3), // Señales de seleccion de mux, la primera escoge el canal 0 si es la primera iteracion, en otro caso escoge el canal 1, y la segunda escoge cual variable (X o Y) debe aparecer a la salida.
.sel_mux_2(sel_mux_2), // Señal de seleccion de mux, que escoge entre X, Y o Z dependiendo de cual variable se deba calcular en ese momento.
.enab_cont_iter(enab_cont_iter),
.load_cont_iter(load_cont_iter), // Señales de habilitacion y carga, respectivamente, en el contador de iteraciones.
.enab_cont_var(enab_cont_var),
.load_cont_var(load_cont_var), // Señales de habilitacion y carga, respectivamente, en el contador de variables.
.enab_RB1(enab_d_ff_RB1),
.enab_RB2(enab_d_ff2_RB2), // Señales de habilitacion para los registros de variables de entrada y para los valores de las variables despues de los primeros mux, respectivamente.
.enab_d_ff_Xn(enab_d_ff4_Xn),
.enab_d_ff_Yn(enab_d_ff4_Yn),
.enab_d_ff_Zn(enab_d_ff4_Zn), // Señales de habilitacion para los registros que guardan los resultados de cada variable en cada iteracion provenientes del modulo de suma/resta.
.enab_d_ff_out(enab_d_ff5_data_out),
.enab_dff_5(enab_dff_5), // Señales de habilitacion para los registros en la salida, el primero antes del cambio de signo y el segundo es el que se encuentra en la salida.
.enab_RB3(enab_RB3), // Señales de habilitacion para los registros que guardan los valores provenientes de la look-up table y del signo, respectivamente.
.enab_reg_sel_mux1(enab_reg_sel_mux1),
.enab_reg_sel_mux2(enab_reg_sel_mux2),
.enab_reg_sel_mux3(enab_reg_sel_mux3)
);
counter_d #(.W(iter_bits)) cont_iter
(
.clk(clk),
.rst(reset_reg_cordic),
.load(load_cont_iter),
.enable(enab_cont_iter),
.d(d_iter),
.max_tick(max_tick_iter),
.min_tick(min_tick_iter),
.q(cont_iter_out)
);
counter_up #(.W(2)) cont_var
(
.clk(clk),
.rst(reset_reg_cordic),
.load(load_cont_var),
.enable(enab_cont_var),
.d(d_var),
.max_tick(max_tick_var),
.min_tick(min_tick_var),
.q(cont_var_out)
);
//--------------------------------------------------------------------------------------------------------------------------------------------------------
//Primera Etapa: Registros que guardan los valores iniciales.
d_ff_en # (.W(1)) reg_operation
(
.clk(clk),//system clock
.rst(reset_reg_cordic), //system reset
.enable(enab_d_ff_RB1), //load signal
.D(operation), //input signal
.Q(d_ff1_operation_out) //output signal
);
d_ff_en # (.W(2)) reg_region_flag
(
.clk(clk),//system clock
.rst(reset_reg_cordic), //system reset
.enable(enab_d_ff_RB1), //load signal
.D(shift_region_flag), //input signal
.Q(d_ff1_shift_region_flag_out) //output signal
);
d_ff_en # (.W(W)) reg_Z0
(
.clk(clk),//system clock
.rst(reset_reg_cordic), //system reset
.enable(enab_d_ff_RB1), //load signal
.D(data_in), //input signal
.Q(d_ff1_Z) //output signal
);
//--------------------------------------------------------------------------------------------------------------------------------------------------------
//Segunda Etapa : Registros que guardan el canal elegido para el mux, asi como los mux.
d_ff_en # (.W(1)) reg_ch_mux_1
(
.clk(clk),//system clock
.rst(reset_reg_cordic), //system reset
.enable(enab_reg_sel_mux1), //load signal
.D(sel_mux_1), //input signal
.Q(sel_mux_1_reg) //output signal
);
Mux_2x1 #(.W(W)) mux1_x0
(
.select(sel_mux_1_reg),
.ch_0(x0),
.ch_1(d_ff_Xn),
.data_out(first_mux_X)
);
Mux_2x1 #(.W(W)) mux1_y0
(
.select(sel_mux_1_reg),
.ch_0(y0),
.ch_1(d_ff_Yn),
.data_out(first_mux_Y)
);
Mux_2x1 #(.W(W)) mux1_z0
(
.select(sel_mux_1_reg),
.ch_0(d_ff1_Z),
.ch_1(d_ff_Zn),
.data_out(first_mux_Z)
);
//----------------------------------------------------------------------------------------------------------------------
//Tercera Etapa: Registros que guardan los datos provenientes de los mux.
d_ff_en # (.W(W)) reg_val_muxX_2stage
(
.clk(clk),//system clock
.rst(reset_reg_cordic), //system reset
.enable(enab_d_ff2_RB2), //load signal
.D(first_mux_X), //input signal
.Q(d_ff2_X) //output signal
);
d_ff_en # (.W(W)) reg_val_muxY_2stage
(
.clk(clk),//system clock
.rst(reset_reg_cordic), //system reset
.enable(enab_d_ff2_RB2), //load signal
.D(first_mux_Y), //input signal
.Q(d_ff2_Y) //output signal
);
d_ff_en # (.W(W)) reg_val_muxZ_2stage
(
.clk(clk),//system clock
.rst(reset_reg_cordic), //system reset
.enable(enab_d_ff2_RB2), //load signal
.D(first_mux_Z), //input signal
.Q(d_ff2_Z) //output signal
);
//----------------------------------------------------------------------------------------------------------------------
//Cuarta Etapa : Restadores para el corrimiento del exponente de X y Y, Lookup-Table y mux de signo dependiendo del modo.
Simple_Subt #(.W(EW),.N(iter_bits)) shift_x
(
.A(d_ff2_X[W-2:SW]),
.B(cont_iter_out),
.Y(sh_exp_x)
);
Simple_Subt #(.W(EW),.N(iter_bits)) shift_y
(
.A(d_ff2_Y[W-2:SW]),
.B(cont_iter_out),
.Y(sh_exp_y)
);
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
generate
case(W)
32:
begin
LUT_ROM_32bits #(.W(W),.N(iter_bits)) LUT32
(
.address(cont_iter_out),
.data_out(data_out_LUT)
);
end
64:
begin
LUT_ROM_64bits #(.W(W),.N(iter_bits)) LUT64
(
.address(cont_iter_out),
.data_out(data_out_LUT)
);
end
default:
begin
LUT_ROM_32bits #(.W(W),.N(iter_bits)) LUT32
(
.address(cont_iter_out),
.data_out(data_out_LUT)
);
end
endcase
endgenerate
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
Mux_2x1 #(.W(1)) mux_sign
(
.select(mode),
.ch_0(d_ff2_Z[W-1]),
.ch_1(d_ff2_Y[W-1]),
.data_out(sign)
);
//-------------------------------------------------------------------------------------------------------------------------
//Quinta Etapa : Registros que guardan los datos provenientes de la etapa anterior.
d_ff_en # (.W(W)) reg_shift_x
(
.clk(clk),//system clock
.rst(reset_reg_cordic), //system reset
.enable(enab_RB3), //load signal
.D({d_ff2_X[W-1],sh_exp_x,d_ff2_X[SW-1:0]}), //input signal
.Q(d_ff3_sh_x_out) //output signal
);
d_ff_en # (.W(W)) reg_shift_y
(
.clk(clk),//system clock
.rst(reset_reg_cordic), //system reset
.enable(enab_RB3), //load signal
.D({d_ff2_Y[W-1],sh_exp_y,d_ff2_Y[SW-1:0]}), //input signal
.Q(d_ff3_sh_y_out) //output signal
);
d_ff_en # (.W(W)) reg_LUT
(
.clk(clk),//system clock
.rst(reset_reg_cordic), //system reset
.enable(enab_RB3), //load signal
.D(data_out_LUT), //input signal
.Q(d_ff3_LUT_out) //output signal
);
d_ff_en # (.W(1)) reg_sign
(
.clk(clk),//system clock
.rst(reset_reg_cordic), //system reset
.enable(enab_RB3), //load signal
.D(sign), //input signal
.Q(d_ff3_sign_out) //output signal
);
//-------------------------------------------------------------------------------------------------------------------------------------------------------
//Sexta Etapa : Mux de 3 canales que se activan dependiendo de la variable a calcular.
d_ff_en # (.W(2)) reg_ch_mux_2
(
.clk(clk),//system clock
.rst(reset_reg_cordic), //system reset
.enable(enab_reg_sel_mux2), //load signal
.D(sel_mux_2), //input signal
.Q(sel_mux_2_reg) //output signal
);
Mux_3x1_b #(.W(W)) mux_3x1_var1
(
.select(sel_mux_2_reg),
.ch_0(d_ff2_X),
.ch_1(d_ff2_Y),
.ch_2(d_ff2_Z),
.data_out(add_subt_dataA)
);
Mux_3x1_b #(.W(W)) mux_3x1_var2
(
.select(sel_mux_2_reg),
.ch_0(d_ff3_sh_y_out),
.ch_1(d_ff3_sh_x_out),
.ch_2(d_ff3_LUT_out),
.data_out(add_subt_dataB)
);
Op_Select op_select_mod
(
.variable(cont_var_out[0]),
.sign(d_ff3_sign_out),
.operation(op_add_subt)
);
//--------------------------------------------------------------------------------------------------------------------------------
//Septima Etapa : Instanciamiento del módulo de suma y resta.
FPU_Add_Subtract_Function #(.W(W),.EW(EW),.SW(SW),.SWR(SWR),.EWR(EWR)) add_subt_module
(
.clk(clk),
.rst(rst),
.beg_FSM(beg_add_subt),
.ack_FSM(ack_add_subt),
.Data_X(add_subt_dataA),
.Data_Y(add_subt_dataB),
.add_subt(op_add_subt),
.r_mode(r_mode),
.overflow_flag(overflow_flag),
.underflow_flag(underflow_flag),
.ready(ready_add_subt),
.final_result_ieee(result_add_subt)
);
//-------------------------------------------------------------------------------------------------------------------------------
//Octava Etapa: Registros que guardan los valores de calculo del modulo de suma y resta.
d_ff_en #(.W(W)) d_ff4_Xn
(
.clk(clk),
.rst(reset_reg_cordic),
.enable(enab_d_ff4_Xn),
.D(result_add_subt),
.Q(d_ff_Xn)
);
d_ff_en #(.W(W)) d_ff4_Yn
(
.clk(clk),
.rst(reset_reg_cordic),
.enable(enab_d_ff4_Yn),
.D(result_add_subt),
.Q(d_ff_Yn)
);
d_ff_en #(.W(W)) d_ff4_Zn
(
.clk(clk),
.rst(reset_reg_cordic),
.enable(enab_d_ff4_Zn),
.D(result_add_subt),
.Q(d_ff_Zn)
);
//--------------------------------------------------------------------------------------------------------------------------------
//Novena Etapa: Mux de selección del valor de salida, así como el modulo de correccion de signo y los registros intermedios que
//guardan los datos de salida.
d_ff_en #(.W(1)) reg_ch_mux_3
(
.clk(clk),
.rst(reset_reg_cordic),
.enable(enab_reg_sel_mux3),
.D(sel_mux_3),
.Q(sel_mux_3_reg)
);
Mux_2x1 #(.W(W)) mux_2x1_sal
(
.select(sel_mux_3_reg),
.ch_0(d_ff_Xn),
.ch_1(d_ff_Yn),
.data_out(mux_sal)
);
d_ff_en #(.W(W)) d_ff5
(
.clk(clk),
.rst(reset_reg_cordic),
.enable(enab_dff_5),
.D(mux_sal),
.Q(data_output2)
);
sign_inverter #(.W(W)) sign_inverter_mod
(
.data(data_output2),
.shift_region_flag(d_ff1_shift_region_flag_out),
.operation(d_ff1_operation_out),
.data_out(sign_inv_out)
);
d_ff_en #(.W(W)) d_ff5_data_out
(
.clk(clk),
.rst(reset_reg_cordic),
.enable(enab_d_ff5_data_out),
.D(sign_inv_out),
.Q(data_output)
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: ram_1clk_1w_1r.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: An inferrable RAM module. Single clock, 1 write port, 1
// read port. In Xilinx designs, specify RAM_STYLE="BLOCK"
// to use BRAM memory or RAM_STYLE="DISTRIBUTED" to use
// LUT memory.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module ram_1clk_1w_1r
#(
parameter C_RAM_WIDTH = 32,
parameter C_RAM_DEPTH = 1024
)
(
input CLK,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRA,
input WEA,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRB,
input [C_RAM_WIDTH-1:0] DINA,
output [C_RAM_WIDTH-1:0] DOUTB
);
`include "functions.vh"
localparam C_RAM_ADDR_BITS = clog2s(C_RAM_DEPTH);
reg [C_RAM_WIDTH-1:0] rRAM [C_RAM_DEPTH-1:0];
reg [C_RAM_WIDTH-1:0] rDout;
assign DOUTB = rDout;
always @(posedge CLK) begin
if (WEA)
rRAM[ADDRA] <= #1 DINA;
rDout <= #1 rRAM[ADDRB];
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:57:50 08/25/2009
// Design Name:
// Module Name: mcu_cmd
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mcu_cmd(
input clk,
input cmd_ready,
input param_ready,
input [7:0] cmd_data,
input [7:0] param_data,
output [2:0] mcu_mapper,
output mcu_rrq,
output mcu_write,
output mcu_wrq,
input mcu_rq_rdy,
output [7:0] mcu_data_out,
input [7:0] mcu_data_in,
output [7:0] spi_data_out,
input [31:0] spi_byte_cnt,
input [2:0] spi_bit_cnt,
output [23:0] addr_out,
output [23:0] saveram_mask_out,
output [23:0] rom_mask_out,
// SD "DMA" extension
output SD_DMA_EN,
input SD_DMA_STATUS,
input SD_DMA_NEXTADDR,
input [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_SRAM_WE,
output [1:0] SD_DMA_TGT,
output SD_DMA_PARTIAL,
output [10:0] SD_DMA_PARTIAL_START,
output [10:0] SD_DMA_PARTIAL_END,
output reg SD_DMA_START_MID_BLOCK,
output reg SD_DMA_END_MID_BLOCK,
// DAC
output [10:0] dac_addr_out,
input DAC_STATUS,
output dac_play_out,
output dac_reset_out,
output reg [2:0] dac_vol_select_out = 3'b000,
output reg dac_palmode_out = 0,
// MSU data
output [13:0] msu_addr_out,
input [7:0] MSU_STATUS,
output [5:0] msu_status_reset_out,
output [5:0] msu_status_set_out,
output msu_status_reset_we,
input [31:0] msu_addressrq,
input [15:0] msu_trackrq,
input [7:0] msu_volumerq,
output [13:0] msu_ptr_out,
output msu_reset_out,
// BS-X
output [7:0] bsx_regs_reset_out,
output [7:0] bsx_regs_set_out,
output bsx_regs_reset_we,
// generic RTC
output [55:0] rtc_data_out,
output rtc_pgm_we,
// S-RTC
output srtc_reset,
// uPD77C25
output reg [23:0] dspx_pgm_data_out,
output reg [10:0] dspx_pgm_addr_out,
output reg dspx_pgm_we_out,
output reg [15:0] dspx_dat_data_out,
output reg [10:0] dspx_dat_addr_out,
output reg dspx_dat_we_out,
output reg dspx_reset_out,
// feature enable
output reg [7:0] featurebits_out,
output reg region_out,
// SNES sync/clk
input snes_sysclk,
// snes cmd interface
input [7:0] snescmd_data_in,
output reg [7:0] snescmd_data_out,
output reg [8:0] snescmd_addr_out,
output reg snescmd_we_out,
// cheat configuration
output reg [7:0] cheat_pgm_idx_out,
output reg [31:0] cheat_pgm_data_out,
output reg cheat_pgm_we_out,
// DSP core features
output reg [15:0] dsp_feat_out = 16'h0000
);
initial begin
dspx_pgm_addr_out = 11'b00000000000;
dspx_dat_addr_out = 10'b0000000000;
dspx_reset_out = 1'b1;
region_out = 0;
SD_DMA_START_MID_BLOCK = 0;
SD_DMA_END_MID_BLOCK = 0;
end
wire [31:0] snes_sysclk_freq;
clk_test snes_clk_test (
.clk(clk),
.sysclk(snes_sysclk),
.snes_sysclk_freq(snes_sysclk_freq)
);
reg [2:0] MAPPER_BUF;
reg [23:0] ADDR_OUT_BUF;
reg [10:0] DAC_ADDR_OUT_BUF;
reg [7:0] DAC_VOL_OUT_BUF;
reg DAC_VOL_LATCH_BUF;
reg DAC_PLAY_OUT_BUF;
reg DAC_RESET_OUT_BUF;
reg [13:0] MSU_ADDR_OUT_BUF;
reg [13:0] MSU_PTR_OUT_BUF;
reg [5:0] msu_status_set_out_buf;
reg [5:0] msu_status_reset_out_buf;
reg msu_status_reset_we_buf;
reg MSU_RESET_OUT_BUF;
reg [7:0] bsx_regs_set_out_buf;
reg [7:0] bsx_regs_reset_out_buf;
reg bsx_regs_reset_we_buf;
reg [55:0] rtc_data_out_buf;
reg rtc_pgm_we_buf;
reg srtc_reset_buf;
initial srtc_reset_buf = 0;
reg [31:0] SNES_SYSCLK_FREQ_BUF;
reg [7:0] MCU_DATA_OUT_BUF;
reg [7:0] MCU_DATA_IN_BUF;
reg [2:0] mcu_nextaddr_buf;
reg [7:0] dsp_feat_tmp;
wire mcu_nextaddr;
reg DAC_STATUSr;
reg SD_DMA_STATUSr;
reg [7:0] MSU_STATUSr;
always @(posedge clk) begin
DAC_STATUSr <= DAC_STATUS;
SD_DMA_STATUSr <= SD_DMA_STATUS;
MSU_STATUSr <= MSU_STATUS;
end
reg SD_DMA_PARTIALr;
assign SD_DMA_PARTIAL = SD_DMA_PARTIALr;
reg SD_DMA_ENr;
assign SD_DMA_EN = SD_DMA_ENr;
reg [1:0] SD_DMA_TGTr;
assign SD_DMA_TGT = SD_DMA_TGTr;
reg [10:0] SD_DMA_PARTIAL_STARTr;
reg [10:0] SD_DMA_PARTIAL_ENDr;
assign SD_DMA_PARTIAL_START = SD_DMA_PARTIAL_STARTr;
assign SD_DMA_PARTIAL_END = SD_DMA_PARTIAL_ENDr;
reg [23:0] SAVERAM_MASK;
reg [23:0] ROM_MASK;
assign spi_data_out = MCU_DATA_IN_BUF;
initial begin
ADDR_OUT_BUF = 0;
DAC_ADDR_OUT_BUF = 0;
MSU_ADDR_OUT_BUF = 0;
SD_DMA_ENr = 0;
MAPPER_BUF = 1;
SD_DMA_PARTIALr = 0;
end
// command interpretation
always @(posedge clk) begin
snescmd_we_out <= 1'b0;
cheat_pgm_we_out <= 1'b0;
if (cmd_ready) begin
case (cmd_data[7:4])
4'h3: // select mapper
MAPPER_BUF <= cmd_data[2:0];
4'h4: begin// SD DMA
SD_DMA_ENr <= 1;
SD_DMA_TGTr <= cmd_data[1:0];
SD_DMA_PARTIALr <= cmd_data[2];
end
4'h8: SD_DMA_TGTr <= 2'b00;
4'h9: SD_DMA_TGTr <= 2'b00; // cmd_data[1:0]; // not implemented
// 4'hE:
// select memory unit
endcase
end else if (param_ready) begin
casex (cmd_data[7:0])
8'h1x:
case (spi_byte_cnt)
32'h2:
ROM_MASK[23:16] <= param_data;
32'h3:
ROM_MASK[15:8] <= param_data;
32'h4:
ROM_MASK[7:0] <= param_data;
endcase
8'h2x:
case (spi_byte_cnt)
32'h2:
SAVERAM_MASK[23:16] <= param_data;
32'h3:
SAVERAM_MASK[15:8] <= param_data;
32'h4:
SAVERAM_MASK[7:0] <= param_data;
endcase
8'h4x:
SD_DMA_ENr <= 1'b0;
8'h6x:
case (spi_byte_cnt)
32'h2: begin
SD_DMA_START_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_STARTr[10:9] <= param_data[1:0];
end
32'h3:
SD_DMA_PARTIAL_STARTr[8:0] <= {param_data, 1'b0};
32'h4: begin
SD_DMA_END_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_ENDr[10:9] <= param_data[1:0];
end
32'h5:
SD_DMA_PARTIAL_ENDr[8:0] <= {param_data, 1'b0};
endcase
8'h9x:
MCU_DATA_OUT_BUF <= param_data;
8'hd0:
case (spi_byte_cnt)
32'h2:
snescmd_addr_out[7:0] <= param_data;
32'h3:
snescmd_addr_out[8] <= param_data[0];
endcase
8'hd1:
snescmd_addr_out <= snescmd_addr_out + 1;
8'hd2: begin
case (spi_byte_cnt)
32'h2:
snescmd_we_out <= 1'b1;
32'h3:
snescmd_addr_out <= snescmd_addr_out + 1;
endcase
snescmd_data_out <= param_data;
end
8'hd3: begin
case (spi_byte_cnt)
32'h2:
cheat_pgm_idx_out <= param_data[2:0];
32'h3:
cheat_pgm_data_out[31:24] <= param_data;
32'h4:
cheat_pgm_data_out[23:16] <= param_data;
32'h5:
cheat_pgm_data_out[15:8] <= param_data;
32'h6: begin
cheat_pgm_data_out[7:0] <= param_data;
cheat_pgm_we_out <= 1'b1;
end
endcase
end
8'he0:
case (spi_byte_cnt)
32'h2: begin
msu_status_set_out_buf <= param_data[5:0];
end
32'h3: begin
msu_status_reset_out_buf <= param_data[5:0];
msu_status_reset_we_buf <= 1'b1;
end
32'h4:
msu_status_reset_we_buf <= 1'b0;
endcase
8'he1: // pause DAC
DAC_PLAY_OUT_BUF <= 1'b0;
8'he2: // resume DAC
DAC_PLAY_OUT_BUF <= 1'b1;
8'he3: // reset DAC (set DAC playback address = 0)
case (spi_byte_cnt)
32'h2:
DAC_RESET_OUT_BUF <= 1'b1;
32'h3:
DAC_RESET_OUT_BUF <= 1'b0;
endcase
8'he4: // reset MSU read buffer pointer
case (spi_byte_cnt)
32'h2: begin
MSU_PTR_OUT_BUF[13:8] <= param_data[5:0];
MSU_PTR_OUT_BUF[7:0] <= 8'h0;
end
32'h3: begin
MSU_PTR_OUT_BUF[7:0] <= param_data;
MSU_RESET_OUT_BUF <= 1'b1;
end
32'h4:
MSU_RESET_OUT_BUF <= 1'b0;
endcase
8'he5:
case (spi_byte_cnt)
32'h2:
rtc_data_out_buf[55:48] <= param_data;
32'h3:
rtc_data_out_buf[47:40] <= param_data;
32'h4:
rtc_data_out_buf[39:32] <= param_data;
32'h5:
rtc_data_out_buf[31:24] <= param_data;
32'h6:
rtc_data_out_buf[23:16] <= param_data;
32'h7:
rtc_data_out_buf[15:8] <= param_data;
32'h8: begin
rtc_data_out_buf[7:0] <= param_data;
rtc_pgm_we_buf <= 1'b1;
end
32'h9:
rtc_pgm_we_buf <= 1'b0;
endcase
8'he6:
case (spi_byte_cnt)
32'h2: begin
bsx_regs_set_out_buf <= param_data[7:0];
end
32'h3: begin
bsx_regs_reset_out_buf <= param_data[7:0];
bsx_regs_reset_we_buf <= 1'b1;
end
32'h4:
bsx_regs_reset_we_buf <= 1'b0;
endcase
8'he7:
case (spi_byte_cnt)
32'h2: begin
srtc_reset_buf <= 1'b1;
end
32'h3: begin
srtc_reset_buf <= 1'b0;
end
endcase
8'he8: begin// reset DSPx PGM+DAT address
case (spi_byte_cnt)
32'h2: begin
dspx_pgm_addr_out <= 11'b00000000000;
dspx_dat_addr_out <= 10'b0000000000;
end
endcase
end
8'he9:// write DSPx PGM w/ increment
case (spi_byte_cnt)
32'h2: dspx_pgm_data_out[23:16] <= param_data[7:0];
32'h3: dspx_pgm_data_out[15:8] <= param_data[7:0];
32'h4: dspx_pgm_data_out[7:0] <= param_data[7:0];
32'h5: dspx_pgm_we_out <= 1'b1;
32'h6: begin
dspx_pgm_we_out <= 1'b0;
dspx_pgm_addr_out <= dspx_pgm_addr_out + 1;
end
endcase
8'hea:// write DSPx DAT w/ increment
case (spi_byte_cnt)
32'h2: dspx_dat_data_out[15:8] <= param_data[7:0];
32'h3: dspx_dat_data_out[7:0] <= param_data[7:0];
32'h4: dspx_dat_we_out <= 1'b1;
32'h5: begin
dspx_dat_we_out <= 1'b0;
dspx_dat_addr_out <= dspx_dat_addr_out + 1;
end
endcase
8'heb: // control DSPx reset
dspx_reset_out <= param_data[0];
8'hec:
begin // set DAC properties
dac_vol_select_out <= param_data[2:0];
dac_palmode_out <= param_data[7];
end
8'hed:
featurebits_out <= param_data;
8'hee:
region_out <= param_data[0];
8'hef:
case (spi_byte_cnt)
32'h2: dsp_feat_tmp <= param_data[7:0];
32'h3: begin
dsp_feat_out <= {dsp_feat_tmp, param_data[7:0]};
end
endcase
endcase
end
end
always @(posedge clk) begin
if(param_ready && cmd_data[7:4] == 4'h0) begin
case (cmd_data[1:0])
2'b01: begin
case (spi_byte_cnt)
32'h2: begin
DAC_ADDR_OUT_BUF[10:8] <= param_data[2:0];
DAC_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
DAC_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
2'b10: begin
case (spi_byte_cnt)
32'h2: begin
MSU_ADDR_OUT_BUF[13:8] <= param_data[5:0];
MSU_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
MSU_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
default:
case (spi_byte_cnt)
32'h2: begin
ADDR_OUT_BUF[23:16] <= param_data;
ADDR_OUT_BUF[15:0] <= 16'b0;
end
32'h3:
ADDR_OUT_BUF[15:8] <= param_data;
32'h4:
ADDR_OUT_BUF[7:0] <= param_data;
endcase
endcase
end else if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4)
&& (cmd_data[3])
&& (spi_byte_cnt >= (32'h1+cmd_data[4])))
) begin
case (SD_DMA_TGTr)
2'b00: ADDR_OUT_BUF <= ADDR_OUT_BUF + 1;
2'b01: DAC_ADDR_OUT_BUF <= DAC_ADDR_OUT_BUF + 1;
2'b10: MSU_ADDR_OUT_BUF <= MSU_ADDR_OUT_BUF + 1;
endcase
end
end
// value fetch during last SPI bit
always @(posedge clk) begin
if (cmd_data[7:4] == 4'h8 && mcu_nextaddr)
MCU_DATA_IN_BUF <= mcu_data_in;
else if (cmd_ready | param_ready /* bit_cnt == 7 */) begin
if (cmd_data[7:4] == 4'hA)
MCU_DATA_IN_BUF <= snescmd_data_in;
if (cmd_data[7:0] == 8'hF0)
MCU_DATA_IN_BUF <= 8'hA5;
else if (cmd_data[7:0] == 8'hF1)
case (spi_byte_cnt[0])
1'b1: // buffer status (1st byte)
MCU_DATA_IN_BUF <= {SD_DMA_STATUSr, DAC_STATUSr, MSU_STATUSr[7], 5'b0};
1'b0: // control status (2nd byte)
MCU_DATA_IN_BUF <= {1'b0, MSU_STATUSr[6:0]};
endcase
else if (cmd_data[7:0] == 8'hF2)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_addressrq[31:24];
32'h2:
MCU_DATA_IN_BUF <= msu_addressrq[23:16];
32'h3:
MCU_DATA_IN_BUF <= msu_addressrq[15:8];
32'h4:
MCU_DATA_IN_BUF <= msu_addressrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF3)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_trackrq[15:8];
32'h2:
MCU_DATA_IN_BUF <= msu_trackrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF4)
MCU_DATA_IN_BUF <= msu_volumerq;
else if (cmd_data[7:0] == 8'hFE)
case (spi_byte_cnt)
32'h1:
SNES_SYSCLK_FREQ_BUF <= snes_sysclk_freq;
32'h2:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
32'h3:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
32'h4:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
32'h5:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
endcase
else if (cmd_data[7:0] == 8'hFF)
MCU_DATA_IN_BUF <= param_data;
else if (cmd_data[7:0] == 8'hD1)
MCU_DATA_IN_BUF <= snescmd_data_in;
end
end
// nextaddr pulse generation
always @(posedge clk) begin
mcu_nextaddr_buf <= {mcu_nextaddr_buf[1:0], mcu_rq_rdy};
end
parameter ST_RQ = 2'b01;
parameter ST_IDLE = 2'b10;
reg [1:0] rrq_state;
initial rrq_state = ST_IDLE;
reg mcu_rrq_r;
reg [1:0] wrq_state;
initial wrq_state = ST_IDLE;
reg mcu_wrq_r;
always @(posedge clk) begin
case(rrq_state)
ST_IDLE: begin
if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
mcu_rrq_r <= 1'b1;
rrq_state <= ST_RQ;
end else
rrq_state <= ST_IDLE;
end
ST_RQ: begin
mcu_rrq_r <= 1'b0;
rrq_state <= ST_IDLE;
end
endcase
end
always @(posedge clk) begin
case(wrq_state)
ST_IDLE: begin
if(param_ready && cmd_data[7:4] == 4'h9) begin
mcu_wrq_r <= 1'b1;
wrq_state <= ST_RQ;
end else
wrq_state <= ST_IDLE;
end
ST_RQ: begin
mcu_wrq_r <= 1'b0;
wrq_state <= ST_IDLE;
end
endcase
end
// trigger for nextaddr
assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
assign mcu_rrq = mcu_rrq_r;
assign mcu_wrq = mcu_wrq_r;
assign mcu_write = SD_DMA_STATUS
?(SD_DMA_TGTr == 2'b00
? SD_DMA_SRAM_WE
: 1'b1
)
: 1'b1;
assign addr_out = ADDR_OUT_BUF;
assign dac_addr_out = DAC_ADDR_OUT_BUF;
assign msu_addr_out = MSU_ADDR_OUT_BUF;
assign dac_play_out = DAC_PLAY_OUT_BUF;
assign dac_reset_out = DAC_RESET_OUT_BUF;
assign msu_status_reset_we = msu_status_reset_we_buf;
assign msu_status_reset_out = msu_status_reset_out_buf;
assign msu_status_set_out = msu_status_set_out_buf;
assign msu_reset_out = MSU_RESET_OUT_BUF;
assign msu_ptr_out = MSU_PTR_OUT_BUF;
assign bsx_regs_reset_we = bsx_regs_reset_we_buf;
assign bsx_regs_reset_out = bsx_regs_reset_out_buf;
assign bsx_regs_set_out = bsx_regs_set_out_buf;
assign rtc_data_out = rtc_data_out_buf;
assign rtc_pgm_we = rtc_pgm_we_buf;
assign srtc_reset = srtc_reset_buf;
assign mcu_data_out = SD_DMA_STATUS ? SD_DMA_SRAM_DATA : MCU_DATA_OUT_BUF;
assign mcu_mapper = MAPPER_BUF;
assign rom_mask_out = ROM_MASK;
assign saveram_mask_out = SAVERAM_MASK;
assign DBG_mcu_nextaddr = mcu_nextaddr;
endmodule
|
// nios_dut_mm_interconnect_0_avalon_st_adapter_008.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_dut_mm_interconnect_0_avalon_st_adapter_008 #(
parameter inBitsPerSymbol = 130,
parameter inUsePackets = 0,
parameter inDataWidth = 130,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 130,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [129:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [129:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 130)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 130)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 130)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_dut_mm_interconnect_0_avalon_st_adapter_008_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : CRT Controller
// File : crt.v
// Author : Frank Bruno
// Created : 30-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module is the CRT Display controller
// this is modified CRT module (top of original crt controler )
// CRTTIMER module is broken in two modules: CRTADDSL and CRTTIMER
// CRTADDSL consist of all adders and substractors common to
// VRAM and DRAM controlers
// Functionality of original CRTTIMER will be intact if CRTADDSEL and
// CRTTIMER have proper port connections.
// To support the "DRAM only" configuration the following mudules are
// added: DC_TOP (and all DC_xxx modules in hierarchy),
// CRTDCVMUX (a mux for selecting syncs from CRT_xx or DC_xxx or VGA)
// Port list of CRT module (this module) has new signals
// added at the end of the original port list.
// It includes new signals to comunicate with mem.controller, data lines etc.
// DC_xxx is also muxing display data from DC_ and from the VGA core
// and gating pixel clock to vga core
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module crt
(
input [1:0] bpp, /* screen depth
* (from idac pixel_representation[2:1] reg)
* 2'b01: 8bpp
* 2'b10: 16pbb
* 2'b11 or 00: 32bpp */
input ovnokey, /* from overlay (overlay on, no key,
* crt can suppress some requsets.) */
input crtclock,
input pixclock,
input hclock,
input hreset,
input hwr_in,
input hcs_in,
input [3:0] hnben_in,
input [31:0] hdat_in,
input [7:2] haddr,
input vga_en,
input [7:0] vga_din,
input dlp_wradd,//write enable to display address register from DLP
input [20:0] dlp_add, // display address from DLP (24:4),
input [31:0] hdat_in_aux, /* data to host from VGA_TOP or Second CRT.
* muxed here only for layout improvement */
// video overlay postion (in pixels)
input [39:0] vid_win_pos,
input mcdc_ready,
input mcpush,
input mclock,
input [127:0] datdc_in,
input vga_blank,
input vga_hsync,
input vga_vsync,
input disp_reg_rep,
input [3:0] disp_reg_crt,
output [31:0] hdat_out_crt_aux,
output [1:0] hint_out_tog, // interrupt
output reg vblnkst2, // to HBI status register
output [15:4] db_pitch_regist,
output reg [24:4] displ_start_vs,
output mcdc_req,
output [9:0] mcdcx,
output [11:0] mcdcyf,
output [4:0] mcdcpg ,
output blank_toidac,hcsync_toidac, vsync_toidac,
output [23:0] datdc_out,// 2 pixels of data to ramdac
output fdp_on, // (flat panel display on)
output [1:0] syncsenable_regist,
output [13:0] hactive_regist
);
parameter disp_param = 4'b0000;
// FIXME These are the values for 2 pixels per clock.
/*
parameter hactv_640 = 14'h0A0,
hactv_800 = 14'h0C0,
hactv_1024 = 14'h100,
hactv_1280 = 14'h140,
hactv_1600 = 14'h190;
*/
parameter hactv8_640 = 14'hA0,
hactv16_640 = 14'h140,
hactv32_640 = 14'h280,
hactv8_800 = 14'hC8,
hactv16_800 = 14'h190,
hactv32_800 = 14'h320,
hactv8_1024 = 14'h100,
hactv16_1024 = 14'h200,
hactv32_1024 = 14'h400,
hactv8_1152 = 14'h120,
hactv16_1152 = 14'h240,
hactv32_1152 = 14'h480,
hactv8_1280 = 14'h140,
hactv16_1280 = 14'h280,
hactv32_1280 = 14'h500,
hactv8_1600 = 14'h190,
hactv16_1600 = 14'h320,
hactv32_1600 = 14'h640;
wire [9:0] ovtl_x = vid_win_pos[39:30];
wire [9:0] ovtl_y = vid_win_pos[29:20];
wire [9:0] ovbr_x = vid_win_pos[19:10];
wire [9:0] ovbr_y = vid_win_pos[9:0];
reg [24:4] displ_start_vst;
wire int_blank_toidac,
int_hcsync_toidac,
int_vsync_toidac;
wire vblnk_early;
wire [11:0] mcdcy;
wire vsync_early;
wire [9:0] ff_stp, ff_rls;
wire [13:0]
hblank_regist,
hfporch_regist,
hswidth_regist;
wire [11:0] hicount_regist;
wire [11:0] vactive_regist,
vblank_regist,
vfporch_regist,
vswidth_regist;
wire [7:0] vicount_regist;
wire [3:0] dzoom_regist;
// CRTADDSL wires
wire [13:0] htotal_add,
hendsync_add,
endequal_add,
halfline_add,
endequalsec_add,
serrlongfp_substr,
serr_substr,
serrsec_substr;
wire [11:0] vendsync_add,
vendequal_add,
vtotal_add;
// other wires
wire [9:0] pinl_regist;
wire [24:4] displ_start_regist;
wire [24:4] sec_start_regist;
wire addr_load;
wire ss_mode;
wire addr_stat;
reg addr_stat1,
addr_stat2,
addr_tr,
ad_strst1,
ad_strst2,
ad_strst3,
vblnkst1;
wire lcounter_enstat;
wire [11:0] lcounter_stat;
reg [11:0] lcounter_stat_s; //latched and synchornized to host clock
reg lcount_toggle,
lcount_le2,
lcount_le1;
wire [127:0] dat_rd128,
dat_out128;
wire [31:0] hdat_out_from_crt;
wire [127:0] crt_data; // Data from ram to adout
wire [9:0] wrusedw;
wire poshs_regist;
wire posvs_regist;
wire compsync_regist;
wire crtintl_regist;
wire videnable_regist;
wire ovignr_regist;
wire ovignr16l_regist;
wire refresh_enable_regist;
wire hfpbhs;
wire dcnreset;
wire hblnk_early;
wire hblnk_late;
wire fsign_early;
wire cblnk_early;
wire rsuppr;
wire pop;
// Muxing for VGA signals
assign blank_toidac = (vga_en) ? vga_blank : int_blank_toidac;
assign hcsync_toidac = (vga_en) ? vga_hsync : int_hcsync_toidac;
assign vsync_toidac = (vga_en) ? vga_vsync : int_vsync_toidac;
// If this CRT is selected or if all CRTs are select pass
// through the chip select.
wire hcsn = (disp_reg_rep | (disp_reg_crt == disp_param)) ?
hcs_in : 1'b1;
//send data from crtregisters whenever chip_select for crt goes low
// otherwise send vga data on the same bus
assign hdat_out_crt_aux = (~hcsn) ? hdat_out_from_crt :
hdat_in_aux;
////////////////////////////////////////////////////////////////////////////
//////// synchronize display start address and make status signals //
always @(posedge pixclock or negedge hreset)
if (!hreset) begin
addr_tr <= 1'b0;
addr_stat1 <= 1'b0;
addr_stat2 <= 1'b0;
end else if (crtclock) begin
addr_stat1 <= addr_stat;
addr_stat2 <= addr_stat1;
if(addr_load & addr_stat2) begin
displ_start_vst[24:4] <= displ_start_regist[24:4];
addr_tr <= ~addr_tr;
end
end
always @(posedge hclock or negedge hreset)
if (!hreset) begin
ad_strst3 <= 1'b0;
ad_strst2 <= 1'b0;
ad_strst1 <= 1'b0;
vblnkst2 <= 1'b0;
vblnkst1 <= 1'b0;
end else begin
ad_strst3 <= ad_strst2 ^ ad_strst1;
ad_strst2 <= ad_strst1;
ad_strst1 <= addr_tr;
vblnkst2 <= vblnkst1;
vblnkst1 <= vblnk_early;
end
// select synchronized display start address if not in ss_mode, and toggle
// start address in ss_mode
// !!! lucy synchronize regist and sec to vsync????????
always @*
casex({ss_mode,mcdcy[0]})
2'b0x: displ_start_vs[24:4]=displ_start_vst[24:4];
2'b10: displ_start_vs[24:4]=displ_start_regist[24:4];
2'b11: displ_start_vs[24:4]=sec_start_regist[24:4];
endcase
//shift down mcdcy final if in ss_mode(will not work with zoom!)
assign mcdcyf = (ss_mode)? {1'b0, mcdcy[11:1]}: mcdcy[11:0];
////////////////////////////////////////////////////////////////////////////
// latch line counter status ( latching signal is synchronized with host
// clock, width active=2hclks, lcounter is stable at that time )
always @(posedge pixclock or negedge hreset)
if (!hreset)
lcount_toggle <= 1'b0;
else if (~lcounter_enstat && crtclock)
lcount_toggle <= ~lcount_toggle;
always @(posedge hclock or negedge hreset) begin
if (!hreset) begin
lcounter_stat_s <= 12'b0;
lcount_le2 <= 1'b0;
lcount_le1 <= 1'b0;
end else begin
if (lcount_le2 ^ lcount_le1) lcounter_stat_s <= lcounter_stat;
lcount_le2 <= lcount_le1;
lcount_le1 <= lcount_toggle;
end
end
crtregist CRTREGIST
(
.hclock (hclock),
.hnreset (hreset),
.hwr (hwr_in),
.hncs (hcsn),
.hnben (hnben_in),
.hdat_in (hdat_in),
.haddr (haddr),
.ad_strst (ad_strst3),
.vblnkst (vblnkst2),
.lcounter_stat (lcounter_stat_s),
.dlp_wradd (dlp_wradd),
.dlp_add (dlp_add),
.hdat_out (hdat_out_from_crt),
.vicount (vicount_regist),
.hicount (hicount_regist),
.hactive_o (hactive_regist),
.hblank_o (hblank_regist),
.hfporch_o (hfporch_regist),
.hswidth_o (hswidth_regist),
.vactive (vactive_regist),
.vblank (vblank_regist),
.vfporch (vfporch_regist),
.vswidth (vswidth_regist),
.dzoom (dzoom_regist),
.db_pitch (db_pitch_regist[15:4]),
.displ_start (displ_start_regist[24:4]),
.sec_start (sec_start_regist[24:4]),
.poshs (poshs_regist),
.posvs (posvs_regist),
.compsync (compsync_regist),
.crtintl (crtintl_regist),
.syncsenable (syncsenable_regist),
.videnable (videnable_regist),
.ovignr (ovignr_regist),
.ovignr16l (ovignr16l_regist),
.refresh_enable (refresh_enable_regist),
.fdp_on (fdp_on),
.addr_stat (addr_stat),
.pinl (pinl_regist),
.ss_mode (ss_mode)
);
crttimer CRTTIMER
(
.hnreset (hreset),
.vga_en (vga_en),
.pixclk (pixclock),
.crtclock (crtclock),
.crtintl_regist (crtintl_regist),
.hblank_regist (hblank_regist),
.hfporch_regist (hfporch_regist),
.vblank_regist (vblank_regist),
.vfporch_regist (vfporch_regist),
.poshs_regist (poshs_regist),
.posvs_regist (posvs_regist),
.compsync_regist (compsync_regist),
.syncsenable_regist(syncsenable_regist),
.videnable_regist(videnable_regist),
.refrenable_regist(refresh_enable_regist),
.vicount_regist (vicount_regist),
.hicount_regist (hicount_regist),
.htotal_add (htotal_add),
.hendsync_add (hendsync_add),
.endequal_add (endequal_add),
.halfline_add (halfline_add),
.endequalsec_add (endequalsec_add),
.serrlongfp_substr(serrlongfp_substr),
.serr_substr (serr_substr),
.serrsec_substr (serrsec_substr),
.vendsync_add (vendsync_add),
.vendequal_add (vendequal_add),
.vtotal_add (vtotal_add),
.hfpbhs (hfpbhs),
.dcnreset (dcnreset),
.dchcsync_o (int_hcsync_toidac),
.dcvsync_o (int_vsync_toidac),
.dcblank_o (int_blank_toidac),// lucy now to ramdac
.hblank (hblnk_early),
.hblank_d (hblnk_late),
.vblank (vblnk_early),
.fsign (fsign_early),
.cblank (cblnk_early),
.vsync (vsync_early),
.crtintdd_tog (hint_out_tog), // interrupts
.addr_load (addr_load),
.lcounter_enstat (lcounter_enstat),
.lcounter_stat (lcounter_stat)
);
crtaddsl CRTADDSL
(
.hactive_regist (hactive_regist),
.hblank_regist (hblank_regist),
.hfporch_regist (hfporch_regist),
.hswidth_regist (hswidth_regist),
.vactive_regist (vactive_regist),
.vblank_regist (vblank_regist),
.vfporch_regist (vfporch_regist),
.vswidth_regist (vswidth_regist),
.htotal_add (htotal_add),
.hendsync_add (hendsync_add),
.endequal_add (endequal_add),
.halfline_add (halfline_add),
.endequalsec_add (endequalsec_add),
.serrlongfp_substr(serrlongfp_substr),
.serr_substr (serr_substr),
.serrsec_substr (serrsec_substr),
.vendsync_add (vendsync_add),
.vendequal_add (vendequal_add),
.vtotal_add (vtotal_add),
.hfpbhs (hfpbhs)
);
dc_contr DCCONTR
(
.dcnreset (dcnreset),
.hnreset (hreset),
.pixclock (pixclock),
.crtclock (crtclock),
.mclock (mclock),
.vsync (vsync_early),
.refresh_enable_regist(refresh_enable_regist),
.dzoom_regist (dzoom_regist),
.vactive_regist (vactive_regist),
.pinl_regist (pinl_regist),
.mcdc_ready (mcdc_ready),
.wrusedw (wrusedw),
.ovtl_x (ovtl_x),
.ovtl_y (ovtl_y),
.ovbr_x (ovbr_x),
.ovbr_y (ovbr_y),
.bpp (bpp),
.ovnokey (ovnokey),
.ovignr_regist (ovignr_regist),
.ovignr16l_regist(ovignr_regist),
.ff_stp (ff_stp),
.ff_rls (ff_rls),
.rsuppr (rsuppr),
.mcdc_req (mcdc_req),
.mcdcy (mcdcy),
.mcdcx (mcdcx),
.mcdcpg (mcdcpg)
);
dc_adout DCADOUT
(
.pixclock (pixclock),
.dcnreset (dcnreset),
.hnreset (hreset),
.vsync (vsync_early),
.cblank (cblnk_early),
.rsuppr (rsuppr),
.ff_stp (ff_stp),
.ff_rls (ff_rls),
.ovtl_y (11'h0), // ovtl_y),
.ovbr_y (11'h0), // ovbr_y),
.bpp (bpp),
.crt_data (crt_data),
.vga_din (vga_din),
.vga_en (vga_en),
.pop (pop),
.datdc_out (datdc_out)
);
// The original Output Ram was as follows:
// ASYNC RAM
// 128 bit output register
// 128 to 64 mux
// 64 bit register
// This has been replaced by an Altera RAM w/ 128 bit input and 64 bit output
// Addresses are registered which replaces the first output flop.
// The output is also registered replacing the 64 bit output register
fifo_128x512a U_DCFIFO
(
.data (datdc_in),
.wrreq (mcpush),
.rdreq (pop),
.rdclk (pixclock),
.wrclk (mclock),
.aclr (~(vsync_early & dcnreset)),
.q (crt_data),
.wrusedw (wrusedw),
.rdempty (),
.wrfull ()
);
endmodule
|
module divider(divident,divisor,quotient);
input wire [31:0] divident;
input wire [31:0] divisor;
output reg [31:0] quotient;
reg [47:0]tmpDivident;
reg [23:0]tmpDivisor;
reg [25:0]tmpQuotient;
reg [25:0] remainder;
reg [8:0]exponent;
reg [8:0]tmp;
integer i; // 整数,用于计数
always @(divident or divisor) // 被除数,除数
begin
quotient=0;
remainder=0;
tmpDivident={1,divident[22:0],24'b0};
tmpDivisor={1,divisor[22:0]};
exponent=divident[30:23]+128-divisor[30:23];
tmpQuotient=0;
// 开始余数和商清零
tmp=divident[30:23]+127;
if(tmp<divisor[30:23])
begin
quotient=0;
end
else if(tmp-divisor[30:23]>254)
begin
quotient={divident[31]^divisor[31],8'b1,23'b0};
end
else if(divident==0||divisor[30:23]-255==0)
begin
quotient=0;
end // 若除数为0则显示错误
else if(divident[30:23]==255)
begin
quotient=divident;
end
else if(divisor==0)
begin // 商0,余数为除数
quotient={divident[31],8'b1,23'b0};
end
else
begin
for (i=48;i>0;i=i-1) // 循环48次
begin
remainder={remainder[25:0],tmpDivident[i-1]}; // 把did[i-1]连接到rem后
tmpQuotient=tmpQuotient<<1; // 商左移一位
if(remainder>=tmpDivisor) // 若拼接后rem>=除数dis
begin
tmpQuotient=tmpQuotient+1; // 商值自加1
remainder=remainder-tmpDivisor; // 新余数变为旧余数减除数
end
end
for(i=3;i>0;i=i-1)
begin
if(tmpQuotient[25]!=1)
begin
tmpQuotient=tmpQuotient*2;//左移
exponent=exponent-1;
end
end
quotient={divident[31]^divisor[31],exponent[7:0],tmpQuotient[24:2]};
end
end // 结束
endmodule
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.0
// \ \ Application: MIG
// / / Filename: ddr2_mem_if_top.v
// /___/ /\ Date Last Modified: $Date: 2009/01/15 14:22:14 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR/DDR2
//Purpose:
// Top-level for parameterizable (DDR or DDR2) memory interface
//Reference:
//Revision History:
// Rev 1.1 - Parameter USE_DM_PORT added. PK. 6/25/08
// Rev 1.2 - Parameter HIGH_PERFORMANCE_MODE added. PK. 7/10/08
// Rev 1.3 - Parameter CS_BITS added. PK. 10/8/08
// Rev 1.4 - Parameter IODELAY_GRP added. PK. 11/27/08
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_mem_if_top #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module ddr2_mig module. Please refer to
// the ddr2_mig module for actual values.
parameter BANK_WIDTH = 2,
parameter CKE_WIDTH = 1,
parameter CLK_WIDTH = 1,
parameter COL_WIDTH = 10,
parameter CS_BITS = 0,
parameter CS_NUM = 1,
parameter CS_WIDTH = 1,
parameter USE_DM_PORT = 1,
parameter DM_WIDTH = 9,
parameter DQ_WIDTH = 72,
parameter DQ_BITS = 7,
parameter DQ_PER_DQS = 8,
parameter DQS_BITS = 4,
parameter DQS_WIDTH = 9,
parameter HIGH_PERFORMANCE_MODE = "TRUE",
parameter IODELAY_GRP = "IODELAY_MIG",
parameter ODT_WIDTH = 1,
parameter ROW_WIDTH = 14,
parameter APPDATA_WIDTH = 144,
parameter ADDITIVE_LAT = 0,
parameter BURST_LEN = 4,
parameter BURST_TYPE = 0,
parameter CAS_LAT = 5,
parameter ECC_ENABLE = 0,
parameter MULTI_BANK_EN = 1,
parameter TWO_T_TIME_EN = 0,
parameter ODT_TYPE = 1,
parameter DDR_TYPE = 1,
parameter REDUCE_DRV = 0,
parameter REG_ENABLE = 1,
parameter TREFI_NS = 7800,
parameter TRAS = 40000,
parameter TRCD = 15000,
parameter TRFC = 105000,
parameter TRP = 15000,
parameter TRTP = 7500,
parameter TWR = 15000,
parameter TWTR = 10000,
parameter CLK_PERIOD = 3000,
parameter SIM_ONLY = 0,
parameter DEBUG_EN = 0,
parameter FPGA_SPEED_GRADE = 2
)
(
input clk0,
input usr_clk, // jb
input clk90,
input clkdiv0,
input rst0,
input rst90,
input rstdiv0,
input [2:0] app_af_cmd,
input [30:0] app_af_addr,
input app_af_wren,
input app_wdf_wren,
input [APPDATA_WIDTH-1:0] app_wdf_data,
input [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
output [1:0] rd_ecc_error,
output app_af_afull,
output app_wdf_afull,
output rd_data_valid,
output [APPDATA_WIDTH-1:0] rd_data_fifo_out,
output phy_init_done,
output [CLK_WIDTH-1:0] ddr_ck,
output [CLK_WIDTH-1:0] ddr_ck_n,
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_ras_n,
output ddr_cas_n,
output ddr_we_n,
output [CS_WIDTH-1:0] ddr_cs_n,
output [CKE_WIDTH-1:0] ddr_cke,
output [ODT_WIDTH-1:0] ddr_odt,
output [DM_WIDTH-1:0] ddr_dm,
inout [DQS_WIDTH-1:0] ddr_dqs,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
inout [DQ_WIDTH-1:0] ddr_dq,
// Debug signals (optional use)
input dbg_idel_up_all,
input dbg_idel_down_all,
input dbg_idel_up_dq,
input dbg_idel_down_dq,
input dbg_idel_up_dqs,
input dbg_idel_down_dqs,
input dbg_idel_up_gate,
input dbg_idel_down_gate,
input [DQ_BITS-1:0] dbg_sel_idel_dq,
input dbg_sel_all_idel_dq,
input [DQS_BITS:0] dbg_sel_idel_dqs,
input dbg_sel_all_idel_dqs,
input [DQS_BITS:0] dbg_sel_idel_gate,
input dbg_sel_all_idel_gate,
output [3:0] dbg_calib_done,
output [3:0] dbg_calib_err,
output [(6*DQ_WIDTH)-1:0] dbg_calib_dq_tap_cnt,
output [(6*DQS_WIDTH)-1:0] dbg_calib_dqs_tap_cnt,
output [(6*DQS_WIDTH)-1:0] dbg_calib_gate_tap_cnt,
output [DQS_WIDTH-1:0] dbg_calib_rd_data_sel,
output [(5*DQS_WIDTH)-1:0] dbg_calib_rden_dly,
output [(5*DQS_WIDTH)-1:0] dbg_calib_gate_dly
);
wire [30:0] af_addr;
wire [2:0] af_cmd;
wire af_empty;
wire [ROW_WIDTH-1:0] ctrl_addr;
wire ctrl_af_rden;
wire [BANK_WIDTH-1:0] ctrl_ba;
wire ctrl_cas_n;
wire [CS_NUM-1:0] ctrl_cs_n;
wire ctrl_ras_n;
wire ctrl_rden;
wire ctrl_ref_flag;
wire ctrl_we_n;
wire ctrl_wren;
wire [DQS_WIDTH-1:0] phy_calib_rden;
wire [DQS_WIDTH-1:0] phy_calib_rden_sel;
wire [DQ_WIDTH-1:0] rd_data_fall;
wire [DQ_WIDTH-1:0] rd_data_rise;
wire [(2*DQ_WIDTH)-1:0] wdf_data;
wire [((2*DQ_WIDTH)/8)-1:0] wdf_mask_data;
wire wdf_rden;
//***************************************************************************
ddr2_phy_top #
(
.BANK_WIDTH (BANK_WIDTH),
.CKE_WIDTH (CKE_WIDTH),
.CLK_WIDTH (CLK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_BITS (CS_BITS),
.CS_NUM (CS_NUM),
.CS_WIDTH (CS_WIDTH),
.USE_DM_PORT (USE_DM_PORT),
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQ_BITS (DQ_BITS),
.DQ_PER_DQS (DQ_PER_DQS),
.DQS_BITS (DQS_BITS),
.DQS_WIDTH (DQS_WIDTH),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.IODELAY_GRP (IODELAY_GRP),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.TWO_T_TIME_EN (TWO_T_TIME_EN),
.ADDITIVE_LAT (ADDITIVE_LAT),
.BURST_LEN (BURST_LEN),
.BURST_TYPE (BURST_TYPE),
.CAS_LAT (CAS_LAT),
.ECC_ENABLE (ECC_ENABLE),
.ODT_TYPE (ODT_TYPE),
.DDR_TYPE (DDR_TYPE),
.REDUCE_DRV (REDUCE_DRV),
.REG_ENABLE (REG_ENABLE),
.TWR (TWR),
.CLK_PERIOD (CLK_PERIOD),
.SIM_ONLY (SIM_ONLY),
.DEBUG_EN (DEBUG_EN),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE)
)
u_phy_top
(
.clk0 (clk0),
.clk90 (clk90),
.clkdiv0 (clkdiv0),
.rst0 (rst0),
.rst90 (rst90),
.rstdiv0 (rstdiv0),
.ctrl_wren (ctrl_wren),
.ctrl_addr (ctrl_addr),
.ctrl_ba (ctrl_ba),
.ctrl_ras_n (ctrl_ras_n),
.ctrl_cas_n (ctrl_cas_n),
.ctrl_we_n (ctrl_we_n),
.ctrl_cs_n (ctrl_cs_n),
.ctrl_rden (ctrl_rden),
.ctrl_ref_flag (ctrl_ref_flag),
.wdf_data (wdf_data),
.wdf_mask_data (wdf_mask_data),
.wdf_rden (wdf_rden),
.phy_init_done (phy_init_done),
.phy_calib_rden (phy_calib_rden),
.phy_calib_rden_sel (phy_calib_rden_sel),
.rd_data_rise (rd_data_rise),
.rd_data_fall (rd_data_fall),
.ddr_ck (ddr_ck),
.ddr_ck_n (ddr_ck_n),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_ras_n (ddr_ras_n),
.ddr_cas_n (ddr_cas_n),
.ddr_we_n (ddr_we_n),
.ddr_cs_n (ddr_cs_n),
.ddr_cke (ddr_cke),
.ddr_odt (ddr_odt),
.ddr_dm (ddr_dm),
.ddr_dqs (ddr_dqs),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dq (ddr_dq),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_dq (dbg_idel_up_dq),
.dbg_idel_down_dq (dbg_idel_down_dq),
.dbg_idel_up_dqs (dbg_idel_up_dqs),
.dbg_idel_down_dqs (dbg_idel_down_dqs),
.dbg_idel_up_gate (dbg_idel_up_gate),
.dbg_idel_down_gate (dbg_idel_down_gate),
.dbg_sel_idel_dq (dbg_sel_idel_dq),
.dbg_sel_all_idel_dq (dbg_sel_all_idel_dq),
.dbg_sel_idel_dqs (dbg_sel_idel_dqs),
.dbg_sel_all_idel_dqs (dbg_sel_all_idel_dqs),
.dbg_sel_idel_gate (dbg_sel_idel_gate),
.dbg_sel_all_idel_gate (dbg_sel_all_idel_gate),
.dbg_calib_done (dbg_calib_done),
.dbg_calib_err (dbg_calib_err),
.dbg_calib_dq_tap_cnt (dbg_calib_dq_tap_cnt),
.dbg_calib_dqs_tap_cnt (dbg_calib_dqs_tap_cnt),
.dbg_calib_gate_tap_cnt (dbg_calib_gate_tap_cnt),
.dbg_calib_rd_data_sel (dbg_calib_rd_data_sel),
.dbg_calib_rden_dly (dbg_calib_rden_dly),
.dbg_calib_gate_dly (dbg_calib_gate_dly)
);
ddr2_usr_top #
(
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_BITS (CS_BITS),
.DQ_WIDTH (DQ_WIDTH),
.DQ_PER_DQS (DQ_PER_DQS),
.DQS_WIDTH (DQS_WIDTH),
.APPDATA_WIDTH (APPDATA_WIDTH),
.ECC_ENABLE (ECC_ENABLE),
.ROW_WIDTH (ROW_WIDTH)
)
u_usr_top
(
.clk0 (clk0),
.usr_clk (usr_clk), //jb
.clk90 (clk90),
.rst0 (rst0),
.rd_data_in_rise (rd_data_rise),
.rd_data_in_fall (rd_data_fall),
.phy_calib_rden (phy_calib_rden),
.phy_calib_rden_sel(phy_calib_rden_sel),
.rd_data_valid (rd_data_valid),
.rd_ecc_error (rd_ecc_error),
.rd_data_fifo_out (rd_data_fifo_out),
.app_af_cmd (app_af_cmd),
.app_af_addr (app_af_addr),
.app_af_wren (app_af_wren),
.ctrl_af_rden (ctrl_af_rden),
.af_cmd (af_cmd),
.af_addr (af_addr),
.af_empty (af_empty),
.app_af_afull (app_af_afull),
.app_wdf_wren (app_wdf_wren),
.app_wdf_data (app_wdf_data),
.app_wdf_mask_data (app_wdf_mask_data),
.wdf_rden (wdf_rden),
.app_wdf_afull (app_wdf_afull),
.wdf_data (wdf_data),
.wdf_mask_data (wdf_mask_data)
);
ddr2_ctrl #
(
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_BITS (CS_BITS),
.CS_NUM (CS_NUM),
.ROW_WIDTH (ROW_WIDTH),
.ADDITIVE_LAT (ADDITIVE_LAT),
.BURST_LEN (BURST_LEN),
.CAS_LAT (CAS_LAT),
.ECC_ENABLE (ECC_ENABLE),
.REG_ENABLE (REG_ENABLE),
.MULTI_BANK_EN (MULTI_BANK_EN),
.TWO_T_TIME_EN (TWO_T_TIME_EN),
.TREFI_NS (TREFI_NS),
.TRAS (TRAS),
.TRCD (TRCD),
.TRFC (TRFC),
.TRP (TRP),
.TRTP (TRTP),
.TWR (TWR),
.TWTR (TWTR),
.CLK_PERIOD (CLK_PERIOD),
.DDR_TYPE (DDR_TYPE)
)
u_ctrl
(
.clk (clk0),
.rst (rst0),
.af_cmd (af_cmd),
.af_addr (af_addr),
.af_empty (af_empty),
.phy_init_done (phy_init_done),
.ctrl_ref_flag (ctrl_ref_flag),
.ctrl_af_rden (ctrl_af_rden),
.ctrl_wren (ctrl_wren),
.ctrl_rden (ctrl_rden),
.ctrl_addr (ctrl_addr),
.ctrl_ba (ctrl_ba),
.ctrl_ras_n (ctrl_ras_n),
.ctrl_cas_n (ctrl_cas_n),
.ctrl_we_n (ctrl_we_n),
.ctrl_cs_n (ctrl_cs_n)
);
endmodule
|
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
//
// This is the chip top that contains the ZAP core along with
// 2 x UARTs
// 2 x Timers
// 1 x VIC
//
// UART0 address space FFFFFFE0 to FFFFFFFF
// Timer0 address space FFFFFFC0 to FFFFFFDF
// VIC0 address space FFFFFFA0 to FFFFFFBF
// UART1 address space FFFFFF80 to FFFFFF9F
// Timer1 address space FFFFFF60 to FFFFFF7F
//
// Accesses outside this go the the wishbone interface.
//
// An extenal Wishbone interface is provided to allow connection to an external
// Wishbone network for RAMs, ROMs etc.
//
module chip_top #(
// CPU config.
parameter DATA_SECTION_TLB_ENTRIES = 4,
parameter DATA_LPAGE_TLB_ENTRIES = 8,
parameter DATA_SPAGE_TLB_ENTRIES = 16,
parameter DATA_FPAGE_TLB_ENTRIES = 32,
parameter DATA_CACHE_SIZE = 1024,
parameter CODE_SECTION_TLB_ENTRIES = 4,
parameter CODE_LPAGE_TLB_ENTRIES = 8,
parameter CODE_SPAGE_TLB_ENTRIES = 16,
parameter CODE_FPAGE_TLB_ENTRIES = 32,
parameter CODE_CACHE_SIZE = 1024,
parameter FIFO_DEPTH = 4,
parameter BP_ENTRIES = 1024,
parameter STORE_BUFFER_DEPTH = 32
)(
// Clk and rst
input wire SYS_CLK,
input wire SYS_RST,
// UART 0
input wire UART0_RXD,
output wire UART0_TXD,
// UART 1
input wire UART1_RXD,
output wire UART1_TXD,
// Remaining IRQs to the interrupt controller.
input wire [27:0] I_IRQ,
// Single FIQ input directly to ZAP CPU.
input wire I_FIQ,
// External Wishbone Connection (for RAMs etc).
output reg O_WB_STB,
output reg O_WB_CYC,
output wire [31:0] O_WB_DAT,
output wire [31:0] O_WB_ADR,
output wire [3:0] O_WB_SEL,
output wire O_WB_WE,
input wire I_WB_ACK,
input wire [31:0] I_WB_DAT
);
`include "zap_defines.vh"
`include "zap_localparams.vh"
`include "zap_functions.vh"
// Peripheral addresses.
localparam UART0_LO = 32'hFFFFFFE0;
localparam UART0_HI = 32'hFFFFFFFF;
localparam TIMER0_LO = 32'hFFFFFFC0;
localparam TIMER0_HI = 32'hFFFFFFDF;
localparam VIC_LO = 32'hFFFFFFA0;
localparam VIC_HI = 32'hFFFFFFBF;
localparam UART1_LO = 32'hFFFFFF80;
localparam UART1_HI = 32'hFFFFFF9F;
localparam TIMER1_LO = 32'hFFFFFF60;
localparam TIMER1_HI = 32'hFFFFFF7F;
// Internal signals.
wire i_clk = SYS_CLK;
wire i_reset = SYS_RST;
wire [1:0] uart_in = {UART1_RXD, UART0_RXD};
wire [1:0] uart_out;
assign {UART1_TXD, UART0_TXD} = uart_out;
wire data_wb_cyc;
wire data_wb_stb;
reg [31:0] data_wb_din;
reg data_wb_ack;
reg data_wb_cyc_uart [1:0], data_wb_cyc_timer [1:0], data_wb_cyc_vic;
reg data_wb_stb_uart [1:0], data_wb_stb_timer [1:0], data_wb_stb_vic;
wire [31:0] data_wb_din_uart [1:0], data_wb_din_timer [1:0], data_wb_din_vic;
wire data_wb_ack_uart [1:0], data_wb_ack_timer [1:0], data_wb_ack_vic;
wire [3:0] data_wb_sel;
wire data_wb_we;
wire [31:0] data_wb_dout;
wire [31:0] data_wb_adr;
wire [2:0] data_wb_cti; // Cycle Type Indicator.
wire global_irq;
wire [1:0] uart_irq;
wire [1:0] timer_irq;
// Common WB signals to output.
assign O_WB_ADR = data_wb_adr;
assign O_WB_WE = data_wb_we;
assign O_WB_DAT = data_wb_dout;
assign O_WB_SEL = data_wb_sel;
// Wishbone fabric.
always @*
begin:blk1
integer ii;
for(ii=0;ii<=1;ii=ii+1)
begin
data_wb_cyc_uart [ii] = 0;
data_wb_stb_uart [ii] = 0;
data_wb_cyc_timer[ii] = 0;
data_wb_stb_timer[ii] = 0;
end
data_wb_cyc_vic = 0;
data_wb_stb_vic = 0;
O_WB_CYC = 0;
O_WB_STB = 0;
if ( data_wb_adr >= UART0_LO && data_wb_adr <= UART0_HI ) // UART0 access
begin
data_wb_cyc_uart[0] = data_wb_cyc;
data_wb_stb_uart[0] = data_wb_stb;
data_wb_ack = data_wb_ack_uart[0];
data_wb_din = data_wb_din_uart[0];
end
else if ( data_wb_adr >= TIMER0_LO && data_wb_adr <= TIMER0_HI ) // Timer0 access
begin
data_wb_cyc_timer[0] = data_wb_cyc;
data_wb_stb_timer[0] = data_wb_stb;
data_wb_ack = data_wb_ack_timer[0];
data_wb_din = data_wb_din_timer[0];
end
else if ( data_wb_adr >= VIC_LO && data_wb_adr <= VIC_HI ) // VIC access.
begin
data_wb_cyc_vic = data_wb_cyc;
data_wb_stb_vic = data_wb_stb;
data_wb_ack = data_wb_ack_vic;
data_wb_din = data_wb_din_vic;
end
else if ( data_wb_adr >= UART1_LO && data_wb_adr <= UART1_HI ) // UART1 access
begin
data_wb_cyc_uart[1] = data_wb_cyc;
data_wb_stb_uart[1] = data_wb_stb;
data_wb_ack = data_wb_ack_uart[1];
data_wb_din = data_wb_din_uart[1];
end
else if ( data_wb_adr >= TIMER1_LO && data_wb_adr <= TIMER1_HI ) // Timer1 access
begin
data_wb_cyc_timer[1] = data_wb_cyc;
data_wb_stb_timer[1] = data_wb_stb;
data_wb_ack = data_wb_ack_timer[1];
data_wb_din = data_wb_din_timer[1];
end
else // External WB access.
begin
O_WB_CYC = data_wb_cyc;
O_WB_STB = data_wb_stb;
data_wb_ack = I_WB_ACK;
data_wb_din = I_WB_DAT;
end
end
// =========================
// Processor core.
// =========================
zap_top #(
.FIFO_DEPTH(FIFO_DEPTH),
.BP_ENTRIES(BP_ENTRIES),
.STORE_BUFFER_DEPTH(STORE_BUFFER_DEPTH),
.DATA_SECTION_TLB_ENTRIES(DATA_SECTION_TLB_ENTRIES),
.DATA_LPAGE_TLB_ENTRIES(DATA_LPAGE_TLB_ENTRIES),
.DATA_SPAGE_TLB_ENTRIES(DATA_SPAGE_TLB_ENTRIES),
.DATA_FPAGE_TLB_ENTRIES(DATA_FPAGE_TLB_ENTRIES),
.DATA_CACHE_SIZE(DATA_CACHE_SIZE),
.CODE_SECTION_TLB_ENTRIES(CODE_SECTION_TLB_ENTRIES),
.CODE_LPAGE_TLB_ENTRIES(CODE_LPAGE_TLB_ENTRIES),
.CODE_SPAGE_TLB_ENTRIES(CODE_SPAGE_TLB_ENTRIES),
.CODE_FPAGE_TLB_ENTRIES(CODE_FPAGE_TLB_ENTRIES),
.CODE_CACHE_SIZE(CODE_CACHE_SIZE)
)
u_zap_top
(
.i_clk(i_clk),
.i_reset(i_reset),
.i_irq(global_irq),
.i_fiq (I_FIQ),
.o_wb_cyc (data_wb_cyc),
.o_wb_stb (data_wb_stb),
.o_wb_adr (data_wb_adr),
.o_wb_we (data_wb_we),
.o_wb_cti (data_wb_cti),
.i_wb_dat (data_wb_din),
.o_wb_dat (data_wb_dout),
.i_wb_ack (data_wb_ack),
.o_wb_sel (data_wb_sel),
.o_wb_bte () // Always zero (Linear)
);
// ===============================
// 2 x UART + 2 x Timer
// ===============================
genvar gi;
generate
begin
for(gi=0;gi<=1;gi=gi+1)
begin: uart_gen
uart_top u_uart_top (
// WISHBONE interface
.wb_clk_i(i_clk),
.wb_rst_i(i_reset),
.wb_adr_i(data_wb_adr),
.wb_dat_i(data_wb_dout),
.wb_dat_o(data_wb_din_uart[gi]),
.wb_we_i (data_wb_we),
.wb_stb_i(data_wb_stb_uart[gi]),
.wb_cyc_i(data_wb_cyc_uart[gi]),
.wb_sel_i(data_wb_sel),
.wb_ack_o(data_wb_ack_uart[gi]),
.int_o (uart_irq[gi]), // Interrupt.
// UART signals.
.srx_pad_i (uart_in[gi]),
.stx_pad_o (uart_out[gi]),
// Tied or open.
.rts_pad_o(),
.cts_pad_i(1'd0),
.dtr_pad_o(),
.dsr_pad_i(1'd0),
.ri_pad_i (1'd0),
.dcd_pad_i(1'd0)
);
timer u_timer (
.i_clk(i_clk),
.i_rst(i_reset),
.i_wb_adr(data_wb_adr),
.i_wb_dat(data_wb_dout),
.i_wb_stb(data_wb_stb_timer[gi]),
.i_wb_cyc(data_wb_cyc_timer[gi]), // From core
.i_wb_wen(data_wb_we),
.i_wb_sel(data_wb_sel),
.o_wb_dat(data_wb_din_timer[gi]), // To core.
.o_wb_ack(data_wb_ack_timer[gi]),
.o_irq(timer_irq[gi]) // Interrupt
);
end
end
endgenerate
// ===============================
// VIC
// ===============================
vic #(.SOURCES(32)) u_vic (
.i_clk (i_clk),
.i_rst (i_reset),
.i_wb_adr(data_wb_adr),
.i_wb_dat(data_wb_dout),
.i_wb_stb(data_wb_stb_vic),
.i_wb_cyc(data_wb_cyc_vic), // From core
.i_wb_wen(data_wb_we),
.i_wb_sel(data_wb_sel),
.o_wb_dat(data_wb_din_vic), // To core.
.o_wb_ack(data_wb_ack_vic),
.i_irq({I_IRQ, timer_irq[1], uart_irq[1], timer_irq[0], uart_irq[0]}), // Concatenate 32 interrupt sources.
.o_irq(global_irq) // Interrupt out
);
endmodule // chip_top
`default_nettype none
module ram #(parameter SIZE_IN_BYTES = 4096) (
input wire i_clk,
input wire i_wb_cyc,
input wire i_wb_stb,
input wire [31:0] i_wb_adr,
input wire [31:0] i_wb_dat,
input wire [3:0] i_wb_sel,
input wire i_wb_we,
output reg [31:0] o_wb_dat = 32'd0,
output reg o_wb_ack = 1'd0
);
`include "zap_defines.vh"
`include "zap_localparams.vh"
`include "zap_functions.vh"
integer seed = `SEED;
reg [31:0] ram [SIZE_IN_BYTES/4 -1:0];
// Initialize the RAM with the generated image.
initial
begin:blk1
integer i;
integer j;
reg [7:0] mem [SIZE_IN_BYTES-1:0];
j = 0;
for ( i=0;i<SIZE_IN_BYTES;i=i+1)
mem[i] = 8'd0;
`include `MEMORY_IMAGE
for (i=0;i<SIZE_IN_BYTES/4;i=i+1)
begin
ram[i] = {mem[j+3], mem[j+2], mem[j+1], mem[j]};
j = j + 4;
end
end
// Wishbone RAM.
// Models a variable delay RAM.
always @ ( negedge i_clk )
begin:blk
reg stall;
stall = $random(seed);
if ( !i_wb_we && i_wb_cyc && i_wb_stb && !stall )
begin
o_wb_ack <= 1'd1;
o_wb_dat <= ram [ i_wb_adr >> 2 ];
end
else if ( i_wb_we && i_wb_cyc && i_wb_stb && !stall )
begin
o_wb_ack <= 1'd1;
o_wb_dat <= 'dx;
if ( i_wb_sel[0] ) ram [ i_wb_adr >> 2 ][7:0] <= i_wb_dat[7:0];
if ( i_wb_sel[1] ) ram [ i_wb_adr >> 2 ][15:8] <= i_wb_dat[15:8];
if ( i_wb_sel[2] ) ram [ i_wb_adr >> 2 ][23:16] <= i_wb_dat[23:16];
if ( i_wb_sel[3] ) ram [ i_wb_adr >> 2 ][31:24] <= i_wb_dat[31:24];
end
else
begin
o_wb_ack <= 1'd0;
o_wb_dat <= 'dx;
end
end
endmodule // ram
`default_nettype wire
`default_nettype none
module timer #(
// Register addresses.
parameter [31:0] TIMER_ENABLE_REGISTER = 32'h0,
parameter [31:0] TIMER_LIMIT_REGISTER = 32'h4,
parameter [31:0] TIMER_INTACK_REGISTER = 32'h8,
parameter [31:0] TIMER_START_REGISTER = 32'hC
) (
// Clock and reset.
input wire i_clk,
input wire i_rst,
// Wishbone interface.
input wire [31:0] i_wb_dat,
input wire [3:0] i_wb_adr,
input wire i_wb_stb,
input wire i_wb_cyc,
input wire i_wb_wen,
input wire [3:0] i_wb_sel,
output reg [31:0] o_wb_dat,
output reg o_wb_ack,
// Interrupt output. Level interrupt.
output reg o_irq
);
// Timer registers.
reg [31:0] DEVEN;
reg [31:0] DEVPR;
reg [31:0] DEVAK;
reg [31:0] DEVST;
`ifndef ZAP_SOC_TIMER
`define ZAP_SOC_TIMER
`define DEVEN TIMER_ENABLE_REGISTER
`define DEVPR TIMER_LIMIT_REGISTER
`define DEVAK TIMER_INTACK_REGISTER
`define DEVST TIMER_START_REGISTER
`endif
// Timer core.
reg [31:0] ctr; // Core counter.
reg start; // Pulse to start the timer. Done signal is cleared.
reg done; // Asserted when timer is done.
reg clr; // Clears the done signal.
reg [31:0] state; // State
reg enable; // 1 to enable the timer.
reg [31:0] finalval; // Final value to count.
reg [31:0] wbstate;
localparam IDLE = 0;
localparam COUNTING = 1;
localparam DONE = 2;
localparam WBIDLE = 0;
localparam WBREAD = 1;
localparam WBWRITE = 2;
localparam WBACK = 3;
localparam WBDONE = 4;
always @ (*)
o_irq = done;
always @ (*)
begin
start = DEVST[0];
enable = DEVEN[0];
finalval = DEVPR;
clr = DEVAK[0];
end
always @ ( posedge i_clk )
begin
DEVST <= 0;
if ( i_rst )
begin
DEVEN <= 0;
DEVPR <= 0;
DEVAK <= 0;
DEVST <= 0;
wbstate <= WBIDLE;
o_wb_dat <= 0;
o_wb_ack <= 0;
end
else
begin
case(wbstate)
WBIDLE:
begin
o_wb_ack <= 1'd0;
if ( i_wb_stb && i_wb_cyc )
begin
if ( i_wb_wen )
wbstate <= WBWRITE;
else
wbstate <= WBREAD;
end
end
WBWRITE:
begin
case(i_wb_adr)
`DEVEN: // DEVEN
begin
$display($time, " - %m :: Writing register DEVEN...");
if ( i_wb_sel[0] ) DEVEN[7:0] <= i_wb_dat >> 0;
if ( i_wb_sel[1] ) DEVEN[15:8] <= i_wb_dat >> 8;
if ( i_wb_sel[2] ) DEVEN[23:16] <= i_wb_dat >> 16;
if ( i_wb_sel[3] ) DEVEN[31:24] <= i_wb_dat >> 24;
end
`DEVPR: // DEVPR
begin
$display($time, " - %m :: Writing register DEVPR...");
if ( i_wb_sel[0] ) DEVPR[7:0] <= i_wb_dat >> 0;
if ( i_wb_sel[1] ) DEVPR[15:8] <= i_wb_dat >> 8;
if ( i_wb_sel[2] ) DEVPR[23:16] <= i_wb_dat >> 16;
if ( i_wb_sel[3] ) DEVPR[31:24] <= i_wb_dat >> 24;
end
`DEVAK: // DEVAK
begin
$display($time, " - %m :: Writing register DEVAK...");
if ( i_wb_sel[0] ) DEVPR[7:0] <= i_wb_dat >> 0;
if ( i_wb_sel[1] ) DEVPR[15:8] <= i_wb_dat >> 8;
if ( i_wb_sel[2] ) DEVPR[23:16] <= i_wb_dat >> 16;
if ( i_wb_sel[3] ) DEVPR[31:24] <= i_wb_dat >> 24;
end
`DEVST: // DEVST
begin
$display($time, " - %m :: Writing register DEVST...");
if ( i_wb_sel[0] ) DEVST[7:0] <= i_wb_dat >> 0;
if ( i_wb_sel[1] ) DEVST[15:8] <= i_wb_dat >> 8;
if ( i_wb_sel[2] ) DEVST[23:16] <= i_wb_dat >> 16;
if ( i_wb_sel[3] ) DEVST[31:24] <= i_wb_dat >> 24;
end
endcase
wbstate <= WBACK;
end
WBREAD:
begin
case(i_wb_adr)
`DEVEN: o_wb_dat <= DEVEN;
`DEVPR: o_wb_dat <= DEVPR;
`DEVAK: o_wb_dat <= done;
`DEVST: o_wb_dat <= 32'd0;
endcase
wbstate <= WBACK;
end
WBACK:
begin
o_wb_ack <= 1'd1;
wbstate <= WBDONE;
end
WBDONE:
begin
o_wb_ack <= 1'd0;
wbstate <= IDLE;
end
endcase
end
end
always @ (posedge i_clk)
begin
if ( i_rst || !enable )
begin
ctr <= 0;
done <= 0;
state <= IDLE;
end
else // if enabled
begin
case(state)
IDLE:
begin
if ( start )
begin
$display($time," - %m :: Timer started counting...");
state <= COUNTING;
end
end
COUNTING:
begin
ctr <= ctr + 1;
if ( ctr == finalval )
begin
$display($time, " - %m :: Timer done counting...");
state <= DONE;
end
end
DONE:
begin
done <= 1;
if ( start )
begin
$display($time, " - %m :: Timer got START from DONE state...");
done <= 0;
state <= COUNTING;
ctr <= 0;
end
else if ( clr ) // Acknowledge.
begin
$display($time, " - %m :: Timer got done in ACK state...");
done <= 0;
state <= IDLE;
ctr <= 0;
end
end
endcase
end
end
endmodule
`default_nettype wire
`default_nettype none
//
// P = 0 UART0 P = 1 UART1
//
// Assumes no parity, 8 bits per character and
// 1 stop bit.
//
// Gets UART characters from file and serializes them.
//
// If UART0, output file is `UART0_FILE_PATH_RX
// If UART1, output file is `UART1_FILE_PATH_RX
//
module uart_rx_logger #(parameter [0:0] P = 0 ) ( input wire i_clk, output reg o_line = 1'd1 );
integer signed fh;
reg feof;
integer signed wchar;
initial
begin
if ( P == 0 )
fh = $fopen(`UART0_FILE_PATH_RX, "r");
else
fh = $fopen(`UART1_FILE_PATH_RX, "r");
if ( fh == 0 )
begin
$display($time, " - %m :: Error: Failed to open UART input stream. Handle = %d", fh);
$finish;
end
while ( 1 )
begin
wchar = $fgetc(fh);
if ( wchar > 0 )
begin
write_to_uart (wchar);
end
else
begin
@(posedge i_clk);
end
end
end
task write_to_uart ( input integer signed wchar );
begin
repeat(16) @(posedge i_clk) o_line <= 1'd0;
repeat(16) @(posedge i_clk) o_line <= wchar[0];
repeat(16) @(posedge i_clk) o_line <= wchar[1];
repeat(16) @(posedge i_clk) o_line <= wchar[2];
repeat(16) @(posedge i_clk) o_line <= wchar[3];
repeat(16) @(posedge i_clk) o_line <= wchar[4];
repeat(16) @(posedge i_clk) o_line <= wchar[5];
repeat(16) @(posedge i_clk) o_line <= wchar[6];
repeat(16) @(posedge i_clk) o_line <= wchar[7];
// Wait 1K clocks between input bytes.
repeat(1024) @(posedge i_clk) o_line <= 1'd1;
end
endtask
endmodule // uart_rx_logger
`default_nettype wire
`default_nettype none
//
// P = 0 UART0 P = 1 UART1
//
// Assumes no parity, 8 bits per character and
// 1 stop bit.
// Writes UART output to a file.
//
// If UART0, output file is `UART0_FILE_PATH
// If UART1, output file is `UART1_FILE_PATH
//
module uart_tx_dumper #(parameter [0:0] P = 0 ) ( input wire i_clk, input wire i_line );
localparam UART_WAIT_FOR_START = 0;
localparam UART_RX = 1;
localparam UART_STOP_BIT = 2;
integer uart_state = UART_WAIT_FOR_START;
reg uart_sof = 1'd0;
reg uart_eof = 1'd0;
integer uart_ctr = 0;
integer uart_bit_ctr = 1'dx;
reg [7:0] uart_sr = 0;
reg [7:0] UART_SR = 0;
reg UART_SR_DAV = 0;
wire uart;
integer signed fh;
assign uart = i_line;
always @ ( posedge i_clk )
begin
UART_SR_DAV = 1'd0;
uart_sof = 1'd0;
uart_eof = 1'd0;
case ( uart_state )
UART_WAIT_FOR_START:
begin
if ( !uart )
begin
uart_ctr = uart_ctr + 1;
uart_sof = 1'd1;
end
if ( !uart && uart_ctr == 16 )
begin
uart_sof = 1'd0;
uart_state = UART_RX;
uart_ctr = 0;
uart_bit_ctr = 0;
end
end
UART_RX:
begin
uart_ctr++;
if ( uart_ctr == 2 )
uart_sr = uart_sr >> 1 | uart << 7;
if ( uart_ctr == 16 )
begin
uart_bit_ctr++;
uart_ctr = 0;
if ( uart_bit_ctr == 8 )
begin
uart_state = UART_STOP_BIT;
UART_SR = uart_sr;
UART_SR_DAV = 1'd1;
uart_ctr = 0;
uart_bit_ctr = 0;
end
end
end
UART_STOP_BIT:
begin
uart_ctr++;
if ( uart && uart_ctr == 16 ) // Stop bit.
begin
uart_state = UART_WAIT_FOR_START;
uart_bit_ctr = 0;
uart_ctr = 0;
end
end
endcase
end
initial
begin
if ( P == 0 )
fh = $fopen(`UART0_FILE_PATH_TX, "w");
else
fh = $fopen(`UART1_FILE_PATH_TX, "w");
if ( fh == -1 )
begin
$display($time, " - %m :: Error: Failed to open UART output log.");
$finish;
end
end
always @ (negedge i_clk)
begin
if ( UART_SR_DAV )
begin
$display("UART Wrote %c", UART_SR);
$fwrite(fh, "%c", UART_SR);
$fflush(fh);
end
end
endmodule // uart_tx_dumper
`default_nettype wire
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016 Revanth Kamaraj. --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
// --
// A simple interrupt controller. --
// --
// Registers: --
// 0x0 - INT_STATUS - Interrupt status as reported by peripherals (sticky). --
// 0x4 - INT_MASK - Interrupt mask - setting a bit to 1 masks the interrupt --
// 0x8 - INT_CLEAR - Write 1 to a particular bit to clear the interrupt --
// status. --
//------------------------------------------------------------------------------
`default_nettype none
module vic #(
parameter [31:0] SOURCES = 32'd4,
parameter [31:0] INTERRUPT_PENDING_REGISTER = 32'h0,
parameter [31:0] INTERRUPT_MASK_REGISTER = 32'h4,
parameter [31:0] INTERRUPT_CLEAR_REGISTER = 32'h8
) (
// Clock and reset.
input wire i_clk,
input wire i_rst,
// Wishbone interface.
input wire [31:0] i_wb_dat,
input wire [3:0] i_wb_adr,
input wire i_wb_stb,
input wire i_wb_cyc,
input wire i_wb_wen,
input wire [3:0] i_wb_sel,
output reg [31:0] o_wb_dat,
output reg o_wb_ack,
// Interrupt sources in. Concatenate all
// sources together.
input wire [SOURCES-1:0] i_irq,
// Interrupt output. Level interrupt.
output reg o_irq
);
`ifndef ZAP_SOC_VIC
`define ZAP_SOC_VIC
`define INT_STATUS INTERRUPT_PENDING_REGISTER
`define INT_MASK INTERRUPT_MASK_REGISTER
`define INT_CLEAR INTERRUPT_CLEAR_REGISTER
`endif
reg [31:0] INT_STATUS;
reg [31:0] INT_MASK;
reg [31:0] wbstate;
// Wishbone states.
localparam WBIDLE = 0;
localparam WBREAD = 1;
localparam WBWRITE = 2;
localparam WBACK = 3;
localparam WBDONE = 4;
// Send out a global interrupt signal.
always @ (posedge i_clk)
begin
o_irq <= | ( INT_STATUS & ~INT_MASK );
end
// Wishbone access FSM
always @ ( posedge i_clk )
begin
if ( i_rst )
begin
wbstate <= WBIDLE;
o_wb_dat <= 0;
o_wb_ack <= 0;
INT_MASK <= 32'hffffffff;
INT_STATUS <= 32'h0;
end
else
begin:blk1
integer i;
// Normally record interrupts. These are sticky bits.
for(i=0;i<SOURCES;i=i+1)
INT_STATUS[i] <= INT_STATUS[i] == 0 ? i_irq[i] : 1'd1;
case(wbstate)
WBIDLE:
begin
o_wb_ack <= 1'd0;
if ( i_wb_stb && i_wb_cyc )
begin
if ( i_wb_wen )
wbstate <= WBWRITE;
else
wbstate <= WBREAD;
end
end
WBWRITE:
begin
case(i_wb_adr)
`INT_MASK: // INT_MASK
begin
$display($time, " - %m :: Writing to INT_MASK register...");
if ( i_wb_sel[0] ) INT_MASK[7:0] <= i_wb_dat >> 0;
if ( i_wb_sel[1] ) INT_MASK[15:8] <= i_wb_dat >> 8;
if ( i_wb_sel[2] ) INT_MASK[23:16] <= i_wb_dat >> 16;
if ( i_wb_sel[3] ) INT_MASK[31:24] <= i_wb_dat >> 24;
end
`INT_CLEAR: // INT_CLEAR
begin: blk22
integer i;
$display($time, " - %m :: Writing to INT_CLEAR register...");
if ( i_wb_sel[0] ) for(i=0; i <=7;i=i+1) if ( i_wb_dat[i] ) INT_STATUS[i] <= 1'd0;
if ( i_wb_sel[1] ) for(i=8; i<=15;i=i+1) if ( i_wb_dat[i] ) INT_STATUS[i] <= 1'd0;
if ( i_wb_sel[2] ) for(i=16;i<=23;i=i+1) if ( i_wb_dat[i] ) INT_STATUS[i] <= 1'd0;
if ( i_wb_sel[3] ) for(i=24;i<=31;i=i+1) if ( i_wb_dat[i] ) INT_STATUS[i] <= 1'd0;
end
default: $display($time, " - %m :: Warning: Attemting to write to illgal register...");
endcase
wbstate <= WBACK;
end
WBREAD:
begin
case(i_wb_adr)
`INT_STATUS: o_wb_dat <= `INT_STATUS;
`INT_MASK: o_wb_dat <= `INT_MASK;
default:
begin
$display($time, " - %m --> Warning: Attempting to read from illegal register. Will return 0...");
o_wb_dat <= 0;
end
endcase
wbstate <= WBACK;
end
WBACK:
begin
o_wb_ack <= 1'd1;
wbstate <= WBDONE;
end
WBDONE:
begin
o_wb_ack <= 1'd0;
wbstate <= WBIDLE;
end
endcase
end
end
endmodule // vic
`default_nettype wire
`default_nettype none
`include "zap_defines.vh"
module zap_test;
// CPU config.
parameter RAM_SIZE = 32768;
parameter DATA_SECTION_TLB_ENTRIES = 4;
parameter DATA_LPAGE_TLB_ENTRIES = 8;
parameter DATA_SPAGE_TLB_ENTRIES = 16;
parameter DATA_FPAGE_TLB_ENTRIES = 32;
parameter DATA_CACHE_SIZE = 1024;
parameter CODE_SECTION_TLB_ENTRIES = 4;
parameter CODE_LPAGE_TLB_ENTRIES = 8;
parameter CODE_SPAGE_TLB_ENTRIES = 16;
parameter CODE_FPAGE_TLB_ENTRIES = 32;
parameter CODE_CACHE_SIZE = 1024;
parameter FIFO_DEPTH = 4;
parameter BP_ENTRIES = 1024;
parameter STORE_BUFFER_DEPTH = 32;
// TB related.
parameter START = 1992;
parameter COUNT = 120;
// Variables
reg i_clk = 1'd0;
reg i_reset = 1'd0;
wire [1:0] uart_in;
wire [1:0] uart_out;
integer i;
reg [3:0] clk_ctr = 4'd0;
integer seed = `SEED;
integer seed_new = `SEED + 1;
// Clock generator.
always #10 i_clk = !i_clk;
wire w_wb_stb;
wire w_wb_cyc;
wire [31:0] w_wb_dat_to_ram;
wire [31:0] w_wb_adr;
wire [3:0] w_wb_sel;
wire w_wb_we;
wire w_wb_ack;
wire [31:0] w_wb_dat_from_ram;
// DUT
chip_top #(
.FIFO_DEPTH(FIFO_DEPTH),
.BP_ENTRIES(BP_ENTRIES),
.STORE_BUFFER_DEPTH(STORE_BUFFER_DEPTH),
.DATA_SECTION_TLB_ENTRIES(DATA_SECTION_TLB_ENTRIES),
.DATA_LPAGE_TLB_ENTRIES(DATA_LPAGE_TLB_ENTRIES),
.DATA_SPAGE_TLB_ENTRIES(DATA_SPAGE_TLB_ENTRIES),
.DATA_FPAGE_TLB_ENTRIES(DATA_FPAGE_TLB_ENTRIES),
.DATA_CACHE_SIZE(DATA_CACHE_SIZE),
.CODE_SECTION_TLB_ENTRIES(CODE_SECTION_TLB_ENTRIES),
.CODE_LPAGE_TLB_ENTRIES(CODE_LPAGE_TLB_ENTRIES),
.CODE_SPAGE_TLB_ENTRIES(CODE_SPAGE_TLB_ENTRIES),
.CODE_FPAGE_TLB_ENTRIES(CODE_FPAGE_TLB_ENTRIES),
.CODE_CACHE_SIZE(CODE_CACHE_SIZE)
) u_chip_top (
.SYS_CLK (i_clk),
.SYS_RST (i_reset),
.UART0_RXD(uart_in[0]),
.UART0_TXD(uart_out[0]),
.UART1_RXD(uart_in[1]),
.UART1_TXD(uart_out[1]),
.I_IRQ (28'd0),
.I_FIQ (1'd0),
.O_WB_STB (w_wb_stb),
.O_WB_CYC (w_wb_cyc),
.O_WB_DAT (w_wb_dat_to_ram),
.O_WB_ADR (w_wb_adr),
.O_WB_SEL (w_wb_sel),
.O_WB_WE (w_wb_we),
.I_WB_ACK (w_wb_ack),
.I_WB_DAT (w_wb_dat_from_ram)
);
// RAM
ram #(.SIZE_IN_BYTES(RAM_SIZE)) u_ram (
.i_clk(i_clk),
.i_wb_stb (w_wb_stb),
.i_wb_cyc (w_wb_cyc),
.i_wb_dat (w_wb_dat_to_ram),
.i_wb_adr (w_wb_adr),
.i_wb_sel (w_wb_sel),
.i_wb_we (w_wb_we),
.o_wb_ack (w_wb_ack),
.o_wb_dat (w_wb_dat_from_ram)
);
// UART 0 dumper.
uart_tx_dumper #(.P(0)) UARTTX0 (
.i_clk (i_clk),
.i_line (uart_out[0])
);
// UART 1 dumper.
uart_tx_dumper #(.P(1)) UARTTX1 (
.i_clk (i_clk),
.i_line (uart_out[1])
);
// UART 0 logger.
uart_rx_logger #(.P(0)) UARTRX0 (
.i_clk (i_clk),
.o_line (uart_in[0])
);
// UART 1 logger.
uart_rx_logger #(.P(1)) UARTRX1 (
.i_clk (i_clk),
.o_line (uart_in[1])
);
// Run for MAX_CLOCK_CYCLES
initial
begin
$display("SEED in decimal = %d", `SEED );
$display("parameter RAM_SIZE = %d", RAM_SIZE );
$display("parameter START = %d", START );
$display("parameter COUNT = %d", COUNT );
$display("parameter FIFO_DEPTH = %d", u_chip_top.FIFO_DEPTH );
$display("parameter DATA_SECTION_TLB_ENTRIES = %d", DATA_SECTION_TLB_ENTRIES ) ;
$display("parameter DATA_LPAGE_TLB_ENTRIES = %d", DATA_LPAGE_TLB_ENTRIES ) ;
$display("parameter DATA_SPAGE_TLB_ENTRIES = %d", DATA_SPAGE_TLB_ENTRIES ) ;
$display("parameter DATA_CACHE_SIZE = %d", DATA_CACHE_SIZE ) ;
$display("parameter CODE_SECTION_TLB_ENTRIES = %d", CODE_SECTION_TLB_ENTRIES ) ;
$display("parameter CODE_LPAGE_TLB_ENTRIES = %d", CODE_LPAGE_TLB_ENTRIES ) ;
$display("parameter CODE_SPAGE_TLB_ENTRIES = %d", CODE_SPAGE_TLB_ENTRIES ) ;
$display("parameter CODE_CACHE_SIZE = %d", CODE_CACHE_SIZE ) ;
$display("parameter STORE_BUFFER_DEPTH = %d", STORE_BUFFER_DEPTH ) ;
`ifdef WAVES
$dumpfile(`VCD_FILE_PATH);
$dumpvars;
`endif
@(posedge i_clk);
i_reset <= 1;
@(posedge i_clk);
i_reset <= 0;
if (`MAX_CLOCK_CYCLES == 0 )
begin
forever @(negedge i_clk);
end
else
begin
repeat(`MAX_CLOCK_CYCLES)
@(negedge i_clk);
end
`include "zap_check.vh"
end
// Bring out registers.
wire [31:0] r0 = `REG_HIER.mem[0];
wire [31:0] r1 = `REG_HIER.mem[1];
wire [31:0] r2 = `REG_HIER.mem[2];
wire [31:0] r3 = `REG_HIER.mem[3];
wire [31:0] r4 = `REG_HIER.mem[4];
wire [31:0] r5 = `REG_HIER.mem[5];
wire [31:0] r6 = `REG_HIER.mem[6];
wire [31:0] r7 = `REG_HIER.mem[7];
wire [31:0] r8 = `REG_HIER.mem[8];
wire [31:0] r9 = `REG_HIER.mem[9];
wire [31:0] r10 = `REG_HIER.mem[10];
wire [31:0] r11 = `REG_HIER.mem[11];
wire [31:0] r12 = `REG_HIER.mem[12];
wire [31:0] r13 = `REG_HIER.mem[13];
wire [31:0] r14 = `REG_HIER.mem[14];
wire [31:0] r15 = `REG_HIER.mem[15];
wire [31:0] r16 = `REG_HIER.mem[16];
wire [31:0] r17 = `REG_HIER.mem[17];
wire [31:0] r18 = `REG_HIER.mem[18];
wire [31:0] r19 = `REG_HIER.mem[19];
wire [31:0] r20 = `REG_HIER.mem[20];
wire [31:0] r21 = `REG_HIER.mem[21];
wire [31:0] r22 = `REG_HIER.mem[22];
wire [31:0] r23 = `REG_HIER.mem[23];
wire [31:0] r24 = `REG_HIER.mem[24];
wire [31:0] r25 = `REG_HIER.mem[25];
wire [31:0] r26 = `REG_HIER.mem[26];
wire [31:0] r27 = `REG_HIER.mem[27];
wire [31:0] r28 = `REG_HIER.mem[28];
wire [31:0] r29 = `REG_HIER.mem[29];
wire [31:0] r30 = `REG_HIER.mem[30];
wire [31:0] r31 = `REG_HIER.mem[31];
wire [31:0] r32 = `REG_HIER.mem[32];
wire [31:0] r33 = `REG_HIER.mem[33];
wire [31:0] r34 = `REG_HIER.mem[34];
wire [31:0] r35 = `REG_HIER.mem[35];
wire [31:0] r36 = `REG_HIER.mem[36];
wire [31:0] r37 = `REG_HIER.mem[37];
wire [31:0] r38 = `REG_HIER.mem[38];
wire [31:0] r39 = `REG_HIER.mem[39];
endmodule // zap_tb
`default_nettype wire
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: lsu_tagdp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module lsu_tagdp( /*AUTOARG*/
// Outputs
so, lsu_misc_rdata_w2, lsu_rd_dtag_parity_g,
// Inputs
rclk, si, se, lsu_va_wtchpt_addr, lsu_va_wtchpt_sel_g, dva_vld_m,
dtag_rdata_w0_m, dtag_rdata_w1_m, dtag_rdata_w2_m,
dtag_rdata_w3_m, lsu_dtag_rsel_m, lsu_local_ldxa_data_g,
lsu_local_ldxa_sel_g, lsu_tlb_rd_data, lsu_local_ldxa_tlbrd_sel_g,
lsu_local_diagnstc_tagrd_sel_g
);
input rclk;
input si;
input se;
output so;
input [47:3] lsu_va_wtchpt_addr ;
input lsu_va_wtchpt_sel_g;
input [3:0] dva_vld_m; // valid array read
input [29:0] dtag_rdata_w0_m; // 29b tag; 1b parity from dtag
input [29:0] dtag_rdata_w1_m; // 29b tag; 1b parity from dtag
input [29:0] dtag_rdata_w2_m; // 29b tag; 1b parity from dtag
input [29:0] dtag_rdata_w3_m; // 29b tag; 1b parity from dtag
input [3:0] lsu_dtag_rsel_m; // select one of the above tag from ??
input [47:0] lsu_local_ldxa_data_g; // from dctl
input lsu_local_ldxa_sel_g; //used to mux ldxa data with 1/4 tags. from ??
input [63:0] lsu_tlb_rd_data; // from tlbdp - used in local ldxa mux
input lsu_local_ldxa_tlbrd_sel_g;
input lsu_local_diagnstc_tagrd_sel_g;
output [63:0] lsu_misc_rdata_w2; // to qdp1
output [3:0] lsu_rd_dtag_parity_g; // parity check on 4 tags. to dctl
wire dtag_rdata_w0_parity_g,
dtag_rdata_w1_parity_g,
dtag_rdata_w2_parity_g,
dtag_rdata_w3_parity_g;
wire [29:0] dtag_rdata_sel_m,
dtag_rdata_sel_g;
wire [3:0] dtag_rdata_w0_8b_parity_m,
dtag_rdata_w1_8b_parity_m,
dtag_rdata_w2_8b_parity_m,
dtag_rdata_w3_8b_parity_m;
wire [3:0] dtag_rdata_w0_8b_parity_g,
dtag_rdata_w1_8b_parity_g,
dtag_rdata_w2_8b_parity_g,
dtag_rdata_w3_8b_parity_g;
wire [63:0] lsu_misc_rdata_g;
wire dtag_vld_sel_m, dtag_vld_sel_g;
wire clk;
assign clk = rclk;
//=================================================================================================
// Select Tag Read data / ldxa data
//=================================================================================================
// select 1 out of 4 tags
mux4ds #(31) dtag_rdata_sel (
.in0 ({dtag_rdata_w0_m[29:0],dva_vld_m[0]}),
.in1 ({dtag_rdata_w1_m[29:0],dva_vld_m[1]}),
.in2 ({dtag_rdata_w2_m[29:0],dva_vld_m[2]}),
.in3 ({dtag_rdata_w3_m[29:0],dva_vld_m[3]}),
.sel0 (lsu_dtag_rsel_m[0]),
.sel1 (lsu_dtag_rsel_m[1]),
.sel2 (lsu_dtag_rsel_m[2]),
.sel3 (lsu_dtag_rsel_m[3]),
.dout ({dtag_rdata_sel_m[29:0],dtag_vld_sel_m})
);
dff_s #(31) dtag_rdata_sel_g_ff (
.din ({dtag_rdata_sel_m[29:0],dtag_vld_sel_m}),
.q ({dtag_rdata_sel_g[29:0],dtag_vld_sel_g}),
.clk (clk),
.se (se), .si (), .so ());
mux4ds #(64) lsu_misc_rdata_sel (
.in0 ({16'h0,lsu_local_ldxa_data_g[47:0]}),
.in1 (lsu_tlb_rd_data[63:0]),
.in2 ({16'h0,lsu_va_wtchpt_addr[47:3],3'b000}),
.in3 ({33'h0,dtag_rdata_sel_g[29:0],dtag_vld_sel_g}),
.sel0 (lsu_local_ldxa_sel_g),
.sel1 (lsu_local_ldxa_tlbrd_sel_g),
.sel2 (lsu_va_wtchpt_sel_g),
.sel3 (lsu_local_diagnstc_tagrd_sel_g),
.dout (lsu_misc_rdata_g[63:0])
);
dff_s #(64) lsu_misc_rdata_w2_ff (
.din (lsu_misc_rdata_g[63:0]),
.q (lsu_misc_rdata_w2[63:0]),
.clk (clk),
.se (se), .si (), .so ());
//=================================================================================================
// Tag Parity Calculation
//=================================================================================================
// flop tag parity bits
dff_s #(4) dtag_rdata_parity_g_ff (
.din ({dtag_rdata_w0_m[29],
dtag_rdata_w1_m[29],
dtag_rdata_w2_m[29],
dtag_rdata_w3_m[29]}),
.q ({dtag_rdata_w0_parity_g,
dtag_rdata_w1_parity_g,
dtag_rdata_w2_parity_g,
dtag_rdata_w3_parity_g}),
.clk (clk),
.se (se), .si (), .so ());
// generate 8bit parity for all ways before g-flop
assign dtag_rdata_w0_8b_parity_m[0] = ^dtag_rdata_w0_m[7:0] ;
assign dtag_rdata_w0_8b_parity_m[1] = ^dtag_rdata_w0_m[15:8] ;
assign dtag_rdata_w0_8b_parity_m[2] = ^dtag_rdata_w0_m[23:16] ;
assign dtag_rdata_w0_8b_parity_m[3] = ^dtag_rdata_w0_m[28:24] ;
assign dtag_rdata_w1_8b_parity_m[0] = ^dtag_rdata_w1_m[7:0] ;
assign dtag_rdata_w1_8b_parity_m[1] = ^dtag_rdata_w1_m[15:8] ;
assign dtag_rdata_w1_8b_parity_m[2] = ^dtag_rdata_w1_m[23:16] ;
assign dtag_rdata_w1_8b_parity_m[3] = ^dtag_rdata_w1_m[28:24] ;
assign dtag_rdata_w2_8b_parity_m[0] = ^dtag_rdata_w2_m[7:0] ;
assign dtag_rdata_w2_8b_parity_m[1] = ^dtag_rdata_w2_m[15:8] ;
assign dtag_rdata_w2_8b_parity_m[2] = ^dtag_rdata_w2_m[23:16] ;
assign dtag_rdata_w2_8b_parity_m[3] = ^dtag_rdata_w2_m[28:24] ;
assign dtag_rdata_w3_8b_parity_m[0] = ^dtag_rdata_w3_m[7:0] ;
assign dtag_rdata_w3_8b_parity_m[1] = ^dtag_rdata_w3_m[15:8] ;
assign dtag_rdata_w3_8b_parity_m[2] = ^dtag_rdata_w3_m[23:16] ;
assign dtag_rdata_w3_8b_parity_m[3] = ^dtag_rdata_w3_m[28:24] ;
// g-flop for 8-bit parity for all 4 ways
dff_s #(4) dtag_rdata_w0_8b_parity_g_ff (
.din (dtag_rdata_w0_8b_parity_m[3:0]),
.q (dtag_rdata_w0_8b_parity_g[3:0]),
.clk (clk),
.se (se), .si (), .so ());
dff_s #(4) dtag_rdata_w1_8b_parity_g_ff (
.din (dtag_rdata_w1_8b_parity_m[3:0]),
.q (dtag_rdata_w1_8b_parity_g[3:0]),
.clk (clk),
.se (se), .si (), .so ());
dff_s #(4) dtag_rdata_w2_8b_parity_g_ff (
.din (dtag_rdata_w2_8b_parity_m[3:0]),
.q (dtag_rdata_w2_8b_parity_g[3:0]),
.clk (clk),
.se (se), .si (), .so ());
dff_s #(4) dtag_rdata_w3_8b_parity_g_ff (
.din (dtag_rdata_w3_8b_parity_m[3:0]),
.q (dtag_rdata_w3_8b_parity_g[3:0]),
.clk (clk),
.se (se), .si (), .so ());
assign lsu_rd_dtag_parity_g[0] = ^({dtag_rdata_w0_8b_parity_g[3:0],dtag_rdata_w0_parity_g});
assign lsu_rd_dtag_parity_g[1] = ^({dtag_rdata_w1_8b_parity_g[3:0],dtag_rdata_w1_parity_g});
assign lsu_rd_dtag_parity_g[2] = ^({dtag_rdata_w2_8b_parity_g[3:0],dtag_rdata_w2_parity_g});
assign lsu_rd_dtag_parity_g[3] = ^({dtag_rdata_w3_8b_parity_g[3:0],dtag_rdata_w3_parity_g});
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_gt_top.v
// Version : 4.1
//----------------------------------------------------------------------------//
//----------------------------------------------------------------------------//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express //
// Filename : pcie3_7x_0_gt_top.v //
// Description : Instantiates the top level of the GT wrapper and also the //
// TX Electrical Idle filter //
// //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
// gt_top.v //
// pcie_tx_elec_idle_filter_7vx.v //
// pipe_clock.v //
// pipe_reset.v //
// qpll_reset.v //
// * Generate GTHE2_CHANNEL for every lane. //
// pipe_user.v //
// pipe_rate.v //
// pipe_sync.v //
// pipe_drp.v //
// pipe_eq.v //
// rxeq_scan.v //
// gt_wrapper.v //
// GTHE2_CHANNEL //
// GTHE2_COMMON //
// * Generate GTHE2_COMMON for every quad. //
// qpll_drp.v //
// qpll_wrapper.v //
//----------------------------------------------------------------------------//
`timescale 1ps / 1ps
module pcie3_7x_0_gt_top #
(
parameter TCQ = 100,
parameter PL_LINK_CAP_MAX_LINK_WIDTH = 8, // 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8
parameter PL_LINK_CAP_MAX_LINK_SPEED = 3, // 1 - Gen 1 , 2 - Gen 2 , 3 - Gen 3
parameter REF_CLK_FREQ = 0, // 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz
// USER_CLK[1/2]_FREQ : 0 = Disable user clock
// : 1 = 31.25 MHz
// : 2 = 62.50 MHz (default)
// : 3 = 125.00 MHz
// : 4 = 250.00 MHz
// : 5 = 500.00 MHz
parameter integer USER_CLK_FREQ = 5,
parameter integer USER_CLK2_FREQ = 4,
parameter PL_SIM_FAST_LINK_TRAINING = "FALSE", // Simulation Speedup
parameter PCIE_EXT_CLK = "FALSE", // Use External Clocking
parameter PCIE_EXT_GT_COMMON = "FALSE", // Use External GT COMMON
parameter EXT_CH_GT_DRP = "FALSE", // PCIe external CH DRP
parameter EXT_QPLL_GT_DRP = "FALSE", // PCIe external QPLL DRP
parameter PCIE_TXBUF_EN = "FALSE",
parameter PCIE_GT_DEVICE = "GTH",
parameter PCIE_CHAN_BOND = 0, // 0 - One Hot, 1 - Daisy Chain, 2 - Binary Tree
parameter PCIE_CHAN_BOND_EN = "FALSE", // Disable Channel bond as Integrated Block perform CB
parameter PCIE_USE_MODE = "1.1",
parameter PCIE_LPM_DFE = "LPM",
parameter TX_MARGIN_FULL_0 = 7'b1001111, // 1000 mV
parameter TX_MARGIN_FULL_1 = 7'b1001110, // 950 mV
parameter TX_MARGIN_FULL_2 = 7'b1001101, // 900 mV
parameter TX_MARGIN_FULL_3 = 7'b1001100, // 850 mV
parameter TX_MARGIN_FULL_4 = 7'b1000011, // 400 mV
parameter TX_MARGIN_LOW_0 = 7'b1000101, // 500 mV
parameter TX_MARGIN_LOW_1 = 7'b1000110 , // 450 mV
parameter TX_MARGIN_LOW_2 = 7'b1000011, // 400 mV
parameter TX_MARGIN_LOW_3 =7'b1000010 , // 350 mV
parameter TX_MARGIN_LOW_4 =7'b1000000 ,
parameter PCIE_LINK_SPEED = 3,
parameter PCIE_ASYNC_EN = "FALSE"
) (
//-----------------------------------------------------------------------------------------------------------------//
// Pipe Per-Link Signals
input wire pipe_tx_rcvr_det,
input wire pipe_tx_reset,
input wire [1:0] pipe_tx_rate,
input wire pipe_tx_deemph,
input wire [2:0] pipe_tx_margin,
input wire pipe_tx_swing,
output wire [5:0] pipe_txeq_fs,
output wire [5:0] pipe_txeq_lf,
input wire [7:0] pipe_rxslide,
output wire [7:0] pipe_rxsync_done,
input wire [5:0] cfg_ltssm_state,
// Pipe Per-Lane Signals - Lane 0
output wire [1:0] pipe_rx0_char_is_k,
output wire [31:0] pipe_rx0_data,
output wire pipe_rx0_valid,
output wire pipe_rx0_chanisaligned,
output wire [2:0] pipe_rx0_status,
output wire pipe_rx0_phy_status,
output wire pipe_rx0_elec_idle,
input wire pipe_rx0_polarity,
input wire pipe_tx0_compliance,
input wire [1:0] pipe_tx0_char_is_k,
input wire [31:0] pipe_tx0_data,
input wire pipe_tx0_elec_idle,
input wire [1:0] pipe_tx0_powerdown,
input wire [1:0] pipe_tx0_eqcontrol,
input wire [3:0] pipe_tx0_eqpreset,
input wire [5:0] pipe_tx0_eqdeemph,
output wire pipe_tx0_eqdone,
output wire [17:0] pipe_tx0_eqcoeff,
input wire [1:0] pipe_rx0_eqcontrol,
input wire [2:0] pipe_rx0_eqpreset,
input wire [5:0] pipe_rx0_eq_lffs,
input wire [3:0] pipe_rx0_eq_txpreset,
output wire [17:0] pipe_rx0_eq_new_txcoeff,
output wire pipe_rx0_eq_lffs_sel,
output wire pipe_rx0_eq_adapt_done,
output wire pipe_rx0_eqdone,
// Pipe Per-Lane Signals - Lane 1
output wire [1:0] pipe_rx1_char_is_k,
output wire [31:0] pipe_rx1_data,
output wire pipe_rx1_valid,
output wire pipe_rx1_chanisaligned,
output wire [2:0] pipe_rx1_status,
output wire pipe_rx1_phy_status,
output wire pipe_rx1_elec_idle,
input wire pipe_rx1_polarity,
input wire pipe_tx1_compliance,
input wire [1:0] pipe_tx1_char_is_k,
input wire [31:0] pipe_tx1_data,
input wire pipe_tx1_elec_idle,
input wire [1:0] pipe_tx1_powerdown,
input wire [1:0] pipe_tx1_eqcontrol,
input wire [3:0] pipe_tx1_eqpreset,
input wire [5:0] pipe_tx1_eqdeemph,
output wire pipe_tx1_eqdone,
output wire [17:0] pipe_tx1_eqcoeff,
input wire [1:0] pipe_rx1_eqcontrol,
input wire [2:0] pipe_rx1_eqpreset,
input wire [5:0] pipe_rx1_eq_lffs,
input wire [3:0] pipe_rx1_eq_txpreset,
output wire [17:0] pipe_rx1_eq_new_txcoeff,
output wire pipe_rx1_eq_lffs_sel,
output wire pipe_rx1_eq_adapt_done,
output wire pipe_rx1_eqdone,
// Pipe Per-Lane Signals - Lane 2
output wire [1:0] pipe_rx2_char_is_k,
output wire [31:0] pipe_rx2_data,
output wire pipe_rx2_valid,
output wire pipe_rx2_chanisaligned,
output wire [2:0] pipe_rx2_status,
output wire pipe_rx2_phy_status,
output wire pipe_rx2_elec_idle,
input wire pipe_rx2_polarity,
input wire pipe_tx2_compliance,
input wire [1:0] pipe_tx2_char_is_k,
input wire [31:0] pipe_tx2_data,
input wire pipe_tx2_elec_idle,
input wire [1:0] pipe_tx2_powerdown,
input wire [1:0] pipe_tx2_eqcontrol,
input wire [3:0] pipe_tx2_eqpreset,
input wire [5:0] pipe_tx2_eqdeemph,
output wire pipe_tx2_eqdone,
output wire [17:0] pipe_tx2_eqcoeff,
input wire [1:0] pipe_rx2_eqcontrol,
input wire [2:0] pipe_rx2_eqpreset,
input wire [5:0] pipe_rx2_eq_lffs,
input wire [3:0] pipe_rx2_eq_txpreset,
output wire [17:0] pipe_rx2_eq_new_txcoeff,
output wire pipe_rx2_eq_lffs_sel,
output wire pipe_rx2_eq_adapt_done,
output wire pipe_rx2_eqdone,
// Pipe Per-Lane Signals - Lane 3
output wire [1:0] pipe_rx3_char_is_k,
output wire [31:0] pipe_rx3_data,
output wire pipe_rx3_valid,
output wire pipe_rx3_chanisaligned,
output wire [2:0] pipe_rx3_status,
output wire pipe_rx3_phy_status,
output wire pipe_rx3_elec_idle,
input wire pipe_rx3_polarity,
input wire pipe_tx3_compliance,
input wire [1:0] pipe_tx3_char_is_k,
input wire [31:0] pipe_tx3_data,
input wire pipe_tx3_elec_idle,
input wire [1:0] pipe_tx3_powerdown,
input wire [1:0] pipe_tx3_eqcontrol,
input wire [3:0] pipe_tx3_eqpreset,
input wire [5:0] pipe_tx3_eqdeemph,
output wire pipe_tx3_eqdone,
output wire [17:0] pipe_tx3_eqcoeff,
input wire [1:0] pipe_rx3_eqcontrol,
input wire [2:0] pipe_rx3_eqpreset,
input wire [5:0] pipe_rx3_eq_lffs,
input wire [3:0] pipe_rx3_eq_txpreset,
output wire [17:0] pipe_rx3_eq_new_txcoeff,
output wire pipe_rx3_eq_lffs_sel,
output wire pipe_rx3_eq_adapt_done,
output wire pipe_rx3_eqdone,
// Pipe Per-Lane Signals - Lane 4
output wire [1:0] pipe_rx4_char_is_k,
output wire [31:0] pipe_rx4_data,
output wire pipe_rx4_valid,
output wire pipe_rx4_chanisaligned,
output wire [2:0] pipe_rx4_status,
output wire pipe_rx4_phy_status,
output wire pipe_rx4_elec_idle,
input wire pipe_rx4_polarity,
input wire pipe_tx4_compliance,
input wire [1:0] pipe_tx4_char_is_k,
input wire [31:0] pipe_tx4_data,
input wire pipe_tx4_elec_idle,
input wire [1:0] pipe_tx4_powerdown,
input wire [1:0] pipe_tx4_eqcontrol,
input wire [3:0] pipe_tx4_eqpreset,
input wire [5:0] pipe_tx4_eqdeemph,
output wire pipe_tx4_eqdone,
output wire [17:0] pipe_tx4_eqcoeff,
input wire [1:0] pipe_rx4_eqcontrol,
input wire [2:0] pipe_rx4_eqpreset,
input wire [5:0] pipe_rx4_eq_lffs,
input wire [3:0] pipe_rx4_eq_txpreset,
output wire [17:0] pipe_rx4_eq_new_txcoeff,
output wire pipe_rx4_eq_lffs_sel,
output wire pipe_rx4_eq_adapt_done,
output wire pipe_rx4_eqdone,
// Pipe Per-Lane Signals - Lane 5
output wire [1:0] pipe_rx5_char_is_k,
output wire [31:0] pipe_rx5_data,
output wire pipe_rx5_valid,
output wire pipe_rx5_chanisaligned,
output wire [2:0] pipe_rx5_status,
output wire pipe_rx5_phy_status,
output wire pipe_rx5_elec_idle,
input wire pipe_rx5_polarity,
input wire pipe_tx5_compliance,
input wire [1:0] pipe_tx5_char_is_k,
input wire [31:0] pipe_tx5_data,
input wire pipe_tx5_elec_idle,
input wire [1:0] pipe_tx5_powerdown,
input wire [1:0] pipe_tx5_eqcontrol,
input wire [3:0] pipe_tx5_eqpreset,
input wire [5:0] pipe_tx5_eqdeemph,
output wire pipe_tx5_eqdone,
output wire [17:0] pipe_tx5_eqcoeff,
input wire [1:0] pipe_rx5_eqcontrol,
input wire [2:0] pipe_rx5_eqpreset,
input wire [5:0] pipe_rx5_eq_lffs,
input wire [3:0] pipe_rx5_eq_txpreset,
output wire [17:0] pipe_rx5_eq_new_txcoeff,
output wire pipe_rx5_eq_lffs_sel,
output wire pipe_rx5_eq_adapt_done,
output wire pipe_rx5_eqdone,
// Pipe Per-Lane Signals - Lane 6
output wire [1:0] pipe_rx6_char_is_k,
output wire [31:0] pipe_rx6_data,
output wire pipe_rx6_valid,
output wire pipe_rx6_chanisaligned,
output wire [2:0] pipe_rx6_status,
output wire pipe_rx6_phy_status,
output wire pipe_rx6_elec_idle,
input wire pipe_rx6_polarity,
input wire pipe_tx6_compliance,
input wire [1:0] pipe_tx6_char_is_k,
input wire [31:0] pipe_tx6_data,
input wire pipe_tx6_elec_idle,
input wire [1:0] pipe_tx6_powerdown,
input wire [1:0] pipe_tx6_eqcontrol,
input wire [3:0] pipe_tx6_eqpreset,
input wire [5:0] pipe_tx6_eqdeemph,
output wire pipe_tx6_eqdone,
output wire [17:0] pipe_tx6_eqcoeff,
input wire [1:0] pipe_rx6_eqcontrol,
input wire [2:0] pipe_rx6_eqpreset,
input wire [5:0] pipe_rx6_eq_lffs,
input wire [3:0] pipe_rx6_eq_txpreset,
output wire [17:0] pipe_rx6_eq_new_txcoeff,
output wire pipe_rx6_eq_lffs_sel,
output wire pipe_rx6_eq_adapt_done,
output wire pipe_rx6_eqdone,
// Pipe Per-Lane Signals - Lane 7
output wire [1:0] pipe_rx7_char_is_k,
output wire [31:0] pipe_rx7_data,
output wire pipe_rx7_valid,
output wire pipe_rx7_chanisaligned,
output wire [2:0] pipe_rx7_status,
output wire pipe_rx7_phy_status,
output wire pipe_rx7_elec_idle,
input wire pipe_rx7_polarity,
input wire pipe_tx7_compliance,
input wire [1:0] pipe_tx7_char_is_k,
input wire [31:0] pipe_tx7_data,
input wire pipe_tx7_elec_idle,
input wire [1:0] pipe_tx7_powerdown,
input wire [1:0] pipe_tx7_eqcontrol,
input wire [3:0] pipe_tx7_eqpreset,
input wire [5:0] pipe_tx7_eqdeemph,
output wire pipe_tx7_eqdone,
output wire [17:0] pipe_tx7_eqcoeff,
input wire [1:0] pipe_rx7_eqcontrol,
input wire [2:0] pipe_rx7_eqpreset,
input wire [5:0] pipe_rx7_eq_lffs,
input wire [3:0] pipe_rx7_eq_txpreset,
output wire [17:0] pipe_rx7_eq_new_txcoeff,
output wire pipe_rx7_eq_lffs_sel,
output wire pipe_rx7_eq_adapt_done,
output wire pipe_rx7_eqdone,
// Manual PCIe Equalization Control
input [(PL_LINK_CAP_MAX_LINK_WIDTH-1):0] pipe_rxeq_user_en,
input [(PL_LINK_CAP_MAX_LINK_WIDTH*18)-1:0] pipe_rxeq_user_txcoeff,
input [(PL_LINK_CAP_MAX_LINK_WIDTH-1):0] pipe_rxeq_user_mode,
// PCIe DRP (PCIe DRP) Interface
input drp_rdy,
input [15:0] drp_do,
output drp_clk,
output drp_en,
output drp_we,
output [10:0] drp_addr,
output [15:0] drp_di,
// PCI Express signals
output wire [ (PL_LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_txn,
output wire [ (PL_LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_txp,
input wire [ (PL_LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_rxn,
input wire [ (PL_LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_rxp,
//---------- PIPE Clock & Reset Ports ------------------
input wire pipe_clk, // Reference clock
input wire sys_rst_n, // PCLK | PCLK
output wire rec_clk, // Recovered Clock
output wire pipe_pclk, // Drives [TX/RX]USRCLK in Gen1/Gen2
output wire core_clk,
output wire user_clk,
output wire phy_rdy,
output wire mmcm_lock,
input pipe_mmcm_rst_n,
//-----------TRANSCEIVER DEBUG--------------------------------
output [4:0] PIPE_RST_FSM,
output [11:0] PIPE_QRST_FSM,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*5)-1:0] PIPE_RATE_FSM,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*6)-1:0] PIPE_SYNC_FSM_TX,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*7)-1:0] PIPE_SYNC_FSM_RX,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*7)-1:0] PIPE_DRP_FSM,
output PIPE_RST_IDLE,
output PIPE_QRST_IDLE,
output PIPE_RATE_IDLE,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_EYESCANDATAERROR,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*3)-1:0] PIPE_RXSTATUS,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*15)-1:0] PIPE_DMONITOROUT,
//---------- Debug Ports -------------------------------
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] PIPE_CPLL_LOCK,
output [(PL_LINK_CAP_MAX_LINK_WIDTH-1)>>2:0] PIPE_QPLL_LOCK,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] PIPE_RXPMARESETDONE,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*3)-1:0] PIPE_RXBUFSTATUS,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] PIPE_TXPHALIGNDONE,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] PIPE_TXPHINITDONE,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] PIPE_TXDLYSRESETDONE,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] PIPE_RXPHALIGNDONE,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] PIPE_RXDLYSRESETDONE,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] PIPE_RXSYNCDONE,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*8)-1:0] PIPE_RXDISPERR,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*8)-1:0] PIPE_RXNOTINTABLE,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] PIPE_RXCOMMADET,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_DEBUG_0,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_DEBUG_1,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_DEBUG_2,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_DEBUG_3,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_DEBUG_4,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_DEBUG_5,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_DEBUG_6,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_DEBUG_7,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_DEBUG_8,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_DEBUG_9,
output [31:0] PIPE_DEBUG,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_JTAG_RDY,
input [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_TXINHIBIT,
input [(PL_LINK_CAP_MAX_LINK_WIDTH*16)-1:0] PIPE_PCSRSVDIN,
input [ 2:0] PIPE_TXPRBSSEL,
input [ 2:0] PIPE_RXPRBSSEL,
input PIPE_TXPRBSFORCEERR,
input PIPE_RXPRBSCNTRESET,
input [ 2:0] PIPE_LOOPBACK,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_RXPRBSERR,
//-----------Channel DRP----------------------------------------
output ext_ch_gt_drpclk,
input [(PL_LINK_CAP_MAX_LINK_WIDTH*9)-1:0] ext_ch_gt_drpaddr,
input [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drpen,
input [(PL_LINK_CAP_MAX_LINK_WIDTH*16)-1:0]ext_ch_gt_drpdi,
input [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drpwe,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*16)-1:0]ext_ch_gt_drpdo,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drprdy,
//----------- Shared Logic Internal--------------------------------------
output INT_PCLK_OUT_SLAVE, // PCLK | PCLK
output INT_RXUSRCLK_OUT, // RXUSERCLK
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] INT_RXOUTCLK_OUT, // RX recovered clock
output INT_DCLK_OUT, // DCLK | DCLK
output INT_USERCLK1_OUT, // Optional user clock
output INT_USERCLK2_OUT, // Optional user clock
output INT_OOBCLK_OUT, // OOB | OOB
output [1:0] INT_QPLLLOCK_OUT,
output [1:0] INT_QPLLOUTCLK_OUT,
output [1:0] INT_QPLLOUTREFCLK_OUT,
input [(PL_LINK_CAP_MAX_LINK_WIDTH-1):0] INT_PCLK_SEL_SLAVE,
// Shared Logic External
//---------- External GT COMMON Ports ----------------------
input [11:0] qpll_drp_crscode,
input [17:0] qpll_drp_fsm,
input [1:0] qpll_drp_done,
input [1:0] qpll_drp_reset,
input [1:0] qpll_qplllock,
input [1:0] qpll_qplloutclk,
input [1:0] qpll_qplloutrefclk,
output qpll_qplld,
output [1:0] qpll_qpllreset,
output qpll_drp_clk,
output qpll_drp_rst_n,
output qpll_drp_ovrd,
output qpll_drp_gen3,
output qpll_drp_start,
//---------- External Clock Ports ----------------------
input PIPE_PCLK_IN, // PCLK | PCLK
input PIPE_RXUSRCLK_IN, // RXUSERCLK
input [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_RXOUTCLK_IN, // RX recovered clock
input PIPE_DCLK_IN, // DCLK | DCLK
input PIPE_USERCLK1_IN, // Optional user clock
input PIPE_USERCLK2_IN, // Optional user clock
input PIPE_OOBCLK_IN, // OOB | OOB
input PIPE_MMCM_LOCK_IN, // Async | Async
output PIPE_TXOUTCLK_OUT, // PCLK | PCLK
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_RXOUTCLK_OUT, // RX recovered clock (for debug only)
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_PCLK_SEL_OUT, // PCLK | PCLK
output PIPE_GEN3_OUT, // PCLK | PCLK
input [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] CPLLPD,
input [(PL_LINK_CAP_MAX_LINK_WIDTH*2)-1:0] TXPD,
input [(PL_LINK_CAP_MAX_LINK_WIDTH*2)-1:0] RXPD,
input [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] TXPDELECIDLEMODE,
input [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] TXDETECTRX,
input [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] TXELECIDLE,
input [(PL_LINK_CAP_MAX_LINK_WIDTH-1)>>2:0] QPLLPD,
input POWERDOWN
);
wire [31:0] gt_rx_data_k_wire;
wire [255:0] gt_rx_data_wire;
wire [7:0] gt_rx_valid_wire;
wire [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] gt_rxchanisaligned_wire;
wire [23:0] gt_rx_status_wire;
wire [7:0] gt_rx_phy_status_wire;
wire [7:0] gt_rx_elec_idle_wire;
wire [7:0] gt_rx_polarity;
wire [31:0] gt_tx_data_k;
wire [255:0] gt_tx_data;
wire [7:0] gt_tx_elec_idle;
wire [7:0] gt_tx_compliance;
wire [15:0] gt_power_down;
wire [15:0] gt_tx_eq_control;
wire [31:0] gt_tx_eq_preset;
wire [47:0] gt_tx_eq_deemph;
wire [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] gt_tx_eq_done;
wire [15:0] gt_rx_eq_control;
wire [23:0] gt_rx_eq_preset;
wire [47:0] gt_rx_eq_lffs;
wire [31:0] gt_rx_eq_txpreset;
wire [143:0] gt_rx_eq_new_txcoeff;
wire [143:0] gt_tx_eq_coeff;
wire [7:0] gt_rx_eq_lffs_sel;
wire [7:0] gt_rx_eq_adapt_done;
wire [7:0] gt_rx_eq_done;
wire gt_tx_detect_rx_loopback;
wire [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_phystatus_rst;
wire clock_locked;
wire phy_rdy_int;
reg [1:0] reg_clock_locked;
reg [1:0] reg_phy_rdy;
wire [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_rxsync_done_w;
assign pipe_rxsync_done = {{(8-PL_LINK_CAP_MAX_LINK_WIDTH){1'b0}},pipe_rxsync_done_w};
localparam PCIE_SIM_SPEEDUP = PL_SIM_FAST_LINK_TRAINING;
//---------- PIPE wrapper Module -------------------------------------------------
pcie3_7x_0_pipe_wrapper #(
.PCIE_SIM_MODE ( PL_SIM_FAST_LINK_TRAINING ),
.PCIE_SIM_SPEEDUP ( PCIE_SIM_SPEEDUP ),
.PCIE_AUX_CDR_GEN3_EN ( "TRUE" ),
.PCIE_ASYNC_EN ( PCIE_ASYNC_EN ),
.PCIE_EXT_CLK ( PCIE_EXT_CLK ),
.PCIE_EXT_GT_COMMON ( PCIE_EXT_GT_COMMON ),
.PCIE_TXBUF_EN ( PCIE_TXBUF_EN ),
.PCIE_GT_DEVICE ( PCIE_GT_DEVICE ),
.PCIE_CHAN_BOND ( PCIE_CHAN_BOND ),
.PCIE_CHAN_BOND_EN ( PCIE_CHAN_BOND_EN ),
.PCIE_USE_MODE ( PCIE_USE_MODE ),
.PCIE_LPM_DFE ( PCIE_LPM_DFE ),
.PCIE_LINK_SPEED ( PCIE_LINK_SPEED ),
.PCIE_LANE ( PL_LINK_CAP_MAX_LINK_WIDTH ),
.PCIE_REFCLK_FREQ ( REF_CLK_FREQ ),
.TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0), // 1000 mV
.TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1), // 950 mV
.TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2), // 900 mV
.TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3), // 850 mV
.TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4), // 400 mV
.TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0), // 500 mV
.TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1), // 450 mV
.TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2), // 400 mV
.TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3), // 350 mV
.TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4),
.PCIE_USERCLK1_FREQ ( USER_CLK_FREQ ),
.PCIE_USERCLK2_FREQ ( USER_CLK2_FREQ )
) pipe_wrapper_i (
//---------- PIPE Clock & Reset Ports ------------------
.PIPE_CLK ( pipe_clk ),
.PIPE_RESET_N ( sys_rst_n ),
.PIPE_PCLK ( pipe_pclk ),
//---------- PIPE TX Data Ports ------------------------
.PIPE_TXDATA ( gt_tx_data[((32*PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXDATAK ( gt_tx_data_k[((4*PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXP ( pci_exp_txp[((PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXN ( pci_exp_txn[((PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
//---------- PIPE RX Data Ports ------------------------
.PIPE_RXP ( pci_exp_rxp[((PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXN ( pci_exp_rxn[((PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXDATA ( gt_rx_data_wire[((32*PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXDATAK ( gt_rx_data_k_wire[((4*PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
//---------- PIPE Command Ports ------------------------
.PIPE_TXDETECTRX ( gt_tx_detect_rx_loopback ),
.PIPE_TXELECIDLE ( gt_tx_elec_idle[((PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXCOMPLIANCE ( gt_tx_compliance[((PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXPOLARITY ( gt_rx_polarity[((PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_POWERDOWN ( gt_power_down[((2*PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RATE ( pipe_tx_rate ),
//---------- PIPE Electrical Command Ports -------------
.PIPE_TXMARGIN ( pipe_tx_margin ),
.PIPE_TXSWING ( pipe_tx_swing ),
.PIPE_TXDEEMPH ( {PL_LINK_CAP_MAX_LINK_WIDTH{pipe_tx_deemph}}),
.PIPE_TXEQ_CONTROL ( gt_tx_eq_control[((2*PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXEQ_PRESET ( gt_tx_eq_preset[((4*PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXEQ_PRESET_DEFAULT ( {PL_LINK_CAP_MAX_LINK_WIDTH{4'b0}} ), // TX Preset Default when reset lifted
.PIPE_RXEQ_CONTROL ( gt_rx_eq_control[((2*PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXEQ_PRESET ( gt_rx_eq_preset[((3*PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXEQ_LFFS ( gt_rx_eq_lffs[((6*PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXEQ_TXPRESET ( gt_rx_eq_txpreset[((4*PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXEQ_USER_EN ( pipe_rxeq_user_en ), // EQUALIZATION Workaround signals
.PIPE_RXEQ_USER_TXCOEFF ( pipe_rxeq_user_txcoeff ), // EQUALIZATION Workaround signals
.PIPE_RXEQ_USER_MODE ( pipe_rxeq_user_mode ), // EQUALIZATION Workaround signals
.PIPE_TXEQ_FS ( pipe_txeq_fs ),
.PIPE_TXEQ_LF ( pipe_txeq_lf ),
.PIPE_TXEQ_DEEMPH ( gt_tx_eq_deemph[((6*PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXEQ_DONE ( gt_tx_eq_done ),
.PIPE_TXEQ_COEFF ( gt_tx_eq_coeff[((18*PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXEQ_NEW_TXCOEFF ( gt_rx_eq_new_txcoeff[((18*PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXEQ_LFFS_SEL ( gt_rx_eq_lffs_sel[((1*PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXEQ_ADAPT_DONE ( gt_rx_eq_adapt_done[((1*PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXEQ_DONE ( gt_rx_eq_done[((1*PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
//---------- PIPE Status Ports -------------------------
.PIPE_RXVALID ( gt_rx_valid_wire[((PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_PHYSTATUS ( gt_rx_phy_status_wire[((PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_PHYSTATUS_RST ( pipe_phystatus_rst ),
.PIPE_RXELECIDLE ( gt_rx_elec_idle_wire[((PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXSTATUS ( gt_rx_status_wire[((3*PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_EYESCANDATAERROR ( PIPE_EYESCANDATAERROR ),
//---------- PIPE User Ports ---------------------------
.PIPE_MMCM_RST_N (pipe_mmcm_rst_n),
.PIPE_RXSLIDE ( pipe_rxslide[((PL_LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_CPLL_LOCK ( PIPE_CPLL_LOCK ),
.PIPE_QPLL_LOCK ( PIPE_QPLL_LOCK),
.PIPE_PCLK_LOCK ( mmcm_lock ),
.PIPE_RXCDRLOCK ( ),
.PIPE_USERCLK1 ( core_clk ), //500MHz for GEN3
.PIPE_USERCLK2 ( user_clk ),
.PIPE_RXUSRCLK ( rec_clk ),
.PIPE_RXOUTCLK ( ),
.PIPE_TXSYNC_DONE ( ),
.PIPE_RXSYNC_DONE ( ),
.PIPE_GEN3_RDY ( pipe_rxsync_done_w ),
.PIPE_RXCHANISALIGNED ( gt_rxchanisaligned_wire ),
.PIPE_ACTIVE_LANE ( ),
// ----------Shared Logic Internal----------------------
.INT_PCLK_OUT_SLAVE ( INT_PCLK_OUT_SLAVE ),
.INT_RXUSRCLK_OUT ( INT_RXUSRCLK_OUT ),
.INT_RXOUTCLK_OUT ( INT_RXOUTCLK_OUT ),
.INT_DCLK_OUT ( INT_DCLK_OUT ),
.INT_USERCLK1_OUT ( INT_USERCLK1_OUT ),
.INT_USERCLK2_OUT ( INT_USERCLK2_OUT),
.INT_OOBCLK_OUT ( INT_OOBCLK_OUT ),
.INT_PCLK_SEL_SLAVE ( INT_PCLK_SEL_SLAVE ),
.INT_QPLLLOCK_OUT ( INT_QPLLLOCK_OUT ),
.INT_QPLLOUTCLK_OUT ( INT_QPLLOUTCLK_OUT ),
.INT_QPLLOUTREFCLK_OUT ( INT_QPLLOUTREFCLK_OUT ),
// ---------- Shared Logic External----------------------
//---------- External Clock Ports ----------------------
.PIPE_PCLK_IN ( PIPE_PCLK_IN ),
.PIPE_RXUSRCLK_IN ( PIPE_RXUSRCLK_IN ),
.PIPE_RXOUTCLK_IN ( PIPE_RXOUTCLK_IN ),
.PIPE_DCLK_IN ( PIPE_DCLK_IN ),
.PIPE_USERCLK1_IN ( PIPE_USERCLK1_IN ),
.PIPE_USERCLK2_IN ( PIPE_USERCLK2_IN ),
.PIPE_OOBCLK_IN ( PIPE_OOBCLK_IN ),
.PIPE_MMCM_LOCK_IN ( PIPE_MMCM_LOCK_IN ),
.PIPE_TXOUTCLK_OUT ( PIPE_TXOUTCLK_OUT ),
.PIPE_RXOUTCLK_OUT ( PIPE_RXOUTCLK_OUT ),
.PIPE_PCLK_SEL_OUT ( PIPE_PCLK_SEL_OUT ),
.PIPE_GEN3_OUT ( PIPE_GEN3_OUT ),
//---------- External GT COMMON Ports ----------------------
.QPLL_DRP_CRSCODE ( qpll_drp_crscode ),
.QPLL_DRP_FSM ( qpll_drp_fsm ),
.QPLL_DRP_DONE ( qpll_drp_done ),
.QPLL_DRP_RESET ( qpll_drp_reset ),
.QPLL_QPLLLOCK ( qpll_qplllock ),
.QPLL_QPLLOUTCLK ( qpll_qplloutclk ),
.QPLL_QPLLOUTREFCLK ( qpll_qplloutrefclk ),
.QPLL_QPLLPD ( qpll_qplld ),
.QPLL_QPLLRESET ( qpll_qpllreset ),
.QPLL_DRP_CLK ( qpll_drp_clk ),
.QPLL_DRP_RST_N ( qpll_drp_rst_n ),
.QPLL_DRP_OVRD ( qpll_drp_ovrd ),
.QPLL_DRP_GEN3 ( qpll_drp_gen3 ),
.QPLL_DRP_START ( qpll_drp_start ),
//--------TRANSCEIVER DEBUG EOU------------------
.EXT_CH_GT_DRPCLK (ext_ch_gt_drpclk),
.EXT_CH_GT_DRPADDR (ext_ch_gt_drpaddr),
.EXT_CH_GT_DRPEN (ext_ch_gt_drpen),
.EXT_CH_GT_DRPDI (ext_ch_gt_drpdi),
.EXT_CH_GT_DRPWE (ext_ch_gt_drpwe),
.EXT_CH_GT_DRPDO (ext_ch_gt_drpdo),
.EXT_CH_GT_DRPRDY (ext_ch_gt_drprdy),
//---------- TRANSCEIVER DEBUG -----------------------
.PIPE_TXPRBSSEL ( PIPE_TXPRBSSEL ),
.PIPE_RXPRBSSEL ( PIPE_RXPRBSSEL ),
.PIPE_TXPRBSFORCEERR ( PIPE_TXPRBSFORCEERR ),
.PIPE_RXPRBSCNTRESET ( PIPE_RXPRBSCNTRESET ),
.PIPE_LOOPBACK ( PIPE_LOOPBACK),
.PIPE_RXPRBSERR ( PIPE_RXPRBSERR),
.PIPE_TXINHIBIT ( PIPE_TXINHIBIT),
.PIPE_PCSRSVDIN ( PIPE_PCSRSVDIN),
.PIPE_RST_FSM (PIPE_RST_FSM),
.PIPE_QRST_FSM (PIPE_QRST_FSM),
.PIPE_RATE_FSM (PIPE_RATE_FSM ),
.PIPE_SYNC_FSM_TX (PIPE_SYNC_FSM_TX ),
.PIPE_SYNC_FSM_RX (PIPE_SYNC_FSM_RX ),
.PIPE_DRP_FSM (PIPE_DRP_FSM ),
.PIPE_RST_IDLE (PIPE_RST_IDLE ),
.PIPE_QRST_IDLE (PIPE_QRST_IDLE ),
.PIPE_RATE_IDLE (PIPE_RATE_IDLE ),
//---------- JTAG Ports --------------------------------
.PIPE_JTAG_EN ( 1'b0 ),
.PIPE_JTAG_RDY (PIPE_JTAG_RDY ),
//---------- Debug Ports -------------------------------
.PIPE_RXPMARESETDONE ( PIPE_RXPMARESETDONE ),
.PIPE_RXBUFSTATUS ( PIPE_RXBUFSTATUS ),
.PIPE_TXPHALIGNDONE ( PIPE_TXPHALIGNDONE ),
.PIPE_TXPHINITDONE ( PIPE_TXPHINITDONE ),
.PIPE_TXDLYSRESETDONE ( PIPE_TXDLYSRESETDONE),
.PIPE_RXPHALIGNDONE ( PIPE_RXPHALIGNDONE ),
.PIPE_RXDLYSRESETDONE ( PIPE_RXDLYSRESETDONE),
.PIPE_RXSYNCDONE ( PIPE_RXSYNCDONE ),
.PIPE_RXDISPERR ( PIPE_RXDISPERR ),
.PIPE_RXNOTINTABLE ( PIPE_RXNOTINTABLE ),
.PIPE_RXCOMMADET ( PIPE_RXCOMMADET ),
.PIPE_DEBUG_0 (PIPE_DEBUG_0 ),
.PIPE_DEBUG_1 (PIPE_DEBUG_1 ),
.PIPE_DEBUG_2 (PIPE_DEBUG_2 ),
.PIPE_DEBUG_3 (PIPE_DEBUG_3 ),
.PIPE_DEBUG_4 (PIPE_DEBUG_4 ),
.PIPE_DEBUG_5 (PIPE_DEBUG_5 ),
.PIPE_DEBUG_6 (PIPE_DEBUG_6 ),
.PIPE_DEBUG_7 (PIPE_DEBUG_7 ),
.PIPE_DEBUG_8 (PIPE_DEBUG_8 ),
.PIPE_DEBUG_9 (PIPE_DEBUG_9 ),
.PIPE_DEBUG (PIPE_DEBUG),
.PIPE_RXEQ_CONVERGE ( ),
.PIPE_DMONITOROUT ( PIPE_DMONITOROUT ),
.PIPE_QDRP_FSM(),
.PIPE_RXEQ_FSM(),
.PIPE_TXEQ_FSM(),
.INT_MMCM_LOCK_OUT(),
.CPLLPD (CPLLPD),
.TXPD (TXPD),
.RXPD (RXPD),
.TXPDELECIDLEMODE (TXPDELECIDLEMODE),
.TXDETECTRX (TXDETECTRX),
.TXELECIDLE (TXELECIDLE),
.QPLLPD (QPLLPD),
.POWERDOWN (POWERDOWN)
);
assign PIPE_RXSTATUS = gt_rx_status_wire[((3*PL_LINK_CAP_MAX_LINK_WIDTH)-1):0];
// Concatenate/Deconcatenate busses to generate correct GT wrapper and PCIe Block connectivity
assign pipe_rx0_phy_status = gt_rx_phy_status_wire[0] ;
assign pipe_rx1_phy_status = (PL_LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_phy_status_wire[1] : 1'b0;
assign pipe_rx2_phy_status = (PL_LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_phy_status_wire[2] : 1'b0;
assign pipe_rx3_phy_status = (PL_LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_phy_status_wire[3] : 1'b0;
assign pipe_rx4_phy_status = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[4] : 1'b0;
assign pipe_rx5_phy_status = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[5] : 1'b0;
assign pipe_rx6_phy_status = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[6] : 1'b0;
assign pipe_rx7_phy_status = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[7] : 1'b0;
assign {pipe_rx7_chanisaligned,pipe_rx6_chanisaligned,pipe_rx5_chanisaligned,pipe_rx4_chanisaligned,pipe_rx3_chanisaligned,pipe_rx2_chanisaligned,pipe_rx1_chanisaligned,pipe_rx0_chanisaligned} = {{(8-PL_LINK_CAP_MAX_LINK_WIDTH){1'b0}},gt_rxchanisaligned_wire};
assign pipe_rx0_char_is_k = {gt_rx_data_k_wire[1], gt_rx_data_k_wire[0]};
assign pipe_rx1_char_is_k = (PL_LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? {gt_rx_data_k_wire[5], gt_rx_data_k_wire[4]} : 2'b0;
assign pipe_rx2_char_is_k = (PL_LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? {gt_rx_data_k_wire[9], gt_rx_data_k_wire[8]} : 2'b0;
assign pipe_rx3_char_is_k = (PL_LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? {gt_rx_data_k_wire[13], gt_rx_data_k_wire[12]} : 2'b0;
assign pipe_rx4_char_is_k = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_k_wire[17], gt_rx_data_k_wire[16]} : 2'b0;
assign pipe_rx5_char_is_k = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_k_wire[21], gt_rx_data_k_wire[20]} : 2'b0;
assign pipe_rx6_char_is_k = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_k_wire[25], gt_rx_data_k_wire[24]} : 2'b0;
assign pipe_rx7_char_is_k = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_k_wire[29], gt_rx_data_k_wire[28]} : 2'b0;
assign pipe_rx0_data = {gt_rx_data_wire[31: 0]};
assign pipe_rx1_data = (PL_LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_data_wire[63:32] : 32'h0;
assign pipe_rx2_data = (PL_LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_data_wire[95:64] : 32'h0;
assign pipe_rx3_data = (PL_LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_data_wire[127:96] : 32'h0;
assign pipe_rx4_data = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_data_wire[159:128] : 32'h0;
assign pipe_rx5_data = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_data_wire[191:160] : 32'h0;
assign pipe_rx6_data = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_data_wire[223:192] : 32'h0;
assign pipe_rx7_data = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_data_wire[255:224] : 32'h0;
assign pipe_rx0_elec_idle = gt_rx_elec_idle_wire[0]; // workaround pcie_tx_elec_idle_filter
assign pipe_rx1_elec_idle = (PL_LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_elec_idle_wire[1] : 1'b1;
assign pipe_rx2_elec_idle = (PL_LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_elec_idle_wire[2] : 1'b1;
assign pipe_rx3_elec_idle = (PL_LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_elec_idle_wire[3] : 1'b1;
assign pipe_rx4_elec_idle = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[4] : 1'b1;
assign pipe_rx5_elec_idle = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[5] : 1'b1;
assign pipe_rx6_elec_idle = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[6] : 1'b1;
assign pipe_rx7_elec_idle = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[7] : 1'b1;
assign pipe_rx0_status = gt_rx_status_wire[ 2: 0];
assign pipe_rx1_status = (PL_LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_status_wire[ 5: 3] : 3'b0;
assign pipe_rx2_status = (PL_LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_status_wire[ 8: 6] : 3'b0;
assign pipe_rx3_status = (PL_LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_status_wire[11: 9] : 3'b0;
assign pipe_rx4_status = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[14:12] : 3'b0;
assign pipe_rx5_status = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[17:15] : 3'b0;
assign pipe_rx6_status = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[20:18] : 3'b0;
assign pipe_rx7_status = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[23:21] : 3'b0;
assign pipe_rx0_valid = gt_rx_valid_wire[0];
assign pipe_rx1_valid = (PL_LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_valid_wire[1] : 1'b0;
assign pipe_rx2_valid = (PL_LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_valid_wire[2] : 1'b0;
assign pipe_rx3_valid = (PL_LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_valid_wire[3] : 1'b0;
assign pipe_rx4_valid = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[4] : 1'b0;
assign pipe_rx5_valid = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[5] : 1'b0;
assign pipe_rx6_valid = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[6] : 1'b0;
assign pipe_rx7_valid = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[7] : 1'b0;
assign gt_rx_polarity[0] = pipe_rx0_polarity;
assign gt_rx_polarity[1] = pipe_rx1_polarity;
assign gt_rx_polarity[2] = pipe_rx2_polarity;
assign gt_rx_polarity[3] = pipe_rx3_polarity;
assign gt_rx_polarity[4] = pipe_rx4_polarity;
assign gt_rx_polarity[5] = pipe_rx5_polarity;
assign gt_rx_polarity[6] = pipe_rx6_polarity;
assign gt_rx_polarity[7] = pipe_rx7_polarity;
assign gt_power_down[ 1: 0] = pipe_tx0_powerdown;
assign gt_power_down[ 3: 2] = pipe_tx1_powerdown;
assign gt_power_down[ 5: 4] = pipe_tx2_powerdown;
assign gt_power_down[ 7: 6] = pipe_tx3_powerdown;
assign gt_power_down[ 9: 8] = pipe_tx4_powerdown;
assign gt_power_down[11:10] = pipe_tx5_powerdown;
assign gt_power_down[13:12] = pipe_tx6_powerdown;
assign gt_power_down[15:14] = pipe_tx7_powerdown;
// Removed gt_tx_char_disp_mode = pipe_tx_compliance_q.
// Moved logic to pcie_tx_elec_idle_filtered.
assign gt_tx_data_k = {2'd0,
pipe_tx7_char_is_k,
2'd0,
pipe_tx6_char_is_k,
2'd0,
pipe_tx5_char_is_k,
2'd0,
pipe_tx4_char_is_k,
2'd0,
pipe_tx3_char_is_k,
2'd0,
pipe_tx2_char_is_k,
2'd0,
pipe_tx1_char_is_k,
2'd0,
pipe_tx0_char_is_k};
assign gt_tx_data = {pipe_tx7_data,
pipe_tx6_data,
pipe_tx5_data,
pipe_tx4_data,
pipe_tx3_data,
pipe_tx2_data,
pipe_tx1_data,
pipe_tx0_data};
assign gt_tx_detect_rx_loopback = pipe_tx_rcvr_det;
assign gt_tx_elec_idle = {pipe_tx7_elec_idle,
pipe_tx6_elec_idle,
pipe_tx5_elec_idle,
pipe_tx4_elec_idle,
pipe_tx3_elec_idle,
pipe_tx2_elec_idle,
pipe_tx1_elec_idle,
pipe_tx0_elec_idle};
assign gt_tx_compliance = {pipe_tx7_compliance,
pipe_tx6_compliance,
pipe_tx5_compliance,
pipe_tx4_compliance,
pipe_tx3_compliance,
pipe_tx2_compliance,
pipe_tx1_compliance,
pipe_tx0_compliance};
assign drp_clk=1'b0;
assign drp_en=1'b0;
assign drp_we=1'b0;
assign drp_addr=11'b0;
assign drp_di=16'b0;
assign gt_tx_eq_control[ 1: 0] = pipe_tx0_eqcontrol;
assign gt_tx_eq_control[ 3: 2] = pipe_tx1_eqcontrol;
assign gt_tx_eq_control[ 5: 4] = pipe_tx2_eqcontrol;
assign gt_tx_eq_control[ 7: 6] = pipe_tx3_eqcontrol;
assign gt_tx_eq_control[ 9: 8] = pipe_tx4_eqcontrol;
assign gt_tx_eq_control[11:10] = pipe_tx5_eqcontrol;
assign gt_tx_eq_control[13:12] = pipe_tx6_eqcontrol;
assign gt_tx_eq_control[15:14] = pipe_tx7_eqcontrol;
assign gt_tx_eq_preset[3:0] = pipe_tx0_eqpreset;
assign gt_tx_eq_preset[7:4] = pipe_tx1_eqpreset;
assign gt_tx_eq_preset[11:8] = pipe_tx2_eqpreset;
assign gt_tx_eq_preset[15:12] = pipe_tx3_eqpreset;
assign gt_tx_eq_preset[19:16] = pipe_tx4_eqpreset;
assign gt_tx_eq_preset[23:20] = pipe_tx5_eqpreset;
assign gt_tx_eq_preset[27:24] = pipe_tx6_eqpreset;
assign gt_tx_eq_preset[31:28] = pipe_tx7_eqpreset;
assign gt_tx_eq_deemph[5:0] = pipe_tx0_eqdeemph;
assign gt_tx_eq_deemph[11:6] = pipe_tx1_eqdeemph;
assign gt_tx_eq_deemph[17:12] = pipe_tx2_eqdeemph;
assign gt_tx_eq_deemph[23:18] = pipe_tx3_eqdeemph;
assign gt_tx_eq_deemph[29:24] = pipe_tx4_eqdeemph;
assign gt_tx_eq_deemph[35:30] = pipe_tx5_eqdeemph;
assign gt_tx_eq_deemph[41:36] = pipe_tx6_eqdeemph;
assign gt_tx_eq_deemph[47:42] = pipe_tx7_eqdeemph;
assign {pipe_tx7_eqdone,pipe_tx6_eqdone,pipe_tx5_eqdone,pipe_tx4_eqdone,pipe_tx3_eqdone,pipe_tx2_eqdone,pipe_tx1_eqdone,pipe_tx0_eqdone} = {{(8-PL_LINK_CAP_MAX_LINK_WIDTH){1'b0}},gt_tx_eq_done};
assign pipe_tx0_eqcoeff = gt_tx_eq_coeff[17:0];
assign pipe_tx1_eqcoeff = (PL_LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_tx_eq_coeff[35:18] : 18'b0;
assign pipe_tx2_eqcoeff = (PL_LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_tx_eq_coeff[53:36] : 18'b0;
assign pipe_tx3_eqcoeff = (PL_LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_tx_eq_coeff[71:54] : 18'b0;
assign pipe_tx4_eqcoeff = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_tx_eq_coeff[89:72] : 18'b0;
assign pipe_tx5_eqcoeff = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_tx_eq_coeff[107:90] : 18'b0;
assign pipe_tx6_eqcoeff = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_tx_eq_coeff[125:108] : 18'b0;
assign pipe_tx7_eqcoeff = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_tx_eq_coeff[143:126] : 18'b0;
assign gt_rx_eq_control[ 1: 0] = pipe_rx0_eqcontrol;
assign gt_rx_eq_control[ 3: 2] = pipe_rx1_eqcontrol;
assign gt_rx_eq_control[ 5: 4] = pipe_rx2_eqcontrol;
assign gt_rx_eq_control[ 7: 6] = pipe_rx3_eqcontrol;
assign gt_rx_eq_control[ 9: 8] = pipe_rx4_eqcontrol;
assign gt_rx_eq_control[11:10] = pipe_rx5_eqcontrol;
assign gt_rx_eq_control[13:12] = pipe_rx6_eqcontrol;
assign gt_rx_eq_control[15:14] = pipe_rx7_eqcontrol;
assign gt_rx_eq_preset[2:0] = pipe_rx0_eqpreset;
assign gt_rx_eq_preset[5:3] = pipe_rx1_eqpreset;
assign gt_rx_eq_preset[8:6] = pipe_rx2_eqpreset;
assign gt_rx_eq_preset[11:9] = pipe_rx3_eqpreset;
assign gt_rx_eq_preset[14:12] = pipe_rx4_eqpreset;
assign gt_rx_eq_preset[17:15] = pipe_rx5_eqpreset;
assign gt_rx_eq_preset[20:18] = pipe_rx6_eqpreset;
assign gt_rx_eq_preset[23:21] = pipe_rx7_eqpreset;
assign gt_rx_eq_lffs[5:0] = pipe_rx0_eq_lffs;
assign gt_rx_eq_lffs[11:6] = pipe_rx1_eq_lffs;
assign gt_rx_eq_lffs[17:12] = pipe_rx2_eq_lffs;
assign gt_rx_eq_lffs[23:18] = pipe_rx3_eq_lffs;
assign gt_rx_eq_lffs[29:24] = pipe_rx4_eq_lffs;
assign gt_rx_eq_lffs[35:30] = pipe_rx5_eq_lffs;
assign gt_rx_eq_lffs[41:36] = pipe_rx6_eq_lffs;
assign gt_rx_eq_lffs[47:42] = pipe_rx7_eq_lffs;
assign gt_rx_eq_txpreset[3:0] = pipe_rx0_eq_txpreset;
assign gt_rx_eq_txpreset[7:4] = pipe_rx1_eq_txpreset;
assign gt_rx_eq_txpreset[11:8] = pipe_rx2_eq_txpreset;
assign gt_rx_eq_txpreset[15:12] = pipe_rx3_eq_txpreset;
assign gt_rx_eq_txpreset[19:16] = pipe_rx4_eq_txpreset;
assign gt_rx_eq_txpreset[23:20] = pipe_rx5_eq_txpreset;
assign gt_rx_eq_txpreset[27:24] = pipe_rx6_eq_txpreset;
assign gt_rx_eq_txpreset[31:28] = pipe_rx7_eq_txpreset;
assign pipe_rx0_eq_new_txcoeff = gt_rx_eq_new_txcoeff[17:0] ;
assign pipe_rx1_eq_new_txcoeff = (PL_LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_eq_new_txcoeff[35:18] : 1'b0;
assign pipe_rx2_eq_new_txcoeff = (PL_LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_eq_new_txcoeff[53:36] : 1'b0;
assign pipe_rx3_eq_new_txcoeff = (PL_LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_eq_new_txcoeff[71:54] : 1'b0;
assign pipe_rx4_eq_new_txcoeff = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_eq_new_txcoeff[89:72] : 1'b0;
assign pipe_rx5_eq_new_txcoeff = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_eq_new_txcoeff[107:90] : 1'b0;
assign pipe_rx6_eq_new_txcoeff = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_eq_new_txcoeff[125:108] : 1'b0;
assign pipe_rx7_eq_new_txcoeff = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_eq_new_txcoeff[143:126] : 1'b0;
assign pipe_rx0_eq_lffs_sel = gt_rx_eq_lffs_sel[0];
assign pipe_rx1_eq_lffs_sel = (PL_LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_eq_lffs_sel[1] : 1'b0;
assign pipe_rx2_eq_lffs_sel = (PL_LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_eq_lffs_sel[2] : 1'b0;
assign pipe_rx3_eq_lffs_sel = (PL_LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_eq_lffs_sel[3] : 1'b0;
assign pipe_rx4_eq_lffs_sel = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_eq_lffs_sel[4] : 1'b0;
assign pipe_rx5_eq_lffs_sel = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_eq_lffs_sel[5] : 1'b0;
assign pipe_rx6_eq_lffs_sel = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_eq_lffs_sel[6] : 1'b0;
assign pipe_rx7_eq_lffs_sel = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_eq_lffs_sel[7] : 1'b0;
assign pipe_rx0_eq_adapt_done = gt_rx_eq_adapt_done[0];
assign pipe_rx1_eq_adapt_done = (PL_LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_eq_adapt_done[1] : 1'b0;
assign pipe_rx2_eq_adapt_done = (PL_LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_eq_adapt_done[2] : 1'b0;
assign pipe_rx3_eq_adapt_done = (PL_LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_eq_adapt_done[3] : 1'b0;
assign pipe_rx4_eq_adapt_done = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_eq_adapt_done[4] : 1'b0;
assign pipe_rx5_eq_adapt_done = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_eq_adapt_done[5] : 1'b0;
assign pipe_rx6_eq_adapt_done = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_eq_adapt_done[6] : 1'b0;
assign pipe_rx7_eq_adapt_done = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_eq_adapt_done[7] : 1'b0;
assign pipe_rx0_eqdone = gt_rx_eq_done[0];
assign pipe_rx1_eqdone = (PL_LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_eq_done[1] : 1'b0;
assign pipe_rx2_eqdone = (PL_LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_eq_done[2] : 1'b0;
assign pipe_rx3_eqdone = (PL_LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_eq_done[3] : 1'b0;
assign pipe_rx4_eqdone = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_eq_done[4] : 1'b0;
assign pipe_rx5_eqdone = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_eq_done[5] : 1'b0;
assign pipe_rx6_eqdone = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_eq_done[6] : 1'b0;
assign pipe_rx7_eqdone = (PL_LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_eq_done[7] : 1'b0;
assign phy_rdy_int = ~|pipe_phystatus_rst;
// Synchronize MMCM lock output
always @ (posedge user_clk or negedge mmcm_lock) begin
if (!mmcm_lock)
reg_clock_locked[1:0] <= #TCQ 2'b11;
else
reg_clock_locked[1:0] <= #TCQ {reg_clock_locked[0], 1'b0};
end
assign clock_locked = !reg_clock_locked[1];
// Synchronize PHY Ready
always @ (posedge user_clk or negedge phy_rdy_int) begin
if (!phy_rdy_int)
reg_phy_rdy[1:0] <= #TCQ 2'b11;
else
reg_phy_rdy[1:0] <= #TCQ {reg_phy_rdy[0], 1'b0};
end
assign phy_rdy = !reg_phy_rdy[1];
endmodule
|
module backup#(
parameter PHYSICAL_ADDR_WIDTH = 25, //flash capacity 16KB*2^25 = 2^39B = 512GB
parameter DRAM_IO_WIDTH = 256, //DRAM IO
parameter DRAM_ADDR_WIDTH = 29, //DRAM cacacity 64bits(2^3B)*2^29=2^32B = 4GB
parameter DRAM_MASK_WIDTH = 32, //8bits/mask bit 256/8 = 32
parameter COMMAND_WIDTH = 128, //
parameter GC_COMMAND_WIDTH = 29, //
parameter CACHE_ADDR_WIDTH = 17, //cache space 16KB*2^17=2^31B=2GB
parameter L2P_TABLE_BASE = 29'b00000_00000000_00000000_00000000, //32bits*2^25=2^27B=128MB
parameter P2L_TABLE_BASE = 29'b00001_00000000_00000000_00000000, //32bits*2^25=2^27B=128MB
parameter FREE_BLOCK_FIFO_BASE = 29'b00010_00000000_00000000_00000000, //32bits*2^17=2^ram_do=512KB
parameter GARBAGE_TABLE_BASE = 29'b00010_00000001_00000000_00000000, //32bits*2^17=2^ram_do=512KB
parameter CACHE_ENTRY_BASE = 29'b00100_00000000_00000000_00000000,
parameter ADDITIONAL_CACHE_FIFO_BASE = 29'b00101_00000000_00000000_00000000,
parameter CACHE_BASE = 29'b10000_00000000_00000000_00000000, //last 2GB space
parameter L2P_TABLE_BASE_FLASH = 22'b111111_11110000_00000000, //128MB/16KB/8(# of channel)=1K=2^10
parameter P2L_TABLE_BASE_FLASH = 22'b111111_11110100_00000000,
parameter FREE_BLOCK_FIFO_BASE_FLASH = 22'b111111_11111000_00000000, //512KB/16KB/8=4, 4pages/channel,32pages total
parameter GARBAGE_TABLE_BASE_FLASH = 22'b111111_11111000_00000100,
parameter REGISTER_BASE_FLASH = 22'b111111_11111000_00001000,
parameter READ = 2'b00,
parameter WRITE = 2'b01,
parameter MOVE = 2'b10,
parameter ERASE = 2'b11
)(
reset,
clk,
dram_backup_en,
backup_op,
fifo_enpty_flag,
state_check,
//与DRAM的交互接口
dram_permit,
data_from_dram,
dram_ready,
rd_data_valid,
//需要备份的寄存器
left_capacity_final,
free_block_fifo_tails,
free_block_fifo_heads,
ssd_command_fifo_full,
controller_command_fifo_full_or_not,
write_data_fifo_prog_full,//8 bit
write_data_fifo_full,
//Output
dram_request,
release_dram,
addr_to_dram,
data_to_dram,
dram_data_mask,
dram_en,
dram_read_or_write,
ssd_command_fifo_in,
ssd_command_fifo_in_en,
controller_command_fifo_in_en,
controller_command_fifo_in,
write_data_fifo_in,
write_data_fifo_in_en,//8 bit
backup_or_checkcache,
backup_or_io
//state
);
input reset;
input clk;
input dram_backup_en;
input [1:0]backup_op;// 1)flush 2'b10 2)backup dram 2'b11
input fifo_enpty_flag;
input state_check;
input dram_permit;
input [DRAM_IO_WIDTH-1:0] data_from_dram;
input dram_ready;
input rd_data_valid;
input [18:0]left_capacity_final;//512GB flash有2的17次方个块
input [127:0] free_block_fifo_tails;
input [127:0] free_block_fifo_heads;
input ssd_command_fifo_full;
input controller_command_fifo_full_or_not;
input write_data_fifo_prog_full;//8 bit
input write_data_fifo_full;
output dram_request;
output release_dram;
output [DRAM_ADDR_WIDTH-1:0] addr_to_dram;
output [DRAM_IO_WIDTH-1:0]data_to_dram;
output [DRAM_MASK_WIDTH-1:0]dram_data_mask;
output dram_en;
output dram_read_or_write;
output [COMMAND_WIDTH-1:0]ssd_command_fifo_in;
output ssd_command_fifo_in_en;
output [7:0]controller_command_fifo_in_en;
output [COMMAND_WIDTH-1:0]controller_command_fifo_in;
output [DRAM_IO_WIDTH-1:0]write_data_fifo_in;
output [7:0]write_data_fifo_in_en;//8 bit
output backup_or_checkcache;
output backup_or_io;
//output [5:0] state;
reg dram_request;
reg release_dram;
reg [DRAM_ADDR_WIDTH-1:0] addr_to_dram;
reg [DRAM_IO_WIDTH-1:0]data_to_dram;
reg [DRAM_MASK_WIDTH-1:0]dram_data_mask;
reg dram_en;
reg dram_read_or_write;
reg [COMMAND_WIDTH-1:0]ssd_command_fifo_in;
reg ssd_command_fifo_in_en;
reg [7:0]controller_command_fifo_in_en;
reg [COMMAND_WIDTH-1:0]controller_command_fifo_in;
reg [DRAM_IO_WIDTH-1:0]write_data_fifo_in;
reg [7:0]write_data_fifo_in_en;//8 bit
reg backup_or_checkcache;
reg backup_or_io;
parameter IDLE =6'b000000;
parameter WAIT_FOR_A_WHILE =6'b000001;
parameter APPLY_DRAM =6'b000010;
parameter WAIT_FOR_DRAM =6'b000011;
parameter GET_ENTRY =6'b000100;
parameter RECEIVE_ENTRY0 =6'b000101;
parameter RECEIVE_ENTRY1 =6'b000110;
parameter CHECK_DIRTY0 =6'b000111;
parameter CHECK_DIRTY1 =6'b001000;
parameter SEND_SSD_COMMAND =6'b001001;
parameter CHECK_INDEX =6'b001010;
parameter WRITE_ENTRY_BACK0 =6'b001011;
parameter WRITE_ENTRY_BACK1 =6'b001100;
parameter WRITE_ENTRY_BACK2 =6'b001101;
parameter CHECK_CACHE_ENTRY_ADDR =6'b001110;
parameter ERASE_FLASH0 =6'b001111;
parameter ERASE_FLASH1 =6'b010000;
parameter ERASE_FLASH2 =6'b010001;
parameter ERASE_FLASH3 =6'b010010;
parameter ERASE_FLASH4 =6'b010011;
parameter READY_FOR_WRITE_L2P =6'b010100;
parameter WRITE_BACK_L2P0 =6'b010101;
parameter WRITE_BACK_L2P1 =6'b010110;
parameter WRITE_BACK_L2P2 =6'b010111;
parameter WRITE_BACK_L2P3 =6'b011000;
parameter CHECK_L2P_CACHE_ADDR =6'b011001;
parameter READY_FOR_WRITE_P2L =6'b011010;
parameter WRITE_BACK_P2L0 =6'b011011;
parameter WRITE_BACK_P2L1 =6'b011100;
parameter WRITE_BACK_P2L2 =6'b011101;
parameter WRITE_BACK_P2L3 =6'b011110;
parameter CHECK_P2L_CACHE_ADDR =6'b011111;
parameter READY_FOR_FREE_BLOCK_FIFO =6'b100000;
parameter WRITE_BACK_FREE_BLOCK_FIFO0 =6'b100001;
parameter WRITE_BACK_FREE_BLOCK_FIFO1 =6'b100010;
parameter WRITE_BACK_FREE_BLOCK_FIFO2 =6'b100011;
parameter WRITE_BACK_FREE_BLOCK_FIFO3 =6'b100100;
parameter CHECK_FREE_BLOCK_CACHE_ADDR =6'b100101;
parameter READY_FOR_GARBAGE_TABLE =6'b100110;
parameter WRITE_BACK_GARBAGE_TABLE0 =6'b100111;
parameter WRITE_BACK_GARBAGE_TABLE1 =6'b101000;
parameter WRITE_BACK_GARBAGE_TABLE2 =6'b101001;
parameter WRITE_BACK_GARBAGE_TABLE3 =6'b101010;
parameter CHECK_FREE_GARBAGE_ADDR =6'b101011;
parameter UNLOCK_DRAM_FOR_A_WHILE =6'b101100;
parameter WAIT_DRAM_FOR_A_WHILE =6'b101101;
parameter CHANCG_TO_STATE_BUF =6'b101110;
parameter UNLOCK_DRAM =6'b101111;
parameter CHECK_ENPTY_FLAG0 =6'b110000;
parameter CHECK_ENPTY_FLAG1 =6'b110001;
parameter CHECK_ENPTY_FLAG2 =6'b110010;
parameter READY_FOR_WRITE_REG =6'b110011;
parameter WRITE_BACK_REG0 =6'b110100;
parameter WRITE_BACK_REG1 =6'b110101;
parameter WRITE_BACK_REG2 =6'b110110;
parameter WRITE_BACK_REG3 =6'b110111;
parameter CHECK_REG_ENTRY =6'b111000;
parameter FINISH =6'b111111;
reg [5:0]state;
reg [5:0]state_buf;
reg [11:0]count;
reg [9:0]count_read;
reg [3:0]index;
reg [2:0]channel_index;
reg [7:0]enable;
reg [DRAM_ADDR_WIDTH-1:0]dram_addr;
reg [21:0]paddr;
reg [511:0]data_from_dram_buf;
reg [27:0]logical_addr;
reg [15:0]cache_entry_addr;//2GB/16KB= 2的17次方个16Kb dram一个地址可以记录两个cache_entry,用16位地址就可以表示cache_entry
always@ (negedge reset or posedge clk)
begin
if(!reset)
begin
dram_request<=0;
release_dram<=0;
addr_to_dram<=0;
data_to_dram<=0;
dram_data_mask<=0;
dram_en<=0;
dram_read_or_write<=0;
ssd_command_fifo_in<=0;
ssd_command_fifo_in_en<=0;
controller_command_fifo_in_en<=0;
controller_command_fifo_in<=0;
write_data_fifo_in<=0;
write_data_fifo_in_en<=0;//8 bit
backup_or_checkcache<=0;
backup_or_io<=0;
state<=IDLE;
state_buf<=0;
count<=0;
count_read<=0;
index<=0;
channel_index<=0;
enable<=0;
dram_addr<=0;
paddr<=0;
data_from_dram_buf<=0;
logical_addr<=0;
cache_entry_addr<=0;
end
else
begin
case (state)
IDLE://00
begin
if(dram_backup_en)
begin
state_buf<=ERASE_FLASH0;
state<=CHECK_ENPTY_FLAG0;
end
else
state<=IDLE;
end
//step 2 erase flash
ERASE_FLASH0://0f
begin
channel_index<=0;
paddr<=22'b000000_00000000_00000000;//22'b111111_11110000_00000000;
state<=ERASE_FLASH1;
end
ERASE_FLASH1://10
begin
case(channel_index)
3'b000:
enable<=8'b00000001;
3'b001:
enable<=8'b00000010;
3'b010:
enable<=8'b00000100;
3'b011:
enable<=8'b00001000;
3'b100:
enable<=8'b00010000;
3'b101:
enable<=8'b00100000;
3'b110:
enable<=8'b01000000;
3'b111:
enable<=8'b10000000;
endcase
state<=ERASE_FLASH2;
end
ERASE_FLASH2://11
begin
if(channel_index==3'b111)
begin
if(controller_command_fifo_full_or_not == 1'b0)
begin
controller_command_fifo_in<= {ERASE, 101'b0,channel_index,paddr};//2+104+22=128
controller_command_fifo_in_en<=enable;
channel_index<=channel_index+1;
state<=ERASE_FLASH3;
paddr<=paddr+256;//one block have 256 pages
end
end
else
begin
if(controller_command_fifo_full_or_not == 1'b0)
begin
controller_command_fifo_in<= {ERASE, 101'b0,channel_index,paddr};//2+104+22=128
controller_command_fifo_in_en<=enable;
channel_index<=channel_index+1;
state<=ERASE_FLASH1;
end
//paddr<=22'b111111_11110000_00000000;
end
end
ERASE_FLASH3://12 check channel_index
begin
controller_command_fifo_in_en<=8'b00000000;
if(paddr==22'b0)//每个通道发送16个erase命令,共擦除128个block
begin
state<=CHECK_ENPTY_FLAG0;
state_buf<=APPLY_DRAM;
end
else
begin
state<=ERASE_FLASH1;
end
end
APPLY_DRAM://02
begin
dram_request <= 1;
state<=WAIT_FOR_DRAM;
end
WAIT_FOR_DRAM://03
begin
if(dram_permit==1)
begin
dram_request <= 0;
state <= GET_ENTRY;
dram_en <= 1;
dram_read_or_write <= 1;//read
cache_entry_addr<=0;
end
else
state<=WAIT_FOR_DRAM;
end
//step1 write back dirty data
GET_ENTRY://04
begin
if(dram_ready)
begin
addr_to_dram <= cache_entry_addr + CACHE_ENTRY_BASE;
dram_en <= 0;
dram_read_or_write <= 1;//read
state <= RECEIVE_ENTRY0;
end
else
begin
state <= GET_ENTRY;
end
end
RECEIVE_ENTRY0: //05
begin
dram_en <= 0;
if(rd_data_valid)
begin
state <= RECEIVE_ENTRY1;
data_from_dram_buf[255:0]<=data_from_dram;
end
else
state <= RECEIVE_ENTRY0;
end
RECEIVE_ENTRY1: //06
begin
if(rd_data_valid)
begin
state <= CHECK_DIRTY0;
index<=0;
data_from_dram_buf[511:256]<=data_from_dram;
end
else
state <= RECEIVE_ENTRY1;
end
CHECK_DIRTY0://7
begin
if(data_from_dram_buf[30] | data_from_dram_buf[62] | data_from_dram_buf[94] | data_from_dram_buf[126] |
data_from_dram_buf[158] | data_from_dram_buf[190] | data_from_dram_buf[222] | data_from_dram_buf[254] |
data_from_dram_buf[286] | data_from_dram_buf[318] | data_from_dram_buf[350] | data_from_dram_buf[382] |
data_from_dram_buf[414] | data_from_dram_buf[446] | data_from_dram_buf[478] | data_from_dram_buf[510])
begin
state<=CHECK_DIRTY1;//有脏数据,需要替换
end
else//无脏数据,取下一组表
begin
cache_entry_addr<=cache_entry_addr+8;//每次可以取512bit,对应8个dram偏移地址
state<=CHECK_CACHE_ENTRY_ADDR;
end
end
CHECK_DIRTY1://08
begin
case(index)
4'b0000:
begin
if(data_from_dram_buf[30])//dirty
begin
data_from_dram_buf[29] <= 1;//locked ,等待数据写回flash,避免数据丢失
data_from_dram_buf[30] <= 0;
logical_addr <= data_from_dram_buf[27:0];
state<=SEND_SSD_COMMAND;
end
else
begin
state<=CHECK_DIRTY1;
end
end
4'b0001:
begin
if(data_from_dram_buf[62])
begin
data_from_dram_buf[61] <= 1;
data_from_dram_buf[62] <= 0;
logical_addr <= data_from_dram_buf[59:32];
state<=SEND_SSD_COMMAND;
end
else
begin
state<=CHECK_DIRTY1;
end
end
4'b0010:
begin
if(data_from_dram_buf[94])
begin
data_from_dram_buf[93] <= 1;
data_from_dram_buf[94] <= 0;
logical_addr <= data_from_dram_buf[91:64];
state<=SEND_SSD_COMMAND;
end
else
begin
state<=CHECK_DIRTY1;
end
end
4'b0011:
begin
if(data_from_dram_buf[126])
begin
data_from_dram_buf[125] <= 1;
data_from_dram_buf[126] <= 0;
logical_addr <= data_from_dram_buf[123:96];
state<=SEND_SSD_COMMAND;
end
else
begin
state<=CHECK_DIRTY1;
end
end
4'b0100:
begin
if(data_from_dram_buf[158])
begin
data_from_dram_buf[157] <= 1;
data_from_dram_buf[158] <= 0;
logical_addr <= data_from_dram_buf[155:128];
state<=SEND_SSD_COMMAND;
end
else
begin
state<=CHECK_DIRTY1;
end
end
4'b0101:
begin
if(data_from_dram_buf[190])
begin
data_from_dram_buf[189] <= 1;
data_from_dram_buf[190] <= 0;
logical_addr <= data_from_dram_buf[187:160];
state<=SEND_SSD_COMMAND;
end
else
begin
state<=CHECK_DIRTY1;
end
end
4'b0110:
begin
if(data_from_dram_buf[222])
begin
data_from_dram_buf[221] <= 1;
data_from_dram_buf[222] <= 0;
logical_addr <= data_from_dram_buf[219:192];
state<=SEND_SSD_COMMAND;
end
else
begin
state<=CHECK_DIRTY1;
end
end
4'b0111:
begin
if(data_from_dram_buf[254])
begin
data_from_dram_buf[253] <= 1;
data_from_dram_buf[254] <= 0;
logical_addr <= data_from_dram_buf[251:224];
state<=SEND_SSD_COMMAND;
end
else
begin
state<=CHECK_DIRTY1;
end
end
4'b1000:
begin
if(data_from_dram_buf[286])
begin
data_from_dram_buf[285] <= 1;
data_from_dram_buf[286] <= 0;
logical_addr <= data_from_dram_buf[283:256];
state<=SEND_SSD_COMMAND;
end
else
begin
state<=CHECK_DIRTY1;
end
end
4'b1001:
begin
if(data_from_dram_buf[318])
begin
data_from_dram_buf[317] <= 1;
data_from_dram_buf[318] <= 0;
logical_addr <= data_from_dram_buf[315:288];
state<=SEND_SSD_COMMAND;
end
else
begin
state<=CHECK_DIRTY1;
end
end
4'b1010:
begin
if(data_from_dram_buf[350])
begin
data_from_dram_buf[349] <= 1;
data_from_dram_buf[350] <= 0;
logical_addr <= data_from_dram_buf[347:320];
state<=SEND_SSD_COMMAND;
end
else
begin
state<=CHECK_DIRTY1;
end
end
4'b1011:
begin
if(data_from_dram_buf[382])
begin
data_from_dram_buf[381] <= 1;
data_from_dram_buf[382] <= 0;
logical_addr <= data_from_dram_buf[379:352];
state<=SEND_SSD_COMMAND;
end
else
begin
state<=CHECK_DIRTY1;
end
end
4'b1100:
begin
if(data_from_dram_buf[414])
begin
data_from_dram_buf[413] <= 1;
data_from_dram_buf[414] <= 0;
logical_addr <= data_from_dram_buf[411:384];
state<=SEND_SSD_COMMAND;
end
else
begin
state<=CHECK_DIRTY1;
end
end
4'b1101:
begin
if(data_from_dram_buf[446])
begin
data_from_dram_buf[445] <= 1;
data_from_dram_buf[446] <= 0;
logical_addr <= data_from_dram_buf[443:416];
state<=SEND_SSD_COMMAND;
end
else
begin
state<=CHECK_DIRTY1;
end
end
4'b1110:
begin
if(data_from_dram_buf[478])
begin
data_from_dram_buf[477] <= 1;
data_from_dram_buf[478] <= 0;
logical_addr <= data_from_dram_buf[475:448];
state<=SEND_SSD_COMMAND;
end
else
begin
state<=CHECK_DIRTY1;
end
end
4'b1111:
begin
if(data_from_dram_buf[510])
begin
data_from_dram_buf[509] <= 1;
data_from_dram_buf[510] <= 0;
logical_addr <= data_from_dram_buf[507:480];
state<=SEND_SSD_COMMAND;
end
else
begin
state<=WRITE_ENTRY_BACK0;//last one
dram_en<= 1;
dram_read_or_write <= 0;//write
end
end
endcase
index<=index+1;
end
SEND_SSD_COMMAND://09
begin
if(ssd_command_fifo_full==1'b0)
begin
ssd_command_fifo_in_en <= 1;
ssd_command_fifo_in <= {2'b01,1'b1,93'b0,4'b0000,logical_addr};
state<=CHECK_INDEX;
end
else
begin
state<=UNLOCK_DRAM_FOR_A_WHILE;
state_buf<=SEND_SSD_COMMAND;
end
end
CHECK_INDEX://a
begin
ssd_command_fifo_in_en <= 0;
if(index==4'b0000)
begin
state<=WRITE_ENTRY_BACK0;
dram_en<= 1;
dram_read_or_write <= 0;//write
end
else
state<=CHECK_DIRTY1;
end
WRITE_ENTRY_BACK0://b unlock
begin
index<=0;
if(dram_ready)
begin
dram_en<= 0;
dram_read_or_write <= 0;//write
addr_to_dram <= cache_entry_addr + CACHE_ENTRY_BASE;
data_to_dram <= data_from_dram_buf[255:0];
dram_data_mask<=0;//mask
state <= WRITE_ENTRY_BACK1;
end
else
state <= WRITE_ENTRY_BACK0;
end
WRITE_ENTRY_BACK1: //c
begin
data_to_dram <=data_from_dram_buf[511:256];
dram_data_mask<=0;
if(count>=2)
begin
count<=0;
state <= CHECK_CACHE_ENTRY_ADDR;
end
else
begin
count<=count+1;
state<=WRITE_ENTRY_BACK1;
end
end
CHECK_CACHE_ENTRY_ADDR://0e
begin
if(cache_entry_addr==16'h0000)
begin
state_buf<=READY_FOR_WRITE_L2P;
state<=CHECK_ENPTY_FLAG0;
release_dram <= 1;
end
else
begin
state <= GET_ENTRY;
dram_en <= 1;
dram_read_or_write <= 1;//read
end
end
//step3 write back L2P table
READY_FOR_WRITE_L2P://14 等待擦除操作全部完成,再写回table
begin
dram_addr<=L2P_TABLE_BASE;
channel_index<=0;
count <= 0;
count_read <= 0;
paddr<=L2P_TABLE_BASE_FLASH;//l2p flash base address
state<=WRITE_BACK_L2P0;
end
WRITE_BACK_L2P0://15
begin
if(!write_data_fifo_prog_full & !controller_command_fifo_full_or_not)
begin
state <= WRITE_BACK_L2P1;
dram_en <= 1;
dram_read_or_write <= 1;//read
end
else
begin
backup_or_io<=0;
state<=UNLOCK_DRAM_FOR_A_WHILE;
state_buf<=WRITE_BACK_L2P0;
end
case(channel_index)
3'b000:
enable<=8'b00000001;
3'b001:
enable<=8'b00000010;
3'b010:
enable<=8'b00000100;
3'b011:
enable<=8'b00001000;
3'b100:
enable<=8'b00010000;
3'b101:
enable<=8'b00100000;
3'b110:
enable<=8'b01000000;
3'b111:
enable<=8'b10000000;
endcase
end
WRITE_BACK_L2P1://16
begin
write_data_fifo_in_en<=8'b0;//默认不往pcie_data_send_fifo发送数据
if(rd_data_valid & !write_data_fifo_full)
begin
write_data_fifo_in_en<=enable;
write_data_fifo_in<=data_from_dram;
count_read<=count_read+1;//计数接收多少个数据
end
else begin end
if(dram_ready)
begin
addr_to_dram <=dram_addr;
dram_en <=0;
count<=count+1;//计数发送多少个读命令
dram_read_or_write <= 1;//read
state <= WRITE_BACK_L2P2;
end
else
begin
state<=WRITE_BACK_L2P1;
end
end
WRITE_BACK_L2P2://17
begin
dram_en <= 0;
write_data_fifo_in_en<=8'b0;//默认不往pcie_data_send_fifo发送数据
dram_addr<=dram_addr+8;//8个64位数据等于512位数据
if(rd_data_valid & !write_data_fifo_full)
begin
write_data_fifo_in_en<=enable;
write_data_fifo_in<=data_from_dram;
count_read<=count_read+1;//计数接收多少个数据
end
else begin end
if(count>=256)//发送256次读命令,256*512b=16KB,为一页大小
begin
state <= WRITE_BACK_L2P3;
count<=0;
end
else
begin
state <= WRITE_BACK_L2P1;
dram_en <= 1;
dram_read_or_write <= 1;//read
end
end
WRITE_BACK_L2P3: //18
begin
write_data_fifo_in_en<=8'b0;//默认不往pcie_data_send_fifo发送数据
if(rd_data_valid & !write_data_fifo_full)
begin
write_data_fifo_in_en<=enable;
write_data_fifo_in<=data_from_dram;
count_read<=count_read+1;//计数接收多少个数据
end
else begin end
if(count_read>=512)//读512次256b的数据
begin
count_read<=0;
controller_command_fifo_in<= {WRITE, 37'b0, channel_index,paddr,64'b0};
controller_command_fifo_in_en<=enable;
channel_index<=channel_index+1;//send to next channel
state <= CHECK_L2P_CACHE_ADDR;//
end
else
begin
state<=WRITE_BACK_L2P3;
end
end
CHECK_L2P_CACHE_ADDR://19
begin
controller_command_fifo_in_en<=0;
if(channel_index==3'b0)
paddr<=paddr+1; //512*256b=16KB(一页)
else begin end
if(dram_addr[23:0]==24'h000000)//L2P table write back done
begin
state_buf<=READY_FOR_WRITE_P2L;
state<=CHECK_ENPTY_FLAG0;
end
else
state<=WRITE_BACK_L2P0;
end
//step4 write back P2L table
READY_FOR_WRITE_P2L://1a 等待擦除操作全部完成,再写回table
begin
dram_addr<=P2L_TABLE_BASE;
channel_index<=0;
count <= 0;
count_read <= 0;
paddr<=P2L_TABLE_BASE_FLASH;//p2l flash base address 128M=8k pages,平均每个通道1k,即2^10
state<=WRITE_BACK_P2L0;
end
WRITE_BACK_P2L0://1b
begin
if(!write_data_fifo_prog_full & !controller_command_fifo_full_or_not)
begin
state <= WRITE_BACK_P2L1;
dram_en <= 1;
dram_read_or_write <= 1;//read
end
else
begin
state<=UNLOCK_DRAM_FOR_A_WHILE;
state_buf<=WRITE_BACK_P2L0;
end
case(channel_index)
3'b000:
enable<=8'b00000001;
3'b001:
enable<=8'b00000010;
3'b010:
enable<=8'b00000100;
3'b011:
enable<=8'b00001000;
3'b100:
enable<=8'b00010000;
3'b101:
enable<=8'b00100000;
3'b110:
enable<=8'b01000000;
3'b111:
enable<=8'b10000000;
endcase
end
WRITE_BACK_P2L1://1c
begin
write_data_fifo_in_en<=8'b0;//默认不往pcie_data_send_fifo发送数据
if(rd_data_valid & !write_data_fifo_full)
begin
write_data_fifo_in_en<=enable;
write_data_fifo_in<=data_from_dram;
count_read<=count_read+1;//计数接收多少个数据
end
else begin end
if(dram_ready)
begin
addr_to_dram <=dram_addr;
dram_en <=0;
count<=count+1;//计数发送多少个读命令
dram_read_or_write <= 1;//read
state <= WRITE_BACK_P2L2;
end
else
begin
state<=WRITE_BACK_P2L1;
end
end
WRITE_BACK_P2L2://1d
begin
dram_en <= 0;
write_data_fifo_in_en<=8'b0;//默认不往pcie_data_send_fifo发送数据
dram_addr<=dram_addr+8;//8个64位数据等于512位数据
if(rd_data_valid & !write_data_fifo_full)
begin
write_data_fifo_in_en<=enable;
write_data_fifo_in<=data_from_dram;
count_read<=count_read+1;//计数接收多少个数据
end
else begin end
if(count>=256)//发送256次读命令,256*512b=16KB,为一页大小
begin
state <= WRITE_BACK_P2L3;
count<=0;
end
else
begin
state <= WRITE_BACK_P2L1;
dram_en <= 1;
dram_read_or_write <= 1;//read
end
end
WRITE_BACK_P2L3: //1e
begin
write_data_fifo_in_en<=8'b0;//默认不往pcie_data_send_fifo发送数据
if(rd_data_valid & !write_data_fifo_full)
begin
write_data_fifo_in_en<=enable;
write_data_fifo_in<=data_from_dram;
count_read<=count_read+1;//计数接收多少个数据
end
else begin end
if(count_read>=512)//读512次256b的数据
begin
state <= CHECK_P2L_CACHE_ADDR;//修改映射表
count_read<=0;
controller_command_fifo_in<= {WRITE, 37'b0, channel_index,paddr,64'b0};
controller_command_fifo_in_en<=enable;
channel_index<=channel_index+1;//send to next channel
end
else
begin
state<=WRITE_BACK_P2L3;
end
end
CHECK_P2L_CACHE_ADDR://1f
begin
controller_command_fifo_in_en<=8'b0;
if(channel_index==3'b0)
paddr<=paddr+1;
if(dram_addr[23:0]==24'h000000)//P2L table write back done
begin
state<=READY_FOR_FREE_BLOCK_FIFO;
end
else
state<=WRITE_BACK_P2L0;
end
//step 5 write back FREE_BLOCK_FIFO table
READY_FOR_FREE_BLOCK_FIFO://20
begin
dram_addr<=FREE_BLOCK_FIFO_BASE;
paddr<=FREE_BLOCK_FIFO_BASE_FLASH;//FREE_BLOCK_FIFO flash base address
count <= 0;
count_read <= 0;
channel_index<=0;
state<=WRITE_BACK_FREE_BLOCK_FIFO0;
end
WRITE_BACK_FREE_BLOCK_FIFO0://21
begin
if(!write_data_fifo_prog_full & !controller_command_fifo_full_or_not)
begin
state <= WRITE_BACK_FREE_BLOCK_FIFO1;
dram_read_or_write <= 1;//read
dram_en <=1;
end
else
begin
backup_or_io<=0;
state<=UNLOCK_DRAM_FOR_A_WHILE;
state_buf<=WRITE_BACK_FREE_BLOCK_FIFO0;
end
case(channel_index)
3'b000:
enable<=8'b00000001;
3'b001:
enable<=8'b00000010;
3'b010:
enable<=8'b00000100;
3'b011:
enable<=8'b00001000;
3'b100:
enable<=8'b00010000;
3'b101:
enable<=8'b00100000;
3'b110:
enable<=8'b01000000;
3'b111:
enable<=8'b10000000;
endcase
end
WRITE_BACK_FREE_BLOCK_FIFO1://22
begin
write_data_fifo_in_en<=8'b0;//默认不往pcie_data_send_fifo发送数据
if(rd_data_valid & !write_data_fifo_full)
begin
write_data_fifo_in_en<=enable;
write_data_fifo_in<=data_from_dram;
count_read<=count_read+1;//计数接收多少个数据
end
else begin end
if(dram_ready)
begin
addr_to_dram <=dram_addr;
dram_en <=0;
count<=count+1;//计数发送多少个读命令
dram_read_or_write <= 1;//read
state <= WRITE_BACK_FREE_BLOCK_FIFO2;
end
else
begin
state<=WRITE_BACK_FREE_BLOCK_FIFO1;
end
end
WRITE_BACK_FREE_BLOCK_FIFO2://23
begin
dram_en <= 0;
write_data_fifo_in_en<=8'b0;//默认不往pcie_data_send_fifo发送数据
dram_addr<=dram_addr+8;//8个64位数据等于512位数据
if(rd_data_valid & !write_data_fifo_full)
begin
write_data_fifo_in_en<=enable;
write_data_fifo_in<=data_from_dram;
count_read<=count_read+1;//计数接收多少个数据
end
else begin end
if(count>=256)//发送256次读命令,256*512b=16KB,为一页大小
begin
state <= WRITE_BACK_FREE_BLOCK_FIFO3;
count<=0;
end
else
begin
state <= WRITE_BACK_FREE_BLOCK_FIFO1;
dram_en <= 1;
dram_read_or_write <= 1;//read
end
end
WRITE_BACK_FREE_BLOCK_FIFO3: //24
begin
write_data_fifo_in_en<=8'b0;//默认不往pcie_data_send_fifo发送数据
if(rd_data_valid & !write_data_fifo_full)
begin
write_data_fifo_in_en<=enable;
write_data_fifo_in<=data_from_dram;
count_read<=count_read+1;//计数接收多少个数据
end
else begin end
if(count_read>=512)//读512次256b的数据
begin
state <= CHECK_FREE_BLOCK_CACHE_ADDR;//修改映射表
count_read<=0;
controller_command_fifo_in<= {WRITE, 37'b0, channel_index,paddr,64'b0};
controller_command_fifo_in_en<=enable;
channel_index<=channel_index+1;//send to next channel
end
else
begin
state<=WRITE_BACK_FREE_BLOCK_FIFO3;
end
end
CHECK_FREE_BLOCK_CACHE_ADDR://25
begin
controller_command_fifo_in_en<=8'b0;
if(channel_index==3'b0)
paddr<=paddr+1;
if(dram_addr[15:0]==16'h000000)//FREE_BLOCK table write back done
begin
state<=READY_FOR_GARBAGE_TABLE;
end
else
state<=WRITE_BACK_FREE_BLOCK_FIFO0;
end
//step 6 write garbage table
READY_FOR_GARBAGE_TABLE://26
begin
dram_addr<=GARBAGE_TABLE_BASE;
paddr<=GARBAGE_TABLE_BASE_FLASH;//garbage table flash base address
channel_index<=0;
count <= 0;
count_read <= 0;
state<=WRITE_BACK_GARBAGE_TABLE0;
end
WRITE_BACK_GARBAGE_TABLE0://27
begin
if(!write_data_fifo_prog_full & !controller_command_fifo_full_or_not)
begin
state <= WRITE_BACK_GARBAGE_TABLE1;
dram_en <= 1;
dram_read_or_write <= 1;//read
end
else
begin
state<=UNLOCK_DRAM_FOR_A_WHILE;
state_buf<=WRITE_BACK_GARBAGE_TABLE0;
end
case(channel_index)
3'b000:
enable<=8'b00000001;
3'b001:
enable<=8'b00000010;
3'b010:
enable<=8'b00000100;
3'b011:
enable<=8'b00001000;
3'b100:
enable<=8'b00010000;
3'b101:
enable<=8'b00100000;
3'b110:
enable<=8'b01000000;
3'b111:
enable<=8'b10000000;
endcase
end
WRITE_BACK_GARBAGE_TABLE1://28
begin
write_data_fifo_in_en<=8'b0;//默认不往pcie_data_send_fifo发送数据
if(rd_data_valid & !write_data_fifo_full)
begin
write_data_fifo_in_en<=enable;
write_data_fifo_in<=data_from_dram;
count_read<=count_read+1;//计数接收多少个数据
end
else begin end
if(dram_ready)
begin
addr_to_dram <=dram_addr;
dram_en <=0;
count<=count+1;//计数发送多少个读命令
dram_read_or_write <= 1;//read
state <= WRITE_BACK_GARBAGE_TABLE2;
end
else
begin
state<=WRITE_BACK_GARBAGE_TABLE1;
end
end
WRITE_BACK_GARBAGE_TABLE2://29
begin
dram_en <= 0;
write_data_fifo_in_en<=8'b0;//默认不往pcie_data_send_fifo发送数据
dram_addr<=dram_addr+8;//8个64位数据等于512位数据
if(rd_data_valid & !write_data_fifo_full)
begin
write_data_fifo_in_en<=enable;
write_data_fifo_in<=data_from_dram;
count_read<=count_read+1;//计数接收多少个数据
end
else begin end
if(count>=256)//发送256次读命令,256*512b=16KB,为一页大小
begin
state <= WRITE_BACK_GARBAGE_TABLE3;
count<=0;
end
else
begin
state <= WRITE_BACK_GARBAGE_TABLE1;
dram_en <= 1;
dram_read_or_write <= 1;//read
end
end
WRITE_BACK_GARBAGE_TABLE3: //2a
begin
write_data_fifo_in_en<=8'b0;//默认不往pcie_data_send_fifo发送数据
if(rd_data_valid & !write_data_fifo_full)
begin
write_data_fifo_in_en<=enable;
write_data_fifo_in<=data_from_dram;
count_read<=count_read+1;//计数接收多少个数据
end
else begin end
if(count_read>=512)//读512次256b的数据
begin
state <= CHECK_FREE_GARBAGE_ADDR;//修改映射表
count_read<=0;
controller_command_fifo_in<= {WRITE, 37'b0, channel_index,paddr,64'b0};
controller_command_fifo_in_en<=enable;
channel_index<=channel_index+1;//send to next channel
end
else
begin
state<=WRITE_BACK_GARBAGE_TABLE3;
end
end
CHECK_FREE_GARBAGE_ADDR://2b
begin
controller_command_fifo_in_en<=8'b0;
if(channel_index==3'b0)
paddr<=paddr+1;
if(dram_addr[15:0]==16'h000000)//FREE_BLOCK table write back done
begin
state<=READY_FOR_WRITE_REG;
end
else
state<=WRITE_BACK_GARBAGE_TABLE0;
end
// step 7 write back registers
READY_FOR_WRITE_REG : //33
begin
count <=0;
enable <=8'b00000001;
paddr <=REGISTER_BASE_FLASH;//register flash base address
state <=WRITE_BACK_REG0;
end
WRITE_BACK_REG0:
begin
write_data_fifo_in_en<=8'b0;//默认不往pcie_data_send_fifo发送数据
if( !write_data_fifo_full & !controller_command_fifo_full_or_not)
begin
write_data_fifo_in_en<=enable;
write_data_fifo_in<={left_capacity_final[16:0],free_block_fifo_heads[111:0],free_block_fifo_tails[111:0],15'b111_1111_1111_1111};
count <=count+1;
state <=WRITE_BACK_REG1;
end
else
begin
state<=UNLOCK_DRAM_FOR_A_WHILE;
state_buf<=WRITE_BACK_REG0;
end
end
WRITE_BACK_REG1:
begin
write_data_fifo_in_en<=8'b0;//默认不往pcie_data_send_fifo发送数据
if(count>=512)//读512次256b的数据
begin
state <= UNLOCK_DRAM;
count<=0;
controller_command_fifo_in<= {WRITE, 37'b0, 3'b000,paddr,64'b0};
controller_command_fifo_in_en<=enable;
end
else begin
if(!write_data_fifo_full)begin
write_data_fifo_in_en<=enable;
write_data_fifo_in<=0;
count<=count+1;//计数接收多少个数据
state<=WRITE_BACK_REG1;
end
else state <= WRITE_BACK_REG1;
end
end
UNLOCK_DRAM_FOR_A_WHILE://2c
begin
release_dram <= 1;
count <= 0;
backup_or_checkcache<=0;
backup_or_io<=0;
state <= WAIT_DRAM_FOR_A_WHILE;
end
WAIT_DRAM_FOR_A_WHILE://2d
begin
release_dram <= 0;
if(count>=1023)
begin
dram_request <= 1;
count<=0;
state <= CHANCG_TO_STATE_BUF;
end
else
begin
count <= count+1;
state<=WAIT_DRAM_FOR_A_WHILE;
end
end
CHANCG_TO_STATE_BUF://2e
begin
if(dram_permit)
begin
dram_request <= 0;
backup_or_checkcache<=1;
backup_or_io<=1;
state <= state_buf;
end
else
state<=CHANCG_TO_STATE_BUF;
end
UNLOCK_DRAM://2f
begin
release_dram <= 1;
controller_command_fifo_in_en <= 0;
state <= FINISH;
end
CHECK_ENPTY_FLAG0://30
begin
backup_or_checkcache<=0;
backup_or_io<=0;
release_dram <= 0;
if(fifo_enpty_flag & state_check<=9)
state<=CHECK_ENPTY_FLAG1;
else
state<=CHECK_ENPTY_FLAG0;
end
CHECK_ENPTY_FLAG1://31
begin
if(count>=8)
begin
count<=0;
if(fifo_enpty_flag & state_check<=9)
begin
state<=CHECK_ENPTY_FLAG2;
dram_request <= 1;
end
else
begin
state<=CHECK_ENPTY_FLAG0;
end
end
else
begin
count<=count+1;
state<=CHECK_ENPTY_FLAG1;
end
end
CHECK_ENPTY_FLAG2://32
begin
if(dram_permit)
begin
backup_or_checkcache<=1;
backup_or_io<=1;
dram_request <= 0;
state<=state_buf;
end
else state <= CHECK_ENPTY_FLAG2;
end
FINISH://3f
begin
release_dram <= 0;
backup_or_checkcache<=0;
backup_or_io<=0;
state <= IDLE;
end
default: state <= IDLE;
endcase
end
end
endmodule
|
//
// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
//
// On Tue Feb 4 14:45:38 EST 2014
//
//
// Ports:
// Name I/O size props
// RDY_server_request_put O 1
// server_response_get O 153
// RDY_server_response_get O 1
// RDY_cpServer_request_put O 1 reg
// cpServer_response_get O 40 reg
// RDY_cpServer_response_get O 1 reg
// led O 2 reg
// wci_m_0_MCmd O 3
// wci_m_0_MAddrSpace O 1
// wci_m_0_MByteEn O 4
// wci_m_0_MAddr O 32
// wci_m_0_MData O 32 reg
// wci_m_0_MFlag O 2 reg
// wci_m_1_MCmd O 3
// wci_m_1_MAddrSpace O 1
// wci_m_1_MByteEn O 4
// wci_m_1_MAddr O 32
// wci_m_1_MData O 32 reg
// wci_m_1_MFlag O 2 reg
// wci_m_2_MCmd O 3
// wci_m_2_MAddrSpace O 1
// wci_m_2_MByteEn O 4
// wci_m_2_MAddr O 32
// wci_m_2_MData O 32 reg
// wci_m_2_MFlag O 2 reg
// wci_m_3_MCmd O 3
// wci_m_3_MAddrSpace O 1
// wci_m_3_MByteEn O 4
// wci_m_3_MAddr O 32
// wci_m_3_MData O 32 reg
// wci_m_3_MFlag O 2 reg
// wci_m_4_MCmd O 3
// wci_m_4_MAddrSpace O 1
// wci_m_4_MByteEn O 4
// wci_m_4_MAddr O 32
// wci_m_4_MData O 32 reg
// wci_m_4_MFlag O 2 reg
// cpNow O 64 reg
// RDY_cpNow O 1 const
// wsi_s_adc_SThreadBusy O 1 const
// wsi_s_adc_SReset_n O 1 const
// wsi_m_dac_MCmd O 3 const
// wsi_m_dac_MReqLast O 1 const
// wsi_m_dac_MBurstPrecise O 1 const
// wsi_m_dac_MBurstLength O 12 const
// wsi_m_dac_MData O 128 const
// wsi_m_dac_MByteEn O 16 const
// wsi_m_dac_MReqInfo O 8 const
// wsi_m_dac_MReset_n O 1 const
// wmemiM0_MCmd O 3 reg
// wmemiM0_MReqLast O 1 reg
// wmemiM0_MAddr O 36 reg
// wmemiM0_MBurstLength O 12 reg
// wmemiM0_MDataValid O 1 reg
// wmemiM0_MDataLast O 1 reg
// wmemiM0_MData O 128 reg
// wmemiM0_MDataByteEn O 16 reg
// wmemiM0_MReset_n O 1
// gps_ppsSyncOut O 1
// RST_N_wci_m_0 O 1 reset
// RST_N_wci_m_1 O 1 reset
// RST_N_wci_m_2 O 1 reset
// RST_N_wci_m_3 O 1 reset
// RST_N_wci_m_4 O 1 reset
// pciDevice I 16
// CLK_sys0_clk I 1 clock
// RST_N_sys0_rst I 1 reset
// CLK I 1 clock
// RST_N I 1 reset
// server_request_put I 153
// cpServer_request_put I 59 reg
// switch_x I 3 reg
// wci_m_0_SResp I 2
// wci_m_0_SData I 32
// wci_m_0_SFlag I 2 reg
// wci_m_1_SResp I 2
// wci_m_1_SData I 32
// wci_m_1_SFlag I 2 reg
// wci_m_2_SResp I 2
// wci_m_2_SData I 32
// wci_m_2_SFlag I 2 reg
// wci_m_3_SResp I 2
// wci_m_3_SData I 32
// wci_m_3_SFlag I 2 reg
// wci_m_4_SResp I 2
// wci_m_4_SData I 32
// wci_m_4_SFlag I 2 reg
// wsi_s_adc_MCmd I 3 unused
// wsi_s_adc_MBurstLength I 12 unused
// wsi_s_adc_MData I 128 unused
// wsi_s_adc_MByteEn I 16 unused
// wsi_s_adc_MReqInfo I 8 unused
// wmemiM0_SResp I 2
// wmemiM0_SData I 128
// gps_ppsSyncIn_x I 1 reg
// EN_server_request_put I 1
// EN_cpServer_request_put I 1
// wci_m_0_SThreadBusy I 1 reg
// wci_m_1_SThreadBusy I 1 reg
// wci_m_2_SThreadBusy I 1 reg
// wci_m_3_SThreadBusy I 1 reg
// wci_m_4_SThreadBusy I 1 reg
// wsi_s_adc_MReqLast I 1 unused
// wsi_s_adc_MBurstPrecise I 1 unused
// wsi_s_adc_MReset_n I 1 unused
// wsi_m_dac_SThreadBusy I 1 unused
// wsi_m_dac_SReset_n I 1 unused
// wmemiM0_SRespLast I 1
// wmemiM0_SCmdAccept I 1
// wmemiM0_SDataAccept I 1
// EN_server_response_get I 1
// EN_cpServer_response_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCTop16B(pciDevice,
CLK_sys0_clk,
RST_N_sys0_rst,
CLK,
RST_N,
server_request_put,
EN_server_request_put,
RDY_server_request_put,
EN_server_response_get,
server_response_get,
RDY_server_response_get,
cpServer_request_put,
EN_cpServer_request_put,
RDY_cpServer_request_put,
EN_cpServer_response_get,
cpServer_response_get,
RDY_cpServer_response_get,
led,
switch_x,
wci_m_0_MCmd,
wci_m_0_MAddrSpace,
wci_m_0_MByteEn,
wci_m_0_MAddr,
wci_m_0_MData,
wci_m_0_SResp,
wci_m_0_SData,
wci_m_0_SThreadBusy,
wci_m_0_SFlag,
wci_m_0_MFlag,
wci_m_1_MCmd,
wci_m_1_MAddrSpace,
wci_m_1_MByteEn,
wci_m_1_MAddr,
wci_m_1_MData,
wci_m_1_SResp,
wci_m_1_SData,
wci_m_1_SThreadBusy,
wci_m_1_SFlag,
wci_m_1_MFlag,
wci_m_2_MCmd,
wci_m_2_MAddrSpace,
wci_m_2_MByteEn,
wci_m_2_MAddr,
wci_m_2_MData,
wci_m_2_SResp,
wci_m_2_SData,
wci_m_2_SThreadBusy,
wci_m_2_SFlag,
wci_m_2_MFlag,
wci_m_3_MCmd,
wci_m_3_MAddrSpace,
wci_m_3_MByteEn,
wci_m_3_MAddr,
wci_m_3_MData,
wci_m_3_SResp,
wci_m_3_SData,
wci_m_3_SThreadBusy,
wci_m_3_SFlag,
wci_m_3_MFlag,
wci_m_4_MCmd,
wci_m_4_MAddrSpace,
wci_m_4_MByteEn,
wci_m_4_MAddr,
wci_m_4_MData,
wci_m_4_SResp,
wci_m_4_SData,
wci_m_4_SThreadBusy,
wci_m_4_SFlag,
wci_m_4_MFlag,
cpNow,
RDY_cpNow,
wsi_s_adc_MCmd,
wsi_s_adc_MReqLast,
wsi_s_adc_MBurstPrecise,
wsi_s_adc_MBurstLength,
wsi_s_adc_MData,
wsi_s_adc_MByteEn,
wsi_s_adc_MReqInfo,
wsi_s_adc_SThreadBusy,
wsi_s_adc_SReset_n,
wsi_s_adc_MReset_n,
wsi_m_dac_MCmd,
wsi_m_dac_MReqLast,
wsi_m_dac_MBurstPrecise,
wsi_m_dac_MBurstLength,
wsi_m_dac_MData,
wsi_m_dac_MByteEn,
wsi_m_dac_MReqInfo,
wsi_m_dac_SThreadBusy,
wsi_m_dac_MReset_n,
wsi_m_dac_SReset_n,
wmemiM0_MCmd,
wmemiM0_MReqLast,
wmemiM0_MAddr,
wmemiM0_MBurstLength,
wmemiM0_MDataValid,
wmemiM0_MDataLast,
wmemiM0_MData,
wmemiM0_MDataByteEn,
wmemiM0_SResp,
wmemiM0_SRespLast,
wmemiM0_SData,
wmemiM0_SCmdAccept,
wmemiM0_SDataAccept,
wmemiM0_MReset_n,
gps_ppsSyncIn_x,
gps_ppsSyncOut,
RST_N_wci_m_0,
RST_N_wci_m_1,
RST_N_wci_m_2,
RST_N_wci_m_3,
RST_N_wci_m_4);
input [15 : 0] pciDevice;
input CLK_sys0_clk;
input RST_N_sys0_rst;
input CLK;
input RST_N;
// action method server_request_put
input [152 : 0] server_request_put;
input EN_server_request_put;
output RDY_server_request_put;
// actionvalue method server_response_get
input EN_server_response_get;
output [152 : 0] server_response_get;
output RDY_server_response_get;
// action method cpServer_request_put
input [58 : 0] cpServer_request_put;
input EN_cpServer_request_put;
output RDY_cpServer_request_put;
// actionvalue method cpServer_response_get
input EN_cpServer_response_get;
output [39 : 0] cpServer_response_get;
output RDY_cpServer_response_get;
// value method led
output [1 : 0] led;
// action method switch
input [2 : 0] switch_x;
// value method wci_m_0_mCmd
output [2 : 0] wci_m_0_MCmd;
// value method wci_m_0_mAddrSpace
output wci_m_0_MAddrSpace;
// value method wci_m_0_mByteEn
output [3 : 0] wci_m_0_MByteEn;
// value method wci_m_0_mAddr
output [31 : 0] wci_m_0_MAddr;
// value method wci_m_0_mData
output [31 : 0] wci_m_0_MData;
// action method wci_m_0_sResp
input [1 : 0] wci_m_0_SResp;
// action method wci_m_0_sData
input [31 : 0] wci_m_0_SData;
// action method wci_m_0_sThreadBusy
input wci_m_0_SThreadBusy;
// action method wci_m_0_sFlag
input [1 : 0] wci_m_0_SFlag;
// value method wci_m_0_mFlag
output [1 : 0] wci_m_0_MFlag;
// value method wci_m_1_mCmd
output [2 : 0] wci_m_1_MCmd;
// value method wci_m_1_mAddrSpace
output wci_m_1_MAddrSpace;
// value method wci_m_1_mByteEn
output [3 : 0] wci_m_1_MByteEn;
// value method wci_m_1_mAddr
output [31 : 0] wci_m_1_MAddr;
// value method wci_m_1_mData
output [31 : 0] wci_m_1_MData;
// action method wci_m_1_sResp
input [1 : 0] wci_m_1_SResp;
// action method wci_m_1_sData
input [31 : 0] wci_m_1_SData;
// action method wci_m_1_sThreadBusy
input wci_m_1_SThreadBusy;
// action method wci_m_1_sFlag
input [1 : 0] wci_m_1_SFlag;
// value method wci_m_1_mFlag
output [1 : 0] wci_m_1_MFlag;
// value method wci_m_2_mCmd
output [2 : 0] wci_m_2_MCmd;
// value method wci_m_2_mAddrSpace
output wci_m_2_MAddrSpace;
// value method wci_m_2_mByteEn
output [3 : 0] wci_m_2_MByteEn;
// value method wci_m_2_mAddr
output [31 : 0] wci_m_2_MAddr;
// value method wci_m_2_mData
output [31 : 0] wci_m_2_MData;
// action method wci_m_2_sResp
input [1 : 0] wci_m_2_SResp;
// action method wci_m_2_sData
input [31 : 0] wci_m_2_SData;
// action method wci_m_2_sThreadBusy
input wci_m_2_SThreadBusy;
// action method wci_m_2_sFlag
input [1 : 0] wci_m_2_SFlag;
// value method wci_m_2_mFlag
output [1 : 0] wci_m_2_MFlag;
// value method wci_m_3_mCmd
output [2 : 0] wci_m_3_MCmd;
// value method wci_m_3_mAddrSpace
output wci_m_3_MAddrSpace;
// value method wci_m_3_mByteEn
output [3 : 0] wci_m_3_MByteEn;
// value method wci_m_3_mAddr
output [31 : 0] wci_m_3_MAddr;
// value method wci_m_3_mData
output [31 : 0] wci_m_3_MData;
// action method wci_m_3_sResp
input [1 : 0] wci_m_3_SResp;
// action method wci_m_3_sData
input [31 : 0] wci_m_3_SData;
// action method wci_m_3_sThreadBusy
input wci_m_3_SThreadBusy;
// action method wci_m_3_sFlag
input [1 : 0] wci_m_3_SFlag;
// value method wci_m_3_mFlag
output [1 : 0] wci_m_3_MFlag;
// value method wci_m_4_mCmd
output [2 : 0] wci_m_4_MCmd;
// value method wci_m_4_mAddrSpace
output wci_m_4_MAddrSpace;
// value method wci_m_4_mByteEn
output [3 : 0] wci_m_4_MByteEn;
// value method wci_m_4_mAddr
output [31 : 0] wci_m_4_MAddr;
// value method wci_m_4_mData
output [31 : 0] wci_m_4_MData;
// action method wci_m_4_sResp
input [1 : 0] wci_m_4_SResp;
// action method wci_m_4_sData
input [31 : 0] wci_m_4_SData;
// action method wci_m_4_sThreadBusy
input wci_m_4_SThreadBusy;
// action method wci_m_4_sFlag
input [1 : 0] wci_m_4_SFlag;
// value method wci_m_4_mFlag
output [1 : 0] wci_m_4_MFlag;
// value method cpNow
output [63 : 0] cpNow;
output RDY_cpNow;
// action method wsi_s_adc_mCmd
input [2 : 0] wsi_s_adc_MCmd;
// action method wsi_s_adc_mReqLast
input wsi_s_adc_MReqLast;
// action method wsi_s_adc_mBurstPrecise
input wsi_s_adc_MBurstPrecise;
// action method wsi_s_adc_mBurstLength
input [11 : 0] wsi_s_adc_MBurstLength;
// action method wsi_s_adc_mData
input [127 : 0] wsi_s_adc_MData;
// action method wsi_s_adc_mByteEn
input [15 : 0] wsi_s_adc_MByteEn;
// action method wsi_s_adc_mReqInfo
input [7 : 0] wsi_s_adc_MReqInfo;
// action method wsi_s_adc_mDataInfo
// value method wsi_s_adc_sThreadBusy
output wsi_s_adc_SThreadBusy;
// value method wsi_s_adc_sReset_n
output wsi_s_adc_SReset_n;
// action method wsi_s_adc_mReset_n
input wsi_s_adc_MReset_n;
// value method wsi_m_dac_mCmd
output [2 : 0] wsi_m_dac_MCmd;
// value method wsi_m_dac_mReqLast
output wsi_m_dac_MReqLast;
// value method wsi_m_dac_mBurstPrecise
output wsi_m_dac_MBurstPrecise;
// value method wsi_m_dac_mBurstLength
output [11 : 0] wsi_m_dac_MBurstLength;
// value method wsi_m_dac_mData
output [127 : 0] wsi_m_dac_MData;
// value method wsi_m_dac_mByteEn
output [15 : 0] wsi_m_dac_MByteEn;
// value method wsi_m_dac_mReqInfo
output [7 : 0] wsi_m_dac_MReqInfo;
// value method wsi_m_dac_mDataInfo
// action method wsi_m_dac_sThreadBusy
input wsi_m_dac_SThreadBusy;
// value method wsi_m_dac_mReset_n
output wsi_m_dac_MReset_n;
// action method wsi_m_dac_sReset_n
input wsi_m_dac_SReset_n;
// value method wmemiM0_mCmd
output [2 : 0] wmemiM0_MCmd;
// value method wmemiM0_mReqLast
output wmemiM0_MReqLast;
// value method wmemiM0_mAddr
output [35 : 0] wmemiM0_MAddr;
// value method wmemiM0_mBurstLength
output [11 : 0] wmemiM0_MBurstLength;
// value method wmemiM0_mDataValid
output wmemiM0_MDataValid;
// value method wmemiM0_mDataLast
output wmemiM0_MDataLast;
// value method wmemiM0_mData
output [127 : 0] wmemiM0_MData;
// value method wmemiM0_mDataByteEn
output [15 : 0] wmemiM0_MDataByteEn;
// action method wmemiM0_sResp
input [1 : 0] wmemiM0_SResp;
// action method wmemiM0_sRespLast
input wmemiM0_SRespLast;
// action method wmemiM0_sData
input [127 : 0] wmemiM0_SData;
// action method wmemiM0_sCmdAccept
input wmemiM0_SCmdAccept;
// action method wmemiM0_sDataAccept
input wmemiM0_SDataAccept;
// value method wmemiM0_mReset_n
output wmemiM0_MReset_n;
// action method gps_ppsSyncIn
input gps_ppsSyncIn_x;
// value method gps_ppsSyncOut
output gps_ppsSyncOut;
// output resets
output RST_N_wci_m_0;
output RST_N_wci_m_1;
output RST_N_wci_m_2;
output RST_N_wci_m_3;
output RST_N_wci_m_4;
// signals for module outputs
wire [152 : 0] server_response_get;
wire [127 : 0] wmemiM0_MData, wsi_m_dac_MData;
wire [63 : 0] cpNow;
wire [39 : 0] cpServer_response_get;
wire [35 : 0] wmemiM0_MAddr;
wire [31 : 0] wci_m_0_MAddr,
wci_m_0_MData,
wci_m_1_MAddr,
wci_m_1_MData,
wci_m_2_MAddr,
wci_m_2_MData,
wci_m_3_MAddr,
wci_m_3_MData,
wci_m_4_MAddr,
wci_m_4_MData;
wire [15 : 0] wmemiM0_MDataByteEn, wsi_m_dac_MByteEn;
wire [11 : 0] wmemiM0_MBurstLength, wsi_m_dac_MBurstLength;
wire [7 : 0] wsi_m_dac_MReqInfo;
wire [3 : 0] wci_m_0_MByteEn,
wci_m_1_MByteEn,
wci_m_2_MByteEn,
wci_m_3_MByteEn,
wci_m_4_MByteEn;
wire [2 : 0] wci_m_0_MCmd,
wci_m_1_MCmd,
wci_m_2_MCmd,
wci_m_3_MCmd,
wci_m_4_MCmd,
wmemiM0_MCmd,
wsi_m_dac_MCmd;
wire [1 : 0] led,
wci_m_0_MFlag,
wci_m_1_MFlag,
wci_m_2_MFlag,
wci_m_3_MFlag,
wci_m_4_MFlag;
wire RDY_cpNow,
RDY_cpServer_request_put,
RDY_cpServer_response_get,
RDY_server_request_put,
RDY_server_response_get,
RST_N_wci_m_0,
RST_N_wci_m_1,
RST_N_wci_m_2,
RST_N_wci_m_3,
RST_N_wci_m_4,
gps_ppsSyncOut,
wci_m_0_MAddrSpace,
wci_m_1_MAddrSpace,
wci_m_2_MAddrSpace,
wci_m_3_MAddrSpace,
wci_m_4_MAddrSpace,
wmemiM0_MDataLast,
wmemiM0_MDataValid,
wmemiM0_MReqLast,
wmemiM0_MReset_n,
wsi_m_dac_MBurstPrecise,
wsi_m_dac_MReqLast,
wsi_m_dac_MReset_n,
wsi_s_adc_SReset_n,
wsi_s_adc_SThreadBusy;
// inlined wires
wire wtiM_0_peerIsReady_1_wget,
wtiM_0_peerIsReady_1_whas,
wtiM_0_sThreadBusy_pw_whas,
wtiM_1_peerIsReady_1_wget,
wtiM_1_peerIsReady_1_whas,
wtiM_1_sThreadBusy_pw_whas,
wtiM_2_peerIsReady_1_wget,
wtiM_2_peerIsReady_1_whas,
wtiM_2_sThreadBusy_pw_whas;
// register wtiM_0_nowReq
reg [66 : 0] wtiM_0_nowReq;
wire [66 : 0] wtiM_0_nowReq_D_IN;
wire wtiM_0_nowReq_EN;
// register wtiM_0_peerIsReady
reg wtiM_0_peerIsReady;
wire wtiM_0_peerIsReady_D_IN, wtiM_0_peerIsReady_EN;
// register wtiM_0_sThreadBusy_d
reg wtiM_0_sThreadBusy_d;
wire wtiM_0_sThreadBusy_d_D_IN, wtiM_0_sThreadBusy_d_EN;
// register wtiM_1_nowReq
reg [66 : 0] wtiM_1_nowReq;
wire [66 : 0] wtiM_1_nowReq_D_IN;
wire wtiM_1_nowReq_EN;
// register wtiM_1_peerIsReady
reg wtiM_1_peerIsReady;
wire wtiM_1_peerIsReady_D_IN, wtiM_1_peerIsReady_EN;
// register wtiM_1_sThreadBusy_d
reg wtiM_1_sThreadBusy_d;
wire wtiM_1_sThreadBusy_d_D_IN, wtiM_1_sThreadBusy_d_EN;
// register wtiM_2_nowReq
reg [66 : 0] wtiM_2_nowReq;
wire [66 : 0] wtiM_2_nowReq_D_IN;
wire wtiM_2_nowReq_EN;
// register wtiM_2_peerIsReady
reg wtiM_2_peerIsReady;
wire wtiM_2_peerIsReady_D_IN, wtiM_2_peerIsReady_EN;
// register wtiM_2_sThreadBusy_d
reg wtiM_2_sThreadBusy_d;
wire wtiM_2_sThreadBusy_d_D_IN, wtiM_2_sThreadBusy_d_EN;
// ports of submodule app
wire [511 : 0] app_uuid;
wire [127 : 0] app_wmemiM0_MData,
app_wmemiM0_SData,
app_wmiM0_MData,
app_wmiM0_SData,
app_wmiM1_MData,
app_wmiM1_SData,
app_wsi_s_adc_MData;
wire [63 : 0] app_wti_s_0_MData, app_wti_s_1_MData, app_wti_s_2_MData;
wire [35 : 0] app_wmemiM0_MAddr;
wire [31 : 0] app_wci_s_0_MAddr,
app_wci_s_0_MData,
app_wci_s_0_SData,
app_wci_s_1_MAddr,
app_wci_s_1_MData,
app_wci_s_1_SData,
app_wci_s_2_MAddr,
app_wci_s_2_MData,
app_wci_s_2_SData,
app_wci_s_3_MAddr,
app_wci_s_3_MData,
app_wci_s_3_SData,
app_wci_s_4_MAddr,
app_wci_s_4_MData,
app_wci_s_4_SData,
app_wci_s_5_MAddr,
app_wci_s_5_MData,
app_wci_s_5_SData,
app_wci_s_6_MAddr,
app_wci_s_6_MData,
app_wci_s_6_SData,
app_wci_s_7_MAddr,
app_wci_s_7_MData,
app_wci_s_7_SData,
app_wmiM0_MFlag,
app_wmiM0_SFlag,
app_wmiM1_MFlag,
app_wmiM1_SFlag;
wire [15 : 0] app_wmemiM0_MDataByteEn,
app_wmiM0_MDataByteEn,
app_wmiM1_MDataByteEn,
app_wsi_s_adc_MByteEn;
wire [13 : 0] app_wmiM0_MAddr, app_wmiM1_MAddr;
wire [11 : 0] app_wmemiM0_MBurstLength,
app_wmiM0_MBurstLength,
app_wmiM1_MBurstLength,
app_wsi_s_adc_MBurstLength;
wire [7 : 0] app_wsi_s_adc_MReqInfo;
wire [3 : 0] app_wci_s_0_MByteEn,
app_wci_s_1_MByteEn,
app_wci_s_2_MByteEn,
app_wci_s_3_MByteEn,
app_wci_s_4_MByteEn,
app_wci_s_5_MByteEn,
app_wci_s_6_MByteEn,
app_wci_s_7_MByteEn;
wire [2 : 0] app_wci_s_0_MCmd,
app_wci_s_1_MCmd,
app_wci_s_2_MCmd,
app_wci_s_3_MCmd,
app_wci_s_4_MCmd,
app_wci_s_5_MCmd,
app_wci_s_6_MCmd,
app_wci_s_7_MCmd,
app_wmemiM0_MCmd,
app_wmiM0_MCmd,
app_wmiM1_MCmd,
app_wsi_s_adc_MCmd,
app_wti_s_0_MCmd,
app_wti_s_1_MCmd,
app_wti_s_2_MCmd;
wire [1 : 0] app_wci_s_0_MFlag,
app_wci_s_0_SFlag,
app_wci_s_0_SResp,
app_wci_s_1_MFlag,
app_wci_s_1_SFlag,
app_wci_s_1_SResp,
app_wci_s_2_MFlag,
app_wci_s_2_SFlag,
app_wci_s_2_SResp,
app_wci_s_3_MFlag,
app_wci_s_3_SFlag,
app_wci_s_3_SResp,
app_wci_s_4_MFlag,
app_wci_s_4_SFlag,
app_wci_s_4_SResp,
app_wci_s_5_MFlag,
app_wci_s_5_SFlag,
app_wci_s_5_SResp,
app_wci_s_6_MFlag,
app_wci_s_6_SFlag,
app_wci_s_6_SResp,
app_wci_s_7_MFlag,
app_wci_s_7_SFlag,
app_wci_s_7_SResp,
app_wmemiM0_SResp,
app_wmiM0_SResp,
app_wmiM1_SResp;
wire app_wci_s_0_MAddrSpace,
app_wci_s_0_SThreadBusy,
app_wci_s_1_MAddrSpace,
app_wci_s_1_SThreadBusy,
app_wci_s_2_MAddrSpace,
app_wci_s_2_SThreadBusy,
app_wci_s_3_MAddrSpace,
app_wci_s_3_SThreadBusy,
app_wci_s_4_MAddrSpace,
app_wci_s_4_SThreadBusy,
app_wci_s_5_MAddrSpace,
app_wci_s_5_SThreadBusy,
app_wci_s_6_MAddrSpace,
app_wci_s_6_SThreadBusy,
app_wci_s_7_MAddrSpace,
app_wci_s_7_SThreadBusy,
app_wmemiM0_MDataLast,
app_wmemiM0_MDataValid,
app_wmemiM0_MReqLast,
app_wmemiM0_MReset_n,
app_wmemiM0_SCmdAccept,
app_wmemiM0_SDataAccept,
app_wmemiM0_SRespLast,
app_wmiM0_MAddrSpace,
app_wmiM0_MDataLast,
app_wmiM0_MDataValid,
app_wmiM0_MReqInfo,
app_wmiM0_MReqLast,
app_wmiM0_MReset_n,
app_wmiM0_SDataThreadBusy,
app_wmiM0_SReset_n,
app_wmiM0_SRespLast,
app_wmiM0_SThreadBusy,
app_wmiM1_MAddrSpace,
app_wmiM1_MDataLast,
app_wmiM1_MDataValid,
app_wmiM1_MReqInfo,
app_wmiM1_MReqLast,
app_wmiM1_MReset_n,
app_wmiM1_SDataThreadBusy,
app_wmiM1_SReset_n,
app_wmiM1_SRespLast,
app_wmiM1_SThreadBusy,
app_wsi_m_dac_SReset_n,
app_wsi_m_dac_SThreadBusy,
app_wsi_s_adc_MBurstPrecise,
app_wsi_s_adc_MReqLast,
app_wsi_s_adc_MReset_n,
app_wti_s_0_SReset_n,
app_wti_s_0_SThreadBusy,
app_wti_s_1_SReset_n,
app_wti_s_1_SThreadBusy,
app_wti_s_2_SReset_n,
app_wti_s_2_SThreadBusy;
// ports of submodule ctNow
wire [63 : 0] ctNow_dD_OUT, ctNow_sD_IN;
wire ctNow_sEN, ctNow_sRDY;
// ports of submodule inf
wire [511 : 0] inf_uuid_arg;
wire [152 : 0] inf_server_request_put, inf_server_response_get;
wire [127 : 0] inf_wmiDP0_MData,
inf_wmiDP0_SData,
inf_wmiDP1_MData,
inf_wmiDP1_SData;
wire [63 : 0] inf_cpNow;
wire [58 : 0] inf_cpServer_request_put;
wire [39 : 0] inf_cpServer_response_get;
wire [31 : 0] inf_wci_m_0_MAddr,
inf_wci_m_0_MData,
inf_wci_m_0_SData,
inf_wci_m_10_MAddr,
inf_wci_m_10_MData,
inf_wci_m_10_SData,
inf_wci_m_11_MAddr,
inf_wci_m_11_MData,
inf_wci_m_11_SData,
inf_wci_m_12_MAddr,
inf_wci_m_12_MData,
inf_wci_m_12_SData,
inf_wci_m_1_MAddr,
inf_wci_m_1_MData,
inf_wci_m_1_SData,
inf_wci_m_2_MAddr,
inf_wci_m_2_MData,
inf_wci_m_2_SData,
inf_wci_m_3_MAddr,
inf_wci_m_3_MData,
inf_wci_m_3_SData,
inf_wci_m_4_MAddr,
inf_wci_m_4_MData,
inf_wci_m_4_SData,
inf_wci_m_5_MAddr,
inf_wci_m_5_MData,
inf_wci_m_5_SData,
inf_wci_m_6_MAddr,
inf_wci_m_6_MData,
inf_wci_m_6_SData,
inf_wci_m_7_MAddr,
inf_wci_m_7_MData,
inf_wci_m_7_SData,
inf_wci_m_8_MAddr,
inf_wci_m_8_MData,
inf_wci_m_8_SData,
inf_wci_m_9_MAddr,
inf_wci_m_9_MData,
inf_wci_m_9_SData,
inf_wmiDP0_SFlag,
inf_wmiDP0_arg_mFlag,
inf_wmiDP1_SFlag,
inf_wmiDP1_arg_mFlag;
wire [15 : 0] inf_wmiDP0_MDataByteEn, inf_wmiDP1_MDataByteEn;
wire [13 : 0] inf_wmiDP0_MAddr, inf_wmiDP1_MAddr;
wire [11 : 0] inf_wmiDP0_MBurstLength, inf_wmiDP1_MBurstLength;
wire [3 : 0] inf_wci_m_0_MByteEn,
inf_wci_m_10_MByteEn,
inf_wci_m_11_MByteEn,
inf_wci_m_12_MByteEn,
inf_wci_m_1_MByteEn,
inf_wci_m_2_MByteEn,
inf_wci_m_3_MByteEn,
inf_wci_m_4_MByteEn,
inf_wci_m_5_MByteEn,
inf_wci_m_6_MByteEn,
inf_wci_m_7_MByteEn,
inf_wci_m_8_MByteEn,
inf_wci_m_9_MByteEn;
wire [2 : 0] inf_switch_x,
inf_wci_m_0_MCmd,
inf_wci_m_10_MCmd,
inf_wci_m_11_MCmd,
inf_wci_m_12_MCmd,
inf_wci_m_1_MCmd,
inf_wci_m_2_MCmd,
inf_wci_m_3_MCmd,
inf_wci_m_4_MCmd,
inf_wci_m_5_MCmd,
inf_wci_m_6_MCmd,
inf_wci_m_7_MCmd,
inf_wci_m_8_MCmd,
inf_wci_m_9_MCmd,
inf_wmiDP0_MCmd,
inf_wmiDP1_MCmd;
wire [1 : 0] inf_led,
inf_wci_m_0_MFlag,
inf_wci_m_0_SFlag,
inf_wci_m_0_SResp,
inf_wci_m_10_MFlag,
inf_wci_m_10_SFlag,
inf_wci_m_10_SResp,
inf_wci_m_11_MFlag,
inf_wci_m_11_SFlag,
inf_wci_m_11_SResp,
inf_wci_m_12_MFlag,
inf_wci_m_12_SFlag,
inf_wci_m_12_SResp,
inf_wci_m_1_MFlag,
inf_wci_m_1_SFlag,
inf_wci_m_1_SResp,
inf_wci_m_2_MFlag,
inf_wci_m_2_SFlag,
inf_wci_m_2_SResp,
inf_wci_m_3_MFlag,
inf_wci_m_3_SFlag,
inf_wci_m_3_SResp,
inf_wci_m_4_MFlag,
inf_wci_m_4_SFlag,
inf_wci_m_4_SResp,
inf_wci_m_5_MFlag,
inf_wci_m_5_SFlag,
inf_wci_m_5_SResp,
inf_wci_m_6_MFlag,
inf_wci_m_6_SFlag,
inf_wci_m_6_SResp,
inf_wci_m_7_MFlag,
inf_wci_m_7_SFlag,
inf_wci_m_7_SResp,
inf_wci_m_8_MFlag,
inf_wci_m_8_SFlag,
inf_wci_m_8_SResp,
inf_wci_m_9_MFlag,
inf_wci_m_9_SFlag,
inf_wci_m_9_SResp,
inf_wmiDP0_SResp,
inf_wmiDP1_SResp;
wire inf_EN_cpServer_request_put,
inf_EN_cpServer_response_get,
inf_EN_server_request_put,
inf_EN_server_response_get,
inf_RDY_cpServer_request_put,
inf_RDY_cpServer_response_get,
inf_RDY_server_request_put,
inf_RDY_server_response_get,
inf_RST_N_wci_m_0,
inf_RST_N_wci_m_1,
inf_RST_N_wci_m_10,
inf_RST_N_wci_m_11,
inf_RST_N_wci_m_12,
inf_RST_N_wci_m_2,
inf_RST_N_wci_m_3,
inf_RST_N_wci_m_4,
inf_RST_N_wci_m_5,
inf_RST_N_wci_m_6,
inf_RST_N_wci_m_7,
inf_RST_N_wci_m_8,
inf_RST_N_wci_m_9,
inf_gps_ppsSyncIn_x,
inf_gps_ppsSyncOut,
inf_wci_m_0_MAddrSpace,
inf_wci_m_0_SThreadBusy,
inf_wci_m_10_MAddrSpace,
inf_wci_m_10_SThreadBusy,
inf_wci_m_11_MAddrSpace,
inf_wci_m_11_SThreadBusy,
inf_wci_m_12_MAddrSpace,
inf_wci_m_12_SThreadBusy,
inf_wci_m_1_MAddrSpace,
inf_wci_m_1_SThreadBusy,
inf_wci_m_2_MAddrSpace,
inf_wci_m_2_SThreadBusy,
inf_wci_m_3_MAddrSpace,
inf_wci_m_3_SThreadBusy,
inf_wci_m_4_MAddrSpace,
inf_wci_m_4_SThreadBusy,
inf_wci_m_5_MAddrSpace,
inf_wci_m_5_SThreadBusy,
inf_wci_m_6_MAddrSpace,
inf_wci_m_6_SThreadBusy,
inf_wci_m_7_MAddrSpace,
inf_wci_m_7_SThreadBusy,
inf_wci_m_8_MAddrSpace,
inf_wci_m_8_SThreadBusy,
inf_wci_m_9_MAddrSpace,
inf_wci_m_9_SThreadBusy,
inf_wmiDP0_MAddrSpace,
inf_wmiDP0_MDataLast,
inf_wmiDP0_MDataValid,
inf_wmiDP0_MReqInfo,
inf_wmiDP0_MReqLast,
inf_wmiDP0_MReset_n,
inf_wmiDP0_SDataThreadBusy,
inf_wmiDP0_SReset_n,
inf_wmiDP0_SRespLast,
inf_wmiDP0_SThreadBusy,
inf_wmiDP1_MAddrSpace,
inf_wmiDP1_MDataLast,
inf_wmiDP1_MDataValid,
inf_wmiDP1_MReqInfo,
inf_wmiDP1_MReqLast,
inf_wmiDP1_MReset_n,
inf_wmiDP1_SDataThreadBusy,
inf_wmiDP1_SReset_n,
inf_wmiDP1_SRespLast,
inf_wmiDP1_SThreadBusy;
// output resets
assign RST_N_wci_m_0 = inf_RST_N_wci_m_8 ;
assign RST_N_wci_m_1 = inf_RST_N_wci_m_9 ;
assign RST_N_wci_m_2 = inf_RST_N_wci_m_10 ;
assign RST_N_wci_m_3 = inf_RST_N_wci_m_11 ;
assign RST_N_wci_m_4 = inf_RST_N_wci_m_12 ;
// action method server_request_put
assign RDY_server_request_put = inf_RDY_server_request_put ;
// actionvalue method server_response_get
assign server_response_get = inf_server_response_get ;
assign RDY_server_response_get = inf_RDY_server_response_get ;
// action method cpServer_request_put
assign RDY_cpServer_request_put = inf_RDY_cpServer_request_put ;
// actionvalue method cpServer_response_get
assign cpServer_response_get = inf_cpServer_response_get ;
assign RDY_cpServer_response_get = inf_RDY_cpServer_response_get ;
// value method led
assign led = inf_led ;
// value method wci_m_0_mCmd
assign wci_m_0_MCmd = inf_wci_m_8_MCmd ;
// value method wci_m_0_mAddrSpace
assign wci_m_0_MAddrSpace = inf_wci_m_8_MAddrSpace ;
// value method wci_m_0_mByteEn
assign wci_m_0_MByteEn = inf_wci_m_8_MByteEn ;
// value method wci_m_0_mAddr
assign wci_m_0_MAddr = inf_wci_m_8_MAddr ;
// value method wci_m_0_mData
assign wci_m_0_MData = inf_wci_m_8_MData ;
// value method wci_m_0_mFlag
assign wci_m_0_MFlag = inf_wci_m_8_MFlag ;
// value method wci_m_1_mCmd
assign wci_m_1_MCmd = inf_wci_m_9_MCmd ;
// value method wci_m_1_mAddrSpace
assign wci_m_1_MAddrSpace = inf_wci_m_9_MAddrSpace ;
// value method wci_m_1_mByteEn
assign wci_m_1_MByteEn = inf_wci_m_9_MByteEn ;
// value method wci_m_1_mAddr
assign wci_m_1_MAddr = inf_wci_m_9_MAddr ;
// value method wci_m_1_mData
assign wci_m_1_MData = inf_wci_m_9_MData ;
// value method wci_m_1_mFlag
assign wci_m_1_MFlag = inf_wci_m_9_MFlag ;
// value method wci_m_2_mCmd
assign wci_m_2_MCmd = inf_wci_m_10_MCmd ;
// value method wci_m_2_mAddrSpace
assign wci_m_2_MAddrSpace = inf_wci_m_10_MAddrSpace ;
// value method wci_m_2_mByteEn
assign wci_m_2_MByteEn = inf_wci_m_10_MByteEn ;
// value method wci_m_2_mAddr
assign wci_m_2_MAddr = inf_wci_m_10_MAddr ;
// value method wci_m_2_mData
assign wci_m_2_MData = inf_wci_m_10_MData ;
// value method wci_m_2_mFlag
assign wci_m_2_MFlag = inf_wci_m_10_MFlag ;
// value method wci_m_3_mCmd
assign wci_m_3_MCmd = inf_wci_m_11_MCmd ;
// value method wci_m_3_mAddrSpace
assign wci_m_3_MAddrSpace = inf_wci_m_11_MAddrSpace ;
// value method wci_m_3_mByteEn
assign wci_m_3_MByteEn = inf_wci_m_11_MByteEn ;
// value method wci_m_3_mAddr
assign wci_m_3_MAddr = inf_wci_m_11_MAddr ;
// value method wci_m_3_mData
assign wci_m_3_MData = inf_wci_m_11_MData ;
// value method wci_m_3_mFlag
assign wci_m_3_MFlag = inf_wci_m_11_MFlag ;
// value method wci_m_4_mCmd
assign wci_m_4_MCmd = inf_wci_m_12_MCmd ;
// value method wci_m_4_mAddrSpace
assign wci_m_4_MAddrSpace = inf_wci_m_12_MAddrSpace ;
// value method wci_m_4_mByteEn
assign wci_m_4_MByteEn = inf_wci_m_12_MByteEn ;
// value method wci_m_4_mAddr
assign wci_m_4_MAddr = inf_wci_m_12_MAddr ;
// value method wci_m_4_mData
assign wci_m_4_MData = inf_wci_m_12_MData ;
// value method wci_m_4_mFlag
assign wci_m_4_MFlag = inf_wci_m_12_MFlag ;
// value method cpNow
assign cpNow = inf_cpNow ;
assign RDY_cpNow = 1'd1 ;
// value method wsi_s_adc_sThreadBusy
assign wsi_s_adc_SThreadBusy = 1'h0 ;
// value method wsi_s_adc_sReset_n
assign wsi_s_adc_SReset_n = 1'h0 ;
// value method wsi_m_dac_mCmd
assign wsi_m_dac_MCmd = 3'h2 ;
// value method wsi_m_dac_mReqLast
assign wsi_m_dac_MReqLast = 1'h0 ;
// value method wsi_m_dac_mBurstPrecise
assign wsi_m_dac_MBurstPrecise = 1'h0 ;
// value method wsi_m_dac_mBurstLength
assign wsi_m_dac_MBurstLength = 12'hAAA ;
// value method wsi_m_dac_mData
assign wsi_m_dac_MData = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
// value method wsi_m_dac_mByteEn
assign wsi_m_dac_MByteEn = 16'hAAAA ;
// value method wsi_m_dac_mReqInfo
assign wsi_m_dac_MReqInfo = 8'hAA ;
// value method wsi_m_dac_mReset_n
assign wsi_m_dac_MReset_n = 1'h0 ;
// value method wmemiM0_mCmd
assign wmemiM0_MCmd = app_wmemiM0_MCmd ;
// value method wmemiM0_mReqLast
assign wmemiM0_MReqLast = app_wmemiM0_MReqLast ;
// value method wmemiM0_mAddr
assign wmemiM0_MAddr = app_wmemiM0_MAddr ;
// value method wmemiM0_mBurstLength
assign wmemiM0_MBurstLength = app_wmemiM0_MBurstLength ;
// value method wmemiM0_mDataValid
assign wmemiM0_MDataValid = app_wmemiM0_MDataValid ;
// value method wmemiM0_mDataLast
assign wmemiM0_MDataLast = app_wmemiM0_MDataLast ;
// value method wmemiM0_mData
assign wmemiM0_MData = app_wmemiM0_MData ;
// value method wmemiM0_mDataByteEn
assign wmemiM0_MDataByteEn = app_wmemiM0_MDataByteEn ;
// value method wmemiM0_mReset_n
assign wmemiM0_MReset_n = app_wmemiM0_MReset_n ;
// value method gps_ppsSyncOut
assign gps_ppsSyncOut = inf_gps_ppsSyncOut ;
// submodule app
mkOCApp16B #(.hasDebugLogic(1'd1)) app(.RST_N_rst_0(inf_RST_N_wci_m_0),
.RST_N_rst_1(inf_RST_N_wci_m_1),
.RST_N_rst_2(inf_RST_N_wci_m_2),
.RST_N_rst_3(inf_RST_N_wci_m_3),
.RST_N_rst_4(inf_RST_N_wci_m_4),
.RST_N_rst_5(inf_RST_N_wci_m_5),
.RST_N_rst_6(inf_RST_N_wci_m_6),
.RST_N_rst_7(inf_RST_N_wci_m_7),
.CLK(CLK),
.RST_N(RST_N),
.wci_s_0_MAddr(app_wci_s_0_MAddr),
.wci_s_0_MAddrSpace(app_wci_s_0_MAddrSpace),
.wci_s_0_MByteEn(app_wci_s_0_MByteEn),
.wci_s_0_MCmd(app_wci_s_0_MCmd),
.wci_s_0_MData(app_wci_s_0_MData),
.wci_s_0_MFlag(app_wci_s_0_MFlag),
.wci_s_1_MAddr(app_wci_s_1_MAddr),
.wci_s_1_MAddrSpace(app_wci_s_1_MAddrSpace),
.wci_s_1_MByteEn(app_wci_s_1_MByteEn),
.wci_s_1_MCmd(app_wci_s_1_MCmd),
.wci_s_1_MData(app_wci_s_1_MData),
.wci_s_1_MFlag(app_wci_s_1_MFlag),
.wci_s_2_MAddr(app_wci_s_2_MAddr),
.wci_s_2_MAddrSpace(app_wci_s_2_MAddrSpace),
.wci_s_2_MByteEn(app_wci_s_2_MByteEn),
.wci_s_2_MCmd(app_wci_s_2_MCmd),
.wci_s_2_MData(app_wci_s_2_MData),
.wci_s_2_MFlag(app_wci_s_2_MFlag),
.wci_s_3_MAddr(app_wci_s_3_MAddr),
.wci_s_3_MAddrSpace(app_wci_s_3_MAddrSpace),
.wci_s_3_MByteEn(app_wci_s_3_MByteEn),
.wci_s_3_MCmd(app_wci_s_3_MCmd),
.wci_s_3_MData(app_wci_s_3_MData),
.wci_s_3_MFlag(app_wci_s_3_MFlag),
.wci_s_4_MAddr(app_wci_s_4_MAddr),
.wci_s_4_MAddrSpace(app_wci_s_4_MAddrSpace),
.wci_s_4_MByteEn(app_wci_s_4_MByteEn),
.wci_s_4_MCmd(app_wci_s_4_MCmd),
.wci_s_4_MData(app_wci_s_4_MData),
.wci_s_4_MFlag(app_wci_s_4_MFlag),
.wci_s_5_MAddr(app_wci_s_5_MAddr),
.wci_s_5_MAddrSpace(app_wci_s_5_MAddrSpace),
.wci_s_5_MByteEn(app_wci_s_5_MByteEn),
.wci_s_5_MCmd(app_wci_s_5_MCmd),
.wci_s_5_MData(app_wci_s_5_MData),
.wci_s_5_MFlag(app_wci_s_5_MFlag),
.wci_s_6_MAddr(app_wci_s_6_MAddr),
.wci_s_6_MAddrSpace(app_wci_s_6_MAddrSpace),
.wci_s_6_MByteEn(app_wci_s_6_MByteEn),
.wci_s_6_MCmd(app_wci_s_6_MCmd),
.wci_s_6_MData(app_wci_s_6_MData),
.wci_s_6_MFlag(app_wci_s_6_MFlag),
.wci_s_7_MAddr(app_wci_s_7_MAddr),
.wci_s_7_MAddrSpace(app_wci_s_7_MAddrSpace),
.wci_s_7_MByteEn(app_wci_s_7_MByteEn),
.wci_s_7_MCmd(app_wci_s_7_MCmd),
.wci_s_7_MData(app_wci_s_7_MData),
.wci_s_7_MFlag(app_wci_s_7_MFlag),
.wmemiM0_SData(app_wmemiM0_SData),
.wmemiM0_SResp(app_wmemiM0_SResp),
.wmiM0_SData(app_wmiM0_SData),
.wmiM0_SFlag(app_wmiM0_SFlag),
.wmiM0_SResp(app_wmiM0_SResp),
.wmiM1_SData(app_wmiM1_SData),
.wmiM1_SFlag(app_wmiM1_SFlag),
.wmiM1_SResp(app_wmiM1_SResp),
.wsi_s_adc_MBurstLength(app_wsi_s_adc_MBurstLength),
.wsi_s_adc_MByteEn(app_wsi_s_adc_MByteEn),
.wsi_s_adc_MCmd(app_wsi_s_adc_MCmd),
.wsi_s_adc_MData(app_wsi_s_adc_MData),
.wsi_s_adc_MReqInfo(app_wsi_s_adc_MReqInfo),
.wti_s_0_MCmd(app_wti_s_0_MCmd),
.wti_s_0_MData(app_wti_s_0_MData),
.wti_s_1_MCmd(app_wti_s_1_MCmd),
.wti_s_1_MData(app_wti_s_1_MData),
.wti_s_2_MCmd(app_wti_s_2_MCmd),
.wti_s_2_MData(app_wti_s_2_MData),
.wmiM0_SThreadBusy(app_wmiM0_SThreadBusy),
.wmiM0_SDataThreadBusy(app_wmiM0_SDataThreadBusy),
.wmiM0_SRespLast(app_wmiM0_SRespLast),
.wmiM0_SReset_n(app_wmiM0_SReset_n),
.wmiM1_SThreadBusy(app_wmiM1_SThreadBusy),
.wmiM1_SDataThreadBusy(app_wmiM1_SDataThreadBusy),
.wmiM1_SRespLast(app_wmiM1_SRespLast),
.wmiM1_SReset_n(app_wmiM1_SReset_n),
.wmemiM0_SRespLast(app_wmemiM0_SRespLast),
.wmemiM0_SCmdAccept(app_wmemiM0_SCmdAccept),
.wmemiM0_SDataAccept(app_wmemiM0_SDataAccept),
.wsi_s_adc_MReqLast(app_wsi_s_adc_MReqLast),
.wsi_s_adc_MBurstPrecise(app_wsi_s_adc_MBurstPrecise),
.wsi_s_adc_MReset_n(app_wsi_s_adc_MReset_n),
.wsi_m_dac_SThreadBusy(app_wsi_m_dac_SThreadBusy),
.wsi_m_dac_SReset_n(app_wsi_m_dac_SReset_n),
.wci_s_0_SResp(app_wci_s_0_SResp),
.wci_s_0_SData(app_wci_s_0_SData),
.wci_s_0_SThreadBusy(app_wci_s_0_SThreadBusy),
.wci_s_0_SFlag(app_wci_s_0_SFlag),
.wci_s_1_SResp(app_wci_s_1_SResp),
.wci_s_1_SData(app_wci_s_1_SData),
.wci_s_1_SThreadBusy(app_wci_s_1_SThreadBusy),
.wci_s_1_SFlag(app_wci_s_1_SFlag),
.wci_s_2_SResp(app_wci_s_2_SResp),
.wci_s_2_SData(app_wci_s_2_SData),
.wci_s_2_SThreadBusy(app_wci_s_2_SThreadBusy),
.wci_s_2_SFlag(app_wci_s_2_SFlag),
.wci_s_3_SResp(app_wci_s_3_SResp),
.wci_s_3_SData(app_wci_s_3_SData),
.wci_s_3_SThreadBusy(app_wci_s_3_SThreadBusy),
.wci_s_3_SFlag(app_wci_s_3_SFlag),
.wci_s_4_SResp(app_wci_s_4_SResp),
.wci_s_4_SData(app_wci_s_4_SData),
.wci_s_4_SThreadBusy(app_wci_s_4_SThreadBusy),
.wci_s_4_SFlag(app_wci_s_4_SFlag),
.wci_s_5_SResp(app_wci_s_5_SResp),
.wci_s_5_SData(app_wci_s_5_SData),
.wci_s_5_SThreadBusy(app_wci_s_5_SThreadBusy),
.wci_s_5_SFlag(app_wci_s_5_SFlag),
.wci_s_6_SResp(app_wci_s_6_SResp),
.wci_s_6_SData(app_wci_s_6_SData),
.wci_s_6_SThreadBusy(app_wci_s_6_SThreadBusy),
.wci_s_6_SFlag(app_wci_s_6_SFlag),
.wci_s_7_SResp(app_wci_s_7_SResp),
.wci_s_7_SData(app_wci_s_7_SData),
.wci_s_7_SThreadBusy(app_wci_s_7_SThreadBusy),
.wci_s_7_SFlag(app_wci_s_7_SFlag),
.wti_s_0_SThreadBusy(app_wti_s_0_SThreadBusy),
.wti_s_0_SReset_n(app_wti_s_0_SReset_n),
.wti_s_1_SThreadBusy(app_wti_s_1_SThreadBusy),
.wti_s_1_SReset_n(app_wti_s_1_SReset_n),
.wti_s_2_SThreadBusy(app_wti_s_2_SThreadBusy),
.wti_s_2_SReset_n(app_wti_s_2_SReset_n),
.wmiM0_MCmd(app_wmiM0_MCmd),
.wmiM0_MReqLast(app_wmiM0_MReqLast),
.wmiM0_MReqInfo(app_wmiM0_MReqInfo),
.wmiM0_MAddrSpace(app_wmiM0_MAddrSpace),
.wmiM0_MAddr(app_wmiM0_MAddr),
.wmiM0_MBurstLength(app_wmiM0_MBurstLength),
.wmiM0_MDataValid(app_wmiM0_MDataValid),
.wmiM0_MDataLast(app_wmiM0_MDataLast),
.wmiM0_MData(app_wmiM0_MData),
.wmiM0_MDataByteEn(app_wmiM0_MDataByteEn),
.wmiM0_MFlag(app_wmiM0_MFlag),
.wmiM0_MReset_n(app_wmiM0_MReset_n),
.wmiM1_MCmd(app_wmiM1_MCmd),
.wmiM1_MReqLast(app_wmiM1_MReqLast),
.wmiM1_MReqInfo(app_wmiM1_MReqInfo),
.wmiM1_MAddrSpace(app_wmiM1_MAddrSpace),
.wmiM1_MAddr(app_wmiM1_MAddr),
.wmiM1_MBurstLength(app_wmiM1_MBurstLength),
.wmiM1_MDataValid(app_wmiM1_MDataValid),
.wmiM1_MDataLast(app_wmiM1_MDataLast),
.wmiM1_MData(app_wmiM1_MData),
.wmiM1_MDataByteEn(app_wmiM1_MDataByteEn),
.wmiM1_MFlag(app_wmiM1_MFlag),
.wmiM1_MReset_n(app_wmiM1_MReset_n),
.wmemiM0_MCmd(app_wmemiM0_MCmd),
.wmemiM0_MReqLast(app_wmemiM0_MReqLast),
.wmemiM0_MAddr(app_wmemiM0_MAddr),
.wmemiM0_MBurstLength(app_wmemiM0_MBurstLength),
.wmemiM0_MDataValid(app_wmemiM0_MDataValid),
.wmemiM0_MDataLast(app_wmemiM0_MDataLast),
.wmemiM0_MData(app_wmemiM0_MData),
.wmemiM0_MDataByteEn(app_wmemiM0_MDataByteEn),
.wmemiM0_MReset_n(app_wmemiM0_MReset_n),
.wsi_s_adc_SThreadBusy(),
.wsi_s_adc_SReset_n(),
.wsi_m_dac_MCmd(),
.wsi_m_dac_MReqLast(),
.wsi_m_dac_MBurstPrecise(),
.wsi_m_dac_MBurstLength(),
.wsi_m_dac_MData(),
.wsi_m_dac_MByteEn(),
.wsi_m_dac_MReqInfo(),
.wsi_m_dac_MReset_n(),
.uuid(app_uuid));
// submodule ctNow
SyncRegister #(.width(32'd64), .init(64'd0)) ctNow(.sCLK(CLK_sys0_clk),
.dCLK(CLK),
.sRST(RST_N_sys0_rst),
.sD_IN(ctNow_sD_IN),
.sEN(ctNow_sEN),
.dD_OUT(ctNow_dD_OUT),
.sRDY(ctNow_sRDY));
// submodule inf
mkOCInf16B inf(.pciDevice(pciDevice),
.CLK_sys0_clk(CLK_sys0_clk),
.RST_N_sys0_rst(RST_N_sys0_rst),
.CLK(CLK),
.RST_N(RST_N),
.cpServer_request_put(inf_cpServer_request_put),
.gps_ppsSyncIn_x(inf_gps_ppsSyncIn_x),
.server_request_put(inf_server_request_put),
.switch_x(inf_switch_x),
.uuid_arg(inf_uuid_arg),
.wci_m_0_SData(inf_wci_m_0_SData),
.wci_m_0_SFlag(inf_wci_m_0_SFlag),
.wci_m_0_SResp(inf_wci_m_0_SResp),
.wci_m_10_SData(inf_wci_m_10_SData),
.wci_m_10_SFlag(inf_wci_m_10_SFlag),
.wci_m_10_SResp(inf_wci_m_10_SResp),
.wci_m_11_SData(inf_wci_m_11_SData),
.wci_m_11_SFlag(inf_wci_m_11_SFlag),
.wci_m_11_SResp(inf_wci_m_11_SResp),
.wci_m_12_SData(inf_wci_m_12_SData),
.wci_m_12_SFlag(inf_wci_m_12_SFlag),
.wci_m_12_SResp(inf_wci_m_12_SResp),
.wci_m_1_SData(inf_wci_m_1_SData),
.wci_m_1_SFlag(inf_wci_m_1_SFlag),
.wci_m_1_SResp(inf_wci_m_1_SResp),
.wci_m_2_SData(inf_wci_m_2_SData),
.wci_m_2_SFlag(inf_wci_m_2_SFlag),
.wci_m_2_SResp(inf_wci_m_2_SResp),
.wci_m_3_SData(inf_wci_m_3_SData),
.wci_m_3_SFlag(inf_wci_m_3_SFlag),
.wci_m_3_SResp(inf_wci_m_3_SResp),
.wci_m_4_SData(inf_wci_m_4_SData),
.wci_m_4_SFlag(inf_wci_m_4_SFlag),
.wci_m_4_SResp(inf_wci_m_4_SResp),
.wci_m_5_SData(inf_wci_m_5_SData),
.wci_m_5_SFlag(inf_wci_m_5_SFlag),
.wci_m_5_SResp(inf_wci_m_5_SResp),
.wci_m_6_SData(inf_wci_m_6_SData),
.wci_m_6_SFlag(inf_wci_m_6_SFlag),
.wci_m_6_SResp(inf_wci_m_6_SResp),
.wci_m_7_SData(inf_wci_m_7_SData),
.wci_m_7_SFlag(inf_wci_m_7_SFlag),
.wci_m_7_SResp(inf_wci_m_7_SResp),
.wci_m_8_SData(inf_wci_m_8_SData),
.wci_m_8_SFlag(inf_wci_m_8_SFlag),
.wci_m_8_SResp(inf_wci_m_8_SResp),
.wci_m_9_SData(inf_wci_m_9_SData),
.wci_m_9_SFlag(inf_wci_m_9_SFlag),
.wci_m_9_SResp(inf_wci_m_9_SResp),
.wmiDP0_MAddr(inf_wmiDP0_MAddr),
.wmiDP0_MAddrSpace(inf_wmiDP0_MAddrSpace),
.wmiDP0_MBurstLength(inf_wmiDP0_MBurstLength),
.wmiDP0_MCmd(inf_wmiDP0_MCmd),
.wmiDP0_MData(inf_wmiDP0_MData),
.wmiDP0_MDataByteEn(inf_wmiDP0_MDataByteEn),
.wmiDP0_MReqInfo(inf_wmiDP0_MReqInfo),
.wmiDP0_arg_mFlag(inf_wmiDP0_arg_mFlag),
.wmiDP1_MAddr(inf_wmiDP1_MAddr),
.wmiDP1_MAddrSpace(inf_wmiDP1_MAddrSpace),
.wmiDP1_MBurstLength(inf_wmiDP1_MBurstLength),
.wmiDP1_MCmd(inf_wmiDP1_MCmd),
.wmiDP1_MData(inf_wmiDP1_MData),
.wmiDP1_MDataByteEn(inf_wmiDP1_MDataByteEn),
.wmiDP1_MReqInfo(inf_wmiDP1_MReqInfo),
.wmiDP1_arg_mFlag(inf_wmiDP1_arg_mFlag),
.EN_server_request_put(inf_EN_server_request_put),
.EN_server_response_get(inf_EN_server_response_get),
.EN_cpServer_request_put(inf_EN_cpServer_request_put),
.EN_cpServer_response_get(inf_EN_cpServer_response_get),
.wci_m_0_SThreadBusy(inf_wci_m_0_SThreadBusy),
.wci_m_1_SThreadBusy(inf_wci_m_1_SThreadBusy),
.wci_m_2_SThreadBusy(inf_wci_m_2_SThreadBusy),
.wci_m_3_SThreadBusy(inf_wci_m_3_SThreadBusy),
.wci_m_4_SThreadBusy(inf_wci_m_4_SThreadBusy),
.wci_m_5_SThreadBusy(inf_wci_m_5_SThreadBusy),
.wci_m_6_SThreadBusy(inf_wci_m_6_SThreadBusy),
.wci_m_7_SThreadBusy(inf_wci_m_7_SThreadBusy),
.wci_m_8_SThreadBusy(inf_wci_m_8_SThreadBusy),
.wci_m_9_SThreadBusy(inf_wci_m_9_SThreadBusy),
.wci_m_10_SThreadBusy(inf_wci_m_10_SThreadBusy),
.wci_m_11_SThreadBusy(inf_wci_m_11_SThreadBusy),
.wci_m_12_SThreadBusy(inf_wci_m_12_SThreadBusy),
.wmiDP0_MReqLast(inf_wmiDP0_MReqLast),
.wmiDP0_MDataValid(inf_wmiDP0_MDataValid),
.wmiDP0_MDataLast(inf_wmiDP0_MDataLast),
.wmiDP0_MReset_n(inf_wmiDP0_MReset_n),
.wmiDP1_MReqLast(inf_wmiDP1_MReqLast),
.wmiDP1_MDataValid(inf_wmiDP1_MDataValid),
.wmiDP1_MDataLast(inf_wmiDP1_MDataLast),
.wmiDP1_MReset_n(inf_wmiDP1_MReset_n),
.RDY_server_request_put(inf_RDY_server_request_put),
.server_response_get(inf_server_response_get),
.RDY_server_response_get(inf_RDY_server_response_get),
.RDY_cpServer_request_put(inf_RDY_cpServer_request_put),
.cpServer_response_get(inf_cpServer_response_get),
.RDY_cpServer_response_get(inf_RDY_cpServer_response_get),
.led(inf_led),
.wci_m_0_MCmd(inf_wci_m_0_MCmd),
.wci_m_0_MAddrSpace(inf_wci_m_0_MAddrSpace),
.wci_m_0_MByteEn(inf_wci_m_0_MByteEn),
.wci_m_0_MAddr(inf_wci_m_0_MAddr),
.wci_m_0_MData(inf_wci_m_0_MData),
.wci_m_0_MFlag(inf_wci_m_0_MFlag),
.wci_m_1_MCmd(inf_wci_m_1_MCmd),
.wci_m_1_MAddrSpace(inf_wci_m_1_MAddrSpace),
.wci_m_1_MByteEn(inf_wci_m_1_MByteEn),
.wci_m_1_MAddr(inf_wci_m_1_MAddr),
.wci_m_1_MData(inf_wci_m_1_MData),
.wci_m_1_MFlag(inf_wci_m_1_MFlag),
.wci_m_2_MCmd(inf_wci_m_2_MCmd),
.wci_m_2_MAddrSpace(inf_wci_m_2_MAddrSpace),
.wci_m_2_MByteEn(inf_wci_m_2_MByteEn),
.wci_m_2_MAddr(inf_wci_m_2_MAddr),
.wci_m_2_MData(inf_wci_m_2_MData),
.wci_m_2_MFlag(inf_wci_m_2_MFlag),
.wci_m_3_MCmd(inf_wci_m_3_MCmd),
.wci_m_3_MAddrSpace(inf_wci_m_3_MAddrSpace),
.wci_m_3_MByteEn(inf_wci_m_3_MByteEn),
.wci_m_3_MAddr(inf_wci_m_3_MAddr),
.wci_m_3_MData(inf_wci_m_3_MData),
.wci_m_3_MFlag(inf_wci_m_3_MFlag),
.wci_m_4_MCmd(inf_wci_m_4_MCmd),
.wci_m_4_MAddrSpace(inf_wci_m_4_MAddrSpace),
.wci_m_4_MByteEn(inf_wci_m_4_MByteEn),
.wci_m_4_MAddr(inf_wci_m_4_MAddr),
.wci_m_4_MData(inf_wci_m_4_MData),
.wci_m_4_MFlag(inf_wci_m_4_MFlag),
.wci_m_5_MCmd(inf_wci_m_5_MCmd),
.wci_m_5_MAddrSpace(inf_wci_m_5_MAddrSpace),
.wci_m_5_MByteEn(inf_wci_m_5_MByteEn),
.wci_m_5_MAddr(inf_wci_m_5_MAddr),
.wci_m_5_MData(inf_wci_m_5_MData),
.wci_m_5_MFlag(inf_wci_m_5_MFlag),
.wci_m_6_MCmd(inf_wci_m_6_MCmd),
.wci_m_6_MAddrSpace(inf_wci_m_6_MAddrSpace),
.wci_m_6_MByteEn(inf_wci_m_6_MByteEn),
.wci_m_6_MAddr(inf_wci_m_6_MAddr),
.wci_m_6_MData(inf_wci_m_6_MData),
.wci_m_6_MFlag(inf_wci_m_6_MFlag),
.wci_m_7_MCmd(inf_wci_m_7_MCmd),
.wci_m_7_MAddrSpace(inf_wci_m_7_MAddrSpace),
.wci_m_7_MByteEn(inf_wci_m_7_MByteEn),
.wci_m_7_MAddr(inf_wci_m_7_MAddr),
.wci_m_7_MData(inf_wci_m_7_MData),
.wci_m_7_MFlag(inf_wci_m_7_MFlag),
.wci_m_8_MCmd(inf_wci_m_8_MCmd),
.wci_m_8_MAddrSpace(inf_wci_m_8_MAddrSpace),
.wci_m_8_MByteEn(inf_wci_m_8_MByteEn),
.wci_m_8_MAddr(inf_wci_m_8_MAddr),
.wci_m_8_MData(inf_wci_m_8_MData),
.wci_m_8_MFlag(inf_wci_m_8_MFlag),
.wci_m_9_MCmd(inf_wci_m_9_MCmd),
.wci_m_9_MAddrSpace(inf_wci_m_9_MAddrSpace),
.wci_m_9_MByteEn(inf_wci_m_9_MByteEn),
.wci_m_9_MAddr(inf_wci_m_9_MAddr),
.wci_m_9_MData(inf_wci_m_9_MData),
.wci_m_9_MFlag(inf_wci_m_9_MFlag),
.wci_m_10_MCmd(inf_wci_m_10_MCmd),
.wci_m_10_MAddrSpace(inf_wci_m_10_MAddrSpace),
.wci_m_10_MByteEn(inf_wci_m_10_MByteEn),
.wci_m_10_MAddr(inf_wci_m_10_MAddr),
.wci_m_10_MData(inf_wci_m_10_MData),
.wci_m_10_MFlag(inf_wci_m_10_MFlag),
.wci_m_11_MCmd(inf_wci_m_11_MCmd),
.wci_m_11_MAddrSpace(inf_wci_m_11_MAddrSpace),
.wci_m_11_MByteEn(inf_wci_m_11_MByteEn),
.wci_m_11_MAddr(inf_wci_m_11_MAddr),
.wci_m_11_MData(inf_wci_m_11_MData),
.wci_m_11_MFlag(inf_wci_m_11_MFlag),
.wci_m_12_MCmd(inf_wci_m_12_MCmd),
.wci_m_12_MAddrSpace(inf_wci_m_12_MAddrSpace),
.wci_m_12_MByteEn(inf_wci_m_12_MByteEn),
.wci_m_12_MAddr(inf_wci_m_12_MAddr),
.wci_m_12_MData(inf_wci_m_12_MData),
.wci_m_12_MFlag(inf_wci_m_12_MFlag),
.wmiDP0_SResp(inf_wmiDP0_SResp),
.wmiDP0_SData(inf_wmiDP0_SData),
.wmiDP0_SThreadBusy(inf_wmiDP0_SThreadBusy),
.wmiDP0_SDataThreadBusy(inf_wmiDP0_SDataThreadBusy),
.wmiDP0_SRespLast(inf_wmiDP0_SRespLast),
.wmiDP0_SFlag(inf_wmiDP0_SFlag),
.wmiDP0_SReset_n(inf_wmiDP0_SReset_n),
.wmiDP1_SResp(inf_wmiDP1_SResp),
.wmiDP1_SData(inf_wmiDP1_SData),
.wmiDP1_SThreadBusy(inf_wmiDP1_SThreadBusy),
.wmiDP1_SDataThreadBusy(inf_wmiDP1_SDataThreadBusy),
.wmiDP1_SRespLast(inf_wmiDP1_SRespLast),
.wmiDP1_SFlag(inf_wmiDP1_SFlag),
.wmiDP1_SReset_n(inf_wmiDP1_SReset_n),
.cpNow(inf_cpNow),
.RDY_cpNow(),
.gps_ppsSyncOut(inf_gps_ppsSyncOut),
.RDY_uuid(),
.RST_N_wci_m_0(inf_RST_N_wci_m_0),
.RST_N_wci_m_1(inf_RST_N_wci_m_1),
.RST_N_wci_m_2(inf_RST_N_wci_m_2),
.RST_N_wci_m_3(inf_RST_N_wci_m_3),
.RST_N_wci_m_4(inf_RST_N_wci_m_4),
.RST_N_wci_m_5(inf_RST_N_wci_m_5),
.RST_N_wci_m_6(inf_RST_N_wci_m_6),
.RST_N_wci_m_7(inf_RST_N_wci_m_7),
.RST_N_wci_m_8(inf_RST_N_wci_m_8),
.RST_N_wci_m_9(inf_RST_N_wci_m_9),
.RST_N_wci_m_10(inf_RST_N_wci_m_10),
.RST_N_wci_m_11(inf_RST_N_wci_m_11),
.RST_N_wci_m_12(inf_RST_N_wci_m_12));
// inlined wires
assign wtiM_0_peerIsReady_1_wget = 1'd1 ;
assign wtiM_0_peerIsReady_1_whas = app_wti_s_0_SReset_n ;
assign wtiM_1_peerIsReady_1_wget = 1'd1 ;
assign wtiM_1_peerIsReady_1_whas = app_wti_s_1_SReset_n ;
assign wtiM_2_peerIsReady_1_wget = 1'd1 ;
assign wtiM_2_peerIsReady_1_whas = app_wti_s_2_SReset_n ;
assign wtiM_0_sThreadBusy_pw_whas = app_wti_s_0_SThreadBusy ;
assign wtiM_1_sThreadBusy_pw_whas = app_wti_s_1_SThreadBusy ;
assign wtiM_2_sThreadBusy_pw_whas = app_wti_s_2_SThreadBusy ;
// register wtiM_0_nowReq
assign wtiM_0_nowReq_D_IN = { 3'd1, ctNow_dD_OUT } ;
assign wtiM_0_nowReq_EN = 1'd1 ;
// register wtiM_0_peerIsReady
assign wtiM_0_peerIsReady_D_IN = app_wti_s_0_SReset_n ;
assign wtiM_0_peerIsReady_EN = 1'd1 ;
// register wtiM_0_sThreadBusy_d
assign wtiM_0_sThreadBusy_d_D_IN = app_wti_s_0_SThreadBusy ;
assign wtiM_0_sThreadBusy_d_EN = 1'd1 ;
// register wtiM_1_nowReq
assign wtiM_1_nowReq_D_IN = wtiM_0_nowReq_D_IN ;
assign wtiM_1_nowReq_EN = 1'd1 ;
// register wtiM_1_peerIsReady
assign wtiM_1_peerIsReady_D_IN = app_wti_s_1_SReset_n ;
assign wtiM_1_peerIsReady_EN = 1'd1 ;
// register wtiM_1_sThreadBusy_d
assign wtiM_1_sThreadBusy_d_D_IN = app_wti_s_1_SThreadBusy ;
assign wtiM_1_sThreadBusy_d_EN = 1'd1 ;
// register wtiM_2_nowReq
assign wtiM_2_nowReq_D_IN = wtiM_0_nowReq_D_IN ;
assign wtiM_2_nowReq_EN = 1'd1 ;
// register wtiM_2_peerIsReady
assign wtiM_2_peerIsReady_D_IN = app_wti_s_2_SReset_n ;
assign wtiM_2_peerIsReady_EN = 1'd1 ;
// register wtiM_2_sThreadBusy_d
assign wtiM_2_sThreadBusy_d_D_IN = app_wti_s_2_SThreadBusy ;
assign wtiM_2_sThreadBusy_d_EN = 1'd1 ;
// submodule app
assign app_wci_s_0_MAddr = inf_wci_m_0_MAddr ;
assign app_wci_s_0_MAddrSpace = inf_wci_m_0_MAddrSpace ;
assign app_wci_s_0_MByteEn = inf_wci_m_0_MByteEn ;
assign app_wci_s_0_MCmd = inf_wci_m_0_MCmd ;
assign app_wci_s_0_MData = inf_wci_m_0_MData ;
assign app_wci_s_0_MFlag = inf_wci_m_0_MFlag ;
assign app_wci_s_1_MAddr = inf_wci_m_1_MAddr ;
assign app_wci_s_1_MAddrSpace = inf_wci_m_1_MAddrSpace ;
assign app_wci_s_1_MByteEn = inf_wci_m_1_MByteEn ;
assign app_wci_s_1_MCmd = inf_wci_m_1_MCmd ;
assign app_wci_s_1_MData = inf_wci_m_1_MData ;
assign app_wci_s_1_MFlag = inf_wci_m_1_MFlag ;
assign app_wci_s_2_MAddr = inf_wci_m_2_MAddr ;
assign app_wci_s_2_MAddrSpace = inf_wci_m_2_MAddrSpace ;
assign app_wci_s_2_MByteEn = inf_wci_m_2_MByteEn ;
assign app_wci_s_2_MCmd = inf_wci_m_2_MCmd ;
assign app_wci_s_2_MData = inf_wci_m_2_MData ;
assign app_wci_s_2_MFlag = inf_wci_m_2_MFlag ;
assign app_wci_s_3_MAddr = inf_wci_m_3_MAddr ;
assign app_wci_s_3_MAddrSpace = inf_wci_m_3_MAddrSpace ;
assign app_wci_s_3_MByteEn = inf_wci_m_3_MByteEn ;
assign app_wci_s_3_MCmd = inf_wci_m_3_MCmd ;
assign app_wci_s_3_MData = inf_wci_m_3_MData ;
assign app_wci_s_3_MFlag = inf_wci_m_3_MFlag ;
assign app_wci_s_4_MAddr = inf_wci_m_4_MAddr ;
assign app_wci_s_4_MAddrSpace = inf_wci_m_4_MAddrSpace ;
assign app_wci_s_4_MByteEn = inf_wci_m_4_MByteEn ;
assign app_wci_s_4_MCmd = inf_wci_m_4_MCmd ;
assign app_wci_s_4_MData = inf_wci_m_4_MData ;
assign app_wci_s_4_MFlag = inf_wci_m_4_MFlag ;
assign app_wci_s_5_MAddr = inf_wci_m_5_MAddr ;
assign app_wci_s_5_MAddrSpace = inf_wci_m_5_MAddrSpace ;
assign app_wci_s_5_MByteEn = inf_wci_m_5_MByteEn ;
assign app_wci_s_5_MCmd = inf_wci_m_5_MCmd ;
assign app_wci_s_5_MData = inf_wci_m_5_MData ;
assign app_wci_s_5_MFlag = inf_wci_m_5_MFlag ;
assign app_wci_s_6_MAddr = inf_wci_m_6_MAddr ;
assign app_wci_s_6_MAddrSpace = inf_wci_m_6_MAddrSpace ;
assign app_wci_s_6_MByteEn = inf_wci_m_6_MByteEn ;
assign app_wci_s_6_MCmd = inf_wci_m_6_MCmd ;
assign app_wci_s_6_MData = inf_wci_m_6_MData ;
assign app_wci_s_6_MFlag = inf_wci_m_6_MFlag ;
assign app_wci_s_7_MAddr = inf_wci_m_7_MAddr ;
assign app_wci_s_7_MAddrSpace = inf_wci_m_7_MAddrSpace ;
assign app_wci_s_7_MByteEn = inf_wci_m_7_MByteEn ;
assign app_wci_s_7_MCmd = inf_wci_m_7_MCmd ;
assign app_wci_s_7_MData = inf_wci_m_7_MData ;
assign app_wci_s_7_MFlag = inf_wci_m_7_MFlag ;
assign app_wmemiM0_SData = wmemiM0_SData ;
assign app_wmemiM0_SResp = wmemiM0_SResp ;
assign app_wmiM0_SData = inf_wmiDP0_SData ;
assign app_wmiM0_SFlag = inf_wmiDP0_SFlag ;
assign app_wmiM0_SResp = inf_wmiDP0_SResp ;
assign app_wmiM1_SData = inf_wmiDP1_SData ;
assign app_wmiM1_SFlag = inf_wmiDP1_SFlag ;
assign app_wmiM1_SResp = inf_wmiDP1_SResp ;
assign app_wsi_s_adc_MBurstLength = 12'h0 ;
assign app_wsi_s_adc_MByteEn = 16'h0 ;
assign app_wsi_s_adc_MCmd = 3'h0 ;
assign app_wsi_s_adc_MData = 128'h0 ;
assign app_wsi_s_adc_MReqInfo = 8'h0 ;
assign app_wti_s_0_MCmd =
wtiM_0_sThreadBusy_d ? 3'd0 : wtiM_0_nowReq[66:64] ;
assign app_wti_s_0_MData = wtiM_0_nowReq[63:0] ;
assign app_wti_s_1_MCmd =
wtiM_1_sThreadBusy_d ? 3'd0 : wtiM_1_nowReq[66:64] ;
assign app_wti_s_1_MData = wtiM_1_nowReq[63:0] ;
assign app_wti_s_2_MCmd =
wtiM_2_sThreadBusy_d ? 3'd0 : wtiM_2_nowReq[66:64] ;
assign app_wti_s_2_MData = wtiM_2_nowReq[63:0] ;
assign app_wmiM0_SThreadBusy = inf_wmiDP0_SThreadBusy ;
assign app_wmiM0_SDataThreadBusy = inf_wmiDP0_SDataThreadBusy ;
assign app_wmiM0_SRespLast = inf_wmiDP0_SRespLast ;
assign app_wmiM0_SReset_n = inf_wmiDP0_SReset_n ;
assign app_wmiM1_SThreadBusy = inf_wmiDP1_SThreadBusy ;
assign app_wmiM1_SDataThreadBusy = inf_wmiDP1_SDataThreadBusy ;
assign app_wmiM1_SRespLast = inf_wmiDP1_SRespLast ;
assign app_wmiM1_SReset_n = inf_wmiDP1_SReset_n ;
assign app_wmemiM0_SRespLast = wmemiM0_SRespLast ;
assign app_wmemiM0_SCmdAccept = wmemiM0_SCmdAccept ;
assign app_wmemiM0_SDataAccept = wmemiM0_SDataAccept ;
assign app_wsi_s_adc_MReqLast = 1'b0 ;
assign app_wsi_s_adc_MBurstPrecise = 1'b0 ;
assign app_wsi_s_adc_MReset_n = 1'b0 ;
assign app_wsi_m_dac_SThreadBusy = 1'b0 ;
assign app_wsi_m_dac_SReset_n = 1'b0 ;
// submodule ctNow
assign ctNow_sD_IN = inf_cpNow ;
assign ctNow_sEN = ctNow_sRDY ;
// submodule inf
assign inf_cpServer_request_put = cpServer_request_put ;
assign inf_gps_ppsSyncIn_x = gps_ppsSyncIn_x ;
assign inf_server_request_put = server_request_put ;
assign inf_switch_x = switch_x ;
assign inf_uuid_arg = app_uuid ;
assign inf_wci_m_0_SData = app_wci_s_0_SData ;
assign inf_wci_m_0_SFlag = app_wci_s_0_SFlag ;
assign inf_wci_m_0_SResp = app_wci_s_0_SResp ;
assign inf_wci_m_10_SData = wci_m_2_SData ;
assign inf_wci_m_10_SFlag = wci_m_2_SFlag ;
assign inf_wci_m_10_SResp = wci_m_2_SResp ;
assign inf_wci_m_11_SData = wci_m_3_SData ;
assign inf_wci_m_11_SFlag = wci_m_3_SFlag ;
assign inf_wci_m_11_SResp = wci_m_3_SResp ;
assign inf_wci_m_12_SData = wci_m_4_SData ;
assign inf_wci_m_12_SFlag = wci_m_4_SFlag ;
assign inf_wci_m_12_SResp = wci_m_4_SResp ;
assign inf_wci_m_1_SData = app_wci_s_1_SData ;
assign inf_wci_m_1_SFlag = app_wci_s_1_SFlag ;
assign inf_wci_m_1_SResp = app_wci_s_1_SResp ;
assign inf_wci_m_2_SData = app_wci_s_2_SData ;
assign inf_wci_m_2_SFlag = app_wci_s_2_SFlag ;
assign inf_wci_m_2_SResp = app_wci_s_2_SResp ;
assign inf_wci_m_3_SData = app_wci_s_3_SData ;
assign inf_wci_m_3_SFlag = app_wci_s_3_SFlag ;
assign inf_wci_m_3_SResp = app_wci_s_3_SResp ;
assign inf_wci_m_4_SData = app_wci_s_4_SData ;
assign inf_wci_m_4_SFlag = app_wci_s_4_SFlag ;
assign inf_wci_m_4_SResp = app_wci_s_4_SResp ;
assign inf_wci_m_5_SData = app_wci_s_5_SData ;
assign inf_wci_m_5_SFlag = app_wci_s_5_SFlag ;
assign inf_wci_m_5_SResp = app_wci_s_5_SResp ;
assign inf_wci_m_6_SData = app_wci_s_6_SData ;
assign inf_wci_m_6_SFlag = app_wci_s_6_SFlag ;
assign inf_wci_m_6_SResp = app_wci_s_6_SResp ;
assign inf_wci_m_7_SData = app_wci_s_7_SData ;
assign inf_wci_m_7_SFlag = app_wci_s_7_SFlag ;
assign inf_wci_m_7_SResp = app_wci_s_7_SResp ;
assign inf_wci_m_8_SData = wci_m_0_SData ;
assign inf_wci_m_8_SFlag = wci_m_0_SFlag ;
assign inf_wci_m_8_SResp = wci_m_0_SResp ;
assign inf_wci_m_9_SData = wci_m_1_SData ;
assign inf_wci_m_9_SFlag = wci_m_1_SFlag ;
assign inf_wci_m_9_SResp = wci_m_1_SResp ;
assign inf_wmiDP0_MAddr = app_wmiM0_MAddr ;
assign inf_wmiDP0_MAddrSpace = app_wmiM0_MAddrSpace ;
assign inf_wmiDP0_MBurstLength = app_wmiM0_MBurstLength ;
assign inf_wmiDP0_MCmd = app_wmiM0_MCmd ;
assign inf_wmiDP0_MData = app_wmiM0_MData ;
assign inf_wmiDP0_MDataByteEn = app_wmiM0_MDataByteEn ;
assign inf_wmiDP0_MReqInfo = app_wmiM0_MReqInfo ;
assign inf_wmiDP0_arg_mFlag = app_wmiM0_MFlag ;
assign inf_wmiDP1_MAddr = app_wmiM1_MAddr ;
assign inf_wmiDP1_MAddrSpace = app_wmiM1_MAddrSpace ;
assign inf_wmiDP1_MBurstLength = app_wmiM1_MBurstLength ;
assign inf_wmiDP1_MCmd = app_wmiM1_MCmd ;
assign inf_wmiDP1_MData = app_wmiM1_MData ;
assign inf_wmiDP1_MDataByteEn = app_wmiM1_MDataByteEn ;
assign inf_wmiDP1_MReqInfo = app_wmiM1_MReqInfo ;
assign inf_wmiDP1_arg_mFlag = app_wmiM1_MFlag ;
assign inf_EN_server_request_put = EN_server_request_put ;
assign inf_EN_server_response_get = EN_server_response_get ;
assign inf_EN_cpServer_request_put = EN_cpServer_request_put ;
assign inf_EN_cpServer_response_get = EN_cpServer_response_get ;
assign inf_wci_m_0_SThreadBusy = app_wci_s_0_SThreadBusy ;
assign inf_wci_m_1_SThreadBusy = app_wci_s_1_SThreadBusy ;
assign inf_wci_m_2_SThreadBusy = app_wci_s_2_SThreadBusy ;
assign inf_wci_m_3_SThreadBusy = app_wci_s_3_SThreadBusy ;
assign inf_wci_m_4_SThreadBusy = app_wci_s_4_SThreadBusy ;
assign inf_wci_m_5_SThreadBusy = app_wci_s_5_SThreadBusy ;
assign inf_wci_m_6_SThreadBusy = app_wci_s_6_SThreadBusy ;
assign inf_wci_m_7_SThreadBusy = app_wci_s_7_SThreadBusy ;
assign inf_wci_m_8_SThreadBusy = wci_m_0_SThreadBusy ;
assign inf_wci_m_9_SThreadBusy = wci_m_1_SThreadBusy ;
assign inf_wci_m_10_SThreadBusy = wci_m_2_SThreadBusy ;
assign inf_wci_m_11_SThreadBusy = wci_m_3_SThreadBusy ;
assign inf_wci_m_12_SThreadBusy = wci_m_4_SThreadBusy ;
assign inf_wmiDP0_MReqLast = app_wmiM0_MReqLast ;
assign inf_wmiDP0_MDataValid = app_wmiM0_MDataValid ;
assign inf_wmiDP0_MDataLast = app_wmiM0_MDataLast ;
assign inf_wmiDP0_MReset_n = app_wmiM0_MReset_n ;
assign inf_wmiDP1_MReqLast = app_wmiM1_MReqLast ;
assign inf_wmiDP1_MDataValid = app_wmiM1_MDataValid ;
assign inf_wmiDP1_MDataLast = app_wmiM1_MDataLast ;
assign inf_wmiDP1_MReset_n = app_wmiM1_MReset_n ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
wtiM_0_nowReq <= `BSV_ASSIGNMENT_DELAY 67'd0;
wtiM_0_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wtiM_0_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wtiM_1_nowReq <= `BSV_ASSIGNMENT_DELAY 67'd0;
wtiM_1_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wtiM_1_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wtiM_2_nowReq <= `BSV_ASSIGNMENT_DELAY 67'd0;
wtiM_2_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wtiM_2_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (wtiM_0_nowReq_EN)
wtiM_0_nowReq <= `BSV_ASSIGNMENT_DELAY wtiM_0_nowReq_D_IN;
if (wtiM_0_peerIsReady_EN)
wtiM_0_peerIsReady <= `BSV_ASSIGNMENT_DELAY wtiM_0_peerIsReady_D_IN;
if (wtiM_0_sThreadBusy_d_EN)
wtiM_0_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wtiM_0_sThreadBusy_d_D_IN;
if (wtiM_1_nowReq_EN)
wtiM_1_nowReq <= `BSV_ASSIGNMENT_DELAY wtiM_1_nowReq_D_IN;
if (wtiM_1_peerIsReady_EN)
wtiM_1_peerIsReady <= `BSV_ASSIGNMENT_DELAY wtiM_1_peerIsReady_D_IN;
if (wtiM_1_sThreadBusy_d_EN)
wtiM_1_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wtiM_1_sThreadBusy_d_D_IN;
if (wtiM_2_nowReq_EN)
wtiM_2_nowReq <= `BSV_ASSIGNMENT_DELAY wtiM_2_nowReq_D_IN;
if (wtiM_2_peerIsReady_EN)
wtiM_2_peerIsReady <= `BSV_ASSIGNMENT_DELAY wtiM_2_peerIsReady_D_IN;
if (wtiM_2_sThreadBusy_d_EN)
wtiM_2_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wtiM_2_sThreadBusy_d_D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
wtiM_0_nowReq = 67'h2AAAAAAAAAAAAAAAA;
wtiM_0_peerIsReady = 1'h0;
wtiM_0_sThreadBusy_d = 1'h0;
wtiM_1_nowReq = 67'h2AAAAAAAAAAAAAAAA;
wtiM_1_peerIsReady = 1'h0;
wtiM_1_sThreadBusy_d = 1'h0;
wtiM_2_nowReq = 67'h2AAAAAAAAAAAAAAAA;
wtiM_2_peerIsReady = 1'h0;
wtiM_2_sThreadBusy_d = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkCTop16B
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:14:08 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire n2827, Shift_reg_FLAGS_7_6, Shift_reg_FLAGS_7_5, intAS, SIGN_FLAG_EXP,
OP_FLAG_EXP, ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1,
ZERO_FLAG_SHT1, Data_array_SWR_3__25_, left_right_SHT2,
SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n470, n471, n472,
n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, n483,
n484, n485, n486, n487, n488, n489, n491, n499, n505, n509, n515,
n516, n517, n518, n519, n520, n521, n522, n523, n524, n525, n526,
n527, n528, n529, n530, n531, n532, n533, n534, n535, n536, n537,
n538, n539, n540, n541, n542, n544, n545, n546, n547, n548, n549,
n550, n551, n552, n553, n554, n555, n556, n557, n558, n559, n560,
n561, n562, n563, n564, n565, n566, n567, n568, n569, n570, n571,
n572, n573, n574, n575, n576, n577, n578, n579, n580, n581, n582,
n583, n584, n585, n586, n587, n588, n589, n590, n591, n592, n593,
n594, n595, n596, n597, n598, n599, n600, n601, n602, n603, n604,
n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615,
n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, n626,
n627, n628, n629, n630, n631, n632, n633, n634, n635, n636, n637,
n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, n648,
n649, n650, n651, n652, n653, n654, n655, n656, n657, n658, n659,
n660, n661, n662, n663, n664, n665, n666, n667, n668, n669, n670,
n671, n672, n673, n674, n675, n676, n677, n678, n679, n680, n681,
n682, n683, n684, n685, n686, n687, n688, n689, n690, n691, n692,
n693, n694, n695, n696, n697, n698, n699, n700, n701, n702, n703,
n704, n705, n706, n707, n708, n709, n710, n711, n712, n713, n714,
n715, n716, n717, n718, n719, n720, n721, n722, n723, n724, n725,
n726, n727, n728, n729, n730, n731, n732, n733, n734, n735, n736,
n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747,
n748, n749, n750, n751, n752, n753, n754, n755, n756, n757, n758,
n759, n760, n761, n762, n763, n764, n765, n766, n767, n768, n769,
n770, n771, n772, n773, n774, n776, n777, n778, n784, n802, n803,
n804, n805, n806, n807, n808, n809, n810, n811, n812, n813, n814,
n815, n816, n817, n818, n819, n820, n822, n823, n824, n825, n826,
n827, n828, n829, n830, n831, n832, n833, n834, n835, n836, n837,
n838, n839, n840, n841, n842, n843, n844, n845, n846, n847, n848,
n849, n850, n851, n852, n853, n854, n855, n856, n857, n858, n859,
n860, n861, n862, n863, n864, n865, n866, n867, n868, n869, n870,
n871, n872, n873, n874, n875, n876, n877, n878, n879, n880, n886,
n887, n888, n889, n890, n891, n892, n893, n894, n895, n903, n904,
n905, n907, n908, n912, n913, n914, n915, n919, n921, n923, n924,
n925, n928, n929, n930, n931, n932, n933, n934, n935, n936, n937,
n938, n939, n940, n941, n942, n943, n946, n947, n948, n949, n950,
n951, n952, n953, n954, n955, n956, n957, n958, n959, n960, n961,
n962, n963, n964, n965, n966, n967, n968, n969, n970, n971, n972,
n973, n974, n975, n976, n977, n978, n979, n980, n981, n982, n983,
n984, n985, n986, n987, n988, n989, n990, n991, n992, n993, n994,
n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004,
n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014,
n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024,
n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034,
n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044,
n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054,
n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064,
n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074,
n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084,
n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094,
n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104,
n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114,
n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124,
n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134,
n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1145,
n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155,
n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165,
n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1174, n1175, n1176,
n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186,
n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196,
n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206,
n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216,
n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226,
n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236,
n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246,
n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256,
n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266,
n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276,
n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286,
n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296,
n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306,
n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316,
n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326,
n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336,
n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346,
n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356,
n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366,
n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376,
n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386,
n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396,
n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406,
n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416,
n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426,
n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436,
n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446,
n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456,
n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466,
n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476,
n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486,
n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496,
n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506,
n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516,
n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526,
n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536,
n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546,
n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556,
n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566,
n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576,
n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586,
n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596,
n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606,
n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616,
n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626,
n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636,
n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646,
n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656,
n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666,
n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676,
n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686,
n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696,
n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706,
n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716,
n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726,
n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736,
n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746,
n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756,
n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766,
n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776,
n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786,
n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796,
n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806,
n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816,
n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826,
n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836,
n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846,
n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856,
n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866,
n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876,
n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886,
n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896,
n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906,
n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916,
n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926,
n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936,
n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946,
n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956,
n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966,
n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976,
n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986,
n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996,
n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006,
n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016,
n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026,
n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036,
n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046,
n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056,
n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066,
n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076,
n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086,
n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096,
n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106,
n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116,
n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126,
n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136,
n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146,
n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155, n2156,
n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165, n2166,
n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175, n2176,
n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185, n2186,
n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195, n2196,
n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206,
n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216,
n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226,
n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236,
n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246,
n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256,
n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266,
n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276,
n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286,
n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296,
n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2305, n2306, n2307,
n2308, n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318,
n2319, n2320, n2321, n2322, n2323, n2324, n2326, n2327, n2328, n2329,
n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339,
n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349,
n2351, n2353, n2354, n2357, n2358, n2359, n2360, n2361, n2362, n2363,
n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373,
n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383,
n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393,
n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403,
n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413,
n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423,
n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433,
n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443,
n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453,
n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463,
n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473,
n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483,
n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493,
n2494, n2495, n2496, n2498, n2499, n2500, n2501, n2502, n2503, n2504,
n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513, n2514,
n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524,
n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534,
n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544,
n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554,
n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564,
n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574,
n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584,
n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594,
n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604,
n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614,
n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624,
n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634,
n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644,
n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654,
n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664,
n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674,
n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684,
n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2693, n2694, n2695,
n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705,
n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715,
n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725,
n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735,
n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745,
n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755,
n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765,
n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775,
n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784, n2785,
n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794, n2795,
n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804, n2805,
n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814, n2815,
n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825,
n2826;
wire [2:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [20:0] Raw_mant_NRM_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [11:5] DmP_mant_SFG_SWR_signed;
wire [10:9] Raw_mant_SGF;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRX1TS R_185 ( .D(n873), .CK(clk), .RN(n1157), .QN(n2360) );
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n777), .CK(clk), .RN(n1161), .Q(
shift_value_SHT2_EWR[2]), .QN(n2397) );
DFFRX2TS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n772), .CK(clk), .RN(n2826),
.Q(Shift_amount_SHT1_EWR[1]), .QN(n2476) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n769), .CK(clk), .RN(n2676),
.Q(Shift_amount_SHT1_EWR[4]), .QN(n2432) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_0_ ( .D(n760), .CK(clk), .RN(n1148), .Q(
DMP_EXP_EWSW[0]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_1_ ( .D(n759), .CK(clk), .RN(n2677), .Q(
DMP_EXP_EWSW[1]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_2_ ( .D(n758), .CK(clk), .RN(n2510), .Q(
DMP_EXP_EWSW[2]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_4_ ( .D(n756), .CK(clk), .RN(n2511), .Q(
DMP_EXP_EWSW[4]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_5_ ( .D(n755), .CK(clk), .RN(n2672), .Q(
DMP_EXP_EWSW[5]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_6_ ( .D(n754), .CK(clk), .RN(n2514), .Q(
DMP_EXP_EWSW[6]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_8_ ( .D(n752), .CK(clk), .RN(n2676), .Q(
DMP_EXP_EWSW[8]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_10_ ( .D(n750), .CK(clk), .RN(n2675), .Q(
DMP_EXP_EWSW[10]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_11_ ( .D(n749), .CK(clk), .RN(n2675), .Q(
DMP_EXP_EWSW[11]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_14_ ( .D(n746), .CK(clk), .RN(n1159), .Q(
DMP_EXP_EWSW[14]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_15_ ( .D(n745), .CK(clk), .RN(n2670), .Q(
DMP_EXP_EWSW[15]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_18_ ( .D(n742), .CK(clk), .RN(n914), .Q(
DMP_EXP_EWSW[18]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_22_ ( .D(n738), .CK(clk), .RN(n1164), .Q(
DMP_EXP_EWSW[22]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n736), .CK(clk), .RN(n2678), .Q(
DMP_EXP_EWSW[24]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n735), .CK(clk), .RN(n2678), .Q(
DMP_EXP_EWSW[25]), .QN(n2376) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n734), .CK(clk), .RN(n2679), .Q(
DMP_EXP_EWSW[26]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_28_ ( .D(n732), .CK(clk), .RN(n2667), .Q(
DMP_EXP_EWSW[28]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_30_ ( .D(n730), .CK(clk), .RN(n2680), .Q(
DMP_EXP_EWSW[30]) );
DFFRX1TS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n729), .CK(clk), .RN(n2677), .Q(
OP_FLAG_EXP) );
DFFRX1TS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n728), .CK(clk), .RN(n2660), .Q(
ZERO_FLAG_EXP), .QN(n2429) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n726), .CK(clk), .RN(n2826), .Q(
DMP_SHT1_EWSW[0]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n725), .CK(clk), .RN(n1170), .Q(
DMP_SHT2_EWSW[0]), .QN(n2366) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n723), .CK(clk), .RN(n2677), .Q(
DMP_SHT1_EWSW[1]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n714), .CK(clk), .RN(n2826), .Q(
DMP_SHT1_EWSW[4]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n711), .CK(clk), .RN(n2511), .Q(
DMP_SHT1_EWSW[5]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n710), .CK(clk), .RN(n2672), .Q(
DMP_SHT2_EWSW[5]), .QN(n2375) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n709), .CK(clk), .RN(n2513), .Q(
DMP_SFG[5]), .QN(n2438) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n708), .CK(clk), .RN(n2508), .Q(
DMP_SHT1_EWSW[6]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n707), .CK(clk), .RN(n2674), .Q(
DMP_SHT2_EWSW[6]), .QN(n2374) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n705), .CK(clk), .RN(n908), .Q(
DMP_SHT1_EWSW[7]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n704), .CK(clk), .RN(n2510), .Q(
DMP_SHT2_EWSW[7]), .QN(n2373) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n702), .CK(clk), .RN(n908), .Q(
DMP_SHT1_EWSW[8]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n701), .CK(clk), .RN(n908), .Q(
DMP_SHT2_EWSW[8]), .QN(n2372) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n699), .CK(clk), .RN(n908), .Q(
DMP_SHT1_EWSW[9]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n696), .CK(clk), .RN(n2675), .Q(
DMP_SHT1_EWSW[10]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n693), .CK(clk), .RN(n2675), .Q(
DMP_SHT1_EWSW[11]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n692), .CK(clk), .RN(n2675), .Q(
DMP_SHT2_EWSW[11]), .QN(n2369) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_11_ ( .D(n691), .CK(clk), .RN(n2675), .Q(
DMP_SFG[11]), .QN(n2437) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n689), .CK(clk), .RN(n2675), .Q(
DMP_SHT2_EWSW[12]), .QN(n2368) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n688), .CK(clk), .RN(n2675), .Q(
DMP_SFG[12]), .QN(n2500) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n684), .CK(clk), .RN(n2513), .Q(
DMP_SHT1_EWSW[14]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n682), .CK(clk), .RN(n2670), .Q(
DMP_SFG[14]), .QN(n2459) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n681), .CK(clk), .RN(n2664), .Q(
DMP_SHT1_EWSW[15]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_15_ ( .D(n679), .CK(clk), .RN(n924), .Q(
DMP_SFG[15]), .QN(n2363) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n678), .CK(clk), .RN(n2665), .Q(
DMP_SHT1_EWSW[16]) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_16_ ( .D(n676), .CK(clk), .RN(n2665), .Q(
DMP_SFG[16]), .QN(n2489) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n675), .CK(clk), .RN(n2665), .Q(
DMP_SHT1_EWSW[17]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_17_ ( .D(n673), .CK(clk), .RN(n2665), .Q(
DMP_SFG[17]), .QN(n2365) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n672), .CK(clk), .RN(n915), .Q(
DMP_SHT1_EWSW[18]) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_18_ ( .D(n670), .CK(clk), .RN(n2665), .Q(
DMP_SFG[18]), .QN(n2488) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n669), .CK(clk), .RN(n914), .Q(
DMP_SHT1_EWSW[19]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_19_ ( .D(n667), .CK(clk), .RN(n913), .Q(
DMP_SFG[19]), .QN(n2364) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n666), .CK(clk), .RN(n913), .Q(
DMP_SHT1_EWSW[20]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n664), .CK(clk), .RN(n913), .Q(
DMP_SFG[20]), .QN(n2362) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n661), .CK(clk), .RN(n2669), .Q(
DMP_SFG[21]), .QN(n2458) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n660), .CK(clk), .RN(n2671), .Q(
DMP_SHT1_EWSW[22]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n658), .CK(clk), .RN(n2667), .Q(
DMP_SFG[22]), .QN(n2460) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n657), .CK(clk), .RN(n2512), .Q(
DMP_SHT1_EWSW[23]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n653), .CK(clk), .RN(n2515), .Q(
DMP_exp_NRM2_EW[0]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n652), .CK(clk), .RN(n2678), .Q(
DMP_SHT1_EWSW[24]) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n649), .CK(clk), .RN(n2661), .Q(
DMP_exp_NRM_EW[1]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n648), .CK(clk), .RN(n2512), .Q(
DMP_exp_NRM2_EW[1]), .QN(n2657) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n644), .CK(clk), .RN(n2678), .Q(
DMP_exp_NRM_EW[2]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n643), .CK(clk), .RN(n2678), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n642), .CK(clk), .RN(n2679), .Q(
DMP_SHT1_EWSW[26]) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n639), .CK(clk), .RN(n2678), .Q(
DMP_exp_NRM_EW[3]) );
DFFRX4TS R_105 ( .D(n638), .CK(clk), .RN(n2678), .Q(DMP_exp_NRM2_EW[3]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n637), .CK(clk), .RN(n2679), .Q(
DMP_SHT1_EWSW[27]) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n634), .CK(clk), .RN(n2679), .Q(
DMP_exp_NRM_EW[4]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n633), .CK(clk), .RN(n2679), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n632), .CK(clk), .RN(n2030), .Q(
DMP_SHT1_EWSW[28]) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n629), .CK(clk), .RN(n2671), .Q(
DMP_exp_NRM_EW[5]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n628), .CK(clk), .RN(n2677), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1014) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n627), .CK(clk), .RN(n2680), .Q(
DMP_SHT1_EWSW[29]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n622), .CK(clk), .RN(n2680), .Q(
DMP_SHT1_EWSW[30]) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n619), .CK(clk), .RN(n2680), .Q(
DMP_exp_NRM_EW[7]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n618), .CK(clk), .RN(n2680), .Q(
DMP_exp_NRM2_EW[7]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_0_ ( .D(n617), .CK(clk), .RN(n1156), .Q(
DmP_EXP_EWSW[0]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n616), .CK(clk), .RN(n2674), .Q(
DmP_mant_SHT1_SW[0]), .QN(n2505) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_1_ ( .D(n615), .CK(clk), .RN(n2511), .Q(
DmP_EXP_EWSW[1]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n614), .CK(clk), .RN(n2514), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n612), .CK(clk), .RN(n2510), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_3_ ( .D(n611), .CK(clk), .RN(n1165), .Q(
DmP_EXP_EWSW[3]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n610), .CK(clk), .RN(n1150), .Q(
DmP_mant_SHT1_SW[3]), .QN(n2425) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n608), .CK(clk), .RN(n2667), .Q(
DmP_mant_SHT1_SW[4]), .QN(n2428) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n606), .CK(clk), .RN(n1154), .Q(
DmP_mant_SHT1_SW[5]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_6_ ( .D(n605), .CK(clk), .RN(n2507), .Q(
DmP_EXP_EWSW[6]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n602), .CK(clk), .RN(n1171), .Q(
DmP_mant_SHT1_SW[7]), .QN(n2427) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_8_ ( .D(n601), .CK(clk), .RN(n1172), .Q(
DmP_EXP_EWSW[8]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_9_ ( .D(n599), .CK(clk), .RN(n924), .Q(
DmP_EXP_EWSW[9]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n598), .CK(clk), .RN(n1172), .Q(
DmP_mant_SHT1_SW[9]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n596), .CK(clk), .RN(n1155), .Q(
DmP_mant_SHT1_SW[10]), .QN(n2443) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_11_ ( .D(n595), .CK(clk), .RN(n2669), .Q(
DmP_EXP_EWSW[11]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n594), .CK(clk), .RN(n2511), .Q(
DmP_mant_SHT1_SW[11]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n592), .CK(clk), .RN(n2514), .Q(
DmP_mant_SHT1_SW[12]), .QN(n2441) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n590), .CK(clk), .RN(n2671), .Q(
DmP_mant_SHT1_SW[13]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_14_ ( .D(n589), .CK(clk), .RN(n2510), .Q(
DmP_EXP_EWSW[14]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n588), .CK(clk), .RN(n2687), .Q(
DmP_mant_SHT1_SW[14]), .QN(n2442) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_15_ ( .D(n587), .CK(clk), .RN(n2687), .Q(
DmP_EXP_EWSW[15]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n586), .CK(clk), .RN(n1171), .Q(
DmP_mant_SHT1_SW[15]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n582), .CK(clk), .RN(n1158), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n580), .CK(clk), .RN(n2669), .Q(
DmP_mant_SHT1_SW[18]), .QN(n2439) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n578), .CK(clk), .RN(n1162), .Q(
DmP_mant_SHT1_SW[19]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n576), .CK(clk), .RN(n1169), .Q(
DmP_mant_SHT1_SW[20]), .QN(n2426) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_21_ ( .D(n575), .CK(clk), .RN(n2662), .Q(
DmP_EXP_EWSW[21]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n571), .CK(clk), .RN(n1158), .Q(
DmP_EXP_EWSW[23]), .QN(n2449) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n570), .CK(clk), .RN(n1150), .Q(
DmP_EXP_EWSW[24]), .QN(n947) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n567), .CK(clk), .RN(n2507), .Q(
DmP_EXP_EWSW[27]) );
DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n564), .CK(clk), .RN(n2660), .Q(
ZERO_FLAG_SHT1) );
DFFRX2TS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n561), .CK(clk), .RN(n2660), .Q(
ZERO_FLAG_NRM) );
DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n558), .CK(clk), .RN(n2677), .Q(
OP_FLAG_SHT1) );
DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n555), .CK(clk), .RN(n2661), .Q(
SIGN_FLAG_SHT1) );
DFFRX2TS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n552), .CK(clk), .RN(n2661), .Q(
SIGN_FLAG_NRM) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n526), .CK(clk), .RN(n1162), .Q(
Raw_mant_NRM_SWR[3]), .QN(n2357) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n521), .CK(clk), .RN(n2510), .Q(
LZD_output_NRM2_EW[0]), .QN(n2656) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n520), .CK(clk), .RN(n1162), .Q(
LZD_output_NRM2_EW[2]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n519), .CK(clk), .RN(n1162), .Q(
DmP_mant_SFG_SWR[2]), .QN(n2472) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n518), .CK(clk), .RN(n1161), .Q(
Raw_mant_NRM_SWR[2]), .QN(n2424) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n516), .CK(clk), .RN(n1159), .Q(
DmP_mant_SFG_SWR[0]), .QN(n2462) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n515), .CK(clk), .RN(n2687), .Q(
Raw_mant_NRM_SWR[0]), .QN(n2361) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n491), .CK(clk), .RN(n1164), .QN(
n2390) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n489), .CK(clk), .RN(n2826), .Q(
DmP_mant_SFG_SWR[6]), .QN(n2461) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n488), .CK(clk), .RN(n2669), .Q(
DmP_mant_SFG_SWR[7]), .QN(n2463) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n487), .CK(clk), .RN(n2667), .Q(
DmP_mant_SFG_SWR[8]), .QN(n2492) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n480), .CK(clk), .RN(n2669), .Q(
DmP_mant_SFG_SWR[15]), .QN(n2464) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n474), .CK(clk), .RN(n2663), .Q(
DmP_mant_SFG_SWR[21]), .QN(n2470) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n473), .CK(clk), .RN(n2663), .Q(
DmP_mant_SFG_SWR[22]), .QN(n2469) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n472), .CK(clk), .RN(n2663), .Q(
DmP_mant_SFG_SWR[23]), .QN(n2468) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n470), .CK(clk), .RN(n2670), .Q(
DmP_mant_SFG_SWR[25]), .QN(n2431) );
DFFSX2TS R_19 ( .D(n2710), .CK(clk), .SN(n925), .Q(n2641) );
DFFRXLTS R_22 ( .D(n2759), .CK(clk), .RN(n1149), .Q(n2638) );
DFFSX1TS R_23 ( .D(n2758), .CK(clk), .SN(n1171), .Q(n2637) );
DFFSX1TS R_25 ( .D(n2756), .CK(clk), .SN(n1148), .Q(n2635) );
DFFSX2TS R_27 ( .D(n2763), .CK(clk), .SN(n1171), .Q(n2633) );
DFFSX1TS R_30 ( .D(n2739), .CK(clk), .SN(n2516), .Q(n2630) );
DFFSX1TS R_31 ( .D(n2738), .CK(clk), .SN(n2516), .Q(n2629) );
DFFSX1TS R_32 ( .D(n2737), .CK(clk), .SN(n2516), .Q(n2628) );
DFFSX1TS R_33 ( .D(n2736), .CK(clk), .SN(n2516), .Q(n2627) );
DFFSX1TS R_38 ( .D(n2715), .CK(clk), .SN(n2669), .Q(n2622) );
DFFSX1TS R_39 ( .D(n2714), .CK(clk), .SN(n2671), .Q(n2621) );
DFFSX1TS R_40 ( .D(n2713), .CK(clk), .SN(n1170), .Q(n2620) );
DFFSX1TS R_41 ( .D(n2712), .CK(clk), .SN(n1156), .Q(n2619) );
DFFSX2TS R_50 ( .D(n2775), .CK(clk), .SN(n1155), .Q(n2610) );
DFFRX2TS R_70 ( .D(n2771), .CK(clk), .RN(n1170), .Q(n2598) );
DFFSX1TS R_79 ( .D(n2778), .CK(clk), .SN(n1165), .Q(n2591) );
DFFSX1TS R_80 ( .D(n2777), .CK(clk), .SN(n2664), .Q(n2590) );
DFFSX1TS R_81 ( .D(n2776), .CK(clk), .SN(n2664), .Q(n2589) );
DFFRXLTS R_78 ( .D(n2779), .CK(clk), .RN(n2663), .Q(n2592) );
DFFSX2TS R_90 ( .D(n2722), .CK(clk), .SN(n2673), .Q(n2582) );
DFFSX1TS R_94 ( .D(n2742), .CK(clk), .SN(n2516), .Q(n2578) );
DFFSX1TS R_95 ( .D(n2741), .CK(clk), .SN(n2516), .Q(n2577) );
DFFSX1TS R_96 ( .D(n2740), .CK(clk), .SN(n2516), .Q(n2576) );
DFFRX4TS R_106 ( .D(n638), .CK(clk), .RN(n2678), .Q(n2655) );
DFFSX2TS R_156 ( .D(n2746), .CK(clk), .SN(n1149), .Q(n2536) );
DFFRX4TS R_172 ( .D(n2527), .CK(clk), .RN(n1165), .Q(
DmP_mant_SFG_SWR_signed[11]) );
DFFRX4TS R_196 ( .D(n2517), .CK(clk), .RN(n2667), .Q(
DmP_mant_SFG_SWR_signed[10]) );
DFFRX4TS R_194 ( .D(n556), .CK(clk), .RN(n1158), .Q(n2688) );
DFFRX1TS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n562), .CK(clk), .RN(n2660), .Q(
ZERO_FLAG_SFG), .QN(n2487) );
DFFRX1TS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n553), .CK(clk), .RN(n2661), .Q(
SIGN_FLAG_SFG), .QN(n2486) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_23_ ( .D(n655), .CK(clk), .RN(n2672), .Q(
DMP_SFG[23]), .QN(n2485) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_24_ ( .D(n650), .CK(clk), .RN(n2513), .Q(
DMP_SFG[24]), .QN(n2484) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_25_ ( .D(n645), .CK(clk), .RN(n2678), .Q(
DMP_SFG[25]), .QN(n2483) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_26_ ( .D(n640), .CK(clk), .RN(n2679), .Q(
DMP_SFG[26]), .QN(n2482) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_27_ ( .D(n635), .CK(clk), .RN(n2679), .Q(
DMP_SFG[27]), .QN(n2481) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_28_ ( .D(n630), .CK(clk), .RN(n2660), .Q(
DMP_SFG[28]), .QN(n2480) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_30_ ( .D(n620), .CK(clk), .RN(n2680), .Q(
DMP_SFG[30]), .QN(n2478) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n471), .CK(clk), .RN(n2513), .Q(
DmP_mant_SFG_SWR[24]), .QN(n2477) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n680), .CK(clk), .RN(n2664), .Q(
DMP_SHT2_EWSW[15]), .QN(n2457) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n668), .CK(clk), .RN(n915), .Q(
DMP_SHT2_EWSW[19]), .QN(n2455) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n665), .CK(clk), .RN(n914), .Q(
DMP_SHT2_EWSW[20]), .QN(n2454) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n683), .CK(clk), .RN(n2670), .Q(
DMP_SHT2_EWSW[14]), .QN(n2385) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n677), .CK(clk), .RN(n2665), .Q(
DMP_SHT2_EWSW[16]), .QN(n2384) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n671), .CK(clk), .RN(n2665), .Q(
DMP_SHT2_EWSW[18]), .QN(n2383) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n662), .CK(clk), .RN(n2669), .Q(
DMP_SHT2_EWSW[21]), .QN(n2382) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n659), .CK(clk), .RN(n2669), .Q(
DMP_SHT2_EWSW[22]), .QN(n2381) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n719), .CK(clk), .RN(n2664), .Q(
DMP_SHT2_EWSW[2]), .QN(n2380) );
DFFRX1TS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n557), .CK(clk), .RN(n2677), .Q(
OP_FLAG_SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n505), .CK(clk), .RN(n2507), .Q(
final_result_ieee[16]), .QN(n2498) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n509), .CK(clk), .RN(n2507), .Q(
final_result_ieee[13]) );
DFFRXLTS R_9 ( .D(final_result_ieee[7]), .CK(clk), .RN(n2508), .Q(n2647) );
DFFRXLTS R_13 ( .D(final_result_ieee[21]), .CK(clk), .RN(n1169), .Q(n2645)
);
DFFRXLTS R_61 ( .D(final_result_ieee[10]), .CK(clk), .RN(n2507), .Q(n2603)
);
DFFSX2TS R_57 ( .D(n2811), .CK(clk), .SN(n2507), .Q(n2605) );
DFFSX2TS R_65 ( .D(n2797), .CK(clk), .SN(n2508), .Q(n2601) );
DFFSX2TS R_69 ( .D(n2802), .CK(clk), .SN(n2507), .Q(n2599) );
DFFSX2TS R_77 ( .D(n2791), .CK(clk), .SN(n2512), .Q(n2593) );
DFFSX2TS R_88 ( .D(n2807), .CK(clk), .SN(n2674), .Q(n2584) );
DFFSX2TS R_110 ( .D(n2788), .CK(clk), .SN(n2514), .Q(n2566) );
DFFSX2TS R_114 ( .D(n2817), .CK(clk), .SN(n2511), .Q(n2564) );
DFFSX2TS R_122 ( .D(n2815), .CK(clk), .SN(n2508), .Q(n2558) );
DFFSX2TS R_126 ( .D(n2793), .CK(clk), .SN(n2674), .Q(n2556) );
DFFSX2TS R_130 ( .D(n2819), .CK(clk), .SN(n1170), .Q(n2554) );
DFFSX2TS R_138 ( .D(n2809), .CK(clk), .SN(n2509), .Q(n2548) );
DFFSX2TS R_146 ( .D(n2813), .CK(clk), .SN(n2509), .Q(n2542) );
DFFSX2TS R_150 ( .D(n2790), .CK(clk), .SN(n2513), .Q(n2540) );
DFFSX2TS R_154 ( .D(n2804), .CK(clk), .SN(n2512), .Q(n2538) );
DFFSX2TS R_162 ( .D(n2821), .CK(clk), .SN(n2514), .Q(n2532) );
DFFSX2TS R_166 ( .D(n2799), .CK(clk), .SN(n2510), .Q(n2530) );
DFFSX2TS R_170 ( .D(n2795), .CK(clk), .SN(n2511), .Q(n2528) );
DFFRX1TS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n761), .CK(clk), .RN(n2661), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n566), .CK(clk), .RN(n2660), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n550), .CK(clk), .RN(n2661), .Q(
final_result_ieee[31]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n559), .CK(clk), .RN(n2660), .Q(
zero_flag) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n647), .CK(clk), .RN(n2678), .QN(
n2453) );
DFFSX2TS R_115 ( .D(n2755), .CK(clk), .SN(n1149), .Q(n2563) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n768), .CK(clk), .RN(n1169), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n767), .CK(clk), .RN(n1169), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n766), .CK(clk), .RN(n1169), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n765), .CK(clk), .RN(n1169), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n764), .CK(clk), .RN(n1169), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n763), .CK(clk), .RN(n2661), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n762), .CK(clk), .RN(n2661), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n565), .CK(clk), .RN(n2660), .Q(
overflow_flag) );
DFFSX2TS R_133 ( .D(n2733), .CK(clk), .SN(n1150), .Q(n2551) );
DFFSX2TS R_131 ( .D(n2735), .CK(clk), .SN(n1150), .Q(n2553) );
DFFSX1TS R_82 ( .D(n2767), .CK(clk), .SN(n1157), .Q(n2588) );
DFFSX1TS R_15 ( .D(n2786), .CK(clk), .SN(n1162), .Q(n2644) );
DFFSX2TS R_2 ( .D(n2731), .CK(clk), .SN(n2516), .Q(n2652) );
DFFSX1TS R_34 ( .D(n2719), .CK(clk), .SN(n2669), .Q(n2626) );
DFFSX1TS R_46 ( .D(n2703), .CK(clk), .SN(n1148), .Q(n2614) );
DFFSX1TS R_35 ( .D(n2718), .CK(clk), .SN(n2662), .Q(n2625) );
DFFSX1TS R_47 ( .D(n2702), .CK(clk), .SN(n2687), .Q(n2613) );
DFFSX1TS R_16 ( .D(n2785), .CK(clk), .SN(n1162), .Q(n2643) );
DFFSX2TS R_141 ( .D(n2749), .CK(clk), .SN(n1148), .Q(n2545) );
DFFSX2TS R_5 ( .D(n2728), .CK(clk), .SN(n2515), .Q(n2649) );
DFFSX1TS R_84 ( .D(n2765), .CK(clk), .SN(n1149), .Q(n2586) );
DFFSX1TS R_83 ( .D(n2766), .CK(clk), .SN(n2667), .Q(n2587) );
DFFSX1TS R_17 ( .D(n2784), .CK(clk), .SN(n1162), .Q(n2642) );
DFFSX1TS R_21 ( .D(n2708), .CK(clk), .SN(n925), .Q(n2639) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n697), .CK(clk), .RN(n908), .Q(
DMP_SFG[9]), .QN(n2502) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n525), .CK(clk), .RN(n2511), .Q(
LZD_output_NRM2_EW[1]), .QN(n2658) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n700), .CK(clk), .RN(n924), .Q(
DMP_SFG[8]), .QN(n2503) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n517), .CK(clk), .RN(n1161), .Q(
LZD_output_NRM2_EW[3]) );
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n776), .CK(clk), .RN(n2667), .Q(
shift_value_SHT2_EWR[3]), .QN(n2396) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n477), .CK(clk), .RN(n2663), .Q(
DmP_mant_SFG_SWR[18]), .QN(n2494) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n835), .CK(clk), .RN(n2680), .Q(
intDY_EWSW[0]), .QN(n2421) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n524), .CK(clk), .RN(n1161), .Q(
LZD_output_NRM2_EW[4]), .QN(n1358) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n486), .CK(clk), .RN(n2515), .Q(
DmP_mant_SFG_SWR[9]), .QN(n2491) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n871), .CK(clk), .RN(n1156), .Q(
Shift_reg_FLAGS_7[1]), .QN(n1012) );
DFFSX4TS R_190 ( .D(n2659), .CK(clk), .SN(n1165), .Q(n2521) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n476), .CK(clk), .RN(n2663), .Q(
DmP_mant_SFG_SWR[19]), .QN(n2493) );
DFFSX4TS R_193 ( .D(n1179), .CK(clk), .SN(n1165), .Q(n2518) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n542), .CK(clk), .RN(n1158), .Q(
Raw_mant_NRM_SWR[11]), .QN(n2387) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n839), .CK(clk), .RN(n2686),
.Q(intDX_EWSW[30]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n846), .CK(clk), .RN(n2686),
.Q(intDX_EWSW[23]), .QN(n1108) );
DFFSX4TS R_52 ( .D(n2773), .CK(clk), .SN(n1154), .Q(n2608) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n541), .CK(clk), .RN(n1164), .Q(
Raw_mant_NRM_SWR[12]), .QN(n2386) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n812), .CK(clk), .RN(n2683),
.Q(intDY_EWSW[23]), .QN(n2401) );
DFFRX4TS R_139 ( .D(n2751), .CK(clk), .RN(n2515), .Q(n2547) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n877), .CK(clk), .RN(
n1156), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n2448) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n852), .CK(clk), .RN(n2685),
.Q(intDX_EWSW[17]), .QN(n981) );
DFFSX1TS R_48 ( .D(n2701), .CK(clk), .SN(n2671), .Q(n2612) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n540), .CK(clk), .RN(n2664), .Q(
Raw_mant_NRM_SWR[13]), .QN(n2423) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n826), .CK(clk), .RN(n2681), .Q(
intDY_EWSW[9]), .QN(n2398) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n815), .CK(clk), .RN(n2682),
.Q(intDY_EWSW[20]), .QN(n2417) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n816), .CK(clk), .RN(n2682),
.Q(intDY_EWSW[19]), .QN(n2414) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n818), .CK(clk), .RN(n2682),
.Q(intDY_EWSW[17]), .QN(n2403) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n817), .CK(clk), .RN(n2682),
.Q(intDY_EWSW[18]), .QN(n2418) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n855), .CK(clk), .RN(n2685),
.Q(intDX_EWSW[14]), .QN(n1084) );
DFFSX4TS R_191 ( .D(Raw_mant_SGF[10]), .CK(clk), .SN(n1165), .Q(n2520) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n820), .CK(clk), .RN(n2682),
.Q(intDY_EWSW[15]), .QN(n2404) );
DFFRX4TS R_192 ( .D(n1022), .CK(clk), .RN(n1165), .Q(n2519) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n840), .CK(clk), .RN(n2686),
.Q(intDX_EWSW[29]), .QN(n1085) );
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n774), .CK(clk), .RN(n2676), .Q(
shift_value_SHT2_EWR[4]), .QN(n2391) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n808), .CK(clk), .RN(n2683),
.Q(intDY_EWSW[27]), .QN(n2400) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n867), .CK(clk), .RN(n2684), .Q(
intDX_EWSW[2]), .QN(n1126) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n841), .CK(clk), .RN(n2686),
.Q(intDX_EWSW[28]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n869), .CK(clk), .RN(n2683), .Q(
intDX_EWSW[0]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n847), .CK(clk), .RN(n2686),
.Q(intDX_EWSW[22]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n857), .CK(clk), .RN(n2685),
.Q(intDX_EWSW[12]), .QN(n1130) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n856), .CK(clk), .RN(n2685),
.Q(intDX_EWSW[13]), .QN(n1125) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n814), .CK(clk), .RN(n2682),
.Q(intDY_EWSW[21]), .QN(n2402) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n859), .CK(clk), .RN(n2684),
.Q(intDX_EWSW[10]), .QN(n1081) );
DFFSRHQX4TS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n551), .CK(clk), .SN(1'b1),
.RN(n1159), .Q(SIGN_FLAG_SHT1SHT2) );
DFFRHQX4TS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n646), .CK(clk), .RN(n1172), .Q(
n2353) );
DFFSX1TS R_124 ( .D(n2794), .CK(clk), .SN(n2514), .Q(n2557) );
DFFSX1TS R_63 ( .D(n2798), .CK(clk), .SN(n2511), .Q(n2602) );
DFFSX1TS R_112 ( .D(n2818), .CK(clk), .SN(n1170), .Q(n2565) );
DFFSX1TS R_75 ( .D(n2792), .CK(clk), .SN(n2513), .Q(n2594) );
DFFSX1TS R_160 ( .D(n2822), .CK(clk), .SN(n2512), .Q(n2533) );
DFFSX1TS R_152 ( .D(n2805), .CK(clk), .SN(n2674), .Q(n2539) );
DFFSX1TS R_67 ( .D(n2803), .CK(clk), .SN(n2513), .Q(n2600) );
DFFSX1TS R_59 ( .D(n2806), .CK(clk), .SN(n2507), .Q(n2604) );
DFFSX1TS R_136 ( .D(n2810), .CK(clk), .SN(n2509), .Q(n2549) );
DFFSX1TS R_168 ( .D(n2796), .CK(clk), .SN(n2672), .Q(n2529) );
DFFSX1TS R_164 ( .D(n2800), .CK(clk), .SN(n2511), .Q(n2531) );
DFFSX1TS R_144 ( .D(n2814), .CK(clk), .SN(n2509), .Q(n2543) );
DFFSX1TS R_120 ( .D(n2816), .CK(clk), .SN(n2509), .Q(n2559) );
DFFSX1TS R_108 ( .D(n2789), .CK(clk), .SN(n2510), .Q(n2567) );
DFFSX1TS R_11 ( .D(n2820), .CK(clk), .SN(n2510), .Q(n2646) );
DFFSX1TS R_86 ( .D(n2808), .CK(clk), .SN(n2512), .Q(n2585) );
DFFSX1TS R_55 ( .D(n2812), .CK(clk), .SN(n2507), .Q(n2606) );
DFFSX1TS R_7 ( .D(n2801), .CK(clk), .SN(n2512), .Q(n2648) );
DFFSX1TS R_148 ( .D(n998), .CK(clk), .SN(n2510), .Q(n2541) );
DFFSX1TS R_128 ( .D(n999), .CK(clk), .SN(n1170), .Q(n2555) );
DFFSX1TS R_45 ( .D(n2724), .CK(clk), .SN(n1158), .Q(n2615) );
DFFSX1TS R_92 ( .D(n2720), .CK(clk), .SN(n1161), .Q(n2580) );
DFFSX1TS R_28 ( .D(n2762), .CK(clk), .SN(n1162), .Q(n2632) );
DFFSX1TS R_132 ( .D(n2734), .CK(clk), .SN(n1150), .Q(n2552) );
DFFSX1TS R_116 ( .D(n2754), .CK(clk), .SN(n1148), .Q(n2562) );
DFFSX1TS R_73 ( .D(n2768), .CK(clk), .SN(n2667), .Q(n2595) );
DFFSX1TS R_158 ( .D(n2744), .CK(clk), .SN(n2515), .Q(n2534) );
DFFSX1TS R_102 ( .D(n2782), .CK(clk), .SN(n2670), .Q(n2570) );
DFFSX1TS R_71 ( .D(n2770), .CK(clk), .SN(n1161), .Q(n2597) );
DFFSX1TS R_29 ( .D(n2761), .CK(clk), .SN(n1171), .Q(n2631) );
DFFSX1TS R_91 ( .D(n2721), .CK(clk), .SN(n1162), .Q(n2581) );
DFFSX1TS R_4 ( .D(n2729), .CK(clk), .SN(n2515), .Q(n2650) );
DFFSX1TS R_20 ( .D(n2709), .CK(clk), .SN(n925), .Q(n2640) );
DFFSX1TS R_42 ( .D(n2727), .CK(clk), .SN(n2662), .Q(n2618) );
DFFSX1TS R_101 ( .D(n2783), .CK(clk), .SN(n2670), .Q(n2571) );
DFFSX1TS R_104 ( .D(n2780), .CK(clk), .SN(n2670), .Q(n2568) );
DFFSX1TS R_72 ( .D(n2769), .CK(clk), .SN(n2513), .Q(n2596) );
DFFSX1TS R_103 ( .D(n2781), .CK(clk), .SN(n2508), .Q(n2569) );
DFFSX1TS R_53 ( .D(n2772), .CK(clk), .SN(n2826), .Q(n2607) );
DFFSX1TS R_3 ( .D(n2730), .CK(clk), .SN(n2515), .Q(n2651) );
DFFSX1TS R_51 ( .D(n2774), .CK(clk), .SN(n1148), .Q(n2609) );
DFFSX1TS R_43 ( .D(n2726), .CK(clk), .SN(n1161), .Q(n2617) );
DFFSX1TS R_134 ( .D(n2732), .CK(clk), .SN(n1164), .Q(n2550) );
DFFSX1TS R_157 ( .D(n2745), .CK(clk), .SN(n2512), .Q(n2535) );
DFFRHQX2TS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n771), .CK(clk), .RN(n1171),
.Q(n2351) );
DFFRHQX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n836), .CK(clk), .RN(n2826),
.Q(left_right_SHT2) );
DFFRHQX2TS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n770), .CK(clk), .RN(n1155),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRHQX1TS R_195 ( .D(n485), .CK(clk), .RN(n1172), .Q(n2349) );
DFFSX4TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1355), .CK(clk), .SN(n1159),
.Q(n2394), .QN(intDY_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n695), .CK(clk), .RN(n2675), .Q(
DMP_SHT2_EWSW[10]), .QN(n2370) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n654), .CK(clk), .RN(n2682), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n722), .CK(clk), .RN(n2677), .Q(
DMP_SHT2_EWSW[1]), .QN(n2377) );
DFFSX1TS R_117 ( .D(n2753), .CK(clk), .SN(n2516), .Q(n2561) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n810), .CK(clk), .RN(n2683),
.Q(intDY_EWSW[25]), .QN(n2420) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n806), .CK(clk), .RN(n2683),
.Q(intDY_EWSW[29]), .QN(n2413) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n811), .CK(clk), .RN(n2683),
.Q(intDY_EWSW[24]), .QN(n2392) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n853), .CK(clk), .RN(n2685),
.Q(intDX_EWSW[16]), .QN(n1145) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n807), .CK(clk), .RN(n2683),
.Q(intDY_EWSW[28]), .QN(n2395) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n851), .CK(clk), .RN(n2685),
.Q(intDX_EWSW[18]), .QN(n1110) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n547), .CK(clk), .RN(n1164), .Q(
Raw_mant_NRM_SWR[6]), .QN(n2422) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n703), .CK(clk), .RN(n2514), .Q(
DMP_SFG[7]), .QN(n2499) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n843), .CK(clk), .RN(n2686),
.Q(intDX_EWSW[26]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n861), .CK(clk), .RN(n2684), .Q(
intDX_EWSW[8]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n862), .CK(clk), .RN(n2684), .Q(
intDX_EWSW[7]), .QN(n946) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n533), .CK(clk), .RN(n2663), .Q(
Raw_mant_NRM_SWR[20]), .QN(n2654) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_6_ ( .D(n706), .CK(clk), .RN(n2508), .Q(
DMP_SFG[6]), .QN(n2504) );
DFFSX4TS R_188 ( .D(Raw_mant_SGF[9]), .CK(clk), .SN(n1165), .Q(n2523) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n546), .CK(clk), .RN(n1164), .Q(
Raw_mant_NRM_SWR[7]), .QN(n2358) );
DFFRX4TS R_189 ( .D(n1052), .CK(clk), .RN(n1164), .Q(n2522) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n715), .CK(clk), .RN(n2673), .Q(
DMP_SFG[3]), .QN(n2490) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n819), .CK(clk), .RN(n2682),
.Q(intDY_EWSW[16]), .QN(n2419) );
DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1156), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n2446) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n823), .CK(clk), .RN(n2682),
.Q(intDY_EWSW[12]), .QN(n2407) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n822), .CK(clk), .RN(n2682),
.Q(intDY_EWSW[13]), .QN(n2415) );
DFFSX4TS R_186 ( .D(n2525), .CK(clk), .SN(n1157), .Q(n2691), .QN(n2689) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n833), .CK(clk), .RN(n2681), .Q(
intDY_EWSW[2]), .QN(n2409) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n827), .CK(clk), .RN(n2681), .Q(
intDY_EWSW[8]), .QN(n2408) );
DFFRX4TS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n837), .CK(clk), .RN(n2677), .Q(
intAS) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n828), .CK(clk), .RN(n2681), .Q(
intDY_EWSW[7]), .QN(n2406) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n824), .CK(clk), .RN(n2681),
.Q(intDY_EWSW[11]), .QN(n2405) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n832), .CK(clk), .RN(n2681), .Q(
intDY_EWSW[3]), .QN(n2416) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n804), .CK(clk), .RN(n2677),
.Q(intDY_EWSW[31]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n829), .CK(clk), .RN(n2681), .Q(
intDY_EWSW[6]), .QN(n2412) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n825), .CK(clk), .RN(n2681),
.Q(intDY_EWSW[10]), .QN(n2411) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n813), .CK(clk), .RN(n2683),
.Q(intDY_EWSW[22]), .QN(n2393) );
DFFSX2TS R_37 ( .D(n2716), .CK(clk), .SN(n1156), .Q(n2623) );
DFFSX2TS R_36 ( .D(n2717), .CK(clk), .SN(n1156), .Q(n2624) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n872), .CK(clk), .RN(n1156), .Q(
Shift_reg_FLAGS_7[2]), .QN(n2452) );
DFFRX2TS R_93 ( .D(n2743), .CK(clk), .RN(n2515), .Q(n2579) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n809), .CK(clk), .RN(n2683),
.Q(intDY_EWSW[26]), .QN(n2410) );
DFFRX4TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n803), .CK(clk), .RN(n1155), .Q(
Data_array_SWR_3__25_) );
DFFRX4TS R_14 ( .D(n2787), .CK(clk), .RN(n1161), .QN(n1054) );
DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n878), .CK(clk), .RN(
n1156), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]), .QN(n2447) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n479), .CK(clk), .RN(n2663), .Q(
DmP_mant_SFG_SWR[16]), .QN(n2496) );
DFFRX4TS R_155 ( .D(n2747), .CK(clk), .RN(n2515), .Q(n2537) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n483), .CK(clk), .RN(n1154), .Q(
DmP_mant_SFG_SWR[12]), .QN(n2467) );
DFFSX2TS R_118 ( .D(n2752), .CK(clk), .SN(n2516), .Q(n2560) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n482), .CK(clk), .RN(n1158), .Q(
DmP_mant_SFG_SWR[13]), .QN(n2466) );
DFFRX4TS R_97 ( .D(n2707), .CK(clk), .RN(n1161), .Q(n2575) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n805), .CK(clk), .RN(n2686),
.Q(intDY_EWSW[30]), .QN(n2399) );
DFFSX2TS R_187 ( .D(n2524), .CK(clk), .SN(n1157), .Q(n2824), .QN(n1011) );
DFFSHQX8TS Ready_reg_Q_reg_0_ ( .D(n2691), .CK(clk), .SN(n1154), .Q(n2354)
);
DFFRHQX8TS R_180 ( .D(n556), .CK(clk), .RN(n2671), .Q(n1147) );
DFFRX4TS R_18 ( .D(n2711), .CK(clk), .RN(n1171), .QN(n1142) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n866), .CK(clk), .RN(n2684),
.Q(n1140) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n539), .CK(clk), .RN(n2826),
.Q(n1135) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n545), .CK(clk), .RN(n1165), .Q(
Raw_mant_NRM_SWR[8]), .QN(n2388) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n868), .CK(clk), .RN(n2683),
.Q(n1127) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n529), .CK(clk), .RN(n2664),
.Q(n1123) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n478), .CK(clk), .RN(n2663), .Q(
DmP_mant_SFG_SWR[17]), .QN(n2495) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n864), .CK(clk), .RN(n2684),
.Q(n1121) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n842), .CK(clk), .RN(n2686),
.Q(n1119) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n845), .CK(clk), .RN(n2686),
.Q(n1118) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n831), .CK(clk), .RN(n2681),
.Q(n1116) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n534), .CK(clk), .RN(n2670),
.Q(n1114) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n528), .CK(clk), .RN(n1161),
.Q(n1112) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n863), .CK(clk), .RN(n2684),
.Q(n1111) );
DFFSX2TS R_44 ( .D(n2725), .CK(clk), .SN(n2671), .Q(n2616) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n538), .CK(clk), .RN(n1150),
.Q(n1102) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n548), .CK(clk), .RN(n1164), .Q(
n1098) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n830), .CK(clk), .RN(n2681),
.Q(n1089) );
DFFRX4TS R_89 ( .D(n2723), .CK(clk), .RN(n1155), .Q(n2583) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n850), .CK(clk), .RN(n2685),
.Q(n1086) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n865), .CK(clk), .RN(n2684),
.Q(n1082) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n858), .CK(clk), .RN(n2684),
.Q(n1078) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n481), .CK(clk), .RN(n924), .QN(
n2465) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n475), .CK(clk), .RN(n2663), .Q(
DmP_mant_SFG_SWR[20]), .QN(n2471) );
DFFRHQX4TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n535), .CK(clk), .RN(n2664),
.Q(n1066) );
DFFRX4TS R_181 ( .D(n2526), .CK(clk), .RN(n2667), .Q(
DmP_mant_SFG_SWR_signed[5]) );
DFFRHQX4TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n802), .CK(clk), .RN(n1155), .Q(
n1064) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_10_ ( .D(n694), .CK(clk), .RN(n2675), .QN(n2436) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n532), .CK(clk), .RN(n2670),
.Q(n1059) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n536), .CK(clk), .RN(n1158),
.Q(n1057) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n537), .CK(clk), .RN(n1158),
.Q(n1055) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n860), .CK(clk), .RN(n2684),
.Q(n1048) );
DFFRHQX2TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n522), .CK(clk), .RN(n2512), .Q(
n1047) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n834), .CK(clk), .RN(n2680),
.Q(n1043) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_27_ ( .D(n733), .CK(clk), .RN(n2679), .Q(
DMP_EXP_EWSW[27]) );
DFFRX1TS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n499), .CK(clk), .RN(n1169), .Q(
final_result_ieee[19]) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n848), .CK(clk), .RN(n2685),
.Q(n1129) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_18_ ( .D(n581), .CK(clk), .RN(n2662), .Q(
DmP_EXP_EWSW[18]) );
DFFRX4TS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n727), .CK(clk), .RN(n2661), .Q(
SIGN_FLAG_EXP) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_16_ ( .D(n744), .CK(clk), .RN(n2665), .Q(
DMP_EXP_EWSW[16]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_29_ ( .D(n731), .CK(clk), .RN(n2680), .Q(
DMP_EXP_EWSW[29]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n656), .CK(clk), .RN(n2660), .Q(
DMP_SHT2_EWSW[23]), .QN(n2699) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n641), .CK(clk), .RN(n2679), .Q(
DMP_SHT2_EWSW[26]), .QN(n2697) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n636), .CK(clk), .RN(n2679), .Q(
DMP_SHT2_EWSW[27]), .QN(n2696) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n631), .CK(clk), .RN(n1154), .Q(
DMP_SHT2_EWSW[28]), .QN(n2695) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n626), .CK(clk), .RN(n2662), .Q(
DMP_SHT2_EWSW[29]), .QN(n2694) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n621), .CK(clk), .RN(n2680), .Q(
DMP_SHT2_EWSW[30]), .QN(n2693) );
DFFRX1TS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n563), .CK(clk), .RN(n2660), .Q(
ZERO_FLAG_SHT2), .QN(n2825) );
DFFRX1TS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n554), .CK(clk), .RN(n2661), .Q(
SIGN_FLAG_SHT2), .QN(n2823) );
DFFSX2TS R_209 ( .D(n1822), .CK(clk), .SN(n908), .Q(n977) );
DFFSX2TS R_210 ( .D(n1823), .CK(clk), .SN(n2668), .Q(n976) );
DFFSX2TS R_211 ( .D(n1821), .CK(clk), .SN(n2668), .Q(n975) );
DFFSX2TS R_212 ( .D(n1976), .CK(clk), .SN(n2673), .Q(n974) );
DFFSX2TS R_213 ( .D(n1977), .CK(clk), .SN(n2673), .Q(n973) );
DFFSX2TS R_214 ( .D(n1975), .CK(clk), .SN(n2673), .Q(n972) );
DFFSX2TS R_215 ( .D(n1842), .CK(clk), .SN(n1171), .Q(n971) );
DFFSX2TS R_216 ( .D(n1843), .CK(clk), .SN(n2672), .Q(n970) );
DFFSX2TS R_217 ( .D(n1841), .CK(clk), .SN(n2672), .Q(n969) );
DFFSX2TS R_218 ( .D(n1838), .CK(clk), .SN(n924), .Q(n968) );
DFFSX2TS R_219 ( .D(n1837), .CK(clk), .SN(n925), .Q(n967) );
DFFSX2TS R_220 ( .D(n1836), .CK(clk), .SN(n924), .Q(n966) );
DFFSX2TS R_221 ( .D(n1835), .CK(clk), .SN(n925), .Q(n965) );
DFFSX2TS R_222 ( .D(n1834), .CK(clk), .SN(n925), .Q(n964) );
DFFSX2TS R_223 ( .D(n1833), .CK(clk), .SN(n925), .Q(n963) );
DFFSX2TS R_224 ( .D(n1858), .CK(clk), .SN(n2674), .Q(n962) );
DFFSX2TS R_225 ( .D(n1857), .CK(clk), .SN(n2513), .Q(n961) );
DFFSX2TS R_226 ( .D(n1856), .CK(clk), .SN(n2674), .Q(n960) );
DFFSX2TS R_227 ( .D(n1971), .CK(clk), .SN(n908), .Q(n959) );
DFFSX2TS R_228 ( .D(n1970), .CK(clk), .SN(n908), .Q(n958) );
DFFSX2TS R_229 ( .D(n1969), .CK(clk), .SN(n908), .Q(n957) );
DFFSX2TS R_230 ( .D(n1848), .CK(clk), .SN(n1155), .Q(n956) );
DFFSX2TS R_231 ( .D(n1849), .CK(clk), .SN(n925), .Q(n955) );
DFFSX2TS R_232 ( .D(n1847), .CK(clk), .SN(n1172), .Q(n954) );
DFFSX2TS R_233 ( .D(n1768), .CK(clk), .SN(n2668), .Q(n953) );
DFFSX2TS R_234 ( .D(n1767), .CK(clk), .SN(n908), .Q(n952) );
DFFSX2TS R_235 ( .D(n1766), .CK(clk), .SN(n2668), .Q(n951) );
DFFSX2TS R_236 ( .D(n1997), .CK(clk), .SN(n915), .Q(n950) );
DFFSX2TS R_237 ( .D(n1998), .CK(clk), .SN(n914), .Q(n949) );
DFFSX2TS R_238 ( .D(n1996), .CK(clk), .SN(n915), .Q(n948) );
DFFSX2TS R_253 ( .D(n2689), .CK(clk), .SN(n2511), .Q(n943) );
DFFSX2TS R_254 ( .D(n2690), .CK(clk), .SN(n2510), .Q(n942) );
DFFSX2TS R_255 ( .D(n2689), .CK(clk), .SN(n2509), .Q(n941) );
DFFSX2TS R_256 ( .D(n2653), .CK(clk), .SN(n2672), .Q(n940) );
DFFSX2TS R_142 ( .D(n2748), .CK(clk), .SN(n1170), .Q(n2544) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n849), .CK(clk), .RN(n2685),
.Q(n1120) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n530), .CK(clk), .RN(n2664),
.Q(n1071) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n724), .CK(clk), .RN(n2667), .Q(
DMP_SFG[0]), .QN(n2435) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n698), .CK(clk), .RN(n924), .Q(
DMP_SHT2_EWSW[9]), .QN(n2371) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n624), .CK(clk), .RN(n2030), .Q(
DMP_exp_NRM_EW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n604), .CK(clk), .RN(n1155), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n674), .CK(clk), .RN(n2665), .Q(
DMP_SHT2_EWSW[17]), .QN(n2456) );
DFFRHQX2TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n572), .CK(clk), .RN(n1172),
.Q(DmP_mant_SHT1_SW[22]) );
DFFSX4TS R_24 ( .D(n2757), .CK(clk), .SN(n924), .Q(n2636) );
DFFRHQX4TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n778), .CK(clk), .RN(n1154), .Q(
n1137) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n713), .CK(clk), .RN(n2673), .Q(
DMP_SHT2_EWSW[4]), .QN(n2378) );
DFFRX4TS R_26 ( .D(n2764), .CK(clk), .RN(n1154), .Q(n2634) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_22_ ( .D(n573), .CK(clk), .RN(n1165), .Q(n904) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_17_ ( .D(n743), .CK(clk), .RN(n2665), .Q(n903) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_12_ ( .D(n748), .CK(clk), .RN(n2676), .Q(
DMP_EXP_EWSW[12]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_19_ ( .D(n579), .CK(clk), .RN(n2671), .Q(
DmP_EXP_EWSW[19]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_16_ ( .D(n585), .CK(clk), .RN(n1159), .Q(
DmP_EXP_EWSW[16]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_2_ ( .D(n613), .CK(clk), .RN(n1171), .Q(
DmP_EXP_EWSW[2]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_17_ ( .D(n583), .CK(clk), .RN(n1158), .Q(
DmP_EXP_EWSW[17]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_20_ ( .D(n740), .CK(clk), .RN(n913), .Q(
DMP_EXP_EWSW[20]) );
DFFRX2TS EXP_STAGE_DmP_Q_reg_13_ ( .D(n591), .CK(clk), .RN(n2508), .Q(
DmP_EXP_EWSW[13]) );
DFFRX2TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n568), .CK(clk), .RN(n2826), .Q(
DmP_EXP_EWSW[26]), .QN(n2445) );
DFFRX2TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n737), .CK(clk), .RN(n2674), .Q(
DMP_EXP_EWSW[23]), .QN(n2450) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n569), .CK(clk), .RN(n2676), .Q(
DmP_EXP_EWSW[25]), .QN(n2430) );
DFFSX2TS R_140 ( .D(n2750), .CK(clk), .SN(n1149), .Q(n2546) );
DFFSX2TS R_99 ( .D(n2705), .CK(clk), .SN(n1149), .Q(n2573) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n527), .CK(clk), .RN(n1162), .Q(
DmP_mant_SFG_SWR[3]), .QN(n2473) );
DFFSX4TS R_98 ( .D(n2706), .CK(clk), .SN(n1150), .Q(n2574) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n531), .CK(clk), .RN(n2664),
.Q(n1132) );
DFFSX4TS R_49 ( .D(n2700), .CK(clk), .SN(n925), .Q(n2611) );
DFFRHQX4TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n549), .CK(clk), .RN(n2662), .Q(
n1104) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n844), .CK(clk), .RN(n2686),
.Q(n1109) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n854), .CK(clk), .RN(n2685),
.Q(n1143) );
DFFSX1TS R_100 ( .D(n2704), .CK(clk), .SN(n2662), .Q(n2572) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n623), .CK(clk), .RN(n924), .Q(
DMP_exp_NRM2_EW[6]) );
DFFRX2TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n773), .CK(clk), .RN(n1164),
.Q(Shift_amount_SHT1_EWR[0]), .QN(n2389) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_2_ ( .D(n718), .CK(clk), .RN(n2670), .Q(
DMP_SFG[2]), .QN(n2475) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_13_ ( .D(n685), .CK(clk), .RN(n2676), .Q(
DMP_SFG[13]), .QN(n2501) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n712), .CK(clk), .RN(n2673), .Q(
DMP_SFG[4]), .QN(n2474) );
DFFRHQX2TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n721), .CK(clk), .RN(n1159), .Q(
DMP_SFG[1]) );
DFFRHQX4TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n784), .CK(clk), .RN(n2826), .Q(
n1128) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n876), .CK(clk), .RN(n1157), .Q(
Shift_reg_FLAGS_7_6), .QN(n2444) );
DFFRX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n874), .CK(clk), .RN(n1157), .Q(
n2827), .QN(n2506) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n838), .CK(clk), .RN(n2677),
.Q(intDX_EWSW[31]), .QN(n2434) );
DFFRX2TS R_183 ( .D(n870), .CK(clk), .RN(n1156), .Q(Shift_reg_FLAGS_7[0]),
.QN(n2653) );
DFFSX4TS R_252 ( .D(n2013), .CK(clk), .SN(n2672), .QN(n880) );
DFFSX4TS R_251 ( .D(n2013), .CK(clk), .SN(n2674), .QN(n879) );
DFFRHQX2TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n574), .CK(clk), .RN(n1171),
.Q(DmP_mant_SHT1_SW[21]) );
DFFSRHQX2TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n600), .CK(clk), .SN(1'b1),
.RN(n1172), .Q(DmP_mant_SHT1_SW[8]) );
DFFSRHQX2TS R_182 ( .D(n2359), .CK(clk), .SN(n1155), .RN(1'b1), .Q(n2760) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_7_ ( .D(n603), .CK(clk), .RN(n925), .Q(n980)
);
DFFRX1TS EXP_STAGE_DMP_Q_reg_21_ ( .D(n739), .CK(clk), .RN(n924), .Q(
DMP_EXP_EWSW[21]) );
DFFRX1TS R_171 ( .D(n484), .CK(clk), .RN(n2515), .QN(n2433) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n523), .CK(clk), .RN(n1172), .Q(
DmP_mant_SFG_SWR[1]) );
DFFRX4TS inst_ShiftRegister_Q_reg_5_ ( .D(n875), .CK(clk), .RN(n1157), .Q(
Shift_reg_FLAGS_7_5), .QN(n2451) );
DFFRHQX1TS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n687), .CK(clk), .RN(n1154), .Q(
DMP_SHT1_EWSW[13]) );
DFFSRHQX2TS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n560), .CK(clk), .SN(1'b1),
.RN(n1159), .Q(ZERO_FLAG_SHT1SHT2) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n663), .CK(clk), .RN(n1159), .Q(
DMP_SHT1_EWSW[21]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_29_ ( .D(n625), .CK(clk), .RN(n2676), .Q(
DMP_SFG[29]), .QN(n2479) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n686), .CK(clk), .RN(n2676), .Q(
DMP_SHT2_EWSW[13]), .QN(n2367) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n651), .CK(clk), .RN(n2676), .Q(
DMP_SHT2_EWSW[24]), .QN(n2698) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n690), .CK(clk), .RN(n2676), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n716), .CK(clk), .RN(n2673), .Q(
DMP_SHT2_EWSW[3]), .QN(n2379) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n717), .CK(clk), .RN(n2673), .Q(
DMP_SHT1_EWSW[3]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n720), .CK(clk), .RN(n2673), .Q(
DMP_SHT1_EWSW[2]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n584), .CK(clk), .RN(n2687), .Q(
DmP_mant_SHT1_SW[16]), .QN(n2440) );
CLKMX2X2TS U904 ( .A(DmP_mant_SHT1_SW[8]), .B(DmP_EXP_EWSW[8]), .S0(n2311),
.Y(n600) );
MXI2X1TS U905 ( .A(n2457), .B(n2363), .S0(n2317), .Y(n679) );
MXI2X1TS U906 ( .A(n2454), .B(n2362), .S0(n2132), .Y(n664) );
AOI22X1TS U907 ( .A0(DmP_mant_SHT1_SW[15]), .A1(n2248), .B0(n2242), .B1(
DmP_mant_SHT1_SW[16]), .Y(n2724) );
CLKMX2X2TS U908 ( .A(Data_X[17]), .B(intDX_EWSW[17]), .S0(n2346), .Y(n852)
);
CLKMX2X2TS U909 ( .A(DmP_mant_SHT1_SW[4]), .B(n609), .S0(n2311), .Y(n608) );
CLKMX2X2TS U910 ( .A(DMP_SHT1_EWSW[16]), .B(DMP_EXP_EWSW[16]), .S0(n2318),
.Y(n678) );
MXI2X1TS U911 ( .A(n2825), .B(n2487), .S0(n2150), .Y(n562) );
MXI2X1TS U912 ( .A(n2456), .B(n2365), .S0(n2317), .Y(n673) );
MXI2X1TS U913 ( .A(n2381), .B(n2460), .S0(n2132), .Y(n658) );
AOI22X1TS U914 ( .A0(n2248), .A1(DmP_mant_SHT1_SW[11]), .B0(n2242), .B1(
DmP_mant_SHT1_SW[12]), .Y(n2736) );
CLKMX2X2TS U915 ( .A(Data_X[12]), .B(intDX_EWSW[12]), .S0(n2346), .Y(n857)
);
CLKMX2X2TS U916 ( .A(DmP_mant_SHT1_SW[20]), .B(n577), .S0(n2311), .Y(n576)
);
CLKMX2X2TS U917 ( .A(DMP_SHT1_EWSW[17]), .B(n903), .S0(n2318), .Y(n675) );
MXI2X1TS U918 ( .A(n2823), .B(n2486), .S0(n2150), .Y(n553) );
MXI2X1TS U919 ( .A(n2385), .B(n2459), .S0(n2317), .Y(n682) );
MXI2X1TS U920 ( .A(n2382), .B(n2458), .S0(n2132), .Y(n661) );
MXI2X1TS U921 ( .A(n2374), .B(n2504), .S0(n2319), .Y(n706) );
MXI2X1TS U922 ( .A(n2378), .B(n2474), .S0(n2306), .Y(n712) );
AOI22X1TS U923 ( .A0(n2248), .A1(DmP_mant_SHT1_SW[9]), .B0(n2242), .B1(
DmP_mant_SHT1_SW[10]), .Y(n2712) );
CLKMX2X3TS U924 ( .A(Data_X[26]), .B(intDX_EWSW[26]), .S0(n2344), .Y(n843)
);
BUFX3TS U925 ( .A(n2030), .Y(n2510) );
BUFX3TS U926 ( .A(n2030), .Y(n2511) );
CLKINVX3TS U927 ( .A(n923), .Y(n925) );
CLKMX2X2TS U928 ( .A(n2655), .B(DMP_exp_NRM_EW[3]), .S0(n2171), .Y(n638) );
CLKMX2X2TS U929 ( .A(DMP_SHT2_EWSW[13]), .B(DMP_SHT1_EWSW[13]), .S0(n2310),
.Y(n686) );
CLKMX2X2TS U930 ( .A(Data_Y[3]), .B(intDY_EWSW[3]), .S0(n2340), .Y(n832) );
NAND2X1TS U931 ( .A(n1938), .B(n1082), .Y(n1837) );
CLKMX2X2TS U932 ( .A(DmP_mant_SHT1_SW[7]), .B(n980), .S0(n2311), .Y(n602) );
CLKMX2X2TS U933 ( .A(DMP_SHT1_EWSW[13]), .B(n747), .S0(n2308), .Y(n687) );
CLKMX2X2TS U934 ( .A(SIGN_FLAG_SHT1), .B(SIGN_FLAG_EXP), .S0(n2318), .Y(n555) );
NAND2X1TS U935 ( .A(n1877), .B(intDX_EWSW[10]), .Y(n1834) );
NAND2X1TS U936 ( .A(n2444), .B(n741), .Y(n1996) );
NAND2X1TS U937 ( .A(n1974), .B(n757), .Y(n1975) );
CLKINVX2TS U938 ( .A(n912), .Y(n914) );
CLKMX2X2TS U939 ( .A(n2202), .B(LZD_output_NRM2_EW[2]), .S0(n1012), .Y(n520)
);
CLKINVX2TS U940 ( .A(n912), .Y(n915) );
MXI2X1TS U941 ( .A(n2455), .B(n2364), .S0(n2317), .Y(n667) );
BUFX3TS U942 ( .A(n1159), .Y(n2676) );
NOR2X1TS U943 ( .A(n2151), .B(n2125), .Y(n565) );
MXI2X1TS U944 ( .A(Data_Y[14]), .B(intDY_EWSW[14]), .S0(n2341), .Y(n1355) );
MXI2X1TS U945 ( .A(n2377), .B(n2040), .S0(n1236), .Y(n721) );
MXI2X1TS U946 ( .A(n2373), .B(n2499), .S0(n2319), .Y(n703) );
NAND2X1TS U947 ( .A(n1878), .B(n577), .Y(n1847) );
NAND2X1TS U948 ( .A(n1878), .B(n607), .Y(n1841) );
NAND2X1TS U949 ( .A(n1878), .B(n609), .Y(n1836) );
NAND2X1TS U950 ( .A(n1878), .B(n597), .Y(n1833) );
MXI2X1TS U951 ( .A(n2380), .B(n2475), .S0(n2306), .Y(n718) );
NAND2X1TS U952 ( .A(n2248), .B(DmP_mant_SHT1_SW[12]), .Y(n2754) );
NAND2X1TS U953 ( .A(n2248), .B(DmP_mant_SHT1_SW[10]), .Y(n2740) );
NAND2X1TS U954 ( .A(n2248), .B(DmP_mant_SHT1_SW[14]), .Y(n2734) );
NAND2X1TS U955 ( .A(n1968), .B(n753), .Y(n1766) );
NAND2X1TS U956 ( .A(n1968), .B(n751), .Y(n1821) );
NAND2X1TS U957 ( .A(n1968), .B(n747), .Y(n1969) );
MXI2X1TS U958 ( .A(n2379), .B(n2490), .S0(n2321), .Y(n715) );
CLKINVX2TS U959 ( .A(n912), .Y(n913) );
NAND2X1TS U960 ( .A(n2324), .B(n2064), .Y(n878) );
OR2X2TS U961 ( .A(n1025), .B(n1010), .Y(n762) );
AOI2BB2X2TS U962 ( .B0(Raw_mant_NRM_SWR[0]), .B1(n1260), .A0N(n2424), .A1N(
n1095), .Y(n2767) );
OAI2BB1X1TS U963 ( .A0N(n2203), .A1N(n1012), .B0(n1229), .Y(n521) );
AOI22X1TS U964 ( .A0(n2249), .A1(DmP_mant_SHT1_SW[19]), .B0(n2242), .B1(
DmP_mant_SHT1_SW[20]), .Y(n2772) );
NAND2X2TS U965 ( .A(n2006), .B(n1176), .Y(n2749) );
NAND2X2TS U966 ( .A(n1351), .B(n2299), .Y(n2753) );
AOI22X1TS U967 ( .A0(n2263), .A1(DmP_mant_SHT1_SW[19]), .B0(n1235), .B1(n931), .Y(n2705) );
OR2X2TS U968 ( .A(n1091), .B(n2505), .Y(n2720) );
BUFX3TS U969 ( .A(n2512), .Y(n2673) );
CLKMX2X3TS U970 ( .A(Data_X[8]), .B(intDX_EWSW[8]), .S0(n2345), .Y(n861) );
CLKMX2X3TS U971 ( .A(Data_X[28]), .B(intDX_EWSW[28]), .S0(n2344), .Y(n841)
);
CLKMX2X3TS U972 ( .A(Data_X[16]), .B(intDX_EWSW[16]), .S0(n2346), .Y(n853)
);
CLKMX2X3TS U973 ( .A(Data_Y[29]), .B(intDY_EWSW[29]), .S0(n2343), .Y(n806)
);
MXI2X2TS U974 ( .A(n1490), .B(n2464), .S0(n2132), .Y(n480) );
NAND3X2TS U975 ( .A(n2005), .B(n2004), .C(n2003), .Y(n739) );
MXI2X2TS U976 ( .A(n1712), .B(n2494), .S0(n2150), .Y(n477) );
INVX8TS U977 ( .A(n2307), .Y(n2311) );
INVX6TS U978 ( .A(n2307), .Y(n2318) );
INVX6TS U979 ( .A(n2307), .Y(n2308) );
OAI21X2TS U980 ( .A0(n2337), .A1(n2136), .B0(n2135), .Y(n2140) );
NAND2X2TS U981 ( .A(n1093), .B(intDX_EWSW[7]), .Y(n1888) );
BUFX3TS U982 ( .A(n2030), .Y(n2512) );
INVX2TS U983 ( .A(n930), .Y(n1153) );
BUFX4TS U984 ( .A(n2824), .Y(n2150) );
OAI2BB1X2TS U985 ( .A0N(n2153), .A1N(n2152), .B0(n2151), .Y(n2154) );
BUFX4TS U986 ( .A(n2824), .Y(n2132) );
NAND3X1TS U987 ( .A(n965), .B(n964), .C(n963), .Y(n597) );
NAND3X1TS U988 ( .A(n971), .B(n970), .C(n969), .Y(n607) );
BUFX4TS U989 ( .A(n1877), .Y(n933) );
NAND3X1TS U990 ( .A(n968), .B(n967), .C(n966), .Y(n609) );
NAND3X1TS U991 ( .A(n956), .B(n955), .C(n954), .Y(n577) );
NAND3X1TS U992 ( .A(n959), .B(n958), .C(n957), .Y(n747) );
NAND3X1TS U993 ( .A(n974), .B(n973), .C(n972), .Y(n757) );
NAND3X1TS U994 ( .A(n953), .B(n952), .C(n951), .Y(n753) );
NAND3X1TS U995 ( .A(n977), .B(n976), .C(n975), .Y(n751) );
NAND3X1TS U996 ( .A(n950), .B(n949), .C(n948), .Y(n741) );
NAND3X1TS U997 ( .A(n962), .B(n961), .C(n960), .Y(n593) );
NAND2X2TS U998 ( .A(n1972), .B(intDY_EWSW[29]), .Y(n1894) );
INVX1TS U999 ( .A(n1102), .Y(n1103) );
NAND2X2TS U1000 ( .A(n891), .B(intDX_EWSW[23]), .Y(n1743) );
NAND2X2TS U1001 ( .A(intDY_EWSW[24]), .B(n2008), .Y(n1752) );
NAND2X1TS U1002 ( .A(n1536), .B(n1535), .Y(n2059) );
NAND3X1TS U1003 ( .A(n1075), .B(n1352), .C(n1123), .Y(n1292) );
NAND2XLTS U1004 ( .A(n931), .B(n2173), .Y(n2174) );
NAND2XLTS U1005 ( .A(n2444), .B(n903), .Y(n1990) );
NAND2X1TS U1006 ( .A(n2295), .B(n1132), .Y(n1313) );
NAND2X1TS U1007 ( .A(n2659), .B(n1059), .Y(n1224) );
NAND2X1TS U1008 ( .A(n1179), .B(n1112), .Y(n1936) );
OAI21X1TS U1009 ( .A0(n2337), .A1(n2333), .B0(n2334), .Y(n2332) );
NAND2X2TS U1010 ( .A(n1938), .B(intDY_EWSW[25]), .Y(n1758) );
NAND2X2TS U1011 ( .A(n1973), .B(intDY_EWSW[25]), .Y(n1745) );
CLKBUFX2TS U1012 ( .A(n2654), .Y(n932) );
AND2X2TS U1013 ( .A(n1412), .B(n1411), .Y(n1490) );
NAND2XLTS U1014 ( .A(n1943), .B(DmP_EXP_EWSW[26]), .Y(n1738) );
NAND2X1TS U1015 ( .A(n2295), .B(Raw_mant_NRM_SWR[6]), .Y(n1290) );
INVX2TS U1016 ( .A(n1160), .Y(n1170) );
AND2X2TS U1017 ( .A(n1442), .B(n1441), .Y(n1712) );
NAND2XLTS U1018 ( .A(n1974), .B(DmP_EXP_EWSW[14]), .Y(n1824) );
NAND2XLTS U1019 ( .A(n1974), .B(DMP_EXP_EWSW[4]), .Y(n1965) );
NAND2XLTS U1020 ( .A(n1974), .B(DMP_EXP_EWSW[6]), .Y(n1950) );
NAND2XLTS U1021 ( .A(n1974), .B(DMP_EXP_EWSW[5]), .Y(n1953) );
NAND2XLTS U1022 ( .A(n2659), .B(Raw_mant_NRM_SWR[7]), .Y(n1219) );
NAND2XLTS U1023 ( .A(n1943), .B(DMP_EXP_EWSW[29]), .Y(n1892) );
AOI22X2TS U1024 ( .A0(n2157), .A1(n1180), .B0(n2108), .B1(n1064), .Y(n2822)
);
XNOR2X2TS U1025 ( .A(n1208), .B(n2200), .Y(n2201) );
CLKINVX2TS U1026 ( .A(n1159), .Y(n923) );
AOI22X2TS U1027 ( .A0(n1423), .A1(n1180), .B0(n2070), .B1(n2108), .Y(n999)
);
NAND2XLTS U1028 ( .A(n2060), .B(DmP_EXP_EWSW[1]), .Y(n1865) );
NAND2XLTS U1029 ( .A(n2060), .B(DMP_EXP_EWSW[28]), .Y(n1889) );
NAND2XLTS U1030 ( .A(n2060), .B(DMP_EXP_EWSW[30]), .Y(n2010) );
NAND2XLTS U1031 ( .A(n2060), .B(DmP_EXP_EWSW[2]), .Y(n1859) );
INVX8TS U1032 ( .A(n1678), .Y(n2249) );
NAND3XLTS U1033 ( .A(n1012), .B(Shift_amount_SHT1_EWR[4]), .C(n2320), .Y(
n2175) );
NAND2X1TS U1034 ( .A(n2306), .B(n1212), .Y(n1211) );
NAND2XLTS U1035 ( .A(n1968), .B(DMP_EXP_EWSW[11]), .Y(n1818) );
NAND2XLTS U1036 ( .A(n1878), .B(DmP_EXP_EWSW[6]), .Y(n1830) );
NAND2XLTS U1037 ( .A(n1943), .B(DMP_EXP_EWSW[1]), .Y(n1944) );
NAND2XLTS U1038 ( .A(n1968), .B(DMP_EXP_EWSW[8]), .Y(n1962) );
NAND2XLTS U1039 ( .A(n1878), .B(DmP_EXP_EWSW[9]), .Y(n1827) );
NAND2XLTS U1040 ( .A(n1878), .B(DmP_EXP_EWSW[21]), .Y(n1871) );
NAND2XLTS U1041 ( .A(n1878), .B(DmP_EXP_EWSW[15]), .Y(n1874) );
NAND2XLTS U1042 ( .A(n1968), .B(DMP_EXP_EWSW[10]), .Y(n1947) );
NAND2XLTS U1043 ( .A(n1968), .B(DMP_EXP_EWSW[12]), .Y(n1956) );
NAND2XLTS U1044 ( .A(n2330), .B(n2329), .Y(n2331) );
NAND2XLTS U1045 ( .A(n2138), .B(n2137), .Y(n2139) );
BUFX12TS U1046 ( .A(n1268), .Y(n1260) );
BUFX8TS U1047 ( .A(n1093), .Y(n934) );
NAND2X6TS U1048 ( .A(n2226), .B(n1177), .Y(n1307) );
NAND2X2TS U1049 ( .A(n2242), .B(DmP_mant_SHT1_SW[7]), .Y(n1301) );
OAI22X1TS U1050 ( .A0(n2237), .A1(n2236), .B0(n2235), .B1(n930), .Y(n2238)
);
XOR2X2TS U1051 ( .A(n1918), .B(n987), .Y(n1291) );
BUFX6TS U1052 ( .A(n2299), .Y(n1174) );
NAND2BXLTS U1053 ( .AN(n1124), .B(n2659), .Y(n1311) );
BUFX8TS U1054 ( .A(n2252), .Y(n1091) );
BUFX8TS U1055 ( .A(n2252), .Y(n1092) );
AND2X2TS U1056 ( .A(n1489), .B(n1488), .Y(n2124) );
INVX2TS U1057 ( .A(n2666), .Y(n912) );
OR2X6TS U1058 ( .A(n1229), .B(n2386), .Y(n2224) );
INVX6TS U1059 ( .A(n2248), .Y(n1678) );
BUFX6TS U1060 ( .A(n1885), .Y(n1943) );
CLKINVX6TS U1061 ( .A(n1175), .Y(n1177) );
BUFX6TS U1062 ( .A(n1885), .Y(n1968) );
BUFX6TS U1063 ( .A(n1885), .Y(n1878) );
INVX4TS U1064 ( .A(rst), .Y(n1159) );
INVX12TS U1065 ( .A(n1257), .Y(n2299) );
OAI21X2TS U1066 ( .A0(n2187), .A1(n2179), .B0(n2178), .Y(n2183) );
NAND2XLTS U1067 ( .A(n1404), .B(n1403), .Y(n1016) );
CLKBUFX2TS U1068 ( .A(intDX_EWSW[13]), .Y(n935) );
BUFX3TS U1069 ( .A(n891), .Y(n889) );
NAND2XLTS U1070 ( .A(n992), .B(n2214), .Y(n2215) );
NAND2X2TS U1071 ( .A(n2111), .B(n1180), .Y(n1489) );
NOR2X2TS U1072 ( .A(n1477), .B(n2285), .Y(n1027) );
OAI21X2TS U1073 ( .A0(n1077), .A1(n2387), .B0(n1327), .Y(n1326) );
BUFX3TS U1074 ( .A(n2452), .Y(n2295) );
NAND2XLTS U1075 ( .A(n2185), .B(n1271), .Y(n2161) );
BUFX3TS U1076 ( .A(n2452), .Y(n1179) );
OAI2BB1X2TS U1077 ( .A0N(n2126), .A1N(n2156), .B0(n1381), .Y(n1383) );
CLKBUFX2TS U1078 ( .A(n2671), .Y(n2666) );
MXI2X2TS U1079 ( .A(n2083), .B(n2082), .S0(n2143), .Y(n2086) );
MXI2X2TS U1080 ( .A(n1813), .B(n1812), .S0(n1180), .Y(n1412) );
NOR2X4TS U1081 ( .A(n1017), .B(n1222), .Y(n556) );
NAND2X6TS U1082 ( .A(n1039), .B(n1197), .Y(n1038) );
NAND2XLTS U1083 ( .A(n1332), .B(n2205), .Y(n2207) );
NAND2X1TS U1084 ( .A(n2272), .B(n2271), .Y(n2273) );
BUFX3TS U1085 ( .A(n1106), .Y(n1075) );
INVX4TS U1086 ( .A(n879), .Y(n921) );
NOR2BX1TS U1087 ( .AN(final_result_ieee[29]), .B(Shift_reg_FLAGS_7[0]), .Y(
n1026) );
BUFX3TS U1088 ( .A(n2452), .Y(n2659) );
CLKBUFX2TS U1089 ( .A(n1154), .Y(n2668) );
INVX3TS U1090 ( .A(n1152), .Y(n1167) );
BUFX6TS U1091 ( .A(n1097), .Y(n890) );
BUFX4TS U1092 ( .A(n2312), .Y(n1168) );
INVX6TS U1093 ( .A(n1175), .Y(n1176) );
INVX2TS U1094 ( .A(n1984), .Y(n888) );
OR2X4TS U1095 ( .A(n1276), .B(n1208), .Y(n988) );
NAND2XLTS U1096 ( .A(n2223), .B(DmP_mant_SHT1_SW[13]), .Y(n1327) );
BUFX6TS U1097 ( .A(n2237), .Y(n1257) );
OR2X6TS U1098 ( .A(n991), .B(n1433), .Y(n1357) );
INVX2TS U1099 ( .A(n2160), .Y(n2187) );
NAND2X1TS U1100 ( .A(n2297), .B(DmP_mant_SHT1_SW[17]), .Y(n2259) );
INVX8TS U1101 ( .A(n1146), .Y(n1352) );
INVX2TS U1102 ( .A(n2691), .Y(n2690) );
BUFX6TS U1103 ( .A(Shift_reg_FLAGS_7[2]), .Y(n2312) );
BUFX3TS U1104 ( .A(n2824), .Y(n2306) );
INVX2TS U1105 ( .A(n2066), .Y(n2269) );
INVX12TS U1106 ( .A(n2009), .Y(n892) );
CLKINVX12TS U1107 ( .A(n1041), .Y(n1175) );
INVX2TS U1108 ( .A(Shift_reg_FLAGS_7[0]), .Y(n2285) );
NAND2XLTS U1109 ( .A(n1911), .B(n1910), .Y(n1912) );
OA21X2TS U1110 ( .A0(n1341), .A1(n1339), .B0(n1337), .Y(n1336) );
NAND2XLTS U1111 ( .A(n1152), .B(n1128), .Y(n1304) );
NAND2X4TS U1112 ( .A(n1208), .B(n1312), .Y(n1039) );
INVX4TS U1113 ( .A(n2156), .Y(n1180) );
NOR2BX2TS U1114 ( .AN(n1340), .B(n1681), .Y(n1402) );
NAND2X2TS U1115 ( .A(n1178), .B(n2105), .Y(n1697) );
CLKBUFX2TS U1116 ( .A(n2691), .Y(n2266) );
NAND3X2TS U1117 ( .A(n1380), .B(n1379), .C(n1378), .Y(n2126) );
NAND2X2TS U1118 ( .A(n1178), .B(n2084), .Y(n1419) );
OAI21X2TS U1119 ( .A0(n1686), .A1(n1925), .B0(n1931), .Y(n1316) );
CLKAND2X2TS U1120 ( .A(n2223), .B(DmP_mant_SHT1_SW[19]), .Y(n1018) );
OAI21X2TS U1121 ( .A0(n1686), .A1(n1685), .B0(n1684), .Y(n1249) );
NAND2X1TS U1122 ( .A(n1178), .B(n2253), .Y(n1797) );
NAND2X1TS U1123 ( .A(Raw_mant_NRM_SWR[0]), .B(n2168), .Y(n2170) );
NOR2X1TS U1124 ( .A(n1508), .B(n1507), .Y(n1531) );
CLKINVX1TS U1125 ( .A(n1098), .Y(n905) );
BUFX6TS U1126 ( .A(n1398), .Y(n2155) );
NAND2X1TS U1127 ( .A(n2095), .B(n1235), .Y(n1376) );
BUFX3TS U1128 ( .A(n1774), .Y(n1131) );
BUFX16TS U1129 ( .A(n1278), .Y(n1208) );
NAND2X4TS U1130 ( .A(n2168), .B(n1802), .Y(n2169) );
NAND2X1TS U1131 ( .A(n1178), .B(n2094), .Y(n2099) );
INVX4TS U1132 ( .A(n1259), .Y(n1354) );
NOR2X1TS U1133 ( .A(n1791), .B(n2257), .Y(n1692) );
AO22XLTS U1134 ( .A0(n2223), .A1(DmP_mant_SHT1_SW[5]), .B0(n2296), .B1(
DmP_mant_SHT1_SW[4]), .Y(n984) );
INVX2TS U1135 ( .A(n2292), .Y(n1681) );
OR2X4TS U1136 ( .A(n1077), .B(n1284), .Y(n1080) );
INVX4TS U1137 ( .A(n2218), .Y(n2297) );
NOR2X1TS U1138 ( .A(n1393), .B(n1342), .Y(n1275) );
NOR2X6TS U1139 ( .A(n1472), .B(n2141), .Y(n1479) );
INVX4TS U1140 ( .A(n930), .Y(n1152) );
NAND2X1TS U1141 ( .A(n1393), .B(n1279), .Y(n1276) );
NAND2X2TS U1142 ( .A(n2093), .B(n2253), .Y(n1484) );
NAND2X2TS U1143 ( .A(n1178), .B(n2258), .Y(n1485) );
NAND2X2TS U1144 ( .A(n1178), .B(n2250), .Y(n1725) );
OR2X1TS U1145 ( .A(n1791), .B(n1138), .Y(n1074) );
INVX2TS U1146 ( .A(n2206), .Y(n1312) );
XOR2X1TS U1147 ( .A(n886), .B(intDX_EWSW[7]), .Y(n1496) );
NAND2X2TS U1148 ( .A(n2093), .B(n2250), .Y(n2075) );
AOI21X2TS U1149 ( .A0(n2134), .A1(n2138), .B0(n1906), .Y(n1907) );
NOR2X2TS U1150 ( .A(n1804), .B(n1770), .Y(n1808) );
AOI22X2TS U1151 ( .A0(n2129), .A1(n2246), .B0(n2117), .B1(n2145), .Y(n1705)
);
AND2X2TS U1152 ( .A(n1392), .B(n1391), .Y(n1393) );
INVX2TS U1153 ( .A(n1434), .Y(n2014) );
INVX2TS U1154 ( .A(n1141), .Y(n2246) );
INVX2TS U1155 ( .A(n1903), .Y(n2138) );
INVX2TS U1156 ( .A(n2204), .Y(n1332) );
INVX2TS U1157 ( .A(n1333), .Y(n1335) );
NOR2X2TS U1158 ( .A(n1368), .B(n1339), .Y(n1338) );
INVX4TS U1159 ( .A(n2143), .Y(n1382) );
NOR2X6TS U1160 ( .A(n1334), .B(n2204), .Y(n1330) );
XNOR2X1TS U1161 ( .A(n1116), .B(n1082), .Y(n1513) );
NAND2X2TS U1162 ( .A(n947), .B(DMP_EXP_EWSW[24]), .Y(n2037) );
XNOR2X2TS U1163 ( .A(intDY_EWSW[20]), .B(n1120), .Y(n1501) );
XOR2X2TS U1164 ( .A(intDY_EWSW[2]), .B(n1126), .Y(n1514) );
XOR2X2TS U1165 ( .A(intDY_EWSW[16]), .B(n1145), .Y(n1519) );
XNOR2X2TS U1166 ( .A(intDY_EWSW[6]), .B(n1111), .Y(n1521) );
NAND2X2TS U1167 ( .A(n2071), .B(n2070), .Y(n1408) );
XNOR2X2TS U1168 ( .A(intDY_EWSW[17]), .B(intDX_EWSW[17]), .Y(n1502) );
NAND2X2TS U1169 ( .A(n2055), .B(DMP_SFG[1]), .Y(n1713) );
XNOR2X2TS U1170 ( .A(intDY_EWSW[21]), .B(n1129), .Y(n1506) );
INVX4TS U1171 ( .A(n1022), .Y(n1122) );
XNOR2X2TS U1172 ( .A(intDY_EWSW[29]), .B(intDX_EWSW[29]), .Y(n1525) );
XNOR2X2TS U1173 ( .A(intDY_EWSW[28]), .B(intDX_EWSW[28]), .Y(n1524) );
XNOR2X2TS U1174 ( .A(intDY_EWSW[26]), .B(intDX_EWSW[26]), .Y(n1492) );
AND2X4TS U1175 ( .A(n2288), .B(n2283), .Y(n1453) );
BUFX6TS U1176 ( .A(n1398), .Y(n2147) );
XNOR2X1TS U1177 ( .A(n1089), .B(n1121), .Y(n1520) );
CLKXOR2X2TS U1178 ( .A(intDY_EWSW[13]), .B(n1125), .Y(n1509) );
XNOR2X1TS U1179 ( .A(intDY_EWSW[27]), .B(n1119), .Y(n1493) );
XNOR2X1TS U1180 ( .A(intDY_EWSW[12]), .B(intDX_EWSW[12]), .Y(n1512) );
NAND2X2TS U1181 ( .A(n1932), .B(DMP_SFG[22]), .Y(n2205) );
INVX6TS U1182 ( .A(n1407), .Y(n2095) );
INVX2TS U1183 ( .A(n995), .Y(n1279) );
BUFX6TS U1184 ( .A(n1227), .Y(n1207) );
AND4X2TS U1185 ( .A(n1142), .B(n2641), .C(n2640), .D(n2639), .Y(n1141) );
NOR2X4TS U1186 ( .A(n1932), .B(DMP_SFG[22]), .Y(n2204) );
OR2X2TS U1187 ( .A(n1188), .B(n2499), .Y(n2329) );
NAND4X4TS U1188 ( .A(n2618), .B(n2617), .C(n2616), .D(n2615), .Y(n1814) );
INVX2TS U1189 ( .A(n1340), .Y(n1339) );
NAND2X2TS U1190 ( .A(n1228), .B(n2260), .Y(n1439) );
NAND2X2TS U1191 ( .A(n2093), .B(n2105), .Y(n1703) );
NAND2X2TS U1192 ( .A(n1899), .B(DMP_SFG[5]), .Y(n1920) );
NOR2X2TS U1193 ( .A(n2288), .B(n2283), .Y(n1466) );
NAND2X1TS U1194 ( .A(DmP_mant_SFG_SWR_signed[5]), .B(DMP_SFG[3]), .Y(n2271)
);
NOR2X2TS U1195 ( .A(DmP_mant_SFG_SWR_signed[5]), .B(DMP_SFG[3]), .Y(n2270)
);
NOR2X6TS U1196 ( .A(n1899), .B(DMP_SFG[5]), .Y(n1919) );
NAND2X2TS U1197 ( .A(n1210), .B(n2501), .Y(n2194) );
XNOR2X2TS U1198 ( .A(n1451), .B(DMP_exp_NRM2_EW[0]), .Y(n2283) );
INVX8TS U1199 ( .A(n2143), .Y(n2156) );
NOR2X4TS U1200 ( .A(n1358), .B(DMP_exp_NRM2_EW[4]), .Y(n1474) );
NAND2X1TS U1201 ( .A(n2347), .B(Shift_amount_SHT1_EWR[1]), .Y(n1266) );
NOR2X4TS U1202 ( .A(Shift_amount_SHT1_EWR[0]), .B(n2171), .Y(n2296) );
NAND2X2TS U1203 ( .A(n1674), .B(n1263), .Y(n1234) );
BUFX6TS U1204 ( .A(left_right_SHT2), .Y(n2143) );
OR2X6TS U1205 ( .A(n1372), .B(DMP_SFG[20]), .Y(n1924) );
OR2X6TS U1206 ( .A(n1365), .B(DMP_SFG[17]), .Y(n992) );
NOR2X4TS U1207 ( .A(n1361), .B(DMP_SFG[14]), .Y(n1342) );
NOR2X4TS U1208 ( .A(n1617), .B(n1590), .Y(n1597) );
NOR2X2TS U1209 ( .A(n1660), .B(n1429), .Y(n1430) );
NAND2X4TS U1210 ( .A(n1184), .B(n2488), .Y(n1340) );
INVX2TS U1211 ( .A(n2180), .Y(n1242) );
OR2X4TS U1212 ( .A(n1362), .B(DMP_SFG[15]), .Y(n1391) );
OR2X4TS U1213 ( .A(n1688), .B(DMP_SFG[21]), .Y(n1929) );
INVX4TS U1214 ( .A(n2179), .Y(n1245) );
OR2X4TS U1215 ( .A(n1320), .B(n1269), .Y(n986) );
NOR2X2TS U1216 ( .A(n1104), .B(n1098), .Y(n1775) );
INVX4TS U1217 ( .A(n1449), .Y(n1030) );
NOR2X6TS U1218 ( .A(n1444), .B(DMP_exp_NRM2_EW[3]), .Y(n1457) );
NAND2X2TS U1219 ( .A(DMP_SFG[11]), .B(n1201), .Y(n2188) );
NAND2X6TS U1220 ( .A(n1539), .B(n1579), .Y(n1582) );
NAND2X6TS U1221 ( .A(n1614), .B(n1589), .Y(n1617) );
NAND2X4TS U1222 ( .A(n1444), .B(n2655), .Y(n1455) );
NAND2X4TS U1223 ( .A(n937), .B(n1006), .Y(n1562) );
NOR2X2TS U1224 ( .A(n990), .B(n1238), .Y(n1283) );
INVX4TS U1225 ( .A(n1202), .Y(n2189) );
CLKINVX6TS U1226 ( .A(Shift_reg_FLAGS_7[1]), .Y(n2347) );
AND2X6TS U1227 ( .A(n1253), .B(n1772), .Y(n1032) );
NOR2X6TS U1228 ( .A(n1594), .B(n1629), .Y(n1595) );
CLKAND2X2TS U1229 ( .A(n2358), .B(Raw_mant_NRM_SWR[6]), .Y(n1323) );
NOR2X6TS U1230 ( .A(n1603), .B(n1195), .Y(n1605) );
INVX2TS U1231 ( .A(n1112), .Y(n1113) );
INVX4TS U1232 ( .A(n2293), .Y(n1309) );
OR2X4TS U1233 ( .A(n2399), .B(intDX_EWSW[30]), .Y(n1631) );
OAI21X2TS U1234 ( .A0(n1557), .A1(n1556), .B0(n1555), .Y(n1560) );
NAND2X4TS U1235 ( .A(n1431), .B(n978), .Y(n1238) );
OAI21X2TS U1236 ( .A0(n1057), .A1(n1056), .B0(n1067), .Y(n1653) );
INVX12TS U1237 ( .A(n1660), .Y(n1778) );
NOR2X2TS U1238 ( .A(n1557), .B(n1554), .Y(n1006) );
NOR2X4TS U1239 ( .A(n1588), .B(n1609), .Y(n1589) );
INVX6TS U1240 ( .A(n1147), .Y(n1192) );
AND2X6TS U1241 ( .A(n1083), .B(n1084), .Y(n1538) );
NOR2X4TS U1242 ( .A(n1112), .B(n1055), .Y(n1431) );
NAND2X1TS U1243 ( .A(n1044), .B(n1127), .Y(n1544) );
INVX4TS U1244 ( .A(n1055), .Y(n1056) );
NOR2X2TS U1245 ( .A(n1117), .B(n1082), .Y(n1554) );
INVX2TS U1246 ( .A(n544), .Y(n1036) );
NOR2X4TS U1247 ( .A(n2398), .B(n1048), .Y(n1566) );
CLKAND2X2TS U1248 ( .A(n1043), .B(n1046), .Y(n1546) );
NOR2X6TS U1249 ( .A(DMP_SFG[9]), .B(DmP_mant_SFG_SWR_signed[11]), .Y(n1909)
);
NOR2X6TS U1250 ( .A(n1201), .B(DMP_SFG[11]), .Y(n1202) );
NAND2X2TS U1251 ( .A(DmP_mant_SFG_SWR_signed[11]), .B(DMP_SFG[9]), .Y(n1910)
);
NOR2X4TS U1252 ( .A(n2412), .B(n1111), .Y(n936) );
NAND2X2TS U1253 ( .A(n2400), .B(n1119), .Y(n1621) );
NAND2X2TS U1254 ( .A(n1090), .B(n1121), .Y(n1555) );
NAND2X2TS U1255 ( .A(n2402), .B(n1129), .Y(n1607) );
NOR2X2TS U1256 ( .A(n2392), .B(n1118), .Y(n1591) );
CLKAND2X4TS U1257 ( .A(n1324), .B(n978), .Y(n1002) );
NAND2X4TS U1258 ( .A(n2412), .B(n1111), .Y(n939) );
NAND2X4TS U1259 ( .A(n1649), .B(n1668), .Y(n1658) );
NOR2X2TS U1260 ( .A(n1055), .B(n1102), .Y(n1325) );
INVX2TS U1261 ( .A(n1098), .Y(n1099) );
NAND2X2TS U1262 ( .A(n1284), .B(Raw_mant_NRM_SWR[0]), .Y(n1252) );
NAND2X6TS U1263 ( .A(n1657), .B(n1256), .Y(n1255) );
INVX6TS U1264 ( .A(n1132), .Y(n1133) );
NOR2X2TS U1265 ( .A(n1112), .B(n1066), .Y(n1256) );
NAND3X6TS U1266 ( .A(n1642), .B(n1643), .C(n1093), .Y(n1648) );
NAND4X6TS U1267 ( .A(n2610), .B(n2609), .C(n2608), .D(n2607), .Y(n1434) );
NAND4X4TS U1268 ( .A(n2090), .B(n2089), .C(n2088), .D(n2087), .Y(n2120) );
AND2X6TS U1269 ( .A(n1727), .B(n1726), .Y(n2820) );
AND2X6TS U1270 ( .A(n1730), .B(n1729), .Y(n2789) );
MXI2X4TS U1271 ( .A(n2127), .B(n2126), .S0(n2143), .Y(n2131) );
OAI21X2TS U1272 ( .A0(n2051), .A1(n2050), .B0(n2049), .Y(n2053) );
OAI22X4TS U1273 ( .A0(n2042), .A1(n2041), .B0(DMP_EXP_EWSW[25]), .B1(n2430),
.Y(n2051) );
OAI21X4TS U1274 ( .A0(n1314), .A1(n2659), .B0(n1313), .Y(n531) );
INVX4TS U1275 ( .A(n1068), .Y(n2106) );
NAND4X4TS U1276 ( .A(n2100), .B(n2099), .C(n2098), .D(n2097), .Y(n2103) );
NAND2X4TS U1277 ( .A(n1217), .B(n1216), .Y(n536) );
NAND4X6TS U1278 ( .A(n1725), .B(n1724), .C(n1723), .D(n1722), .Y(n1728) );
NAND4X6TS U1279 ( .A(n1699), .B(n1700), .C(n1698), .D(n1697), .Y(n2157) );
NAND2X6TS U1280 ( .A(n1218), .B(n1168), .Y(n1217) );
MX2X4TS U1281 ( .A(n1139), .B(DmP_mant_SFG_SWR[1]), .S0(n2306), .Y(n523) );
NAND4BX2TS U1282 ( .AN(n2583), .B(n2582), .C(n2581), .D(n2580), .Y(n1691) );
NAND4X6TS U1283 ( .A(n1485), .B(n1484), .C(n1483), .D(n1482), .Y(n2111) );
BUFX20TS U1284 ( .A(n1790), .Y(n1690) );
NAND2X8TS U1285 ( .A(n2297), .B(n1041), .Y(n2252) );
NAND2X2TS U1286 ( .A(n989), .B(n2070), .Y(n2073) );
NAND3X8TS U1287 ( .A(n988), .B(n1272), .C(n1274), .Y(n1218) );
AND4X4TS U1288 ( .A(n1232), .B(n1452), .C(n1453), .D(n2278), .Y(n1464) );
AND2X6TS U1289 ( .A(n2114), .B(n2113), .Y(n2792) );
INVX12TS U1290 ( .A(n1683), .Y(n1931) );
INVX16TS U1291 ( .A(n1280), .Y(n2248) );
NAND2X8TS U1292 ( .A(n1281), .B(n1088), .Y(n1280) );
NAND2X8TS U1293 ( .A(n1317), .B(n2028), .Y(n2233) );
XNOR2X4TS U1294 ( .A(n2183), .B(n2182), .Y(n2184) );
NAND2X4TS U1295 ( .A(n1228), .B(n2094), .Y(n1694) );
NAND4X4TS U1296 ( .A(n2571), .B(n2570), .C(n2569), .D(n2568), .Y(n2239) );
AOI22X1TS U1297 ( .A0(DmP_mant_SHT1_SW[17]), .A1(n2249), .B0(n2242), .B1(
DmP_mant_SHT1_SW[18]), .Y(n2700) );
AOI22X1TS U1298 ( .A0(n2249), .A1(DmP_mant_SHT1_SW[13]), .B0(n2242), .B1(
DmP_mant_SHT1_SW[14]), .Y(n2716) );
AOI22X2TS U1299 ( .A0(n2129), .A1(n2253), .B0(n2117), .B1(n2121), .Y(n2091)
);
NAND4X6TS U1300 ( .A(n2169), .B(n1811), .C(n1810), .D(n1809), .Y(n2024) );
OAI21X2TS U1301 ( .A0(n1167), .A1(n2397), .B0(n1785), .Y(n777) );
MXI2X2TS U1302 ( .A(n2288), .B(final_result_ieee[24]), .S0(n2691), .Y(n2289)
);
BUFX16TS U1303 ( .A(intDY_EWSW[7]), .Y(n886) );
NAND3X4TS U1304 ( .A(n2176), .B(n2175), .C(n2174), .Y(n774) );
NAND2X6TS U1305 ( .A(n1282), .B(n986), .Y(n1265) );
NAND2X8TS U1306 ( .A(n1206), .B(n1205), .Y(n2359) );
NOR2X8TS U1307 ( .A(n1791), .B(n2156), .Y(n1398) );
NAND2BX4TS U1308 ( .AN(DMP_exp_NRM2_EW[5]), .B(n1473), .Y(n1065) );
NAND4X4TS U1309 ( .A(n1502), .B(n1501), .C(n1500), .D(n1499), .Y(n1508) );
NAND3X6TS U1310 ( .A(n1397), .B(n1396), .C(n1395), .Y(n2082) );
NAND2X4TS U1311 ( .A(n2233), .B(n1176), .Y(n2029) );
BUFX20TS U1312 ( .A(n1677), .Y(n2242) );
NAND2X6TS U1313 ( .A(n1227), .B(n2391), .Y(n1790) );
NAND2X8TS U1314 ( .A(n1308), .B(n1403), .Y(n1683) );
NAND2X8TS U1315 ( .A(n1404), .B(n1309), .Y(n1308) );
NAND4BX4TS U1316 ( .AN(n2579), .B(n2578), .C(n2577), .D(n2576), .Y(n2250) );
MXI2X2TS U1317 ( .A(n2792), .B(n2390), .S0(n2132), .Y(n491) );
AOI22X2TS U1318 ( .A0(n1260), .A1(n1059), .B0(n2242), .B1(
DmP_mant_SHT1_SW[3]), .Y(n2778) );
AOI21X2TS U1319 ( .A0(n1260), .A1(Raw_mant_NRM_SWR[3]), .B0(n2238), .Y(n2748) );
AOI22X2TS U1320 ( .A0(n979), .A1(n1260), .B0(n2242), .B1(DmP_mant_SHT1_SW[4]), .Y(n2782) );
AOI21X2TS U1321 ( .A0(n1166), .A1(Raw_mant_NRM_SWR[7]), .B0(n2221), .Y(n2744) );
AOI22X2TS U1322 ( .A0(n1055), .A1(n1166), .B0(n2242), .B1(
DmP_mant_SHT1_SW[8]), .Y(n2770) );
NAND3X6TS U1323 ( .A(n1410), .B(n1409), .C(n1408), .Y(n1812) );
NAND2X6TS U1324 ( .A(n2172), .B(n1181), .Y(n2176) );
XNOR2X4TS U1325 ( .A(n2191), .B(n2190), .Y(n2192) );
OAI21X4TS U1326 ( .A0(n2187), .A1(n2186), .B0(n2185), .Y(n2191) );
MXI2X4TS U1327 ( .A(n2806), .B(n2467), .S0(n2132), .Y(n483) );
OR2X6TS U1328 ( .A(n928), .B(n1343), .Y(n2007) );
NAND3X8TS U1329 ( .A(n1895), .B(n1896), .C(n1897), .Y(n2305) );
NAND2X4TS U1330 ( .A(n889), .B(intDY_EWSW[9]), .Y(n1823) );
NAND2X4TS U1331 ( .A(n889), .B(intDX_EWSW[22]), .Y(n1845) );
NAND2X8TS U1332 ( .A(n1310), .B(n2364), .Y(n1404) );
INVX8TS U1333 ( .A(n1203), .Y(n1310) );
INVX4TS U1334 ( .A(n1454), .Y(n1446) );
INVX16TS U1335 ( .A(n1024), .Y(n1475) );
OAI22X2TS U1336 ( .A0(n1712), .A1(n2013), .B0(n2689), .B1(n2498), .Y(n505)
);
OAI2BB2X2TS U1337 ( .B0(n1490), .B1(n2013), .A0N(n2266), .A1N(
final_result_ieee[13]), .Y(n509) );
OAI2BB2X2TS U1338 ( .B0(n2124), .B1(n2013), .A0N(n2691), .A1N(
final_result_ieee[19]), .Y(n499) );
NAND2X4TS U1339 ( .A(n2290), .B(n2289), .Y(n767) );
NAND2X4TS U1340 ( .A(n2290), .B(n2287), .Y(n763) );
NAND2X4TS U1341 ( .A(n2290), .B(n2284), .Y(n768) );
NAND2X4TS U1342 ( .A(n2290), .B(n2281), .Y(n764) );
NAND2X4TS U1343 ( .A(n2290), .B(n2279), .Y(n766) );
NAND2X4TS U1344 ( .A(n2290), .B(n2277), .Y(n765) );
NOR2X6TS U1345 ( .A(n1270), .B(n931), .Y(n1041) );
NAND2X8TS U1346 ( .A(n1244), .B(n2500), .Y(n2181) );
NOR2X4TS U1347 ( .A(n1099), .B(n1045), .Y(n2022) );
NAND2X6TS U1348 ( .A(n1187), .B(n1186), .Y(n1223) );
NAND2X4TS U1349 ( .A(n1200), .B(n2436), .Y(n1271) );
NAND2X4TS U1350 ( .A(n2301), .B(n1174), .Y(n2741) );
NAND2X4TS U1351 ( .A(n2301), .B(n1176), .Y(n2752) );
NAND3X4TS U1352 ( .A(n1746), .B(n1745), .C(n1744), .Y(n569) );
NAND3X2TS U1353 ( .A(n1860), .B(n1861), .C(n1859), .Y(n613) );
NAND2X4TS U1354 ( .A(n1093), .B(n1109), .Y(n1746) );
NAND2X4TS U1355 ( .A(n1093), .B(n1116), .Y(n1966) );
NAND2X4TS U1356 ( .A(n1093), .B(intDY_EWSW[28]), .Y(n1891) );
NAND2X4TS U1357 ( .A(n1093), .B(n1143), .Y(n1875) );
NAND2X4TS U1358 ( .A(n1093), .B(n1111), .Y(n1831) );
NAND2X4TS U1359 ( .A(n1093), .B(intDY_EWSW[6]), .Y(n1951) );
NAND3X2TS U1360 ( .A(n1732), .B(n1733), .C(n1731), .Y(n733) );
NAND3X2TS U1361 ( .A(n1957), .B(n1958), .C(n1956), .Y(n748) );
NAND3X4TS U1362 ( .A(n1888), .B(n1887), .C(n1886), .Y(n603) );
NAND2X4TS U1363 ( .A(n1986), .B(n887), .Y(n746) );
NOR2BX4TS U1364 ( .AN(n1985), .B(n888), .Y(n887) );
NAND2X4TS U1365 ( .A(n895), .B(intDY_EWSW[14]), .Y(n1825) );
NAND2X4TS U1366 ( .A(n1972), .B(intDX_EWSW[26]), .Y(n1740) );
NAND3X6TS U1367 ( .A(n1740), .B(n1739), .C(n1738), .Y(n568) );
NAND3X4TS U1368 ( .A(n1752), .B(n1751), .C(n1750), .Y(n736) );
NAND2X4TS U1369 ( .A(n2403), .B(intDX_EWSW[17]), .Y(n1598) );
NAND3X4TS U1370 ( .A(n1758), .B(n1757), .C(n1756), .Y(n735) );
BUFX20TS U1371 ( .A(n1734), .Y(n891) );
CLKINVX3TS U1372 ( .A(n923), .Y(n908) );
CLKINVX3TS U1373 ( .A(n923), .Y(n924) );
BUFX20TS U1374 ( .A(n1061), .Y(n2009) );
CLKINVX12TS U1375 ( .A(n2009), .Y(n893) );
CLKINVX12TS U1376 ( .A(n2009), .Y(n894) );
CLKINVX12TS U1377 ( .A(n2009), .Y(n895) );
NAND2BX1TS U1378 ( .AN(n1233), .B(intDX_EWSW[8]), .Y(n1863) );
OR2X8TS U1379 ( .A(n1644), .B(n2060), .Y(n1233) );
NAND3X4TS U1380 ( .A(n1982), .B(n1983), .C(n1981), .Y(n740) );
NAND3X4TS U1381 ( .A(n1883), .B(n1884), .C(n1882), .Y(n583) );
INVX12TS U1382 ( .A(n1061), .Y(n1063) );
NAND3X4TS U1383 ( .A(n1880), .B(n1881), .C(n1879), .Y(n579) );
NAND2X8TS U1384 ( .A(n1665), .B(n1237), .Y(n2006) );
BUFX16TS U1385 ( .A(n1076), .Y(n1259) );
NAND2X8TS U1386 ( .A(n1664), .B(n2171), .Y(n1294) );
NAND2X8TS U1387 ( .A(n1321), .B(n1680), .Y(n2226) );
OAI2BB1X4TS U1388 ( .A0N(n1402), .A1N(n1208), .B0(n1336), .Y(n1405) );
BUFX16TS U1389 ( .A(n1146), .Y(n1229) );
NOR2X6TS U1390 ( .A(n1146), .B(n1106), .Y(n1676) );
AOI2BB1X4TS U1391 ( .A0N(n1259), .A1N(n905), .B0(n1018), .Y(n1237) );
BUFX20TS U1392 ( .A(n1062), .Y(n907) );
CLKINVX3TS U1393 ( .A(rst), .Y(n1172) );
INVX16TS U1394 ( .A(n880), .Y(n919) );
MXI2X4TS U1395 ( .A(n2433), .B(n2805), .S0(n1011), .Y(n484) );
INVX2TS U1396 ( .A(n1086), .Y(n1087) );
NAND2X2TS U1397 ( .A(n2413), .B(intDX_EWSW[29]), .Y(n1627) );
NAND2X2TS U1398 ( .A(n2406), .B(intDX_EWSW[7]), .Y(n938) );
AND2X2TS U1399 ( .A(n2399), .B(intDX_EWSW[30]), .Y(n1630) );
XOR2X1TS U1400 ( .A(intDY_EWSW[11]), .B(n1079), .Y(n1511) );
NAND2X1TS U1401 ( .A(n2223), .B(DmP_mant_SHT1_SW[15]), .Y(n1344) );
AND2X2TS U1402 ( .A(n1929), .B(n1926), .Y(n1689) );
NAND2X2TS U1403 ( .A(n2079), .B(n2173), .Y(n1420) );
NOR2X1TS U1404 ( .A(n1807), .B(n1012), .Y(n1810) );
NAND2X1TS U1405 ( .A(n2295), .B(n1071), .Y(n1246) );
OAI22X2TS U1406 ( .A0(n1095), .A1(n1060), .B0(n1092), .B1(n2425), .Y(n2764)
);
NOR2X2TS U1407 ( .A(n2388), .B(n1146), .Y(n928) );
INVX12TS U1408 ( .A(n978), .Y(n979) );
BUFX20TS U1409 ( .A(n892), .Y(n929) );
OAI2BB1X2TS U1410 ( .A0N(final_result_ieee[30]), .A1N(n2285), .B0(n2142),
.Y(n761) );
NOR2X4TS U1411 ( .A(n1686), .B(n1335), .Y(n1199) );
MXI2X2TS U1412 ( .A(n2808), .B(n2466), .S0(n2132), .Y(n482) );
AND2X4TS U1413 ( .A(n2102), .B(n2101), .Y(n2801) );
AND3X8TS U1414 ( .A(n1234), .B(n1267), .C(n1266), .Y(n996) );
NAND2X2TS U1415 ( .A(n2111), .B(n1382), .Y(n2114) );
CLKMX2X2TS U1416 ( .A(Data_X[14]), .B(intDX_EWSW[14]), .S0(n2346), .Y(n855)
);
CLKMX2X2TS U1417 ( .A(Data_Y[8]), .B(intDY_EWSW[8]), .S0(n2340), .Y(n827) );
CLKMX2X2TS U1418 ( .A(Data_Y[6]), .B(intDY_EWSW[6]), .S0(n2340), .Y(n829) );
CLKMX2X2TS U1419 ( .A(Data_X[29]), .B(intDX_EWSW[29]), .S0(n2344), .Y(n840)
);
CLKMX2X2TS U1420 ( .A(Data_Y[31]), .B(intDY_EWSW[31]), .S0(n2339), .Y(n804)
);
CLKMX2X2TS U1421 ( .A(Data_Y[16]), .B(intDY_EWSW[16]), .S0(n2341), .Y(n819)
);
CLKMX2X2TS U1422 ( .A(Data_Y[11]), .B(intDY_EWSW[11]), .S0(n2340), .Y(n824)
);
CLKMX2X2TS U1423 ( .A(Data_Y[13]), .B(intDY_EWSW[13]), .S0(n2341), .Y(n822)
);
CLKMX2X2TS U1424 ( .A(Data_Y[2]), .B(intDY_EWSW[2]), .S0(n2340), .Y(n833) );
CLKMX2X2TS U1425 ( .A(Data_Y[22]), .B(intDY_EWSW[22]), .S0(n2343), .Y(n813)
);
CLKMX2X2TS U1426 ( .A(Data_Y[10]), .B(intDY_EWSW[10]), .S0(n2340), .Y(n825)
);
CLKMX2X2TS U1427 ( .A(Data_Y[12]), .B(intDY_EWSW[12]), .S0(n2341), .Y(n823)
);
CLKMX2X2TS U1428 ( .A(add_subt), .B(intAS), .S0(n2339), .Y(n837) );
CLKMX2X2TS U1429 ( .A(Data_X[31]), .B(intDX_EWSW[31]), .S0(n2339), .Y(n838)
);
CLKMX2X2TS U1430 ( .A(Data_Y[7]), .B(n886), .S0(n2340), .Y(n828) );
CLKMX2X2TS U1431 ( .A(Data_X[18]), .B(intDX_EWSW[18]), .S0(n2346), .Y(n851)
);
CLKMX2X2TS U1432 ( .A(Data_Y[28]), .B(intDY_EWSW[28]), .S0(n2343), .Y(n807)
);
CLKMX2X2TS U1433 ( .A(Data_Y[24]), .B(intDY_EWSW[24]), .S0(n2343), .Y(n811)
);
CLKMX2X2TS U1434 ( .A(Data_Y[25]), .B(intDY_EWSW[25]), .S0(n2343), .Y(n810)
);
NAND2X4TS U1435 ( .A(n1391), .B(n2199), .Y(n2208) );
INVX2TS U1436 ( .A(n2205), .Y(n1329) );
INVX8TS U1437 ( .A(n2218), .Y(n2223) );
INVX2TS U1438 ( .A(n556), .Y(n1221) );
BUFX8TS U1439 ( .A(n1399), .Y(n2129) );
NAND2X2TS U1440 ( .A(n2093), .B(n1128), .Y(n1724) );
INVX2TS U1441 ( .A(n2214), .Y(n1366) );
NOR2X2TS U1442 ( .A(n1534), .B(n2060), .Y(n1535) );
AND2X6TS U1443 ( .A(n1361), .B(DMP_SFG[14]), .Y(n995) );
INVX2TS U1444 ( .A(n1392), .Y(n1363) );
INVX3TS U1445 ( .A(n1370), .Y(n1184) );
BUFX20TS U1446 ( .A(n1885), .Y(n2060) );
CLKMX2X2TS U1447 ( .A(DmP_mant_SHT1_SW[16]), .B(DmP_EXP_EWSW[16]), .S0(n2326), .Y(n584) );
NOR2X4TS U1448 ( .A(n2321), .B(OP_FLAG_SHT2), .Y(n1222) );
CLKMX2X2TS U1449 ( .A(zero_flag), .B(ZERO_FLAG_SHT1SHT2), .S0(n2690), .Y(
n559) );
NOR2X2TS U1450 ( .A(n1114), .B(n1059), .Y(n1324) );
NOR2X4TS U1451 ( .A(DMP_EXP_EWSW[23]), .B(n2449), .Y(n2315) );
INVX2TS U1452 ( .A(n1043), .Y(n1044) );
INVX6TS U1453 ( .A(n1057), .Y(n1058) );
INVX2TS U1454 ( .A(n1127), .Y(n1046) );
BUFX12TS U1455 ( .A(shift_value_SHT2_EWR[4]), .Y(n2173) );
INVX12TS U1456 ( .A(n1258), .Y(n2243) );
NAND2X4TS U1457 ( .A(n1208), .B(n1275), .Y(n1274) );
NOR2X4TS U1458 ( .A(n1199), .B(n1198), .Y(n1197) );
MX2X2TS U1459 ( .A(n2197), .B(n1102), .S0(n2295), .Y(n538) );
OR2X4TS U1460 ( .A(n1027), .B(n1026), .Y(n1010) );
MX2X2TS U1461 ( .A(n2069), .B(n1104), .S0(n1179), .Y(n549) );
NAND2X2TS U1462 ( .A(n2103), .B(n1382), .Y(n2102) );
NAND2X2TS U1463 ( .A(n2103), .B(n1180), .Y(n2107) );
NAND2X2TS U1464 ( .A(n2115), .B(n2143), .Y(n1442) );
NOR2X4TS U1465 ( .A(n931), .B(n1433), .Y(n1281) );
NAND2X4TS U1466 ( .A(n1203), .B(DMP_SFG[19]), .Y(n1403) );
CLKMX2X2TS U1467 ( .A(Data_Y[4]), .B(n1116), .S0(n2340), .Y(n831) );
CLKMX2X2TS U1468 ( .A(Data_X[27]), .B(n1119), .S0(n2344), .Y(n842) );
CLKMX2X2TS U1469 ( .A(Data_X[19]), .B(n1086), .S0(n2346), .Y(n850) );
CLKMX2X2TS U1470 ( .A(Data_X[15]), .B(n1143), .S0(n2346), .Y(n854) );
CLKMX2X2TS U1471 ( .A(Data_X[9]), .B(n1048), .S0(n2345), .Y(n860) );
CLKMX2X2TS U1472 ( .A(Data_Y[17]), .B(intDY_EWSW[17]), .S0(n2341), .Y(n818)
);
CLKMX2X2TS U1473 ( .A(Data_X[1]), .B(n1127), .S0(n2343), .Y(n868) );
CLKMX2X2TS U1474 ( .A(Data_X[7]), .B(intDX_EWSW[7]), .S0(n2345), .Y(n862) );
CLKMX2X2TS U1475 ( .A(Data_X[24]), .B(n1118), .S0(n2344), .Y(n845) );
CLKMX2X2TS U1476 ( .A(Data_X[11]), .B(n1078), .S0(n2345), .Y(n858) );
NAND2X2TS U1477 ( .A(n873), .B(n2525), .Y(n2524) );
INVX2TS U1478 ( .A(n1052), .Y(n2018) );
CLKMX2X2TS U1479 ( .A(Data_X[20]), .B(n1120), .S0(n2346), .Y(n849) );
CLKMX2X2TS U1480 ( .A(Data_X[21]), .B(n1129), .S0(n2346), .Y(n848) );
CLKMX2X2TS U1481 ( .A(Data_X[5]), .B(n1121), .S0(n2345), .Y(n864) );
CLKMX2X2TS U1482 ( .A(Data_Y[1]), .B(n1043), .S0(n2339), .Y(n834) );
AND2X4TS U1483 ( .A(n1445), .B(n1455), .Y(n1040) );
INVX4TS U1484 ( .A(n870), .Y(n2525) );
BUFX12TS U1485 ( .A(n2342), .Y(n2345) );
BUFX12TS U1486 ( .A(n2342), .Y(n2341) );
AND2X4TS U1487 ( .A(n1073), .B(n1074), .Y(n1800) );
INVX3TS U1488 ( .A(n2209), .Y(n1367) );
BUFX12TS U1489 ( .A(n2342), .Y(n2346) );
INVX6TS U1490 ( .A(n1690), .Y(n1151) );
BUFX12TS U1491 ( .A(n2342), .Y(n2343) );
BUFX12TS U1492 ( .A(n2342), .Y(n2344) );
BUFX6TS U1493 ( .A(n2342), .Y(n2339) );
BUFX12TS U1494 ( .A(n2342), .Y(n2340) );
CLKMX2X2TS U1495 ( .A(ZERO_FLAG_NRM), .B(ZERO_FLAG_SFG), .S0(n1168), .Y(n561) );
INVX16TS U1496 ( .A(n931), .Y(n930) );
INVX6TS U1497 ( .A(n1658), .Y(n1803) );
CLKMX2X2TS U1498 ( .A(DMP_exp_NRM_EW[7]), .B(DMP_SFG[30]), .S0(n1168), .Y(
n619) );
AND2X4TS U1499 ( .A(n1432), .B(n1113), .Y(n1263) );
CLKMX2X2TS U1500 ( .A(DmP_mant_SHT1_SW[10]), .B(n597), .S0(n2311), .Y(n596)
);
INVX8TS U1501 ( .A(n2296), .Y(n1433) );
MXI2X1TS U1502 ( .A(n2324), .B(inst_FSM_INPUT_ENABLE_state_reg[0]), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X4TS U1503 ( .A(n1364), .B(DMP_SFG[16]), .Y(n2209) );
INVX2TS U1504 ( .A(n1360), .Y(n1210) );
NOR2X4TS U1505 ( .A(n1650), .B(n1071), .Y(n1020) );
XNOR2X1TS U1506 ( .A(n1191), .B(DmP_mant_SFG_SWR[25]), .Y(n1356) );
INVX2TS U1507 ( .A(n2239), .Y(n1414) );
INVX8TS U1508 ( .A(n2506), .Y(n2310) );
CLKMX2X2TS U1509 ( .A(DMP_exp_NRM_EW[0]), .B(DMP_SFG[23]), .S0(n2312), .Y(
n654) );
NAND2X4TS U1510 ( .A(n1124), .B(n2387), .Y(n1254) );
BUFX16TS U1511 ( .A(n2321), .Y(n1236) );
CLKMX2X2TS U1512 ( .A(DMP_exp_NRM_EW[6]), .B(DMP_SFG[29]), .S0(n2312), .Y(
n624) );
NOR2X8TS U1513 ( .A(n1711), .B(n1710), .Y(n2348) );
CLKMX2X2TS U1514 ( .A(DMP_exp_NRM_EW[3]), .B(DMP_SFG[26]), .S0(n2312), .Y(
n639) );
INVX2TS U1515 ( .A(n1691), .Y(n2257) );
NAND2X2TS U1516 ( .A(n2659), .B(n1057), .Y(n1216) );
INVX6TS U1517 ( .A(n1135), .Y(n1136) );
INVX8TS U1518 ( .A(Shift_reg_FLAGS_7_5), .Y(n2307) );
NAND2X2TS U1519 ( .A(n2445), .B(DMP_EXP_EWSW[26]), .Y(n2049) );
INVX6TS U1520 ( .A(n1114), .Y(n1115) );
INVX8TS U1521 ( .A(n1059), .Y(n1060) );
NOR2X4TS U1522 ( .A(Raw_mant_NRM_SWR[2]), .B(n1104), .Y(n1251) );
INVX6TS U1523 ( .A(n1123), .Y(n1124) );
INVX2TS U1524 ( .A(n1078), .Y(n1079) );
INVX4TS U1525 ( .A(n2394), .Y(n1083) );
INVX2TS U1526 ( .A(SIGN_FLAG_SHT1SHT2), .Y(n2152) );
INVX2TS U1527 ( .A(DmP_mant_SHT1_SW[8]), .Y(n2254) );
INVX2TS U1528 ( .A(n2353), .Y(n2322) );
INVX2TS U1529 ( .A(n1137), .Y(n1138) );
NAND2X2TS U1530 ( .A(n2243), .B(Raw_mant_NRM_SWR[2]), .Y(n2785) );
NOR2X4TS U1531 ( .A(n1134), .B(n1303), .Y(n1302) );
NAND2X2TS U1532 ( .A(n2233), .B(n2299), .Y(n2784) );
NAND2X4TS U1533 ( .A(n1676), .B(n1055), .Y(n1305) );
MX2X2TS U1534 ( .A(n2217), .B(n1114), .S0(n2295), .Y(n534) );
MX2X2TS U1535 ( .A(n2201), .B(n1055), .S0(n2452), .Y(n537) );
NAND3X2TS U1536 ( .A(n1870), .B(n1869), .C(n1868), .Y(n591) );
AND2X2TS U1537 ( .A(n1268), .B(n1057), .Y(n1134) );
MX2X2TS U1538 ( .A(n2184), .B(n1135), .S0(n2295), .Y(n539) );
NAND2X6TS U1539 ( .A(n2794), .B(n1011), .Y(n1206) );
MX2X2TS U1540 ( .A(n2275), .B(n1098), .S0(n2295), .Y(n548) );
MX2X2TS U1541 ( .A(n2338), .B(Raw_mant_NRM_SWR[8]), .S0(n1179), .Y(n545) );
OAI21X2TS U1542 ( .A0(n1393), .A1(n995), .B0(n1273), .Y(n1272) );
INVX4TS U1543 ( .A(n1232), .Y(n1467) );
NAND2X6TS U1544 ( .A(n1341), .B(n1368), .Y(n2291) );
NAND2X4TS U1545 ( .A(n1183), .B(n1924), .Y(n1685) );
NAND2X2TS U1546 ( .A(n1100), .B(n1673), .Y(n1675) );
CLKMX2X2TS U1547 ( .A(Data_X[4]), .B(n1082), .S0(n2345), .Y(n865) );
CLKMX2X2TS U1548 ( .A(Data_Y[15]), .B(intDY_EWSW[15]), .S0(n2341), .Y(n820)
);
CLKMX2X2TS U1549 ( .A(Data_Y[19]), .B(intDY_EWSW[19]), .S0(n2341), .Y(n816)
);
CLKMX2X2TS U1550 ( .A(Data_Y[20]), .B(intDY_EWSW[20]), .S0(n2341), .Y(n815)
);
CLKMX2X2TS U1551 ( .A(Data_Y[18]), .B(intDY_EWSW[18]), .S0(n2341), .Y(n817)
);
CLKMX2X2TS U1552 ( .A(Data_X[6]), .B(n1111), .S0(n2345), .Y(n863) );
NAND4X2TS U1553 ( .A(n1438), .B(n1437), .C(n1436), .D(n1435), .Y(n2115) );
CLKMX2X2TS U1554 ( .A(Data_X[30]), .B(intDX_EWSW[30]), .S0(n2344), .Y(n839)
);
CLKMX2X2TS U1555 ( .A(Data_X[23]), .B(intDX_EWSW[23]), .S0(n2344), .Y(n846)
);
NAND4X2TS U1556 ( .A(n2075), .B(n2074), .C(n2073), .D(n2072), .Y(n2078) );
INVX2TS U1557 ( .A(n1271), .Y(n2186) );
NAND2X4TS U1558 ( .A(n2112), .B(n2173), .Y(n1702) );
NAND2X6TS U1559 ( .A(n1387), .B(n992), .Y(n1369) );
NAND4X6TS U1560 ( .A(n1652), .B(n1803), .C(n1651), .D(n1019), .Y(n1777) );
NAND2X6TS U1561 ( .A(n1271), .B(n2189), .Y(n2179) );
NAND2X4TS U1562 ( .A(n1151), .B(n1814), .Y(n1397) );
CLKMX2X2TS U1563 ( .A(Data_X[0]), .B(intDX_EWSW[0]), .S0(n2343), .Y(n869) );
CLKMX2X2TS U1564 ( .A(Data_X[13]), .B(n935), .S0(n2346), .Y(n856) );
CLKMX2X2TS U1565 ( .A(Data_Y[21]), .B(intDY_EWSW[21]), .S0(n2341), .Y(n814)
);
BUFX12TS U1566 ( .A(n1269), .Y(n1262) );
NAND2X6TS U1567 ( .A(n1929), .B(n1924), .Y(n1930) );
NAND2X4TS U1568 ( .A(n1240), .B(DMP_SFG[12]), .Y(n2180) );
CLKMX2X2TS U1569 ( .A(DMP_SHT2_EWSW[23]), .B(DMP_SHT1_EWSW[23]), .S0(busy),
.Y(n656) );
CLKMX2X2TS U1570 ( .A(DMP_SHT2_EWSW[24]), .B(DMP_SHT1_EWSW[24]), .S0(busy),
.Y(n651) );
MXI2X2TS U1571 ( .A(n2322), .B(n2483), .S0(n1236), .Y(n645) );
CLKMX2X2TS U1572 ( .A(DMP_SHT2_EWSW[26]), .B(DMP_SHT1_EWSW[26]), .S0(busy),
.Y(n641) );
NAND2X4TS U1573 ( .A(n1252), .B(n1251), .Y(n1250) );
CLKMX2X2TS U1574 ( .A(DMP_SHT2_EWSW[27]), .B(DMP_SHT1_EWSW[27]), .S0(busy),
.Y(n636) );
CLKMX2X2TS U1575 ( .A(DMP_SHT2_EWSW[28]), .B(DMP_SHT1_EWSW[28]), .S0(busy),
.Y(n631) );
CLKMX2X2TS U1576 ( .A(DMP_SHT2_EWSW[29]), .B(DMP_SHT1_EWSW[29]), .S0(busy),
.Y(n626) );
CLKMX2X2TS U1577 ( .A(DMP_SHT2_EWSW[30]), .B(DMP_SHT1_EWSW[30]), .S0(n2320),
.Y(n621) );
CLKMX2X2TS U1578 ( .A(ZERO_FLAG_SHT2), .B(ZERO_FLAG_SHT1), .S0(n2320), .Y(
n563) );
NAND2X4TS U1579 ( .A(n1360), .B(DMP_SFG[13]), .Y(n2193) );
MXI2X2TS U1580 ( .A(n2389), .B(n2316), .S0(n2318), .Y(n773) );
MXI2X1TS U1581 ( .A(n2361), .B(n2313), .S0(n1168), .Y(n515) );
INVX12TS U1582 ( .A(n1053), .Y(n2070) );
NAND2X2TS U1583 ( .A(n2306), .B(n2760), .Y(n1205) );
NAND2X2TS U1584 ( .A(n2061), .B(inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(
n2064) );
NAND4X2TS U1585 ( .A(n1506), .B(n1505), .C(n1504), .D(n1503), .Y(n1507) );
AND2X4TS U1586 ( .A(n2321), .B(n1192), .Y(n1017) );
INVX16TS U1587 ( .A(n1679), .Y(n931) );
CLKMX2X2TS U1588 ( .A(DmP_mant_SHT1_SW[22]), .B(n904), .S0(n2326), .Y(n572)
);
CLKMX2X2TS U1589 ( .A(DmP_mant_SHT1_SW[21]), .B(DmP_EXP_EWSW[21]), .S0(n2326), .Y(n574) );
INVX8TS U1590 ( .A(n2506), .Y(busy) );
NAND2X6TS U1591 ( .A(DmP_mant_SFG_SWR_signed[10]), .B(DMP_SFG[8]), .Y(n2137)
);
NOR2X6TS U1592 ( .A(DmP_mant_SFG_SWR_signed[10]), .B(DMP_SFG[8]), .Y(n1903)
);
XNOR2X2TS U1593 ( .A(intDY_EWSW[15]), .B(n1143), .Y(n1515) );
INVX8TS U1594 ( .A(n2506), .Y(n2323) );
INVX12TS U1595 ( .A(Shift_reg_FLAGS_7_6), .Y(n1885) );
INVX6TS U1596 ( .A(n1116), .Y(n1117) );
INVX6TS U1597 ( .A(n1089), .Y(n1090) );
NAND4X4TS U1598 ( .A(n2622), .B(n2621), .C(n2620), .D(n2619), .Y(n2105) );
NOR2X6TS U1599 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n2448), .Y(n2063) );
NOR2X2TS U1600 ( .A(n2446), .B(inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n1710) );
NOR2X1TS U1601 ( .A(n2689), .B(overflow_flag), .Y(n2125) );
MXI2X2TS U1602 ( .A(n2447), .B(inst_FSM_INPUT_ENABLE_state_reg[1]), .S0(
inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n1711) );
OR2X6TS U1603 ( .A(n1132), .B(n1059), .Y(n1650) );
INVX2TS U1604 ( .A(n2351), .Y(n2033) );
INVX2TS U1605 ( .A(n1104), .Y(n1105) );
BUFX8TS U1606 ( .A(n2824), .Y(n2321) );
INVX6TS U1607 ( .A(n1047), .Y(n1284) );
INVX8TS U1608 ( .A(LZD_output_NRM2_EW[1]), .Y(n2198) );
INVX2TS U1609 ( .A(DmP_mant_SHT1_SW[21]), .Y(n2255) );
NAND2X4TS U1610 ( .A(intDY_EWSW[0]), .B(n893), .Y(n1941) );
NAND2X4TS U1611 ( .A(n894), .B(intDY_EWSW[9]), .Y(n1828) );
NAND2X2TS U1612 ( .A(n1943), .B(DmP_EXP_EWSW[27]), .Y(n1786) );
NAND2X2TS U1613 ( .A(n1878), .B(DmP_EXP_EWSW[19]), .Y(n1879) );
NAND2X2TS U1614 ( .A(n1885), .B(DmP_EXP_EWSW[11]), .Y(n1707) );
NAND2X2TS U1615 ( .A(n2444), .B(DMP_EXP_EWSW[20]), .Y(n1981) );
NAND2X2TS U1616 ( .A(n2060), .B(DMP_EXP_EWSW[22]), .Y(n1999) );
NAND2X2TS U1617 ( .A(n1885), .B(DmP_EXP_EWSW[8]), .Y(n1862) );
NAND2X2TS U1618 ( .A(n1943), .B(DMP_EXP_EWSW[27]), .Y(n1731) );
NAND2X4TS U1619 ( .A(intDY_EWSW[23]), .B(n1973), .Y(n1742) );
NAND2X4TS U1620 ( .A(n1973), .B(intDX_EWSW[2]), .Y(n1961) );
NAND2X4TS U1621 ( .A(n907), .B(intDX_EWSW[29]), .Y(n1893) );
NAND3X4TS U1622 ( .A(n1736), .B(n1737), .C(n1735), .Y(n570) );
NAND2X4TS U1623 ( .A(n907), .B(intDY_EWSW[13]), .Y(n1869) );
NAND2X4TS U1624 ( .A(n907), .B(n1143), .Y(n1994) );
AND2X8TS U1625 ( .A(n1166), .B(n1135), .Y(n1261) );
NOR2X2TS U1626 ( .A(Raw_mant_NRM_SWR[13]), .B(Raw_mant_NRM_SWR[12]), .Y(
n1424) );
NAND3X6TS U1627 ( .A(n996), .B(n1264), .C(n1213), .Y(n1088) );
NAND2X4TS U1628 ( .A(intDX_EWSW[0]), .B(n2002), .Y(n1720) );
NAND3X2TS U1629 ( .A(n1721), .B(n1720), .C(n1719), .Y(n760) );
NOR2X4TS U1630 ( .A(n2408), .B(intDX_EWSW[8]), .Y(n1540) );
NAND2X6TS U1631 ( .A(n2408), .B(intDX_EWSW[8]), .Y(n1565) );
AND2X4TS U1632 ( .A(n1253), .B(n1659), .Y(n1007) );
NOR2X4TS U1633 ( .A(n2654), .B(n1059), .Y(n1655) );
CLKINVX12TS U1634 ( .A(n2521), .Y(n1347) );
AND2X8TS U1635 ( .A(n1401), .B(n1400), .Y(n2805) );
NAND3X2TS U1636 ( .A(n2011), .B(n2012), .C(n2010), .Y(n730) );
OAI21X4TS U1637 ( .A0(n1611), .A1(n1612), .B0(n1610), .Y(n1613) );
AND2X8TS U1638 ( .A(n1108), .B(intDY_EWSW[23]), .Y(n1612) );
AND2X8TS U1639 ( .A(n1085), .B(intDY_EWSW[29]), .Y(n1629) );
NOR2X6TS U1640 ( .A(n2405), .B(n1078), .Y(n1569) );
NAND2X8TS U1641 ( .A(n2195), .B(n2194), .Y(n1209) );
NAND2X8TS U1642 ( .A(n1243), .B(n1241), .Y(n2195) );
NOR2X8TS U1643 ( .A(n2410), .B(intDX_EWSW[26]), .Y(n1592) );
NOR2X8TS U1644 ( .A(n1135), .B(Raw_mant_NRM_SWR[12]), .Y(n1425) );
NOR2X8TS U1645 ( .A(n1230), .B(n993), .Y(n1042) );
NAND3X8TS U1646 ( .A(n982), .B(n1297), .C(n1002), .Y(n1230) );
OAI2BB1X4TS U1647 ( .A0N(Raw_mant_NRM_SWR[0]), .A1N(n2264), .B0(n1288), .Y(
n803) );
NOR2X8TS U1648 ( .A(n2237), .B(n2218), .Y(n1677) );
AOI21X4TS U1649 ( .A0(n1208), .A1(n1371), .B0(n1316), .Y(n1315) );
NAND2X2TS U1650 ( .A(n1207), .B(n2245), .Y(n1696) );
NAND3X4TS U1651 ( .A(n1749), .B(n1748), .C(n1747), .Y(n734) );
MXI2X2TS U1652 ( .A(n2046), .B(n2045), .S0(n2307), .Y(n770) );
OAI21X4TS U1653 ( .A0(Raw_mant_NRM_SWR[2]), .A1(Raw_mant_NRM_SWR[3]), .B0(
n1775), .Y(n1426) );
NAND2X2TS U1654 ( .A(n1207), .B(n2234), .Y(n1796) );
NOR2X1TS U1655 ( .A(n2043), .B(n2050), .Y(n2044) );
OAI21X4TS U1656 ( .A0(n1600), .A1(n1599), .B0(n1598), .Y(n1606) );
AND2X8TS U1657 ( .A(n981), .B(intDY_EWSW[17]), .Y(n1600) );
NAND3X2TS U1658 ( .A(n1008), .B(n1840), .C(n1839), .Y(n611) );
NAND2X4TS U1659 ( .A(n1097), .B(intDX_EWSW[31]), .Y(n1647) );
BUFX20TS U1660 ( .A(n1063), .Y(n2002) );
BUFX20TS U1661 ( .A(n1063), .Y(n1096) );
NAND3X8TS U1662 ( .A(n996), .B(n1213), .C(n1264), .Y(n1270) );
NAND2X4TS U1663 ( .A(intDY_EWSW[3]), .B(n1096), .Y(n1840) );
NOR2X8TS U1664 ( .A(n936), .B(n1558), .Y(n937) );
AND2X8TS U1665 ( .A(n946), .B(intDY_EWSW[7]), .Y(n1558) );
AOI21X4TS U1666 ( .A0(n1560), .A1(n937), .B0(n1559), .Y(n1561) );
OAI21X4TS U1667 ( .A0(n1558), .A1(n939), .B0(n938), .Y(n1559) );
NAND2X4TS U1668 ( .A(n1109), .B(n1973), .Y(n1757) );
NAND2X4TS U1669 ( .A(intDX_EWSW[23]), .B(n1097), .Y(n1754) );
NAND2X4TS U1670 ( .A(n1097), .B(intDY_EWSW[26]), .Y(n1739) );
NAND2X4TS U1671 ( .A(n907), .B(n1118), .Y(n1751) );
OAI22X1TS U1672 ( .A0(n919), .A1(n2541), .B0(n942), .B1(n2540), .Y(
final_result_ieee[1]) );
OAI22X1TS U1673 ( .A0(n919), .A1(n2549), .B0(n943), .B1(n2548), .Y(
final_result_ieee[12]) );
OAI22X1TS U1674 ( .A0(n919), .A1(n2555), .B0(n943), .B1(n2554), .Y(
final_result_ieee[20]) );
OAI22X1TS U1675 ( .A0(n919), .A1(n2567), .B0(n942), .B1(n2566), .Y(
final_result_ieee[0]) );
OAI2BB2X1TS U1676 ( .B0(n919), .B1(n2604), .A0N(n940), .A1N(n2603), .Y(
final_result_ieee[10]) );
OAI2BB2X1TS U1677 ( .B0(n919), .B1(n2646), .A0N(n940), .A1N(n2645), .Y(
final_result_ieee[21]) );
OAI2BB2X1TS U1678 ( .B0(n919), .B1(n2648), .A0N(n940), .A1N(n2647), .Y(
final_result_ieee[7]) );
OAI22X1TS U1679 ( .A0(n919), .A1(n2539), .B0(n943), .B1(n2538), .Y(
final_result_ieee[9]) );
OAI22X1TS U1680 ( .A0(n919), .A1(n2585), .B0(n943), .B1(n2584), .Y(
final_result_ieee[11]) );
OAI22X1TS U1681 ( .A0(n919), .A1(n2600), .B0(n943), .B1(n2599), .Y(
final_result_ieee[8]) );
OAI22X1TS U1682 ( .A0(n921), .A1(n2529), .B0(n942), .B1(n2528), .Y(
final_result_ieee[4]) );
OAI22X1TS U1683 ( .A0(n921), .A1(n2533), .B0(n941), .B1(n2532), .Y(
final_result_ieee[22]) );
OAI22X1TS U1684 ( .A0(n921), .A1(n2543), .B0(n941), .B1(n2542), .Y(
final_result_ieee[15]) );
OAI22X1TS U1685 ( .A0(n921), .A1(n2559), .B0(n941), .B1(n2558), .Y(
final_result_ieee[17]) );
OAI22X1TS U1686 ( .A0(n921), .A1(n2565), .B0(n941), .B1(n2564), .Y(
final_result_ieee[18]) );
OAI22X1TS U1687 ( .A0(n921), .A1(n2602), .B0(n943), .B1(n2601), .Y(
final_result_ieee[5]) );
OAI22X1TS U1688 ( .A0(n921), .A1(n2606), .B0(n941), .B1(n2605), .Y(
final_result_ieee[14]) );
OAI22X1TS U1689 ( .A0(n921), .A1(n2531), .B0(n943), .B1(n2530), .Y(
final_result_ieee[6]) );
OAI22X1TS U1690 ( .A0(n921), .A1(n2557), .B0(n942), .B1(n2556), .Y(
final_result_ieee[3]) );
OAI22X1TS U1691 ( .A0(n921), .A1(n2594), .B0(n942), .B1(n2593), .Y(
final_result_ieee[2]) );
NAND2X2TS U1692 ( .A(n929), .B(intDX_EWSW[7]), .Y(n1768) );
NAND2X2TS U1693 ( .A(n933), .B(n886), .Y(n1767) );
NAND2X2TS U1694 ( .A(n929), .B(n886), .Y(n1887) );
NAND2X2TS U1695 ( .A(n1968), .B(DmP_EXP_EWSW[24]), .Y(n1735) );
NAND2X2TS U1696 ( .A(n2008), .B(n1118), .Y(n1737) );
NAND2X2TS U1697 ( .A(n907), .B(intDY_EWSW[24]), .Y(n1736) );
CLKMX2X2TS U1698 ( .A(DmP_mant_SHT1_SW[5]), .B(n607), .S0(n2311), .Y(n606)
);
NOR2X8TS U1699 ( .A(n979), .B(n1059), .Y(n1005) );
CLKINVX12TS U1700 ( .A(Raw_mant_NRM_SWR[20]), .Y(n978) );
NAND2X4TS U1701 ( .A(n1904), .B(DMP_SFG[6]), .Y(n1189) );
NOR2X2TS U1702 ( .A(n1903), .B(n1909), .Y(n1186) );
NOR3X4TS U1703 ( .A(Raw_mant_NRM_SWR[11]), .B(n1066), .C(n1123), .Y(n1297)
);
INVX8TS U1704 ( .A(n985), .Y(n2096) );
NOR2X2TS U1705 ( .A(n2270), .B(n2268), .Y(n1716) );
NOR2X2TS U1706 ( .A(n2417), .B(n1120), .Y(n1588) );
NAND2X2TS U1707 ( .A(n1058), .B(n1135), .Y(n1429) );
INVX4TS U1708 ( .A(n1350), .Y(n1035) );
CLKINVX3TS U1709 ( .A(n1930), .Y(n1204) );
NAND2X6TS U1710 ( .A(n1333), .B(n2292), .Y(n2206) );
NOR2X2TS U1711 ( .A(n1416), .B(n1415), .Y(n1422) );
INVX6TS U1712 ( .A(n985), .Y(n2071) );
NAND2X4TS U1713 ( .A(n2169), .B(n2166), .Y(n1226) );
AND4X4TS U1714 ( .A(n1054), .B(n2644), .C(n2643), .D(n2642), .Y(n1053) );
INVX2TS U1715 ( .A(n2256), .Y(n1789) );
NOR2X4TS U1716 ( .A(n1338), .B(n1309), .Y(n1337) );
NAND2X2TS U1717 ( .A(n2096), .B(n2232), .Y(n1395) );
NAND2X4TS U1718 ( .A(n1481), .B(n1480), .Y(n2145) );
NAND4X6TS U1719 ( .A(n1704), .B(n1703), .C(n1702), .D(n1701), .Y(n2144) );
NAND2X2TS U1720 ( .A(n2096), .B(n2094), .Y(n1701) );
NAND4X4TS U1721 ( .A(n2563), .B(n2562), .C(n2561), .D(n2560), .Y(n2258) );
OAI21X2TS U1722 ( .A0(n1291), .A1(n1179), .B0(n1290), .Y(n547) );
MX2X1TS U1723 ( .A(Data_X[2]), .B(intDX_EWSW[2]), .S0(n2345), .Y(n867) );
MX2X1TS U1724 ( .A(Data_Y[23]), .B(intDY_EWSW[23]), .S0(n2343), .Y(n812) );
NOR2X6TS U1725 ( .A(n2400), .B(n1119), .Y(n1623) );
NAND2X2TS U1726 ( .A(n1117), .B(n1082), .Y(n1556) );
NAND2X2TS U1727 ( .A(n2414), .B(n1086), .Y(n1601) );
NAND2X4TS U1728 ( .A(n2392), .B(n1118), .Y(n1619) );
NOR2X4TS U1729 ( .A(n2420), .B(n1109), .Y(n1620) );
NOR2X2TS U1730 ( .A(n1057), .B(n1112), .Y(n1298) );
NAND2X4TS U1731 ( .A(n1542), .B(n1571), .Y(n1543) );
NOR2X2TS U1732 ( .A(n2419), .B(intDX_EWSW[16]), .Y(n1194) );
NOR2X6TS U1733 ( .A(n1262), .B(n1066), .Y(n1769) );
CLKINVX6TS U1734 ( .A(n1300), .Y(n1299) );
XNOR2X2TS U1735 ( .A(intDY_EWSW[19]), .B(n1086), .Y(n1500) );
AND3X6TS U1736 ( .A(n1353), .B(n1250), .C(n1659), .Y(n1051) );
NOR2X4TS U1737 ( .A(n1112), .B(n1123), .Y(n1673) );
NAND4X4TS U1738 ( .A(n1769), .B(n1668), .C(n1778), .D(n1135), .Y(n1669) );
NOR3X2TS U1739 ( .A(n1066), .B(n1114), .C(n1123), .Y(n1652) );
NAND2X2TS U1740 ( .A(n1393), .B(n1277), .Y(n1273) );
NAND2X2TS U1741 ( .A(n1279), .B(n1342), .Y(n1277) );
INVX6TS U1742 ( .A(n2210), .Y(n1387) );
INVX2TS U1743 ( .A(n2270), .Y(n2272) );
NAND2X4TS U1744 ( .A(n1333), .B(n1332), .Y(n1331) );
NAND2X2TS U1745 ( .A(n2248), .B(DmP_mant_SHT1_SW[6]), .Y(n1306) );
INVX2TS U1746 ( .A(n2147), .Y(n1069) );
NAND2X2TS U1747 ( .A(n2093), .B(n2258), .Y(n2090) );
NAND2X2TS U1748 ( .A(n989), .B(n2232), .Y(n1436) );
INVX2TS U1749 ( .A(n2672), .Y(n1163) );
NAND2X2TS U1750 ( .A(n1974), .B(n904), .Y(n1844) );
NAND2X2TS U1751 ( .A(n2444), .B(DMP_EXP_EWSW[16]), .Y(n1978) );
NAND2X2TS U1752 ( .A(n1974), .B(DmP_EXP_EWSW[18]), .Y(n1850) );
MXI2X1TS U1753 ( .A(n1284), .B(n2065), .S0(n1168), .Y(n522) );
MXI2X2TS U1754 ( .A(n998), .B(n2473), .S0(n2150), .Y(n527) );
NAND2X6TS U1755 ( .A(n2305), .B(n2299), .Y(n1898) );
OAI21X2TS U1756 ( .A0(n1220), .A1(n1179), .B0(n1219), .Y(n546) );
INVX2TS U1757 ( .A(DMP_SFG[1]), .Y(n2040) );
NAND2X2TS U1758 ( .A(n2007), .B(n1177), .Y(n2745) );
NAND2X2TS U1759 ( .A(n1351), .B(n1177), .Y(n2732) );
NAND2X2TS U1760 ( .A(n2243), .B(n1114), .Y(n2709) );
NAND2X2TS U1761 ( .A(n2243), .B(Raw_mant_NRM_SWR[6]), .Y(n2729) );
NAND2X2TS U1762 ( .A(n2243), .B(n1071), .Y(n2721) );
MX2X1TS U1763 ( .A(Data_X[10]), .B(intDX_EWSW[10]), .S0(n2345), .Y(n859) );
MX2X1TS U1764 ( .A(Data_X[22]), .B(intDX_EWSW[22]), .S0(n2344), .Y(n847) );
INVX2TS U1765 ( .A(n2491), .Y(n1212) );
NOR2X4TS U1766 ( .A(n2357), .B(n1045), .Y(n2015) );
NOR2X4TS U1767 ( .A(n1001), .B(n1261), .Y(n2713) );
OAI22X2TS U1768 ( .A0(n1095), .A1(n1058), .B0(n1091), .B1(n2427), .Y(n2759)
);
BUFX3TS U1769 ( .A(n2513), .Y(n2663) );
CLKMX2X2TS U1770 ( .A(SIGN_FLAG_SHT2), .B(SIGN_FLAG_SHT1), .S0(n2323), .Y(
n554) );
NAND3X2TS U1771 ( .A(n1787), .B(n1788), .C(n1786), .Y(n567) );
NAND2X2TS U1772 ( .A(n1968), .B(DmP_EXP_EWSW[23]), .Y(n1741) );
CLKINVX3TS U1773 ( .A(n1163), .Y(n1165) );
NAND2X1TS U1774 ( .A(n1878), .B(DmP_EXP_EWSW[3]), .Y(n1839) );
INVX3TS U1775 ( .A(n1163), .Y(n1156) );
BUFX3TS U1776 ( .A(n1149), .Y(n2669) );
CLKINVX3TS U1777 ( .A(rst), .Y(n1155) );
OAI22X2TS U1778 ( .A0(n1642), .A1(n2059), .B0(Shift_reg_FLAGS_7_6), .B1(
n2429), .Y(n728) );
NAND2X2TS U1779 ( .A(n1943), .B(DMP_EXP_EWSW[26]), .Y(n1747) );
NAND2X2TS U1780 ( .A(n1943), .B(DMP_EXP_EWSW[25]), .Y(n1756) );
BUFX3TS U1781 ( .A(n2514), .Y(n2670) );
NAND2X1TS U1782 ( .A(n2444), .B(DMP_EXP_EWSW[15]), .Y(n1993) );
CLKBUFX3TS U1783 ( .A(n2030), .Y(n2672) );
NAND2X1TS U1784 ( .A(n1974), .B(DMP_EXP_EWSW[2]), .Y(n1959) );
NAND2X1TS U1785 ( .A(n1943), .B(DMP_EXP_EWSW[0]), .Y(n1719) );
INVX3TS U1786 ( .A(n1160), .Y(n1161) );
INVX16TS U1787 ( .A(n1061), .Y(n1062) );
NAND3X4TS U1788 ( .A(n1846), .B(n1845), .C(n1844), .Y(n573) );
NAND3X4TS U1789 ( .A(n1894), .B(n1893), .C(n1892), .Y(n731) );
NOR2X4TS U1790 ( .A(n1194), .B(n1600), .Y(n1193) );
NAND2X4TS U1791 ( .A(n1605), .B(n1193), .Y(n1590) );
NAND3X4TS U1792 ( .A(n1980), .B(n1979), .C(n1978), .Y(n744) );
NAND3X4TS U1793 ( .A(n1648), .B(n1647), .C(n1646), .Y(n727) );
NAND3X4TS U1794 ( .A(n1991), .B(n1992), .C(n1990), .Y(n743) );
NAND3X4TS U1795 ( .A(n1851), .B(n1852), .C(n1850), .Y(n581) );
NAND3X4TS U1796 ( .A(n1743), .B(n1742), .C(n1741), .Y(n571) );
NOR2X6TS U1797 ( .A(n2411), .B(intDX_EWSW[10]), .Y(n1541) );
NAND2X4TS U1798 ( .A(n1129), .B(n1972), .Y(n1872) );
NAND2X4TS U1799 ( .A(n1129), .B(n1097), .Y(n2004) );
NOR2X6TS U1800 ( .A(n2402), .B(n1129), .Y(n1609) );
OAI21X2TS U1801 ( .A0(n1427), .A1(n1428), .B0(n1659), .Y(n1100) );
NAND2X2TS U1802 ( .A(n1005), .B(n1066), .Y(n1320) );
BUFX12TS U1803 ( .A(n1147), .Y(n1191) );
NOR2X6TS U1804 ( .A(n1658), .B(n1255), .Y(n1772) );
AND4X8TS U1805 ( .A(n1298), .B(n1659), .C(n1425), .D(n1325), .Y(n982) );
AND2X2TS U1806 ( .A(n1473), .B(n1014), .Y(n983) );
CLKINVX3TS U1807 ( .A(n1163), .Y(n1164) );
OR2X8TS U1808 ( .A(n1374), .B(shift_value_SHT2_EWR[4]), .Y(n985) );
AND2X2TS U1809 ( .A(n1718), .B(n1916), .Y(n987) );
NOR2X6TS U1810 ( .A(n544), .B(Raw_mant_NRM_SWR[8]), .Y(n2163) );
AND2X6TS U1811 ( .A(n1228), .B(n2173), .Y(n989) );
OR3X2TS U1812 ( .A(n1123), .B(n1059), .C(n1057), .Y(n990) );
OR2X8TS U1813 ( .A(n1270), .B(n931), .Y(n991) );
OR2X6TS U1814 ( .A(n1350), .B(Raw_mant_NRM_SWR[13]), .Y(n993) );
AO21X4TS U1815 ( .A0(n1929), .A1(n1928), .B0(n1927), .Y(n994) );
OAI21X1TS U1816 ( .A0(n1123), .A1(n1072), .B0(n1113), .Y(n997) );
AOI22X2TS U1817 ( .A0(n1423), .A1(n1382), .B0(n2155), .B1(n2070), .Y(n998)
);
OR2X8TS U1818 ( .A(intDY_EWSW[12]), .B(n1130), .Y(n1000) );
AND3X2TS U1819 ( .A(n1075), .B(n1352), .C(n1102), .Y(n1001) );
NAND2X6TS U1820 ( .A(n1404), .B(n1340), .Y(n1925) );
CLKINVX6TS U1821 ( .A(n1925), .Y(n1183) );
AND2X8TS U1822 ( .A(n1901), .B(n1902), .Y(n1003) );
CLKINVX6TS U1823 ( .A(n1240), .Y(n1244) );
AND2X4TS U1824 ( .A(n2163), .B(n1323), .Y(n1004) );
NAND2X2TS U1825 ( .A(n1877), .B(n1140), .Y(n1008) );
NOR2X2TS U1826 ( .A(n1146), .B(n1122), .Y(n1009) );
NAND2X4TS U1827 ( .A(n1349), .B(n1348), .Y(n1022) );
INVX4TS U1828 ( .A(n1342), .Y(n2199) );
AND2X2TS U1829 ( .A(n931), .B(Data_array_SWR_3__25_), .Y(n1013) );
NAND2X1TS U1830 ( .A(n1340), .B(n2293), .Y(n1015) );
NAND2X4TS U1831 ( .A(n1370), .B(DMP_SFG[18]), .Y(n2293) );
CLKINVX3TS U1832 ( .A(rst), .Y(n1171) );
BUFX3TS U1833 ( .A(n1150), .Y(n2662) );
CLKINVX3TS U1834 ( .A(n1160), .Y(n1158) );
CLKINVX3TS U1835 ( .A(n1160), .Y(n1162) );
INVX2TS U1836 ( .A(n1160), .Y(n1169) );
INVX2TS U1837 ( .A(n1163), .Y(n1157) );
CLKBUFX2TS U1838 ( .A(n2668), .Y(n2687) );
INVX2TS U1839 ( .A(n2662), .Y(n1160) );
AOI21X4TS U1840 ( .A0(n1021), .A1(n2386), .B0(n1777), .Y(n1346) );
AND2X8TS U1841 ( .A(n2423), .B(n1020), .Y(n1019) );
OAI21X4TS U1842 ( .A0(n1023), .A1(n1022), .B0(n2387), .Y(n1021) );
NOR2X6TS U1843 ( .A(n1052), .B(n2388), .Y(n1023) );
NAND2X8TS U1844 ( .A(n1286), .B(n1285), .Y(n1052) );
OAI21X4TS U1845 ( .A0(n1475), .A1(n1474), .B0(n983), .Y(n1461) );
NAND2X8TS U1846 ( .A(n1358), .B(DMP_exp_NRM2_EW[4]), .Y(n1473) );
AO21X4TS U1847 ( .A0(n1459), .A1(n1460), .B0(n1458), .Y(n1024) );
OAI21X4TS U1848 ( .A0(n1448), .A1(n1450), .B0(n1449), .Y(n1459) );
NOR2X8TS U1849 ( .A(n1451), .B(DMP_exp_NRM2_EW[0]), .Y(n1450) );
CLKINVX12TS U1850 ( .A(LZD_output_NRM2_EW[0]), .Y(n1451) );
NOR2X8TS U1851 ( .A(DMP_exp_NRM2_EW[1]), .B(n2198), .Y(n1448) );
NAND2X8TS U1852 ( .A(n2658), .B(DMP_exp_NRM2_EW[1]), .Y(n1449) );
NAND3X8TS U1853 ( .A(n1479), .B(n1478), .C(n1477), .Y(n2153) );
INVX12TS U1854 ( .A(n1025), .Y(n2290) );
NOR2X8TS U1855 ( .A(n2153), .B(n2266), .Y(n1025) );
XOR2X4TS U1856 ( .A(n1028), .B(n1450), .Y(n2288) );
NAND2BX4TS U1857 ( .AN(n1448), .B(n1449), .Y(n1028) );
XOR2X4TS U1858 ( .A(n1029), .B(n1040), .Y(n1232) );
OAI21X4TS U1859 ( .A0(n1101), .A1(n1454), .B0(n1456), .Y(n1029) );
NOR2X8TS U1860 ( .A(n1031), .B(n1030), .Y(n1101) );
NOR2X4TS U1861 ( .A(n1448), .B(n1450), .Y(n1031) );
NAND3X8TS U1862 ( .A(n1051), .B(n1032), .C(n1771), .Y(n1037) );
AND3X8TS U1863 ( .A(n1036), .B(n1035), .C(n1033), .Y(n1771) );
AND2X8TS U1864 ( .A(n2386), .B(n1034), .Y(n1033) );
NOR2X4TS U1865 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[13]), .Y(n1034) );
INVX12TS U1866 ( .A(n1037), .Y(n1774) );
NOR2X8TS U1867 ( .A(n1350), .B(Raw_mant_NRM_SWR[11]), .Y(n1666) );
NAND2X8TS U1868 ( .A(n1349), .B(n1348), .Y(n1350) );
OR2X8TS U1869 ( .A(n1110), .B(intDY_EWSW[18]), .Y(n1602) );
XOR2X4TS U1870 ( .A(n1038), .B(n2207), .Y(n1196) );
AOI22X1TS U1871 ( .A0(n2263), .A1(DmP_mant_SHT1_SW[6]), .B0(n2253), .B1(
n1153), .Y(n2757) );
BUFX16TS U1872 ( .A(n1793), .Y(n1228) );
BUFX20TS U1873 ( .A(n1062), .Y(n1973) );
NOR2X4TS U1874 ( .A(n993), .B(n1230), .Y(n1671) );
NOR2X6TS U1875 ( .A(n1547), .B(n1550), .Y(n1552) );
OAI21X4TS U1876 ( .A0(n1457), .A1(n1456), .B0(n1455), .Y(n1458) );
OR2X8TS U1877 ( .A(n1146), .B(n1106), .Y(n1045) );
INVX8TS U1878 ( .A(n2282), .Y(n1477) );
NAND2X4TS U1879 ( .A(n2398), .B(n1048), .Y(n1564) );
NAND3X2TS U1880 ( .A(n1708), .B(n1709), .C(n1707), .Y(n595) );
XOR2X4TS U1881 ( .A(n1147), .B(DmP_mant_SFG_SWR[3]), .Y(n2055) );
BUFX20TS U1882 ( .A(n1062), .Y(n1097) );
NAND2X4TS U1883 ( .A(shift_value_SHT2_EWR[3]), .B(shift_value_SHT2_EWR[2]),
.Y(n1374) );
AND2X8TS U1884 ( .A(n1115), .B(n1060), .Y(n1049) );
OAI22X4TS U1885 ( .A0(n1656), .A1(n1262), .B0(n1050), .B1(n997), .Y(n1231)
);
NOR3X6TS U1886 ( .A(n1655), .B(n1123), .C(n1132), .Y(n1050) );
NAND2X4TS U1887 ( .A(n1227), .B(n2070), .Y(n1440) );
NOR3X4TS U1888 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[3]), .C(n1284),
.Y(n1802) );
AOI22X2TS U1889 ( .A0(n2129), .A1(n2105), .B0(n2117), .B1(n2104), .Y(n2101)
);
NAND4X4TS U1890 ( .A(n1532), .B(n1531), .C(n1530), .D(n1529), .Y(n1642) );
NOR2X2TS U1891 ( .A(n1518), .B(n1517), .Y(n1530) );
AND2X4TS U1892 ( .A(n2499), .B(n1188), .Y(n2328) );
INVX12TS U1893 ( .A(n1905), .Y(n1188) );
MXI2X4TS U1894 ( .A(n1070), .B(n932), .S0(n2295), .Y(n533) );
AOI22X2TS U1895 ( .A0(n2147), .A1(n2253), .B0(n2146), .B1(n2121), .Y(n2122)
);
NAND4BX4TS U1896 ( .AN(n2638), .B(n2637), .C(n2636), .D(n2635), .Y(n2253) );
XOR2X4TS U1897 ( .A(n2294), .B(n1015), .Y(n1070) );
NAND2X6TS U1898 ( .A(n2521), .B(n2522), .Y(n1285) );
INVX16TS U1899 ( .A(n1939), .Y(n1061) );
NAND3X8TS U1900 ( .A(n2229), .B(n2228), .C(n2227), .Y(n2302) );
NAND2X8TS U1901 ( .A(n2231), .B(n1319), .Y(n2303) );
NAND3X4TS U1902 ( .A(n1007), .B(n1772), .C(n1771), .Y(n1776) );
AO21X2TS U1903 ( .A0(n1278), .A1(n1386), .B0(n1385), .Y(n1389) );
OR2X4TS U1904 ( .A(n1146), .B(n2361), .Y(n2028) );
OR2X4TS U1905 ( .A(n1146), .B(n1058), .Y(n2229) );
OR2X4TS U1906 ( .A(n1146), .B(n1067), .Y(n1680) );
OR2X4TS U1907 ( .A(n1146), .B(n1133), .Y(n1897) );
NAND3X4TS U1908 ( .A(n1464), .B(n2280), .C(n2282), .Y(n1465) );
OAI2BB1X4TS U1909 ( .A0N(n1153), .A1N(n1064), .B0(n2029), .Y(n802) );
INVX6TS U1910 ( .A(n1676), .Y(n2265) );
INVX8TS U1911 ( .A(n1258), .Y(n2244) );
OR2X8TS U1912 ( .A(DMP_exp_NRM2_EW[6]), .B(n1065), .Y(n1469) );
XNOR2X4TS U1913 ( .A(n1461), .B(DMP_exp_NRM2_EW[6]), .Y(n2282) );
NOR2X4TS U1914 ( .A(n2416), .B(n1140), .Y(n1550) );
OAI22X4TS U1915 ( .A0(n1095), .A1(n1103), .B0(n2251), .B1(n1167), .Y(n2743)
);
INVX4TS U1916 ( .A(n1066), .Y(n1067) );
NOR2X6TS U1917 ( .A(n1537), .B(n1574), .Y(n1539) );
NOR2X6TS U1918 ( .A(n984), .B(n1322), .Y(n1321) );
MXI2X4TS U1919 ( .A(n2054), .B(n2432), .S0(n2307), .Y(n769) );
XOR2X4TS U1920 ( .A(n2053), .B(n2052), .Y(n2054) );
MXI2X2TS U1921 ( .A(n2818), .B(n2471), .S0(n2150), .Y(n475) );
OAI2BB2X2TS U1922 ( .B0(n1069), .B1(n1764), .A0N(n2146), .A1N(n2104), .Y(
n1068) );
NAND2X4TS U1923 ( .A(n1462), .B(n1473), .Y(n1463) );
INVX4TS U1924 ( .A(n1071), .Y(n1072) );
NAND2X4TS U1925 ( .A(n2395), .B(intDX_EWSW[28]), .Y(n1628) );
OR2X4TS U1926 ( .A(n1790), .B(n1789), .Y(n1073) );
OR2X8TS U1927 ( .A(n1295), .B(n1294), .Y(n1076) );
OR2X8TS U1928 ( .A(n1295), .B(n1294), .Y(n1077) );
AND2X8TS U1929 ( .A(n2027), .B(n1080), .Y(n1317) );
OR2X8TS U1930 ( .A(intDY_EWSW[10]), .B(n1081), .Y(n1568) );
NOR2X8TS U1931 ( .A(n1541), .B(n1569), .Y(n1571) );
XNOR2X2TS U1932 ( .A(intDY_EWSW[22]), .B(intDX_EWSW[22]), .Y(n1499) );
NOR2X8TS U1933 ( .A(n2393), .B(intDX_EWSW[22]), .Y(n1587) );
NAND2X4TS U1934 ( .A(n2393), .B(intDX_EWSW[22]), .Y(n1611) );
NOR2X8TS U1935 ( .A(n1587), .B(n1612), .Y(n1614) );
NAND2X2TS U1936 ( .A(n1938), .B(intDX_EWSW[16]), .Y(n1855) );
NAND2X4TS U1937 ( .A(n1673), .B(n1659), .Y(n1269) );
NAND2X6TS U1938 ( .A(n1663), .B(n1664), .Y(n1661) );
NOR2X2TS U1939 ( .A(n1122), .B(n1777), .Y(n1805) );
INVX2TS U1940 ( .A(n1666), .Y(n1667) );
BUFX20TS U1941 ( .A(n1734), .Y(n1093) );
BUFX20TS U1942 ( .A(n1287), .Y(n2264) );
INVX16TS U1943 ( .A(n2264), .Y(n1094) );
INVX12TS U1944 ( .A(n2264), .Y(n1095) );
NOR2X4TS U1945 ( .A(n1259), .B(n1115), .Y(n1322) );
NAND4X4TS U1946 ( .A(n1783), .B(n1782), .C(n1781), .D(n1780), .Y(n2202) );
BUFX16TS U1947 ( .A(n1268), .Y(n1166) );
AOI21X2TS U1948 ( .A0(n1278), .A1(n2213), .B0(n2212), .Y(n2216) );
AND4X8TS U1949 ( .A(n1107), .B(n986), .C(n2166), .D(n1675), .Y(n1106) );
OA21X4TS U1950 ( .A0(n1777), .A1(n1670), .B0(n1669), .Y(n1107) );
NOR2X6TS U1951 ( .A(n1090), .B(n1121), .Y(n1557) );
MXI2X4TS U1952 ( .A(n2798), .B(n2463), .S0(n2132), .Y(n488) );
NOR2X2TS U1953 ( .A(n1776), .B(n1099), .Y(n1773) );
NAND2X4TS U1954 ( .A(n2419), .B(intDX_EWSW[16]), .Y(n1599) );
NAND2X6TS U1955 ( .A(n1042), .B(n1296), .Y(n2166) );
AOI2BB2X2TS U1956 ( .B0(n931), .B1(n1137), .A0N(n1077), .A1N(n1113), .Y(
n1293) );
NAND2X4TS U1957 ( .A(n1354), .B(n1071), .Y(n1895) );
NAND3X4TS U1958 ( .A(n1898), .B(n1293), .C(n1292), .Y(n778) );
NOR2X8TS U1959 ( .A(n1577), .B(n1538), .Y(n1579) );
AOI22X2TS U1960 ( .A0(n1052), .A1(n2244), .B0(Raw_mant_NRM_SWR[8]), .B1(
n1260), .Y(n2725) );
OAI2BB1X2TS U1961 ( .A0N(final_result_ieee[31]), .A1N(n2285), .B0(n2154),
.Y(n550) );
XNOR2X4TS U1962 ( .A(intDY_EWSW[10]), .B(intDX_EWSW[10]), .Y(n1504) );
NAND2X2TS U1963 ( .A(n2151), .B(n2141), .Y(n2142) );
NAND3X4TS U1964 ( .A(n1467), .B(n1468), .C(n1466), .Y(n1472) );
NAND3X4TS U1965 ( .A(n1306), .B(n1305), .C(n1304), .Y(n1303) );
MXI2X2TS U1966 ( .A(n2814), .B(n2495), .S0(n2150), .Y(n478) );
NAND2X8TS U1967 ( .A(n2519), .B(n2518), .Y(n1348) );
NAND2X2TS U1968 ( .A(n2168), .B(Raw_mant_NRM_SWR[3]), .Y(n1781) );
NOR2X2TS U1969 ( .A(n1045), .B(n2422), .Y(n2747) );
NOR2X2TS U1970 ( .A(n1045), .B(n2424), .Y(n2751) );
NOR2X2TS U1971 ( .A(n2265), .B(n932), .Y(n2779) );
NOR2X4TS U1972 ( .A(n1591), .B(n1620), .Y(n1593) );
AO22X4TS U1973 ( .A0(n2157), .A1(n1382), .B0(n1064), .B1(n2155), .Y(n1139)
);
OAI2BB1X4TS U1974 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n2347), .B0(n2176),
.Y(n524) );
AOI22X2TS U1975 ( .A0(n2243), .A1(n1098), .B0(n1166), .B1(n1104), .Y(n2773)
);
OR2X6TS U1976 ( .A(n1009), .B(n1326), .Y(n1351) );
AND2X8TS U1977 ( .A(intDY_EWSW[19]), .B(n1087), .Y(n1603) );
XNOR2X4TS U1978 ( .A(intDY_EWSW[23]), .B(intDX_EWSW[23]), .Y(n1505) );
NAND4X2TS U1979 ( .A(n1526), .B(n1525), .C(n1524), .D(n1523), .Y(n1527) );
XNOR2X2TS U1980 ( .A(intDY_EWSW[8]), .B(intDX_EWSW[8]), .Y(n1523) );
OAI21X4TS U1981 ( .A0(n1629), .A1(n1628), .B0(n1627), .Y(n1632) );
INVX8TS U1982 ( .A(n1185), .Y(n1905) );
BUFX20TS U1983 ( .A(n1662), .Y(n1146) );
NOR2X2TS U1984 ( .A(n2023), .B(n2022), .Y(n2703) );
NOR2X2TS U1985 ( .A(n2020), .B(n2019), .Y(n2719) );
AND2X4TS U1986 ( .A(n1672), .B(n2163), .Y(n1296) );
NAND2X4TS U1987 ( .A(n2163), .B(n1181), .Y(n1300) );
NOR2X2TS U1988 ( .A(n1761), .B(n1760), .Y(n2739) );
NAND2X2TS U1989 ( .A(n1938), .B(n935), .Y(n1870) );
NAND2X2TS U1990 ( .A(n1877), .B(intDX_EWSW[2]), .Y(n1861) );
NAND2X2TS U1991 ( .A(n891), .B(n1127), .Y(n1866) );
NAND2X2TS U1992 ( .A(n891), .B(intDX_EWSW[0]), .Y(n1942) );
INVX2TS U1993 ( .A(n1163), .Y(n1148) );
INVX2TS U1994 ( .A(n1163), .Y(n1149) );
INVX2TS U1995 ( .A(n1163), .Y(n1150) );
NAND2X2TS U1996 ( .A(n2093), .B(n2094), .Y(n1377) );
NAND2X2TS U1997 ( .A(n2093), .B(n2219), .Y(n1380) );
NAND2X2TS U1998 ( .A(n2093), .B(n2084), .Y(n1438) );
INVX16TS U1999 ( .A(n1790), .Y(n2093) );
CLKINVX3TS U2000 ( .A(rst), .Y(n1154) );
AOI22X2TS U2001 ( .A0(n2244), .A1(Raw_mant_NRM_SWR[7]), .B0(
Raw_mant_NRM_SWR[6]), .B1(n1166), .Y(n2701) );
AOI22X2TS U2002 ( .A0(n2244), .A1(Raw_mant_NRM_SWR[13]), .B0(
Raw_mant_NRM_SWR[12]), .B1(n1260), .Y(n2737) );
AOI22X2TS U2003 ( .A0(n2244), .A1(Raw_mant_NRM_SWR[3]), .B0(n1166), .B1(
Raw_mant_NRM_SWR[2]), .Y(n2706) );
AOI22X2TS U2004 ( .A0(n2244), .A1(n1055), .B0(n1260), .B1(n1102), .Y(n2758)
);
NAND2X4TS U2005 ( .A(n1914), .B(n1168), .Y(n1915) );
MXI2X2TS U2006 ( .A(n2424), .B(n2048), .S0(n1168), .Y(n518) );
NAND2X2TS U2007 ( .A(n1938), .B(n1119), .Y(n1788) );
NAND2X2TS U2008 ( .A(n1877), .B(intDY_EWSW[30]), .Y(n2012) );
NAND2X2TS U2009 ( .A(n933), .B(intDY_EWSW[13]), .Y(n1970) );
NAND2X2TS U2010 ( .A(n891), .B(intDY_EWSW[18]), .Y(n1988) );
NAND2X2TS U2011 ( .A(n1938), .B(intDY_EWSW[11]), .Y(n1820) );
NAND2X2TS U2012 ( .A(n1972), .B(intDY_EWSW[14]), .Y(n1986) );
NAND2X2TS U2013 ( .A(n891), .B(intDY_EWSW[10]), .Y(n1949) );
NAND2X2TS U2014 ( .A(n934), .B(intDY_EWSW[19]), .Y(n1998) );
NAND2X2TS U2015 ( .A(n2008), .B(intDY_EWSW[21]), .Y(n2005) );
NAND2X2TS U2016 ( .A(n1972), .B(intDY_EWSW[27]), .Y(n1733) );
INVX12TS U2017 ( .A(n1357), .Y(n2263) );
INVX16TS U2018 ( .A(n1357), .Y(n1289) );
NAND2X2TS U2019 ( .A(n1877), .B(intDY_EWSW[8]), .Y(n1963) );
NAND2X2TS U2020 ( .A(n2008), .B(intDX_EWSW[17]), .Y(n1884) );
NAND2X2TS U2021 ( .A(n934), .B(intDY_EWSW[3]), .Y(n1977) );
NAND2X2TS U2022 ( .A(n2008), .B(intDY_EWSW[20]), .Y(n1983) );
NAND2X2TS U2023 ( .A(n891), .B(intDY_EWSW[15]), .Y(n1995) );
NAND2X2TS U2024 ( .A(n1938), .B(intDY_EWSW[26]), .Y(n1749) );
NAND2X2TS U2025 ( .A(n1877), .B(intDY_EWSW[23]), .Y(n1755) );
NAND2X2TS U2026 ( .A(n1938), .B(n1043), .Y(n1946) );
NAND2X2TS U2027 ( .A(n1972), .B(intDY_EWSW[2]), .Y(n1960) );
NAND2X2TS U2028 ( .A(n2008), .B(intDY_EWSW[16]), .Y(n1979) );
NAND2X2TS U2029 ( .A(n1972), .B(intDY_EWSW[17]), .Y(n1992) );
NAND2X2TS U2030 ( .A(n1877), .B(n1089), .Y(n1955) );
NAND2X2TS U2031 ( .A(n1972), .B(intDY_EWSW[22]), .Y(n2000) );
NAND2X2TS U2032 ( .A(n894), .B(intDY_EWSW[27]), .Y(n1787) );
NAND2X2TS U2033 ( .A(n2303), .B(n2299), .Y(n2722) );
NAND2X2TS U2034 ( .A(n2302), .B(n2299), .Y(n2708) );
INVX16TS U2035 ( .A(n1407), .Y(n1178) );
NAND2X2TS U2036 ( .A(n2095), .B(n2260), .Y(n1409) );
NAND2X2TS U2037 ( .A(n2095), .B(n1814), .Y(n1437) );
MX2X4TS U2038 ( .A(n2192), .B(Raw_mant_NRM_SWR[13]), .S0(n1179), .Y(n540) );
NOR2X6TS U2039 ( .A(n1791), .B(n2143), .Y(n1399) );
NAND2X2TS U2040 ( .A(n2008), .B(intDX_EWSW[18]), .Y(n1852) );
NAND2X2TS U2041 ( .A(n1877), .B(intDY_EWSW[12]), .Y(n1958) );
BUFX20TS U2042 ( .A(n2171), .Y(n1181) );
OR2X8TS U2043 ( .A(n2389), .B(n1181), .Y(n2218) );
OR2X4TS U2044 ( .A(n2171), .B(n2827), .Y(n1679) );
CLKINVX3TS U2045 ( .A(rst), .Y(n2826) );
AOI22X2TS U2046 ( .A0(n1289), .A1(DmP_mant_SHT1_SW[14]), .B0(
DmP_mant_SHT1_SW[16]), .B1(n2249), .Y(n2746) );
OAI21X4TS U2047 ( .A0(n1182), .A1(n1617), .B0(n1616), .Y(n1638) );
AOI21X4TS U2048 ( .A0(n1606), .A1(n1605), .B0(n1604), .Y(n1182) );
BUFX20TS U2049 ( .A(n1734), .Y(n1938) );
AND2X8TS U2050 ( .A(n1204), .B(n1183), .Y(n1333) );
OAI22X4TS U2051 ( .A0(n1190), .A1(n1189), .B0(n1188), .B1(n2499), .Y(n1187)
);
XOR2X4TS U2052 ( .A(n2688), .B(DmP_mant_SFG_SWR[8]), .Y(n1904) );
NOR2X8TS U2053 ( .A(n1905), .B(DMP_SFG[7]), .Y(n1190) );
XNOR2X4TS U2054 ( .A(n2688), .B(DmP_mant_SFG_SWR[9]), .Y(n1185) );
XNOR2X4TS U2055 ( .A(n1192), .B(DmP_mant_SFG_SWR[18]), .Y(n1364) );
NOR2X8TS U2056 ( .A(n2418), .B(intDX_EWSW[18]), .Y(n1195) );
OAI21X4TS U2057 ( .A0(n1196), .A1(n2659), .B0(n1311), .Y(n529) );
INVX2TS U2058 ( .A(n1334), .Y(n1198) );
OAI21X4TS U2059 ( .A0(n1202), .A1(n2185), .B0(n2188), .Y(n2177) );
OR2X8TS U2060 ( .A(n1200), .B(n2436), .Y(n2185) );
XNOR2X4TS U2061 ( .A(n1147), .B(DmP_mant_SFG_SWR[12]), .Y(n1200) );
XOR2X4TS U2062 ( .A(n1147), .B(DmP_mant_SFG_SWR[13]), .Y(n1201) );
XOR2X4TS U2063 ( .A(n485), .B(n556), .Y(n2517) );
MXI2X8TS U2064 ( .A(n2803), .B(n1817), .S0(n2306), .Y(n485) );
XOR2X4TS U2065 ( .A(n1191), .B(DmP_mant_SFG_SWR[21]), .Y(n1203) );
AND2X8TS U2066 ( .A(n1706), .B(n1705), .Y(n2794) );
NAND2X1TS U2067 ( .A(n1227), .B(Data_array_SWR_3__25_), .Y(n1487) );
NOR2X8TS U2068 ( .A(n2397), .B(shift_value_SHT2_EWR[3]), .Y(n1227) );
NAND2X8TS U2069 ( .A(n1209), .B(n2193), .Y(n1278) );
NOR2X6TS U2070 ( .A(n1364), .B(DMP_SFG[16]), .Y(n2210) );
OAI21X4TS U2071 ( .A0(n1475), .A1(n1474), .B0(n1473), .Y(n1476) );
OAI21X4TS U2072 ( .A0(n2801), .A1(n2321), .B0(n1211), .Y(n486) );
NAND2X8TS U2073 ( .A(n1265), .B(n1181), .Y(n1213) );
NOR2X8TS U2074 ( .A(n1214), .B(n994), .Y(n1334) );
NOR2X8TS U2075 ( .A(n1931), .B(n1930), .Y(n1214) );
NAND2X2TS U2076 ( .A(n1667), .B(n2386), .Y(n1670) );
OAI21X4TS U2077 ( .A0(n1569), .A1(n1568), .B0(n1567), .Y(n1570) );
OAI21X4TS U2078 ( .A0(n1577), .A1(n1576), .B0(n1575), .Y(n1578) );
OAI21X4TS U2079 ( .A0(n1908), .A1(n2337), .B0(n1907), .Y(n1913) );
NOR2X8TS U2080 ( .A(n1900), .B(n1003), .Y(n2337) );
BUFX6TS U2081 ( .A(n1904), .Y(n1215) );
OAI21X4TS U2082 ( .A0(n2270), .A1(n2267), .B0(n2271), .Y(n1901) );
OAI21X4TS U2083 ( .A0(n1550), .A1(n1549), .B0(n1548), .Y(n1551) );
AOI2BB1X2TS U2084 ( .A0N(n2265), .A1N(n2423), .B0(n1765), .Y(n2715) );
AOI2BB1X2TS U2085 ( .A0N(n2265), .A1N(n2358), .B0(n1763), .Y(n2727) );
NOR2X2TS U2086 ( .A(n2016), .B(n2015), .Y(n2775) );
NOR2X4TS U2087 ( .A(intDX_EWSW[2]), .B(n2409), .Y(n1547) );
NAND2X4TS U2088 ( .A(n2047), .B(DMP_SFG[0]), .Y(n2056) );
XOR2X4TS U2089 ( .A(n1923), .B(n1922), .Y(n1220) );
NAND3X8TS U2090 ( .A(n1042), .B(n1299), .C(n1672), .Y(n1264) );
MXI2X4TS U2091 ( .A(n2800), .B(n2492), .S0(n2306), .Y(n487) );
XOR2X4TS U2092 ( .A(n2359), .B(n1221), .Y(n2526) );
NAND2X8TS U2093 ( .A(n1223), .B(n1239), .Y(n2160) );
OAI21X4TS U2094 ( .A0(n1225), .A1(n2659), .B0(n1224), .Y(n532) );
XOR2X4TS U2095 ( .A(n1405), .B(n1016), .Y(n1225) );
NOR2X8TS U2096 ( .A(n2415), .B(intDX_EWSW[13]), .Y(n1574) );
OAI21X4TS U2097 ( .A0(n1566), .A1(n1565), .B0(n1564), .Y(n1572) );
OAI21X4TS U2098 ( .A0(n1574), .A1(n1000), .B0(n1573), .Y(n1580) );
NAND2X2TS U2099 ( .A(n1228), .B(n2219), .Y(n1794) );
INVX8TS U2100 ( .A(n1663), .Y(n1295) );
NAND2X2TS U2101 ( .A(n2104), .B(n2173), .Y(n1799) );
NAND3BX4TS U2102 ( .AN(n1226), .B(n2170), .C(n2167), .Y(n2172) );
INVX2TS U2103 ( .A(n2163), .Y(n2164) );
BUFX8TS U2104 ( .A(n2824), .Y(n2319) );
NAND2X2TS U2105 ( .A(n2093), .B(n2247), .Y(n1410) );
NAND3X4TS U2106 ( .A(n1430), .B(n1432), .C(n1431), .Y(n1267) );
AND2X8TS U2107 ( .A(n1072), .B(n1133), .Y(n1659) );
INVX8TS U2108 ( .A(n2518), .Y(n1318) );
NOR2X8TS U2109 ( .A(n1076), .B(n991), .Y(n1287) );
NOR2X8TS U2110 ( .A(n1346), .B(n1231), .Y(n1664) );
NAND2X8TS U2111 ( .A(n1661), .B(n1181), .Y(n1662) );
NOR2X8TS U2112 ( .A(n2237), .B(n1077), .Y(n1268) );
INVX16TS U2113 ( .A(n1233), .Y(n1734) );
NAND2X4TS U2114 ( .A(n1593), .B(n1625), .Y(n1596) );
NAND2X6TS U2115 ( .A(n2409), .B(intDX_EWSW[2]), .Y(n1549) );
AOI21X4TS U2116 ( .A0(n1058), .A1(n1102), .B0(n1114), .Y(n1427) );
NAND2X6TS U2117 ( .A(n1595), .B(n1631), .Y(n1634) );
BUFX20TS U2118 ( .A(n1734), .Y(n1877) );
OAI21X4TS U2119 ( .A0(n1918), .A1(n1917), .B0(n1916), .Y(n1923) );
AOI21X4TS U2120 ( .A0(n1716), .A1(n2066), .B0(n1901), .Y(n1918) );
NOR2X6TS U2121 ( .A(n2404), .B(n1143), .Y(n1577) );
NOR2X6TS U2122 ( .A(DMP_SFG[2]), .B(n1715), .Y(n2268) );
BUFX6TS U2123 ( .A(n2245), .Y(n1235) );
NAND2X4TS U2124 ( .A(n1487), .B(n1486), .Y(n2112) );
AND2X8TS U2125 ( .A(n1671), .B(n1004), .Y(n1345) );
NOR2X8TS U2126 ( .A(n1055), .B(n1057), .Y(n1668) );
NOR2X2TS U2127 ( .A(n1807), .B(n1779), .Y(n1780) );
BUFX20TS U2128 ( .A(Shift_reg_FLAGS_7[1]), .Y(n2171) );
AOI22X2TS U2129 ( .A0(n2247), .A1(n2147), .B0(n2108), .B1(n2084), .Y(n1400)
);
XOR2X4TS U2130 ( .A(n484), .B(n556), .Y(n2527) );
OAI21X4TS U2131 ( .A0(n1167), .A1(n2396), .B0(n2026), .Y(n776) );
NOR2X8TS U2132 ( .A(n1330), .B(n1329), .Y(n1328) );
AOI22X2TS U2133 ( .A0(n2250), .A1(n2108), .B0(n2155), .B1(n1814), .Y(n1815)
);
AND2X8TS U2134 ( .A(n1816), .B(n1815), .Y(n2803) );
NOR2X2TS U2135 ( .A(n1806), .B(n1805), .Y(n1811) );
NAND2X6TS U2136 ( .A(n1715), .B(DMP_SFG[2]), .Y(n2267) );
AOI21X4TS U2137 ( .A0(n1208), .A1(n1687), .B0(n1249), .Y(n1248) );
NAND3X8TS U2138 ( .A(n2160), .B(n1245), .C(n2181), .Y(n1243) );
CLKINVX3TS U2139 ( .A(n1359), .Y(n1239) );
AOI21X4TS U2140 ( .A0(n2177), .A1(n2181), .B0(n1242), .Y(n1241) );
XNOR2X4TS U2141 ( .A(n1147), .B(n2465), .Y(n1240) );
OAI21X4TS U2142 ( .A0(n1247), .A1(n2295), .B0(n1246), .Y(n530) );
XOR2X4TS U2143 ( .A(n1248), .B(n1689), .Y(n1247) );
NOR2X8TS U2144 ( .A(n1660), .B(n1254), .Y(n1253) );
NAND2X8TS U2145 ( .A(n2654), .B(n1049), .Y(n1660) );
NAND2X8TS U2146 ( .A(n1352), .B(n1106), .Y(n1258) );
NAND2X8TS U2147 ( .A(n1088), .B(n930), .Y(n2237) );
OAI21X4TS U2148 ( .A0(n1427), .A1(n1428), .B0(n1659), .Y(n1674) );
NOR3X2TS U2149 ( .A(n1136), .B(n1057), .C(n1102), .Y(n1654) );
OAI21X4TS U2150 ( .A0(n2269), .A1(n2268), .B0(n2267), .Y(n2274) );
XOR2X4TS U2151 ( .A(n1191), .B(DmP_mant_SFG_SWR[2]), .Y(n2047) );
NAND3X6TS U2152 ( .A(n1307), .B(n1302), .C(n1301), .Y(n784) );
NAND3BX4TS U2153 ( .AN(n1666), .B(n1424), .C(n1283), .Y(n1282) );
NAND2X8TS U2154 ( .A(n1286), .B(n1285), .Y(n544) );
NAND2X8TS U2155 ( .A(n1347), .B(n2523), .Y(n1286) );
NOR2X8TS U2156 ( .A(n1289), .B(n1013), .Y(n1288) );
OAI21X4TS U2157 ( .A0(n1714), .A1(n2056), .B0(n1713), .Y(n2066) );
AOI2BB2X4TS U2158 ( .B0(n2223), .B1(DmP_mant_SHT1_SW[11]), .A0N(n1259),
.A1N(n2423), .Y(n2225) );
XOR2X4TS U2159 ( .A(n1191), .B(DmP_mant_SFG_SWR[19]), .Y(n1365) );
XOR2X4TS U2160 ( .A(n1315), .B(n1373), .Y(n1314) );
NAND2X8TS U2161 ( .A(n1318), .B(n2520), .Y(n1349) );
OA21X4TS U2162 ( .A0(n1133), .A1(n1077), .B0(n2230), .Y(n1319) );
NOR2X8TS U2163 ( .A(n1774), .B(n1345), .Y(n1663) );
XNOR2X4TS U2164 ( .A(n1192), .B(DmP_mant_SFG_SWR[16]), .Y(n1361) );
OR2X8TS U2165 ( .A(n1369), .B(n2211), .Y(n1341) );
OAI21X4TS U2166 ( .A0(n1686), .A1(n1331), .B0(n1328), .Y(n1933) );
INVX12TS U2167 ( .A(n2291), .Y(n1686) );
NOR2X8TS U2168 ( .A(n1369), .B(n2208), .Y(n2292) );
OAI21X4TS U2169 ( .A0(n1259), .A1(n2018), .B0(n1344), .Y(n1343) );
NAND2BX4TS U2170 ( .AN(n1259), .B(n1066), .Y(n2227) );
NOR2X8TS U2171 ( .A(Raw_mant_NRM_SWR[7]), .B(Raw_mant_NRM_SWR[6]), .Y(n1657)
);
OA21X4TS U2172 ( .A0(n2357), .A1(n1104), .B0(n1099), .Y(n1353) );
AO22X4TS U2173 ( .A0(n1176), .A1(n2261), .B0(n2260), .B1(n1152), .Y(n2262)
);
NOR2X4TS U2174 ( .A(n1690), .B(n1413), .Y(n1416) );
NAND2X2TS U2175 ( .A(n2276), .B(n2299), .Y(n2756) );
OAI21X2TS U2176 ( .A0(n2328), .A1(n2334), .B0(n2329), .Y(n2134) );
NOR2X4TS U2177 ( .A(n2328), .B(n2333), .Y(n2133) );
NAND4X4TS U2178 ( .A(n2630), .B(n2629), .C(n2628), .D(n2627), .Y(n2084) );
AOI21X4TS U2179 ( .A0(n1632), .A1(n1631), .B0(n1630), .Y(n1633) );
MXI2X2TS U2180 ( .A(n2810), .B(n2465), .S0(n2132), .Y(n481) );
AOI22X2TS U2181 ( .A0(n2243), .A1(Raw_mant_NRM_SWR[11]), .B0(n1022), .B1(
n1166), .Y(n2717) );
AOI22X1TS U2182 ( .A0(n2263), .A1(DmP_mant_SHT1_SW[20]), .B0(n2070), .B1(
n1153), .Y(n2786) );
AOI21X2TS U2183 ( .A0(n1289), .A1(DmP_mant_SHT1_SW[16]), .B0(n2262), .Y(
n2731) );
AOI2BB2X2TS U2184 ( .B0(n1289), .B1(DmP_mant_SHT1_SW[11]), .A0N(n1091),
.A1N(n2441), .Y(n2718) );
OAI21X4TS U2185 ( .A0(n1602), .A1(n1603), .B0(n1601), .Y(n1604) );
NAND2X4TS U2186 ( .A(n1207), .B(n2232), .Y(n1418) );
NAND3X6TS U2187 ( .A(n2588), .B(n2587), .C(n2586), .Y(n2232) );
OAI21X4TS U2188 ( .A0(n1609), .A1(n1608), .B0(n1607), .Y(n1615) );
OAI22X2TS U2189 ( .A0(n1257), .A1(n2259), .B0(n2220), .B1(n930), .Y(n2221)
);
OAI21X4TS U2190 ( .A0(n1635), .A1(n1634), .B0(n1633), .Y(n1636) );
NOR2X4TS U2191 ( .A(n1693), .B(n1692), .Y(n1700) );
NAND2X4TS U2192 ( .A(n1597), .B(n1637), .Y(n1640) );
NOR2X4TS U2193 ( .A(n2206), .B(n2204), .Y(n1934) );
NAND2X2TS U2194 ( .A(n891), .B(n1048), .Y(n1829) );
NAND2X2TS U2195 ( .A(n891), .B(intDX_EWSW[14]), .Y(n1826) );
NAND2X2TS U2196 ( .A(n933), .B(intDX_EWSW[12]), .Y(n1857) );
AOI22X2TS U2197 ( .A0(n2109), .A1(n1382), .B0(Data_array_SWR_3__25_), .B1(
n2155), .Y(n1801) );
NAND2X2TS U2198 ( .A(n2008), .B(n1086), .Y(n1881) );
NAND2X2TS U2199 ( .A(n934), .B(n1120), .Y(n1849) );
NAND2X2TS U2200 ( .A(n934), .B(n1121), .Y(n1843) );
MXI2X2TS U2201 ( .A(n2110), .B(n2431), .S0(n2317), .Y(n470) );
AOI22X2TS U2202 ( .A0(n2109), .A1(n1180), .B0(n2108), .B1(
Data_array_SWR_3__25_), .Y(n2110) );
NAND2X2TS U2203 ( .A(n2401), .B(intDX_EWSW[23]), .Y(n1610) );
NAND2X4TS U2204 ( .A(n2421), .B(intDX_EWSW[0]), .Y(n1545) );
NAND4X6TS U2205 ( .A(n2614), .B(n2613), .C(n2612), .D(n2611), .Y(n2094) );
AOI21X4TS U2206 ( .A0(n1580), .A1(n1579), .B0(n1578), .Y(n1581) );
NAND2X2TS U2207 ( .A(n2417), .B(n1120), .Y(n1608) );
NAND4BX4TS U2208 ( .AN(n2598), .B(n2597), .C(n2596), .D(n2595), .Y(n2241) );
NAND2X2TS U2209 ( .A(n2226), .B(n2299), .Y(n2761) );
AOI21X4TS U2210 ( .A0(n1625), .A1(n1626), .B0(n1624), .Y(n1635) );
NOR2X8TS U2211 ( .A(n1623), .B(n1592), .Y(n1625) );
NOR2X4TS U2212 ( .A(n2407), .B(intDX_EWSW[12]), .Y(n1537) );
NOR2X2TS U2213 ( .A(n1808), .B(n1773), .Y(n1783) );
NOR2X2TS U2214 ( .A(n1805), .B(n1131), .Y(n1782) );
OAI21X4TS U2215 ( .A0(n1623), .A1(n1622), .B0(n1621), .Y(n1624) );
NAND2X4TS U2216 ( .A(n2116), .B(n2173), .Y(n1723) );
NAND2X4TS U2217 ( .A(n1440), .B(n1439), .Y(n2116) );
NAND2X2TS U2218 ( .A(n2405), .B(n1078), .Y(n1567) );
NAND2X4TS U2219 ( .A(n2145), .B(n2173), .Y(n1483) );
NOR2X8TS U2220 ( .A(n1596), .B(n1634), .Y(n1637) );
AOI21X4TS U2221 ( .A0(n1638), .A1(n1637), .B0(n1636), .Y(n1639) );
AOI2BB2X2TS U2222 ( .B0(n1289), .B1(DmP_mant_SHT1_SW[15]), .A0N(n1091),
.A1N(n2440), .Y(n2702) );
AOI2BB2X2TS U2223 ( .B0(n1289), .B1(DmP_mant_SHT1_SW[17]), .A0N(n1091),
.A1N(n2439), .Y(n2774) );
AOI2BB2X2TS U2224 ( .B0(n1289), .B1(DmP_mant_SHT1_SW[13]), .A0N(n1092),
.A1N(n2442), .Y(n2726) );
NAND4X6TS U2225 ( .A(n2553), .B(n2552), .C(n2551), .D(n2550), .Y(n2247) );
OAI21X4TS U2226 ( .A0(n1546), .A1(n1545), .B0(n1544), .Y(n1553) );
NAND2X2TS U2227 ( .A(n2404), .B(n1143), .Y(n1575) );
NAND2X2TS U2228 ( .A(n2416), .B(n1140), .Y(n1548) );
XNOR2X2TS U2229 ( .A(intDY_EWSW[14]), .B(intDX_EWSW[14]), .Y(n1510) );
NAND2X2TS U2230 ( .A(n2394), .B(intDX_EWSW[14]), .Y(n1576) );
MXI2X4TS U2231 ( .A(n2124), .B(n2470), .S0(n2150), .Y(n474) );
XNOR2X4TS U2232 ( .A(n1192), .B(DmP_mant_SFG_SWR[6]), .Y(n1717) );
NAND2X2TS U2233 ( .A(n2415), .B(intDX_EWSW[13]), .Y(n1573) );
AOI2BB2X2TS U2234 ( .B0(n1289), .B1(DmP_mant_SHT1_SW[9]), .A0N(n1092), .A1N(
n2443), .Y(n2738) );
NAND2X2TS U2235 ( .A(n1228), .B(n2245), .Y(n1486) );
NAND2X2TS U2236 ( .A(n1228), .B(n2234), .Y(n1480) );
NAND2X2TS U2237 ( .A(n1228), .B(n1434), .Y(n1417) );
OAI21X4TS U2238 ( .A0(n2315), .A1(n2035), .B0(n2037), .Y(n2042) );
NAND2X2TS U2239 ( .A(n2420), .B(n1109), .Y(n1618) );
NAND2X4TS U2240 ( .A(DMP_SFG[6]), .B(n1215), .Y(n2334) );
NOR2X4TS U2241 ( .A(DMP_SFG[6]), .B(n1215), .Y(n2333) );
NOR2X4TS U2242 ( .A(n2387), .B(n1045), .Y(n1760) );
NOR2X4TS U2243 ( .A(n1045), .B(n2018), .Y(n2019) );
NAND2BX2TS U2244 ( .AN(n1045), .B(n1114), .Y(n2783) );
AOI2BB2X2TS U2245 ( .B0(n1289), .B1(DmP_mant_SHT1_SW[7]), .A0N(n1092), .A1N(
n2254), .Y(n2714) );
NOR2X4TS U2246 ( .A(n1045), .B(n1103), .Y(n2771) );
NAND4BX4TS U2247 ( .AN(n2575), .B(n2574), .C(n2573), .D(n2572), .Y(n2245) );
MXI2X4TS U2248 ( .A(n2083), .B(n2082), .S0(n2156), .Y(n1401) );
OAI22X4TS U2249 ( .A0(n1394), .A1(n1690), .B0(n1407), .B1(n1053), .Y(n2083)
);
AOI2BB2X2TS U2250 ( .B0(n2249), .B1(DmP_mant_SHT1_SW[18]), .A0N(n2358),
.A1N(n1095), .Y(n2730) );
NAND2X8TS U2251 ( .A(n1443), .B(DMP_exp_NRM2_EW[2]), .Y(n1456) );
CLKINVX12TS U2252 ( .A(LZD_output_NRM2_EW[2]), .Y(n1443) );
OAI22X2TS U2253 ( .A0(n1094), .A1(n2422), .B0(n2014), .B1(n1167), .Y(n2016)
);
OAI22X2TS U2254 ( .A0(n1094), .A1(n1056), .B0(n1764), .B1(n1167), .Y(n1765)
);
OAI22X2TS U2255 ( .A0(n1095), .A1(n1105), .B0(n1092), .B1(n2426), .Y(n2707)
);
OAI22X2TS U2256 ( .A0(n1095), .A1(n1124), .B0(n2257), .B1(n1167), .Y(n2723)
);
OAI22X2TS U2257 ( .A0(n1095), .A1(n2357), .B0(n1092), .B1(n2255), .Y(n2787)
);
OAI22X2TS U2258 ( .A0(n1095), .A1(n932), .B0(n1091), .B1(n2428), .Y(n2711)
);
OAI22X2TS U2259 ( .A0(n1094), .A1(n2388), .B0(n2021), .B1(n1167), .Y(n2023)
);
OAI22X2TS U2260 ( .A0(n1094), .A1(n1136), .B0(n1759), .B1(n930), .Y(n1761)
);
XNOR2X4TS U2261 ( .A(n2274), .B(n2273), .Y(n2275) );
NOR2X4TS U2262 ( .A(n1454), .B(n1457), .Y(n1460) );
NOR2X8TS U2263 ( .A(DMP_exp_NRM2_EW[2]), .B(n1443), .Y(n1454) );
AOI21X4TS U2264 ( .A0(n1615), .A1(n1614), .B0(n1613), .Y(n1616) );
NOR2X4TS U2265 ( .A(n2395), .B(intDX_EWSW[28]), .Y(n1594) );
NOR2X4TS U2266 ( .A(n1566), .B(n1540), .Y(n1542) );
OAI21X4TS U2267 ( .A0(n1229), .A1(n1284), .B0(n2298), .Y(n2300) );
OAI21X4TS U2268 ( .A0(n1229), .A1(n1136), .B0(n2222), .Y(n2276) );
OR2X8TS U2269 ( .A(n1229), .B(n1060), .Y(n2231) );
OR2X8TS U2270 ( .A(n1229), .B(n1105), .Y(n1665) );
NAND4X6TS U2271 ( .A(n2652), .B(n2651), .C(n2650), .D(n2649), .Y(n2260) );
XOR2X4TS U2272 ( .A(n1191), .B(DmP_mant_SFG_SWR[15]), .Y(n1360) );
NAND2X4TS U2273 ( .A(n2410), .B(intDX_EWSW[26]), .Y(n1622) );
NAND2X4TS U2274 ( .A(n1688), .B(DMP_SFG[21]), .Y(n1926) );
XNOR2X4TS U2275 ( .A(n1471), .B(DMP_exp_NRM2_EW[7]), .Y(n2141) );
OAI21X4TS U2276 ( .A0(n1475), .A1(n1474), .B0(n1470), .Y(n1471) );
NAND2X4TS U2277 ( .A(n1418), .B(n1417), .Y(n2079) );
NAND2X2TS U2278 ( .A(n2006), .B(n2299), .Y(n2728) );
NOR2X4TS U2279 ( .A(n979), .B(n1112), .Y(n1651) );
NAND4BX4TS U2280 ( .AN(n2537), .B(n2536), .C(n2535), .D(n2534), .Y(n2219) );
OAI21X4TS U2281 ( .A0(n1583), .A1(n1582), .B0(n1581), .Y(n1584) );
XOR2X4TS U2282 ( .A(n1191), .B(DmP_mant_SFG_SWR[24]), .Y(n1932) );
OAI21X4TS U2283 ( .A0(n1563), .A1(n1562), .B0(n1561), .Y(n1585) );
AOI21X4TS U2284 ( .A0(n1552), .A1(n1553), .B0(n1551), .Y(n1563) );
NAND4BX4TS U2285 ( .AN(n2547), .B(n2546), .C(n2545), .D(n2544), .Y(n2234) );
NAND2X8TS U2286 ( .A(n2391), .B(n1793), .Y(n1791) );
NAND2X4TS U2287 ( .A(n1365), .B(DMP_SFG[17]), .Y(n2214) );
XOR2X4TS U2288 ( .A(n1192), .B(n2390), .Y(n1715) );
XNOR2X2TS U2289 ( .A(n2332), .B(n2331), .Y(Raw_mant_SGF[9]) );
NOR2X4TS U2290 ( .A(n2347), .B(n1123), .Y(n1432) );
CLKINVX12TS U2291 ( .A(LZD_output_NRM2_EW[3]), .Y(n1444) );
AOI21X2TS U2292 ( .A0(n1924), .A1(n1683), .B0(n1928), .Y(n1684) );
NAND3X4TS U2293 ( .A(n1377), .B(n1376), .C(n1375), .Y(n2127) );
NAND2X4TS U2294 ( .A(n1372), .B(DMP_SFG[20]), .Y(n1682) );
NAND2X2TS U2295 ( .A(n989), .B(n1064), .Y(n2088) );
MXI2X4TS U2296 ( .A(n2796), .B(n2461), .S0(n2321), .Y(n489) );
AND2X8TS U2297 ( .A(n2081), .B(n2080), .Y(n2796) );
MXI2X4TS U2298 ( .A(n2816), .B(n2493), .S0(n2150), .Y(n476) );
AND2X8TS U2299 ( .A(n2077), .B(n2076), .Y(n2816) );
OAI21X4TS U2300 ( .A0(n1620), .A1(n1619), .B0(n1618), .Y(n1626) );
NAND2X8TS U2301 ( .A(n1792), .B(n2391), .Y(n1407) );
NOR2X6TS U2302 ( .A(n2396), .B(shift_value_SHT2_EWR[2]), .Y(n1792) );
MXI2X4TS U2303 ( .A(n2812), .B(n2496), .S0(n2150), .Y(n479) );
AND2X8TS U2304 ( .A(n2107), .B(n2106), .Y(n2812) );
NAND4X4TS U2305 ( .A(n2626), .B(n2625), .C(n2624), .D(n2623), .Y(n2128) );
XNOR2X4TS U2306 ( .A(intDY_EWSW[9]), .B(n1048), .Y(n1503) );
NAND2X4TS U2307 ( .A(n1362), .B(DMP_SFG[15]), .Y(n1392) );
XOR2X4TS U2308 ( .A(n1101), .B(n1447), .Y(n2278) );
NAND2X2TS U2309 ( .A(n1446), .B(n1456), .Y(n1447) );
OAI22X4TS U2310 ( .A0(n1690), .A1(n2014), .B0(n1407), .B1(n1406), .Y(n1813)
);
XOR2X4TS U2311 ( .A(n1475), .B(n1463), .Y(n2280) );
BUFX3TS U2312 ( .A(n2508), .Y(n2682) );
OAI22X2TS U2313 ( .A0(n1094), .A1(n2386), .B0(n2017), .B1(n1167), .Y(n2020)
);
CLKBUFX3TS U2314 ( .A(n2030), .Y(n2513) );
CLKBUFX3TS U2315 ( .A(n1157), .Y(n2516) );
MXI2X4TS U2316 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n2063), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n2158) );
NAND2X8TS U2317 ( .A(n2158), .B(beg_OP), .Y(n2342) );
INVX2TS U2320 ( .A(n2354), .Y(ready) );
OAI21X1TS U2323 ( .A0(n1909), .A1(n2137), .B0(n1910), .Y(n1359) );
XOR2X4TS U2324 ( .A(n1147), .B(DmP_mant_SFG_SWR[17]), .Y(n1362) );
XOR2X4TS U2325 ( .A(n1147), .B(DmP_mant_SFG_SWR[20]), .Y(n1370) );
NOR2X2TS U2326 ( .A(n1681), .B(n1925), .Y(n1371) );
AOI21X4TS U2327 ( .A0(n1391), .A1(n995), .B0(n1363), .Y(n2211) );
AOI21X4TS U2328 ( .A0(n992), .A1(n1367), .B0(n1366), .Y(n1368) );
XOR2X4TS U2329 ( .A(n1147), .B(DmP_mant_SFG_SWR[22]), .Y(n1372) );
AND2X2TS U2330 ( .A(n1924), .B(n1682), .Y(n1373) );
NAND2X1TS U2331 ( .A(n2071), .B(Data_array_SWR_3__25_), .Y(n1375) );
NOR2BX2TS U2332 ( .AN(n2127), .B(n2156), .Y(n1384) );
NAND2X2TS U2333 ( .A(n1178), .B(n2234), .Y(n1379) );
NAND2X1TS U2334 ( .A(n2071), .B(n1064), .Y(n1378) );
NOR2X8TS U2335 ( .A(shift_value_SHT2_EWR[3]), .B(shift_value_SHT2_EWR[2]),
.Y(n1793) );
AOI22X1TS U2336 ( .A0(n2129), .A1(n2258), .B0(n2155), .B1(n2128), .Y(n1381)
);
NOR2X4TS U2337 ( .A(n1384), .B(n1383), .Y(n2806) );
INVX2TS U2338 ( .A(n2208), .Y(n1386) );
INVX2TS U2339 ( .A(n2211), .Y(n1385) );
AND2X2TS U2340 ( .A(n1387), .B(n2209), .Y(n1388) );
XOR2X4TS U2341 ( .A(n1389), .B(n1388), .Y(n1390) );
MX2X4TS U2342 ( .A(n1390), .B(n1066), .S0(n1179), .Y(n535) );
INVX2TS U2343 ( .A(n2260), .Y(n1394) );
NAND2X2TS U2344 ( .A(n2095), .B(n1434), .Y(n1396) );
BUFX8TS U2345 ( .A(n1399), .Y(n2108) );
INVX2TS U2346 ( .A(n2232), .Y(n1406) );
AOI22X1TS U2347 ( .A0(n2250), .A1(n2147), .B0(n2108), .B1(n1814), .Y(n1411)
);
INVX2TS U2348 ( .A(n2241), .Y(n1413) );
NOR2X1TS U2349 ( .A(n1791), .B(n1414), .Y(n1415) );
NAND2X1TS U2350 ( .A(n2096), .B(n1814), .Y(n1421) );
NAND4X4TS U2351 ( .A(n1422), .B(n1421), .C(n1420), .D(n1419), .Y(n1423) );
BUFX8TS U2352 ( .A(n2824), .Y(n2317) );
MXI2X4TS U2353 ( .A(n999), .B(n2469), .S0(n2317), .Y(n473) );
NAND2X2TS U2354 ( .A(n1426), .B(n1657), .Y(n1672) );
OAI21X4TS U2355 ( .A0(n1114), .A1(n1056), .B0(n1005), .Y(n1428) );
INVX8TS U2356 ( .A(n2506), .Y(n2320) );
AOI22X2TS U2357 ( .A0(n1289), .A1(DmP_mant_SHT1_SW[18]), .B0(n2249), .B1(
DmP_mant_SHT1_SW[20]), .Y(n2750) );
NAND2X1TS U2358 ( .A(n2096), .B(n1434), .Y(n1435) );
NOR2X4TS U2359 ( .A(n2173), .B(n2143), .Y(n2146) );
AOI22X1TS U2360 ( .A0(n2147), .A1(n2241), .B0(n2146), .B1(n2116), .Y(n1441)
);
INVX2TS U2361 ( .A(n1457), .Y(n1445) );
NOR2X1TS U2362 ( .A(n1469), .B(DMP_exp_NRM2_EW[7]), .Y(n1452) );
INVX2TS U2363 ( .A(n1474), .Y(n1462) );
AND2X8TS U2364 ( .A(n1465), .B(n2690), .Y(n2151) );
INVX2TS U2365 ( .A(n2278), .Y(n1468) );
INVX2TS U2366 ( .A(n1469), .Y(n1470) );
XNOR2X4TS U2367 ( .A(n1476), .B(DMP_exp_NRM2_EW[5]), .Y(n2286) );
NOR2X6TS U2368 ( .A(n2280), .B(n2286), .Y(n1478) );
NAND2X8TS U2369 ( .A(n2151), .B(n2153), .Y(n2013) );
NAND2X1TS U2370 ( .A(n1227), .B(n1064), .Y(n1481) );
NAND2X1TS U2371 ( .A(n2096), .B(n2219), .Y(n1482) );
NAND4BX2TS U2372 ( .AN(n2634), .B(n2633), .C(n2632), .D(n2631), .Y(n2256) );
AOI22X1TS U2373 ( .A0(n2147), .A1(n2256), .B0(n2146), .B1(n2112), .Y(n1488)
);
XNOR2X1TS U2374 ( .A(n1043), .B(n1127), .Y(n1494) );
XNOR2X1TS U2375 ( .A(intDY_EWSW[18]), .B(intDX_EWSW[18]), .Y(n1491) );
NAND4X1TS U2376 ( .A(n1494), .B(n1493), .C(n1492), .D(n1491), .Y(n1498) );
XOR2X1TS U2377 ( .A(intDY_EWSW[30]), .B(intDX_EWSW[30]), .Y(n1497) );
XOR2X1TS U2378 ( .A(intDY_EWSW[25]), .B(n1109), .Y(n1495) );
NOR4X2TS U2379 ( .A(n1498), .B(n1497), .C(n1496), .D(n1495), .Y(n1532) );
NAND4X1TS U2380 ( .A(n1512), .B(n1511), .C(n1510), .D(n1509), .Y(n1518) );
XNOR2X1TS U2381 ( .A(intDY_EWSW[24]), .B(n1118), .Y(n1516) );
NAND4X1TS U2382 ( .A(n1516), .B(n1515), .C(n1514), .D(n1513), .Y(n1517) );
XNOR2X1TS U2383 ( .A(intDY_EWSW[3]), .B(n1140), .Y(n1522) );
NAND4X1TS U2384 ( .A(n1522), .B(n1521), .C(n1520), .D(n1519), .Y(n1528) );
XNOR2X1TS U2385 ( .A(intDX_EWSW[0]), .B(intDY_EWSW[0]), .Y(n1526) );
NOR2X1TS U2386 ( .A(n1528), .B(n1527), .Y(n1529) );
CLKXOR2X2TS U2387 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1643) );
INVX2TS U2388 ( .A(n1643), .Y(n1533) );
NOR2X4TS U2389 ( .A(n1533), .B(n2434), .Y(n1645) );
INVX2TS U2390 ( .A(n1645), .Y(n1536) );
NOR2X1TS U2391 ( .A(intDX_EWSW[31]), .B(n1643), .Y(n1534) );
NOR2X4TS U2392 ( .A(n1582), .B(n1543), .Y(n1586) );
AOI21X4TS U2393 ( .A0(n1572), .A1(n1571), .B0(n1570), .Y(n1583) );
AOI21X4TS U2394 ( .A0(n1585), .A1(n1586), .B0(n1584), .Y(n1641) );
OAI21X4TS U2395 ( .A0(n1641), .A1(n1640), .B0(n1639), .Y(n1644) );
AND2X8TS U2396 ( .A(n1644), .B(Shift_reg_FLAGS_7_6), .Y(n1939) );
MXI2X1TS U2397 ( .A(n1645), .B(SIGN_FLAG_EXP), .S0(n2444), .Y(n1646) );
NOR2X4TS U2398 ( .A(n1135), .B(n1102), .Y(n1649) );
OAI21X4TS U2399 ( .A0(n1654), .A1(n1653), .B0(n1778), .Y(n1656) );
NOR2X2TS U2400 ( .A(n1681), .B(n1685), .Y(n1687) );
INVX2TS U2401 ( .A(n1682), .Y(n1928) );
XOR2X4TS U2402 ( .A(n1191), .B(DmP_mant_SFG_SWR[23]), .Y(n1688) );
NOR2X2TS U2403 ( .A(n1690), .B(n1141), .Y(n1693) );
NAND2X1TS U2404 ( .A(n1792), .B(Data_array_SWR_3__25_), .Y(n1695) );
NAND3X4TS U2405 ( .A(n1696), .B(n1695), .C(n1694), .Y(n2121) );
NAND2X4TS U2406 ( .A(n2121), .B(n2173), .Y(n1699) );
NAND2X1TS U2407 ( .A(n2096), .B(n2128), .Y(n1698) );
NAND2X2TS U2408 ( .A(n1178), .B(n2128), .Y(n1704) );
NAND2X4TS U2409 ( .A(n2144), .B(n1382), .Y(n1706) );
NOR2X4TS U2410 ( .A(n2156), .B(n2173), .Y(n2117) );
NAND2X2TS U2411 ( .A(n1972), .B(n1078), .Y(n1709) );
NAND2X2TS U2412 ( .A(n895), .B(intDY_EWSW[11]), .Y(n1708) );
MXI2X4TS U2413 ( .A(n2506), .B(n2360), .S0(n2348), .Y(n873) );
MXI2X4TS U2414 ( .A(n1012), .B(n2266), .S0(n2348), .Y(n870) );
NOR2X2TS U2415 ( .A(n2055), .B(DMP_SFG[1]), .Y(n1714) );
NOR2X4TS U2416 ( .A(n1717), .B(DMP_SFG[4]), .Y(n1917) );
INVX2TS U2417 ( .A(n1917), .Y(n1718) );
NAND2X4TS U2418 ( .A(n1717), .B(DMP_SFG[4]), .Y(n1916) );
NAND2X2TS U2419 ( .A(n1938), .B(intDY_EWSW[0]), .Y(n1721) );
MXI2X4TS U2420 ( .A(n2822), .B(n2477), .S0(n2317), .Y(n471) );
NAND4BX2TS U2421 ( .AN(n2592), .B(n2591), .C(n2590), .D(n2589), .Y(n2240) );
AOI22X1TS U2422 ( .A0(n2240), .A1(n2155), .B0(n2108), .B1(n2232), .Y(n1727)
);
NAND2X1TS U2423 ( .A(n2096), .B(n2247), .Y(n1722) );
NAND2X2TS U2424 ( .A(n1728), .B(n1180), .Y(n1726) );
MXI2X4TS U2425 ( .A(n2820), .B(n2468), .S0(n2317), .Y(n472) );
AOI22X1TS U2426 ( .A0(n2240), .A1(n2108), .B0(n2155), .B1(n2232), .Y(n1730)
);
NAND2X2TS U2427 ( .A(n1728), .B(n1382), .Y(n1729) );
MXI2X4TS U2428 ( .A(n2789), .B(n2472), .S0(n2150), .Y(n519) );
BUFX20TS U2429 ( .A(n1734), .Y(n2008) );
NAND2X2TS U2430 ( .A(n1096), .B(n1119), .Y(n1732) );
BUFX20TS U2431 ( .A(n1734), .Y(n1972) );
NAND2X2TS U2432 ( .A(n1968), .B(DmP_EXP_EWSW[25]), .Y(n1744) );
NAND2X2TS U2433 ( .A(n1973), .B(intDX_EWSW[26]), .Y(n1748) );
NAND2X2TS U2434 ( .A(n1943), .B(DMP_EXP_EWSW[24]), .Y(n1750) );
NAND2X2TS U2435 ( .A(n1943), .B(DMP_EXP_EWSW[23]), .Y(n1753) );
NAND3X2TS U2436 ( .A(n1755), .B(n1754), .C(n1753), .Y(n737) );
INVX2TS U2437 ( .A(n2084), .Y(n1759) );
INVX2TS U2438 ( .A(n1814), .Y(n1762) );
OAI22X2TS U2439 ( .A0(n1094), .A1(n1122), .B0(n1762), .B1(n1167), .Y(n1763)
);
INVX2TS U2440 ( .A(n2105), .Y(n1764) );
NAND2X4TS U2441 ( .A(n1769), .B(n1778), .Y(n1804) );
OAI21X1TS U2442 ( .A0(Raw_mant_NRM_SWR[13]), .A1(Raw_mant_NRM_SWR[11]), .B0(
n1803), .Y(n1770) );
INVX2TS U2443 ( .A(n1775), .Y(n2165) );
NOR2X8TS U2444 ( .A(n1776), .B(n2165), .Y(n2168) );
NOR2X2TS U2445 ( .A(n1777), .B(n2386), .Y(n1807) );
OAI21X1TS U2446 ( .A0(n1778), .A1(n1262), .B0(n986), .Y(n1779) );
NOR2X1TS U2447 ( .A(n931), .B(n2033), .Y(n1784) );
MXI2X4TS U2448 ( .A(n2202), .B(n1784), .S0(n1012), .Y(n1785) );
NAND2X1TS U2449 ( .A(n1792), .B(n1064), .Y(n1795) );
NAND3X4TS U2450 ( .A(n1796), .B(n1795), .C(n1794), .Y(n2104) );
NAND2X1TS U2451 ( .A(n2096), .B(n2258), .Y(n1798) );
NAND4X4TS U2452 ( .A(n1800), .B(n1799), .C(n1798), .D(n1797), .Y(n2109) );
MXI2X2TS U2453 ( .A(n1801), .B(n2462), .S0(n2132), .Y(n516) );
NOR2X1TS U2454 ( .A(n1804), .B(n1803), .Y(n1806) );
INVX2TS U2455 ( .A(n1808), .Y(n1809) );
OA21X4TS U2456 ( .A0(n1181), .A1(LZD_output_NRM2_EW[3]), .B0(n2024), .Y(n517) );
MXI2X4TS U2457 ( .A(n1813), .B(n1812), .S0(n2156), .Y(n1816) );
INVX2TS U2458 ( .A(n2349), .Y(n1817) );
NAND2X2TS U2459 ( .A(n1096), .B(n1078), .Y(n1819) );
NAND3X2TS U2460 ( .A(n1819), .B(n1820), .C(n1818), .Y(n749) );
NAND2X2TS U2461 ( .A(n929), .B(n1048), .Y(n1822) );
BUFX12TS U2462 ( .A(n1885), .Y(n1974) );
NAND3X2TS U2463 ( .A(n1826), .B(n1825), .C(n1824), .Y(n589) );
NAND3X2TS U2464 ( .A(n1829), .B(n1828), .C(n1827), .Y(n599) );
NAND2X2TS U2465 ( .A(n895), .B(intDY_EWSW[6]), .Y(n1832) );
NAND3X2TS U2466 ( .A(n1832), .B(n1831), .C(n1830), .Y(n605) );
NAND2X2TS U2467 ( .A(n929), .B(intDY_EWSW[10]), .Y(n1835) );
NAND2X2TS U2468 ( .A(n890), .B(n1116), .Y(n1838) );
NAND2X2TS U2469 ( .A(n929), .B(n1089), .Y(n1842) );
NAND2X2TS U2470 ( .A(n890), .B(intDY_EWSW[22]), .Y(n1846) );
NAND2X2TS U2471 ( .A(n929), .B(intDY_EWSW[20]), .Y(n1848) );
NAND2X2TS U2472 ( .A(n1973), .B(intDY_EWSW[18]), .Y(n1851) );
NAND2X2TS U2473 ( .A(n2002), .B(intDY_EWSW[16]), .Y(n1854) );
NAND2X2TS U2474 ( .A(n1974), .B(DmP_EXP_EWSW[16]), .Y(n1853) );
NAND3X2TS U2475 ( .A(n1854), .B(n1855), .C(n1853), .Y(n585) );
NAND2X2TS U2476 ( .A(n929), .B(intDY_EWSW[12]), .Y(n1858) );
NAND2X1TS U2477 ( .A(n1885), .B(n593), .Y(n1856) );
NAND2X2TS U2478 ( .A(n2002), .B(intDY_EWSW[2]), .Y(n1860) );
NAND2X2TS U2479 ( .A(n1096), .B(intDY_EWSW[8]), .Y(n1864) );
NAND3X2TS U2480 ( .A(n1864), .B(n1863), .C(n1862), .Y(n601) );
NAND2X2TS U2481 ( .A(n893), .B(n1043), .Y(n1867) );
NAND3X2TS U2482 ( .A(n1867), .B(n1866), .C(n1865), .Y(n615) );
NAND2X1TS U2483 ( .A(n1885), .B(DmP_EXP_EWSW[13]), .Y(n1868) );
NAND2X2TS U2484 ( .A(n1096), .B(intDY_EWSW[21]), .Y(n1873) );
NAND3X2TS U2485 ( .A(n1873), .B(n1872), .C(n1871), .Y(n575) );
NAND2X2TS U2486 ( .A(n2002), .B(intDY_EWSW[15]), .Y(n1876) );
NAND3X2TS U2487 ( .A(n1876), .B(n1875), .C(n1874), .Y(n587) );
NAND2X2TS U2488 ( .A(n1096), .B(intDY_EWSW[19]), .Y(n1880) );
NAND2X2TS U2489 ( .A(n892), .B(intDY_EWSW[17]), .Y(n1883) );
NAND2X2TS U2490 ( .A(n1974), .B(DmP_EXP_EWSW[17]), .Y(n1882) );
NAND2X1TS U2491 ( .A(n1885), .B(n980), .Y(n1886) );
NAND2X2TS U2492 ( .A(n893), .B(intDX_EWSW[28]), .Y(n1890) );
NAND3X2TS U2493 ( .A(n1890), .B(n1891), .C(n1889), .Y(n732) );
AOI22X1TS U2494 ( .A0(n2223), .A1(DmP_mant_SHT1_SW[1]), .B0(n2296), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1896) );
XNOR2X4TS U2495 ( .A(n1192), .B(DmP_mant_SFG_SWR[7]), .Y(n1899) );
NOR2X4TS U2496 ( .A(n1917), .B(n1919), .Y(n1902) );
OAI21X4TS U2497 ( .A0(n1919), .A1(n1916), .B0(n1920), .Y(n1900) );
NAND2X1TS U2498 ( .A(n2133), .B(n2138), .Y(n1908) );
INVX2TS U2499 ( .A(n2137), .Y(n1906) );
INVX2TS U2500 ( .A(n1909), .Y(n1911) );
XNOR2X4TS U2501 ( .A(n1913), .B(n1912), .Y(n1914) );
OAI2BB1X4TS U2502 ( .A0N(Raw_mant_NRM_SWR[11]), .A1N(n2295), .B0(n1915), .Y(
n542) );
INVX2TS U2503 ( .A(n1919), .Y(n1921) );
NAND2X1TS U2504 ( .A(n1921), .B(n1920), .Y(n1922) );
INVX2TS U2505 ( .A(n1926), .Y(n1927) );
AOI21X4TS U2506 ( .A0(n1208), .A1(n1934), .B0(n1933), .Y(n1935) );
XOR2X4TS U2507 ( .A(n1935), .B(n1356), .Y(n1937) );
OAI21X4TS U2508 ( .A0(n1937), .A1(n1179), .B0(n1936), .Y(n528) );
NAND2X1TS U2509 ( .A(n2060), .B(DmP_EXP_EWSW[0]), .Y(n1940) );
NAND3X2TS U2510 ( .A(n1942), .B(n1941), .C(n1940), .Y(n617) );
NAND2X2TS U2511 ( .A(n1096), .B(n1127), .Y(n1945) );
NAND3X2TS U2512 ( .A(n1945), .B(n1946), .C(n1944), .Y(n759) );
NAND2X2TS U2513 ( .A(n895), .B(intDX_EWSW[10]), .Y(n1948) );
NAND3X2TS U2514 ( .A(n1948), .B(n1949), .C(n1947), .Y(n750) );
NAND2X2TS U2515 ( .A(n2002), .B(n1111), .Y(n1952) );
NAND3X2TS U2516 ( .A(n1952), .B(n1951), .C(n1950), .Y(n754) );
NAND2X2TS U2517 ( .A(n2002), .B(n1121), .Y(n1954) );
NAND3X2TS U2518 ( .A(n1954), .B(n1955), .C(n1953), .Y(n755) );
NAND2X2TS U2519 ( .A(n2002), .B(intDX_EWSW[12]), .Y(n1957) );
NAND3X2TS U2520 ( .A(n1960), .B(n1961), .C(n1959), .Y(n758) );
NAND2X2TS U2521 ( .A(n894), .B(intDX_EWSW[8]), .Y(n1964) );
NAND3X2TS U2522 ( .A(n1964), .B(n1963), .C(n1962), .Y(n752) );
NAND2X2TS U2523 ( .A(n1096), .B(n1082), .Y(n1967) );
NAND3X2TS U2524 ( .A(n1967), .B(n1966), .C(n1965), .Y(n756) );
NAND2X2TS U2525 ( .A(n929), .B(n935), .Y(n1971) );
NAND2X2TS U2526 ( .A(n929), .B(n1140), .Y(n1976) );
NAND2X2TS U2527 ( .A(n907), .B(intDX_EWSW[16]), .Y(n1980) );
NAND2X2TS U2528 ( .A(n2002), .B(n1120), .Y(n1982) );
NAND2X2TS U2529 ( .A(n1062), .B(intDX_EWSW[14]), .Y(n1985) );
NAND2X2TS U2530 ( .A(n2444), .B(DMP_EXP_EWSW[14]), .Y(n1984) );
NAND2X2TS U2531 ( .A(n894), .B(intDX_EWSW[18]), .Y(n1989) );
NAND2X2TS U2532 ( .A(n2444), .B(DMP_EXP_EWSW[18]), .Y(n1987) );
NAND3X2TS U2533 ( .A(n1989), .B(n1988), .C(n1987), .Y(n742) );
NAND2X2TS U2534 ( .A(n890), .B(intDX_EWSW[17]), .Y(n1991) );
NAND3X2TS U2535 ( .A(n1995), .B(n1994), .C(n1993), .Y(n745) );
NAND2X2TS U2536 ( .A(n929), .B(n1086), .Y(n1997) );
NAND2X2TS U2537 ( .A(n892), .B(intDX_EWSW[22]), .Y(n2001) );
NAND3X2TS U2538 ( .A(n2001), .B(n2000), .C(n1999), .Y(n738) );
NAND2X2TS U2539 ( .A(n2060), .B(DMP_EXP_EWSW[21]), .Y(n2003) );
NAND2X4TS U2540 ( .A(n2007), .B(n1174), .Y(n2733) );
NAND2X2TS U2541 ( .A(n893), .B(intDX_EWSW[30]), .Y(n2011) );
OAI2BB1X4TS U2542 ( .A0N(underflow_flag), .A1N(n2266), .B0(n2290), .Y(n566)
);
INVX2TS U2543 ( .A(n2128), .Y(n2017) );
INVX2TS U2544 ( .A(n2094), .Y(n2021) );
NAND2X1TS U2545 ( .A(Shift_amount_SHT1_EWR[3]), .B(n2320), .Y(n2025) );
OAI2BB1X4TS U2546 ( .A0N(n1012), .A1N(n2025), .B0(n2024), .Y(n2026) );
AOI21X1TS U2547 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n2347), .B0(n2223), .Y(
n2027) );
CLKBUFX3TS U2548 ( .A(n1172), .Y(n2030) );
CLKBUFX3TS U2549 ( .A(n2030), .Y(n2514) );
CLKBUFX2TS U2550 ( .A(n2514), .Y(n2509) );
CLKBUFX3TS U2551 ( .A(n2030), .Y(n2508) );
CLKBUFX3TS U2552 ( .A(n2508), .Y(n2507) );
BUFX3TS U2553 ( .A(n2662), .Y(n2665) );
BUFX3TS U2554 ( .A(n2672), .Y(n2664) );
BUFX3TS U2555 ( .A(n1170), .Y(n2675) );
BUFX3TS U2556 ( .A(n1155), .Y(n2667) );
CLKBUFX3TS U2557 ( .A(n2509), .Y(n2671) );
BUFX3TS U2558 ( .A(n1148), .Y(n2679) );
BUFX3TS U2559 ( .A(n1157), .Y(n2515) );
BUFX3TS U2560 ( .A(n1148), .Y(n2680) );
BUFX3TS U2561 ( .A(n1149), .Y(n2681) );
BUFX3TS U2562 ( .A(n2514), .Y(n2678) );
CLKBUFX3TS U2563 ( .A(n2030), .Y(n2674) );
BUFX3TS U2564 ( .A(n2687), .Y(n2683) );
BUFX3TS U2565 ( .A(n2662), .Y(n2660) );
BUFX3TS U2566 ( .A(n2669), .Y(n2677) );
BUFX3TS U2567 ( .A(n1172), .Y(n2661) );
BUFX3TS U2568 ( .A(n1149), .Y(n2686) );
BUFX3TS U2569 ( .A(n1148), .Y(n2684) );
BUFX3TS U2570 ( .A(n2674), .Y(n2685) );
CLKMX2X2TS U2571 ( .A(SIGN_FLAG_SHT1SHT2), .B(SIGN_FLAG_NRM), .S0(n2171),
.Y(n551) );
OAI21X1TS U2572 ( .A0(n2320), .A1(n1382), .B0(n1012), .Y(n836) );
CLKMX2X2TS U2573 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n2171),
.Y(n623) );
CLKMX2X2TS U2574 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n2171),
.Y(n618) );
CLKMX2X2TS U2575 ( .A(ZERO_FLAG_SHT1SHT2), .B(ZERO_FLAG_NRM), .S0(n1181),
.Y(n560) );
CLKMX2X2TS U2576 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n1181),
.Y(n628) );
CLKMX2X2TS U2577 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n2171),
.Y(n643) );
CLKMX2X2TS U2578 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n1181),
.Y(n653) );
CLKMX2X2TS U2579 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n1181),
.Y(n633) );
INVX2TS U2580 ( .A(n2657), .Y(n2031) );
CLKMX2X2TS U2581 ( .A(n2031), .B(DMP_exp_NRM_EW[1]), .S0(n2171), .Y(n648) );
NOR2X2TS U2582 ( .A(DMP_EXP_EWSW[24]), .B(n947), .Y(n2035) );
XNOR2X1TS U2583 ( .A(DMP_EXP_EWSW[25]), .B(DmP_EXP_EWSW[25]), .Y(n2032) );
XNOR2X1TS U2584 ( .A(n2042), .B(n2032), .Y(n2034) );
MXI2X1TS U2585 ( .A(n2034), .B(n2033), .S0(n2307), .Y(n771) );
INVX2TS U2586 ( .A(n2035), .Y(n2036) );
NAND2X1TS U2587 ( .A(n2037), .B(n2036), .Y(n2038) );
XNOR2X1TS U2588 ( .A(n2038), .B(n2315), .Y(n2039) );
MXI2X1TS U2589 ( .A(n2039), .B(n2476), .S0(n2307), .Y(n772) );
MXI2X2TS U2590 ( .A(n2695), .B(n2480), .S0(n1236), .Y(n630) );
MXI2X2TS U2591 ( .A(n2696), .B(n2481), .S0(n1236), .Y(n635) );
MXI2X2TS U2592 ( .A(n2699), .B(n2485), .S0(n1236), .Y(n655) );
MXI2X2TS U2593 ( .A(n2697), .B(n2482), .S0(n1236), .Y(n640) );
MXI2X2TS U2594 ( .A(n2693), .B(n2478), .S0(n1236), .Y(n620) );
MXI2X2TS U2595 ( .A(n2694), .B(n2479), .S0(n1236), .Y(n625) );
MXI2X2TS U2596 ( .A(n2698), .B(n2484), .S0(n1236), .Y(n650) );
NOR2X1TS U2597 ( .A(n2376), .B(DmP_EXP_EWSW[25]), .Y(n2041) );
INVX2TS U2598 ( .A(n2049), .Y(n2043) );
NOR2X2TS U2599 ( .A(DMP_EXP_EWSW[26]), .B(n2445), .Y(n2050) );
XOR2X1TS U2600 ( .A(n2051), .B(n2044), .Y(n2046) );
INVX2TS U2601 ( .A(Shift_amount_SHT1_EWR[3]), .Y(n2045) );
XNOR2X1TS U2602 ( .A(n2047), .B(DMP_SFG[0]), .Y(n2048) );
CLKMX2X2TS U2603 ( .A(DMP_exp_NRM_EW[4]), .B(DMP_SFG[27]), .S0(n2312), .Y(
n634) );
CLKMX2X2TS U2604 ( .A(DMP_exp_NRM_EW[2]), .B(DMP_SFG[25]), .S0(n2312), .Y(
n644) );
CLKMX2X2TS U2605 ( .A(DMP_exp_NRM_EW[1]), .B(DMP_SFG[24]), .S0(n2312), .Y(
n649) );
CLKMX2X2TS U2606 ( .A(SIGN_FLAG_NRM), .B(SIGN_FLAG_SFG), .S0(n2312), .Y(n552) );
CLKMX2X2TS U2607 ( .A(DMP_exp_NRM_EW[5]), .B(DMP_SFG[28]), .S0(n2312), .Y(
n629) );
XOR2X1TS U2608 ( .A(DMP_EXP_EWSW[27]), .B(DmP_EXP_EWSW[27]), .Y(n2052) );
XOR2X1TS U2609 ( .A(n2055), .B(DMP_SFG[1]), .Y(n2057) );
XOR2X1TS U2610 ( .A(n2057), .B(n2056), .Y(n2058) );
MXI2X1TS U2611 ( .A(n2357), .B(n2058), .S0(n2312), .Y(n526) );
OAI2BB1X2TS U2612 ( .A0N(OP_FLAG_EXP), .A1N(n2060), .B0(n2059), .Y(n729) );
MXI2X1TS U2613 ( .A(beg_OP), .B(n2447), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n2062) );
NOR2X1TS U2614 ( .A(inst_FSM_INPUT_ENABLE_state_reg[1]), .B(
inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n2061) );
OAI21X1TS U2615 ( .A0(n2062), .A1(n2063), .B0(n2064), .Y(n877) );
INVX2TS U2616 ( .A(n2063), .Y(n2324) );
XNOR2X1TS U2617 ( .A(n1191), .B(DmP_mant_SFG_SWR[1]), .Y(n2065) );
INVX2TS U2618 ( .A(n2268), .Y(n2067) );
NAND2X1TS U2619 ( .A(n2067), .B(n2267), .Y(n2068) );
XOR2X1TS U2620 ( .A(n2269), .B(n2068), .Y(n2069) );
NAND2X2TS U2621 ( .A(n1178), .B(n2247), .Y(n2074) );
NAND2X1TS U2622 ( .A(n2096), .B(n2260), .Y(n2072) );
NAND2X2TS U2623 ( .A(n2078), .B(n1180), .Y(n2077) );
AOI22X1TS U2624 ( .A0(n2147), .A1(n1128), .B0(n2146), .B1(n2079), .Y(n2076)
);
NAND2X2TS U2625 ( .A(n2078), .B(n1382), .Y(n2081) );
AOI22X1TS U2626 ( .A0(n2129), .A1(n1128), .B0(n2117), .B1(n2079), .Y(n2080)
);
AOI22X1TS U2627 ( .A0(n2247), .A1(n2108), .B0(n2155), .B1(n2084), .Y(n2085)
);
AND2X4TS U2628 ( .A(n2086), .B(n2085), .Y(n2810) );
NAND2X2TS U2629 ( .A(n1178), .B(n2219), .Y(n2089) );
NAND2X1TS U2630 ( .A(n2071), .B(n2234), .Y(n2087) );
NAND2X2TS U2631 ( .A(n2120), .B(n1382), .Y(n2092) );
AND2X4TS U2632 ( .A(n2092), .B(n2091), .Y(n2800) );
NAND2X1TS U2633 ( .A(n2093), .B(n2128), .Y(n2100) );
NAND2X1TS U2634 ( .A(n989), .B(Data_array_SWR_3__25_), .Y(n2098) );
NAND2X1TS U2635 ( .A(n2096), .B(n1235), .Y(n2097) );
AOI22X1TS U2636 ( .A0(n2129), .A1(n2256), .B0(n2117), .B1(n2112), .Y(n2113)
);
NAND2X2TS U2637 ( .A(n2115), .B(n2156), .Y(n2119) );
AOI22X1TS U2638 ( .A0(n2129), .A1(n2241), .B0(n2117), .B1(n2116), .Y(n2118)
);
AND2X4TS U2639 ( .A(n2119), .B(n2118), .Y(n2798) );
NAND2X2TS U2640 ( .A(n2120), .B(n1180), .Y(n2123) );
AND2X4TS U2641 ( .A(n2123), .B(n2122), .Y(n2814) );
AOI22X1TS U2642 ( .A0(n2129), .A1(n2128), .B0(n2155), .B1(n2258), .Y(n2130)
);
AND2X4TS U2643 ( .A(n2131), .B(n2130), .Y(n2808) );
INVX2TS U2644 ( .A(n2133), .Y(n2136) );
INVX2TS U2645 ( .A(n2134), .Y(n2135) );
XNOR2X1TS U2646 ( .A(n2140), .B(n2139), .Y(Raw_mant_SGF[10]) );
NAND2X2TS U2647 ( .A(n2144), .B(n2143), .Y(n2149) );
AOI22X1TS U2648 ( .A0(n2147), .A1(n2246), .B0(n2146), .B1(n2145), .Y(n2148)
);
AND2X4TS U2649 ( .A(n2149), .B(n2148), .Y(n2818) );
MXI2X1TS U2650 ( .A(n2444), .B(n2307), .S0(n2348), .Y(n875) );
CLKINVX1TS U2651 ( .A(n2158), .Y(n2159) );
MXI2X1TS U2652 ( .A(n2159), .B(n2444), .S0(n2348), .Y(n876) );
XOR2X1TS U2653 ( .A(n2187), .B(n2161), .Y(n2162) );
CLKMX2X2TS U2654 ( .A(n2162), .B(Raw_mant_NRM_SWR[12]), .S0(n2659), .Y(n541)
);
OAI21X1TS U2655 ( .A0(n2165), .A1(n2164), .B0(n1042), .Y(n2167) );
INVX2TS U2656 ( .A(n2177), .Y(n2178) );
NAND2X1TS U2657 ( .A(n2180), .B(n2181), .Y(n2182) );
NAND2X1TS U2658 ( .A(n2189), .B(n2188), .Y(n2190) );
NAND2X1TS U2659 ( .A(n2194), .B(n2193), .Y(n2196) );
XNOR2X1TS U2660 ( .A(n2196), .B(n2195), .Y(n2197) );
MXI2X1TS U2661 ( .A(n1106), .B(n2198), .S0(n1012), .Y(n525) );
NAND2X1TS U2662 ( .A(n1279), .B(n2199), .Y(n2200) );
INVX2TS U2663 ( .A(n2656), .Y(n2203) );
NOR2X1TS U2664 ( .A(n2208), .B(n2210), .Y(n2213) );
OAI21X1TS U2665 ( .A0(n2211), .A1(n2210), .B0(n2209), .Y(n2212) );
XOR2X4TS U2666 ( .A(n2216), .B(n2215), .Y(n2217) );
INVX2TS U2667 ( .A(n2219), .Y(n2220) );
AOI22X1TS U2668 ( .A0(n2223), .A1(DmP_mant_SHT1_SW[9]), .B0(n2296), .B1(
DmP_mant_SHT1_SW[8]), .Y(n2222) );
NAND2X8TS U2669 ( .A(n2225), .B(n2224), .Y(n2301) );
AOI22X1TS U2670 ( .A0(n2297), .A1(DmP_mant_SHT1_SW[6]), .B0(n2296), .B1(
DmP_mant_SHT1_SW[5]), .Y(n2228) );
AOI22X1TS U2671 ( .A0(n2297), .A1(DmP_mant_SHT1_SW[2]), .B0(n2296), .B1(
DmP_mant_SHT1_SW[1]), .Y(n2230) );
AOI21X1TS U2672 ( .A0(n1153), .A1(n2232), .B0(n2249), .Y(n2766) );
NAND2X1TS U2673 ( .A(n2297), .B(DmP_mant_SHT1_SW[21]), .Y(n2236) );
INVX2TS U2674 ( .A(n2234), .Y(n2235) );
AOI22X1TS U2675 ( .A0(n2249), .A1(DmP_mant_SHT1_SW[3]), .B0(n2239), .B1(
n1153), .Y(n2781) );
NAND2X2TS U2676 ( .A(n2243), .B(n979), .Y(n2762) );
AOI22X1TS U2677 ( .A0(n2249), .A1(DmP_mant_SHT1_SW[2]), .B0(n2240), .B1(
n1153), .Y(n2776) );
AOI22X1TS U2678 ( .A0(n2248), .A1(DmP_mant_SHT1_SW[7]), .B0(n2241), .B1(
n1153), .Y(n2768) );
AOI22X1TS U2679 ( .A0(n2263), .A1(DmP_mant_SHT1_SW[3]), .B0(n2246), .B1(n931), .Y(n2710) );
AOI22X1TS U2680 ( .A0(n2263), .A1(DmP_mant_SHT1_SW[12]), .B0(n2247), .B1(
n1152), .Y(n2735) );
INVX2TS U2681 ( .A(n2250), .Y(n2251) );
AOI22X1TS U2682 ( .A0(n2263), .A1(DmP_mant_SHT1_SW[2]), .B0(n2256), .B1(
n1152), .Y(n2763) );
AOI22X1TS U2683 ( .A0(n2263), .A1(DmP_mant_SHT1_SW[10]), .B0(n2258), .B1(
n1153), .Y(n2755) );
INVX2TS U2684 ( .A(n2259), .Y(n2261) );
MXI2X1TS U2685 ( .A(n2360), .B(n1179), .S0(n2348), .Y(n872) );
NAND2X2TS U2686 ( .A(n2276), .B(n1177), .Y(n2742) );
INVX2TS U2687 ( .A(final_result_ieee[5]), .Y(n2797) );
INVX2TS U2688 ( .A(final_result_ieee[14]), .Y(n2811) );
INVX2TS U2689 ( .A(final_result_ieee[1]), .Y(n2790) );
INVX2TS U2690 ( .A(final_result_ieee[17]), .Y(n2815) );
INVX2TS U2691 ( .A(final_result_ieee[0]), .Y(n2788) );
INVX2TS U2692 ( .A(final_result_ieee[4]), .Y(n2795) );
INVX2TS U2693 ( .A(final_result_ieee[12]), .Y(n2809) );
INVX2TS U2694 ( .A(final_result_ieee[15]), .Y(n2813) );
INVX2TS U2695 ( .A(final_result_ieee[20]), .Y(n2819) );
INVX2TS U2696 ( .A(final_result_ieee[18]), .Y(n2817) );
INVX2TS U2697 ( .A(final_result_ieee[22]), .Y(n2821) );
INVX2TS U2698 ( .A(final_result_ieee[8]), .Y(n2802) );
INVX2TS U2699 ( .A(final_result_ieee[3]), .Y(n2793) );
INVX2TS U2700 ( .A(final_result_ieee[2]), .Y(n2791) );
INVX2TS U2701 ( .A(final_result_ieee[9]), .Y(n2804) );
INVX2TS U2702 ( .A(final_result_ieee[6]), .Y(n2799) );
INVX2TS U2703 ( .A(final_result_ieee[11]), .Y(n2807) );
MXI2X1TS U2704 ( .A(n1232), .B(final_result_ieee[26]), .S0(n2285), .Y(n2277)
);
MXI2X1TS U2705 ( .A(n2278), .B(final_result_ieee[25]), .S0(n2285), .Y(n2279)
);
MXI2X1TS U2706 ( .A(n2280), .B(final_result_ieee[27]), .S0(n2285), .Y(n2281)
);
MXI2X1TS U2707 ( .A(n2283), .B(final_result_ieee[23]), .S0(n2285), .Y(n2284)
);
MXI2X1TS U2708 ( .A(n2286), .B(final_result_ieee[28]), .S0(n2285), .Y(n2287)
);
AO21X4TS U2709 ( .A0(n2292), .A1(n1278), .B0(n2291), .Y(n2294) );
AOI22X1TS U2710 ( .A0(n2297), .A1(DmP_mant_SHT1_SW[22]), .B0(n2296), .B1(
DmP_mant_SHT1_SW[21]), .Y(n2298) );
NAND2X2TS U2711 ( .A(n2300), .B(n2299), .Y(n2704) );
NAND2X2TS U2712 ( .A(n2300), .B(n1177), .Y(n2765) );
NAND2X2TS U2713 ( .A(n2302), .B(n1177), .Y(n2769) );
NAND2X2TS U2714 ( .A(n2303), .B(n1177), .Y(n2780) );
NAND2X2TS U2715 ( .A(n2305), .B(n1177), .Y(n2777) );
CLKMX2X2TS U2716 ( .A(DMP_SHT1_EWSW[11]), .B(DMP_EXP_EWSW[11]), .S0(n2308),
.Y(n693) );
CLKMX2X2TS U2717 ( .A(DMP_SHT1_EWSW[12]), .B(DMP_EXP_EWSW[12]), .S0(n2308),
.Y(n690) );
CLKMX2X2TS U2718 ( .A(DMP_SHT1_EWSW[8]), .B(DMP_EXP_EWSW[8]), .S0(n2308),
.Y(n702) );
CLKMX2X2TS U2719 ( .A(DMP_SHT1_EWSW[5]), .B(DMP_EXP_EWSW[5]), .S0(n2308),
.Y(n711) );
CLKMX2X2TS U2720 ( .A(DMP_SHT1_EWSW[0]), .B(DMP_EXP_EWSW[0]), .S0(n2308),
.Y(n726) );
CLKMX2X2TS U2721 ( .A(DMP_SHT1_EWSW[6]), .B(DMP_EXP_EWSW[6]), .S0(n2308),
.Y(n708) );
CLKMX2X2TS U2722 ( .A(DMP_SHT1_EWSW[7]), .B(n753), .S0(n2308), .Y(n705) );
CLKMX2X2TS U2723 ( .A(DMP_SHT1_EWSW[10]), .B(DMP_EXP_EWSW[10]), .S0(n2308),
.Y(n696) );
CLKMX2X2TS U2724 ( .A(DMP_SHT1_EWSW[9]), .B(n751), .S0(n2308), .Y(n699) );
CLKMX2X2TS U2725 ( .A(DMP_SHT2_EWSW[1]), .B(DMP_SHT1_EWSW[1]), .S0(busy),
.Y(n722) );
CLKMX2X2TS U2726 ( .A(OP_FLAG_SHT2), .B(OP_FLAG_SHT1), .S0(busy), .Y(n557)
);
CLKMX2X2TS U2727 ( .A(DMP_SHT2_EWSW[19]), .B(DMP_SHT1_EWSW[19]), .S0(n2310),
.Y(n668) );
CLKMX2X2TS U2728 ( .A(DMP_SHT2_EWSW[11]), .B(DMP_SHT1_EWSW[11]), .S0(n2310),
.Y(n692) );
CLKMX2X2TS U2729 ( .A(DMP_SHT2_EWSW[0]), .B(DMP_SHT1_EWSW[0]), .S0(n2310),
.Y(n725) );
CLKMX2X2TS U2730 ( .A(DMP_SHT2_EWSW[12]), .B(DMP_SHT1_EWSW[12]), .S0(n2310),
.Y(n689) );
CLKMX2X2TS U2731 ( .A(DMP_SHT2_EWSW[10]), .B(DMP_SHT1_EWSW[10]), .S0(n2310),
.Y(n695) );
CLKMX2X2TS U2732 ( .A(DMP_SHT2_EWSW[9]), .B(DMP_SHT1_EWSW[9]), .S0(n2310),
.Y(n698) );
CLKMX2X2TS U2733 ( .A(DMP_SHT2_EWSW[8]), .B(DMP_SHT1_EWSW[8]), .S0(n2310),
.Y(n701) );
CLKMX2X2TS U2734 ( .A(DMP_SHT2_EWSW[6]), .B(DMP_SHT1_EWSW[6]), .S0(n2310),
.Y(n707) );
CLKMX2X2TS U2735 ( .A(DMP_SHT2_EWSW[7]), .B(DMP_SHT1_EWSW[7]), .S0(n2310),
.Y(n704) );
CLKMX2X2TS U2736 ( .A(DMP_SHT2_EWSW[16]), .B(DMP_SHT1_EWSW[16]), .S0(n2320),
.Y(n677) );
CLKMX2X2TS U2737 ( .A(DMP_SHT2_EWSW[14]), .B(DMP_SHT1_EWSW[14]), .S0(n2320),
.Y(n683) );
CLKMX2X2TS U2738 ( .A(DMP_SHT2_EWSW[17]), .B(DMP_SHT1_EWSW[17]), .S0(n2320),
.Y(n674) );
CLKMX2X2TS U2739 ( .A(DMP_SHT1_EWSW[30]), .B(DMP_EXP_EWSW[30]), .S0(n2318),
.Y(n622) );
CLKMX2X2TS U2740 ( .A(DMP_SHT1_EWSW[18]), .B(DMP_EXP_EWSW[18]), .S0(n2318),
.Y(n672) );
CLKMX2X2TS U2741 ( .A(DMP_SHT1_EWSW[14]), .B(DMP_EXP_EWSW[14]), .S0(n2318),
.Y(n684) );
CLKMX2X2TS U2742 ( .A(DMP_SHT1_EWSW[19]), .B(n741), .S0(n2318), .Y(n669) );
CLKMX2X2TS U2743 ( .A(DMP_SHT1_EWSW[15]), .B(DMP_EXP_EWSW[15]), .S0(n2318),
.Y(n681) );
CLKMX2X2TS U2744 ( .A(DmP_mant_SHT1_SW[9]), .B(DmP_EXP_EWSW[9]), .S0(n2311),
.Y(n598) );
CLKMX2X2TS U2745 ( .A(DmP_mant_SHT1_SW[6]), .B(DmP_EXP_EWSW[6]), .S0(n2311),
.Y(n604) );
CLKMX2X2TS U2746 ( .A(DmP_mant_SHT1_SW[3]), .B(DmP_EXP_EWSW[3]), .S0(n2311),
.Y(n610) );
CLKMX2X2TS U2747 ( .A(DmP_mant_SHT1_SW[19]), .B(DmP_EXP_EWSW[19]), .S0(n2311), .Y(n578) );
XNOR2X1TS U2748 ( .A(n1191), .B(DmP_mant_SFG_SWR[0]), .Y(n2313) );
NOR2X1TS U2749 ( .A(n2450), .B(DmP_EXP_EWSW[23]), .Y(n2314) );
NOR2X1TS U2750 ( .A(n2315), .B(n2314), .Y(n2316) );
MXI2X1TS U2751 ( .A(n2384), .B(n2489), .S0(n2317), .Y(n676) );
MXI2X1TS U2752 ( .A(n2383), .B(n2488), .S0(n2317), .Y(n670) );
MXI2X1TS U2753 ( .A(n2371), .B(n2502), .S0(n2319), .Y(n697) );
MXI2X1TS U2754 ( .A(n2372), .B(n2503), .S0(n2319), .Y(n700) );
MXI2X1TS U2755 ( .A(n2453), .B(n2376), .S0(n2318), .Y(n647) );
MXI2X1TS U2756 ( .A(n2375), .B(n2438), .S0(n2319), .Y(n709) );
MXI2X1TS U2757 ( .A(n2366), .B(n2435), .S0(n2319), .Y(n724) );
MXI2X1TS U2758 ( .A(n2369), .B(n2437), .S0(n2319), .Y(n691) );
MXI2X1TS U2759 ( .A(n2370), .B(n2436), .S0(n2319), .Y(n694) );
MXI2X1TS U2760 ( .A(n2368), .B(n2500), .S0(n2319), .Y(n688) );
MXI2X1TS U2761 ( .A(n2367), .B(n2501), .S0(n2319), .Y(n685) );
MXI2X1TS U2762 ( .A(n2322), .B(n2453), .S0(n2320), .Y(n646) );
CLKMX2X2TS U2763 ( .A(DMP_SHT2_EWSW[21]), .B(DMP_SHT1_EWSW[21]), .S0(n2323),
.Y(n662) );
CLKMX2X2TS U2764 ( .A(DMP_SHT2_EWSW[20]), .B(DMP_SHT1_EWSW[20]), .S0(n2323),
.Y(n665) );
CLKMX2X2TS U2765 ( .A(DMP_SHT2_EWSW[3]), .B(DMP_SHT1_EWSW[3]), .S0(n2323),
.Y(n716) );
CLKMX2X2TS U2766 ( .A(DMP_SHT2_EWSW[2]), .B(DMP_SHT1_EWSW[2]), .S0(n2323),
.Y(n719) );
CLKMX2X2TS U2767 ( .A(DMP_SHT2_EWSW[18]), .B(DMP_SHT1_EWSW[18]), .S0(n2323),
.Y(n671) );
CLKMX2X2TS U2768 ( .A(DMP_SHT2_EWSW[22]), .B(DMP_SHT1_EWSW[22]), .S0(n2323),
.Y(n659) );
CLKMX2X2TS U2769 ( .A(DMP_SHT2_EWSW[5]), .B(DMP_SHT1_EWSW[5]), .S0(n2323),
.Y(n710) );
CLKMX2X2TS U2770 ( .A(DMP_SHT2_EWSW[15]), .B(DMP_SHT1_EWSW[15]), .S0(n2323),
.Y(n680) );
CLKMX2X2TS U2771 ( .A(DMP_SHT2_EWSW[4]), .B(DMP_SHT1_EWSW[4]), .S0(n2323),
.Y(n713) );
CLKMX2X2TS U2772 ( .A(DMP_SHT1_EWSW[26]), .B(DMP_EXP_EWSW[26]), .S0(
Shift_reg_FLAGS_7_5), .Y(n642) );
CLKMX2X2TS U2773 ( .A(DMP_SHT1_EWSW[27]), .B(DMP_EXP_EWSW[27]), .S0(
Shift_reg_FLAGS_7_5), .Y(n637) );
CLKMX2X2TS U2774 ( .A(DMP_SHT1_EWSW[1]), .B(DMP_EXP_EWSW[1]), .S0(
Shift_reg_FLAGS_7_5), .Y(n723) );
CLKMX2X2TS U2775 ( .A(OP_FLAG_SHT1), .B(OP_FLAG_EXP), .S0(
Shift_reg_FLAGS_7_5), .Y(n558) );
CLKMX2X2TS U2776 ( .A(DMP_SHT1_EWSW[28]), .B(DMP_EXP_EWSW[28]), .S0(
Shift_reg_FLAGS_7_5), .Y(n632) );
CLKMX2X2TS U2777 ( .A(DMP_SHT1_EWSW[23]), .B(DMP_EXP_EWSW[23]), .S0(
Shift_reg_FLAGS_7_5), .Y(n657) );
CLKMX2X2TS U2778 ( .A(DMP_SHT1_EWSW[24]), .B(DMP_EXP_EWSW[24]), .S0(
Shift_reg_FLAGS_7_5), .Y(n652) );
CLKMX2X2TS U2779 ( .A(DMP_SHT1_EWSW[29]), .B(DMP_EXP_EWSW[29]), .S0(
Shift_reg_FLAGS_7_5), .Y(n627) );
INVX4TS U2780 ( .A(n2451), .Y(n2326) );
CLKMX2X2TS U2781 ( .A(DMP_SHT1_EWSW[2]), .B(DMP_EXP_EWSW[2]), .S0(n2326),
.Y(n720) );
INVX4TS U2782 ( .A(n2451), .Y(n2327) );
CLKMX2X2TS U2783 ( .A(DMP_SHT1_EWSW[21]), .B(DMP_EXP_EWSW[21]), .S0(n2327),
.Y(n663) );
CLKMX2X2TS U2784 ( .A(DMP_SHT1_EWSW[22]), .B(DMP_EXP_EWSW[22]), .S0(n2327),
.Y(n660) );
CLKMX2X2TS U2785 ( .A(ZERO_FLAG_SHT1), .B(ZERO_FLAG_EXP), .S0(n2326), .Y(
n564) );
CLKMX2X2TS U2786 ( .A(DMP_SHT1_EWSW[20]), .B(DMP_EXP_EWSW[20]), .S0(n2327),
.Y(n666) );
CLKMX2X2TS U2787 ( .A(DMP_SHT1_EWSW[3]), .B(n757), .S0(n2326), .Y(n717) );
CLKMX2X2TS U2788 ( .A(DMP_SHT1_EWSW[4]), .B(DMP_EXP_EWSW[4]), .S0(n2326),
.Y(n714) );
CLKMX2X2TS U2789 ( .A(DmP_mant_SHT1_SW[17]), .B(DmP_EXP_EWSW[17]), .S0(n2326), .Y(n582) );
CLKMX2X2TS U2790 ( .A(DmP_mant_SHT1_SW[0]), .B(DmP_EXP_EWSW[0]), .S0(n2327),
.Y(n616) );
CLKMX2X2TS U2791 ( .A(DmP_mant_SHT1_SW[18]), .B(DmP_EXP_EWSW[18]), .S0(n2326), .Y(n580) );
CLKMX2X2TS U2792 ( .A(DmP_mant_SHT1_SW[14]), .B(DmP_EXP_EWSW[14]), .S0(n2327), .Y(n588) );
CLKMX2X2TS U2793 ( .A(DmP_mant_SHT1_SW[12]), .B(n593), .S0(n2327), .Y(n592)
);
CLKMX2X2TS U2794 ( .A(DmP_mant_SHT1_SW[13]), .B(DmP_EXP_EWSW[13]), .S0(n2327), .Y(n590) );
CLKMX2X2TS U2795 ( .A(DmP_mant_SHT1_SW[1]), .B(DmP_EXP_EWSW[1]), .S0(n2327),
.Y(n614) );
CLKMX2X2TS U2796 ( .A(DmP_mant_SHT1_SW[15]), .B(DmP_EXP_EWSW[15]), .S0(n2326), .Y(n586) );
CLKMX2X2TS U2797 ( .A(DmP_mant_SHT1_SW[2]), .B(DmP_EXP_EWSW[2]), .S0(n2327),
.Y(n612) );
CLKMX2X2TS U2798 ( .A(DmP_mant_SHT1_SW[11]), .B(DmP_EXP_EWSW[11]), .S0(n2327), .Y(n594) );
INVX2TS U2799 ( .A(n2328), .Y(n2330) );
INVX2TS U2800 ( .A(n2333), .Y(n2335) );
NAND2X1TS U2801 ( .A(n2335), .B(n2334), .Y(n2336) );
XOR2X4TS U2802 ( .A(n2337), .B(n2336), .Y(n2338) );
CLKMX2X2TS U2803 ( .A(Data_Y[0]), .B(intDY_EWSW[0]), .S0(n2339), .Y(n835) );
CLKMX2X2TS U2804 ( .A(Data_Y[30]), .B(intDY_EWSW[30]), .S0(n2344), .Y(n805)
);
CLKMX2X2TS U2805 ( .A(Data_Y[5]), .B(n1089), .S0(n2340), .Y(n830) );
CLKMX2X2TS U2806 ( .A(Data_Y[9]), .B(intDY_EWSW[9]), .S0(n2340), .Y(n826) );
CLKMX2X2TS U2807 ( .A(Data_Y[26]), .B(intDY_EWSW[26]), .S0(n2343), .Y(n809)
);
CLKMX2X2TS U2808 ( .A(Data_Y[27]), .B(intDY_EWSW[27]), .S0(n2343), .Y(n808)
);
CLKMX2X2TS U2809 ( .A(Data_X[3]), .B(n1140), .S0(n2345), .Y(n866) );
CLKMX2X2TS U2810 ( .A(Data_X[25]), .B(n1109), .S0(n2344), .Y(n844) );
MXI2X1TS U2811 ( .A(n2659), .B(n1012), .S0(n2348), .Y(n871) );
MXI2X1TS U2812 ( .A(n2307), .B(n2506), .S0(n2348), .Y(n874) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk1.tcl_ETAIIN16Q8_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DFF_NSR_BLACKBOX_V
`define SKY130_FD_SC_HD__UDP_DFF_NSR_BLACKBOX_V
/**
* udp_dff$NSR: Negative edge triggered D flip-flop (Q output UDP)
* with both active high reset and set (set dominate).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_dff$NSR (
Q ,
SET ,
RESET,
CLK_N,
D
);
output Q ;
input SET ;
input RESET;
input CLK_N;
input D ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DFF_NSR_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4BB_TB_V
`define SKY130_FD_SC_LP__AND4BB_TB_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and4bb.v"
module top();
// Inputs are registered
reg A_N;
reg B_N;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B_N = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B_N = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B_N = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B_N = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B_N = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B_N = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_lp__and4bb dut (.A_N(A_N), .B_N(B_N), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4BB_TB_V
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_buf.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_0_ecc_buf
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
rd_merge_data,
// Inputs
clk, rst, rd_data_addr, rd_data_offset, wr_data_addr,
wr_data_offset, rd_data, wr_ecc_buf
);
input clk;
input rst;
// RMW architecture supports only 16 data buffer entries.
// Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but
// assume the upper bits are used for tagging.
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire [4:0] buf_wr_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
reg [4:0] buf_rd_addr_r;
generate
if (DATA_BUF_ADDR_WIDTH >= 4) begin : ge_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{wr_data_addr[3:0], wr_data_offset};
assign buf_wr_addr = {rd_data_addr[3:0], rd_data_offset};
end
else begin : lt_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{{4-DATA_BUF_ADDR_WIDTH{1'b0}},
wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
wr_data_offset};
assign buf_wr_addr = {{4-DATA_BUF_ADDR_WIDTH{1'b0}},
rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
rd_data_offset};
end
endgenerate
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] payload;
integer h;
always @(/*AS*/rd_data)
for (h=0; h<2*nCK_PER_CLK; h=h+1)
payload[h*DATA_WIDTH+:DATA_WIDTH] =
rd_data[h*PAYLOAD_WIDTH+:DATA_WIDTH];
input wr_ecc_buf;
localparam BUF_WIDTH = 2*nCK_PER_CLK*DATA_WIDTH;
localparam FULL_RAM_CNT = (BUF_WIDTH/6);
localparam REMAINDER = BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] buf_out_data;
generate
begin : ram_buf
wire [RAM_WIDTH-1:0] buf_in_data;
if (REMAINDER == 0)
assign buf_in_data = payload;
else
assign buf_in_data = {{6-REMAINDER{1'b0}}, payload};
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(buf_out_data[((i*6)+4)+:2]),
.DOB(buf_out_data[((i*6)+2)+:2]),
.DOC(buf_out_data[((i*6)+0)+:2]),
.DOD(),
.DIA(buf_in_data[((i*6)+4)+:2]),
.DIB(buf_in_data[((i*6)+2)+:2]),
.DIC(buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(buf_rd_addr_r),
.ADDRB(buf_rd_addr_r),
.ADDRC(buf_rd_addr_r),
.ADDRD(buf_wr_addr),
.WE(wr_ecc_buf),
.WCLK(clk)
);
end // block: rd_buffer_ram
end
endgenerate
output wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
assign rd_merge_data = buf_out_data[2*nCK_PER_CLK*DATA_WIDTH-1:0];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND2B_BEHAVIORAL_V
`define SKY130_FD_SC_MS__NAND2B_BEHAVIORAL_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nand2b (
Y ,
A_N,
B
);
// Module ports
output Y ;
input A_N;
input B ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire or0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y, not0_out, A_N );
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND2B_BEHAVIORAL_V |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_frame_out_p,
dac_frame_out_n,
dac_data_out_p,
dac_data_out_n,
adc_clk_in_p,
adc_clk_in_n,
adc_or_in_p,
adc_or_in_n,
adc_data_in_p,
adc_data_in_n,
ref_clk_out_p,
ref_clk_out_n,
iic_scl,
iic_sda);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [14:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output dac_frame_out_p;
output dac_frame_out_n;
output [15:0] dac_data_out_p;
output [15:0] dac_data_out_n;
input adc_clk_in_p;
input adc_clk_in_n;
input adc_or_in_p;
input adc_or_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
output ref_clk_out_p;
output ref_clk_out_n;
inout iic_scl;
inout iic_sda;
// internal registers
reg [63:0] dac_ddata_0 = 'd0;
reg [63:0] dac_ddata_1 = 'd0;
reg dac_dma_rd = 'd0;
reg adc_data_cnt = 'd0;
reg adc_dma_wr = 'd0;
reg [31:0] adc_dma_wdata = 'd0;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 2:0] spi0_csn;
wire spi0_clk;
wire spi0_mosi;
wire spi0_miso;
wire [ 2:0] spi1_csn;
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
wire dac_clk;
wire dac_valid_0;
wire dac_enable_0;
wire dac_valid_1;
wire dac_enable_1;
wire [63:0] dac_dma_rdata;
wire adc_clk;
wire adc_valid_0;
wire adc_enable_0;
wire [15:0] adc_data_0;
wire adc_valid_1;
wire adc_enable_1;
wire [15:0] adc_data_1;
wire ref_clk;
wire oddr_ref_clk;
// instantiations
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
i_oddr_ref_clk (
.S (1'b0),
.CE (1'b1),
.R (1'b0),
.C (ref_clk),
.D1 (1'b1),
.D2 (1'b0),
.Q (oddr_ref_clk));
OBUFDS i_obufds_ref_clk (
.I (oddr_ref_clk),
.O (ref_clk_out_p),
.OB (ref_clk_out_n));
ad_iobuf #(
.DATA_WIDTH(15))
i_gpio_bd (
.dio_t(gpio_t[14:0]),
.dio_i(gpio_o[14:0]),
.dio_o(gpio_i[14:0]),
.dio_p(gpio_bd));
always @(posedge dac_clk) begin
dac_dma_rd <= dac_valid_0 & dac_enable_0;
dac_ddata_1[63:48] <= dac_dma_rdata[63:48];
dac_ddata_1[47:32] <= dac_dma_rdata[63:48];
dac_ddata_1[31:16] <= dac_dma_rdata[31:16];
dac_ddata_1[15: 0] <= dac_dma_rdata[31:16];
dac_ddata_0[63:48] <= dac_dma_rdata[47:32];
dac_ddata_0[47:32] <= dac_dma_rdata[47:32];
dac_ddata_0[31:16] <= dac_dma_rdata[15: 0];
dac_ddata_0[15: 0] <= dac_dma_rdata[15: 0];
end
always @(posedge adc_clk) begin
adc_data_cnt <= ~adc_data_cnt ;
case ({adc_enable_1, adc_enable_0})
2'b10: begin
adc_dma_wr <= adc_data_cnt;
adc_dma_wdata <= {adc_data_1, adc_dma_wdata[31:16]};
end
2'b01: begin
adc_dma_wr <= adc_data_cnt;
adc_dma_wdata <= {adc_data_0, adc_dma_wdata[31:16]};
end
default: begin
adc_dma_wr <= 1'b1;
adc_dma_wdata <= {adc_data_1, adc_data_0};
end
endcase
end
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.adc_clk (adc_clk),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_data_0 (adc_data_0),
.adc_data_1 (adc_data_1),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_dma_wdata (adc_dma_wdata),
.adc_dma_wr (adc_dma_wr),
.adc_enable_0 (adc_enable_0),
.adc_enable_1 (adc_enable_1),
.adc_or_in_n (adc_or_in_n),
.adc_or_in_p (adc_or_in_p),
.adc_valid_0 (adc_valid_0),
.adc_valid_1 (adc_valid_1),
.dac_clk (dac_clk),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_data_out_n (dac_data_out_n),
.dac_data_out_p (dac_data_out_p),
.dac_ddata_0 (dac_ddata_0),
.dac_ddata_1 (dac_ddata_1),
.dac_dma_rd (dac_dma_rd),
.dac_dma_rdata (dac_dma_rdata),
.dac_enable_0 (dac_enable_0),
.dac_enable_1 (dac_enable_1),
.dac_frame_out_n (dac_frame_out_n),
.dac_frame_out_p (dac_frame_out_p),
.dac_valid_0 (dac_valid_0),
.dac_valid_1 (dac_valid_1),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.ref_clk (ref_clk),
.spdif (spdif),
.spi0_clk_i (spi0_clk),
.spi0_clk_o (spi0_clk),
.spi0_csn_0_o (spi0_csn[0]),
.spi0_csn_1_o (spi0_csn[1]),
.spi0_csn_2_o (spi0_csn[2]),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi0_miso),
.spi0_sdo_i (spi0_mosi),
.spi0_sdo_o (spi0_mosi),
.spi1_clk_i (spi1_clk),
.spi1_clk_o (spi1_clk),
.spi1_csn_0_o (spi1_csn[0]),
.spi1_csn_1_o (spi1_csn[1]),
.spi1_csn_2_o (spi1_csn[2]),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b1),
.spi1_sdo_i (spi1_mosi),
.spi1_sdo_o (spi1_mosi));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_t
//
// Generated
// by: wig
// on: Tue Jul 4 08:52:39 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_t.v,v 1.2 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: ent_t.v,v $
// Revision 1.2 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_t
//
// No user `defines in this module
module ent_t
//
// Generated Module inst_t
//
(
sig_i_a,
sig_i_a2,
sig_i_ae,
sig_o_a,
sig_o_a2,
sig_o_ae
);
// Generated Module Inputs:
input sig_i_a;
input sig_i_a2;
input [6:0] sig_i_ae;
// Generated Module Outputs:
output sig_o_a;
output sig_o_a2;
output [7:0] sig_o_ae;
// Generated Wires:
wire sig_i_a;
wire sig_i_a2;
wire [6:0] sig_i_ae;
wire sig_o_a;
wire sig_o_a2;
wire [7:0] sig_o_ae;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire sig_01;
wire sig_03;
wire sig_04;
wire [3:0] sig_05;
wire [3:0] sig_06;
wire [5:0] sig_07;
wire [8:2] sig_08;
// __I_OUT_OPEN wire [4:0] sig_13; // __W_BAD_BRANCH
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
`ifdef exclude_inst_a
// assign sig_04 = open;
// assign sig_06 = open;
// assign sig_07 = open;
// assign sig_i_a = open;
// assign sig_i_a2 = open;
// assign sig_i_ae = open;
assign sig_01 = 1'b0;
assign sig_03 = 1'b0;
assign sig_05 = 1'b0;
assign sig_08 = 7'b1111111;
assign sig_13 = 5'b00000;
assign sig_o_a = 1'b0;
assign sig_o_a2 = 1'b0;
assign sig_o_ae = 8'b00000000;
`else
// Generated Instance Port Map for inst_a
ent_a inst_a (
.p_mix_sig_01_go(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.p_mix_sig_03_go(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.p_mix_sig_04_gi(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.p_mix_sig_05_2_1_go(sig_05[2:1]), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.p_mix_sig_06_gi(sig_06), // Conflicting definition (X2)
.p_mix_sig_i_ae_gi(sig_i_ae), // Input Bus
.p_mix_sig_o_ae_go(sig_o_ae), // Output Bus
.port_i_a(sig_i_a), // Input Port
.port_o_a(sig_o_a), // Output Port
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_13(), // Create internal signal name
.sig_i_a2(sig_i_a2), // Input Port
.sig_o_a2(sig_o_a2) // Output Port
);
// End of Generated Instance Port Map for inst_a
`endif
`ifdef exclude_inst_b
// assign sig_01 = open;
// assign sig_03 = open;
// assign sig_05 = open;
// assign sig_06 = open;
// assign sig_07 = open;
// assign sig_08 = open;
assign sig_04 = 1'b0;
assign sig_06 = 4'b0000;
`else
// Generated Instance Port Map for inst_b
ent_b inst_b (
.port_b_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_b_3(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.port_b_4(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.port_b_5_1(sig_05[2]), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_b_5_2(sig_05[1]), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_b_6i(sig_06), // Conflicting definition (X2)
.port_b_6o(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08) // VHDL intermediate needed (port name)
);
// End of Generated Instance Port Map for inst_b
`endif
endmodule
//
// End of Generated Module rtl of ent_t
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21AI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O21AI_PP_SYMBOL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o21ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21AI_PP_SYMBOL_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIEBus_pipe_reset.v
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : pipe_reset.v
// Description : PIPE Reset Module for 7 Series Transceiver
// Version : 20.2
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Reset Module -------------------------------------------------
module PCIEBus_pipe_reset #
(
//---------- Global ------------------------------------
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
parameter PCIE_GT_DEVICE = "GTX",
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable
parameter PCIE_LANE = 1, // PCIe number of lanes
//---------- Local -------------------------------------
parameter CFG_WAIT_MAX = 6'd63, // Configuration wait max
parameter BYPASS_RXCDRLOCK = 1 // Bypass RXCDRLOCK
)
(
//---------- Input -------------------------------------
input RST_CLK,
input RST_RXUSRCLK,
input RST_DCLK,
input RST_RST_N,
input [PCIE_LANE-1:0] RST_DRP_DONE,
input [PCIE_LANE-1:0] RST_RXPMARESETDONE,
input [PCIE_LANE-1:0] RST_CPLLLOCK,
input RST_QPLL_IDLE,
input [PCIE_LANE-1:0] RST_RATE_IDLE,
input [PCIE_LANE-1:0] RST_RXCDRLOCK,
input RST_MMCM_LOCK,
input [PCIE_LANE-1:0] RST_RESETDONE,
input [PCIE_LANE-1:0] RST_PHYSTATUS,
input [PCIE_LANE-1:0] RST_TXSYNC_DONE,
//---------- Output ------------------------------------
output RST_CPLLRESET,
output RST_CPLLPD,
output reg RST_DRP_START,
output reg RST_DRP_X16X20_MODE,
output reg RST_DRP_X16,
output RST_RXUSRCLK_RESET,
output RST_DCLK_RESET,
output RST_GTRESET,
output RST_USERRDY,
output RST_TXSYNC_START,
output RST_IDLE,
output [4:0] RST_FSM
);
//---------- Input Register ----------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qpll_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qpll_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg2;
//---------- Internal Signal ---------------------------
reg [ 5:0] cfg_wait_cnt = 6'd0;
//---------- Output Register ---------------------------
reg cpllreset = 1'd0;
reg cpllpd = 1'd0;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxusrclk_rst_reg1 = 1'd0;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxusrclk_rst_reg2 = 1'd0;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg dclk_rst_reg1 = 1'd0;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg dclk_rst_reg2 = 1'd0;
reg gtreset = 1'd0;
reg userrdy = 1'd0;
reg [4:0] fsm = 5'h2;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 5'h0;
localparam FSM_CFG_WAIT = 5'h1;
localparam FSM_CPLLRESET = 5'h2;
localparam FSM_DRP_X16_START = 5'h3;
localparam FSM_DRP_X16_DONE = 5'h4;
localparam FSM_CPLLLOCK = 5'h5;
localparam FSM_DRP = 5'h6;
localparam FSM_GTRESET = 5'h7;
localparam FSM_RXPMARESETDONE_1 = 5'h8;
localparam FSM_RXPMARESETDONE_2 = 5'h9;
localparam FSM_DRP_X20_START = 5'hA;
localparam FSM_DRP_X20_DONE = 5'hB;
localparam FSM_MMCM_LOCK = 5'hC;
localparam FSM_RESETDONE = 5'hD;
localparam FSM_CPLL_PD = 5'hE;
localparam FSM_TXSYNC_START = 5'hF;
localparam FSM_TXSYNC_DONE = 5'h10;
//---------- Input FF ----------------------------------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
begin
//---------- 1st Stage FF --------------------------
drp_done_reg1 <= {PCIE_LANE{1'd0}};
rxpmaresetdone_reg1 <= {PCIE_LANE{1'd0}};
cplllock_reg1 <= {PCIE_LANE{1'd0}};
qpll_idle_reg1 <= 1'd0;
rate_idle_reg1 <= {PCIE_LANE{1'd0}};
rxcdrlock_reg1 <= {PCIE_LANE{1'd0}};
mmcm_lock_reg1 <= 1'd0;
resetdone_reg1 <= {PCIE_LANE{1'd0}};
phystatus_reg1 <= {PCIE_LANE{1'd0}};
txsync_done_reg1 <= {PCIE_LANE{1'd0}};
//---------- 2nd Stage FF --------------------------
drp_done_reg2 <= {PCIE_LANE{1'd0}};
rxpmaresetdone_reg2 <= {PCIE_LANE{1'd0}};
cplllock_reg2 <= {PCIE_LANE{1'd0}};
qpll_idle_reg2 <= 1'd0;
rate_idle_reg2 <= {PCIE_LANE{1'd0}};
rxcdrlock_reg2 <= {PCIE_LANE{1'd0}};
mmcm_lock_reg2 <= 1'd0;
resetdone_reg2 <= {PCIE_LANE{1'd0}};
phystatus_reg2 <= {PCIE_LANE{1'd0}};
txsync_done_reg2 <= {PCIE_LANE{1'd0}};
end
else
begin
//---------- 1st Stage FF --------------------------
drp_done_reg1 <= RST_DRP_DONE;
rxpmaresetdone_reg1 <= RST_RXPMARESETDONE;
cplllock_reg1 <= RST_CPLLLOCK;
qpll_idle_reg1 <= RST_QPLL_IDLE;
rate_idle_reg1 <= RST_RATE_IDLE;
rxcdrlock_reg1 <= RST_RXCDRLOCK;
mmcm_lock_reg1 <= RST_MMCM_LOCK;
resetdone_reg1 <= RST_RESETDONE;
phystatus_reg1 <= RST_PHYSTATUS;
txsync_done_reg1 <= RST_TXSYNC_DONE;
//---------- 2nd Stage FF --------------------------
drp_done_reg2 <= drp_done_reg1;
rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
cplllock_reg2 <= cplllock_reg1;
qpll_idle_reg2 <= qpll_idle_reg1;
rate_idle_reg2 <= rate_idle_reg1;
rxcdrlock_reg2 <= rxcdrlock_reg1;
mmcm_lock_reg2 <= mmcm_lock_reg1;
resetdone_reg2 <= resetdone_reg1;
phystatus_reg2 <= phystatus_reg1;
txsync_done_reg2 <= txsync_done_reg1;
end
end
//---------- Configuration Reset Wait Counter ----------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
cfg_wait_cnt <= 6'd0;
else
//---------- Increment Configuration Reset Wait Counter
if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt < CFG_WAIT_MAX))
cfg_wait_cnt <= cfg_wait_cnt + 6'd1;
//---------- Hold Configuration Reset Wait Counter -
else if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt == CFG_WAIT_MAX))
cfg_wait_cnt <= cfg_wait_cnt;
//---------- Reset Configuration Reset Wait Counter
else
cfg_wait_cnt <= 6'd0;
end
//---------- PIPE Reset FSM ----------------------------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
begin
fsm <= FSM_CFG_WAIT;
cpllreset <= 1'd0;
cpllpd <= 1'd0;
gtreset <= 1'd0;
userrdy <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
if (!RST_RST_N)
begin
fsm <= FSM_CFG_WAIT;
cpllreset <= 1'd0;
cpllpd <= 1'd0;
gtreset <= 1'd0;
userrdy <= 1'd0;
end
else
begin
fsm <= FSM_IDLE;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
end
//---------- Wait for Configuration Reset Delay ---
FSM_CFG_WAIT :
begin
fsm <= ((cfg_wait_cnt == CFG_WAIT_MAX) ? FSM_CPLLRESET : FSM_CFG_WAIT);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Hold CPLL and GTX Channel in Reset ----
FSM_CPLLRESET :
begin
fsm <= ((&(~cplllock_reg2) && (&(~resetdone_reg2))) ? FSM_CPLLLOCK : FSM_CPLLRESET);
cpllreset <= 1'd1;
cpllpd <= cpllpd;
gtreset <= 1'd1;
userrdy <= userrdy;
end
//---------- Wait for CPLL Lock --------------------
FSM_CPLLLOCK :
begin
fsm <= (&cplllock_reg2 ? FSM_DRP : FSM_CPLLLOCK);
cpllreset <= 1'd0;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for DRP Done to Setup Gen1 -------
FSM_DRP :
begin
fsm <= (&rate_idle_reg2 ? ((PCIE_GT_DEVICE == "GTX") ? FSM_GTRESET : FSM_DRP_X16_START) : FSM_DRP);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Start DRP x16 -------------------------
FSM_DRP_X16_START :
begin
fsm <= &(~drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for DRP x16 Done -----------------
FSM_DRP_X16_DONE :
begin
fsm <= (&drp_done_reg2) ? FSM_GTRESET : FSM_DRP_X16_DONE;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Release GTX Channel Reset -------------
FSM_GTRESET :
begin
fsm <= (PCIE_GT_DEVICE == "GTX") ? FSM_MMCM_LOCK : FSM_RXPMARESETDONE_1;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= 1'b0;
userrdy <= userrdy;
end
//---------- Wait for RXPMARESETDONE Assertion -----
FSM_RXPMARESETDONE_1 :
begin
fsm <= (&rxpmaresetdone_reg2 || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_RXPMARESETDONE_2 : FSM_RXPMARESETDONE_1;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for RXPMARESETDONE De-assertion --
FSM_RXPMARESETDONE_2 :
begin
fsm <= (&(~rxpmaresetdone_reg2) || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE_2;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Start DRP x20 -------------------------
FSM_DRP_X20_START :
begin
fsm <= &(~drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for DRP x20 Done -----------------
FSM_DRP_X20_DONE :
begin
fsm <= (&drp_done_reg2) ? FSM_MMCM_LOCK : FSM_DRP_X20_DONE;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for MMCM and RX CDR Lock ---------
FSM_MMCM_LOCK :
begin
if (mmcm_lock_reg2 && (&rxcdrlock_reg2 || (BYPASS_RXCDRLOCK == 1)) && (qpll_idle_reg2 || (PCIE_PLL_SEL == "CPLL")))
begin
fsm <= FSM_RESETDONE;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= 1'd1;
end
else
begin
fsm <= FSM_MMCM_LOCK;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= 1'd0;
end
end
//---------- Wait for [TX/RX]RESETDONE and PHYSTATUS
FSM_RESETDONE :
begin
fsm <= (&resetdone_reg2 && (&(~phystatus_reg2)) ? FSM_CPLL_PD : FSM_RESETDONE);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Power-Down CPLL if QPLL is Used for Gen1/Gen2
FSM_CPLL_PD :
begin
fsm <= ((PCIE_TXBUF_EN == "TRUE") ? FSM_IDLE : FSM_TXSYNC_START);
cpllreset <= cpllreset;
cpllpd <= (PCIE_PLL_SEL == "QPLL");
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Start TX Sync -------------------------
FSM_TXSYNC_START :
begin
fsm <= (&(~txsync_done_reg2) ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for TX Sync Done -----------------
FSM_TXSYNC_DONE :
begin
fsm <= (&txsync_done_reg2 ? FSM_IDLE : FSM_TXSYNC_DONE);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_CFG_WAIT;
cpllreset <= 1'd0;
cpllpd <= 1'd0;
gtreset <= 1'd0;
userrdy <= 1'd0;
end
endcase
end
end
//---------- RXUSRCLK Reset Synchronizer ---------------------------------------
always @ (posedge RST_RXUSRCLK)
begin
if (cpllreset)
begin
rxusrclk_rst_reg1 <= 1'd1;
rxusrclk_rst_reg2 <= 1'd1;
end
else
begin
rxusrclk_rst_reg1 <= 1'd0;
rxusrclk_rst_reg2 <= rxusrclk_rst_reg1;
end
end
//---------- DCLK Reset Synchronizer -------------------------------------------
always @ (posedge RST_DCLK)
begin
if (fsm == FSM_CFG_WAIT)
begin
dclk_rst_reg1 <= 1'd1;
dclk_rst_reg2 <= dclk_rst_reg1;
end
else
begin
dclk_rst_reg1 <= 1'd0;
dclk_rst_reg2 <= dclk_rst_reg1;
end
end
//---------- PIPE Reset Output -------------------------------------------------
assign RST_CPLLRESET = cpllreset;
assign RST_CPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllpd);
assign RST_RXUSRCLK_RESET = rxusrclk_rst_reg2;
assign RST_DCLK_RESET = dclk_rst_reg2;
assign RST_GTRESET = gtreset;
assign RST_USERRDY = userrdy;
assign RST_TXSYNC_START = (fsm == FSM_TXSYNC_START);
assign RST_IDLE = (fsm == FSM_IDLE);
assign RST_FSM = fsm;
//--------------------------------------------------------------------------------------------------
// Register Output
//--------------------------------------------------------------------------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
begin
RST_DRP_START <= 1'd0;
RST_DRP_X16X20_MODE <= 1'd0;
RST_DRP_X16 <= 1'd0;
end
else
begin
RST_DRP_START <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START);
RST_DRP_X16X20_MODE <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE) || (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE);
RST_DRP_X16 <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
end
end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bg_mid (
clka,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [14 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [11 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [11 : 0] douta;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("bg_mid.mif"),
.C_INIT_FILE("bg_mid.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_READ_WIDTH_A(12),
.C_WRITE_DEPTH_A(18560),
.C_READ_DEPTH_A(18560),
.C_ADDRA_WIDTH(15),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(12),
.C_READ_WIDTH_B(12),
.C_WRITE_DEPTH_B(18560),
.C_READ_DEPTH_B(18560),
.C_ADDRB_WIDTH(15),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("5"),
.C_COUNT_18K_BRAM("5"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 7.0707579999999997 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(15'B0),
.dinb(12'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(12'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4B_2_V
`define SKY130_FD_SC_HDLL__OR4B_2_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog wrapper for or4b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or4b_2 (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or4b_2 (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4B_2_V
|
module t(
input clk_sys,
input _0_t,
input taa,
input tab,
input trb,
input clockta,
input clocktb,
input clocktc,
input t_1_d,
input [0:39] k,
input m_1,
output reg [-1:39] t
);
always @ (posedge clk_sys, posedge _0_t) begin
if (_0_t) t[0:15] <= 0;
else if (clockta) case ({~tab, ~taa})
2'b00: t[0:15] <= t[0:15];
2'b01: t[0:15] <= t[-1:14];
2'b10: t[0:15] <= t[1:16];
2'b11: t[0:15] <= k[0:15];
endcase
end
always @ (posedge clk_sys, posedge _0_t) begin
if (_0_t) t[16:31] <= 0;
else if (clocktb) case ({~trb, ~taa})
2'b00: t[16:31] <= t[16:31];
2'b01: t[16:31] <= t[15:30];
2'b10: t[16:31] <= t[17:32];
2'b11: t[16:31] <= k[16:31];
endcase
end
always @ (posedge clk_sys, posedge _0_t) begin
if (_0_t) t[32:39] <= 0;
else if (clocktc) case ({~trb, ~taa})
2'b00: t[32:39] <= t[32:39];
2'b01: t[32:39] <= t[31:38];
2'b10: t[32:39] <= {t[33:39], m_1};
2'b11: t[32:39] <= k[32:39];
endcase
end
always @ (posedge clk_sys, posedge _0_t) begin
if (_0_t) t[-1] <= 1'b0;
else if (clockta) t[-1] <= t_1_d;
end
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRBP_2_V
`define SKY130_FD_SC_LP__SDFRBP_2_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfrbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfrbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfrbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRBP_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_16_V
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_16_V
/**
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
*
* Verilog wrapper for lpflow_clkinvkapwr with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_clkinvkapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_clkinvkapwr_16 (
Y ,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
output Y ;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_clkinvkapwr base (
.Y(Y),
.A(A),
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_clkinvkapwr_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_clkinvkapwr base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_16_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22A_4_V
`define SKY130_FD_SC_LS__O22A_4_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o22a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o22a_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o22a_4 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22A_4_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`ifdef USE_VPI_NOT_DPI
//We call it via $c so we can verify DPI isn't required - see bug572
`else
import "DPI-C" context function integer mon_check();
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
`ifdef VERILATOR
`systemc_header
extern "C" int mon_check();
`verilog
`endif
input clk;
reg onebit /*verilator public_flat_rw @(posedge clk) */;
reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */;
reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */;
reg [61:0] quads[3:2] /*verilator public_flat_rw @(posedge clk) */;
reg [31:0] count /*verilator public_flat_rd */;
reg [31:0] half_count /*verilator public_flat_rd */;
reg [7:0] text_byte /*verilator public_flat_rw @(posedge clk) */;
reg [15:0] text_half /*verilator public_flat_rw @(posedge clk) */;
reg [31:0] text_word /*verilator public_flat_rw @(posedge clk) */;
reg [63:0] text_long /*verilator public_flat_rw @(posedge clk) */;
reg [511:0] text /*verilator public_flat_rw @(posedge clk) */;
integer status;
sub sub();
// Test loop
initial begin
count = 0;
onebit = 1'b0;
fourthreetwoone[3] = 0; // stop icarus optimizing away
text_byte = "B";
text_half = "Hf";
text_word = "Word";
text_long = "Long64b";
text = "Verilog Test module";
`ifdef VERILATOR
status = $c32("mon_check()");
`endif
`ifdef iverilog
status = $mon_check();
`endif
`ifndef USE_VPI_NOT_DPI
status = mon_check();
`endif
if (status!=0) begin
$write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status);
$stop;
end
$write("%%Info: Checking results\n");
if (onebit != 1'b1) $stop;
if (quads[2] != 62'h12819213_abd31a1c) $stop;
if (quads[3] != 62'h1c77bb9b_3784ea09) $stop;
if (text_byte != "A") $stop;
if (text_half != "T2") $stop;
if (text_word != "Tree") $stop;
if (text_long != "44Four44") $stop;
if (text != "lorem ipsum") $stop;
end
always @(posedge clk) begin
count <= count + 2;
if (count[1])
half_count <= half_count + 2;
if (count == 1000) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
genvar i;
generate
for (i=1; i<=128; i=i+1) begin : arr
arr #(.LENGTH(i)) arr();
end endgenerate
endmodule : t
module sub;
reg subsig1 /*verilator public_flat_rd*/;
reg subsig2 /*verilator public_flat_rd*/;
`ifdef iverilog
// stop icarus optimizing signals away
wire redundant = subsig1 | subsig2;
`endif
endmodule : sub
module arr;
parameter LENGTH = 1;
reg [LENGTH-1:0] sig /*verilator public_flat_rw*/;
reg [LENGTH-1:0] rfr /*verilator public_flat_rw*/;
reg check /*verilator public_flat_rw*/;
reg verbose /*verilator public_flat_rw*/;
initial begin
sig = {LENGTH{1'b0}};
rfr = {LENGTH{1'b0}};
end
always @(posedge check) begin
if (verbose) $display("%m : %x %x", sig, rfr);
if (check && sig != rfr) $stop;
check <= 0;
end
endmodule : arr
|
`timescale 1ns/1ns
//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner ([email protected])
//
// Copyright (c) 2004 Guy Hutchison ([email protected])
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
module tv80s (/*AUTOARG*/
// Outputs
m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout,
// Inputs
reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di
);
parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
parameter T2Write = 1; // 0 => wr_n active in T3, /=0 => wr_n active in T2
parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
input reset_n;
input clk;
input wait_n;
input int_n;
input nmi_n;
input busrq_n;
output m1_n;
output mreq_n;
output iorq_n;
output rd_n;
output wr_n;
output rfsh_n;
output halt_n;
output busak_n;
output [15:0] A;
input [7:0] di;
output [7:0] dout;
reg mreq_n;
reg iorq_n;
reg rd_n;
reg wr_n;
wire cen;
wire intcycle_n;
wire no_read;
wire write;
wire iorq;
reg [7:0] di_reg;
wire [6:0] mcycle;
wire [6:0] tstate;
assign cen = 1;
tv80_core #(Mode, IOWait) i_tv80_core
(
.cen (cen),
.m1_n (m1_n),
.iorq (iorq),
.no_read (no_read),
.write (write),
.rfsh_n (rfsh_n),
.halt_n (halt_n),
.wait_n (wait_n),
.int_n (int_n),
.nmi_n (nmi_n),
.reset_n (reset_n),
.busrq_n (busrq_n),
.busak_n (busak_n),
.clk (clk),
.IntE (),
.stop (),
.A (A),
.dinst (di),
.di (di_reg),
.dout (dout),
.mc (mcycle),
.ts (tstate),
.intcycle_n (intcycle_n)
);
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
rd_n <= #1 1'b1;
wr_n <= #1 1'b1;
iorq_n <= #1 1'b1;
mreq_n <= #1 1'b1;
di_reg <= #1 0;
end
else
begin
rd_n <= #1 1'b1;
wr_n <= #1 1'b1;
iorq_n <= #1 1'b1;
mreq_n <= #1 1'b1;
if (mcycle[0])
begin
if (tstate[1] || (tstate[2] && wait_n == 1'b0))
begin
rd_n <= #1 ~ intcycle_n;
mreq_n <= #1 ~ intcycle_n;
iorq_n <= #1 intcycle_n;
end
`ifdef TV80_REFRESH
if (tstate[3])
mreq_n <= #1 1'b0;
`endif
end // if (mcycle[0])
else
begin
if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && no_read == 1'b0 && write == 1'b0)
begin
rd_n <= #1 1'b0;
iorq_n <= #1 ~ iorq;
mreq_n <= #1 iorq;
end
if (T2Write == 0)
begin
if (tstate[2] && write == 1'b1)
begin
wr_n <= #1 1'b0;
iorq_n <= #1 ~ iorq;
mreq_n <= #1 iorq;
end
end
else
begin
if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && write == 1'b1)
begin
wr_n <= #1 1'b0;
iorq_n <= #1 ~ iorq;
mreq_n <= #1 iorq;
end
end // else: !if(T2write == 0)
end // else: !if(mcycle[0])
if (tstate[2] && wait_n == 1'b1)
di_reg <= #1 di;
end // else: !if(!reset_n)
end // always @ (posedge clk or negedge reset_n)
endmodule // t80s
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DLATCH_P_SYMBOL_V
`define SKY130_FD_SC_MS__UDP_DLATCH_P_SYMBOL_V
/**
* udp_dlatch$P: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_dlatch$P (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DLATCH_P_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Christian P. Feist
//
// Create Date: 20:31:12 10/06/2016
// Design Name: /
// Module Name: axi_trivium_v1_0_S00_AXI
// Project Name: Trivium
// Target Devices: Spartan-6, Zynq
// Tool versions: ISE 14.7, Vivado v2016.2
// Description: The top module of the Trivium IP core. Its interface is designed
// such that it can connected as an AXI4LITE slave.
// The module contains several registers that may be read or written to,
// a full list is given below.
// Register map (All values are interpreted as little-endian):
// +0: Control register (RW)
// -0.0: UNUSED | ... | UNUSED | Process (RWS) | Stop (RWS)| Init (RWS)
// -0.1: UNUSED | ... | UNUSED | Output valid (R) | Init done (R) | Busy (R)
// -0.2: UNUSED | ... | UNUSED
// -0.3: UNUSED | ... | UNUSED
// +1 to 3: Key register (Least significant bytes at bottom of 1, RW)
// +4 to 6: IV register (Least significant bytes at bottom of 4, RW)
// +7: Input data register (RW)
// +8: Output data register (R)
//
// Notation: R(Read), W(Write), S(Self clearing, will read as zero)
//
// Dependencies: /
//
// Revision:
// Revision 0.01 - File Created
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 1 ps
module axi_trivium_v1_0_S00_AXI #
(
/* Width of S_AXI data bus */
parameter integer C_S_AXI_DATA_WIDTH = 32,
/* Width of S_AXI address bus */
parameter integer C_S_AXI_ADDR_WIDTH = 6
)
(
/* Global Clock Signal */
input wire S_AXI_ACLK,
/* Global Reset Signal. This Signal is Active LOW */
input wire S_AXI_ARESETN,
/* Write address (issued by master, acceped by Slave) */
input wire [C_S_AXI_ADDR_WIDTH - 1:0] S_AXI_AWADDR,
/*
* Write channel Protection type. This signal indicates the
* privilege and security level of the transaction, and whether
* the transaction is a data access or an instruction access.
*/
input wire [2:0] S_AXI_AWPROT,
/*
* Write address valid. This signal indicates that the master signaling
* valid write address and control information.
*/
input wire S_AXI_AWVALID,
/*
* Write address ready. This signal indicates that the slave is ready
* to accept an address and associated control signals.
*/
output wire S_AXI_AWREADY,
/* Write data (issued by master, acceped by Slave) */
input wire [C_S_AXI_DATA_WIDTH - 1:0] S_AXI_WDATA,
/*
* Write strobes. This signal indicates which byte lanes hold
* valid data. There is one write strobe bit for each eight
* bits of the write data bus.
*/
input wire [(C_S_AXI_DATA_WIDTH/8) - 1:0] S_AXI_WSTRB,
/*
* Write valid. This signal indicates that valid write
* data and strobes are available.
*/
input wire S_AXI_WVALID,
/*
* Write ready. This signal indicates that the slave
* can accept the write data.
*/
output wire S_AXI_WREADY,
/*
* Write response. This signal indicates the status
* of the write transaction.
*/
output wire [1:0] S_AXI_BRESP,
/*
* Write response valid. This signal indicates that the channel
* is signaling a valid write response.
*/
output wire S_AXI_BVALID,
/*
* Response ready. This signal indicates that the master
* can accept a write response.
*/
input wire S_AXI_BREADY,
/* Read address (issued by master, acceped by Slave) */
input wire [C_S_AXI_ADDR_WIDTH - 1:0] S_AXI_ARADDR,
/*
* Protection type. This signal indicates the privilege
* and security level of the transaction, and whether the
* transaction is a data access or an instruction access.
*/
input wire [2:0] S_AXI_ARPROT,
/*
* Read address valid. This signal indicates that the channel
* is signaling valid read address and control information.
*/
input wire S_AXI_ARVALID,
/*
* Read address ready. This signal indicates that the slave is
* ready to accept an address and associated control signals.
*/
output wire S_AXI_ARREADY,
/* Read data (issued by slave) */
output wire [C_S_AXI_DATA_WIDTH - 1:0] S_AXI_RDATA,
/*
* Read response. This signal indicates the status of the
* read transfer.
*/
output wire [1:0] S_AXI_RRESP,
/*
* Read valid. This signal indicates that the channel is
* signaling the required read data.
*/
output wire S_AXI_RVALID,
/*
* Read ready. This signal indicates that the master can
* accept the read data and response information.
*/
input wire S_AXI_RREADY
);
//////////////////////////////////////////////////////////////////////////////////
// AXI4LITE signals
//////////////////////////////////////////////////////////////////////////////////
reg [C_S_AXI_ADDR_WIDTH - 1:0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1:0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH - 1:0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH - 1:0] axi_rdata;
reg [1:0] axi_rresp;
reg axi_rvalid;
//////////////////////////////////////////////////////////////////////////////////
// Register space related signals and parameters
//////////////////////////////////////////////////////////////////////////////////
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 3;
reg [C_S_AXI_DATA_WIDTH - 1:0] reg_conf_r; /* Configuration register */
reg [C_S_AXI_DATA_WIDTH - 1:0] reg_key_lo_r; /* Key register LO */
reg [C_S_AXI_DATA_WIDTH - 1:0] reg_key_mid_r; /* Key register MID */
reg [C_S_AXI_DATA_WIDTH - 1:0] reg_key_hi_r; /* Key register HI */
reg [C_S_AXI_DATA_WIDTH - 1:0] reg_iv_lo_r; /* IV register LO */
reg [C_S_AXI_DATA_WIDTH - 1:0] reg_iv_mid_r; /* IV register MID */
reg [C_S_AXI_DATA_WIDTH - 1:0] reg_iv_hi_r; /* IV register HI */
reg [C_S_AXI_DATA_WIDTH - 1:0] reg_idat_r; /* Input data register */
wire [C_S_AXI_DATA_WIDTH - 1:0] reg_odat_s; /* Output data register */
reg [C_S_AXI_DATA_WIDTH - 1:0] ld_dat_r; /* Data loaded into register a or b */
reg [2:0] ld_sel_a_r; /* Register a slice selection */
reg [2:0] ld_sel_b_r; /* Register b slice selection */
reg init_r; /* Init cipher */
reg stop_r; /* Stop any calculations and reset the core */
reg proc_r; /* Start processing */
reg gen_output_r; /* Register stating whether output is being computed */
wire busy_s; /* Flag indicating whether core is busy */
reg init_active_r; /* Flag indicating whether init process is active */
reg init_done_r; /* Flag indicating whether init process is done */
wire slv_reg_rden_r; /* Signal that triggers the output of data */
wire slv_reg_wren_r; /* Signal that triggers the capture of input data */
reg [C_S_AXI_DATA_WIDTH - 1:0] reg_data_out; /* Data being read from registers */
integer byte_index; /* Iteration index used for byte access of registers */
//////////////////////////////////////////////////////////////////////////////////
// I/O Connection Assignments
//////////////////////////////////////////////////////////////////////////////////
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
//////////////////////////////////////////////////////////////////////////////////
// Module instantiations
//////////////////////////////////////////////////////////////////////////////////
trivium_top trivium(
.clk_i(S_AXI_ACLK),
.n_rst_i(S_AXI_ARESETN & ~stop_r),
.dat_i(reg_idat_r),
.ld_dat_i(ld_dat_r),
.ld_reg_a_i(ld_sel_a_r),
.ld_reg_b_i(ld_sel_b_r),
.init_i(init_r),
.proc_i(proc_r),
.dat_o(reg_odat_s),
.busy_o(busy_s)
);
/*
* Implement axi_awready generation
* axi_awready is asserted for one S_AXI_ACLK clock cycle when both
* S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
* de-asserted when reset is low.
*/
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESETN == 1'b0)
axi_awready <= 1'b0;
else begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID) begin
/*
* Slave is ready to accept write address when
* there is a valid write address and write data
* on the write address and data bus. This design
* expects no outstanding transactions.
*/
axi_awready <= 1'b1;
end
else
axi_awready <= 1'b0;
end
end
/*
* Implement axi_awaddr latching
* This process is used to latch the address when both
* S_AXI_AWVALID and S_AXI_WVALID are valid.
*/
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESETN == 1'b0)
axi_awaddr <= 0;
else begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID) begin
/* Write Address latching */
axi_awaddr <= S_AXI_AWADDR;
end
end
end
/*
* Implement axi_wready generation
* axi_wready is asserted for one S_AXI_ACLK clock cycle when both
* S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
* de-asserted when reset is low.
*/
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESETN == 1'b0)
axi_wready <= 1'b0;
else begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID) begin
/*
* Slave is ready to accept write data when
* there is a valid write address and write data
* on the write address and data bus. This design
* expects no outstanding transactions.
*/
axi_wready <= 1'b1;
end
else
axi_wready <= 1'b0;
end
end
/*
* Implement memory mapped register select and write logic generation
* The write data is accepted and written to memory mapped registers when
* axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
* select byte enables of slave registers while writing.
* These registers are cleared when reset (active low) is applied.
* Slave register write enable is asserted when valid address and data are available
* and the slave is ready to accept the write address and write data.
*/
assign slv_reg_wren_r = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESETN == 1'b0) begin
/* Reset addressable registers driven here */
reg_conf_r <= 0;
reg_key_lo_r <= 0;
reg_key_mid_r <= 0;
reg_key_hi_r <= 0;
reg_iv_lo_r <= 0;
reg_iv_mid_r <= 0;
reg_iv_hi_r <= 0;
reg_idat_r <= 0;
/* Reset any other registers driven here */
init_r <= 0;
stop_r <= 0;
proc_r <= 0;
gen_output_r <= 0;
ld_dat_r <= 0;
ld_sel_a_r <= 0;
ld_sel_b_r <= 0;
end
else begin
if (slv_reg_wren_r) begin
case (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB])
4'h0: /* Configuration register */
/* Currently only byte 0 of configuration register is writable */
if (S_AXI_WSTRB[0] == 1'b1) begin
if (S_AXI_WDATA[1] == 1'b1) begin /* Bit 1 resets core in any case */
stop_r <= 1'b1;
gen_output_r <= 0;
end
else if (S_AXI_WDATA[0] == 1'b1 & !busy_s) begin /* Bit 0 triggers init if core is not busy */
init_r <= 1'b1;
gen_output_r <= 0;
end
else if (S_AXI_WDATA[2] == 1'b1 & !busy_s) begin /* Bit 2 triggers processing if core is not busy */
proc_r <= 1'b1;
gen_output_r <= 1'b1;
end
end
4'h1: begin /* LO key register */
/* Reconstruct key LO value written so far */
ld_dat_r <= reg_key_lo_r;
ld_sel_a_r[0] <= 1'b1;
for (byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1) begin
/* Incorporate the rest that is currently being written */
if (S_AXI_WSTRB[byte_index] == 1) begin
ld_dat_r[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
reg_key_lo_r[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
end
end
4'h2: begin /* MID key register */
/* Reconstruct key MID value written so far */
ld_dat_r <= reg_key_mid_r;
ld_sel_a_r[1] <= 1'b1;
for (byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1) begin
/* Incorporate the rest that is currently being written */
if (S_AXI_WSTRB[byte_index] == 1) begin
ld_dat_r[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
reg_key_mid_r[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
end
end
4'h3: begin /* HI key register */
/* Reconstruct key HI value written so far */
ld_dat_r <= reg_key_hi_r;
ld_sel_a_r[2] <= 1'b1;
for (byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1) begin
/* Incorporate the rest that is currently being written */
if (S_AXI_WSTRB[byte_index] == 1) begin
ld_dat_r[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
reg_key_hi_r[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
end
end
4'h4: begin /* LO IV register */
/* Reconstruct IV LO value written so far */
ld_dat_r <= reg_iv_lo_r;
ld_sel_b_r[0] <= 1'b1;
for (byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1) begin
/* Incorporate the rest that is currently being written */
if (S_AXI_WSTRB[byte_index] == 1) begin
ld_dat_r[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
reg_iv_lo_r[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
end
end
4'h5:begin /* MID IV register */
/* Reconstruct IV MID value written so far */
ld_dat_r <= reg_iv_mid_r;
ld_sel_b_r[1] <= 1'b1;
for (byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1) begin
/* Incorporate the rest that is currently being written */
if (S_AXI_WSTRB[byte_index] == 1) begin
ld_dat_r[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
reg_iv_mid_r[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
end
end
4'h6:begin /* LO IV register */
/* Reconstruct IV HI value written so far */
ld_dat_r <= reg_iv_hi_r;
ld_sel_b_r[2] <= 1'b1;
for (byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1) begin
/* Incorporate the rest that is currently being written */
if (S_AXI_WSTRB[byte_index] == 1) begin
ld_dat_r[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
reg_iv_hi_r[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
end
end
4'h7: /* Input data register */
/* Respective byte enables are asserted as per write strobes */
for (byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1)
if (S_AXI_WSTRB[byte_index] == 1) begin
reg_idat_r[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
default: begin
reg_conf_r <= reg_conf_r;
reg_key_lo_r <= reg_key_lo_r;
reg_key_mid_r <= reg_key_mid_r;
reg_key_hi_r <= reg_key_hi_r;
reg_iv_lo_r <= reg_iv_lo_r;
reg_iv_mid_r <= reg_iv_mid_r;
reg_iv_hi_r <= reg_iv_hi_r;
reg_idat_r <= reg_idat_r;
end
endcase
end
else begin
/* Reset all strobes/pulses that resulted from a register write */
init_r <= 0;
stop_r <= 0;
proc_r <= 0;
ld_sel_a_r <= 0;
ld_sel_b_r <= 0;
end
end
end
/*
* Implement write response logic generation
* The write response and response valid signals are asserted by the slave
* when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
* This marks the acceptance of address and indicates the status of
* write transaction.
*/
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESETN == 1'b0) begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID) begin
/* Indicates a valid write response is available */
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; /* 'OKAY' response */
end /* work error responses in future */
else begin
if (S_AXI_BREADY && axi_bvalid) begin
/* Check if bready is asserted while bvalid is high) */
/* (there is a possibility that bready is always asserted high) */
axi_bvalid <= 1'b0;
end
end
end
end
/*
* Implement axi_arready generation
* axi_arready is asserted for one S_AXI_ACLK clock cycle when
* S_AXI_ARVALID is asserted. axi_awready is
* de-asserted when reset (active low) is asserted.
* The read address is also latched when S_AXI_ARVALID is
* asserted. axi_araddr is reset to zero on reset assertion.
*/
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESETN == 1'b0) begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else begin
if (~axi_arready && S_AXI_ARVALID) begin
/* Indicates that the slave has acceped the valid read address */
axi_arready <= 1'b1;
/* Read address latching */
axi_araddr <= S_AXI_ARADDR;
end
else
axi_arready <= 1'b0;
end
end
/*
* Implement axi_arvalid generation
* axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
* S_AXI_ARVALID and axi_arready are asserted. The slave registers
* data are available on the axi_rdata bus at this instance. The
* assertion of axi_rvalid marks the validity of read data on the
* bus and axi_rresp indicates the status of read transaction.axi_rvalid
* is deasserted on reset (active low). axi_rresp and axi_rdata are
* cleared to zero on reset (active low).
*/
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESETN == 1'b0) begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid) begin
/* Valid read data is available at the read data bus */
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; /* 'OKAY' response */
end
else if (axi_rvalid && S_AXI_RREADY) begin
/* Read data is accepted by the master */
axi_rvalid <= 1'b0;
end
end
end
/*
* Implement memory mapped register select and read logic generation
* Slave register read enable is asserted when valid address is available
* and the slave is ready to accept the read address.
*/
assign slv_reg_rden_r = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*) begin
/* Address decoding for reading registers */
case (axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB])
4'h0: reg_data_out <= {16'h0000, 5'b00000, gen_output_r & ~busy_s, init_done_r, busy_s, 8'h00};
4'h1: reg_data_out <= reg_key_lo_r;
4'h2: reg_data_out <= reg_key_mid_r;
4'h3: reg_data_out <= reg_key_hi_r;
4'h4: reg_data_out <= reg_iv_lo_r;
4'h5: reg_data_out <= reg_iv_mid_r;
4'h6: reg_data_out <= reg_iv_hi_r;
4'h7: reg_data_out <= reg_idat_r;
4'h8: reg_data_out <= reg_odat_s;
default: reg_data_out <= 0;
endcase
end
/* Output register or memory read data */
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESETN == 1'b0)
axi_rdata <= 0;
else begin
/*
* When there is a valid read address (S_AXI_ARVALID) with
* acceptance of read address by the slave (axi_arready),
* output the read dada
*/
if (slv_reg_rden_r)
axi_rdata <= reg_data_out; /* Register read data */
end
end
/*
* This process monitors the initialization process of
* the core.
*/
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESETN == 1'b0 || stop_r == 1'b1) begin
init_active_r <= 0;
init_done_r <= 0;
end
else begin
if (init_r == 1'b1 && init_done_r == 1'b0 && busy_s == 1'b0)
init_active_r <= 1'b1;
else if (init_active_r == 1'b1 && busy_s == 1'b0)
init_done_r <= 1'b1;
end
end
endmodule
|
module master(
input wire [6:0] address,
input wire [7:0] register,
input wire refresh_clk,
input wire sys_clk,
input wire mode,
input wire en,
input wire reset,
input wire Start,
input wire Stop,
input wire repeat_start,
output reg [7:0] out,
output reg ack,
inout wire sda,
inout wire scl
);
reg [3:0] state;
reg [4:0] counter;
wire sda_in, scl_in;
reg sda_enable, sda_out, scl_enable, scl_out, clk_enable, sda_output, sda_en;
assign sda = ( sda_en ) ? (sda_output) ? 1'bz : 1'b0 : 1'bz;
assign sda_in = sda;
assign scl = ( scl_enable ) ? ( clk_enable ) ? (sys_clk) ? 1'bz : 1'b0 : scl_out : 1'bZ;
assign scl_in = scl;
always@(posedge refresh_clk)
begin
sda_en <= sda_enable;
sda_output <= sda_out;
end
always@(posedge sys_clk or negedge reset)
begin
if( ~reset )
begin
state <= 0;
sda_enable <= 0;
sda_out <= 0;
scl_enable <= 0;
clk_enable <= 0;
scl_out <= 0;
out <= 0;
counter <= 0;
ack <= 1'b0;
end
else
begin
case( state )
0:
begin
if((( Start || repeat_start ) ) && ( en ))
begin
state <= 1;
sda_enable <= 1'b1;
sda_out <= 1'b0;
scl_enable <= 1'b0;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b0;
end
else
begin
state <= 0;
sda_enable <= 1'b0;
sda_out <= 1'b0;
scl_enable <= 1'b0;
clk_enable <= 1'b0;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b0;
end
end
1:
begin
if(counter < 7)
begin
state <= 1;
sda_enable <= 1'b1;
sda_out <= address[6-counter];
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= counter + 1;
ack <= 1'b0;
end
else
begin
state <= 2;
sda_enable <= 1'b1;
sda_out <= mode;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b0;
end
end
2:
begin
state <= 3;
sda_enable <= 1'b0;
sda_out <= 0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b1;
end
3:
begin
if( ~sda_in )
begin
if( mode )
begin
state <= 4;
sda_enable <= 1'b0;
sda_out <= 0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b0;
end
else
begin
state <= 5;
sda_enable <= 1'b1;
sda_out <= register[7 - counter];
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b0;
end
end
else
begin
state <= 7;
sda_enable <= 1'b1;
sda_out <= 0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b1;
out <= out;
counter <= 0;
ack <= 1'b0;
end
end
4:
begin
if(counter < 7)
begin
state <= 4;
sda_enable <= 1'b0;
sda_out <= 1'b0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out[7-counter] <= sda_in;
counter <= counter + 1;
ack <= 1'b0;
end
else
begin
if( Stop )
begin
state <= 7;
sda_enable <= 1'b1;
sda_out <= 1'b1;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out[7-counter] <= sda_in;
counter <= 0;
ack <= 1'b1;
end
else
begin
state <= 8;
sda_enable <= 1'b1;
sda_out <= 1'b0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out[7-counter] <= sda_in;
counter <= 0;
ack <= 1'b1;
end
end
end
5:
begin
if(counter < 8)
begin
state <= 5;
sda_enable <= 1'b1;
sda_out <= register[7 - counter];
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= counter + 1;
ack <= 1'b0;
end
else
begin
state <= 6;
sda_enable <= 1'b0;
sda_out <= 1'b0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b1;
end
end
6:
begin
if(( Stop ) || ( sda_in ))
begin
state <= 7;
sda_enable <= 1'b1;
sda_out <= 0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b0;
end
else if( repeat_start )
begin
state <= 0;
sda_enable <= 1'b1;
sda_out <= 1;
scl_enable <= 1'b1;
clk_enable <= 1'b0;
scl_out <= 1'b1;
out <= out;
counter <= 0;
ack <= 1'b0;
end
else
begin
state <= 5;
sda_enable <= 1'b1;
sda_out <= register[7 - counter];
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= counter + 1;
ack <= 1'b0;
end
end
7:
begin
state <= 9;
sda_enable <= 1'b1;
sda_out <= 0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b0;
end
8:
begin
if( repeat_start )
begin
state <= 0;
sda_enable <= 1'b1;
sda_out <= 1;
scl_enable <= 1'b1;
clk_enable <= 1'b0;
scl_out <= 1'b1;
out <= out;
counter <= 0;
ack <= 1'b0;
end
else
begin
state <= 4;
sda_enable <= 1'b0;
sda_out <= 0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b0;
end
end
9:
begin
state <= 15;
sda_enable <= 1'b1;
sda_out <= 0;
scl_enable <= 1'b1;
clk_enable <= 1'b0;
scl_out <= 1'b1;
out <= out;
counter <= 0;
ack <= 1'b0;
end
15:
begin
state <= 15;
sda_enable <= 1'b0;
sda_out <= 0;
scl_enable <= 1'b0;
clk_enable <= 1'b0;
scl_out <= 1'b1;
out <= out;
counter <= 0;
ack <= 1'b0;
end
endcase
end
end
endmodule
|
// FP16 Regular/Relaxed version.
// TODO: Implement overflow/underflow.
module FP16RMulS0Of2(
input clk,
input rst,
input [15:0] arg_0,
input [15:0] arg_1,
output ret_0,
output [4:0] ret_1,
output [4:0] ret_2,
output [11:0] ret_3);
wire s0;
wire s1;
wire [4:0] e0;
wire [4:0] e1;
wire [9:0] f0;
wire [9:0] f1;
wire [10:0] ff0;
wire [10:0] ff1;
wire [21:0] z;
wire [11:0] zz;
assign s0 = arg_0[15:15];
assign s1 = arg_1[15:15];
assign e0 = arg_0[14:10];
assign e1 = arg_1[14:10];
assign f0 = arg_0[9:0];
assign f1 = arg_1[9:0];
// sign
assign ret_0 = s0 ^ s1;
// exponent
assign ret_1 = e0;
assign ret_2 = e1;
assign ff0 = {(e0 == 0 ? 1'b0 : 1'b1), f0};
assign ff1 = {(e1 == 0 ? 1'b0 : 1'b1), f1};
assign z = ff0 * ff1;
assign zz = z[21:10];
// fraction
assign ret_3 = zz;
endmodule // FP16RMulS0Of2
module FP16RMulS1Of2(
input clk,
input rst,
input arg_0,
input [4:0] arg_1,
input [4:0] arg_2,
input [11:0] arg_3,
output [15:0] ret_0);
wire s;
wire c;
wire [9:0] fc;
wire [9:0] uc;
wire [6:0] e7;
wire [4:0] e;
wire underflow;
wire overflow;
wire infinput;
assign s = arg_0;
assign c = arg_3[11:11];
assign e7 = arg_1 + arg_2 - 15 + c;
assign fc = c ? arg_3[10:1] : arg_3[9:0];
assign infinput = (arg_1 == 31) || (arg_2 == 31);
// e7[6:6] negative by subtraction.
// e7[5:5] overflow (> 31) by addition.
assign underflow = e7[6:6];
assign overflow = !underflow && (e7[5:5] || e7[4:0] == 31 || infinput);
assign e = underflow ? 0 : (overflow ? 31 : e7[4:0]);
assign uc = (underflow || e7[4:0] == 0) ? 0 : fc;
assign ret_0 = {s, e, uc};
endmodule // FP16RMulS1Of2
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Sun Sep 22 02:34:40 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// d:/github/Digital-Hardware-Modelling/xilinx-vivado/hls_tutorial_lab1/hls_tutorial_lab1.srcs/sources_1/bd/zybo_zynq_design/ip/zybo_zynq_design_hls_macc_0_0/zybo_zynq_design_hls_macc_0_0_stub.v
// Design : zybo_zynq_design_hls_macc_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "hls_macc,Vivado 2018.2" *)
module zybo_zynq_design_hls_macc_0_0(s_axi_HLS_MACC_PERIPH_BUS_AWADDR,
s_axi_HLS_MACC_PERIPH_BUS_AWVALID, s_axi_HLS_MACC_PERIPH_BUS_AWREADY,
s_axi_HLS_MACC_PERIPH_BUS_WDATA, s_axi_HLS_MACC_PERIPH_BUS_WSTRB,
s_axi_HLS_MACC_PERIPH_BUS_WVALID, s_axi_HLS_MACC_PERIPH_BUS_WREADY,
s_axi_HLS_MACC_PERIPH_BUS_BRESP, s_axi_HLS_MACC_PERIPH_BUS_BVALID,
s_axi_HLS_MACC_PERIPH_BUS_BREADY, s_axi_HLS_MACC_PERIPH_BUS_ARADDR,
s_axi_HLS_MACC_PERIPH_BUS_ARVALID, s_axi_HLS_MACC_PERIPH_BUS_ARREADY,
s_axi_HLS_MACC_PERIPH_BUS_RDATA, s_axi_HLS_MACC_PERIPH_BUS_RRESP,
s_axi_HLS_MACC_PERIPH_BUS_RVALID, s_axi_HLS_MACC_PERIPH_BUS_RREADY, ap_clk, ap_rst_n,
interrupt)
/* synthesis syn_black_box black_box_pad_pin="s_axi_HLS_MACC_PERIPH_BUS_AWADDR[5:0],s_axi_HLS_MACC_PERIPH_BUS_AWVALID,s_axi_HLS_MACC_PERIPH_BUS_AWREADY,s_axi_HLS_MACC_PERIPH_BUS_WDATA[31:0],s_axi_HLS_MACC_PERIPH_BUS_WSTRB[3:0],s_axi_HLS_MACC_PERIPH_BUS_WVALID,s_axi_HLS_MACC_PERIPH_BUS_WREADY,s_axi_HLS_MACC_PERIPH_BUS_BRESP[1:0],s_axi_HLS_MACC_PERIPH_BUS_BVALID,s_axi_HLS_MACC_PERIPH_BUS_BREADY,s_axi_HLS_MACC_PERIPH_BUS_ARADDR[5:0],s_axi_HLS_MACC_PERIPH_BUS_ARVALID,s_axi_HLS_MACC_PERIPH_BUS_ARREADY,s_axi_HLS_MACC_PERIPH_BUS_RDATA[31:0],s_axi_HLS_MACC_PERIPH_BUS_RRESP[1:0],s_axi_HLS_MACC_PERIPH_BUS_RVALID,s_axi_HLS_MACC_PERIPH_BUS_RREADY,ap_clk,ap_rst_n,interrupt" */;
input [5:0]s_axi_HLS_MACC_PERIPH_BUS_AWADDR;
input s_axi_HLS_MACC_PERIPH_BUS_AWVALID;
output s_axi_HLS_MACC_PERIPH_BUS_AWREADY;
input [31:0]s_axi_HLS_MACC_PERIPH_BUS_WDATA;
input [3:0]s_axi_HLS_MACC_PERIPH_BUS_WSTRB;
input s_axi_HLS_MACC_PERIPH_BUS_WVALID;
output s_axi_HLS_MACC_PERIPH_BUS_WREADY;
output [1:0]s_axi_HLS_MACC_PERIPH_BUS_BRESP;
output s_axi_HLS_MACC_PERIPH_BUS_BVALID;
input s_axi_HLS_MACC_PERIPH_BUS_BREADY;
input [5:0]s_axi_HLS_MACC_PERIPH_BUS_ARADDR;
input s_axi_HLS_MACC_PERIPH_BUS_ARVALID;
output s_axi_HLS_MACC_PERIPH_BUS_ARREADY;
output [31:0]s_axi_HLS_MACC_PERIPH_BUS_RDATA;
output [1:0]s_axi_HLS_MACC_PERIPH_BUS_RRESP;
output s_axi_HLS_MACC_PERIPH_BUS_RVALID;
input s_axi_HLS_MACC_PERIPH_BUS_RREADY;
input ap_clk;
input ap_rst_n;
output interrupt;
endmodule
|
`include "constants.vh"
module pLayer(state_in, state_out, clk, rst, out_rdy, en);
input clk;
input rst;
input [263:0] state_in;
input en;
output reg [263:0] state_out;
output reg out_rdy;
wire [7:0] out_comb;
reg [7:0] permute [0:32];
reg [263:0] state_comb;
reg [7:0] x, y;
reg [31:0] j, PermutedBitNo;
wire [8:0] pi_out_field [8:0][32:0];
reg [31:0] idx;
integer k;
initial begin
for (k=0; k<`nSBox; k=k+1)
permute[k] = 0;
end
genvar itr_i, itr_j;
generate begin
for (itr_i = 0; itr_i<`nSBox; itr_i=itr_i+1) begin : Pi_i
for (itr_j = 0; itr_j<8; itr_j=itr_j+1) begin : Pi_j
Pi_mod pi(.in ((itr_i<<3)+itr_j), .out (pi_out_field[itr_j][itr_i]), .clk (clk), .rst (rst));
end
end
end endgenerate
always @ (posedge clk or posedge rst) begin
if (rst) begin
state_out = 0;
state_comb = 0;
idx = 0;
out_rdy = 0;
for (k=0; k<`nSBox; k=k+1)
permute[k] = 0;
end else if(en) begin
for (j=0; j<8; j=j+1) begin
x = (state_in[(idx*8)+:8]>>j) & 8'b00000001;
PermutedBitNo = pi_out_field[j][idx];
y = PermutedBitNo>>3;
permute[y] = permute[y] ^ (x << (PermutedBitNo - 8*y));
state_comb = state_comb | permute[y] << (y*8);
end
if (idx==32) begin
state_out = state_comb;
out_rdy = 1'b1;
end else begin
out_rdy = 1'b0;
end
idx = idx + 1;
end
end
endmodule
|
/**
* bsg_cache_to_test_dram_tx.v
*
*/
`include "bsg_defines.v"
module bsg_cache_to_test_dram_tx
#(parameter `BSG_INV_PARAM(num_cache_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter `BSG_INV_PARAM(dma_data_width_p)
, parameter `BSG_INV_PARAM(dram_data_width_p)
, parameter num_req_lp = (block_size_in_words_p*data_width_p/dram_data_width_p)
, parameter lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p)
)
(
input core_clk_i
, input core_reset_i
, input v_i
, input [lg_num_cache_lp-1:0] tag_i
, output logic ready_o
, input [num_cache_p-1:0][dma_data_width_p-1:0] dma_data_i
, input [num_cache_p-1:0] dma_data_v_i
, output logic [num_cache_p-1:0] dma_data_yumi_o
, input dram_clk_i
, input dram_reset_i
, output logic dram_data_v_o
, output logic [dram_data_width_p-1:0] dram_data_o
, input dram_data_yumi_i
);
// tag fifo
//
logic tag_v_lo;
logic [lg_num_cache_lp-1:0] tag_lo;
logic tag_yumi_li;
bsg_fifo_1r1w_small #(
.width_p(lg_num_cache_lp)
,.els_p(num_cache_p*num_req_lp)
) tag_fifo (
.clk_i(core_clk_i)
,.reset_i(core_reset_i)
,.v_i(v_i)
,.ready_o(ready_o)
,.data_i(tag_i)
,.v_o(tag_v_lo)
,.data_o(tag_lo)
,.yumi_i(tag_yumi_li)
);
logic [num_cache_p-1:0] cache_sel;
bsg_decode_with_v #(
.num_out_p(num_cache_p)
) demux (
.i(tag_lo)
,.v_i(tag_v_lo)
,.o(cache_sel)
);
// de-serialization
//
logic [num_cache_p-1:0] sipo_v_li;
logic [num_cache_p-1:0] sipo_ready_lo;
logic [num_cache_p-1:0][dma_data_width_p-1:0] sipo_data_li;
logic [num_cache_p-1:0] sipo_v_lo;
logic [num_cache_p-1:0][dram_data_width_p-1:0] sipo_data_lo;
logic [num_cache_p-1:0] sipo_yumi_li;
for (genvar i = 0; i < num_cache_p; i++) begin
bsg_serial_in_parallel_out_full #(
.width_p(dma_data_width_p)
,.els_p(dram_data_width_p/dma_data_width_p)
) sipo (
.clk_i(core_clk_i)
,.reset_i(core_reset_i)
,.v_i(sipo_v_li[i])
,.data_i(sipo_data_li[i])
,.ready_o(sipo_ready_lo[i])
,.v_o(sipo_v_lo[i])
,.data_o(sipo_data_lo[i])
,.yumi_i(sipo_yumi_li[i])
);
end
if (num_req_lp == 1) begin
assign sipo_v_li = dma_data_v_i;
assign sipo_data_li = dma_data_i;
assign dma_data_yumi_o = dma_data_v_i & sipo_ready_lo;
end
else begin
logic [num_cache_p-1:0] fifo_ready_lo;
for (genvar i = 0; i < num_cache_p; i++) begin
bsg_fifo_1r1w_small #(
.width_p(dma_data_width_p)
,.els_p(block_size_in_words_p*data_width_p/dma_data_width_p)
) fifo0 (
.clk_i(core_clk_i)
,.reset_i(core_reset_i)
,.v_i(dma_data_v_i[i])
,.ready_o(fifo_ready_lo[i])
,.data_i(dma_data_i[i])
,.v_o(sipo_v_li[i])
,.data_o(sipo_data_li[i])
,.yumi_i(sipo_v_li[i] & sipo_ready_lo[i])
);
assign dma_data_yumi_o[i] = fifo_ready_lo[i] & dma_data_v_i[i];
end
end
// async fifo
//
logic afifo_full;
logic [dram_data_width_p-1:0] afifo_data_li;
logic afifo_enq;
bsg_async_fifo #(
.lg_size_p(`BSG_SAFE_CLOG2(`BSG_MAX(num_cache_p*num_req_lp,4)))
,.width_p(dram_data_width_p)
) data_afifo (
.w_clk_i(core_clk_i)
,.w_reset_i(core_reset_i)
,.w_enq_i(afifo_enq)
,.w_data_i(afifo_data_li)
,.w_full_o(afifo_full)
,.r_clk_i(dram_clk_i)
,.r_reset_i(dram_reset_i)
,.r_deq_i(dram_data_yumi_i)
,.r_data_o(dram_data_o)
,.r_valid_o(dram_data_v_o)
);
wire send_data = tag_v_lo & ~afifo_full & sipo_v_lo[tag_lo];
assign afifo_enq = send_data;
assign tag_yumi_li = send_data;
assign afifo_data_li = sipo_data_lo[tag_lo];
bsg_decode_with_v #(
.num_out_p(num_cache_p)
) demux0 (
.i(tag_lo)
,.v_i(send_data)
,.o(sipo_yumi_li)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_cache_to_test_dram_tx)
|
`timescale 1ns / 1ps
//------------------------------------------------
module UPCOUNTER_POSEDGE # (parameter SIZE=16)
(
input wire Clock, Reset,
input wire [SIZE-1:0] Initial,
input wire Enable,
output reg [SIZE-1:0] Q
);
always @(posedge Clock )
begin
if (Reset)
Q = Initial;
else
begin
if (Enable)
Q = Q + 1;
end
end
endmodule
//----------------------------------------------------
module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=8 )
(
input wire Clock,
input wire Reset,
input wire Enable,
input wire [SIZE-1:0] D,
output reg [SIZE-1:0] Q
);
always @ (posedge Clock)
begin
if ( Reset )
Q <= 0;
else
begin
if (Enable)
Q <= D;
end
end//always
endmodule
//----------------------------------------------------------------------
module MUX4X1 #(parameter SIZE=32)
(
input wire[SIZE-1:0] iInput0,
input wire[SIZE-1:0] iInput1,
input wire[SIZE-1:0] iInput2,
input wire[SIZE-1:0] iInput3,
input wire[1:0] iSelect,
output reg[SIZE-1:0] oOutput
);
always @(*) begin
case (iSelect)
2'd0: oOutput=iInput0;
2'd1: oOutput=iInput1;
2'd2: oOutput=iInput2;
2'd3: oOutput=iInput3;
endcase
end
endmodule
//*********************************************************************
//RAM Controller
//*********************************************************************
module RAM_controller(
inout [15:0], // Input/Output port
output reg address [17:0], // Address
output reg CE, //Chip Select Enaeble (en cero)
output UB, //High Byte [16-bit data word] (en cero)
output LB,// Low byte [16-bit data word] (en cero)
output WE, //write-enable (en cero)
output OE //read-enable (en cero)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Avalon memory interface functional model
// File :
// Author : Frank Bruno
// Created : 10-19-2010
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description : This models a memory based on the avalon interface to
// speed up simulations.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`define INFO $display
`timescale 1ns / 10ps
//parameter READ_DELAY = 37;
parameter READ_DELAY = 10;
parameter READ_PIPE = READ_DELAY+1;
parameter MEM_SIZE = 32'h100000;
// parameter full_mem_bits = 28;
parameter full_mem_bits = 27;
parameter part_mem_bits = 23;
parameter ADDR_INCR = 1;
module avalon_fast_model
(
local_address,
local_write_req,
local_read_req,
local_wdata,
local_be,
local_size,
global_reset_n,
pll_ref_clk,
soft_reset_n,
local_ready,
local_rdata,
local_rdata_valid,
local_burstbegin,
reset_request_n,
mem_odt,
mem_cs_n,
mem_cke,
mem_addr,
mem_ba,
mem_ras_n,
mem_cas_n,
mem_we_n,
mem_dm,
local_refresh_ack,
local_wdata_req,
local_init_done,
reset_phy_clk_n,
mem_reset_n,
dll_reference_clk,
dqs_delay_ctrl_export,
phy_clk,
aux_full_rate_clk,
aux_half_rate_clk,
mem_clk,
mem_clk_n,
mem_dq,
mem_dqs,
mem_dqsn);
input pll_ref_clk;
input global_reset_n;
input [23:0] local_address;
input local_write_req;
input local_burstbegin;
input local_read_req;
input [127:0] local_wdata;
input [15:0] local_be;
input [4:0] local_size;
input soft_reset_n;
output local_ready;
output [127:0] local_rdata;
output local_rdata_valid;
output reset_request_n;
output local_refresh_ack;
output local_wdata_req;
output local_init_done;
//Unused in this model
output phy_clk;
output aux_full_rate_clk;
output aux_half_rate_clk;
output reset_phy_clk_n;
output mem_reset_n;
output dll_reference_clk;
output [5:0] dqs_delay_ctrl_export;
output [0:0] mem_odt;
output [0:0] mem_cs_n;
output [0:0] mem_cke;
output [12:0] mem_addr;
output [2:0] mem_ba;
output mem_ras_n;
output mem_cas_n;
output mem_we_n;
output [3:0] mem_dm;
inout mem_clk;
inout mem_clk_n;
inout [31:0] mem_dq;
inout [3:0] mem_dqs;
inout [3:0] mem_dqsn;
`define B0 [7:0]
`define B1 [15:8]
`define B2 [23:16]
`define B3 [31:24]
`define B4 [39:32]
`define B5 [47:40]
`define B6 [55:48]
`define B7 [63:56]
`define B8 [71:64]
`define B9 [79:72]
`define B10 [87:80]
`define B11 [95:88]
`define B12 [103:96]
`define B13 [111:104]
`define B14 [119:112]
`define B15 [127:120]
// Wires.
logic clk;
assign clk = pll_ref_clk;
logic phy_clk;
assign phy_clk = aux_half_rate_clk;
logic reset_phy_clk_n;
//assign reset_phy_clk_n = 1'b1;
logic aux_full_rate_clk;
assign aux_full_rate_clk = clk;
wire [0:0] mem_clk;
assign mem_clk = clk;
wire [0:0] mem_clk_n;
assign mem_clk_n = !clk;
logic reset;
assign reset = !global_reset_n;
// Registers.
//logic [31:13] pxa_to_dsp1_ipc_map;
logic aux_half_rate_clk;
logic local_ready;
logic [127:0] local_rdata;
logic local_rdata_valid;
logic reset_request_n;
logic local_refresh_ack;
logic local_wdata_req;
logic local_wdata_req_q1;
logic local_init_done;
logic [15:0] local_be_q0;
logic [15:0] local_be_q1;
logic [127:0] local_wdata_q0;
logic [127:0] local_wdata_q1;
logic local_burstbegin_q0;
logic local_burstbegin_q1;
logic [127:0] local_rdata_d;
logic [127:0] buf_data;
logic local_rdata_valid_d;
logic [23:0] local_address_q0;
logic [23:0] local_address_q1;
logic [5:0] local_size_q0;
logic [5:0] local_size_q1;
logic local_read_req_q0;
logic [23:0] addr, current_addr;
//logic [127:0] mem[MEM_SIZE];
// Memory Banks
`ifdef FAST_MEM_FULL
// logic [127:0] mem[0:MEM_SIZE];
logic [7:0] mem[0 : (1<<full_mem_bits)-1];
`else
logic [127:0] mem[0 : (1<<part_mem_bits)-1];
reg [127: 0] mem_array [0 : (1<<part_mem_bits)-1];
reg [full_mem_bits - 1 : 0] addr_array [0 : (1<<part_mem_bits)-1];
reg [part_mem_bits : 0] mem_used;
reg [part_mem_bits : 0] memory_index;
initial mem_used = 0;
`endif
//Pipeline to delay rd data
logic [127:0] pipe_rdat[READ_PIPE];
logic pipe_rval[READ_PIPE];
integer pipe_i;
integer byte_en;
logic [ 4:0] reset_counter;
logic [31:0] pop_dat;
logic pop_dat_vld ;
logic afull;
//66.5MHz
//parameter HALF_PERIOD = 7.519ns; //66.5MHx
parameter HALF_PERIOD = 2.501ns;
always begin
#HALF_PERIOD aux_half_rate_clk = 0;
#HALF_PERIOD aux_half_rate_clk = 1;
end
//Drive reset_phy_clk_n for 8 clks after reset
always @(posedge clk) begin
if (reset) begin
reset_phy_clk_n <= 0;
reset_counter <= 0;
end
else begin
if (reset_counter<8)
reset_counter <= reset_counter + 1;
reset_phy_clk_n <= reset_counter[3];
end
end
always @(posedge phy_clk) begin
if (reset) begin
for (pipe_i=0; pipe_i<READ_PIPE; pipe_i++) begin
pipe_rdat[pipe_i] <= 128'b0;
pipe_rval[pipe_i] <= 1'b0;
end
end
else begin
for (pipe_i=0; pipe_i<READ_PIPE-1; pipe_i++) begin
pipe_rdat[pipe_i] <= pipe_rdat[pipe_i+1] ;
pipe_rval[pipe_i] <= pipe_rval[pipe_i+1] ;
end
pipe_rdat[READ_DELAY]<= local_rdata_d ;
pipe_rval[READ_DELAY]<= local_rdata_valid_d;
end
end
always @(posedge phy_clk) begin
if (reset) begin
local_ready <= 1'b0 ;
local_init_done <= 1'b0 ;
local_refresh_ack <= 1'b0 ;
end
else begin
//local_ready <= (local_burstbegin && local_read_req)? 1'b0 : 1'b1;
local_ready <= ~afull;
local_init_done <= 1'b1 ;
local_refresh_ack <= 1'b0 ;
local_address_q1 <= local_address_q0 ;
local_address_q0 <= local_address ;
local_size_q1 <= local_size_q0 ;
local_size_q0 <= {1'b0, local_size} ;
local_read_req_q0 <= local_read_req ;
local_rdata <= pipe_rdat[ 0 ] ;
local_rdata_valid <= pipe_rval[ 0 ] ;
local_wdata_req_q1 <= local_wdata_req;
local_wdata_req <= local_write_req ;
local_be_q1 <= local_be_q0;
local_be_q0 <= local_be;
local_wdata_q1 <= local_wdata_q0;
local_wdata_q0 <= local_wdata;
local_burstbegin_q1 <= local_burstbegin_q0;
local_burstbegin_q0 <= local_burstbegin ;
end
end
assign addr = (local_burstbegin_q1?local_address_q1:local_address_q1+ADDR_INCR);
// Write First Data.
always @(posedge phy_clk) begin
if (local_wdata_req_q1 && local_burstbegin_q1) begin
current_addr <= addr + 1;
`INFO("%t: DDR_CTRL wr: addr %0h \t data %0h mask %0h", $time, addr , local_wdata_q1, local_be_q1);
write_mem(addr, local_be_q1, local_wdata_q1);
end
// Write any remaining data.
else if (local_wdata_req_q1) begin
current_addr <= current_addr + 1;
`INFO("%t: DDR_CTRL wr: addr %0h \t data %0h mask %0h", $time, current_addr , local_wdata_q1, local_be_q1);
write_mem(current_addr, local_be_q1, local_wdata_q1);
end
end
// always_comb begin, Aldec has a problem with this.
always @* begin
local_rdata_valid_d = pop_dat_vld;
if (pop_dat_vld) begin
read_mem(pop_dat, local_rdata_d);
`INFO("%t: DDR_CTRL rd: addr %0h \t data %0h", $time, pop_dat , local_rdata_d);
end
end
// Write Memory
task write_mem;
input [full_mem_bits - 1 : 0] addr;
input [15 : 0] be;
input [127 : 0] data;
reg [part_mem_bits : 0] i;
begin
@(negedge phy_clk) begin
if(be[15]) mem[{addr, 4'd15}] = data`B15;
if(be[14]) mem[{addr, 4'd14}] = data`B14;
if(be[13]) mem[{addr, 4'd13}] = data`B13;
if(be[12]) mem[{addr, 4'd12}] = data`B12;
if(be[11]) mem[{addr, 4'd11}] = data`B11;
if(be[10]) mem[{addr, 4'd10}] = data`B10;
if(be[9]) mem[{addr, 4'd9 }] = data`B9;
if(be[8]) mem[{addr, 4'd8 }] = data`B8;
if(be[7]) mem[{addr, 4'd7 }] = data`B7;
if(be[6]) mem[{addr, 4'd6 }] = data`B6;
if(be[5]) mem[{addr, 4'd5 }] = data`B5;
if(be[4]) mem[{addr, 4'd4 }] = data`B4;
if(be[3]) mem[{addr, 4'd3 }] = data`B3;
if(be[2]) mem[{addr, 4'd2 }] = data`B2;
if(be[1]) mem[{addr, 4'd1 }] = data`B1;
if(be[0]) mem[{addr, 4'd0 }] = data`B0;
end
end
endtask
// Read Memory
task read_mem;
input [full_mem_bits - 1 : 0] addr;
output [127 : 0] data;
reg [part_mem_bits : 0] i;
begin
`ifdef FAST_MEM_FULL
data`B15 = mem[{addr, 4'd15}];
data`B14 = mem[{addr, 4'd14}];
data`B13 = mem[{addr, 4'd13}];
data`B12 = mem[{addr, 4'd12}];
data`B11 = mem[{addr, 4'd11}];
data`B10 = mem[{addr, 4'd10}];
data`B9 = mem[{addr, 4'd9 }];
data`B8 = mem[{addr, 4'd8 }];
data`B7 = mem[{addr, 4'd7 }];
data`B6 = mem[{addr, 4'd6 }];
data`B5 = mem[{addr, 4'd5 }];
data`B4 = mem[{addr, 4'd4 }];
data`B3 = mem[{addr, 4'd3 }];
data`B2 = mem[{addr, 4'd2 }];
data`B1 = mem[{addr, 4'd1 }];
data`B0 = mem[{addr, 4'd0 }];
`else
begin : loop
for (i = 0; i < mem_used; i = i + 1) begin
if (addr_array[i] === addr) begin
disable loop;
end
end
end
if (i <= mem_used) begin
data = mem_array[i];
end else begin
data = 'bx;
end
`endif
end
endtask
sync_fifo u_sync_fifo(
.push (local_read_req_q0 && local_burstbegin_q0),
.burst (local_burstbegin_q0),
.burst_count (local_size_q0),
.push_dat (local_address_q0),
.pop (1'b1),
.pop_dat (pop_dat),
.pop_dat_vld (pop_dat_vld),
.full (),
.afull (afull),
.empty (),
.clk (phy_clk),
.reset (reset)
);
endmodule
// FIFO
//
parameter FIFO_DEPTH = 128;
parameter AFULL_SIZE = 64;
module sync_fifo (
push,
burst,
burst_count,
push_dat,
pop,
pop_dat,
pop_dat_vld ,
full,
afull,
empty,
clk,
reset
);
input push;
input burst;
input [5:0] burst_count;
input [31:0] push_dat;
input pop;
output [31:0] pop_dat;
output pop_dat_vld ;
output full;
output afull;
output empty;
input clk;
input reset;
logic full;
logic afull;
//----------------------------------
// Fifo and pointers
bit [31:0] fifo[FIFO_DEPTH-1:0];
bit [31:0] wr_ptr;
bit [31:0] rd_ptr;
bit [5:0] count;
logic [31:0] pop_dat;
logic pop_dat_vld ;
integer verbose = 0;
//----------------------------------
assign pop_dat = fifo[rd_ptr];
assign empty = (rd_ptr == wr_ptr);
//---------------------------------
// Init fifo
//---------------------------------
initial begin
for (int jj=0;jj<FIFO_DEPTH;jj++) begin
fifo[jj] = 0;
end
wr_ptr = 0;
rd_ptr = 0;
full = 0;
afull = 0;
end // initial
assign pop_dat_vld = (pop && (wr_ptr != rd_ptr));
always @(negedge clk) begin
if (!reset) begin
//POP
//incr Rd ptr if diff
if (pop && (wr_ptr != rd_ptr)) begin
fifo[rd_ptr] <= 0;
rd_ptr <= fifo_ptr_inc(rd_ptr);
end
//PUSH
count = 1;
if (push) begin
fifo_push(push_dat);
if (burst)
while (count != burst_count)
fifo_push(push_dat + count++);
end
end
end
always @(wr_ptr or rd_ptr) begin
full = (fifo_space() == 0);
afull = (fifo_avail(AFULL_SIZE)== 0 );
end
//Push new ddr_req onto fifo after checking for space
task fifo_push(
input [31:0] ddr_rq);
begin
if (fifo_space()) begin
if (verbose>10)
$display("%t: fifo_model: OutputQ.Push : rq:%0d; wr_ptr:%0d, rd_ptr:%0d",
$time, ddr_rq, wr_ptr, rd_ptr );
fifo[wr_ptr] = ddr_rq;
wr_ptr = fifo_ptr_inc(wr_ptr);
end
else begin
$display("%t:%m: attempting to write to fifo but no space left",
$time);
$display("%t: Q.Push : rd_ptr:%0d; wr_ptr:%0d",
$time, rd_ptr, wr_ptr );
$finish();
end
end
endtask
function bit [31:0] fifo_ptr_inc;
input bit [31:0] ptr;
begin
fifo_ptr_inc = (ptr==(FIFO_DEPTH-1))? 0: ptr+1;
end
endfunction
function logic fifo_space();
begin
fifo_space= fifo_avail(1);
end
endfunction
//Check is there are num spaces available
function logic fifo_avail(bit[15:0] num = 1);
begin
fifo_avail= wr_ptr == rd_ptr ||
( rd_ptr > wr_ptr &&
(rd_ptr - wr_ptr > num)) ||
( wr_ptr > rd_ptr &&
( FIFO_DEPTH-1 -
(wr_ptr - rd_ptr) >= num)) ;
end
endfunction
endmodule
|
(** * Auto: More Automation *)
Require Export Imp.
(** Up to now, we've continued to use a quite restricted set of
Coq's tactic facilities. In this chapter, we'll learn more about
two very powerful features of Coq's tactic language:
proof search via the [auto] and [eauto] tactics, and
automated forward reasoning via the [Ltac] hypothesis matching
machinery. Using these features together with Ltac's scripting facilities
will enable us to make our proofs startlingly short! Used properly,
they can also make proofs more maintainable and robust in the face
of incremental changes to underlying definitions.
There's a third major source of automation we haven't
fully studied yet, namely built-in decision procedures for specific
kinds of problems: [omega] is one example, but there are others.
This topic will be defered for a while longer.
*)
(** Our motivating example will be this proof, repeated with
just a few small changes from [Imp]. We will try to simplify
this proof in several stages. *)
Ltac inv H := inversion H; subst; clear H.
Theorem ceval_deterministic: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2.
Case "E_Skip". reflexivity.
Case "E_Ass". reflexivity.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption.
Case "E_IfTrue".
SCase "b evaluates to true".
apply IHE1. assumption.
SCase "b evaluates to false (contradiction)".
rewrite H in H5. inversion H5.
Case "E_IfFalse".
SCase "b evaluates to true (contradiction)".
rewrite H in H5. inversion H5.
SCase "b evaluates to false".
apply IHE1. assumption.
Case "E_WhileEnd".
SCase "b evaluates to false".
reflexivity.
SCase "b evaluates to true (contradiction)".
rewrite H in H2. inversion H2.
Case "E_WhileLoop".
SCase "b evaluates to false (contradiction)".
rewrite H in H4. inversion H4.
SCase "b evaluates to true".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption. Qed.
(** * The [auto] and [eauto] tactics *)
(** Thus far, we have (nearly) always written proof scripts that
apply relevant hypothoses or lemmas by name. In particular, when
a chain of hypothesis applications is needed, we have specified
them explicitly. (The only exceptions introduced so far are using
[assumption] to find a matching unqualified hypothesis
or [(e)constructor] to find a matching constructor.) *)
Example auto_example_1 : forall (P Q R: Prop), (P -> Q) -> (Q -> R) -> P -> R.
Proof.
intros P Q R H1 H2 H3.
apply H2. apply H1. assumption.
Qed.
(** The [auto] tactic frees us from this drudgery by _searching_
for a sequence of applications that will prove the goal *)
Example auto_example_1' : forall (P Q R: Prop), (P -> Q) -> (Q -> R) -> P -> R.
Proof.
(*intros P Q R H1 H2 H3. *)
auto.
Qed.
(** The [auto] tactic solves goals that are solvable by any combination of
- [intros],
- [apply] (with a local hypothesis, by default).
The [eauto] tactic works just like [auto], except that it uses
[eapply] instead of [apply]. *)
(** Using [auto] is always "safe" in the sense that it will never fail
and will never change the proof state: either it completely solves
the current goal, or it does nothing.
*)
(** A more complicated example: *)
Example auto_example_2 : forall P Q R S T U : Prop,
(P -> Q) ->
(P -> R) ->
(T -> R) ->
(S -> T -> U) ->
((P->Q) -> (P->S)) ->
T ->
P ->
U.
Proof. auto. Qed.
(** Search can take an arbitrarily long time, so there are limits to
how far [auto] will search by default *)
Example auto_example_3 : forall (P Q R S T U: Prop),
(P -> Q) -> (Q -> R) -> (R -> S) ->
(S -> T) -> (T -> U) -> P -> U.
Proof.
auto. (* When it cannot solve the goal, does nothing! *)
auto 6. (* Optional argument says how deep to search (default depth is 5) *)
Qed.
(** When searching for potential proofs of the current goal, [auto]
and [eauto] consider the hypotheses in the current context
together with a _hint database_ of other lemmas and constructors.
Some of the lemmas and constructors we've already seen -- e.g.,
[eq_refl], [conj], [or_introl], and [or_intror] -- are installed in this hint
database by default. *)
Example auto_example_4 : forall P Q R : Prop,
Q ->
(Q -> R) ->
P \/ (Q /\ R).
Proof.
auto. Qed.
(** If we want to see which facts [auto] is using, we can use [info_auto] instead. *)
Example auto_example_5: 2 = 2.
Proof.
info_auto. (* subsumes reflexivity because eq_refl is in hint database *)
Qed.
(** We can extend the hint database just for the purposes of one
application of [auto] or [eauto] by writing [auto using ...]. *)
Lemma le_antisym : forall n m: nat, (n <= m /\ m <= n) -> n = m.
Proof. intros. omega. Qed.
Example auto_example_6 : forall n m p : nat,
(n<= p -> (n <= m /\ m <= n)) ->
n <= p ->
n = m.
Proof.
intros.
auto. (* does nothing: auto doesn't destruct hypotheses! *)
auto using le_antisym.
Qed.
(** Of course, in any given development there will also be some of our
own specific constructors and lemmas that are used very often in
proofs. We can add these to the global hint database by writing
Hint Resolve T.
at the top level, where [T] is a top-level theorem or a
constructor of an inductively defined proposition (i.e., anything
whose type is an implication). As a shorthand, we can write
Hint Constructors c.
to tell Coq to do a [Hint Resolve] for _all_ of the constructors
from the inductive definition of [c].
It is also sometimes necessary to add
Hint Unfold d.
where [d] is a defined symbol, so that [auto] knows to expand
uses of [d] and enable further possibilities for applying
lemmas that it knows about. *)
Hint Resolve le_antisym.
Example auto_example_6' : forall n m p : nat,
(n<= p -> (n <= m /\ m <= n)) ->
n <= p ->
n = m.
Proof.
(*intros.*)
auto. (* picks up hint from database *)
Qed.
Definition is_fortytwo x := x = 42.
Example auto_example_7: forall x, (x <= 42 /\ 42 <= x) -> is_fortytwo x.
Proof.
auto. (* does nothing *)
Abort.
Hint Unfold is_fortytwo.
Example auto_example_7' : forall x, (x <= 42 /\ 42 <= x) -> is_fortytwo x.
Proof.
info_auto.
Qed.
Hint Constructors ceval.
Definition st12 := update (update empty_state X 1) Y 2.
Definition st21 := update (update empty_state X 2) Y 1.
Example auto_example_8 : exists s',
(IFB (BLe (AId X) (AId Y))
THEN (Z ::= AMinus (AId Y) (AId X))
ELSE (Y ::= APlus (AId X) (AId Z))
FI) / st21 || s'.
Proof.
eexists. info_auto.
Qed.
Example auto_example_8' : exists s',
(IFB (BLe (AId X) (AId Y))
THEN (Z ::= AMinus (AId Y) (AId X))
ELSE (Y ::= APlus (AId X) (AId Z))
FI) / st12 || s'.
Proof.
eexists. info_auto.
Qed.
(** Now let's take a pass over [ceval_deterministic] using [auto]
to simplify the proof script. We see that all simple sequences of hypothesis
applications and all uses of [reflexivity] can be replaces by [auto],
which we add to the default tactic to be applied to each case.
*)
Theorem ceval_deterministic': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2; auto.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". auto.
subst st'0.
auto.
Case "E_IfTrue".
SCase "b evaluates to false (contradiction)".
rewrite H in H5. inversion H5.
Case "E_IfFalse".
SCase "b evaluates to true (contradiction)".
rewrite H in H5. inversion H5.
Case "E_WhileEnd".
SCase "b evaluates to true (contradiction)".
rewrite H in H2. inversion H2.
Case "E_WhileLoop".
SCase "b evaluates to false (contradiction)".
rewrite H in H4. inversion H4.
SCase "b evaluates to true".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". auto.
subst st'0.
auto. Qed.
(** * Searching Hypotheses *)
(** The proof has become simpler, but there is still an annoying amount
of repetition. Let's start by tackling the contradiction cases. Each
of them occurs in a situation where we have both
[H1: beval st b = false]
and
[H2: beval st b = true]
as hypotheses. The contradiction is evident, but demonstrating it
is a little complicated: we have to locate the two hypotheses [H1] and [H2]
and do a [rewrite] following by an [inversion]. We'd like to automate
this process.
Note: In fact, Coq has a built-in tactic [congruence] that will do the
job. But we'll ignore the existence of this tactic for now, in order
to demonstrate how to build forward search tactics by hand.
*)
(** As a first step, we can abstract out the piece of script in question by
writing a small amount of paramerized Ltac. *)
Ltac rwinv H1 H2 := rewrite H1 in H2; inv H2.
Theorem ceval_deterministic'': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2; auto.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". auto.
subst st'0.
auto.
Case "E_IfTrue".
SCase "b evaluates to false (contradiction)".
rwinv H H5.
Case "E_IfFalse".
SCase "b evaluates to true (contradiction)".
rwinv H H5.
Case "E_WhileEnd".
SCase "b evaluates to true (contradiction)".
rwinv H H2.
Case "E_WhileLoop".
SCase "b evaluates to false (contradiction)".
rwinv H H4.
SCase "b evaluates to true".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". auto.
subst st'0.
auto. Qed.
(** But this is not much better. We really want Coq to discover
the relevant hypotheses for us. We can do this by using the
[match goal with ... end] facility of Ltac. *)
Ltac find_rwinv :=
match goal with
H1: ?E = true, H2: ?E = false |- _ => rwinv H1 H2
end.
(** In words, this [match goal] looks for two (distinct) hypotheses that have
the form of equalities with the same arbitrary expression [E] on the
left and conflicting boolean values on the right; if such hypotheses are
found, it binds [H1] and [H2] to their names, and applies the tactic
after the [=>].
Adding this tactic to our default string handles all the contradiction cases. *)
Theorem ceval_deterministic''': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2; try find_rwinv; auto.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". auto.
subst st'0.
auto.
Case "E_WhileLoop".
SCase "b evaluates to true".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". auto.
subst st'0.
auto. Qed.
(** Finally, let's see about the remaining cases. Each of them involves
applying a conditional hypothesis to extract an equality. Currently
we have phrased these as assertions, so that we have to predict what
the resulting equality will be (although we can then use [auto]
to prove it.) An alternative is to pick the relevant
hypotheses to use, and then rewrite with them, as follows:
*)
Theorem ceval_deterministic'''': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2; try find_rwinv; auto.
Case "E_Seq".
rewrite (IHE1_1 st'0 H1) in *. auto.
Case "E_WhileLoop".
SCase "b evaluates to true".
rewrite (IHE1_1 st'0 H3) in *. auto. Qed.
(** Now we can automate the task of finding the relevant hypotheses to
rewrite with. *)
Ltac find_eqn :=
match goal with
H1: forall x, ?P x -> ?L = ?R, H2: ?P ?X |- _ =>
rewrite (H1 X H2) in *
end.
(** But there are several pairs of hypotheses that have the correct
general form, and it seems tricky to pick out the correct ones.
The important thing to realize is that we can _try them all_!
Here's how this works:
- [rewrite] will fail given a trivial equation of the form [X = X].
- each execution of [match goal] will keep trying to find a valid pair of
hypotheses until the tactic on the RHS of the match succeeds;
if there are no such pairs, it fails.
- we can wrap the whole thing in a [repeat] which will keep
doing useful rewrites until only trivial ones are left.
*)
Theorem ceval_deterministic''''': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2; try find_rwinv; repeat find_eqn; auto.
Qed.
(** The big pay-off in this approach is that our proof script
should be robust in the face of modest changes to our language.
For example, we can add a [REPEAT] command to the language.
(This was an exercise in [Hoare.v].) *)
Module Repeat.
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CRepeat : com -> bexp -> com.
(** [REPEAT] behaves like [WHILE], except that the loop guard is
checked _after_ each execution of the body, with the loop
repeating as long as the guard stays _false_. Because of this,
the body will always execute at least once. *)
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE"
| Case_aux c "CRepeat" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'REPEAT' e1 'UNTIL' b2 'END'" :=
(CRepeat e1 b2) (at level 80, right associativity).
Inductive ceval : state -> com -> state -> Prop :=
| E_Skip : forall st,
ceval st SKIP st
| E_Ass : forall st a1 n X,
aeval st a1 = n ->
ceval st (X ::= a1) (update st X n)
| E_Seq : forall c1 c2 st st' st'',
ceval st c1 st' ->
ceval st' c2 st'' ->
ceval st (c1 ; c2) st''
| E_IfTrue : forall st st' b1 c1 c2,
beval st b1 = true ->
ceval st c1 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_IfFalse : forall st st' b1 c1 c2,
beval st b1 = false ->
ceval st c2 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_WhileEnd : forall b1 st c1,
beval st b1 = false ->
ceval st (WHILE b1 DO c1 END) st
| E_WhileLoop : forall st st' st'' b1 c1,
beval st b1 = true ->
ceval st c1 st' ->
ceval st' (WHILE b1 DO c1 END) st'' ->
ceval st (WHILE b1 DO c1 END) st''
| E_RepeatEnd : forall st st' b1 c1,
ceval st c1 st' ->
beval st' b1 = true ->
ceval st (CRepeat c1 b1) st'
| E_RepeatLoop : forall st st' st'' b1 c1,
ceval st c1 st' ->
beval st' b1 = false ->
ceval st' (CRepeat c1 b1) st'' ->
ceval st (CRepeat c1 b1) st''
.
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass"
| Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
| Case_aux c "E_RepeatEnd" | Case_aux c "E_RepeatLoop"
].
Notation "c1 '/' st '||' st'" := (ceval st c1 st')
(at level 40, st at level 39).
Theorem ceval_deterministic: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2; try find_rwinv; repeat find_eqn; auto.
Case "E_RepeatEnd".
SCase "b evaluates to false (contradiction)".
find_rwinv.
(* oops: why didn't [find_rwinv] solve this for us already?
answer: we did things in the wrong order. *)
case "E_RepeatLoop".
SCase "b evaluates to true (contradiction)".
find_rwinv.
Qed.
Theorem ceval_deterministic': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2; repeat find_eqn; try find_rwinv; auto.
Qed.
End Repeat.
(** These examples just give a flavor of what "hyper-automation" can do...
The details of using [match goal] are tricky, and debugging is
not pleasant at all. But it is well worth adding at least simple
uses to your proofs to avoid tedium and "future proof" your scripts.
*)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
|
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// Copyright 2006, 2007, 2008 Xilinx, Inc.
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// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.6.1
// \ \ Application: MIG
// / / Filename: ddr2_tb_test_addr_gen.v
// /___/ /\ Date Last Modified: $Date: 2010/11/26 18:26:02 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// The address for the memory and the various user commands can be given
// through this module. It instantiates the block RAM which stores all the
// information in particular sequence. The data stored should be in a
// sequence starting from LSB:
// column address, row address, bank address, commands.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_tb_test_addr_gen #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_36_1 module. Please refer to
// the mig_36_1 module for actual values.
parameter BANK_WIDTH = 2,
parameter COL_WIDTH = 10,
parameter ROW_WIDTH = 14
)
(
input clk,
input rst,
input wr_addr_en,
output reg [2:0] app_af_cmd,
output reg [30:0] app_af_addr,
output reg app_af_wren
);
// RAM initialization patterns
// NOTE: Not all bits in each range may be used (e.g. in an application
// using only 10 column bits, bits[11:10] of ROM output will be unused
// COLUMN = [11:0]
// ROW = [27:12]
// BANK = [30:28]
// CHIP = [31]
// COMMAND = [35:32]
localparam RAM_INIT_00 = {128'h800020C0_800020C8_000020D0_000020D8,
128'h000010E0_000010E8_800010F0_800010F8};
localparam RAM_INIT_01 = {128'h800020C0_800020C8_000020D0_000020D8,
128'h000010E0_000010E8_800010F0_800010F8};
localparam RAM_INIT_02 = {128'h100040C0_100040C8_900040D0_900040D8,
128'h900030E0_900030E8_100030F0_100030F8};
localparam RAM_INIT_03 = {128'h100040C0_100040C8_900040D0_900040D8,
128'h900030E0_900030E8_100030F0_100030F8};
localparam RAM_INIT_04 = {128'hA00060C0_200060C8_200060D0_A00060D8,
128'h200050E0_A00050E8_A00050F0_200050F8};
localparam RAM_INIT_05 = {128'hA00060C0_200060C8_200060D0_A00060D8,
128'h200050E0_A00050E8_A00050F0_200050F8};
localparam RAM_INIT_06 = {128'h300080C0_B00080C8_B00080D0_300080D8,
128'hB00070E0_300070E8_300070F0_B00070F8};
localparam RAM_INIT_07 = {128'h300080C0_B00080C8_B00080D0_300080D8,
128'hB00070E0_300070E8_300070F0_B00070F8};
localparam RAM_INITP_00 = {128'h11111111_00000000_11111111_00000000,
128'h11111111_00000000_11111111_00000000};
reg wr_addr_en_r1;
reg [2:0] af_cmd_r;
reg [30:0] af_addr_r;
reg af_wren_r;
wire [15:0] ramb_addr;
wire [35:0] ramb_dout;
reg rst_r
/* synthesis syn_preserve = 1 */;
reg rst_r1
/* synthesis syn_maxfan = 10 */;
reg [5:0] wr_addr_cnt;
reg wr_addr_en_r0;
// XST attributes for local reset "tree"
// synthesis attribute shreg_extract of rst_r is "no";
// synthesis attribute shreg_extract of rst_r1 is "no";
// synthesis attribute equivalent_register_removal of rst_r is "no"
//*****************************************************************
// local reset "tree" for controller logic only. Create this to ease timing
// on reset path. Prohibit equivalent register removal on RST_R to prevent
// "sharing" with other local reset trees (caution: make sure global fanout
// limit is set to larger than fanout on RST_R, otherwise SLICES will be
// used for fanout control on RST_R.
always @(posedge clk) begin
rst_r <= rst;
rst_r1 <= rst_r;
end
//***************************************************************************
// ADDRESS generation for Write and Read Address FIFOs:
// ROM with address patterns
// 512x36 mode is used with addresses 0-127 for storing write addresses and
// addresses (128-511) for storing read addresses
// INIP_OO: read 1
// INIP_OO: write 0
//***************************************************************************
assign ramb_addr = {5'b00000, wr_addr_cnt, 5'b00000};
RAMB36 #
(
.READ_WIDTH_A (36),
.READ_WIDTH_B (36),
.DOA_REG (1), // register to help timing
.INIT_00 (RAM_INIT_00),
.INIT_01 (RAM_INIT_01),
.INIT_02 (RAM_INIT_02),
.INIT_03 (RAM_INIT_03),
.INIT_04 (RAM_INIT_04),
.INIT_05 (RAM_INIT_05),
.INIT_06 (RAM_INIT_06),
.INIT_07 (RAM_INIT_07),
.INITP_00 (RAM_INITP_00)
)
u_wr_rd_addr_lookup
(
.CASCADEOUTLATA (),
.CASCADEOUTLATB (),
.CASCADEOUTREGA (),
.CASCADEOUTREGB (),
.DOA (ramb_dout[31:0]),
.DOB (),
.DOPA (ramb_dout[35:32]),
.DOPB (),
.ADDRA (ramb_addr),
.ADDRB (16'h0000),
.CASCADEINLATA (),
.CASCADEINLATB (),
.CASCADEINREGA (),
.CASCADEINREGB (),
.CLKA (clk),
.CLKB (clk),
.DIA (32'b0),
.DIB (32'b0),
.DIPA (4'b0),
.DIPB (4'b0),
.ENA (1'b1),
.ENB (1'b1),
.REGCEA (1'b1),
.REGCEB (1'b1),
.SSRA (1'b0),
.SSRB (1'b0),
.WEA (4'b0000),
.WEB (4'b0000)
);
// register backend enables / FIFO enables
// write enable for Command/Address FIFO is generated 2 CC after WR_ADDR_EN
// (takes 2 CC to come out of test RAM)
always @(posedge clk)
if (rst_r1) begin
app_af_wren <= 1'b0;
wr_addr_en_r0 <= 1'b0;
wr_addr_en_r1 <= 1'b0;
af_wren_r <= 1'b0;
end else begin
wr_addr_en_r0 <= wr_addr_en;
wr_addr_en_r1 <= wr_addr_en_r0;
af_wren_r <= wr_addr_en_r1;
app_af_wren <= af_wren_r;
end
// FIFO addresses
always @(posedge clk) begin
af_addr_r <= {30{1'b0}};
af_addr_r[COL_WIDTH-1:0] <= ramb_dout[COL_WIDTH-1:0];
af_addr_r[ROW_WIDTH+COL_WIDTH-1:COL_WIDTH]
<= ramb_dout[ROW_WIDTH+11:12];
af_addr_r[BANK_WIDTH+ROW_WIDTH+COL_WIDTH-1:ROW_WIDTH+COL_WIDTH]
<= ramb_dout[BANK_WIDTH+27:28];
af_addr_r[BANK_WIDTH+ROW_WIDTH+COL_WIDTH]
<= ramb_dout[31];
// only reads and writes are supported for now
af_cmd_r <= {1'b0, ramb_dout[33:32]};
app_af_cmd <= af_cmd_r;
app_af_addr <= af_addr_r;
end
// address input for RAM
always @ (posedge clk)
if (rst_r1)
wr_addr_cnt <= 6'b000000;
else if (wr_addr_en)
wr_addr_cnt <= wr_addr_cnt + 1;
endmodule
|
// update_remote_update_0.v
// This file was auto-generated from altera_remote_update_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module update_remote_update_0 (
output wire busy, // busy.busy
output wire [28:0] data_out, // data_out.data_out
input wire [2:0] param, // param.param
input wire read_param, // read_param.read_param
input wire reconfig, // reconfig.reconfig
input wire reset_timer, // reset_timer.reset_timer
input wire [1:0] read_source, // read_source.read_source
input wire clock, // clock.clk
input wire reset // reset.reset
);
altera_remote_update_core remote_update_core (
.read_param (read_param), // read_param.read_param
.param (param), // param.param
.reconfig (reconfig), // reconfig.reconfig
.reset_timer (reset_timer), // reset_timer.reset_timer
.clock (clock), // clock.clk
.reset (reset), // reset.reset
.busy (busy), // busy.busy
.data_out (data_out), // data_out.data_out
.read_source (read_source), // read_source.read_source
.ctl_nupdt (1'b0) // (terminated)
);
endmodule
|
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// mv_read O 64
// mav_write O 64
// mv_sip_read O 64
// mav_sip_write O 64
// CLK I 1 clock
// RST_N I 1 reset
// mav_write_misa I 28
// mav_write_wordxl I 64
// mav_sip_write_misa I 28
// mav_sip_write_wordxl I 64
// m_external_interrupt_req_req I 1 reg
// s_external_interrupt_req_req I 1 reg
// software_interrupt_req_req I 1 reg
// timer_interrupt_req_req I 1 reg
// EN_reset I 1
// EN_mav_write I 1
// EN_mav_sip_write I 1
//
// Combinational paths from inputs to outputs:
// (mav_write_misa, mav_write_wordxl) -> mav_write
// (mav_sip_write_misa, mav_sip_write_wordxl) -> mav_sip_write
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCSR_MIP(CLK,
RST_N,
EN_reset,
mv_read,
mav_write_misa,
mav_write_wordxl,
EN_mav_write,
mav_write,
mv_sip_read,
mav_sip_write_misa,
mav_sip_write_wordxl,
EN_mav_sip_write,
mav_sip_write,
m_external_interrupt_req_req,
s_external_interrupt_req_req,
software_interrupt_req_req,
timer_interrupt_req_req);
input CLK;
input RST_N;
// action method reset
input EN_reset;
// value method mv_read
output [63 : 0] mv_read;
// actionvalue method mav_write
input [27 : 0] mav_write_misa;
input [63 : 0] mav_write_wordxl;
input EN_mav_write;
output [63 : 0] mav_write;
// value method mv_sip_read
output [63 : 0] mv_sip_read;
// actionvalue method mav_sip_write
input [27 : 0] mav_sip_write_misa;
input [63 : 0] mav_sip_write_wordxl;
input EN_mav_sip_write;
output [63 : 0] mav_sip_write;
// action method m_external_interrupt_req
input m_external_interrupt_req_req;
// action method s_external_interrupt_req
input s_external_interrupt_req_req;
// action method software_interrupt_req
input software_interrupt_req_req;
// action method timer_interrupt_req
input timer_interrupt_req_req;
// signals for module outputs
wire [63 : 0] mav_sip_write, mav_write, mv_read, mv_sip_read;
// register rg_meip
reg rg_meip;
wire rg_meip$D_IN, rg_meip$EN;
// register rg_msip
reg rg_msip;
wire rg_msip$D_IN, rg_msip$EN;
// register rg_mtip
reg rg_mtip;
wire rg_mtip$D_IN, rg_mtip$EN;
// register rg_seip
reg rg_seip;
wire rg_seip$D_IN, rg_seip$EN;
// register rg_ssip
reg rg_ssip;
reg rg_ssip$D_IN;
wire rg_ssip$EN;
// register rg_stip
reg rg_stip;
wire rg_stip$D_IN, rg_stip$EN;
// register rg_ueip
reg rg_ueip;
reg rg_ueip$D_IN;
wire rg_ueip$EN;
// register rg_usip
reg rg_usip;
reg rg_usip$D_IN;
wire rg_usip$EN;
// register rg_utip
reg rg_utip;
wire rg_utip$D_IN, rg_utip$EN;
// rule scheduling signals
wire CAN_FIRE_m_external_interrupt_req,
CAN_FIRE_mav_sip_write,
CAN_FIRE_mav_write,
CAN_FIRE_reset,
CAN_FIRE_s_external_interrupt_req,
CAN_FIRE_software_interrupt_req,
CAN_FIRE_timer_interrupt_req,
WILL_FIRE_m_external_interrupt_req,
WILL_FIRE_mav_sip_write,
WILL_FIRE_mav_write,
WILL_FIRE_reset,
WILL_FIRE_s_external_interrupt_req,
WILL_FIRE_software_interrupt_req,
WILL_FIRE_timer_interrupt_req;
// remaining internal signals
wire [11 : 0] new_mip__h1072, new_mip__h600;
wire seip__h634,
ssip__h1112,
ssip__h638,
stip__h636,
ueip__h1111,
ueip__h635,
usip__h1113,
usip__h639,
utip__h637;
// action method reset
assign CAN_FIRE_reset = 1'd1 ;
assign WILL_FIRE_reset = EN_reset ;
// value method mv_read
assign mv_read = { 52'd0, new_mip__h600 } ;
// actionvalue method mav_write
assign mav_write = { 52'd0, new_mip__h1072 } ;
assign CAN_FIRE_mav_write = 1'd1 ;
assign WILL_FIRE_mav_write = EN_mav_write ;
// value method mv_sip_read
assign mv_sip_read =
{ 54'd0,
rg_seip,
rg_ueip,
2'b0,
rg_stip,
rg_utip,
2'b0,
rg_ssip,
rg_usip } ;
// actionvalue method mav_sip_write
assign mav_sip_write =
{ 54'd0,
rg_seip,
ueip__h1111,
2'b0,
rg_stip,
rg_utip,
2'b0,
ssip__h1112,
usip__h1113 } ;
assign CAN_FIRE_mav_sip_write = 1'd1 ;
assign WILL_FIRE_mav_sip_write = EN_mav_sip_write ;
// action method m_external_interrupt_req
assign CAN_FIRE_m_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_m_external_interrupt_req = 1'd1 ;
// action method s_external_interrupt_req
assign CAN_FIRE_s_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_s_external_interrupt_req = 1'd1 ;
// action method software_interrupt_req
assign CAN_FIRE_software_interrupt_req = 1'd1 ;
assign WILL_FIRE_software_interrupt_req = 1'd1 ;
// action method timer_interrupt_req
assign CAN_FIRE_timer_interrupt_req = 1'd1 ;
assign WILL_FIRE_timer_interrupt_req = 1'd1 ;
// register rg_meip
assign rg_meip$D_IN = m_external_interrupt_req_req ;
assign rg_meip$EN = 1'b1 ;
// register rg_msip
assign rg_msip$D_IN = software_interrupt_req_req ;
assign rg_msip$EN = 1'b1 ;
// register rg_mtip
assign rg_mtip$D_IN = timer_interrupt_req_req ;
assign rg_mtip$EN = 1'b1 ;
// register rg_seip
assign rg_seip$D_IN = s_external_interrupt_req_req ;
assign rg_seip$EN = 1'b1 ;
// register rg_ssip
always@(EN_reset or
EN_mav_write or ssip__h638 or EN_mav_sip_write or ssip__h1112)
case (1'b1)
EN_reset: rg_ssip$D_IN = 1'd0;
EN_mav_write: rg_ssip$D_IN = ssip__h638;
EN_mav_sip_write: rg_ssip$D_IN = ssip__h1112;
default: rg_ssip$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign rg_ssip$EN = EN_mav_write || EN_mav_sip_write || EN_reset ;
// register rg_stip
assign rg_stip$D_IN = !EN_reset && stip__h636 ;
assign rg_stip$EN = EN_mav_write || EN_reset ;
// register rg_ueip
always@(EN_reset or
EN_mav_write or ueip__h635 or EN_mav_sip_write or ueip__h1111)
case (1'b1)
EN_reset: rg_ueip$D_IN = 1'd0;
EN_mav_write: rg_ueip$D_IN = ueip__h635;
EN_mav_sip_write: rg_ueip$D_IN = ueip__h1111;
default: rg_ueip$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign rg_ueip$EN = EN_mav_write || EN_mav_sip_write || EN_reset ;
// register rg_usip
always@(EN_reset or
EN_mav_write or usip__h639 or EN_mav_sip_write or usip__h1113)
case (1'b1)
EN_reset: rg_usip$D_IN = 1'd0;
EN_mav_write: rg_usip$D_IN = usip__h639;
EN_mav_sip_write: rg_usip$D_IN = usip__h1113;
default: rg_usip$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign rg_usip$EN = EN_mav_write || EN_mav_sip_write || EN_reset ;
// register rg_utip
assign rg_utip$D_IN = !EN_reset && utip__h637 ;
assign rg_utip$EN = EN_mav_write || EN_reset ;
// remaining internal signals
assign new_mip__h1072 =
{ rg_meip,
1'b0,
seip__h634,
ueip__h635,
rg_mtip,
1'b0,
stip__h636,
utip__h637,
rg_msip,
1'b0,
ssip__h638,
usip__h639 } ;
assign new_mip__h600 =
{ rg_meip,
1'b0,
rg_seip,
rg_ueip,
rg_mtip,
1'b0,
rg_stip,
rg_utip,
rg_msip,
1'b0,
rg_ssip,
rg_usip } ;
assign seip__h634 = mav_write_misa[18] && mav_write_wordxl[9] ;
assign ssip__h1112 = mav_sip_write_misa[18] && mav_sip_write_wordxl[1] ;
assign ssip__h638 = mav_write_misa[18] && mav_write_wordxl[1] ;
assign stip__h636 = mav_write_misa[18] && mav_write_wordxl[5] ;
assign ueip__h1111 = mav_sip_write_misa[13] && mav_sip_write_wordxl[8] ;
assign ueip__h635 = mav_write_misa[13] && mav_write_wordxl[8] ;
assign usip__h1113 = mav_sip_write_misa[13] && mav_sip_write_wordxl[0] ;
assign usip__h639 = mav_write_misa[13] && mav_write_wordxl[0] ;
assign utip__h637 = mav_write_misa[13] && mav_write_wordxl[4] ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_meip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_msip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_seip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_ssip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_stip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_ueip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_usip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_utip <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (rg_meip$EN) rg_meip <= `BSV_ASSIGNMENT_DELAY rg_meip$D_IN;
if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN;
if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN;
if (rg_seip$EN) rg_seip <= `BSV_ASSIGNMENT_DELAY rg_seip$D_IN;
if (rg_ssip$EN) rg_ssip <= `BSV_ASSIGNMENT_DELAY rg_ssip$D_IN;
if (rg_stip$EN) rg_stip <= `BSV_ASSIGNMENT_DELAY rg_stip$D_IN;
if (rg_ueip$EN) rg_ueip <= `BSV_ASSIGNMENT_DELAY rg_ueip$D_IN;
if (rg_usip$EN) rg_usip <= `BSV_ASSIGNMENT_DELAY rg_usip$D_IN;
if (rg_utip$EN) rg_utip <= `BSV_ASSIGNMENT_DELAY rg_utip$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_meip = 1'h0;
rg_msip = 1'h0;
rg_mtip = 1'h0;
rg_seip = 1'h0;
rg_ssip = 1'h0;
rg_stip = 1'h0;
rg_ueip = 1'h0;
rg_usip = 1'h0;
rg_utip = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkCSR_MIP
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool versions:
// Description: Master Control FSM
//
// Dependencies: address
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module main(
/* input clock */
input CLKIN,
/* SNES signals */
input [23:0] SNES_ADDR_IN,
input SNES_READ_IN,
input SNES_WRITE_IN,
input SNES_CS,
inout [7:0] SNES_DATA,
input SNES_CPU_CLK_IN,
input SNES_REFRESH,
output SNES_IRQ,
output SNES_DATABUS_OE,
output SNES_DATABUS_DIR,
input SNES_SYSCLK,
input [7:0] SNES_PA,
input SNES_PARD_IN,
input SNES_PAWR_IN,
/* SRAM signals */
/* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
inout [15:0] ROM_DATA,
output [22:0] ROM_ADDR,
output ROM_CE,
output ROM_OE,
output ROM_WE,
output ROM_BHE,
output ROM_BLE,
/* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
inout [7:0] RAM_DATA,
output [18:0] RAM_ADDR,
output RAM_CE,
output RAM_OE,
output RAM_WE,
/* MCU signals */
input SPI_MOSI,
inout SPI_MISO,
input SPI_SS,
inout SPI_SCK,
input MCU_OVR,
output MCU_RDY,
output DAC_MCLK,
output DAC_LRCK,
output DAC_SDOUT,
/* SD signals */
input [3:0] SD_DAT,
inout SD_CMD,
inout SD_CLK,
/* debug */
output p113_out
);
wire CLK2;
wire dspx_dp_enable;
wire [7:0] spi_cmd_data;
wire [7:0] spi_param_data;
wire [7:0] spi_input_data;
wire [31:0] spi_byte_cnt;
wire [2:0] spi_bit_cnt;
wire [23:0] MCU_ADDR;
wire [2:0] MAPPER;
wire [23:0] SAVERAM_MASK;
wire [23:0] ROM_MASK;
wire [7:0] SD_DMA_SRAM_DATA;
wire [1:0] SD_DMA_TGT;
wire [10:0] SD_DMA_PARTIAL_START;
wire [10:0] SD_DMA_PARTIAL_END;
wire [10:0] dac_addr;
//wire [7:0] dac_volume;
wire [7:0] msu_volumerq_out;
wire [6:0] msu_status_out;
wire [31:0] msu_addressrq_out;
wire [15:0] msu_trackrq_out;
wire [13:0] msu_write_addr;
wire [13:0] msu_ptr_addr;
wire [7:0] MSU_SNES_DATA_IN;
wire [7:0] MSU_SNES_DATA_OUT;
wire [5:0] msu_status_reset_bits;
wire [5:0] msu_status_set_bits;
wire [14:0] bsx_regs;
wire [7:0] BSX_SNES_DATA_IN;
wire [7:0] BSX_SNES_DATA_OUT;
wire [7:0] bsx_regs_reset_bits;
wire [7:0] bsx_regs_set_bits;
wire [59:0] rtc_data;
wire [55:0] rtc_data_in;
wire [59:0] srtc_rtc_data_out;
wire [3:0] SRTC_SNES_DATA_IN;
wire [7:0] SRTC_SNES_DATA_OUT;
wire [7:0] DSPX_SNES_DATA_IN;
wire [7:0] DSPX_SNES_DATA_OUT;
wire [23:0] dspx_pgm_data;
wire [10:0] dspx_pgm_addr;
wire dspx_pgm_we;
wire [15:0] dspx_dat_data;
wire [10:0] dspx_dat_addr;
wire dspx_dat_we;
wire [7:0] featurebits;
wire [23:0] MAPPED_SNES_ADDR;
wire ROM_ADDR0;
wire [9:0] bs_page;
wire [8:0] bs_page_offset;
wire bs_page_enable;
wire [4:0] DBG_srtc_state;
wire DBG_srtc_we_rising;
wire [3:0] DBG_srtc_ptr;
wire [5:0] DBG_srtc_we_sreg;
wire [13:0] DBG_msu_address;
wire DBG_msu_reg_oe_rising;
wire DBG_msu_reg_oe_falling;
wire DBG_msu_reg_we_rising;
wire [2:0] SD_DMA_DBG_clkcnt;
wire [10:0] SD_DMA_DBG_cyclecnt;
wire [8:0] snescmd_addr_mcu;
wire [7:0] snescmd_data_out_mcu;
wire [7:0] snescmd_data_in_mcu;
reg [7:0] SNES_PARDr;
reg [7:0] SNES_READr;
reg [7:0] SNES_WRITEr;
reg [7:0] SNES_CPU_CLKr;
reg [23:0] SNES_ADDRr [5:0];
reg [23:0] SNES_ADDR_CYCLEr = 24'h000000;
reg [7:0] BUS_DATA;
always @(posedge CLK2) begin
if(~SNES_READ_IN | ~SNES_WRITE_IN) BUS_DATA <= SNES_DATA;
end
reg SNES_DEADr = 1;
reg SNES_reset_strobe = 0;
reg free_strobe = 0;
wire SNES_PARD_start = ((SNES_PARDr[6:1] | SNES_PARDr[7:2]) == 6'b111110);
wire SNES_RD_start = ((SNES_READr[6:1] | SNES_READr[7:2]) == 6'b111110);
wire SNES_RD_end = ((SNES_READr[6:1] & SNES_READr[7:2]) == 6'b000001);
wire SNES_WR_end = ((SNES_WRITEr[6:1] & SNES_WRITEr[7:2]) == 6'b000001);
wire SNES_cycle_start = ((SNES_CPU_CLKr[5:2] & SNES_CPU_CLKr[4:1]) == 4'b0001);
wire SNES_cycle_end = ((SNES_CPU_CLKr[5:2] | SNES_CPU_CLKr[4:1]) == 4'b1110);
wire SNES_WRITE = SNES_WRITEr[2] & SNES_WRITEr[1];
wire SNES_READ = SNES_READr[2] & SNES_READr[1];
wire SNES_CPU_CLK = SNES_CPU_CLKr[2] & SNES_CPU_CLKr[1];
wire SNES_PARD = SNES_PARDr[2] & SNES_PARDr[1];
wire [23:0] SNES_ADDR = (SNES_ADDRr[5] & SNES_ADDRr[4]);
wire free_slot = SNES_cycle_end | free_strobe;
wire ROM_HIT;
assign DCM_RST=0;
always @(posedge CLK2) begin
free_strobe <= 1'b0;
if(SNES_cycle_start) free_strobe <= ~ROM_HIT;
end
always @(posedge CLK2) begin
SNES_PARDr <= {SNES_PARDr[6:0], SNES_PARD_IN};
SNES_READr <= {SNES_READr[6:0], SNES_READ_IN};
SNES_WRITEr <= {SNES_WRITEr[6:0], SNES_WRITE_IN};
SNES_CPU_CLKr <= {SNES_CPU_CLKr[6:0], SNES_CPU_CLK_IN};
SNES_ADDRr[5] <= SNES_ADDRr[4];
SNES_ADDRr[4] <= SNES_ADDRr[3];
SNES_ADDRr[3] <= SNES_ADDRr[2];
SNES_ADDRr[2] <= SNES_ADDRr[1];
SNES_ADDRr[1] <= SNES_ADDRr[0];
SNES_ADDRr[0] <= SNES_ADDR_IN;
end
parameter ST_IDLE = 5'b00001;
parameter ST_MCU_RD_ADDR = 5'b00010;
parameter ST_MCU_RD_END = 5'b00100;
parameter ST_MCU_WR_ADDR = 5'b01000;
parameter ST_MCU_WR_END = 5'b10000;
parameter SNES_DEAD_TIMEOUT = 17'd88000; // 1ms
parameter ROM_CYCLE_LEN = 4'd7;
reg [4:0] STATE;
initial STATE = ST_IDLE;
assign DSPX_SNES_DATA_IN = BUS_DATA;
assign SRTC_SNES_DATA_IN = BUS_DATA[3:0];
assign MSU_SNES_DATA_IN = BUS_DATA;
assign BSX_SNES_DATA_IN = BUS_DATA;
sd_dma snes_sd_dma(
.CLK(CLK2),
.SD_DAT(SD_DAT),
.SD_CLK(SD_CLK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
.DBG_cyclecnt(SD_DMA_DBG_cyclecnt),
.DBG_clkcnt(SD_DMA_DBG_clkcnt)
);
wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
dac snes_dac(
.clkin(CLK2),
.sysclk(SNES_SYSCLK),
.mclk(DAC_MCLK),
.lrck(DAC_LRCK),
.sdout(DAC_SDOUT),
.we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
.pgm_address(dac_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.DAC_STATUS(DAC_STATUS),
.volume(msu_volumerq_out),
.vol_latch(msu_volume_latch_out),
.play(dac_play),
.reset(dac_reset)
);
srtc snes_srtc (
.clkin(CLK2),
.addr_in(SNES_ADDR[0]),
.data_in(SRTC_SNES_DATA_IN),
.data_out(SRTC_SNES_DATA_OUT),
.rtc_data_in(rtc_data),
.enable(srtc_enable),
.rtc_data_out(srtc_rtc_data_out),
.reg_oe_falling(SNES_RD_start),
.reg_oe_rising(SNES_RD_end),
.reg_we_rising(SNES_WR_end),
.rtc_we(srtc_rtc_we),
.reset(srtc_reset),
.srtc_state(DBG_srtc_state),
.srtc_reg_we_rising(DBG_srtc_we_rising),
.srtc_rtc_ptr(DBG_srtc_ptr),
.srtc_we_sreg(DBG_srtc_we_sreg)
);
rtc snes_rtc (
.clkin(CLKIN),
.rtc_data(rtc_data),
.rtc_data_in(rtc_data_in),
.pgm_we(rtc_pgm_we),
.rtc_data_in1(srtc_rtc_data_out),
.we1(srtc_rtc_we)
);
msu snes_msu (
.clkin(CLK2),
.enable(msu_enable),
.pgm_address(msu_write_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1),
.reg_addr(SNES_ADDR[2:0]),
.reg_data_in(MSU_SNES_DATA_IN),
.reg_data_out(MSU_SNES_DATA_OUT),
.reg_oe_falling(SNES_RD_start),
.reg_oe_rising(SNES_RD_end),
.reg_we_rising(SNES_WR_end),
.status_out(msu_status_out),
.volume_out(msu_volumerq_out),
.volume_latch_out(msu_volume_latch_out),
.addr_out(msu_addressrq_out),
.track_out(msu_trackrq_out),
.status_reset_bits(msu_status_reset_bits),
.status_set_bits(msu_status_set_bits),
.status_reset_we(msu_status_reset_we),
.msu_address_ext(msu_ptr_addr),
.msu_address_ext_write(msu_addr_reset),
.DBG_msu_reg_oe_rising(DBG_msu_reg_oe_rising),
.DBG_msu_reg_oe_falling(DBG_msu_reg_oe_falling),
.DBG_msu_reg_we_rising(DBG_msu_reg_we_rising),
.DBG_msu_address(DBG_msu_address),
.DBG_msu_address_ext_write_rising(DBG_msu_address_ext_write_rising)
);
bsx snes_bsx(
.clkin(CLK2),
.use_bsx(use_bsx),
.pgm_we(bsx_regs_reset_we),
.snes_addr(SNES_ADDR),
.reg_data_in(BSX_SNES_DATA_IN),
.reg_data_out(BSX_SNES_DATA_OUT),
.reg_oe_falling(SNES_RD_start),
.reg_oe_rising(SNES_RD_end),
.reg_we_rising(SNES_WR_end),
.regs_out(bsx_regs),
.reg_reset_bits(bsx_regs_reset_bits),
.reg_set_bits(bsx_regs_set_bits),
.data_ovr(bsx_data_ovr),
.flash_writable(IS_FLASHWR),
.rtc_data(rtc_data[59:0]),
.bs_page_out(bs_page), // support only page 0000-03ff
.bs_page_enable(bs_page_enable),
.bs_page_offset(bs_page_offset)
);
spi snes_spi(
.clk(CLK2),
.MOSI(SPI_MOSI),
.MISO(SPI_MISO),
.SSEL(SPI_SS),
.SCK(SPI_SCK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.endmessage(spi_endmessage),
.startmessage(spi_startmessage),
.input_data(spi_input_data),
.byte_cnt(spi_byte_cnt),
.bit_cnt(spi_bit_cnt)
);
wire [15:0] dsp_feat;
upd77c25 snes_dspx (
.DI(DSPX_SNES_DATA_IN),
.DO(DSPX_SNES_DATA_OUT),
.A0(DSPX_A0),
.enable(dspx_enable),
.reg_oe_falling(SNES_RD_start),
.reg_oe_rising(SNES_RD_end),
.reg_we_rising(SNES_WR_end),
.RST(~dspx_reset),
.CLK(CLK2),
.PGM_WR(dspx_pgm_we),
.PGM_DI(dspx_pgm_data),
.PGM_WR_ADDR(dspx_pgm_addr),
.DAT_WR(dspx_dat_we),
.DAT_DI(dspx_dat_data),
.DAT_WR_ADDR(dspx_dat_addr),
.DP_enable(dspx_dp_enable),
.DP_ADDR(SNES_ADDR[10:0]),
.dsp_feat(dsp_feat)
);
reg [7:0] MCU_DINr;
wire [7:0] MCU_DOUT;
wire [31:0] cheat_pgm_data;
wire [7:0] cheat_data_out;
wire [2:0] cheat_pgm_idx;
mcu_cmd snes_mcu_cmd(
.clk(CLK2),
.snes_sysclk(SNES_SYSCLK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.mcu_mapper(MAPPER),
.mcu_write(MCU_WRITE),
.mcu_data_in(MCU_DINr),
.mcu_data_out(MCU_DOUT),
.spi_byte_cnt(spi_byte_cnt),
.spi_bit_cnt(spi_bit_cnt),
.spi_data_out(spi_input_data),
.addr_out(MCU_ADDR),
.saveram_mask_out(SAVERAM_MASK),
.rom_mask_out(ROM_MASK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_TGT(SD_DMA_TGT),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
.dac_addr_out(dac_addr),
.DAC_STATUS(DAC_STATUS),
.dac_play_out(dac_play),
.dac_reset_out(dac_reset),
.msu_addr_out(msu_write_addr),
.MSU_STATUS(msu_status_out),
.msu_status_reset_out(msu_status_reset_bits),
.msu_status_set_out(msu_status_set_bits),
.msu_status_reset_we(msu_status_reset_we),
.msu_volumerq(msu_volumerq_out),
.msu_addressrq(msu_addressrq_out),
.msu_trackrq(msu_trackrq_out),
.msu_ptr_out(msu_ptr_addr),
.msu_reset_out(msu_addr_reset),
.bsx_regs_set_out(bsx_regs_set_bits),
.bsx_regs_reset_out(bsx_regs_reset_bits),
.bsx_regs_reset_we(bsx_regs_reset_we),
.rtc_data_out(rtc_data_in),
.rtc_pgm_we(rtc_pgm_we),
.srtc_reset(srtc_reset),
.dspx_pgm_data_out(dspx_pgm_data),
.dspx_pgm_addr_out(dspx_pgm_addr),
.dspx_pgm_we_out(dspx_pgm_we),
.dspx_dat_data_out(dspx_dat_data),
.dspx_dat_addr_out(dspx_dat_addr),
.dspx_dat_we_out(dspx_dat_we),
.dspx_reset_out(dspx_reset),
.featurebits_out(featurebits),
.mcu_rrq(MCU_RRQ),
.mcu_wrq(MCU_WRQ),
.mcu_rq_rdy(MCU_RDY),
.region_out(mcu_region),
.snescmd_addr_out(snescmd_addr_mcu),
.snescmd_we_out(snescmd_we_mcu),
.snescmd_data_out(snescmd_data_out_mcu),
.snescmd_data_in(snescmd_data_in_mcu),
.cheat_pgm_idx_out(cheat_pgm_idx),
.cheat_pgm_data_out(cheat_pgm_data),
.cheat_pgm_we_out(cheat_pgm_we),
.dsp_feat_out(dsp_feat)
);
wire [7:0] DCM_STATUS;
// dcm1: dfs 4x
my_dcm snes_dcm(
.CLKIN(CLKIN),
.CLKFX(CLK2),
.LOCKED(DCM_LOCKED),
.RST(DCM_RST),
.STATUS(DCM_STATUS)
);
address snes_addr(
.CLK(CLK2),
.MAPPER(MAPPER),
.featurebits(featurebits),
.SNES_ADDR(SNES_ADDR), // requested address from SNES
.SNES_PA(SNES_PA),
.ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
.ROM_HIT(ROM_HIT), // want to access RAM0
.IS_SAVERAM(IS_SAVERAM),
.IS_ROM(IS_ROM),
.IS_WRITABLE(IS_WRITABLE),
.SAVERAM_MASK(SAVERAM_MASK),
.ROM_MASK(ROM_MASK),
//MSU-1
.msu_enable(msu_enable),
//BS-X
.use_bsx(use_bsx),
.bsx_regs(bsx_regs),
.bs_page_offset(bs_page_offset),
.bs_page(bs_page),
.bs_page_enable(bs_page_enable),
.bsx_tristate(bsx_tristate),
//SRTC
.srtc_enable(srtc_enable),
//uPD77C25
.dspx_enable(dspx_enable),
.dspx_dp_enable(dspx_dp_enable),
.dspx_a0(DSPX_A0),
.r213f_enable(r213f_enable),
.snescmd_enable(snescmd_enable)
);
cheat snes_cheat(
.clk(CLK2),
.SNES_ADDR(SNES_ADDR),
.SNES_DATA(SNES_DATA),
.SNES_reset_strobe(SNES_reset_strobe),
.snescmd_wr_strobe(SNES_WR_end & snescmd_enable),
.SNES_cycle_start(SNES_RD_start),
.pgm_idx(cheat_pgm_idx),
.pgm_we(cheat_pgm_we),
.pgm_in(cheat_pgm_data),
.data_out(cheat_data_out),
.cheat_hit(cheat_hit),
.snescmd_unlock(snescmd_unlock)
);
wire [7:0] snescmd_dout;
reg [7:0] r213fr;
reg r213f_forceread;
reg [2:0] r213f_delay;
reg [1:0] r213f_state;
initial r213fr = 8'h55;
initial r213f_forceread = 0;
initial r213f_state = 2'b01;
initial r213f_delay = 3'b000;
assign SNES_DATA = (r213f_enable & ~SNES_PARD & ~r213f_forceread) ? r213fr
:(~SNES_READ ^ (r213f_forceread & r213f_enable & ~SNES_PARD))
? (srtc_enable ? SRTC_SNES_DATA_OUT
:dspx_enable ? DSPX_SNES_DATA_OUT
:dspx_dp_enable ? DSPX_SNES_DATA_OUT
:msu_enable ? MSU_SNES_DATA_OUT
:bsx_data_ovr ? BSX_SNES_DATA_OUT
:(snescmd_unlock & snescmd_enable) ? snescmd_dout
:cheat_hit ? cheat_data_out
:(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])
) : 8'bZ;
reg [3:0] ST_MEM_DELAYr;
reg MCU_RD_PENDr = 0;
reg MCU_WR_PENDr = 0;
reg [23:0] ROM_ADDRr;
reg RQ_MCU_RDYr;
initial RQ_MCU_RDYr = 1'b1;
assign MCU_RDY = RQ_MCU_RDYr;
wire MCU_WR_HIT = |(STATE & ST_MCU_WR_ADDR);
wire MCU_RD_HIT = |(STATE & ST_MCU_RD_ADDR);
wire MCU_HIT = MCU_WR_HIT | MCU_RD_HIT;
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : MCU_HIT ? ROM_ADDRr[23:1] : MAPPED_SNES_ADDR[23:1];
assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : MCU_HIT ? ROM_ADDRr[0] : MAPPED_SNES_ADDR[0];
reg[17:0] SNES_DEAD_CNTr;
initial SNES_DEAD_CNTr = 0;
always @(posedge CLK2) begin
if(MCU_RRQ) begin
MCU_RD_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(MCU_WRQ) begin
MCU_WR_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
MCU_RD_PENDr <= 1'b0;
MCU_WR_PENDr <= 1'b0;
RQ_MCU_RDYr <= 1'b1;
end
end
always @(posedge CLK2) begin
if(~SNES_CPU_CLKr[1]) SNES_DEAD_CNTr <= SNES_DEAD_CNTr + 1;
else SNES_DEAD_CNTr <= 17'h0;
end
always @(posedge CLK2) begin
SNES_reset_strobe <= 1'b0;
if(SNES_CPU_CLKr[1]) begin
SNES_DEADr <= 1'b0;
if(SNES_DEADr) SNES_reset_strobe <= 1'b1;
end
else if(SNES_DEAD_CNTr > SNES_DEAD_TIMEOUT) SNES_DEADr <= 1'b1;
end
always @(posedge CLK2) begin
if(SNES_DEADr & SNES_CPU_CLKr[1]) STATE <= ST_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
else
case(STATE)
ST_IDLE: begin
STATE <= ST_IDLE;
if(free_slot | SNES_DEADr) begin
if(MCU_RD_PENDr) begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
else if(MCU_WR_PENDr) begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
end
end
ST_MCU_RD_ADDR: begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_RD_END;
MCU_DINr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
end
ST_MCU_WR_ADDR: begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_WR_END;
end
ST_MCU_RD_END, ST_MCU_WR_END: begin
STATE <= ST_IDLE;
end
endcase
end
always @(posedge CLK2) begin
if(SNES_cycle_end) r213f_forceread <= 1'b1;
else if(SNES_PARD_start & r213f_enable) begin
r213f_delay <= 3'b000;
r213f_state <= 2'b10;
end else if(r213f_state == 2'b10) begin
r213f_delay <= r213f_delay - 1;
if(r213f_delay == 3'b000) begin
r213f_forceread <= 1'b0;
r213f_state <= 2'b01;
r213fr <= {SNES_DATA[7:5], mcu_region, SNES_DATA[3:0]};
end
end
end
reg MCU_WRITE_1;
always @(posedge CLK2) MCU_WRITE_1<= MCU_WRITE;
assign ROM_DATA[7:0] = ROM_ADDR0
?(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: (ROM_HIT & ~SNES_WRITE) ? SNES_DATA
: MCU_WR_HIT ? MCU_DOUT : 8'bZ
)
:8'bZ;
assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
:(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: (ROM_HIT & ~SNES_WRITE) ? SNES_DATA
: MCU_WR_HIT ? MCU_DOUT
: 8'bZ
);
assign ROM_WE = SD_DMA_TO_ROM
?MCU_WRITE
: (ROM_HIT & (IS_WRITABLE | IS_FLASHWR) & SNES_CPU_CLK) ? SNES_WRITE
: MCU_WR_HIT ? 1'b0
: 1'b1;
// OE always active. Overridden by WE when needed.
assign ROM_OE = 1'b0;
assign ROM_CE = 1'b0;
assign ROM_BHE = ROM_ADDR0;
assign ROM_BLE = !ROM_ADDR0;
wire snoop_4200_enable = {SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h04200;
assign SNES_DATABUS_OE = (dspx_enable | dspx_dp_enable) ? 1'b0 :
msu_enable ? 1'b0 :
bsx_data_ovr ? (SNES_READ & SNES_WRITE) :
srtc_enable ? (SNES_READ & SNES_WRITE) :
snescmd_enable ? ((~snescmd_unlock | SNES_READ) & SNES_WRITE) :
bs_page_enable ? (SNES_READ) :
r213f_enable & !SNES_PARD ? 1'b0 :
snoop_4200_enable ? SNES_WRITE :
((IS_ROM & SNES_CS)
|(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR)
|(SNES_READ & SNES_WRITE)
| bsx_tristate
);
assign SNES_DATABUS_DIR = (!SNES_READ | (!SNES_PARD & (r213f_enable)))
? 1'b1 ^ (r213f_forceread & r213f_enable & ~SNES_PARD)
: 1'b0;
assign SNES_IRQ = 1'b0;
assign p113_out = 1'b0;
wire [8:0] snescmd_addra = snoop_4200_enable ? 9'h1fa : SNES_ADDR[8:0];
snescmd_buf snescmd (
.clka(CLK2), // input clka
.wea(SNES_WR_end & ((snescmd_unlock & snescmd_enable) | snoop_4200_enable)), // input [0 : 0] wea
.addra(snescmd_addra), // input [8 : 0] addra
.dina(SNES_DATA), // input [7 : 0] dina
.douta(snescmd_dout), // output [7 : 0] douta
.clkb(CLK2), // input clkb
.web(snescmd_we_mcu), // input [0 : 0] web
.addrb(snescmd_addr_mcu), // input [8 : 0] addrb
.dinb(snescmd_data_out_mcu), // input [7 : 0] dinb
.doutb(snescmd_data_in_mcu) // output [7 : 0] doutb
);
/*
wire [35:0] CONTROL0;
chipscope_icon icon (
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
);
chipscope_ila ila (
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(CLK2), // IN
.TRIG0(SNES_ADDR), // IN BUS [23:0]
.TRIG1(SNES_DATA), // IN BUS [7:0]
.TRIG2({SNES_READ, SNES_WRITE, SNES_CPU_CLK, SNES_cycle_start, SNES_cycle_end, SNES_DEADr, MCU_RRQ, MCU_WRQ, MCU_RDY, ROM_WEr, ROM_WE, ROM_DOUT_ENr, ROM_SA, DBG_mcu_nextaddr, SNES_DATABUS_DIR, SNES_DATABUS_OE}), // IN BUS [15:0]
.TRIG3({bsx_data_ovr, r213f_forceread, r213f_enable, SNES_PARD, spi_cmd_ready, spi_param_ready, spi_input_data, SD_DAT}), // IN BUS [17:0]
.TRIG4(ROM_ADDRr), // IN BUS [23:0]
.TRIG5(ROM_DATA), // IN BUS [15:0]
.TRIG6(MCU_DINr), // IN BUS [7:0]
.TRIG7(spi_byte_cnt[3:0])
);
/*
ila_srtc ila (
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(CLK2), // IN
.TRIG0(SD_DMA_DBG_cyclecnt), // IN BUS [23:0]
.TRIG1(SD_DMA_SRAM_DATA), // IN BUS [7:0]
.TRIG2({SPI_SCK, SPI_MOSI, SPI_MISO, spi_cmd_ready, SD_DMA_SRAM_WE, SD_DMA_EN, SD_CLK, SD_DAT, SD_DMA_NEXTADDR, SD_DMA_STATUS, 3'b000}), // IN BUS [15:0]
.TRIG3({spi_cmd_data, spi_param_data}), // IN BUS [17:0]
.TRIG4(ROM_ADDRr), // IN BUS [23:0]
.TRIG5(ROM_DATA), // IN BUS [15:0]
.TRIG6(MCU_DINr), // IN BUS [7:0]
.TRIG7(ST_MEM_DELAYr)
);
*/
endmodule
|
Require Import FcEtt.sigs.
Require Import FcEtt.fc_dec_fuel.
Require Import FcEtt.fc_dec_aux.
Require Import FcEtt.imports.
Require Export FcEtt.ett_inf_cs.
Require Import FcEtt.ett_ind.
Require Export FcEtt.fc_invert.
Require Import FcEtt.dep_prog.
Require Import FcEtt.toplevel.
Require Import FcEtt.fc_get.
Require Import FcEtt.fc_context_fv.
Module fc_dec_fun (wf : fc_wf_sig) (weak : fc_weak_sig) (subst : fc_subst_sig) (unique: fc_unique_sig).
Module invert := fc_invert wf weak subst.
Module fuel := fc_dec_fuel wf weak subst unique.
Module aux := fc_dec_aux wf weak subst unique.
Module get := fc_get wf weak subst unique.
Import fuel aux unique wf subst invert get.
Unset Implicit Arguments.
Ltac obtacpre :=
intros; simpl in *.
Ltac obtacsolve :=
intros; simpl in *; try solve [ok].
Lemma An_IsoConv': ∀ (G : context) (D : available_props)
(a1 a2 A a1' a2' B : tm) phi1 phi2 (g : co),
phi1 = (Eq a1 a2 A) →
phi2 = (Eq a1' a2' B) →
AnnDefEq G D g A B →
AnnPropWff G phi1 →
AnnPropWff G phi2 →
erase_tm a1 = erase_tm a1' →
erase_tm a2 = erase_tm a2' →
AnnIso G D (g_IsoConv phi1 phi2 g) phi1 phi2.
Proof.
intros.
subst phi1 phi2.
eauto.
Qed.
(* More pratical version of these lemma (both forms are useful, though) *)
Lemma get_tpg_correct' : ∀ {G : context} {a A : tm},
AnnTyping G a A → A = get_tpg G a.
Proof.
move => G a A tpg.
by rewrite (@get_tpg_correct _ _ _(get_tpg G a) tpg _).
Defined.
Lemma get_deq_correct' : ∀ {G : context} {D : available_props} {g : co} {A B},
AnnDefEq G D g A B → get_deq G g = (A, B).
Proof.
move => G ? g A B deq.
have eq: get_deq G g = (fst (get_deq G g), snd (get_deq G g)) by destruct (get_deq G g).
by move: (@get_deq_correct _ _ _ _ _ (fst (get_deq G g)) (snd (get_deq G g)) deq eq) => [-> ->].
Defined.
Lemma get_iso_correct' : ∀ {G : context} {D : available_props} {g : co} {phi1 phi2 : constraint}, AnnIso G D g phi1 phi2 → get_iso G g = (phi1, phi2).
Proof.
move => G ? g phi1 phi2 iso.
have eq: get_iso G g = (fst (get_iso G g), snd (get_iso G g)) by destruct (get_iso G g).
by move: (@get_iso_correct _ _ _ _ _ (fst (get_iso G g)) (snd (get_iso G g)) iso eq) => [-> ->].
Defined.
(**** Tactics ****)
(* TODO: reorganize the tactics, and move the ones which don't belong here *)
(* FIXME: that may be defined in fc_dec_fun *)
Ltac clear_annoying :=
repeat match goal with
| [H: <<_>> = _ |- _ ] => clear H
| [H: <<_, _>> = _ |- _ ] => clear H
| [H: !! = _ |- _ ] => clear H
| [H: yeah = _ |- _ ] => clear H
| [H: nope = _ |- _ ] => clear H
| [ H : !! = _ |- _ ] => clear H
| [ H : _ + { _ } |- _ ] => clear H
| [ H : { _ } + { _ } |- _ ] => clear H
| [ H : { _ | _} + { _ } |- _ ] => clear H
| [ H : { _, _ | _} + { _ } |- _ ] => clear H
end.
Ltac intro_uniq_full H :=
match type of H with
| AnnTyping ?G ?a ?A =>
let x := fresh "u" in
move : (@AnnTyping_unique G a A H) => x;
(* Apply uniqueness to other hyps about the same term (and ctx) and discard them *)
repeat match goal with
| [H' : AnnTyping G a ?A' |- _ ] => move: (x _ H') => ?; wrap_hyp H'
end
| AnnDefEq ?G ?L ?g ?A1 ?A2 =>
let x := fresh "u" in
move : (@AnnDefEq_unique G L g A1 A2 H) => x;
(* Apply uniqueness to other hyps about the same term (and ctx) and discard them *)
repeat match goal with
| [H' : AnnDefEq G L g ?A1' ?A2' |- _ ] => move: (x _ _ H') => ?; wrap_hyp H'
end
| AnnIso ?G ?L ?g ?phi1 ?phi2 =>
let x := fresh "u" in
move : (@AnnIso_unique G L g phi1 phi2 H) => x;
(* Apply uniqueness to other hyps about the same term (and ctx) and discard them *)
repeat match goal with
| [H' : AnnIso G L g ?phi1' ?phi2' |- _ ] => move: (x _ _ H') => ?; wrap_hyp H'
end
end.
(* Apply uniqueness of type to existing typing hyps *)
Ltac auto_uniq_full :=
revert_all_with intro_uniq_full; intros; pcess_hyps.
Ltac terminator := auto_uniq_full; subst_forall; subst; cbn; pcess_hyps;
(* FIXME: eauto db version: basic_nosolve_n 3 *)
(* FIXME: eauto doesn't (always, at least) use the typing constructors, while in theory it should... *)
try solve [try econstructor; intuition (subst; eauto 3) | intuition (subst; eauto 3 with smart_cons_exists)].
Ltac hacky :=
do 3 (
intros;
(*
repeat match goal with
| [ p : tm * tm |- _ ] => destruct p; cbn in *
end; *)
try(
try (multimatch goal with
| [ |- ¬ _ ] => let H := fresh in intro H; inversion H; terminator
| _ => idtac
end);
try (multimatch goal with
| [ H : ¬ _ |- _ ] => solve [edestruct H; terminator]
| [ H : forall _, ¬ _ |- _ ] => solve [edestruct H; terminator]
| [ H : forall _ _, ¬ _ |- _ ] => solve [edestruct H; terminator]
end); terminator)).
(* Cleanup tactics
TODO: do we want them here or elsewhere? *)
Ltac clearbodies :=
repeat match goal with
| [ H := _ : _ |- _] => clearbody H
end.
(* TODO: should be in tactics.v *)
Ltac clearbodies' :=
repeat match goal with
| [ x := ?bdy : _ |- _] =>
move: (eq_refl x);
rewrite -{2}[x]/bdy;
clearbody x;
let eqname := fresh "eq" x in
move => eqname
end.
(* Ugly to have to grab them by their types, but we can't refer to their names (even after the definitions) *)
Ltac clean_fun :=
match goal with
| [
AnnTyping_dec : Tactics.fix_proto (∀ (G : context) (t : tm), fuel_tpg t → AnnCtx G → {T : tm | AnnTyping G t T} + {(∀ T : tm, ¬ AnnTyping G t T)}),
AnnPropWff_dec : Tactics.fix_proto (∀ (G : context) (phi : constraint), fuel_pwf phi → AnnCtx G → {AnnPropWff G phi} + {¬ AnnPropWff G phi}),
AnnDefEq_dec : Tactics.fix_proto (∀ (G : context) (S : available_props) (g : co), fuel_deq g → AnnCtx G → {A, B | AnnDefEq G S g A B} + {(∀ A B : tm, ¬ AnnDefEq G S g A B)}),
AnnIso_dec : Tactics.fix_proto (∀ (G : context) (S : available_props) (g : co), fuel_iso g → AnnCtx G → {phi1, phi2 | AnnIso G S g phi1 phi2} + {(∀ phi1 phi2 : constraint, ¬ AnnIso G S g phi1 phi2)})
|- _ ] => clear AnnTyping_dec AnnPropWff_dec AnnDefEq_dec AnnIso_dec
end.
Ltac clear_sums :=
repeat match goal with
| [ H : !! = _ |- _ ] => clear H
| [ H : _ + { _ } |- _ ] => clear H
| [ H : { _ } + { _ } |- _ ] => clear H
end.
Ltac cleanup_param cbodies sbst:=
clear_annoying;
intros; simpl in *;
cbodies;
try solve [ok];
try clean_fun;
clear_sums;
sbst. (* FIXME: for some reason, that subst breaks clear_fun if placed before it *)
Ltac cleanup := cleanup_param clearbodies subst.
Ltac cleanup' := cleanup_param clearbodies' idtac.
Obligation Tactic := try solve [hacky].
(* We need an unfueled version for AnnIso_dec - in that case, we have the subterms and a typing for them (by regularity), but no *fuel* *)
Program Definition AnnPropWff_dec' (G: context) (a b A : tm) (A' B': tm) (H : AnnCtx G)
(pA: AnnTyping G a A') (pB: AnnTyping G b B') : {AnnPropWff G (Eq a b A)} + {¬ AnnPropWff G (Eq a b A)} :=
tm_eq_dec A A' >-->
tm_eq_dec (erase A) (erase B') >-->
yeah.
Obligation Tactic := obtacpre; first [match goal with [|- tm] => idtac end | eassumption].
(** A system FC development wouldn't be right without a good, Haskell-style code. So please, enjoy. **)
(* Naming scheme: fX is the name of the fuel for X *)
Program Fixpoint AnnTyping_dec (G : context) (t : tm) (fuel : fuel_tpg t) (H : AnnCtx G) {struct fuel} : {T : tm | AnnTyping G t T } + {(forall T, ¬ AnnTyping G t T)} :=
match fuel with
| FT_Star => << a_Star >>
| FT_Var_f x =>
A <- binds_dec_tm x G;
<< A >>
| FT_Pi rho A B fB fA =>
let (x, p) := atom_fresh (dom G \u fv_tm_tm_tm B) in
KA <- AnnTyping_dec G A fA _;
tm_eq_dec KA a_Star >--->
KB <- AnnTyping_dec ([(x, Tm A)] ++ G) (open_tm_wrt_tm B (a_Var_f x)) (fB x _) _;
tm_eq_dec KB a_Star >--->
<< a_Star >>
| FT_Abs rho a A fa fA =>
(* (∀ x : atom, ¬ x `in` L → Typing ([(x, Tm A)] ++ G) (open_tm_wrt_tm a (a_Var_f x)) (open_tm_wrt_tm B (a_Var_f x))) *)
let (x, p) := atom_fresh (dom G \u fv_tm_tm_tm a) in
KA <- AnnTyping_dec G A fA _;
tm_eq_dec KA a_Star >--->
B <- AnnTyping_dec ([(x, Tm A)] ++ G) (open_tm_wrt_tm a (a_Var_f x)) (fa x _) _;
RhoCheck_erase_dec rho x (open_tm_wrt_tm a (a_Var_f x)) _ >--->
<< a_Pi rho A (close_tm_wrt_tm x B )>>
| FT_App rho b a fb fa =>
A <- AnnTyping_dec G a fa _;
Tf <- AnnTyping_dec G b fb _;
match Tf with
| a_Pi rho' A' B =>
tm_eq_dec A' A >--->
rho_eq_dec rho rho' >---> << open_tm_wrt_tm B a >>
| _ => !!
end
| FT_Conv a g fa fg =>
A <- AnnTyping_dec G a fa _;
A' & B <- AnnDefEq_dec G (dom G) g fg _;
let K := get_tpg G B in
(* K <- AnnTyping_dec G B _ _; *)
tm_eq_dec K a_Star >--->
tm_eq_dec A A' >--->
<< B >>
| FT_CApp b g fb fg =>
TB <- AnnTyping_dec G b fb _ ;
A1' & A2' <- AnnDefEq_dec G (dom G) g fg _;
match TB with
| (a_CPi (Eq A1 A2 K) B) =>
tm_eq_dec A1 A1' >--->
tm_eq_dec A2 A2' >--->
<< open_tm_wrt_co B g >>
| _ => !!
end
(* | FT_Const T =>
K <- binds_dec_cs T an_toplevel;
(@DataTy_Star_dec K) _ >--->
<< K >> *)
| FT_CPi phi B fB fphi =>
AnnPropWff_dec G phi fphi _ >--->
let (c, p) := atom_fresh (dom G \u fv_co_co_tm B) in
KB <- AnnTyping_dec ([(c, Co phi)] ++ G) (open_tm_wrt_co B (g_Var_f c)) (fB c _) _;
tm_eq_dec KB a_Star >--->
<< a_Star >>
| FT_CAbs a phi fa fphi =>
AnnPropWff_dec G phi fphi _ >--->
let (c, p) := atom_fresh (dom G \u fv_co_co_constraint phi \u fv_co_co_tm a) in
Bc <- AnnTyping_dec ((c ~ Co phi ) ++ G) (open_tm_wrt_co a (g_Var_f c)) (fa c _) _;
<< a_CPi phi (close_tm_wrt_co c Bc) >>
(* Erased language side: not typable in the annotated *)
| FT_Const T => !!
| FT_UAbs _ _ => !!
| FT_UCAbs _ => !!
| FT_Bullet => !!
| FT_Var_b _ => !!
(* | a_FamApp _ _ => !! *)
| FT_DataCon _ => !!
| FT_Case _ _ => !!
| FT_Fam F =>
a & A <- binds_dec_ax F an_toplevel;
<< A >>
end
with AnnPropWff_dec (G: context) (phi : constraint) (fuel : fuel_pwf phi)
(H : AnnCtx G) {struct fuel} : {AnnPropWff G phi} + {¬ AnnPropWff G phi} :=
match fuel with
| FP_fuel_pwf a b K fa fb =>
Ka <-- AnnTyping_dec G a fa _;
Kb <-- AnnTyping_dec G b fb _;
tm_eq_dec K Ka >-->
tm_eq_dec (erase K) (erase Kb) >--> yeah
end
with AnnDefEq_dec (G: context) (S : available_props) (g : co) (fuel : fuel_deq g)
(H: AnnCtx G) {struct fuel} : {A, B | AnnDefEq G S g A B} + {(forall A B, ¬ AnnDefEq G S g A B)} :=
match fuel with
| FD_Assn c =>
in_dec c S >--->
AB & K <- binds_dec_co c G;
<< fst AB, snd AB >>
| FD_Refl a fa =>
A <- AnnTyping_dec G a fa _;
<<a, a>>
| FD_Refl2 a b g fa fb fg =>
A <- AnnTyping_dec G a fa _;
B <- AnnTyping_dec G b fb _;
tm_eq_dec (erase_tm a) (erase_tm b) >--->
A' & B' <- AnnDefEq_dec G (dom G) g fg _;
tm_eq_dec A A' >--->
tm_eq_dec B B' >--->
<< a, b >>
| FD_Sym g fg =>
b & a <- AnnDefEq_dec G S g fg _;
<< a, b >>
| FD_Trans g1 g2 fg1 fg2 =>
a & c <- AnnDefEq_dec G S g1 fg1 _;
d & b <- AnnDefEq_dec G S g2 fg2 _;
tm_eq_dec c d >--->
<< a, b >>
| FD_Beta a1 a2 fa1 fa2 =>
A1 <- AnnTyping_dec G a1 fa1 _;
A2 <- AnnTyping_dec G a2 fa2 _;
tm_eq_dec (erase_tm A1) (erase_tm A2) >--->
@beta_dec (erase_tm a1) (erase_tm a2) _ >--->
<< a1, a2 >>
| FD_PiCong rho g1 g2 fg1 fg2 =>
A1 & A2 <- AnnDefEq_dec G S g1 fg1 _;
tm_eq_dec (get_tpg G A1) a_Star >--->
tm_eq_dec (get_tpg G A2) a_Star >--->
let (x, _) := atom_fresh (dom G \u fv_tm_tm_co g1 \u fv_tm_tm_co g2) in
B1x & B2x <- AnnDefEq_dec ([(x, Tm A1)] ++ G) S (open_co_wrt_tm g2 (a_Var_f x)) (fg2 x _) _;
let B1 := close_tm_wrt_tm x B1x in
let B2 := close_tm_wrt_tm x B2x in
let B3x := tm_subst_tm_tm (a_Conv (a_Var_f x) (g_Sym g1)) x B2x in
let B3 := close_tm_wrt_tm x B3x in
(* let B3 := close_tm_wrt_tm x (tm_subst_tm_tm (a_Conv (a_Var_f x) (g_Sym g1)) x B2x) in *)
tm_eq_dec (get_tpg ([(x, Tm A1)] ++ G) B1x) a_Star >--->
tm_eq_dec (get_tpg ([(x, Tm A1)] ++ G) B2x) a_Star >--->
tm_eq_dec (get_tpg ([(x, Tm A2)] ++ G) B3x) a_Star >--->
<< a_Pi rho A1 B1, a_Pi rho A2 B3 >>
| FD_AbsCong rho g1 g2 fg1 fg2 =>
A1 & A2 <- AnnDefEq_dec G S g1 fg1 _;
tm_eq_dec (get_tpg G A1) a_Star >--->
tm_eq_dec (get_tpg G A2) a_Star >--->
let (x, p) := atom_fresh (dom G \u fv_tm_tm_co g1 \u fv_tm_tm_co g2) in
B1x & B2x <- AnnDefEq_dec ([(x, Tm A1)] ++ G) S (open_co_wrt_tm g2 (a_Var_f x)) (fg2 x _) _;
let B1 := close_tm_wrt_tm x B1x in
let B2 := close_tm_wrt_tm x B2x in
let B3x := tm_subst_tm_tm (a_Conv (a_Var_f x) (g_Sym g1)) x B2x in
let B3 := close_tm_wrt_tm x B3x in
(* let B3 := close_tm_wrt_tm x (open_tm_wrt_tm B2 (a_Conv (a_Var_f x) (g_Sym g1))) in *)
(* let B3 := close_tm_wrt_tm x (tm_subst_tm_tm (a_Conv (a_Var_f x) (g_Sym g1)) x B2x) in *)
RhoCheck_erase_dec rho x B1x _ >--->
RhoCheck_erase_dec rho x B3x _ >--->
(* B <- AnnTyping_dec G (a_Abs rho A1 B2) _ _; *)
<< a_Abs rho A1 B1, a_Abs rho A2 B3 >>
| FD_AppCong g1 g2 rho fg1 fg2 =>
a1 & a2 <- AnnDefEq_dec G S g1 fg1 _;
b1 & b2 <- AnnDefEq_dec G S g2 fg2 _;
let Ta1 := get_tpg G a1 in
let Ta2 := get_tpg G a2 in
let Tb1 := get_tpg G b1 in
let Tb2 := get_tpg G b2 in
match Ta1, Ta2 with
| a_Pi rho1 A1 _, a_Pi rho2 A2 _ =>
tm_eq_dec A1 Tb1 >--->
tm_eq_dec A2 Tb2 >--->
rho_eq_dec rho rho1 >--->
rho_eq_dec rho rho2 >--->
<< a_App a1 rho b1, a_App a2 rho b2 >>
| _, _ => !!
end
| FD_CPiCong g1 g3 fg1 fg3 =>
phi1 & phi2 <- AnnIso_dec G S g1 fg1 _;
let (c, _) := atom_fresh (S \u dom G \u fv_co_co_co g1 \u fv_co_co_co g3) in
B1c & B2c <- AnnDefEq_dec ([(c, Co phi1)] ++ G) S (open_co_wrt_co g3 (g_Var_f c)) (fg3 c _) _;
let B1 := close_tm_wrt_co c B1c in
let B2 := close_tm_wrt_co c B2c in
let B3c := open_tm_wrt_co B2 (g_Cast (g_Var_f c) (g_Sym g1)) in
let B3 := close_tm_wrt_co c (B3c) in
tm_eq_dec (get_tpg ([(c,Co phi1)] ++ G) B1c) a_Star >--->
tm_eq_dec (get_tpg ([(c,Co phi2)] ++ G) B3c) a_Star >--->
tm_eq_dec (get_tpg ([(c,Co phi1)] ++ G) B2c) a_Star >--->
<< a_CPi phi1 B1, a_CPi phi2 B3 >>
| FD_CAbsCong g1 g3 g4 fg1 fg3 fg4 =>
phi1 & phi2 <- AnnIso_dec G S g1 fg1 _;
let (c, _) := atom_fresh (S \u dom G \u fv_co_co_co g1 \u fv_co_co_co g3) in
a1c & a2c <- AnnDefEq_dec ([(c, Co phi1)] ++ G) S (open_co_wrt_co g3 (g_Var_f c)) (fg3 c _) _;
let a1 := close_tm_wrt_co c a1c in
let a2 := close_tm_wrt_co c a2c in
let a3c := open_tm_wrt_co a2 (g_Cast (g_Var_f c) (g_Sym g1)) in
let a3 := close_tm_wrt_co c a3c in
let B1c := get_tpg ([(c, Co phi1)] ++ G) a1c in
let B3c := get_tpg ([(c, Co phi2)] ++ G) a3c in
CPi1 & CPi2 <- AnnDefEq_dec G (dom G) g4 fg4 _;
tm_eq_dec CPi1 (a_CPi phi1 (close_tm_wrt_co c B1c)) >--->
tm_eq_dec CPi2 (a_CPi phi2 (close_tm_wrt_co c B3c)) >--->
<< a_CAbs phi1 a1, a_CAbs phi2 a3 >>
| FD_CAppCong g1 g2 g3 fg1 fg2 fg3 =>
a1 & a2 <- AnnDefEq_dec G S g1 fg1 _;
b1 & b2 <- AnnDefEq_dec G (dom G) g2 fg2 _;
c1 & c2 <- AnnDefEq_dec G (dom G) g3 fg3 _;
let Ta1 := get_tpg G a1 in
let Ta2 := get_tpg G a2 in
match Ta1, Ta2 with
| a_CPi (Eq Ta11 Ta12 _) _, a_CPi (Eq Ta21 Ta22 _) _ =>
(* TODO: in theory, one would want to do a cons_eq_dec - but DeqEq_dec doesn't return the type *)
tm_eq_dec Ta11 b1 >--->
tm_eq_dec Ta12 b2 >--->
tm_eq_dec Ta21 c1 >--->
tm_eq_dec Ta22 c2 >--->
<< a_CApp a1 g2, a_CApp a2 g3 >>
| _, _ => !!
end
| FD_CPiSnd g1 g2 g3 fg1 fg2 fg3 =>
a1 & a2 <- AnnDefEq_dec G S g1 fg1 _;
a & a' <- AnnDefEq_dec G (dom G) g2 fg2 _;
b & b' <- AnnDefEq_dec G (dom G) g3 fg3 _;
match a1, a2 with
| a_CPi (Eq a_ a_' _) B1, a_CPi (Eq b_ b_' _) B2 =>
tm_eq_dec a a_ >--->
tm_eq_dec a' a_' >--->
tm_eq_dec b b_ >--->
tm_eq_dec b' b_' >--->
<< open_tm_wrt_co B1 g2, open_tm_wrt_co B2 g3 >>
| _, _ => !!
end
| FD_Cast g1 g2 fg1 fg2 =>
a & a' <- AnnDefEq_dec G S g1 fg1 _;
phi1 & phi2 <- AnnIso_dec G S g2 fg2 _;
match phi1, phi2 with
| Eq a_ a'_ _, Eq b b' _ =>
tm_eq_dec a a_ >--->
tm_eq_dec a' a'_ >--->
<< b, b' >>
end
| FD_PiFst g fg =>
T1 & T2 <- AnnDefEq_dec G S g fg _;
match T1, T2 with
| a_Pi rho1 A1 B1, a_Pi rho2 A2 B2 => rho_eq_dec rho1 rho2 >---> << A1, A2 >>
| _, _ => !!
end
| FD_PiSnd g1 g2 fg1 fg2 =>
T1 & T2 <- AnnDefEq_dec G S g1 fg1 _;
a1 & a2 <- AnnDefEq_dec G S g2 fg2 _;
(* A1 <- AnnTyping_dec G a1 _ _;
A2 <- AnnTyping_dec G a2 _ _; *)
let A1 := get_tpg G a1 in
let A2 := get_tpg G a2 in
match T1 with
| a_Pi rho A1' B1 =>
tm_eq_dec A1 A1' >--->
match T2 with
| a_Pi rho' A2' B2 =>
tm_eq_dec A2 A2' >--->
rho_eq_dec rho rho' >--->
<< open_tm_wrt_tm B1 a1, open_tm_wrt_tm B2 a2 >>
| _ => !!
end
| _ => !!
end
| FD_IsoSnd g fg =>
phi1 & phi2 <- AnnIso_dec G S g fg _;
match phi1, phi2 with
| (Eq _ _ A), (Eq _ _ B) => << A, B>>
end
| FD_Eta b fb =>
let (x, p) := atom_fresh (dom G \u fv_tm_tm_tm b) in
T <- AnnTyping_dec G b fb _;
match T with
| a_Pi Rel A B =>
<< a_Abs Rel A (close_tm_wrt_tm x (a_App b Rel (a_Var_f x))), b >>
| a_Pi Irrel A B =>
<< a_Abs Irrel A (close_tm_wrt_tm x (a_App b Irrel (a_Var_f x))), b >>
| a_CPi phi B =>
<< a_CAbs phi (close_tm_wrt_co x (a_CApp b (g_Var_f x))), b >>
| _ => !!
end
| FD_Left g1 g2 fg1 fg2 => !!
| FD_Right _ _ _ _ => !!
(* Left/Right. This doesn't work yet.
| FD_Left g1 g2 fg1 fg2 =>
s1 & s2 <- AnnDefEq_dec G S g1 fg1 _;
t1 & t2 <- AnnDefEq_dec G (dom G) g2 fg2 _ ;
match s1 with
| (a_App a1 Rel a2) =>
match s2 with
| (a_App a1' Rel a2') =>
match t1 with
| (a_Pi Rel A1 B1) =>
match t2 with
| (a_Pi Rel A2 B2) =>
path_dec a1 >--->
path_dec a1' >--->
let A := get_tpg G a1 in
let A' := get_tpg G a1' in
tm_eq_dec A (a_Pi Rel A1 B1) >--->
tm_eq_dec A' (a_Pi Rel A2 B2) >--->
<< a1 , a1' >>
| _ => !!
end
| _ => !!
end
| _ => !!
end
| _ => !!
end
(*
| (a_App a1 Irrel a2, a_App a1' Irrel a2', a_Pi Irrel A1 B1, a_Pi Irrel A2 B2) =>
let A := get_tpg G a1 in
let A' := get_tpg G a1' in
tm_eq_dec A (a_Pi Irrel A1 B1) >--->
tm_eq_dec A' (a_Pi Irrel A2 B2) >--->
<< a1 , a1' >>
| (a_CApp a1 a2, a_CApp a1' a2', a_CPi A1 B1, a_CPi A2 B2) =>
let A := get_tpg G a1 in
let A' := get_tpg G a1' in
tm_eq_dec A (a_CPi A1 B1) >--->
tm_eq_dec A' (a_CPi A2 B2) >--->
<< a1 , a1' >>
| _ => !!
end *)
| FD_Right g1 g2 fg1 fg2 =>
s1 & s2 <- AnnDefEq_dec G S g1 fg1 _;
t1 & t2 <- AnnDefEq_dec G (dom G) g2 fg2 _ ;
match (s1, s2, t1, t2) with
| (a_App a1 r1 a2, a_App a1' r2 a2', a_Pi r3 A1 B1, a_Pi r4 A2 B2) =>
let A := get_tpg G a1 in
let A' := get_tpg G a1' in
tm_eq_dec A (a_Pi r3 A1 B1) >--->
tm_eq_dec A' (a_Pi r4 A2 B2) >--->
rho_eq_dec r1 r2 >--->
rho_eq_dec r1 r3 >--->
rho_eq_dec r1 r4 >--->
<< a2 , a2' >>
| _ => !!
end
*)
(* Trivial cases *)
| FD_Triv => !!
| FD_Var_b _ => !!
| FD_CPiFst _ => !!
| FD_Cong _ _ _ => !!
| FD_IsoConv _ _ _ => !!
end
with AnnIso_dec (G: context) (S : available_props) (g : co) (fuel : fuel_iso g)
(H: AnnCtx G) {struct fuel} : {phi1, phi2 | AnnIso G S g phi1 phi2} + {(forall phi1 phi2, ¬ AnnIso G S g phi1 phi2)} :=
match fuel with
| FI_Cong g1 A g2 fg1 fg2 =>
A1 & A2 <- AnnDefEq_dec G S g1 fg1 _;
B1 & B2 <- AnnDefEq_dec G S g2 fg2 _;
AnnPropWff_dec' G A1 B1 A (get_tpg G A1) (get_tpg G B1) _ _ _ >--->
AnnPropWff_dec' G A2 B2 A (get_tpg G A2) (get_tpg G B2) _ _ _ >--->
<< Eq A1 B1 A, Eq A2 B2 A >>
| FI_CPiFst g fg =>
pi1 & pi2 <- AnnDefEq_dec G S g fg _;
match pi1, pi2 with
| a_CPi phi1 _, a_CPi phi2 _ =>
<< phi1, phi2 >>
| _, _ => !!
end
| FI_IsoSym g fg =>
phi2 & phi1 <- AnnIso_dec G S g fg _;
<< phi1, phi2 >>
| FI_IsoConv g phi1 phi2 fg fpwf1 fpwf2 =>
A' & B' <- AnnDefEq_dec G S g fg _;
AnnPropWff_dec G phi1 fpwf1 _ >--->
AnnPropWff_dec G phi2 fpwf2 _ >--->
match phi1, phi2 with
| Eq a1 a2 A, Eq a1' a2' B =>
tm_eq_dec (erase_tm a1) (erase_tm a1') >--->
tm_eq_dec (erase_tm a2) (erase_tm a2') >--->
tm_eq_dec A A' >--->
tm_eq_dec B B' >--->
<< phi1, phi2 >>
end
(* Non-iso coercions *)
| FI_Var_f c => !!
| FI_Var_b _ => !!
| FI_Refl a => !!
| FI_Refl2 a b g => !!
| FI_Trans g1 g2 => !!
| FI_Beta a1 a2 => !!
| FI_PiCong rho g1 g2 => !!
| FI_AbsCong _ _ _ => !!
| FI_AppCong g1 rho g2 => !!
| FI_CAbsCong _ _ _ => !!
| FI_CAppCong g1 g2 g3 => !!
| FI_PiFst g => !!
| FI_Cast g1 g2 => !!
| FI_PiSnd g1 g2 => !!
| FI_Triv => !!
| FI_CPiCong _ _ => !!
| FI_CPiSnd _ _ _ => !!
| FI_IsoSnd _ => !!
| FI_Eta _ => !!
| FI_Left _ _ => !!
| FI_Right _ _ => !!
end
.
(*
Solve Obligations of AnnDefEq_dec with obtacpre; first [match goal with [|- tm] => idtac end | eassumption].
*)
Obligation Tactic :=
obtacsolve.
(******** AnnDefEq_dec ********)
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
Defined.
Next Obligation.
hacky.
Defined.
(* An_EraseEq *)
Next Obligation.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
Defined.
(* An_Sym *)
Next Obligation.
hacky.
Defined.
Obligation Tactic := obtacpre.
Next Obligation.
eauto using An_Sym2.
Defined.
(* An_Trans *)
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
subst.
eauto using An_Trans2.
Defined.
(* An_Beta *)
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
move: lc_erase => [h0 _].
eapply h0.
move: (AnnTyping_lc wildcard'0) => [h1 _].
auto.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
cleanup.
Defined.
(* FIXME: in the following hard cases (Abs/CAbs/Pi/CPi -Cong), the code likely contains a lot of junk
It could also be made more concise, by using more ssr magic *)
(* TODO: this belongs in tactics *)
Ltac reg H :=
match type of H with
| AnnTyping _ ?a ?A =>
first
[ let tpgA := fresh "tpg" A in move: (AnnTyping_regularity H) => tpgA
| let tpgA := fresh "tpg" in move: (AnnTyping_regularity H) => tpgA]
| AnnDefEq _ _ ?g ?A ?B =>
let KA := fresh "K" A in
let KB := fresh "K" B in
let g' := fresh "g" in
let tpgA := fresh "tpg" A in
let tpgB := fresh "tpg" B in
(* let deqg' := fresh "deq" g' in *)
move: (AnnDefEq_regularity H) => [KA [KB [g' [tpgA [tpgB (* deqg' *) _]]]]]
(* FIXME: this is the same case than above, with less informative fresh names.
This is needed because fresh can fail (like, seriously?)
TODO: failproof version of fresh *)
| AnnDefEq _ _ ?g ?A ?B =>
let KA := fresh "K" in
let KB := fresh "K" in
let g' := fresh "g" in
let tpgA := fresh "tpg" in
let tpgB := fresh "tpg" in
(* let deqg' := fresh "deq" g' in *)
move: (AnnDefEq_regularity H) => [KA [KB [g' [tpgA [tpgB (* deqg' *) _]]]]]
| AnnIso _ _ ?g ?phi1 ?phi2 =>
let pwfp1 := fresh "pwf" phi1 in
let pwfp2 := fresh "pwf" phi2 in
move: (AnnIso_regularity H) => [pwfp1 pwfp2]
end.
Ltac cleanup_getcor :=
repeat match goal with
| [ _: get_tpg _ _ = get_tpg _ _ |- _ ] => fail
| [ eq: _ = get_tpg _ _ |- _ ] => symmetry in eq
end.
(* FIXME: same, should be elsewhere (fc_invert.v?) *)
Ltac getcor a :=
cleanup_getcor;
match goal with
| [ eq: get_tpg ?G a = _,
tpg : AnnTyping ?G a ?A |- _ ] =>
let t := fresh tpg in
move: (get_tpg_correct tpg eq) => t; subst A
end.
(* TODO: location *)
(* For now, this assumes that we only need regularity on defeq hyps *)
Ltac autoreg :=
repeat match goal with
| [ H: AnnDefEq _ _ _ _ _ |- _ ] =>
reg H; wrap_hyp H
| [ H: AnnIso _ _ _ _ _ |- _ ] =>
reg H; wrap_hyp H
end;
pcess_hyps.
Ltac clearget :=
cleanup_getcor;
repeat match goal with
| [ H: get_tpg _ _ = get_tpg _ _ |- _ ] => fail
| [ eqTa : get_tpg ?G ?a = ?Ta,
tpga : AnnTyping ?G ?a ?Ta' |- _ ] =>
let eq := fresh in
(* FIXME: in the following subst, we don't control which equation gets rewritten -> inconsistent results *)
move:(get_tpg_correct' tpga); move=> eq; rewrite <- eq in *; clear eq; subst Ta'
end.
(* An_PiCong *)
Next Obligation.
hacky.
Defined.
Next Obligation.
cleanup.
inversion 1.
auto_uniq_full.
apply wildcard'.
have: A0 = A1 by done. move => <-.
inversion H9.
by move: (get_tpg_correct' H21) => <-.
Defined.
Next Obligation.
cleanup.
inversion 1.
auto_uniq_full.
apply wildcard'.
have: A3 = A2 by done. move => <-.
inversion H12.
by move: (get_tpg_correct' H21) => <-.
Defined.
Next Obligation. (* Fuel: aux obligation *)
fsetdec.
Defined.
Next Obligation. (* Ctx wf *)
econstructor; try eassumption.
- cleanup.
reg wildcard'0.
by getcor A1.
- fsetdec.
Defined.
Next Obligation.
cleanup.
move /An_PiCong_inversion.
move => [a1 [b1 [a2 [b2 [b3 [eqA [eqB [tpg1 [tpg2 [tpg3 [defeq h]]]]]]]]]]].
apply: wildcard'.
have xnotin: x `notin` dom G by fsetdec.
move: (h _ xnotin) => [h' _].
auto_uniq_full; subst.
by apply: h'.
Defined.
Next Obligation.
cleanup'.
move /An_PiCong_inversion.
move => [a1 [b1 [a2 [b2 [b3 [eqA [eqB [tpg1 [tpg2 [tpg3 [defeq h]]]]]]]]]]].
eapply wildcard'.
have xG: x `notin` dom G by fsetdec.
move: (h _ xG) => /= [h' _].
have: A1 = a1 by cleanup; auto_uniq_full. move => ?; subst A1.
auto_uniq_full.
move: (An_Pi_inversion tpg1) => [_ [_]] /(_ _ xG).
by move: (u3 _ _ wildcard'3) => [<- _] => /(get_tpg_correct') ->.
Defined.
Next Obligation.
cleanup'.
move /An_PiCong_inversion.
move => [a1 [b1 [a2 [b2 [b3 [eqA [eqB [tpg1 [tpg2 [tpg3 [defeq h]]]]]]]]]]].
eapply wildcard'.
have xG: x `notin` dom G by fsetdec.
move: (h _ xG) => /= [h' _].
have: A1 = a1 by cleanup; auto_uniq_full. move => ?; subst A1.
clearbodies'.
auto_uniq_full.
move: (An_Pi_inversion tpg3) => [_ [_]] /(_ _ xG).
by move: (u3 _ _ wildcard'3) => [_ <-] => /(get_tpg_correct') ->.
Defined.
Next Obligation.
cleanup'.
move /An_PiCong_inversion.
move => [a1 [b1 [a2 [b2 [b3 [eqA [eqB [tpg1 [tpg2 [tpg3 [defeq h]]]]]]]]]]].
eapply wildcard'.
have xG: x `notin` dom G by fsetdec.
move: (h _ xG) => /= [h' eqb3].
have: A1 = a1 by cleanup; auto_uniq_full. move => ?; subst A1.
have: A2 = a2 by cleanup; auto_uniq_full. move => ?; subst A2.
clearbodies'.
auto_uniq_full.
move: (An_Pi_inversion tpg2) => [_ [_]] /(_ _ xG).
have realeq : B3x = open_tm_wrt_tm B2 (a_Conv (a_Var_f x) (g_Sym g1)) by rewrite eqB3x eqB2 tm_subst_tm_tm_spec.
move: realeq eqb3 eqB2 H2 => -> -> -> <-. rewrite close_tm_wrt_tm_open_tm_wrt_tm.
- by move => /(get_tpg_correct') ->.
- (* Fv in context for tpg hyp *) (* TODO: tactic *)
move: ann_context_fv_mutual => [h'' [_ [_ [_ _] ] ] ]; move: h'' => /(_ _ _ _ tpg3) /= [htmco [hcoco [htmtm hcotm ] ] ].
by fsetdec.
Defined.
Next Obligation.
cleanup'.
rewrite eqB1 eqB3.
eapply An_PiCong_exists3 with (x := x); try eassumption.
fsetdec.
Defined.
(* An_AbsCong *)
Next Obligation.
hacky.
Defined.
Next Obligation.
cleanup.
move /An_AbsCong_inversion => [a1' [a2' [b1' [b2' [b3' [B' h]]]]]].
move: h => [eqA [eqB [tpga1' [tpga2' [defg1 [tpga1b2' h]]]]]].
apply: wildcard'.
have: A1 = a1' by auto_uniq_full.
move=> ->.
by rewrite (get_tpg_correct' tpga1').
Defined.
Next Obligation.
cleanup.
move /An_AbsCong_inversion => [a1' [a2' [b1' [b2' [b3' [B' h]]]]]].
move: h => [eqA [eqB [tpga1' [tpga2' [defg1 [tpga1b2' h]]]]]].
apply: wildcard'.
have: A2 = a2' by auto_uniq_full.
move=> ->.
by rewrite (get_tpg_correct' tpga2').
Defined.
Next Obligation. (* Fuel: aux obligation *)
fsetdec.
Defined.
Next Obligation. (* Ctx wf *)
econstructor; try eassumption.
- cleanup.
reg wildcard'0.
by getcor A1.
- fsetdec.
Defined.
Next Obligation.
cleanup.
move /An_AbsCong_inversion => [a1' [a2' [b1' [b2' [b3' [B' h]]]]]].
move: h => [eqA [eqB [tpga1' [tpga2' [defg1 [tpga1b2' h]]]]]].
apply: wildcard'.
auto_uniq_full.
have: A1 = a1' /\ A2 = a2' by split; congruence.
move=> [? ?]. subst A1 A2.
have xG: x `notin` dom G by fsetdec.
move: (h x xG) => [tpgg2 [_ [h' _] ] ].
eassumption.
Defined.
Next Obligation.
by move: (wf.AnnDefEq_lc1 wildcard').
Defined.
Next Obligation.
cleanup.
move /An_AbsCong_inversion => [a1' [a2' [b1' [b2' [b3' [B' h]]]]]].
move: h => [eqA [eqB [tpga1' [tpga2' [defg1 [tpga1b2' h]]]]]].
have p': x `notin` dom G by fsetdec.
move: (h x p') => [tpgg2 [_ [h' _] ] ].
apply wildcard'.
suff eq: B1x = open_tm_wrt_tm b1' (a_Var_f x) by rewrite eq.
auto_uniq_full.
move: (u2 _ _ wildcard'0) => [eqA1 _].
rewrite eqA1 in tpgg2.
by move: (u _ _ tpgg2) => [->].
Defined.
Next Obligation.
cleanup'.
move: (wf.AnnDefEq_lc2 wildcard'3).
rewrite eqB3x => ?.
apply: tm_subst_tm_tm_lc_tm => /=.
+ done.
+ apply lc_a_Conv.
- done.
- move: (wf.AnnDefEq_lc3 wildcard'0) => ?.
econstructor; eassumption.
Defined.
Next Obligation.
clear dependent filtered_var.
cleanup'.
move=> tpgg1g2. move: (tpgg1g2).
move /An_AbsCong_inversion => [a1' [a2' [b1' [b2' [b3' [B' h]]]]]].
move: h => [eqA [eqB [tpga1' [tpga2' [defg1 [tpga1b2' h]]]]]].
apply wildcard'.
have p': x `notin` dom G by fsetdec.
move: (h x p') => [tpgg2 [eqb3' [_ h'] ] ].
suff eq: B3x = open_tm_wrt_tm b3' (a_Var_f x) by rewrite eq.
auto_uniq_full.
have: A1 = a1' /\ A2 = a2' by split; congruence.
move=> [? ?]. subst A1 A2.
rewrite eqB3x.
move: (u5 _ _ wildcard'3) => [_ eqb2'].
rewrite -eqb2' eqb3' tm_subst_tm_tm_spec close_tm_wrt_tm_open_tm_wrt_tm.
- done.
- (* Fv in context for tpg hyp *)
move: ann_context_fv_mutual => [h''' [_ [_ [_ _] ] ] ]; move: h''' => /(_ _ _ _ tpga1b2') /= [htmco'' [hcoco'' [htmtm'' hcotm'' ] ] ].
by fsetdec.
Defined.
Next Obligation.
clear dependent filtered_var.
cleanup'.
rewrite eqB1 eqB3.
eapply An_AbsCong_exists3; try eassumption.
- fsetdec.
- reflexivity.
Defined.
(* An_AppCong *)
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
cleanup'.
inversion 1.
apply wildcard'.
reg wildcard'2.
reg wildcard'1.
getcor a1.
getcor b1.
subst Ta1 Tb1.
auto_uniq_full.
intro_uniq_full wildcard'2. (* FIXME: auto_uniq_full not working here *)
intro_uniq_full wildcard'1. (* FIXME: auto_uniq_full not working here *)
have: a0 = a1 by congruence => [-> _].
move=> ?.
subst a0. subst a3.
inversion H8.
intro_uniq_full H19. (* TODO: this proof is messy *)
have: A1 = A3 by congruence. move => ->.
by move: (get_tpg_correct' H21).
Defined.
Next Obligation.
cleanup'.
inversion 1.
apply wildcard'.
reg wildcard'2.
reg wildcard'1.
getcor a2.
getcor b2.
subst Ta2 Tb2.
auto_uniq_full.
intro_uniq_full wildcard'2. (* FIXME: auto_uniq_full not working here *)
intro_uniq_full wildcard'1. (* FIXME: auto_uniq_full not working here *)
have: a0 = a1 by congruence => [-> _].
move=> ?.
subst b0. subst b2.
inversion H11.
intro_uniq_full H20. (* TODO: this proof is messy *)
have: A2 = A3 by congruence. move => ->.
by move: (get_tpg_correct' H21).
Defined.
Next Obligation.
cleanup'.
cleanup_getcor.
autoreg.
clearget.
inversion 1. inversion H8.
apply: wildcard'.
auto_uniq_full. subst a0.
move: (u9 _ tpga1).
congruence.
Defined.
Next Obligation.
cleanup'.
cleanup_getcor.
autoreg.
clearget.
inversion 1. inversion H11.
apply: wildcard'.
auto_uniq_full. subst b0.
move: (u9 _ tpga2).
congruence.
Defined.
Next Obligation.
(* FIXME: cleanup' not working *)
clear dependent filtered_var.
clear dependent filtered_var1.
clear dependent filtered_var0.
clear dependent filtered_var2.
clear dependent filtered_var4.
clear dependent filtered_var3. subst. clear dependent fuel.
clean_fun. clearbodies'.
autoreg.
clearget.
auto_uniq_full.
eapply An_AppCong2; try eassumption.
all: econstructor;
eauto using An_AppCong2.
subst Ta1. eassumption.
subst Ta2. eassumption.
Defined.
Next Obligation.
cleanup'.
autoreg.
clearget.
hacky.
Defined.
(* The numerous cases for the pattern match have been inlined -> solving them automatically *)
Ltac discr_pat_match :=
solve [obtacpre; solve [ let eq1 := fresh in let eq2 := fresh in move=> [eq1 eq2]; try discriminate eq1; discriminate eq2
| subst; inversion 1 ] ].
Solve Obligations of AnnDefEq_dec with discr_pat_match.
(* An_CPiCong *)
Next Obligation.
hacky.
Defined.
Next Obligation. (* Fuel: Aux *)
fsetdec.
Defined.
Next Obligation.
econstructor.
- eassumption.
- cleanup'. by autoreg.
- fsetdec.
Defined.
Next Obligation.
cleanup.
move /An_CPiCong_inversion.
move => [ph1 [ph2 [b1 [b2 [b3 [eqA [eqB [isoph1 [tpgp1 [tpgp2 [tpg3 h]]]]]]]]]]].
apply: wildcard'.
have cG: c `notin` dom G by ok.
move: (h _ cG) => /= [h' _].
auto_uniq_full; subst.
by apply: h'.
Defined.
Next Obligation.
cleanup'.
pcess_hyps.
move /An_CPiCong_inversion.
move => [ph1 [ph2 [b1 [b2 [b3 [eqA [eqB [isoph1 [tpgp1 [tpgp2 [tpg3 h]]]]]]]]]]].
apply: wildcard'.
auto_uniq_full.
have cG: c `notin` dom G by ok.
have: phi1 = ph1 by congruence. move=> eqphi. rewrite eqphi.
move: (An_CPi_inversion tpgp1). do 2 move=> [_]. move => /(_ c cG) h'.
move: (get_tpg_correct' h') => ->.
suff: B1c = (open_tm_wrt_co b1 (g_Var_f c)) by move=> ->.
move: (h _ cG) => /= [h'' _].
auto_uniq_full.
(* Fv in context for tpg hyp *)
move: ann_context_fv_mutual => [h''' [_ [_ [_ _] ] ] ]; move: h''' => /(_ _ _ _ tpgp1) /= [? [? [? ?]]].
rewrite eqphi in wildcard'1.
by move: (u10 _ _ wildcard'1) => [<- _].
Defined.
Next Obligation.
cleanup'.
move /An_CPiCong_inversion.
move => [ph1 [ph2 [b1 [b2 [b3 [eqA [eqB [isoph1 [tpgp1 [tpgp2 [tpg3 h]]]]]]]]]]].
apply: wildcard'.
auto_uniq_full.
have cG: c `notin` dom G by ok.
have: phi1 = ph1 by congruence. move=> eqph1.
have: phi2 = ph2 by congruence. move=> eqph2. rewrite eqph2.
move: (An_CPi_inversion tpgp2). do 2 move=> [_]. move => /(_ c cG) h'.
move: (get_tpg_correct' h') => ->.
suff: B3c = (open_tm_wrt_co b3 (g_Var_f c)) by move=> ->.
move: (h _ cG) => /= [h'' eqb3].
auto_uniq_full.
(* Fv in context for tpg hyp *)
move: ann_context_fv_mutual => [h''' [_ [_ [_ _] ] ] ]; move: h''' => /(_ _ _ _ tpg3) /= [? [? [? ?]]].
rewrite eqph1 in wildcard'2.
rewrite eqB3c eqB2 eqb3.
subst phi1.
move: (u10 _ _ wildcard'1) => [_ <-].
rewrite close_tm_wrt_co_open_tm_wrt_co; by [|fsetdec].
Defined.
Next Obligation.
cleanup'.
move /An_CPiCong_inversion.
move => [ph1 [ph2 [b1 [b2 [b3 [eqA [eqB [isoph1 [tpgp1 [tpgp2 [tpg3 h]]]]]]]]]]].
apply: wildcard'.
auto_uniq_full.
have cG: c `notin` dom G by ok.
have: phi1 = ph1 by congruence. move=> eqph1.
have: phi2 = ph2 by congruence. move=> eqph2. rewrite eqph1.
move: (An_CPi_inversion tpg3). do 2 move=> [_]. move => /(_ c cG) h'.
move: (get_tpg_correct' h') => ->.
suff: B2c = (open_tm_wrt_co b2 (g_Var_f c)) by move=> ->.
move: (h _ cG) => /= [h'' eqb3].
auto_uniq_full.
(* Fv in context for tpg hyp *)
move: ann_context_fv_mutual => [h''' [_ [_ [_ _] ] ] ]; move: h''' => /(_ _ _ _ tpg3) /= [? [? [? ?]]].
rewrite eqph1 in wildcard'2.
subst ph1.
by move: (u10 _ _ wildcard'1) => [_ <-].
Defined.
Next Obligation.
cleanup'.
(* Fv in context for eqdec hyp *)
move: ann_context_fv_mutual => [_ [_ [_ [h''' _] ] ] ]; move: h''' => /(_ _ _ _ _ _ wildcard'1) /= [? [? [? ?]]].
autoreg.
rewrite eqB1 eqB3.
eapply An_CPiCong_exists_3 with (c := c) (B2 := B2c);
try eassumption.
- fsetdec.
- move: co_subst_co_tm_spec. congruence.
Defined.
(* An_CAbsCong *)
Next Obligation.
hacky.
Defined.
Next Obligation. (* Fuel: aux *)
fsetdec.
Defined.
Next Obligation. (* Ctx wf *)
cleanup'.
autoreg.
econstructor; try eassumption.
fsetdec.
Defined.
Next Obligation.
cleanup.
move /An_CAbsCong_inversion.
move => [ph1 [ph2 [a1' [a2' [a3' [B1' [B2' [B3' [eqA [eqB [isoph12 [tpg1 [tpg2 [tpg3 [defeq4 h]]]]]]]]]]]]]]].
have cG: c `notin` dom G by ok.
move: (h _ cG) => /= [defeq3 eq23].
apply: wildcard'.
auto_uniq_full; subst.
by apply: defeq3.
Defined.
Next Obligation.
eassumption.
Defined.
Next Obligation.
cleanup_param clearbodies' idtac.
move /An_CAbsCong_inversion.
move => [ph1 [ph2 [a1' [a2' [a3' [B1' [B2' [B3' [eqA [eqB [isoph12 [tpg1 [tpg2 [tpg3 [defeq4 h]]]]]]]]]]]]]]].
(* Fv in context for eqdec hyp *)
move: ann_context_fv_mutual => [h'' [_ [_ [_ _] ] ] ]; move: h'' => /(_ _ _ _ tpg1) /= [? [? [? ?] ] ].
have cG: c `notin` dom G by ok.
move: (h _ cG) => /= [defeq3 eq23].
apply: wildcard'.
auto_uniq_full. (* TODO: it needs to be smarter on the opened contexts/when things are just congruent *)
have eqphi1: phi1 = ph1 by move: (u0 _ _ wildcard'0) => [-> _].
suff: a1 = a1' by move: (eqphi1) => [-> ->]; eassumption.
rewrite eqphi1 in wildcard'1.
move: (eqa1) (u5 _ _ wildcard'1) close_tm_wrt_co_open_tm_wrt_co => -> [<- _] ->; ok.
Defined.
Next Obligation.
cleanup'.
move /An_CAbsCong_inversion.
move => [ph1 [ph2 [a1' [a2' [a3' [B1' [B2' [B3' [eqA [eqB [isoph12 [tpg1 [tpg2 [tpg3 [defeq4 h]]]]]]]]]]]]]]].
(* Fv in context for eqdec hyp *)
move: ann_context_fv_mutual => [h'' [_ [_ [_ _] ] ] ]; move: h'' => /(_ _ _ _ tpg1) /= [? [? [? ?] ] ].
move: ann_context_fv_mutual => [h'' [_ [_ [_ _] ] ] ]; move: h'' => /(_ _ _ _ tpg2) /= [? [? [? ?] ] ].
move: ann_context_fv_mutual => [h'' [_ [_ [_ _] ] ] ]; move: h'' => /(_ _ _ _ tpg3) /= [? [? [? ?] ] ].
have cG: c `notin` dom G by ok.
move: (h _ cG) => /= [defeq3 eq23].
apply: wildcard'.
auto_uniq_full. (* TODO: it needs to be smarter on the opened contexts/when things are just congruent *)
have [eqphi1 eqphi2] : phi1 = ph1 /\ phi2 = ph2 by move: (u0 _ _ wildcard'0) => [-> ->]. subst ph1 ph2.
subst CPi1.
have: a1 = a1' by move: eqa1 (u _ _ defeq3) => -> [-> _]; autorewrite with lngen.
intros; subst a1'.
rewrite eqB1c.
move: (An_CAbs_inversion tpg1) => [B0 [tmp h'']]. injection tmp.
intros; subst B0.
move: (h'' c cG) => [_ tpga1].
move: (get_tpg_correct' tpga1).
rewrite eqa1. autorewrite with lngen.
move=> <-.
by autorewrite with lngen.
Defined.
Next Obligation.
cleanup'.
move /An_CAbsCong_inversion.
move => [ph1 [ph2 [a1' [a2' [a3' [B1' [B2' [B3' [eqA [eqB [isoph12 [tpg1 [tpg2 [tpg3 [defeq4 h]]]]]]]]]]]]]]].
(* Fv in context for eqdec hyp *)
move: ann_context_fv_mutual => [h'' [_ [_ [_ _] ] ] ]; move: h'' => /(_ _ _ _ tpg1) /= [? [? [? ?] ] ].
move: ann_context_fv_mutual => [h'' [_ [_ [_ _] ] ] ]; move: h'' => /(_ _ _ _ tpg2) /= [? [? [? ?] ] ].
move: ann_context_fv_mutual => [h'' [_ [_ [_ _] ] ] ]; move: h'' => /(_ _ _ _ tpg3) /= [? [? [? ?] ] ].
have cG: c `notin` dom G by ok.
move: (h _ cG) => /= [defeq3 eq23].
apply: wildcard'.
auto_uniq_full. (* TODO: it needs to be smarter on the opened contexts/when things are just congruent *)
have [eqphi1 eqphi2] : phi1 = ph1 /\ phi2 = ph2 by move: (u0 _ _ wildcard'0) => [-> ->]. subst ph1 ph2.
subst CPi2.
have: a2 = a2' by move: eqa2 (u _ _ defeq3) => -> [_ ->]; autorewrite with lngen.
intros; subst a2'.
have: a3 = a3' by rewrite eqa3 eqa3c -eq23; autorewrite with lngen.
intros; subst a3'.
rewrite eqB3c.
move: (An_CAbs_inversion tpg2) => [B0 [tmp h'']]. injection tmp.
intros; subst B0.
move: (h'' c cG) => [_ tpga2].
move: (get_tpg_correct' tpga2).
rewrite eqa3. autorewrite with lngen.
move=> <-.
by autorewrite with lngen.
Defined.
Next Obligation.
cleanup'.
(* Fv in context for eqdec hyp *)
move: ann_context_fv_mutual => [_ [_ [_ [h''' _]]]]; move: h''' => /(_ _ _ _ _ _ wildcard'2) /= [? [? [? ?]]].
rewrite eqa1 eqa3.
autoreg.
(* FIXME: clearget not working here (losing an eq) *)
(* clearget. *)
eapply An_CAbsCong_exists3 with (c := c) (a2 := a2c) (B1 := B1c) (B3 := B3c); try eassumption; try congruence.
- fsetdec.
- rewrite co_subst_co_tm_spec.
congruence.
- by rewrite eqB1c.
- by rewrite eqB3c.
Defined.
Next Obligation.
hacky.
Defined.
(* An_CAppCong *)
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
cleanup'.
autoreg.
clearget.
subst Ta1 Ta2.
(* Inversion and glueing *)
inversion 1.
have: a0 = a1 /\ b0 = a2 by auto_uniq_full; split; congruence.
move=> [? ?]; subst a0 b0; clear H4.
have: a3 = b1 /\ b3 = b2 by auto_uniq_full; split; congruence.
move=> [? ?]; subst a3 b3; clear H5.
(* Contra *)
apply wildcard'.
inversion H9.
have: Ta11 = a0 by auto_uniq_full; congruence.
move=> ?; subst a0.
by auto_uniq_full.
Defined.
Next Obligation.
cleanup'.
autoreg.
clearget.
subst Ta1 Ta2.
(* Inversion and glueing *)
inversion 1.
have: a0 = a1 /\ b0 = a2 by auto_uniq_full; split; congruence.
move=> [? ?]; subst a0 b0; clear H4.
have: a3 = b1 /\ b3 = b2 by auto_uniq_full; split; congruence.
move=> [? ?]; subst a3 b3; clear H5.
(* Contra *)
apply wildcard'.
inversion H9.
have: Ta12 = b2 by auto_uniq_full; congruence.
move=> ?; subst b2.
by auto_uniq_full.
Defined.
Next Obligation.
cleanup'.
autoreg.
clearget.
subst Ta1 Ta2.
(* Inversion and glueing *)
inversion 1.
have: a0 = a1 /\ b0 = a2 by auto_uniq_full; split; congruence.
move=> [? ?]; subst a0 b0; clear H4.
have: a3 = b1 /\ b3 = b2 by auto_uniq_full; split; congruence.
move=> [? ?]; subst a3 b3; clear H5.
(* Contra *)
apply wildcard'.
inversion H12.
have: Ta21 = c1 by auto_uniq_full; congruence.
move=> ?; subst c1.
by auto_uniq_full.
Defined.
Next Obligation.
cleanup'.
autoreg.
clearget.
subst Ta1 Ta2.
(* Inversion and glueing *)
inversion 1.
have: a0 = a1 /\ b0 = a2 by auto_uniq_full; split; congruence.
move=> [? ?]; subst a0 b0; clear H4.
have: a3 = b1 /\ b3 = b2 by auto_uniq_full; split; congruence.
move=> [? ?]; subst a3 b3; clear H5.
(* Contra *)
apply wildcard'.
inversion H12.
have: Ta22 = c2 by auto_uniq_full; congruence.
move=> ?; subst c2.
by auto_uniq_full.
Defined.
Next Obligation.
(* FIXME: cleanup' not working *)
clear dependent filtered_var.
clear dependent filtered_var2.
clear dependent filtered_var1.
clear dependent filtered_var0.
clear dependent filtered_var4.
clear dependent filtered_var3. subst. clear dependent fuel.
clean_fun. clearbodies'.
autoreg.
clearget.
subst.
apply: An_CAppCong2;
try econstructor; eassumption.
Defined.
Next Obligation.
cleanup'.
autoreg.
clearget.
hacky.
Defined.
Solve Obligations of AnnDefEq_dec with discr_pat_match.
(* An_CPiSnd *)
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Solve Obligations of AnnDefEq_dec with discr_pat_match.
(* FIXME FIXME FIXME FIXME FIXME
FIXME FIXME FIXME FIXME FIXME
FIXME FIXME FIXME FIXME FIXME
FIXME FIXME FIXME FIXME FIXME
FIXME FIXME FIXME FIXME FIXME
FIXME FIXME FIXME FIXME FIXME
Make the pattern-match inversion tactic check whether or not it is applied to a goal it can solve (too slow to run on everything)
FIXME FIXME FIXME FIXME FIXME
FIXME FIXME FIXME FIXME FIXME
FIXME FIXME FIXME FIXME FIXME
FIXME FIXME FIXME FIXME FIXME
FIXME FIXME FIXME FIXME FIXME
FIXME FIXME FIXME FIXME FIXME
*)
(* An_CastCo *)
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
(* An_PiFst *)
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Solve Obligations of AnnDefEq_dec with discr_pat_match.
(* An_PiSnd *)
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
cleanup'.
autoreg.
clearget.
hacky.
Defined.
Next Obligation.
cleanup'.
autoreg.
clearget.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
cleanup'.
autoreg.
clearget.
apply: An_PiSnd;
subst; eauto.
Defined.
Next Obligation.
hacky.
Defined.
Solve Obligations of AnnDefEq_dec with discr_pat_match.
Next Obligation.
hacky.
Defined.
Solve Obligations of AnnDefEq_dec with discr_pat_match.
(* An_IsoSnd *)
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
(* FIXME: old cases. Currently, DefEq_dec is done at that point *)
(*
(* g_triv (impossible) *)
Next Obligation.
(* FIXME: discriminate doesn't work *)
inversion 1; ok.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
cleanup'. autoreg.
econstructor.
move: (AnnDefEq_regularity wildcard'6). => [KA [KB [g' [tpgA [tpgB (* deqg' *) _]]]]]
reg wildcard'6.
ok.
Defined.
Next Obligation.
ok.
Defined.
Next Obligation.
ok.
Defined.
Next Obligation.
ok.
Defined.
*)
(* An_Eta *)
Next Obligation.
hacky.
Defined.
Next Obligation.
eapply An_Eta with (L := dom G)(B := B).
subst. auto.
intros.
rewrite -tm_subst_tm_tm_spec.
simpl. destruct eq_dec; try done.
rewrite tm_subst_tm_tm_fresh_eq. auto.
auto.
Defined.
Next Obligation.
eapply An_Eta with (L := dom G)(B := B).
subst. auto.
intros.
rewrite -tm_subst_tm_tm_spec.
simpl. edestruct eq_dec; try done.
rewrite tm_subst_tm_tm_fresh_eq. auto.
auto.
Defined.
Next Obligation.
eapply An_EtaC with (L := dom G).
subst. eapply wildcard'.
intros.
rewrite -co_subst_co_tm_spec.
simpl. edestruct eq_dec; try done.
rewrite co_subst_co_tm_fresh_eq. auto.
move: (AnnTyping_context_fv wildcard') => h0.
fsetdec.
Defined.
Next Obligation.
cleanup. inversion 1; subst;
inversion H0; clear H0;
inversion H4; clear H4.
destruct rho.
move: (H5 A0 B0) => h0.
destruct h0.
eapply AnnTyping_unique. eauto. eauto.
move: (H2 A0 B0) => h0.
destruct h0.
eapply AnnTyping_unique. eauto. eauto.
move: (H0 phi) => h0.
edestruct h0.
eapply AnnTyping_unique. eauto. eauto.
Defined.
Next Obligation.
unfold wildcard'.
repeat split; intros; discriminate.
Defined.
Next Obligation.
unfold wildcard'.
repeat split; intros; discriminate.
Defined.
Next Obligation.
unfold wildcard'.
repeat split; intros; discriminate.
Defined.
Next Obligation.
unfold wildcard'.
repeat split; intros; discriminate.
Defined.
Next Obligation.
unfold wildcard'.
repeat split; intros; discriminate.
Defined.
Next Obligation.
unfold wildcard'.
repeat split; intros; discriminate.
Defined.
Next Obligation.
unfold wildcard'.
repeat split; intros; discriminate.
Defined.
Next Obligation.
unfold wildcard'.
repeat split; intros; discriminate.
Defined.
Next Obligation.
unfold wildcard'.
repeat split; intros; discriminate.
Defined.
Next Obligation.
unfold wildcard'.
repeat split; intros; discriminate.
Defined.
Next Obligation.
unfold wildcard'.
repeat split; intros; discriminate.
Defined.
Next Obligation.
unfold wildcard'.
repeat split; intros; discriminate.
Defined.
Next Obligation.
unfold wildcard'.
repeat split; intros; discriminate.
Defined.
Next Obligation.
unfold wildcard'.
repeat split; intros; discriminate.
Defined.
Next Obligation.
unfold wildcard'.
repeat split; intros; discriminate.
Defined.
(* cleanup'.
subst.
move=> h0.
inversion h0. subst.
apply (H0 A0 B0).
auto_uniq_full.
apply u0.
auto. admit. admit. *)
(*
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined. *)
(*
(* An_Left *)
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
cleanup'.
autoreg.
intro h0; inversion h0. subst.
eapply wildcard'.
erewrite <- get_tpg_correct'. eauto.
auto_uniq_full.
eauto.
subst. eapply wildcard'.
erewrite <- get_tpg_correct'. eauto.
auto_uniq_full.
try done.
Defined.
Next Obligation.
cleanup'.
autoreg.
intro h0; inversion h0. subst.
eapply wildcard'.
erewrite <- get_tpg_correct'. eauto.
auto_uniq_full.
try done.
subst. eapply wildcard'.
erewrite <- get_tpg_correct'. eauto.
auto_uniq_full.
try done.
Defined.
Next Obligation.
eapply An_Left2; try eassumption.
*)
(******** AnnIso_dec ********)
(* An_Cong *)
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
cleanup'.
autoreg.
erewrite <- get_tpg_correct'; eassumption.
Defined.
Next Obligation.
cleanup'.
autoreg.
erewrite <- get_tpg_correct'; eassumption.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
eassumption.
Defined.
Next Obligation.
cleanup'.
autoreg.
erewrite <- get_tpg_correct'; eassumption.
Defined.
Next Obligation.
cleanup'.
autoreg.
erewrite <- get_tpg_correct'; eassumption.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
eauto.
Defined.
(* An_CPiFst *)
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Solve Obligations of AnnIso_dec with discr_pat_match.
(* An_IsoSym *)
Next Obligation.
hacky.
Defined.
Next Obligation.
eauto.
Defined.
(* An_IsoConv *)
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
rewrite Heq_phi1 Heq_phi2.
subst A' B'.
eapply An_IsoConv'.
rewrite -Heq_phi1. reflexivity.
rewrite -Heq_phi2. reflexivity.
all: try eassumption.
Defined.
(******** AnnPropWff_dec ********)
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
(******** AnnTyping_dec ********)
(* An_Star *)
Next Obligation.
hacky.
Defined.
(* An_Var *)
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
(* An_Pi *)
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation. (* Fuel: aux *)
fsetdec.
Defined.
Next Obligation. (* Ctx Wf *)
cleanup'.
autoreg.
subst.
econstructor; eauto.
Defined.
Next Obligation.
move /An_Pi_inversion => [_ [_] ].
have xG: x `notin` dom G by fsetdec.
move /(_ x xG).
ok.
Defined.
Next Obligation.
move /An_Pi_inversion => [? ?].
cleanup.
apply: wildcard'.
auto_uniq_full.
ok.
Defined.
Next Obligation.
apply An_Pi_exists2 with (x := x); ok.
Defined.
(* An_Abs *)
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation. (* Fuel: aux *)
fsetdec.
Defined.
Next Obligation. (* Ctx Wf *)
cleanup'.
autoreg.
subst.
econstructor; eauto.
Defined.
Next Obligation.
cleanup.
move /An_Abs_inversion => [? [_ [_] ] ].
have xG: x `notin` dom G by fsetdec.
move /(_ x xG).
ok.
Defined.
Next Obligation.
by move: (wf.AnnTyping_lc1 wildcard').
Defined.
Next Obligation.
cleanup.
move /An_Abs_inversion => [? [_ [_] ] ].
have xG: x `notin` dom G by fsetdec.
move /(_ x xG) => [h _].
by apply wildcard'.
Defined.
Next Obligation.
move: ann_context_fv_mutual => [h'' [_ [_ [_ _] ] ] ]; move: h'' => /(_ _ _ _ wildcard'2) /= [? [? [? ?] ] ].
eapply An_Abs_exists with (x := x); try done.
- autorewrite with lngen. fsetdec.
- by subst.
- by autorewrite with lngen.
Defined.
(* An_App *)
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
subst.
apply: An_App; eassumption.
Defined.
Next Obligation.
hacky.
Defined.
Solve All Obligations with discr_pat_match.
(* An_Cast *)
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
cleanup'.
autoreg.
clearget.
hacky.
Defined.
Next Obligation.
hacky.
Unshelve.
all: apply a_Star.
Defined.
Next Obligation.
cleanup'.
autoreg.
clearget.
subst.
apply: An_Conv; eassumption.
Defined.
(* An_CApp *)
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
hacky.
Defined.
Next Obligation.
subst.
apply: An_CApp; eassumption.
Defined.
Next Obligation.
hacky.
Defined.
Solve All Obligations with discr_pat_match.
(*
(* An_Const *)
Next Obligation.
hacky.
Defined.
Next Obligation.
move: (an_toplevel_to_const wildcard') => AT.
move: (AnnTyping_lc AT) => [lc1 lc2].
eapply lc_set_tm_of_lc_tm. eauto.
Defined.
Next Obligation.
inversion 1.
(* TODO: uniq should be discharged via typeclasses/CS *)
move: (binds_unique _ _ _ _ _ H3 wildcard'0 uniq_an_toplevel).
intro h0. inversion h0. subst.
move: (binds_to_type _ _ AnnSig_an_toplevel H3) => h1. done.
Defined.
Next Obligation.
subst.
apply: An_Const; eauto.
eapply an_toplevel_to_const; eauto.
Defined. *)
(* An_CPi *)
Next Obligation.
hacky.
Defined.
Next Obligation. (* Fuel: aux *)
fsetdec.
Defined.
Next Obligation.
cleanup'.
econstructor; try eassumption.
fsetdec.
Defined.
Next Obligation.
move /An_CPi_inversion => [_ [_] ].
have cG: c `notin` dom G by fsetdec.
move /(_ c cG).
ok.
Defined.
Next Obligation.
move /An_CPi_inversion => [_ [_] ].
have cG: c `notin` dom G by fsetdec.
move /(_ c cG) => /= h.
apply wildcard'.
auto_uniq_full.
by move: (u0 _ wildcard'1) => ->.
Defined.
Next Obligation.
apply An_CPi_exists with (c := c);
ok.
Defined.
(* An_CAbs *)
Next Obligation.
hacky.
Defined.
Next Obligation. (* Fuel: aux *)
fsetdec.
Defined.
Next Obligation.
cleanup'.
econstructor; try eassumption.
fsetdec.
Defined.
Next Obligation.
move /An_CAbs_inversion => [? [? ] ].
have cG: c `notin` dom G by fsetdec.
move /(_ _ cG).
ok.
Defined.
Next Obligation.
move: ann_context_fv_mutual => [h'' [_ [_ [_ _] ] ] ]; move: h'' => /(_ _ _ _ wildcard') /= [? [? [? ?] ] ].
apply An_CAbs_exists with (c := c); try eassumption.
- autorewrite with lngen. fsetdec.
- autorewrite with lngen. eassumption.
Defined.
(* An_Fam *)
Next Obligation.
hacky.
Defined.
Next Obligation.
clear_annoying.
subst.
move: (an_toplevel_closed wildcard') => tpg.
autoreg. (* TODO: autoreg should do this one too (only use case though...) *)
move: (AnnTyping_regularity tpg) => kdg.
econstructor; eassumption.
Defined.
End fc_dec_fun.
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Tue Apr 18 23:15:14 2017
// Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_1024_1/bram_1024_1_sim_netlist.v
// Design : bram_1024_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "bram_1024_1,blk_mem_gen_v8_3_5,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
(* NotValidForBitStream *)
module bram_1024_1
(clka,
ena,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [9:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [19:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [19:0]douta;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [19:0]NLW_U0_doutb_UNCONNECTED;
wire [9:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [9:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [19:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "10" *)
(* C_ADDRB_WIDTH = "10" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.74095 mW" *)
(* C_FAMILY = "zynq" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "bram_1024_1.mem" *)
(* C_INIT_FILE_NAME = "bram_1024_1.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "1024" *)
(* C_READ_DEPTH_B = "1024" *)
(* C_READ_WIDTH_A = "20" *)
(* C_READ_WIDTH_B = "20" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "1024" *)
(* C_WRITE_DEPTH_B = "1024" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "20" *)
(* C_WRITE_WIDTH_B = "20" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
bram_1024_1_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[19:0]),
.eccpipece(1'b0),
.ena(ena),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[9:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[9:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[19:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module bram_1024_1_blk_mem_gen_generic_cstr
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
bram_1024_1_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bram_1024_1_blk_mem_gen_prim_width
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
bram_1024_1_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bram_1024_1_blk_mem_gen_prim_wrapper_init
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 ;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
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.INIT_00(256'h0000001E0000001A00000016000000120000000E0000000A0000000600000002),
.INIT_01(256'h0000011E0000011A00000116000001120000010E0000010A0000010600000102),
.INIT_02(256'h0000021E0000021A00000216000002120000020E0000020A0000020600000202),
.INIT_03(256'h0000031E0000031A00000316000003120000030E0000030A0000030600000302),
.INIT_04(256'h0000041E0000041A00000416000004120000040E0000040A0000040600000402),
.INIT_05(256'h0000051E0000051A00000516000005120000050E0000050A0000050600000502),
.INIT_06(256'h0000061E0000061A00000616000006120000060E0000060A0000060600000602),
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.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,dina[19:15],1'b0,1'b0,1'b0,dina[14:10],1'b0,1'b0,1'b0,dina[9:5],1'b0,1'b0,1'b0,dina[4:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23 ,douta[19:15],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31 ,douta[14:10],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39 ,douta[9:5],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47 ,douta[4:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module bram_1024_1_blk_mem_gen_top
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
bram_1024_1_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "10" *) (* C_ADDRB_WIDTH = "10" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.74095 mW" *)
(* C_FAMILY = "zynq" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "bram_1024_1.mem" *)
(* C_INIT_FILE_NAME = "bram_1024_1.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "1024" *) (* C_READ_DEPTH_B = "1024" *) (* C_READ_WIDTH_A = "20" *)
(* C_READ_WIDTH_B = "20" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "1024" *) (* C_WRITE_DEPTH_B = "1024" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "20" *) (* C_WRITE_WIDTH_B = "20" *)
(* C_XDEVICEFAMILY = "zynq" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) (* downgradeipidentifiedwarnings = "yes" *)
module bram_1024_1_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [9:0]addra;
input [19:0]dina;
output [19:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [9:0]addrb;
input [19:0]dinb;
output [19:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [9:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [19:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [19:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [9:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[19] = \<const0> ;
assign doutb[18] = \<const0> ;
assign doutb[17] = \<const0> ;
assign doutb[16] = \<const0> ;
assign doutb[15] = \<const0> ;
assign doutb[14] = \<const0> ;
assign doutb[13] = \<const0> ;
assign doutb[12] = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
bram_1024_1_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *)
module bram_1024_1_blk_mem_gen_v8_3_5_synth
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
bram_1024_1_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1 ns / 1 ps
`include "defines.v"
`ifndef ICE
`define REGFILE_REGISTERED_OUT 1
`endif
module regfile
#(parameter [0:0] MICROOPS_ENABLED = 1)
(input clk,
input rst,
input [31:0] PC,
input [4:0] addr1,
input [4:0] addr2,
input [4:0] addrw,
`ifdef REGFILE_REGISTERED_OUT
output reg [31:0] out1,
output reg [31:0] out2,
`else
output [31:0] out1,
output [31:0] out2,
`endif
input [4:0] dbgreg,
input dbgreg_en,
input [31:0] wdata,
input we,
input [31:0] clkcounter);
reg [31:0] mem [0:31];
wire [31:0] out1_next;
wire [31:0] out2_next;
// PC+1 if microops enabled, otherwise PC+2
wire [31:0] delta1;
wire [31:0] delta2;
assign delta1 = MICROOPS_ENABLED?1:2;
`ifdef REGFILE_REGISTERED_OUT
assign delta2 = 0;
`else
assign delta2 = -1;
`endif
assign out1_next = addr1==0?0:
(addr1==1?1:
(addr1==31?(PC+(delta1+delta2)):
(addrw==addr1?wdata:mem[addr1])));
assign out2_next = addr2==0?0:
(addr2==1?1:
(addr2==31?(PC+(delta1+delta2)):
(addrw==addr2?wdata:mem[addr2])));
`ifndef REGFILE_REGISTERED_OUT
assign out1 = out1_next;
assign out2 = out2_next;
`endif
always @(posedge clk)
begin
if (we) begin
mem[addrw] <= wdata;
end
`ifdef REGFILE_REGISTERED_OUT
out1 <= out1_next;
out2 <= out2_next;
`endif
if (dbgreg_en)
$write("[R%0d=%0d]", dbgreg, mem[dbgreg]);
end
endmodule
|
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