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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface
`timescale 1ns/100ps
module axi_ad9680_if (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_data,
// adc data output
adc_clk,
adc_rst,
adc_data_a,
adc_data_b,
adc_or_a,
adc_or_b,
adc_status);
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [127:0] rx_data;
// adc data output
output adc_clk;
input adc_rst;
output [55:0] adc_data_a;
output [55:0] adc_data_b;
output adc_or_a;
output adc_or_b;
output adc_status;
// internal registers
reg adc_status = 'd0;
// internal signals
wire [15:0] adc_data_a_s3_s;
wire [15:0] adc_data_a_s2_s;
wire [15:0] adc_data_a_s1_s;
wire [15:0] adc_data_a_s0_s;
wire [15:0] adc_data_b_s3_s;
wire [15:0] adc_data_b_s2_s;
wire [15:0] adc_data_b_s1_s;
wire [15:0] adc_data_b_s0_s;
// adc clock is the reference clock
assign adc_clk = rx_clk;
assign adc_or_a = 1'b0;
assign adc_or_b = 1'b0;
// adc channels
assign adc_data_a = { adc_data_a_s3_s[13:0], adc_data_a_s2_s[13:0],
adc_data_a_s1_s[13:0], adc_data_a_s0_s[13:0]};
assign adc_data_b = { adc_data_b_s3_s[13:0], adc_data_b_s2_s[13:0],
adc_data_b_s1_s[13:0], adc_data_b_s0_s[13:0]};
// data multiplex
assign adc_data_a_s3_s = {rx_data[ 57: 56], rx_data[ 31: 24], rx_data[ 63: 58]};
assign adc_data_a_s2_s = {rx_data[ 49: 48], rx_data[ 23: 16], rx_data[ 55: 50]};
assign adc_data_a_s1_s = {rx_data[ 41: 40], rx_data[ 15: 8], rx_data[ 47: 42]};
assign adc_data_a_s0_s = {rx_data[ 33: 32], rx_data[ 7: 0], rx_data[ 39: 34]};
assign adc_data_b_s3_s = {rx_data[121:120], rx_data[ 95: 88], rx_data[127:122]};
assign adc_data_b_s2_s = {rx_data[113:112], rx_data[ 87: 80], rx_data[119:114]};
assign adc_data_b_s1_s = {rx_data[105:104], rx_data[ 79: 72], rx_data[111:106]};
assign adc_data_b_s0_s = {rx_data[ 97: 96], rx_data[ 71: 64], rx_data[103: 98]};
// status
always @(posedge rx_clk) begin
if (adc_rst == 1'b1) begin
adc_status <= 1'b0;
end else begin
adc_status <= 1'b1;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(* This file is (C) Copyright 2006-2015 Microsoft Corporation and Inria. *)
Require Import ssreflect.
(******************************************************************************)
(* This file contains the basic definitions and notations for working with *)
(* functions. The definitions provide for: *)
(* *)
(* - Pair projections: *)
(* p.1 == first element of a pair *)
(* p.2 == second element of a pair *)
(* These notations also apply to p : P /\ Q, via an and >-> pair coercion. *)
(* *)
(* - Simplifying functions, beta-reduced by /= and simpl: *)
(* [fun : T => E] == constant function from type T that returns E *)
(* [fun x => E] == unary function *)
(* [fun x : T => E] == unary function with explicit domain type *)
(* [fun x y => E] == binary function *)
(* [fun x y : T => E] == binary function with common domain type *)
(* [fun (x : T) y => E] \ *)
(* [fun (x : xT) (y : yT) => E] | == binary function with (some) explicit, *)
(* [fun x (y : T) => E] / independent domain types for each argument *)
(* *)
(* - Partial functions using option type: *)
(* oapp f d ox == if ox is Some x returns f x, d otherwise *)
(* odflt d ox == if ox is Some x returns x, d otherwise *)
(* obind f ox == if ox is Some x returns f x, None otherwise *)
(* omap f ox == if ox is Some x returns Some (f x), None otherwise *)
(* *)
(* - Singleton types: *)
(* all_equal_to x0 == x0 is the only value in its type, so any such value *)
(* can be rewritten to x0. *)
(* *)
(* - A generic wrapper type: *)
(* wrapped T == the inductive type with values Wrap x for x : T. *)
(* unwrap w == the projection of w : wrapped T on T. *)
(* wrap x == the canonical injection of x : T into wrapped T; it is *)
(* equivalent to Wrap x, but is declared as a (default) *)
(* Canonical Structure, which lets the Coq HO unification *)
(* automatically expand x into unwrap (wrap x). The delta *)
(* reduction of wrap x to Wrap can be exploited to *)
(* introduce controlled nondeterminism in Canonical *)
(* Structure inference, as in the implementation of *)
(* the mxdirect predicate in matrix.v. *)
(* *)
(* - Sigma types: *)
(* tag w == the i of w : {i : I & T i}. *)
(* tagged w == the T i component of w : {i : I & T i}. *)
(* Tagged T x == the {i : I & T i} with component x : T i. *)
(* tag2 w == the i of w : {i : I & T i & U i}. *)
(* tagged2 w == the T i component of w : {i : I & T i & U i}. *)
(* tagged2' w == the U i component of w : {i : I & T i & U i}. *)
(* Tagged2 T U x y == the {i : I & T i} with components x : T i and y : U i. *)
(* sval u == the x of u : {x : T | P x}. *)
(* s2val u == the x of u : {x : T | P x & Q x}. *)
(* The properties of sval u, s2val u are given by lemmas svalP, s2valP, and *)
(* s2valP'. We provide coercions sigT2 >-> sigT and sig2 >-> sig >-> sigT. *)
(* A suite of lemmas (all_sig, ...) let us skolemize sig, sig2, sigT, sigT2 *)
(* and pair, e.g., *)
(* have /all_sig[f fP] (x : T): {y : U | P y} by ... *)
(* yields an f : T -> U such that fP : forall x, P (f x). *)
(* - Identity functions: *)
(* id == NOTATION for the explicit identity function fun x => x. *)
(* @id T == notation for the explicit identity at type T. *)
(* idfun == an expression with a head constant, convertible to id; *)
(* idfun x simplifies to x. *)
(* @idfun T == the expression above, specialized to type T. *)
(* phant_id x y == the function type phantom _ x -> phantom _ y. *)
(* *** In addition to their casual use in functional programming, identity *)
(* functions are often used to trigger static unification as part of the *)
(* construction of dependent Records and Structures. For example, if we need *)
(* a structure sT over a type T, we take as arguments T, sT, and a "dummy" *)
(* function T -> sort sT: *)
(* Definition foo T sT & T -> sort sT := ... *)
(* We can avoid specifying sT directly by calling foo (@id T), or specify *)
(* the call completely while still ensuring the consistency of T and sT, by *)
(* calling @foo T sT idfun. The phant_id type allows us to extend this trick *)
(* to non-Type canonical projections. It also allows us to sidestep *)
(* dependent type constraints when building explicit records, e.g., given *)
(* Record r := R {x; y : T(x)}. *)
(* if we need to build an r from a given y0 while inferring some x0, such *)
(* that y0 : T(x0), we pose *)
(* Definition mk_r .. y .. (x := ...) y' & phant_id y y' := R x y'. *)
(* Calling @mk_r .. y0 .. id will cause Coq to use y' := y0, while checking *)
(* the dependent type constraint y0 : T(x0). *)
(* *)
(* - Extensional equality for functions and relations (i.e. functions of two *)
(* arguments): *)
(* f1 =1 f2 == f1 x is equal to f2 x for all x. *)
(* f1 =1 f2 :> A == ... and f2 is explicitly typed. *)
(* f1 =2 f2 == f1 x y is equal to f2 x y for all x y. *)
(* f1 =2 f2 :> A == ... and f2 is explicitly typed. *)
(* *)
(* - Composition for total and partial functions: *)
(* f^~ y == function f with second argument specialised to y, *)
(* i.e., fun x => f x y *)
(* CAVEAT: conditional (non-maximal) implicit arguments *)
(* of f are NOT inserted in this context *)
(* @^~ x == application at x, i.e., fun f => f x *)
(* [eta f] == the explicit eta-expansion of f, i.e., fun x => f x *)
(* CAVEAT: conditional (non-maximal) implicit arguments *)
(* of f are NOT inserted in this context. *)
(* fun=> v := the constant function fun _ => v. *)
(* f1 \o f2 == composition of f1 and f2. *)
(* Note: (f1 \o f2) x simplifies to f1 (f2 x). *)
(* f1 \; f2 == categorical composition of f1 and f2. This expands to *)
(* to f2 \o f1 and (f1 \; f2) x simplifies to f2 (f1 x). *)
(* pcomp f1 f2 == composition of partial functions f1 and f2. *)
(* *)
(* *)
(* - Properties of functions: *)
(* injective f <-> f is injective. *)
(* cancel f g <-> g is a left inverse of f / f is a right inverse of g. *)
(* pcancel f g <-> g is a left inverse of f where g is partial. *)
(* ocancel f g <-> g is a left inverse of f where f is partial. *)
(* bijective f <-> f is bijective (has a left and right inverse). *)
(* involutive f <-> f is involutive. *)
(* *)
(* - Properties for operations. *)
(* left_id e op <-> e is a left identity for op (e op x = x). *)
(* right_id e op <-> e is a right identity for op (x op e = x). *)
(* left_inverse e inv op <-> inv is a left inverse for op wrt identity e, *)
(* i.e., (inv x) op x = e. *)
(* right_inverse e inv op <-> inv is a right inverse for op wrt identity e *)
(* i.e., x op (i x) = e. *)
(* self_inverse e op <-> each x is its own op-inverse (x op x = e). *)
(* idempotent op <-> op is idempotent for op (x op x = x). *)
(* associative op <-> op is associative, i.e., *)
(* x op (y op z) = (x op y) op z. *)
(* commutative op <-> op is commutative (x op y = y op x). *)
(* left_commutative op <-> op is left commutative, i.e., *)
(* x op (y op z) = y op (x op z). *)
(* right_commutative op <-> op is right commutative, i.e., *)
(* (x op y) op z = (x op z) op y. *)
(* left_zero z op <-> z is a left zero for op (z op x = z). *)
(* right_zero z op <-> z is a right zero for op (x op z = z). *)
(* left_distributive op1 op2 <-> op1 distributes over op2 to the left: *)
(* (x op2 y) op1 z = (x op1 z) op2 (y op1 z). *)
(* right_distributive op1 op2 <-> op distributes over add to the right: *)
(* x op1 (y op2 z) = (x op1 z) op2 (x op1 z). *)
(* interchange op1 op2 <-> op1 and op2 satisfy an interchange law: *)
(* (x op2 y) op1 (z op2 t) = (x op1 z) op2 (y op1 t). *)
(* Note that interchange op op is a commutativity property. *)
(* left_injective op <-> op is injective in its left argument: *)
(* x op y = z op y -> x = z. *)
(* right_injective op <-> op is injective in its right argument: *)
(* x op y = x op z -> y = z. *)
(* left_loop inv op <-> op, inv obey the inverse loop left axiom: *)
(* (inv x) op (x op y) = y for all x, y, i.e., *)
(* op (inv x) is always a left inverse of op x *)
(* rev_left_loop inv op <-> op, inv obey the inverse loop reverse left *)
(* axiom: x op ((inv x) op y) = y, for all x, y. *)
(* right_loop inv op <-> op, inv obey the inverse loop right axiom: *)
(* (x op y) op (inv y) = x for all x, y. *)
(* rev_right_loop inv op <-> op, inv obey the inverse loop reverse right *)
(* axiom: (x op y) op (inv y) = x for all x, y. *)
(* Note that familiar "cancellation" identities like x + y - y = x or *)
(* x - y + y = x are respectively instances of right_loop and rev_right_loop *)
(* The corresponding lemmas will use the K and NK/VK suffixes, respectively. *)
(* *)
(* - Morphisms for functions and relations: *)
(* {morph f : x / a >-> r} <-> f is a morphism with respect to functions *)
(* (fun x => a) and (fun x => r); if r == R[x], *)
(* this states that f a = R[f x] for all x. *)
(* {morph f : x / a} <-> f is a morphism with respect to the *)
(* function expression (fun x => a). This is *)
(* shorthand for {morph f : x / a >-> a}; note *)
(* that the two instances of a are often *)
(* interpreted at different types. *)
(* {morph f : x y / a >-> r} <-> f is a morphism with respect to functions *)
(* (fun x y => a) and (fun x y => r). *)
(* {morph f : x y / a} <-> f is a morphism with respect to the *)
(* function expression (fun x y => a). *)
(* {homo f : x / a >-> r} <-> f is a homomorphism with respect to the *)
(* predicates (fun x => a) and (fun x => r); *)
(* if r == R[x], this states that a -> R[f x] *)
(* for all x. *)
(* {homo f : x / a} <-> f is a homomorphism with respect to the *)
(* predicate expression (fun x => a). *)
(* {homo f : x y / a >-> r} <-> f is a homomorphism with respect to the *)
(* relations (fun x y => a) and (fun x y => r). *)
(* {homo f : x y / a} <-> f is a homomorphism with respect to the *)
(* relation expression (fun x y => a). *)
(* {mono f : x / a >-> r} <-> f is monotone with respect to projectors *)
(* (fun x => a) and (fun x => r); if r == R[x], *)
(* this states that R[f x] = a for all x. *)
(* {mono f : x / a} <-> f is monotone with respect to the projector *)
(* expression (fun x => a). *)
(* {mono f : x y / a >-> r} <-> f is monotone with respect to relators *)
(* (fun x y => a) and (fun x y => r). *)
(* {mono f : x y / a} <-> f is monotone with respect to the relator *)
(* expression (fun x y => a). *)
(* *)
(* The file also contains some basic lemmas for the above concepts. *)
(* Lemmas relative to cancellation laws use some abbreviated suffixes: *)
(* K - a cancellation rule like esymK : cancel (@esym T x y) (@esym T y x). *)
(* LR - a lemma moving an operation from the left hand side of a relation to *)
(* the right hand side, like canLR: cancel g f -> x = g y -> f x = y. *)
(* RL - a lemma moving an operation from the right to the left, e.g., canRL. *)
(* Beware that the LR and RL orientations refer to an "apply" (back chaining) *)
(* usage; when using the same lemmas with "have" or "move" (forward chaining) *)
(* the directions will be reversed!. *)
(******************************************************************************)
Set Implicit Arguments.
Unset Strict Implicit.
Unset Printing Implicit Defensive.
Delimit Scope fun_scope with FUN.
Open Scope fun_scope.
(* Notations for argument transpose *)
Notation "f ^~ y" := (fun x => f x y)
(at level 10, y at level 8, no associativity, format "f ^~ y") : fun_scope.
Notation "@^~ x" := (fun f => f x)
(at level 10, x at level 8, no associativity, format "@^~ x") : fun_scope.
Delimit Scope pair_scope with PAIR.
Open Scope pair_scope.
(* Notations for pair/conjunction projections *)
Notation "p .1" := (fst p)
(at level 2, left associativity, format "p .1") : pair_scope.
Notation "p .2" := (snd p)
(at level 2, left associativity, format "p .2") : pair_scope.
Coercion pair_of_and P Q (PandQ : P /\ Q) := (proj1 PandQ, proj2 PandQ).
Definition all_pair I T U (w : forall i : I, T i * U i) :=
(fun i => (w i).1, fun i => (w i).2).
(* Complements on the option type constructor, used below to *)
(* encode partial functions. *)
Module Option.
Definition apply aT rT (f : aT -> rT) x u := if u is Some y then f y else x.
Definition default T := apply (fun x : T => x).
Definition bind aT rT (f : aT -> option rT) := apply f None.
Definition map aT rT (f : aT -> rT) := bind (fun x => Some (f x)).
End Option.
Notation oapp := Option.apply.
Notation odflt := Option.default.
Notation obind := Option.bind.
Notation omap := Option.map.
Notation some := (@Some _) (only parsing).
(* Shorthand for some basic equality lemmas. *)
Notation erefl := refl_equal.
Notation ecast i T e x := (let: erefl in _ = i := e return T in x).
Definition esym := sym_eq.
Definition nesym := sym_not_eq.
Definition etrans := trans_eq.
Definition congr1 := f_equal.
Definition congr2 := f_equal2.
(* Force at least one implicit when used as a view. *)
Prenex Implicits esym nesym.
(* A predicate for singleton types. *)
Definition all_equal_to T (x0 : T) := forall x, unkeyed x = x0.
Lemma unitE : all_equal_to tt. Proof. by case. Qed.
(* A generic wrapper type *)
Structure wrapped T := Wrap {unwrap : T}.
Canonical wrap T x := @Wrap T x.
Prenex Implicits unwrap wrap Wrap.
(* Syntax for defining auxiliary recursive function. *)
(* Usage: *)
(* Section FooDefinition. *)
(* Variables (g1 : T1) (g2 : T2). (globals) *)
(* Fixoint foo_auxiliary (a3 : T3) ... := *)
(* body, using [rec e3, ...] for recursive calls *)
(* where "[ 'rec' a3 , a4 , ... ]" := foo_auxiliary. *)
(* Definition foo x y .. := [rec e1, ...]. *)
(* + proofs about foo *)
(* End FooDefinition. *)
Reserved Notation "[ 'rec' a0 ]"
(at level 0, format "[ 'rec' a0 ]").
Reserved Notation "[ 'rec' a0 , a1 ]"
(at level 0, format "[ 'rec' a0 , a1 ]").
Reserved Notation "[ 'rec' a0 , a1 , a2 ]"
(at level 0, format "[ 'rec' a0 , a1 , a2 ]").
Reserved Notation "[ 'rec' a0 , a1 , a2 , a3 ]"
(at level 0, format "[ 'rec' a0 , a1 , a2 , a3 ]").
Reserved Notation "[ 'rec' a0 , a1 , a2 , a3 , a4 ]"
(at level 0, format "[ 'rec' a0 , a1 , a2 , a3 , a4 ]").
Reserved Notation "[ 'rec' a0 , a1 , a2 , a3 , a4 , a5 ]"
(at level 0, format "[ 'rec' a0 , a1 , a2 , a3 , a4 , a5 ]").
Reserved Notation "[ 'rec' a0 , a1 , a2 , a3 , a4 , a5 , a6 ]"
(at level 0, format "[ 'rec' a0 , a1 , a2 , a3 , a4 , a5 , a6 ]").
Reserved Notation "[ 'rec' a0 , a1 , a2 , a3 , a4 , a5 , a6 , a7 ]"
(at level 0,
format "[ 'rec' a0 , a1 , a2 , a3 , a4 , a5 , a6 , a7 ]").
Reserved Notation "[ 'rec' a0 , a1 , a2 , a3 , a4 , a5 , a6 , a7 , a8 ]"
(at level 0,
format "[ 'rec' a0 , a1 , a2 , a3 , a4 , a5 , a6 , a7 , a8 ]").
Reserved Notation "[ 'rec' a0 , a1 , a2 , a3 , a4 , a5 , a6 , a7 , a8 , a9 ]"
(at level 0,
format "[ 'rec' a0 , a1 , a2 , a3 , a4 , a5 , a6 , a7 , a8 , a9 ]").
(* Definitions and notation for explicit functions with simplification, *)
(* i.e., which simpl and /= beta expand (this is complementary to nosimpl). *)
Section SimplFun.
Variables aT rT : Type.
CoInductive simpl_fun := SimplFun of aT -> rT.
Definition fun_of_simpl f := fun x => let: SimplFun lam := f in lam x.
Coercion fun_of_simpl : simpl_fun >-> Funclass.
End SimplFun.
Notation "[ 'fun' : T => E ]" := (SimplFun (fun _ : T => E))
(at level 0,
format "'[hv' [ 'fun' : T => '/ ' E ] ']'") : fun_scope.
Notation "[ 'fun' x => E ]" := (SimplFun (fun x => E))
(at level 0, x ident,
format "'[hv' [ 'fun' x => '/ ' E ] ']'") : fun_scope.
Notation "[ 'fun' x : T => E ]" := (SimplFun (fun x : T => E))
(at level 0, x ident, only parsing) : fun_scope.
Notation "[ 'fun' x y => E ]" := (fun x => [fun y => E])
(at level 0, x ident, y ident,
format "'[hv' [ 'fun' x y => '/ ' E ] ']'") : fun_scope.
Notation "[ 'fun' x y : T => E ]" := (fun x : T => [fun y : T => E])
(at level 0, x ident, y ident, only parsing) : fun_scope.
Notation "[ 'fun' ( x : T ) y => E ]" := (fun x : T => [fun y => E])
(at level 0, x ident, y ident, only parsing) : fun_scope.
Notation "[ 'fun' x ( y : T ) => E ]" := (fun x => [fun y : T => E])
(at level 0, x ident, y ident, only parsing) : fun_scope.
Notation "[ 'fun' ( x : xT ) ( y : yT ) => E ]" :=
(fun x : xT => [fun y : yT => E])
(at level 0, x ident, y ident, only parsing) : fun_scope.
(* For delta functions in eqtype.v. *)
Definition SimplFunDelta aT rT (f : aT -> aT -> rT) := [fun z => f z z].
(* Extensional equality, for unary and binary functions, including syntactic *)
(* sugar. *)
Section ExtensionalEquality.
Variables A B C : Type.
Definition eqfun (f g : B -> A) : Prop := forall x, f x = g x.
Definition eqrel (r s : C -> B -> A) : Prop := forall x y, r x y = s x y.
Lemma frefl f : eqfun f f. Proof. by []. Qed.
Lemma fsym f g : eqfun f g -> eqfun g f. Proof. by move=> eq_fg x. Qed.
Lemma ftrans f g h : eqfun f g -> eqfun g h -> eqfun f h.
Proof. by move=> eq_fg eq_gh x; rewrite eq_fg. Qed.
Lemma rrefl r : eqrel r r. Proof. by []. Qed.
End ExtensionalEquality.
Typeclasses Opaque eqfun.
Typeclasses Opaque eqrel.
Hint Resolve frefl rrefl.
Notation "f1 =1 f2" := (eqfun f1 f2)
(at level 70, no associativity) : fun_scope.
Notation "f1 =1 f2 :> A" := (f1 =1 (f2 : A))
(at level 70, f2 at next level, A at level 90) : fun_scope.
Notation "f1 =2 f2" := (eqrel f1 f2)
(at level 70, no associativity) : fun_scope.
Notation "f1 =2 f2 :> A" := (f1 =2 (f2 : A))
(at level 70, f2 at next level, A at level 90) : fun_scope.
Section Composition.
Variables A B C : Type.
Definition funcomp u (f : B -> A) (g : C -> B) x := let: tt := u in f (g x).
Definition catcomp u g f := funcomp u f g.
Local Notation comp := (funcomp tt).
Definition pcomp (f : B -> option A) (g : C -> option B) x := obind f (g x).
Lemma eq_comp f f' g g' : f =1 f' -> g =1 g' -> comp f g =1 comp f' g'.
Proof. by move=> eq_ff' eq_gg' x; rewrite /= eq_gg' eq_ff'. Qed.
End Composition.
Notation comp := (funcomp tt).
Notation "@ 'comp'" := (fun A B C => @funcomp A B C tt).
Notation "f1 \o f2" := (comp f1 f2)
(at level 50, format "f1 \o '/ ' f2") : fun_scope.
Notation "f1 \; f2" := (catcomp tt f1 f2)
(at level 60, right associativity, format "f1 \; '/ ' f2") : fun_scope.
Notation "[ 'eta' f ]" := (fun x => f x)
(at level 0, format "[ 'eta' f ]") : fun_scope.
Notation "'fun' => E" := (fun _ => E) (at level 200, only parsing) : fun_scope.
Notation id := (fun x => x).
Notation "@ 'id' T" := (fun x : T => x)
(at level 10, T at level 8, only parsing) : fun_scope.
Definition id_head T u x : T := let: tt := u in x.
Definition explicit_id_key := tt.
Notation idfun := (id_head tt).
Notation "@ 'idfun' T " := (@id_head T explicit_id_key)
(at level 10, T at level 8, format "@ 'idfun' T") : fun_scope.
Definition phant_id T1 T2 v1 v2 := phantom T1 v1 -> phantom T2 v2.
(* Strong sigma types. *)
Section Tag.
Variables (I : Type) (i : I) (T_ U_ : I -> Type).
Definition tag := projT1.
Definition tagged : forall w, T_(tag w) := @projT2 I [eta T_].
Definition Tagged x := @existT I [eta T_] i x.
Definition tag2 (w : @sigT2 I T_ U_) := let: existT2 _ _ i _ _ := w in i.
Definition tagged2 w : T_(tag2 w) := let: existT2 _ _ _ x _ := w in x.
Definition tagged2' w : U_(tag2 w) := let: existT2 _ _ _ _ y := w in y.
Definition Tagged2 x y := @existT2 I [eta T_] [eta U_] i x y.
End Tag.
Arguments Tagged [I i].
Arguments Tagged2 [I i].
Prenex Implicits tag tagged Tagged tag2 tagged2 tagged2' Tagged2.
Coercion tag_of_tag2 I T_ U_ (w : @sigT2 I T_ U_) :=
Tagged (fun i => T_ i * U_ i)%type (tagged2 w, tagged2' w).
Lemma all_tag I T U :
(forall x : I, {y : T x & U x y}) ->
{f : forall x, T x & forall x, U x (f x)}.
Proof. by move=> fP; exists (fun x => tag (fP x)) => x; case: (fP x). Qed.
Lemma all_tag2 I T U V :
(forall i : I, {y : T i & U i y & V i y}) ->
{f : forall i, T i & forall i, U i (f i) & forall i, V i (f i)}.
Proof. by case/all_tag=> f /all_pair[]; exists f. Qed.
(* Refinement types. *)
(* Prenex Implicits and renaming. *)
Notation sval := (@proj1_sig _ _).
Notation "@ 'sval'" := (@proj1_sig) (at level 10, format "@ 'sval'").
Section Sig.
Variables (T : Type) (P Q : T -> Prop).
Lemma svalP (u : sig P) : P (sval u). Proof. by case: u. Qed.
Definition s2val (u : sig2 P Q) := let: exist2 _ _ x _ _ := u in x.
Lemma s2valP u : P (s2val u). Proof. by case: u. Qed.
Lemma s2valP' u : Q (s2val u). Proof. by case: u. Qed.
End Sig.
Prenex Implicits svalP s2val s2valP s2valP'.
Coercion tag_of_sig I P (u : @sig I P) := Tagged P (svalP u).
Coercion sig_of_sig2 I P Q (u : @sig2 I P Q) :=
exist (fun i => P i /\ Q i) (s2val u) (conj (s2valP u) (s2valP' u)).
Lemma all_sig I T P :
(forall x : I, {y : T x | P x y}) ->
{f : forall x, T x | forall x, P x (f x)}.
Proof. by case/all_tag=> f; exists f. Qed.
Lemma all_sig2 I T P Q :
(forall x : I, {y : T x | P x y & Q x y}) ->
{f : forall x, T x | forall x, P x (f x) & forall x, Q x (f x)}.
Proof. by case/all_sig=> f /all_pair[]; exists f. Qed.
Section Morphism.
Variables (aT rT sT : Type) (f : aT -> rT).
(* Morphism property for unary and binary functions *)
Definition morphism_1 aF rF := forall x, f (aF x) = rF (f x).
Definition morphism_2 aOp rOp := forall x y, f (aOp x y) = rOp (f x) (f y).
(* Homomorphism property for unary and binary relations *)
Definition homomorphism_1 (aP rP : _ -> Prop) := forall x, aP x -> rP (f x).
Definition homomorphism_2 (aR rR : _ -> _ -> Prop) :=
forall x y, aR x y -> rR (f x) (f y).
(* Stability property for unary and binary relations *)
Definition monomorphism_1 (aP rP : _ -> sT) := forall x, rP (f x) = aP x.
Definition monomorphism_2 (aR rR : _ -> _ -> sT) :=
forall x y, rR (f x) (f y) = aR x y.
End Morphism.
Notation "{ 'morph' f : x / a >-> r }" :=
(morphism_1 f (fun x => a) (fun x => r))
(at level 0, f at level 99, x ident,
format "{ 'morph' f : x / a >-> r }") : type_scope.
Notation "{ 'morph' f : x / a }" :=
(morphism_1 f (fun x => a) (fun x => a))
(at level 0, f at level 99, x ident,
format "{ 'morph' f : x / a }") : type_scope.
Notation "{ 'morph' f : x y / a >-> r }" :=
(morphism_2 f (fun x y => a) (fun x y => r))
(at level 0, f at level 99, x ident, y ident,
format "{ 'morph' f : x y / a >-> r }") : type_scope.
Notation "{ 'morph' f : x y / a }" :=
(morphism_2 f (fun x y => a) (fun x y => a))
(at level 0, f at level 99, x ident, y ident,
format "{ 'morph' f : x y / a }") : type_scope.
Notation "{ 'homo' f : x / a >-> r }" :=
(homomorphism_1 f (fun x => a) (fun x => r))
(at level 0, f at level 99, x ident,
format "{ 'homo' f : x / a >-> r }") : type_scope.
Notation "{ 'homo' f : x / a }" :=
(homomorphism_1 f (fun x => a) (fun x => a))
(at level 0, f at level 99, x ident,
format "{ 'homo' f : x / a }") : type_scope.
Notation "{ 'homo' f : x y / a >-> r }" :=
(homomorphism_2 f (fun x y => a) (fun x y => r))
(at level 0, f at level 99, x ident, y ident,
format "{ 'homo' f : x y / a >-> r }") : type_scope.
Notation "{ 'homo' f : x y / a }" :=
(homomorphism_2 f (fun x y => a) (fun x y => a))
(at level 0, f at level 99, x ident, y ident,
format "{ 'homo' f : x y / a }") : type_scope.
Notation "{ 'homo' f : x y /~ a }" :=
(homomorphism_2 f (fun y x => a) (fun x y => a))
(at level 0, f at level 99, x ident, y ident,
format "{ 'homo' f : x y /~ a }") : type_scope.
Notation "{ 'mono' f : x / a >-> r }" :=
(monomorphism_1 f (fun x => a) (fun x => r))
(at level 0, f at level 99, x ident,
format "{ 'mono' f : x / a >-> r }") : type_scope.
Notation "{ 'mono' f : x / a }" :=
(monomorphism_1 f (fun x => a) (fun x => a))
(at level 0, f at level 99, x ident,
format "{ 'mono' f : x / a }") : type_scope.
Notation "{ 'mono' f : x y / a >-> r }" :=
(monomorphism_2 f (fun x y => a) (fun x y => r))
(at level 0, f at level 99, x ident, y ident,
format "{ 'mono' f : x y / a >-> r }") : type_scope.
Notation "{ 'mono' f : x y / a }" :=
(monomorphism_2 f (fun x y => a) (fun x y => a))
(at level 0, f at level 99, x ident, y ident,
format "{ 'mono' f : x y / a }") : type_scope.
Notation "{ 'mono' f : x y /~ a }" :=
(monomorphism_2 f (fun y x => a) (fun x y => a))
(at level 0, f at level 99, x ident, y ident,
format "{ 'mono' f : x y /~ a }") : type_scope.
(* In an intuitionistic setting, we have two degrees of injectivity. The *)
(* weaker one gives only simplification, and the strong one provides a left *)
(* inverse (we show in `fintype' that they coincide for finite types). *)
(* We also define an intermediate version where the left inverse is only a *)
(* partial function. *)
Section Injections.
(* rT must come first so we can use @ to mitigate the Coq 1st order *)
(* unification bug (e..g., Coq can't infer rT from a "cancel" lemma). *)
Variables (rT aT : Type) (f : aT -> rT).
Definition injective := forall x1 x2, f x1 = f x2 -> x1 = x2.
Definition cancel g := forall x, g (f x) = x.
Definition pcancel g := forall x, g (f x) = Some x.
Definition ocancel (g : aT -> option rT) h := forall x, oapp h x (g x) = x.
Lemma can_pcan g : cancel g -> pcancel (fun y => Some (g y)).
Proof. by move=> fK x; congr (Some _). Qed.
Lemma pcan_inj g : pcancel g -> injective.
Proof. by move=> fK x y /(congr1 g); rewrite !fK => [[]]. Qed.
Lemma can_inj g : cancel g -> injective.
Proof. by move/can_pcan; apply: pcan_inj. Qed.
Lemma canLR g x y : cancel g -> x = f y -> g x = y.
Proof. by move=> fK ->. Qed.
Lemma canRL g x y : cancel g -> f x = y -> x = g y.
Proof. by move=> fK <-. Qed.
End Injections.
Lemma Some_inj {T} : injective (@Some T). Proof. by move=> x y []. Qed.
(* Force implicits to use as a view. *)
Prenex Implicits Some_inj.
(* cancellation lemmas for dependent type casts. *)
Lemma esymK T x y : cancel (@esym T x y) (@esym T y x).
Proof. by case: y /. Qed.
Lemma etrans_id T x y (eqxy : x = y :> T) : etrans (erefl x) eqxy = eqxy.
Proof. by case: y / eqxy. Qed.
Section InjectionsTheory.
Variables (A B C : Type) (f g : B -> A) (h : C -> B).
Lemma inj_id : injective (@id A).
Proof. by []. Qed.
Lemma inj_can_sym f' : cancel f f' -> injective f' -> cancel f' f.
Proof. by move=> fK injf' x; apply: injf'. Qed.
Lemma inj_comp : injective f -> injective h -> injective (f \o h).
Proof. by move=> injf injh x y /injf; apply: injh. Qed.
Lemma can_comp f' h' : cancel f f' -> cancel h h' -> cancel (f \o h) (h' \o f').
Proof. by move=> fK hK x; rewrite /= fK hK. Qed.
Lemma pcan_pcomp f' h' :
pcancel f f' -> pcancel h h' -> pcancel (f \o h) (pcomp h' f').
Proof. by move=> fK hK x; rewrite /pcomp fK /= hK. Qed.
Lemma eq_inj : injective f -> f =1 g -> injective g.
Proof. by move=> injf eqfg x y; rewrite -2!eqfg; apply: injf. Qed.
Lemma eq_can f' g' : cancel f f' -> f =1 g -> f' =1 g' -> cancel g g'.
Proof. by move=> fK eqfg eqfg' x; rewrite -eqfg -eqfg'. Qed.
Lemma inj_can_eq f' : cancel f f' -> injective f' -> cancel g f' -> f =1 g.
Proof. by move=> fK injf' gK x; apply: injf'; rewrite fK. Qed.
End InjectionsTheory.
Section Bijections.
Variables (A B : Type) (f : B -> A).
CoInductive bijective : Prop := Bijective g of cancel f g & cancel g f.
Hypothesis bijf : bijective.
Lemma bij_inj : injective f.
Proof. by case: bijf => g fK _; apply: can_inj fK. Qed.
Lemma bij_can_sym f' : cancel f' f <-> cancel f f'.
Proof.
split=> fK; first exact: inj_can_sym fK bij_inj.
by case: bijf => h _ hK x; rewrite -[x]hK fK.
Qed.
Lemma bij_can_eq f' f'' : cancel f f' -> cancel f f'' -> f' =1 f''.
Proof.
by move=> fK fK'; apply: (inj_can_eq _ bij_inj); apply/bij_can_sym.
Qed.
End Bijections.
Section BijectionsTheory.
Variables (A B C : Type) (f : B -> A) (h : C -> B).
Lemma eq_bij : bijective f -> forall g, f =1 g -> bijective g.
Proof. by case=> f' fK f'K g eqfg; exists f'; eapply eq_can; eauto. Qed.
Lemma bij_comp : bijective f -> bijective h -> bijective (f \o h).
Proof.
by move=> [f' fK f'K] [h' hK h'K]; exists (h' \o f'); apply: can_comp; auto.
Qed.
Lemma bij_can_bij : bijective f -> forall f', cancel f f' -> bijective f'.
Proof. by move=> bijf; exists f; first by apply/(bij_can_sym bijf). Qed.
End BijectionsTheory.
Section Involutions.
Variables (A : Type) (f : A -> A).
Definition involutive := cancel f f.
Hypothesis Hf : involutive.
Lemma inv_inj : injective f. Proof. exact: can_inj Hf. Qed.
Lemma inv_bij : bijective f. Proof. by exists f. Qed.
End Involutions.
Section OperationProperties.
Variables S T R : Type.
Section SopTisR.
Implicit Type op : S -> T -> R.
Definition left_inverse e inv op := forall x, op (inv x) x = e.
Definition right_inverse e inv op := forall x, op x (inv x) = e.
Definition left_injective op := forall x, injective (op^~ x).
Definition right_injective op := forall y, injective (op y).
End SopTisR.
Section SopTisS.
Implicit Type op : S -> T -> S.
Definition right_id e op := forall x, op x e = x.
Definition left_zero z op := forall x, op z x = z.
Definition right_commutative op := forall x y z, op (op x y) z = op (op x z) y.
Definition left_distributive op add :=
forall x y z, op (add x y) z = add (op x z) (op y z).
Definition right_loop inv op := forall y, cancel (op^~ y) (op^~ (inv y)).
Definition rev_right_loop inv op := forall y, cancel (op^~ (inv y)) (op^~ y).
End SopTisS.
Section SopTisT.
Implicit Type op : S -> T -> T.
Definition left_id e op := forall x, op e x = x.
Definition right_zero z op := forall x, op x z = z.
Definition left_commutative op := forall x y z, op x (op y z) = op y (op x z).
Definition right_distributive op add :=
forall x y z, op x (add y z) = add (op x y) (op x z).
Definition left_loop inv op := forall x, cancel (op x) (op (inv x)).
Definition rev_left_loop inv op := forall x, cancel (op (inv x)) (op x).
End SopTisT.
Section SopSisT.
Implicit Type op : S -> S -> T.
Definition self_inverse e op := forall x, op x x = e.
Definition commutative op := forall x y, op x y = op y x.
End SopSisT.
Section SopSisS.
Implicit Type op : S -> S -> S.
Definition idempotent op := forall x, op x x = x.
Definition associative op := forall x y z, op x (op y z) = op (op x y) z.
Definition interchange op1 op2 :=
forall x y z t, op1 (op2 x y) (op2 z t) = op2 (op1 x z) (op1 y t).
End SopSisS.
End OperationProperties.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BAI_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O21BAI_BLACKBOX_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o21bai (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BAI_BLACKBOX_V
|
/*================================================
Thomas Gorham
ECE 441 Spring 2017
Project 2 - lfsr
Description: This module implements a LFSR for
the generation of pseudorandom numbers.
It will use an 8 bit register with the polynomial
x^8+x^6+x^5+x^4+1
================================================*/
`timescale 100 ns / 1 ns
module lfsr(clk, ar, sr, q);
/*======================================
Input/Output Declaration
======================================*/
input clk, ar;
output q; // Output clocks
output reg [7:0] sr; // Need a 26 bit counter reg
/*======================================
Internal wires/registers
======================================*/
wire polynomial;
/*======================================
Asynchronous Logic
======================================*/
assign polynomial = sr[7]^sr[5]^sr[4]^sr[3]; // 8, 6, 5, 4
assign q = sr[7];
/*======================================
Synchronous Logic
======================================*/
always @ (posedge clk or negedge ar)
begin
if(~ar) // If reset has negedge down to level 0,
begin
sr <= 8'b00000001;
end
else
begin
sr <= { sr[6:0], polynomial };
end
end
endmodule |
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// mrram.v: Multiread-RAM based on bank replication using generic dual-ported RAM //
// with optional single-stage or two-stage bypass/ for normal mode ports //
// //
// Author: Ameer M.S. Abdelhadi ([email protected], [email protected]) //
// Switched SRAM-based Multi-ported RAM; University of British Columbia, 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module mrram
#( parameter MEMD = 16, // memory depth
parameter DATW = 32, // data width
parameter nRP = 3 , // number of reading ports
parameter BYPS = 1 , // bypass? 0:none; 1: single-stage; 2:two-stages
parameter ZERO = 0 , // binary / Initial RAM with zeros (has priority over FILE)
parameter FILE = "" // initialization mif file (don't pass extension), optional
)( input clk , // clock
input WEnb , // write enable (1 port)
input [`log2(MEMD) -1:0] WAddr, // write address (1 port)
input [DATW -1:0] WData, // write data (1 port)
input [`log2(MEMD)*nRP-1:0] RAddr, // read addresses - packed from nRP read ports
output reg [DATW *nRP-1:0] RData); // read data - packed from nRP read ports
localparam ADRW = `log2(MEMD); // address width
// unpacked read addresses/data
reg [ADRW-1:0] RAddr_upk [nRP-1:0]; // read addresses - unpacked 2D array
wire [DATW-1:0] RData_upk [nRP-1:0]; // read data - unpacked 2D array
// unpack read addresses; pack read data
`ARRINIT;
always @* begin
// packing/unpacking arrays into 1D/2D/3D structures; see utils.vh for definitions
`ARR1D2D(nRP,ADRW,RAddr,RAddr_upk);
`ARR2D1D(nRP,DATW,RData_upk,RData);
end
// generate and instantiate generic RAM blocks
genvar rpi;
generate
for (rpi=0 ; rpi<nRP ; rpi=rpi+1) begin: RPORTrpi
// generic dual-ported ram instantiation
dpram_bbs #( .MEMD (MEMD ), // memory depth
.DATW (DATW ), // data width
.BYPS (BYPS ), // bypass? 0: none; 1: single-stage; 2:two-stages
.ZERO (ZERO ), // binary / Initial RAM with zeros (has priority over INITFILE)
.FILE (FILE )) // initialization file, optional
dpram_bbsi ( .clk (clk ), // clock - in
.WEnb_A (1'b0 ), // write enable - in
.WEnb_B (WEnb ), // write enable - in
.Addr_A (RAddr_upk[rpi]), // write address - in : [`log2(MEMD)-1:0]
.Addr_B (WAddr ), // write address - in : [`log2(MEMD)-1:0]
.WData_A ({DATW{1'b1}} ), // write data - in : [DATW -1:0] / constant
.WData_B (WData ), // write data - in : [DATW -1:0]
.RData_A (RData_upk[rpi]), // read data - out: [DATW -1:0]
.RData_B ( )); // read data - out: [DATW -1:0]
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4_FUNCTIONAL_V
`define SKY130_FD_SC_HS__NAND4_FUNCTIONAL_V
/**
* nand4: 4-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand4 (
VPWR,
VGND,
Y ,
A ,
B ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
input C ;
input D ;
// Local signals
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , D, C, B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4_FUNCTIONAL_V |
//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner ([email protected])
//
// Copyright (c) 2004 Guy Hutchison ([email protected])
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
module tv80_core (/*AUTOARG*/
// Outputs
m1_n, iorq, no_read, write, rfsh_n, halt_n, busak_n, A, dout, mc,
ts, intcycle_n, IntE, stop,
// Inputs
reset_n, clk, cen, wait_n, int_n, nmi_n, busrq_n, dinst, di
);
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
parameter Mode = 1; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
parameter Flag_C = 0;
parameter Flag_N = 1;
parameter Flag_P = 2;
parameter Flag_X = 3;
parameter Flag_H = 4;
parameter Flag_Y = 5;
parameter Flag_Z = 6;
parameter Flag_S = 7;
input reset_n;
input clk;
input cen;
input wait_n;
input int_n;
input nmi_n;
input busrq_n;
output m1_n;
output iorq;
output no_read;
output write;
output rfsh_n;
output halt_n;
output busak_n;
output [15:0] A;
input [7:0] dinst;
input [7:0] di;
output [7:0] dout;
output [6:0] mc;
output [6:0] ts;
output intcycle_n;
output IntE;
output stop;
reg m1_n;
reg iorq;
`ifdef TV80_REFRESH
reg rfsh_n;
`endif
reg halt_n;
reg busak_n;
reg [15:0] A;
reg [7:0] dout;
reg [6:0] mc;
reg [6:0] ts;
reg intcycle_n;
reg IntE;
reg stop;
parameter aNone = 3'b111;
parameter aBC = 3'b000;
parameter aDE = 3'b001;
parameter aXY = 3'b010;
parameter aIOA = 3'b100;
parameter aSP = 3'b101;
parameter aZI = 3'b110;
// Registers
reg [7:0] ACC, F;
reg [7:0] Ap, Fp;
reg [7:0] I;
`ifdef TV80_REFRESH
reg [7:0] R;
`endif
reg [15:0] SP, PC;
reg [7:0] RegDIH;
reg [7:0] RegDIL;
wire [15:0] RegBusA;
wire [15:0] RegBusB;
wire [15:0] RegBusC;
reg [2:0] RegAddrA_r;
reg [2:0] RegAddrA;
reg [2:0] RegAddrB_r;
reg [2:0] RegAddrB;
reg [2:0] RegAddrC;
reg RegWEH;
reg RegWEL;
reg Alternate;
// Help Registers
reg [15:0] TmpAddr; // Temporary address register
reg [7:0] IR; // Instruction register
reg [1:0] ISet; // Instruction set selector
reg [15:0] RegBusA_r;
reg [15:0] ID16;
reg [7:0] Save_Mux;
reg [6:0] tstate;
reg [6:0] mcycle;
reg last_mcycle, last_tstate;
reg IntE_FF1;
reg IntE_FF2;
reg Halt_FF;
reg BusReq_s;
reg BusAck;
reg ClkEn;
reg NMI_s;
reg INT_s;
reg [1:0] IStatus;
reg [7:0] DI_Reg;
reg T_Res;
reg [1:0] XY_State;
reg [2:0] Pre_XY_F_M;
reg NextIs_XY_Fetch;
reg XY_Ind;
reg No_BTR;
reg BTR_r;
reg Auto_Wait;
reg Auto_Wait_t1;
reg Auto_Wait_t2;
reg IncDecZ;
// ALU signals
reg [7:0] BusB;
reg [7:0] BusA;
wire [7:0] ALU_Q;
wire [7:0] F_Out;
// Registered micro code outputs
reg [4:0] Read_To_Reg_r;
reg Arith16_r;
reg Z16_r;
reg [3:0] ALU_Op_r;
reg Save_ALU_r;
reg PreserveC_r;
reg [2:0] mcycles;
// Micro code outputs
wire [2:0] mcycles_d;
wire [2:0] tstates;
reg IntCycle;
reg NMICycle;
wire Inc_PC;
wire Inc_WZ;
wire [3:0] IncDec_16;
wire [1:0] Prefix;
wire Read_To_Acc;
wire Read_To_Reg;
wire [3:0] Set_BusB_To;
wire [3:0] Set_BusA_To;
wire [3:0] ALU_Op;
wire Save_ALU;
wire PreserveC;
wire Arith16;
wire [2:0] Set_Addr_To;
wire Jump;
wire JumpE;
wire JumpXY;
wire Call;
wire RstP;
wire LDZ;
wire LDW;
wire LDSPHL;
wire iorq_i;
wire [2:0] Special_LD;
wire ExchangeDH;
wire ExchangeRp;
wire ExchangeAF;
wire ExchangeRS;
wire I_DJNZ;
wire I_CPL;
wire I_CCF;
wire I_SCF;
wire I_RETN;
wire I_BT;
wire I_BC;
wire I_BTR;
wire I_RLD;
wire I_RRD;
wire I_INRC;
wire SetDI;
wire SetEI;
wire [1:0] IMode;
wire Halt;
reg [15:0] PC16;
reg [15:0] PC16_B;
reg [15:0] SP16, SP16_A, SP16_B;
reg [15:0] ID16_B;
reg Oldnmi_n;
tv80_mcode #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_mcode
(
.IR (IR),
.ISet (ISet),
.MCycle (mcycle),
.F (F),
.NMICycle (NMICycle),
.IntCycle (IntCycle),
.MCycles (mcycles_d),
.TStates (tstates),
.Prefix (Prefix),
.Inc_PC (Inc_PC),
.Inc_WZ (Inc_WZ),
.IncDec_16 (IncDec_16),
.Read_To_Acc (Read_To_Acc),
.Read_To_Reg (Read_To_Reg),
.Set_BusB_To (Set_BusB_To),
.Set_BusA_To (Set_BusA_To),
.ALU_Op (ALU_Op),
.Save_ALU (Save_ALU),
.PreserveC (PreserveC),
.Arith16 (Arith16),
.Set_Addr_To (Set_Addr_To),
.IORQ (iorq_i),
.Jump (Jump),
.JumpE (JumpE),
.JumpXY (JumpXY),
.Call (Call),
.RstP (RstP),
.LDZ (LDZ),
.LDW (LDW),
.LDSPHL (LDSPHL),
.Special_LD (Special_LD),
.ExchangeDH (ExchangeDH),
.ExchangeRp (ExchangeRp),
.ExchangeAF (ExchangeAF),
.ExchangeRS (ExchangeRS),
.I_DJNZ (I_DJNZ),
.I_CPL (I_CPL),
.I_CCF (I_CCF),
.I_SCF (I_SCF),
.I_RETN (I_RETN),
.I_BT (I_BT),
.I_BC (I_BC),
.I_BTR (I_BTR),
.I_RLD (I_RLD),
.I_RRD (I_RRD),
.I_INRC (I_INRC),
.SetDI (SetDI),
.SetEI (SetEI),
.IMode (IMode),
.Halt (Halt),
.NoRead (no_read),
.Write (write)
);
tv80_alu #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_alu
(
.Arith16 (Arith16_r),
.Z16 (Z16_r),
.ALU_Op (ALU_Op_r),
.IR (IR[5:0]),
.ISet (ISet),
.BusA (BusA),
.BusB (BusB),
.F_In (F),
.Q (ALU_Q),
.F_Out (F_Out)
);
function [6:0] number_to_bitvec;
input [2:0] num;
begin
case (num)
1 : number_to_bitvec = 7'b0000001;
2 : number_to_bitvec = 7'b0000010;
3 : number_to_bitvec = 7'b0000100;
4 : number_to_bitvec = 7'b0001000;
5 : number_to_bitvec = 7'b0010000;
6 : number_to_bitvec = 7'b0100000;
7 : number_to_bitvec = 7'b1000000;
default : number_to_bitvec = 7'bx;
endcase // case(num)
end
endfunction // number_to_bitvec
function [2:0] mcyc_to_number;
input [6:0] mcyc;
begin
casez (mcyc)
7'b1zzzzzz : mcyc_to_number = 3'h7;
7'b01zzzzz : mcyc_to_number = 3'h6;
7'b001zzzz : mcyc_to_number = 3'h5;
7'b0001zzz : mcyc_to_number = 3'h4;
7'b00001zz : mcyc_to_number = 3'h3;
7'b000001z : mcyc_to_number = 3'h2;
7'b0000001 : mcyc_to_number = 3'h1;
default : mcyc_to_number = 3'h1;
endcase
end
endfunction
always @(/*AUTOSENSE*/mcycle or mcycles or tstate or tstates)
begin
case (mcycles)
1 : last_mcycle = mcycle[0];
2 : last_mcycle = mcycle[1];
3 : last_mcycle = mcycle[2];
4 : last_mcycle = mcycle[3];
5 : last_mcycle = mcycle[4];
6 : last_mcycle = mcycle[5];
7 : last_mcycle = mcycle[6];
default : last_mcycle = 1'bx;
endcase // case(mcycles)
case (tstates)
0 : last_tstate = tstate[0];
1 : last_tstate = tstate[1];
2 : last_tstate = tstate[2];
3 : last_tstate = tstate[3];
4 : last_tstate = tstate[4];
5 : last_tstate = tstate[5];
6 : last_tstate = tstate[6];
default : last_tstate = 1'bx;
endcase
end // always @ (...
always @(/*AUTOSENSE*/ALU_Q or BusAck or BusB or DI_Reg
or ExchangeRp or IR or Save_ALU_r or Set_Addr_To or XY_Ind
or XY_State or cen or last_tstate or mcycle)
begin
ClkEn = cen && ~ BusAck;
if (last_tstate)
T_Res = 1'b1;
else T_Res = 1'b0;
if (XY_State != 2'b00 && XY_Ind == 1'b0 &&
((Set_Addr_To == aXY) ||
(mcycle[0] && IR == 8'b11001011) ||
(mcycle[0] && IR == 8'b00110110)))
NextIs_XY_Fetch = 1'b1;
else
NextIs_XY_Fetch = 1'b0;
if (ExchangeRp)
Save_Mux = BusB;
else if (!Save_ALU_r)
Save_Mux = DI_Reg;
else
Save_Mux = ALU_Q;
end // always @ *
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0 )
begin
PC <= #1 0; // Program Counter
A <= #1 0;
TmpAddr <= #1 0;
IR <= #1 8'b00000000;
ISet <= #1 2'b00;
XY_State <= #1 2'b00;
IStatus <= #1 2'b00;
mcycles <= #1 3'b000;
dout <= #1 8'b00000000;
ACC <= #1 8'hFF;
F <= #1 8'hFF;
Ap <= #1 8'hFF;
Fp <= #1 8'hFF;
I <= #1 0;
`ifdef TV80_REFRESH
R <= #1 0;
`endif
SP <= #1 16'hFFFF;
Alternate <= #1 1'b0;
Read_To_Reg_r <= #1 5'b00000;
Arith16_r <= #1 1'b0;
BTR_r <= #1 1'b0;
Z16_r <= #1 1'b0;
ALU_Op_r <= #1 4'b0000;
Save_ALU_r <= #1 1'b0;
PreserveC_r <= #1 1'b0;
XY_Ind <= #1 1'b0;
end
else
begin
if (ClkEn == 1'b1 )
begin
ALU_Op_r <= #1 4'b0000;
Save_ALU_r <= #1 1'b0;
Read_To_Reg_r <= #1 5'b00000;
mcycles <= #1 mcycles_d;
if (IMode != 2'b11 )
begin
IStatus <= #1 IMode;
end
Arith16_r <= #1 Arith16;
PreserveC_r <= #1 PreserveC;
if (ISet == 2'b10 && ALU_Op[2] == 1'b0 && ALU_Op[0] == 1'b1 && mcycle[2] )
begin
Z16_r <= #1 1'b1;
end
else
begin
Z16_r <= #1 1'b0;
end
if (mcycle[0] && (tstate[1] | tstate[2] | tstate[3] ))
begin
// mcycle == 1 && tstate == 1, 2, || 3
if (tstate[2] && wait_n == 1'b1 )
begin
`ifdef TV80_REFRESH
if (Mode < 2 )
begin
A[7:0] <= #1 R;
A[15:8] <= #1 I;
R[6:0] <= #1 R[6:0] + 1;
end
`endif
if (Jump == 1'b0 && Call == 1'b0 && NMICycle == 1'b0 && IntCycle == 1'b0 && ~ (Halt_FF == 1'b1 || Halt == 1'b1) )
begin
PC <= #1 PC16;
end
if (IntCycle == 1'b1 && IStatus == 2'b01 )
begin
IR <= #1 8'b11111111;
end
else if (Halt_FF == 1'b1 || (IntCycle == 1'b1 && IStatus == 2'b10) || NMICycle == 1'b1 )
begin
IR <= #1 8'b00000000;
TmpAddr[7:0] <= #1 dinst; // Special M1 vector fetch
end
else
begin
IR <= #1 dinst;
end
ISet <= #1 2'b00;
if (Prefix != 2'b00 )
begin
if (Prefix == 2'b11 )
begin
if (IR[5] == 1'b1 )
begin
XY_State <= #1 2'b10;
end
else
begin
XY_State <= #1 2'b01;
end
end
else
begin
if (Prefix == 2'b10 )
begin
XY_State <= #1 2'b00;
XY_Ind <= #1 1'b0;
end
ISet <= #1 Prefix;
end
end
else
begin
XY_State <= #1 2'b00;
XY_Ind <= #1 1'b0;
end
end // if (tstate == 2 && wait_n == 1'b1 )
end
else
begin
// either (mcycle > 1) OR (mcycle == 1 AND tstate > 3)
if (mcycle[5] )
begin
XY_Ind <= #1 1'b1;
if (Prefix == 2'b01 )
begin
ISet <= #1 2'b01;
end
end
if (T_Res == 1'b1 )
begin
BTR_r <= #1 (I_BT || I_BC || I_BTR) && ~ No_BTR;
if (Jump == 1'b1 )
begin
A[15:8] <= #1 DI_Reg;
A[7:0] <= #1 TmpAddr[7:0];
PC[15:8] <= #1 DI_Reg;
PC[7:0] <= #1 TmpAddr[7:0];
end
else if (JumpXY == 1'b1 )
begin
A <= #1 RegBusC;
PC <= #1 RegBusC;
end else if (Call == 1'b1 || RstP == 1'b1 )
begin
A <= #1 TmpAddr;
PC <= #1 TmpAddr;
end
else if (last_mcycle && NMICycle == 1'b1 )
begin
A <= #1 16'b0000000001100110;
PC <= #1 16'b0000000001100110;
end
else if (mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 )
begin
A[15:8] <= #1 I;
A[7:0] <= #1 TmpAddr[7:0];
PC[15:8] <= #1 I;
PC[7:0] <= #1 TmpAddr[7:0];
end
else
begin
case (Set_Addr_To)
aXY :
begin
if (XY_State == 2'b00 )
begin
A <= #1 RegBusC;
end
else
begin
if (NextIs_XY_Fetch == 1'b1 )
begin
A <= #1 PC;
end
else
begin
A <= #1 TmpAddr;
end
end // else: !if(XY_State == 2'b00 )
end // case: aXY
aIOA :
begin
if (Mode == 3 )
begin
// Memory map I/O on GBZ80
A[15:8] <= #1 8'hFF;
end
else if (Mode == 2 )
begin
// Duplicate I/O address on 8080
A[15:8] <= #1 DI_Reg;
end
else
begin
A[15:8] <= #1 ACC;
end
A[7:0] <= #1 DI_Reg;
end // case: aIOA
aSP :
begin
A <= #1 SP;
end
aBC :
begin
if (Mode == 3 && iorq_i == 1'b1 )
begin
// Memory map I/O on GBZ80
A[15:8] <= #1 8'hFF;
A[7:0] <= #1 RegBusC[7:0];
end
else
begin
A <= #1 RegBusC;
end
end // case: aBC
aDE :
begin
A <= #1 RegBusC;
end
aZI :
begin
if (Inc_WZ == 1'b1 )
begin
A <= #1 TmpAddr + 16'd1; // ***kyp*** A <= #1 TmpAddr + 1;
end
else
begin
A[15:8] <= #1 DI_Reg;
A[7:0] <= #1 TmpAddr[7:0];
end
end // case: aZI
default :
begin
A <= #1 PC;
end
endcase // case(Set_Addr_To)
end // else: !if(mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 )
Save_ALU_r <= #1 Save_ALU;
ALU_Op_r <= #1 ALU_Op;
if (I_CPL == 1'b1 )
begin
// CPL
ACC <= #1 ~ ACC;
F[Flag_Y] <= #1 ~ ACC[5];
F[Flag_H] <= #1 1'b1;
F[Flag_X] <= #1 ~ ACC[3];
F[Flag_N] <= #1 1'b1;
end
if (I_CCF == 1'b1 )
begin
// CCF
F[Flag_C] <= #1 ~ F[Flag_C];
F[Flag_Y] <= #1 ACC[5];
F[Flag_H] <= #1 F[Flag_C];
F[Flag_X] <= #1 ACC[3];
F[Flag_N] <= #1 1'b0;
end
if (I_SCF == 1'b1 )
begin
// SCF
F[Flag_C] <= #1 1'b1;
F[Flag_Y] <= #1 ACC[5];
F[Flag_H] <= #1 1'b0;
F[Flag_X] <= #1 ACC[3];
F[Flag_N] <= #1 1'b0;
end
end // if (T_Res == 1'b1 )
if (tstate[2] && wait_n == 1'b1 )
begin
if (ISet == 2'b01 && mcycle[6] )
begin
IR <= #1 dinst;
end
if (JumpE == 1'b1 )
begin
PC <= #1 PC16;
end
else if (Inc_PC == 1'b1 )
begin
//PC <= #1 PC + 1;
PC <= #1 PC16;
end
if (BTR_r == 1'b1 )
begin
//PC <= #1 PC - 2;
PC <= #1 PC16;
end
if (RstP == 1'b1 )
begin
TmpAddr <= #1 { 10'h0, IR[5:3], 3'h0 };
//TmpAddr <= #1 (others =>1'b0);
//TmpAddr[5:3] <= #1 IR[5:3];
end
end
if (tstate[3] && mcycle[5] )
begin
TmpAddr <= #1 SP16;
end
if ((tstate[2] && wait_n == 1'b1) || (tstate[4] && mcycle[0]) )
begin
if (IncDec_16[2:0] == 3'b111 )
begin
SP <= #1 SP16;
end
end
if (LDSPHL == 1'b1 )
begin
SP <= #1 RegBusC;
end
if (ExchangeAF == 1'b1 )
begin
Ap <= #1 ACC;
ACC <= #1 Ap;
Fp <= #1 F;
F <= #1 Fp;
end
if (ExchangeRS == 1'b1 )
begin
Alternate <= #1 ~ Alternate;
end
end // else: !if(mcycle == 3'b001 && tstate(2) == 1'b0 )
if (tstate[3] )
begin
if (LDZ == 1'b1 )
begin
TmpAddr[7:0] <= #1 DI_Reg;
end
if (LDW == 1'b1 )
begin
TmpAddr[15:8] <= #1 DI_Reg;
end
if (Special_LD[2] == 1'b1 )
begin
case (Special_LD[1:0])
2'b00 :
begin
ACC <= #1 I;
F[Flag_P] <= #1 IntE_FF2;
F[Flag_Z] <= (I == 0);
F[Flag_S] <= I[7];
F[Flag_H] <= 0;
F[Flag_N] <= 0;
end
2'b01 :
begin
`ifdef TV80_REFRESH
ACC <= #1 R;
`else
ACC <= #1 0;
`endif
F[Flag_P] <= #1 IntE_FF2;
F[Flag_Z] <= (I == 0);
F[Flag_S] <= I[7];
F[Flag_H] <= 0;
F[Flag_N] <= 0;
end
2'b10 :
I <= #1 ACC;
`ifdef TV80_REFRESH
default :
R <= #1 ACC;
`else
default : ;
`endif
endcase
end
end // if (tstate == 3 )
if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 )
begin
if (Mode == 3 )
begin
F[6] <= #1 F_Out[6];
F[5] <= #1 F_Out[5];
F[7] <= #1 F_Out[7];
if (PreserveC_r == 1'b0 )
begin
F[4] <= #1 F_Out[4];
end
end
else
begin
F[7:1] <= #1 F_Out[7:1];
if (PreserveC_r == 1'b0 )
begin
F[Flag_C] <= #1 F_Out[0];
end
end
end // if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 )
if (T_Res == 1'b1 && I_INRC == 1'b1 )
begin
F[Flag_H] <= #1 1'b0;
F[Flag_N] <= #1 1'b0;
if (DI_Reg[7:0] == 8'b00000000 )
begin
F[Flag_Z] <= #1 1'b1;
end
else
begin
F[Flag_Z] <= #1 1'b0;
end
F[Flag_S] <= #1 DI_Reg[7];
F[Flag_P] <= #1 ~ (^DI_Reg[7:0]);
end // if (T_Res == 1'b1 && I_INRC == 1'b1 )
if (tstate[1] && Auto_Wait_t1 == 1'b0 )
begin
dout <= #1 BusB;
if (I_RLD == 1'b1 )
begin
dout[3:0] <= #1 BusA[3:0];
dout[7:4] <= #1 BusB[3:0];
end
if (I_RRD == 1'b1 )
begin
dout[3:0] <= #1 BusB[7:4];
dout[7:4] <= #1 BusA[3:0];
end
end
if (T_Res == 1'b1 )
begin
Read_To_Reg_r[3:0] <= #1 Set_BusA_To;
Read_To_Reg_r[4] <= #1 Read_To_Reg;
if (Read_To_Acc == 1'b1 )
begin
Read_To_Reg_r[3:0] <= #1 4'b0111;
Read_To_Reg_r[4] <= #1 1'b1;
end
end
if (tstate[1] && I_BT == 1'b1 )
begin
F[Flag_X] <= #1 ALU_Q[3];
F[Flag_Y] <= #1 ALU_Q[1];
F[Flag_H] <= #1 1'b0;
F[Flag_N] <= #1 1'b0;
end
if (I_BC == 1'b1 || I_BT == 1'b1 )
begin
F[Flag_P] <= #1 IncDecZ;
end
if ((tstate[1] && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||
(Save_ALU_r == 1'b1 && ALU_Op_r != 4'b0111) )
begin
case (Read_To_Reg_r)
5'b10111 :
ACC <= #1 Save_Mux;
5'b10110 :
dout <= #1 Save_Mux;
5'b11000 :
SP[7:0] <= #1 Save_Mux;
5'b11001 :
SP[15:8] <= #1 Save_Mux;
5'b11011 :
F <= #1 Save_Mux;
default : ;
endcase
end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||...
end // if (ClkEn == 1'b1 )
end // else: !if(reset_n == 1'b0 )
end
//-------------------------------------------------------------------------
//
// BC('), DE('), HL('), IX && IY
//
//-------------------------------------------------------------------------
always @ (posedge clk)
begin
if (ClkEn == 1'b1 )
begin
// Bus A / Write
RegAddrA_r <= #1 { Alternate, Set_BusA_To[2:1] };
if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusA_To[2:1] == 2'b10 )
begin
RegAddrA_r <= #1 { XY_State[1], 2'b11 };
end
// Bus B
RegAddrB_r <= #1 { Alternate, Set_BusB_To[2:1] };
if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusB_To[2:1] == 2'b10 )
begin
RegAddrB_r <= #1 { XY_State[1], 2'b11 };
end
// Address from register
RegAddrC <= #1 { Alternate, Set_Addr_To[1:0] };
// Jump (HL), LD SP,HL
if ((JumpXY == 1'b1 || LDSPHL == 1'b1) )
begin
RegAddrC <= #1 { Alternate, 2'b10 };
end
if (((JumpXY == 1'b1 || LDSPHL == 1'b1) && XY_State != 2'b00) || (mcycle[5]) )
begin
RegAddrC <= #1 { XY_State[1], 2'b11 };
end
if (I_DJNZ == 1'b1 && Save_ALU_r == 1'b1 && Mode < 2 )
begin
IncDecZ <= #1 F_Out[Flag_Z];
end
if ((tstate[2] || (tstate[3] && mcycle[0])) && IncDec_16[2:0] == 3'b100 )
begin
if (ID16 == 0 )
begin
IncDecZ <= #1 1'b0;
end
else
begin
IncDecZ <= #1 1'b1;
end
end
RegBusA_r <= #1 RegBusA;
end
end // always @ (posedge clk)
always @(/*AUTOSENSE*/Alternate or ExchangeDH or IncDec_16
or RegAddrA_r or RegAddrB_r or XY_State or mcycle or tstate)
begin
if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && XY_State == 2'b00)
RegAddrA = { Alternate, IncDec_16[1:0] };
else if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && IncDec_16[1:0] == 2'b10)
RegAddrA = { XY_State[1], 2'b11 };
else if (ExchangeDH == 1'b1 && tstate[3])
RegAddrA = { Alternate, 2'b10 };
else if (ExchangeDH == 1'b1 && tstate[4])
RegAddrA = { Alternate, 2'b01 };
else
RegAddrA = RegAddrA_r;
if (ExchangeDH == 1'b1 && tstate[3])
RegAddrB = { Alternate, 2'b01 };
else
RegAddrB = RegAddrB_r;
end // always @ *
always @(/*AUTOSENSE*/ALU_Op_r or Auto_Wait_t1 or ExchangeDH
or IncDec_16 or Read_To_Reg_r or Save_ALU_r or mcycle
or tstate or wait_n)
begin
RegWEH = 1'b0;
RegWEL = 1'b0;
if ((tstate[1] && ~Save_ALU_r && ~Auto_Wait_t1) ||
(Save_ALU_r && (ALU_Op_r != 4'b0111)) )
begin
case (Read_To_Reg_r)
5'b10000 , 5'b10001 , 5'b10010 , 5'b10011 , 5'b10100 , 5'b10101 :
begin
RegWEH = ~ Read_To_Reg_r[0];
RegWEL = Read_To_Reg_r[0];
end // UNMATCHED !!
default : ;
endcase // case(Read_To_Reg_r)
end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||...
if (ExchangeDH && (tstate[3] || tstate[4]) )
begin
RegWEH = 1'b1;
RegWEL = 1'b1;
end
if (IncDec_16[2] && ((tstate[2] && wait_n && ~mcycle[0]) || (tstate[3] && mcycle[0])) )
begin
case (IncDec_16[1:0])
2'b00 , 2'b01 , 2'b10 :
begin
RegWEH = 1'b1;
RegWEL = 1'b1;
end // UNMATCHED !!
default : ;
endcase
end
end // always @ *
always @(/*AUTOSENSE*/ExchangeDH or ID16 or IncDec_16 or RegBusA_r
or RegBusB or Save_Mux or mcycle or tstate)
begin
RegDIH = Save_Mux;
RegDIL = Save_Mux;
if (ExchangeDH == 1'b1 && tstate[3] )
begin
RegDIH = RegBusB[15:8];
RegDIL = RegBusB[7:0];
end
else if (ExchangeDH == 1'b1 && tstate[4] )
begin
RegDIH = RegBusA_r[15:8];
RegDIL = RegBusA_r[7:0];
end
else if (IncDec_16[2] == 1'b1 && ((tstate[2] && ~mcycle[0]) || (tstate[3] && mcycle[0])) )
begin
RegDIH = ID16[15:8];
RegDIL = ID16[7:0];
end
end
tv80_reg i_reg
(
.clk (clk),
.CEN (ClkEn),
.WEH (RegWEH),
.WEL (RegWEL),
.AddrA (RegAddrA),
.AddrB (RegAddrB),
.AddrC (RegAddrC),
.DIH (RegDIH),
.DIL (RegDIL),
.DOAH (RegBusA[15:8]),
.DOAL (RegBusA[7:0]),
.DOBH (RegBusB[15:8]),
.DOBL (RegBusB[7:0]),
.DOCH (RegBusC[15:8]),
.DOCL (RegBusC[7:0])
);
//-------------------------------------------------------------------------
//
// Buses
//
//-------------------------------------------------------------------------
always @ (posedge clk)
begin
if (ClkEn == 1'b1 )
begin
case (Set_BusB_To)
4'b0111 :
BusB <= #1 ACC;
4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 :
begin
if (Set_BusB_To[0] == 1'b1 )
begin
BusB <= #1 RegBusB[7:0];
end
else
begin
BusB <= #1 RegBusB[15:8];
end
end
4'b0110 :
BusB <= #1 DI_Reg;
4'b1000 :
BusB <= #1 SP[7:0];
4'b1001 :
BusB <= #1 SP[15:8];
4'b1010 :
BusB <= #1 8'b00000001;
4'b1011 :
BusB <= #1 F;
4'b1100 :
BusB <= #1 PC[7:0];
4'b1101 :
BusB <= #1 PC[15:8];
4'b1110 :
BusB <= #1 8'b00000000;
default :
BusB <= #1 8'h0;
endcase
case (Set_BusA_To)
4'b0111 :
BusA <= #1 ACC;
4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 :
begin
if (Set_BusA_To[0] == 1'b1 )
begin
BusA <= #1 RegBusA[7:0];
end
else
begin
BusA <= #1 RegBusA[15:8];
end
end
4'b0110 :
BusA <= #1 DI_Reg;
4'b1000 :
BusA <= #1 SP[7:0];
4'b1001 :
BusA <= #1 SP[15:8];
4'b1010 :
BusA <= #1 8'b00000000;
default :
BusA <= #1 8'h0;
endcase
end
end
//-------------------------------------------------------------------------
//
// Generate external control signals
//
//-------------------------------------------------------------------------
`ifdef TV80_REFRESH
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0 )
begin
rfsh_n <= #1 1'b1;
end
else
begin
if (cen == 1'b1 )
begin
if (mcycle[0] && ((tstate[2] && wait_n == 1'b1) || tstate[3]) )
begin
rfsh_n <= #1 1'b0;
end
else
begin
rfsh_n <= #1 1'b1;
end
end
end
end // always @ (posedge clk or negedge reset_n)
`else // !`ifdef TV80_REFRESH
assign rfsh_n = 1'b1;
`endif
always @(/*AUTOSENSE*/BusAck or Halt_FF or I_DJNZ or IntCycle
or IntE_FF1 or di or iorq_i or mcycle or tstate)
begin
mc = mcycle;
ts = tstate;
DI_Reg = di;
halt_n = ~ Halt_FF;
busak_n = ~ BusAck;
intcycle_n = ~ IntCycle;
IntE = IntE_FF1;
iorq = iorq_i;
stop = I_DJNZ;
end
//-----------------------------------------------------------------------
//
// Syncronise inputs
//
//-----------------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : sync_inputs
if (~reset_n)
begin
BusReq_s <= #1 1'b0;
INT_s <= #1 1'b0;
NMI_s <= #1 1'b0;
Oldnmi_n <= #1 1'b0;
end
else
begin
if (cen == 1'b1 )
begin
BusReq_s <= #1 ~ busrq_n;
INT_s <= #1 ~ int_n;
if (NMICycle == 1'b1 )
begin
NMI_s <= #1 1'b0;
end
else if (nmi_n == 1'b0 && Oldnmi_n == 1'b1 )
begin
NMI_s <= #1 1'b1;
end
Oldnmi_n <= #1 nmi_n;
end
end
end
//-----------------------------------------------------------------------
//
// Main state machine
//
//-----------------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0 )
begin
mcycle <= #1 7'b0000001;
tstate <= #1 7'b0000001;
Pre_XY_F_M <= #1 3'b000;
Halt_FF <= #1 1'b0;
BusAck <= #1 1'b0;
NMICycle <= #1 1'b0;
IntCycle <= #1 1'b0;
IntE_FF1 <= #1 1'b0;
IntE_FF2 <= #1 1'b0;
No_BTR <= #1 1'b0;
Auto_Wait_t1 <= #1 1'b0;
Auto_Wait_t2 <= #1 1'b0;
m1_n <= #1 1'b1;
end
else
begin
if (cen == 1'b1 )
begin
if (T_Res == 1'b1 )
begin
Auto_Wait_t1 <= #1 1'b0;
end
else
begin
Auto_Wait_t1 <= #1 Auto_Wait || (iorq_i & ~Auto_Wait_t2);
end
Auto_Wait_t2 <= #1 Auto_Wait_t1 & !T_Res;
No_BTR <= #1 (I_BT && (~ IR[4] || ~ F[Flag_P])) ||
(I_BC && (~ IR[4] || F[Flag_Z] || ~ F[Flag_P])) ||
(I_BTR && (~ IR[4] || F[Flag_Z]));
if (tstate[2] )
begin
if (SetEI == 1'b1 )
begin
if (!NMICycle)
IntE_FF1 <= #1 1'b1;
IntE_FF2 <= #1 1'b1;
end
if (I_RETN == 1'b1 )
begin
IntE_FF1 <= #1 IntE_FF2;
end
end
if (tstate[3] )
begin
if (SetDI == 1'b1 )
begin
IntE_FF1 <= #1 1'b0;
IntE_FF2 <= #1 1'b0;
end
end
if (IntCycle == 1'b1 || NMICycle == 1'b1 )
begin
Halt_FF <= #1 1'b0;
end
if (mcycle[0] && tstate[2] && wait_n == 1'b1 )
begin
m1_n <= #1 1'b1;
end
if (BusReq_s == 1'b1 && BusAck == 1'b1 )
begin
end
else
begin
BusAck <= #1 1'b0;
if (tstate[2] && wait_n == 1'b0 )
begin
end
else if (T_Res == 1'b1 )
begin
if (Halt == 1'b1 )
begin
Halt_FF <= #1 1'b1;
end
if (BusReq_s == 1'b1 )
begin
BusAck <= #1 1'b1;
end
else
begin
tstate <= #1 7'b0000010;
if (NextIs_XY_Fetch == 1'b1 )
begin
mcycle <= #1 7'b0100000;
Pre_XY_F_M <= #1 mcyc_to_number(mcycle);
if (IR == 8'b00110110 && Mode == 0 )
begin
Pre_XY_F_M <= #1 3'b010;
end
end
else if ((mcycle[6]) || (mcycle[5] && Mode == 1 && ISet != 2'b01) )
begin
mcycle <= #1 number_to_bitvec(Pre_XY_F_M + 1);
end
else if ((last_mcycle) ||
No_BTR == 1'b1 ||
(mcycle[1] && I_DJNZ == 1'b1 && IncDecZ == 1'b1) )
begin
m1_n <= #1 1'b0;
mcycle <= #1 7'b0000001;
IntCycle <= #1 1'b0;
NMICycle <= #1 1'b0;
if (NMI_s == 1'b1 && Prefix == 2'b00 )
begin
NMICycle <= #1 1'b1;
IntE_FF1 <= #1 1'b0;
end
else if ((IntE_FF1 == 1'b1 && INT_s == 1'b1) && Prefix == 2'b00 && SetEI == 1'b0 )
begin
IntCycle <= #1 1'b1;
IntE_FF1 <= #1 1'b0;
IntE_FF2 <= #1 1'b0;
end
end
else
begin
mcycle <= #1 { mcycle[5:0], mcycle[6] };
end
end
end
else
begin // verilog has no "nor" operator
if ( ~(Auto_Wait == 1'b1 && Auto_Wait_t2 == 1'b0) &&
~(IOWait == 1 && iorq_i == 1'b1 && Auto_Wait_t1 == 1'b0) )
begin
tstate <= #1 { tstate[5:0], tstate[6] };
end
end
end
if (tstate[0])
begin
m1_n <= #1 1'b0;
end
end
end
end
always @(/*AUTOSENSE*/BTR_r or DI_Reg or IncDec_16 or JumpE or PC
or RegBusA or RegBusC or SP or tstate)
begin
if (JumpE == 1'b1 )
begin
PC16_B = { {8{DI_Reg[7]}}, DI_Reg };
end
else if (BTR_r == 1'b1 )
begin
PC16_B = -2;
end
else
begin
PC16_B = 1;
end
if (tstate[3])
begin
SP16_A = RegBusC;
SP16_B = { {8{DI_Reg[7]}}, DI_Reg };
end
else
begin
// suspect that ID16 and SP16 could be shared
SP16_A = SP;
if (IncDec_16[3] == 1'b1)
SP16_B = -1;
else
SP16_B = 1;
end
if (IncDec_16[3])
ID16_B = -1;
else
ID16_B = 1;
ID16 = RegBusA + ID16_B;
PC16 = PC + PC16_B;
SP16 = SP16_A + SP16_B;
end // always @ *
always @(/*AUTOSENSE*/IntCycle or NMICycle or mcycle)
begin
Auto_Wait = 1'b0;
if (IntCycle == 1'b1 || NMICycle == 1'b1 )
begin
if (mcycle[0] )
begin
Auto_Wait = 1'b1;
end
end
end // always @ *
endmodule // T80
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:56:12 10/31/2015
// Design Name:
// Module Name: RAM_addresser_and_data
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RAM_addresser_and_data(
input [3:0] address_in,
input [3:0] data_in,
input read_mode,
input write_mode,
input clock,
output [3:0] data_out,
output reg reading,
output reg writing
);
reg read_write;
RAM_ram_bank RAM (
.clka(clock),
.wea(read_write),
.addra(address_in),
.dina(data_in),
.douta(data_out)
);
always@(read_mode, write_mode) begin
read_write = write_mode & ~read_mode;
end
always@(read_write) begin
if(read_write == 0) begin
reading = 1;
writing = 0;
end
else begin
reading = 0;
writing = 1;
end
end
endmodule
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 21-03-2019
*/
// calculates d=a/b
// a = b*d + r
module jt10_adpcm_div #(parameter dw=16)(
input rst_n,
input clk, // CPU clock
input cen,
input start, // strobe
input [dw-1:0] a,
input [dw-1:0] b,
output reg [dw-1:0] d,
output reg [dw-1:0] r,
output working
);
reg [dw-1:0] cycle;
assign working = cycle[0];
wire [dw:0] sub = { r[dw-2:0], d[dw-1] } - b;
always @(posedge clk or negedge rst_n)
if( !rst_n ) begin
cycle <= 'd0;
end else if(cen) begin
if( start ) begin
cycle <= ~16'd0;
r <= 16'd0;
d <= a;
end else if(cycle[0]) begin
cycle <= { 1'b0, cycle[dw-1:1] };
if( sub[dw] == 0 ) begin
r <= sub[dw-1:0];
d <= { d[dw-2:0], 1'b1};
end else begin
r <= { r[dw-2:0], d[dw-1] };
d <= { d[dw-2:0], 1'b0 };
end
end
end
endmodule // jt10_adpcm_div
|
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_merge_enc.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module ecc_merge_enc
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter CODE_WIDTH = 72,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter DQ_WIDTH = 72,
parameter ECC_WIDTH = 8,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
mc_wrdata, mc_wrdata_mask,
// Inputs
clk, rst, wr_data, wr_data_mask, rd_merge_data, h_rows, raw_not_ecc
);
input clk;
input rst;
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data;
input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask;
input [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data_r;
reg [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask_r;
reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data_r;
always @(posedge clk) wr_data_r <= #TCQ wr_data;
always @(posedge clk) wr_data_mask_r <= #TCQ wr_data_mask;
always @(posedge clk) rd_merge_data_r <= #TCQ rd_merge_data;
// Merge new data with memory read data.
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] merged_data;
genvar h;
genvar i;
generate
for (h=0; h<2*nCK_PER_CLK; h=h+1) begin : merge_data_outer
for (i=0; i<DATA_WIDTH/8; i=i+1) begin : merge_data_inner
assign merged_data[h*PAYLOAD_WIDTH+i*8+:8] =
wr_data_mask[h*DATA_WIDTH/8+i]
? rd_merge_data[h*DATA_WIDTH+i*8+:8]
: wr_data[h*PAYLOAD_WIDTH+i*8+:8];
end
if (PAYLOAD_WIDTH > DATA_WIDTH)
assign merged_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]=
wr_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH];
end
endgenerate
// Generate ECC and overlay onto mc_wrdata.
input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
input [2*nCK_PER_CLK-1:0] raw_not_ecc;
reg [2*nCK_PER_CLK-1:0] raw_not_ecc_r;
always @(posedge clk) raw_not_ecc_r <= #TCQ raw_not_ecc;
output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata;
reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata_c;
genvar j;
integer k;
generate
for (j=0; j<2*nCK_PER_CLK; j=j+1) begin : ecc_word
always @(/*AS*/h_rows or merged_data or raw_not_ecc_r) begin
mc_wrdata_c[j*DQ_WIDTH+:DQ_WIDTH] =
{{DQ_WIDTH-PAYLOAD_WIDTH{1'b0}},
merged_data[j*PAYLOAD_WIDTH+:PAYLOAD_WIDTH]};
for (k=0; k<ECC_WIDTH; k=k+1)
if (~raw_not_ecc_r[j])
mc_wrdata_c[j*DQ_WIDTH+CODE_WIDTH-k-1] =
^(merged_data[j*PAYLOAD_WIDTH+:DATA_WIDTH] &
h_rows[k*CODE_WIDTH+:DATA_WIDTH]);
end
end
endgenerate
always @(posedge clk) mc_wrdata <= mc_wrdata_c;
// Set all DRAM masks to zero.
output wire[2*nCK_PER_CLK*DQ_WIDTH/8-1:0] mc_wrdata_mask;
assign mc_wrdata_mask = {2*nCK_PER_CLK*DQ_WIDTH/8{1'b0}};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3B_1_V
`define SKY130_FD_SC_HS__NOR3B_1_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog wrapper for nor3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nor3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor3b_1 (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor3b_1 (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3B_1_V
|
/**
* This file is part of pyBAR.
*
* pyBAR is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* pyBAR is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with pyBAR. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`default_nettype none
module mmc3_beast_eth(
input wire RESET_N,
input wire clkin,
output wire [3:0] rgmii_txd,
output wire rgmii_tx_ctl,
output wire rgmii_txc,
input wire [3:0] rgmii_rxd,
input wire rgmii_rx_ctl,
input wire rgmii_rxc,
output wire mdio_phy_mdc,
inout wire mdio_phy_mdio,
output wire phy_rst_n,
output wire [7:0] LED,
output wire CMD_CLK_P, CMD_CLK_N,
output wire CMD_DATA_P, CMD_DATA_N,
input wire [4:0] RJ45_HITOR_N, RJ45_HITOR_P,
input wire [4:0] DOBOUT_N, DOBOUT_P,
output wire RJ45_BUSY_LEMO_TX1, RJ45_CLK_LEMO_TX0,
output wire [1:0] LEMO_TX, // individual LEMO TX only available on MMC3 revision 1.2
input wire RJ45_TRIGGER, RJ45_RESET,
input wire [1:0] LEMO_RX,
inout wire [7:0] PMOD // 2-row PMOD header for general purpose IOs
);
wire RST;
wire CLK125PLLTX, CLK125PLLTX90;
wire PLL_FEEDBACK, LOCKED;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
.CLKFBOUT_MULT(10), // Multiply value for all CLKOUT, (2-64)
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
.CLKIN1_PERIOD(10.000), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
.CLKOUT0_DIVIDE(8), // Divide amount for CLKOUT0 (1-128)
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT0_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.CLKOUT1_DIVIDE(8), // Divide amount for CLKOUT0 (1-128)
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT1_PHASE(90.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.DIVCLK_DIVIDE(1), // Master division value, (1-56)
.REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999).
.STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
) PLLE2_BASE_inst (
.CLKOUT0(CLK125PLLTX),
.CLKOUT1(CLK125PLLTX90),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(PLL_FEEDBACK),
.LOCKED(LOCKED), // 1-bit output: LOCK
// Input 100 MHz clock
.CLKIN1(clkin),
// Control Ports
.PWRDWN(0),
.RST(!RESET_N),
// Feedback
.CLKFBIN(PLL_FEEDBACK)
);
wire CLK160_PLL, CLK320_PLL, CLK40_PLL, CLK16_PLL, BUS_CLK_PLL;
wire PLL_FEEDBACK2, LOCKED2;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(16),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(10.000),
.CLKOUT0_DIVIDE(10),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_DIVIDE(40),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_DIVIDE(5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_DIVIDE(100),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_DIVIDE(12),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0.0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.0),
.STARTUP_WAIT("FALSE")
) PLLE2_BASE_inst_2 (
.CLKOUT0(CLK160_PLL),
.CLKOUT1(CLK40_PLL),
.CLKOUT2(CLK320_PLL),
.CLKOUT3(CLK16_PLL),
.CLKOUT4(BUS_CLK_PLL),
.CLKOUT5(),
.CLKFBOUT(PLL_FEEDBACK2),
.LOCKED(LOCKED2), // 1-bit output: LOCK
.CLKIN1(clkin),
.PWRDWN(0),
.RST(!RESET_N),
.CLKFBIN(PLL_FEEDBACK2)
);
wire CLK160, CLK40, CLK320, CLK16, BUS_CLK;
BUFG BUFG_inst_160 (.O(CLK160), .I(CLK160_PLL));
BUFG BUFG_inst_40 (.O(CLK40), .I(CLK40_PLL));
BUFG BUFG_inst_320 (.O(CLK320), .I(CLK320_PLL));
BUFG BUFG_inst_16 (.O(CLK16), .I(CLK16_PLL));
BUFG BUFG_inst_BUS_CLK (.O(BUS_CLK), .I(BUS_CLK_PLL));
// BUFG BUFG_inst_200 (.O(CLK200), .I(CLK200_PLL));
// wire IDELAYCTRL_RDY;
// IDELAYCTRL IDELAYCTRL_inst (
// .RDY(IDELAYCTRL_RDY),
// .REFCLK(CLK200),
// .RST(!LOCKED2)
// );
wire CLK125TX, CLK125TX90, CLK125RX;
BUFG BUFG_inst_CLK125TX(.O(CLK125TX), .I(CLK125PLLTX));
BUFG BUFG_inst_CLK125TX90(.O(CLK125TX90), .I(CLK125PLLTX90));
BUFG BUFG_inst_CLK125RX(.O(CLK125RX), .I(rgmii_rxc));
assign RST = !RESET_N | !LOCKED | !LOCKED2;
wire gmii_tx_clk;
wire gmii_tx_en;
wire [7:0] gmii_txd;
wire gmii_tx_er;
wire gmii_crs;
wire gmii_col;
wire gmii_rx_clk;
wire gmii_rx_dv;
wire [7:0] gmii_rxd;
wire gmii_rx_er;
wire mdio_gem_mdc;
wire mdio_gem_i;
wire mdio_gem_o;
wire mdio_gem_t;
wire link_status;
wire [1:0] clock_speed;
wire duplex_status;
rgmii_io rgmii
(
.rgmii_txd(rgmii_txd),
.rgmii_tx_ctl(rgmii_tx_ctl),
.rgmii_txc(rgmii_txc),
.rgmii_rxd(rgmii_rxd),
.rgmii_rx_ctl(rgmii_rx_ctl),
.gmii_txd_int(gmii_txd), // Internal gmii_txd signal.
.gmii_tx_en_int(gmii_tx_en),
.gmii_tx_er_int(gmii_tx_er),
.gmii_col_int(gmii_col),
.gmii_crs_int(gmii_crs),
.gmii_rxd_reg(gmii_rxd), // RGMII double data rate data valid.
.gmii_rx_dv_reg(gmii_rx_dv), // gmii_rx_dv_ibuf registered in IOBs.
.gmii_rx_er_reg(gmii_rx_er), // gmii_rx_er_ibuf registered in IOBs.
.eth_link_status(link_status),
.eth_clock_speed(clock_speed),
.eth_duplex_status(duplex_status),
// Following are generated by DCMs
.tx_rgmii_clk_int(CLK125TX), // Internal RGMII transmitter clock.
.tx_rgmii_clk90_int(CLK125TX90), // Internal RGMII transmitter clock w/ 90 deg phase
.rx_rgmii_clk_int(CLK125RX), // Internal RGMII receiver clock
.reset(!phy_rst_n)
);
// Instantiate tri-state buffer for MDIO
IOBUF i_iobuf_mdio(
.O(mdio_gem_i),
.IO(mdio_phy_mdio),
.I(mdio_gem_o),
.T(mdio_gem_t));
wire EEPROM_CS, EEPROM_SK, EEPROM_DI;
wire TCP_CLOSE_REQ;
wire RBCP_ACT, RBCP_WE, RBCP_RE;
wire [7:0] RBCP_WD, RBCP_RD;
wire [31:0] RBCP_ADDR;
wire TCP_RX_WR;
wire [7:0] TCP_RX_DATA;
wire [15:0] TCP_RX_WC;
wire RBCP_ACK;
wire SiTCP_RST;
wire TCP_TX_FULL;
wire TCP_TX_WR;
wire [7:0] TCP_TX_DATA;
wire [7:0] PMOD_O;
IOBUF iobuf_pmod [7:0] (
.O(PMOD_O),
.IO(PMOD),
.I({8'b1111_0000}),
.T({8'b0000_1111})
);
wire [7:0] IP_ADDR_SEL;
assign IP_ADDR_SEL = {4'b0, PMOD_O[3], PMOD_O[2], PMOD_O[1], PMOD_O[0]}; // MSB: PMOD[3]; LSB: PMOD[0]
WRAP_SiTCP_GMII_XC7K_32K sitcp(
.CLK(BUS_CLK), // in : System Clock >129MHz
.RST(RST), // in : System reset
// Configuration parameters
.FORCE_DEFAULTn(1'b0), // in : Load default parameters
.EXT_IP_ADDR({8'd192, 8'd168, 8'd10 + IP_ADDR_SEL, 8'd11}), // in : IP address[31:0] //192.168.10.11
.EXT_TCP_PORT(16'd24), // in : TCP port #[15:0]
.EXT_RBCP_PORT(16'd4660), // in : RBCP port #[15:0]
.PHY_ADDR(5'd3), // in : PHY-device MIF address[4:0]
// EEPROM
.EEPROM_CS(EEPROM_CS), // out : Chip select
.EEPROM_SK(EEPROM_SK), // out : Serial data clock
.EEPROM_DI(EEPROM_DI), // out : Serial write data
.EEPROM_DO(1'b0), // in : Serial read data
// user data, intialial values are stored in the EEPROM, 0xFFFF_FC3C-3F
.USR_REG_X3C(), // out : Stored at 0xFFFF_FF3C
.USR_REG_X3D(), // out : Stored at 0xFFFF_FF3D
.USR_REG_X3E(), // out : Stored at 0xFFFF_FF3E
.USR_REG_X3F(), // out : Stored at 0xFFFF_FF3F
// MII interface
.GMII_RSTn(phy_rst_n), // out : PHY reset
.GMII_1000M(1'b1), // in : GMII mode (0:MII, 1:GMII)
// TX
.GMII_TX_CLK(CLK125TX), // in : Tx clock
.GMII_TX_EN(gmii_tx_en), // out : Tx enable
.GMII_TXD(gmii_txd), // out : Tx data[7:0]
.GMII_TX_ER(gmii_tx_er), // out : TX error
// RX
.GMII_RX_CLK(CLK125RX), // in : Rx clock
.GMII_RX_DV(gmii_rx_dv), // in : Rx data valid
.GMII_RXD(gmii_rxd), // in : Rx data[7:0]
.GMII_RX_ER(gmii_rx_er), // in : Rx error
.GMII_CRS(gmii_crs), // in : Carrier sense
.GMII_COL(gmii_col), // in : Collision detected
// Management IF
.GMII_MDC(mdio_phy_mdc), // out : Clock for MDIO
.GMII_MDIO_IN(mdio_gem_i), // in : Data
.GMII_MDIO_OUT(mdio_gem_o), // out : Data
.GMII_MDIO_OE(mdio_gem_t), // out : MDIO output enable
// User I/F
.SiTCP_RST(SiTCP_RST), // out : Reset for SiTCP and related circuits
// TCP connection control
.TCP_OPEN_REQ(1'b0), // in : Reserved input, shoud be 0
.TCP_OPEN_ACK(), // out : Acknowledge for open (=Socket busy)
.TCP_ERROR(), // out : TCP error, its active period is equal to MSL
.TCP_CLOSE_REQ(TCP_CLOSE_REQ), // out : Connection close request
.TCP_CLOSE_ACK(TCP_CLOSE_REQ), // in : Acknowledge for closing
// FIFO I/F
.TCP_RX_WC(TCP_RX_WC), // in : Rx FIFO write count[15:0] (Unused bits should be set 1)
.TCP_RX_WR(TCP_RX_WR), // out : Write enable
.TCP_RX_DATA(TCP_RX_DATA), // out : Write data[7:0]
.TCP_TX_FULL(TCP_TX_FULL), // out : Almost full flag
.TCP_TX_WR(TCP_TX_WR), // in : Write enable
.TCP_TX_DATA(TCP_TX_DATA), // in : Write data[7:0]
// RBCP
.RBCP_ACT(RBCP_ACT), // out : RBCP active
.RBCP_ADDR(RBCP_ADDR), // out : Address[31:0]
.RBCP_WD(RBCP_WD), // out : Data[7:0]
.RBCP_WE(RBCP_WE), // out : Write enable
.RBCP_RE(RBCP_RE), // out : Read enable
.RBCP_ACK(RBCP_ACK), // in : Access acknowledge
.RBCP_RD(RBCP_RD) // in : Read data[7:0]
);
// ------- BUS SIGNALLING ------- //
wire BUS_WR, BUS_RD, BUS_RST;
wire [31:0] BUS_ADD;
wire [7:0] BUS_DATA;
wire INVALID;
assign BUS_RST = SiTCP_RST;
tcp_to_bus itcp_to_bus(
.BUS_RST(BUS_RST),
.BUS_CLK(BUS_CLK),
.TCP_RX_WC(TCP_RX_WC),
.TCP_RX_WR(TCP_RX_WR),
.TCP_RX_DATA(TCP_RX_DATA),
.RBCP_ACT(RBCP_ACT),
.RBCP_ADDR(RBCP_ADDR),
.RBCP_WD(RBCP_WD),
.RBCP_WE(RBCP_WE),
.RBCP_RE(RBCP_RE),
.RBCP_ACK(RBCP_ACK),
.RBCP_RD(RBCP_RD),
.BUS_WR(BUS_WR),
.BUS_RD(BUS_RD),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.INVALID(INVALID)
);
// ------- MODULE ADDRESSES ------- //
localparam CMD_BASEADDR = 32'h0000;
localparam CMD_HIGHADDR = 32'h8000-1;
localparam TLU_BASEADDR = 32'h8200;
localparam TLU_HIGHADDR = 32'h8300-1;
localparam RX_BASEADDR = 32'h9000;
localparam RX_HIGHADDR = 32'h9100-1;
localparam TDC_BASEADDR = 32'ha000;
localparam TDC_HIGHADDR = 32'ha100-1;
localparam GPIO_DLY_BASEADDR = 32'hb000;
localparam GPIO_DLY_HIGHADDR = 32'hb100-1;
// ------- USER MODULES ------- //
wire [47:0] GPIO_DLY_IO;
gpio
#(
.BASEADDR(GPIO_DLY_BASEADDR),
.HIGHADDR(GPIO_DLY_HIGHADDR),
.IO_WIDTH(48),
.IO_DIRECTION(48'hffffffffffff),
.IO_TRI(48'h000000000000),
.ABUSWIDTH(32)
) i_gpio
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(GPIO_DLY_IO)
);
wire [4:0] IDELAYE_CINVCTRL;
wire [4:0] IDELAYE_LD;
wire [4:0] IDELAYE_CNTVALUEIN [4:0];
wire [2:0] SEL_CLK40;
assign IDELAYE_LD[0] = GPIO_DLY_IO[7];
assign IDELAYE_CINVCTRL[0] = GPIO_DLY_IO[6];
assign IDELAYE_CNTVALUEIN[0] = GPIO_DLY_IO[4:0];
assign IDELAYE_LD[1] = GPIO_DLY_IO[7+1*8];
assign IDELAYE_CINVCTRL[1] = GPIO_DLY_IO[6+1*8];
assign IDELAYE_CNTVALUEIN[1] = GPIO_DLY_IO[4+1*8:0+1*8];
assign IDELAYE_LD[2] = GPIO_DLY_IO[7+2*8];
assign IDELAYE_CINVCTRL[2] = GPIO_DLY_IO[6+2*8];
assign IDELAYE_CNTVALUEIN[2] = GPIO_DLY_IO[4+2*8:0+2*8];
assign IDELAYE_LD[3] = GPIO_DLY_IO[7+3*8];
assign IDELAYE_CINVCTRL[3] = GPIO_DLY_IO[6+3*8];
assign IDELAYE_CNTVALUEIN[3] = GPIO_DLY_IO[4+3*8:0+3*8];
assign IDELAYE_LD[4] = GPIO_DLY_IO[7+4*8];
assign IDELAYE_CINVCTRL[4] = GPIO_DLY_IO[6+4*8];
assign IDELAYE_CNTVALUEIN[4] = GPIO_DLY_IO[4+4*8:0+4*8];
assign SEL_CLK40 = GPIO_DLY_IO[42:40];
wire CMD_DATA, CMD_CLK;
wire TRIGGER_ENABLE; // from CMD FSM
wire CMD_READY; // from CMD FSM
wire CMD_START_FLAG;
wire TRIGGER_ACCEPTED_FLAG;
wire CMD_EXT_START_FLAG;
assign CMD_EXT_START_FLAG = TRIGGER_ACCEPTED_FLAG;
wire EXT_TRIGGER_ENABLE;
cmd_seq #(
.BASEADDR(CMD_BASEADDR),
.HIGHADDR(CMD_HIGHADDR),
.ABUSWIDTH(32)
) icmd (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.CMD_CLK_IN(CLK40),
.CMD_CLK_OUT(CMD_CLK),
.CMD_DATA(CMD_DATA),
.CMD_EXT_START_FLAG(CMD_EXT_START_FLAG),
.CMD_EXT_START_ENABLE(EXT_TRIGGER_ENABLE),
.CMD_READY(CMD_READY),
.CMD_START_FLAG(CMD_START_FLAG)
);
reg [7:0] CLK_SR;
reg CLK40_OUT_SEL;
always@(posedge CLK320)
CLK_SR <= {CLK_SR[6:0],CLK40};
always@(posedge CLK320)
CLK40_OUT_SEL <= CLK_SR[SEL_CLK40];
OBUFDS #(
.IOSTANDARD("LVDS_25"),
.SLEW("SLOW")
) OBUFDS_inst_cmd_clk_out (
.O(CMD_CLK_P),
.OB(CMD_CLK_N),
.I(CLK40_OUT_SEL)
);
OBUFDS #(
.IOSTANDARD("LVDS_25"),
.SLEW("SLOW")
) OBUFDS_inst_cmd_data (
.O(CMD_DATA_P),
.OB(CMD_DATA_N),
.I(CMD_DATA)
);
wire TRIGGER_ACKNOWLEDGE_FLAG; // to TLU FSM
reg CMD_READY_FF;
always @ (posedge CLK40)
begin
CMD_READY_FF <= CMD_READY;
end
assign TRIGGER_ACKNOWLEDGE_FLAG = CMD_READY & ~CMD_READY_FF;
wire [4:0] RX_ENABLED, RX_ENABLED_CLK40;
three_stage_synchronizer #(
.WIDTH(5)
) three_stage_sync_rx_enable_clk40 (
.CLK(CLK40),
.IN(RX_ENABLED),
.OUT(RX_ENABLED_CLK40)
);
wire [4:0] FE_FIFO_EMPTY, FE_FIFO_EMPTY_CLK40;
three_stage_synchronizer #(
.WIDTH(5)
) three_stage_sync_fe_fifo_empty_clk40 (
.CLK(CLK40),
.IN(FE_FIFO_EMPTY),
.OUT(FE_FIFO_EMPTY_CLK40)
);
parameter max_wait_cycles = 64;
reg STARTED_READY_COUNTER;
reg CMD_FIFO_READY;
integer fifo_empty_counter;
wire CMD_FIFO_READY_FLAG;
reg CMD_FIFO_READY_FF;
wire TRIGGER_FIFO_READ;
wire TRIGGER_FIFO_EMPTY;
wire [31:0] TRIGGER_FIFO_DATA;
wire TRIGGER_FIFO_PREEMPT_REQ;
wire [31:0] TIMESTAMP;
wire [4:0] TDC_OUT;
wire [4:0] RX_READY, RX_8B10B_DECODER_ERR, RX_FIFO_OVERFLOW_ERR, RX_FIFO_FULL;
wire FIFO_FULL;
wire TLU_BUSY, TLU_CLOCK;
wire TRIGGER_ENABLED, TLU_ENABLED;
assign RJ45_BUSY_LEMO_TX1 = TLU_BUSY;
assign LEMO_TX[1] = RJ45_BUSY_LEMO_TX1; // add LEMO TX0 and TX1 for MMC3 revision 1.2; LEMO TX0 and TX1 are not connected to RJ45_CLK_LEMO_TX0 and RJ45_BUSY_LEMO_TX1 anymore
assign RJ45_CLK_LEMO_TX0 = TLU_CLOCK;
assign LEMO_TX[0] = RJ45_CLK_LEMO_TX0; // add LEMO TX0 and TX1 for MMC3 revision 1.2; LEMO TX0 and TX1 are not connected to RJ45_CLK_LEMO_TX0 and RJ45_BUSY_LEMO_TX1 anymore
always @(posedge CLK40)
begin
if (~EXT_TRIGGER_ENABLE || ~TRIGGER_ENABLED)
begin
STARTED_READY_COUNTER <= 1'b0;
CMD_FIFO_READY <= 1'b1;
fifo_empty_counter <= 0;
end
else if (STARTED_READY_COUNTER == 1'b0 && TRIGGER_ACKNOWLEDGE_FLAG == 1'b1)
begin
STARTED_READY_COUNTER <= 1'b1;
CMD_FIFO_READY <= 1'b0;
fifo_empty_counter <= 0;
end
else if (STARTED_READY_COUNTER == 1'b1 && |(~FE_FIFO_EMPTY_CLK40 & RX_ENABLED_CLK40))
begin
fifo_empty_counter <= 0;
end
else if (STARTED_READY_COUNTER == 1'b1 && fifo_empty_counter == max_wait_cycles)
begin
STARTED_READY_COUNTER <= 1'b0;
CMD_FIFO_READY <= 1'b1;
end
else if (STARTED_READY_COUNTER == 1'b1 && &(FE_FIFO_EMPTY_CLK40 | ~RX_ENABLED_CLK40))
begin
fifo_empty_counter <= fifo_empty_counter + 1;
end
end
always @ (posedge CLK40)
begin
CMD_FIFO_READY_FF <= CMD_FIFO_READY;
end
assign CMD_FIFO_READY_FLAG = CMD_FIFO_READY & ~CMD_FIFO_READY_FF;
tlu_controller #(
.BASEADDR(TLU_BASEADDR),
.HIGHADDR(TLU_HIGHADDR),
.DIVISOR(8),
.ABUSWIDTH(32),
.WIDTH(6),
.TLU_TRIGGER_MAX_CLOCK_CYCLES(32)
) i_tlu_controller (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.TRIGGER_CLK(CLK40),
.FIFO_READ(TRIGGER_FIFO_READ),
.FIFO_EMPTY(TRIGGER_FIFO_EMPTY),
.FIFO_DATA(TRIGGER_FIFO_DATA),
.FIFO_PREEMPT_REQ(TRIGGER_FIFO_PREEMPT_REQ),
.TRIGGER_ENABLED(TRIGGER_ENABLED),
.TRIGGER_SELECTED(),
.TLU_ENABLED(TLU_ENABLED),
.TRIGGER({TDC_OUT, LEMO_RX[0]}),
.TRIGGER_VETO({RX_FIFO_FULL, FIFO_FULL}),
.TIMESTAMP_RESET(1'b0),
.EXT_TRIGGER_ENABLE(EXT_TRIGGER_ENABLE),
.TRIGGER_ACKNOWLEDGE(CMD_FIFO_READY_FLAG),
.TRIGGER_ACCEPTED_FLAG(TRIGGER_ACCEPTED_FLAG),
.TLU_TRIGGER(RJ45_TRIGGER),
.TLU_RESET(RJ45_RESET),
.TLU_BUSY(TLU_BUSY),
.TLU_CLOCK(TLU_CLOCK),
.EXT_TIMESTAMP(),
.TIMESTAMP(TIMESTAMP)
);
//reg [31:0] timestamp_gray;
//always@(posedge BUS_CLK)
// timestamp_gray <= (TIMESTAMP>>1) ^ TIMESTAMP;
wire [4:0] FE_FIFO_READ;
//wire [4:0] FE_FIFO_EMPTY;
wire [31:0] FE_FIFO_DATA [4:0];
wire [4:0] TDC_FIFO_READ;
wire [4:0] TDC_FIFO_EMPTY;
wire [31:0] TDC_FIFO_DATA [4:0];
genvar i;
generate
for (i = 0; i < 5; i = i + 1) begin: rx_gen
wire DOBOUT;
reg DOBOUT_DLY;
fei4_rx #(
.BASEADDR(RX_BASEADDR+32'h0100*i),
.HIGHADDR(RX_HIGHADDR+32'h0100*i),
.DSIZE(10),
.DATA_IDENTIFIER(i),
.ABUSWIDTH(32)
) i_fei4_rx (
.RX_CLK(CLK160),
.RX_CLK2X(CLK320),
.DATA_CLK(CLK16),
.RX_DATA(DOBOUT_DLY),
.RX_READY(RX_READY[i]),
.RX_8B10B_DECODER_ERR(RX_8B10B_DECODER_ERR[i]),
.RX_FIFO_OVERFLOW_ERR(RX_FIFO_OVERFLOW_ERR[i]),
.FIFO_CLK(1'b0),
.FIFO_READ(FE_FIFO_READ[i]),
.FIFO_EMPTY(FE_FIFO_EMPTY[i]),
.FIFO_DATA(FE_FIFO_DATA[i]),
.RX_FIFO_FULL(RX_FIFO_FULL[i]),
.RX_ENABLED(RX_ENABLED[i]),
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR)
);
IBUFDS #(
.DIFF_TERM("TRUE"),
.IBUF_LOW_PWR("FALSE"),
.IOSTANDARD("LVDS_25")
) IBUFDS_inst_i (
.O(DOBOUT),
.I(DOBOUT_P[i]),
.IB(DOBOUT_N[i])
);
/*
reg [1:0] DOBOUT_DDR;
wire DOBOUT_IDELAYE;
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.IDELAY_VALUE(0), // Input delay tap setting (0-31)
.PIPE_SEL("FALSE"), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
.SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
)
IDELAYE2_inst (
.CNTVALUEOUT(), // 5-bit output: Counter value output
.DATAOUT(DOBOUT_IDELAYE), // 1-bit output: Delayed data output
.C(BUS_CLK), // 1-bit input: Clock input
.CE(1'b0), // 1-bit input: Active high enable increment/decrement input
.CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
.CNTVALUEIN(IDELAYE_CNTVALUEIN[i]), // 5-bit input: Counter value input
.DATAIN(1'b0), // 1-bit input: Internal delay data input
.IDATAIN(DOBOUT), // 1-bit input: Data input from the I/O
.INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
.LD(IDELAYE_LD[i]), // 1-bit input: Load IDELAY_VALUE input
.LDPIPEEN(1'b0), // 1-bit input: Enable PIPELINE register to load data input
.REGRST(!LOCKED2) // 1-bit input: Active-high reset tap-delay input
);
always@(posedge CLK160)
DOBOUT_DDR[0] <= DOBOUT_IDELAYE;
always@(negedge CLK160)
DOBOUT_DDR[1] <= DOBOUT_IDELAYE;
always@(posedge CLK160)
DOBOUT_DLY <= IDELAYE_CINVCTRL[i] ? DOBOUT_DDR[1] : DOBOUT_DDR[0];
*/
always@(*) DOBOUT_DLY = DOBOUT;
wire RJ45_HITOR;
tdc_s3 #(
.BASEADDR(TDC_BASEADDR+32'h0100*i),
.HIGHADDR(TDC_HIGHADDR+32'h0100*i),
.ABUSWIDTH(32),
.CLKDV(4),
.DATA_IDENTIFIER(4'b0001 + i),
.FAST_TDC(1),
.FAST_TRIGGER(0)
) i_tdc (
.CLK320(CLK320),
.CLK160(CLK160),
.DV_CLK(CLK40),
.TDC_IN(RJ45_HITOR),
.TDC_OUT(TDC_OUT[i]),
.TRIG_IN(1'b0),
.TRIG_OUT(),
.FAST_TRIGGER_IN(),
.FAST_TRIGGER_OUT(),
.FIFO_READ(TDC_FIFO_READ[i]),
.FIFO_EMPTY(TDC_FIFO_EMPTY[i]),
.FIFO_DATA(TDC_FIFO_DATA[i]),
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.ARM_TDC(CMD_START_FLAG), // arm TDC by sending commands
.EXT_EN(1'b0),
.TIMESTAMP(TIMESTAMP[15:0])
);
IBUFDS #(
.DIFF_TERM("TRUE"),
.IBUF_LOW_PWR("FALSE"),
.IOSTANDARD("LVDS_25")
) IBUFDS_inst_RJ45_HITOR (
.O(RJ45_HITOR),
.I(RJ45_HITOR_P[i]),
.IB(RJ45_HITOR_N[i])
);
end
endgenerate
wire ARB_READY_OUT, ARB_WRITE_OUT;
wire [31:0] ARB_DATA_OUT;
wire [10:0] READ_GRANT;
rrp_arbiter #(
.WIDTH(11)
) i_rrp_arbiter (
.RST(BUS_RST),
.CLK(BUS_CLK),
.WRITE_REQ({~TDC_FIFO_EMPTY, ~FE_FIFO_EMPTY, ~TRIGGER_FIFO_EMPTY}),
.HOLD_REQ({10'b0, TRIGGER_FIFO_PREEMPT_REQ }),
.DATA_IN({TDC_FIFO_DATA[4], TDC_FIFO_DATA[3], TDC_FIFO_DATA[2], TDC_FIFO_DATA[1], TDC_FIFO_DATA[0], FE_FIFO_DATA[4], FE_FIFO_DATA[3], FE_FIFO_DATA[2], FE_FIFO_DATA[1], FE_FIFO_DATA[0], TRIGGER_FIFO_DATA}),
.READ_GRANT(READ_GRANT),
.READY_OUT(ARB_READY_OUT),
.WRITE_OUT(ARB_WRITE_OUT),
.DATA_OUT(ARB_DATA_OUT)
);
assign TRIGGER_FIFO_READ = READ_GRANT[0];
assign FE_FIFO_READ = READ_GRANT[5:1];
assign TDC_FIFO_READ = READ_GRANT[10:6];
//cdc_fifo is for timing reasons
wire [31:0] cdc_data_out;
wire full_32to8, cdc_fifo_empty;
wire FIFO_EMPTY;
cdc_syncfifo #(.DSIZE(32), .ASIZE(3)) cdc_syncfifo_i
(
.rdata(cdc_data_out),
.wfull(FIFO_FULL),
.rempty(cdc_fifo_empty),
.wdata(ARB_DATA_OUT),
.winc(ARB_WRITE_OUT), .wclk(BUS_CLK), .wrst(BUS_RST),
.rinc(!full_32to8), .rclk(BUS_CLK), .rrst(BUS_RST)
);
assign ARB_READY_OUT = !FIFO_FULL;
fifo_32_to_8 #(.DEPTH(256*1024)) i_data_fifo (
.RST(BUS_RST),
.CLK(BUS_CLK),
.WRITE(!cdc_fifo_empty),
.READ(TCP_TX_WR),
.DATA_IN(cdc_data_out),
.FULL(full_32to8),
.EMPTY(FIFO_EMPTY),
.DATA_OUT(TCP_TX_DATA)
);
assign TCP_TX_WR = !TCP_TX_FULL && !FIFO_EMPTY;
wire CLK_1HZ;
clock_divider #(
.DIVISOR(40000000)
) i_clock_divisor_40MHz_to_1Hz (
.CLK(CLK40),
.RESET(1'b0),
.CE(),
.CLOCK(CLK_1HZ)
);
wire CLK_3HZ;
clock_divider #(
.DIVISOR(13333333)
) i_clock_divisor_40MHz_to_3Hz (
.CLK(CLK40),
.RESET(1'b0),
.CE(),
.CLOCK(CLK_3HZ)
);
reg [7:0] RX_ENABLED_CLK40_FF;
wire [7:0] RX_ENABLED_CLK40_FLAG;
always @ (posedge CLK40)
begin
RX_ENABLED_CLK40_FF <= RX_ENABLED_CLK40;
end
assign RX_ENABLED_CLK40_FLAG = RX_ENABLED_CLK40 & ~RX_ENABLED_CLK40_FF;
reg [7:0] RX_ENABLED_CLK40_BUF;
always @ (posedge CLK40)
begin
if (|RX_ENABLED_CLK40_FLAG)
RX_ENABLED_CLK40_BUF <= RX_ENABLED_CLK40;
else
RX_ENABLED_CLK40_BUF <= RX_ENABLED_CLK40_BUF;
end
assign LED[7:4] = 4'hf;
assign LED[0] = ~((CLK_1HZ | FIFO_FULL) & LOCKED & LOCKED2);
assign LED[1] = ~(((|(~RX_READY & RX_ENABLED_CLK40_BUF) || |(RX_8B10B_DECODER_ERR & RX_ENABLED_CLK40_BUF))? CLK_3HZ : CLK_1HZ) | (|(RX_FIFO_OVERFLOW_ERR & RX_ENABLED_CLK40_BUF)) | (|(RX_FIFO_FULL & RX_ENABLED_CLK40_BUF)));
assign LED[2] = 1'b1;
assign LED[3] = 1'b1;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_addr_gen_lo.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_addr_gen_lo(/*AUTOARG*/
// Outputs
addr_err, rank_adr, stack_adr, bank_adr, ras_adr, cas_adr, addr_parity,
// Inputs
addr_in, config_reg, rank1_present, two_channel_mode, eight_bank_mode
);
input [39:4] addr_in;
input [8:0] config_reg;
input rank1_present;
input eight_bank_mode;
input two_channel_mode;
output addr_parity;
output addr_err;
output rank_adr;
output stack_adr;
output [2:0] bank_adr;
output [14:0] ras_adr;
output [13:0] cas_adr;
//////////////////////////////////////////////////////////////////
// WIRE
//////////////////////////////////////////////////////////////////
wire [14:0] ras_adr_cas12;
wire [14:0] ras_adr_cas11;
//////////////////////////////////////////////////////////////////
// Mux the RAS address
//////////////////////////////////////////////////////////////////
assign ras_adr_cas12[14:0] = two_channel_mode ? (
eight_bank_mode ? (
rank1_present ? (config_reg[0] ? addr_in[36:22] : addr_in[35:21]) :
(config_reg[0] ? addr_in[35:21] : addr_in[34:20])) :
(rank1_present ? (config_reg[0] ? addr_in[35:21] : addr_in[34:20]) :
(config_reg[0] ? addr_in[34:20] : addr_in[33:19])) ) :
(eight_bank_mode ? (
rank1_present ? (config_reg[0] ? addr_in[37:23] : addr_in[36:22]) :
(config_reg[0] ? addr_in[36:22] : addr_in[35:21])) :
rank1_present ? (config_reg[0] ? addr_in[36:22] : addr_in[35:21]) :
(config_reg[0] ? addr_in[35:21] : addr_in[34:20]));
assign ras_adr_cas11[14:0] = two_channel_mode ? (
eight_bank_mode ? (
rank1_present ? (config_reg[0] ? addr_in[35:21] : addr_in[34:20]) :
(config_reg[0] ? addr_in[34:20] : addr_in[33:19])) :
(rank1_present ? (config_reg[0] ? addr_in[34:20] : addr_in[33:19]) :
(config_reg[0] ? addr_in[33:19] : addr_in[32:18])) ) :
(eight_bank_mode ? (
rank1_present ? (config_reg[0] ? addr_in[36:22] : addr_in[35:21]) :
(config_reg[0] ? addr_in[35:21] : addr_in[34:20])) :
rank1_present ? (config_reg[0] ? addr_in[35:21] : addr_in[34:20]) :
(config_reg[0] ? addr_in[34:20] : addr_in[33:19]));
assign ras_adr[14:0] = (config_reg[4:1] == 4'hc) ? ras_adr_cas12[14:0] : ras_adr_cas11[14:0];
wire [7:0] upper_addr_cas12 = two_channel_mode? (
eight_bank_mode ? (
rank1_present ? (
config_reg[0] ? (
(config_reg[8:5] == 4'hf) ? {5'h0,addr_in[39:37]} :
(config_reg[8:5] == 4'he) ? {4'h0,addr_in[39:36]} : {3'h0,addr_in[39:35]}) :
(config_reg[8:5] == 4'hf) ? {4'h0,addr_in[39:36]} :
(config_reg[8:5] == 4'he) ? {3'h0,addr_in[39:35]} : {2'h0,addr_in[39:34]}) :
(config_reg[0] ? (
(config_reg[8:5] == 4'hf) ? {4'h0,addr_in[39:36]} :
(config_reg[8:5] == 4'he) ? {3'h0,addr_in[39:35]} : {2'h0,addr_in[39:34]}) :
(config_reg[8:5] == 4'hf) ? {3'h0,addr_in[39:35]} :
(config_reg[8:5] == 4'he) ? {2'h0,addr_in[39:34]} : {1'h0,addr_in[39:33]})) :
(rank1_present ? (
config_reg[0] ? (
(config_reg[8:5] == 4'hf) ? {4'h0,addr_in[39:36]} :
(config_reg[8:5] == 4'he) ? {3'h0,addr_in[39:35]} : {2'h0,addr_in[39:34]}) :
(config_reg[8:5] == 4'hf) ? {3'h0,addr_in[39:35]} :
(config_reg[8:5] == 4'he) ? {2'h0,addr_in[39:34]} : {1'h0,addr_in[39:33]}) :
(config_reg[0] ? (
(config_reg[8:5] == 4'hf) ? {3'h0,addr_in[39:35]} :
(config_reg[8:5] == 4'he) ? {2'h0,addr_in[39:34]} : {1'h0,addr_in[39:33]}) :
(config_reg[8:5] == 4'hf) ? {2'h0,addr_in[39:34]} :
(config_reg[8:5] == 4'he) ? {1'h0,addr_in[39:33]} : addr_in[39:32]))) :
eight_bank_mode ? (
rank1_present ? (
config_reg[0] ? (
(config_reg[8:5] == 4'hf) ? {6'h0,addr_in[39:38]} :
(config_reg[8:5] == 4'he) ? {5'h0,addr_in[39:37]} : {4'h0,addr_in[39:36]}) :
(config_reg[8:5] == 4'hf) ? {5'h0,addr_in[39:37]} :
(config_reg[8:5] == 4'he) ? {4'h0,addr_in[39:36]} : {3'h0,addr_in[39:35]}) :
(config_reg[0] ? (
(config_reg[8:5] == 4'hf) ? {5'h0,addr_in[39:37]} :
(config_reg[8:5] == 4'he) ? {4'h0,addr_in[39:36]} : {3'h0,addr_in[39:35]}) :
(config_reg[8:5] == 4'hf) ? {4'h0,addr_in[39:36]} :
(config_reg[8:5] == 4'he) ? {3'h0,addr_in[39:35]} : {2'h0,addr_in[39:34]})) :
(rank1_present ? (
config_reg[0] ? (
(config_reg[8:5] == 4'hf) ? {5'h0,addr_in[39:37]} :
(config_reg[8:5] == 4'he) ? {4'h0,addr_in[39:36]} : {3'h0,addr_in[39:35]}) :
(config_reg[8:5] == 4'hf) ? {4'h0,addr_in[39:36]} :
(config_reg[8:5] == 4'he) ? {3'h0,addr_in[39:35]} : {2'h0,addr_in[39:34]}) :
(config_reg[0] ? (
(config_reg[8:5] == 4'hf) ? {4'h0,addr_in[39:36]} :
(config_reg[8:5] == 4'he) ? {3'h0,addr_in[39:35]} : {2'h0,addr_in[39:34]}) :
(config_reg[8:5] == 4'hf) ? {3'h0,addr_in[39:35]} :
(config_reg[8:5] == 4'he) ? {2'h0,addr_in[39:34]} : {1'h0,addr_in[39:33]})) ;
wire [8:0] upper_addr_cas11 = two_channel_mode? (
eight_bank_mode ? (
rank1_present ? (
config_reg[0] ? (
(config_reg[8:5] == 4'hf) ? {5'h0,addr_in[39:36]} :
(config_reg[8:5] == 4'he) ? {4'h0,addr_in[39:35]} : {3'h0,addr_in[39:34]}) :
(config_reg[8:5] == 4'hf) ? {4'h0,addr_in[39:35]} :
(config_reg[8:5] == 4'he) ? {3'h0,addr_in[39:34]} : {2'h0,addr_in[39:33]}) :
(config_reg[0] ? (
(config_reg[8:5] == 4'hf) ? {4'h0,addr_in[39:35]} :
(config_reg[8:5] == 4'he) ? {3'h0,addr_in[39:34]} : {2'h0,addr_in[39:33]}) :
(config_reg[8:5] == 4'hf) ? {3'h0,addr_in[39:34]} :
(config_reg[8:5] == 4'he) ? {2'h0,addr_in[39:33]} : {1'h0,addr_in[39:32]})) :
(rank1_present ? (
config_reg[0] ? (
(config_reg[8:5] == 4'hf) ? {4'h0,addr_in[39:35]} :
(config_reg[8:5] == 4'he) ? {3'h0,addr_in[39:34]} : {2'h0,addr_in[39:33]}) :
(config_reg[8:5] == 4'hf) ? {3'h0,addr_in[39:34]} :
(config_reg[8:5] == 4'he) ? {2'h0,addr_in[39:33]} : {1'h0,addr_in[39:32]}) :
(config_reg[0] ? (
(config_reg[8:5] == 4'hf) ? {3'h0,addr_in[39:34]} :
(config_reg[8:5] == 4'he) ? {2'h0,addr_in[39:33]} : {1'h0,addr_in[39:32]}) :
(config_reg[8:5] == 4'hf) ? {2'h0,addr_in[39:33]} :
(config_reg[8:5] == 4'he) ? {1'h0,addr_in[39:32]} : addr_in[39:31]))) :
eight_bank_mode ? (
rank1_present ? (
config_reg[0] ? (
(config_reg[8:5] == 4'hf) ? {6'h0,addr_in[39:37]} :
(config_reg[8:5] == 4'he) ? {5'h0,addr_in[39:36]} : {4'h0,addr_in[39:35]}) :
(config_reg[8:5] == 4'hf) ? {5'h0,addr_in[39:36]} :
(config_reg[8:5] == 4'he) ? {4'h0,addr_in[39:35]} : {3'h0,addr_in[39:34]}) :
(config_reg[0] ? (
(config_reg[8:5] == 4'hf) ? {5'h0,addr_in[39:36]} :
(config_reg[8:5] == 4'he) ? {4'h0,addr_in[39:35]} : {3'h0,addr_in[39:34]}) :
(config_reg[8:5] == 4'hf) ? {4'h0,addr_in[39:35]} :
(config_reg[8:5] == 4'he) ? {3'h0,addr_in[39:34]} : {2'h0,addr_in[39:33]})) :
(rank1_present ? (
config_reg[0] ? (
(config_reg[8:5] == 4'hf) ? {5'h0,addr_in[39:36]} :
(config_reg[8:5] == 4'he) ? {4'h0,addr_in[39:35]} : {3'h0,addr_in[39:34]}) :
(config_reg[8:5] == 4'hf) ? {4'h0,addr_in[39:35]} :
(config_reg[8:5] == 4'he) ? {3'h0,addr_in[39:34]} : {2'h0,addr_in[39:33]}) :
(config_reg[0] ? (
(config_reg[8:5] == 4'hf) ? {4'h0,addr_in[39:35]} :
(config_reg[8:5] == 4'he) ? {3'h0,addr_in[39:34]} : {2'h0,addr_in[39:33]}) :
(config_reg[8:5] == 4'hf) ? {3'h0,addr_in[39:34]} :
(config_reg[8:5] == 4'he) ? {2'h0,addr_in[39:33]} : {1'h0,addr_in[39:32]})) ;
wire [8:0] upper_addr = (config_reg[4:1] == 4'hc) ? {1'b0, upper_addr_cas12} : upper_addr_cas11;
wire addr_err = |upper_addr[8:0];
//////////////////////////////////////////////////////////////////
// Mux the CAS address
//////////////////////////////////////////////////////////////////
assign cas_adr[13:0] = two_channel_mode ? (
(eight_bank_mode) ? (
(rank1_present) ? (
(config_reg[0]) ? (
(config_reg[4:1] == 4'hc) ?
{1'h0,addr_in[21:20],1'b1,addr_in[19:12],addr_in[5:4]} :
{2'h0,addr_in[20],1'b1,addr_in[19:12],addr_in[5:4]}) :
((config_reg[4:1] == 4'hc) ?
{1'h0,addr_in[20:19],1'b1,addr_in[18:11],addr_in[5:4]} :
{2'h0,addr_in[19],1'b1,addr_in[18:11],addr_in[5:4]}) ) :
(config_reg[0]) ? (
(config_reg[4:1] == 4'hc) ?
{1'h0,addr_in[20:19],1'b1,addr_in[18:11],addr_in[5:4]} :
{2'h0,addr_in[19],1'b1,addr_in[18:11],addr_in[5:4]}) :
((config_reg[4:1] == 4'hc) ?
{1'h0,addr_in[19:18],1'b1,addr_in[17:10],addr_in[5:4]} :
{2'h0,addr_in[18],1'b1,addr_in[17:10],addr_in[5:4]}) ) :
((rank1_present) ? (
(config_reg[0]) ? (
(config_reg[4:1] == 4'hc) ?
{1'h0,addr_in[20:19],1'b1,addr_in[18:11],addr_in[5:4]} :
{2'h0,addr_in[19],1'b1,addr_in[18:11],addr_in[5:4]}) :
((config_reg[4:1] == 4'hc) ?
{1'h0,addr_in[19:18],1'b1,addr_in[17:10],addr_in[5:4]} :
{2'h0,addr_in[18],1'b1,addr_in[17:10],addr_in[5:4]}) ) :
(config_reg[0]) ? (
(config_reg[4:1] == 4'hc) ?
{1'h0,addr_in[19:18],1'b1,addr_in[17:10],addr_in[5:4]} :
{2'h0,addr_in[18],1'b1,addr_in[17:10],addr_in[5:4]}) :
((config_reg[4:1] == 4'hc) ?
{1'h0,addr_in[18:17],1'b1,addr_in[16:9],addr_in[5:4]} :
{2'h0,addr_in[17],1'b1,addr_in[16:9],addr_in[5:4]})) ) :
((eight_bank_mode) ? (
(rank1_present) ? (
(config_reg[0]) ? (
(config_reg[4:1] == 4'hc) ?
{1'h0,addr_in[22:21],1'b1,addr_in[20:13],addr_in[5:4]} :
{2'h0,addr_in[21],1'b1,addr_in[20:13],addr_in[5:4]}) :
((config_reg[4:1] == 4'hc) ?
{1'h0,addr_in[21:20],1'b1,addr_in[19:12],addr_in[5:4]} :
{2'h0,addr_in[20],1'b1,addr_in[19:12],addr_in[5:4]}) ) :
(config_reg[0]) ? (
(config_reg[4:1] == 4'hc) ?
{1'h0,addr_in[21:20],1'b1,addr_in[19:12],addr_in[5:4]} :
{2'h0,addr_in[20],1'b1,addr_in[19:12],addr_in[5:4]}) :
((config_reg[4:1] == 4'hc) ?
{1'h0,addr_in[20:19],1'b1,addr_in[18:11],addr_in[5:4]} :
{2'h0,addr_in[19],1'b1,addr_in[18:11],addr_in[5:4]}) ) :
((rank1_present) ? (
(config_reg[0]) ? (
(config_reg[4:1] == 4'hc) ?
{1'h0,addr_in[21:20],1'b1,addr_in[19:12],addr_in[5:4]} :
{2'h0,addr_in[20],1'b1,addr_in[19:12],addr_in[5:4]}) :
((config_reg[4:1] == 4'hc) ?
{1'h0,addr_in[20:19],1'b1,addr_in[18:11],addr_in[5:4]} :
{2'h0,addr_in[19],1'b1,addr_in[18:11],addr_in[5:4]}) ) :
(config_reg[0]) ? (
(config_reg[4:1] == 4'hc) ?
{1'h0,addr_in[20:19],1'b1,addr_in[18:11],addr_in[5:4]} :
{2'h0,addr_in[19],1'b1,addr_in[18:11],addr_in[5:4]}) :
((config_reg[4:1] == 4'hc) ?
{1'h0,addr_in[19:18],1'b1,addr_in[17:10],addr_in[5:4]} :
{2'h0,addr_in[18],1'b1,addr_in[17:10],addr_in[5:4]})) );
wire rank_adr = two_channel_mode ? (
eight_bank_mode ? (
rank1_present ? (config_reg[0] ? addr_in[11] : addr_in[10]) : 1'b0) :
rank1_present ? (config_reg[0] ? addr_in[10] : addr_in[9]) : 1'b0) :
(eight_bank_mode ? (
rank1_present ? (config_reg[0] ? addr_in[12] : addr_in[11]) : 1'b0) :
rank1_present ? (config_reg[0] ? addr_in[11] : addr_in[10]) : 1'b0 );
assign stack_adr = two_channel_mode ? (
eight_bank_mode ? (config_reg[0] ? addr_in[10] : 1'b0) :
config_reg[0] ? addr_in[9] : 1'b0) :
(eight_bank_mode ? (config_reg[0] ? addr_in[11] : 1'b0) :
config_reg[0] ? addr_in[10] : 1'b0);
assign bank_adr[2:0] = two_channel_mode ? (
eight_bank_mode ? addr_in[9:7] ^ addr_in[20:18] ^ addr_in[30:28] :
config_reg[0] ? { stack_adr, addr_in[8:7] ^ addr_in[19:18] ^ addr_in[29:28] } :
rank1_present ? {rank_adr, addr_in[8:7] ^ addr_in[19:18] ^ addr_in[29:28] } :
{1'b0, addr_in[8:7] ^ addr_in[19:18] ^ addr_in[29:28] }) :
(eight_bank_mode ? addr_in[10:8] ^ addr_in[20:18] ^ addr_in[30:28] :
config_reg[0] ? { stack_adr, addr_in[9:8] ^ addr_in[19:18] ^ addr_in[29:28]} :
rank1_present ? {rank_adr, addr_in[9:8] ^ addr_in[19:18] ^ addr_in[29:28] } :
{1'b0, addr_in[9:8] ^ addr_in[19:18] ^ addr_in[29:28] });
wire addr_parity = two_channel_mode ? ^(addr_in[39:7]) : ^(addr_in[39:8]);
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/rtl")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAHCON_SYMBOL_V
`define SKY130_FD_SC_LS__FAHCON_SYMBOL_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fahcon (
//# {{data|Data Signals}}
input A ,
input B ,
input CI ,
output COUT_N,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAHCON_SYMBOL_V
|
// file: mmcm_mkid_exdes.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module mmcm_mkid_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [4:1] CLK_OUT,
// High bits of counters driven by clocks
output [4:1] COUNT,
// Status and control signals
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// Number of counters
localparam NUM_C = 4;
genvar count_gen;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || COUNTER_RESET;
reg [NUM_C:1] rst_sync;
reg [NUM_C:1] rst_sync_int;
reg [NUM_C:1] rst_sync_int1;
reg [NUM_C:1] rst_sync_int2;
// Connect the feedback on chip
wire CLKFB_OUT;
wire CLKFB_IN;
// Declare the clocks and counters
wire [NUM_C:1] clk_int;
wire [NUM_C:1] clk;
reg [C_W-1:0] counter [NUM_C:1];
// Connect the feedback on chip- duplicate the delay for CLK_OUT1
assign CLKFB_IN = CLKFB_OUT;
// Instantiation of the clocking network
//--------------------------------------
mmcm_mkid clknetwork
(// Clock in ports
.CLK_IN1 (CLK_IN1),
.CLKFB_IN (CLKFB_IN),
// Clock out ports
.CLK_OUT1 (clk_int[1]),
.CLK_OUT2 (clk_int[2]),
.CLK_OUT3 (clk_int[3]),
.CLK_OUT4 (clk_int[4]),
.CLKFB_OUT (CLKFB_OUT),
// Status and control signals
.LOCKED (LOCKED));
genvar clk_out_pins;
generate
for (clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1)
begin: gen_outclk_oddr
ODDR clkout_oddr
(.Q (CLK_OUT[clk_out_pins]),
.C (clk[clk_out_pins]),
.CE (1'b1),
.D1 (1'b1),
.D2 (1'b0),
.R (1'b0),
.S (1'b0));
end
endgenerate
// Connect the output clocks to the design
//-----------------------------------------
BUFG clkout1_buf
(.O (clk[1]),
.I (clk_int[1]));
BUFG clkout2_buf
(.O (clk[2]),
.I (clk_int[2]));
BUFG clkout3_buf
(.O (clk[3]),
.I (clk_int[3]));
BUFG clkout4_buf
(.O (clk[4]),
.I (clk_int[4]));
// Reset synchronizer
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1
always @(posedge reset_int or posedge clk[count_gen]) begin
if (reset_int) begin
rst_sync[count_gen] <= 1'b1;
rst_sync_int[count_gen]<= 1'b1;
rst_sync_int1[count_gen]<= 1'b1;
rst_sync_int2[count_gen]<= 1'b1;
end
else begin
rst_sync[count_gen] <= 1'b0;
rst_sync_int[count_gen] <= rst_sync[count_gen];
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
end
end
end
endgenerate
// Output clock sampling
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
if (rst_sync_int2[count_gen]) begin
counter[count_gen] <= #TCQ { C_W { 1'b 0 } };
end else begin
counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;
end
end
// alias the high bit of each counter to the corresponding
// bit in the output bus
assign COUNT[count_gen] = counter[count_gen][C_W-1];
end
endgenerate
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ddr_ch.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module ddr_ch(update_dr_in ,mode_ctrl_in ,shift_dr_in ,clock_dr_in ,
hiz_n_in ,afo ,serial_in ,afi ,serial_out ,testmode_l ,test_mode ,
bypass_enable_out ,ps_select_out ,rclk ,se ,pad_clk_so ,pad_clk_si
,dram_io_data_out ,spare_ddr_pin ,spare_ddr_data , arst_l_out,
dram_io_ptr_clk_inv ,bso ,bsi ,mode_ctrl_out ,update_dr_out ,
shift_dr_out ,clock_dr_out ,hiz_n_out ,bypass_enable_in ,
ps_select_in ,strobe ,io_dram_data_in ,io_dram_ecc_in ,dram_io_addr
,dram_io_clk_enable ,dram_io_cke ,dram_io_bank ,dram_io_ras_l ,
dram_io_write_en_l ,dram_io_cas_l ,dram_io_cs_l ,dram_dq ,dram_addr
,dram_cb ,dram_dqs ,dram_cke ,dram_ba ,dram_ck_n ,dram_ck_p ,
io_dram_data_valid ,dram_ras_l ,dram_we_l ,dram_cas_l ,dram_cs_l ,
burst_length_four ,dram_io_pad_clk_inv ,dram_io_pad_enable ,
dram_io_drive_enable ,rst_l ,lpf_code ,dram_io_channel_disabled ,
dram_io_drive_data ,cbu ,vdd_h ,cbd, dram_arst_l );
output arst_l_out ;
output [143:0] afi ;
output [143:0] serial_out ;
output [255:0] io_dram_data_in ;
output [31:0] io_dram_ecc_in ;
input [143:0] afo ;
input [143:0] serial_in ;
input [287:0] dram_io_data_out ;
input [9:0] spare_ddr_data ;
input [4:0] dram_io_ptr_clk_inv ;
input [14:0] dram_io_addr ;
input [2:0] dram_io_bank ;
input [3:0] dram_io_cs_l ;
input [4:0] lpf_code ;
input [8:1] cbu ;
input [8:1] cbd ;
inout [9:0] spare_ddr_pin ;
inout [127:0] dram_dq ;
inout [14:0] dram_addr ;
inout [15:0] dram_cb ;
inout [35:0] dram_dqs ;
inout [2:0] dram_ba ;
inout [3:0] dram_ck_n ;
inout [3:0] dram_ck_p ;
inout [3:0] dram_cs_l ;
output bypass_enable_out ;
output ps_select_out ;
output pad_clk_so ;
output bso ;
output mode_ctrl_out ;
output update_dr_out ;
output shift_dr_out ;
output clock_dr_out ;
output hiz_n_out ;
output io_dram_data_valid ;
input update_dr_in ;
input mode_ctrl_in ;
input shift_dr_in ;
input clock_dr_in ;
input hiz_n_in ;
input testmode_l ;
input test_mode ;
input rclk ;
input se ;
input pad_clk_si ;
input bsi ;
input bypass_enable_in ;
input ps_select_in ;
input strobe ;
input dram_io_clk_enable ;
input dram_io_cke ;
input dram_io_ras_l ;
input dram_io_write_en_l ;
input dram_io_cas_l ;
input burst_length_four ;
input dram_io_pad_clk_inv ;
input dram_io_pad_enable ;
input dram_io_drive_enable ;
input rst_l ;
input dram_arst_l ;
input dram_io_channel_disabled ;
input dram_io_drive_data ;
input vdd_h ;
inout dram_cke ;
inout dram_ras_l ;
inout dram_we_l ;
inout dram_cas_l ;
wire [7:0] net0126 ;
wire [7:0] net0180 ;
wire [8:1] cbd_l ;
wire [7:0] net0181 ;
wire [7:0] net0189 ;
wire [8:1] cbu_l ;
wire [7:0] net0128 ;
wire [1:0] pad_pos_cnt ;
wire [1:0] pad_neg_cnt ;
wire net0173 ;
wire net0200 ;
wire net0201 ;
wire net0202 ;
wire net0300 ;
wire net0203 ;
wire net0301 ;
wire net0302 ;
wire net0204 ;
wire net0303 ;
wire net0304 ;
wire net0207 ;
wire net0305 ;
wire net0306 ;
wire bot_so_pvt_si ;
wire net0253 ;
wire net0254 ;
wire bso0_bsi1 ;
wire pad_clk_so0_plogic_si1 ;
wire se_out ;
wire net0241 ;
wire net0247 ;
wire net0249 ;
wire net0191 ;
wire net0192 ;
wire net0193 ;
wire net0212 ;
wire net0194 ;
wire net0213 ;
wire net0195 ;
wire net0196 ;
wire net0197 ;
wire net0198 ;
wire net0199 ;
wire plogic_clk_so1_pad_si2 ;
bw_io_ddr_sig_top I0 (
.spare_ddr_data ({spare_ddr_data[9:8] } ),
.vrefcode_i_l ({net0189[0] ,net0189[1] ,net0189[2] ,net0189[3] ,
net0189[4] ,net0189[5] ,net0189[6] ,net0189[7] } ),
.vrefcode_i_r ({net0189[0] ,net0189[1] ,net0189[2] ,net0189[3] ,
net0189[4] ,net0189[5] ,net0189[6] ,net0189[7] } ),
.afo ({afo[71:0] } ),
.serial_in ({serial_in[71:0] } ),
.serial_out ({serial_out[71:0] } ),
.afi ({afi[71:0] } ),
.lpf_code_i_r ({lpf_code } ),
.dram_io_ptr_clk_inv_i_r ({dram_io_ptr_clk_inv[1:0] } ),
.pad_pos_cnt_i_r ({pad_pos_cnt } ),
.pad_neg_cnt_i_r ({pad_neg_cnt } ),
.cbu_i_r ({net0180[0] ,net0180[1] ,net0180[2] ,net0180[3] ,
net0180[4] ,net0180[5] ,net0180[6] ,net0180[7] } ),
.cbd_i_r ({net0181[0] ,net0181[1] ,net0181[2] ,net0181[3] ,
net0181[4] ,net0181[5] ,net0181[6] ,net0181[7] } ),
.lpf_code_i_l ({lpf_code } ),
.dram_io_ptr_clk_inv_i_l ({dram_io_ptr_clk_inv[1:0] } ),
.cbd_i_l ({cbd_l } ),
.spare_ddr_pin ({spare_ddr_pin[9:8] } ),
.dram_ck_n ({dram_ck_n } ),
.dram_ck_p ({dram_ck_p } ),
.dram_io_bank ({dram_io_bank[2] } ),
.dram_ba ({dram_ba[2] } ),
.pad_neg_cnt_i_l ({pad_neg_cnt } ),
.cbu_i_l ({cbu_l } ),
.dram_cb ({dram_cb[7:0] } ),
.pad_pos_cnt_i_l ({pad_pos_cnt } ),
.mode_ctrl_out (net0306 ),
.update_dr_out (net0305 ),
.shift_dr_out (net0304 ),
.clock_dr_out (net0303 ),
.hiz_n_out (net0302 ),
.bypass_enable_out (net0301 ),
.ps_select_out (net0300 ),
.test_mode_i_r (test_mode ),
.strobe_i_r (strobe ),
.testmode_l_i_l (testmode_l ),
.burst_length_four_i_r (burst_length_four ),
.dram_io_pad_enable_i_r (dram_io_pad_enable ),
.dram_io_drive_enable_i_r (dram_io_drive_enable ),
.rst_l_i_r (rst_l ),
.arst_l_i_r (dram_arst_l ),
.dram_io_channel_disabled_i_r (dram_io_channel_disabled ),
.dram_io_drive_data_i_r (dram_io_drive_data ),
.se_i_r (se ),
.mode_ctrl_i_r (net0191 ),
.shift_dr_i_r (net0193 ),
.clock_dr_i_r (net0194 ),
.hiz_n_i_r (net0195 ),
.update_dr_i_r (net0192 ),
.vdd_h (vdd_h ),
.strobe_i_l (strobe ),
.bypass_enable_i_l (net0203 ),
.ps_select_i_r (net0197 ),
.ps_select_i_l (net0204 ),
.test_mode_i_l (test_mode ),
.testmode_l_i_r (testmode_l ),
.dram_io_pad_enable_i_l (dram_io_pad_enable ),
.burst_length_four_i_l (burst_length_four ),
.\dram_io_data_out[95] (dram_io_data_out[95] ),
.\dram_io_data_out[94] (dram_io_data_out[94] ),
.\dram_io_data_out[93] (dram_io_data_out[93] ),
.\dram_io_data_out[92] (dram_io_data_out[92] ),
.\dram_io_data_out[91] (dram_io_data_out[91] ),
.\dram_io_data_out[90] (dram_io_data_out[90] ),
.\dram_io_data_out[89] (dram_io_data_out[89] ),
.\dram_io_data_out[88] (dram_io_data_out[88] ),
.\dram_io_data_out[87] (dram_io_data_out[87] ),
.\dram_io_data_out[86] (dram_io_data_out[86] ),
.\dram_io_data_out[85] (dram_io_data_out[85] ),
.\dram_io_data_out[84] (dram_io_data_out[84] ),
.\dram_io_data_out[83] (dram_io_data_out[83] ),
.\dram_io_data_out[82] (dram_io_data_out[82] ),
.\dram_io_data_out[81] (dram_io_data_out[81] ),
.\dram_io_data_out[80] (dram_io_data_out[80] ),
.\dram_io_data_out[79] (dram_io_data_out[79] ),
.\dram_io_data_out[78] (dram_io_data_out[78] ),
.\dram_io_data_out[77] (dram_io_data_out[77] ),
.\dram_io_data_out[76] (dram_io_data_out[76] ),
.\dram_io_data_out[75] (dram_io_data_out[75] ),
.\dram_io_data_out[74] (dram_io_data_out[74] ),
.\dram_io_data_out[73] (dram_io_data_out[73] ),
.\dram_io_data_out[72] (dram_io_data_out[72] ),
.\dram_io_data_out[71] (dram_io_data_out[71] ),
.\dram_io_data_out[70] (dram_io_data_out[70] ),
.\dram_io_data_out[69] (dram_io_data_out[69] ),
.\dram_io_data_out[68] (dram_io_data_out[68] ),
.\dram_io_data_out[67] (dram_io_data_out[67] ),
.\dram_io_data_out[66] (dram_io_data_out[66] ),
.\dram_io_data_out[65] (dram_io_data_out[65] ),
.\dram_io_data_out[64] (dram_io_data_out[64] ),
.\dram_io_data_out[31] (dram_io_data_out[31] ),
.\dram_io_data_out[30] (dram_io_data_out[30] ),
.\dram_io_data_out[29] (dram_io_data_out[29] ),
.\dram_io_data_out[28] (dram_io_data_out[28] ),
.\dram_io_data_out[27] (dram_io_data_out[27] ),
.\dram_io_data_out[26] (dram_io_data_out[26] ),
.\dram_io_data_out[25] (dram_io_data_out[25] ),
.\dram_io_data_out[24] (dram_io_data_out[24] ),
.\dram_io_data_out[23] (dram_io_data_out[23] ),
.\dram_io_data_out[22] (dram_io_data_out[22] ),
.\dram_io_data_out[21] (dram_io_data_out[21] ),
.\dram_io_data_out[20] (dram_io_data_out[20] ),
.\dram_io_data_out[19] (dram_io_data_out[19] ),
.\dram_io_data_out[18] (dram_io_data_out[18] ),
.\dram_io_data_out[17] (dram_io_data_out[17] ),
.\dram_io_data_out[16] (dram_io_data_out[16] ),
.\dram_io_data_out[15] (dram_io_data_out[15] ),
.\dram_io_data_out[14] (dram_io_data_out[14] ),
.\dram_io_data_out[13] (dram_io_data_out[13] ),
.\dram_io_data_out[12] (dram_io_data_out[12] ),
.\dram_io_data_out[11] (dram_io_data_out[11] ),
.\dram_io_data_out[10] (dram_io_data_out[10] ),
.\dram_io_data_out[9] (dram_io_data_out[9] ),
.\dram_io_data_out[8] (dram_io_data_out[8] ),
.\dram_io_data_out[7] (dram_io_data_out[7] ),
.\dram_io_data_out[6] (dram_io_data_out[6] ),
.\dram_io_data_out[5] (dram_io_data_out[5] ),
.\dram_io_data_out[4] (dram_io_data_out[4] ),
.\dram_io_data_out[3] (dram_io_data_out[3] ),
.\dram_io_data_out[2] (dram_io_data_out[2] ),
.\dram_io_data_out[1] (dram_io_data_out[1] ),
.\dram_io_data_out[0] (dram_io_data_out[0] ),
.dram_io_channel_disabled_i_l (dram_io_channel_disabled ),
.dram_io_drive_enable_i_l (dram_io_drive_enable ),
.rclk (rclk ),
.\dram_io_data_out[175] (dram_io_data_out[175] ),
.\dram_io_data_out[174] (dram_io_data_out[174] ),
.\dram_io_data_out[173] (dram_io_data_out[173] ),
.\dram_io_data_out[172] (dram_io_data_out[172] ),
.\dram_io_data_out[171] (dram_io_data_out[171] ),
.\dram_io_data_out[170] (dram_io_data_out[170] ),
.\dram_io_data_out[169] (dram_io_data_out[169] ),
.\dram_io_data_out[168] (dram_io_data_out[168] ),
.\dram_io_data_out[167] (dram_io_data_out[167] ),
.\dram_io_data_out[166] (dram_io_data_out[166] ),
.\dram_io_data_out[165] (dram_io_data_out[165] ),
.\dram_io_data_out[164] (dram_io_data_out[164] ),
.\dram_io_data_out[163] (dram_io_data_out[163] ),
.\dram_io_data_out[162] (dram_io_data_out[162] ),
.\dram_io_data_out[161] (dram_io_data_out[161] ),
.\dram_io_data_out[160] (dram_io_data_out[160] ),
.\dram_io_data_out[159] (dram_io_data_out[159] ),
.\dram_io_data_out[158] (dram_io_data_out[158] ),
.\dram_io_data_out[157] (dram_io_data_out[157] ),
.\dram_io_data_out[156] (dram_io_data_out[156] ),
.\dram_io_data_out[155] (dram_io_data_out[155] ),
.\dram_io_data_out[154] (dram_io_data_out[154] ),
.\dram_io_data_out[153] (dram_io_data_out[153] ),
.\dram_io_data_out[152] (dram_io_data_out[152] ),
.\dram_io_data_out[151] (dram_io_data_out[151] ),
.\dram_io_data_out[150] (dram_io_data_out[150] ),
.\dram_io_data_out[149] (dram_io_data_out[149] ),
.\dram_io_data_out[148] (dram_io_data_out[148] ),
.\dram_io_data_out[147] (dram_io_data_out[147] ),
.\dram_io_data_out[146] (dram_io_data_out[146] ),
.\dram_io_data_out[145] (dram_io_data_out[145] ),
.\dram_io_data_out[144] (dram_io_data_out[144] ),
.\dram_io_data_out[279] (dram_io_data_out[279] ),
.\dram_io_data_out[278] (dram_io_data_out[278] ),
.\dram_io_data_out[277] (dram_io_data_out[277] ),
.\dram_io_data_out[276] (dram_io_data_out[276] ),
.\dram_io_data_out[275] (dram_io_data_out[275] ),
.\dram_io_data_out[274] (dram_io_data_out[274] ),
.\dram_io_data_out[273] (dram_io_data_out[273] ),
.\dram_io_data_out[272] (dram_io_data_out[272] ),
.\io_dram_data_in[223] (io_dram_data_in[223] ),
.\io_dram_data_in[222] (io_dram_data_in[222] ),
.\io_dram_data_in[221] (io_dram_data_in[221] ),
.\io_dram_data_in[220] (io_dram_data_in[220] ),
.\io_dram_data_in[219] (io_dram_data_in[219] ),
.\io_dram_data_in[218] (io_dram_data_in[218] ),
.\io_dram_data_in[217] (io_dram_data_in[217] ),
.\io_dram_data_in[216] (io_dram_data_in[216] ),
.\io_dram_data_in[215] (io_dram_data_in[215] ),
.\io_dram_data_in[214] (io_dram_data_in[214] ),
.\io_dram_data_in[213] (io_dram_data_in[213] ),
.\io_dram_data_in[212] (io_dram_data_in[212] ),
.\io_dram_data_in[211] (io_dram_data_in[211] ),
.\io_dram_data_in[210] (io_dram_data_in[210] ),
.\io_dram_data_in[209] (io_dram_data_in[209] ),
.\io_dram_data_in[208] (io_dram_data_in[208] ),
.\io_dram_data_in[207] (io_dram_data_in[207] ),
.\io_dram_data_in[206] (io_dram_data_in[206] ),
.\io_dram_data_in[205] (io_dram_data_in[205] ),
.\io_dram_data_in[204] (io_dram_data_in[204] ),
.\io_dram_data_in[203] (io_dram_data_in[203] ),
.\io_dram_data_in[202] (io_dram_data_in[202] ),
.\io_dram_data_in[201] (io_dram_data_in[201] ),
.\io_dram_data_in[200] (io_dram_data_in[200] ),
.\io_dram_data_in[199] (io_dram_data_in[199] ),
.\io_dram_data_in[198] (io_dram_data_in[198] ),
.\io_dram_data_in[197] (io_dram_data_in[197] ),
.\io_dram_data_in[196] (io_dram_data_in[196] ),
.\io_dram_data_in[195] (io_dram_data_in[195] ),
.\io_dram_data_in[194] (io_dram_data_in[194] ),
.\io_dram_data_in[193] (io_dram_data_in[193] ),
.\io_dram_data_in[192] (io_dram_data_in[192] ),
.\dram_io_data_out[135] (dram_io_data_out[135] ),
.\dram_io_data_out[134] (dram_io_data_out[134] ),
.\dram_io_data_out[133] (dram_io_data_out[133] ),
.\dram_io_data_out[132] (dram_io_data_out[132] ),
.\dram_io_data_out[131] (dram_io_data_out[131] ),
.\dram_io_data_out[130] (dram_io_data_out[130] ),
.\dram_io_data_out[129] (dram_io_data_out[129] ),
.\dram_io_data_out[128] (dram_io_data_out[128] ),
.\io_dram_ecc_in[23] (io_dram_ecc_in[23] ),
.\io_dram_ecc_in[22] (io_dram_ecc_in[22] ),
.\io_dram_ecc_in[21] (io_dram_ecc_in[21] ),
.\io_dram_ecc_in[20] (io_dram_ecc_in[20] ),
.\io_dram_ecc_in[19] (io_dram_ecc_in[19] ),
.\io_dram_ecc_in[18] (io_dram_ecc_in[18] ),
.\io_dram_ecc_in[17] (io_dram_ecc_in[17] ),
.\io_dram_ecc_in[16] (io_dram_ecc_in[16] ),
.\io_dram_ecc_in[7] (io_dram_ecc_in[7] ),
.\io_dram_ecc_in[6] (io_dram_ecc_in[6] ),
.\io_dram_ecc_in[5] (io_dram_ecc_in[5] ),
.\io_dram_ecc_in[4] (io_dram_ecc_in[4] ),
.\io_dram_ecc_in[3] (io_dram_ecc_in[3] ),
.\io_dram_ecc_in[2] (io_dram_ecc_in[2] ),
.\io_dram_ecc_in[1] (io_dram_ecc_in[1] ),
.\io_dram_ecc_in[0] (io_dram_ecc_in[0] ),
.\io_dram_data_in[159] (io_dram_data_in[159] ),
.\io_dram_data_in[158] (io_dram_data_in[158] ),
.\io_dram_data_in[157] (io_dram_data_in[157] ),
.\io_dram_data_in[156] (io_dram_data_in[156] ),
.\io_dram_data_in[155] (io_dram_data_in[155] ),
.\io_dram_data_in[154] (io_dram_data_in[154] ),
.\io_dram_data_in[153] (io_dram_data_in[153] ),
.\io_dram_data_in[152] (io_dram_data_in[152] ),
.\io_dram_data_in[151] (io_dram_data_in[151] ),
.\io_dram_data_in[150] (io_dram_data_in[150] ),
.\io_dram_data_in[149] (io_dram_data_in[149] ),
.\io_dram_data_in[148] (io_dram_data_in[148] ),
.\io_dram_data_in[147] (io_dram_data_in[147] ),
.\io_dram_data_in[146] (io_dram_data_in[146] ),
.\io_dram_data_in[145] (io_dram_data_in[145] ),
.\io_dram_data_in[144] (io_dram_data_in[144] ),
.\io_dram_data_in[143] (io_dram_data_in[143] ),
.\io_dram_data_in[142] (io_dram_data_in[142] ),
.\io_dram_data_in[141] (io_dram_data_in[141] ),
.\io_dram_data_in[140] (io_dram_data_in[140] ),
.\io_dram_data_in[139] (io_dram_data_in[139] ),
.\io_dram_data_in[138] (io_dram_data_in[138] ),
.\io_dram_data_in[137] (io_dram_data_in[137] ),
.\io_dram_data_in[136] (io_dram_data_in[136] ),
.\io_dram_data_in[135] (io_dram_data_in[135] ),
.\io_dram_data_in[134] (io_dram_data_in[134] ),
.\io_dram_data_in[133] (io_dram_data_in[133] ),
.\io_dram_data_in[132] (io_dram_data_in[132] ),
.\io_dram_data_in[131] (io_dram_data_in[131] ),
.\io_dram_data_in[130] (io_dram_data_in[130] ),
.\io_dram_data_in[129] (io_dram_data_in[129] ),
.\io_dram_data_in[128] (io_dram_data_in[128] ),
.\io_dram_data_in[31] (io_dram_data_in[31] ),
.\io_dram_data_in[30] (io_dram_data_in[30] ),
.\io_dram_data_in[29] (io_dram_data_in[29] ),
.\io_dram_data_in[28] (io_dram_data_in[28] ),
.\io_dram_data_in[27] (io_dram_data_in[27] ),
.\io_dram_data_in[26] (io_dram_data_in[26] ),
.\io_dram_data_in[25] (io_dram_data_in[25] ),
.\io_dram_data_in[24] (io_dram_data_in[24] ),
.\io_dram_data_in[23] (io_dram_data_in[23] ),
.\io_dram_data_in[22] (io_dram_data_in[22] ),
.\io_dram_data_in[21] (io_dram_data_in[21] ),
.\io_dram_data_in[20] (io_dram_data_in[20] ),
.\io_dram_data_in[19] (io_dram_data_in[19] ),
.\io_dram_data_in[18] (io_dram_data_in[18] ),
.\io_dram_data_in[17] (io_dram_data_in[17] ),
.\io_dram_data_in[16] (io_dram_data_in[16] ),
.\io_dram_data_in[15] (io_dram_data_in[15] ),
.\io_dram_data_in[14] (io_dram_data_in[14] ),
.\io_dram_data_in[13] (io_dram_data_in[13] ),
.\io_dram_data_in[12] (io_dram_data_in[12] ),
.\io_dram_data_in[11] (io_dram_data_in[11] ),
.\io_dram_data_in[10] (io_dram_data_in[10] ),
.\io_dram_data_in[9] (io_dram_data_in[9] ),
.\io_dram_data_in[8] (io_dram_data_in[8] ),
.\io_dram_data_in[7] (io_dram_data_in[7] ),
.\io_dram_data_in[6] (io_dram_data_in[6] ),
.\io_dram_data_in[5] (io_dram_data_in[5] ),
.\io_dram_data_in[4] (io_dram_data_in[4] ),
.\io_dram_data_in[3] (io_dram_data_in[3] ),
.\io_dram_data_in[2] (io_dram_data_in[2] ),
.\io_dram_data_in[1] (io_dram_data_in[1] ),
.\io_dram_data_in[0] (io_dram_data_in[0] ),
.pad_clk_so (pad_clk_so0_plogic_si1 ),
.pad_clk_si (pad_clk_si ),
.\dram_addr[9] (dram_addr[9] ),
.\dram_addr[8] (dram_addr[8] ),
.\dram_addr[7] (dram_addr[7] ),
.\dram_addr[6] (dram_addr[6] ),
.\dram_addr[5] (dram_addr[5] ),
.\dram_addr[4] (dram_addr[4] ),
.\dram_addr[3] (dram_addr[3] ),
.\dram_addr[2] (dram_addr[2] ),
.\dram_addr[1] (dram_addr[1] ),
.\dram_addr[0] (dram_addr[0] ),
.\dram_io_addr[9] (dram_io_addr[9] ),
.\dram_io_addr[8] (dram_io_addr[8] ),
.\dram_io_addr[7] (dram_io_addr[7] ),
.\dram_io_addr[6] (dram_io_addr[6] ),
.\dram_io_addr[5] (dram_io_addr[5] ),
.\dram_io_addr[4] (dram_io_addr[4] ),
.\dram_io_addr[3] (dram_io_addr[3] ),
.\dram_io_addr[2] (dram_io_addr[2] ),
.\dram_io_addr[1] (dram_io_addr[1] ),
.\dram_io_addr[0] (dram_io_addr[0] ),
.\dram_dqs[12] (dram_dqs[12] ),
.\dram_dqs[11] (dram_dqs[11] ),
.\dram_dqs[10] (dram_dqs[10] ),
.\dram_dqs[9] (dram_dqs[9] ),
.\dram_dqs[8] (dram_dqs[8] ),
.bso (bso0_bsi1 ),
.bsi (bsi ),
.dram_io_clk_enable (dram_io_clk_enable ),
.\dram_addr[14] (dram_addr[14] ),
.\dram_addr[13] (dram_addr[13] ),
.\dram_addr[12] (dram_addr[12] ),
.\dram_addr[11] (dram_addr[11] ),
.dram_cke (dram_cke ),
.dram_io_cke (dram_io_cke ),
.\dram_io_addr[14] (dram_io_addr[14] ),
.\dram_io_addr[13] (dram_io_addr[13] ),
.\dram_io_addr[12] (dram_io_addr[12] ),
.\dram_io_addr[11] (dram_io_addr[11] ),
.\dram_dq[95] (dram_dq[95] ),
.\dram_dq[94] (dram_dq[94] ),
.\dram_dq[93] (dram_dq[93] ),
.\dram_dq[92] (dram_dq[92] ),
.\dram_dq[91] (dram_dq[91] ),
.\dram_dq[90] (dram_dq[90] ),
.\dram_dq[89] (dram_dq[89] ),
.\dram_dq[88] (dram_dq[88] ),
.\dram_dq[87] (dram_dq[87] ),
.\dram_dq[86] (dram_dq[86] ),
.\dram_dq[85] (dram_dq[85] ),
.\dram_dq[84] (dram_dq[84] ),
.\dram_dq[83] (dram_dq[83] ),
.\dram_dq[82] (dram_dq[82] ),
.\dram_dq[81] (dram_dq[81] ),
.\dram_dq[80] (dram_dq[80] ),
.\dram_dq[79] (dram_dq[79] ),
.\dram_dq[78] (dram_dq[78] ),
.\dram_dq[77] (dram_dq[77] ),
.\dram_dq[76] (dram_dq[76] ),
.\dram_dq[75] (dram_dq[75] ),
.\dram_dq[74] (dram_dq[74] ),
.\dram_dq[73] (dram_dq[73] ),
.\dram_dq[72] (dram_dq[72] ),
.\dram_dq[71] (dram_dq[71] ),
.\dram_dq[70] (dram_dq[70] ),
.\dram_dq[69] (dram_dq[69] ),
.\dram_dq[68] (dram_dq[68] ),
.\dram_dq[67] (dram_dq[67] ),
.\dram_dq[66] (dram_dq[66] ),
.\dram_dq[65] (dram_dq[65] ),
.\dram_dq[64] (dram_dq[64] ),
.\dram_dq[31] (dram_dq[31] ),
.\dram_dq[30] (dram_dq[30] ),
.\dram_dq[29] (dram_dq[29] ),
.\dram_dq[28] (dram_dq[28] ),
.\dram_dq[27] (dram_dq[27] ),
.\dram_dq[26] (dram_dq[26] ),
.\dram_dq[25] (dram_dq[25] ),
.\dram_dq[24] (dram_dq[24] ),
.\dram_dq[23] (dram_dq[23] ),
.\dram_dq[22] (dram_dq[22] ),
.\dram_dq[21] (dram_dq[21] ),
.\dram_dq[20] (dram_dq[20] ),
.\dram_dq[19] (dram_dq[19] ),
.\dram_dq[18] (dram_dq[18] ),
.\dram_dq[17] (dram_dq[17] ),
.\dram_dq[16] (dram_dq[16] ),
.\dram_dq[15] (dram_dq[15] ),
.\dram_dq[14] (dram_dq[14] ),
.\dram_dq[13] (dram_dq[13] ),
.\dram_dq[12] (dram_dq[12] ),
.\dram_dq[11] (dram_dq[11] ),
.\dram_dq[10] (dram_dq[10] ),
.\dram_dq[9] (dram_dq[9] ),
.\dram_dq[8] (dram_dq[8] ),
.\dram_dq[7] (dram_dq[7] ),
.\dram_dq[6] (dram_dq[6] ),
.\dram_dq[5] (dram_dq[5] ),
.\dram_dq[4] (dram_dq[4] ),
.\dram_dq[3] (dram_dq[3] ),
.\dram_dq[2] (dram_dq[2] ),
.\dram_dq[1] (dram_dq[1] ),
.\dram_dq[0] (dram_dq[0] ),
.\dram_dqs[3] (dram_dqs[3] ),
.\dram_dqs[2] (dram_dqs[2] ),
.\dram_dqs[1] (dram_dqs[1] ),
.\dram_dqs[0] (dram_dqs[0] ),
.\dram_dqs[21] (dram_dqs[21] ),
.\dram_dqs[20] (dram_dqs[20] ),
.\dram_dqs[19] (dram_dqs[19] ),
.\dram_dqs[18] (dram_dqs[18] ),
.\dram_dqs[17] (dram_dqs[17] ),
.\dram_dqs[30] (dram_dqs[30] ),
.\dram_dqs[29] (dram_dqs[29] ),
.\dram_dqs[28] (dram_dqs[28] ),
.\dram_dqs[27] (dram_dqs[27] ),
.rst_l_i_l (rst_l ),
.arst_l_i_l (dram_arst_l ),
.bypass_enable_i_r (net0196 ),
.hiz_n_i_l (net0202 ),
.shift_dr_i_l (net0200 ),
.mode_ctrl_i_l (net0198 ),
.dram_io_drive_data_i_l (dram_io_drive_data ),
.se_i_l (se ),
.update_dr_i_l (net0199 ),
.clock_dr_i_l (net0201 ),
.\io_dram_data_in[95] (io_dram_data_in[95] ),
.\io_dram_data_in[94] (io_dram_data_in[94] ),
.\io_dram_data_in[93] (io_dram_data_in[93] ),
.\io_dram_data_in[92] (io_dram_data_in[92] ),
.\io_dram_data_in[91] (io_dram_data_in[91] ),
.\io_dram_data_in[90] (io_dram_data_in[90] ),
.\io_dram_data_in[89] (io_dram_data_in[89] ),
.\io_dram_data_in[88] (io_dram_data_in[88] ),
.\io_dram_data_in[87] (io_dram_data_in[87] ),
.\io_dram_data_in[86] (io_dram_data_in[86] ),
.\io_dram_data_in[85] (io_dram_data_in[85] ),
.\io_dram_data_in[84] (io_dram_data_in[84] ),
.\io_dram_data_in[83] (io_dram_data_in[83] ),
.\io_dram_data_in[82] (io_dram_data_in[82] ),
.\io_dram_data_in[81] (io_dram_data_in[81] ),
.\io_dram_data_in[80] (io_dram_data_in[80] ),
.\io_dram_data_in[79] (io_dram_data_in[79] ),
.\io_dram_data_in[78] (io_dram_data_in[78] ),
.\io_dram_data_in[77] (io_dram_data_in[77] ),
.\io_dram_data_in[76] (io_dram_data_in[76] ),
.\io_dram_data_in[75] (io_dram_data_in[75] ),
.\io_dram_data_in[74] (io_dram_data_in[74] ),
.\io_dram_data_in[73] (io_dram_data_in[73] ),
.\io_dram_data_in[72] (io_dram_data_in[72] ),
.\io_dram_data_in[71] (io_dram_data_in[71] ),
.\io_dram_data_in[70] (io_dram_data_in[70] ),
.\io_dram_data_in[69] (io_dram_data_in[69] ),
.\io_dram_data_in[68] (io_dram_data_in[68] ),
.\io_dram_data_in[67] (io_dram_data_in[67] ),
.\io_dram_data_in[66] (io_dram_data_in[66] ),
.\io_dram_data_in[65] (io_dram_data_in[65] ),
.\io_dram_data_in[64] (io_dram_data_in[64] ),
.\dram_io_data_out[239] (dram_io_data_out[239] ),
.\dram_io_data_out[238] (dram_io_data_out[238] ),
.\dram_io_data_out[237] (dram_io_data_out[237] ),
.\dram_io_data_out[236] (dram_io_data_out[236] ),
.\dram_io_data_out[235] (dram_io_data_out[235] ),
.\dram_io_data_out[234] (dram_io_data_out[234] ),
.\dram_io_data_out[233] (dram_io_data_out[233] ),
.\dram_io_data_out[232] (dram_io_data_out[232] ),
.\dram_io_data_out[231] (dram_io_data_out[231] ),
.\dram_io_data_out[230] (dram_io_data_out[230] ),
.\dram_io_data_out[229] (dram_io_data_out[229] ),
.\dram_io_data_out[228] (dram_io_data_out[228] ),
.\dram_io_data_out[227] (dram_io_data_out[227] ),
.\dram_io_data_out[226] (dram_io_data_out[226] ),
.\dram_io_data_out[225] (dram_io_data_out[225] ),
.\dram_io_data_out[224] (dram_io_data_out[224] ),
.\dram_io_data_out[223] (dram_io_data_out[223] ),
.\dram_io_data_out[222] (dram_io_data_out[222] ),
.\dram_io_data_out[221] (dram_io_data_out[221] ),
.\dram_io_data_out[220] (dram_io_data_out[220] ),
.\dram_io_data_out[219] (dram_io_data_out[219] ),
.\dram_io_data_out[218] (dram_io_data_out[218] ),
.\dram_io_data_out[217] (dram_io_data_out[217] ),
.\dram_io_data_out[216] (dram_io_data_out[216] ),
.\dram_io_data_out[215] (dram_io_data_out[215] ),
.\dram_io_data_out[214] (dram_io_data_out[214] ),
.\dram_io_data_out[213] (dram_io_data_out[213] ),
.\dram_io_data_out[212] (dram_io_data_out[212] ),
.\dram_io_data_out[211] (dram_io_data_out[211] ),
.\dram_io_data_out[210] (dram_io_data_out[210] ),
.\dram_io_data_out[209] (dram_io_data_out[209] ),
.\dram_io_data_out[208] (dram_io_data_out[208] ) );
bw_io_ddr_sig_bot I1 (
.arst_l_out (arst_l_out),
.cbd_o_l ({cbd_l } ),
.cbu_o_l ({cbu_l } ),
.cbu_o_r ({net0180[0] ,net0180[1] ,net0180[2] ,net0180[3] ,
net0180[4] ,net0180[5] ,net0180[6] ,net0180[7] } ),
.cbd_o_r ({net0181[0] ,net0181[1] ,net0181[2] ,net0181[3] ,
net0181[4] ,net0181[5] ,net0181[6] ,net0181[7] } ),
.cbd_i_l ({net0126[0] ,net0126[1] ,net0126[2] ,net0126[3] ,
net0126[4] ,net0126[5] ,net0126[6] ,net0126[7] } ),
.cbu_i_r ({net0128[0] ,net0128[1] ,net0128[2] ,net0128[3] ,
net0128[4] ,net0128[5] ,net0128[6] ,net0128[7] } ),
.cbd_i_r ({net0126[0] ,net0126[1] ,net0126[2] ,net0126[3] ,
net0126[4] ,net0126[5] ,net0126[6] ,net0126[7] } ),
.vrefcode_i_l ({net0189[0] ,net0189[1] ,net0189[2] ,net0189[3] ,
net0189[4] ,net0189[5] ,net0189[6] ,net0189[7] } ),
.vrefcode_i_r ({net0189[0] ,net0189[1] ,net0189[2] ,net0189[3] ,
net0189[4] ,net0189[5] ,net0189[6] ,net0189[7] } ),
.serial_in ({serial_in[143:72] } ),
.afo ({afo[143:72] } ),
.serial_out ({serial_out[143:72] } ),
.afi ({afi[143:72] } ),
.spare_ddr_data ({spare_ddr_data[7:0] } ),
.spare_ddr_pin ({spare_ddr_pin[7:0] } ),
.cbu_i_l ({net0128[0] ,net0128[1] ,net0128[2] ,net0128[3] ,
net0128[4] ,net0128[5] ,net0128[6] ,net0128[7] } ),
.dram_io_ptr_clk_inv_i_l ({dram_io_ptr_clk_inv[1:0] } ),
.lpf_code_i_l ({lpf_code } ),
.pad_pos_cnt_i_l ({pad_pos_cnt } ),
.pad_neg_cnt_i_l ({pad_neg_cnt } ),
.dram_cs_l ({dram_cs_l } ),
.dram_cb ({dram_cb[15:8] } ),
.pad_neg_cnt_i_r ({pad_neg_cnt } ),
.dram_io_bank ({dram_io_bank[1:0] } ),
.dram_addr ({dram_addr[10] } ),
.lpf_code_i_r ({lpf_code } ),
.dram_io_ptr_clk_inv_i_r ({dram_io_ptr_clk_inv[1:0] } ),
.dram_io_cs_l ({dram_io_cs_l } ),
.dram_ba ({dram_ba[1:0] } ),
.dram_io_addr ({dram_io_addr[10] } ),
.pad_pos_cnt_i_r ({pad_pos_cnt } ),
.dram_io_drive_enable_o_l (net0207 ),
.se_o_l (se_out ),
.ps_select_i_r (net0212 ),
.test_mode_i_l (test_mode ),
.testmode_l_i_r (testmode_l ),
.test_mode_i_r (test_mode ),
.bypass_enable_i_l (net0213 ),
.bypass_enable_i_r (net0213 ),
.ps_select_i_l (net0212 ),
.update_dr_o_l (net0199 ),
.shift_dr_o_l (net0200 ),
.clock_dr_o_l (net0201 ),
.hiz_n_o_l (net0202 ),
.bypass_enable_o_l (net0203 ),
.ps_select_o_r (net0197 ),
.mode_ctrl_o_r (net0191 ),
.update_dr_o_r (net0192 ),
.se_i_r (se ),
.mode_ctrl_i_r (net0249 ),
.clock_dr_i_r (net0241 ),
.mode_ctrl_o_l (net0198 ),
.hiz_n_i_r (net0247 ),
.update_dr_i_r (net0254 ),
.shift_dr_o_r (net0193 ),
.dram_io_drive_enable_i_r (dram_io_drive_enable ),
.clock_dr_o_r (net0194 ),
.hiz_n_o_r (net0195 ),
.ps_select_o_l (net0204 ),
.rclk (rclk ),
.testmode_l_i_l (testmode_l ),
.burst_length_four_i_l (burst_length_four ),
.dram_io_pad_enable_i_l (dram_io_pad_enable ),
.dram_io_drive_enable_i_l (dram_io_drive_enable ),
.rst_l_i_l (rst_l ),
.arst_l_i_l (dram_arst_l ),
.strobe_i_l (strobe ),
.dram_io_channel_disabled_i_l (dram_io_channel_disabled ),
.dram_io_drive_data_i_l (dram_io_drive_data ),
.dram_io_channel_disabled_i_r (dram_io_channel_disabled ),
.dram_io_write_en_l (dram_io_write_en_l ),
.\dram_io_data_out[63] (dram_io_data_out[63] ),
.\dram_io_data_out[62] (dram_io_data_out[62] ),
.\dram_io_data_out[61] (dram_io_data_out[61] ),
.\dram_io_data_out[60] (dram_io_data_out[60] ),
.\dram_io_data_out[59] (dram_io_data_out[59] ),
.\dram_io_data_out[58] (dram_io_data_out[58] ),
.\dram_io_data_out[57] (dram_io_data_out[57] ),
.\dram_io_data_out[56] (dram_io_data_out[56] ),
.\dram_io_data_out[55] (dram_io_data_out[55] ),
.\dram_io_data_out[54] (dram_io_data_out[54] ),
.\dram_io_data_out[53] (dram_io_data_out[53] ),
.\dram_io_data_out[52] (dram_io_data_out[52] ),
.\dram_io_data_out[51] (dram_io_data_out[51] ),
.\dram_io_data_out[50] (dram_io_data_out[50] ),
.\dram_io_data_out[49] (dram_io_data_out[49] ),
.\dram_io_data_out[48] (dram_io_data_out[48] ),
.\dram_io_data_out[47] (dram_io_data_out[47] ),
.\dram_io_data_out[46] (dram_io_data_out[46] ),
.\dram_io_data_out[45] (dram_io_data_out[45] ),
.\dram_io_data_out[44] (dram_io_data_out[44] ),
.\dram_io_data_out[43] (dram_io_data_out[43] ),
.\dram_io_data_out[42] (dram_io_data_out[42] ),
.\dram_io_data_out[41] (dram_io_data_out[41] ),
.\dram_io_data_out[40] (dram_io_data_out[40] ),
.\dram_io_data_out[39] (dram_io_data_out[39] ),
.\dram_io_data_out[38] (dram_io_data_out[38] ),
.\dram_io_data_out[37] (dram_io_data_out[37] ),
.\dram_io_data_out[36] (dram_io_data_out[36] ),
.\dram_io_data_out[35] (dram_io_data_out[35] ),
.\dram_io_data_out[34] (dram_io_data_out[34] ),
.\dram_io_data_out[33] (dram_io_data_out[33] ),
.\dram_io_data_out[32] (dram_io_data_out[32] ),
.\io_dram_data_in[255] (io_dram_data_in[255] ),
.\io_dram_data_in[254] (io_dram_data_in[254] ),
.\io_dram_data_in[253] (io_dram_data_in[253] ),
.\io_dram_data_in[252] (io_dram_data_in[252] ),
.\io_dram_data_in[251] (io_dram_data_in[251] ),
.\io_dram_data_in[250] (io_dram_data_in[250] ),
.\io_dram_data_in[249] (io_dram_data_in[249] ),
.\io_dram_data_in[248] (io_dram_data_in[248] ),
.\io_dram_data_in[247] (io_dram_data_in[247] ),
.\io_dram_data_in[246] (io_dram_data_in[246] ),
.\io_dram_data_in[245] (io_dram_data_in[245] ),
.\io_dram_data_in[244] (io_dram_data_in[244] ),
.\io_dram_data_in[243] (io_dram_data_in[243] ),
.\io_dram_data_in[242] (io_dram_data_in[242] ),
.\io_dram_data_in[241] (io_dram_data_in[241] ),
.\io_dram_data_in[240] (io_dram_data_in[240] ),
.\io_dram_data_in[239] (io_dram_data_in[239] ),
.\io_dram_data_in[238] (io_dram_data_in[238] ),
.\io_dram_data_in[237] (io_dram_data_in[237] ),
.\io_dram_data_in[236] (io_dram_data_in[236] ),
.\io_dram_data_in[235] (io_dram_data_in[235] ),
.\io_dram_data_in[234] (io_dram_data_in[234] ),
.\io_dram_data_in[233] (io_dram_data_in[233] ),
.\io_dram_data_in[232] (io_dram_data_in[232] ),
.\io_dram_data_in[231] (io_dram_data_in[231] ),
.\io_dram_data_in[230] (io_dram_data_in[230] ),
.\io_dram_data_in[229] (io_dram_data_in[229] ),
.\io_dram_data_in[228] (io_dram_data_in[228] ),
.\io_dram_data_in[227] (io_dram_data_in[227] ),
.\io_dram_data_in[226] (io_dram_data_in[226] ),
.\io_dram_data_in[225] (io_dram_data_in[225] ),
.\io_dram_data_in[224] (io_dram_data_in[224] ),
.dram_io_cas_l (dram_io_cas_l ),
.dram_we_l (dram_we_l ),
.dram_cas_l (dram_cas_l ),
.\dram_dq[127] (dram_dq[127] ),
.\dram_dq[126] (dram_dq[126] ),
.\dram_dq[125] (dram_dq[125] ),
.\dram_dq[124] (dram_dq[124] ),
.\dram_dq[123] (dram_dq[123] ),
.\dram_dq[122] (dram_dq[122] ),
.\dram_dq[121] (dram_dq[121] ),
.\dram_dq[120] (dram_dq[120] ),
.\dram_dq[119] (dram_dq[119] ),
.\dram_dq[118] (dram_dq[118] ),
.\dram_dq[117] (dram_dq[117] ),
.\dram_dq[116] (dram_dq[116] ),
.\dram_dq[115] (dram_dq[115] ),
.\dram_dq[114] (dram_dq[114] ),
.\dram_dq[113] (dram_dq[113] ),
.\dram_dq[112] (dram_dq[112] ),
.\dram_dq[111] (dram_dq[111] ),
.\dram_dq[110] (dram_dq[110] ),
.\dram_dq[109] (dram_dq[109] ),
.\dram_dq[108] (dram_dq[108] ),
.\dram_dq[107] (dram_dq[107] ),
.\dram_dq[106] (dram_dq[106] ),
.\dram_dq[105] (dram_dq[105] ),
.\dram_dq[104] (dram_dq[104] ),
.\dram_dq[103] (dram_dq[103] ),
.\dram_dq[102] (dram_dq[102] ),
.\dram_dq[101] (dram_dq[101] ),
.\dram_dq[100] (dram_dq[100] ),
.\dram_dq[99] (dram_dq[99] ),
.\dram_dq[98] (dram_dq[98] ),
.\dram_dq[97] (dram_dq[97] ),
.\dram_dq[96] (dram_dq[96] ),
.\dram_io_data_out[287] (dram_io_data_out[287] ),
.\dram_io_data_out[286] (dram_io_data_out[286] ),
.\dram_io_data_out[285] (dram_io_data_out[285] ),
.\dram_io_data_out[284] (dram_io_data_out[284] ),
.\dram_io_data_out[283] (dram_io_data_out[283] ),
.\dram_io_data_out[282] (dram_io_data_out[282] ),
.\dram_io_data_out[281] (dram_io_data_out[281] ),
.\dram_io_data_out[280] (dram_io_data_out[280] ),
.\dram_io_data_out[143] (dram_io_data_out[143] ),
.\dram_io_data_out[142] (dram_io_data_out[142] ),
.\dram_io_data_out[141] (dram_io_data_out[141] ),
.\dram_io_data_out[140] (dram_io_data_out[140] ),
.\dram_io_data_out[139] (dram_io_data_out[139] ),
.\dram_io_data_out[138] (dram_io_data_out[138] ),
.\dram_io_data_out[137] (dram_io_data_out[137] ),
.\dram_io_data_out[136] (dram_io_data_out[136] ),
.\io_dram_ecc_in[31] (io_dram_ecc_in[31] ),
.\io_dram_ecc_in[30] (io_dram_ecc_in[30] ),
.\io_dram_ecc_in[29] (io_dram_ecc_in[29] ),
.\io_dram_ecc_in[28] (io_dram_ecc_in[28] ),
.\io_dram_ecc_in[27] (io_dram_ecc_in[27] ),
.\io_dram_ecc_in[26] (io_dram_ecc_in[26] ),
.\io_dram_ecc_in[25] (io_dram_ecc_in[25] ),
.\io_dram_ecc_in[24] (io_dram_ecc_in[24] ),
.\io_dram_ecc_in[15] (io_dram_ecc_in[15] ),
.\io_dram_ecc_in[14] (io_dram_ecc_in[14] ),
.\io_dram_ecc_in[13] (io_dram_ecc_in[13] ),
.\io_dram_ecc_in[12] (io_dram_ecc_in[12] ),
.\io_dram_ecc_in[11] (io_dram_ecc_in[11] ),
.\io_dram_ecc_in[10] (io_dram_ecc_in[10] ),
.\io_dram_ecc_in[9] (io_dram_ecc_in[9] ),
.\io_dram_ecc_in[8] (io_dram_ecc_in[8] ),
.\dram_io_data_out[127] (dram_io_data_out[127] ),
.\dram_io_data_out[126] (dram_io_data_out[126] ),
.\dram_io_data_out[125] (dram_io_data_out[125] ),
.\dram_io_data_out[124] (dram_io_data_out[124] ),
.\dram_io_data_out[123] (dram_io_data_out[123] ),
.\dram_io_data_out[122] (dram_io_data_out[122] ),
.\dram_io_data_out[121] (dram_io_data_out[121] ),
.\dram_io_data_out[120] (dram_io_data_out[120] ),
.\dram_io_data_out[119] (dram_io_data_out[119] ),
.\dram_io_data_out[118] (dram_io_data_out[118] ),
.\dram_io_data_out[117] (dram_io_data_out[117] ),
.\dram_io_data_out[116] (dram_io_data_out[116] ),
.\dram_io_data_out[115] (dram_io_data_out[115] ),
.\dram_io_data_out[114] (dram_io_data_out[114] ),
.\dram_io_data_out[113] (dram_io_data_out[113] ),
.\dram_io_data_out[112] (dram_io_data_out[112] ),
.\dram_io_data_out[111] (dram_io_data_out[111] ),
.\dram_io_data_out[110] (dram_io_data_out[110] ),
.\dram_io_data_out[109] (dram_io_data_out[109] ),
.\dram_io_data_out[108] (dram_io_data_out[108] ),
.\dram_io_data_out[107] (dram_io_data_out[107] ),
.\dram_io_data_out[106] (dram_io_data_out[106] ),
.\dram_io_data_out[105] (dram_io_data_out[105] ),
.\dram_io_data_out[104] (dram_io_data_out[104] ),
.\dram_io_data_out[103] (dram_io_data_out[103] ),
.\dram_io_data_out[102] (dram_io_data_out[102] ),
.\dram_io_data_out[101] (dram_io_data_out[101] ),
.\dram_io_data_out[100] (dram_io_data_out[100] ),
.\dram_io_data_out[99] (dram_io_data_out[99] ),
.\dram_io_data_out[98] (dram_io_data_out[98] ),
.\dram_io_data_out[97] (dram_io_data_out[97] ),
.\dram_io_data_out[96] (dram_io_data_out[96] ),
.\io_dram_data_in[191] (io_dram_data_in[191] ),
.\io_dram_data_in[190] (io_dram_data_in[190] ),
.\io_dram_data_in[189] (io_dram_data_in[189] ),
.\io_dram_data_in[188] (io_dram_data_in[188] ),
.\io_dram_data_in[187] (io_dram_data_in[187] ),
.\io_dram_data_in[186] (io_dram_data_in[186] ),
.\io_dram_data_in[185] (io_dram_data_in[185] ),
.\io_dram_data_in[184] (io_dram_data_in[184] ),
.\io_dram_data_in[183] (io_dram_data_in[183] ),
.\io_dram_data_in[182] (io_dram_data_in[182] ),
.\io_dram_data_in[181] (io_dram_data_in[181] ),
.\io_dram_data_in[180] (io_dram_data_in[180] ),
.\io_dram_data_in[179] (io_dram_data_in[179] ),
.\io_dram_data_in[178] (io_dram_data_in[178] ),
.\io_dram_data_in[177] (io_dram_data_in[177] ),
.\io_dram_data_in[176] (io_dram_data_in[176] ),
.\io_dram_data_in[175] (io_dram_data_in[175] ),
.\io_dram_data_in[174] (io_dram_data_in[174] ),
.\io_dram_data_in[173] (io_dram_data_in[173] ),
.\io_dram_data_in[172] (io_dram_data_in[172] ),
.\io_dram_data_in[171] (io_dram_data_in[171] ),
.\io_dram_data_in[170] (io_dram_data_in[170] ),
.\io_dram_data_in[169] (io_dram_data_in[169] ),
.\io_dram_data_in[168] (io_dram_data_in[168] ),
.\io_dram_data_in[167] (io_dram_data_in[167] ),
.\io_dram_data_in[166] (io_dram_data_in[166] ),
.\io_dram_data_in[165] (io_dram_data_in[165] ),
.\io_dram_data_in[164] (io_dram_data_in[164] ),
.\io_dram_data_in[163] (io_dram_data_in[163] ),
.\io_dram_data_in[162] (io_dram_data_in[162] ),
.\io_dram_data_in[161] (io_dram_data_in[161] ),
.\io_dram_data_in[160] (io_dram_data_in[160] ),
.rst_l_i_r (rst_l ),
.arst_l_i_r (dram_arst_l ),
.\io_dram_data_in[127] (io_dram_data_in[127] ),
.\io_dram_data_in[126] (io_dram_data_in[126] ),
.\io_dram_data_in[125] (io_dram_data_in[125] ),
.\io_dram_data_in[124] (io_dram_data_in[124] ),
.\io_dram_data_in[123] (io_dram_data_in[123] ),
.\io_dram_data_in[122] (io_dram_data_in[122] ),
.\io_dram_data_in[121] (io_dram_data_in[121] ),
.\io_dram_data_in[120] (io_dram_data_in[120] ),
.\io_dram_data_in[119] (io_dram_data_in[119] ),
.\io_dram_data_in[118] (io_dram_data_in[118] ),
.\io_dram_data_in[117] (io_dram_data_in[117] ),
.\io_dram_data_in[116] (io_dram_data_in[116] ),
.\io_dram_data_in[115] (io_dram_data_in[115] ),
.\io_dram_data_in[114] (io_dram_data_in[114] ),
.\io_dram_data_in[113] (io_dram_data_in[113] ),
.\io_dram_data_in[112] (io_dram_data_in[112] ),
.\io_dram_data_in[111] (io_dram_data_in[111] ),
.\io_dram_data_in[110] (io_dram_data_in[110] ),
.\io_dram_data_in[109] (io_dram_data_in[109] ),
.\io_dram_data_in[108] (io_dram_data_in[108] ),
.\io_dram_data_in[107] (io_dram_data_in[107] ),
.\io_dram_data_in[106] (io_dram_data_in[106] ),
.\io_dram_data_in[105] (io_dram_data_in[105] ),
.\io_dram_data_in[104] (io_dram_data_in[104] ),
.\io_dram_data_in[103] (io_dram_data_in[103] ),
.\io_dram_data_in[102] (io_dram_data_in[102] ),
.\io_dram_data_in[101] (io_dram_data_in[101] ),
.\io_dram_data_in[100] (io_dram_data_in[100] ),
.\io_dram_data_in[99] (io_dram_data_in[99] ),
.\io_dram_data_in[98] (io_dram_data_in[98] ),
.\io_dram_data_in[97] (io_dram_data_in[97] ),
.\io_dram_data_in[96] (io_dram_data_in[96] ),
.pad_clk_si (plogic_clk_so1_pad_si2 ),
.dram_ras_l (dram_ras_l ),
.dram_io_pad_enable_i_r (dram_io_pad_enable ),
.\dram_io_data_out[271] (dram_io_data_out[271] ),
.\dram_io_data_out[270] (dram_io_data_out[270] ),
.\dram_io_data_out[269] (dram_io_data_out[269] ),
.\dram_io_data_out[268] (dram_io_data_out[268] ),
.\dram_io_data_out[267] (dram_io_data_out[267] ),
.\dram_io_data_out[266] (dram_io_data_out[266] ),
.\dram_io_data_out[265] (dram_io_data_out[265] ),
.\dram_io_data_out[264] (dram_io_data_out[264] ),
.\dram_io_data_out[263] (dram_io_data_out[263] ),
.\dram_io_data_out[262] (dram_io_data_out[262] ),
.\dram_io_data_out[261] (dram_io_data_out[261] ),
.\dram_io_data_out[260] (dram_io_data_out[260] ),
.\dram_io_data_out[259] (dram_io_data_out[259] ),
.\dram_io_data_out[258] (dram_io_data_out[258] ),
.\dram_io_data_out[257] (dram_io_data_out[257] ),
.\dram_io_data_out[256] (dram_io_data_out[256] ),
.\dram_io_data_out[255] (dram_io_data_out[255] ),
.\dram_io_data_out[254] (dram_io_data_out[254] ),
.\dram_io_data_out[253] (dram_io_data_out[253] ),
.\dram_io_data_out[252] (dram_io_data_out[252] ),
.\dram_io_data_out[251] (dram_io_data_out[251] ),
.\dram_io_data_out[250] (dram_io_data_out[250] ),
.\dram_io_data_out[249] (dram_io_data_out[249] ),
.\dram_io_data_out[248] (dram_io_data_out[248] ),
.\dram_io_data_out[247] (dram_io_data_out[247] ),
.\dram_io_data_out[246] (dram_io_data_out[246] ),
.\dram_io_data_out[245] (dram_io_data_out[245] ),
.\dram_io_data_out[244] (dram_io_data_out[244] ),
.\dram_io_data_out[243] (dram_io_data_out[243] ),
.\dram_io_data_out[242] (dram_io_data_out[242] ),
.\dram_io_data_out[241] (dram_io_data_out[241] ),
.\dram_io_data_out[240] (dram_io_data_out[240] ),
.mode_ctrl_i_l (net0249 ),
.\dram_dqs[7] (dram_dqs[7] ),
.\dram_dqs[6] (dram_dqs[6] ),
.\dram_dqs[5] (dram_dqs[5] ),
.\dram_dqs[4] (dram_dqs[4] ),
.bsi (bso0_bsi1 ),
.bso (bso_pre_latch ),
.burst_length_four_i_r (burst_length_four ),
.strobe_i_r (strobe ),
.update_dr_i_l (net0254 ),
.hiz_n_i_l (net0247 ),
.clock_dr_i_l (net0241 ),
.shift_dr_i_l (net0253 ),
.se_i_l (se ),
.pad_clk_so (bot_so_pvt_si ),
.dram_io_ras_l (dram_io_ras_l ),
.\dram_dq[63] (dram_dq[63] ),
.\dram_dq[62] (dram_dq[62] ),
.\dram_dq[61] (dram_dq[61] ),
.\dram_dq[60] (dram_dq[60] ),
.\dram_dq[59] (dram_dq[59] ),
.\dram_dq[58] (dram_dq[58] ),
.\dram_dq[57] (dram_dq[57] ),
.\dram_dq[56] (dram_dq[56] ),
.\dram_dq[55] (dram_dq[55] ),
.\dram_dq[54] (dram_dq[54] ),
.\dram_dq[53] (dram_dq[53] ),
.\dram_dq[52] (dram_dq[52] ),
.\dram_dq[51] (dram_dq[51] ),
.\dram_dq[50] (dram_dq[50] ),
.\dram_dq[49] (dram_dq[49] ),
.\dram_dq[48] (dram_dq[48] ),
.\dram_dq[47] (dram_dq[47] ),
.\dram_dq[46] (dram_dq[46] ),
.\dram_dq[45] (dram_dq[45] ),
.\dram_dq[44] (dram_dq[44] ),
.\dram_dq[43] (dram_dq[43] ),
.\dram_dq[42] (dram_dq[42] ),
.\dram_dq[41] (dram_dq[41] ),
.\dram_dq[40] (dram_dq[40] ),
.\dram_dq[39] (dram_dq[39] ),
.\dram_dq[38] (dram_dq[38] ),
.\dram_dq[37] (dram_dq[37] ),
.\dram_dq[36] (dram_dq[36] ),
.\dram_dq[35] (dram_dq[35] ),
.\dram_dq[34] (dram_dq[34] ),
.\dram_dq[33] (dram_dq[33] ),
.\dram_dq[32] (dram_dq[32] ),
.\dram_dqs[35] (dram_dqs[35] ),
.\dram_dqs[34] (dram_dqs[34] ),
.\dram_dqs[33] (dram_dqs[33] ),
.\dram_dqs[32] (dram_dqs[32] ),
.\dram_dqs[31] (dram_dqs[31] ),
.\dram_dqs[16] (dram_dqs[16] ),
.\dram_dqs[15] (dram_dqs[15] ),
.\dram_dqs[14] (dram_dqs[14] ),
.\dram_dqs[13] (dram_dqs[13] ),
.\dram_dqs[26] (dram_dqs[26] ),
.\dram_dqs[25] (dram_dqs[25] ),
.\dram_dqs[24] (dram_dqs[24] ),
.\dram_dqs[23] (dram_dqs[23] ),
.\dram_dqs[22] (dram_dqs[22] ),
.dram_io_drive_data_i_r (dram_io_drive_data ),
.shift_dr_i_r (net0253 ),
.bypass_enable_o_r (net0196 ),
.vdd_h (vdd_h ),
.\io_dram_data_in[63] (io_dram_data_in[63] ),
.\io_dram_data_in[62] (io_dram_data_in[62] ),
.\io_dram_data_in[61] (io_dram_data_in[61] ),
.\io_dram_data_in[60] (io_dram_data_in[60] ),
.\io_dram_data_in[59] (io_dram_data_in[59] ),
.\io_dram_data_in[58] (io_dram_data_in[58] ),
.\io_dram_data_in[57] (io_dram_data_in[57] ),
.\io_dram_data_in[56] (io_dram_data_in[56] ),
.\io_dram_data_in[55] (io_dram_data_in[55] ),
.\io_dram_data_in[54] (io_dram_data_in[54] ),
.\io_dram_data_in[53] (io_dram_data_in[53] ),
.\io_dram_data_in[52] (io_dram_data_in[52] ),
.\io_dram_data_in[51] (io_dram_data_in[51] ),
.\io_dram_data_in[50] (io_dram_data_in[50] ),
.\io_dram_data_in[49] (io_dram_data_in[49] ),
.\io_dram_data_in[48] (io_dram_data_in[48] ),
.\io_dram_data_in[47] (io_dram_data_in[47] ),
.\io_dram_data_in[46] (io_dram_data_in[46] ),
.\io_dram_data_in[45] (io_dram_data_in[45] ),
.\io_dram_data_in[44] (io_dram_data_in[44] ),
.\io_dram_data_in[43] (io_dram_data_in[43] ),
.\io_dram_data_in[42] (io_dram_data_in[42] ),
.\io_dram_data_in[41] (io_dram_data_in[41] ),
.\io_dram_data_in[40] (io_dram_data_in[40] ),
.\io_dram_data_in[39] (io_dram_data_in[39] ),
.\io_dram_data_in[38] (io_dram_data_in[38] ),
.\io_dram_data_in[37] (io_dram_data_in[37] ),
.\io_dram_data_in[36] (io_dram_data_in[36] ),
.\io_dram_data_in[35] (io_dram_data_in[35] ),
.\io_dram_data_in[34] (io_dram_data_in[34] ),
.\io_dram_data_in[33] (io_dram_data_in[33] ),
.\io_dram_data_in[32] (io_dram_data_in[32] ),
.\dram_io_data_out[207] (dram_io_data_out[207] ),
.\dram_io_data_out[206] (dram_io_data_out[206] ),
.\dram_io_data_out[205] (dram_io_data_out[205] ),
.\dram_io_data_out[204] (dram_io_data_out[204] ),
.\dram_io_data_out[203] (dram_io_data_out[203] ),
.\dram_io_data_out[202] (dram_io_data_out[202] ),
.\dram_io_data_out[201] (dram_io_data_out[201] ),
.\dram_io_data_out[200] (dram_io_data_out[200] ),
.\dram_io_data_out[199] (dram_io_data_out[199] ),
.\dram_io_data_out[198] (dram_io_data_out[198] ),
.\dram_io_data_out[197] (dram_io_data_out[197] ),
.\dram_io_data_out[196] (dram_io_data_out[196] ),
.\dram_io_data_out[195] (dram_io_data_out[195] ),
.\dram_io_data_out[194] (dram_io_data_out[194] ),
.\dram_io_data_out[193] (dram_io_data_out[193] ),
.\dram_io_data_out[192] (dram_io_data_out[192] ),
.\dram_io_data_out[191] (dram_io_data_out[191] ),
.\dram_io_data_out[190] (dram_io_data_out[190] ),
.\dram_io_data_out[189] (dram_io_data_out[189] ),
.\dram_io_data_out[188] (dram_io_data_out[188] ),
.\dram_io_data_out[187] (dram_io_data_out[187] ),
.\dram_io_data_out[186] (dram_io_data_out[186] ),
.\dram_io_data_out[185] (dram_io_data_out[185] ),
.\dram_io_data_out[184] (dram_io_data_out[184] ),
.\dram_io_data_out[183] (dram_io_data_out[183] ),
.\dram_io_data_out[182] (dram_io_data_out[182] ),
.\dram_io_data_out[181] (dram_io_data_out[181] ),
.\dram_io_data_out[180] (dram_io_data_out[180] ),
.\dram_io_data_out[179] (dram_io_data_out[179] ),
.\dram_io_data_out[178] (dram_io_data_out[178] ),
.\dram_io_data_out[177] (dram_io_data_out[177] ),
.\dram_io_data_out[176] (dram_io_data_out[176] ) );
dram_pad_logic I9 (
.pad_neg_cnt ({pad_neg_cnt } ),
.pad_pos_cnt ({pad_pos_cnt } ),
.testmode_l (testmode_l ),
.pad_logic_clk_se (se ),
.pad_logic_clk_si (pad_clk_so0_plogic_si1 ),
.dram_io_pad_clk_inv (dram_io_pad_clk_inv ),
.dram_io_pad_enable (dram_io_pad_enable ),
.burst_length_four (burst_length_four ),
.clk (net0173 ),
.io_dram_data_valid (io_dram_data_valid ),
.arst_l (dram_arst_l ),
.rst_l (rst_l ),
.pad_logic_clk_so (plogic_clk_so1_pad_si2 ) );
bw_u1_buf_15x I140 (
.z (net0249 ),
.a (mode_ctrl_in ) );
bw_u1_buf_15x I141 (
.z (net0254 ),
.a (update_dr_in ) );
bw_u1_buf_15x I142 (
.z (net0253 ),
.a (shift_dr_in ) );
bw_u1_buf_15x I143 (
.z (net0241 ),
.a (clock_dr_in ) );
bw_u1_buf_15x I144 (
.z (net0247 ),
.a (hiz_n_in ) );
bw_u1_buf_15x I145 (
.z (net0213 ),
.a (bypass_enable_in ) );
bw_u1_buf_15x I146 (
.z (net0212 ),
.a (ps_select_in ) );
bw_u1_buf_15x I155 (
.z (shift_dr_out ),
.a (net0304 ) );
bw_u1_buf_15x I156 (
.z (mode_ctrl_out ),
.a (net0306 ) );
bw_u1_buf_15x I157 (
.z (bypass_enable_out ),
.a (net0301 ) );
bw_u1_buf_15x I158 (
.z (clock_dr_out ),
.a (net0303 ) );
bw_u1_buf_15x I159 (
.z (update_dr_out ),
.a (net0305 ) );
bw_u1_buf_15x I160 (
.z (hiz_n_out ),
.a (net0302 ) );
bw_u1_buf_15x I161 (
.z (ps_select_out ),
.a (net0300 ) );
bw_io_ddr_vref_logic I177 (
.vrefcode ({net0189[0] ,net0189[1] ,net0189[2] ,net0189[3] ,
net0189[4] ,net0189[5] ,net0189[6] ,net0189[7] } ),
.a (dram_io_ptr_clk_inv[2] ),
.c (dram_io_ptr_clk_inv[4] ),
.b (dram_io_ptr_clk_inv[3] ),
.vdd18 (vdd_h ) );
bw_io_ddr_pvt_enable I186 (
.cbd_in ({cbd } ),
.cbu_in ({cbu } ),
.cbu_out ({net0128[0] ,net0128[1] ,net0128[2] ,net0128[3] ,
net0128[4] ,net0128[5] ,net0128[6] ,net0128[7] } ),
.cbd_out ({net0126[0] ,net0126[1] ,net0126[2] ,net0126[3] ,
net0126[4] ,net0126[5] ,net0126[6] ,net0126[7] } ),
.si (bot_so_pvt_si ),
.en (net0207 ),
.rclk (rclk ),
.se (se_out ),
.so (pad_clk_so ) );
bw_u1_ckbuf_6x I124 (
.clk (net0173 ),
.rclk (rclk ) );
bw_u1_scanl_2x lockup_latch(
.so(bso),
.sd(bso_pre_latch),
.ck(clock_dr_in));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVPWRVGND_SYMBOL_V
`define SKY130_FD_SC_LS__TAPVPWRVGND_SYMBOL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__tapvpwrvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVPWRVGND_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__NAND2_BEHAVIORAL_PP_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand2 (
VPWR,
VGND,
Y ,
A ,
B
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
// Local signals
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2111OI_BEHAVIORAL_V
`define SKY130_FD_SC_HS__A2111OI_BEHAVIORAL_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a2111oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
// Local signals
wire C1 and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, C1, D1, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2111OI_BEHAVIORAL_V |
////////////////////////////////////////////////////////////////////////////////////////////////////
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
// 02111-1307, USA.
//
// ©2013 - Roman Ovseitsev <[email protected]>
////////////////////////////////////////////////////////////////////////////////////////////////////
//##################################################################################################
//
// Test module for HostIo functions and the SDRAM controller.
//
//##################################################################################################
`timescale 1ns / 1ps
module Test (clk_i, sdClk_o, sdClkFb_i, sdRas_bo, sdCas_bo, sdWe_bo, sdBs_o, sdAddr_o, sdData_io);
localparam SADDR_WIDTH = 12; // SDRAM-side address width.
localparam DATA_WIDTH = 16; // Host & SDRAM data width.
input clk_i;
output sdClk_o; // SDRAM master clock.
input sdClkFb_i; // Clock feedback from SDRAM.
output sdRas_bo; // SDRAM row address strobe.
output sdCas_bo; // SDRAM column address strobe.
output sdWe_bo; // SDRAM write enable.
output sdBs_o; // SDRAM bank address.
output [SADDR_WIDTH-1:0] sdAddr_o; // SDRAM row/column address.
inout [DATA_WIDTH-1:0] sdData_io; // Data to/from SDRAM.
wire drck1;
wire reset;
wire sel1;
wire shift;
wire tdi;
wire tdo1;
wire tdo1_1;
wire tdo1_2;
// Generate 24MHz clock and feed it to SDRAM.
ClkGen #(.MUL(2), .DIV(1), .IN_FREQ(12.0)) clkgen_inst
(
.clk_i(clk_i),
.clk_o(sdClk_o)
);
// Instantiate BSCAN primitive for HostIo modules.
BSCAN bscan
(
.drck1_o(drck1), .reset_o(reset), .sel1_o(sel1), .shift_o(shift), .tdi_o(tdi), .tdo1_i(tdo1)
);
// HostIoRam SDRAM R/W test
TestRam #(.SADDR_WIDTH(SADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH)) test1
(
.drck1_i(drck1), .reset_i(reset), .sel1_i(sel1), .shift_i(shift), .tdi_i(tdi), .tdo1_o(tdo1_1),
.sdRas_bo(sdRas_bo),
.sdCas_bo(sdCas_bo),
.sdWe_bo(sdWe_bo),
.sdBs_o(sdBs_o),
.sdAddr_o(sdAddr_o),
.sdData_io(sdData_io),
.sdClkFb_i(sdClkFb_i)
);
// HostIoDut test
TestCnt test2
(
.drck1_i(drck1), .reset_i(reset), .sel1_i(sel1), .shift_i(shift), .tdi_i(tdi), .tdo1_o(tdo1_2)
);
// Since we are using multiple HostIo module instances,
// their TDO outputs should be multiplexed into BSCAN primitive TDO input
assign tdo1 = tdo1_1 | tdo1_2;
endmodule
//**************************************************************************************************
// Setups SDRAM <-> PC communication. Application on the PC side can perform tests by writing and
// reading back from the SDRAM memory.
//**************************************************************************************************
module TestRam (drck1_i, reset_i, sel1_i, shift_i, tdi_i, tdo1_o,
sdRas_bo, sdCas_bo, sdWe_bo, sdBs_o, sdAddr_o, sdData_io, sdClkFb_i);
parameter SADDR_WIDTH = 12; // SDRAM-side address width.
parameter DATA_WIDTH = 16; // Host & SDRAM data width.
output sdRas_bo; // SDRAM row address strobe.
output sdCas_bo; // SDRAM column address strobe.
output sdWe_bo; // SDRAM write enable.
output [1:0] sdBs_o; // SDRAM bank address.
output [SADDR_WIDTH-1:0] sdAddr_o; // SDRAM row/column address.
inout [DATA_WIDTH-1:0] sdData_io; // Data to/from SDRAM.
input sdClkFb_i;
input drck1_i;
input reset_i;
input sel1_i;
input shift_i;
input tdi_i;
output tdo1_o;
wire wrDone;
wire rdDone;
wire [22:0] sdraddr;
wire [15:0] datai;
wire [15:0] datao;
wire wrJtag;
wire rdJtag;
wire wrSdram;
wire rdSdram;
wire rwDone_s;
wire rdDone_s;
wire wrDone_s;
wire opBegun_o;
HostIoRam #(.ID(3), .DATA_WIDTH(16), .ADDR_WIDTH(23)) hostioram
(
.addr_o(sdraddr),.dataFromHost_o(datai),
.dataToHost_i(datao),
.wr_o(wrJtag), .rd_o(rdJtag), .rwDone_i(rwDone_s),
.drck1_i(drck1_i), .reset_i(reset_i), .sel1_i(sel1_i), .shift_i(shift_i), .tdi_i(tdi_i), .tdo1_o(tdo1_o)
);
RamCtrlSync syncRead
(
.drck_i(drck1_i), // Clock from JTAG domain.
.clk_i(sdClkFb_i), // Clock from RAM domain.
.ctrlIn_i(rdJtag), // Control signal from JTAG domain.
.ctrlOut_o(rdSdram), // Control signal to RAM domain.
.opBegun_i(opBegun_o), // R/W operation begun signal from RAM domain.
.doneIn_i(rdDone), // R/W operation done signal from RAM domain.
.doneOut_o(rdDone_s) // R/W operation done signal to the JTAG domain.
);
RamCtrlSync syncWrite
(
.drck_i(drck1_i), // Clock from JTAG domain.
.clk_i(sdClkFb_i), // Clock from RAM domain.
.ctrlIn_i(wrJtag), // Control signal from JTAG domain.
.ctrlOut_o(wrSdram), // Control signal to RAM domain.
.opBegun_i(opBegun_o), // R/W operation begun signal from RAM domain.
.doneIn_i(wrDone), // R/W operation done signal from RAM domain.
.doneOut_o(wrDone_s) // R/W operation done signal to the JTAG domain.
);
assign rwDone_s = rdDone_s | wrDone_s;
SdramCtrl #(.FREQ(24.0)) sdram
(
.clk_i(sdClkFb_i),
.lock_i(1'b1),
.rst_i(1'b0),
.rd_i(rdSdram),
.wr_i(wrSdram),
.opBegun_o(opBegun_o),
.done_o(wrDone),
.rdDone_o(rdDone),
.addr_i(sdraddr),
.data_i(datai),
.data_o(datao),
.sdRas_bo(sdRas_bo),
.sdCas_bo(sdCas_bo),
.sdWe_bo(sdWe_bo),
.sdBs_o(sdBs_o),
.sdAddr_o(sdAddr_o),
.sdData_io(sdData_io)
);
endmodule
//**************************************************************************************************
// Simple counter for HostIoDut test. Application on the PC side can perform tests by sending
// a value to DUT (pulsing the counter's clock) and reading back the new counter value.
//**************************************************************************************************
module TestCnt (drck1_i, reset_i, sel1_i, shift_i, tdi_i, tdo1_o);
input drck1_i;
input reset_i;
input sel1_i;
input shift_i;
input tdi_i;
output tdo1_o;
reg [4:0] from = 0;
(* BUFFER_TYPE="BUFG" *)
wire clkDut;
HostIODut #(.ID(1), .FROM_DUT_LENGTH(5), .TO_DUT_LENGTH(4)) hostiodut
(
.fromDut_i(from),
//.toDut_o(to),
.clkDut_o(clkDut),
.drck1_i(drck1_i), .reset_i(reset_i), .sel1_i(sel1_i), .shift_i(shift_i), .tdi_i(tdi_i), .tdo1_o(tdo1_o)
);
always @(posedge clkDut)
from <= from + 1;
endmodule
|
/*
* freq_gen_tb.v: Test bench for freq_gen.v
* author: Till Mahlburg
* year: 2019
* organization: Universität Leipzig
* license: ISC
*
*/
`timescale 1 ns / 1 ps
`ifndef WAIT_INTERVAL
`define WAIT_INTERVAL 1000
`endif
`ifndef M_1000
`define M_1000 1000
`endif
`ifndef D
`define D 1
`endif
`ifndef O_1000
`define O_1000 1000
`endif
module freq_gen_tb ();
reg RST;
reg PWRDWN;
reg period_stable;
reg [31:0] ref_period_length_1000;
reg clk;
wire out;
wire [31:0] out_period_length_1000;
/* resets the high counter module used for frequency checks */
wire [31:0] highs_counted;
integer pass_count;
integer fail_count;
/* adjust according to the number of test cases */
localparam total = 6;
freq_gen dut (
.M_1000(`M_1000),
.D(`D),
.O_1000(`O_1000),
.RST(RST),
.PWRDWN(PWRDWN),
.ref_period_1000(ref_period_length_1000),
.clk(clk),
.out(out),
.out_period_length_1000(out_period_length_1000),
.period_stable(period_stable));
high_counter high_counter (
.clk(out),
.rst(~period_stable),
.count(highs_counted));
initial begin
$dumpfile("freq_gen_tb.vcd");
$dumpvars(0, freq_gen_tb);
RST = 0;
PWRDWN = 0;
period_stable = 0;
clk = 0;
ref_period_length_1000 = 20 * 1000;
pass_count = 0;
fail_count = 0;
#10;
RST = 1;
#10;
if (out === 1'b0) begin
$display("PASSED: RST");
pass_count = pass_count + 1;
end else begin
$display("FAILED: RST");
fail_count = fail_count + 1;
end
period_stable = 1;
RST = 0;
#((ref_period_length_1000 / 1000.0) + 11);
if (out === 1'b1) begin
$display("PASSED: rising edge detection");
pass_count = pass_count + 1;
end else begin
$display("FAILED: rising edge detection");
fail_count = fail_count + 1;
end
#(`WAIT_INTERVAL - ((ref_period_length_1000 / 1000.0) + 11));
/* use 1.0 to calculate floating point numbers */
if ($floor(`WAIT_INTERVAL / highs_counted) == $floor((ref_period_length_1000 / 1000.0) * ((`D * (`O_1000 / 1000.0) * 1.0) / (`M_1000 / 1000.0)))) begin
$display("PASSED: ref period = 20");
pass_count = pass_count + 1;
end else begin
$display("FAILED: ref period = 20");
fail_count = fail_count + 1;
end
period_stable = 0;
ref_period_length_1000 = 10 * 1000;
#`WAIT_INTERVAL;
period_stable = 1;
#`WAIT_INTERVAL;
if ($floor(`WAIT_INTERVAL / highs_counted) == $floor((ref_period_length_1000 / 1000.0) * ((`D * (`O_1000 / 1000.0) * 1.0) / (`M_1000 / 1000.0)))) begin
$display("PASSED: ref period = 10");
pass_count = pass_count + 1;
end else begin
$display("FAILED: ref period = 10");
fail_count = fail_count + 1;
end
period_stable = 0;
ref_period_length_1000 = 5600;
#`WAIT_INTERVAL;
period_stable = 1;
#`WAIT_INTERVAL;
if ($floor(`WAIT_INTERVAL / highs_counted) == $floor((ref_period_length_1000 / 1000.0) * ((`D * (`O_1000 / 1000.0) * 1.0) / (`M_1000 / 1000.0)))) begin
$display("PASSED: ref period = 5.6");
pass_count = pass_count + 1;
end else begin
$display("FAILED: ref period = 5.6");
fail_count = fail_count + 1;
end
if ($floor((`WAIT_INTERVAL + (ref_period_length_1000 / 1000.0)) / highs_counted) == $floor(out_period_length_1000 / 1000.0)) begin
$display("PASSED: period length output");
pass_count = pass_count + 1;
end else begin
$display("FAILED: period length output");
fail_count = fail_count + 1;
end
if ((pass_count + fail_count) == total) begin
$display("PASSED: number of test cases");
pass_count = pass_count + 1;
end else begin
$display("FAILED: number of test cases");
fail_count = fail_count + 1;
end
$display("%0d/%0d PASSED", pass_count, (total + 1));
$finish;
end
always #((ref_period_length_1000 / 1000.0) / 2.0) clk <= ~clk;
endmodule
|
/*******************************************************************
date:2016/3/31
designer:ZhaiShaoMin
module name:tb_dc_rep_upload
module function:find out errors in the design unit
********************************************************************/
`timescale 1ns/1ps
module tb_dc_rep_upload();
//input
reg clk;
reg rst;
reg [175:0] dc_flits_rep;
reg v_dc_flits_rep;
reg [3:0] flits_max;
reg en_flits_max;
reg rep_fifo_rdy;
//output
wire [15:0] dc_flit_out;
wire v_dc_flit_out;
wire [1:0] dc_ctrl_out;
wire dc_rep_upload_state;
//instante
dc_rep_upload uut(//input
.clk(clk),
.rst(rst),
.dc_flits_rep(dc_flits_rep),
.v_dc_flits_rep(v_dc_flits_rep),
.flits_max(flits_max),
.en_flits_max(en_flits_max),
.rep_fifo_rdy(rep_fifo_rdy),
//output
.dc_flit_out(dc_flit_out),
.v_dc_flit_out(v_dc_flit_out),
.dc_ctrl_out(dc_ctrl_out),
.dc_rep_upload_state(dc_rep_upload_state)
);
//initial inputs
initial begin
clk=1'b0;
rst=1'b1;
dc_flits_rep=176'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;
v_dc_flits_rep=1'b0;
en_flits_max=1'b0;
flits_max=4'b0000;
rep_fifo_rdy=1'b0;
end
`define clk_step #14;
always #7 clk=~clk;
//////////////////////////////////////////////////////////////////
////////////BEGIN TEST////////////////////////////////////////////
initial begin
`clk_step
rst=1'b0;
`clk_step
////////////////////////////////////////////////////////////////
//////////////1st case:one flit long msg such as C2Cinvrep//////
///this time dc_flits_rep is not ready
dc_flits_rep=176'h2011_2010_2009_2008_2007_2006_2005_2004_2003_2002_2001;
v_dc_flits_rep=1'b0;
en_flits_max=1'b1;
flits_max=4'b0001;
rep_fifo_rdy=1'b1;
`clk_step
///this cycle dc_flits_rep is ready !
dc_flits_rep=176'h2011_2010_2009_2008_2007_2006_2005_2004_2003_2002_2001;
v_dc_flits_rep=1'b1;
en_flits_max=1'b0;
flits_max=4'b0000;
rep_fifo_rdy=1'b1;
`clk_step
///by the end of this cycle ,the upload will be empty for that's a one-flit msg
dc_flits_rep=176'h2016_2015_2014_2013_2012_2011_2010_2009_2008_2007_2006; v_dc_flits_rep=1'b1;
en_flits_max=1'b0;
flits_max=4'b0000;
rep_fifo_rdy=1'b1;
`clk_step
///next six cycles there is no valid msg coming!
v_dc_flits_rep=1'b0;
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
////////////////////////////////////////////////////////////////////////////////
/////////2nd case: 9-flits msg is coming!///////////////////////////////////////
en_flits_max=1'b1;
flits_max=4'b1000;
`clk_step
v_dc_flits_rep=1'b1;
dc_flits_rep=176'hc0de_c1de_c2de_c3de_c4de_c5de_c6de_c7de_c8de_c9de_cade;
`clk_step
v_dc_flits_rep=1'b0;
en_flits_max=1'b0;
//first flit is poped to rep fifo
`clk_step
//second flit is poped to rep fifo
`clk_step
// 3rd flit is poped to rep fifo
`clk_step
///now assume that rep fifo is full
rep_fifo_rdy=1'b0;
`clk_step
///now assume that rep fifo is full
`clk_step
///now assume that rep fifo is full
`clk_step
///now assume that rep fifo is full
`clk_step
///now assume that rep fifo is not full! And 4th flit is poped to rep fifo
`clk_step
rep_fifo_rdy=1'b1;
`clk_step
///5th flit is poped to rep fifo
`clk_step
///6th flit is poped to rep fifo
`clk_step
///7th flit is poped to rep fifo
`clk_step
///now assume rep fifo become full once again!
rep_fifo_rdy=1'b0;
`clk_step
///still full
`clk_step
///still full
`clk_step
///rep fifo is not full now! So the 8th flit is poped to rep fifo
rep_fifo_rdy=1'b1;
`clk_step
/// the last flit is poped to rep fifo!
`clk_step
///dc_rep_upload will be idle
en_flits_max=1'b1;
flits_max=4'b1010;
rep_fifo_rdy=1'b0;
`clk_step
////////////////////////////////////////////////////////////////////////////
//////////////3rd case: 11-flits msg is coming!/////////////////////////////
v_dc_flits_rep=1'b1;
dc_flits_rep=176'h0331_0401_0402_0403_0404_0405_0406_0407_0408_0409_040a;
`clk_step
//due to rep fifo being full,no flit poped to rep fifo
`clk_step
`clk_step
`clk_step
//now rep fifo become not full and first flit is poped to rep fifo
`clk_step
//due to fifo being full ,second flit still sit in dc_rep_upload
`clk_step
//now rep fifo become not full , second flit is poped to rep fifo
`clk_step
//3rd flit to rep fifo
`clk_step
//4th flit to rep fifo
`clk_step
//5th flit to reo fifo
`clk_step
//6th flit ro rep fifo
`clk_step
///// rep fifo become full again!
rep_fifo_rdy=1'b0;
`clk_step
`clk_step
`clk_step
///rep fifo changes to be not full, and 7th flit to rep fifo
rep_fifo_rdy=1'b1;
`clk_step
//8th flit to rep fifo
`clk_step
//9th flit to rep fifo
`clk_step
//10th flit to rep fifo
`clk_step
//11th flit to rep fifo
`clk_step
//////dc_rep_upload become idle!
`clk_step
$stop;
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:22:46 05/08/2015
// Design Name: branch
// Module Name: /media/BELGELER/Workspaces/Xilinx/processor/test_branch.v
// Project Name: processor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: branch
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_branch;
// Inputs
reg branch_d;
reg [3:0] branch_condition_d;
reg Z;
reg N;
reg V;
reg C;
// Outputs
wire PC_source;
// Instantiate the Unit Under Test (UUT)
branch uut (
.branch_d(branch_d),
.branch_condition_d(branch_condition_d),
.Z(Z),
.N(N),
.V(V),
.C(C),
.PC_source(PC_source)
);
initial begin
// Initialize Inputs
branch_d = 0;
branch_condition_d = 0;
Z = 0;
N = 0;
V = 0;
C = 0;
// Wait 100 ns for global reset to finish
//#100;
#1;
branch_condition_d = 4'h1;
branch_d = 1;
#1;
branch_condition_d = 4'h2;
#1;
branch_condition_d = 4'h3;
#1;
C = 1;
branch_condition_d = 4'h8;
#1;
branch_condition_d = 4'ha;
#1;
V = 1;
// Add stimulus here
end
endmodule
|
module testbench();
localparam ways_p = 8;
localparam lg_ways_lp =`BSG_SAFE_CLOG2(ways_p);
logic [ways_p-2:0] lru_li;
logic [lg_ways_lp-1:0] way_id_lo;
bsg_lru_pseudo_tree_encode #(
.ways_p(ways_p)
) DUT (
.lru_i(lru_li)
,.way_id_o(way_id_lo)
);
task test(
input [ways_p-2:0] lru
, input [lg_ways_lp-1:0] expected
);
lru_li = lru;
#10;
assert(expected == way_id_lo) else
$fatal("[BSG_FATAL] expected: %b, actual: %b", expected, way_id_lo);
#10;
endtask
initial begin
// 0
test(7'b000_0000, 3'b000);
test(7'b000_0100, 3'b000);
test(7'b111_0100, 3'b000);
test(7'b101_0100, 3'b000);
// 1
test(7'b000_1000, 3'b001);
test(7'b000_1100, 3'b001);
test(7'b100_1000, 3'b001);
test(7'b110_1000, 3'b001);
// 2
test(7'b000_0010, 3'b010);
test(7'b000_1010, 3'b010);
test(7'b100_1010, 3'b010);
test(7'b110_1010, 3'b010);
// 3
test(7'b001_0010, 3'b011);
test(7'b001_0110, 3'b011);
test(7'b101_0110, 3'b011);
test(7'b111_0110, 3'b011);
// 4
test(7'b000_0001, 3'b100);
test(7'b000_1001, 3'b100);
test(7'b001_1001, 3'b100);
test(7'b101_1001, 3'b100);
// 5
test(7'b010_0001, 3'b101);
test(7'b010_0011, 3'b101);
test(7'b010_1011, 3'b101);
test(7'b011_1011, 3'b101);
// 6
test(7'b000_0101, 3'b110);
test(7'b010_0101, 3'b110);
test(7'b011_0101, 3'b110);
test(7'b011_1101, 3'b110);
// 7
test(7'b100_0101, 3'b111);
test(7'b100_0111, 3'b111);
test(7'b111_1111, 3'b111);
test(7'b101_1111, 3'b111);
$display("[BSG_FINISH] Test Successful!");
$finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 15:45:17 04/03/2016
// Design Name:
// Module Name: contador_AD_YEAR_2dig
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module contador_AD_YEAR_2dig
(
input wire clk,
input wire reset,
input wire [3:0] en_count,
input wire enUP,
input wire enDOWN,
output wire [7:0] data_YEAR
);
localparam N = 7; // Para definir el número de bits del contador (hasta 99->7 bits)
//Declaración de señales
reg [N-1:0] q_act, q_next;
wire [N-1:0] count_data;
reg [3:0] digit1, digit0;
//Descripción del comportamiento
always@(posedge clk, posedge reset)
begin
if(reset)
begin
q_act <= 7'b0;
end
else
begin
q_act <= q_next;
end
end
//Lógica de salida
always@*
begin
if (en_count == 4)
begin
if (enUP)
begin
if (q_act >= 7'd99) q_next = 7'd0;
else q_next = q_act + 7'd1;
end
else if (enDOWN)
begin
if (q_act == 7'd0) q_next = 7'd99;
else q_next = q_act - 7'd1;
end
else q_next = q_act;
end
else q_next = q_act;
end
assign count_data = q_act;
//Decodificación BCD (2 dígitos)
always@*
begin
case(count_data)
7'd0: begin digit1 = 4'b0000; digit0 = 4'b0000; end
7'd1: begin digit1 = 4'b0000; digit0 = 4'b0001; end
7'd2: begin digit1 = 4'b0000; digit0 = 4'b0010; end
7'd3: begin digit1 = 4'b0000; digit0 = 4'b0011; end
7'd4: begin digit1 = 4'b0000; digit0 = 4'b0100; end
7'd5: begin digit1 = 4'b0000; digit0 = 4'b0101; end
7'd6: begin digit1 = 4'b0000; digit0 = 4'b0110; end
7'd7: begin digit1 = 4'b0000; digit0 = 4'b0111; end
7'd8: begin digit1 = 4'b0000; digit0 = 4'b1000; end
7'd9: begin digit1 = 4'b0000; digit0 = 4'b1001; end
7'd10: begin digit1 = 4'b0001; digit0 = 4'b0000; end
7'd11: begin digit1 = 4'b0001; digit0 = 4'b0001; end
7'd12: begin digit1 = 4'b0001; digit0 = 4'b0010; end
7'd13: begin digit1 = 4'b0001; digit0 = 4'b0011; end
7'd14: begin digit1 = 4'b0001; digit0 = 4'b0100; end
7'd15: begin digit1 = 4'b0001; digit0 = 4'b0101; end
7'd16: begin digit1 = 4'b0001; digit0 = 4'b0110; end
7'd17: begin digit1 = 4'b0001; digit0 = 4'b0111; end
7'd18: begin digit1 = 4'b0001; digit0 = 4'b1000; end
7'd19: begin digit1 = 4'b0001; digit0 = 4'b1001; end
7'd20: begin digit1 = 4'b0010; digit0 = 4'b0000; end
7'd21: begin digit1 = 4'b0010; digit0 = 4'b0001; end
7'd22: begin digit1 = 4'b0010; digit0 = 4'b0010; end
7'd23: begin digit1 = 4'b0010; digit0 = 4'b0011; end
7'd24: begin digit1 = 4'b0010; digit0 = 4'b0100; end
7'd25: begin digit1 = 4'b0010; digit0 = 4'b0101; end
7'd26: begin digit1 = 4'b0010; digit0 = 4'b0110; end
7'd27: begin digit1 = 4'b0010; digit0 = 4'b0111; end
7'd28: begin digit1 = 4'b0010; digit0 = 4'b1000; end
7'd29: begin digit1 = 4'b0010; digit0 = 4'b1001; end
7'd30: begin digit1 = 4'b0011; digit0 = 4'b0000; end
7'd31: begin digit1 = 4'b0011; digit0 = 4'b0001; end
7'd32: begin digit1 = 4'b0011; digit0 = 4'b0010; end
7'd33: begin digit1 = 4'b0011; digit0 = 4'b0011; end
7'd34: begin digit1 = 4'b0011; digit0 = 4'b0100; end
7'd35: begin digit1 = 4'b0011; digit0 = 4'b0101; end
7'd36: begin digit1 = 4'b0011; digit0 = 4'b0110; end
7'd37: begin digit1 = 4'b0011; digit0 = 4'b0111; end
7'd38: begin digit1 = 4'b0011; digit0 = 4'b1000; end
7'd39: begin digit1 = 4'b0011; digit0 = 4'b1001; end
7'd40: begin digit1 = 4'b0100; digit0 = 4'b0000; end
7'd41: begin digit1 = 4'b0100; digit0 = 4'b0001; end
7'd42: begin digit1 = 4'b0100; digit0 = 4'b0010; end
7'd43: begin digit1 = 4'b0100; digit0 = 4'b0011; end
7'd44: begin digit1 = 4'b0100; digit0 = 4'b0100; end
7'd45: begin digit1 = 4'b0100; digit0 = 4'b0101; end
7'd46: begin digit1 = 4'b0100; digit0 = 4'b0110; end
7'd47: begin digit1 = 4'b0100; digit0 = 4'b0111; end
7'd48: begin digit1 = 4'b0100; digit0 = 4'b1000; end
7'd49: begin digit1 = 4'b0100; digit0 = 4'b1001; end
7'd50: begin digit1 = 4'b0101; digit0 = 4'b0000; end
7'd51: begin digit1 = 4'b0101; digit0 = 4'b0001; end
7'd52: begin digit1 = 4'b0101; digit0 = 4'b0010; end
7'd53: begin digit1 = 4'b0101; digit0 = 4'b0011; end
7'd54: begin digit1 = 4'b0101; digit0 = 4'b0100; end
7'd55: begin digit1 = 4'b0101; digit0 = 4'b0101; end
7'd56: begin digit1 = 4'b0101; digit0 = 4'b0110; end
7'd57: begin digit1 = 4'b0101; digit0 = 4'b0111; end
7'd58: begin digit1 = 4'b0101; digit0 = 4'b1000; end
7'd59: begin digit1 = 4'b0101; digit0 = 4'b1001; end
7'd60: begin digit1 = 4'b0110; digit0 = 4'b0000; end
7'd61: begin digit1 = 4'b0110; digit0 = 4'b0001; end
7'd62: begin digit1 = 4'b0110; digit0 = 4'b0010; end
7'd63: begin digit1 = 4'b0110; digit0 = 4'b0011; end
7'd64: begin digit1 = 4'b0110; digit0 = 4'b0100; end
7'd65: begin digit1 = 4'b0110; digit0 = 4'b0101; end
7'd66: begin digit1 = 4'b0110; digit0 = 4'b0110; end
7'd67: begin digit1 = 4'b0110; digit0 = 4'b0111; end
7'd68: begin digit1 = 4'b0110; digit0 = 4'b1000; end
7'd69: begin digit1 = 4'b0110; digit0 = 4'b1001; end
7'd70: begin digit1 = 4'b0111; digit0 = 4'b0000; end
7'd71: begin digit1 = 4'b0111; digit0 = 4'b0001; end
7'd72: begin digit1 = 4'b0111; digit0 = 4'b0010; end
7'd73: begin digit1 = 4'b0111; digit0 = 4'b0011; end
7'd74: begin digit1 = 4'b0111; digit0 = 4'b0100; end
7'd75: begin digit1 = 4'b0111; digit0 = 4'b0101; end
7'd76: begin digit1 = 4'b0111; digit0 = 4'b0110; end
7'd77: begin digit1 = 4'b0111; digit0 = 4'b0111; end
7'd78: begin digit1 = 4'b0111; digit0 = 4'b1000; end
7'd79: begin digit1 = 4'b0111; digit0 = 4'b1001; end
7'd80: begin digit1 = 4'b1000; digit0 = 4'b0000; end
7'd81: begin digit1 = 4'b1000; digit0 = 4'b0001; end
7'd82: begin digit1 = 4'b1000; digit0 = 4'b0010; end
7'd83: begin digit1 = 4'b1000; digit0 = 4'b0011; end
7'd84: begin digit1 = 4'b1000; digit0 = 4'b0100; end
7'd85: begin digit1 = 4'b1000; digit0 = 4'b0101; end
7'd86: begin digit1 = 4'b1000; digit0 = 4'b0110; end
7'd87: begin digit1 = 4'b1000; digit0 = 4'b0111; end
7'd88: begin digit1 = 4'b1000; digit0 = 4'b1000; end
7'd89: begin digit1 = 4'b1000; digit0 = 4'b1001; end
7'd90: begin digit1 = 4'b1001; digit0 = 4'b0000; end
7'd91: begin digit1 = 4'b1001; digit0 = 4'b0001; end
7'd92: begin digit1 = 4'b1001; digit0 = 4'b0010; end
7'd93: begin digit1 = 4'b1001; digit0 = 4'b0011; end
7'd94: begin digit1 = 4'b1001; digit0 = 4'b0100; end
7'd95: begin digit1 = 4'b1001; digit0 = 4'b0101; end
7'd96: begin digit1 = 4'b1001; digit0 = 4'b0110; end
7'd97: begin digit1 = 4'b1001; digit0 = 4'b0111; end
7'd98: begin digit1 = 4'b1001; digit0 = 4'b1000; end
7'd99: begin digit1 = 4'b1001; digit0 = 4'b1001; end
default: begin digit1 = 0; digit0 = 0; end
endcase
end
assign data_YEAR = {digit1,digit0};
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Expert(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Mon Oct 17 14:00:22 2016
/////////////////////////////////////////////////////////////
module FSM_Add_Subtract ( clk, rst, rst_FSM, beg_FSM, zero_flag_i,
norm_iteration_i, add_overflow_i, round_i, load_1_o, load_2_o,
load_3_o, load_8_o, A_S_op_o, load_4_o, left_right_o, bit_shift_o,
load_5_o, load_6_o, load_7_o, ctrl_a_o, ctrl_b_o, ctrl_b_load_o,
ctrl_c_o, ctrl_d_o, rst_int, ready );
output [1:0] ctrl_b_o;
input clk, rst, rst_FSM, beg_FSM, zero_flag_i, norm_iteration_i,
add_overflow_i, round_i;
output load_1_o, load_2_o, load_3_o, load_8_o, A_S_op_o, load_4_o,
left_right_o, bit_shift_o, load_5_o, load_6_o, load_7_o, ctrl_a_o,
ctrl_b_load_o, ctrl_c_o, ctrl_d_o, rst_int, ready;
wire n1, n2, n4, ctrl_a_o, n7, n8, n9, n10, n11, n15, n16, n17, n18, n19,
n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33,
n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47,
n48, n49, n50, n51, n52, n53, n54, n55, n56;
wire [3:0] state_reg;
assign ctrl_d_o = ctrl_a_o;
INVX2TS U3 ( .A(rst), .Y(n1) );
DFFRX2TS \state_reg_reg[3] ( .D(n55), .CK(clk), .RN(n1), .Q(state_reg[3]),
.QN(n9) );
DFFRX2TS \state_reg_reg[1] ( .D(n54), .CK(clk), .RN(n1), .Q(state_reg[1]),
.QN(n16) );
DFFRX2TS \state_reg_reg[0] ( .D(n56), .CK(clk), .RN(n1), .Q(state_reg[0]),
.QN(n17) );
DFFRX2TS \state_reg_reg[2] ( .D(n53), .CK(clk), .RN(n1), .Q(state_reg[2]),
.QN(n15) );
NAND3X1TS U4 ( .A(state_reg[1]), .B(n49), .C(state_reg[3]), .Y(n20) );
NOR3X1TS U5 ( .A(load_2_o), .B(load_1_o), .C(load_7_o), .Y(n31) );
NOR2X1TS U6 ( .A(n16), .B(state_reg[3]), .Y(n51) );
AOI21X1TS U7 ( .A0(load_2_o), .A1(zero_flag_i), .B0(load_7_o), .Y(n22) );
NOR3BX1TS U8 ( .AN(n45), .B(n17), .C(state_reg[1]), .Y(n25) );
NAND3X1TS U9 ( .A(n16), .B(n9), .C(n49), .Y(n41) );
NAND3X1TS U10 ( .A(n16), .B(n9), .C(n50), .Y(n32) );
NAND3X1TS U11 ( .A(state_reg[1]), .B(n17), .C(n45), .Y(n29) );
NAND2X1TS U12 ( .A(n43), .B(n27), .Y(load_5_o) );
NOR2BX1TS U13 ( .AN(ctrl_b_load_o), .B(add_overflow_i), .Y(ctrl_b_o[0]) );
OA21XLTS U14 ( .A0(n36), .A1(load_8_o), .B0(add_overflow_i), .Y(bit_shift_o)
);
INVX2TS U15 ( .A(n43), .Y(ctrl_c_o) );
INVX2TS U16 ( .A(n20), .Y(ready) );
OAI21X1TS U17 ( .A0(n32), .A1(n18), .B0(n24), .Y(n36) );
INVX2TS U18 ( .A(n40), .Y(load_2_o) );
INVX2TS U19 ( .A(n22), .Y(n10) );
INVX2TS U20 ( .A(n32), .Y(n8) );
NAND2X1TS U21 ( .A(n51), .B(n49), .Y(n43) );
NAND2X1TS U22 ( .A(n50), .B(n51), .Y(n27) );
INVX2TS U23 ( .A(n41), .Y(n4) );
INVX2TS U24 ( .A(n29), .Y(n7) );
INVX2TS U25 ( .A(n39), .Y(rst_int) );
INVX2TS U26 ( .A(n44), .Y(load_6_o) );
NOR4XLTS U27 ( .A(n48), .B(ctrl_b_load_o), .C(load_5_o), .D(load_4_o), .Y(
n47) );
NAND2X1TS U28 ( .A(n32), .B(n24), .Y(load_4_o) );
NAND3X1TS U29 ( .A(n20), .B(n39), .C(n42), .Y(n48) );
AOI211X1TS U30 ( .A0(n4), .A1(n18), .B0(n50), .C0(n25), .Y(n46) );
NAND2X1TS U31 ( .A(n44), .B(n29), .Y(ctrl_b_load_o) );
NAND4X1TS U32 ( .A(add_overflow_i), .B(n31), .C(n46), .D(n47), .Y(A_S_op_o)
);
OAI21X1TS U33 ( .A0(n18), .A1(n41), .B0(n33), .Y(load_8_o) );
OAI2BB1X1TS U34 ( .A0N(load_6_o), .A1N(add_overflow_i), .B0(n29), .Y(
ctrl_b_o[1]) );
AOI211X1TS U35 ( .A0(n41), .A1(n32), .B0(n18), .C0(add_overflow_i), .Y(
left_right_o) );
INVX2TS U36 ( .A(n28), .Y(ctrl_a_o) );
OAI22X1TS U37 ( .A0(beg_FSM), .A1(n39), .B0(rst_FSM), .B1(n20), .Y(n26) );
NAND4BX1TS U38 ( .AN(load_5_o), .B(n33), .C(n34), .D(n35), .Y(n55) );
AOI21X1TS U39 ( .A0(n25), .A1(n19), .B0(n7), .Y(n34) );
AOI211X1TS U40 ( .A0(state_reg[3]), .A1(n26), .B0(n36), .C0(n10), .Y(n35) );
INVX2TS U41 ( .A(round_i), .Y(n19) );
NAND4X1TS U42 ( .A(n27), .B(n28), .C(n29), .D(n30), .Y(n54) );
AOI221X1TS U43 ( .A0(n8), .A1(n18), .B0(state_reg[1]), .B1(n26), .C0(n11),
.Y(n30) );
INVX2TS U44 ( .A(n31), .Y(n11) );
NOR2X1TS U45 ( .A(n15), .B(state_reg[0]), .Y(n49) );
NAND3X1TS U46 ( .A(n21), .B(n22), .C(n23), .Y(n53) );
NOR4BX1TS U47 ( .AN(n24), .B(load_3_o), .C(load_6_o), .D(n25), .Y(n23) );
AOI22X1TS U48 ( .A0(n8), .A1(n18), .B0(state_reg[2]), .B1(n26), .Y(n21) );
NAND3X1TS U49 ( .A(n41), .B(n42), .C(n33), .Y(load_3_o) );
AOI31X1TS U50 ( .A0(n37), .A1(n2), .A2(n38), .B0(n26), .Y(n56) );
INVX2TS U51 ( .A(n36), .Y(n2) );
AOI2BB1X1TS U52 ( .A0N(n40), .A1N(zero_flag_i), .B0(n7), .Y(n37) );
NOR3X1TS U53 ( .A(n25), .B(rst_int), .C(n4), .Y(n38) );
AND2X2TS U54 ( .A(n52), .B(state_reg[0]), .Y(load_1_o) );
NOR2X1TS U55 ( .A(n9), .B(state_reg[2]), .Y(n45) );
NOR2X1TS U56 ( .A(n17), .B(n15), .Y(n50) );
NOR3X1TS U57 ( .A(state_reg[2]), .B(state_reg[3]), .C(state_reg[1]), .Y(n52)
);
NAND3X1TS U58 ( .A(n51), .B(n15), .C(state_reg[0]), .Y(n42) );
NAND2X1TS U59 ( .A(n52), .B(n17), .Y(n39) );
NAND3X1TS U60 ( .A(n17), .B(n15), .C(n51), .Y(n40) );
NAND3X1TS U61 ( .A(n49), .B(n16), .C(state_reg[3]), .Y(n24) );
AND3X2TS U62 ( .A(n50), .B(state_reg[3]), .C(n16), .Y(load_7_o) );
NAND3X1TS U63 ( .A(n17), .B(n16), .C(n45), .Y(n44) );
NAND3X1TS U64 ( .A(state_reg[0]), .B(state_reg[1]), .C(n45), .Y(n33) );
NAND2X1TS U65 ( .A(round_i), .B(n25), .Y(n28) );
INVX2TS U66 ( .A(norm_iteration_i), .Y(n18) );
endmodule
module FPU_Add_Subtract_Function_W32_EW8_SW23_SWR26_EWR5_FSM_Add_Subtract (
clk, rst, beg_FSM, ack_FSM, Data_X, Data_Y, add_subt, r_mode,
overflow_flag, underflow_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
input [1:0] r_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM, add_subt;
output overflow_flag, underflow_flag, ready;
FSM_Add_Subtract FS_Module ( .clk(clk), .rst(rst), .rst_FSM(ack_FSM),
.beg_FSM(beg_FSM), .zero_flag_i(1'b0), .norm_iteration_i(1'b0),
.add_overflow_i(1'b0), .round_i(1'b0), .ready(ready) );
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of rs_cfg_fe1
//
// Generated
// by: lutscher
// on: Tue Jun 23 11:51:21 2009
// cmd: /home/lutscher/work/MIX/mix_1.pl rs_test.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author$
// $Id$
// $Date$
// $Log$
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.109 2008/04/01 12:48:34 wig Exp
//
// Generator: mix_1.pl Revision: 1.3 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of rs_cfg_fe1
//
// No user `defines in this module
`define tie0_1_c 1'b0
module rs_cfg_fe1
//
// Generated Module rs_cfg_fe1_i
//
(
input wire clk_f20_i,
input wire res_f20_n_i,
input wire [13:0] addr_i,
input wire [31:0] wr_data_i,
input wire rd_wr_i,
output wire [31:0] rd_data_o,
output wire rd_err_o,
output wire trans_done_o,
input wire trans_start_1_i,
output wire [2:0] cvbsdetect_par_o,
input wire [2:0] cvbsdetect_set_p_i,
output reg cvbsdetect_trg_p_o,
input wire [7:0] sha_r_test_par_i,
output wire sha_r_test_trg_p_o,
input wire usr_r_test_par_i,
input wire usr_r_test_trans_done_p_i,
output reg usr_r_test_rd_p_o,
input wire ycdetect_par_i,
output wire [3:0] mvstart_par_o,
output reg [3:0] mvstop_par_o,
input wire [1:0] usr_ali_par_i,
input wire usr_ali_trans_done_p_i,
output reg usr_ali_rd_p_o,
output wire [3:0] usr_rw_test_par_o,
input wire [3:0] usr_rw_test_in_par_i,
input wire usr_rw_test_trans_done_p_i,
output reg usr_rw_test_rd_p_o,
output reg usr_rw_test_wr_p_o,
output reg [31:0] sha_rw2_par_o,
output wire [15:0] wd_16_test_par_o,
output wire [7:0] wd_16_test2_par_o,
output wire wd_16_test2_trg_p_o,
input wire upd_rw_en_i,
input wire upd_rw_force_i,
input wire upd_rw_i,
input wire upd_r_en_i,
input wire upd_r_force_i,
input wire upd_r_i
);
// Module parameters:
parameter sync = 0;
parameter P__MVSTOP = -1;
parameter P__CVBSDETECT = -1;
parameter P__WD_16_TEST2 = -1;
parameter P__WD_16_TEST = -1;
parameter P__SHA_RW2 = -1;
parameter P__MVSTART = -1;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire clk_f20; // __W_PORT_SIGNAL_MAP_REQ
wire res_f20_n; // __W_PORT_SIGNAL_MAP_REQ
wire tie0_1;
wire u10_sync_generic_i_int_upd_r_arm_p;
wire u5_sync_generic_i_trans_start_p;
wire u6_sync_rst_i_int_rst_n;
wire u7_sync_generic_i_int_upd_rw_p;
wire u8_sync_generic_i_int_upd_rw_arm_p;
wire u9_sync_generic_i_int_upd_r_p;
wire upd_r; // __W_PORT_SIGNAL_MAP_REQ
wire upd_r_en; // __W_PORT_SIGNAL_MAP_REQ
wire upd_rw; // __W_PORT_SIGNAL_MAP_REQ
wire upd_rw_en; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign clk_f20 = clk_f20_i; // __I_I_BIT_PORT
assign res_f20_n = res_f20_n_i; // __I_I_BIT_PORT
assign tie0_1 = `tie0_1_c;
assign upd_r = upd_r_i; // __I_I_BIT_PORT
assign upd_r_en = upd_r_en_i; // __I_I_BIT_PORT
assign upd_rw = upd_rw_i; // __I_I_BIT_PORT
assign upd_rw_en = upd_rw_en_i; // __I_I_BIT_PORT
/* ------------------------------------------------------------
Generator information:
used package Micronas::Reg is version 1.88
this package RegViews.pm is version 1.93
use with RTL libraries (this release or higher):
ip_ocp/0002/ip_ocp_016_21Jan2009
ip_sync/0001/ip_sync_006_23jan2008
------------------------------------------------------------ */
/*
local definitions
*/
`define REG_00_OFFS 0 // reg_0x0
`define REG_04_OFFS 1 // reg_0x4
`define REG_08_OFFS 2 // reg_0x8
`define REG_0C_OFFS 3 // reg_0xC
`define REG_10_OFFS 4 // reg_0x10
`define REG_14_OFFS 5 // reg_0x14
`define REG_18_OFFS 6 // reg_0x18
`define REG_1C_OFFS 7 // reg_0x1C
`define REG_20_OFFS 8 // reg_0x20
`define REG_28_OFFS 10 // reg_0x28
/*
local wire or register declarations
*/
reg [31:0] REG_00;
reg [31:0] REG_04;
reg [31:0] REG_08;
reg [7:0] sha_r_test_shdw;
reg [31:0] REG_0C;
wire [3:0] mvstop_shdw;
reg [31:0] REG_10;
reg [31:0] REG_14;
wire [31:0] sha_rw2_shdw;
reg [31:0] REG_18;
reg [31:0] REG_1C;
reg int_REG_1C_trg_p;
reg [31:0] REG_20;
reg [31:0] REG_28;
reg int_upd_rw;
reg int_upd_rw_en;
reg int_upd_r;
reg int_upd_r_en;
wire wr_p;
wire wr_done_p;
wire rd_p;
wire rd_done_p;
wire [3:0] iaddr;
wire addr_overshoot;
wire trans_done_p;
reg ts_del_p;
reg int_trans_done;
reg fwd_txn;
wire [2:0] fwd_decode_vec;
wire fwd_rd_done_p;
wire fwd_wr_done_p;
reg [31:0] mux_rd_data;
reg mux_rd_err;
/*
local wire and output assignments
*/
assign cvbsdetect_par_o[2:0] = cond_slice(P__CVBSDETECT, REG_04[2:0]);
assign mvstart_par_o[3:0] = cond_slice(P__MVSTART, REG_0C[3:0]);
assign mvstop_shdw[3:0] = cond_slice(P__MVSTOP, REG_0C[7:4]);
assign sha_rw2_shdw[31:0] = cond_slice(P__SHA_RW2, REG_14);
assign wd_16_test_par_o[15:0] = cond_slice(P__WD_16_TEST, REG_18[15:0]);
assign wd_16_test2_par_o[7:0] = cond_slice(P__WD_16_TEST2, REG_1C[7:0]);
assign wd_16_test2_trg_p_o = int_REG_1C_trg_p;
assign sha_r_test_trg_p_o = int_upd_r;
assign usr_rw_test_par_o[3:0] = wr_data_i[14:11];
// clip address to decoded range
assign iaddr = addr_i[5:2];
assign addr_overshoot = |addr_i[13:6];
/*
generate transaction-handling signals
*/
assign trans_done_p = rd_done_p | wr_done_p;
// write txn start pulse
assign
// synopsys translate_off
#0.1
// synopsys translate_on
wr_p = ~rd_wr_i & u5_sync_generic_i_trans_start_p;
// read done pulse
assign rd_done_p = rd_p;
assign fwd_rd_done_p = usr_r_test_trans_done_p_i | usr_rw_test_trans_done_p_i | usr_ali_trans_done_p_i;
assign fwd_wr_done_p = usr_rw_test_trans_done_p_i;
assign rd_p = rd_wr_i & ((ts_del_p & ~fwd_txn) | (fwd_rd_done_p & fwd_txn)); // read txn start pulse
assign wr_done_p = ~rd_wr_i & ((ts_del_p & ~fwd_txn) | (fwd_wr_done_p & fwd_txn)); // write done pulse
always @(posedge clk_f20_i or negedge u6_sync_rst_i_int_rst_n) begin
if (~u6_sync_rst_i_int_rst_n) begin
int_trans_done <= 0;
ts_del_p <= 0;
end
else begin
ts_del_p <= u5_sync_generic_i_trans_start_p;
if (trans_done_p)
int_trans_done <= ~int_trans_done;
end
end
assign trans_done_o = int_trans_done;
/*
helper function for conditional FFs
*/
// msd parse off
function [31:0] cond_slice(input integer enable, input [31:0] vec);
begin
cond_slice = (enable < 0) ? vec : enable;
end
endfunction
// msd parse on
/*
write process
*/
always @(posedge clk_f20_i or negedge u6_sync_rst_i_int_rst_n) begin
if (~u6_sync_rst_i_int_rst_n) begin
REG_0C[3:0] <= 'h7;
REG_0C[7:4] <= 'hc;
REG_14 <= 'h0;
REG_18[15:0] <= 'ha;
REG_1C[7:0] <= 'hff;
end
else begin
if (wr_p)
case (iaddr)
`REG_0C_OFFS: begin
REG_0C[3:0] <= wr_data_i[3:0];
REG_0C[7:4] <= wr_data_i[7:4];
end
`REG_14_OFFS: begin
REG_14 <= wr_data_i;
end
`REG_18_OFFS: begin
REG_18[15:0] <= wr_data_i[15:0];
end
`REG_1C_OFFS: begin
REG_1C[7:0] <= wr_data_i[7:0];
end
default: ;
endcase
end
end
/*
write trigger process
*/
always @(posedge clk_f20_i or negedge u6_sync_rst_i_int_rst_n) begin
if (~u6_sync_rst_i_int_rst_n) begin
int_REG_1C_trg_p <= 0;
end
else begin
int_REG_1C_trg_p <= 0;
case (iaddr)
`REG_1C_OFFS: int_REG_1C_trg_p <= wr_p;
default: ;
endcase
end
end
/*
write process for status registers
*/
always @(posedge clk_f20_i or negedge u6_sync_rst_i_int_rst_n) begin
if (~u6_sync_rst_i_int_rst_n) begin
REG_04[2:0] <= 'h0;
cvbsdetect_trg_p_o <= 0;
end
else begin
if (cvbsdetect_set_p_i[0])
REG_04[0] <= 1;
else if (wr_p && iaddr == `REG_04_OFFS) begin
REG_04[0] <= REG_04[0] & ~wr_data_i[0];
end
if (wr_p && iaddr == `REG_04_OFFS) begin // write trigger for address REG_04_OFFS
cvbsdetect_trg_p_o <= 1;
end
else begin
cvbsdetect_trg_p_o <= 0;
end
if (cvbsdetect_set_p_i[1])
REG_04[1] <= 1;
else if (wr_p && iaddr == `REG_04_OFFS) begin
REG_04[1] <= REG_04[1] & ~wr_data_i[1];
end
if (cvbsdetect_set_p_i[2])
REG_04[2] <= 1;
else if (wr_p && iaddr == `REG_04_OFFS) begin
REG_04[2] <= REG_04[2] & ~wr_data_i[2];
end
end
end
/*
txn forwarding process
*/
// decode addresses of USR registers and read/write
assign fwd_decode_vec = {(iaddr == `REG_08_OFFS) & rd_wr_i, (iaddr == `REG_0C_OFFS) & rd_wr_i, (iaddr == `REG_10_OFFS)};
always @(posedge clk_f20_i or negedge u6_sync_rst_i_int_rst_n) begin
if (~u6_sync_rst_i_int_rst_n) begin
fwd_txn <= 0;
usr_r_test_rd_p_o <= 0;
usr_ali_rd_p_o <= 0;
usr_rw_test_rd_p_o <= 0;
usr_rw_test_wr_p_o <= 0;
end
else begin
usr_r_test_rd_p_o <= 0;
usr_ali_rd_p_o <= 0;
usr_rw_test_rd_p_o <= 0;
usr_rw_test_wr_p_o <= 0;
if (u5_sync_generic_i_trans_start_p) begin
fwd_txn <= |fwd_decode_vec; // set flag for forwarded txn
usr_r_test_rd_p_o <= fwd_decode_vec[2] & rd_wr_i;
usr_ali_rd_p_o <= fwd_decode_vec[1] & rd_wr_i;
usr_rw_test_rd_p_o <= fwd_decode_vec[0] & rd_wr_i;
usr_rw_test_wr_p_o <= fwd_decode_vec[0] & ~rd_wr_i;
end
else if (trans_done_p)
fwd_txn <= 0; // reset flag for forwarded transaction
end
end
/*
shadowing for update signal 'upd_rw'
*/
// generate internal update signal
always @(posedge clk_f20_i or negedge u6_sync_rst_i_int_rst_n) begin
if (~u6_sync_rst_i_int_rst_n) begin
int_upd_rw <= 1;
int_upd_rw_en <= 0;
end
else begin
int_upd_rw <= (u7_sync_generic_i_int_upd_rw_p & int_upd_rw_en) | upd_rw_force_i;
if (u8_sync_generic_i_int_upd_rw_arm_p)
int_upd_rw_en <= 1; // arm enable signal
else if(u7_sync_generic_i_int_upd_rw_p)
int_upd_rw_en <= 0; // reset enable signal after update-event
end
end
// shadow process
always @(posedge clk_f20_i or negedge u6_sync_rst_i_int_rst_n) begin
if (~u6_sync_rst_i_int_rst_n) begin
mvstop_par_o <= 'hc;
sha_rw2_par_o <= 'h0;
end
else begin
if (int_upd_rw) begin
mvstop_par_o <= mvstop_shdw;
sha_rw2_par_o <= sha_rw2_shdw;
end
end
end
/*
shadowing for update signal 'upd_r'
*/
// generate internal update signal
always @(posedge clk_f20_i or negedge u6_sync_rst_i_int_rst_n) begin
if (~u6_sync_rst_i_int_rst_n) begin
int_upd_r <= 1;
int_upd_r_en <= 0;
end
else begin
int_upd_r <= (u9_sync_generic_i_int_upd_r_p & int_upd_r_en) | upd_r_force_i;
if (u10_sync_generic_i_int_upd_r_arm_p)
int_upd_r_en <= 1; // arm enable signal
else if(u9_sync_generic_i_int_upd_r_p)
int_upd_r_en <= 0; // reset enable signal after update-event
end
end
// shadow process
always @(posedge clk_f20_i or negedge u6_sync_rst_i_int_rst_n) begin
if (~u6_sync_rst_i_int_rst_n) begin
sha_r_test_shdw <= 'h0;
end
else begin
if (int_upd_r) begin
sha_r_test_shdw <= sha_r_test_par_i;
end
end
end
/*
read logic and mux process
*/
assign rd_data_o = mux_rd_data;
assign rd_err_o = mux_rd_err | addr_overshoot;
always @( REG_04 or REG_0C or REG_18 or iaddr or mvstop_shdw or sha_r_test_shdw or sha_rw2_shdw or usr_ali_par_i or usr_r_test_par_i or usr_rw_test_in_par_i or ycdetect_par_i) begin
mux_rd_err <= 0;
mux_rd_data <= 0;
case (iaddr)
`REG_04_OFFS : begin
mux_rd_data[2:0] <= cond_slice(P__CVBSDETECT, REG_04[2:0]);
end
`REG_08_OFFS : begin
mux_rd_data[10:3] <= sha_r_test_shdw;
mux_rd_data[2] <= usr_r_test_par_i;
mux_rd_data[1] <= ycdetect_par_i;
end
`REG_0C_OFFS : begin
mux_rd_data[3:0] <= cond_slice(P__MVSTART, REG_0C[3:0]);
mux_rd_data[7:4] <= mvstop_shdw;
mux_rd_data[9:8] <= usr_ali_par_i;
end
`REG_10_OFFS : begin
mux_rd_data[14:11] <= usr_rw_test_in_par_i;
end
`REG_14_OFFS : begin
mux_rd_data <= sha_rw2_shdw;
end
`REG_18_OFFS : begin
mux_rd_data[15:0] <= cond_slice(P__WD_16_TEST, REG_18[15:0]);
end
default: begin
mux_rd_err <= 1; // no decode
end
endcase
end
/*
checking code
*/
`ifdef ASSERT_ON
// msd parse off
property p_pos_pulse_check (sig); // check for positive pulse
@(posedge clk_f20_i) disable iff (~u6_sync_rst_i_int_rst_n)
sig |=> ~sig;
endproperty
assert_cvbsdetect_set_p_i0_is_a_pulse: assert property(p_pos_pulse_check(cvbsdetect_set_p_i[0]));
assert_cvbsdetect_set_p_i1_is_a_pulse: assert property(p_pos_pulse_check(cvbsdetect_set_p_i[1]));
assert_cvbsdetect_set_p_i2_is_a_pulse: assert property(p_pos_pulse_check(cvbsdetect_set_p_i[2]));
assert_usr_r_test_trans_done_p_i_is_a_pulse: assert property(p_pos_pulse_check(usr_r_test_trans_done_p_i));
assert_usr_ali_trans_done_p_i_is_a_pulse: assert property(p_pos_pulse_check(usr_ali_trans_done_p_i));
assert_usr_rw_test_trans_done_p_i_is_a_pulse: assert property(p_pos_pulse_check(usr_rw_test_trans_done_p_i));
// all acks for forwarded txns
wire [2:0] fwd_done_vec;
assign fwd_done_vec = {usr_r_test_trans_done_p_i, usr_rw_test_trans_done_p_i, usr_ali_trans_done_p_i};
assert_fwd_done_onehot: assert property
(
@(posedge clk_f20_i) disable iff (~u6_sync_rst_i_int_rst_n)
fwd_done_vec != 0 |-> onehot(fwd_done_vec)
);
assert_fwd_done_only_when_fwd_txn: assert property
(
@(posedge clk_f20_i) disable iff (~u6_sync_rst_i_int_rst_n)
fwd_done_vec != 0 |-> fwd_txn
);
function onehot (input [2:0] vec);
integer i,j;
begin
j = 0;
for (i=0; i<3; i=i+1) j = j + vec[i] ? 1 : 0;
onehot = (j==1) ? 1 : 0;
end
endfunction
// msd parse on
`endif
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for u10_sync_generic_i
sync_generic #(
.act(1),
.kind(3),
.rstact(0),
.rstval(0),
.sync(1)
) u10_sync_generic_i ( // Synchronizer for update-enable signal upd_r_en
.clk_r(clk_f20),
.clk_s(tie0_1),
.rcv_o(u10_sync_generic_i_int_upd_r_arm_p),
.rst_r(res_f20_n),
.rst_s(tie0_1),
.snd_i(upd_r_en)
);
// End of Generated Instance Port Map for u10_sync_generic_i
// Generated Instance Port Map for u5_sync_generic_i
sync_generic #(
.act(1),
.kind(2),
.rstact(0),
.rstval(0),
.sync(sync)
) u5_sync_generic_i ( // Synchronizer for trans_start signal
.clk_r(clk_f20),
.clk_s(tie0_1),
.rcv_o(u5_sync_generic_i_trans_start_p),
.rst_r(res_f20_n),
.rst_s(tie0_1),
.snd_i(trans_start_1_i) // __I_USE_PORT trans_start_1_i for signal trans_start_1
);
// End of Generated Instance Port Map for u5_sync_generic_i
// Generated Instance Port Map for u6_sync_rst_i
sync_rst #(
.act(0),
.sync(0)
) u6_sync_rst_i ( // Reset synchronizer (in bypass-mode)
.clk_r(clk_f20),
.rst_i(res_f20_n),
.rst_o(u6_sync_rst_i_int_rst_n),
.test_i(tie0_1)
);
// End of Generated Instance Port Map for u6_sync_rst_i
// Generated Instance Port Map for u7_sync_generic_i
sync_generic #(
.act(1),
.kind(3),
.rstact(0),
.rstval(0),
.sync(1)
) u7_sync_generic_i ( // Synchronizer for update-signal upd_rw
.clk_r(clk_f20),
.clk_s(tie0_1),
.rcv_o(u7_sync_generic_i_int_upd_rw_p),
.rst_r(res_f20_n),
.rst_s(tie0_1),
.snd_i(upd_rw)
);
// End of Generated Instance Port Map for u7_sync_generic_i
// Generated Instance Port Map for u8_sync_generic_i
sync_generic #(
.act(1),
.kind(3),
.rstact(0),
.rstval(0),
.sync(1)
) u8_sync_generic_i ( // Synchronizer for update-enable signal upd_rw_en
.clk_r(clk_f20),
.clk_s(tie0_1),
.rcv_o(u8_sync_generic_i_int_upd_rw_arm_p),
.rst_r(res_f20_n),
.rst_s(tie0_1),
.snd_i(upd_rw_en)
);
// End of Generated Instance Port Map for u8_sync_generic_i
// Generated Instance Port Map for u9_sync_generic_i
sync_generic #(
.act(1),
.kind(3),
.rstact(0),
.rstval(0),
.sync(1)
) u9_sync_generic_i ( // Synchronizer for update-signal upd_r
.clk_r(clk_f20),
.clk_s(tie0_1),
.rcv_o(u9_sync_generic_i_int_upd_r_p),
.rst_r(res_f20_n),
.rst_s(tie0_1),
.snd_i(upd_r)
);
// End of Generated Instance Port Map for u9_sync_generic_i
endmodule
//
// End of Generated Module rtl of rs_cfg_fe1
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A211OI_TB_V
`define SKY130_FD_SC_MS__A211OI_TB_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a211oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 C1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 C1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 C1 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 C1 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_ms__a211oi dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A211OI_TB_V
|
//=============================================================
//
// Copyright (c) 2017 Simon Southwell. All rights reserved.
//
// Date: 30th May 2017
//
// This code is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// The code is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this code. If not, see <http://www.gnu.org/licenses/>.
//
// $Id: sram.v,v 1.2 2017/08/28 10:33:37 simon Exp $
// $Source: /home/simon/CVS/src/cpu/mico32/HDL/test/verilog/sram.v,v $
//
//=============================================================
//
// Simple model of a 512KB SRAM memory (256K x 16).
//
//=============================================================
`include "test_defs.vh"
// SRAM 512KB
`define MEMBYTEADDRBITS 19
`define MEMSIZEBYTES (1 << `MEMBYTEADDRBITS)
module sram (
inout [15:0] SRAM_DQ,
input [17:0] SRAM_ADDR,
input SRAM_UB_N,
input SRAM_LB_N,
input SRAM_WE_N,
input SRAM_CE_N,
input SRAM_OE_N
);
reg [7:0] mem[`MEMSIZEBYTES-1:0];
wire [`MEMBYTEADDRBITS-1:0] byte_addr0 = {SRAM_ADDR, 1'b0};
wire [`MEMBYTEADDRBITS-1:0] byte_addr1 = {SRAM_ADDR, 1'b1};
wire sram_read = ~SRAM_CE_N & ~SRAM_OE_N;
// DQ tristate control. Only drive if chip selected and output enable active.
assign SRAM_DQ = {(~sram_read | SRAM_UB_N) ? 8'hzz : mem[byte_addr1],
(~sram_read | SRAM_LB_N) ? 8'hzz : mem[byte_addr0]};
always @(*)
begin
// Write to memory if chip selected, WE active and one or more
// byte enables active.
if (~SRAM_CE_N & ~SRAM_WE_N)
begin
if (~SRAM_LB_N)
mem[byte_addr0] = SRAM_DQ [7:0];
if (~SRAM_UB_N)
mem[byte_addr1] = SRAM_DQ [15:8];
end
end
endmodule |
//****************************************************************************************************
//*----------------Copyright (c) 2016 C-L-G.FPGA1988.Roger Wang. All rights reserved------------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : symmetric_mem_core.v
//Project Name : azpr_soc
//Description : the symmetric_mem_core.
//Github Address : https://github.com/C-L-G/gt0000/trunk/ic/digital/rtl/symmetric_mem_core.v
//License : CPL
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 2016-12-05 17:00(1th Fri,July,2016)
//First Author : Roger Wang
//Modify Date : 2016-12-05 14:20(1th Sun,July,2016)
//Last Author : Roger Wang
//Version Number : 002
//Last Commit : 2016-12-05 14:30(1th Sun,July,2016)
//****************************************************************************************************
//Change History(latest change first)
//yyyy.mm.dd - Author - Your log of change
//****************************************************************************************************
//2016.12.05 - Roger Wang - The initial version.
//****************************************************************************************************
`timescale 1ns / 1ps
module symmetric_mem_core #(
parameter RAM_WIDTH = 16,
parameter RAM_ADDR_BITS = 5
)(
input wire clockA,
input wire clockB,
input wire write_enableA,
input wire write_enableB,
input wire [RAM_ADDR_BITS-1:0] addressA,
input wire [RAM_ADDR_BITS-1:0] addressB,
input wire [RAM_WIDTH-1:0] input_dataA,
input wire [RAM_WIDTH-1:0] input_dataB,
output reg [RAM_WIDTH-1:0] output_dataA,
output reg [RAM_WIDTH-1:0] output_dataB
);
//************************************************************************************************
// 1.Parameter and constant define
//************************************************************************************************
`define SIM
//************************************************************************************************
// 2.input and output declaration
//************************************************************************************************
// (* RAM_STYLE="{AUTO | BLOCK | BLOCK_POWER1 | BLOCK_POWER2}" *)
(* RAM_STYLE="BLOCK" *)
reg [RAM_WIDTH-1:0] sym_ram [(2**RAM_ADDR_BITS)-1:0];
wire enableA;
wire enableB;
integer begin_address = 0;
integer end_address = 2**RAM_ADDR_BITS)-1;
//************************************************************************************************
// 3.Register and wire declaration
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 3.1 the clk wire signal
//------------------------------------------------------------------------------------------------
assign enableA = 1'b1;
assign enableB = 1'b1;
// The forllowing code is only necessary if you wish to initialize the RAM
// contents via an external file (use $readmemb for binary data)
`ifdef SIM
integer i;
initial begin
for(i=0;i<2**RAM_ADDR_BITS;i=i+1)
sym_ram[i] = 'd0;
end
`else
initial
$readmemh("data_file_name", sym_ram, begin_address, end_address);
`endif
always @(posedge clockA)
if (enableA) begin
if (write_enableA)
sym_ram[addressA] <= input_dataA;
output_dataA <= sym_ram[addressA];
end
always @(posedge clockB)
if (enableB) begin
if (write_enableB)
sym_ram[addressB] <= input_dataB;
output_dataB <= sym_ram[addressB];
end
endmodule
//****************************************************************************************************
//End of Module
//**************************************************************************************************** |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVPWRVGND_FUNCTIONAL_V
`define SKY130_FD_SC_LP__TAPVPWRVGND_FUNCTIONAL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__tapvpwrvgnd ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVPWRVGND_FUNCTIONAL_V |
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * CNRS-Ecole Polytechnique-INRIA Futurs-Universite Paris Sud *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(* Typeclass-based relations, tactics and standard instances.
This is the basic theory needed to formalize morphisms and setoids.
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - UniversitÃcopyright Paris Sud
91405 Orsay, France *)
(* $Id: RelationClasses.v 12187 2009-06-13 19:36:59Z msozeau $ *)
Require Export Coq.Classes.Init.
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Require Import Coq.Relations.Relation_Definitions.
(** We allow to unfold the [relation] definition while doing morphism search. *)
Notation inverse R := (flip (R:relation _) : relation _).
Definition complement {A} (R : relation A) : relation A := fun x y => R x y -> False.
(** Opaque for proof-search. *)
Typeclasses Opaque complement.
(** These are convertible. *)
Lemma complement_inverse : forall A (R : relation A), complement (inverse R) = inverse (complement R).
Proof. reflexivity. Qed.
(** We rebind relations in separate classes to be able to overload each proof. *)
Set Implicit Arguments.
Unset Strict Implicit.
Class Reflexive {A} (R : relation A) :=
reflexivity : forall x, R x x.
Class Irreflexive {A} (R : relation A) :=
irreflexivity :> Reflexive (complement R).
Class Symmetric {A} (R : relation A) :=
symmetry : forall x y, R x y -> R y x.
Class Asymmetric {A} (R : relation A) :=
asymmetry : forall x y, R x y -> R y x -> False.
Class Transitive {A} (R : relation A) :=
transitivity : forall x y z, R x y -> R y z -> R x z.
Hint Resolve @irreflexivity : ord.
Unset Implicit Arguments.
(** A HintDb for relations. *)
Ltac solve_relation :=
match goal with
| [ |- ?R ?x ?x ] => reflexivity
| [ H : ?R ?x ?y |- ?R ?y ?x ] => symmetry ; exact H
end.
Hint Extern 4 => solve_relation : relations.
(** We can already dualize all these properties. *)
Program Instance flip_Reflexive `(Reflexive A R) : Reflexive (flip R) :=
reflexivity (R:=R).
Program Instance flip_Irreflexive `(Irreflexive A R) : Irreflexive (flip R) :=
irreflexivity (R:=R).
Program Instance flip_Symmetric `(Symmetric A R) : Symmetric (flip R).
Solve Obligations using unfold flip ; intros ; tcapp symmetry ; assumption.
Program Instance flip_Asymmetric `(Asymmetric A R) : Asymmetric (flip R).
Solve Obligations using program_simpl ; unfold flip in * ; intros ; typeclass_app asymmetry ; eauto.
Program Instance flip_Transitive `(Transitive A R) : Transitive (flip R).
Solve Obligations using unfold flip ; program_simpl ; typeclass_app transitivity ; eauto.
Program Instance Reflexive_complement_Irreflexive `(Reflexive A (R : relation A))
: Irreflexive (complement R).
Next Obligation.
Proof. firstorder. Qed.
Program Instance complement_Symmetric `(Symmetric A (R : relation A)) : Symmetric (complement R).
Next Obligation.
Proof. firstorder. Qed.
(** * Standard instances. *)
Ltac reduce_hyp H :=
match type of H with
| context [ _ <-> _ ] => fail 1
| _ => red in H ; try reduce_hyp H
end.
Ltac reduce_goal :=
match goal with
| [ |- _ <-> _ ] => fail 1
| _ => red ; intros ; try reduce_goal
end.
Tactic Notation "reduce" "in" hyp(Hid) := reduce_hyp Hid.
Ltac reduce := reduce_goal.
Tactic Notation "apply" "*" constr(t) :=
first [ refine t | refine (t _) | refine (t _ _) | refine (t _ _ _) | refine (t _ _ _ _) |
refine (t _ _ _ _ _) | refine (t _ _ _ _ _ _) | refine (t _ _ _ _ _ _ _) ].
Ltac simpl_relation :=
unfold flip, impl, arrow ; try reduce ; program_simpl ;
try ( solve [ intuition ]).
Ltac obligation_tactic ::= simpl_relation.
(** Logical implication. *)
Program Instance impl_Reflexive : Reflexive impl.
Program Instance impl_Transitive : Transitive impl.
(** Logical equivalence. *)
Program Instance iff_Reflexive : Reflexive iff.
Program Instance iff_Symmetric : Symmetric iff.
Program Instance iff_Transitive : Transitive iff.
(** Leibniz equality. *)
Program Instance eq_Reflexive : Reflexive (@eq A).
Program Instance eq_Symmetric : Symmetric (@eq A).
Program Instance eq_Transitive : Transitive (@eq A).
(** Various combinations of reflexivity, symmetry and transitivity. *)
(** A [PreOrder] is both Reflexive and Transitive. *)
Class PreOrder {A} (R : relation A) : Prop := {
PreOrder_Reflexive :> Reflexive R ;
PreOrder_Transitive :> Transitive R }.
(** A partial equivalence relation is Symmetric and Transitive. *)
Class PER {A} (R : relation A) : Prop := {
PER_Symmetric :> Symmetric R ;
PER_Transitive :> Transitive R }.
(** Equivalence relations. *)
Class Equivalence {A} (R : relation A) : Prop := {
Equivalence_Reflexive :> Reflexive R ;
Equivalence_Symmetric :> Symmetric R ;
Equivalence_Transitive :> Transitive R }.
(** An Equivalence is a PER plus reflexivity. *)
Instance Equivalence_PER `(Equivalence A R) : PER R | 10 :=
{ PER_Symmetric := Equivalence_Symmetric ;
PER_Transitive := Equivalence_Transitive }.
(** We can now define antisymmetry w.r.t. an equivalence relation on the carrier. *)
Class Antisymmetric A eqA `{equ : Equivalence A eqA} (R : relation A) :=
antisymmetry : forall x y, R x y -> R y x -> eqA x y.
Program Instance flip_antiSymmetric `(Antisymmetric A eqA R) :
! Antisymmetric A eqA (flip R).
(** Leibinz equality [eq] is an equivalence relation.
The instance has low priority as it is always applicable
if only the type is constrained. *)
Program Instance eq_equivalence : Equivalence (@eq A) | 10.
(** Logical equivalence [iff] is an equivalence relation. *)
Program Instance iff_equivalence : Equivalence iff.
(** We now develop a generalization of results on relations for arbitrary predicates.
The resulting theory can be applied to homogeneous binary relations but also to
arbitrary n-ary predicates. *)
Require Import Coq.Lists.List.
(* Notation " [ ] " := nil : list_scope. *)
(* Notation " [ x ; .. ; y ] " := (cons x .. (cons y nil) ..) (at level 1) : list_scope. *)
(* Open Local Scope list_scope. *)
(** A compact representation of non-dependent arities, with the codomain singled-out. *)
Fixpoint arrows (l : list Type) (r : Type) : Type :=
match l with
| nil => r
| A :: l' => A -> arrows l' r
end.
(** We can define abbreviations for operation and relation types based on [arrows]. *)
Definition unary_operation A := arrows (cons A nil) A.
Definition binary_operation A := arrows (cons A (cons A nil)) A.
Definition ternary_operation A := arrows (cons A (cons A (cons A nil))) A.
(** We define n-ary [predicate]s as functions into [Prop]. *)
Notation predicate l := (arrows l Prop).
(** Unary predicates, or sets. *)
Definition unary_predicate A := predicate (cons A nil).
(** Homogeneous binary relations, equivalent to [relation A]. *)
Definition binary_relation A := predicate (cons A (cons A nil)).
(** We can close a predicate by universal or existential quantification. *)
Fixpoint predicate_all (l : list Type) : predicate l -> Prop :=
match l with
| nil => fun f => f
| A :: tl => fun f => forall x : A, predicate_all tl (f x)
end.
Fixpoint predicate_exists (l : list Type) : predicate l -> Prop :=
match l with
| nil => fun f => f
| A :: tl => fun f => exists x : A, predicate_exists tl (f x)
end.
(** Pointwise extension of a binary operation on [T] to a binary operation
on functions whose codomain is [T].
For an operator on [Prop] this lifts the operator to a binary operation. *)
Fixpoint pointwise_extension {T : Type} (op : binary_operation T)
(l : list Type) : binary_operation (arrows l T) :=
match l with
| nil => fun R R' => op R R'
| A :: tl => fun R R' =>
fun x => pointwise_extension op tl (R x) (R' x)
end.
(** Pointwise lifting, equivalent to doing [pointwise_extension] and closing using [predicate_all]. *)
Fixpoint pointwise_lifting (op : binary_relation Prop) (l : list Type) : binary_relation (predicate l) :=
match l with
| nil => fun R R' => op R R'
| A :: tl => fun R R' =>
forall x, pointwise_lifting op tl (R x) (R' x)
end.
(** The n-ary equivalence relation, defined by lifting the 0-ary [iff] relation. *)
Definition predicate_equivalence {l : list Type} : binary_relation (predicate l) :=
pointwise_lifting iff l.
(** The n-ary implication relation, defined by lifting the 0-ary [impl] relation. *)
Definition predicate_implication {l : list Type} :=
pointwise_lifting impl l.
(** Notations for pointwise equivalence and implication of predicates. *)
Infix "<∙>" := predicate_equivalence (at level 95, no associativity) : predicate_scope.
Infix "-∙>" := predicate_implication (at level 70, right associativity) : predicate_scope.
Open Local Scope predicate_scope.
(** The pointwise liftings of conjunction and disjunctions.
Note that these are [binary_operation]s, building new relations out of old ones. *)
Definition predicate_intersection := pointwise_extension and.
Definition predicate_union := pointwise_extension or.
Infix "/∙\" := predicate_intersection (at level 80, right associativity) : predicate_scope.
Infix "\∙/" := predicate_union (at level 85, right associativity) : predicate_scope.
(** The always [True] and always [False] predicates. *)
Fixpoint true_predicate {l : list Type} : predicate l :=
match l with
| nil => True
| A :: tl => fun _ => @true_predicate tl
end.
Fixpoint false_predicate {l : list Type} : predicate l :=
match l with
| nil => False
| A :: tl => fun _ => @false_predicate tl
end.
Notation "∙⊤∙" := true_predicate : predicate_scope.
Notation "∙⊥∙" := false_predicate : predicate_scope.
(** Predicate equivalence is an equivalence, and predicate implication defines a preorder. *)
Program Instance predicate_equivalence_equivalence :
Equivalence (@predicate_equivalence l).
Next Obligation.
induction l ; firstorder.
Qed.
Next Obligation.
induction l ; firstorder.
Qed.
Next Obligation.
fold pointwise_lifting.
induction l. firstorder.
intros. simpl in *. pose (IHl (x x0) (y x0) (z x0)).
firstorder.
Qed.
Program Instance predicate_implication_preorder :
PreOrder (@predicate_implication l).
Next Obligation.
induction l ; firstorder.
Qed.
Next Obligation.
induction l. firstorder.
unfold predicate_implication in *. simpl in *.
intro. pose (IHl (x x0) (y x0) (z x0)). firstorder.
Qed.
(** We define the various operations which define the algebra on binary relations,
from the general ones. *)
Definition relation_equivalence {A : Type} : relation (relation A) :=
@predicate_equivalence (cons _ (cons _ nil)).
Class subrelation {A:Type} (R R' : relation A) : Prop :=
is_subrelation : @predicate_implication (cons A (cons A nil)) R R'.
Implicit Arguments subrelation [[A]].
Definition relation_conjunction {A} (R : relation A) (R' : relation A) : relation A :=
@predicate_intersection (cons A (cons A nil)) R R'.
Definition relation_disjunction {A} (R : relation A) (R' : relation A) : relation A :=
@predicate_union (cons A (cons A nil)) R R'.
(** Relation equivalence is an equivalence, and subrelation defines a partial order. *)
Instance relation_equivalence_equivalence (A : Type) :
Equivalence (@relation_equivalence A).
Proof. intro A. exact (@predicate_equivalence_equivalence (cons A (cons A nil))). Qed.
Instance relation_implication_preorder : PreOrder (@subrelation A).
Proof. intro A. exact (@predicate_implication_preorder (cons A (cons A nil))). Qed.
(** *** Partial Order.
A partial order is a preorder which is additionally antisymmetric.
We give an equivalent definition, up-to an equivalence relation
on the carrier. *)
Class PartialOrder {A} eqA `{equ : Equivalence A eqA} R `{preo : PreOrder A R} :=
partial_order_equivalence : relation_equivalence eqA (relation_conjunction R (inverse R)).
(** The equivalence proof is sufficient for proving that [R] must be a morphism
for equivalence (see Morphisms).
It is also sufficient to show that [R] is antisymmetric w.r.t. [eqA] *)
Instance partial_order_antisym `(PartialOrder A eqA R) : ! Antisymmetric A eqA R.
Proof with auto.
reduce_goal.
pose proof partial_order_equivalence as poe. do 3 red in poe.
apply <- poe. firstorder.
Qed.
(** The partial order defined by subrelation and relation equivalence. *)
Program Instance subrelation_partial_order :
! PartialOrder (relation A) relation_equivalence subrelation.
Next Obligation.
Proof.
unfold relation_equivalence in *. firstorder.
Qed.
Typeclasses Opaque arrows predicate_implication predicate_equivalence
relation_equivalence pointwise_lifting.
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O22AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__O22AI_BEHAVIORAL_PP_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o22ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O22AI_BEHAVIORAL_PP_V |
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* v0(a)+v1(a)+v2(a) == a^3 in GF(3^m) */
/* c == v0(a) */
module v0(a, c);
input [193:0] a;
output [193:0] c;
assign c[1:0] = a[1:0];
assign c[3:2] = a[131:130];
assign c[5:4] = a[67:66];
assign c[7:6] = a[3:2];
assign c[9:8] = a[133:132];
assign c[11:10] = a[69:68];
assign c[13:12] = a[5:4];
assign c[15:14] = a[135:134];
assign c[17:16] = a[71:70];
assign c[19:18] = a[193:192];
assign c[21:20] = {a[128], a[129]};
assign c[23:22] = a[73:72];
assign c[25:24] = {a[178], a[179]};
assign c[27:26] = a[131:130];
assign c[29:28] = {a[66], a[67]};
assign c[31:30] = {a[180], a[181]};
assign c[33:32] = a[133:132];
assign c[35:34] = {a[68], a[69]};
assign c[37:36] = {a[182], a[183]};
assign c[39:38] = a[127:126];
assign c[41:40] = {a[70], a[71]};
assign c[43:42] = {a[184], a[185]};
assign c[45:44] = a[145:144];
assign c[47:46] = a[81:80];
assign c[49:48] = a[17:16];
assign c[51:50] = a[147:146];
assign c[53:52] = a[83:82];
assign c[55:54] = a[19:18];
assign c[57:56] = a[149:148];
assign c[59:58] = a[85:84];
assign c[61:60] = a[21:20];
assign c[63:62] = a[135:134];
assign c[65:64] = a[87:86];
assign c[67:66] = {a[192], a[193]};
assign c[69:68] = a[145:144];
assign c[71:70] = {a[80], a[81]};
assign c[73:72] = a[25:24];
assign c[75:74] = a[147:146];
assign c[77:76] = {a[82], a[83]};
assign c[79:78] = a[27:26];
assign c[81:80] = a[149:148];
assign c[83:82] = {a[84], a[85]};
assign c[85:84] = a[29:28];
assign c[87:86] = a[143:142];
assign c[89:88] = {a[86], a[87]};
assign c[91:90] = a[31:30];
assign c[93:92] = a[161:160];
assign c[95:94] = a[97:96];
assign c[97:96] = a[33:32];
assign c[99:98] = a[163:162];
assign c[101:100] = a[99:98];
assign c[103:102] = a[35:34];
assign c[105:104] = a[165:164];
assign c[107:106] = a[101:100];
assign c[109:108] = a[37:36];
assign c[111:110] = a[151:150];
assign c[113:112] = a[103:102];
assign c[115:114] = a[39:38];
assign c[117:116] = a[161:160];
assign c[119:118] = {a[96], a[97]};
assign c[121:120] = a[41:40];
assign c[123:122] = a[163:162];
assign c[125:124] = {a[98], a[99]};
assign c[127:126] = a[43:42];
assign c[129:128] = a[165:164];
assign c[131:130] = {a[100], a[101]};
assign c[133:132] = a[45:44];
assign c[135:134] = a[159:158];
assign c[137:136] = {a[102], a[103]};
assign c[139:138] = a[47:46];
assign c[141:140] = a[177:176];
assign c[143:142] = a[113:112];
assign c[145:144] = a[49:48];
assign c[147:146] = a[179:178];
assign c[149:148] = a[115:114];
assign c[151:150] = a[51:50];
assign c[153:152] = a[181:180];
assign c[155:154] = a[117:116];
assign c[157:156] = a[53:52];
assign c[159:158] = a[167:166];
assign c[161:160] = a[119:118];
assign c[163:162] = a[55:54];
assign c[165:164] = a[177:176];
assign c[167:166] = {a[112], a[113]};
assign c[169:168] = a[57:56];
assign c[171:170] = a[179:178];
assign c[173:172] = {a[114], a[115]};
assign c[175:174] = a[59:58];
assign c[177:176] = a[181:180];
assign c[179:178] = {a[116], a[117]};
assign c[181:180] = a[61:60];
assign c[183:182] = a[175:174];
assign c[185:184] = {a[118], a[119]};
assign c[187:186] = a[63:62];
assign c[189:188] = a[193:192];
assign c[191:190] = a[129:128];
assign c[193:192] = a[65:64];
endmodule
/* c == v1(a) */
module v1(a, c);
input [193:0] a;
output [193:0] c;
assign c[1:0] = a[179:178];
assign c[3:2] = {a[122], a[123]};
assign c[5:4] = 0;
assign c[7:6] = a[181:180];
assign c[9:8] = {a[124], a[125]};
assign c[11:10] = 0;
assign c[13:12] = a[183:182];
assign c[15:14] = {a[126], a[127]};
assign c[17:16] = 0;
assign c[19:18] = a[7:6];
assign c[21:20] = a[137:136];
assign c[23:22] = 0;
assign c[25:24] = a[9:8];
assign c[27:26] = a[139:138];
assign c[29:28] = a[75:74];
assign c[31:30] = a[11:10];
assign c[33:32] = a[125:124];
assign c[35:34] = a[77:76];
assign c[37:36] = a[13:12];
assign c[39:38] = a[135:134];
assign c[41:40] = a[79:78];
assign c[43:42] = a[15:14];
assign c[45:44] = a[129:128];
assign c[47:46] = {a[72], a[73]};
assign c[49:48] = {a[186], a[187]};
assign c[51:50] = a[139:138];
assign c[53:52] = {a[74], a[75]};
assign c[55:54] = {a[188], a[189]};
assign c[57:56] = a[133:132];
assign c[59:58] = {a[76], a[77]};
assign c[61:60] = {a[190], a[191]};
assign c[63:62] = a[151:150];
assign c[65:64] = {a[78], a[79]};
assign c[67:66] = a[23:22];
assign c[69:68] = a[137:136];
assign c[71:70] = a[89:88];
assign c[73:72] = 0;
assign c[75:74] = a[155:154];
assign c[77:76] = a[91:90];
assign c[79:78] = 0;
assign c[81:80] = a[141:140];
assign c[83:82] = a[93:92];
assign c[85:84] = 0;
assign c[87:86] = a[151:150];
assign c[89:88] = a[95:94];
assign c[91:90] = 0;
assign c[93:92] = a[145:144];
assign c[95:94] = {a[88], a[89]};
assign c[97:96] = 0;
assign c[99:98] = a[155:154];
assign c[101:100] = {a[90], a[91]};
assign c[103:102] = 0;
assign c[105:104] = a[149:148];
assign c[107:106] = {a[92], a[93]};
assign c[109:108] = 0;
assign c[111:110] = a[167:166];
assign c[113:112] = {a[94], a[95]};
assign c[115:114] = 0;
assign c[117:116] = a[153:152];
assign c[119:118] = a[105:104];
assign c[121:120] = 0;
assign c[123:122] = a[171:170];
assign c[125:124] = a[107:106];
assign c[127:126] = 0;
assign c[129:128] = a[157:156];
assign c[131:130] = a[109:108];
assign c[133:132] = 0;
assign c[135:134] = a[167:166];
assign c[137:136] = a[111:110];
assign c[139:138] = 0;
assign c[141:140] = a[161:160];
assign c[143:142] = {a[104], a[105]};
assign c[145:144] = 0;
assign c[147:146] = a[171:170];
assign c[149:148] = {a[106], a[107]};
assign c[151:150] = 0;
assign c[153:152] = a[165:164];
assign c[155:154] = {a[108], a[109]};
assign c[157:156] = 0;
assign c[159:158] = a[183:182];
assign c[161:160] = {a[110], a[111]};
assign c[163:162] = 0;
assign c[165:164] = a[169:168];
assign c[167:166] = a[121:120];
assign c[169:168] = 0;
assign c[171:170] = a[187:186];
assign c[173:172] = a[123:122];
assign c[175:174] = 0;
assign c[177:176] = a[173:172];
assign c[179:178] = a[125:124];
assign c[181:180] = 0;
assign c[183:182] = a[183:182];
assign c[185:184] = a[127:126];
assign c[187:186] = 0;
assign c[189:188] = a[177:176];
assign c[191:190] = {a[120], a[121]};
assign c[193:192] = 0;
endmodule
/* c == v2(a) */
module v2(a, c);
input [193:0] a;
output [193:0] c;
assign c[1:0] = a[187:186];
assign c[3:2] = 0;
assign c[5:4] = 0;
assign c[7:6] = a[189:188];
assign c[9:8] = 0;
assign c[11:10] = 0;
assign c[13:12] = a[191:190];
assign c[15:14] = 0;
assign c[17:16] = 0;
assign c[19:18] = a[185:184];
assign c[21:20] = 0;
assign c[23:22] = 0;
assign c[25:24] = 0;
assign c[27:26] = a[123:122];
assign c[29:28] = 0;
assign c[31:30] = 0;
assign c[33:32] = a[141:140];
assign c[35:34] = 0;
assign c[37:36] = 0;
assign c[39:38] = a[143:142];
assign c[41:40] = 0;
assign c[43:42] = 0;
assign c[45:44] = a[137:136];
assign c[47:46] = 0;
assign c[49:48] = 0;
assign c[51:50] = a[131:130];
assign c[53:52] = 0;
assign c[55:54] = 0;
assign c[57:56] = a[141:140];
assign c[59:58] = 0;
assign c[61:60] = 0;
assign c[63:62] = a[143:142];
assign c[65:64] = 0;
assign c[67:66] = 0;
assign c[69:68] = a[153:152];
assign c[71:70] = 0;
assign c[73:72] = 0;
assign c[75:74] = a[139:138];
assign c[77:76] = 0;
assign c[79:78] = 0;
assign c[81:80] = a[157:156];
assign c[83:82] = 0;
assign c[85:84] = 0;
assign c[87:86] = a[159:158];
assign c[89:88] = 0;
assign c[91:90] = 0;
assign c[93:92] = a[153:152];
assign c[95:94] = 0;
assign c[97:96] = 0;
assign c[99:98] = a[147:146];
assign c[101:100] = 0;
assign c[103:102] = 0;
assign c[105:104] = a[157:156];
assign c[107:106] = 0;
assign c[109:108] = 0;
assign c[111:110] = a[159:158];
assign c[113:112] = 0;
assign c[115:114] = 0;
assign c[117:116] = a[169:168];
assign c[119:118] = 0;
assign c[121:120] = 0;
assign c[123:122] = a[155:154];
assign c[125:124] = 0;
assign c[127:126] = 0;
assign c[129:128] = a[173:172];
assign c[131:130] = 0;
assign c[133:132] = 0;
assign c[135:134] = a[175:174];
assign c[137:136] = 0;
assign c[139:138] = 0;
assign c[141:140] = a[169:168];
assign c[143:142] = 0;
assign c[145:144] = 0;
assign c[147:146] = a[163:162];
assign c[149:148] = 0;
assign c[151:150] = 0;
assign c[153:152] = a[173:172];
assign c[155:154] = 0;
assign c[157:156] = 0;
assign c[159:158] = a[175:174];
assign c[161:160] = 0;
assign c[163:162] = 0;
assign c[165:164] = a[185:184];
assign c[167:166] = 0;
assign c[169:168] = 0;
assign c[171:170] = a[171:170];
assign c[173:172] = 0;
assign c[175:174] = 0;
assign c[177:176] = a[189:188];
assign c[179:178] = 0;
assign c[181:180] = 0;
assign c[183:182] = a[191:190];
assign c[185:184] = 0;
assign c[187:186] = 0;
assign c[189:188] = a[185:184];
assign c[191:190] = 0;
assign c[193:192] = 0;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_buf_p1.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module pcx_buf_p1(/*AUTOARG*/
// Outputs
scache0_pcx_stall_bufp1_pq, spc0_pcx_req_bufp1_pq,
spc0_pcx_atom_bufp1_pq, spc1_pcx_req_bufp1_pq,
spc1_pcx_atom_bufp1_pq, spc2_pcx_req_bufp1_pq,
spc2_pcx_atom_bufp1_pq, spc3_pcx_req_bufp1_pq,
spc3_pcx_atom_bufp1_pq, spc4_pcx_req_bufp1_pq,
spc4_pcx_atom_bufp1_pq, pcx_spc0_grant_bufp1_pa_l,
pcx_spc1_grant_bufp1_pa_l, pcx_spc2_grant_bufp1_pa_l,
arbpc0_pcxdp_grant_bufp1_pa_l, arbpc0_pcxdp_q0_hold_bufp1_pa,
arbpc0_pcxdp_qsel0_bufp1_pa_l, arbpc0_pcxdp_qsel1_bufp1_pa,
arbpc0_pcxdp_shift_bufp1_px_l, arbpc1_pcxdp_grant_bufp1_pa_l,
arbpc1_pcxdp_q0_hold_bufp1_pa, arbpc1_pcxdp_qsel0_bufp1_pa_l,
arbpc1_pcxdp_qsel1_bufp1_pa, arbpc1_pcxdp_shift_bufp1_px_l,
arbpc2_pcxdp_grant_bufp1_pa_l, arbpc2_pcxdp_q0_hold_bufp1_pa,
arbpc2_pcxdp_qsel0_bufp1_pa_l, arbpc2_pcxdp_qsel1_bufp1_pa,
arbpc2_pcxdp_shift_bufp1_px_l, arbpc3_pcxdp_grant_bufp1_pa_l,
arbpc3_pcxdp_q0_hold_bufp1_pa, arbpc3_pcxdp_qsel0_bufp1_pa_l,
arbpc3_pcxdp_qsel1_bufp1_pa, arbpc3_pcxdp_shift_bufp1_px_l,
arbpc4_pcxdp_grant_bufp1_pa_l, arbpc4_pcxdp_q0_hold_bufp1_pa,
arbpc4_pcxdp_qsel0_bufp1_pa_l, arbpc4_pcxdp_qsel1_bufp1_pa,
arbpc4_pcxdp_shift_bufp1_px_l, sctag1_pcx_stall_bufp1_pq,
// Inputs
scache0_pcx_stall_bufp0even_pq, spc0_pcx_req_bufp0_pq,
spc0_pcx_atom_bufp0_pq, spc1_pcx_req_bufp0_pq,
spc1_pcx_atom_bufp0_pq, spc2_pcx_req_bufpt_pq_l,
spc2_pcx_atom_bufpt_pq_l, spc3_pcx_req_bufpt1_pq,
spc3_pcx_atom_bufpt1_pq, spc4_pcx_req_bufpt1_pq,
spc4_pcx_atom_bufpt1_pq, pcx_spc0_grant_pa, pcx_spc1_grant_pa,
pcx_spc2_grant_pa, arbpc0_pcxdp_grant_arbbf_pa,
arbpc0_pcxdp_q0_hold_arbbf_pa_l, arbpc0_pcxdp_qsel0_arbbf_pa,
arbpc0_pcxdp_qsel1_arbbf_pa_l, arbpc0_pcxdp_shift_arbbf_px,
arbpc1_pcxdp_grant_arbbf_pa, arbpc1_pcxdp_q0_hold_arbbf_pa_l,
arbpc1_pcxdp_qsel0_arbbf_pa, arbpc1_pcxdp_qsel1_arbbf_pa_l,
arbpc1_pcxdp_shift_arbbf_px, arbpc2_pcxdp_grant_arbbf_pa,
arbpc2_pcxdp_q0_hold_arbbf_pa_l, arbpc2_pcxdp_qsel0_arbbf_pa,
arbpc2_pcxdp_qsel1_arbbf_pa_l, arbpc2_pcxdp_shift_arbbf_px,
arbpc3_pcxdp_grant_arbbf_pa, arbpc3_pcxdp_q0_hold_arbbf_pa_l,
arbpc3_pcxdp_qsel0_arbbf_pa, arbpc3_pcxdp_qsel1_arbbf_pa_l,
arbpc3_pcxdp_shift_arbbf_px, arbpc4_pcxdp_grant_arbbf_pa,
arbpc4_pcxdp_q0_hold_arbbf_pa_l, arbpc4_pcxdp_qsel0_arbbf_pa,
arbpc4_pcxdp_qsel1_arbbf_pa_l, arbpc4_pcxdp_shift_arbbf_px,
sctag1_pcx_stall_bufp0odd_pq
);
output scache0_pcx_stall_bufp1_pq ;
output [4:0] spc0_pcx_req_bufp1_pq ;
output spc0_pcx_atom_bufp1_pq ;
output [4:0] spc1_pcx_req_bufp1_pq ;
output spc1_pcx_atom_bufp1_pq ;
output [4:0] spc2_pcx_req_bufp1_pq ;
output spc2_pcx_atom_bufp1_pq ;
output [4:0] spc3_pcx_req_bufp1_pq ;
output spc3_pcx_atom_bufp1_pq ;
output [4:0] spc4_pcx_req_bufp1_pq ;
output spc4_pcx_atom_bufp1_pq ;
output [4:0] pcx_spc0_grant_bufp1_pa_l;
output [4:0] pcx_spc1_grant_bufp1_pa_l;
output [4:0] pcx_spc2_grant_bufp1_pa_l;
output [2:0] arbpc0_pcxdp_grant_bufp1_pa_l;
output [2:0] arbpc0_pcxdp_q0_hold_bufp1_pa;
output [2:0] arbpc0_pcxdp_qsel0_bufp1_pa_l;
output [2:0] arbpc0_pcxdp_qsel1_bufp1_pa;
output [2:0] arbpc0_pcxdp_shift_bufp1_px_l;
output [2:0] arbpc1_pcxdp_grant_bufp1_pa_l;
output [2:0] arbpc1_pcxdp_q0_hold_bufp1_pa;
output [2:0] arbpc1_pcxdp_qsel0_bufp1_pa_l;
output [2:0] arbpc1_pcxdp_qsel1_bufp1_pa;
output [2:0] arbpc1_pcxdp_shift_bufp1_px_l;
output [2:0] arbpc2_pcxdp_grant_bufp1_pa_l;
output [2:0] arbpc2_pcxdp_q0_hold_bufp1_pa;
output [2:0] arbpc2_pcxdp_qsel0_bufp1_pa_l;
output [2:0] arbpc2_pcxdp_qsel1_bufp1_pa;
output [2:0] arbpc2_pcxdp_shift_bufp1_px_l;
output [2:0] arbpc3_pcxdp_grant_bufp1_pa_l;
output [2:0] arbpc3_pcxdp_q0_hold_bufp1_pa;
output [2:0] arbpc3_pcxdp_qsel0_bufp1_pa_l;
output [2:0] arbpc3_pcxdp_qsel1_bufp1_pa;
output [2:0] arbpc3_pcxdp_shift_bufp1_px_l;
output [2:0] arbpc4_pcxdp_grant_bufp1_pa_l;
output [2:0] arbpc4_pcxdp_q0_hold_bufp1_pa;
output [2:0] arbpc4_pcxdp_qsel0_bufp1_pa_l;
output [2:0] arbpc4_pcxdp_qsel1_bufp1_pa;
output [2:0] arbpc4_pcxdp_shift_bufp1_px_l;
output sctag1_pcx_stall_bufp1_pq;
input scache0_pcx_stall_bufp0even_pq ;
input [4:0] spc0_pcx_req_bufp0_pq;
input spc0_pcx_atom_bufp0_pq;
input [4:0] spc1_pcx_req_bufp0_pq;
input spc1_pcx_atom_bufp0_pq;
input [4:0] spc2_pcx_req_bufpt_pq_l;
input spc2_pcx_atom_bufpt_pq_l;
input [4:0] spc3_pcx_req_bufpt1_pq;
input spc3_pcx_atom_bufpt1_pq;
input [4:0] spc4_pcx_req_bufpt1_pq;
input spc4_pcx_atom_bufpt1_pq;
input [4:0] pcx_spc0_grant_pa;
input [4:0] pcx_spc1_grant_pa;
input [4:0] pcx_spc2_grant_pa;
input [2:0] arbpc0_pcxdp_grant_arbbf_pa;
input [2:0] arbpc0_pcxdp_q0_hold_arbbf_pa_l;
input [2:0] arbpc0_pcxdp_qsel0_arbbf_pa;
input [2:0] arbpc0_pcxdp_qsel1_arbbf_pa_l;
input [2:0] arbpc0_pcxdp_shift_arbbf_px;
input [2:0] arbpc1_pcxdp_grant_arbbf_pa;
input [2:0] arbpc1_pcxdp_q0_hold_arbbf_pa_l;
input [2:0] arbpc1_pcxdp_qsel0_arbbf_pa;
input [2:0] arbpc1_pcxdp_qsel1_arbbf_pa_l;
input [2:0] arbpc1_pcxdp_shift_arbbf_px;
input [2:0] arbpc2_pcxdp_grant_arbbf_pa;
input [2:0] arbpc2_pcxdp_q0_hold_arbbf_pa_l;
input [2:0] arbpc2_pcxdp_qsel0_arbbf_pa;
input [2:0] arbpc2_pcxdp_qsel1_arbbf_pa_l;
input [2:0] arbpc2_pcxdp_shift_arbbf_px;
input [2:0] arbpc3_pcxdp_grant_arbbf_pa;
input [2:0] arbpc3_pcxdp_q0_hold_arbbf_pa_l;
input [2:0] arbpc3_pcxdp_qsel0_arbbf_pa;
input [2:0] arbpc3_pcxdp_qsel1_arbbf_pa_l;
input [2:0] arbpc3_pcxdp_shift_arbbf_px;
input [2:0] arbpc4_pcxdp_grant_arbbf_pa;
input [2:0] arbpc4_pcxdp_q0_hold_arbbf_pa_l;
input [2:0] arbpc4_pcxdp_qsel0_arbbf_pa;
input [2:0] arbpc4_pcxdp_qsel1_arbbf_pa_l;
input [2:0] arbpc4_pcxdp_shift_arbbf_px;
input sctag1_pcx_stall_bufp0odd_pq;
assign sctag1_pcx_stall_bufp1_pq = sctag1_pcx_stall_bufp0odd_pq;
assign scache0_pcx_stall_bufp1_pq = scache0_pcx_stall_bufp0even_pq;
assign spc0_pcx_req_bufp1_pq[4:0] = spc0_pcx_req_bufp0_pq[4:0];
assign spc0_pcx_atom_bufp1_pq = spc0_pcx_atom_bufp0_pq;
assign spc1_pcx_req_bufp1_pq[4:0] = spc1_pcx_req_bufp0_pq[4:0];
assign spc1_pcx_atom_bufp1_pq = spc1_pcx_atom_bufp0_pq;
assign spc2_pcx_req_bufp1_pq[4:0] = ~spc2_pcx_req_bufpt_pq_l[4:0];
assign spc2_pcx_atom_bufp1_pq = ~spc2_pcx_atom_bufpt_pq_l;
assign spc3_pcx_req_bufp1_pq[4:0] = spc3_pcx_req_bufpt1_pq[4:0];
assign spc3_pcx_atom_bufp1_pq = spc3_pcx_atom_bufpt1_pq;
assign spc4_pcx_req_bufp1_pq[4:0] = spc4_pcx_req_bufpt1_pq[4:0];
assign spc4_pcx_atom_bufp1_pq = spc4_pcx_atom_bufpt1_pq;
assign pcx_spc0_grant_bufp1_pa_l[4:0] = ~pcx_spc0_grant_pa[4:0];
assign pcx_spc1_grant_bufp1_pa_l[4:0] = ~pcx_spc1_grant_pa[4:0];
assign pcx_spc2_grant_bufp1_pa_l[4:0] = ~pcx_spc2_grant_pa[4:0];
assign arbpc0_pcxdp_grant_bufp1_pa_l = ~arbpc0_pcxdp_grant_arbbf_pa;
assign arbpc0_pcxdp_q0_hold_bufp1_pa = ~arbpc0_pcxdp_q0_hold_arbbf_pa_l;
assign arbpc0_pcxdp_qsel0_bufp1_pa_l = ~arbpc0_pcxdp_qsel0_arbbf_pa;
assign arbpc0_pcxdp_qsel1_bufp1_pa = ~arbpc0_pcxdp_qsel1_arbbf_pa_l;
assign arbpc0_pcxdp_shift_bufp1_px_l = ~arbpc0_pcxdp_shift_arbbf_px;
assign arbpc1_pcxdp_grant_bufp1_pa_l = ~arbpc1_pcxdp_grant_arbbf_pa;
assign arbpc1_pcxdp_q0_hold_bufp1_pa = ~arbpc1_pcxdp_q0_hold_arbbf_pa_l;
assign arbpc1_pcxdp_qsel0_bufp1_pa_l = ~arbpc1_pcxdp_qsel0_arbbf_pa;
assign arbpc1_pcxdp_qsel1_bufp1_pa = ~arbpc1_pcxdp_qsel1_arbbf_pa_l;
assign arbpc1_pcxdp_shift_bufp1_px_l = ~arbpc1_pcxdp_shift_arbbf_px;
assign arbpc2_pcxdp_grant_bufp1_pa_l = ~arbpc2_pcxdp_grant_arbbf_pa;
assign arbpc2_pcxdp_q0_hold_bufp1_pa = ~arbpc2_pcxdp_q0_hold_arbbf_pa_l;
assign arbpc2_pcxdp_qsel0_bufp1_pa_l = ~arbpc2_pcxdp_qsel0_arbbf_pa;
assign arbpc2_pcxdp_qsel1_bufp1_pa = ~arbpc2_pcxdp_qsel1_arbbf_pa_l;
assign arbpc2_pcxdp_shift_bufp1_px_l = ~arbpc2_pcxdp_shift_arbbf_px;
assign arbpc3_pcxdp_grant_bufp1_pa_l = ~arbpc3_pcxdp_grant_arbbf_pa;
assign arbpc3_pcxdp_q0_hold_bufp1_pa = ~arbpc3_pcxdp_q0_hold_arbbf_pa_l;
assign arbpc3_pcxdp_qsel0_bufp1_pa_l = ~arbpc3_pcxdp_qsel0_arbbf_pa;
assign arbpc3_pcxdp_qsel1_bufp1_pa = ~arbpc3_pcxdp_qsel1_arbbf_pa_l;
assign arbpc3_pcxdp_shift_bufp1_px_l = ~arbpc3_pcxdp_shift_arbbf_px;
assign arbpc4_pcxdp_grant_bufp1_pa_l = ~arbpc4_pcxdp_grant_arbbf_pa;
assign arbpc4_pcxdp_q0_hold_bufp1_pa = ~arbpc4_pcxdp_q0_hold_arbbf_pa_l;
assign arbpc4_pcxdp_qsel0_bufp1_pa_l = ~arbpc4_pcxdp_qsel0_arbbf_pa;
assign arbpc4_pcxdp_qsel1_bufp1_pa = ~arbpc4_pcxdp_qsel1_arbbf_pa_l;
assign arbpc4_pcxdp_shift_bufp1_px_l = ~arbpc4_pcxdp_shift_arbbf_px;
endmodule // pcx_grant_ff
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Setoid.
Require Import PeanoNat Le Gt Minus Bool Lt.
Set Implicit Arguments.
(* Set Universe Polymorphism. *)
(******************************************************************)
(** * Basics: definition of polymorphic lists and some operations *)
(******************************************************************)
(** The definition of [list] is now in [Init/Datatypes],
as well as the definitions of [length] and [app] *)
Open Scope list_scope.
(** Standard notations for lists.
In a special module to avoid conflicts. *)
Module ListNotations.
Notation "[ ]" := nil (format "[ ]") : list_scope.
Notation "[ x ]" := (cons x nil) : list_scope.
Notation "[ x ; y ; .. ; z ]" := (cons x (cons y .. (cons z nil) ..)) : list_scope.
End ListNotations.
Import ListNotations.
Section Lists.
Variable A : Type.
(** Head and tail *)
Definition hd (default:A) (l:list A) :=
match l with
| [] => default
| x :: _ => x
end.
Definition hd_error (l:list A) :=
match l with
| [] => None
| x :: _ => Some x
end.
Definition tl (l:list A) :=
match l with
| [] => nil
| a :: m => m
end.
(** The [In] predicate *)
Fixpoint In (a:A) (l:list A) : Prop :=
match l with
| [] => False
| b :: m => b = a \/ In a m
end.
End Lists.
Section Facts.
Variable A : Type.
(** *** Generic facts *)
(** Discrimination *)
Theorem nil_cons : forall (x:A) (l:list A), [] <> x :: l.
Proof.
intros; discriminate.
Qed.
(** Destruction *)
Theorem destruct_list : forall l : list A, {x:A & {tl:list A | l = x::tl}}+{l = []}.
Proof.
induction l as [|a tail].
right; reflexivity.
left; exists a, tail; reflexivity.
Qed.
Lemma hd_error_tl_repr : forall l (a:A) r,
hd_error l = Some a /\ tl l = r <-> l = a :: r.
Proof. destruct l as [|x xs].
- unfold hd_error, tl; intros a r. split; firstorder discriminate.
- intros. simpl. split.
* intros (H1, H2). inversion H1. rewrite H2. reflexivity.
* inversion 1. subst. auto.
Qed.
Lemma hd_error_some_nil : forall l (a:A), hd_error l = Some a -> l <> nil.
Proof. unfold hd_error. destruct l; now discriminate. Qed.
Theorem length_zero_iff_nil (l : list A):
length l = 0 <-> l=[].
Proof.
split; [now destruct l | now intros ->].
Qed.
(** *** Head and tail *)
Theorem hd_error_nil : hd_error (@nil A) = None.
Proof.
simpl; reflexivity.
Qed.
Theorem hd_error_cons : forall (l : list A) (x : A), hd_error (x::l) = Some x.
Proof.
intros; simpl; reflexivity.
Qed.
(************************)
(** *** Facts about [In] *)
(************************)
(** Characterization of [In] *)
Theorem in_eq : forall (a:A) (l:list A), In a (a :: l).
Proof.
simpl; auto.
Qed.
Theorem in_cons : forall (a b:A) (l:list A), In b l -> In b (a :: l).
Proof.
simpl; auto.
Qed.
Theorem not_in_cons (x a : A) (l : list A):
~ In x (a::l) <-> x<>a /\ ~ In x l.
Proof.
simpl. intuition.
Qed.
Theorem in_nil : forall a:A, ~ In a [].
Proof.
unfold not; intros a H; inversion_clear H.
Qed.
Theorem in_split : forall x (l:list A), In x l -> exists l1 l2, l = l1++x::l2.
Proof.
induction l; simpl; destruct 1.
subst a; auto.
exists [], l; auto.
destruct (IHl H) as (l1,(l2,H0)).
exists (a::l1), l2; simpl. apply f_equal. auto.
Qed.
(** Inversion *)
Lemma in_inv : forall (a b:A) (l:list A), In b (a :: l) -> a = b \/ In b l.
Proof.
intros a b l H; inversion_clear H; auto.
Qed.
(** Decidability of [In] *)
Theorem in_dec :
(forall x y:A, {x = y} + {x <> y}) ->
forall (a:A) (l:list A), {In a l} + {~ In a l}.
Proof.
intro H; induction l as [| a0 l IHl].
right; apply in_nil.
destruct (H a0 a); simpl; auto.
destruct IHl; simpl; auto.
right; unfold not; intros [Hc1| Hc2]; auto.
Defined.
(**************************)
(** *** Facts about [app] *)
(**************************)
(** Discrimination *)
Theorem app_cons_not_nil : forall (x y:list A) (a:A), [] <> x ++ a :: y.
Proof.
unfold not.
destruct x as [| a l]; simpl; intros.
discriminate H.
discriminate H.
Qed.
(** Concat with [nil] *)
Theorem app_nil_l : forall l:list A, [] ++ l = l.
Proof.
reflexivity.
Qed.
Theorem app_nil_r : forall l:list A, l ++ [] = l.
Proof.
induction l; simpl; f_equal; auto.
Qed.
(* begin hide *)
(* Deprecated *)
Theorem app_nil_end : forall (l:list A), l = l ++ [].
Proof. symmetry; apply app_nil_r. Qed.
(* end hide *)
(** [app] is associative *)
Theorem app_assoc : forall l m n:list A, l ++ m ++ n = (l ++ m) ++ n.
Proof.
intros l m n; induction l; simpl; f_equal; auto.
Qed.
(* begin hide *)
(* Deprecated *)
Theorem app_assoc_reverse : forall l m n:list A, (l ++ m) ++ n = l ++ m ++ n.
Proof.
auto using app_assoc.
Qed.
Hint Resolve app_assoc_reverse : core.
(* end hide *)
(** [app] commutes with [cons] *)
Theorem app_comm_cons : forall (x y:list A) (a:A), a :: (x ++ y) = (a :: x) ++ y.
Proof.
auto.
Qed.
(** Facts deduced from the result of a concatenation *)
Theorem app_eq_nil : forall l l':list A, l ++ l' = [] -> l = [] /\ l' = [].
Proof.
destruct l as [| x l]; destruct l' as [| y l']; simpl; auto.
intro; discriminate.
intros H; discriminate H.
Qed.
Theorem app_eq_unit :
forall (x y:list A) (a:A),
x ++ y = [a] -> x = [] /\ y = [a] \/ x = [a] /\ y = [].
Proof.
destruct x as [| a l]; [ destruct y as [| a l] | destruct y as [| a0 l0] ];
simpl.
intros a H; discriminate H.
left; split; auto.
right; split; auto.
generalize H.
generalize (app_nil_r l); intros E.
rewrite -> E; auto.
intros.
injection H as H H0.
assert ([] = l ++ a0 :: l0) by auto.
apply app_cons_not_nil in H1 as [].
Qed.
Lemma app_inj_tail :
forall (x y:list A) (a b:A), x ++ [a] = y ++ [b] -> x = y /\ a = b.
Proof.
induction x as [| x l IHl];
[ destruct y as [| a l] | destruct y as [| a l0] ];
simpl; auto.
- intros a b H.
injection H.
auto.
- intros a0 b H.
injection H as H1 H0.
apply app_cons_not_nil in H0 as [].
- intros a b H.
injection H as H1 H0.
assert ([] = l ++ [a]) by auto.
apply app_cons_not_nil in H as [].
- intros a0 b H.
injection H as <- H0.
destruct (IHl l0 a0 b H0) as (<-,<-).
split; auto.
Qed.
(** Compatibility with other operations *)
Lemma app_length : forall l l' : list A, length (l++l') = length l + length l'.
Proof.
induction l; simpl; auto.
Qed.
Lemma in_app_or : forall (l m:list A) (a:A), In a (l ++ m) -> In a l \/ In a m.
Proof.
intros l m a.
elim l; simpl; auto.
intros a0 y H H0.
now_show ((a0 = a \/ In a y) \/ In a m).
elim H0; auto.
intro H1.
now_show ((a0 = a \/ In a y) \/ In a m).
elim (H H1); auto.
Qed.
Lemma in_or_app : forall (l m:list A) (a:A), In a l \/ In a m -> In a (l ++ m).
Proof.
intros l m a.
elim l; simpl; intro H.
now_show (In a m).
elim H; auto; intro H0.
now_show (In a m).
elim H0. (* subProof completed *)
intros y H0 H1.
now_show (H = a \/ In a (y ++ m)).
elim H1; auto 4.
intro H2.
now_show (H = a \/ In a (y ++ m)).
elim H2; auto.
Qed.
Lemma in_app_iff : forall l l' (a:A), In a (l++l') <-> In a l \/ In a l'.
Proof.
split; auto using in_app_or, in_or_app.
Qed.
Lemma app_inv_head:
forall l l1 l2 : list A, l ++ l1 = l ++ l2 -> l1 = l2.
Proof.
induction l; simpl; auto; injection 1; auto.
Qed.
Lemma app_inv_tail:
forall l l1 l2 : list A, l1 ++ l = l2 ++ l -> l1 = l2.
Proof.
intros l l1 l2; revert l1 l2 l.
induction l1 as [ | x1 l1]; destruct l2 as [ | x2 l2];
simpl; auto; intros l H.
absurd (length (x2 :: l2 ++ l) <= length l).
simpl; rewrite app_length; auto with arith.
rewrite <- H; auto with arith.
absurd (length (x1 :: l1 ++ l) <= length l).
simpl; rewrite app_length; auto with arith.
rewrite H; auto with arith.
injection H as H H0; f_equal; eauto.
Qed.
End Facts.
Hint Resolve app_assoc app_assoc_reverse: datatypes.
Hint Resolve app_comm_cons app_cons_not_nil: datatypes.
Hint Immediate app_eq_nil: datatypes.
Hint Resolve app_eq_unit app_inj_tail: datatypes.
Hint Resolve in_eq in_cons in_inv in_nil in_app_or in_or_app: datatypes.
(*******************************************)
(** * Operations on the elements of a list *)
(*******************************************)
Section Elts.
Variable A : Type.
(*****************************)
(** ** Nth element of a list *)
(*****************************)
Fixpoint nth (n:nat) (l:list A) (default:A) {struct l} : A :=
match n, l with
| O, x :: l' => x
| O, other => default
| S m, [] => default
| S m, x :: t => nth m t default
end.
Fixpoint nth_ok (n:nat) (l:list A) (default:A) {struct l} : bool :=
match n, l with
| O, x :: l' => true
| O, other => false
| S m, [] => false
| S m, x :: t => nth_ok m t default
end.
Lemma nth_in_or_default :
forall (n:nat) (l:list A) (d:A), {In (nth n l d) l} + {nth n l d = d}.
Proof.
intros n l d; revert n; induction l.
- right; destruct n; trivial.
- intros [|n]; simpl.
* left; auto.
* destruct (IHl n); auto.
Qed.
Lemma nth_S_cons :
forall (n:nat) (l:list A) (d a:A),
In (nth n l d) l -> In (nth (S n) (a :: l) d) (a :: l).
Proof.
simpl; auto.
Qed.
Fixpoint nth_error (l:list A) (n:nat) {struct n} : option A :=
match n, l with
| O, x :: _ => Some x
| S n, _ :: l => nth_error l n
| _, _ => None
end.
Definition nth_default (default:A) (l:list A) (n:nat) : A :=
match nth_error l n with
| Some x => x
| None => default
end.
Lemma nth_default_eq :
forall n l (d:A), nth_default d l n = nth n l d.
Proof.
unfold nth_default; induction n; intros [ | ] ?; simpl; auto.
Qed.
(** Results about [nth] *)
Lemma nth_In :
forall (n:nat) (l:list A) (d:A), n < length l -> In (nth n l d) l.
Proof.
unfold lt; induction n as [| n hn]; simpl.
- destruct l; simpl; [ inversion 2 | auto ].
- destruct l; simpl.
* inversion 2.
* intros d ie; right; apply hn; auto with arith.
Qed.
Lemma In_nth l x d : In x l ->
exists n, n < length l /\ nth n l d = x.
Proof.
induction l as [|a l IH].
- easy.
- intros [H|H].
* subst; exists 0; simpl; auto with arith.
* destruct (IH H) as (n & Hn & Hn').
exists (S n); simpl; auto with arith.
Qed.
Lemma nth_overflow : forall l n d, length l <= n -> nth n l d = d.
Proof.
induction l; destruct n; simpl; intros; auto.
- inversion H.
- apply IHl; auto with arith.
Qed.
Lemma nth_indep :
forall l n d d', n < length l -> nth n l d = nth n l d'.
Proof.
induction l.
- inversion 1.
- intros [|n] d d'; simpl; auto with arith.
Qed.
Lemma app_nth1 :
forall l l' d n, n < length l -> nth n (l++l') d = nth n l d.
Proof.
induction l.
- inversion 1.
- intros l' d [|n]; simpl; auto with arith.
Qed.
Lemma app_nth2 :
forall l l' d n, n >= length l -> nth n (l++l') d = nth (n-length l) l' d.
Proof.
induction l; intros l' d [|n]; auto.
- inversion 1.
- intros; simpl; rewrite IHl; auto with arith.
Qed.
Lemma nth_split n l d : n < length l ->
exists l1, exists l2, l = l1 ++ nth n l d :: l2 /\ length l1 = n.
Proof.
revert l.
induction n as [|n IH]; intros [|a l] H; try easy.
- exists nil; exists l; now simpl.
- destruct (IH l) as (l1 & l2 & Hl & Hl1); auto with arith.
exists (a::l1); exists l2; simpl; split; now f_equal.
Qed.
(** Results about [nth_error] *)
Lemma nth_error_In l n x : nth_error l n = Some x -> In x l.
Proof.
revert n. induction l as [|a l IH]; intros [|n]; simpl; try easy.
- injection 1; auto.
- eauto.
Qed.
Lemma In_nth_error l x : In x l -> exists n, nth_error l n = Some x.
Proof.
induction l as [|a l IH].
- easy.
- intros [H|H].
* subst; exists 0; simpl; auto with arith.
* destruct (IH H) as (n,Hn).
exists (S n); simpl; auto with arith.
Qed.
Lemma nth_error_None l n : nth_error l n = None <-> length l <= n.
Proof.
revert n. induction l; destruct n; simpl.
- split; auto.
- split; auto with arith.
- split; now auto with arith.
- rewrite IHl; split; auto with arith.
Qed.
Lemma nth_error_Some l n : nth_error l n <> None <-> n < length l.
Proof.
revert n. induction l; destruct n; simpl.
- split; [now destruct 1 | inversion 1].
- split; [now destruct 1 | inversion 1].
- split; now auto with arith.
- rewrite IHl; split; auto with arith.
Qed.
Lemma nth_error_split l n a : nth_error l n = Some a ->
exists l1, exists l2, l = l1 ++ a :: l2 /\ length l1 = n.
Proof.
revert l.
induction n as [|n IH]; intros [|x l] H; simpl in *; try easy.
- exists nil; exists l. now injection H as ->.
- destruct (IH _ H) as (l1 & l2 & H1 & H2).
exists (x::l1); exists l2; simpl; split; now f_equal.
Qed.
Lemma nth_error_app1 l l' n : n < length l ->
nth_error (l++l') n = nth_error l n.
Proof.
revert l.
induction n; intros [|a l] H; auto; try solve [inversion H].
simpl in *. apply IHn. auto with arith.
Qed.
Lemma nth_error_app2 l l' n : length l <= n ->
nth_error (l++l') n = nth_error l' (n-length l).
Proof.
revert l.
induction n; intros [|a l] H; auto; try solve [inversion H].
simpl in *. apply IHn. auto with arith.
Qed.
(*****************)
(** ** Remove *)
(*****************)
Hypothesis eq_dec : forall x y : A, {x = y}+{x <> y}.
Fixpoint remove (x : A) (l : list A) : list A :=
match l with
| [] => []
| y::tl => if (eq_dec x y) then remove x tl else y::(remove x tl)
end.
Theorem remove_In : forall (l : list A) (x : A), ~ In x (remove x l).
Proof.
induction l as [|x l]; auto.
intro y; simpl; destruct (eq_dec y x) as [yeqx | yneqx].
apply IHl.
unfold not; intro HF; simpl in HF; destruct HF; auto.
apply (IHl y); assumption.
Qed.
(******************************)
(** ** Last element of a list *)
(******************************)
(** [last l d] returns the last element of the list [l],
or the default value [d] if [l] is empty. *)
Fixpoint last (l:list A) (d:A) : A :=
match l with
| [] => d
| [a] => a
| a :: l => last l d
end.
(** [removelast l] remove the last element of [l] *)
Fixpoint removelast (l:list A) : list A :=
match l with
| [] => []
| [a] => []
| a :: l => a :: removelast l
end.
Lemma app_removelast_last :
forall l d, l <> [] -> l = removelast l ++ [last l d].
Proof.
induction l.
destruct 1; auto.
intros d _.
destruct l; auto.
pattern (a0::l) at 1; rewrite IHl with d; auto; discriminate.
Qed.
Lemma exists_last :
forall l, l <> [] -> { l' : (list A) & { a : A | l = l' ++ [a]}}.
Proof.
induction l.
destruct 1; auto.
intros _.
destruct l.
exists [], a; auto.
destruct IHl as [l' (a',H)]; try discriminate.
rewrite H.
exists (a::l'), a'; auto.
Qed.
Lemma removelast_app :
forall l l', l' <> [] -> removelast (l++l') = l ++ removelast l'.
Proof.
induction l.
simpl; auto.
simpl; intros.
assert (l++l' <> []).
destruct l.
simpl; auto.
simpl; discriminate.
specialize (IHl l' H).
destruct (l++l'); [elim H0; auto|f_equal; auto].
Qed.
(******************************************)
(** ** Counting occurrences of an element *)
(******************************************)
Fixpoint count_occ (l : list A) (x : A) : nat :=
match l with
| [] => 0
| y :: tl =>
let n := count_occ tl x in
if eq_dec y x then S n else n
end.
(** Compatibility of count_occ with operations on list *)
Theorem count_occ_In l x : In x l <-> count_occ l x > 0.
Proof.
induction l as [|y l]; simpl.
- split; [destruct 1 | apply gt_irrefl].
- destruct eq_dec as [->|Hneq]; rewrite IHl; intuition.
Qed.
Theorem count_occ_not_In l x : ~ In x l <-> count_occ l x = 0.
Proof.
rewrite count_occ_In. unfold gt. now rewrite Nat.nlt_ge, Nat.le_0_r.
Qed.
Lemma count_occ_nil x : count_occ [] x = 0.
Proof.
reflexivity.
Qed.
Theorem count_occ_inv_nil l :
(forall x:A, count_occ l x = 0) <-> l = [].
Proof.
split.
- induction l as [|x l]; trivial.
intros H. specialize (H x). simpl in H.
destruct eq_dec as [_|NEQ]; [discriminate|now elim NEQ].
- now intros ->.
Qed.
Lemma count_occ_cons_eq l x y :
x = y -> count_occ (x::l) y = S (count_occ l y).
Proof.
intros H. simpl. now destruct (eq_dec x y).
Qed.
Lemma count_occ_cons_neq l x y :
x <> y -> count_occ (x::l) y = count_occ l y.
Proof.
intros H. simpl. now destruct (eq_dec x y).
Qed.
End Elts.
(*******************************)
(** * Manipulating whole lists *)
(*******************************)
Section ListOps.
Variable A : Type.
(*************************)
(** ** Reverse *)
(*************************)
Fixpoint rev (l:list A) : list A :=
match l with
| [] => []
| x :: l' => rev l' ++ [x]
end.
Lemma rev_app_distr : forall x y:list A, rev (x ++ y) = rev y ++ rev x.
Proof.
induction x as [| a l IHl].
destruct y as [| a l].
simpl.
auto.
simpl.
rewrite app_nil_r; auto.
intro y.
simpl.
rewrite (IHl y).
rewrite app_assoc; trivial.
Qed.
Remark rev_unit : forall (l:list A) (a:A), rev (l ++ [a]) = a :: rev l.
Proof.
intros.
apply (rev_app_distr l [a]); simpl; auto.
Qed.
Lemma rev_involutive : forall l:list A, rev (rev l) = l.
Proof.
induction l as [| a l IHl].
simpl; auto.
simpl.
rewrite (rev_unit (rev l) a).
rewrite IHl; auto.
Qed.
(** Compatibility with other operations *)
Lemma in_rev : forall l x, In x l <-> In x (rev l).
Proof.
induction l.
simpl; intuition.
intros.
simpl.
intuition.
subst.
apply in_or_app; right; simpl; auto.
apply in_or_app; left; firstorder.
destruct (in_app_or _ _ _ H); firstorder.
Qed.
Lemma rev_length : forall l, length (rev l) = length l.
Proof.
induction l;simpl; auto.
rewrite app_length.
rewrite IHl.
simpl.
elim (length l); simpl; auto.
Qed.
Lemma rev_nth : forall l d n, n < length l ->
nth n (rev l) d = nth (length l - S n) l d.
Proof.
induction l.
intros; inversion H.
intros.
simpl in H.
simpl (rev (a :: l)).
simpl (length (a :: l) - S n).
inversion H.
rewrite <- minus_n_n; simpl.
rewrite <- rev_length.
rewrite app_nth2; auto.
rewrite <- minus_n_n; auto.
rewrite app_nth1; auto.
rewrite (minus_plus_simpl_l_reverse (length l) n 1).
replace (1 + length l) with (S (length l)); auto with arith.
rewrite <- minus_Sn_m; auto with arith.
apply IHl ; auto with arith.
rewrite rev_length; auto.
Qed.
(** An alternative tail-recursive definition for reverse *)
Fixpoint rev_append (l l': list A) : list A :=
match l with
| [] => l'
| a::l => rev_append l (a::l')
end.
Definition rev' l : list A := rev_append l [].
Lemma rev_append_rev : forall l l', rev_append l l' = rev l ++ l'.
Proof.
induction l; simpl; auto; intros.
rewrite <- app_assoc; firstorder.
Qed.
Lemma rev_alt : forall l, rev l = rev_append l [].
Proof.
intros; rewrite rev_append_rev.
rewrite app_nil_r; trivial.
Qed.
(*********************************************)
(** Reverse Induction Principle on Lists *)
(*********************************************)
Section Reverse_Induction.
Lemma rev_list_ind :
forall P:list A-> Prop,
P [] ->
(forall (a:A) (l:list A), P (rev l) -> P (rev (a :: l))) ->
forall l:list A, P (rev l).
Proof.
induction l; auto.
Qed.
Theorem rev_ind :
forall P:list A -> Prop,
P [] ->
(forall (x:A) (l:list A), P l -> P (l ++ [x])) -> forall l:list A, P l.
Proof.
intros.
generalize (rev_involutive l).
intros E; rewrite <- E.
apply (rev_list_ind P).
auto.
simpl.
intros.
apply (H0 a (rev l0)).
auto.
Qed.
End Reverse_Induction.
(*************************)
(** ** Concatenation *)
(*************************)
Fixpoint concat (l : list (list A)) : list A :=
match l with
| nil => nil
| cons x l => x ++ concat l
end.
Lemma concat_nil : concat nil = nil.
Proof.
reflexivity.
Qed.
Lemma concat_cons : forall x l, concat (cons x l) = x ++ concat l.
Proof.
reflexivity.
Qed.
Lemma concat_app : forall l1 l2, concat (l1 ++ l2) = concat l1 ++ concat l2.
Proof.
intros l1; induction l1 as [|x l1 IH]; intros l2; simpl.
+ reflexivity.
+ rewrite IH; apply app_assoc.
Qed.
(***********************************)
(** ** Decidable equality on lists *)
(***********************************)
Hypothesis eq_dec : forall (x y : A), {x = y}+{x <> y}.
Lemma list_eq_dec : forall l l':list A, {l = l'} + {l <> l'}.
Proof. decide equality. Defined.
End ListOps.
(***************************************************)
(** * Applying functions to the elements of a list *)
(***************************************************)
(************)
(** ** Map *)
(************)
Section Map.
Variables (A : Type) (B : Type).
Variable f : A -> B.
Fixpoint map (l:list A) : list B :=
match l with
| [] => []
| a :: t => (f a) :: (map t)
end.
Lemma map_cons (x:A)(l:list A) : map (x::l) = (f x) :: (map l).
Proof.
reflexivity.
Qed.
Lemma in_map :
forall (l:list A) (x:A), In x l -> In (f x) (map l).
Proof.
induction l; firstorder (subst; auto).
Qed.
Lemma in_map_iff : forall l y, In y (map l) <-> exists x, f x = y /\ In x l.
Proof.
induction l; firstorder (subst; auto).
Qed.
Lemma map_length : forall l, length (map l) = length l.
Proof.
induction l; simpl; auto.
Qed.
Lemma map_nth : forall l d n,
nth n (map l) (f d) = f (nth n l d).
Proof.
induction l; simpl map; destruct n; firstorder.
Qed.
Lemma map_nth_error : forall n l d,
nth_error l n = Some d -> nth_error (map l) n = Some (f d).
Proof.
induction n; intros [ | ] ? Heq; simpl in *; inversion Heq; auto.
Qed.
Lemma map_app : forall l l',
map (l++l') = (map l)++(map l').
Proof.
induction l; simpl; auto.
intros; rewrite IHl; auto.
Qed.
Lemma map_rev : forall l, map (rev l) = rev (map l).
Proof.
induction l; simpl; auto.
rewrite map_app.
rewrite IHl; auto.
Qed.
Lemma map_eq_nil : forall l, map l = [] -> l = [].
Proof.
destruct l; simpl; reflexivity || discriminate.
Qed.
(** [map] and count of occurrences *)
Hypothesis decA: forall x1 x2 : A, {x1 = x2} + {x1 <> x2}.
Hypothesis decB: forall y1 y2 : B, {y1 = y2} + {y1 <> y2}.
Hypothesis Hfinjective: forall x1 x2: A, (f x1) = (f x2) -> x1 = x2.
Theorem count_occ_map x l:
count_occ decA l x = count_occ decB (map l) (f x).
Proof.
revert x. induction l as [| a l' Hrec]; intro x; simpl.
- reflexivity.
- specialize (Hrec x).
destruct (decA a x) as [H1|H1], (decB (f a) (f x)) as [H2|H2].
* rewrite Hrec. reflexivity.
* contradiction H2. rewrite H1. reflexivity.
* specialize (Hfinjective H2). contradiction H1.
* assumption.
Qed.
(** [flat_map] *)
Definition flat_map (f:A -> list B) :=
fix flat_map (l:list A) : list B :=
match l with
| nil => nil
| cons x t => (f x)++(flat_map t)
end.
Lemma in_flat_map : forall (f:A->list B)(l:list A)(y:B),
In y (flat_map f l) <-> exists x, In x l /\ In y (f x).
Proof using A B.
clear Hfinjective.
induction l; simpl; split; intros.
contradiction.
destruct H as (x,(H,_)); contradiction.
destruct (in_app_or _ _ _ H).
exists a; auto.
destruct (IHl y) as (H1,_); destruct (H1 H0) as (x,(H2,H3)).
exists x; auto.
apply in_or_app.
destruct H as (x,(H0,H1)); destruct H0.
subst; auto.
right; destruct (IHl y) as (_,H2); apply H2.
exists x; auto.
Qed.
End Map.
Lemma flat_map_concat_map : forall A B (f : A -> list B) l,
flat_map f l = concat (map f l).
Proof.
intros A B f l; induction l as [|x l IH]; simpl.
+ reflexivity.
+ rewrite IH; reflexivity.
Qed.
Lemma concat_map : forall A B (f : A -> B) l, map f (concat l) = concat (map (map f) l).
Proof.
intros A B f l; induction l as [|x l IH]; simpl.
+ reflexivity.
+ rewrite map_app, IH; reflexivity.
Qed.
Lemma map_id : forall (A :Type) (l : list A),
map (fun x => x) l = l.
Proof.
induction l; simpl; auto; rewrite IHl; auto.
Qed.
Lemma map_map : forall (A B C:Type)(f:A->B)(g:B->C) l,
map g (map f l) = map (fun x => g (f x)) l.
Proof.
induction l; simpl; auto.
rewrite IHl; auto.
Qed.
Lemma map_ext_in :
forall (A B : Type)(f g:A->B) l, (forall a, In a l -> f a = g a) -> map f l = map g l.
Proof.
induction l; simpl; auto.
intros; rewrite H by intuition; rewrite IHl; auto.
Qed.
Lemma ext_in_map :
forall (A B : Type)(f g:A->B) l, map f l = map g l -> forall a, In a l -> f a = g a.
Proof. induction l; intros [=] ? []; subst; auto. Qed.
Arguments ext_in_map [A B f g l].
Lemma map_ext_in_iff :
forall (A B : Type)(f g:A->B) l, map f l = map g l <-> forall a, In a l -> f a = g a.
Proof. split; [apply ext_in_map | apply map_ext_in]. Qed.
Arguments map_ext_in_iff {A B f g l}.
Lemma map_ext :
forall (A B : Type)(f g:A->B), (forall a, f a = g a) -> forall l, map f l = map g l.
Proof.
intros; apply map_ext_in; auto.
Qed.
(************************************)
(** Left-to-right iterator on lists *)
(************************************)
Section Fold_Left_Recursor.
Variables (A : Type) (B : Type).
Variable f : A -> B -> A.
Fixpoint fold_left (l:list B) (a0:A) : A :=
match l with
| nil => a0
| cons b t => fold_left t (f a0 b)
end.
Lemma fold_left_app : forall (l l':list B)(i:A),
fold_left (l++l') i = fold_left l' (fold_left l i).
Proof.
induction l.
simpl; auto.
intros.
simpl.
auto.
Qed.
End Fold_Left_Recursor.
Lemma fold_left_length :
forall (A:Type)(l:list A), fold_left (fun x _ => S x) l 0 = length l.
Proof.
intros A l.
enough (H : forall n, fold_left (fun x _ => S x) l n = n + length l) by exact (H 0).
induction l; simpl; auto.
intros; rewrite IHl.
simpl; auto with arith.
Qed.
(************************************)
(** Right-to-left iterator on lists *)
(************************************)
Section Fold_Right_Recursor.
Variables (A : Type) (B : Type).
Variable f : B -> A -> A.
Variable a0 : A.
Fixpoint fold_right (l:list B) : A :=
match l with
| nil => a0
| cons b t => f b (fold_right t)
end.
End Fold_Right_Recursor.
Lemma fold_right_app : forall (A B:Type)(f:A->B->B) l l' i,
fold_right f i (l++l') = fold_right f (fold_right f i l') l.
Proof.
induction l.
simpl; auto.
simpl; intros.
f_equal; auto.
Qed.
Lemma fold_left_rev_right : forall (A B:Type)(f:A->B->B) l i,
fold_right f i (rev l) = fold_left (fun x y => f y x) l i.
Proof.
induction l.
simpl; auto.
intros.
simpl.
rewrite fold_right_app; simpl; auto.
Qed.
Theorem fold_symmetric :
forall (A : Type) (f : A -> A -> A),
(forall x y z : A, f x (f y z) = f (f x y) z) ->
forall (a0 : A), (forall y : A, f a0 y = f y a0) ->
forall (l : list A), fold_left f l a0 = fold_right f a0 l.
Proof.
intros A f assoc a0 comma0 l.
induction l as [ | a1 l ]; [ simpl; reflexivity | ].
simpl. rewrite <- IHl. clear IHl. revert a1. induction l; [ auto | ].
simpl. intro. rewrite <- assoc. rewrite IHl. rewrite IHl. auto.
Qed.
(** [(list_power x y)] is [y^x], or the set of sequences of elts of [y]
indexed by elts of [x], sorted in lexicographic order. *)
Fixpoint list_power (A B:Type)(l:list A) (l':list B) :
list (list (A * B)) :=
match l with
| nil => cons nil nil
| cons x t =>
flat_map (fun f:list (A * B) => map (fun y:B => cons (x, y) f) l')
(list_power t l')
end.
(*************************************)
(** ** Boolean operations over lists *)
(*************************************)
Section Bool.
Variable A : Type.
Variable f : A -> bool.
(** find whether a boolean function can be satisfied by an
elements of the list. *)
Fixpoint existsb (l:list A) : bool :=
match l with
| nil => false
| a::l => f a || existsb l
end.
Lemma existsb_exists :
forall l, existsb l = true <-> exists x, In x l /\ f x = true.
Proof.
induction l; simpl; intuition.
inversion H.
firstorder.
destruct (orb_prop _ _ H1); firstorder.
firstorder.
subst.
rewrite H2; auto.
Qed.
Lemma existsb_nth : forall l n d, n < length l ->
existsb l = false -> f (nth n l d) = false.
Proof.
induction l.
inversion 1.
simpl; intros.
destruct (orb_false_elim _ _ H0); clear H0; auto.
destruct n ; auto.
rewrite IHl; auto with arith.
Qed.
Lemma existsb_app : forall l1 l2,
existsb (l1++l2) = existsb l1 || existsb l2.
Proof.
induction l1; intros l2; simpl.
solve[auto].
case (f a); simpl; solve[auto].
Qed.
(** find whether a boolean function is satisfied by
all the elements of a list. *)
Fixpoint forallb (l:list A) : bool :=
match l with
| nil => true
| a::l => f a && forallb l
end.
Lemma forallb_forall :
forall l, forallb l = true <-> (forall x, In x l -> f x = true).
Proof.
induction l; simpl; intuition.
destruct (andb_prop _ _ H1).
congruence.
destruct (andb_prop _ _ H1); auto.
assert (forallb l = true).
apply H0; intuition.
rewrite H1; auto.
Qed.
Lemma forallb_app :
forall l1 l2, forallb (l1++l2) = forallb l1 && forallb l2.
Proof.
induction l1; simpl.
solve[auto].
case (f a); simpl; solve[auto].
Qed.
(** [filter] *)
Fixpoint filter (l:list A) : list A :=
match l with
| nil => nil
| x :: l => if f x then x::(filter l) else filter l
end.
Lemma filter_In : forall x l, In x (filter l) <-> In x l /\ f x = true.
Proof.
induction l; simpl.
intuition.
intros.
case_eq (f a); intros; simpl; intuition congruence.
Qed.
(** [find] *)
Fixpoint find (l:list A) : option A :=
match l with
| nil => None
| x :: tl => if f x then Some x else find tl
end.
Lemma find_some l x : find l = Some x -> In x l /\ f x = true.
Proof.
induction l as [|a l IH]; simpl; [easy| ].
case_eq (f a); intros Ha Eq.
* injection Eq as ->; auto.
* destruct (IH Eq); auto.
Qed.
Lemma find_none l : find l = None -> forall x, In x l -> f x = false.
Proof.
induction l as [|a l IH]; simpl; [easy|].
case_eq (f a); intros Ha Eq x IN; [easy|].
destruct IN as [<-|IN]; auto.
Qed.
(** [partition] *)
Fixpoint partition (l:list A) : list A * list A :=
match l with
| nil => (nil, nil)
| x :: tl => let (g,d) := partition tl in
if f x then (x::g,d) else (g,x::d)
end.
Theorem partition_cons1 a l l1 l2:
partition l = (l1, l2) ->
f a = true ->
partition (a::l) = (a::l1, l2).
Proof.
simpl. now intros -> ->.
Qed.
Theorem partition_cons2 a l l1 l2:
partition l = (l1, l2) ->
f a=false ->
partition (a::l) = (l1, a::l2).
Proof.
simpl. now intros -> ->.
Qed.
Theorem partition_length l l1 l2:
partition l = (l1, l2) ->
length l = length l1 + length l2.
Proof.
revert l1 l2. induction l as [ | a l' Hrec]; intros l1 l2.
- now intros [= <- <- ].
- simpl. destruct (f a), (partition l') as (left, right);
intros [= <- <- ]; simpl; rewrite (Hrec left right); auto.
Qed.
Theorem partition_inv_nil (l : list A):
partition l = ([], []) <-> l = [].
Proof.
split.
- destruct l as [|a l'].
* intuition.
* simpl. destruct (f a), (partition l'); now intros [= -> ->].
- now intros ->.
Qed.
Theorem elements_in_partition l l1 l2:
partition l = (l1, l2) ->
forall x:A, In x l <-> In x l1 \/ In x l2.
Proof.
revert l1 l2. induction l as [| a l' Hrec]; simpl; intros l1 l2 Eq x.
- injection Eq as <- <-. tauto.
- destruct (partition l') as (left, right).
specialize (Hrec left right eq_refl x).
destruct (f a); injection Eq as <- <-; simpl; tauto.
Qed.
End Bool.
(******************************************************)
(** ** Operations on lists of pairs or lists of lists *)
(******************************************************)
Section ListPairs.
Variables (A : Type) (B : Type).
(** [split] derives two lists from a list of pairs *)
Fixpoint split (l:list (A*B)) : list A * list B :=
match l with
| [] => ([], [])
| (x,y) :: tl => let (left,right) := split tl in (x::left, y::right)
end.
Lemma in_split_l : forall (l:list (A*B))(p:A*B),
In p l -> In (fst p) (fst (split l)).
Proof.
induction l; simpl; intros; auto.
destruct p; destruct a; destruct (split l); simpl in *.
destruct H.
injection H; auto.
right; apply (IHl (a0,b) H).
Qed.
Lemma in_split_r : forall (l:list (A*B))(p:A*B),
In p l -> In (snd p) (snd (split l)).
Proof.
induction l; simpl; intros; auto.
destruct p; destruct a; destruct (split l); simpl in *.
destruct H.
injection H; auto.
right; apply (IHl (a0,b) H).
Qed.
Lemma split_nth : forall (l:list (A*B))(n:nat)(d:A*B),
nth n l d = (nth n (fst (split l)) (fst d), nth n (snd (split l)) (snd d)).
Proof.
induction l.
destruct n; destruct d; simpl; auto.
destruct n; destruct d; simpl; auto.
destruct a; destruct (split l); simpl; auto.
destruct a; destruct (split l); simpl in *; auto.
apply IHl.
Qed.
Lemma split_length_l : forall (l:list (A*B)),
length (fst (split l)) = length l.
Proof.
induction l; simpl; auto.
destruct a; destruct (split l); simpl; auto.
Qed.
Lemma split_length_r : forall (l:list (A*B)),
length (snd (split l)) = length l.
Proof.
induction l; simpl; auto.
destruct a; destruct (split l); simpl; auto.
Qed.
(** [combine] is the opposite of [split].
Lists given to [combine] are meant to be of same length.
If not, [combine] stops on the shorter list *)
Fixpoint combine (l : list A) (l' : list B) : list (A*B) :=
match l,l' with
| x::tl, y::tl' => (x,y)::(combine tl tl')
| _, _ => nil
end.
Lemma split_combine : forall (l: list (A*B)),
let (l1,l2) := split l in combine l1 l2 = l.
Proof.
induction l.
simpl; auto.
destruct a; simpl.
destruct (split l); simpl in *.
f_equal; auto.
Qed.
Lemma combine_split : forall (l:list A)(l':list B), length l = length l' ->
split (combine l l') = (l,l').
Proof.
induction l, l'; simpl; trivial; try discriminate.
now intros [= ->%IHl].
Qed.
Lemma in_combine_l : forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (combine l l') -> In x l.
Proof.
induction l.
simpl; auto.
destruct l'; simpl; auto; intros.
contradiction.
destruct H.
injection H; auto.
right; apply IHl with l' y; auto.
Qed.
Lemma in_combine_r : forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (combine l l') -> In y l'.
Proof.
induction l.
simpl; intros; contradiction.
destruct l'; simpl; auto; intros.
destruct H.
injection H; auto.
right; apply IHl with x; auto.
Qed.
Lemma combine_length : forall (l:list A)(l':list B),
length (combine l l') = min (length l) (length l').
Proof.
induction l.
simpl; auto.
destruct l'; simpl; auto.
Qed.
Lemma combine_nth : forall (l:list A)(l':list B)(n:nat)(x:A)(y:B),
length l = length l' ->
nth n (combine l l') (x,y) = (nth n l x, nth n l' y).
Proof.
induction l; destruct l'; intros; try discriminate.
destruct n; simpl; auto.
destruct n; simpl in *; auto.
Qed.
(** [list_prod] has the same signature as [combine], but unlike
[combine], it adds every possible pairs, not only those at the
same position. *)
Fixpoint list_prod (l:list A) (l':list B) :
list (A * B) :=
match l with
| nil => nil
| cons x t => (map (fun y:B => (x, y)) l')++(list_prod t l')
end.
Lemma in_prod_aux :
forall (x:A) (y:B) (l:list B),
In y l -> In (x, y) (map (fun y0:B => (x, y0)) l).
Proof.
induction l;
[ simpl; auto
| simpl; destruct 1 as [H1| ];
[ left; rewrite H1; trivial | right; auto ] ].
Qed.
Lemma in_prod :
forall (l:list A) (l':list B) (x:A) (y:B),
In x l -> In y l' -> In (x, y) (list_prod l l').
Proof.
induction l;
[ simpl; tauto
| simpl; intros; apply in_or_app; destruct H;
[ left; rewrite H; apply in_prod_aux; assumption | right; auto ] ].
Qed.
Lemma in_prod_iff :
forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (list_prod l l') <-> In x l /\ In y l'.
Proof.
split; [ | intros; apply in_prod; intuition ].
induction l; simpl; intros.
intuition.
destruct (in_app_or _ _ _ H); clear H.
destruct (in_map_iff (fun y : B => (a, y)) l' (x,y)) as (H1,_).
destruct (H1 H0) as (z,(H2,H3)); clear H0 H1.
injection H2 as -> ->; intuition.
intuition.
Qed.
Lemma prod_length : forall (l:list A)(l':list B),
length (list_prod l l') = (length l) * (length l').
Proof.
induction l; simpl; auto.
intros.
rewrite app_length.
rewrite map_length.
auto.
Qed.
End ListPairs.
(*****************************************)
(** * Miscellaneous operations on lists *)
(*****************************************)
(******************************)
(** ** Length order of lists *)
(******************************)
Section length_order.
Variable A : Type.
Definition lel (l m:list A) := length l <= length m.
Variables a b : A.
Variables l m n : list A.
Lemma lel_refl : lel l l.
Proof.
unfold lel; auto with arith.
Qed.
Lemma lel_trans : lel l m -> lel m n -> lel l n.
Proof.
unfold lel; intros.
now_show (length l <= length n).
apply le_trans with (length m); auto with arith.
Qed.
Lemma lel_cons_cons : lel l m -> lel (a :: l) (b :: m).
Proof.
unfold lel; simpl; auto with arith.
Qed.
Lemma lel_cons : lel l m -> lel l (b :: m).
Proof.
unfold lel; simpl; auto with arith.
Qed.
Lemma lel_tail : lel (a :: l) (b :: m) -> lel l m.
Proof.
unfold lel; simpl; auto with arith.
Qed.
Lemma lel_nil : forall l':list A, lel l' nil -> nil = l'.
Proof.
intro l'; elim l'; auto with arith.
intros a' y H H0.
now_show (nil = a' :: y).
absurd (S (length y) <= 0); auto with arith.
Qed.
End length_order.
Hint Resolve lel_refl lel_cons_cons lel_cons lel_nil lel_nil nil_cons:
datatypes.
(******************************)
(** ** Set inclusion on list *)
(******************************)
Section SetIncl.
Variable A : Type.
Definition incl (l m:list A) := forall a:A, In a l -> In a m.
Hint Unfold incl : core.
Lemma incl_refl : forall l:list A, incl l l.
Proof.
auto.
Qed.
Hint Resolve incl_refl : core.
Lemma incl_tl : forall (a:A) (l m:list A), incl l m -> incl l (a :: m).
Proof.
auto with datatypes.
Qed.
Hint Immediate incl_tl : core.
Lemma incl_tran : forall l m n:list A, incl l m -> incl m n -> incl l n.
Proof.
auto.
Qed.
Lemma incl_appl : forall l m n:list A, incl l n -> incl l (n ++ m).
Proof.
auto with datatypes.
Qed.
Hint Immediate incl_appl : core.
Lemma incl_appr : forall l m n:list A, incl l n -> incl l (m ++ n).
Proof.
auto with datatypes.
Qed.
Hint Immediate incl_appr : core.
Lemma incl_cons :
forall (a:A) (l m:list A), In a m -> incl l m -> incl (a :: l) m.
Proof.
unfold incl; simpl; intros a l m H H0 a0 H1.
now_show (In a0 m).
elim H1.
now_show (a = a0 -> In a0 m).
elim H1; auto; intro H2.
now_show (a = a0 -> In a0 m).
elim H2; auto. (* solves subgoal *)
now_show (In a0 l -> In a0 m).
auto.
Qed.
Hint Resolve incl_cons : core.
Lemma incl_app : forall l m n:list A, incl l n -> incl m n -> incl (l ++ m) n.
Proof.
unfold incl; simpl; intros l m n H H0 a H1.
now_show (In a n).
elim (in_app_or _ _ _ H1); auto.
Qed.
Hint Resolve incl_app : core.
End SetIncl.
Hint Resolve incl_refl incl_tl incl_tran incl_appl incl_appr incl_cons
incl_app: datatypes.
(**************************************)
(** * Cutting a list at some position *)
(**************************************)
Section Cutting.
Variable A : Type.
Fixpoint firstn (n:nat)(l:list A) : list A :=
match n with
| 0 => nil
| S n => match l with
| nil => nil
| a::l => a::(firstn n l)
end
end.
Lemma firstn_nil n: firstn n [] = [].
Proof. induction n; now simpl. Qed.
Lemma firstn_cons n a l: firstn (S n) (a::l) = a :: (firstn n l).
Proof. now simpl. Qed.
Lemma firstn_all l: firstn (length l) l = l.
Proof. induction l as [| ? ? H]; simpl; [reflexivity | now rewrite H]. Qed.
Lemma firstn_all2 n: forall (l:list A), (length l) <= n -> firstn n l = l.
Proof. induction n as [|k iHk].
- intro. inversion 1 as [H1|?].
rewrite (length_zero_iff_nil l) in H1. subst. now simpl.
- destruct l as [|x xs]; simpl.
* now reflexivity.
* simpl. intro H. apply Peano.le_S_n in H. f_equal. apply iHk, H.
Qed.
Lemma firstn_O l: firstn 0 l = [].
Proof. now simpl. Qed.
Lemma firstn_le_length n: forall l:list A, length (firstn n l) <= n.
Proof.
induction n as [|k iHk]; simpl; [auto | destruct l as [|x xs]; simpl].
- auto with arith.
- apply Peano.le_n_S, iHk.
Qed.
Lemma firstn_length_le: forall l:list A, forall n:nat,
n <= length l -> length (firstn n l) = n.
Proof. induction l as [|x xs Hrec].
- simpl. intros n H. apply le_n_0_eq in H. rewrite <- H. now simpl.
- destruct n.
* now simpl.
* simpl. intro H. apply le_S_n in H. now rewrite (Hrec n H).
Qed.
Lemma firstn_app n:
forall l1 l2,
firstn n (l1 ++ l2) = (firstn n l1) ++ (firstn (n - length l1) l2).
Proof. induction n as [|k iHk]; intros l1 l2.
- now simpl.
- destruct l1 as [|x xs].
* unfold firstn at 2, length. now rewrite 2!app_nil_l, <- minus_n_O.
* rewrite <- app_comm_cons. simpl. f_equal. apply iHk.
Qed.
Lemma firstn_app_2 n:
forall l1 l2,
firstn ((length l1) + n) (l1 ++ l2) = l1 ++ firstn n l2.
Proof. induction n as [| k iHk];intros l1 l2.
- unfold firstn at 2. rewrite <- plus_n_O, app_nil_r.
rewrite firstn_app. rewrite <- minus_diag_reverse.
unfold firstn at 2. rewrite app_nil_r. apply firstn_all.
- destruct l2 as [|x xs].
* simpl. rewrite app_nil_r. apply firstn_all2. auto with arith.
* rewrite firstn_app. assert (H0 : (length l1 + S k - length l1) = S k).
auto with arith.
rewrite H0, firstn_all2; [reflexivity | auto with arith].
Qed.
Lemma firstn_firstn:
forall l:list A,
forall i j : nat,
firstn i (firstn j l) = firstn (min i j) l.
Proof. induction l as [|x xs Hl].
- intros. simpl. now rewrite ?firstn_nil.
- destruct i.
* intro. now simpl.
* destruct j.
+ now simpl.
+ simpl. f_equal. apply Hl.
Qed.
Fixpoint skipn (n:nat)(l:list A) : list A :=
match n with
| 0 => l
| S n => match l with
| nil => nil
| a::l => skipn n l
end
end.
Lemma firstn_skipn_comm : forall m n l,
firstn m (skipn n l) = skipn n (firstn (n + m) l).
Proof. now intros m; induction n; intros []; simpl; destruct m. Qed.
Lemma skipn_firstn_comm : forall m n l,
skipn m (firstn n l) = firstn (n - m) (skipn m l).
Proof. now induction m; intros [] []; simpl; rewrite ?firstn_nil. Qed.
Lemma skipn_O : forall l, skipn 0 l = l.
Proof. reflexivity. Qed.
Lemma skipn_nil : forall n, skipn n ([] : list A) = [].
Proof. now intros []. Qed.
Lemma skipn_cons n a l: skipn (S n) (a::l) = skipn n l.
Proof. reflexivity. Qed.
Lemma skipn_none : forall l, skipn (length l) l = [].
Proof. now induction l. Qed.
Lemma skipn_all2 n: forall l, length l <= n -> skipn n l = [].
Proof.
intros l L%Nat.sub_0_le; rewrite <-(firstn_all l) at 1.
now rewrite skipn_firstn_comm, L.
Qed.
Lemma firstn_skipn : forall n l, firstn n l ++ skipn n l = l.
Proof.
induction n.
simpl; auto.
destruct l; simpl; auto.
f_equal; auto.
Qed.
Lemma firstn_length : forall n l, length (firstn n l) = min n (length l).
Proof.
induction n; destruct l; simpl; auto.
Qed.
Lemma skipn_length n :
forall l, length (skipn n l) = length l - n.
Proof.
induction n.
- intros l; simpl; rewrite Nat.sub_0_r; reflexivity.
- destruct l; simpl; auto.
Qed.
Lemma skipn_all l: skipn (length l) l = nil.
Proof. now induction l. Qed.
Lemma skipn_app n : forall l1 l2,
skipn n (l1 ++ l2) = (skipn n l1) ++ (skipn (n - length l1) l2).
Proof. induction n; auto; intros [|]; simpl; auto. Qed.
Lemma firstn_skipn_rev: forall x l,
firstn x l = rev (skipn (length l - x) (rev l)).
Proof.
intros x l; rewrite <-(firstn_skipn x l) at 3.
rewrite rev_app_distr, skipn_app, rev_app_distr, rev_length,
skipn_length, Nat.sub_diag; simpl; rewrite rev_involutive.
rewrite <-app_nil_r at 1; f_equal; symmetry; apply length_zero_iff_nil.
repeat rewrite rev_length, skipn_length; apply Nat.sub_diag.
Qed.
Lemma firstn_rev: forall x l,
firstn x (rev l) = rev (skipn (length l - x) l).
Proof.
now intros x l; rewrite firstn_skipn_rev, rev_involutive, rev_length.
Qed.
Lemma skipn_rev: forall x l,
skipn x (rev l) = rev (firstn (length l - x) l).
Proof.
intros x l; rewrite firstn_skipn_rev, rev_involutive, <-rev_length.
destruct (Nat.le_ge_cases (length (rev l)) x) as [L | L].
- rewrite skipn_all2; [apply Nat.sub_0_le in L | trivial].
now rewrite L, Nat.sub_0_r, skipn_none.
- replace (length (rev l) - (length (rev l) - x))
with (length (rev l) + x - length (rev l)).
rewrite minus_plus. reflexivity.
rewrite <- (Nat.sub_add _ _ L) at 2.
now rewrite <-!(Nat.add_comm x), <-minus_plus_simpl_l_reverse.
Qed.
Lemma removelast_firstn : forall n l, n < length l ->
removelast (firstn (S n) l) = firstn n l.
Proof.
induction n; destruct l.
simpl; auto.
simpl; auto.
simpl; auto.
intros.
simpl in H.
change (firstn (S (S n)) (a::l)) with ((a::nil)++firstn (S n) l).
change (firstn (S n) (a::l)) with (a::firstn n l).
rewrite removelast_app.
rewrite IHn; auto with arith.
clear IHn; destruct l; simpl in *; try discriminate.
inversion_clear H.
inversion_clear H0.
Qed.
Lemma firstn_removelast : forall n l, n < length l ->
firstn n (removelast l) = firstn n l.
Proof.
induction n; destruct l.
simpl; auto.
simpl; auto.
simpl; auto.
intros.
simpl in H.
change (removelast (a :: l)) with (removelast ((a::nil)++l)).
rewrite removelast_app.
simpl; f_equal; auto with arith.
intro H0; rewrite H0 in H; inversion_clear H; inversion_clear H1.
Qed.
End Cutting.
(**********************************************************************)
(** ** Predicate for List addition/removal (no need for decidability) *)
(**********************************************************************)
Section Add.
Variable A : Type.
(* [Add a l l'] means that [l'] is exactly [l], with [a] added
once somewhere *)
Inductive Add (a:A) : list A -> list A -> Prop :=
| Add_head l : Add a l (a::l)
| Add_cons x l l' : Add a l l' -> Add a (x::l) (x::l').
Lemma Add_app a l1 l2 : Add a (l1++l2) (l1++a::l2).
Proof.
induction l1; simpl; now constructor.
Qed.
Lemma Add_split a l l' :
Add a l l' -> exists l1 l2, l = l1++l2 /\ l' = l1++a::l2.
Proof.
induction 1.
- exists nil; exists l; split; trivial.
- destruct IHAdd as (l1 & l2 & Hl & Hl').
exists (x::l1); exists l2; split; simpl; f_equal; trivial.
Qed.
Lemma Add_in a l l' : Add a l l' ->
forall x, In x l' <-> In x (a::l).
Proof.
induction 1; intros; simpl in *; rewrite ?IHAdd; tauto.
Qed.
Lemma Add_length a l l' : Add a l l' -> length l' = S (length l).
Proof.
induction 1; simpl; auto with arith.
Qed.
Lemma Add_inv a l : In a l -> exists l', Add a l' l.
Proof.
intro Ha. destruct (in_split _ _ Ha) as (l1 & l2 & ->).
exists (l1 ++ l2). apply Add_app.
Qed.
Lemma incl_Add_inv a l u v :
~In a l -> incl (a::l) v -> Add a u v -> incl l u.
Proof.
intros Ha H AD y Hy.
assert (Hy' : In y (a::u)).
{ rewrite <- (Add_in AD). apply H; simpl; auto. }
destruct Hy'; [ subst; now elim Ha | trivial ].
Qed.
End Add.
(********************************)
(** ** Lists without redundancy *)
(********************************)
Section ReDun.
Variable A : Type.
Inductive NoDup : list A -> Prop :=
| NoDup_nil : NoDup nil
| NoDup_cons : forall x l, ~ In x l -> NoDup l -> NoDup (x::l).
Lemma NoDup_Add a l l' : Add a l l' -> (NoDup l' <-> NoDup l /\ ~In a l).
Proof.
induction 1 as [l|x l l' AD IH].
- split; [ inversion_clear 1; now split | now constructor ].
- split.
+ inversion_clear 1. rewrite IH in *. rewrite (Add_in AD) in *.
simpl in *; split; try constructor; intuition.
+ intros (N,IN). inversion_clear N. constructor.
* rewrite (Add_in AD); simpl in *; intuition.
* apply IH. split; trivial. simpl in *; intuition.
Qed.
Lemma NoDup_remove l l' a :
NoDup (l++a::l') -> NoDup (l++l') /\ ~In a (l++l').
Proof.
apply NoDup_Add. apply Add_app.
Qed.
Lemma NoDup_remove_1 l l' a : NoDup (l++a::l') -> NoDup (l++l').
Proof.
intros. now apply NoDup_remove with a.
Qed.
Lemma NoDup_remove_2 l l' a : NoDup (l++a::l') -> ~In a (l++l').
Proof.
intros. now apply NoDup_remove.
Qed.
Theorem NoDup_cons_iff a l:
NoDup (a::l) <-> ~ In a l /\ NoDup l.
Proof.
split.
+ inversion_clear 1. now split.
+ now constructor.
Qed.
(** Effective computation of a list without duplicates *)
Hypothesis decA: forall x y : A, {x = y} + {x <> y}.
Fixpoint nodup (l : list A) : list A :=
match l with
| [] => []
| x::xs => if in_dec decA x xs then nodup xs else x::(nodup xs)
end.
Lemma nodup_In l x : In x (nodup l) <-> In x l.
Proof.
induction l as [|a l' Hrec]; simpl.
- reflexivity.
- destruct (in_dec decA a l'); simpl; rewrite Hrec.
* intuition; now subst.
* reflexivity.
Qed.
Lemma NoDup_nodup l: NoDup (nodup l).
Proof.
induction l as [|a l' Hrec]; simpl.
- constructor.
- destruct (in_dec decA a l'); simpl.
* assumption.
* constructor; [ now rewrite nodup_In | assumption].
Qed.
Lemma nodup_inv k l a : nodup k = a :: l -> ~ In a l.
Proof.
intros H.
assert (H' : NoDup (a::l)).
{ rewrite <- H. apply NoDup_nodup. }
now inversion_clear H'.
Qed.
Theorem NoDup_count_occ l:
NoDup l <-> (forall x:A, count_occ decA l x <= 1).
Proof.
induction l as [| a l' Hrec].
- simpl; split; auto. constructor.
- rewrite NoDup_cons_iff, Hrec, (count_occ_not_In decA). clear Hrec. split.
+ intros (Ha, H) x. simpl. destruct (decA a x); auto.
subst; now rewrite Ha.
+ split.
* specialize (H a). rewrite count_occ_cons_eq in H; trivial.
now inversion H.
* intros x. specialize (H x). simpl in *. destruct (decA a x); auto.
now apply Nat.lt_le_incl.
Qed.
Theorem NoDup_count_occ' l:
NoDup l <-> (forall x:A, In x l -> count_occ decA l x = 1).
Proof.
rewrite NoDup_count_occ.
setoid_rewrite (count_occ_In decA). unfold gt, lt in *.
split; intros H x; specialize (H x);
set (n := count_occ decA l x) in *; clearbody n.
(* the rest would be solved by omega if we had it here... *)
- now apply Nat.le_antisymm.
- destruct (Nat.le_gt_cases 1 n); trivial.
+ rewrite H; trivial.
+ now apply Nat.lt_le_incl.
Qed.
(** Alternative characterisations of being without duplicates,
thanks to [nth_error] and [nth] *)
Lemma NoDup_nth_error l :
NoDup l <->
(forall i j, i<length l -> nth_error l i = nth_error l j -> i = j).
Proof.
split.
{ intros H; induction H as [|a l Hal Hl IH]; intros i j Hi E.
- inversion Hi.
- destruct i, j; simpl in *; auto.
* elim Hal. eapply nth_error_In; eauto.
* elim Hal. eapply nth_error_In; eauto.
* f_equal. apply IH; auto with arith. }
{ induction l as [|a l]; intros H; constructor.
* intro Ha. apply In_nth_error in Ha. destruct Ha as (n,Hn).
assert (n < length l) by (now rewrite <- nth_error_Some, Hn).
specialize (H 0 (S n)). simpl in H. discriminate H; auto with arith.
* apply IHl.
intros i j Hi E. apply eq_add_S, H; simpl; auto with arith. }
Qed.
Lemma NoDup_nth l d :
NoDup l <->
(forall i j, i<length l -> j<length l ->
nth i l d = nth j l d -> i = j).
Proof.
split.
{ intros H; induction H as [|a l Hal Hl IH]; intros i j Hi Hj E.
- inversion Hi.
- destruct i, j; simpl in *; auto.
* elim Hal. subst a. apply nth_In; auto with arith.
* elim Hal. subst a. apply nth_In; auto with arith.
* f_equal. apply IH; auto with arith. }
{ induction l as [|a l]; intros H; constructor.
* intro Ha. eapply In_nth in Ha. destruct Ha as (n & Hn & Hn').
specialize (H 0 (S n)). simpl in H. discriminate H; eauto with arith.
* apply IHl.
intros i j Hi Hj E. apply eq_add_S, H; simpl; auto with arith. }
Qed.
(** Having [NoDup] hypotheses bring more precise facts about [incl]. *)
Lemma NoDup_incl_length l l' :
NoDup l -> incl l l' -> length l <= length l'.
Proof.
intros N. revert l'. induction N as [|a l Hal N IH]; simpl.
- auto with arith.
- intros l' H.
destruct (Add_inv a l') as (l'', AD). { apply H; simpl; auto. }
rewrite (Add_length AD). apply le_n_S. apply IH.
now apply incl_Add_inv with a l'.
Qed.
Lemma NoDup_length_incl l l' :
NoDup l -> length l' <= length l -> incl l l' -> incl l' l.
Proof.
intros N. revert l'. induction N as [|a l Hal N IH].
- destruct l'; easy.
- intros l' E H x Hx.
destruct (Add_inv a l') as (l'', AD). { apply H; simpl; auto. }
rewrite (Add_in AD) in Hx. simpl in Hx.
destruct Hx as [Hx|Hx]; [left; trivial|right].
revert x Hx. apply (IH l''); trivial.
* apply le_S_n. now rewrite <- (Add_length AD).
* now apply incl_Add_inv with a l'.
Qed.
End ReDun.
(** NoDup and map *)
(** NB: the reciprocal result holds only for injective functions,
see FinFun.v *)
Lemma NoDup_map_inv A B (f:A->B) l : NoDup (map f l) -> NoDup l.
Proof.
induction l; simpl; inversion_clear 1; subst; constructor; auto.
intro H. now apply (in_map f) in H.
Qed.
(***********************************)
(** ** Sequence of natural numbers *)
(***********************************)
Section NatSeq.
(** [seq] computes the sequence of [len] contiguous integers
that starts at [start]. For instance, [seq 2 3] is [2::3::4::nil]. *)
Fixpoint seq (start len:nat) : list nat :=
match len with
| 0 => nil
| S len => start :: seq (S start) len
end.
Lemma seq_length : forall len start, length (seq start len) = len.
Proof.
induction len; simpl; auto.
Qed.
Lemma seq_nth : forall len start n d,
n < len -> nth n (seq start len) d = start+n.
Proof.
induction len; intros.
inversion H.
simpl seq.
destruct n; simpl.
auto with arith.
rewrite IHlen;simpl; auto with arith.
Qed.
Lemma seq_shift : forall len start,
map S (seq start len) = seq (S start) len.
Proof.
induction len; simpl; auto.
intros.
rewrite IHlen.
auto with arith.
Qed.
Lemma in_seq len start n :
In n (seq start len) <-> start <= n < start+len.
Proof.
revert start. induction len; simpl; intros.
- rewrite <- plus_n_O. split;[easy|].
intros (H,H'). apply (Lt.lt_irrefl _ (Lt.le_lt_trans _ _ _ H H')).
- rewrite IHlen, <- plus_n_Sm; simpl; split.
* intros [H|H]; subst; intuition auto with arith.
* intros (H,H'). destruct (Lt.le_lt_or_eq _ _ H); intuition.
Qed.
Lemma seq_NoDup len start : NoDup (seq start len).
Proof.
revert start; induction len; simpl; constructor; trivial.
rewrite in_seq. intros (H,_). apply (Lt.lt_irrefl _ H).
Qed.
Lemma seq_app : forall len1 len2 start,
seq start (len1 + len2) = seq start len1 ++ seq (start + len1) len2.
Proof.
induction len1 as [|len1' IHlen]; intros; simpl in *.
- now rewrite Nat.add_0_r.
- now rewrite Nat.add_succ_r, IHlen.
Qed.
End NatSeq.
Section Exists_Forall.
(** * Existential and universal predicates over lists *)
Variable A:Type.
Section One_predicate.
Variable P:A->Prop.
Inductive Exists : list A -> Prop :=
| Exists_cons_hd : forall x l, P x -> Exists (x::l)
| Exists_cons_tl : forall x l, Exists l -> Exists (x::l).
Hint Constructors Exists : core.
Lemma Exists_exists (l:list A) :
Exists l <-> (exists x, In x l /\ P x).
Proof.
split.
- induction 1; firstorder.
- induction l; firstorder; subst; auto.
Qed.
Lemma Exists_nil : Exists nil <-> False.
Proof. split; inversion 1. Qed.
Lemma Exists_cons x l:
Exists (x::l) <-> P x \/ Exists l.
Proof. split; inversion 1; auto. Qed.
Lemma Exists_dec l:
(forall x:A, {P x} + { ~ P x }) ->
{Exists l} + {~ Exists l}.
Proof.
intro Pdec. induction l as [|a l' Hrec].
- right. abstract now rewrite Exists_nil.
- destruct Hrec as [Hl'|Hl'].
* left. now apply Exists_cons_tl.
* destruct (Pdec a) as [Ha|Ha].
+ left. now apply Exists_cons_hd.
+ right. abstract now inversion 1.
Defined.
Inductive Forall : list A -> Prop :=
| Forall_nil : Forall nil
| Forall_cons : forall x l, P x -> Forall l -> Forall (x::l).
Hint Constructors Forall : core.
Lemma Forall_forall (l:list A):
Forall l <-> (forall x, In x l -> P x).
Proof.
split.
- induction 1; firstorder; subst; auto.
- induction l; firstorder.
Qed.
Lemma Forall_inv : forall (a:A) l, Forall (a :: l) -> P a.
Proof.
intros; inversion H; trivial.
Qed.
Lemma Forall_rect : forall (Q : list A -> Type),
Q [] -> (forall b l, P b -> Q (b :: l)) -> forall l, Forall l -> Q l.
Proof.
intros Q H H'; induction l; intro; [|eapply H', Forall_inv]; eassumption.
Qed.
Lemma Forall_dec :
(forall x:A, {P x} + { ~ P x }) ->
forall l:list A, {Forall l} + {~ Forall l}.
Proof.
intro Pdec. induction l as [|a l' Hrec].
- left. apply Forall_nil.
- destruct Hrec as [Hl'|Hl'].
+ destruct (Pdec a) as [Ha|Ha].
* left. now apply Forall_cons.
* right. abstract now inversion 1.
+ right. abstract now inversion 1.
Defined.
End One_predicate.
Theorem Forall_inv_tail
: forall (P : A -> Prop) (x0 : A) (xs : list A), Forall P (x0 :: xs) -> Forall P xs.
Proof.
intros P x0 xs H.
apply Forall_forall with (l := xs).
assert (H0 : forall x : A, In x (x0 :: xs) -> P x).
apply Forall_forall with (P := P) (l := x0 :: xs).
exact H.
assert (H1 : forall (x : A) (H2 : In x xs), P x).
intros x H2.
apply (H0 x).
right.
exact H2.
intros x H2.
apply (H1 x H2).
Qed.
Theorem Exists_impl
: forall (P Q : A -> Prop), (forall x : A, P x -> Q x) -> forall xs : list A, Exists P xs -> Exists Q xs.
Proof.
intros P Q H xs H0.
induction H0.
apply (Exists_cons_hd Q x l (H x H0)).
apply (Exists_cons_tl x IHExists).
Qed.
Lemma Forall_Exists_neg (P:A->Prop)(l:list A) :
Forall (fun x => ~ P x) l <-> ~(Exists P l).
Proof.
rewrite Forall_forall, Exists_exists. firstorder.
Qed.
Lemma Exists_Forall_neg (P:A->Prop)(l:list A) :
(forall x, P x \/ ~P x) ->
Exists (fun x => ~ P x) l <-> ~(Forall P l).
Proof.
intro Dec.
split.
- rewrite Forall_forall, Exists_exists; firstorder.
- intros NF.
induction l as [|a l IH].
+ destruct NF. constructor.
+ destruct (Dec a) as [Ha|Ha].
* apply Exists_cons_tl, IH. contradict NF. now constructor.
* now apply Exists_cons_hd.
Qed.
Lemma neg_Forall_Exists_neg (P:A->Prop) (l:list A) :
(forall x:A, {P x} + { ~ P x }) ->
~ Forall P l ->
Exists (fun x => ~ P x) l.
Proof.
intro Dec.
apply Exists_Forall_neg; intros.
destruct (Dec x); auto.
Qed.
Lemma Forall_Exists_dec (P:A->Prop) :
(forall x:A, {P x} + { ~ P x }) ->
forall l:list A,
{Forall P l} + {Exists (fun x => ~ P x) l}.
Proof.
intros Pdec l.
destruct (Forall_dec P Pdec l); [left|right]; trivial.
now apply neg_Forall_Exists_neg.
Defined.
Lemma Forall_impl : forall (P Q : A -> Prop), (forall a, P a -> Q a) ->
forall l, Forall P l -> Forall Q l.
Proof.
intros P Q H l. rewrite !Forall_forall. firstorder.
Qed.
End Exists_Forall.
Hint Constructors Exists : core.
Hint Constructors Forall : core.
Section Forall2.
(** [Forall2]: stating that elements of two lists are pairwise related. *)
Variables A B : Type.
Variable R : A -> B -> Prop.
Inductive Forall2 : list A -> list B -> Prop :=
| Forall2_nil : Forall2 [] []
| Forall2_cons : forall x y l l',
R x y -> Forall2 l l' -> Forall2 (x::l) (y::l').
Hint Constructors Forall2 : core.
Theorem Forall2_refl : Forall2 [] [].
Proof. intros; apply Forall2_nil. Qed.
Theorem Forall2_app_inv_l : forall l1 l2 l',
Forall2 (l1 ++ l2) l' ->
exists l1' l2', Forall2 l1 l1' /\ Forall2 l2 l2' /\ l' = l1' ++ l2'.
Proof.
induction l1; intros.
exists [], l'; auto.
simpl in H; inversion H; subst; clear H.
apply IHl1 in H4 as (l1' & l2' & Hl1 & Hl2 & ->).
exists (y::l1'), l2'; simpl; auto.
Qed.
Theorem Forall2_app_inv_r : forall l1' l2' l,
Forall2 l (l1' ++ l2') ->
exists l1 l2, Forall2 l1 l1' /\ Forall2 l2 l2' /\ l = l1 ++ l2.
Proof.
induction l1'; intros.
exists [], l; auto.
simpl in H; inversion H; subst; clear H.
apply IHl1' in H4 as (l1 & l2 & Hl1 & Hl2 & ->).
exists (x::l1), l2; simpl; auto.
Qed.
Theorem Forall2_app : forall l1 l2 l1' l2',
Forall2 l1 l1' -> Forall2 l2 l2' -> Forall2 (l1 ++ l2) (l1' ++ l2').
Proof.
intros. induction l1 in l1', H, H0 |- *; inversion H; subst; simpl; auto.
Qed.
End Forall2.
Hint Constructors Forall2 : core.
Section ForallPairs.
(** [ForallPairs] : specifies that a certain relation should
always hold when inspecting all possible pairs of elements of a list. *)
Variable A : Type.
Variable R : A -> A -> Prop.
Definition ForallPairs l :=
forall a b, In a l -> In b l -> R a b.
(** [ForallOrdPairs] : we still check a relation over all pairs
of elements of a list, but now the order of elements matters. *)
Inductive ForallOrdPairs : list A -> Prop :=
| FOP_nil : ForallOrdPairs nil
| FOP_cons : forall a l,
Forall (R a) l -> ForallOrdPairs l -> ForallOrdPairs (a::l).
Hint Constructors ForallOrdPairs : core.
Lemma ForallOrdPairs_In : forall l,
ForallOrdPairs l ->
forall x y, In x l -> In y l -> x=y \/ R x y \/ R y x.
Proof.
induction 1.
inversion 1.
simpl; destruct 1; destruct 1; subst; auto.
right; left. apply -> Forall_forall; eauto.
right; right. apply -> Forall_forall; eauto.
Qed.
(** [ForallPairs] implies [ForallOrdPairs]. The reverse implication is true
only when [R] is symmetric and reflexive. *)
Lemma ForallPairs_ForallOrdPairs l: ForallPairs l -> ForallOrdPairs l.
Proof.
induction l; auto. intros H.
constructor.
apply <- Forall_forall. intros; apply H; simpl; auto.
apply IHl. red; intros; apply H; simpl; auto.
Qed.
Lemma ForallOrdPairs_ForallPairs :
(forall x, R x x) ->
(forall x y, R x y -> R y x) ->
forall l, ForallOrdPairs l -> ForallPairs l.
Proof.
intros Refl Sym l Hl x y Hx Hy.
destruct (ForallOrdPairs_In Hl _ _ Hx Hy); subst; intuition.
Qed.
End ForallPairs.
(** * Inversion of predicates over lists based on head symbol *)
Ltac is_list_constr c :=
match c with
| nil => idtac
| (_::_) => idtac
| _ => fail
end.
Ltac invlist f :=
match goal with
| H:f ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ _ _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ _ _ _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| _ => idtac
end.
(** * Exporting hints and tactics *)
Hint Rewrite
rev_involutive (* rev (rev l) = l *)
rev_unit (* rev (l ++ a :: nil) = a :: rev l *)
map_nth (* nth n (map f l) (f d) = f (nth n l d) *)
map_length (* length (map f l) = length l *)
seq_length (* length (seq start len) = len *)
app_length (* length (l ++ l') = length l + length l' *)
rev_length (* length (rev l) = length l *)
app_nil_r (* l ++ nil = l *)
: list.
Ltac simpl_list := autorewrite with list.
Ltac ssimpl_list := autorewrite with list using simpl.
(* begin hide *)
(* Compatibility notations after the migration of [list] to [Datatypes] *)
Notation list := list (only parsing).
Notation list_rect := list_rect (only parsing).
Notation list_rec := list_rec (only parsing).
Notation list_ind := list_ind (only parsing).
Notation nil := nil (only parsing).
Notation cons := cons (only parsing).
Notation length := length (only parsing).
Notation app := app (only parsing).
(* Compatibility Names *)
Notation tail := tl (only parsing).
Notation head := hd_error (only parsing).
Notation head_nil := hd_error_nil (only parsing).
Notation head_cons := hd_error_cons (only parsing).
Notation ass_app := app_assoc (only parsing).
Notation app_ass := app_assoc_reverse (only parsing).
Notation In_split := in_split (only parsing).
Notation In_rev := in_rev (only parsing).
Notation In_dec := in_dec (only parsing).
Notation distr_rev := rev_app_distr (only parsing).
Notation rev_acc := rev_append (only parsing).
Notation rev_acc_rev := rev_append_rev (only parsing).
Notation AllS := Forall (only parsing). (* was formerly in TheoryList *)
Hint Resolve app_nil_end : datatypes.
(* end hide *)
Section Repeat.
Variable A : Type.
Fixpoint repeat (x : A) (n: nat ) :=
match n with
| O => []
| S k => x::(repeat x k)
end.
Theorem repeat_length x n:
length (repeat x n) = n.
Proof.
induction n as [| k Hrec]; simpl; rewrite ?Hrec; reflexivity.
Qed.
Theorem repeat_spec n x y:
In y (repeat x n) -> y=x.
Proof.
induction n as [|k Hrec]; simpl; destruct 1; auto.
Qed.
End Repeat.
(* Unset Universe Polymorphism. *)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221OI_BEHAVIORAL_V
`define SKY130_FD_SC_LP__A221OI_BEHAVIORAL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a221oi (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, C1, and1_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221OI_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22A_TB_V
`define SKY130_FD_SC_LS__O22A_TB_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o22a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_ls__o22a dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22A_TB_V
|
//-----------------------------------------------------------------------------
// Title : KPU main test bench file
// Project : KPU
//-----------------------------------------------------------------------------
// File : kpu_soc.v
// Author : acorallo <[email protected]>
// Created : 17.12.2016
//-----------------------------------------------------------------------------
// Description :
// Main file for KPU SoC
//-----------------------------------------------------------------------------
// This file is part of KPU.
// KPU is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
// KPU is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY;
// without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with KPU. If not, see <http://www.gnu.org/licenses/>.
//
// Copyright (c) 2016 by Andrea Corallo.
//------------------------------------------------------------------------------
// Modification history :
// 17.12.2016 : created
// 04.04.2017 : renamed kpu_soc.v
//-----------------------------------------------------------------------------
`timescale 1ns/1ps
`include "kpu_conf.v"
`include "kcache_defs.v"
module kpu_soc(
input CLK100MHZ,
input rst_ext,
`ifdef KPU_SIM_TRACE
input stop_debug,
input [`IO_INT_N-1:0] io_int_line_debug,
`endif
// IO ports
input uart_rx,
output uart_tx,
output reg [7:0] ja,
// External SRAM interface
output wire [`SRAM_ADDR_W-1:0] sram_addr_o,
inout wire [`SRAM_DATA_W-1:0] sram_data_io,
output wire sram_cs_o,
output wire sram_we_o,
output wire sram_oe_o,
output wire sram_hb_o,
output wire sram_lb_o,
// JTAG
input tms_pad_i, // JTAG test mode select pad
input tck_pad_i, // JTAG test clock pad
input trstn_pad_i, // JTAG test reset pad
input tdi_pad_i, // JTAG test data input pad
output tdo_pad_o, // JTAG test data output pad
output tdo_padoe_o // JTAG test data output enable pad
);
`ifndef KPU_SIM_TRACE
reg [`IO_INT_N-1:0] io_int_line_debug = `IO_INT_N'h0;
reg stop_debug = 1'b0;
`endif
wire sys_clk;
wire kpu_clk;
wire debug_mode;
reg rst;
reg rst_pw_on;
reg [31:0] pw_on_cnt;
reg [`IO_INT_N-1:0] io_int_line;
wire mem_wait;
wire io_int;
wire int_ctrl_rst;
wire [`N-1:0] io_int_num;
wire [`N-1:0] kpu_gpo;
wire kpu_stop;
wire wb_int_send;
wire rts;
wire cts;
// memory lines
wire [`N-1:0] inst_addr;
wire [`N-1:0] kpu_inst_data;
wire [`N-1:0] mem_inst_data;
wire [`N-1:0] data_addr;
wire [3:0] kpu_data_b_sel;
wire [3:0] mem_data_b_sel;
wire [`N-1:0] kpu_data_o;
wire [`N-1:0] mem_data_o;
wire [`N-1:0] kpu_data_i;
wire [`N-1:0] mem_data_i;
// wishbone bridge lines
wire wb_i_ready;
wire [31:0] wb_i_command;
wire [31:0] wb_i_address;
wire [31:0] wb_i_data;
wire [27:0] wb_i_data_count;
wire [31:0] wb_o_status;
wire wb_o_en;
wire [31:0] wb_o_address;
wire [31:0] wb_o_data;
wire [27:0] wb_o_data_count;
// wishbone bus lines
wire wb_we_send;
wire wb_cyc_send;
wire [3:0] wb_sel_send;
wire [31:0] wb_dat_send;
wire wb_stb_send;
wire wb_ack_recv;
wire [31:0] wb_dat_recv;
wire [31:0] wb_adr_send;
always @(*) begin
ja = kpu_gpo[7:0];
`ifdef KPU_SIM_TRACE
io_int_line = io_int_line_debug;
`endif
io_int_line[0] = wb_int_send;
end
`ifdef KPU_SIM_TRACE
assign sys_clk = CLK100MHZ;
`else
clk_wiz_0 clk_wiz_i(.clk_out1(sys_clk), // output clk_out1
.reset(1'b0), // input reset
.locked(lk), // output locked
.clk_in1(CLK100MHZ)); // input clk_in1
`endif
initial begin
rst_pw_on = 1;
pw_on_cnt = 1;
end
always @(posedge sys_clk) begin
if (pw_on_cnt[31])
rst_pw_on <= 0;
else
pw_on_cnt <= pw_on_cnt << 1;
end
always @(*)
rst = rst_ext | rst_pw_on;
kpu kpu_i(.clk_i(kpu_clk),
.rst_i(rst),
.stop_i(kpu_stop),
.io_int_i(io_int),
.inst_addr_o(inst_addr),
.inst_data_i(kpu_inst_data),
.data_addr_o(data_addr),
.data_b_sel_o(kpu_data_b_sel),
.data_o(kpu_data_o),
.data_i(kpu_data_i),
.debug_i(debug_mode));
dgb dgb_i(.clk_i(sys_clk),
.debug_o(debug_mode),
// JTAG
.tck_pad_i(tck_pad_i),
.tms_pad_i(tms_pad_i),
.tdi_pad_i(tdi_pad_i),
.tdo_pad_o(tdo_pad_o),
.tdo_padoe_o(tdo_padoe_o),
.trstn_pad_i(trstn_pad_i),
// From to KPU
.kpu_clk_o(kpu_clk),
.kpu_wait_o(kpu_stop),
.kpu_d_sel_i(kpu_data_b_sel),
.kpu_d_data_i(kpu_data_o),
.kpu_i_data_o(kpu_inst_data),
.kpu_d_data_o(kpu_data_i),
// From to mem
.mem_kpu_wait_i(mem_wait || stop_debug),
.mem_d_sel_o(mem_data_b_sel),
.mem_i_data_i(mem_inst_data),
.mem_d_data_i(mem_data_i),
.mem_d_data_o(mem_data_o));
mem mem_i(.clk_i(sys_clk),
.kpu_wait_o(mem_wait),
.i_addr_i(inst_addr),
.i_data_o(mem_inst_data),
.d_addr_i(data_addr),
.d_sel_i(mem_data_b_sel),
.d_data_i(mem_data_o),
.d_data_o(mem_data_i),
.d_gp_i(0),
.d_gp_o(kpu_gpo),
.io_int_num_i(io_int_num),
.int_ctrl_rst_o(int_ctrl_rst),
.wb_ready_o(wb_i_ready),
.wb_command_o(wb_i_command),
.wb_addr_o(wb_i_address),
.wb_data_o(wb_i_data),
.wb_data_count_o(wb_i_data_count),
.wb_data_count_i(wb_o_data_count),
.wb_status_i(wb_o_status),
.wb_data_i(wb_o_data),
.wb_o_en_i(wb_o_en),
.sram_addr_o(sram_addr_o),
.sram_data_io(sram_data_io),
.sram_cs_o(sram_cs_o),
.sram_we_o(sram_we_o),
.sram_oe_o(sram_oe_o),
.sram_hb_o(sram_hb_o),
.sram_lb_o(sram_lb_o)
);
int_ctrl int_ctrl_i(.clk_i(sys_clk),
.rst_i(int_ctrl_rst),
.io_int_i(io_int_line),
.io_int_o(io_int),
.int_num_o(io_int_num));
wishbone_master wb_m_i(.clk(sys_clk),
.rst(rst),
.i_ih_rst(rst),
.i_ready(wb_i_ready),
.i_command(wb_i_command),
.i_address(wb_i_address),
.i_data(wb_i_data),
.i_data_count(wb_i_data_count),
.i_out_ready(1'b1),
.o_en(wb_o_en),
.o_status(wb_o_status),
.o_address(wb_o_address),
.o_data(wb_o_data),
.o_data_count(wb_o_data_count),
// wishbone bus
.o_per_adr(wb_adr_send),
.o_per_dat(wb_dat_send),
.i_per_dat(wb_dat_recv),
.o_per_stb(wb_stb_send),
.o_per_cyc(wb_cyc_send),
.o_per_we(wb_we_send),
.o_per_msk(),
.o_per_sel(wb_sel_send),
.i_per_ack(wb_ack_recv),
.i_per_int(1'b0),
.i_mem_dat(`N'b0),
.i_mem_ack(1'b0),
.i_mem_int(1'b0));
wb_uart wb_uart_i(.clk(sys_clk),
.rst(rst),
.i_wbs_we(wb_we_send),
.i_wbs_cyc(wb_cyc_send),
.i_wbs_sel(wb_sel_send),
.i_wbs_dat(wb_dat_send),
.i_wbs_stb(wb_stb_send),
.o_wbs_ack(wb_ack_recv),
.o_wbs_dat(wb_dat_recv),
.i_wbs_adr(wb_adr_send),
.o_wbs_int(wb_int_send),
.o_tx(uart_tx),
.i_rx(uart_rx),
.i_rts(rts),
.o_cts(cts),
.i_dtr(1'b0));
endmodule // kpu_test
|
/**
* bsg_lru_pseudo_tree_encode.v
*
* Pseudo-Tree-LRU encode unit.
* Given the LRU bits, traverses the pseudo-LRU tree and returns the
* LRU way_id.
* Only for power-of-2 ways.
*
* --------------------
* Example (ways_p=8)
* --------------------
* lru_i way_id_o
* ----- --------
* xxx_0x00 0
* xxx_1x00 1
* xx0 xx10 2
* xx1 xx10 3
* x0x x0x1 4
* x1x x0x1 5
* 0xx x1x1 6
* 1xx x1x1 7
* --------------------
* 'x' means don't care.
*
* @author tommy
*
*/
`include "bsg_defines.v"
module bsg_lru_pseudo_tree_encode
#(parameter `BSG_INV_PARAM(ways_p)
, parameter lg_ways_lp = `BSG_SAFE_CLOG2(ways_p)
)
(
input [`BSG_SAFE_MINUS(ways_p, 2):0] lru_i
, output logic [lg_ways_lp-1:0] way_id_o
);
if (ways_p == 1) begin: no_lru
assign way_id_o = 1'b0;
end
else begin: lru
for (genvar i = 0; i < lg_ways_lp; i++) begin: rank
if (i == 0) begin: z
// top way_id_o bit is just the lowest LRU bit
assign way_id_o[lg_ways_lp-1] = lru_i[0]; // root
end
else begin: nz
// each output way_id_o bit uses *all* of the way_id_o bits above it in the way_id_o vector
// as the select to a mux which has as input an exponentially growing (2^i) collection of unique LRU bits
bsg_mux #(
.width_p(1)
,.els_p(2**i)
) mux (
.data_i(lru_i[((2**i)-1)+:(2**i)])
,.sel_i(way_id_o[lg_ways_lp-1-:i])
,.data_o(way_id_o[lg_ways_lp-1-i])
);
end
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_lru_psuedo_tree_encode)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGND_1_V
`define SKY130_FD_SC_LS__TAPVGND_1_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog wrapper for tapvgnd with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__tapvgnd.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__tapvgnd_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__tapvgnd base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__tapvgnd_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__tapvgnd base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGND_1_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:03:17 03/01/2016
// Design Name: Pc
// Module Name: C:/Users/Ranolazine/Desktop/Lab/lab5/test_pc_.v
// Project Name: lab5
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Pc
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_pc_;
// Inputs
reg clock_in;
reg [31:0] nextPC;
reg rst;
// Outputs
wire [31:0] currPC;
// Instantiate the Unit Under Test (UUT)
Pc uut (
.clock_in(clock_in),
.nextPC(nextPC),
.currPC(currPC),
.rst(rst)
);
always #5 clock_in = ~clock_in;
initial begin
// Initialize Inputs
clock_in = 0;
nextPC = 0;
rst = 1;
// Wait 100 ns for global reset to finish
#100;
nextPC = 'b11111111111111111111111111111111;
rst = 0;
#100;
nextPC = 'b00000000000000000000000000010000;
#100;
rst =1;
// Add stimulus here
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FA_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__FA_BEHAVIORAL_PP_V
/**
* fa: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__fa (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire nor0_out ;
wire nor1_out ;
wire or1_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire or2_out_SUM ;
wire pwrgood_pp1_out_SUM ;
// Name Output Other arguments
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT , and1_out, and0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, or1_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , or2_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FA_BEHAVIORAL_PP_V |
module ball_control(
input clock, reset, load, enable, floor,
input [5:0] radius,
input [9:0] load_x, load_y,
input [3:0] s_x, s_y,
input [5:0] seed,
input bd_p, bd_bl,
input [1:0] bd_di,
output reg [9:0] x, y,
output dead
);
`include "def.v"
wire rstx, rsty;
wire [UBIT-1:0] cntx, cnty;
wire [31:0] rnum;
reg di_x, di_y;
reg [5:0] ang_x, ang_y;
wire [5:0] next_ang_x, next_ang_y;
assign rstx = reset || cntx*ang_x >= UNIT;
assign rsty = reset || cnty*ang_y >= UNIT;
assign bd = bd_p | bd_bl;
counter #(UBIT) cnt0(clock, rstx, enable, cntx);
counter #(UBIT) cnt1(clock, rsty, enable, cnty);
rand rnd(clock, reset, rnum);
// Ball moving
always @(posedge clock)
begin
if (reset) begin
x <= LEFT+MAXX;
y <= TOP+MAXY;
end else if (load) begin
x <= load_x;
y <= load_y;
end else if (enable) begin
if (rstx) begin
if (di_x)
x <= x-1;
else
x <= x+1;
end
if (rsty) begin
if (di_y)
y <= y-1;
else
y <= y+1;
end
end
end
// Ball bouncing
always @(posedge clock)
begin
if (reset) begin
di_x <= 1'b0;
di_y <= 1'b0;
end else if (enable) begin
if (bd) begin
case (bd_di)
B_UP: di_y <= 1'b1;
B_RIGHT: di_x <= 1'b0;
B_DOWN: di_y <= 1'b0;
B_LEFT: di_x <= 1'b1;
endcase
end
// bounce wall take priority ($note. nonblocking assignment of
// the same variable can be used in the same always block.)
if (LEFT + radius >= x) // bounce left side
di_x <= 1'b0;
else if (x + radius >= LEFT+MAXX) // bounce right side
di_x <= 1'b1;
if (TOP + radius > y) // bounce top side
di_y <= 1'b0;
else if (floor && y + radius >= TOP+MAXY) // bounce down side
di_y <= 1'b1;
end
end
// Ball speeding
always @(posedge clock)
begin
if (reset) begin
ang_x <= rnum[7:4] ? rnum[7:4] : 5;
ang_y <= rnum[11:8] ? rnum[11:8] : 6;
end else if (load) begin
ang_x <= rnum[7:4] + seed ? rnum[7:4] : 5;
ang_y <= rnum[11:8] - seed ? rnum[11:8] : 6;
end else if (enable && bd) begin
if (s_x) ang_x <= next_ang_x ? next_ang_x : ang_x;
if (s_y) ang_y <= next_ang_y ? next_ang_y : ang_y;
end
if (ang_x == 0) ang_x <= 5;
if (ang_y == 0) ang_y <= 6;
end
assign next_ang_x = rnum[1:0] + s_x;
assign next_ang_y = rnum[3:2] + s_y;
assign dead = y >= TOP+MAXY;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3B_SYMBOL_V
`define SKY130_FD_SC_HS__OR3B_SYMBOL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3B_SYMBOL_V
|
// ik_swift_hps_0.v
// This file was auto-generated from altera_hps_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 13.1.1 166 at 2014.05.05.12:48:21
`timescale 1 ps / 1 ps
module ik_swift_hps_0 #(
parameter F2S_Width = 2,
parameter S2F_Width = 2
) (
output wire h2f_rst_n, // h2f_reset.reset_n
input wire f2h_axi_clk, // f2h_axi_clock.clk
input wire [7:0] f2h_AWID, // f2h_axi_slave.awid
input wire [31:0] f2h_AWADDR, // .awaddr
input wire [3:0] f2h_AWLEN, // .awlen
input wire [2:0] f2h_AWSIZE, // .awsize
input wire [1:0] f2h_AWBURST, // .awburst
input wire [1:0] f2h_AWLOCK, // .awlock
input wire [3:0] f2h_AWCACHE, // .awcache
input wire [2:0] f2h_AWPROT, // .awprot
input wire f2h_AWVALID, // .awvalid
output wire f2h_AWREADY, // .awready
input wire [4:0] f2h_AWUSER, // .awuser
input wire [7:0] f2h_WID, // .wid
input wire [63:0] f2h_WDATA, // .wdata
input wire [7:0] f2h_WSTRB, // .wstrb
input wire f2h_WLAST, // .wlast
input wire f2h_WVALID, // .wvalid
output wire f2h_WREADY, // .wready
output wire [7:0] f2h_BID, // .bid
output wire [1:0] f2h_BRESP, // .bresp
output wire f2h_BVALID, // .bvalid
input wire f2h_BREADY, // .bready
input wire [7:0] f2h_ARID, // .arid
input wire [31:0] f2h_ARADDR, // .araddr
input wire [3:0] f2h_ARLEN, // .arlen
input wire [2:0] f2h_ARSIZE, // .arsize
input wire [1:0] f2h_ARBURST, // .arburst
input wire [1:0] f2h_ARLOCK, // .arlock
input wire [3:0] f2h_ARCACHE, // .arcache
input wire [2:0] f2h_ARPROT, // .arprot
input wire f2h_ARVALID, // .arvalid
output wire f2h_ARREADY, // .arready
input wire [4:0] f2h_ARUSER, // .aruser
output wire [7:0] f2h_RID, // .rid
output wire [63:0] f2h_RDATA, // .rdata
output wire [1:0] f2h_RRESP, // .rresp
output wire f2h_RLAST, // .rlast
output wire f2h_RVALID, // .rvalid
input wire f2h_RREADY, // .rready
input wire h2f_lw_axi_clk, // h2f_lw_axi_clock.clk
output wire [11:0] h2f_lw_AWID, // h2f_lw_axi_master.awid
output wire [20:0] h2f_lw_AWADDR, // .awaddr
output wire [3:0] h2f_lw_AWLEN, // .awlen
output wire [2:0] h2f_lw_AWSIZE, // .awsize
output wire [1:0] h2f_lw_AWBURST, // .awburst
output wire [1:0] h2f_lw_AWLOCK, // .awlock
output wire [3:0] h2f_lw_AWCACHE, // .awcache
output wire [2:0] h2f_lw_AWPROT, // .awprot
output wire h2f_lw_AWVALID, // .awvalid
input wire h2f_lw_AWREADY, // .awready
output wire [11:0] h2f_lw_WID, // .wid
output wire [31:0] h2f_lw_WDATA, // .wdata
output wire [3:0] h2f_lw_WSTRB, // .wstrb
output wire h2f_lw_WLAST, // .wlast
output wire h2f_lw_WVALID, // .wvalid
input wire h2f_lw_WREADY, // .wready
input wire [11:0] h2f_lw_BID, // .bid
input wire [1:0] h2f_lw_BRESP, // .bresp
input wire h2f_lw_BVALID, // .bvalid
output wire h2f_lw_BREADY, // .bready
output wire [11:0] h2f_lw_ARID, // .arid
output wire [20:0] h2f_lw_ARADDR, // .araddr
output wire [3:0] h2f_lw_ARLEN, // .arlen
output wire [2:0] h2f_lw_ARSIZE, // .arsize
output wire [1:0] h2f_lw_ARBURST, // .arburst
output wire [1:0] h2f_lw_ARLOCK, // .arlock
output wire [3:0] h2f_lw_ARCACHE, // .arcache
output wire [2:0] h2f_lw_ARPROT, // .arprot
output wire h2f_lw_ARVALID, // .arvalid
input wire h2f_lw_ARREADY, // .arready
input wire [11:0] h2f_lw_RID, // .rid
input wire [31:0] h2f_lw_RDATA, // .rdata
input wire [1:0] h2f_lw_RRESP, // .rresp
input wire h2f_lw_RLAST, // .rlast
input wire h2f_lw_RVALID, // .rvalid
output wire h2f_lw_RREADY, // .rready
input wire h2f_axi_clk, // h2f_axi_clock.clk
output wire [11:0] h2f_AWID, // h2f_axi_master.awid
output wire [29:0] h2f_AWADDR, // .awaddr
output wire [3:0] h2f_AWLEN, // .awlen
output wire [2:0] h2f_AWSIZE, // .awsize
output wire [1:0] h2f_AWBURST, // .awburst
output wire [1:0] h2f_AWLOCK, // .awlock
output wire [3:0] h2f_AWCACHE, // .awcache
output wire [2:0] h2f_AWPROT, // .awprot
output wire h2f_AWVALID, // .awvalid
input wire h2f_AWREADY, // .awready
output wire [11:0] h2f_WID, // .wid
output wire [63:0] h2f_WDATA, // .wdata
output wire [7:0] h2f_WSTRB, // .wstrb
output wire h2f_WLAST, // .wlast
output wire h2f_WVALID, // .wvalid
input wire h2f_WREADY, // .wready
input wire [11:0] h2f_BID, // .bid
input wire [1:0] h2f_BRESP, // .bresp
input wire h2f_BVALID, // .bvalid
output wire h2f_BREADY, // .bready
output wire [11:0] h2f_ARID, // .arid
output wire [29:0] h2f_ARADDR, // .araddr
output wire [3:0] h2f_ARLEN, // .arlen
output wire [2:0] h2f_ARSIZE, // .arsize
output wire [1:0] h2f_ARBURST, // .arburst
output wire [1:0] h2f_ARLOCK, // .arlock
output wire [3:0] h2f_ARCACHE, // .arcache
output wire [2:0] h2f_ARPROT, // .arprot
output wire h2f_ARVALID, // .arvalid
input wire h2f_ARREADY, // .arready
input wire [11:0] h2f_RID, // .rid
input wire [63:0] h2f_RDATA, // .rdata
input wire [1:0] h2f_RRESP, // .rresp
input wire h2f_RLAST, // .rlast
input wire h2f_RVALID, // .rvalid
output wire h2f_RREADY, // .rready
input wire [31:0] f2h_irq_p0, // f2h_irq0.irq
input wire [31:0] f2h_irq_p1, // f2h_irq1.irq
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_io_qspi_inst_IO0, // .hps_io_qspi_inst_IO0
inout wire hps_io_qspi_inst_IO1, // .hps_io_qspi_inst_IO1
inout wire hps_io_qspi_inst_IO2, // .hps_io_qspi_inst_IO2
inout wire hps_io_qspi_inst_IO3, // .hps_io_qspi_inst_IO3
output wire hps_io_qspi_inst_SS0, // .hps_io_qspi_inst_SS0
output wire hps_io_qspi_inst_CLK, // .hps_io_qspi_inst_CLK
inout wire hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_io_spim0_inst_CLK, // .hps_io_spim0_inst_CLK
output wire hps_io_spim0_inst_MOSI, // .hps_io_spim0_inst_MOSI
input wire hps_io_spim0_inst_MISO, // .hps_io_spim0_inst_MISO
output wire hps_io_spim0_inst_SS0, // .hps_io_spim0_inst_SS0
output wire hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_io_i2c1_inst_SCL // .hps_io_i2c1_inst_SCL
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (F2S_Width != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
f2s_width_check ( .error(1'b1) );
end
if (S2F_Width != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
s2f_width_check ( .error(1'b1) );
end
endgenerate
ik_swift_hps_0_fpga_interfaces fpga_interfaces (
.h2f_rst_n (h2f_rst_n), // h2f_reset.reset_n
.f2h_axi_clk (f2h_axi_clk), // f2h_axi_clock.clk
.f2h_AWID (f2h_AWID), // f2h_axi_slave.awid
.f2h_AWADDR (f2h_AWADDR), // .awaddr
.f2h_AWLEN (f2h_AWLEN), // .awlen
.f2h_AWSIZE (f2h_AWSIZE), // .awsize
.f2h_AWBURST (f2h_AWBURST), // .awburst
.f2h_AWLOCK (f2h_AWLOCK), // .awlock
.f2h_AWCACHE (f2h_AWCACHE), // .awcache
.f2h_AWPROT (f2h_AWPROT), // .awprot
.f2h_AWVALID (f2h_AWVALID), // .awvalid
.f2h_AWREADY (f2h_AWREADY), // .awready
.f2h_AWUSER (f2h_AWUSER), // .awuser
.f2h_WID (f2h_WID), // .wid
.f2h_WDATA (f2h_WDATA), // .wdata
.f2h_WSTRB (f2h_WSTRB), // .wstrb
.f2h_WLAST (f2h_WLAST), // .wlast
.f2h_WVALID (f2h_WVALID), // .wvalid
.f2h_WREADY (f2h_WREADY), // .wready
.f2h_BID (f2h_BID), // .bid
.f2h_BRESP (f2h_BRESP), // .bresp
.f2h_BVALID (f2h_BVALID), // .bvalid
.f2h_BREADY (f2h_BREADY), // .bready
.f2h_ARID (f2h_ARID), // .arid
.f2h_ARADDR (f2h_ARADDR), // .araddr
.f2h_ARLEN (f2h_ARLEN), // .arlen
.f2h_ARSIZE (f2h_ARSIZE), // .arsize
.f2h_ARBURST (f2h_ARBURST), // .arburst
.f2h_ARLOCK (f2h_ARLOCK), // .arlock
.f2h_ARCACHE (f2h_ARCACHE), // .arcache
.f2h_ARPROT (f2h_ARPROT), // .arprot
.f2h_ARVALID (f2h_ARVALID), // .arvalid
.f2h_ARREADY (f2h_ARREADY), // .arready
.f2h_ARUSER (f2h_ARUSER), // .aruser
.f2h_RID (f2h_RID), // .rid
.f2h_RDATA (f2h_RDATA), // .rdata
.f2h_RRESP (f2h_RRESP), // .rresp
.f2h_RLAST (f2h_RLAST), // .rlast
.f2h_RVALID (f2h_RVALID), // .rvalid
.f2h_RREADY (f2h_RREADY), // .rready
.h2f_lw_axi_clk (h2f_lw_axi_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (h2f_lw_AWID), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (h2f_lw_AWADDR), // .awaddr
.h2f_lw_AWLEN (h2f_lw_AWLEN), // .awlen
.h2f_lw_AWSIZE (h2f_lw_AWSIZE), // .awsize
.h2f_lw_AWBURST (h2f_lw_AWBURST), // .awburst
.h2f_lw_AWLOCK (h2f_lw_AWLOCK), // .awlock
.h2f_lw_AWCACHE (h2f_lw_AWCACHE), // .awcache
.h2f_lw_AWPROT (h2f_lw_AWPROT), // .awprot
.h2f_lw_AWVALID (h2f_lw_AWVALID), // .awvalid
.h2f_lw_AWREADY (h2f_lw_AWREADY), // .awready
.h2f_lw_WID (h2f_lw_WID), // .wid
.h2f_lw_WDATA (h2f_lw_WDATA), // .wdata
.h2f_lw_WSTRB (h2f_lw_WSTRB), // .wstrb
.h2f_lw_WLAST (h2f_lw_WLAST), // .wlast
.h2f_lw_WVALID (h2f_lw_WVALID), // .wvalid
.h2f_lw_WREADY (h2f_lw_WREADY), // .wready
.h2f_lw_BID (h2f_lw_BID), // .bid
.h2f_lw_BRESP (h2f_lw_BRESP), // .bresp
.h2f_lw_BVALID (h2f_lw_BVALID), // .bvalid
.h2f_lw_BREADY (h2f_lw_BREADY), // .bready
.h2f_lw_ARID (h2f_lw_ARID), // .arid
.h2f_lw_ARADDR (h2f_lw_ARADDR), // .araddr
.h2f_lw_ARLEN (h2f_lw_ARLEN), // .arlen
.h2f_lw_ARSIZE (h2f_lw_ARSIZE), // .arsize
.h2f_lw_ARBURST (h2f_lw_ARBURST), // .arburst
.h2f_lw_ARLOCK (h2f_lw_ARLOCK), // .arlock
.h2f_lw_ARCACHE (h2f_lw_ARCACHE), // .arcache
.h2f_lw_ARPROT (h2f_lw_ARPROT), // .arprot
.h2f_lw_ARVALID (h2f_lw_ARVALID), // .arvalid
.h2f_lw_ARREADY (h2f_lw_ARREADY), // .arready
.h2f_lw_RID (h2f_lw_RID), // .rid
.h2f_lw_RDATA (h2f_lw_RDATA), // .rdata
.h2f_lw_RRESP (h2f_lw_RRESP), // .rresp
.h2f_lw_RLAST (h2f_lw_RLAST), // .rlast
.h2f_lw_RVALID (h2f_lw_RVALID), // .rvalid
.h2f_lw_RREADY (h2f_lw_RREADY), // .rready
.h2f_axi_clk (h2f_axi_clk), // h2f_axi_clock.clk
.h2f_AWID (h2f_AWID), // h2f_axi_master.awid
.h2f_AWADDR (h2f_AWADDR), // .awaddr
.h2f_AWLEN (h2f_AWLEN), // .awlen
.h2f_AWSIZE (h2f_AWSIZE), // .awsize
.h2f_AWBURST (h2f_AWBURST), // .awburst
.h2f_AWLOCK (h2f_AWLOCK), // .awlock
.h2f_AWCACHE (h2f_AWCACHE), // .awcache
.h2f_AWPROT (h2f_AWPROT), // .awprot
.h2f_AWVALID (h2f_AWVALID), // .awvalid
.h2f_AWREADY (h2f_AWREADY), // .awready
.h2f_WID (h2f_WID), // .wid
.h2f_WDATA (h2f_WDATA), // .wdata
.h2f_WSTRB (h2f_WSTRB), // .wstrb
.h2f_WLAST (h2f_WLAST), // .wlast
.h2f_WVALID (h2f_WVALID), // .wvalid
.h2f_WREADY (h2f_WREADY), // .wready
.h2f_BID (h2f_BID), // .bid
.h2f_BRESP (h2f_BRESP), // .bresp
.h2f_BVALID (h2f_BVALID), // .bvalid
.h2f_BREADY (h2f_BREADY), // .bready
.h2f_ARID (h2f_ARID), // .arid
.h2f_ARADDR (h2f_ARADDR), // .araddr
.h2f_ARLEN (h2f_ARLEN), // .arlen
.h2f_ARSIZE (h2f_ARSIZE), // .arsize
.h2f_ARBURST (h2f_ARBURST), // .arburst
.h2f_ARLOCK (h2f_ARLOCK), // .arlock
.h2f_ARCACHE (h2f_ARCACHE), // .arcache
.h2f_ARPROT (h2f_ARPROT), // .arprot
.h2f_ARVALID (h2f_ARVALID), // .arvalid
.h2f_ARREADY (h2f_ARREADY), // .arready
.h2f_RID (h2f_RID), // .rid
.h2f_RDATA (h2f_RDATA), // .rdata
.h2f_RRESP (h2f_RRESP), // .rresp
.h2f_RLAST (h2f_RLAST), // .rlast
.h2f_RVALID (h2f_RVALID), // .rvalid
.h2f_RREADY (h2f_RREADY), // .rready
.f2h_irq_p0 (f2h_irq_p0), // f2h_irq0.irq
.f2h_irq_p1 (f2h_irq_p1) // f2h_irq1.irq
);
ik_swift_hps_0_hps_io hps_io (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_qspi_inst_IO0 (hps_io_qspi_inst_IO0), // .hps_io_qspi_inst_IO0
.hps_io_qspi_inst_IO1 (hps_io_qspi_inst_IO1), // .hps_io_qspi_inst_IO1
.hps_io_qspi_inst_IO2 (hps_io_qspi_inst_IO2), // .hps_io_qspi_inst_IO2
.hps_io_qspi_inst_IO3 (hps_io_qspi_inst_IO3), // .hps_io_qspi_inst_IO3
.hps_io_qspi_inst_SS0 (hps_io_qspi_inst_SS0), // .hps_io_qspi_inst_SS0
.hps_io_qspi_inst_CLK (hps_io_qspi_inst_CLK), // .hps_io_qspi_inst_CLK
.hps_io_sdio_inst_CMD (hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim0_inst_CLK (hps_io_spim0_inst_CLK), // .hps_io_spim0_inst_CLK
.hps_io_spim0_inst_MOSI (hps_io_spim0_inst_MOSI), // .hps_io_spim0_inst_MOSI
.hps_io_spim0_inst_MISO (hps_io_spim0_inst_MISO), // .hps_io_spim0_inst_MISO
.hps_io_spim0_inst_SS0 (hps_io_spim0_inst_SS0), // .hps_io_spim0_inst_SS0
.hps_io_spim1_inst_CLK (hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c1_inst_SDA (hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_i2c1_inst_SCL) // .hps_io_i2c1_inst_SCL
);
endmodule
|
/*
* spi_top.v
* Top-level module which encompasses the SPI map containing all the
* control registers, and the digital register test interface.
*/
module spi_top(
// Outputs
o_ena_spi_clk, o_sdo, o_drvb,
// Map read-only inputs
vi_adc_data, vi_dco_freq_count, i_dtst_value_a, i_dtst_value_b,
// Map write-only outputs
o_adc_samp, o_clk_step, o_dco_step_clk, o_dcycle_cal_0_step_clk,
o_dcycle_cal_1_step_clk, o_dlc_f2p_step_clk,
o_dlc_iir_0_step_clk, o_dlc_iir_1_step_clk,
o_dlc_iir_2_step_clk, o_dlc_iir_3_step_clk, o_dlc_pi_step_clk,
o_dlc_qnc_step_clk, o_dlc_step_clk, o_fdelta_cal_0_step_clk,
o_fdelta_cal_1_step_clk, o_fdelta_lms_0_step_clk,
o_fdelta_lms_1_step_clk, o_get_dco_freq, o_rfdc_0_step_clk,
o_rfdc_1_step_clk, o_rfdc_state_0_step_clk,
o_rfdc_state_1_step_clk, o_srst_dco, o_srst_dlc, o_srst_rfdc_0,
o_srst_rfdc_1, o_sync_samp_0, o_sync_samp_1,
// Map registered outputs
o_adc_pol, vo_atst_dac_sel, o_atst_drive_pad,
o_atst_pwm_dac_sel, vo_atst_sel, o_clkgen_clk_dco_pol,
vo_clkgen_clkf_sel, vo_clkgen_clkr_sel, vo_clkgen_clkv_sel,
vo_clkgen_dco_del, vo_clkgen_dlc_del, vo_clkgen_rfdc_del_0,
vo_clkgen_rfdc_del_1, vo_dac_data, vo_dco_amp_trim,
vo_dco_buffer_bias, o_dco_byp_agc, o_dco_ena_div_buffer,
o_dco_ena_fce_dem, o_dco_hold, o_dco_pol, vo_dco_requant_type,
vo_dco_tune, vo_dcycle_byp_m_0, vo_dcycle_byp_m_1,
o_dcycle_cal_0_hold, o_dcycle_cal_1_hold, o_dcycle_ena_cal_0,
o_dcycle_ena_cal_1, vo_dcycle_hyst_0, vo_dcycle_hyst_1,
vo_dcycle_target_0, vo_dcycle_target_1, o_dlc_ena_qnc,
o_dlc_ena_type2, o_dlc_f2p_hold, o_dlc_hold, o_dlc_iir_0_hold,
o_dlc_iir_1_hold, o_dlc_iir_2_hold, o_dlc_iir_3_hold,
o_dlc_iir_ena_0, o_dlc_iir_ena_1, o_dlc_iir_ena_2,
o_dlc_iir_ena_3, o_dlc_pi_hold, o_dlc_qnc_hold, vo_dmro_ifast_0,
vo_dmro_ifast_1, vo_dmro_islow_0, vo_dmro_islow_1,
vo_dmro_reg_frc_0, vo_dmro_reg_frc_1, o_dmro_rst_0,
o_dmro_rst_1, o_dmro_sel_manual_0, o_dmro_sel_manual_1,
vo_dmro_tune_0, vo_dmro_tune_1, o_dtst_drive_pad_a,
o_dtst_drive_pad_b, vo_dtst_sel_a, vo_dtst_sel_b, o_ena_dco,
o_ena_dlc, o_ena_ext_osc, o_ena_fbdiv_0, o_ena_fbdiv_1,
o_ena_rfdc_0, o_ena_rfdc_1, vo_fdelta_byp_knorm_0,
vo_fdelta_byp_knorm_1, o_fdelta_cal_0_hold, o_fdelta_cal_1_hold,
vo_fdelta_cal_gain_0, vo_fdelta_cal_gain_1, o_fdelta_del_v_0,
o_fdelta_del_v_1, o_fdelta_ena_cal_0, o_fdelta_ena_cal_1,
o_fdelta_lms_0_hold, o_fdelta_lms_1_hold, vo_frac_alpha,
vo_freq_meas_sel, o_gate_dco_fast, o_gate_dco_slow, o_gate_dlc,
o_gate_rfdc_0, o_gate_rfdc_1, o_ibias_sel_ext, vo_iir_pole_0,
vo_iir_pole_1, vo_iir_pole_2, vo_iir_pole_3, vo_integer_n,
o_ldo_dco_byp, o_ldo_dco_dis, o_ldo_dig_byp, vo_ldo_dig_trim,
o_ldo_dmro_byp_0, o_ldo_dmro_byp_1, vo_ldo_dmro_trim_0,
vo_ldo_dmro_trim_1, vo_ldo_fce_trim, vo_ldo_osc_trim,
o_ldo_pfd_byp_0, o_ldo_pfd_byp_1, vo_ldo_pfd_trim_0,
vo_ldo_pfd_trim_1, o_ldo_rfdc_dis_0, o_ldo_rfdc_dis_1,
vo_ldo_rfdiv_trim, o_ldo_sync_byp_0, o_ldo_sync_byp_1,
vo_ldo_sync_trim_0, vo_ldo_sync_trim_1, o_ldo_xo_byp,
o_ldo_xo_dis, vo_ldo_xo_trim, vo_num_ref_periods, vo_pfd_mode_0,
vo_pfd_mode_1, o_pfd_pol_0, o_pfd_pol_1, vo_pi_ki, vo_pi_km,
vo_pi_kp, vo_pswap_count_0, vo_pswap_count_1, o_pswap_ena_0,
o_pswap_ena_1, vo_ref_clk_sel, o_ref_pol_0, o_ref_pol_1,
o_rfdc_0_hold, o_rfdc_1_hold, vo_rfdc_path_sel, o_rfdc_pol_0,
o_rfdc_pol_1, o_rfdc_state_0_hold, o_rfdc_state_1_hold,
o_rng_ena_dco_req, o_rng_ena_dlc_req, o_rng_ena_iir_req_0,
o_rng_ena_iir_req_1, o_rng_ena_iir_req_2, o_rng_ena_iir_req_3,
o_rng_ena_pi_req, o_rng_ena_pswap_0, o_rng_ena_pswap_1,
vo_sync_del_0, vo_sync_del_1, o_sync_mode_0, o_sync_mode_1,
o_sync_pol_0, o_sync_pol_1,
// Register read signals
o_dco_rd, o_dcycle_cal_0_rd, o_dcycle_cal_1_rd, o_dlc_rd,
o_dlc_f2p_rd, o_dlc_iir_0_rd, o_dlc_iir_1_rd, o_dlc_iir_2_rd,
o_dlc_iir_3_rd, o_dlc_pi_rd, o_dlc_qnc_rd, o_fdelta_cal_0_rd,
o_fdelta_cal_1_rd, o_fdelta_lms_0_rd, o_fdelta_lms_1_rd,
o_rfdc_0_rd, o_rfdc_1_rd, o_rfdc_state_0_rd, o_rfdc_state_1_rd,
// Register write signals
o_dco_wr, o_dcycle_cal_0_wr, o_dcycle_cal_1_wr, o_dlc_wr,
o_dlc_f2p_wr, o_dlc_iir_0_wr, o_dlc_iir_1_wr, o_dlc_iir_2_wr,
o_dlc_iir_3_wr, o_dlc_pi_wr, o_dlc_qnc_wr, o_fdelta_cal_0_wr,
o_fdelta_cal_1_wr, o_fdelta_lms_0_wr, o_fdelta_lms_1_wr,
o_rfdc_0_wr, o_rfdc_1_wr, o_rfdc_state_0_wr, o_rfdc_state_1_wr,
// Inouts
io_success, vio_tbus,
// Inputs
i_rstb, i_clk_ext_osc, i_cs, i_sck, i_sdi);
// Clock and reset
input i_rstb;
input i_clk_ext_osc;
output o_ena_spi_clk;
// SPI interface
output o_sdo;
output o_drvb;
input i_cs;
input i_sck;
input i_sdi;
// SPI map controls
// Read-only inputs
input [7:0] vi_adc_data;
input [15:0] vi_dco_freq_count;
input i_dtst_value_a;
input i_dtst_value_b;
// Write-only inputs
output o_adc_samp;
output o_clk_step;
output o_dco_step_clk;
output o_dcycle_cal_0_step_clk;
output o_dcycle_cal_1_step_clk;
output o_dlc_f2p_step_clk;
output o_dlc_iir_0_step_clk;
output o_dlc_iir_1_step_clk;
output o_dlc_iir_2_step_clk;
output o_dlc_iir_3_step_clk;
output o_dlc_pi_step_clk;
output o_dlc_qnc_step_clk;
output o_dlc_step_clk;
output o_fdelta_cal_0_step_clk;
output o_fdelta_cal_1_step_clk;
output o_fdelta_lms_0_step_clk;
output o_fdelta_lms_1_step_clk;
output o_get_dco_freq;
output o_rfdc_0_step_clk;
output o_rfdc_1_step_clk;
output o_rfdc_state_0_step_clk;
output o_rfdc_state_1_step_clk;
output o_srst_dco;
output o_srst_dlc;
output o_srst_rfdc_0;
output o_srst_rfdc_1;
output o_sync_samp_0;
output o_sync_samp_1;
// Registered outputs
output o_adc_pol;
output [3:0] vo_atst_dac_sel;
output o_atst_drive_pad;
output o_atst_pwm_dac_sel;
output [4:0] vo_atst_sel;
output o_clkgen_clk_dco_pol;
output [1:0] vo_clkgen_clkf_sel;
output [1:0] vo_clkgen_clkr_sel;
output [1:0] vo_clkgen_clkv_sel;
output [3:0] vo_clkgen_dco_del;
output [3:0] vo_clkgen_dlc_del;
output [3:0] vo_clkgen_rfdc_del_0;
output [3:0] vo_clkgen_rfdc_del_1;
output [9:0] vo_dac_data;
output [2:0] vo_dco_amp_trim;
output [2:0] vo_dco_buffer_bias;
output o_dco_byp_agc;
output o_dco_ena_div_buffer;
output o_dco_ena_fce_dem;
output o_dco_hold;
output o_dco_pol;
output [1:0] vo_dco_requant_type;
output [6:0] vo_dco_tune;
output [6:0] vo_dcycle_byp_m_0;
output [6:0] vo_dcycle_byp_m_1;
output o_dcycle_cal_0_hold;
output o_dcycle_cal_1_hold;
output o_dcycle_ena_cal_0;
output o_dcycle_ena_cal_1;
output [3:0] vo_dcycle_hyst_0;
output [3:0] vo_dcycle_hyst_1;
output [7:0] vo_dcycle_target_0;
output [7:0] vo_dcycle_target_1;
output o_dlc_ena_qnc;
output o_dlc_ena_type2;
output o_dlc_f2p_hold;
output o_dlc_hold;
output o_dlc_iir_0_hold;
output o_dlc_iir_1_hold;
output o_dlc_iir_2_hold;
output o_dlc_iir_3_hold;
output o_dlc_iir_ena_0;
output o_dlc_iir_ena_1;
output o_dlc_iir_ena_2;
output o_dlc_iir_ena_3;
output o_dlc_pi_hold;
output o_dlc_qnc_hold;
output [6:0] vo_dmro_ifast_0;
output [6:0] vo_dmro_ifast_1;
output [3:0] vo_dmro_islow_0;
output [3:0] vo_dmro_islow_1;
output [1:0] vo_dmro_reg_frc_0;
output [1:0] vo_dmro_reg_frc_1;
output o_dmro_rst_0;
output o_dmro_rst_1;
output o_dmro_sel_manual_0;
output o_dmro_sel_manual_1;
output [2:0] vo_dmro_tune_0;
output [2:0] vo_dmro_tune_1;
output o_dtst_drive_pad_a;
output o_dtst_drive_pad_b;
output [4:0] vo_dtst_sel_a;
output [4:0] vo_dtst_sel_b;
output o_ena_dco;
output o_ena_dlc;
output o_ena_ext_osc;
output o_ena_fbdiv_0;
output o_ena_fbdiv_1;
output o_ena_rfdc_0;
output o_ena_rfdc_1;
output [9:0] vo_fdelta_byp_knorm_0;
output [9:0] vo_fdelta_byp_knorm_1;
output o_fdelta_cal_0_hold;
output o_fdelta_cal_1_hold;
output [2:0] vo_fdelta_cal_gain_0;
output [2:0] vo_fdelta_cal_gain_1;
output o_fdelta_del_v_0;
output o_fdelta_del_v_1;
output o_fdelta_ena_cal_0;
output o_fdelta_ena_cal_1;
output o_fdelta_lms_0_hold;
output o_fdelta_lms_1_hold;
output [15:0] vo_frac_alpha;
output [1:0] vo_freq_meas_sel;
output o_gate_dco_fast;
output o_gate_dco_slow;
output o_gate_dlc;
output o_gate_rfdc_0;
output o_gate_rfdc_1;
output o_ibias_sel_ext;
output [2:0] vo_iir_pole_0;
output [2:0] vo_iir_pole_1;
output [2:0] vo_iir_pole_2;
output [2:0] vo_iir_pole_3;
output [7:0] vo_integer_n;
output o_ldo_dco_byp;
output o_ldo_dco_dis;
output o_ldo_dig_byp;
output [2:0] vo_ldo_dig_trim;
output o_ldo_dmro_byp_0;
output o_ldo_dmro_byp_1;
output [2:0] vo_ldo_dmro_trim_0;
output [2:0] vo_ldo_dmro_trim_1;
output [2:0] vo_ldo_fce_trim;
output [2:0] vo_ldo_osc_trim;
output o_ldo_pfd_byp_0;
output o_ldo_pfd_byp_1;
output [2:0] vo_ldo_pfd_trim_0;
output [2:0] vo_ldo_pfd_trim_1;
output o_ldo_rfdc_dis_0;
output o_ldo_rfdc_dis_1;
output [2:0] vo_ldo_rfdiv_trim;
output o_ldo_sync_byp_0;
output o_ldo_sync_byp_1;
output [2:0] vo_ldo_sync_trim_0;
output [2:0] vo_ldo_sync_trim_1;
output o_ldo_xo_byp;
output o_ldo_xo_dis;
output [2:0] vo_ldo_xo_trim;
output [1:0] vo_num_ref_periods;
output [1:0] vo_pfd_mode_0;
output [1:0] vo_pfd_mode_1;
output o_pfd_pol_0;
output o_pfd_pol_1;
output [3:0] vo_pi_ki;
output [1:0] vo_pi_km;
output [3:0] vo_pi_kp;
output [5:0] vo_pswap_count_0;
output [5:0] vo_pswap_count_1;
output o_pswap_ena_0;
output o_pswap_ena_1;
output [1:0] vo_ref_clk_sel;
output o_ref_pol_0;
output o_ref_pol_1;
output o_rfdc_0_hold;
output o_rfdc_1_hold;
output [1:0] vo_rfdc_path_sel;
output o_rfdc_pol_0;
output o_rfdc_pol_1;
output o_rfdc_state_0_hold;
output o_rfdc_state_1_hold;
output o_rng_ena_dco_req;
output o_rng_ena_dlc_req;
output o_rng_ena_iir_req_0;
output o_rng_ena_iir_req_1;
output o_rng_ena_iir_req_2;
output o_rng_ena_iir_req_3;
output o_rng_ena_pi_req;
output o_rng_ena_pswap_0;
output o_rng_ena_pswap_1;
output [3:0] vo_sync_del_0;
output [3:0] vo_sync_del_1;
output o_sync_mode_0;
output o_sync_mode_1;
output o_sync_pol_0;
output o_sync_pol_1;
// Digital register interface
inout io_success;
inout [36:0] vio_tbus;
// Register read signals
output o_dco_rd;
output o_dcycle_cal_0_rd;
output o_dcycle_cal_1_rd;
output o_dlc_rd;
output o_dlc_f2p_rd;
output o_dlc_iir_0_rd;
output o_dlc_iir_1_rd;
output o_dlc_iir_2_rd;
output o_dlc_iir_3_rd;
output o_dlc_pi_rd;
output o_dlc_qnc_rd;
output o_fdelta_cal_0_rd;
output o_fdelta_cal_1_rd;
output o_fdelta_lms_0_rd;
output o_fdelta_lms_1_rd;
output o_rfdc_0_rd;
output o_rfdc_1_rd;
output o_rfdc_state_0_rd;
output o_rfdc_state_1_rd;
// Register write signals
output o_dco_wr;
output o_dcycle_cal_0_wr;
output o_dcycle_cal_1_wr;
output o_dlc_wr;
output o_dlc_f2p_wr;
output o_dlc_iir_0_wr;
output o_dlc_iir_1_wr;
output o_dlc_iir_2_wr;
output o_dlc_iir_3_wr;
output o_dlc_pi_wr;
output o_dlc_qnc_wr;
output o_fdelta_cal_0_wr;
output o_fdelta_cal_1_wr;
output o_fdelta_lms_0_wr;
output o_fdelta_lms_1_wr;
output o_rfdc_0_wr;
output o_rfdc_1_wr;
output o_rfdc_state_0_wr;
output o_rfdc_state_1_wr;
/*
* SPI core
*/
wire spi_active;
wire rx_valid;
wire [2:0] v_byte_num;
wire [7:0] v_data_rx;
wire [7:0] v_data_tx;
assign o_ena_spi_clk = spi_active;
spi_core #(.BITS_IN_BYTE(8), .NBIT_BIT_CTR(3), .NBIT_BYTE_CTR(3))
spi_interface(
// Outputs
.o_sdo (o_sdo),
.o_drvb (o_drvb),
.o_spi_active (spi_active),
.o_rx_valid (rx_valid),
.vo_byte_num (v_byte_num),
.vo_data_rx (v_data_rx),
// Inputs
.i_rstb (i_rstb),
.i_cs (i_cs),
.i_sck (i_sck),
.i_sdi (i_sdi),
.i_epol (1'b1),
.i_cpol (1'b1),
.i_cpha (1'b0),
.vi_data_tx (v_data_tx));
/*
* SPI map
*/
spi_map
spi_map_interface(
// Read-only inputs
.vi_adc_data (vi_adc_data),
.vi_dco_freq_count (vi_dco_freq_count),
.i_dtst_value_a (i_dtst_value_a),
.i_dtst_value_b (i_dtst_value_b),
// Write-only inputs
.o_adc_samp (o_adc_samp),
.o_clk_step (o_clk_step),
.o_dco_step_clk (o_dco_step_clk),
.o_dcycle_cal_0_step_clk (o_dcycle_cal_0_step_clk),
.o_dcycle_cal_1_step_clk (o_dcycle_cal_1_step_clk),
.o_dlc_f2p_step_clk (o_dlc_f2p_step_clk),
.o_dlc_iir_0_step_clk (o_dlc_iir_0_step_clk),
.o_dlc_iir_1_step_clk (o_dlc_iir_1_step_clk),
.o_dlc_iir_2_step_clk (o_dlc_iir_2_step_clk),
.o_dlc_iir_3_step_clk (o_dlc_iir_3_step_clk),
.o_dlc_pi_step_clk (o_dlc_pi_step_clk),
.o_dlc_qnc_step_clk (o_dlc_qnc_step_clk),
.o_dlc_step_clk (o_dlc_step_clk),
.o_fdelta_cal_0_step_clk (o_fdelta_cal_0_step_clk),
.o_fdelta_cal_1_step_clk (o_fdelta_cal_1_step_clk),
.o_fdelta_lms_0_step_clk (o_fdelta_lms_0_step_clk),
.o_fdelta_lms_1_step_clk (o_fdelta_lms_1_step_clk),
.o_get_dco_freq (o_get_dco_freq),
.o_rfdc_0_step_clk (o_rfdc_0_step_clk),
.o_rfdc_1_step_clk (o_rfdc_1_step_clk),
.o_rfdc_state_0_step_clk (o_rfdc_state_0_step_clk),
.o_rfdc_state_1_step_clk (o_rfdc_state_1_step_clk),
.o_srst_dco (o_srst_dco),
.o_srst_dlc (o_srst_dlc),
.o_srst_rfdc_0 (o_srst_rfdc_0),
.o_srst_rfdc_1 (o_srst_rfdc_1),
.o_sync_samp_0 (o_sync_samp_0),
.o_sync_samp_1 (o_sync_samp_1),
// Registered outputs
.o_adc_pol (o_adc_pol),
.vo_atst_dac_sel (vo_atst_dac_sel),
.o_atst_drive_pad (o_atst_drive_pad),
.o_atst_pwm_dac_sel (o_atst_pwm_dac_sel),
.vo_atst_sel (vo_atst_sel),
.o_clkgen_clk_dco_pol (o_clkgen_clk_dco_pol),
.vo_clkgen_clkf_sel (vo_clkgen_clkf_sel),
.vo_clkgen_clkr_sel (vo_clkgen_clkr_sel),
.vo_clkgen_clkv_sel (vo_clkgen_clkv_sel),
.vo_clkgen_dco_del (vo_clkgen_dco_del),
.vo_clkgen_dlc_del (vo_clkgen_dlc_del),
.vo_clkgen_rfdc_del_0 (vo_clkgen_rfdc_del_0),
.vo_clkgen_rfdc_del_1 (vo_clkgen_rfdc_del_1),
.vo_dac_data (vo_dac_data),
.vo_dco_amp_trim (vo_dco_amp_trim),
.vo_dco_buffer_bias (vo_dco_buffer_bias),
.o_dco_byp_agc (o_dco_byp_agc),
.o_dco_ena_div_buffer (o_dco_ena_div_buffer),
.o_dco_ena_fce_dem (o_dco_ena_fce_dem),
.o_dco_hold (o_dco_hold),
.o_dco_pol (o_dco_pol),
.vo_dco_requant_type (vo_dco_requant_type),
.vo_dco_tune (vo_dco_tune),
.vo_dcycle_byp_m_0 (vo_dcycle_byp_m_0),
.vo_dcycle_byp_m_1 (vo_dcycle_byp_m_1),
.o_dcycle_cal_0_hold (o_dcycle_cal_0_hold),
.o_dcycle_cal_1_hold (o_dcycle_cal_1_hold),
.o_dcycle_ena_cal_0 (o_dcycle_ena_cal_0),
.o_dcycle_ena_cal_1 (o_dcycle_ena_cal_1),
.vo_dcycle_hyst_0 (vo_dcycle_hyst_0),
.vo_dcycle_hyst_1 (vo_dcycle_hyst_1),
.vo_dcycle_target_0 (vo_dcycle_target_0),
.vo_dcycle_target_1 (vo_dcycle_target_1),
.o_dlc_ena_qnc (o_dlc_ena_qnc),
.o_dlc_ena_type2 (o_dlc_ena_type2),
.o_dlc_f2p_hold (o_dlc_f2p_hold),
.o_dlc_hold (o_dlc_hold),
.o_dlc_iir_0_hold (o_dlc_iir_0_hold),
.o_dlc_iir_1_hold (o_dlc_iir_1_hold),
.o_dlc_iir_2_hold (o_dlc_iir_2_hold),
.o_dlc_iir_3_hold (o_dlc_iir_3_hold),
.o_dlc_iir_ena_0 (o_dlc_iir_ena_0),
.o_dlc_iir_ena_1 (o_dlc_iir_ena_1),
.o_dlc_iir_ena_2 (o_dlc_iir_ena_2),
.o_dlc_iir_ena_3 (o_dlc_iir_ena_3),
.o_dlc_pi_hold (o_dlc_pi_hold),
.o_dlc_qnc_hold (o_dlc_qnc_hold),
.vo_dmro_ifast_0 (vo_dmro_ifast_0),
.vo_dmro_ifast_1 (vo_dmro_ifast_1),
.vo_dmro_islow_0 (vo_dmro_islow_0),
.vo_dmro_islow_1 (vo_dmro_islow_1),
.vo_dmro_reg_frc_0 (vo_dmro_reg_frc_0),
.vo_dmro_reg_frc_1 (vo_dmro_reg_frc_1),
.o_dmro_rst_0 (o_dmro_rst_0),
.o_dmro_rst_1 (o_dmro_rst_1),
.o_dmro_sel_manual_0 (o_dmro_sel_manual_0),
.o_dmro_sel_manual_1 (o_dmro_sel_manual_1),
.vo_dmro_tune_0 (vo_dmro_tune_0),
.vo_dmro_tune_1 (vo_dmro_tune_1),
.o_dtst_drive_pad_a (o_dtst_drive_pad_a),
.o_dtst_drive_pad_b (o_dtst_drive_pad_b),
.vo_dtst_sel_a (vo_dtst_sel_a),
.vo_dtst_sel_b (vo_dtst_sel_b),
.o_ena_dco (o_ena_dco),
.o_ena_dlc (o_ena_dlc),
.o_ena_ext_osc (o_ena_ext_osc),
.o_ena_fbdiv_0 (o_ena_fbdiv_0),
.o_ena_fbdiv_1 (o_ena_fbdiv_1),
.o_ena_rfdc_0 (o_ena_rfdc_0),
.o_ena_rfdc_1 (o_ena_rfdc_1),
.vo_fdelta_byp_knorm_0 (vo_fdelta_byp_knorm_0),
.vo_fdelta_byp_knorm_1 (vo_fdelta_byp_knorm_1),
.o_fdelta_cal_0_hold (o_fdelta_cal_0_hold),
.o_fdelta_cal_1_hold (o_fdelta_cal_1_hold),
.vo_fdelta_cal_gain_0 (vo_fdelta_cal_gain_0),
.vo_fdelta_cal_gain_1 (vo_fdelta_cal_gain_1),
.o_fdelta_del_v_0 (o_fdelta_del_v_0),
.o_fdelta_del_v_1 (o_fdelta_del_v_1),
.o_fdelta_ena_cal_0 (o_fdelta_ena_cal_0),
.o_fdelta_ena_cal_1 (o_fdelta_ena_cal_1),
.o_fdelta_lms_0_hold (o_fdelta_lms_0_hold),
.o_fdelta_lms_1_hold (o_fdelta_lms_1_hold),
.vo_frac_alpha (vo_frac_alpha),
.vo_freq_meas_sel (vo_freq_meas_sel),
.o_gate_dco_fast (o_gate_dco_fast),
.o_gate_dco_slow (o_gate_dco_slow),
.o_gate_dlc (o_gate_dlc),
.o_gate_rfdc_0 (o_gate_rfdc_0),
.o_gate_rfdc_1 (o_gate_rfdc_1),
.o_ibias_sel_ext (o_ibias_sel_ext),
.vo_iir_pole_0 (vo_iir_pole_0),
.vo_iir_pole_1 (vo_iir_pole_1),
.vo_iir_pole_2 (vo_iir_pole_2),
.vo_iir_pole_3 (vo_iir_pole_3),
.vo_integer_n (vo_integer_n),
.o_ldo_dco_byp (o_ldo_dco_byp),
.o_ldo_dco_dis (o_ldo_dco_dis),
.o_ldo_dig_byp (o_ldo_dig_byp),
.vo_ldo_dig_trim (vo_ldo_dig_trim),
.o_ldo_dmro_byp_0 (o_ldo_dmro_byp_0),
.o_ldo_dmro_byp_1 (o_ldo_dmro_byp_1),
.vo_ldo_dmro_trim_0 (vo_ldo_dmro_trim_0),
.vo_ldo_dmro_trim_1 (vo_ldo_dmro_trim_1),
.vo_ldo_fce_trim (vo_ldo_fce_trim),
.vo_ldo_osc_trim (vo_ldo_osc_trim),
.o_ldo_pfd_byp_0 (o_ldo_pfd_byp_0),
.o_ldo_pfd_byp_1 (o_ldo_pfd_byp_1),
.vo_ldo_pfd_trim_0 (vo_ldo_pfd_trim_0),
.vo_ldo_pfd_trim_1 (vo_ldo_pfd_trim_1),
.o_ldo_rfdc_dis_0 (o_ldo_rfdc_dis_0),
.o_ldo_rfdc_dis_1 (o_ldo_rfdc_dis_1),
.vo_ldo_rfdiv_trim (vo_ldo_rfdiv_trim),
.o_ldo_sync_byp_0 (o_ldo_sync_byp_0),
.o_ldo_sync_byp_1 (o_ldo_sync_byp_1),
.vo_ldo_sync_trim_0 (vo_ldo_sync_trim_0),
.vo_ldo_sync_trim_1 (vo_ldo_sync_trim_1),
.o_ldo_xo_byp (o_ldo_xo_byp),
.o_ldo_xo_dis (o_ldo_xo_dis),
.vo_ldo_xo_trim (vo_ldo_xo_trim),
.vo_num_ref_periods (vo_num_ref_periods),
.vo_pfd_mode_0 (vo_pfd_mode_0),
.vo_pfd_mode_1 (vo_pfd_mode_1),
.o_pfd_pol_0 (o_pfd_pol_0),
.o_pfd_pol_1 (o_pfd_pol_1),
.vo_pi_ki (vo_pi_ki),
.vo_pi_km (vo_pi_km),
.vo_pi_kp (vo_pi_kp),
.vo_pswap_count_0 (vo_pswap_count_0),
.vo_pswap_count_1 (vo_pswap_count_1),
.o_pswap_ena_0 (o_pswap_ena_0),
.o_pswap_ena_1 (o_pswap_ena_1),
.vo_ref_clk_sel (vo_ref_clk_sel),
.o_ref_pol_0 (o_ref_pol_0),
.o_ref_pol_1 (o_ref_pol_1),
.o_rfdc_0_hold (o_rfdc_0_hold),
.o_rfdc_1_hold (o_rfdc_1_hold),
.vo_rfdc_path_sel (vo_rfdc_path_sel),
.o_rfdc_pol_0 (o_rfdc_pol_0),
.o_rfdc_pol_1 (o_rfdc_pol_1),
.o_rfdc_state_0_hold (o_rfdc_state_0_hold),
.o_rfdc_state_1_hold (o_rfdc_state_1_hold),
.o_rng_ena_dco_req (o_rng_ena_dco_req),
.o_rng_ena_dlc_req (o_rng_ena_dlc_req),
.o_rng_ena_iir_req_0 (o_rng_ena_iir_req_0),
.o_rng_ena_iir_req_1 (o_rng_ena_iir_req_1),
.o_rng_ena_iir_req_2 (o_rng_ena_iir_req_2),
.o_rng_ena_iir_req_3 (o_rng_ena_iir_req_3),
.o_rng_ena_pi_req (o_rng_ena_pi_req),
.o_rng_ena_pswap_0 (o_rng_ena_pswap_0),
.o_rng_ena_pswap_1 (o_rng_ena_pswap_1),
.vo_sync_del_0 (vo_sync_del_0),
.vo_sync_del_1 (vo_sync_del_1),
.o_sync_mode_0 (o_sync_mode_0),
.o_sync_mode_1 (o_sync_mode_1),
.o_sync_pol_0 (o_sync_pol_0),
.o_sync_pol_1 (o_sync_pol_1),
// Inouts
.vio_data_spi (v_data_tx),
// Inputs
.i_rstb (i_rstb),
.i_spi_active (spi_active),
.vi_data_rx (v_data_rx),
.i_rx_valid (rx_valid),
.vi_byte_num (v_byte_num));
/*
* SPI reg
*/
spi_reg
spi_reg_interface(// Register read signals
.o_dco_rd (o_dco_rd),
.o_dcycle_cal_0_rd (o_dcycle_cal_0_rd),
.o_dcycle_cal_1_rd (o_dcycle_cal_1_rd),
.o_dlc_rd (o_dlc_rd),
.o_dlc_f2p_rd (o_dlc_f2p_rd),
.o_dlc_iir_0_rd (o_dlc_iir_0_rd),
.o_dlc_iir_1_rd (o_dlc_iir_1_rd),
.o_dlc_iir_2_rd (o_dlc_iir_2_rd),
.o_dlc_iir_3_rd (o_dlc_iir_3_rd),
.o_dlc_pi_rd (o_dlc_pi_rd),
.o_dlc_qnc_rd (o_dlc_qnc_rd),
.o_fdelta_cal_0_rd (o_fdelta_cal_0_rd),
.o_fdelta_cal_1_rd (o_fdelta_cal_1_rd),
.o_fdelta_lms_0_rd (o_fdelta_lms_0_rd),
.o_fdelta_lms_1_rd (o_fdelta_lms_1_rd),
.o_rfdc_0_rd (o_rfdc_0_rd),
.o_rfdc_1_rd (o_rfdc_1_rd),
.o_rfdc_state_0_rd (o_rfdc_state_0_rd),
.o_rfdc_state_1_rd (o_rfdc_state_1_rd),
// Register write signals
.o_dco_wr (o_dco_wr),
.o_dcycle_cal_0_wr (o_dcycle_cal_0_wr),
.o_dcycle_cal_1_wr (o_dcycle_cal_1_wr),
.o_dlc_wr (o_dlc_wr),
.o_dlc_f2p_wr (o_dlc_f2p_wr),
.o_dlc_iir_0_wr (o_dlc_iir_0_wr),
.o_dlc_iir_1_wr (o_dlc_iir_1_wr),
.o_dlc_iir_2_wr (o_dlc_iir_2_wr),
.o_dlc_iir_3_wr (o_dlc_iir_3_wr),
.o_dlc_pi_wr (o_dlc_pi_wr),
.o_dlc_qnc_wr (o_dlc_qnc_wr),
.o_fdelta_cal_0_wr (o_fdelta_cal_0_wr),
.o_fdelta_cal_1_wr (o_fdelta_cal_1_wr),
.o_fdelta_lms_0_wr (o_fdelta_lms_0_wr),
.o_fdelta_lms_1_wr (o_fdelta_lms_1_wr),
.o_rfdc_0_wr (o_rfdc_0_wr),
.o_rfdc_1_wr (o_rfdc_1_wr),
.o_rfdc_state_0_wr (o_rfdc_state_0_wr),
.o_rfdc_state_1_wr (o_rfdc_state_1_wr),
// Inouts
.vio_data_regs (v_data_tx),
.io_success (io_success),
.vio_tbus (vio_tbus),
// Inputs
.i_rstb (i_rstb),
.i_clk_ext_osc (i_clk_ext_osc),
.i_spi_active (spi_active),
.vi_data_rx (v_data_rx),
.i_rx_valid (rx_valid),
.vi_byte_num (v_byte_num));
// Local Variables:
// verilog-library-directories:("/home/colinww/git/doormat_dig/scripts/spi_generation/" "/home/colinww/git/doormat_dig/source/spi_dig/")
// verilog-library-extensions:(".v" ".h")
// End:
endmodule // spi_top
|
// Directive indicates that 1ns is the time period used when specifying delays
// (i.e., #10 means 10ns); 100ps is the smallest unit of time precision that
// will be simulated (100ps = .1ns; thus #.1 is meaningful, #.00001 is equivalent
// to #0)
`timescale 1ns / 100ps
module testbench ();
reg clk;
reg reset_;
reg up_;
reg down_;
reg left_;
reg right_;
wire [6:0] segment_;
wire [3:0] digit_enable_;
// Create an instance of the circuit under test
konamiacceptor uut (
.clk(clk),
.reset_(reset_),
.up_(up_),
.down_(down_),
.left_(left_),
.right_(right_),
.segment_(segment_),
.digit_enable_(digit_enable_)
);
always@ (uut.state)
$display("Konami state changed to %d (%s)", uut.state,
uut.state == 4'd0 ? "START" :
uut.state == 4'd1 ? "UP_1" :
uut.state == 4'd2 ? "UP_2" :
uut.state == 4'd3 ? "DOWN_1" :
uut.state == 4'd4 ? "DOWN_2" :
uut.state == 4'd5 ? "LEFT_1" :
uut.state == 4'd6 ? "RIGHT_1" :
uut.state == 4'd7 ? "LEFT_2" :
uut.state == 4'd9 ? "ACCEPT" :
uut.state == 4'd10 ? "REJECT" : "(BUG!)"
);
// Initialize the clock signal to zero; drive reset_ active (low) for the
// first 100ns of the simulation.
initial begin
clk = 1'b0;
reset_ = 1'b0;
up_ = 1'b1;
down_ = 1'b1;
left_ = 1'b1;
right_ = 1'b1;
#100 reset_ = 1'b1;
end
// Stop the simulation after 400ms; note that simulations can run indefinitely
// (with waveforms loaded incrementally in the viewer.) Press ctrl-c to break
// iverilog, then enter '$finish' to stop the simulation.
initial begin
#400000000 $finish; // 400ms
end
// Toggle the clock every 31.25ns (32 MHz frequency)
initial begin forever
#31.25 clk = ~clk;
end
initial begin
#500;
press_up();
press_up();
press_down();
press_down();
press_left();
press_right();
press_left();
press_right();
#100000;
$finish;
end
// Produce a waveform output of this simulation
initial begin
$dumpfile("waveform.vcd");
$dumpvars();
end
task press_up;
begin
up_ <= 1'b0;
@(posedge uut.up_debounced);
up_ <= 1'b1;
@(negedge uut.up_debounced);
end
endtask
task press_down;
begin
down_ <= 1'b0;
@(posedge uut.down_debounced);
down_ <= 1'b1;
@(negedge uut.down_debounced);
end
endtask
task press_left;
begin
left_ <= 1'b0;
@(posedge uut.left_debounced);
left_ <= 1'b1;
@(negedge uut.left_debounced);
end
endtask
task press_right;
begin
right_ <= 1'b0;
@(posedge uut.right_debounced);
right_ <= 1'b1;
@(negedge uut.right_debounced);
end
endtask
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21BO_BEHAVIORAL_V
`define SKY130_FD_SC_HS__A21BO_BEHAVIORAL_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a21bo (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
// Local signals
wire nand0_out ;
wire nand1_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X , B1_N, nand0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, nand1_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21BO_BEHAVIORAL_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_cclk_hdr_64x.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_clk_cclk_hdr_64x (/*AUTOARG*/
// Outputs
rst_l, dbginit_l, clk, so,
// Inputs
gclk, cluster_cken, arst_l, grst_l, adbginit_l, gdbginit_l, si, se,
rclk
);
input gclk;
input rclk;
input cluster_cken;
input arst_l;
input grst_l;
input adbginit_l;
input gdbginit_l;
output dbginit_l;
output rst_l;
output clk;
input si; //scan ports for reset flop repeaters
input se;
output so;
wire pre_sync_enable;
wire sync_enable;
wire cluster_grst_l;
wire dbginit_l;
wire rst_sync_so;
bw_u1_syncff_4x sync_cluster_master ( // no scan hook-up
.so(),
.q (pre_sync_enable),
.ck (gclk),
.d (cluster_cken),
.sd(1'b0),
.se(1'b0)
);
bw_u1_scanlg_2x sync_cluster_slave ( // use scan lock-up latch
.so (sync_enable),
.ck (gclk),
.sd (pre_sync_enable),
.se(1'b1)
);
// NOTE! Pound delay in the below statement is meant to provide 10 ps
// delay between gclk and rclk to allow the synchronizer for rst, dbginit,
// and sync pulses to be modelled accurately. gclk and rclk need to have
// at least one simulator timestep separation to allow the flop->flop
// synchronizer to work correctly.
assign #10 clk = gclk & sync_enable;
synchronizer_asr rst_repeater (
.sync_out(rst_l),
.so(rst_sync_so),
.async_in(grst_l),
.gclk(gclk),
.rclk(rclk),
.arst_l(arst_l),
.si(si),
.se(se)
);
synchronizer_asr dbginit_repeater (
.sync_out(dbginit_l),
.so(so),
.async_in(gdbginit_l),
.gclk(gclk),
.rclk(rclk),
.arst_l(adbginit_l),
.si(rst_sync_so),
.se(se)
);
endmodule // bw_clk_cclk_hdr_64x
|
// -----------------------------------------------------------------------
//
// Copyright 2004,2007-2008 Tommy Thorn - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
`timescale 1ns/10ps
module rs232in
(// Control
input wire clock,
// Serial line
input wire serial_in,
output reg attention = 0,
output reg [7:0] received_data = 0);
parameter bps = 57_600;
parameter frequency = 25_000_000;
parameter period = (frequency + bps/2) / bps;
reg [16:0] ttyclk = 0;
wire [31:0] ttyclk_bit = period - 2;
wire [31:0] ttyclk_start = (3 * period) / 2 - 2;
reg [ 7:0] shift_in = 0;
reg [ 4:0] count = 0;
reg rxd = 0;
reg rxd2 = 0;
/*
* The theory: look for a negedge, then wait 1.5 bit period to skip
* start bit and center in first bit. Keep shifting bits until a full
* byte is collected.
*
* Start Stop
* data ~\__ B0 B1 B2 B3 B4 B5 B6 B7 ~~
* count 8 7 6 5 4 3 2 1
*/
always @(posedge clock) begin
attention <= 0;
// Get rid of meta stability.
{rxd2,rxd} <= {rxd,serial_in};
if (~ttyclk[16]) begin
ttyclk <= ttyclk - 1'd1;
end else if (count) begin
if (count == 1) begin
received_data <= {rxd2, shift_in[7:1]};
attention <= 1;
end
count <= count - 1'd1;
shift_in <= {rxd2, shift_in[7:1]}; // Shift in from the left
ttyclk <= ttyclk_bit[16:0];
end else if (~rxd2) begin
// Just saw the negedge of the start bit
ttyclk <= ttyclk_start[16:0];
count <= 8;
end
end
endmodule
|
module nios_dut (
audio_in_data,
audio_in_valid,
audio_in_ready,
audio_out_data,
audio_out_valid,
audio_out_ready,
dummy_export,
io_ack,
io_rdata,
io_read,
io_wdata,
io_write,
io_address,
io_irq,
io_u2p_ack,
io_u2p_rdata,
io_u2p_read,
io_u2p_wdata,
io_u2p_write,
io_u2p_address,
io_u2p_irq,
jtag_io_input_vector,
jtag_io_output_vector,
jtag_test_clocks_clock_1,
jtag_test_clocks_clock_2,
mem_mem_req_address,
mem_mem_req_byte_en,
mem_mem_req_read_writen,
mem_mem_req_request,
mem_mem_req_tag,
mem_mem_req_wdata,
mem_mem_resp_dack_tag,
mem_mem_resp_data,
mem_mem_resp_rack_tag,
pio1_export,
pio2_export,
pio3_export,
sys_clock_clk,
sys_reset_reset_n,
uart_rxd,
uart_txd,
uart_cts_n,
uart_rts_n);
input [31:0] audio_in_data;
input audio_in_valid;
output audio_in_ready;
output [31:0] audio_out_data;
output audio_out_valid;
input audio_out_ready;
input dummy_export;
input io_ack;
input [7:0] io_rdata;
output io_read;
output [7:0] io_wdata;
output io_write;
output [19:0] io_address;
input io_irq;
input io_u2p_ack;
input [7:0] io_u2p_rdata;
output io_u2p_read;
output [7:0] io_u2p_wdata;
output io_u2p_write;
output [19:0] io_u2p_address;
input io_u2p_irq;
input [47:0] jtag_io_input_vector;
output [7:0] jtag_io_output_vector;
input jtag_test_clocks_clock_1;
input jtag_test_clocks_clock_2;
output [25:0] mem_mem_req_address;
output [3:0] mem_mem_req_byte_en;
output mem_mem_req_read_writen;
output mem_mem_req_request;
output [7:0] mem_mem_req_tag;
output [31:0] mem_mem_req_wdata;
input [7:0] mem_mem_resp_dack_tag;
input [31:0] mem_mem_resp_data;
input [7:0] mem_mem_resp_rack_tag;
input [31:0] pio1_export;
input [19:0] pio2_export;
output [7:0] pio3_export;
input sys_clock_clk;
input sys_reset_reset_n;
input uart_rxd;
output uart_txd;
input uart_cts_n;
output uart_rts_n;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFXBP_TB_V
`define SKY130_FD_SC_HDLL__SDFXBP_TB_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfxbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 SCD = 1'b0;
#340 SCE = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SCE = 1'b1;
#540 SCD = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SCE = 1'bx;
#680 SCD = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hdll__sdfxbp dut (.D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFXBP_TB_V
|
module serializer
#( parameter INLOGBITS = 6,
parameter OUTLOGBITS = 3,
localparam INWIDTH = 1<<INLOGBITS,
localparam OUTWIDTH = 1<<OUTLOGBITS)
(
input clk,
input rst_n,
input in_valid,
output reg in_ready,
input [INWIDTH-1:0] in_data,
output out_valid,
input out_ready,
output [OUTWIDTH-1:0] out_data
);
localparam LOGBITDIFF = INLOGBITS-OUTLOGBITS ;
localparam MAXCNT = (1<<LOGBITDIFF)-1;
reg [LOGBITDIFF-1:0] cnt;
reg [LOGBITDIFF-1:0] cnt_next;
reg [INWIDTH-1:0] in_buf;
wire [INWIDTH-1:0] in_buf_shifted;
reg [INWIDTH-1:0] in_buf_next;
assign in_buf_shifted = in_buf >> OUTWIDTH ;
assign out_data = in_buf[OUTWIDTH-1:0] ;
reg in_buf_valid;
reg in_buf_valid_next;
assign out_valid = in_buf_valid;
always @(*) begin
in_buf_next = in_buf;
in_ready = 0;
in_buf_valid_next = in_buf_valid;
cnt_next = cnt;
if (cnt == MAXCNT && !in_buf_valid && in_valid) begin
in_buf_next = in_data;
in_buf_valid_next = 1;
in_ready = 1;
end
else if (cnt == 0 && out_ready && in_valid) begin // in_valid better be valid
cnt_next = cnt - 1'b1;
in_buf_valid_next = 1;
in_buf_next = in_data;
in_ready = 1;
end
else if (cnt == 0 && out_ready && !in_valid) begin // should never be here for vga
in_buf_valid_next = 0;
in_ready = 1;
end
else if (out_ready) begin
cnt_next = cnt - 1'b1;
in_buf_next = in_buf_shifted;
in_ready = 0;
end
end
`REG(clk, cnt, MAXCNT, cnt_next)
`REG(clk, in_buf_valid, 0, in_buf_valid_next)
`REG(clk, in_buf, 0, in_buf_next)
endmodule
/*
serializer #(.INLOGBITS(6), .OUTLOGBITS(3)) inst_XXX(
.clk(clk),
.rst_n(rst_n),
.in_valid(XXX_in_valid),
.in_ready(XXX_in_ready),
.in_data(XXX_in_data),
.out_valid(XXX_out_valid),
.out_ready(XXX_out_ready),
.out_data(XXX_out_data)
);
*/
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: txc_engine_classic.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The TXC Engine takes unformatted completions, formats
// these packets into "TLP's" or Transaction Layer Packets. These
// packets must meet max-request, max-payload, and payload termination
// requirements (see Read Completion Boundary). The TXC Engine does not
// check these requirements during operation, but may do so during
// simulation.
// This file also contains the txc_formatter module, which formats
// completion headers.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh" // Defines the user-facing signal widths.
`include "tlp.vh" // Defines the endpoint-facing field widths in a TLP
module txc_engine_classic
#(parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 0,
parameter C_MAX_PAYLOAD_DWORDS = 64,
parameter C_DEPTH_PACKETS = 10,
parameter C_VENDOR = "ALTERA")
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN, // Addition for RIFFA_RST
output DONE_TXC_RST,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: TXC Classic
input TXC_TLP_READY,
output [C_PCI_DATA_WIDTH-1:0] TXC_TLP,
output TXC_TLP_VALID,
output TXC_TLP_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_TLP_START_OFFSET,
output TXC_TLP_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_TLP_END_OFFSET,
// Interface: TXC Engine
input TXC_DATA_VALID,
input [C_PCI_DATA_WIDTH-1:0] TXC_DATA,
input TXC_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET,
input TXC_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET,
output TXC_DATA_READY,
input TXC_META_VALID,
input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
input [`SIG_TAG_W-1:0] TXC_META_TAG,
input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
input [`SIG_TC_W-1:0] TXC_META_TC,
input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
input TXC_META_EP,
output TXC_META_READY);
`include "functions.vh"
localparam C_DATA_WIDTH = C_PCI_DATA_WIDTH;
localparam C_MAX_HDR_WIDTH = `TLP_MAXHDR_W;
localparam C_MAX_ALIGN_WIDTH = (C_VENDOR == "ALTERA") ? 32:
(C_VENDOR == "XILINX") ? 0 :
0;
localparam C_PIPELINE_FORMATTER_INPUT = C_PIPELINE_INPUT;
localparam C_PIPELINE_FORMATTER_OUTPUT = C_PIPELINE_OUTPUT;
localparam C_FORMATTER_DELAY = C_PIPELINE_FORMATTER_OUTPUT + C_PIPELINE_FORMATTER_INPUT;
/*AUTOWIRE*/
/*AUTOINPUT*/
///*AUTOOUTPUT*/
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_TYPE_W-1:0] wTxType;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNopayload;
assign DONE_TXC_RST = ~RST_IN;
txc_formatter_classic
#(
.C_PIPELINE_OUTPUT (C_PIPELINE_FORMATTER_OUTPUT),
.C_PIPELINE_INPUT (C_PIPELINE_FORMATTER_INPUT),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_MAX_ALIGN_WIDTH (C_MAX_ALIGN_WIDTH),
.C_VENDOR (C_VENDOR))
txc_formatter_inst
(
// Outputs
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
// Inputs
.TX_HDR_READY (wTxHdrReady),
/*AUTOINST*/
// Outputs
.TXC_META_READY (TXC_META_READY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.TXC_META_VALID (TXC_META_VALID),
.TXC_META_FDWBE (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
.TXC_META_LENGTH (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (TXC_META_TAG[`SIG_TAG_W-1:0]),
.TXC_META_TYPE (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
.TXC_META_REQUESTER_ID (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.TXC_META_TC (TXC_META_TC[`SIG_TC_W-1:0]),
.TXC_META_ATTR (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
.TXC_META_EP (TXC_META_EP));
tx_engine
#(
.C_DATA_WIDTH (C_PCI_DATA_WIDTH),
/*AUTOINSTPARAM*/
// Parameters
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_FORMATTER_DELAY (C_FORMATTER_DELAY),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS),
.C_VENDOR (C_VENDOR))
txc_engine_inst
(
// Outputs
.TX_HDR_READY (wTxHdrReady),
.TX_DATA_READY (TXC_DATA_READY),
.TX_PKT (TXC_TLP[C_DATA_WIDTH-1:0]),
.TX_PKT_START_FLAG (TXC_TLP_START_FLAG),
.TX_PKT_START_OFFSET (TXC_TLP_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_END_FLAG (TXC_TLP_END_FLAG),
.TX_PKT_END_OFFSET (TXC_TLP_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_VALID (TXC_TLP_VALID),
// Inputs
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
.TX_DATA_VALID (TXC_DATA_VALID),
.TX_DATA (TXC_DATA[C_DATA_WIDTH-1:0]),
.TX_DATA_START_FLAG (TXC_DATA_START_FLAG),
.TX_DATA_START_OFFSET (TXC_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_DATA_END_FLAG (TXC_DATA_END_FLAG),
.TX_DATA_END_OFFSET (TXC_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_READY (TXC_TLP_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
module txc_formatter_classic
#(
parameter C_PCI_DATA_WIDTH = 10'd128,
parameter C_MAX_HDR_WIDTH = `TLP_MAXHDR_W,
parameter C_MAX_ALIGN_WIDTH = 32,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: TXC
input TXC_META_VALID,
input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
input [`SIG_TAG_W-1:0] TXC_META_TAG,
input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
input [`SIG_TC_W-1:0] TXC_META_TC,
input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
input TXC_META_EP,
output TXC_META_READY,
// Interface: TX HDR
output TX_HDR_VALID,
output [C_MAX_HDR_WIDTH-1:0] TX_HDR,
output [`SIG_LEN_W-1:0] TX_HDR_PAYLOAD_LEN,
output [`SIG_NONPAY_W-1:0] TX_HDR_NONPAY_LEN,
output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
output TX_HDR_NOPAYLOAD,
input TX_HDR_READY
);
`include "functions.vh"
wire [C_MAX_HDR_WIDTH-1:0] wCplHdr;
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_TYPE_W-1:0] wTxType;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNopayload;
wire [`TLP_CPLADDR_W-1:0] wTxLoAddr;
// Reserved Fields
assign wCplHdr[`TLP_RSVD0_R] = `TLP_RSVD0_V;
assign wCplHdr[`TLP_ADDRTYPE_R] = `TLP_ADDRTYPE_W'b0;
assign wCplHdr[`TLP_TH_R] = `TLP_TH_W'b0;
assign wCplHdr[`TLP_RSVD1_R] = `TLP_RSVD1_V;
assign wCplHdr[`TLP_RSVD2_R] = `TLP_RSVD2_V;
assign wCplHdr[`TLP_CPLBCM_R] = `TLP_CPLBCM_W'b0;
assign wCplHdr[`TLP_CPLRSVD0_R] = `TLP_CPLRSVD0_W'b0;
assign wCplHdr[127:96] = 32'b0;
// Generic Header Fields
assign wCplHdr[`TLP_LEN_R] = TXC_META_LENGTH;
assign wCplHdr[`TLP_EP_R] = TXC_META_EP;
assign wCplHdr[`TLP_TD_R] = `TLP_NODIGEST_V;
assign wCplHdr[`TLP_ATTR0_R] = TXC_META_ATTR[1:0];
assign wCplHdr[`TLP_ATTR1_R] = TXC_META_ATTR[2];
assign {wCplHdr[`TLP_FMT_R], wCplHdr[`TLP_TYPE_R]} = trellis_to_tlp_type(TXC_META_TYPE,0);
assign wCplHdr[`TLP_TC_R] = TXC_META_TC;
// Completion Specific Fields
assign wCplHdr[`TLP_CPLBYTECNT_R] = TXC_META_BYTE_COUNT;
assign wCplHdr[`TLP_CPLSTAT_R] = 0;
assign wCplHdr[`TLP_CPLCPLID_R] = CONFIG_COMPLETER_ID;
assign wCplHdr[`TLP_CPLADDR_R] = TXC_META_ADDR;
assign wCplHdr[`TLP_CPLTAG_R] = TXC_META_TAG;
assign wCplHdr[`TLP_CPLREQID_R] = TXC_META_REQUESTER_ID;
// Metadata, to the aligner
assign wTxLoAddr = wTxHdr[`TLP_CPLADDR_R];
assign wTxHdrNopayload = ~wTxHdr[`TLP_PAYBIT_I];
assign wTxHdrNonpayLen = 3 + ((C_VENDOR == "ALTERA")? {3'b0,(~wTxLoAddr[2] & ~wTxHdrNopayload)} : 4'b0);
assign wTxHdrPayloadLen = wTxHdrNopayload ? 0 : wTxHdr[`TLP_LEN_R];
assign wTxHdrPacketLen = wTxHdrPayloadLen + wTxHdrNonpayLen;
pipeline
#(// Parameters
.C_DEPTH (C_PIPELINE_INPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
input_inst
(// Outputs
.WR_DATA_READY (TXC_META_READY),
.RD_DATA (wTxHdr),
.RD_DATA_VALID (wTxHdrValid),
// Inputs
.WR_DATA (wCplHdr),
.WR_DATA_VALID (TXC_META_VALID),
.RD_DATA_READY (wTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
pipeline
#(
// Parameters
.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH+ 1 + `SIG_PACKETLEN_W + `SIG_LEN_W + `SIG_NONPAY_W),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_inst
(
// Outputs
.WR_DATA_READY (wTxHdrReady),
.RD_DATA ({TX_HDR,TX_HDR_NOPAYLOAD,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NONPAY_LEN}),
.RD_DATA_VALID (TX_HDR_VALID),
// Inputs
.WR_DATA ({wTxHdr,wTxHdrNopayload,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNonpayLen}),
.WR_DATA_VALID (wTxHdrValid),
.RD_DATA_READY (TX_HDR_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/" "../../common/")
// End:
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:19:51 10/29/2015
// Design Name: eightInput_PE
// Module Name: /home/sidharth/Documents/Xilinx Projects/PriorityEncoder/eightInput_tester.v
// Project Name: PriorityEncoder
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: eightInput_PE
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module eightInput_tester;
// Inputs
reg [7:0] in;
// Outputs
wire [3:0] out;
// Instantiate the Unit Under Test (UUT)
eightInput_PE uut (
.out(out),
.in(in)
);
initial begin
// Initialize Inputs
in = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
integer i;
// Check at all possible values of input
initial begin
for (i = 0; i < 256; i=i+1) begin
in = i;
#50;
end
end
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: drom32.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module drom32 (
address,
clock,
q);
input [11:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({32{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../rom_data.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../rom_data.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../rom_data.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL drom32.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL drom32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL drom32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL drom32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL drom32_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL drom32_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//////////////////////////////////////////////////////////////////////
/// ////
/// ORPSoC ML501 testbench ////
/// ////
/// Instantiate ORPSoC, monitors, provide stimulus ////
/// ////
/// Julius Baxter, [email protected] ////
/// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "orpsoc-defines.v"
`include "orpsoc-testbench-defines.v"
`include "test-defines.v"
`include "timescale.v"
// Xilinx simulation:
`include "glbl.v"
module orpsoc_testbench;
// Clock and reset signal registers
reg clk = 0;
reg rst_n = 1; // Active LOW
always
#((`BOARD_CLOCK_PERIOD)/2) clk <= ~clk;
wire clk_n, clk_p;
assign clk_p = clk;
assign clk_n = ~clk;
// Reset, ACTIVE LOW
initial
begin
#1;
repeat (32) @(negedge clk)
rst_n <= 1;
repeat (32) @(negedge clk)
rst_n <= 0;
repeat (32) @(negedge clk)
rst_n <= 1;
end
// Include design parameters file
`include "orpsoc-params.v"
// Pullup bus for I2C
tri1 i2c_scl, i2c_sda;
`ifdef JTAG_DEBUG
wire tdo_pad_o;
wire tck_pad_i;
wire tms_pad_i;
wire tdi_pad_i;
`endif
`ifdef UART0
wire uart0_stx_pad_o;
wire uart0_srx_pad_i;
`endif
`ifdef GPIO0
wire [gpio0_io_width-1:0] gpio0_io;
`endif
`ifdef SPI0
wire spi0_mosi_o;
wire spi0_miso_i;
wire spi0_sck_o;
wire spi0_hold_n_o;
wire spi0_w_n_o;
wire [spi0_ss_width-1:0] spi0_ss_o;
`endif
`ifdef ETH0
wire mtx_clk_o;
wire [3:0] ethphy_mii_tx_d;
wire ethphy_mii_tx_en;
wire ethphy_mii_tx_err;
wire mrx_clk_o;
wire [3:0] mrxd_o;
wire mrxdv_o;
wire mrxerr_o;
wire mcoll_o;
wire mcrs_o;
wire ethphy_rst_n;
wire eth0_mdc_pad_o;
wire eth0_md_pad_io;
`endif
`ifdef XILINX_DDR2
`include "xilinx_ddr2_params.v"
localparam DEVICE_WIDTH = 16; // Memory device data width
localparam real CLK_PERIOD_NS = CLK_PERIOD / 1000.0;
localparam real TCYC_200 = 5.0;
localparam real TPROP_DQS = 0.00; // Delay for DQS signal during Write Operation
localparam real TPROP_DQS_RD = 0.00; // Delay for DQS signal during Read Operation
localparam real TPROP_PCB_CTRL = 0.00; // Delay for Address and Ctrl signals
localparam real TPROP_PCB_DATA = 0.00; // Delay for data signal during Write operation
localparam real TPROP_PCB_DATA_RD = 0.00; // Delay for data signal during Read operation
wire [DQ_WIDTH-1:0] ddr2_dq_sdram;
wire [DQS_WIDTH-1:0] ddr2_dqs_sdram;
wire [DQS_WIDTH-1:0] ddr2_dqs_n_sdram;
wire [DM_WIDTH-1:0] ddr2_dm_sdram;
reg [DM_WIDTH-1:0] ddr2_dm_sdram_tmp;
reg [CLK_WIDTH-1:0] ddr2_ck_sdram;
reg [CLK_WIDTH-1:0] ddr2_ck_n_sdram;
reg [ROW_WIDTH-1:0] ddr2_a_sdram;
reg [BANK_WIDTH-1:0] ddr2_ba_sdram;
reg ddr2_ras_n_sdram;
reg ddr2_cas_n_sdram;
reg ddr2_we_n_sdram;
reg [CS_WIDTH-1:0] ddr2_cs_n_sdram;
reg [CKE_WIDTH-1:0] ddr2_cke_sdram;
reg [ODT_WIDTH-1:0] ddr2_odt_sdram;
wire [DQ_WIDTH-1:0] ddr2_dq_fpga;
wire [DQS_WIDTH-1:0] ddr2_dqs_fpga;
wire [DQS_WIDTH-1:0] ddr2_dqs_n_fpga;
wire [DM_WIDTH-1:0] ddr2_dm_fpga;
wire [CLK_WIDTH-1:0] ddr2_ck_fpga;
wire [CLK_WIDTH-1:0] ddr2_ck_n_fpga;
wire [ROW_WIDTH-1:0] ddr2_a_fpga;
wire [BANK_WIDTH-1:0] ddr2_ba_fpga;
wire ddr2_ras_n_fpga;
wire ddr2_cas_n_fpga;
wire ddr2_we_n_fpga;
wire [CS_WIDTH-1:0] ddr2_cs_n_fpga;
wire [CKE_WIDTH-1:0] ddr2_cke_fpga;
wire [ODT_WIDTH-1:0] ddr2_odt_fpga;
`endif
`ifdef XILINX_SSRAM
wire sram_clk;
wire sram_clk_fb;
wire sram_adv_ld_n;
wire [3:0] sram_bw;
wire sram_cen;
wire [21:1] sram_flash_addr;
wire [31:0] sram_flash_data;
wire sram_flash_oe_n;
wire sram_flash_we_n;
wire sram_mode;
`endif
orpsoc_top dut
(
`ifdef JTAG_DEBUG
.tms_pad_i (tms_pad_i),
.tck_pad_i (tck_pad_i),
.tdi_pad_i (tdi_pad_i),
.tdo_pad_o (tdo_pad_o),
.jtag_vdd (),
.jtag_gnd(),
`endif
`ifdef XILINX_DDR2
.ddr2_a (ddr2_a_fpga),
.ddr2_ba (ddr2_ba_fpga),
.ddr2_ras_n (ddr2_ras_n_fpga),
.ddr2_cas_n (ddr2_cas_n_fpga),
.ddr2_we_n (ddr2_we_n_fpga),
.ddr2_cs_n (ddr2_cs_n_fpga),
.ddr2_odt (ddr2_odt_fpga),
.ddr2_cke (ddr2_cke_fpga),
.ddr2_dm (ddr2_dm_fpga),
.ddr2_ck (ddr2_ck_fpga),
.ddr2_ck_n (ddr2_ck_n_fpga),
.ddr2_dq (ddr2_dq_fpga),
.ddr2_dqs (ddr2_dqs_fpga),
.ddr2_dqs_n (ddr2_dqs_n_fpga),
`endif
`ifdef XILINX_SSRAM
.sram_clk (sram_clk),
.sram_flash_addr (sram_flash_addr),
.sram_cen (sram_cen),
.sram_flash_oe_n (sram_flash_oe_n),
.sram_flash_we_n (sram_flash_we_n),
.sram_bw (sram_bw),
.sram_adv_ld_n (sram_adv_ld_n),
.sram_mode (sram_mode),
.sram_clk_fb (sram_clk_fb),
.sram_flash_data (sram_flash_data),
`endif
`ifdef UART0
.uart0_stx_pad_o (uart0_stx_pad_o),
.uart0_srx_pad_i (uart0_srx_pad_i),
.uart0_stx_expheader_pad_o (uart0_stx_pad_o),
.uart0_srx_expheader_pad_i (uart0_srx_pad_i),
`endif
`ifdef SPI0
/*
via STARTUP_VIRTEX5
.spi0_sck_o (spi0_sck_o),
.spi0_miso_i (spi0_miso_i),
*/
.spi0_mosi_o (spi0_mosi_o),
.spi0_ss_o (spi0_ss_o),
`endif
`ifdef I2C0
.i2c0_sda_io (i2c_sda),
.i2c0_scl_io (i2c_scl),
`endif
`ifdef I2C1
.i2c1_sda_io (i2c_sda),
.i2c1_scl_io (i2c_scl),
`endif
`ifdef GPIO0
.gpio0_io (gpio0_io),
`endif
`ifdef ETH0
.eth0_tx_clk (mtx_clk_o),
.eth0_tx_data (ethphy_mii_tx_d),
.eth0_tx_en (ethphy_mii_tx_en),
.eth0_tx_er (ethphy_mii_tx_err),
.eth0_rx_clk (mrx_clk_o),
.eth0_rx_data (mrxd_o),
.eth0_dv (mrxdv_o),
.eth0_rx_er (mrxerr_o),
.eth0_col (mcoll_o),
.eth0_crs (mcrs_o),
.eth0_rst_n_o (ethphy_rst_n),
.eth0_mdc_pad_o (eth0_mdc_pad_o),
.eth0_md_pad_io (eth0_md_pad_io),
`endif // `ifdef ETH0
.sys_clk_in_p (clk_p),
.sys_clk_in_n (clk_n),
.rst_n_pad_i (rst_n)
);
//
// Instantiate OR1200 monitor
//
or1200_monitor monitor();
`include "or1200_defines.v"
`include "or1200_monitor_defines.v"
`include "test-defines.v"
integer r3;
//
// Get GPR
//
task get_gpr;
input [4:0] gpr_no;
output [31:0] gpr;
integer j;
begin
`ifdef OR1200_RFRAM_GENERIC
for(j = 0; j < 32; j = j + 1) begin
gpr[j] = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.mem[gpr_no*32+j];
end
`else
//gpr = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.mem[gpr_no];
gpr = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.get_gpr(gpr_no);
`endif
end
endtask
//
// Hooks for:
// - displaying registers
// - end of simulation
// - access to SPRs
//
always @(posedge `CPU_CORE_CLK)
if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze) begin
if (((`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP)
| !`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[16])
& !(`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe &
`OR1200_TOP.`CPU_cpu.`CPU_except.ex_dslot))
;
else
// small hack to stop simulation (l.nop 1):
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0001) begin
get_gpr(3, r3);
$display("%t: l.nop exit (%h)", $time, r3);
$finish;
end
// debug if test (l.nop 10)
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_000a) begin
$display("%t: l.nop dbg_if_test", $time);
end
// simulation reports (l.nop 2)
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0002) begin
get_gpr(3, r3);
$display("%t: l.nop report (0x%h)", $time, r3);
end
// simulation printfs (l.nop 3)
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0003) begin
get_gpr(3, r3);
$display("%t: l.nop printf (%h)", $time, r3);
end
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0004) begin
// simulation putc (l.nop 4)
get_gpr(3, r3);
$write("%c", r3);
$display("%t: l.nop putc (%c)", $time, r3);
end
end
`define CPU_ic_top or1200_ic_top
`define CPU_dc_top or1200_dc_top
wire ic_en = orpsoc_testbench.dut.or1200_top0.or1200_ic_top.ic_en;
always @(posedge ic_en)
$display("Or1200 IC enabled at %t", $time);
wire dc_en = orpsoc_testbench.dut.or1200_top0.or1200_dc_top.dc_en;
always @(posedge dc_en)
$display("Or1200 DC enabled at %t", $time);
`ifdef JTAG_DEBUG
`ifdef VPI_DEBUG
// Debugging interface
vpi_debug_module vpi_dbg
(
.tms(tms_pad_i),
.tck(tck_pad_i),
.tdi(tdi_pad_i),
.tdo(tdo_pad_o)
);
`else
// If no VPI debugging, tie off JTAG inputs
assign tdi_pad_i = 1;
assign tck_pad_i = 0;
assign tms_pad_i = 1;
`endif // !`ifdef VPI_DEBUG_ENABLE
`endif // `ifdef JTAG_DEBUG
`ifdef SPI0
// STARTUP_VIRTEX5 module routes these out on the board.
// So for now just connect directly to the internals here.
assign spi0_sck_o = dut.spi0_sck_o;
assign dut.spi0_miso_i = spi0_miso_i;
// SPI flash memory - M25P16 compatible SPI protocol
AT26DFxxx
#(.MEMSIZE(2048*1024)) // 2MB flash on ML501
spi0_flash
(// Outputs
.SO (spi0_miso_i),
// Inputs
.CSB (spi0_ss_o),
.SCK (spi0_sck_o),
.SI (spi0_mosi_o),
.WPB (1'b1)
);
`endif // `ifdef SPI0
`ifdef ETH0
/* TX/RXes packets and checks them, enabled when ethernet MAC is */
`include "eth_stim.v"
eth_phy eth_phy0
(
// Outputs
.mtx_clk_o (mtx_clk_o),
.mrx_clk_o (mrx_clk_o),
.mrxd_o (mrxd_o[3:0]),
.mrxdv_o (mrxdv_o),
.mrxerr_o (mrxerr_o),
.mcoll_o (mcoll_o),
.mcrs_o (mcrs_o),
.link_o (),
.speed_o (),
.duplex_o (),
.smii_clk_i (1'b0),
.smii_sync_i (1'b0),
.smii_rx_o (),
// Inouts
.md_io (eth0_md_pad_io),
// Inputs
`ifndef ETH0_PHY_RST
// If no reset out from the design, hook up to the board's active low rst
.m_rst_n_i (rst_n),
`else
.m_rst_n_i (ethphy_rst_n),
`endif
.mtxd_i (ethphy_mii_tx_d[3:0]),
.mtxen_i (ethphy_mii_tx_en),
.mtxerr_i (ethphy_mii_tx_err),
.mdc_i (eth0_mdc_pad_o));
`endif // `ifdef ETH0
`ifdef XILINX_SSRAM
wire [18:0] sram_a;
wire [3:0] dqp;
assign sram_a[18:0] = sram_flash_addr[19:1];
wire sram_ce1b, sram_ce2, sram_ce3b;
assign sram_ce1b = 1'b0;
assign sram_ce2 = 1'b1;
assign sram_ce3b = 1'b0;
assign sram_clk_fb = sram_clk;
cy7c1354 ssram0
(
// Inouts
// This model puts each parity bit after each byte, but the ML501's part
// doesn't, so we wire up the data bus like so.
.d ({dqp[3],sram_flash_data[31:24],
dqp[2],sram_flash_data[23:16],
dqp[1],sram_flash_data[15:8],
dqp[0],sram_flash_data[7:0]}),
// Inputs
.clk (sram_clk),
.we_b (sram_flash_we_n),
.adv_lb (sram_adv_ld_n),
.ce1b (sram_ce1b),
.ce2 (sram_ce2),
.ce3b (sram_ce3b),
.oeb (sram_flash_oe_n),
.cenb (sram_cen),
.mode (sram_mode),
.bws (sram_bw),
.a (sram_a));
`endif
`ifdef XILINX_DDR2
`ifndef GATE_SIM
defparam dut.xilinx_ddr2_0.xilinx_ddr2_if0.ddr2_mig0.SIM_ONLY = 1;
`endif
always @( * ) begin
ddr2_ck_sdram <= #(TPROP_PCB_CTRL) ddr2_ck_fpga;
ddr2_ck_n_sdram <= #(TPROP_PCB_CTRL) ddr2_ck_n_fpga;
ddr2_a_sdram <= #(TPROP_PCB_CTRL) ddr2_a_fpga;
ddr2_ba_sdram <= #(TPROP_PCB_CTRL) ddr2_ba_fpga;
ddr2_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr2_ras_n_fpga;
ddr2_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr2_cas_n_fpga;
ddr2_we_n_sdram <= #(TPROP_PCB_CTRL) ddr2_we_n_fpga;
ddr2_cs_n_sdram <= #(TPROP_PCB_CTRL) ddr2_cs_n_fpga;
ddr2_cke_sdram <= #(TPROP_PCB_CTRL) ddr2_cke_fpga;
ddr2_odt_sdram <= #(TPROP_PCB_CTRL) ddr2_odt_fpga;
ddr2_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr2_dm_fpga;//DM signal generation
end // always @ ( * )
// Model delays on bi-directional BUS
genvar dqwd;
generate
for (dqwd = 0;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay
wiredelay #
(
.Delay_g (TPROP_PCB_DATA),
.Delay_rd (TPROP_PCB_DATA_RD)
)
u_delay_dq
(
.A (ddr2_dq_fpga[dqwd]),
.B (ddr2_dq_sdram[dqwd]),
.reset (rst_n)
);
end
endgenerate
genvar dqswd;
generate
for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay
wiredelay #
(
.Delay_g (TPROP_DQS),
.Delay_rd (TPROP_DQS_RD)
)
u_delay_dqs
(
.A (ddr2_dqs_fpga[dqswd]),
.B (ddr2_dqs_sdram[dqswd]),
.reset (rst_n)
);
wiredelay #
(
.Delay_g (TPROP_DQS),
.Delay_rd (TPROP_DQS_RD)
)
u_delay_dqs_n
(
.A (ddr2_dqs_n_fpga[dqswd]),
.B (ddr2_dqs_n_sdram[dqswd]),
.reset (rst_n)
);
end
endgenerate
assign ddr2_dm_sdram = ddr2_dm_sdram_tmp;
parameter NUM_PROGRAM_WORDS=67108864;
integer program_word_ptr, k;
integer burst_address;
reg [31:0] program_array [0:NUM_PROGRAM_WORDS-1]; // 1M words = 4MB
reg [8*16-1:0] ddr2_ram_mem_line; //8*16-bits= 8 shorts (half-words)
genvar i, j;
generate
// if the data width is multiple of 16
for(j = 0; j < CS_NUM; j = j+1) begin : gen_cs // Loop of 1
for(i = 0; i < DQS_WIDTH/2; i = i+1) begin : gen // Loop of 4 (DQS_WIDTH=8)
initial
begin
// `ifdef PRELOAD_RAM
`include "ddr2_model_preload.v"
//`endif
end
ddr2_model u_mem0
(
.ck (ddr2_ck_sdram[CLK_WIDTH*i/DQS_WIDTH]),
.ck_n (ddr2_ck_n_sdram[CLK_WIDTH*i/DQS_WIDTH]),
.cke (ddr2_cke_sdram[j]),
.cs_n (ddr2_cs_n_sdram[CS_WIDTH*i/DQS_WIDTH]),
.ras_n (ddr2_ras_n_sdram),
.cas_n (ddr2_cas_n_sdram),
.we_n (ddr2_we_n_sdram),
.dm_rdqs (ddr2_dm_sdram[(2*(i+1))-1 : i*2]),
.ba (ddr2_ba_sdram),
.addr (ddr2_a_sdram),
.dq (ddr2_dq_sdram[(16*(i+1))-1 : i*16]),
.dqs (ddr2_dqs_sdram[(2*(i+1))-1 : i*2]),
.dqs_n (ddr2_dqs_n_sdram[(2*(i+1))-1 : i*2]),
.rdqs_n (),
.odt (ddr2_odt_sdram[ODT_WIDTH*i/DQS_WIDTH])
);
end
end
endgenerate
`endif
`ifdef VCD
reg vcd_go = 0;
always @(vcd_go)
begin : fjfk
// integer r, t;
// `ifdef VCD_DELAY
// #(`VCD_DELAY);
/*for(r = 0; r < 1000; r = r + 1)begin
for(t = 0; t < 10; t = t + 1) begin
#(331900000);
end
end*/
// `endif
// Delay by x insns
`ifdef VCD_DELAY_INSNS
#10; // Delay until after the value becomes valid
while (monitor.insns < `VCD_DELAY_INSNS)
@(posedge clk);
`endif
`ifdef SIMULATOR_MODELSIM
// Modelsim can GZip VCDs on the fly if given in the suffix
`define VCD_SUFFIX ".vcd.gz"
`else
`define VCD_SUFFIX ".vcd"
`endif
`define TEST_NAME_STRING "hwinv"
$display("* VCD in %s\n", {"",`TEST_NAME_STRING,`VCD_SUFFIX});
$dumpfile({"",`TEST_NAME_STRING,`VCD_SUFFIX});
`ifndef VCD_DEPTH
`define VCD_DEPTH 0
`endif
$dumpvars(/*`VCD_DEPTH*/3, orpsoc_testbench.dut.or1200_top0.or1200_cpu);
/*for(r = 0; r < 1000; r = r + 1)begin
for(t = 0; t < 10; t = t + 1) begin
#(2000000);
end
end
$finish;
*/
end
`endif // `ifdef VCD
initial
begin
$display("\n* Starting simulation of design RTL.\n* Test: %s\n",
`TEST_NAME_STRING );
`ifdef VCD
vcd_go = 1;
`endif
end // initial begin
`ifdef END_TIME
initial begin
#(`END_TIME);
$display("* Finish simulation due to END_TIME being set at %t", $time);
$finish;
end
`endif
`ifdef END_INSNS
initial begin
#10
while (monitor.insns < `END_INSNS)
@(posedge clk);
$display("* Finish simulation due to END_INSNS count (%d) reached at %t",
`END_INSNS, $time);
$finish;
end
`endif
`ifdef UART0
//
// UART0 decoder
//
uart_decoder
#(
.uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS
)
uart0_decoder
(
.clk(clk),
.uart_tx(uart0_stx_pad_o)
);
// Loopback UART lines
assign uart0_srx_pad_i = uart0_stx_pad_o;
`endif // `ifdef UART0
endmodule // orpsoc_testbench
// Local Variables:
// verilog-library-directories:("." "../../rtl/verilog/orpsoc_top")
// verilog-library-files:()
// verilog-library-extensions:(".v" ".h")
// End:
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 08:23:53 2016
/////////////////////////////////////////////////////////////
module CORDIC_Arch3_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
overflow_flag, underflow_flag, zero_flag, busy, data_output );
input [31:0] data_in;
input [1:0] shift_region_flag;
output [31:0] data_output;
input clk, rst, beg_fsm_cordic, ack_cordic, operation;
output ready_cordic, overflow_flag, underflow_flag, zero_flag, busy;
wire d_ff1_operation_out, d_ff3_sign_out,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SFG,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SFG,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_NRM,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_NRM,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1SHT2,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1SHT2,
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT2,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT2,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT2,
inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2,
inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2,
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT1,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_EXP,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_EXP,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_EXP,
inst_FPU_PIPELINED_FPADDSUB_intAS,
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_5,
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_6,
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_, n866,
n867, n868, n869, n870, n871, n872, n873, n874, n875, n876, n877,
n878, n879, n880, n881, n882, n883, n884, n885, n886, n887, n888,
n889, n890, n891, n892, n893, n894, n895, n896, n897, n898, n899,
n900, n901, n902, n903, n904, n905, n906, n907, n908, n909, n910,
n911, n912, n913, n914, n915, n916, n917, n918, n919, n920, n922,
n923, n924, n926, n927, n928, n929, n930, n931, n932, n933, n934,
n935, n936, n937, n938, n939, n940, n941, n942, n943, n944, n945,
n946, n947, n948, n949, n950, n951, n952, n953, n954, n955, n956,
n957, n958, n959, n960, n961, n962, n963, n964, n965, n967, n968,
n969, n970, n971, n972, n973, n974, n975, n976, n977, n978, n979,
n981, n982, n983, n984, n985, n986, n988, n989, n990, n991, n992,
n993, n995, n996, n997, n998, n999, n1000, n1002, n1003, n1004, n1005,
n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015,
n1016, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026,
n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036,
n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046,
n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056,
n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066,
n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076,
n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086,
n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096,
n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106,
n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116,
n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126,
n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136,
n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146,
n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156,
n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166,
n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1175, n1176, n1177,
n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187,
n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197,
n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207,
n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217,
n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227,
n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237,
n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247,
n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257,
n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267,
n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277,
n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287,
n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297,
n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307,
n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317,
n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327,
n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337,
n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347,
n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357,
n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367,
n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377,
n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387,
n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397,
n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407,
n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417,
n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427,
n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437,
n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447,
n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457,
n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467,
n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477,
n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487,
n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497,
n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507,
n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517,
n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527,
n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537,
n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547,
n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557,
n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567,
n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577,
n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587,
n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597,
n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607,
n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617,
n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627,
n1628, n1629, DP_OP_33J115_122_2179_n18, DP_OP_33J115_122_2179_n17,
DP_OP_33J115_122_2179_n16, DP_OP_33J115_122_2179_n15,
DP_OP_33J115_122_2179_n14, DP_OP_33J115_122_2179_n8,
DP_OP_33J115_122_2179_n7, DP_OP_33J115_122_2179_n6,
DP_OP_33J115_122_2179_n5, DP_OP_33J115_122_2179_n4,
DP_OP_33J115_122_2179_n3, DP_OP_33J115_122_2179_n2,
DP_OP_33J115_122_2179_n1, intadd_356_B_1_, intadd_356_CI,
intadd_356_SUM_2_, intadd_356_SUM_1_, intadd_356_SUM_0_,
intadd_356_n3, intadd_356_n2, intadd_356_n1, intadd_357_CI,
intadd_357_SUM_2_, intadd_357_SUM_1_, intadd_357_SUM_0_,
intadd_357_n3, intadd_357_n2, intadd_357_n1, n1633, n1634, n1635,
n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645,
n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655,
n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665,
n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675,
n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685,
n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695,
n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705,
n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715,
n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725,
n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735,
n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745,
n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755,
n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765,
n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775,
n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785,
n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795,
n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805,
n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815,
n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825,
n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835,
n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845,
n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855,
n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865,
n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875,
n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885,
n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895,
n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905,
n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915,
n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925,
n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935,
n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945,
n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955,
n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965,
n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975,
n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985,
n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995,
n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005,
n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015,
n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025,
n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035,
n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045,
n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055,
n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065,
n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075,
n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085,
n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095,
n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105,
n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115,
n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125,
n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135,
n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145,
n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155,
n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165,
n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175,
n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185,
n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195,
n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205,
n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215,
n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225,
n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235,
n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245,
n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255,
n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265,
n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275,
n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285,
n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295,
n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305,
n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315,
n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325,
n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335,
n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345,
n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355,
n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365,
n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375,
n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385,
n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395,
n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405,
n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415,
n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425,
n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435,
n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445,
n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455,
n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465,
n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475,
n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485,
n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495,
n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505,
n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515,
n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525,
n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535,
n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545,
n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555,
n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565,
n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575,
n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585,
n2586, n2587, n2588, n2590, n2591, n2592, n2593, n2594, n2595, n2596,
n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605, n2606,
n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615, n2616,
n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625, n2626,
n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635, n2636,
n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645, n2646,
n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655, n2656,
n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665, n2666,
n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675, n2676,
n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685, n2686,
n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695, n2696,
n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705, n2706,
n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715, n2716,
n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725, n2726,
n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735, n2736,
n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745, n2746,
n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755, n2756,
n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765, n2766,
n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775, n2776,
n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784, n2785, n2786,
n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794, n2795, n2796,
n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804, n2805, n2806,
n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814, n2815, n2816,
n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825, n2826,
n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835, n2836,
n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844, n2845, n2846,
n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855, n2856,
n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864, n2865, n2866,
n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874, n2875, n2876,
n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884, n2885, n2886,
n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894, n2895, n2896,
n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904, n2905, n2906,
n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914, n2915, n2916,
n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924, n2925, n2926,
n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934, n2935, n2936,
n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944, n2945, n2946,
n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954, n2955, n2956,
n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964, n2965, n2966,
n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974, n2975, n2976,
n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984, n2985, n2986,
n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994, n2995, n2996,
n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005, n3006,
n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015, n3016,
n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024, n3025, n3026,
n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034, n3035, n3036,
n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044, n3045, n3046,
n3047, n3048, n3049, n3050, n3051, n3053, n3054, n3055, n3057, n3058,
n3059, n3060, n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068,
n3069, n3070, n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078,
n3079, n3080, n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088,
n3089, n3090, n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098,
n3099, n3100, n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108,
n3109, n3110, n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118,
n3119, n3120, n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128,
n3129, n3130, n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138,
n3139, n3140, n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148,
n3149, n3150, n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158,
n3159, n3160, n3161, n3162, n3163, n3164, n3165, n3166, n3167, n3168,
n3169, n3170, n3171, n3172, n3173, n3174, n3175, n3176, n3177, n3178,
n3179, n3180, n3181, n3182, n3183, n3184, n3185, n3186, n3187, n3188,
n3189, n3190, n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198,
n3199, n3200, n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208,
n3209, n3210, n3211, n3212, n3213, n3214, n3215, n3216, n3217, n3218,
n3219, n3220, n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228,
n3229, n3230, n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238,
n3239, n3240, n3241, n3242, n3243, n3244, n3245, n3246, n3247, n3248,
n3249, n3250, n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258,
n3259, n3260, n3261, n3262, n3263, n3264, n3265, n3266, n3267;
wire [3:1] cont_iter_out;
wire [1:0] cont_var_out;
wire [1:0] d_ff1_shift_region_flag_out;
wire [31:0] d_ff1_Z;
wire [31:0] d_ff_Xn;
wire [31:0] d_ff_Yn;
wire [31:0] d_ff_Zn;
wire [31:0] d_ff2_X;
wire [31:0] d_ff2_Y;
wire [31:0] d_ff2_Z;
wire [31:0] d_ff3_sh_x_out;
wire [31:0] d_ff3_sh_y_out;
wire [27:0] d_ff3_LUT_out;
wire [31:0] result_add_subt;
wire [7:0] inst_CORDIC_FSM_v3_state_next;
wire [7:0] inst_CORDIC_FSM_v3_state_reg;
wire [25:0] inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] inst_FPU_PIPELINED_FPADDSUB_DMP_SFG;
wire [7:0] inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW;
wire [7:0] inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW;
wire [25:0] inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR;
wire [25:0] inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR;
wire [4:0] inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW;
wire [27:0] inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW;
wire [30:0] inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW;
wire [31:0] inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW;
wire [31:0] inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW;
wire [3:0] inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7;
wire [2:0] inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS ITER_CONT_temp_reg_2_ ( .D(n1618), .CK(clk), .RN(n3264), .Q(
cont_iter_out[2]), .QN(n1712) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n3264), .Q(
inst_CORDIC_FSM_v3_state_reg[7]), .QN(n3075) );
DFFRX2TS inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n2091), .CK(clk), .RN(
n3265), .Q(inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(n1590), .CK(clk), .RN(n3263), .Q(d_ff1_Z[30])
);
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(n1589), .CK(clk), .RN(n3263), .Q(d_ff1_Z[29])
);
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(n1588), .CK(clk), .RN(n3263), .Q(d_ff1_Z[28])
);
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(n1587), .CK(clk), .RN(n3263), .Q(d_ff1_Z[27])
);
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(n1586), .CK(clk), .RN(n3263), .Q(d_ff1_Z[26])
);
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(n1585), .CK(clk), .RN(n3263), .Q(d_ff1_Z[25])
);
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(n1584), .CK(clk), .RN(n3262), .Q(d_ff1_Z[24])
);
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(n1583), .CK(clk), .RN(n3262), .Q(d_ff1_Z[23])
);
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(n1582), .CK(clk), .RN(n3262), .Q(d_ff1_Z[22])
);
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(n1581), .CK(clk), .RN(n3262), .Q(d_ff1_Z[21])
);
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(n1580), .CK(clk), .RN(n3262), .Q(d_ff1_Z[20])
);
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(n1579), .CK(clk), .RN(n3262), .Q(d_ff1_Z[19])
);
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(n1578), .CK(clk), .RN(n3262), .Q(d_ff1_Z[18])
);
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(n1577), .CK(clk), .RN(n3262), .Q(d_ff1_Z[17])
);
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(n1576), .CK(clk), .RN(n3262), .Q(d_ff1_Z[16])
);
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(n1575), .CK(clk), .RN(n3262), .Q(d_ff1_Z[15])
);
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(n1574), .CK(clk), .RN(n3265), .Q(d_ff1_Z[14])
);
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(n1573), .CK(clk), .RN(n3264), .Q(d_ff1_Z[13])
);
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(n1572), .CK(clk), .RN(n3265), .Q(d_ff1_Z[12])
);
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(n1571), .CK(clk), .RN(n3264), .Q(d_ff1_Z[11])
);
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(n1570), .CK(clk), .RN(n1172), .Q(d_ff1_Z[10])
);
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(n1569), .CK(clk), .RN(n1172), .Q(d_ff1_Z[9])
);
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(n1568), .CK(clk), .RN(n1172), .Q(d_ff1_Z[8])
);
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(n1567), .CK(clk), .RN(n1172), .Q(d_ff1_Z[7])
);
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(n1566), .CK(clk), .RN(n1172), .Q(d_ff1_Z[6])
);
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(n1565), .CK(clk), .RN(n1172), .Q(d_ff1_Z[5])
);
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(n1564), .CK(clk), .RN(n3261), .Q(d_ff1_Z[4])
);
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(n1563), .CK(clk), .RN(n3261), .Q(d_ff1_Z[3])
);
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(n1562), .CK(clk), .RN(n3261), .Q(d_ff1_Z[2])
);
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(n1561), .CK(clk), .RN(n3261), .Q(d_ff1_Z[1])
);
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(n1560), .CK(clk), .RN(n3261), .Q(d_ff1_Z[0])
);
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(n1559), .CK(clk), .RN(n3261), .Q(d_ff1_Z[31])
);
DFFRX2TS inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n3261), .Q(
inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n1627),
.CK(clk), .RN(n3186), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_6), .QN(n1714) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(n1626),
.CK(clk), .RN(n3186), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_5), .QN(n3170) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(n1624),
.CK(clk), .RN(n3227), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(n1622),
.CK(clk), .RN(n3227), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n1701) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(n1608), .CK(clk), .RN(n3260), .Q(
d_ff3_LUT_out[19]) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(n1606), .CK(clk), .RN(n3260), .Q(
d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n1602), .CK(clk), .RN(n3260), .Q(
d_ff3_LUT_out[8]) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(n1613), .CK(clk), .RN(n3260), .Q(
d_ff3_LUT_out[26]) );
DFFRXLTS reg_LUT_Q_reg_3_ ( .D(n1597), .CK(clk), .RN(n3260), .Q(
d_ff3_LUT_out[3]), .QN(n3176) );
DFFRXLTS reg_LUT_Q_reg_15_ ( .D(n1607), .CK(clk), .RN(n3259), .Q(
d_ff3_LUT_out[15]), .QN(n3175) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(n1603), .CK(clk), .RN(n3259), .Q(
d_ff3_LUT_out[9]), .QN(n3174) );
DFFRXLTS reg_LUT_Q_reg_5_ ( .D(n1599), .CK(clk), .RN(n3259), .Q(
d_ff3_LUT_out[5]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(n1429), .CK(clk), .RN(n3258), .Q(
d_ff3_sh_x_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(n1428), .CK(clk), .RN(n3258), .Q(
d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(n1427), .CK(clk), .RN(n3258), .Q(
d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(n1426), .CK(clk), .RN(n3258), .Q(
d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(n1425), .CK(clk), .RN(n3258), .Q(
d_ff3_sh_x_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(n1424), .CK(clk), .RN(n3258), .Q(
d_ff3_sh_x_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(n1423), .CK(clk), .RN(n3258), .Q(
d_ff3_sh_x_out[30]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(n1338), .CK(clk), .RN(n3257), .Q(
d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(n1336), .CK(clk), .RN(n3257), .Q(
d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(n1334), .CK(clk), .RN(n3257), .Q(
d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(n1332), .CK(clk), .RN(n3257), .Q(
d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(n1330), .CK(clk), .RN(n3257), .Q(
d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(n1328), .CK(clk), .RN(n3257), .Q(
d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(n1326), .CK(clk), .RN(n3257), .Q(
d_ff3_sh_y_out[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(n1297), .CK(clk), .RN(n3257), .Q(
d_ff_Zn[23]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_23_ ( .D(n1229), .CK(clk), .RN(n3257),
.Q(d_ff2_Z[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(n1294), .CK(clk), .RN(n3256), .Q(
d_ff_Zn[24]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_24_ ( .D(n1227), .CK(clk), .RN(n3256),
.Q(d_ff2_Z[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(n1291), .CK(clk), .RN(n3255), .Q(
d_ff_Zn[25]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_25_ ( .D(n1225), .CK(clk), .RN(n3255),
.Q(d_ff2_Z[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(n1288), .CK(clk), .RN(n3255), .Q(
d_ff_Zn[26]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_26_ ( .D(n1223), .CK(clk), .RN(n3255),
.Q(d_ff2_Z[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(n1285), .CK(clk), .RN(n3254), .Q(
d_ff_Zn[27]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_27_ ( .D(n1221), .CK(clk), .RN(n3254),
.Q(d_ff2_Z[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(n1282), .CK(clk), .RN(n3253), .Q(
d_ff_Zn[28]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_28_ ( .D(n1219), .CK(clk), .RN(n3253),
.Q(d_ff2_Z[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(n1279), .CK(clk), .RN(n3253), .Q(
d_ff_Zn[29]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_29_ ( .D(n1217), .CK(clk), .RN(n3252),
.Q(d_ff2_Z[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(n1276), .CK(clk), .RN(n3252), .Q(
d_ff_Zn[30]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_30_ ( .D(n1215), .CK(clk), .RN(n3252),
.Q(d_ff2_Z[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(
n1327), .CK(clk), .RN(n3188), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .QN(n3083) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(n1487), .CK(clk), .RN(n3251), .Q(
d_ff_Zn[22]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_22_ ( .D(n1231), .CK(clk), .RN(n3251),
.Q(d_ff2_Z[22]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(n1350), .CK(clk), .RN(n3251), .Q(
d_ff3_sh_y_out[22]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(n1439), .CK(clk), .RN(n3250), .Q(
d_ff3_sh_x_out[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(n1508), .CK(clk), .RN(n3250), .Q(
d_ff_Zn[15]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_15_ ( .D(n1245), .CK(clk), .RN(n3250),
.Q(d_ff2_Z[15]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(n1371), .CK(clk), .RN(n3250), .Q(
d_ff3_sh_y_out[15]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(n1453), .CK(clk), .RN(n3250), .Q(
d_ff3_sh_x_out[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(n1499), .CK(clk), .RN(n3250), .Q(
d_ff_Zn[18]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_18_ ( .D(n1239), .CK(clk), .RN(n3249),
.Q(d_ff2_Z[18]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(n1362), .CK(clk), .RN(n3249), .Q(
d_ff3_sh_y_out[18]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(n1447), .CK(clk), .RN(n3249), .Q(
d_ff3_sh_x_out[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(n1490), .CK(clk), .RN(n3249), .Q(
d_ff_Zn[21]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_21_ ( .D(n1233), .CK(clk), .RN(n3249),
.Q(d_ff2_Z[21]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(n1353), .CK(clk), .RN(n3248), .Q(
d_ff3_sh_y_out[21]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(n1441), .CK(clk), .RN(n3248), .Q(
d_ff3_sh_x_out[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(n1496), .CK(clk), .RN(n3248), .Q(
d_ff_Zn[19]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_19_ ( .D(n1237), .CK(clk), .RN(n3248),
.Q(d_ff2_Z[19]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(n1359), .CK(clk), .RN(n3248), .Q(
d_ff3_sh_y_out[19]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(n1445), .CK(clk), .RN(n3247), .Q(
d_ff3_sh_x_out[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(n1493), .CK(clk), .RN(n3247), .Q(
d_ff_Zn[20]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_20_ ( .D(n1235), .CK(clk), .RN(n3247),
.Q(d_ff2_Z[20]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(n1356), .CK(clk), .RN(n3247), .Q(
d_ff3_sh_y_out[20]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(n1443), .CK(clk), .RN(n3246), .Q(
d_ff3_sh_x_out[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(n1502), .CK(clk), .RN(n3246), .Q(
d_ff_Zn[17]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_17_ ( .D(n1241), .CK(clk), .RN(n3246),
.Q(d_ff2_Z[17]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(n1365), .CK(clk), .RN(n3246), .Q(
d_ff3_sh_y_out[17]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(n1449), .CK(clk), .RN(n3246), .Q(
d_ff3_sh_x_out[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n1541), .CK(clk), .RN(n3246), .Q(d_ff_Zn[4])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_4_ ( .D(n1267), .CK(clk), .RN(n3245), .Q(
d_ff2_Z[4]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(n1404), .CK(clk), .RN(n3245), .Q(
d_ff3_sh_y_out[4]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(n1475), .CK(clk), .RN(n3245), .Q(
d_ff3_sh_x_out[4]) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n1535), .CK(clk), .RN(n3245), .Q(d_ff_Zn[6])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_6_ ( .D(n1263), .CK(clk), .RN(n3245), .Q(
d_ff2_Z[6]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(n1398), .CK(clk), .RN(n3244), .Q(
d_ff3_sh_y_out[6]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(n1471), .CK(clk), .RN(n3244), .Q(
d_ff3_sh_x_out[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(n1514), .CK(clk), .RN(n3244), .Q(
d_ff_Zn[13]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_13_ ( .D(n1249), .CK(clk), .RN(n3244),
.Q(d_ff2_Z[13]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(n1377), .CK(clk), .RN(n3244), .Q(
d_ff3_sh_y_out[13]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(n1457), .CK(clk), .RN(n3243), .Q(
d_ff3_sh_x_out[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(n1505), .CK(clk), .RN(n3243), .Q(
d_ff_Zn[16]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_16_ ( .D(n1243), .CK(clk), .RN(n3243),
.Q(d_ff2_Z[16]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(n1368), .CK(clk), .RN(n3243), .Q(
d_ff3_sh_y_out[16]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(n1451), .CK(clk), .RN(n3242), .Q(
d_ff3_sh_x_out[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n1529), .CK(clk), .RN(n3242), .Q(d_ff_Zn[8])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_8_ ( .D(n1259), .CK(clk), .RN(n3242), .Q(
d_ff2_Z[8]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(n1392), .CK(clk), .RN(n3242), .Q(
d_ff3_sh_y_out[8]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(n1467), .CK(clk), .RN(n3242), .Q(
d_ff3_sh_x_out[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(n1520), .CK(clk), .RN(n3242), .Q(
d_ff_Zn[11]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_11_ ( .D(n1253), .CK(clk), .RN(n3241),
.Q(d_ff2_Z[11]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(n1383), .CK(clk), .RN(n3241), .Q(
d_ff3_sh_y_out[11]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(n1461), .CK(clk), .RN(n3241), .Q(
d_ff3_sh_x_out[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(n1511), .CK(clk), .RN(n3241), .Q(
d_ff_Zn[14]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_14_ ( .D(n1247), .CK(clk), .RN(n3241),
.Q(d_ff2_Z[14]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(n1374), .CK(clk), .RN(n3240), .Q(
d_ff3_sh_y_out[14]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(n1455), .CK(clk), .RN(n3240), .Q(
d_ff3_sh_x_out[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n1523), .CK(clk), .RN(n3240), .Q(
d_ff_Zn[10]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(n1255), .CK(clk), .RN(n3240),
.Q(d_ff2_Z[10]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(n1386), .CK(clk), .RN(n3240), .Q(
d_ff3_sh_y_out[10]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(n1463), .CK(clk), .RN(n3239), .Q(
d_ff3_sh_x_out[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n1517), .CK(clk), .RN(n3239), .Q(
d_ff_Zn[12]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_12_ ( .D(n1251), .CK(clk), .RN(n3239),
.Q(d_ff2_Z[12]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(n1380), .CK(clk), .RN(n3239), .Q(
d_ff3_sh_y_out[12]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(n1459), .CK(clk), .RN(n3238), .Q(
d_ff3_sh_x_out[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(n1419), .CK(clk), .RN(n3238), .Q(
d_ff_Zn[31]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(n1208), .CK(clk), .RN(n3238), .Q(
d_ff3_sh_y_out[31]) );
DFFRXLTS d_ff4_Xn_Q_reg_31_ ( .D(n1206), .CK(clk), .RN(n3238), .Q(
d_ff_Xn[31]), .QN(n3173) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(n1421), .CK(clk), .RN(n3238), .Q(
d_ff3_sh_x_out[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n1544), .CK(clk), .RN(n3237), .Q(d_ff_Zn[3])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_3_ ( .D(n1269), .CK(clk), .RN(n3237), .Q(
d_ff2_Z[3]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(n1407), .CK(clk), .RN(n3237), .Q(
d_ff3_sh_y_out[3]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(n1477), .CK(clk), .RN(n3237), .Q(
d_ff3_sh_x_out[3]) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n1547), .CK(clk), .RN(n3237), .Q(d_ff_Zn[2])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_2_ ( .D(n1271), .CK(clk), .RN(n3236), .Q(
d_ff2_Z[2]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(n1410), .CK(clk), .RN(n3236), .Q(
d_ff3_sh_y_out[2]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(n1479), .CK(clk), .RN(n3236), .Q(
d_ff3_sh_x_out[2]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(n1532), .CK(clk), .RN(n3236), .Q(d_ff_Zn[7])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_7_ ( .D(n1261), .CK(clk), .RN(n3236), .Q(
d_ff2_Z[7]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(n1395), .CK(clk), .RN(n3235), .Q(
d_ff3_sh_y_out[7]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(n1469), .CK(clk), .RN(n3235), .Q(
d_ff3_sh_x_out[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(
n1394), .CK(clk), .RN(n3194), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]), .QN(n1633) );
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n1553), .CK(clk), .RN(n3235), .Q(d_ff_Zn[0])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_0_ ( .D(n1275), .CK(clk), .RN(n3235), .Q(
d_ff2_Z[0]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(n1416), .CK(clk), .RN(n3234), .Q(
d_ff3_sh_y_out[0]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(n1483), .CK(clk), .RN(n3234), .Q(
d_ff3_sh_x_out[0]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n1550), .CK(clk), .RN(n3234), .Q(d_ff_Zn[1])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_1_ ( .D(n1273), .CK(clk), .RN(n3234), .Q(
d_ff2_Z[1]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(n1413), .CK(clk), .RN(n3233), .Q(
d_ff3_sh_y_out[1]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(n1481), .CK(clk), .RN(n3233), .Q(
d_ff3_sh_x_out[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n1526), .CK(clk), .RN(n3233), .Q(d_ff_Zn[9])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_9_ ( .D(n1257), .CK(clk), .RN(n3233), .Q(
d_ff2_Z[9]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(n1389), .CK(clk), .RN(n3233), .Q(
d_ff3_sh_y_out[9]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(n1465), .CK(clk), .RN(n3232), .Q(
d_ff3_sh_x_out[9]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(n1538), .CK(clk), .RN(n3232), .Q(d_ff_Zn[5])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_5_ ( .D(n1265), .CK(clk), .RN(n3232), .Q(
d_ff2_Z[5]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(n1401), .CK(clk), .RN(n3232), .Q(
d_ff3_sh_y_out[5]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(n1473), .CK(clk), .RN(n3231), .Q(
d_ff3_sh_x_out[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(
n1171), .CK(clk), .RN(n3196), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(
n1167), .CK(clk), .RN(n3196), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(n1153),
.CK(clk), .RN(n3197), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[28])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(n1152),
.CK(clk), .RN(n3197), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[29])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(n1151),
.CK(clk), .RN(n3197), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[30])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(n1148),
.CK(clk), .RN(n3197), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1147),
.CK(clk), .RN(n3213), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(n1143),
.CK(clk), .RN(n3197), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1142),
.CK(clk), .RN(n3214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(n1138),
.CK(clk), .RN(n3198), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[25]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1137),
.CK(clk), .RN(n3214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(n1133),
.CK(clk), .RN(n3198), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1132),
.CK(clk), .RN(n3214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(n1128),
.CK(clk), .RN(n3198), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1127),
.CK(clk), .RN(n3214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(n1123),
.CK(clk), .RN(n3199), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[28]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(n1118),
.CK(clk), .RN(n3199), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[29]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(n1113),
.CK(clk), .RN(n3199), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1102), .CK(clk), .RN(n3213), .Q(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[1])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(n1100),
.CK(clk), .RN(n3200), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[22])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(n1097),
.CK(clk), .RN(n3200), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[15])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(n1094),
.CK(clk), .RN(n3200), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[18])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(n1091),
.CK(clk), .RN(n3201), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[21])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(n1088),
.CK(clk), .RN(n3201), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[19])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(n1085),
.CK(clk), .RN(n3201), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[20])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(n1082),
.CK(clk), .RN(n3201), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[17])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(n1079),
.CK(clk), .RN(n3201), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[4])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(n1076),
.CK(clk), .RN(n3202), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[6])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(n1073),
.CK(clk), .RN(n1921), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[13])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(n1070),
.CK(clk), .RN(n1919), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[16])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(n1067),
.CK(clk), .RN(n1920), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[8])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(n1064),
.CK(clk), .RN(n3227), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[11])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(n1061),
.CK(clk), .RN(n3203), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[14])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(n1058),
.CK(clk), .RN(n3208), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[10])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1055),
.CK(clk), .RN(n3204), .Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1052),
.CK(clk), .RN(n1919), .Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1049), .CK(clk), .RN(n3202), .Q(result_add_subt[31]), .QN(n3090) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1048),
.CK(clk), .RN(n1921), .Q(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n1044),
.CK(clk), .RN(n3219), .Q(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM),
.QN(n3108) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1034),
.CK(clk), .RN(n3217), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .QN(n3074) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1033),
.CK(clk), .RN(n3217), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .QN(n3096) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1028), .CK(clk), .RN(n3218), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[14]),
.QN(n3091) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1024), .CK(clk), .RN(n3218), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]),
.QN(n3106) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(
n1023), .CK(clk), .RN(n3213), .Q(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(n1021),
.CK(clk), .RN(n3205), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[3])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(n1019),
.CK(clk), .RN(n3205), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[3])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(
n1015), .CK(clk), .RN(n3213), .Q(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(
n1011), .CK(clk), .RN(n3213), .Q(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(n1005),
.CK(clk), .RN(n3205), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[2])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(n1003),
.CK(clk), .RN(n3205), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[2])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(n998), .CK(
clk), .RN(n3205), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(n996), .CK(
clk), .RN(n3206), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(n991), .CK(
clk), .RN(n3206), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(n989), .CK(
clk), .RN(n3206), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(n984), .CK(
clk), .RN(n3206), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(n982), .CK(
clk), .RN(n3206), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(n977), .CK(
clk), .RN(n3207), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(n975), .CK(
clk), .RN(n3207), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(n970), .CK(
clk), .RN(n3207), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(n968), .CK(
clk), .RN(n3207), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n964),
.CK(clk), .RN(n3203), .Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_EXP) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n961),
.CK(clk), .RN(n3202), .Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SFG) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(n957),
.CK(clk), .RN(n1921), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[12])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(n955),
.CK(clk), .RN(n1919), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[12])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(n951),
.CK(clk), .RN(n3209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[10])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(n947),
.CK(clk), .RN(n3209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[14])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(n943),
.CK(clk), .RN(n3209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[11])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(n939), .CK(
clk), .RN(n3209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(n935),
.CK(clk), .RN(n3209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[16])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(n931),
.CK(clk), .RN(n3210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[13])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(n927), .CK(
clk), .RN(n3210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(n923), .CK(
clk), .RN(n3210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(n919),
.CK(clk), .RN(n3210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[17])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(n915),
.CK(clk), .RN(n3210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[20])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(n911),
.CK(clk), .RN(n3211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[19])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(n907),
.CK(clk), .RN(n3211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[21])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(n903),
.CK(clk), .RN(n3211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[18])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(n899),
.CK(clk), .RN(n3211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[15])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(n895),
.CK(clk), .RN(n3211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[22])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n891),
.CK(clk), .RN(n3219), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[0]), .QN(n3172) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n866),
.CK(clk), .RN(n3222), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[25]), .QN(n3164) );
CMPR32X2TS DP_OP_33J115_122_2179_U9 ( .A(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[0]), .B(n3094), .C(
DP_OP_33J115_122_2179_n18), .CO(DP_OP_33J115_122_2179_n8), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[0]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_28_ ( .D(n1433), .CK(clk), .RN(n3253),
.Q(d_ff2_X[28]), .QN(n3142) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_28_ ( .D(n1343), .CK(clk), .RN(n3253),
.Q(d_ff2_Y[28]), .QN(n3141) );
DFFRX1TS reg_region_flag_Q_reg_0_ ( .D(n1592), .CK(clk), .RN(n3263), .Q(
d_ff1_shift_region_flag_out[0]), .QN(n3133) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(n1158),
.CK(clk), .RN(n3196), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[23]),
.QN(n3129) );
DFFRX4TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(
n1043), .CK(clk), .RN(n3213), .Q(
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .QN(n3094) );
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(n1591), .CK(clk), .RN(n3263), .Q(
d_ff1_shift_region_flag_out[1]), .QN(n3085) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1322),
.CK(clk), .RN(n3194), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]), .QN(n3082) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n3261), .Q(
inst_CORDIC_FSM_v3_state_reg[4]), .QN(n3077) );
DFFRX1TS reg_operation_Q_reg_0_ ( .D(n1593), .CK(clk), .RN(n3263), .Q(
d_ff1_operation_out), .QN(n3070) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1105),
.CK(clk), .RN(n3200), .Q(underflow_flag) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1104),
.CK(clk), .RN(n3212), .Q(overflow_flag) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(n1182), .CK(clk), .RN(n3256), .Q(
data_output[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(n1181), .CK(clk), .RN(n3255), .Q(
data_output[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(n1180), .CK(clk), .RN(n3255), .Q(
data_output[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(n1179), .CK(clk), .RN(n3254), .Q(
data_output[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(n1178), .CK(clk), .RN(n3253), .Q(
data_output[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(n1177), .CK(clk), .RN(n3253), .Q(
data_output[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(n1176), .CK(clk), .RN(n3252), .Q(
data_output[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(n1175), .CK(clk), .RN(n3251), .Q(
data_output[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(n1202), .CK(clk), .RN(n3237), .Q(
data_output[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(n1203), .CK(clk), .RN(n3236), .Q(
data_output[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(n1198), .CK(clk), .RN(n3235), .Q(
data_output[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(n1205), .CK(clk), .RN(n3234), .Q(
data_output[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(n1204), .CK(clk), .RN(n3233), .Q(
data_output[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(n1196), .CK(clk), .RN(n3232), .Q(
data_output[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(n1200), .CK(clk), .RN(n3231), .Q(
data_output[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(n1193), .CK(clk), .RN(n3231), .Q(
data_output[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(n1195), .CK(clk), .RN(n3231), .Q(
data_output[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(n1191), .CK(clk), .RN(n3231), .Q(
data_output[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(n1194), .CK(clk), .RN(n3231), .Q(
data_output[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(n1197), .CK(clk), .RN(n3231), .Q(
data_output[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(n1189), .CK(clk), .RN(n3231), .Q(
data_output[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(n1192), .CK(clk), .RN(n3230), .Q(
data_output[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(n1199), .CK(clk), .RN(n3230), .Q(
data_output[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(n1201), .CK(clk), .RN(n3230), .Q(
data_output[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(n1188), .CK(clk), .RN(n3230), .Q(
data_output[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(n1185), .CK(clk), .RN(n3230), .Q(
data_output[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(n1186), .CK(clk), .RN(n3230), .Q(
data_output[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(n1184), .CK(clk), .RN(n3230), .Q(
data_output[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(n1187), .CK(clk), .RN(n3230), .Q(
data_output[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(n1183), .CK(clk), .RN(n3230), .Q(
data_output[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(n1173), .CK(clk), .RN(n3231), .Q(
data_output[31]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(n1190), .CK(clk), .RN(n3230), .Q(
data_output[15]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(
n1420), .CK(clk), .RN(n3193), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[31]), .QN(n3137) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(
n1218), .CK(clk), .RN(n3187), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[28]), .QN(n3100) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n877),
.CK(clk), .RN(n3221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[14]), .QN(n3163) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n876),
.CK(clk), .RN(n3221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n3150) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(
n1337), .CK(clk), .RN(n3187), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .QN(n3069) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(
n1325), .CK(clk), .RN(n3188), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]), .QN(n3140) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(
n1324), .CK(clk), .RN(n3187), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[30]), .QN(n3105) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(
n1388), .CK(clk), .RN(n3195), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .QN(n3123) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n1916), .Q(
inst_CORDIC_FSM_v3_state_reg[6]), .QN(n3104) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(
n1415), .CK(clk), .RN(n3194), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]), .QN(n3120) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n889),
.CK(clk), .RN(n3219), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[2]), .QN(n3157) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n888),
.CK(clk), .RN(n3219), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n3156) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n886),
.CK(clk), .RN(n3220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n3155) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n884),
.CK(clk), .RN(n3220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n3154) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n882),
.CK(clk), .RN(n3220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n3153) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n887),
.CK(clk), .RN(n3220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[4]), .QN(n3145) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n885),
.CK(clk), .RN(n3220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[6]), .QN(n3144) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n883),
.CK(clk), .RN(n3220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[8]), .QN(n3143) );
DFFRX2TS inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n3263), .Q(
inst_CORDIC_FSM_v3_state_reg[2]) );
DFFRX2TS inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n3265), .Q(
inst_CORDIC_FSM_v3_state_reg[1]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(
n1370), .CK(clk), .RN(n3188), .QN(n3111) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(
n1406), .CK(clk), .RN(n3193), .QN(n3112) );
CMPR32X2TS DP_OP_33J115_122_2179_U3 ( .A(n3094), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[6]), .C(
DP_OP_33J115_122_2179_n3), .CO(DP_OP_33J115_122_2179_n2), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_33J115_122_2179_U5 ( .A(DP_OP_33J115_122_2179_n14), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[4]), .C(
DP_OP_33J115_122_2179_n5), .CO(DP_OP_33J115_122_2179_n4), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_33J115_122_2179_U7 ( .A(DP_OP_33J115_122_2179_n16), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[2]), .C(
DP_OP_33J115_122_2179_n7), .CO(DP_OP_33J115_122_2179_n6), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_33J115_122_2179_U8 ( .A(DP_OP_33J115_122_2179_n17), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[1]), .C(
DP_OP_33J115_122_2179_n8), .CO(DP_OP_33J115_122_2179_n7), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[1]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(
n1268), .CK(clk), .RN(n3193), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(n1000),
.CK(clk), .RN(n3222), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(n979), .CK(
clk), .RN(n3222), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]) );
DFFRX2TS VAR_CONT_temp_reg_0_ ( .D(n1616), .CK(clk), .RN(n3261), .Q(
cont_var_out[0]), .QN(n3097) );
DFFRX2TS ITER_CONT_temp_reg_1_ ( .D(n1619), .CK(clk), .RN(n3264), .Q(
cont_iter_out[1]), .QN(n3098) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1027), .CK(clk), .RN(n3219), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]),
.QN(n3171) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(
n1556), .CK(clk), .RN(n3193), .Q(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n3067) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(
n1555), .CK(clk), .RN(n3193), .Q(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]), .QN(n3068) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(
n1226), .CK(clk), .RN(n3186), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .QN(n3134) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(
n1254), .CK(clk), .RN(n3192), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .QN(n3093) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(
n1264), .CK(clk), .RN(n3195), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[5]), .QN(n3126) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(
n1333), .CK(clk), .RN(n3187), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]), .QN(n3117) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(
n1335), .CK(clk), .RN(n3187), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]), .QN(n3118) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(
n1352), .CK(clk), .RN(n3189), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .QN(n3124) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(
n1339), .CK(clk), .RN(n3187), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .QN(n3125) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(
n1379), .CK(clk), .RN(n3192), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .QN(n3119) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(
n1391), .CK(clk), .RN(n3191), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]), .QN(n3122) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(
n1400), .CK(clk), .RN(n3195), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .QN(n3103) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(
n1355), .CK(clk), .RN(n3189), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]), .QN(n3110) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(n892),
.CK(clk), .RN(n3226), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(n912),
.CK(clk), .RN(n3226), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(n900),
.CK(clk), .RN(n3225), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(n904),
.CK(clk), .RN(n3226), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(n908),
.CK(clk), .RN(n3226), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(n932),
.CK(clk), .RN(n3225), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(n944),
.CK(clk), .RN(n3225), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(n952),
.CK(clk), .RN(n3224), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(n916),
.CK(clk), .RN(n3225), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(n896),
.CK(clk), .RN(n3225), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(n928),
.CK(clk), .RN(n3224), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(n940),
.CK(clk), .RN(n3224), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(n948),
.CK(clk), .RN(n3224), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ (
.D(inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_),
.CK(clk), .RN(n3186), .Q(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(
n3266) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1103), .CK(clk), .RN(n3219), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(n3182),
.CK(clk), .RN(n3223), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[7])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(n933),
.CK(clk), .RN(n3225), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n997),
.CK(clk), .RN(n3206), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1139),
.CK(clk), .RN(n3198), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1150),
.CK(clk), .RN(n3197), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1066), .CK(clk), .RN(n3204), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(
n1169), .CK(clk), .RN(n3196), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n956), .CK(clk), .RN(n2084), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[12])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1122),
.CK(clk), .RN(n3214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS ITER_CONT_temp_reg_0_ ( .D(n1620), .CK(clk), .RN(n3265), .Q(n1709),
.QN(n3185) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(
n1228), .CK(clk), .RN(n3186), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(
n1244), .CK(clk), .RN(n3188), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(
n1248), .CK(clk), .RN(n3191), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(
n1232), .CK(clk), .RN(n3189), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(
n1252), .CK(clk), .RN(n3192), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(
n1240), .CK(clk), .RN(n3190), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(
n1258), .CK(clk), .RN(n3191), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(
n1554), .CK(clk), .RN(n3193), .Q(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n1639) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(
n1234), .CK(clk), .RN(n3190), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(
n1256), .CK(clk), .RN(n3195), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(
n1220), .CK(clk), .RN(n3187), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(
n1270), .CK(clk), .RN(n3194), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]) );
DFFRX2TS VAR_CONT_temp_reg_1_ ( .D(n1615), .CK(clk), .RN(n3261), .Q(
cont_var_out[1]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(
n1274), .CK(clk), .RN(n3194), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[0]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1035),
.CK(clk), .RN(n3217), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]) );
DFFRX4TS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(n1625),
.CK(clk), .RN(n3186), .Q(busy), .QN(n3228) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1314),
.CK(clk), .RN(n3190), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1319),
.CK(clk), .RN(n3188), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1310),
.CK(clk), .RN(n3191), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(
n1260), .CK(clk), .RN(n3194), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[7]), .QN(n3095) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1313),
.CK(clk), .RN(n3191), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1312),
.CK(clk), .RN(n3191), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(
n1224), .CK(clk), .RN(n3186), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[25]), .QN(n3086) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1040),
.CK(clk), .RN(n3217), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_27_ ( .D(n1434), .CK(clk), .RN(n3253),
.Q(d_ff2_X[27]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(
n1403), .CK(clk), .RN(n3190), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[4]), .QN(n1640) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ (
.D(n1629), .CK(clk), .RN(n3186), .Q(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .QN(
n3132) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1037),
.CK(clk), .RN(n3216), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n3073) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(
n1397), .CK(clk), .RN(n3190), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .QN(n1653) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1039),
.CK(clk), .RN(n3217), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n1634) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1315),
.CK(clk), .RN(n3195), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]), .QN(n3127) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1308),
.CK(clk), .RN(n3195), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[10]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1309),
.CK(clk), .RN(n3192), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[11]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(
n1385), .CK(clk), .RN(n3192), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .QN(n1654) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1036),
.CK(clk), .RN(n3217), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n3092) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(n1342), .CK(clk), .RN(n3252),
.Q(d_ff2_Y[29]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(n1432), .CK(clk), .RN(n3252),
.Q(d_ff2_X[29]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_23_ ( .D(n1438), .CK(clk), .RN(n3256),
.Q(d_ff2_X[23]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1163), .CK(clk), .RN(n3212), .Q(result_add_subt[26]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1164), .CK(clk), .RN(n3212), .Q(result_add_subt[25]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n971),
.CK(clk), .RN(n3207), .Q(result_add_subt[5]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n978),
.CK(clk), .RN(n3207), .Q(result_add_subt[9]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n985),
.CK(clk), .RN(n3206), .Q(result_add_subt[1]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n992),
.CK(clk), .RN(n3206), .Q(result_add_subt[0]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n999),
.CK(clk), .RN(n3205), .Q(result_add_subt[7]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1006),
.CK(clk), .RN(n3205), .Q(result_add_subt[2]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1022),
.CK(clk), .RN(n3205), .Q(result_add_subt[3]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1056), .CK(clk), .RN(n3204), .Q(result_add_subt[12]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1059), .CK(clk), .RN(n3208), .Q(result_add_subt[10]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1062), .CK(clk), .RN(n3202), .Q(result_add_subt[14]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1065), .CK(clk), .RN(n3204), .Q(result_add_subt[11]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1068),
.CK(clk), .RN(n1921), .Q(result_add_subt[8]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1071), .CK(clk), .RN(n1919), .Q(result_add_subt[16]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1074), .CK(clk), .RN(n2084), .Q(result_add_subt[13]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1077),
.CK(clk), .RN(n3208), .Q(result_add_subt[6]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1080),
.CK(clk), .RN(n3201), .Q(result_add_subt[4]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1083), .CK(clk), .RN(n3201), .Q(result_add_subt[17]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1086), .CK(clk), .RN(n3201), .Q(result_add_subt[20]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1089), .CK(clk), .RN(n3201), .Q(result_add_subt[19]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1092), .CK(clk), .RN(n3201), .Q(result_add_subt[21]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1095), .CK(clk), .RN(n3200), .Q(result_add_subt[18]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1098), .CK(clk), .RN(n3200), .Q(result_add_subt[15]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1101), .CK(clk), .RN(n3200), .Q(result_add_subt[22]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1159), .CK(clk), .RN(n3212), .Q(result_add_subt[30]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(
n1207), .CK(clk), .RN(n3193), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[31]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1038),
.CK(clk), .RN(n3216), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .QN(n3102) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(
n1262), .CK(clk), .RN(n3190), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .QN(n3076) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(
n1329), .CK(clk), .RN(n3188), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .QN(n1656) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1032), .CK(clk), .RN(n3217), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10])
);
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1041),
.CK(clk), .RN(n3217), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n1645) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n881),
.CK(clk), .RN(n3220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[10]), .QN(n1644) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(
n1367), .CK(clk), .RN(n3191), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(n1345), .CK(clk), .RN(n3254),
.Q(d_ff2_Y[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(n1347), .CK(clk), .RN(n3256),
.Q(d_ff2_Y[24]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(n1435), .CK(clk), .RN(n3254),
.Q(d_ff2_X[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(n1436), .CK(clk), .RN(n3255),
.Q(d_ff2_X[25]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(n1437), .CK(clk), .RN(n3256),
.Q(d_ff2_X[24]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1303),
.CK(clk), .RN(n3188), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[5]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_31_ ( .D(n1214), .CK(clk), .RN(n3238),
.Q(d_ff2_Z[31]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n879),
.CK(clk), .RN(n3220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[12]), .QN(n3152) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_30_ ( .D(n1341), .CK(clk), .RN(n3252),
.Q(d_ff2_Y[30]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_30_ ( .D(n1431), .CK(clk), .RN(n3251),
.Q(d_ff2_X[30]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(n1157),
.CK(clk), .RN(n3196), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[24]),
.QN(n3084) );
DFFRX1TS d_ff4_Xn_Q_reg_28_ ( .D(n1280), .CK(clk), .RN(n3253), .Q(
d_ff_Xn[28]) );
DFFRX1TS d_ff4_Yn_Q_reg_31_ ( .D(n1418), .CK(clk), .RN(n3238), .Q(
d_ff_Yn[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_5_ ( .D(n1402), .CK(clk), .RN(n3232), .Q(
d_ff2_Y[5]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_1_ ( .D(n1414), .CK(clk), .RN(n3234), .Q(
d_ff2_Y[1]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_3_ ( .D(n1408), .CK(clk), .RN(n3237), .Q(
d_ff2_Y[3]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_12_ ( .D(n1381), .CK(clk), .RN(n3239),
.Q(d_ff2_Y[12]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_10_ ( .D(n1387), .CK(clk), .RN(n3240),
.Q(d_ff2_Y[10]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_14_ ( .D(n1375), .CK(clk), .RN(n3240),
.Q(d_ff2_Y[14]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_16_ ( .D(n1369), .CK(clk), .RN(n3243),
.Q(d_ff2_Y[16]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_4_ ( .D(n1405), .CK(clk), .RN(n3245), .Q(
d_ff2_Y[4]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_19_ ( .D(n1360), .CK(clk), .RN(n3248),
.Q(d_ff2_Y[19]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_18_ ( .D(n1363), .CK(clk), .RN(n3249),
.Q(d_ff2_Y[18]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_22_ ( .D(n1351), .CK(clk), .RN(n3251),
.Q(d_ff2_Y[22]) );
DFFRX1TS d_ff4_Yn_Q_reg_27_ ( .D(n1284), .CK(clk), .RN(n3254), .Q(
d_ff_Yn[27]) );
DFFRX1TS d_ff4_Yn_Q_reg_23_ ( .D(n1296), .CK(clk), .RN(n3257), .Q(
d_ff_Yn[23]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_5_ ( .D(n1474), .CK(clk), .RN(n3231), .Q(
d_ff2_X[5]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_1_ ( .D(n1482), .CK(clk), .RN(n3233), .Q(
d_ff2_X[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_7_ ( .D(n1470), .CK(clk), .RN(n3235), .Q(
d_ff2_X[7]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_2_ ( .D(n1480), .CK(clk), .RN(n3236), .Q(
d_ff2_X[2]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_3_ ( .D(n1478), .CK(clk), .RN(n3237), .Q(
d_ff2_X[3]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_12_ ( .D(n1460), .CK(clk), .RN(n3239),
.Q(d_ff2_X[12]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_10_ ( .D(n1464), .CK(clk), .RN(n3239),
.Q(d_ff2_X[10]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_14_ ( .D(n1456), .CK(clk), .RN(n3240),
.Q(d_ff2_X[14]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_16_ ( .D(n1452), .CK(clk), .RN(n3243),
.Q(d_ff2_X[16]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_13_ ( .D(n1458), .CK(clk), .RN(n3243),
.Q(d_ff2_X[13]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_6_ ( .D(n1472), .CK(clk), .RN(n3244), .Q(
d_ff2_X[6]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_17_ ( .D(n1450), .CK(clk), .RN(n3246),
.Q(d_ff2_X[17]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_20_ ( .D(n1444), .CK(clk), .RN(n3247),
.Q(d_ff2_X[20]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_19_ ( .D(n1446), .CK(clk), .RN(n3247),
.Q(d_ff2_X[19]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_9_ ( .D(n1466), .CK(clk), .RN(n3232), .Q(
d_ff2_X[9]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_0_ ( .D(n1484), .CK(clk), .RN(n3234), .Q(
d_ff2_X[0]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_11_ ( .D(n1462), .CK(clk), .RN(n3241),
.Q(d_ff2_X[11]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_8_ ( .D(n1468), .CK(clk), .RN(n3242), .Q(
d_ff2_X[8]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_4_ ( .D(n1476), .CK(clk), .RN(n3245), .Q(
d_ff2_X[4]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_21_ ( .D(n1442), .CK(clk), .RN(n3248),
.Q(d_ff2_X[21]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_18_ ( .D(n1448), .CK(clk), .RN(n3249),
.Q(d_ff2_X[18]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_15_ ( .D(n1454), .CK(clk), .RN(n3250),
.Q(d_ff2_X[15]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_22_ ( .D(n1440), .CK(clk), .RN(n3251),
.Q(d_ff2_X[22]) );
DFFRX1TS d_ff4_Yn_Q_reg_28_ ( .D(n1281), .CK(clk), .RN(n3253), .Q(
d_ff_Yn[28]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1160), .CK(clk), .RN(n3212), .Q(result_add_subt[29]), .QN(n3169) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1165), .CK(clk), .RN(n3212), .Q(result_add_subt[24]), .QN(n3166) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(n993), .CK(
clk), .RN(n3223), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(n1016),
.CK(clk), .RN(n3222), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(n920), .CK(
clk), .RN(n3223), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(n924), .CK(
clk), .RN(n3223), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(n965), .CK(
clk), .RN(n3223), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(n986), .CK(
clk), .RN(n3222), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(n972), .CK(
clk), .RN(n3224), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1320),
.CK(clk), .RN(n3194), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1321),
.CK(clk), .RN(n3194), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(
n1412), .CK(clk), .RN(n3195), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[1]), .QN(n3121) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(
n1358), .CK(clk), .RN(n3189), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .QN(n3116) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(
n1373), .CK(clk), .RN(n3192), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .QN(n3078) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1299),
.CK(clk), .RN(n3188), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[1]) );
DFFRX1TS reg_LUT_Q_reg_0_ ( .D(n1594), .CK(clk), .RN(n3258), .Q(
d_ff3_LUT_out[0]) );
DFFRX1TS reg_LUT_Q_reg_4_ ( .D(n1598), .CK(clk), .RN(n3259), .Q(
d_ff3_LUT_out[4]) );
DFFRX1TS reg_LUT_Q_reg_12_ ( .D(n1605), .CK(clk), .RN(n3259), .Q(
d_ff3_LUT_out[12]) );
DFFRX1TS reg_LUT_Q_reg_21_ ( .D(n1609), .CK(clk), .RN(n3259), .Q(
d_ff3_LUT_out[21]) );
DFFRX1TS reg_LUT_Q_reg_24_ ( .D(n1611), .CK(clk), .RN(n3260), .Q(
d_ff3_LUT_out[24]) );
DFFRX1TS reg_LUT_Q_reg_23_ ( .D(n1610), .CK(clk), .RN(n3260), .Q(
d_ff3_LUT_out[23]) );
DFFRX1TS reg_LUT_Q_reg_2_ ( .D(n1596), .CK(clk), .RN(n3259), .Q(
d_ff3_LUT_out[2]) );
DFFRX1TS reg_LUT_Q_reg_6_ ( .D(n1600), .CK(clk), .RN(n3259), .Q(
d_ff3_LUT_out[6]) );
DFFRX1TS reg_LUT_Q_reg_25_ ( .D(n1612), .CK(clk), .RN(n3260), .Q(
d_ff3_LUT_out[25]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1298),
.CK(clk), .RN(n3215), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[0]) );
DFFRX1TS reg_LUT_Q_reg_10_ ( .D(n1604), .CK(clk), .RN(n3259), .Q(
d_ff3_LUT_out[10]) );
DFFRX1TS reg_LUT_Q_reg_7_ ( .D(n1601), .CK(clk), .RN(n3259), .Q(
d_ff3_LUT_out[7]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(
n1238), .CK(clk), .RN(n3189), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(
n1272), .CK(clk), .RN(n3195), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(
n1250), .CK(clk), .RN(n3193), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(
n1236), .CK(clk), .RN(n3189), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(
n1230), .CK(clk), .RN(n3188), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(
n1246), .CK(clk), .RN(n3192), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(
n1216), .CK(clk), .RN(n3187), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(
n1242), .CK(clk), .RN(n3191), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .QN(n3099) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(
n1266), .CK(clk), .RN(n3190), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .QN(n3071) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1311),
.CK(clk), .RN(n3192), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(
n1222), .CK(clk), .RN(n3187), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[26]), .QN(n3087) );
DFFRX2TS reg_val_muxY_2stage_Q_reg_27_ ( .D(n1344), .CK(clk), .RN(n3254),
.Q(d_ff2_Y[27]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1307),
.CK(clk), .RN(n3192), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[9]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1306),
.CK(clk), .RN(n3195), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[8]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(
n1409), .CK(clk), .RN(n3194), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .QN(n1655) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_23_ ( .D(n1348), .CK(clk), .RN(n3256),
.Q(d_ff2_Y[23]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(n1346), .CK(clk), .RN(n3255),
.Q(d_ff2_Y[25]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1302),
.CK(clk), .RN(n3196), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[4]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1318),
.CK(clk), .RN(n3189), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[20]), .QN(n3128) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1316),
.CK(clk), .RN(n3195), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[18]), .QN(n3131) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1304),
.CK(clk), .RN(n3190), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[6]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(
n1349), .CK(clk), .RN(n3188), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .QN(n3080) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(
n1361), .CK(clk), .RN(n3189), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]), .QN(n3079) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(
n1364), .CK(clk), .RN(n3190), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]), .QN(n3115) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1323),
.CK(clk), .RN(n3194), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[25]), .QN(n3081) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1317),
.CK(clk), .RN(n3190), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[19]), .QN(n3130) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_23_ ( .D(n1110),
.CK(clk), .RN(n3199), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[23])
);
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(n1156),
.CK(clk), .RN(n3196), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[25]),
.QN(n1706) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(n1154),
.CK(clk), .RN(n3197), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[27])
);
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n871),
.CK(clk), .RN(n3221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[20]), .QN(n3160) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n869),
.CK(clk), .RN(n3221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[22]), .QN(n3159) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n875),
.CK(clk), .RN(n3221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[16]), .QN(n3162) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n873),
.CK(clk), .RN(n3221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[18]), .QN(n3161) );
DFFRX1TS d_ff4_Xn_Q_reg_1_ ( .D(n1548), .CK(clk), .RN(n3233), .Q(d_ff_Xn[1])
);
DFFRX1TS d_ff4_Xn_Q_reg_5_ ( .D(n1536), .CK(clk), .RN(n3232), .Q(d_ff_Xn[5])
);
DFFRX1TS d_ff4_Xn_Q_reg_2_ ( .D(n1545), .CK(clk), .RN(n3236), .Q(d_ff_Xn[2])
);
DFFRX1TS d_ff4_Xn_Q_reg_7_ ( .D(n1530), .CK(clk), .RN(n3235), .Q(d_ff_Xn[7])
);
DFFRX1TS d_ff4_Xn_Q_reg_12_ ( .D(n1515), .CK(clk), .RN(n3239), .Q(
d_ff_Xn[12]) );
DFFRX1TS d_ff4_Xn_Q_reg_3_ ( .D(n1542), .CK(clk), .RN(n3237), .Q(d_ff_Xn[3])
);
DFFRX1TS d_ff4_Xn_Q_reg_14_ ( .D(n1509), .CK(clk), .RN(n3240), .Q(
d_ff_Xn[14]) );
DFFRX1TS d_ff4_Xn_Q_reg_10_ ( .D(n1521), .CK(clk), .RN(n3239), .Q(
d_ff_Xn[10]) );
DFFRX1TS d_ff4_Xn_Q_reg_13_ ( .D(n1512), .CK(clk), .RN(n3243), .Q(
d_ff_Xn[13]) );
DFFRX1TS d_ff4_Xn_Q_reg_16_ ( .D(n1503), .CK(clk), .RN(n3243), .Q(
d_ff_Xn[16]) );
DFFRX1TS d_ff4_Xn_Q_reg_17_ ( .D(n1500), .CK(clk), .RN(n3246), .Q(
d_ff_Xn[17]) );
DFFRX1TS d_ff4_Xn_Q_reg_6_ ( .D(n1533), .CK(clk), .RN(n3244), .Q(d_ff_Xn[6])
);
DFFRX1TS d_ff4_Xn_Q_reg_19_ ( .D(n1494), .CK(clk), .RN(n3247), .Q(
d_ff_Xn[19]) );
DFFRX1TS d_ff4_Xn_Q_reg_20_ ( .D(n1491), .CK(clk), .RN(n3247), .Q(
d_ff_Xn[20]) );
DFFRX1TS d_ff4_Xn_Q_reg_26_ ( .D(n1286), .CK(clk), .RN(n3254), .Q(
d_ff_Xn[26]) );
DFFRX1TS d_ff4_Xn_Q_reg_29_ ( .D(n1277), .CK(clk), .RN(n3252), .Q(
d_ff_Xn[29]) );
DFFRX1TS d_ff4_Xn_Q_reg_24_ ( .D(n1292), .CK(clk), .RN(n3256), .Q(
d_ff_Xn[24]) );
DFFRX1TS d_ff4_Xn_Q_reg_25_ ( .D(n1289), .CK(clk), .RN(n3255), .Q(
d_ff_Xn[25]) );
DFFRX1TS d_ff4_Xn_Q_reg_0_ ( .D(n1551), .CK(clk), .RN(n3234), .Q(d_ff_Xn[0])
);
DFFRX1TS d_ff4_Xn_Q_reg_9_ ( .D(n1524), .CK(clk), .RN(n3232), .Q(d_ff_Xn[9])
);
DFFRX1TS d_ff4_Xn_Q_reg_8_ ( .D(n1527), .CK(clk), .RN(n3242), .Q(d_ff_Xn[8])
);
DFFRX1TS d_ff4_Xn_Q_reg_11_ ( .D(n1518), .CK(clk), .RN(n3241), .Q(
d_ff_Xn[11]) );
DFFRX1TS d_ff4_Xn_Q_reg_21_ ( .D(n1488), .CK(clk), .RN(n3248), .Q(
d_ff_Xn[21]) );
DFFRX1TS d_ff4_Xn_Q_reg_4_ ( .D(n1539), .CK(clk), .RN(n3245), .Q(d_ff_Xn[4])
);
DFFRX1TS d_ff4_Xn_Q_reg_15_ ( .D(n1506), .CK(clk), .RN(n3250), .Q(
d_ff_Xn[15]) );
DFFRX1TS d_ff4_Xn_Q_reg_18_ ( .D(n1497), .CK(clk), .RN(n3249), .Q(
d_ff_Xn[18]) );
DFFRX1TS d_ff4_Xn_Q_reg_30_ ( .D(n1210), .CK(clk), .RN(n3251), .Q(
d_ff_Xn[30]) );
DFFRX1TS d_ff4_Xn_Q_reg_22_ ( .D(n1485), .CK(clk), .RN(n3251), .Q(
d_ff_Xn[22]) );
DFFRX1TS d_ff4_Xn_Q_reg_27_ ( .D(n1283), .CK(clk), .RN(n3254), .Q(
d_ff_Xn[27]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n867),
.CK(clk), .RN(n3222), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[24]), .QN(n3158) );
DFFRX1TS d_ff4_Yn_Q_reg_5_ ( .D(n1537), .CK(clk), .RN(n3232), .Q(d_ff_Yn[5])
);
DFFRX1TS d_ff4_Yn_Q_reg_1_ ( .D(n1549), .CK(clk), .RN(n3234), .Q(d_ff_Yn[1])
);
DFFRX1TS d_ff4_Yn_Q_reg_9_ ( .D(n1525), .CK(clk), .RN(n3233), .Q(d_ff_Yn[9])
);
DFFRX1TS d_ff4_Yn_Q_reg_7_ ( .D(n1531), .CK(clk), .RN(n3235), .Q(d_ff_Yn[7])
);
DFFRX1TS d_ff4_Yn_Q_reg_0_ ( .D(n1552), .CK(clk), .RN(n3235), .Q(d_ff_Yn[0])
);
DFFRX1TS d_ff4_Yn_Q_reg_3_ ( .D(n1543), .CK(clk), .RN(n3237), .Q(d_ff_Yn[3])
);
DFFRX1TS d_ff4_Yn_Q_reg_2_ ( .D(n1546), .CK(clk), .RN(n3236), .Q(d_ff_Yn[2])
);
DFFRX1TS d_ff4_Yn_Q_reg_10_ ( .D(n1522), .CK(clk), .RN(n3240), .Q(
d_ff_Yn[10]) );
DFFRX1TS d_ff4_Yn_Q_reg_12_ ( .D(n1516), .CK(clk), .RN(n3239), .Q(
d_ff_Yn[12]) );
DFFRX1TS d_ff4_Yn_Q_reg_11_ ( .D(n1519), .CK(clk), .RN(n3241), .Q(
d_ff_Yn[11]) );
DFFRX1TS d_ff4_Yn_Q_reg_14_ ( .D(n1510), .CK(clk), .RN(n3241), .Q(
d_ff_Yn[14]) );
DFFRX1TS d_ff4_Yn_Q_reg_16_ ( .D(n1504), .CK(clk), .RN(n3243), .Q(
d_ff_Yn[16]) );
DFFRX1TS d_ff4_Yn_Q_reg_8_ ( .D(n1528), .CK(clk), .RN(n3242), .Q(d_ff_Yn[8])
);
DFFRX1TS d_ff4_Yn_Q_reg_6_ ( .D(n1534), .CK(clk), .RN(n3245), .Q(d_ff_Yn[6])
);
DFFRX1TS d_ff4_Yn_Q_reg_13_ ( .D(n1513), .CK(clk), .RN(n3244), .Q(
d_ff_Yn[13]) );
DFFRX1TS d_ff4_Yn_Q_reg_17_ ( .D(n1501), .CK(clk), .RN(n3246), .Q(
d_ff_Yn[17]) );
DFFRX1TS d_ff4_Yn_Q_reg_4_ ( .D(n1540), .CK(clk), .RN(n3245), .Q(d_ff_Yn[4])
);
DFFRX1TS d_ff4_Yn_Q_reg_24_ ( .D(n1293), .CK(clk), .RN(n3256), .Q(
d_ff_Yn[24]) );
DFFRX1TS d_ff4_Yn_Q_reg_25_ ( .D(n1290), .CK(clk), .RN(n3255), .Q(
d_ff_Yn[25]) );
DFFRX1TS d_ff4_Yn_Q_reg_26_ ( .D(n1287), .CK(clk), .RN(n3254), .Q(
d_ff_Yn[26]) );
DFFRX1TS d_ff4_Yn_Q_reg_29_ ( .D(n1278), .CK(clk), .RN(n3252), .Q(
d_ff_Yn[29]) );
DFFRX1TS d_ff4_Yn_Q_reg_30_ ( .D(n1211), .CK(clk), .RN(n3252), .Q(
d_ff_Yn[30]) );
DFFRX1TS d_ff4_Yn_Q_reg_22_ ( .D(n1486), .CK(clk), .RN(n3251), .Q(
d_ff_Yn[22]) );
DFFRX1TS d_ff4_Yn_Q_reg_15_ ( .D(n1507), .CK(clk), .RN(n3250), .Q(
d_ff_Yn[15]) );
DFFRX1TS d_ff4_Yn_Q_reg_18_ ( .D(n1498), .CK(clk), .RN(n3249), .Q(
d_ff_Yn[18]) );
DFFRX1TS d_ff4_Yn_Q_reg_21_ ( .D(n1489), .CK(clk), .RN(n3249), .Q(
d_ff_Yn[21]) );
DFFRX1TS d_ff4_Yn_Q_reg_19_ ( .D(n1495), .CK(clk), .RN(n3248), .Q(
d_ff_Yn[19]) );
DFFRX1TS d_ff4_Yn_Q_reg_20_ ( .D(n1492), .CK(clk), .RN(n3247), .Q(
d_ff_Yn[20]) );
DFFRX1TS d_ff4_Xn_Q_reg_23_ ( .D(n1295), .CK(clk), .RN(n3256), .Q(
d_ff_Xn[23]) );
DFFRX4TS ITER_CONT_temp_reg_3_ ( .D(n1617), .CK(clk), .RN(n1917), .Q(
cont_iter_out[3]), .QN(n3072) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1166), .CK(clk), .RN(n3213), .Q(result_add_subt[23]), .QN(n3165) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1162), .CK(clk), .RN(n3212), .Q(result_add_subt[27]), .QN(n3167) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1161), .CK(clk), .RN(n3212), .Q(result_add_subt[28]), .QN(n3168) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(n936), .CK(
clk), .RN(n3223), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_24_ ( .D(n1109),
.CK(clk), .RN(n3199), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[24]),
.QN(n1657) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_26_ ( .D(n1107),
.CK(clk), .RN(n3200), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[26]),
.QN(n1658) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(
n1558), .CK(clk), .RN(n3193), .Q(
inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2), .QN(n1649) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1212),
.CK(clk), .RN(n3193), .Q(inst_FPU_PIPELINED_FPADDSUB_intAS) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(
n1376), .CK(clk), .RN(n3191), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .QN(n3114) );
DFFRX1TS reg_shift_x_Q_reg_23_ ( .D(n1430), .CK(clk), .RN(n3258), .Q(
d_ff3_sh_x_out[23]) );
DFFRX1TS reg_LUT_Q_reg_1_ ( .D(n1595), .CK(clk), .RN(n3260), .Q(
d_ff3_LUT_out[1]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1300),
.CK(clk), .RN(n3189), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[2]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1301),
.CK(clk), .RN(n3189), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[3]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n890),
.CK(clk), .RN(n3219), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[1]), .QN(n3089) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(n1106),
.CK(clk), .RN(n3200), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[27])
);
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_25_ ( .D(n1108),
.CK(clk), .RN(n3200), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[25]),
.QN(n3136) );
DFFRX1TS reg_shift_y_Q_reg_23_ ( .D(n1340), .CK(clk), .RN(n3258), .Q(
d_ff3_sh_y_out[23]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(
n1382), .CK(clk), .RN(n3192), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]), .QN(n3113) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ (
.D(n1628), .CK(clk), .RN(n3186), .Q(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(
n1643) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1305),
.CK(clk), .RN(n3191), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[7]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(
n1331), .CK(clk), .RN(n3187), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n878),
.CK(clk), .RN(n3221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n3151) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n874),
.CK(clk), .RN(n3221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n3149) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n872),
.CK(clk), .RN(n3221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n3148) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n870),
.CK(clk), .RN(n3221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n3147) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n868),
.CK(clk), .RN(n3222), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n3146) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_15_ ( .D(n1372), .CK(clk), .RN(n3250),
.Q(d_ff2_Y[15]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_21_ ( .D(n1354), .CK(clk), .RN(n3248),
.Q(d_ff2_Y[21]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_20_ ( .D(n1357), .CK(clk), .RN(n3247),
.Q(d_ff2_Y[20]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_17_ ( .D(n1366), .CK(clk), .RN(n3246),
.Q(d_ff2_Y[17]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_6_ ( .D(n1399), .CK(clk), .RN(n3244), .Q(
d_ff2_Y[6]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_13_ ( .D(n1378), .CK(clk), .RN(n3244),
.Q(d_ff2_Y[13]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_8_ ( .D(n1393), .CK(clk), .RN(n3242), .Q(
d_ff2_Y[8]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_11_ ( .D(n1384), .CK(clk), .RN(n3241),
.Q(d_ff2_Y[11]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_31_ ( .D(n1209), .CK(clk), .RN(n3238),
.Q(d_ff2_Y[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_2_ ( .D(n1411), .CK(clk), .RN(n3236), .Q(
d_ff2_Y[2]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_7_ ( .D(n1396), .CK(clk), .RN(n3235), .Q(
d_ff2_Y[7]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_0_ ( .D(n1417), .CK(clk), .RN(n3234), .Q(
d_ff2_Y[0]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_9_ ( .D(n1390), .CK(clk), .RN(n3233), .Q(
d_ff2_Y[9]) );
DFFRX1TS reg_sign_Q_reg_0_ ( .D(n1213), .CK(clk), .RN(n3238), .Q(
d_ff3_sign_out) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n880),
.CK(clk), .RN(n3220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n1707) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_31_ ( .D(n1422), .CK(clk), .RN(n3238),
.Q(d_ff2_X[31]) );
DFFSX1TS inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n3265), .Q(
inst_CORDIC_FSM_v3_state_reg[0]), .QN(n3101) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1025), .CK(clk), .RN(n3219), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17])
);
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1014), .CK(clk), .RN(n3218), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19])
);
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1013), .CK(clk), .RN(n3218), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20])
);
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1012), .CK(clk), .RN(n3218), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]),
.QN(n3109) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1010), .CK(clk), .RN(n3218), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22])
);
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1009), .CK(clk), .RN(n3218), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23])
);
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1008), .CK(clk), .RN(n3218), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24])
);
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1029), .CK(clk), .RN(n3218), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]),
.QN(n3139) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1030), .CK(clk), .RN(n3217), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]),
.QN(n3138) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1031), .CK(clk), .RN(n3218), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]),
.QN(n3088) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_Ready_reg_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n3186), .QN(n3267) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1111), .CK(clk), .RN(n3215), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1116), .CK(clk), .RN(n3214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1126), .CK(clk), .RN(n3214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1136), .CK(clk), .RN(n3214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1141), .CK(clk), .RN(n3213), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1146), .CK(clk), .RN(n3213), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1042),
.CK(clk), .RN(n3217), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[0]), .QN(n3229) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1121), .CK(clk), .RN(n3214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1131), .CK(clk), .RN(n3214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(n901),
.CK(clk), .RN(n3226), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(n905),
.CK(clk), .RN(n3226), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(n913),
.CK(clk), .RN(n3226), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(n909),
.CK(clk), .RN(n3226), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(n917),
.CK(clk), .RN(n3225), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(n945),
.CK(clk), .RN(n3225), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(n929),
.CK(clk), .RN(n3225), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(n941),
.CK(clk), .RN(n3224), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(n949),
.CK(clk), .RN(n3224), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(n937),
.CK(clk), .RN(n3224), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[8])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1149),
.CK(clk), .RN(n3197), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(n3178),
.CK(clk), .RN(n3223), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[6])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(n3179),
.CK(clk), .RN(n3223), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[5])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(n3177),
.CK(clk), .RN(n3223), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[4])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(n995),
.CK(clk), .RN(n3206), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[7])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1018),
.CK(clk), .RN(n3205), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[3])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1002),
.CK(clk), .RN(n3205), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[2])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(n981),
.CK(clk), .RN(n3207), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[1])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(n988),
.CK(clk), .RN(n3206), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[0])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1020), .CK(clk), .RN(n3215), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n983),
.CK(clk), .RN(n3215), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n990),
.CK(clk), .RN(n3215), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1004), .CK(clk), .RN(n3215), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1053),
.CK(clk), .RN(n3203), .Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT2)
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n962),
.CK(clk), .RN(n1920), .Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT2)
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1114),
.CK(clk), .RN(n3199), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1119),
.CK(clk), .RN(n3199), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1124),
.CK(clk), .RN(n3199), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1129),
.CK(clk), .RN(n3198), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1134),
.CK(clk), .RN(n3198), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1046),
.CK(clk), .RN(n1921), .Q(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT2) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(n953),
.CK(clk), .RN(n3224), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(n973),
.CK(clk), .RN(n3224), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[9])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1144),
.CK(clk), .RN(n3197), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(n893),
.CK(clk), .RN(n3226), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(n897),
.CK(clk), .RN(n3225), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(n3184),
.CK(clk), .RN(n3223), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[3])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(n3183),
.CK(clk), .RN(n3222), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[2])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(n3180),
.CK(clk), .RN(n3222), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[1])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(n3181),
.CK(clk), .RN(n3222), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[0])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(n894),
.CK(clk), .RN(n3212), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(n898),
.CK(clk), .RN(n3211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1051),
.CK(clk), .RN(n1919), .Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n958),
.CK(clk), .RN(n3202), .Q(zero_flag) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(
n1050), .CK(clk), .RN(n3212), .Q(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n959), .CK(clk), .RN(n3204), .Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1SHT2) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(
n1168), .CK(clk), .RN(n3196), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1047),
.CK(clk), .RN(n2084), .Q(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1054),
.CK(clk), .RN(n3202), .Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1)
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(
n1099), .CK(clk), .RN(n3216), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(
n1090), .CK(clk), .RN(n3216), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(
n1084), .CK(clk), .RN(n3216), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(
n1087), .CK(clk), .RN(n3216), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(
n1093), .CK(clk), .RN(n3216), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(
n1081), .CK(clk), .RN(n3216), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(
n1069), .CK(clk), .RN(n1921), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(
n1096), .CK(clk), .RN(n3216), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(
n1060), .CK(clk), .RN(n3204), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(
n1072), .CK(clk), .RN(n1919), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(
n1063), .CK(clk), .RN(n3208), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(
n1057), .CK(clk), .RN(n3203), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1075), .CK(clk), .RN(n3216), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1078), .CK(clk), .RN(n3215), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1115),
.CK(clk), .RN(n3199), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1120),
.CK(clk), .RN(n3199), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1125),
.CK(clk), .RN(n3198), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1130),
.CK(clk), .RN(n3198), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1135),
.CK(clk), .RN(n3198), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1145),
.CK(clk), .RN(n3197), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1140),
.CK(clk), .RN(n3198), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n963),
.CK(clk), .RN(n3208), .Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1)
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(n934),
.CK(clk), .RN(n3210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(n946),
.CK(clk), .RN(n3209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(n930),
.CK(clk), .RN(n3210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(n954),
.CK(clk), .RN(n3209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(n942),
.CK(clk), .RN(n3209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(n950),
.CK(clk), .RN(n3209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(n974),
.CK(clk), .RN(n3207), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[9])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(n938),
.CK(clk), .RN(n3209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[8])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(n926),
.CK(clk), .RN(n3210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[6])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(n967),
.CK(clk), .RN(n3207), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[5])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(n922),
.CK(clk), .RN(n3210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[4])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n976),
.CK(clk), .RN(n3207), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n969),
.CK(clk), .RN(n3215), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(n906),
.CK(clk), .RN(n3211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(n914),
.CK(clk), .RN(n3211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(n910),
.CK(clk), .RN(n3211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(n902),
.CK(clk), .RN(n3211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(n918),
.CK(clk), .RN(n3210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1045),
.CK(clk), .RN(n3219), .Q(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(
n1170), .CK(clk), .RN(n3196), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS reg_LUT_Q_reg_27_ ( .D(n1614), .CK(clk), .RN(n3260), .Q(
d_ff3_LUT_out[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n960),
.CK(clk), .RN(n3203), .Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_NRM) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1112),
.CK(clk), .RN(n3215), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1117),
.CK(clk), .RN(n3215), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(n1155),
.CK(clk), .RN(n3196), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[26]),
.QN(n3135) );
ADDFHX2TS DP_OP_33J115_122_2179_U4 ( .A(n3094), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[5]), .CI(
DP_OP_33J115_122_2179_n4), .CO(DP_OP_33J115_122_2179_n3), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[5]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1026), .CK(clk), .RN(n3219), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]),
.QN(n3107) );
ADDFHX2TS DP_OP_33J115_122_2179_U6 ( .A(DP_OP_33J115_122_2179_n15), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[3]), .CI(
DP_OP_33J115_122_2179_n6), .CO(DP_OP_33J115_122_2179_n5), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[3]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1007), .CK(clk), .RN(n3213), .Q(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[0])
);
DFFRX4TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(
n1557), .CK(clk), .RN(n3220), .Q(
inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .QN(n1637) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(n1623),
.CK(clk), .RN(n3227), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .QN(n1713) );
CMPR32X2TS DP_OP_33J115_122_2179_U2 ( .A(n3094), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[7]), .C(
DP_OP_33J115_122_2179_n2), .CO(DP_OP_33J115_122_2179_n1), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[7]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(n1621),
.CK(clk), .RN(n3226), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .QN(n1638) );
CMPR32X2TS intadd_356_U4 ( .A(d_ff2_Y[24]), .B(n3098), .C(intadd_356_CI),
.CO(intadd_356_n3), .S(intadd_356_SUM_0_) );
CMPR32X2TS intadd_357_U4 ( .A(d_ff2_X[24]), .B(n3098), .C(intadd_357_CI),
.CO(intadd_357_n3), .S(intadd_357_SUM_0_) );
CMPR32X2TS intadd_357_U3 ( .A(d_ff2_X[25]), .B(intadd_356_B_1_), .C(
intadd_357_n3), .CO(intadd_357_n2), .S(intadd_357_SUM_1_) );
CMPR32X2TS intadd_356_U3 ( .A(d_ff2_Y[25]), .B(intadd_356_B_1_), .C(
intadd_356_n3), .CO(intadd_356_n2), .S(intadd_356_SUM_1_) );
CMPR32X2TS intadd_357_U2 ( .A(d_ff2_X[26]), .B(n3072), .C(intadd_357_n2),
.CO(intadd_357_n1), .S(intadd_357_SUM_2_) );
CMPR32X2TS intadd_356_U2 ( .A(d_ff2_Y[26]), .B(n3072), .C(intadd_356_n2),
.CO(intadd_356_n1), .S(intadd_356_SUM_2_) );
AOI32X1TS U1643 ( .A0(n3072), .A1(n2842), .A2(n2835), .B0(d_ff3_LUT_out[26]),
.B1(n2834), .Y(n2837) );
AOI222X1TS U1644 ( .A0(n2123), .A1(d_ff2_Z[1]), .B0(n2108), .B1(d_ff1_Z[1]),
.C0(d_ff_Zn[1]), .C1(n2987), .Y(n2109) );
AOI222X1TS U1645 ( .A0(n2123), .A1(d_ff2_Z[3]), .B0(n2108), .B1(d_ff1_Z[3]),
.C0(d_ff_Zn[3]), .C1(n2987), .Y(n2110) );
AOI222X1TS U1646 ( .A0(n2986), .A1(d_ff2_Z[2]), .B0(n2108), .B1(d_ff1_Z[2]),
.C0(d_ff_Zn[2]), .C1(n2122), .Y(n2119) );
AOI222X1TS U1647 ( .A0(n2986), .A1(d_ff2_Z[12]), .B0(n2114), .B1(d_ff1_Z[12]), .C0(d_ff_Zn[12]), .C1(n2122), .Y(n2115) );
AOI222X1TS U1648 ( .A0(n2921), .A1(d_ff2_Z[10]), .B0(n2108), .B1(d_ff1_Z[10]), .C0(d_ff_Zn[10]), .C1(n2122), .Y(n2124) );
AOI222X1TS U1649 ( .A0(n2897), .A1(d_ff2_Z[11]), .B0(n2108), .B1(d_ff1_Z[11]), .C0(d_ff_Zn[11]), .C1(n2104), .Y(n2105) );
AOI222X1TS U1650 ( .A0(n2914), .A1(d_ff2_Z[8]), .B0(n2102), .B1(d_ff1_Z[8]),
.C0(d_ff_Zn[8]), .C1(n2122), .Y(n2117) );
AOI222X1TS U1651 ( .A0(n2871), .A1(d_ff2_Z[6]), .B0(n2102), .B1(d_ff1_Z[6]),
.C0(d_ff_Zn[6]), .C1(n2122), .Y(n2111) );
AOI222X1TS U1652 ( .A0(n2123), .A1(d_ff2_Z[4]), .B0(n2108), .B1(d_ff1_Z[4]),
.C0(d_ff_Zn[4]), .C1(n2122), .Y(n2118) );
AOI222X1TS U1653 ( .A0(n2112), .A1(d_ff2_Z[13]), .B0(n2114), .B1(d_ff1_Z[13]), .C0(d_ff_Zn[13]), .C1(n2122), .Y(n2113) );
AOI222X1TS U1654 ( .A0(n2112), .A1(d_ff2_Z[22]), .B0(n2134), .B1(d_ff1_Z[22]), .C0(d_ff_Zn[22]), .C1(n2104), .Y(n2103) );
AOI222X1TS U1655 ( .A0(n2112), .A1(d_ff2_Z[21]), .B0(n2114), .B1(d_ff1_Z[21]), .C0(d_ff_Zn[21]), .C1(n2104), .Y(n2101) );
AOI222X1TS U1656 ( .A0(n2112), .A1(d_ff2_Z[20]), .B0(n2114), .B1(d_ff1_Z[20]), .C0(d_ff_Zn[20]), .C1(n2104), .Y(n2100) );
AOI222X1TS U1657 ( .A0(n2112), .A1(d_ff2_Z[16]), .B0(n2114), .B1(d_ff1_Z[16]), .C0(d_ff_Zn[16]), .C1(n2104), .Y(n2099) );
AOI222X1TS U1658 ( .A0(n2112), .A1(d_ff2_Z[14]), .B0(n2114), .B1(d_ff1_Z[14]), .C0(d_ff_Zn[14]), .C1(n2104), .Y(n2098) );
AOI222X1TS U1659 ( .A0(n2112), .A1(d_ff2_Z[18]), .B0(n2114), .B1(d_ff1_Z[18]), .C0(d_ff_Zn[18]), .C1(n2104), .Y(n2097) );
AOI222X1TS U1660 ( .A0(n2112), .A1(d_ff2_Z[15]), .B0(n2114), .B1(d_ff1_Z[15]), .C0(d_ff_Zn[15]), .C1(n2104), .Y(n2096) );
AOI222X1TS U1661 ( .A0(n2112), .A1(d_ff2_Z[17]), .B0(n2114), .B1(d_ff1_Z[17]), .C0(d_ff_Zn[17]), .C1(n2104), .Y(n2095) );
AOI222X1TS U1662 ( .A0(n2986), .A1(d_ff2_Z[19]), .B0(n2114), .B1(d_ff1_Z[19]), .C0(d_ff_Zn[19]), .C1(n2104), .Y(n2094) );
AOI222X1TS U1663 ( .A0(n2135), .A1(d_ff2_Z[26]), .B0(n2134), .B1(d_ff1_Z[26]), .C0(d_ff_Zn[26]), .C1(n2133), .Y(n2136) );
AOI222X1TS U1664 ( .A0(n2135), .A1(d_ff2_Z[25]), .B0(n2134), .B1(d_ff1_Z[25]), .C0(d_ff_Zn[25]), .C1(n2133), .Y(n2127) );
AOI222X1TS U1665 ( .A0(n2135), .A1(d_ff2_Z[24]), .B0(n2134), .B1(d_ff1_Z[24]), .C0(d_ff_Zn[24]), .C1(n2133), .Y(n2130) );
AOI222X1TS U1666 ( .A0(n2135), .A1(d_ff2_Z[23]), .B0(n2134), .B1(d_ff1_Z[23]), .C0(d_ff_Zn[23]), .C1(n2133), .Y(n2132) );
AOI222X1TS U1667 ( .A0(n2135), .A1(d_ff2_Z[28]), .B0(n2134), .B1(d_ff1_Z[28]), .C0(d_ff_Zn[28]), .C1(n2133), .Y(n2129) );
AOI222X1TS U1668 ( .A0(n2921), .A1(d_ff2_Z[0]), .B0(n2133), .B1(d_ff_Zn[0]),
.C0(n2108), .C1(d_ff1_Z[0]), .Y(n2107) );
BUFX3TS U1669 ( .A(n1825), .Y(n2505) );
INVX2TS U1670 ( .A(n1642), .Y(n1690) );
INVX2TS U1671 ( .A(n1641), .Y(n1695) );
CLKBUFX2TS U1672 ( .A(n1823), .Y(n2475) );
AND2X2TS U1673 ( .A(n3012), .B(n1824), .Y(n1825) );
NAND2BX2TS U1674 ( .AN(n2264), .B(n2261), .Y(n3015) );
INVX2TS U1675 ( .A(n1687), .Y(n1688) );
AOI32X1TS U1676 ( .A0(n1822), .A1(n1821), .A2(n1820), .B0(n1819), .B1(n1822),
.Y(n1824) );
CLKBUFX2TS U1677 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(
n1674) );
INVX2TS U1678 ( .A(n3012), .Y(n2306) );
INVX4TS U1679 ( .A(n2875), .Y(n1687) );
INVX4TS U1680 ( .A(n2031), .Y(n2975) );
BUFX3TS U1681 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_6), .Y(
n3012) );
BUFX3TS U1682 ( .A(n2093), .Y(n2875) );
NAND4BX1TS U1683 ( .AN(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[4]),
.B(n2257), .C(n2301), .D(n2297), .Y(n2258) );
NAND2X2TS U1684 ( .A(n2092), .B(n2874), .Y(n2093) );
NAND4X1TS U1685 ( .A(inst_CORDIC_FSM_v3_state_reg[5]), .B(n1895), .C(n3077),
.D(n3101), .Y(n2814) );
NOR2X1TS U1686 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n2152) );
INVX2TS U1687 ( .A(n3054), .Y(n2330) );
BUFX3TS U1688 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n3054) );
OAI21XLTS U1689 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .A1(n3121),
.B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[0]), .Y(n1772) );
OAI21XLTS U1690 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .A1(n3111), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]), .Y(n1792) );
NOR2XLTS U1691 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[0]), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n2257) );
NOR2X1TS U1692 ( .A(n1644), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .Y(
n1842) );
NOR2X6TS U1693 ( .A(n1735), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n1725) );
CLKINVX3TS U1694 ( .A(n2377), .Y(n2361) );
OAI21X1TS U1695 ( .A0(n2773), .A1(n1828), .B0(n1827), .Y(n1923) );
NAND2X1TS U1696 ( .A(n2329), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n2333) );
OR3X1TS U1697 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .C(n3068), .Y(
n1636) );
NOR2XLTS U1698 ( .A(n1697), .B(n2570), .Y(n2557) );
INVX2TS U1699 ( .A(n1641), .Y(n1694) );
CLKINVX3TS U1700 ( .A(n2205), .Y(n2291) );
BUFX3TS U1701 ( .A(n2091), .Y(n2874) );
NOR2X1TS U1702 ( .A(n3015), .B(n3055), .Y(n3014) );
INVX1TS U1703 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(
n2522) );
OAI211XLTS U1704 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]),
.A1(n3168), .B0(n2303), .C0(n2295), .Y(n1161) );
OAI211XLTS U1705 ( .A0(n2391), .A1(n1671), .B0(n2390), .C0(n2389), .Y(n1317)
);
OAI211XLTS U1706 ( .A0(n2429), .A1(n1670), .B0(n2425), .C0(n2424), .Y(n1311)
);
OAI211XLTS U1707 ( .A0(n2345), .A1(n1642), .B0(n2322), .C0(n2321), .Y(n1298)
);
OAI211XLTS U1708 ( .A0(n2403), .A1(n1667), .B0(n2402), .C0(n2401), .Y(n1320)
);
OAI211XLTS U1709 ( .A0(n2983), .A1(n2494), .B0(n2240), .C0(n2247), .Y(n1367)
);
OAI211XLTS U1710 ( .A0(n2297), .A1(n3055), .B0(n2303), .C0(n2296), .Y(n1164)
);
OAI211XLTS U1711 ( .A0(n2442), .A1(n1666), .B0(n2441), .C0(n2440), .Y(n1312)
);
OAI21XLTS U1712 ( .A0(n2181), .A1(n2377), .B0(n2180), .Y(n1554) );
OAI211XLTS U1713 ( .A0(n2983), .A1(n3112), .B0(n2248), .C0(n2247), .Y(n1406)
);
OAI21XLTS U1714 ( .A0(n2181), .A1(n2824), .B0(n2179), .Y(n1023) );
INVX2TS U1715 ( .A(n3049), .Y(n1692) );
OAI211X1TS U1716 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]),
.A1(n3167), .B0(n2303), .C0(n2294), .Y(n1162) );
OAI211X1TS U1717 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]),
.A1(n3166), .B0(n2303), .C0(n2299), .Y(n1165) );
AO22X1TS U1718 ( .A0(n3016), .A1(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[7]), .B0(
result_add_subt[30]), .B1(n3055), .Y(n1159) );
INVX4TS U1719 ( .A(n2505), .Y(n3011) );
OAI21X1TS U1720 ( .A0(n2468), .A1(n3039), .B0(n2465), .Y(n2466) );
OAI2BB1X2TS U1721 ( .A0N(n1711), .A1N(n2264), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(n2265) );
INVX4TS U1722 ( .A(n1823), .Y(n3013) );
NAND3X1TS U1723 ( .A(n1725), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .C(n3096), .Y(n1726)
);
AO22X1TS U1724 ( .A0(n2989), .A1(n2883), .B0(n2988), .B1(d_ff3_sh_x_out[30]),
.Y(n1423) );
OAI21X1TS U1725 ( .A0(n2204), .A1(n2205), .B0(n2203), .Y(n1173) );
AO22X1TS U1726 ( .A0(n2980), .A1(n2942), .B0(n2979), .B1(d_ff3_sh_y_out[30]),
.Y(n1326) );
NOR2X1TS U1727 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .B(
n1735), .Y(n1739) );
INVX4TS U1728 ( .A(n2205), .Y(n2287) );
OAI21X1TS U1729 ( .A0(n2830), .A1(n2190), .B0(n2189), .Y(n1598) );
INVX4TS U1730 ( .A(n2253), .Y(n2079) );
INVX4TS U1731 ( .A(n2253), .Y(n2965) );
BUFX3TS U1732 ( .A(n2033), .Y(n2062) );
OAI211X1TS U1733 ( .A0(n2194), .A1(n2190), .B0(n2163), .C0(n2162), .Y(n1604)
);
OAI211X1TS U1734 ( .A0(n2194), .A1(n1635), .B0(n2193), .C0(n2192), .Y(n1599)
);
OAI211X1TS U1735 ( .A0(n2842), .A1(n3174), .B0(n2193), .C0(n2191), .Y(n1603)
);
OAI211X1TS U1736 ( .A0(n2842), .A1(n3175), .B0(n2187), .C0(n2843), .Y(n1607)
);
OAI211X1TS U1737 ( .A0(n2842), .A1(n3176), .B0(n2187), .C0(n2191), .Y(n1597)
);
INVX4TS U1738 ( .A(n2406), .Y(n2423) );
INVX4TS U1739 ( .A(n3037), .Y(n2558) );
INVX4TS U1740 ( .A(n2874), .Y(n2135) );
NAND3X1TS U1741 ( .A(n2813), .B(n2826), .C(n3267), .Y(n2833) );
INVX4TS U1742 ( .A(n2947), .Y(n2349) );
OR2X2TS U1743 ( .A(cont_iter_out[1]), .B(n2840), .Y(n1635) );
OAI211X1TS U1744 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]), .A1(n3122), .B0(n1785), .C0(n1788), .Y(n1767) );
NAND2BX1TS U1745 ( .AN(d_ff3_LUT_out[27]), .B(n2866), .Y(n1614) );
NOR2X1TS U1746 ( .A(n1717), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]), .Y(n1721) );
NOR2X1TS U1747 ( .A(n1783), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]),
.Y(n1784) );
NOR2X1TS U1748 ( .A(n1817), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]),
.Y(n1754) );
INVX4TS U1749 ( .A(n2830), .Y(intadd_356_B_1_) );
INVX4TS U1750 ( .A(n2196), .Y(n2827) );
INVX4TS U1751 ( .A(n1712), .Y(n2830) );
OAI211X1TS U1752 ( .A0(n2435), .A1(n1667), .B0(n2408), .C0(n2407), .Y(n1308)
);
OAI211X1TS U1753 ( .A0(n2396), .A1(n1671), .B0(n2395), .C0(n2394), .Y(n1303)
);
OAI21X1TS U1754 ( .A0(n2305), .A1(n1671), .B0(n2304), .Y(n1322) );
OAI211X1TS U1755 ( .A0(n2380), .A1(n1671), .B0(n2379), .C0(n2378), .Y(n1305)
);
OAI211X1TS U1756 ( .A0(n2386), .A1(n1670), .B0(n2385), .C0(n2384), .Y(n1301)
);
OAI211X1TS U1757 ( .A0(n2356), .A1(n1671), .B0(n2351), .C0(n2350), .Y(n1315)
);
OAI211X1TS U1758 ( .A0(n2345), .A1(n1671), .B0(n2341), .C0(n2340), .Y(n1300)
);
OAI211X1TS U1759 ( .A0(n2356), .A1(n1667), .B0(n2355), .C0(n2354), .Y(n1314)
);
OAI211X1TS U1760 ( .A0(n2374), .A1(n1671), .B0(n2373), .C0(n2372), .Y(n1319)
);
OAI211X1TS U1761 ( .A0(n2345), .A1(n1667), .B0(n2344), .C0(n2343), .Y(n1299)
);
OAI211X1TS U1762 ( .A0(n2416), .A1(n1671), .B0(n2410), .C0(n2409), .Y(n1307)
);
OAI211X1TS U1763 ( .A0(n2435), .A1(n1671), .B0(n2433), .C0(n2432), .Y(n1309)
);
OAI211X1TS U1764 ( .A0(n2380), .A1(n1667), .B0(n2365), .C0(n2364), .Y(n1304)
);
OAI211X1TS U1765 ( .A0(n2391), .A1(n1667), .B0(n2335), .C0(n2334), .Y(n1316)
);
OAI211X1TS U1766 ( .A0(n2416), .A1(n1666), .B0(n2415), .C0(n2414), .Y(n1306)
);
OAI211X1TS U1767 ( .A0(n2374), .A1(n1667), .B0(n2368), .C0(n2367), .Y(n1318)
);
OAI211X1TS U1768 ( .A0(n2396), .A1(n1667), .B0(n2370), .C0(n2369), .Y(n1302)
);
INVX4TS U1769 ( .A(n1672), .Y(n1665) );
INVX2TS U1770 ( .A(n2327), .Y(n2434) );
INVX2TS U1771 ( .A(n1751), .Y(n1672) );
OAI21X1TS U1772 ( .A0(n2330), .A1(n2146), .B0(n2145), .Y(n1011) );
OAI211X2TS U1773 ( .A0(n1743), .A1(n1742), .B0(n1741), .C0(n2149), .Y(n2517)
);
OAI21X1TS U1774 ( .A0(n2146), .A1(n2377), .B0(n2144), .Y(n1556) );
OAI21X1TS U1775 ( .A0(n2160), .A1(n2377), .B0(n2159), .Y(n1555) );
OAI21X1TS U1776 ( .A0(n2160), .A1(n2824), .B0(n2158), .Y(n1015) );
OAI211X1TS U1777 ( .A0(n1684), .A1(n3169), .B0(n2303), .C0(n2302), .Y(n1160)
);
OAI211X1TS U1778 ( .A0(n2301), .A1(n3055), .B0(n2303), .C0(n2300), .Y(n1163)
);
OAI211X1TS U1779 ( .A0(n1684), .A1(n3165), .B0(n2303), .C0(n2298), .Y(n1166)
);
OAI21X1TS U1780 ( .A0(n3080), .A1(n2465), .B0(n2460), .Y(n1100) );
OAI21X1TS U1781 ( .A0(n3124), .A1(n2463), .B0(n2452), .Y(n1091) );
NAND2X6TS U1782 ( .A(n3016), .B(n3015), .Y(n3049) );
OAI21X1TS U1783 ( .A0(n2511), .A1(n3011), .B0(n2510), .Y(n1106) );
OAI21X1TS U1784 ( .A0(n2266), .A1(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(n3016), .Y(n2267)
);
OAI211X1TS U1785 ( .A0(n2253), .A1(n2451), .B0(n2230), .C0(n2231), .Y(n1358)
);
OAI211X1TS U1786 ( .A0(n2253), .A1(n2511), .B0(n2242), .C0(n2241), .Y(n1331)
);
OAI211X1TS U1787 ( .A0(n2253), .A1(n2225), .B0(n2224), .C0(n2238), .Y(n1361)
);
OAI211X1TS U1788 ( .A0(n2253), .A1(n2233), .B0(n2232), .C0(n2231), .Y(n1349)
);
OAI21X1TS U1789 ( .A0(n3079), .A1(n2501), .B0(n2470), .Y(n903) );
OAI21X1TS U1790 ( .A0(n3124), .A1(n3013), .B0(n2472), .Y(n907) );
OAI21X1TS U1791 ( .A0(n3116), .A1(n2499), .B0(n2487), .Y(n911) );
OAI21X1TS U1792 ( .A0(n2494), .A1(n2499), .B0(n2493), .Y(n935) );
OAI21X1TS U1793 ( .A0(n3122), .A1(n2499), .B0(n2498), .Y(n939) );
OAI21X1TS U1794 ( .A0(n3113), .A1(n2501), .B0(n2471), .Y(n943) );
OAI211X1TS U1795 ( .A0(n2253), .A1(n1656), .B0(n2234), .C0(n2241), .Y(n1329)
);
OAI21X1TS U1796 ( .A0(n2253), .A1(n3140), .B0(n2210), .Y(n1325) );
OAI21X1TS U1797 ( .A0(n3126), .A1(n3011), .B0(n2506), .Y(n968) );
OAI21X1TS U1798 ( .A0(n2511), .A1(n2501), .B0(n2500), .Y(n1154) );
OAI21X1TS U1799 ( .A0(n3103), .A1(n3011), .B0(n2508), .Y(n970) );
OAI21X1TS U1800 ( .A0(n3110), .A1(n2499), .B0(n2477), .Y(n915) );
OAI211X1TS U1801 ( .A0(n2983), .A1(n3111), .B0(n2246), .C0(n2251), .Y(n1370)
);
OAI211X1TS U1802 ( .A0(n2983), .A1(n1699), .B0(n2236), .C0(n2235), .Y(n1394)
);
OAI21X1TS U1803 ( .A0(n3123), .A1(n3011), .B0(n2509), .Y(n977) );
OAI21X1TS U1804 ( .A0(n2489), .A1(n2463), .B0(n2459), .Y(n1073) );
OAI21X1TS U1805 ( .A0(n1656), .A1(n3013), .B0(n2464), .Y(n1153) );
OAI211X1TS U1806 ( .A0(n2253), .A1(n3110), .B0(n2252), .C0(n2251), .Y(n1355)
);
OAI21X1TS U1807 ( .A0(n1655), .A1(n2504), .B0(n2483), .Y(n1003) );
NAND2X6TS U1808 ( .A(n2173), .B(n3092), .Y(n2140) );
OAI211X1TS U1809 ( .A0(n2983), .A1(n3103), .B0(n2245), .C0(n2244), .Y(n1400)
);
OAI21X1TS U1810 ( .A0(n2482), .A1(n2504), .B0(n2481), .Y(n982) );
OAI211X1TS U1811 ( .A0(n2253), .A1(n2229), .B0(n2228), .C0(n2241), .Y(n1327)
);
OAI21X1TS U1812 ( .A0(n1653), .A1(n2463), .B0(n2444), .Y(n1076) );
OAI21X1TS U1813 ( .A0(n1640), .A1(n2463), .B0(n2446), .Y(n1079) );
OAI21X1TS U1814 ( .A0(n3140), .A1(n2499), .B0(n2478), .Y(n1151) );
OAI21X1TS U1815 ( .A0(n2494), .A1(n2463), .B0(n2454), .Y(n1070) );
OAI21X1TS U1816 ( .A0(n3113), .A1(n2457), .B0(n1892), .Y(n1064) );
OAI21X1TS U1817 ( .A0(n3120), .A1(n2504), .B0(n2480), .Y(n989) );
OAI21X1TS U1818 ( .A0(n1699), .A1(n2504), .B0(n2492), .Y(n996) );
OAI21X1TS U1819 ( .A0(n3112), .A1(n2504), .B0(n2503), .Y(n1019) );
AO22XLTS U1820 ( .A0(n2987), .A1(d_ff_Yn[24]), .B0(d_ff2_Y[24]), .B1(n2986),
.Y(n1347) );
AO22XLTS U1821 ( .A0(n2987), .A1(d_ff_Yn[30]), .B0(d_ff2_Y[30]), .B1(n2986),
.Y(n1341) );
OAI21X1TS U1822 ( .A0(n1699), .A1(n2457), .B0(n2310), .Y(n998) );
AOI222X1TS U1823 ( .A0(n2135), .A1(d_ff2_Z[31]), .B0(n2134), .B1(d_ff1_Z[31]), .C0(d_ff_Zn[31]), .C1(n2133), .Y(n2128) );
OAI21X1TS U1824 ( .A0(n1655), .A1(n2457), .B0(n2309), .Y(n1005) );
OAI21X1TS U1825 ( .A0(n3120), .A1(n2457), .B0(n2307), .Y(n991) );
OAI21X1TS U1826 ( .A0(n2482), .A1(n2457), .B0(n2308), .Y(n984) );
AO22XLTS U1827 ( .A0(n2922), .A1(d_ff_Xn[18]), .B0(d_ff2_X[18]), .B1(n2986),
.Y(n1448) );
AO22XLTS U1828 ( .A0(n2913), .A1(d_ff_Yn[8]), .B0(d_ff2_Y[8]), .B1(n2986),
.Y(n1393) );
INVX2TS U1829 ( .A(n1825), .Y(n2457) );
INVX2TS U1830 ( .A(n1825), .Y(n2463) );
AO22XLTS U1831 ( .A0(n2906), .A1(d_ff_Xn[30]), .B0(d_ff2_X[30]), .B1(n2986),
.Y(n1431) );
NOR2X1TS U1832 ( .A(n2258), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(n2259) );
BUFX3TS U1833 ( .A(n2062), .Y(n2209) );
INVX4TS U1834 ( .A(n1688), .Y(n2906) );
AO22XLTS U1835 ( .A0(n1687), .A1(d_ff_Yn[2]), .B0(d_ff2_Y[2]), .B1(n2986),
.Y(n1411) );
AO22XLTS U1836 ( .A0(n1687), .A1(d_ff_Xn[31]), .B0(d_ff2_X[31]), .B1(n2986),
.Y(n1422) );
NOR2X1TS U1837 ( .A(n1696), .B(n2570), .Y(n2564) );
OAI21X1TS U1838 ( .A0(n1799), .A1(n1798), .B0(n1797), .Y(n1800) );
OAI21X1TS U1839 ( .A0(intadd_356_B_1_), .A1(n2836), .B0(n2170), .Y(n1596) );
OAI21X1TS U1840 ( .A0(n2834), .A1(n2161), .B0(n2088), .Y(n1610) );
NOR2X1TS U1841 ( .A(n1647), .B(n2570), .Y(n2535) );
NOR2X1TS U1842 ( .A(n2593), .B(n2570), .Y(n2567) );
NOR2X1TS U1843 ( .A(n2598), .B(n2570), .Y(n2561) );
INVX2TS U1844 ( .A(n2534), .Y(n2572) );
NOR2X1TS U1845 ( .A(n2588), .B(n2570), .Y(n2571) );
NOR2X1TS U1846 ( .A(n1703), .B(n2570), .Y(n2544) );
NOR2X1TS U1847 ( .A(n1719), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n1720) );
NOR2X1TS U1848 ( .A(n2609), .B(n2570), .Y(n2539) );
NOR2X1TS U1849 ( .A(n2603), .B(n2570), .Y(n2554) );
NOR2X4TS U1850 ( .A(n2802), .B(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG), .Y(
n1944) );
OAI21X1TS U1851 ( .A0(n2834), .A1(intadd_356_CI), .B0(n2085), .Y(n1340) );
OAI21X1TS U1852 ( .A0(n2834), .A1(intadd_357_CI), .B0(n2086), .Y(n1430) );
AOI211X1TS U1853 ( .A0(n1796), .A1(n1795), .B0(n1794), .C0(n1793), .Y(n1797)
);
NOR2X1TS U1854 ( .A(n1696), .B(n2617), .Y(n2596) );
INVX2TS U1855 ( .A(n2915), .Y(n2123) );
INVX3TS U1856 ( .A(n2938), .Y(n2834) );
INVX3TS U1857 ( .A(n2315), .Y(n2421) );
NOR2X1TS U1858 ( .A(n1697), .B(n2617), .Y(n2601) );
NOR2X1TS U1859 ( .A(n1703), .B(n2617), .Y(n2607) );
NOR2X1TS U1860 ( .A(n2609), .B(n2617), .Y(n2610) );
NOR2X1TS U1861 ( .A(n2593), .B(n2617), .Y(n2594) );
NOR2X1TS U1862 ( .A(n2598), .B(n2617), .Y(n2599) );
NOR2X1TS U1863 ( .A(n2603), .B(n2617), .Y(n2604) );
NOR2X1TS U1864 ( .A(n2588), .B(n2617), .Y(n2591) );
AND2X4TS U1865 ( .A(n2167), .B(n2819), .Y(n2031) );
NAND4XLTS U1866 ( .A(n2008), .B(n2007), .C(n2006), .D(n2005), .Y(n2027) );
AND2X2TS U1867 ( .A(n1674), .B(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG), .Y(
n2702) );
NOR2X4TS U1868 ( .A(n2522), .B(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(n2524) );
NAND4XLTS U1869 ( .A(n2016), .B(n2015), .C(n2014), .D(n2013), .Y(n2026) );
AOI21X2TS U1870 ( .A0(n1923), .A1(n1832), .B0(n1831), .Y(n1934) );
AOI21X2TS U1871 ( .A0(n2553), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]), .B0(n2543), .Y(n1647)
);
INVX2TS U1872 ( .A(n2856), .Y(n2858) );
AOI31X2TS U1873 ( .A0(n2827), .A1(n3072), .A2(intadd_356_B_1_), .B0(n2195),
.Y(n2839) );
AOI32X2TS U1874 ( .A0(n2830), .A1(n2842), .A2(n3072), .B0(n2183), .B1(n2842),
.Y(n2187) );
OR2X2TS U1875 ( .A(n2357), .B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM),
.Y(n2315) );
CLKAND2X4TS U1876 ( .A(n2590), .B(n1686), .Y(n2618) );
NAND4XLTS U1877 ( .A(n2000), .B(n1999), .C(n1998), .D(n1997), .Y(n2028) );
AOI211X1TS U1878 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .A1(
n3100), .B0(n1761), .C0(n1759), .Y(n1816) );
OAI211X2TS U1879 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .A1(
n3110), .B0(n1814), .C0(n1764), .Y(n1808) );
OR2X2TS U1880 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .B(
n2551), .Y(n1909) );
AOI32X2TS U1881 ( .A0(n2196), .A1(n3072), .A2(intadd_356_B_1_), .B0(n2830),
.B1(cont_iter_out[3]), .Y(n2841) );
BUFX3TS U1882 ( .A(n2861), .Y(n2856) );
NAND3X1TS U1883 ( .A(n3117), .B(n1755), .C(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[26]), .Y(n1757) );
OAI211X2TS U1884 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .A1(
n3119), .B0(n1796), .C0(n1766), .Y(n1790) );
INVX1TS U1885 ( .A(n2812), .Y(n1898) );
OAI21X1TS U1886 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .A1(n3125), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]), .Y(n1810) );
NAND2BX1TS U1887 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .Y(n1755) );
NAND2BX1TS U1888 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .Y(n1764) );
NAND2BX1TS U1889 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .Y(n1785) );
NAND2BX1TS U1890 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .Y(n1756) );
NAND2BX1TS U1891 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .Y(n1766) );
NAND2BX1TS U1892 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .Y(n1805) );
OR3X2TS U1893 ( .A(cont_var_out[0]), .B(cont_var_out[1]), .C(n3267), .Y(
n2855) );
CLKINVX2TS U1894 ( .A(n1633), .Y(n1700) );
NAND2BX1TS U1895 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .Y(n1815) );
CLKBUFX2TS U1896 ( .A(n1633), .Y(n1699) );
OAI2BB1X2TS U1897 ( .A0N(n2701), .A1N(n1891), .B0(n1890), .Y(n1103) );
AOI22X2TS U1898 ( .A0(n1889), .A1(n1944), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]), .B1(n2822), .Y(
n1890) );
AOI21X2TS U1899 ( .A0(n1904), .A1(n1900), .B0(n1888), .Y(n1893) );
XNOR2X2TS U1900 ( .A(DP_OP_33J115_122_2179_n1), .B(
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2264) );
NOR2X4TS U1901 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n1730) );
OAI21X2TS U1902 ( .A0(n2678), .A1(n2672), .B0(n2673), .Y(n2687) );
OAI21X1TS U1903 ( .A0(n2659), .A1(n2653), .B0(n2654), .Y(n1904) );
OAI21X4TS U1904 ( .A0(n2630), .A1(n2624), .B0(n2625), .Y(n2639) );
OAI21X2TS U1905 ( .A0(n1842), .A1(n2748), .B0(n1841), .Y(n2733) );
NAND2X1TS U1906 ( .A(n3153), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .Y(
n2748) );
OAI21X2TS U1907 ( .A0(n2657), .A1(n1869), .B0(n1868), .Y(n1902) );
AOI21X4TS U1908 ( .A0(n2666), .A1(n1867), .B0(n1866), .Y(n2657) );
CLKINVX12TS U1909 ( .A(n2140), .Y(n2178) );
OAI211X1TS U1910 ( .A0(n2429), .A1(n1666), .B0(n2428), .C0(n2427), .Y(n1310)
);
OAI21X2TS U1911 ( .A0(n2676), .A1(n1861), .B0(n1860), .Y(n2685) );
AOI21X4TS U1912 ( .A0(n2706), .A1(n1859), .B0(n1858), .Y(n2676) );
OAI21X2TS U1913 ( .A0(n2695), .A1(n1865), .B0(n1864), .Y(n2666) );
AOI21X4TS U1914 ( .A0(n2685), .A1(n1863), .B0(n1862), .Y(n2695) );
OAI21X2TS U1915 ( .A0(n2725), .A1(n1849), .B0(n1848), .Y(n2715) );
AOI21X2TS U1916 ( .A0(n2731), .A1(n1847), .B0(n1846), .Y(n2725) );
OAI21X2TS U1917 ( .A0(n2628), .A1(n1853), .B0(n1852), .Y(n2637) );
AOI21X4TS U1918 ( .A0(n2715), .A1(n1851), .B0(n1850), .Y(n2628) );
OAI21X4TS U1919 ( .A0(n2697), .A1(n2691), .B0(n2692), .Y(n2668) );
AOI21X4TS U1920 ( .A0(n2687), .A1(n2683), .B0(n1886), .Y(n2697) );
OAI21X4TS U1921 ( .A0(n2649), .A1(n2643), .B0(n2644), .Y(n2708) );
AOI21X4TS U1922 ( .A0(n2639), .A1(n2635), .B0(n1884), .Y(n2649) );
OAI21X4TS U1923 ( .A0(n1955), .A1(n1878), .B0(n1877), .Y(n2740) );
AOI21X2TS U1924 ( .A0(n1929), .A1(n1874), .B0(n1873), .Y(n1955) );
OAI21X2TS U1925 ( .A0(n2647), .A1(n1857), .B0(n1856), .Y(n2706) );
AOI21X4TS U1926 ( .A0(n2637), .A1(n1855), .B0(n1854), .Y(n2647) );
NOR2X1TS U1927 ( .A(n1925), .B(n1830), .Y(n1832) );
OAI21X1TS U1928 ( .A0(n1830), .A1(n1924), .B0(n1829), .Y(n1831) );
NAND2X1TS U1929 ( .A(n3156), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .Y(
n1924) );
NOR2X1TS U1930 ( .A(n3145), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .Y(
n1830) );
AOI21X2TS U1931 ( .A0(n1902), .A1(n1871), .B0(n1870), .Y(n1872) );
CLKAND2X2TS U1932 ( .A(n3163), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]),
.Y(n1850) );
OR2X1TS U1933 ( .A(n3163), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]), .Y(
n1851) );
CLKAND2X2TS U1934 ( .A(n3159), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]),
.Y(n1866) );
CLKAND2X2TS U1935 ( .A(n3161), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]),
.Y(n1858) );
AOI2BB2XLTS U1936 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .B1(
n3112), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .A1N(n1775),
.Y(n1776) );
AOI21X2TS U1937 ( .A0(n2717), .A1(n2713), .B0(n1883), .Y(n2630) );
AOI21X2TS U1938 ( .A0(n2668), .A1(n2664), .B0(n1887), .Y(n2659) );
AOI21X2TS U1939 ( .A0(n2708), .A1(n2704), .B0(n1885), .Y(n2678) );
CLKAND2X2TS U1940 ( .A(n3160), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]),
.Y(n1862) );
CLKAND2X2TS U1941 ( .A(n3162), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]),
.Y(n1854) );
NAND2BXLTS U1942 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .Y(n1787) );
NAND3XLTS U1943 ( .A(n3122), .B(n1785), .C(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]), .Y(n1786) );
OAI2BB2XLTS U1944 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .B1(
n1782), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .A1N(n3114),
.Y(n1795) );
OAI2BB2XLTS U1945 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .B1(
n1792), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .A1N(n3111),
.Y(n1793) );
OAI2BB2XLTS U1946 ( .B0(n1791), .B1(n1790), .A0N(n1789), .A1N(n1788), .Y(
n1794) );
OAI32X1TS U1947 ( .A0(n1781), .A1(n1780), .A2(n1779), .B0(n1778), .B1(n1780),
.Y(n1798) );
INVX2TS U1948 ( .A(n1769), .Y(n1799) );
NOR2BX1TS U1949 ( .AN(n1768), .B(n1767), .Y(n1769) );
INVX2TS U1950 ( .A(n1790), .Y(n1768) );
AOI2BB1XLTS U1951 ( .A0N(n1716), .A1N(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n1717) );
AOI2BB1XLTS U1952 ( .A0N(n3107), .A1N(n1722), .B0(n1718), .Y(n1719) );
NOR3XLTS U1953 ( .A(n2150), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]), .C(n3091), .Y(n1718) );
AOI211X2TS U1954 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]), .A1(
n2547), .B0(n2531), .C0(n2530), .Y(n2593) );
OAI211X1TS U1955 ( .A0(n2606), .A1(n1668), .B0(n2560), .C0(n2559), .Y(n2600)
);
AO21XLTS U1956 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]), .A1(
n2547), .B0(n2546), .Y(n1650) );
NOR2X1TS U1957 ( .A(n2749), .B(n1842), .Y(n2732) );
AOI2BB2X1TS U1958 ( .B0(n1763), .B1(n1816), .A0N(n1762), .A1N(n1761), .Y(
n1822) );
INVX2TS U1959 ( .A(n3185), .Y(n2196) );
NOR2BX2TS U1960 ( .AN(n2200), .B(n2216), .Y(n2255) );
INVX2TS U1961 ( .A(n2721), .Y(n2723) );
INVX2TS U1962 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[0]), .Y(
n2767) );
BUFX3TS U1963 ( .A(n1825), .Y(n2514) );
BUFX3TS U1964 ( .A(n1825), .Y(n2496) );
NOR2XLTS U1965 ( .A(n3146), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]), .Y(
n1869) );
NOR2XLTS U1966 ( .A(n3147), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]), .Y(
n1865) );
NOR2XLTS U1967 ( .A(n3148), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]), .Y(
n1861) );
INVX2TS U1968 ( .A(n2475), .Y(n2504) );
NOR2XLTS U1969 ( .A(n3149), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]), .Y(
n1857) );
NOR2XLTS U1970 ( .A(n3150), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]), .Y(
n1853) );
NOR2XLTS U1971 ( .A(n3151), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]), .Y(
n1849) );
OAI21XLTS U1972 ( .A0(n2799), .A1(n2798), .B0(n2797), .Y(n2801) );
BUFX3TS U1973 ( .A(n1823), .Y(n2458) );
BUFX3TS U1974 ( .A(n2475), .Y(n2513) );
INVX2TS U1975 ( .A(n2475), .Y(n2499) );
OAI211XLTS U1976 ( .A0(n2031), .A1(n2227), .B0(n2226), .C0(n2251), .Y(n1364)
);
AO22XLTS U1977 ( .A0(n2987), .A1(d_ff_Yn[27]), .B0(d_ff2_Y[27]), .B1(n2897),
.Y(n1344) );
OAI222X1TS U1978 ( .A0(n3011), .A1(n3087), .B0(n3135), .B1(n3012), .C0(n3117), .C1(n3013), .Y(n1155) );
AO22XLTS U1979 ( .A0(n2987), .A1(d_ff_Yn[29]), .B0(d_ff2_Y[29]), .B1(n2123),
.Y(n1342) );
AO21XLTS U1980 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[25]), .A1(
n2558), .B0(n2529), .Y(n866) );
AOI2BB2XLTS U1981 ( .B0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .B1(
n2621), .A0N(n2616), .A1N(n2570), .Y(n2528) );
NAND2BXLTS U1982 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .Y(n1773) );
NAND2X1TS U1983 ( .A(n1801), .B(n1800), .Y(n1821) );
NOR2BX1TS U1984 ( .AN(n1765), .B(n1803), .Y(n1801) );
NAND2X4TS U1985 ( .A(n1740), .B(n3091), .Y(n2137) );
OAI21XLTS U1986 ( .A0(n1836), .A1(n1963), .B0(n1835), .Y(n1837) );
INVX2TS U1987 ( .A(n1659), .Y(n1660) );
AO21XLTS U1988 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]), .A1(
n2547), .B0(n2536), .Y(n1651) );
INVX2TS U1989 ( .A(n2740), .Y(n2786) );
AOI21X1TS U1990 ( .A0(n2733), .A1(n1710), .B0(n1843), .Y(n2777) );
CLKAND2X2TS U1991 ( .A(n1707), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]),
.Y(n1843) );
OR2X1TS U1992 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n2664) );
NOR3X2TS U1993 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .C(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n2138) );
NOR2X1TS U1994 ( .A(n1715), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]), .Y(n2151) );
OR2X1TS U1995 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n2704) );
OR2X1TS U1996 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[14]), .Y(n2713) );
OAI21X1TS U1997 ( .A0(n2727), .A1(n2721), .B0(n2722), .Y(n2717) );
OR2X1TS U1998 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[24]), .Y(n1900) );
NAND4XLTS U1999 ( .A(n2024), .B(n2023), .C(n2022), .D(n2021), .Y(n2025) );
INVX2TS U2000 ( .A(n2855), .Y(n2854) );
AND3X1TS U2001 ( .A(n2313), .B(n2312), .C(n2311), .Y(n2345) );
OAI21XLTS U2002 ( .A0(n2796), .A1(n2749), .B0(n2748), .Y(n2753) );
OAI21XLTS U2003 ( .A0(n2762), .A1(n1925), .B0(n1924), .Y(n1928) );
NAND3XLTS U2004 ( .A(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
n3266), .C(n1643), .Y(n2817) );
INVX2TS U2005 ( .A(n1665), .Y(n1666) );
INVX2TS U2006 ( .A(n1641), .Y(n1693) );
INVX2TS U2007 ( .A(n2809), .Y(n2818) );
BUFX3TS U2008 ( .A(n2063), .Y(n2972) );
BUFX3TS U2009 ( .A(n2066), .Y(n2971) );
AOI31X1TS U2010 ( .A0(n1727), .A1(n2143), .A2(n1726), .B0(n2821), .Y(n2808)
);
BUFX3TS U2011 ( .A(n2243), .Y(n2961) );
BUFX3TS U2012 ( .A(n2209), .Y(n2931) );
BUFX3TS U2013 ( .A(n2066), .Y(n2930) );
NOR2X1TS U2014 ( .A(n2826), .B(n2815), .Y(n2197) );
OAI21XLTS U2015 ( .A0(n2786), .A1(n2741), .B0(n2750), .Y(n2743) );
INVX2TS U2016 ( .A(n2732), .Y(n2735) );
OAI21XLTS U2017 ( .A0(n2786), .A1(n2785), .B0(n2784), .Y(n2788) );
INVX2TS U2018 ( .A(n2779), .Y(n2781) );
NAND2X1TS U2019 ( .A(n1705), .B(n2590), .Y(n2534) );
OAI21XLTS U2020 ( .A0(n1978), .A1(n1964), .B0(n1963), .Y(n1967) );
INVX2TS U2021 ( .A(n1734), .Y(n1742) );
AOI211X1TS U2022 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]),
.A1(n1739), .B0(n1738), .C0(n2177), .Y(n1741) );
NAND3X1TS U2023 ( .A(cont_iter_out[1]), .B(n2196), .C(n2195), .Y(n2815) );
INVX2TS U2024 ( .A(n2828), .Y(n2826) );
AO22XLTS U2025 ( .A0(n2980), .A1(d_ff2_Z[31]), .B0(n2840), .B1(
d_ff3_sign_out), .Y(n1213) );
AO22XLTS U2026 ( .A0(n2913), .A1(d_ff_Yn[9]), .B0(d_ff2_Y[9]), .B1(n2921),
.Y(n1390) );
AO22XLTS U2027 ( .A0(n1687), .A1(d_ff_Yn[0]), .B0(d_ff2_Y[0]), .B1(n2123),
.Y(n1417) );
AO22XLTS U2028 ( .A0(n2913), .A1(d_ff_Yn[7]), .B0(d_ff2_Y[7]), .B1(n2123),
.Y(n1396) );
AO22XLTS U2029 ( .A0(n2987), .A1(d_ff_Yn[31]), .B0(d_ff2_Y[31]), .B1(n2921),
.Y(n1209) );
AO22XLTS U2030 ( .A0(n2913), .A1(d_ff_Yn[11]), .B0(d_ff2_Y[11]), .B1(n2897),
.Y(n1384) );
AO22XLTS U2031 ( .A0(n2913), .A1(d_ff_Yn[13]), .B0(d_ff2_Y[13]), .B1(n2914),
.Y(n1378) );
AO22XLTS U2032 ( .A0(n2913), .A1(d_ff_Yn[6]), .B0(d_ff2_Y[6]), .B1(n2871),
.Y(n1399) );
AO22XLTS U2033 ( .A0(n2920), .A1(d_ff_Yn[17]), .B0(d_ff2_Y[17]), .B1(n2921),
.Y(n1366) );
AO22XLTS U2034 ( .A0(n2920), .A1(d_ff_Yn[20]), .B0(d_ff2_Y[20]), .B1(n2897),
.Y(n1357) );
AO22XLTS U2035 ( .A0(n2920), .A1(d_ff_Yn[21]), .B0(d_ff2_Y[21]), .B1(n2914),
.Y(n1354) );
AO22XLTS U2036 ( .A0(n2920), .A1(d_ff_Yn[15]), .B0(d_ff2_Y[15]), .B1(n2871),
.Y(n1372) );
OAI211XLTS U2037 ( .A0(n2031), .A1(n2223), .B0(n2222), .C0(n2235), .Y(n1382)
);
NOR2XLTS U2038 ( .A(n2617), .B(n1647), .Y(n2613) );
AO22XLTS U2039 ( .A0(n2983), .A1(n2982), .B0(n2981), .B1(
inst_FPU_PIPELINED_FPADDSUB_intAS), .Y(n1212) );
AOI2BB2XLTS U2040 ( .B0(cont_var_out[0]), .B1(d_ff3_sign_out), .A0N(
d_ff3_sign_out), .A1N(cont_var_out[0]), .Y(n2982) );
OAI21XLTS U2041 ( .A0(n2947), .A1(n1649), .B0(n2423), .Y(n1558) );
MX2X1TS U2042 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[8]), .S0(n3009), .Y(n936) );
AO22XLTS U2043 ( .A0(n2991), .A1(result_add_subt[23]), .B0(n2950), .B1(
d_ff_Xn[23]), .Y(n1295) );
AO22XLTS U2044 ( .A0(n2952), .A1(result_add_subt[20]), .B0(n2984), .B1(
d_ff_Yn[20]), .Y(n1492) );
AO22XLTS U2045 ( .A0(n2952), .A1(result_add_subt[19]), .B0(n2984), .B1(
d_ff_Yn[19]), .Y(n1495) );
AO22XLTS U2046 ( .A0(n2985), .A1(result_add_subt[21]), .B0(n2984), .B1(
d_ff_Yn[21]), .Y(n1489) );
AO22XLTS U2047 ( .A0(n2952), .A1(result_add_subt[18]), .B0(n2984), .B1(
d_ff_Yn[18]), .Y(n1498) );
AO22XLTS U2048 ( .A0(n2952), .A1(result_add_subt[15]), .B0(n2984), .B1(
d_ff_Yn[15]), .Y(n1507) );
AO22XLTS U2049 ( .A0(n2985), .A1(result_add_subt[22]), .B0(n2984), .B1(
d_ff_Yn[22]), .Y(n1486) );
AO22XLTS U2050 ( .A0(n2985), .A1(result_add_subt[30]), .B0(n2984), .B1(
d_ff_Yn[30]), .Y(n1211) );
AO22XLTS U2051 ( .A0(n2985), .A1(result_add_subt[29]), .B0(n2955), .B1(
d_ff_Yn[29]), .Y(n1278) );
AO22XLTS U2052 ( .A0(n2952), .A1(result_add_subt[26]), .B0(n2955), .B1(
d_ff_Yn[26]), .Y(n1287) );
AO22XLTS U2053 ( .A0(n2985), .A1(result_add_subt[25]), .B0(n2955), .B1(
d_ff_Yn[25]), .Y(n1290) );
AO22XLTS U2054 ( .A0(n2985), .A1(result_add_subt[24]), .B0(n2955), .B1(
d_ff_Yn[24]), .Y(n1293) );
AO22XLTS U2055 ( .A0(n2858), .A1(result_add_subt[4]), .B0(n2856), .B1(
d_ff_Yn[4]), .Y(n1540) );
AO22XLTS U2056 ( .A0(n2952), .A1(result_add_subt[17]), .B0(n2984), .B1(
d_ff_Yn[17]), .Y(n1501) );
AO22XLTS U2057 ( .A0(n2952), .A1(result_add_subt[13]), .B0(n2861), .B1(
d_ff_Yn[13]), .Y(n1513) );
AO22XLTS U2058 ( .A0(n2858), .A1(result_add_subt[6]), .B0(n2856), .B1(
d_ff_Yn[6]), .Y(n1534) );
AO22XLTS U2059 ( .A0(n2858), .A1(result_add_subt[8]), .B0(n2861), .B1(
d_ff_Yn[8]), .Y(n1528) );
AO22XLTS U2060 ( .A0(n2952), .A1(result_add_subt[16]), .B0(n2984), .B1(
d_ff_Yn[16]), .Y(n1504) );
AO22XLTS U2061 ( .A0(n2952), .A1(result_add_subt[14]), .B0(n2861), .B1(
d_ff_Yn[14]), .Y(n1510) );
AO22XLTS U2062 ( .A0(n2858), .A1(result_add_subt[11]), .B0(n2861), .B1(
d_ff_Yn[11]), .Y(n1519) );
AO22XLTS U2063 ( .A0(n2952), .A1(result_add_subt[12]), .B0(n2861), .B1(
d_ff_Yn[12]), .Y(n1516) );
AO22XLTS U2064 ( .A0(n2858), .A1(result_add_subt[10]), .B0(n2861), .B1(
d_ff_Yn[10]), .Y(n1522) );
AO22XLTS U2065 ( .A0(n2858), .A1(result_add_subt[2]), .B0(n2955), .B1(
d_ff_Yn[2]), .Y(n1546) );
AO22XLTS U2066 ( .A0(n2858), .A1(result_add_subt[3]), .B0(n2856), .B1(
d_ff_Yn[3]), .Y(n1543) );
AO22XLTS U2067 ( .A0(n2985), .A1(result_add_subt[0]), .B0(n2955), .B1(
d_ff_Yn[0]), .Y(n1552) );
AO22XLTS U2068 ( .A0(n2858), .A1(result_add_subt[7]), .B0(n2861), .B1(
d_ff_Yn[7]), .Y(n1531) );
AO22XLTS U2069 ( .A0(n2858), .A1(result_add_subt[9]), .B0(n2861), .B1(
d_ff_Yn[9]), .Y(n1525) );
AO22XLTS U2070 ( .A0(n2886), .A1(result_add_subt[1]), .B0(n2955), .B1(
d_ff_Yn[1]), .Y(n1549) );
AO22XLTS U2071 ( .A0(n2858), .A1(result_add_subt[5]), .B0(n2856), .B1(
d_ff_Yn[5]), .Y(n1537) );
AO22XLTS U2072 ( .A0(n2991), .A1(result_add_subt[27]), .B0(n2990), .B1(
d_ff_Xn[27]), .Y(n1283) );
AO22XLTS U2073 ( .A0(n2991), .A1(result_add_subt[22]), .B0(n2950), .B1(
d_ff_Xn[22]), .Y(n1485) );
AO22XLTS U2074 ( .A0(n2991), .A1(result_add_subt[30]), .B0(n2990), .B1(
d_ff_Xn[30]), .Y(n1210) );
AO22XLTS U2075 ( .A0(n2865), .A1(result_add_subt[18]), .B0(n2950), .B1(
d_ff_Xn[18]), .Y(n1497) );
AO22XLTS U2076 ( .A0(n2865), .A1(result_add_subt[15]), .B0(n2950), .B1(
d_ff_Xn[15]), .Y(n1506) );
AO22XLTS U2077 ( .A0(n2859), .A1(result_add_subt[4]), .B0(n2990), .B1(
d_ff_Xn[4]), .Y(n1539) );
AO22XLTS U2078 ( .A0(n2865), .A1(result_add_subt[21]), .B0(n2950), .B1(
d_ff_Xn[21]), .Y(n1488) );
AO22XLTS U2079 ( .A0(n2859), .A1(result_add_subt[11]), .B0(n2860), .B1(
d_ff_Xn[11]), .Y(n1518) );
AO22XLTS U2080 ( .A0(n2859), .A1(result_add_subt[8]), .B0(n2860), .B1(
d_ff_Xn[8]), .Y(n1527) );
AO22XLTS U2081 ( .A0(n2859), .A1(result_add_subt[9]), .B0(n2860), .B1(
d_ff_Xn[9]), .Y(n1524) );
AO22XLTS U2082 ( .A0(n2854), .A1(result_add_subt[0]), .B0(n2855), .B1(
d_ff_Xn[0]), .Y(n1551) );
AO22XLTS U2083 ( .A0(n2991), .A1(result_add_subt[25]), .B0(n2990), .B1(
d_ff_Xn[25]), .Y(n1289) );
AO22XLTS U2084 ( .A0(n2991), .A1(result_add_subt[24]), .B0(n2950), .B1(
d_ff_Xn[24]), .Y(n1292) );
AO22XLTS U2085 ( .A0(n2991), .A1(result_add_subt[29]), .B0(n2990), .B1(
d_ff_Xn[29]), .Y(n1277) );
AO22XLTS U2086 ( .A0(n2991), .A1(result_add_subt[26]), .B0(n2990), .B1(
d_ff_Xn[26]), .Y(n1286) );
AO22XLTS U2087 ( .A0(n2865), .A1(result_add_subt[20]), .B0(n2950), .B1(
d_ff_Xn[20]), .Y(n1491) );
AO22XLTS U2088 ( .A0(n2865), .A1(result_add_subt[19]), .B0(n2950), .B1(
d_ff_Xn[19]), .Y(n1494) );
AO22XLTS U2089 ( .A0(n2859), .A1(result_add_subt[6]), .B0(n2860), .B1(
d_ff_Xn[6]), .Y(n1533) );
AO22XLTS U2090 ( .A0(n2865), .A1(result_add_subt[17]), .B0(n2950), .B1(
d_ff_Xn[17]), .Y(n1500) );
AO22XLTS U2091 ( .A0(n2865), .A1(result_add_subt[16]), .B0(n2950), .B1(
d_ff_Xn[16]), .Y(n1503) );
AO22XLTS U2092 ( .A0(n2865), .A1(result_add_subt[13]), .B0(n2860), .B1(
d_ff_Xn[13]), .Y(n1512) );
AO22XLTS U2093 ( .A0(n2859), .A1(result_add_subt[10]), .B0(n2860), .B1(
d_ff_Xn[10]), .Y(n1521) );
AO22XLTS U2094 ( .A0(n2865), .A1(result_add_subt[14]), .B0(n2860), .B1(
d_ff_Xn[14]), .Y(n1509) );
AO22XLTS U2095 ( .A0(n2859), .A1(result_add_subt[3]), .B0(n2855), .B1(
d_ff_Xn[3]), .Y(n1542) );
AO22XLTS U2096 ( .A0(n2865), .A1(result_add_subt[12]), .B0(n2860), .B1(
d_ff_Xn[12]), .Y(n1515) );
AO22XLTS U2097 ( .A0(n2859), .A1(result_add_subt[7]), .B0(n2860), .B1(
d_ff_Xn[7]), .Y(n1530) );
AO22XLTS U2098 ( .A0(n2859), .A1(result_add_subt[2]), .B0(n2855), .B1(
d_ff_Xn[2]), .Y(n1545) );
AO22XLTS U2099 ( .A0(n2859), .A1(result_add_subt[5]), .B0(n2860), .B1(
d_ff_Xn[5]), .Y(n1536) );
AO22XLTS U2100 ( .A0(n2854), .A1(result_add_subt[1]), .B0(n2990), .B1(
d_ff_Xn[1]), .Y(n1548) );
AO22XLTS U2101 ( .A0(n2987), .A1(d_ff_Yn[25]), .B0(d_ff2_Y[25]), .B1(n2921),
.Y(n1346) );
AO22XLTS U2102 ( .A0(n2920), .A1(d_ff_Yn[23]), .B0(d_ff2_Y[23]), .B1(n2921),
.Y(n1348) );
MX2X1TS U2103 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[9]), .S0(n3009), .Y(n972) );
MX2X1TS U2104 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[0]), .S0(n3037), .Y(n986) );
MX2X1TS U2105 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[5]), .S0(n3009), .Y(n965) );
MX2X1TS U2106 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[6]), .S0(n3009), .Y(n924) );
MX2X1TS U2107 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[4]), .S0(n3009), .Y(n920) );
MX2X1TS U2108 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[3]), .S0(n3009), .Y(n1016)
);
MX2X1TS U2109 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[7]), .S0(n3009), .Y(n993) );
AO22XLTS U2110 ( .A0(n2985), .A1(result_add_subt[28]), .B0(n2955), .B1(
d_ff_Yn[28]), .Y(n1281) );
AO22XLTS U2111 ( .A0(n1687), .A1(d_ff_Xn[22]), .B0(d_ff2_X[22]), .B1(n2123),
.Y(n1440) );
AO22XLTS U2112 ( .A0(n2922), .A1(d_ff_Xn[15]), .B0(d_ff2_X[15]), .B1(n2123),
.Y(n1454) );
AO22XLTS U2113 ( .A0(n1687), .A1(d_ff_Xn[21]), .B0(d_ff2_X[21]), .B1(n2921),
.Y(n1442) );
AO22XLTS U2114 ( .A0(n1687), .A1(d_ff_Xn[4]), .B0(d_ff2_X[4]), .B1(n2921),
.Y(n1476) );
AO22XLTS U2115 ( .A0(n2922), .A1(d_ff_Xn[8]), .B0(d_ff2_X[8]), .B1(n2897),
.Y(n1468) );
AO22XLTS U2116 ( .A0(n2922), .A1(d_ff_Xn[11]), .B0(d_ff2_X[11]), .B1(n2871),
.Y(n1462) );
AO22XLTS U2117 ( .A0(n2987), .A1(d_ff_Xn[0]), .B0(d_ff2_X[0]), .B1(n2914),
.Y(n1484) );
AO22XLTS U2118 ( .A0(n2922), .A1(d_ff_Xn[9]), .B0(d_ff2_X[9]), .B1(n2914),
.Y(n1466) );
AO22XLTS U2119 ( .A0(n2985), .A1(result_add_subt[23]), .B0(n2984), .B1(
d_ff_Yn[23]), .Y(n1296) );
AO22XLTS U2120 ( .A0(n2985), .A1(result_add_subt[27]), .B0(n2955), .B1(
d_ff_Yn[27]), .Y(n1284) );
AO22XLTS U2121 ( .A0(n2920), .A1(d_ff_Yn[22]), .B0(d_ff2_Y[22]), .B1(n2123),
.Y(n1351) );
AO22XLTS U2122 ( .A0(n2920), .A1(d_ff_Yn[18]), .B0(d_ff2_Y[18]), .B1(n2914),
.Y(n1363) );
AO22XLTS U2123 ( .A0(n2920), .A1(d_ff_Yn[19]), .B0(d_ff2_Y[19]), .B1(n2871),
.Y(n1360) );
AO22XLTS U2124 ( .A0(n1687), .A1(d_ff_Yn[4]), .B0(d_ff2_Y[4]), .B1(n2914),
.Y(n1405) );
AO22XLTS U2125 ( .A0(n2920), .A1(d_ff_Yn[16]), .B0(d_ff2_Y[16]), .B1(n2897),
.Y(n1369) );
AO22XLTS U2126 ( .A0(n2913), .A1(d_ff_Yn[14]), .B0(d_ff2_Y[14]), .B1(n2871),
.Y(n1375) );
AO22XLTS U2127 ( .A0(n2920), .A1(d_ff_Yn[10]), .B0(d_ff2_Y[10]), .B1(n2897),
.Y(n1387) );
AO22XLTS U2128 ( .A0(n2913), .A1(d_ff_Yn[12]), .B0(d_ff2_Y[12]), .B1(n2914),
.Y(n1381) );
AO22XLTS U2129 ( .A0(n2913), .A1(d_ff_Yn[3]), .B0(d_ff2_Y[3]), .B1(n2897),
.Y(n1408) );
AO22XLTS U2130 ( .A0(n1687), .A1(d_ff_Yn[1]), .B0(d_ff2_Y[1]), .B1(n2921),
.Y(n1414) );
AO22XLTS U2131 ( .A0(n2913), .A1(d_ff_Yn[5]), .B0(d_ff2_Y[5]), .B1(n2871),
.Y(n1402) );
AO22XLTS U2132 ( .A0(n2991), .A1(result_add_subt[28]), .B0(n2990), .B1(
d_ff_Xn[28]), .Y(n1280) );
AO22XLTS U2133 ( .A0(n2987), .A1(d_ff_Yn[26]), .B0(d_ff2_Y[26]), .B1(n2871),
.Y(n1345) );
AO22XLTS U2134 ( .A0(n2922), .A1(d_ff_Xn[23]), .B0(d_ff2_X[23]), .B1(n2123),
.Y(n1438) );
XOR2XLTS U2135 ( .A(n1954), .B(n1953), .Y(n1959) );
XOR2XLTS U2136 ( .A(n2762), .B(n2761), .Y(n2766) );
XOR2XLTS U2137 ( .A(n2774), .B(n2773), .Y(n2776) );
CLKAND2X2TS U2138 ( .A(n2772), .B(n2771), .Y(n2774) );
XOR2XLTS U2139 ( .A(n1978), .B(n1977), .Y(n1987) );
AO22XLTS U2140 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[28]), .B0(n3008), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[5]), .Y(n1122) );
AO22XLTS U2141 ( .A0(n3058), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[12]), .B0(n3060), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[12]), .Y(n956) );
AO22XLTS U2142 ( .A0(n3010), .A1(n2999), .B0(n3007), .B1(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[1]), .Y(n1169) );
AO22XLTS U2143 ( .A0(n3041), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[8]), .B0(n3033), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[8]), .Y(n1066)
);
AO22XLTS U2144 ( .A0(n3010), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[23]), .B0(n3007), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[23]), .Y(n1150) );
AO22XLTS U2145 ( .A0(n1659), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[25]), .B0(n3066), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[25]), .Y(n1139) );
AO22XLTS U2146 ( .A0(n1922), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[7]), .B0(n3040), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[7]), .Y(n997)
);
AO22XLTS U2147 ( .A0(n3063), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[16]), .B0(n1661), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[16]), .Y(n933) );
AO22XLTS U2148 ( .A0(n1659), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[7]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[7]), .B1(n1661), .Y(n3182)
);
XOR2XLTS U2149 ( .A(n1872), .B(n3164), .Y(n1891) );
AO22XLTS U2150 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[29]), .B0(n1713), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[6]), .Y(n1117) );
AO22XLTS U2151 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[30]), .B0(n1713), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[7]), .Y(n1112) );
AO22XLTS U2152 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SFG), .B0(n3008), .B1(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_NRM), .Y(n960) );
AO22XLTS U2153 ( .A0(n3010), .A1(n2995), .B0(n3007), .B1(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[2]), .Y(n1170) );
MX2X1TS U2154 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[10]), .S0(n2523), .Y(n948)
);
MX2X1TS U2155 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[11]), .S0(n2523), .Y(n940)
);
MX2X1TS U2156 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[13]), .S0(n2523), .Y(n928)
);
MX2X1TS U2157 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[15]), .S0(n2523), .Y(n896)
);
MX2X1TS U2158 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[17]), .S0(n2523), .Y(n916)
);
MX2X1TS U2159 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[12]), .S0(n2523), .Y(n952)
);
MX2X1TS U2160 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[14]), .S0(n2523), .Y(n944)
);
MX2X1TS U2161 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[16]), .S0(n2523), .Y(n932)
);
MX2X1TS U2162 ( .A(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG), .B(
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT2), .S0(n3037), .Y(n1045) );
AO22XLTS U2163 ( .A0(n3062), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[17]), .B0(n3061), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[17]), .Y(n918) );
AO22XLTS U2164 ( .A0(n3062), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[18]), .B0(n3061), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[18]), .Y(n902) );
AO22XLTS U2165 ( .A0(n3062), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[19]), .B0(n3061), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[19]), .Y(n910) );
AO22XLTS U2166 ( .A0(n3062), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[20]), .B0(n3061), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[20]), .Y(n914) );
AO22XLTS U2167 ( .A0(n3062), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[21]), .B0(n3061), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[21]), .Y(n906) );
AO22XLTS U2168 ( .A0(n3058), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[5]), .B0(n3051), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n969)
);
AO22XLTS U2169 ( .A0(n3058), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[9]), .B0(n3051), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[9]), .Y(n976)
);
AO22XLTS U2170 ( .A0(n3062), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[4]), .B0(n3060), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[4]), .Y(n922) );
AO22XLTS U2171 ( .A0(n3058), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[5]), .B0(n3051), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[5]), .Y(n967) );
AO22XLTS U2172 ( .A0(n3062), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[6]), .B0(n3060), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[6]), .Y(n926) );
AO22XLTS U2173 ( .A0(n3062), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[8]), .B0(n3060), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[8]), .Y(n938) );
AO22XLTS U2174 ( .A0(n3058), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[9]), .B0(n3051), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[9]), .Y(n974) );
AO22XLTS U2175 ( .A0(n3058), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[10]), .B0(n3060), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[10]), .Y(n950) );
AO22XLTS U2176 ( .A0(n3058), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[11]), .B0(n3060), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[11]), .Y(n942) );
AO22XLTS U2177 ( .A0(n3058), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[12]), .B0(n3060), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[12]), .Y(n954) );
AO22XLTS U2178 ( .A0(n3062), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[13]), .B0(n3060), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[13]), .Y(n930) );
AO22XLTS U2179 ( .A0(n3058), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[14]), .B0(n3060), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[14]), .Y(n946) );
AO22XLTS U2180 ( .A0(n3062), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[16]), .B0(n3060), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[16]), .Y(n934) );
AO22XLTS U2181 ( .A0(n3058), .A1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_EXP),
.B0(n3051), .B1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1), .Y(n963)
);
MX2X1TS U2182 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[19]), .S0(n2524), .Y(n908)
);
MX2X1TS U2183 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[21]), .S0(n2524), .Y(n904)
);
MX2X1TS U2184 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[18]), .S0(n2524), .Y(n900)
);
MX2X1TS U2185 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[20]), .S0(n2524), .Y(n912)
);
MX2X1TS U2186 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[22]), .S0(n2524), .Y(n892)
);
AO22XLTS U2187 ( .A0(n3010), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[25]), .B0(n3020), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[25]), .Y(n1140) );
AO22XLTS U2188 ( .A0(n3010), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[24]), .B0(n3020), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[24]), .Y(n1145) );
AO22XLTS U2189 ( .A0(n3010), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[26]), .B0(n3020), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[26]), .Y(n1135) );
AO22XLTS U2190 ( .A0(n3010), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[27]), .B0(n3020), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[27]), .Y(n1130) );
AO22XLTS U2191 ( .A0(n3025), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[28]), .B0(n3020), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[28]), .Y(n1125) );
AO22XLTS U2192 ( .A0(n3025), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[29]), .B0(n3020), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[29]), .Y(n1120) );
AO22XLTS U2193 ( .A0(n3025), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[30]), .B0(n3020), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[30]), .Y(n1115) );
AO22XLTS U2194 ( .A0(n3041), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[4]), .B0(n3033), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[4]), .Y(n1078)
);
AO22XLTS U2195 ( .A0(n3041), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[6]), .B0(n3033), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n1075)
);
AO22XLTS U2196 ( .A0(n3041), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[10]), .B0(n3040), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[10]), .Y(n1057) );
AO22XLTS U2197 ( .A0(n3041), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[11]), .B0(n3033), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[11]), .Y(n1063) );
AO22XLTS U2198 ( .A0(n3041), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[13]), .B0(n3033), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[13]), .Y(n1072) );
AO22XLTS U2199 ( .A0(n3041), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[14]), .B0(n3040), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[14]), .Y(n1060) );
AO22XLTS U2200 ( .A0(n3025), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[15]), .B0(n3020), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n1096) );
AO22XLTS U2201 ( .A0(n3041), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[16]), .B0(n3033), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n1069) );
AO22XLTS U2202 ( .A0(n3025), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[17]), .B0(n3033), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n1081) );
AO22XLTS U2203 ( .A0(n3025), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[18]), .B0(n3020), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[18]), .Y(n1093) );
AO22XLTS U2204 ( .A0(n3025), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[19]), .B0(n3033), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n1087) );
AO22XLTS U2205 ( .A0(n3025), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[20]), .B0(n3033), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[20]), .Y(n1084) );
AO22XLTS U2206 ( .A0(n3025), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[21]), .B0(n3033), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n1090) );
AO22XLTS U2207 ( .A0(n3025), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[22]), .B0(n3020), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n1099) );
AO22XLTS U2208 ( .A0(n3041), .A1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_EXP),
.B0(n3040), .B1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1), .Y(n1054)
);
AO22XLTS U2209 ( .A0(n3041), .A1(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_EXP),
.B0(n3040), .B1(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT1), .Y(n1047)
);
AO22XLTS U2210 ( .A0(n3010), .A1(n3001), .B0(n3007), .B1(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[0]), .Y(n1168) );
AO22XLTS U2211 ( .A0(n3054), .A1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_NRM),
.B0(n3053), .B1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1SHT2), .Y(
n959) );
AO22XLTS U2212 ( .A0(n3054), .A1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_NRM),
.B0(n3053), .B1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1SHT2), .Y(
n1050) );
AO22XLTS U2213 ( .A0(n1684), .A1(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1SHT2), .B0(n3055), .B1(
zero_flag), .Y(n958) );
AO22XLTS U2214 ( .A0(n1674), .A1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SFG),
.B0(n2822), .B1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_NRM), .Y(n1051)
);
AO22XLTS U2215 ( .A0(n3065), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[15]), .B0(n3064), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[15]), .Y(n898) );
AO22XLTS U2216 ( .A0(n3065), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[22]), .B0(n3040), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[22]), .Y(n894) );
AO22XLTS U2217 ( .A0(busy), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[0]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[0]), .B1(n3066), .Y(n3181) );
AO22XLTS U2218 ( .A0(busy), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[1]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[1]), .B1(n3066), .Y(n3180) );
AO22XLTS U2219 ( .A0(n1659), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[2]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[2]), .B1(n3066), .Y(n3183)
);
AO22XLTS U2220 ( .A0(n1659), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[3]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[3]), .B1(n3066), .Y(n3184)
);
AO22XLTS U2221 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[15]), .B0(n3066), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[15]), .Y(n897) );
AO22XLTS U2222 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[22]), .B0(n3066), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[22]), .Y(n893) );
AO22XLTS U2223 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[24]), .B0(n3066), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[24]), .Y(n1144) );
AO22XLTS U2224 ( .A0(n3059), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[9]), .B0(n3228), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[9]), .Y(n973) );
AO22XLTS U2225 ( .A0(n3059), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[12]), .B0(n3228), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[12]), .Y(n953) );
AO22XLTS U2226 ( .A0(n3059), .A1(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT1),
.B0(n3228), .B1(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT2), .Y(n1046)
);
AO22XLTS U2227 ( .A0(n3059), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[26]), .B0(n1661), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[26]), .Y(n1134) );
AO22XLTS U2228 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[27]), .B0(n1661), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[27]), .Y(n1129) );
AO22XLTS U2229 ( .A0(n3059), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[28]), .B0(n1661), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[28]), .Y(n1124) );
AO22XLTS U2230 ( .A0(n3059), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[29]), .B0(n3228), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[29]), .Y(n1119) );
AO22XLTS U2231 ( .A0(n3059), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[30]), .B0(n3228), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[30]), .Y(n1114) );
AO22XLTS U2232 ( .A0(n3059), .A1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1),
.B0(n3228), .B1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT2), .Y(n962)
);
AO22XLTS U2233 ( .A0(n3059), .A1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1),
.B0(n3228), .B1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT2), .Y(n1053)
);
AO22XLTS U2234 ( .A0(n1922), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[2]), .B0(n3040), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n1004)
);
AO22XLTS U2235 ( .A0(n1922), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[0]), .B0(n3051), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n990)
);
AO22XLTS U2236 ( .A0(n1922), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[1]), .B0(n3051), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[1]), .Y(n983)
);
AO22XLTS U2237 ( .A0(n1922), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[3]), .B0(n3040), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n1020)
);
AO22XLTS U2238 ( .A0(n1922), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[0]), .B0(n3051), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[0]), .Y(n988) );
AO22XLTS U2239 ( .A0(n1922), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[1]), .B0(n3051), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[1]), .Y(n981) );
AO22XLTS U2240 ( .A0(n1922), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[2]), .B0(n3040), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[2]), .Y(n1002) );
AO22XLTS U2241 ( .A0(n1922), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[3]), .B0(n3040), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[3]), .Y(n1018) );
AO22XLTS U2242 ( .A0(n1922), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[7]), .B0(n3051), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[7]), .Y(n995) );
AO22XLTS U2243 ( .A0(busy), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[4]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[4]), .B1(n1661), .Y(n3177) );
AO22XLTS U2244 ( .A0(busy), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[5]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[5]), .B1(n1661), .Y(n3179) );
AO22XLTS U2245 ( .A0(busy), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[6]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[6]), .B1(n1661), .Y(n3178) );
AO22XLTS U2246 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[23]), .B0(n1661), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[23]), .Y(n1149) );
AO22XLTS U2247 ( .A0(n3063), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[8]), .B0(n3228), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[8]), .Y(n937) );
AO22XLTS U2248 ( .A0(n3063), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[10]), .B0(n3228), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[10]), .Y(n949) );
AO22XLTS U2249 ( .A0(n3063), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[11]), .B0(n1660), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[11]), .Y(n941) );
AO22XLTS U2250 ( .A0(n3059), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[13]), .B0(n1660), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[13]), .Y(n929) );
AO22XLTS U2251 ( .A0(n3063), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[14]), .B0(n1660), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[14]), .Y(n945) );
AO22XLTS U2252 ( .A0(n3063), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[17]), .B0(n1660), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[17]), .Y(n917) );
AO22XLTS U2253 ( .A0(n3063), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[19]), .B0(n1660), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[19]), .Y(n909) );
AO22XLTS U2254 ( .A0(n3063), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[20]), .B0(n1660), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[20]), .Y(n913) );
AO22XLTS U2255 ( .A0(n3063), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[21]), .B0(n1660), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[21]), .Y(n905) );
AO22XLTS U2256 ( .A0(n3063), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[18]), .B0(n1661), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[18]), .Y(n901) );
MX2X1TS U2257 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[3]), .S0(n3054), .Y(n1131)
);
MX2X1TS U2258 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[5]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[5]), .S0(n3054), .Y(n1121)
);
MX2X1TS U2259 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[0]), .S0(n1702), .Y(n1146)
);
MX2X1TS U2260 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[1]), .S0(n1702), .Y(n1141)
);
MX2X1TS U2261 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[2]), .S0(n3054), .Y(n1136)
);
MX2X1TS U2262 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[4]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[4]), .S0(n3054), .Y(n1126)
);
MX2X1TS U2263 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[6]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[6]), .S0(n3054), .Y(n1116)
);
MX2X1TS U2264 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[7]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[7]), .S0(n3054), .Y(n1111)
);
XOR2XLTS U2265 ( .A(n2628), .B(n2627), .Y(n2633) );
MX2X1TS U2266 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[1]), .S0(n3037), .Y(n979) );
MX2X1TS U2267 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[2]), .S0(n3009), .Y(n1000)
);
AO21XLTS U2268 ( .A0(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[0]),
.A1(n2824), .B0(n2808), .Y(n1007) );
AO21XLTS U2269 ( .A0(n2828), .A1(n2815), .B0(n2811), .Y(
inst_CORDIC_FSM_v3_state_next[2]) );
NOR2XLTS U2270 ( .A(n2814), .B(n2862), .Y(inst_CORDIC_FSM_v3_state_next[6])
);
AOI2BB1XLTS U2271 ( .A0N(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]),
.A1N(overflow_flag), .B0(n3016), .Y(n1104) );
AO21XLTS U2272 ( .A0(underflow_flag), .A1(n1683), .B0(n3014), .Y(n1105) );
AO22XLTS U2273 ( .A0(n2846), .A1(d_ff1_operation_out), .B0(n2845), .B1(
operation), .Y(n1593) );
OAI21XLTS U2274 ( .A0(n1898), .A1(n2813), .B0(n2868), .Y(
inst_CORDIC_FSM_v3_state_next[4]) );
AO22XLTS U2275 ( .A0(n2846), .A1(d_ff1_shift_region_flag_out[1]), .B0(n2845),
.B1(shift_region_flag[1]), .Y(n1591) );
AO22XLTS U2276 ( .A0(n2846), .A1(d_ff1_shift_region_flag_out[0]), .B0(n2845),
.B1(shift_region_flag[0]), .Y(n1592) );
XOR2XLTS U2277 ( .A(n2725), .B(n2724), .Y(n2730) );
AO22XLTS U2278 ( .A0(d_ff2_Y[28]), .A1(n2897), .B0(n2922), .B1(d_ff_Yn[28]),
.Y(n1343) );
OAI21XLTS U2279 ( .A0(n3080), .A1(n2504), .B0(n2497), .Y(n895) );
OAI21XLTS U2280 ( .A0(n3111), .A1(n2499), .B0(n1826), .Y(n899) );
OAI21XLTS U2281 ( .A0(n3115), .A1(n2499), .B0(n2495), .Y(n919) );
OAI21XLTS U2282 ( .A0(n1640), .A1(n2499), .B0(n2486), .Y(n923) );
OAI21XLTS U2283 ( .A0(n1653), .A1(n2499), .B0(n2485), .Y(n927) );
OAI21XLTS U2284 ( .A0(n2489), .A1(n2499), .B0(n2488), .Y(n931) );
OAI21XLTS U2285 ( .A0(n2491), .A1(n2504), .B0(n2490), .Y(n947) );
OAI21XLTS U2286 ( .A0(n1654), .A1(n2504), .B0(n2484), .Y(n951) );
OAI21XLTS U2287 ( .A0(n3119), .A1(n2504), .B0(n2476), .Y(n955) );
OAI21XLTS U2288 ( .A0(n3119), .A1(n2457), .B0(n2448), .Y(n957) );
AO22XLTS U2289 ( .A0(n2524), .A1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT2),
.B0(n2558), .B1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SFG), .Y(n961)
);
AO22XLTS U2290 ( .A0(n3038), .A1(n2469), .B0(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_EXP), .B1(n3039), .Y(n964) );
OAI21XLTS U2291 ( .A0(n3123), .A1(n2504), .B0(n2479), .Y(n975) );
XOR2XLTS U2292 ( .A(n2657), .B(n2656), .Y(n2662) );
XOR2XLTS U2293 ( .A(n2695), .B(n2694), .Y(n2700) );
XOR2XLTS U2294 ( .A(n2676), .B(n2675), .Y(n2681) );
OAI21XLTS U2295 ( .A0(n3112), .A1(n2457), .B0(n2455), .Y(n1021) );
XOR2XLTS U2296 ( .A(n2647), .B(n2646), .Y(n2652) );
XOR2XLTS U2297 ( .A(n2796), .B(n2795), .Y(n2806) );
AO22X1TS U2298 ( .A0(n1894), .A1(n1944), .B0(
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM), .B1(n2822), .Y(n1044) );
AO21XLTS U2299 ( .A0(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_EXP), .A1(n3039),
.B0(n3038), .Y(n1048) );
AO22XLTS U2300 ( .A0(n3037), .A1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT2),
.B0(n2585), .B1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SFG), .Y(n1052)
);
OAI21XLTS U2301 ( .A0(n1654), .A1(n2457), .B0(n2443), .Y(n1058) );
OAI21XLTS U2302 ( .A0(n2491), .A1(n2457), .B0(n2456), .Y(n1061) );
OAI21XLTS U2303 ( .A0(n3122), .A1(n2457), .B0(n2449), .Y(n1067) );
OAI21XLTS U2304 ( .A0(n3110), .A1(n2463), .B0(n2445), .Y(n1085) );
OAI21XLTS U2305 ( .A0(n2451), .A1(n2463), .B0(n2450), .Y(n1088) );
OAI21XLTS U2306 ( .A0(n3111), .A1(n2463), .B0(n2453), .Y(n1097) );
MX2X1TS U2307 ( .A(n2517), .B(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[1]), .S0(n2824), .Y(
n1102) );
AO22XLTS U2308 ( .A0(n3037), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[30]), .B0(n2612), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[30]), .Y(n1113) );
AO22XLTS U2309 ( .A0(n3037), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[29]), .B0(n2612), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[29]), .Y(n1118) );
AO22XLTS U2310 ( .A0(n3037), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[28]), .B0(n2612), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[28]), .Y(n1123) );
AO22XLTS U2311 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[27]), .B0(n3008), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[4]), .Y(n1127) );
AO22XLTS U2312 ( .A0(n3037), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[27]), .B0(n2622), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[27]), .Y(n1128) );
AO22XLTS U2313 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[26]), .B0(n3008), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[3]), .Y(n1132) );
AO22XLTS U2314 ( .A0(n3037), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[26]), .B0(n2585), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[26]), .Y(n1133) );
AO22XLTS U2315 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[25]), .B0(n3008), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[2]), .Y(n1137) );
AO22XLTS U2316 ( .A0(n2523), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[25]), .B0(n2558), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[25]), .Y(n1138) );
AO22XLTS U2317 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[24]), .B0(n3008), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[1]), .Y(n1142) );
AO22XLTS U2318 ( .A0(n3009), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[24]), .B0(n2622), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[24]), .Y(n1143) );
AO22XLTS U2319 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[23]), .B0(n3008), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[0]), .Y(n1147) );
AO22XLTS U2320 ( .A0(n2523), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[23]), .B0(n2558), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[23]), .Y(n1148) );
AO22XLTS U2321 ( .A0(n3010), .A1(n3006), .B0(n3007), .B1(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[4]), .Y(n1167) );
AO22XLTS U2322 ( .A0(n3010), .A1(n1989), .B0(n3064), .B1(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[3]), .Y(n1171) );
OAI21XLTS U2323 ( .A0(beg_fsm_cordic), .A1(n2810), .B0(n2169), .Y(
inst_CORDIC_FSM_v3_state_next[0]) );
AO22XLTS U2324 ( .A0(n2870), .A1(d_ff2_X[5]), .B0(n2866), .B1(
d_ff3_sh_x_out[5]), .Y(n1473) );
AO22XLTS U2325 ( .A0(n2980), .A1(d_ff2_Y[5]), .B0(n2912), .B1(
d_ff3_sh_y_out[5]), .Y(n1401) );
AO22XLTS U2326 ( .A0(n2857), .A1(result_add_subt[5]), .B0(n2862), .B1(
d_ff_Zn[5]), .Y(n1538) );
AO22XLTS U2327 ( .A0(n2940), .A1(d_ff2_X[9]), .B0(n2866), .B1(
d_ff3_sh_x_out[9]), .Y(n1465) );
AO22XLTS U2328 ( .A0(n2903), .A1(d_ff2_Y[9]), .B0(n2912), .B1(
d_ff3_sh_y_out[9]), .Y(n1389) );
AO22XLTS U2329 ( .A0(n2864), .A1(result_add_subt[9]), .B0(n2863), .B1(
d_ff_Zn[9]), .Y(n1526) );
AO22XLTS U2330 ( .A0(n2870), .A1(d_ff2_X[1]), .B0(n2868), .B1(
d_ff3_sh_x_out[1]), .Y(n1481) );
AO22XLTS U2331 ( .A0(n2980), .A1(d_ff2_Y[1]), .B0(n2988), .B1(
d_ff3_sh_y_out[1]), .Y(n1413) );
AO22XLTS U2332 ( .A0(n2857), .A1(result_add_subt[1]), .B0(n2862), .B1(
d_ff_Zn[1]), .Y(n1550) );
AO22XLTS U2333 ( .A0(n2870), .A1(d_ff2_X[0]), .B0(n2979), .B1(
d_ff3_sh_x_out[0]), .Y(n1483) );
AO22XLTS U2334 ( .A0(n2989), .A1(d_ff2_Y[0]), .B0(n2988), .B1(
d_ff3_sh_y_out[0]), .Y(n1416) );
AO22XLTS U2335 ( .A0(n2857), .A1(result_add_subt[0]), .B0(n2954), .B1(
d_ff_Zn[0]), .Y(n1553) );
AO22XLTS U2336 ( .A0(n2929), .A1(d_ff2_X[7]), .B0(n2979), .B1(
d_ff3_sh_x_out[7]), .Y(n1469) );
AO22XLTS U2337 ( .A0(n2938), .A1(d_ff2_Y[7]), .B0(n2912), .B1(
d_ff3_sh_y_out[7]), .Y(n1395) );
AO22XLTS U2338 ( .A0(n2857), .A1(result_add_subt[7]), .B0(n2863), .B1(
d_ff_Zn[7]), .Y(n1532) );
AO22XLTS U2339 ( .A0(n2870), .A1(d_ff2_X[2]), .B0(n2866), .B1(
d_ff3_sh_x_out[2]), .Y(n1479) );
AO22XLTS U2340 ( .A0(n2989), .A1(d_ff2_Y[2]), .B0(n2988), .B1(
d_ff3_sh_y_out[2]), .Y(n1410) );
AO22XLTS U2341 ( .A0(n2857), .A1(result_add_subt[2]), .B0(n2862), .B1(
d_ff_Zn[2]), .Y(n1547) );
AO22XLTS U2342 ( .A0(n2870), .A1(d_ff2_X[3]), .B0(n2840), .B1(
d_ff3_sh_x_out[3]), .Y(n1477) );
AO22XLTS U2343 ( .A0(n2980), .A1(d_ff2_Y[3]), .B0(n2988), .B1(
d_ff3_sh_y_out[3]), .Y(n1407) );
AO22XLTS U2344 ( .A0(n2857), .A1(result_add_subt[3]), .B0(n2862), .B1(
d_ff_Zn[3]), .Y(n1544) );
OAI21XLTS U2345 ( .A0(n2947), .A1(n1685), .B0(n2377), .Y(n1557) );
AO22XLTS U2346 ( .A0(n2989), .A1(d_ff2_X[31]), .B0(n2988), .B1(
d_ff3_sh_x_out[31]), .Y(n1421) );
AO22XLTS U2347 ( .A0(n2989), .A1(d_ff2_Y[31]), .B0(n2988), .B1(
d_ff3_sh_y_out[31]), .Y(n1208) );
AO22XLTS U2348 ( .A0(n2953), .A1(result_add_subt[31]), .B0(n2951), .B1(
d_ff_Zn[31]), .Y(n1419) );
AO22XLTS U2349 ( .A0(n2879), .A1(d_ff2_X[12]), .B0(n2868), .B1(
d_ff3_sh_x_out[12]), .Y(n1459) );
AO22XLTS U2350 ( .A0(n2989), .A1(d_ff2_Y[12]), .B0(n2912), .B1(
d_ff3_sh_y_out[12]), .Y(n1380) );
AO22XLTS U2351 ( .A0(n2864), .A1(result_add_subt[12]), .B0(n2863), .B1(
d_ff_Zn[12]), .Y(n1517) );
AO22XLTS U2352 ( .A0(n2940), .A1(d_ff2_X[10]), .B0(n2840), .B1(
d_ff3_sh_x_out[10]), .Y(n1463) );
AO22XLTS U2353 ( .A0(n2938), .A1(d_ff2_Y[10]), .B0(n2912), .B1(
d_ff3_sh_y_out[10]), .Y(n1386) );
AO22XLTS U2354 ( .A0(n2864), .A1(result_add_subt[10]), .B0(n2863), .B1(
d_ff_Zn[10]), .Y(n1523) );
AO22XLTS U2355 ( .A0(n2903), .A1(d_ff2_X[14]), .B0(n2872), .B1(
d_ff3_sh_x_out[14]), .Y(n1455) );
AO22XLTS U2356 ( .A0(n2989), .A1(d_ff2_Y[14]), .B0(n2919), .B1(
d_ff3_sh_y_out[14]), .Y(n1374) );
AO22XLTS U2357 ( .A0(n2864), .A1(result_add_subt[14]), .B0(n2954), .B1(
d_ff_Zn[14]), .Y(n1511) );
AO22XLTS U2358 ( .A0(n2989), .A1(d_ff2_X[11]), .B0(n2979), .B1(
d_ff3_sh_x_out[11]), .Y(n1461) );
AO22XLTS U2359 ( .A0(n2938), .A1(d_ff2_Y[11]), .B0(n2912), .B1(
d_ff3_sh_y_out[11]), .Y(n1383) );
AO22XLTS U2360 ( .A0(n2864), .A1(result_add_subt[11]), .B0(n2863), .B1(
d_ff_Zn[11]), .Y(n1520) );
AO22XLTS U2361 ( .A0(n2879), .A1(d_ff2_X[8]), .B0(n2868), .B1(
d_ff3_sh_x_out[8]), .Y(n1467) );
AO22XLTS U2362 ( .A0(n2938), .A1(d_ff2_Y[8]), .B0(n2912), .B1(
d_ff3_sh_y_out[8]), .Y(n1392) );
AO22XLTS U2363 ( .A0(n2857), .A1(result_add_subt[8]), .B0(n2863), .B1(
d_ff_Zn[8]), .Y(n1529) );
AO22XLTS U2364 ( .A0(n2870), .A1(d_ff2_X[16]), .B0(n2872), .B1(
d_ff3_sh_x_out[16]), .Y(n1451) );
AO22XLTS U2365 ( .A0(n2980), .A1(d_ff2_Y[16]), .B0(n2919), .B1(
d_ff3_sh_y_out[16]), .Y(n1368) );
AO22XLTS U2366 ( .A0(n2864), .A1(result_add_subt[16]), .B0(n2862), .B1(
d_ff_Zn[16]), .Y(n1505) );
AO22XLTS U2367 ( .A0(n2940), .A1(d_ff2_X[13]), .B0(n2866), .B1(
d_ff3_sh_x_out[13]), .Y(n1457) );
AO22XLTS U2368 ( .A0(n2938), .A1(d_ff2_Y[13]), .B0(n2912), .B1(
d_ff3_sh_y_out[13]), .Y(n1377) );
AO22XLTS U2369 ( .A0(n2864), .A1(result_add_subt[13]), .B0(n2954), .B1(
d_ff_Zn[13]), .Y(n1514) );
AO22XLTS U2370 ( .A0(n2879), .A1(d_ff2_X[6]), .B0(n2840), .B1(
d_ff3_sh_x_out[6]), .Y(n1471) );
AO22XLTS U2371 ( .A0(n2989), .A1(d_ff2_Y[6]), .B0(n2912), .B1(
d_ff3_sh_y_out[6]), .Y(n1398) );
AO22XLTS U2372 ( .A0(n2857), .A1(result_add_subt[6]), .B0(n2862), .B1(
d_ff_Zn[6]), .Y(n1535) );
AO22XLTS U2373 ( .A0(n2870), .A1(d_ff2_X[4]), .B0(n2868), .B1(
d_ff3_sh_x_out[4]), .Y(n1475) );
AO22XLTS U2374 ( .A0(n2980), .A1(d_ff2_Y[4]), .B0(n2912), .B1(
d_ff3_sh_y_out[4]), .Y(n1404) );
AO22XLTS U2375 ( .A0(n2857), .A1(result_add_subt[4]), .B0(n2862), .B1(
d_ff_Zn[4]), .Y(n1541) );
AO22XLTS U2376 ( .A0(n2929), .A1(d_ff2_X[17]), .B0(n2872), .B1(
d_ff3_sh_x_out[17]), .Y(n1449) );
AO22XLTS U2377 ( .A0(n2989), .A1(d_ff2_Y[17]), .B0(n2919), .B1(
d_ff3_sh_y_out[17]), .Y(n1365) );
AO22XLTS U2378 ( .A0(n2864), .A1(result_add_subt[17]), .B0(n2951), .B1(
d_ff_Zn[17]), .Y(n1502) );
AO22XLTS U2379 ( .A0(n2870), .A1(d_ff2_X[20]), .B0(n2872), .B1(
d_ff3_sh_x_out[20]), .Y(n1443) );
AO22XLTS U2380 ( .A0(n2929), .A1(d_ff2_Y[20]), .B0(n2919), .B1(
d_ff3_sh_y_out[20]), .Y(n1356) );
AO22XLTS U2381 ( .A0(n2953), .A1(result_add_subt[20]), .B0(n2951), .B1(
d_ff_Zn[20]), .Y(n1493) );
AO22XLTS U2382 ( .A0(n2879), .A1(d_ff2_X[19]), .B0(n2872), .B1(
d_ff3_sh_x_out[19]), .Y(n1445) );
AO22XLTS U2383 ( .A0(n2929), .A1(d_ff2_Y[19]), .B0(n2919), .B1(
d_ff3_sh_y_out[19]), .Y(n1359) );
AO22XLTS U2384 ( .A0(n2953), .A1(result_add_subt[19]), .B0(n2951), .B1(
d_ff_Zn[19]), .Y(n1496) );
AO22XLTS U2385 ( .A0(n2879), .A1(d_ff2_X[21]), .B0(n2872), .B1(
d_ff3_sh_x_out[21]), .Y(n1441) );
AO22XLTS U2386 ( .A0(n2929), .A1(d_ff2_Y[21]), .B0(n2919), .B1(
d_ff3_sh_y_out[21]), .Y(n1353) );
AO22XLTS U2387 ( .A0(n2953), .A1(result_add_subt[21]), .B0(n2951), .B1(
d_ff_Zn[21]), .Y(n1490) );
AO22XLTS U2388 ( .A0(n2879), .A1(d_ff2_X[18]), .B0(n2872), .B1(
d_ff3_sh_x_out[18]), .Y(n1447) );
AO22XLTS U2389 ( .A0(n2929), .A1(d_ff2_Y[18]), .B0(n2919), .B1(
d_ff3_sh_y_out[18]), .Y(n1362) );
AO22XLTS U2390 ( .A0(n2864), .A1(result_add_subt[18]), .B0(n2951), .B1(
d_ff_Zn[18]), .Y(n1499) );
AO22XLTS U2391 ( .A0(n2869), .A1(d_ff2_X[15]), .B0(n2872), .B1(
d_ff3_sh_x_out[15]), .Y(n1453) );
AO22XLTS U2392 ( .A0(n2980), .A1(d_ff2_Y[15]), .B0(n2919), .B1(
d_ff3_sh_y_out[15]), .Y(n1371) );
AO22XLTS U2393 ( .A0(n2864), .A1(result_add_subt[15]), .B0(n2862), .B1(
d_ff_Zn[15]), .Y(n1508) );
AO22XLTS U2394 ( .A0(n2879), .A1(d_ff2_X[22]), .B0(n2872), .B1(
d_ff3_sh_x_out[22]), .Y(n1439) );
AO22XLTS U2395 ( .A0(n2929), .A1(d_ff2_Y[22]), .B0(n2919), .B1(
d_ff3_sh_y_out[22]), .Y(n1350) );
AO22XLTS U2396 ( .A0(n2953), .A1(result_add_subt[22]), .B0(n2951), .B1(
d_ff_Zn[22]), .Y(n1487) );
AO22XLTS U2397 ( .A0(n2956), .A1(result_add_subt[30]), .B0(n2954), .B1(
d_ff_Zn[30]), .Y(n1276) );
AO22XLTS U2398 ( .A0(n2956), .A1(result_add_subt[29]), .B0(n2863), .B1(
d_ff_Zn[29]), .Y(n1279) );
AO22XLTS U2399 ( .A0(n2956), .A1(result_add_subt[28]), .B0(n2954), .B1(
d_ff_Zn[28]), .Y(n1282) );
AO22XLTS U2400 ( .A0(n2953), .A1(result_add_subt[27]), .B0(n2954), .B1(
d_ff_Zn[27]), .Y(n1285) );
AO22XLTS U2401 ( .A0(n2953), .A1(result_add_subt[26]), .B0(n2954), .B1(
d_ff_Zn[26]), .Y(n1288) );
AO22XLTS U2402 ( .A0(n2953), .A1(result_add_subt[25]), .B0(n2951), .B1(
d_ff_Zn[25]), .Y(n1291) );
AO22XLTS U2403 ( .A0(n2953), .A1(result_add_subt[24]), .B0(n2951), .B1(
d_ff_Zn[24]), .Y(n1294) );
AO22XLTS U2404 ( .A0(n2953), .A1(result_add_subt[23]), .B0(n2951), .B1(
d_ff_Zn[23]), .Y(n1297) );
AOI2BB2XLTS U2405 ( .B0(n2940), .B1(n2939), .A0N(d_ff3_sh_y_out[29]), .A1N(
n2938), .Y(n1328) );
AO22XLTS U2406 ( .A0(n2980), .A1(n2936), .B0(n2979), .B1(d_ff3_sh_y_out[28]),
.Y(n1330) );
OAI21XLTS U2407 ( .A0(n2935), .A1(n3141), .B0(n2937), .Y(n2936) );
AOI2BB2XLTS U2408 ( .B0(n2940), .B1(n2934), .A0N(d_ff3_sh_y_out[27]), .A1N(
n2938), .Y(n1332) );
AO22XLTS U2409 ( .A0(n2929), .A1(intadd_356_SUM_2_), .B0(n2866), .B1(
d_ff3_sh_y_out[26]), .Y(n1334) );
AO22XLTS U2410 ( .A0(n2929), .A1(intadd_356_SUM_1_), .B0(n2868), .B1(
d_ff3_sh_y_out[25]), .Y(n1336) );
AO22XLTS U2411 ( .A0(n2929), .A1(intadd_356_SUM_0_), .B0(n2919), .B1(
d_ff3_sh_y_out[24]), .Y(n1338) );
AOI2BB2XLTS U2412 ( .B0(n2940), .B1(n2881), .A0N(d_ff3_sh_x_out[29]), .A1N(
n2938), .Y(n1424) );
AO22XLTS U2413 ( .A0(n2879), .A1(n2878), .B0(n2988), .B1(d_ff3_sh_x_out[28]),
.Y(n1425) );
OAI21XLTS U2414 ( .A0(n2877), .A1(n3142), .B0(n2880), .Y(n2878) );
AOI2BB2XLTS U2415 ( .B0(n2940), .B1(n2876), .A0N(d_ff3_sh_x_out[27]), .A1N(
n2938), .Y(n1426) );
AO22XLTS U2416 ( .A0(n2879), .A1(intadd_357_SUM_2_), .B0(n2988), .B1(
d_ff3_sh_x_out[26]), .Y(n1427) );
AO22XLTS U2417 ( .A0(n2870), .A1(intadd_357_SUM_1_), .B0(n2988), .B1(
d_ff3_sh_x_out[25]), .Y(n1428) );
AO22XLTS U2418 ( .A0(n2879), .A1(intadd_357_SUM_0_), .B0(n2872), .B1(
d_ff3_sh_x_out[24]), .Y(n1429) );
AO22XLTS U2419 ( .A0(n2870), .A1(intadd_356_B_1_), .B0(n2979), .B1(
d_ff3_LUT_out[8]), .Y(n1602) );
AO22XLTS U2420 ( .A0(n2940), .A1(n2839), .B0(n2840), .B1(d_ff3_LUT_out[13]),
.Y(n1606) );
AO22XLTS U2421 ( .A0(n2980), .A1(n2838), .B0(n2840), .B1(d_ff3_LUT_out[19]),
.Y(n1608) );
AO22XLTS U2422 ( .A0(n2825), .A1(n1659), .B0(n2823), .B1(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n1624) );
AO22XLTS U2423 ( .A0(n2823), .A1(n3012), .B0(n2825), .B1(n2819), .Y(n1627)
);
AO22XLTS U2424 ( .A0(n2853), .A1(d_ff1_Z[31]), .B0(n2852), .B1(data_in[31]),
.Y(n1559) );
AO22XLTS U2425 ( .A0(n2853), .A1(d_ff1_Z[0]), .B0(n2852), .B1(data_in[0]),
.Y(n1560) );
AO22XLTS U2426 ( .A0(n2853), .A1(d_ff1_Z[1]), .B0(n2852), .B1(data_in[1]),
.Y(n1561) );
AO22XLTS U2427 ( .A0(n2853), .A1(d_ff1_Z[2]), .B0(n2852), .B1(data_in[2]),
.Y(n1562) );
AO22XLTS U2428 ( .A0(n2853), .A1(d_ff1_Z[3]), .B0(n2851), .B1(data_in[3]),
.Y(n1563) );
AO22XLTS U2429 ( .A0(n2853), .A1(d_ff1_Z[4]), .B0(n2852), .B1(data_in[4]),
.Y(n1564) );
AO22XLTS U2430 ( .A0(n2850), .A1(d_ff1_Z[5]), .B0(n2852), .B1(data_in[5]),
.Y(n1565) );
AO22XLTS U2431 ( .A0(n2850), .A1(d_ff1_Z[6]), .B0(n2849), .B1(data_in[6]),
.Y(n1566) );
AO22XLTS U2432 ( .A0(n2850), .A1(d_ff1_Z[7]), .B0(n2849), .B1(data_in[7]),
.Y(n1567) );
AO22XLTS U2433 ( .A0(n2850), .A1(d_ff1_Z[8]), .B0(n2849), .B1(data_in[8]),
.Y(n1568) );
AO22XLTS U2434 ( .A0(n2850), .A1(d_ff1_Z[9]), .B0(n2849), .B1(data_in[9]),
.Y(n1569) );
AO22XLTS U2435 ( .A0(n2850), .A1(d_ff1_Z[10]), .B0(n2849), .B1(data_in[10]),
.Y(n1570) );
AO22XLTS U2436 ( .A0(n2850), .A1(d_ff1_Z[11]), .B0(n2849), .B1(data_in[11]),
.Y(n1571) );
AO22XLTS U2437 ( .A0(n2850), .A1(d_ff1_Z[12]), .B0(n2849), .B1(data_in[12]),
.Y(n1572) );
AO22XLTS U2438 ( .A0(n2850), .A1(d_ff1_Z[13]), .B0(n2849), .B1(data_in[13]),
.Y(n1573) );
AO22XLTS U2439 ( .A0(n2850), .A1(d_ff1_Z[14]), .B0(n2849), .B1(data_in[14]),
.Y(n1574) );
AO22XLTS U2440 ( .A0(n2848), .A1(d_ff1_Z[15]), .B0(n2849), .B1(data_in[15]),
.Y(n1575) );
AO22XLTS U2441 ( .A0(n2848), .A1(d_ff1_Z[16]), .B0(n2847), .B1(data_in[16]),
.Y(n1576) );
AO22XLTS U2442 ( .A0(n2848), .A1(d_ff1_Z[17]), .B0(n2847), .B1(data_in[17]),
.Y(n1577) );
AO22XLTS U2443 ( .A0(n2848), .A1(d_ff1_Z[18]), .B0(n2847), .B1(data_in[18]),
.Y(n1578) );
AO22XLTS U2444 ( .A0(n2848), .A1(d_ff1_Z[19]), .B0(n2847), .B1(data_in[19]),
.Y(n1579) );
AO22XLTS U2445 ( .A0(n2848), .A1(d_ff1_Z[20]), .B0(n2847), .B1(data_in[20]),
.Y(n1580) );
AO22XLTS U2446 ( .A0(n2848), .A1(d_ff1_Z[21]), .B0(n2847), .B1(data_in[21]),
.Y(n1581) );
AO22XLTS U2447 ( .A0(n2848), .A1(d_ff1_Z[22]), .B0(n2847), .B1(data_in[22]),
.Y(n1582) );
AO22XLTS U2448 ( .A0(n2848), .A1(d_ff1_Z[23]), .B0(n2847), .B1(data_in[23]),
.Y(n1583) );
AO22XLTS U2449 ( .A0(n2848), .A1(d_ff1_Z[24]), .B0(n2847), .B1(data_in[24]),
.Y(n1584) );
AO22XLTS U2450 ( .A0(n2846), .A1(d_ff1_Z[25]), .B0(n2847), .B1(data_in[25]),
.Y(n1585) );
AO22XLTS U2451 ( .A0(n2846), .A1(d_ff1_Z[26]), .B0(n2845), .B1(data_in[26]),
.Y(n1586) );
AO22XLTS U2452 ( .A0(n2846), .A1(d_ff1_Z[27]), .B0(n2845), .B1(data_in[27]),
.Y(n1587) );
AO22XLTS U2453 ( .A0(n2846), .A1(d_ff1_Z[28]), .B0(n2845), .B1(data_in[28]),
.Y(n1588) );
AO22XLTS U2454 ( .A0(n2846), .A1(d_ff1_Z[29]), .B0(n2845), .B1(data_in[29]),
.Y(n1589) );
AO22XLTS U2455 ( .A0(n2846), .A1(d_ff1_Z[30]), .B0(n2845), .B1(data_in[30]),
.Y(n1590) );
AOI2BB2XLTS U2456 ( .B0(n2830), .B1(n2829), .A0N(n2829), .A1N(
cont_iter_out[2]), .Y(n1618) );
INVX2TS U2457 ( .A(n1642), .Y(n1691) );
CLKBUFX2TS U2458 ( .A(n1686), .Y(n2620) );
INVX2TS U2459 ( .A(n3228), .Y(n1659) );
NOR2X1TS U2460 ( .A(n2314), .B(n2948), .Y(n2327) );
OR2X2TS U2461 ( .A(n2317), .B(n2316), .Y(n1641) );
OR2X2TS U2462 ( .A(n2314), .B(n2316), .Y(n1642) );
NOR2X2TS U2463 ( .A(n2196), .B(n2979), .Y(n1646) );
OR2X1TS U2464 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .B(
n2545), .Y(n1648) );
OR3X1TS U2465 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .B(
n3067), .C(n3068), .Y(n1652) );
INVX2TS U2466 ( .A(n1659), .Y(n1661) );
INVX2TS U2467 ( .A(n2434), .Y(n1662) );
INVX2TS U2468 ( .A(n1692), .Y(n1663) );
INVX2TS U2469 ( .A(n1692), .Y(n1664) );
INVX4TS U2470 ( .A(n1665), .Y(n1667) );
INVX2TS U2471 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .Y(
n1668) );
INVX2TS U2472 ( .A(n2434), .Y(n1669) );
INVX2TS U2473 ( .A(n1669), .Y(n1670) );
INVX2TS U2474 ( .A(n1669), .Y(n1671) );
INVX4TS U2475 ( .A(n1672), .Y(n1673) );
INVX2TS U2476 ( .A(n1652), .Y(n1675) );
INVX2TS U2477 ( .A(n1652), .Y(n1676) );
INVX2TS U2478 ( .A(n1909), .Y(n1677) );
INVX2TS U2479 ( .A(n1909), .Y(n1678) );
INVX2TS U2480 ( .A(n1636), .Y(n1679) );
INVX2TS U2481 ( .A(n1636), .Y(n1680) );
INVX2TS U2482 ( .A(n1648), .Y(n1681) );
INVX2TS U2483 ( .A(n1648), .Y(n1682) );
INVX2TS U2484 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(
n1683) );
INVX2TS U2485 ( .A(n1683), .Y(n1684) );
INVX2TS U2486 ( .A(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .Y(n1685)
);
INVX2TS U2487 ( .A(n1685), .Y(n1686) );
INVX4TS U2488 ( .A(n1642), .Y(n1689) );
OAI21X2TS U2489 ( .A0(n1634), .A1(n2377), .B0(n2366), .Y(n2397) );
OAI21X2TS U2490 ( .A0(n3171), .A1(n2377), .B0(n2376), .Y(n2411) );
OAI21X2TS U2491 ( .A0(n3107), .A1(n2423), .B0(n2352), .Y(n2436) );
OAI21X2TS U2492 ( .A0(n3138), .A1(n2423), .B0(n2405), .Y(n2431) );
OAI21X2TS U2493 ( .A0(n3091), .A1(n2423), .B0(n2422), .Y(n2439) );
OAI21X2TS U2494 ( .A0(n3092), .A1(n2423), .B0(n2363), .Y(n2393) );
OAI21X2TS U2495 ( .A0(n2423), .A1(n3106), .B0(n2328), .Y(n2418) );
OAI21XLTS U2496 ( .A0(n1684), .A1(n3090), .B0(n2267), .Y(n1049) );
OAI21XLTS U2497 ( .A0(n3083), .A1(n3013), .B0(n2474), .Y(n1152) );
CLKBUFX3TS U2498 ( .A(n1918), .Y(n1917) );
OAI31XLTS U2499 ( .A0(n2469), .A1(n3013), .A2(n2468), .B0(n2467), .Y(n1055)
);
AOI222X4TS U2500 ( .A0(n2897), .A1(d_ff2_Z[5]), .B0(n2102), .B1(d_ff1_Z[5]),
.C0(d_ff_Zn[5]), .C1(n2122), .Y(n2116) );
AOI222X4TS U2501 ( .A0(n2914), .A1(d_ff2_Z[9]), .B0(n2108), .B1(d_ff1_Z[9]),
.C0(d_ff_Zn[9]), .C1(n2122), .Y(n2121) );
AOI222X4TS U2502 ( .A0(n2871), .A1(d_ff2_Z[7]), .B0(n2108), .B1(d_ff1_Z[7]),
.C0(d_ff_Zn[7]), .C1(n2122), .Y(n2120) );
AOI222X4TS U2503 ( .A0(n2135), .A1(d_ff2_Z[30]), .B0(n2134), .B1(d_ff1_Z[30]), .C0(d_ff_Zn[30]), .C1(n2133), .Y(n2125) );
AOI222X4TS U2504 ( .A0(n2135), .A1(d_ff2_Z[29]), .B0(n2134), .B1(d_ff1_Z[29]), .C0(d_ff_Zn[29]), .C1(n2133), .Y(n2131) );
AOI222X4TS U2505 ( .A0(n2135), .A1(d_ff2_Z[27]), .B0(n2134), .B1(d_ff1_Z[27]), .C0(d_ff_Zn[27]), .C1(n2133), .Y(n2126) );
OAI211XLTS U2506 ( .A0(n2031), .A1(n2489), .B0(n2239), .C0(n2238), .Y(n1376)
);
OAI33X4TS U2507 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(
d_ff1_operation_out), .A2(n3133), .B0(n3085), .B1(n3070), .B2(
d_ff1_shift_region_flag_out[0]), .Y(n2201) );
AOI211X1TS U2508 ( .A0(cont_iter_out[1]), .A1(n2196), .B0(n2830), .C0(n2834),
.Y(n2089) );
INVX2TS U2509 ( .A(n1651), .Y(n1696) );
NOR2XLTS U2510 ( .A(n2617), .B(n2616), .Y(n2619) );
AOI21X2TS U2511 ( .A0(n2553), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[25]), .B0(n2543), .Y(n2616)
);
AOI21X2TS U2512 ( .A0(n2553), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]), .B0(n2543), .Y(n2609)
);
INVX2TS U2513 ( .A(n1650), .Y(n1697) );
NAND3X2TS U2514 ( .A(n2320), .B(n2319), .C(n2318), .Y(n2381) );
OAI21X2TS U2515 ( .A0(n2377), .A1(n3229), .B0(n1728), .Y(n2399) );
NAND2X4TS U2516 ( .A(n1668), .B(n1704), .Y(n2570) );
INVX2TS U2517 ( .A(n1635), .Y(n1698) );
NAND2BX2TS U2518 ( .AN(n1747), .B(n2947), .Y(n2948) );
NAND2X2TS U2519 ( .A(n1747), .B(n2947), .Y(n2316) );
AOI32X1TS U2520 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[4]),
.A1(n2947), .A2(n2824), .B0(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .B1(n2398), .Y(
n2180) );
NAND2X4TS U2521 ( .A(n3053), .B(n3066), .Y(n2947) );
AOI222X1TS U2522 ( .A0(n2285), .A1(data_output[23]), .B0(n2292), .B1(
d_ff_Yn[23]), .C0(n2291), .C1(d_ff_Xn[23]), .Y(n2269) );
AOI222X1TS U2523 ( .A0(n2285), .A1(data_output[20]), .B0(n2284), .B1(
d_ff_Yn[20]), .C0(n2291), .C1(d_ff_Xn[20]), .Y(n2270) );
AOI222X1TS U2524 ( .A0(n2285), .A1(data_output[19]), .B0(n2284), .B1(
d_ff_Yn[19]), .C0(n2287), .C1(d_ff_Xn[19]), .Y(n2283) );
AOI222X1TS U2525 ( .A0(n2285), .A1(data_output[21]), .B0(n2284), .B1(
d_ff_Yn[21]), .C0(n2291), .C1(d_ff_Xn[21]), .Y(n2268) );
AOI222X1TS U2526 ( .A0(n2285), .A1(data_output[18]), .B0(n2284), .B1(
d_ff_Yn[18]), .C0(n2287), .C1(d_ff_Xn[18]), .Y(n2278) );
AOI222X1TS U2527 ( .A0(n2285), .A1(data_output[15]), .B0(n2284), .B1(
d_ff_Yn[15]), .C0(n2287), .C1(d_ff_Xn[15]), .Y(n2256) );
AOI222X1TS U2528 ( .A0(n2216), .A1(data_output[22]), .B0(n2292), .B1(
d_ff_Yn[22]), .C0(n2291), .C1(d_ff_Xn[22]), .Y(n2293) );
AOI222X1TS U2529 ( .A0(n2254), .A1(data_output[30]), .B0(n2292), .B1(
d_ff_Yn[30]), .C0(n2206), .C1(d_ff_Xn[30]), .Y(n2207) );
AOI222X1TS U2530 ( .A0(n2254), .A1(data_output[29]), .B0(n2292), .B1(
d_ff_Yn[29]), .C0(n2291), .C1(d_ff_Xn[29]), .Y(n2271) );
AOI222X1TS U2531 ( .A0(n2254), .A1(data_output[26]), .B0(n2292), .B1(
d_ff_Yn[26]), .C0(n2291), .C1(d_ff_Xn[26]), .Y(n2276) );
AOI222X1TS U2532 ( .A0(n2254), .A1(data_output[25]), .B0(n2292), .B1(
d_ff_Yn[25]), .C0(n2291), .C1(d_ff_Xn[25]), .Y(n2274) );
AOI222X1TS U2533 ( .A0(n2254), .A1(data_output[24]), .B0(n2292), .B1(
d_ff_Yn[24]), .C0(n2291), .C1(d_ff_Xn[24]), .Y(n2273) );
AOI222X1TS U2534 ( .A0(n2289), .A1(data_output[4]), .B0(n2288), .B1(
d_ff_Yn[4]), .C0(n2206), .C1(d_ff_Xn[4]), .Y(n2214) );
AOI222X1TS U2535 ( .A0(n2285), .A1(data_output[17]), .B0(n2284), .B1(
d_ff_Yn[17]), .C0(n2287), .C1(d_ff_Xn[17]), .Y(n2282) );
AOI222X1TS U2536 ( .A0(n2285), .A1(data_output[13]), .B0(n2284), .B1(
d_ff_Yn[13]), .C0(n2287), .C1(d_ff_Xn[13]), .Y(n2279) );
AOI222X1TS U2537 ( .A0(n2289), .A1(data_output[6]), .B0(n2288), .B1(
d_ff_Yn[6]), .C0(n2199), .C1(d_ff_Xn[6]), .Y(n2220) );
AOI222X1TS U2538 ( .A0(n2289), .A1(data_output[8]), .B0(n2288), .B1(
d_ff_Yn[8]), .C0(n2206), .C1(d_ff_Xn[8]), .Y(n2213) );
AOI222X1TS U2539 ( .A0(n2285), .A1(data_output[16]), .B0(n2284), .B1(
d_ff_Yn[16]), .C0(n2287), .C1(d_ff_Xn[16]), .Y(n2286) );
AOI222X1TS U2540 ( .A0(n2289), .A1(data_output[11]), .B0(n2288), .B1(
d_ff_Yn[11]), .C0(n2287), .C1(d_ff_Xn[11]), .Y(n2277) );
AOI222X1TS U2541 ( .A0(n2285), .A1(data_output[14]), .B0(n2284), .B1(
d_ff_Yn[14]), .C0(n2287), .C1(d_ff_Xn[14]), .Y(n2281) );
AOI222X1TS U2542 ( .A0(n2289), .A1(data_output[12]), .B0(n2284), .B1(
d_ff_Yn[12]), .C0(n2287), .C1(d_ff_Xn[12]), .Y(n2280) );
AOI222X1TS U2543 ( .A0(n2289), .A1(data_output[10]), .B0(n2288), .B1(
d_ff_Yn[10]), .C0(n2287), .C1(d_ff_Xn[10]), .Y(n2290) );
AOI222X1TS U2544 ( .A0(n2216), .A1(data_output[2]), .B0(n2288), .B1(
d_ff_Yn[2]), .C0(n2206), .C1(d_ff_Xn[2]), .Y(n2215) );
AOI222X1TS U2545 ( .A0(n2289), .A1(data_output[3]), .B0(n2288), .B1(
d_ff_Yn[3]), .C0(n2199), .C1(d_ff_Xn[3]), .Y(n2221) );
AOI222X1TS U2546 ( .A0(n2254), .A1(data_output[0]), .B0(n2255), .B1(
d_ff_Yn[0]), .C0(n2206), .C1(d_ff_Xn[0]), .Y(n2212) );
AOI222X1TS U2547 ( .A0(n2289), .A1(data_output[7]), .B0(n2288), .B1(
d_ff_Yn[7]), .C0(n2206), .C1(d_ff_Xn[7]), .Y(n2218) );
AOI222X1TS U2548 ( .A0(n2289), .A1(data_output[9]), .B0(n2288), .B1(
d_ff_Yn[9]), .C0(n2206), .C1(d_ff_Xn[9]), .Y(n2211) );
AOI222X1TS U2549 ( .A0(n2216), .A1(data_output[1]), .B0(n2255), .B1(
d_ff_Yn[1]), .C0(n2206), .C1(d_ff_Xn[1]), .Y(n2217) );
CLKBUFX3TS U2550 ( .A(n2084), .Y(n1920) );
AOI222X1TS U2551 ( .A0(n2289), .A1(data_output[5]), .B0(n2288), .B1(
d_ff_Yn[5]), .C0(n2206), .C1(d_ff_Xn[5]), .Y(n2219) );
AOI222X1TS U2552 ( .A0(n2254), .A1(data_output[27]), .B0(n2292), .B1(
d_ff_Yn[27]), .C0(n2291), .C1(d_ff_Xn[27]), .Y(n2275) );
OR2X1TS U2553 ( .A(n3162), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]), .Y(
n1855) );
OR2X1TS U2554 ( .A(n3161), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]), .Y(
n1859) );
OR2X1TS U2555 ( .A(n3160), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]), .Y(
n1863) );
OR2X1TS U2556 ( .A(n3159), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]), .Y(
n1867) );
OAI222X1TS U2557 ( .A0(n3011), .A1(n3086), .B0(n1706), .B1(n3012), .C0(n3118), .C1(n3013), .Y(n1156) );
OAI21X1TS U2558 ( .A0(n2545), .A1(n3130), .B0(n2550), .Y(n2540) );
OAI21XLTS U2559 ( .A0(n3115), .A1(n2463), .B0(n2461), .Y(n1082) );
OAI21XLTS U2560 ( .A0(n3079), .A1(n2463), .B0(n2462), .Y(n1094) );
OAI21XLTS U2561 ( .A0(n2545), .A1(n3131), .B0(n2550), .Y(n2536) );
CLKBUFX3TS U2562 ( .A(n1920), .Y(n3227) );
OR2X1TS U2563 ( .A(d_ff2_Y[23]), .B(n2827), .Y(intadd_356_CI) );
AOI221X1TS U2564 ( .A0(n3118), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[25]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[26]), .B1(n3117), .C0(n1995),
.Y(n1999) );
AOI221X1TS U2565 ( .A0(n1655), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .B1(n1640), .C0(n2018), .Y(
n2023) );
AOI221X1TS U2566 ( .A0(n2494), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .B1(n3125), .C0(n2002),
.Y(n2007) );
AOI221X1TS U2567 ( .A0(n3124), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]), .B1(n2229), .C0(n2001),
.Y(n2008) );
NOR2X1TS U2568 ( .A(n2229), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]),
.Y(n1759) );
AOI221X1TS U2569 ( .A0(n2489), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]), .B1(n2491), .C0(n2012),
.Y(n2013) );
AOI221X1TS U2570 ( .A0(n3122), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]), .B1(n2233), .C0(n2009), .Y(
n2016) );
AOI32X1TS U2571 ( .A0(n2225), .A1(n1805), .A2(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .B1(n2451), .Y(n1806) );
AOI221X1TS U2572 ( .A0(n2451), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .B1(n3110), .C0(n2004),
.Y(n2005) );
AOI221X1TS U2573 ( .A0(n2223), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .B1(n3119), .C0(n2011),
.Y(n2014) );
OAI2BB2XLTS U2574 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]), .B1(
n1772), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .A1N(n3121),
.Y(n1774) );
AOI221X1TS U2575 ( .A0(n2482), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .B1(n3111), .C0(n2017), .Y(
n2024) );
AOI221X1TS U2576 ( .A0(n2227), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]), .B1(n2225), .C0(n2003),
.Y(n2006) );
OAI21X2TS U2577 ( .A0(n1934), .A1(n1840), .B0(n1839), .Y(n2731) );
NOR3X1TS U2578 ( .A(inst_CORDIC_FSM_v3_state_reg[5]), .B(
inst_CORDIC_FSM_v3_state_reg[0]), .C(inst_CORDIC_FSM_v3_state_reg[4]),
.Y(n1897) );
OAI211XLTS U2579 ( .A0(n2196), .A1(n2836), .B0(n2185), .C0(n2184), .Y(n1600)
);
OAI21XLTS U2580 ( .A0(n2195), .A1(n2190), .B0(n2087), .Y(n1609) );
CLKBUFX3TS U2581 ( .A(n1915), .Y(n1916) );
OAI211XLTS U2582 ( .A0(n2031), .A1(n2491), .B0(n2237), .C0(n2244), .Y(n1373)
);
NOR4BX2TS U2583 ( .AN(n2143), .B(n2147), .C(n2142), .D(n2141), .Y(n2146) );
INVX2TS U2584 ( .A(n1701), .Y(n1702) );
OAI21XLTS U2585 ( .A0(n3054), .A1(n3094), .B0(n2423), .Y(n1043) );
AOI211X2TS U2586 ( .A0(n2553), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]), .B0(n2531), .C0(n2525), .Y(n2588) );
NOR2X2TS U2587 ( .A(n3067), .B(n2550), .Y(n2531) );
AOI21X2TS U2588 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]), .A1(
n2547), .B0(n2540), .Y(n2598) );
AOI21X1TS U2589 ( .A0(n2553), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]), .B0(n2543), .Y(n1703)
);
OAI21XLTS U2590 ( .A0(n1941), .A1(n1940), .B0(n1939), .Y(n1943) );
NOR2XLTS U2591 ( .A(n1940), .B(n1935), .Y(n1874) );
NOR2X2TS U2592 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[4]), .Y(n1940) );
OR2X1TS U2593 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[11]), .Y(n2737) );
NOR2XLTS U2594 ( .A(n3157), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .Y(
n1828) );
NOR2X2TS U2595 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[7]), .Y(n1974) );
NOR2X2TS U2596 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[8]), .Y(n2798) );
OAI32X1TS U2597 ( .A0(n2829), .A1(n2826), .A2(n2827), .B0(n3098), .B1(n2829),
.Y(n1619) );
NOR3X4TS U2598 ( .A(n2826), .B(n3098), .C(n2827), .Y(n2829) );
AOI222X1TS U2599 ( .A0(n2254), .A1(data_output[28]), .B0(n2292), .B1(
d_ff_Yn[28]), .C0(n2291), .C1(d_ff_Xn[28]), .Y(n2272) );
OAI222X1TS U2600 ( .A0(n3011), .A1(n3134), .B0(n3084), .B1(n3012), .C0(n3069), .C1(n3013), .Y(n1157) );
NAND2X1TS U2601 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]), .B(
n1725), .Y(n2153) );
OAI21X2TS U2602 ( .A0(n3102), .A1(n2423), .B0(n2336), .Y(n2383) );
OAI21X2TS U2603 ( .A0(n3073), .A1(n2377), .B0(n2326), .Y(n2388) );
OAI21X2TS U2604 ( .A0(n3074), .A1(n2423), .B0(n2362), .Y(n2413) );
INVX2TS U2605 ( .A(n2620), .Y(n1704) );
INVX2TS U2606 ( .A(n2620), .Y(n1705) );
XNOR2X2TS U2607 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[31]), .B(
inst_FPU_PIPELINED_FPADDSUB_intAS), .Y(n2468) );
BUFX3TS U2608 ( .A(n2084), .Y(n1919) );
NOR2X4TS U2609 ( .A(n2828), .B(rst), .Y(n2084) );
OR2X1TS U2610 ( .A(d_ff2_X[23]), .B(n2827), .Y(intadd_357_CI) );
OAI21X1TS U2611 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .B0(n1736), .Y(n1737) );
AOI22X1TS U2612 ( .A0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n2809), .B0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(
n3266), .Y(n2819) );
AOI222X1TS U2613 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[4]), .A1(n3071), .B0(n1777), .B1(n1776), .C0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .C1(
n3126), .Y(n1779) );
OAI211XLTS U2614 ( .A0(n2442), .A1(n1670), .B0(n2420), .C0(n2419), .Y(n1313)
);
AOI21X2TS U2615 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]), .A1(
n2553), .B0(n2552), .Y(n2603) );
OAI31X1TS U2616 ( .A0(n2832), .A1(cont_var_out[1]), .A2(n3097), .B0(n2516),
.Y(n1615) );
OAI21XLTS U2617 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .A1(n3112),
.B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .Y(n1775) );
NOR2X1TS U2618 ( .A(n2227), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]),
.Y(n1803) );
NOR2X1TS U2619 ( .A(n2223), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]),
.Y(n1783) );
OAI21XLTS U2620 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .A1(n3124), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .Y(n1802) );
OAI21XLTS U2621 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .A1(n3114), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .Y(n1782) );
OA22X1TS U2622 ( .A0(n3078), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]),
.B0(n3111), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .Y(n1796)
);
OA22X1TS U2623 ( .A0(n2233), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]),
.B0(n3125), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .Y(n1814)
);
OR2X1TS U2624 ( .A(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .B(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n1708) );
OR2X1TS U2625 ( .A(n1707), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]), .Y(
n1710) );
AND2X2TS U2626 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[7]), .B(
n2263), .Y(n1711) );
CLKBUFX2TS U2627 ( .A(n2889), .Y(n2894) );
BUFX3TS U2628 ( .A(n2032), .Y(n2889) );
CLKBUFX2TS U2629 ( .A(n2243), .Y(n2066) );
BUFX3TS U2630 ( .A(n2030), .Y(n2243) );
BUFX3TS U2631 ( .A(n2031), .Y(n2983) );
NOR2XLTS U2632 ( .A(n1803), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]),
.Y(n1804) );
OAI21XLTS U2633 ( .A0(n2792), .A1(n2797), .B0(n2793), .Y(n1875) );
INVX2TS U2634 ( .A(n2624), .Y(n2626) );
OR2X1TS U2635 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n2683) );
OR2X1TS U2636 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n2635) );
OAI21XLTS U2637 ( .A0(n2545), .A1(n3128), .B0(n2550), .Y(n2546) );
NAND2X1TS U2638 ( .A(n2732), .B(n1710), .Y(n2778) );
NOR2BX1TS U2639 ( .AN(n2260), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[7]), .Y(n2261) );
INVX2TS U2640 ( .A(n2317), .Y(n2314) );
OAI21XLTS U2641 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[25]), .A1(
n1706), .B0(n2992), .Y(n2993) );
OAI21XLTS U2642 ( .A0(n2796), .A1(n2735), .B0(n2734), .Y(n2739) );
XOR2X1TS U2643 ( .A(n1893), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n1889) );
OAI21XLTS U2644 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[23]), .A1(
n3129), .B0(n3000), .Y(n3001) );
INVX2TS U2645 ( .A(n3014), .Y(n2303) );
BUFX3TS U2646 ( .A(n2983), .Y(n2253) );
BUFX3TS U2647 ( .A(n2330), .Y(n2824) );
INVX2TS U2648 ( .A(n1730), .Y(n1715) );
NOR2X2TS U2649 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n1734) );
NOR2X2TS U2650 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n1731) );
AND2X4TS U2651 ( .A(n1734), .B(n1731), .Y(n2139) );
NAND2X4TS U2652 ( .A(n2139), .B(n2138), .Y(n1722) );
OR2X8TS U2653 ( .A(n1722), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]), .Y(n2150) );
NOR2BX4TS U2654 ( .AN(n2151), .B(n2150), .Y(n1740) );
NOR2X8TS U2655 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .B(
n2137), .Y(n2157) );
INVX6TS U2656 ( .A(n2157), .Y(n1735) );
NOR3BX4TS U2657 ( .AN(n1725), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .C(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n2172) );
NAND2X1TS U2658 ( .A(n3096), .B(n3074), .Y(n2171) );
NOR2BX4TS U2659 ( .AN(n2172), .B(n2171), .Y(n1736) );
NOR2BX4TS U2660 ( .AN(n1736), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .Y(n2173) );
AOI21X1TS U2661 ( .A0(n3109), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n1716) );
AOI211X1TS U2662 ( .A0(n2173), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .B0(n1721), .C0(
n1720), .Y(n1727) );
OAI22X1TS U2663 ( .A0(n2153), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .B0(n3106), .B1(
n1722), .Y(n1738) );
AOI32X1TS U2664 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(
n1634), .A2(n1645), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .B1(n1634), .Y(n1723) );
AOI211X2TS U2665 ( .A0(n3102), .A1(n1723), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .C0(n2140), .Y(n1724) );
AOI211X2TS U2666 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]),
.A1(n2157), .B0(n1738), .C0(n1724), .Y(n2143) );
BUFX3TS U2667 ( .A(n2330), .Y(n2821) );
BUFX3TS U2668 ( .A(n2330), .Y(n2357) );
NOR2X1TS U2669 ( .A(n2357), .B(n3108), .Y(n2329) );
INVX2TS U2670 ( .A(n2329), .Y(n1729) );
INVX2TS U2671 ( .A(n1729), .Y(n2406) );
AOI211X4TS U2672 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[0]),
.A1(n2824), .B0(n2808), .C0(n2406), .Y(n2317) );
BUFX3TS U2673 ( .A(n2315), .Y(n2377) );
AOI21X1TS U2674 ( .A0(n2377), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]), .B0(n2824), .Y(
n1728) );
INVX2TS U2675 ( .A(n1729), .Y(n2417) );
AOI21X1TS U2676 ( .A0(n2317), .A1(n2399), .B0(n2417), .Y(n2949) );
BUFX3TS U2677 ( .A(n2330), .Y(n3053) );
INVX2TS U2678 ( .A(n2315), .Y(n2404) );
AOI21X1TS U2679 ( .A0(n1730), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n1732) );
OAI31X1TS U2680 ( .A0(n1732), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .A2(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(n1731), .Y(
n1733) );
INVX2TS U2681 ( .A(n1733), .Y(n1743) );
NAND3X4TS U2682 ( .A(n2178), .B(n3073), .C(n3102), .Y(n2174) );
OAI21X4TS U2683 ( .A0(n2152), .A1(n2174), .B0(n1737), .Y(n2177) );
NAND2X1TS U2684 ( .A(n1740), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[14]), .Y(n2149) );
AO22X4TS U2685 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[1]),
.A1(n3053), .B0(n2404), .B1(n2517), .Y(n1747) );
BUFX3TS U2686 ( .A(n1660), .Y(n3066) );
NAND2X1TS U2687 ( .A(n2406), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n1746) );
NAND2X1TS U2688 ( .A(n2361), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n1745) );
NAND2X1TS U2689 ( .A(n2330), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n1744) );
NAND3X1TS U2690 ( .A(n1746), .B(n1745), .C(n1744), .Y(n2371) );
INVX2TS U2691 ( .A(n2371), .Y(n2403) );
NAND2X1TS U2692 ( .A(n2417), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n1750) );
NAND2X1TS U2693 ( .A(n2361), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n1749) );
NAND2X1TS U2694 ( .A(n3053), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n1748) );
NAND3X1TS U2695 ( .A(n1750), .B(n1749), .C(n1748), .Y(n2400) );
INVX2TS U2696 ( .A(n2400), .Y(n2305) );
NOR2X2TS U2697 ( .A(n2948), .B(n2317), .Y(n1751) );
OAI22X1TS U2698 ( .A0(n2403), .A1(n1670), .B0(n2305), .B1(n1666), .Y(n1752)
);
AOI21X1TS U2699 ( .A0(n2349), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]), .B0(n1752), .Y(n1753)
);
OAI21X2TS U2700 ( .A0(n2949), .A1(n2316), .B0(n1753), .Y(n1321) );
NOR2X1TS U2701 ( .A(n3118), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[25]),
.Y(n1817) );
AOI22X1TS U2702 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[25]), .A1(n3118), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .B1(n1754), .Y(n1758) );
OAI21X1TS U2703 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[26]), .A1(n3117), .B0(n1755), .Y(n1818) );
OAI211X1TS U2704 ( .A0(n1758), .A1(n1818), .B0(n1757), .C0(n1756), .Y(n1763)
);
NOR2X1TS U2705 ( .A(n3140), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[30]),
.Y(n1761) );
INVX2TS U2706 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .Y(n2229) );
NOR3X1TS U2707 ( .A(n3100), .B(n1759), .C(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .Y(n1760) );
AOI221X1TS U2708 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[30]), .A1(
n3140), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]), .B1(n2229),
.C0(n1760), .Y(n1762) );
INVX2TS U2709 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .Y(n2233) );
INVX2TS U2710 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]), .Y(n2225) );
OAI21X1TS U2711 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]), .A1(n2225), .B0(n1805), .Y(n1809) );
AOI211X1TS U2712 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .A1(
n3099), .B0(n1808), .C0(n1809), .Y(n1765) );
INVX2TS U2713 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]), .Y(n2227) );
INVX2TS U2714 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]), .Y(n2223) );
AOI21X1TS U2715 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .A1(n3093), .B0(n1783), .Y(n1788) );
OAI2BB1X1TS U2716 ( .A0N(n3126), .A1N(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .Y(n1770) );
OAI22X1TS U2717 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[4]), .A1(n1770),
.B0(n3126), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .Y(n1781)
);
OAI2BB1X1TS U2718 ( .A0N(n3095), .A1N(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .Y(n1771) );
OAI22X1TS U2719 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .A1(n1771),
.B0(n3095), .B1(n1700), .Y(n1780) );
OAI211X1TS U2720 ( .A0(n3112), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .B0(n1774), .C0(n1773), .Y(n1777) );
AOI22X1TS U2721 ( .A0(n1700), .A1(n3095), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .B1(n3076), .Y(n1778) );
AOI22X1TS U2722 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]), .A1(n2223), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .B1(n1784), .Y(n1791) );
AOI21X1TS U2723 ( .A0(n1787), .A1(n1786), .B0(n1790), .Y(n1789) );
OAI2BB2XLTS U2724 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]), .B1(
n1802), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .A1N(n3124),
.Y(n1813) );
AOI22X1TS U2725 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]), .A1(n2227), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .B1(n1804), .Y(n1807) );
INVX2TS U2726 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .Y(n2451) );
OAI32X1TS U2727 ( .A0(n1809), .A1(n1808), .A2(n1807), .B0(n1806), .B1(n1808),
.Y(n1812) );
OAI2BB2XLTS U2728 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .B1(
n1810), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .A1N(n3125),
.Y(n1811) );
AOI211X1TS U2729 ( .A0(n1814), .A1(n1813), .B0(n1812), .C0(n1811), .Y(n1820)
);
NAND4BBX1TS U2730 ( .AN(n1818), .BN(n1817), .C(n1816), .D(n1815), .Y(n1819)
);
BUFX3TS U2731 ( .A(n2306), .Y(n3039) );
NOR2X4TS U2732 ( .A(n1824), .B(n3039), .Y(n1823) );
CLKBUFX2TS U2733 ( .A(n2306), .Y(n2447) );
BUFX3TS U2734 ( .A(n2447), .Y(n2820) );
AOI22X1TS U2735 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .A1(n2514), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[15]), .B1(n2820), .Y(n1826) );
BUFX3TS U2736 ( .A(n2702), .Y(n2701) );
NAND2X1TS U2737 ( .A(n3089), .B(n2767), .Y(n2773) );
NAND2X1TS U2738 ( .A(n3157), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .Y(
n1827) );
NOR2X1TS U2739 ( .A(n3156), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .Y(
n1925) );
NAND2X1TS U2740 ( .A(n3145), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .Y(
n1829) );
NOR2X1TS U2741 ( .A(n3155), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .Y(
n1948) );
NOR2X1TS U2742 ( .A(n3144), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .Y(
n1834) );
NOR2X1TS U2743 ( .A(n1948), .B(n1834), .Y(n1961) );
NOR2X1TS U2744 ( .A(n3154), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]), .Y(
n1964) );
NOR2X1TS U2745 ( .A(n3143), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .Y(
n1836) );
NOR2X1TS U2746 ( .A(n1964), .B(n1836), .Y(n1838) );
NAND2X1TS U2747 ( .A(n1961), .B(n1838), .Y(n1840) );
NAND2X1TS U2748 ( .A(n3155), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .Y(
n1949) );
NAND2X1TS U2749 ( .A(n3144), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .Y(
n1833) );
OAI21X1TS U2750 ( .A0(n1834), .A1(n1949), .B0(n1833), .Y(n1960) );
NAND2X1TS U2751 ( .A(n3154), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]), .Y(
n1963) );
NAND2X1TS U2752 ( .A(n3143), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .Y(
n1835) );
AOI21X1TS U2753 ( .A0(n1960), .A1(n1838), .B0(n1837), .Y(n1839) );
NOR2X1TS U2754 ( .A(n3153), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .Y(
n2749) );
NOR2X1TS U2755 ( .A(n3152), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]), .Y(
n1845) );
NOR2X2TS U2756 ( .A(n2778), .B(n1845), .Y(n1847) );
NAND2X1TS U2757 ( .A(n1644), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .Y(
n1841) );
NAND2X1TS U2758 ( .A(n3152), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]),
.Y(n1844) );
OAI21X1TS U2759 ( .A0(n2777), .A1(n1845), .B0(n1844), .Y(n1846) );
NAND2X1TS U2760 ( .A(n3151), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]),
.Y(n1848) );
NAND2X1TS U2761 ( .A(n3150), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]),
.Y(n1852) );
NAND2X1TS U2762 ( .A(n3149), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]),
.Y(n1856) );
NAND2X1TS U2763 ( .A(n3148), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]),
.Y(n1860) );
NAND2X1TS U2764 ( .A(n3147), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]),
.Y(n1864) );
NAND2X1TS U2765 ( .A(n3146), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]),
.Y(n1868) );
OR2X1TS U2766 ( .A(n3158), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]), .Y(
n1871) );
CLKAND2X2TS U2767 ( .A(n3158), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]),
.Y(n1870) );
NOR2X1TS U2768 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[3]), .Y(n2758) );
NAND2X1TS U2769 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[2]), .Y(n2771) );
NAND2X1TS U2770 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[3]), .Y(n2759) );
OAI21X1TS U2771 ( .A0(n2758), .A1(n2771), .B0(n2759), .Y(n1929) );
NOR2X2TS U2772 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[5]), .Y(n1935) );
NAND2X1TS U2773 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[4]), .Y(n1939) );
NAND2X1TS U2774 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[5]), .Y(n1936) );
OAI21X1TS U2775 ( .A0(n1935), .A1(n1939), .B0(n1936), .Y(n1873) );
NOR2X1TS U2776 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[6]), .Y(n1952) );
NOR2X1TS U2777 ( .A(n1952), .B(n1974), .Y(n1969) );
NOR2X2TS U2778 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[9]), .Y(n2792) );
NOR2X1TS U2779 ( .A(n2798), .B(n2792), .Y(n1876) );
NAND2X1TS U2780 ( .A(n1969), .B(n1876), .Y(n1878) );
NAND2X1TS U2781 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[6]), .Y(n1979) );
NAND2X1TS U2782 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[7]), .Y(n1975) );
OAI21X1TS U2783 ( .A0(n1974), .A1(n1979), .B0(n1975), .Y(n1968) );
NAND2X1TS U2784 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[8]), .Y(n2797) );
NAND2X1TS U2785 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[9]), .Y(n2793) );
AOI21X1TS U2786 ( .A0(n1968), .A1(n1876), .B0(n1875), .Y(n1877) );
NOR2X1TS U2787 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[10]), .Y(n2741) );
INVX2TS U2788 ( .A(n2741), .Y(n2751) );
NAND2X1TS U2789 ( .A(n2751), .B(n2737), .Y(n2785) );
NOR2X2TS U2790 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[12]), .Y(n2779) );
NOR2X1TS U2791 ( .A(n2785), .B(n2779), .Y(n1882) );
NAND2X1TS U2792 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[10]), .Y(n2750) );
INVX2TS U2793 ( .A(n2750), .Y(n1880) );
NAND2X1TS U2794 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[11]), .Y(n2736) );
INVX2TS U2795 ( .A(n2736), .Y(n1879) );
AOI21X1TS U2796 ( .A0(n2737), .A1(n1880), .B0(n1879), .Y(n2784) );
NAND2X1TS U2797 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[12]), .Y(n2780) );
OAI21X1TS U2798 ( .A0(n2784), .A1(n2779), .B0(n2780), .Y(n1881) );
AOI21X2TS U2799 ( .A0(n2740), .A1(n1882), .B0(n1881), .Y(n2727) );
NOR2X1TS U2800 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[13]), .Y(n2721) );
NAND2X1TS U2801 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[13]), .Y(n2722) );
NAND2X1TS U2802 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[14]), .Y(n2712) );
INVX2TS U2803 ( .A(n2712), .Y(n1883) );
NOR2X1TS U2804 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n2624) );
NAND2X1TS U2805 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n2625) );
NAND2X1TS U2806 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n2634) );
INVX2TS U2807 ( .A(n2634), .Y(n1884) );
NOR2X1TS U2808 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n2643) );
NAND2X1TS U2809 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n2644) );
NAND2X1TS U2810 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n2703) );
INVX2TS U2811 ( .A(n2703), .Y(n1885) );
NOR2X1TS U2812 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n2672) );
NAND2X1TS U2813 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n2673) );
NAND2X1TS U2814 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n2682) );
INVX2TS U2815 ( .A(n2682), .Y(n1886) );
NOR2X1TS U2816 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n2691) );
NAND2X1TS U2817 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n2692) );
NAND2X1TS U2818 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n2663) );
INVX2TS U2819 ( .A(n2663), .Y(n1887) );
NOR2X1TS U2820 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n2653) );
NAND2X1TS U2821 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n2654) );
NAND2X1TS U2822 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[24]), .Y(n1899) );
INVX2TS U2823 ( .A(n1899), .Y(n1888) );
INVX2TS U2824 ( .A(n1674), .Y(n3008) );
BUFX3TS U2825 ( .A(n3008), .Y(n2802) );
BUFX3TS U2826 ( .A(n3008), .Y(n2822) );
BUFX3TS U2827 ( .A(n2447), .Y(n2502) );
AOI22X1TS U2828 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]), .A1(n2458), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[11]), .B1(n2502), .Y(n1892) );
NAND2X1TS U2829 ( .A(n1893), .B(n3164), .Y(n1894) );
NOR3X2TS U2830 ( .A(inst_CORDIC_FSM_v3_state_reg[1]), .B(
inst_CORDIC_FSM_v3_state_reg[2]), .C(inst_CORDIC_FSM_v3_state_reg[6]),
.Y(n1896) );
NOR3BX1TS U2831 ( .AN(n1896), .B(inst_CORDIC_FSM_v3_state_reg[7]), .C(
inst_CORDIC_FSM_v3_state_reg[3]), .Y(n1895) );
NAND2X1TS U2832 ( .A(cont_var_out[1]), .B(n3097), .Y(n2029) );
OR2X2TS U2833 ( .A(n2029), .B(n3267), .Y(n2863) );
BUFX3TS U2834 ( .A(n2863), .Y(n2862) );
NOR4X2TS U2835 ( .A(inst_CORDIC_FSM_v3_state_reg[5]), .B(
inst_CORDIC_FSM_v3_state_reg[0]), .C(inst_CORDIC_FSM_v3_state_reg[3]),
.D(inst_CORDIC_FSM_v3_state_reg[4]), .Y(n1913) );
NAND3X1TS U2836 ( .A(inst_CORDIC_FSM_v3_state_reg[7]), .B(n1913), .C(n1896),
.Y(n2816) );
INVX2TS U2837 ( .A(n2816), .Y(ready_cordic) );
NAND2X1TS U2838 ( .A(cont_var_out[0]), .B(cont_var_out[1]), .Y(n2812) );
NOR4BX2TS U2839 ( .AN(n1896), .B(inst_CORDIC_FSM_v3_state_reg[7]), .C(
inst_CORDIC_FSM_v3_state_reg[5]), .D(inst_CORDIC_FSM_v3_state_reg[3]),
.Y(n2164) );
NAND3X2TS U2840 ( .A(inst_CORDIC_FSM_v3_state_reg[4]), .B(n2164), .C(n3101),
.Y(n2813) );
AND4X2TS U2841 ( .A(inst_CORDIC_FSM_v3_state_reg[3]), .B(n1897), .C(n1896),
.D(n3075), .Y(n2869) );
INVX2TS U2842 ( .A(n2869), .Y(n2840) );
NAND2X1TS U2843 ( .A(n1900), .B(n1899), .Y(n1903) );
INVX2TS U2844 ( .A(n1903), .Y(n1901) );
XNOR2X1TS U2845 ( .A(n1902), .B(n1901), .Y(n1907) );
XNOR2X1TS U2846 ( .A(n1904), .B(n1903), .Y(n1905) );
AOI22X1TS U2847 ( .A0(n1905), .A1(n1944), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]), .B1(n2822), .Y(
n1906) );
OAI2BB1X1TS U2848 ( .A0N(n2701), .A1N(n1907), .B0(n1906), .Y(n1008) );
NAND3X1TS U2849 ( .A(n3075), .B(n1913), .C(n3104), .Y(n2165) );
NOR3BX2TS U2850 ( .AN(inst_CORDIC_FSM_v3_state_reg[2]), .B(
inst_CORDIC_FSM_v3_state_reg[1]), .C(n2165), .Y(n2091) );
BUFX3TS U2851 ( .A(n2091), .Y(n2915) );
NOR2X2TS U2852 ( .A(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
n1643), .Y(n2809) );
NAND2X2TS U2853 ( .A(n2814), .B(n2813), .Y(n2167) );
AOI22X1TS U2854 ( .A0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n3132), .B0(n2167), .B1(n3266), .Y(n1908) );
OAI21XLTS U2855 ( .A0(n2809), .A1(n1908), .B0(n2817), .Y(n1628) );
NOR2X2TS U2856 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]),
.B(n3067), .Y(n2547) );
INVX2TS U2857 ( .A(n2547), .Y(n2551) );
NOR2X4TS U2858 ( .A(n1668), .B(n1649), .Y(n2590) );
NAND2X2TS U2859 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]),
.B(inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2), .Y(n2550) );
NOR2X1TS U2860 ( .A(n2590), .B(n2531), .Y(n2578) );
NAND2X2TS U2861 ( .A(n3067), .B(n3068), .Y(n2545) );
AOI22X1TS U2862 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]), .A1(
n1680), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]), .B1(n1682), .Y(n1910) );
OAI211X1TS U2863 ( .A0(n3130), .A1(n1909), .B0(n2578), .C0(n1910), .Y(n2573)
);
AOI21X1TS U2864 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]), .A1(
n1678), .B0(n2590), .Y(n1912) );
AOI22X1TS U2865 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]), .A1(
n1676), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[10]), .B1(n1682), .Y(n1911) );
OAI211X1TS U2866 ( .A0(n3131), .A1(n1636), .B0(n1912), .C0(n1911), .Y(n2574)
);
AOI22X1TS U2867 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(
n2573), .B0(n2574), .B1(n1704), .Y(n3031) );
INVX2TS U2868 ( .A(n2524), .Y(n2612) );
BUFX3TS U2869 ( .A(n2612), .Y(n2585) );
MXI2X1TS U2870 ( .A(n3031), .B(n1644), .S0(n2585), .Y(n881) );
INVX2TS U2871 ( .A(rst), .Y(n1172) );
CLKBUFX2TS U2872 ( .A(n1172), .Y(n1918) );
BUFX3TS U2873 ( .A(n1918), .Y(n3250) );
NAND2X1TS U2874 ( .A(n3075), .B(n1913), .Y(n1914) );
NOR4X4TS U2875 ( .A(n1914), .B(inst_CORDIC_FSM_v3_state_reg[2]), .C(
inst_CORDIC_FSM_v3_state_reg[1]), .D(n3104), .Y(n2828) );
CLKBUFX3TS U2876 ( .A(n2084), .Y(n1921) );
BUFX3TS U2877 ( .A(n1919), .Y(n3199) );
BUFX3TS U2878 ( .A(n3203), .Y(n3198) );
BUFX3TS U2879 ( .A(n3202), .Y(n3214) );
BUFX3TS U2880 ( .A(n3204), .Y(n3197) );
BUFX3TS U2881 ( .A(n1917), .Y(n3249) );
BUFX3TS U2882 ( .A(n3208), .Y(n3201) );
BUFX3TS U2883 ( .A(n3208), .Y(n3216) );
CLKBUFX2TS U2884 ( .A(n1172), .Y(n1915) );
BUFX3TS U2885 ( .A(n1915), .Y(n3238) );
BUFX3TS U2886 ( .A(n1918), .Y(n3245) );
BUFX3TS U2887 ( .A(n1916), .Y(n3239) );
BUFX3TS U2888 ( .A(n1916), .Y(n3240) );
BUFX3TS U2889 ( .A(n1917), .Y(n3244) );
BUFX3TS U2890 ( .A(n1915), .Y(n3241) );
BUFX3TS U2891 ( .A(n1918), .Y(n3243) );
BUFX3TS U2892 ( .A(n1918), .Y(n3242) );
BUFX3TS U2893 ( .A(n1917), .Y(n3248) );
BUFX3TS U2894 ( .A(n1917), .Y(n3247) );
BUFX3TS U2895 ( .A(n1917), .Y(n3246) );
BUFX3TS U2896 ( .A(n1919), .Y(n3210) );
BUFX3TS U2897 ( .A(n1915), .Y(n3230) );
BUFX3TS U2898 ( .A(n1915), .Y(n3231) );
BUFX3TS U2899 ( .A(n1916), .Y(n3232) );
BUFX3TS U2900 ( .A(n1915), .Y(n3233) );
BUFX3TS U2901 ( .A(n1921), .Y(n3211) );
BUFX3TS U2902 ( .A(n1916), .Y(n3234) );
BUFX3TS U2903 ( .A(n1916), .Y(n3235) );
BUFX3TS U2904 ( .A(n1916), .Y(n3236) );
BUFX3TS U2905 ( .A(n1916), .Y(n3237) );
BUFX3TS U2906 ( .A(n3203), .Y(n3226) );
BUFX3TS U2907 ( .A(n1917), .Y(n3251) );
BUFX3TS U2908 ( .A(n1917), .Y(n3252) );
BUFX3TS U2909 ( .A(n1916), .Y(n3264) );
BUFX3TS U2910 ( .A(n3264), .Y(n3258) );
BUFX3TS U2911 ( .A(n3204), .Y(n3212) );
BUFX3TS U2912 ( .A(n1918), .Y(n3253) );
BUFX3TS U2913 ( .A(n3203), .Y(n3217) );
BUFX3TS U2914 ( .A(n3208), .Y(n3213) );
BUFX3TS U2915 ( .A(n3208), .Y(n3218) );
BUFX3TS U2916 ( .A(n1917), .Y(n3265) );
BUFX3TS U2917 ( .A(n3265), .Y(n3261) );
BUFX3TS U2918 ( .A(n3264), .Y(n3259) );
BUFX3TS U2919 ( .A(n3265), .Y(n3260) );
BUFX3TS U2920 ( .A(n1172), .Y(n3254) );
BUFX3TS U2921 ( .A(n1920), .Y(n3205) );
BUFX3TS U2922 ( .A(n3203), .Y(n3220) );
BUFX3TS U2923 ( .A(n1919), .Y(n3219) );
BUFX3TS U2924 ( .A(n3203), .Y(n3206) );
BUFX3TS U2925 ( .A(n1919), .Y(n3194) );
BUFX3TS U2926 ( .A(n1921), .Y(n3222) );
BUFX3TS U2927 ( .A(n3264), .Y(n3255) );
BUFX3TS U2928 ( .A(n3265), .Y(n3263) );
BUFX3TS U2929 ( .A(n3202), .Y(n3215) );
BUFX3TS U2930 ( .A(n1921), .Y(n3195) );
BUFX3TS U2931 ( .A(n3202), .Y(n3223) );
BUFX3TS U2932 ( .A(n3264), .Y(n3257) );
BUFX3TS U2933 ( .A(n3204), .Y(n3225) );
BUFX3TS U2934 ( .A(n3202), .Y(n3221) );
BUFX3TS U2935 ( .A(n1920), .Y(n3188) );
BUFX3TS U2936 ( .A(n3208), .Y(n3224) );
BUFX3TS U2937 ( .A(n3204), .Y(n3209) );
BUFX3TS U2938 ( .A(n1920), .Y(n3189) );
BUFX3TS U2939 ( .A(n1920), .Y(n3191) );
BUFX3TS U2940 ( .A(n1920), .Y(n3186) );
BUFX3TS U2941 ( .A(n3264), .Y(n3256) );
BUFX3TS U2942 ( .A(n3265), .Y(n3262) );
BUFX3TS U2943 ( .A(n1920), .Y(n3190) );
BUFX3TS U2944 ( .A(n1920), .Y(n3187) );
INVX2TS U2945 ( .A(n3170), .Y(n1922) );
INVX2TS U2946 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_5), .Y(
n3057) );
BUFX3TS U2947 ( .A(n3057), .Y(n3051) );
BUFX3TS U2948 ( .A(n3057), .Y(n3040) );
CLKBUFX2TS U2949 ( .A(n3057), .Y(n3064) );
INVX2TS U2950 ( .A(n3064), .Y(n3065) );
BUFX3TS U2951 ( .A(n2524), .Y(n2523) );
BUFX3TS U2952 ( .A(n2524), .Y(n3037) );
INVX2TS U2953 ( .A(n1923), .Y(n2762) );
INVX2TS U2954 ( .A(n1940), .Y(n1926) );
NAND2X1TS U2955 ( .A(n1926), .B(n1939), .Y(n1930) );
INVX2TS U2956 ( .A(n1930), .Y(n1927) );
XNOR2X1TS U2957 ( .A(n1928), .B(n1927), .Y(n1933) );
INVX2TS U2958 ( .A(n1929), .Y(n1941) );
XOR2X1TS U2959 ( .A(n1941), .B(n1930), .Y(n1931) );
BUFX3TS U2960 ( .A(n1944), .Y(n2803) );
AOI22X1TS U2961 ( .A0(n1931), .A1(n2803), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .B1(n2802), .Y(n1932) );
OAI2BB1X1TS U2962 ( .A0N(n2702), .A1N(n1933), .B0(n1932), .Y(n1038) );
INVX2TS U2963 ( .A(n1934), .Y(n1962) );
INVX2TS U2964 ( .A(n1935), .Y(n1937) );
NAND2X1TS U2965 ( .A(n1937), .B(n1936), .Y(n1942) );
INVX2TS U2966 ( .A(n1942), .Y(n1938) );
XNOR2X1TS U2967 ( .A(n1962), .B(n1938), .Y(n1947) );
XNOR2X1TS U2968 ( .A(n1943), .B(n1942), .Y(n1945) );
BUFX3TS U2969 ( .A(n1944), .Y(n2744) );
AOI22X1TS U2970 ( .A0(n1945), .A1(n2744), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .B1(n2802), .Y(n1946) );
OAI2BB1X1TS U2971 ( .A0N(n2702), .A1N(n1947), .B0(n1946), .Y(n1037) );
INVX2TS U2972 ( .A(n1948), .Y(n1951) );
INVX2TS U2973 ( .A(n1949), .Y(n1950) );
AOI21X1TS U2974 ( .A0(n1962), .A1(n1951), .B0(n1950), .Y(n1954) );
INVX2TS U2975 ( .A(n1952), .Y(n1981) );
NAND2X1TS U2976 ( .A(n1981), .B(n1979), .Y(n1956) );
INVX2TS U2977 ( .A(n1956), .Y(n1953) );
INVX2TS U2978 ( .A(n1955), .Y(n1982) );
XNOR2X1TS U2979 ( .A(n1982), .B(n1956), .Y(n1957) );
AOI22X1TS U2980 ( .A0(n1957), .A1(n2803), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .B1(n2802), .Y(n1958) );
OAI2BB1X1TS U2981 ( .A0N(n2702), .A1N(n1959), .B0(n1958), .Y(n1036) );
AOI21X1TS U2982 ( .A0(n1962), .A1(n1961), .B0(n1960), .Y(n1978) );
INVX2TS U2983 ( .A(n2798), .Y(n1965) );
NAND2X1TS U2984 ( .A(n1965), .B(n2797), .Y(n1970) );
INVX2TS U2985 ( .A(n1970), .Y(n1966) );
XNOR2X1TS U2986 ( .A(n1967), .B(n1966), .Y(n1973) );
AOI21X1TS U2987 ( .A0(n1982), .A1(n1969), .B0(n1968), .Y(n2799) );
XOR2X1TS U2988 ( .A(n2799), .B(n1970), .Y(n1971) );
AOI22X1TS U2989 ( .A0(n1971), .A1(n2803), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .B1(n2802), .Y(n1972) );
OAI2BB1X1TS U2990 ( .A0N(n2702), .A1N(n1973), .B0(n1972), .Y(n1034) );
INVX2TS U2991 ( .A(n1974), .Y(n1976) );
NAND2X1TS U2992 ( .A(n1976), .B(n1975), .Y(n1983) );
INVX2TS U2993 ( .A(n1983), .Y(n1977) );
INVX2TS U2994 ( .A(n1979), .Y(n1980) );
AOI21X1TS U2995 ( .A0(n1982), .A1(n1981), .B0(n1980), .Y(n1984) );
XOR2X1TS U2996 ( .A(n1984), .B(n1983), .Y(n1985) );
AOI22X1TS U2997 ( .A0(n1985), .A1(n2803), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .B1(n2802), .Y(n1986) );
OAI2BB1X1TS U2998 ( .A0N(n2702), .A1N(n1987), .B0(n1986), .Y(n1035) );
BUFX3TS U2999 ( .A(n3057), .Y(n3061) );
INVX2TS U3000 ( .A(n3061), .Y(n3010) );
NAND2X1TS U3001 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[25]), .B(n1706), .Y(n2992) );
NAND2X1TS U3002 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[23]), .B(n3129), .Y(n3000) );
INVX2TS U3003 ( .A(n3000), .Y(n2998) );
NOR2X1TS U3004 ( .A(n1657), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[24]),
.Y(n2996) );
OAI22X1TS U3005 ( .A0(n2998), .A1(n2996), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[24]), .B1(n3084), .Y(n2994)
);
AOI22X1TS U3006 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[25]), .A1(
n3136), .B0(n2992), .B1(n2994), .Y(n3002) );
NOR2X1TS U3007 ( .A(n1658), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[26]),
.Y(n3003) );
AOI21X1TS U3008 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[26]), .A1(
n1658), .B0(n3003), .Y(n1988) );
XNOR2X1TS U3009 ( .A(n3002), .B(n1988), .Y(n1989) );
CLKBUFX2TS U3010 ( .A(n2869), .Y(n2867) );
BUFX3TS U3011 ( .A(n2867), .Y(n2879) );
CLKBUFX2TS U3012 ( .A(n2869), .Y(n2903) );
INVX2TS U3013 ( .A(n2903), .Y(n2872) );
BUFX3TS U3014 ( .A(n2867), .Y(n2870) );
INVX2TS U3015 ( .A(n2903), .Y(n2988) );
BUFX3TS U3016 ( .A(n2867), .Y(n2929) );
INVX2TS U3017 ( .A(n2903), .Y(n2919) );
INVX2TS U3018 ( .A(n2869), .Y(n2979) );
BUFX3TS U3019 ( .A(n2867), .Y(n2938) );
AOI22X1TS U3020 ( .A0(n1698), .A1(n2841), .B0(d_ff3_LUT_out[1]), .B1(n2834),
.Y(n1990) );
BUFX3TS U3021 ( .A(n2869), .Y(n2842) );
NOR2X2TS U3022 ( .A(n2830), .B(n3072), .Y(n2183) );
NAND2X1TS U3023 ( .A(n1990), .B(n2187), .Y(n1595) );
NOR2X4TS U3024 ( .A(n3072), .B(intadd_356_B_1_), .Y(n2195) );
BUFX3TS U3025 ( .A(n2869), .Y(n2940) );
NAND2X2TS U3026 ( .A(n2940), .B(cont_iter_out[1]), .Y(n2190) );
INVX2TS U3027 ( .A(n2190), .Y(n2186) );
AOI22X1TS U3028 ( .A0(n2839), .A1(n2186), .B0(d_ff3_LUT_out[0]), .B1(n2868),
.Y(n1991) );
OAI211X1TS U3029 ( .A0(cont_iter_out[3]), .A1(n2827), .B0(n1698), .C0(
intadd_356_B_1_), .Y(n2162) );
NAND2X1TS U3030 ( .A(n1991), .B(n2162), .Y(n1594) );
AOI22X1TS U3031 ( .A0(n2842), .A1(n2183), .B0(d_ff3_LUT_out[12]), .B1(n2834),
.Y(n1992) );
NAND2X1TS U3032 ( .A(n2186), .B(n2841), .Y(n2193) );
NAND2X1TS U3033 ( .A(n1992), .B(n2193), .Y(n1605) );
INVX2TS U3034 ( .A(n2468), .Y(n1993) );
AOI221X1TS U3035 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[31]), .A1(
n1993), .B0(n3137), .B1(n2468), .C0(n2820), .Y(n3038) );
OAI22X1TS U3036 ( .A0(n3120), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[0]),
.B0(n3069), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .Y(n1994)
);
AOI221X1TS U3037 ( .A0(n3120), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[0]), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .B1(n3069), .C0(n1994), .Y(
n2000) );
OAI22X1TS U3038 ( .A0(n3118), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[25]), .B0(n3117), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[26]), .Y(n1995) );
INVX2TS U3039 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .Y(n2511) );
OAI22X1TS U3040 ( .A0(n2511), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .B0(n1656), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[28]), .Y(n1996) );
AOI221X1TS U3041 ( .A0(n2511), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[28]), .B1(n1656), .C0(n1996),
.Y(n1998) );
AOI22X1TS U3042 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .A1(n3126),
.B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[5]), .B1(n3103), .Y(n1997)
);
OAI22X1TS U3043 ( .A0(n3124), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .B0(n3083), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]), .Y(n2001) );
INVX2TS U3044 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .Y(n2494) );
OAI22X1TS U3045 ( .A0(n2494), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .B0(n3125), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .Y(n2002) );
OAI22X1TS U3046 ( .A0(n3115), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]), .B0(n3079), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]), .Y(n2003) );
OAI22X1TS U3047 ( .A0(n3116), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .B0(n3110), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .Y(n2004) );
OAI22X1TS U3048 ( .A0(n3122), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]),
.B0(n3080), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]), .Y(n2009)
);
OAI22X1TS U3049 ( .A0(n3123), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]),
.B0(n1654), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .Y(n2010)
);
AOI221X1TS U3050 ( .A0(n3123), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .B1(n1654), .C0(n2010), .Y(
n2015) );
OAI22X1TS U3051 ( .A0(n3113), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]), .B0(n3119), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .Y(n2011) );
INVX2TS U3052 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .Y(n2489) );
INVX2TS U3053 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .Y(n2491) );
OAI22X1TS U3054 ( .A0(n2489), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .B0(n2491), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]), .Y(n2012) );
INVX2TS U3055 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[1]), .Y(n2482) );
OAI22X1TS U3056 ( .A0(n2482), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]),
.B0(n3111), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .Y(n2017)
);
OAI22X1TS U3057 ( .A0(n1655), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]),
.B0(n1640), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .Y(n2018)
);
OAI22X1TS U3058 ( .A0(n1653), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]),
.B0(n3105), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]), .Y(n2019)
);
AOI221X1TS U3059 ( .A0(n1653), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]), .B1(n3105), .C0(n2019), .Y(
n2022) );
OAI22X1TS U3060 ( .A0(n3112), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]),
.B0(n1699), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[7]), .Y(n2020)
);
AOI221X1TS U3061 ( .A0(n3112), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[7]), .B1(n1699), .C0(n2020), .Y(
n2021) );
NOR4X1TS U3062 ( .A(n2028), .B(n2027), .C(n2026), .D(n2025), .Y(n2469) );
NOR2X2TS U3063 ( .A(n2975), .B(n2029), .Y(n2030) );
AOI22X1TS U3064 ( .A0(d_ff2_Y[4]), .A1(n2961), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .B1(n2965), .Y(n2035) );
NOR2X2TS U3065 ( .A(n2975), .B(n2812), .Y(n2032) );
BUFX3TS U3066 ( .A(n2894), .Y(n2962) );
NOR3X1TS U3067 ( .A(cont_var_out[1]), .B(n3097), .C(n2975), .Y(n2033) );
AOI22X1TS U3068 ( .A0(n2962), .A1(d_ff2_Z[4]), .B0(n2062), .B1(d_ff2_X[4]),
.Y(n2034) );
NAND2X1TS U3069 ( .A(n2035), .B(n2034), .Y(n1266) );
INVX2TS U3070 ( .A(n2983), .Y(n2943) );
AOI22X1TS U3071 ( .A0(d_ff2_Y[0]), .A1(n2961), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[0]), .B1(n2916), .Y(n2037) );
AOI22X1TS U3072 ( .A0(n2962), .A1(d_ff2_Z[0]), .B0(n2062), .B1(d_ff2_X[0]),
.Y(n2036) );
NAND2X1TS U3073 ( .A(n2037), .B(n2036), .Y(n1274) );
AOI22X1TS U3074 ( .A0(d_ff2_Y[16]), .A1(n2930), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .B1(n2079), .Y(n2039) );
BUFX3TS U3075 ( .A(n2894), .Y(n2966) );
AOI22X1TS U3076 ( .A0(n2966), .A1(d_ff2_Z[16]), .B0(n2063), .B1(d_ff2_X[16]),
.Y(n2038) );
NAND2X1TS U3077 ( .A(n2039), .B(n2038), .Y(n1242) );
AOI22X1TS U3078 ( .A0(d_ff2_Y[9]), .A1(n2066), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .B1(n2965), .Y(n2041) );
AOI22X1TS U3079 ( .A0(n2966), .A1(d_ff2_Z[9]), .B0(n2063), .B1(d_ff2_X[9]),
.Y(n2040) );
NAND2X1TS U3080 ( .A(n2041), .B(n2040), .Y(n1256) );
AOI22X1TS U3081 ( .A0(d_ff2_Y[2]), .A1(n2961), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .B1(n2943), .Y(n2043) );
AOI22X1TS U3082 ( .A0(n2962), .A1(d_ff2_Z[2]), .B0(n2209), .B1(d_ff2_X[2]),
.Y(n2042) );
NAND2X1TS U3083 ( .A(n2043), .B(n2042), .Y(n1270) );
AOI22X1TS U3084 ( .A0(d_ff2_Y[1]), .A1(n2961), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .B1(n2916), .Y(n2045) );
AOI22X1TS U3085 ( .A0(n2962), .A1(d_ff2_Z[1]), .B0(n2209), .B1(d_ff2_X[1]),
.Y(n2044) );
NAND2X1TS U3086 ( .A(n2045), .B(n2044), .Y(n1272) );
AOI22X1TS U3087 ( .A0(d_ff2_Y[14]), .A1(n2961), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]), .B1(n2079), .Y(n2047) );
AOI22X1TS U3088 ( .A0(n2966), .A1(d_ff2_Z[14]), .B0(n2063), .B1(d_ff2_X[14]),
.Y(n2046) );
NAND2X1TS U3089 ( .A(n2047), .B(n2046), .Y(n1246) );
AOI22X1TS U3090 ( .A0(d_ff2_Y[11]), .A1(n2030), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]), .B1(n2965), .Y(n2049) );
AOI22X1TS U3091 ( .A0(n2966), .A1(d_ff2_Z[11]), .B0(n2063), .B1(d_ff2_X[11]),
.Y(n2048) );
NAND2X1TS U3092 ( .A(n2049), .B(n2048), .Y(n1252) );
AOI22X1TS U3093 ( .A0(d_ff2_Y[12]), .A1(n2066), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .B1(n2965), .Y(n2051) );
AOI22X1TS U3094 ( .A0(n2966), .A1(d_ff2_Z[12]), .B0(n2063), .B1(d_ff2_X[12]),
.Y(n2050) );
NAND2X1TS U3095 ( .A(n2051), .B(n2050), .Y(n1250) );
AOI22X1TS U3096 ( .A0(d_ff2_Y[17]), .A1(n2930), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]), .B1(n2079), .Y(n2053) );
AOI22X1TS U3097 ( .A0(n2966), .A1(d_ff2_Z[17]), .B0(n2063), .B1(d_ff2_X[17]),
.Y(n2052) );
NAND2X1TS U3098 ( .A(n2053), .B(n2052), .Y(n1240) );
AOI22X1TS U3099 ( .A0(d_ff2_Y[8]), .A1(n2030), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]), .B1(n2965), .Y(n2055) );
AOI22X1TS U3100 ( .A0(n2962), .A1(d_ff2_Z[8]), .B0(n2063), .B1(d_ff2_X[8]),
.Y(n2054) );
NAND2X1TS U3101 ( .A(n2055), .B(n2054), .Y(n1258) );
AOI22X1TS U3102 ( .A0(d_ff2_Y[15]), .A1(n2930), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .B1(n2079), .Y(n2057) );
AOI22X1TS U3103 ( .A0(n2966), .A1(d_ff2_Z[15]), .B0(n2063), .B1(d_ff2_X[15]),
.Y(n2056) );
NAND2X1TS U3104 ( .A(n2057), .B(n2056), .Y(n1244) );
AOI22X1TS U3105 ( .A0(d_ff2_Y[13]), .A1(n2030), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .B1(n2079), .Y(n2059) );
AOI22X1TS U3106 ( .A0(n2966), .A1(d_ff2_Z[13]), .B0(n2063), .B1(d_ff2_X[13]),
.Y(n2058) );
NAND2X1TS U3107 ( .A(n2059), .B(n2058), .Y(n1248) );
AOI22X1TS U3108 ( .A0(d_ff2_Y[3]), .A1(n2961), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .B1(n2981), .Y(n2061) );
AOI22X1TS U3109 ( .A0(n2962), .A1(d_ff2_Z[3]), .B0(n2209), .B1(d_ff2_X[3]),
.Y(n2060) );
NAND2X1TS U3110 ( .A(n2061), .B(n2060), .Y(n1268) );
BUFX3TS U3111 ( .A(n2243), .Y(n2976) );
AOI22X1TS U3112 ( .A0(d_ff2_Y[29]), .A1(n2976), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]), .B1(n2975), .Y(n2065) );
BUFX3TS U3113 ( .A(n2062), .Y(n2063) );
AOI22X1TS U3114 ( .A0(n2962), .A1(d_ff2_Z[29]), .B0(n2062), .B1(d_ff2_X[29]),
.Y(n2064) );
NAND2X1TS U3115 ( .A(n2065), .B(n2064), .Y(n1216) );
AOI22X1TS U3116 ( .A0(d_ff2_Y[26]), .A1(n2971), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[26]), .B1(n2975), .Y(n2068) );
AOI22X1TS U3117 ( .A0(n2032), .A1(d_ff2_Z[26]), .B0(n2972), .B1(d_ff2_X[26]),
.Y(n2067) );
NAND2X1TS U3118 ( .A(n2068), .B(n2067), .Y(n1222) );
AOI22X1TS U3119 ( .A0(d_ff2_Y[22]), .A1(n2971), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]), .B1(n2079), .Y(n2070) );
AOI22X1TS U3120 ( .A0(n2894), .A1(d_ff2_Z[22]), .B0(n2972), .B1(d_ff2_X[22]),
.Y(n2069) );
NAND2X1TS U3121 ( .A(n2070), .B(n2069), .Y(n1230) );
AOI22X1TS U3122 ( .A0(d_ff2_Y[19]), .A1(n2930), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .B1(n2965), .Y(n2072) );
AOI22X1TS U3123 ( .A0(n2894), .A1(d_ff2_Z[19]), .B0(n2972), .B1(d_ff2_X[19]),
.Y(n2071) );
NAND2X1TS U3124 ( .A(n2072), .B(n2071), .Y(n1236) );
AOI22X1TS U3125 ( .A0(d_ff2_Y[18]), .A1(n2930), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]), .B1(n2079), .Y(n2074) );
AOI22X1TS U3126 ( .A0(n2966), .A1(d_ff2_Z[18]), .B0(n2972), .B1(d_ff2_X[18]),
.Y(n2073) );
NAND2X1TS U3127 ( .A(n2074), .B(n2073), .Y(n1238) );
AOI22X1TS U3128 ( .A0(d_ff2_Y[20]), .A1(n2971), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .B1(n2079), .Y(n2076) );
AOI22X1TS U3129 ( .A0(n2900), .A1(d_ff2_Z[20]), .B0(n2972), .B1(d_ff2_X[20]),
.Y(n2075) );
NAND2X1TS U3130 ( .A(n2076), .B(n2075), .Y(n1234) );
AOI22X1TS U3131 ( .A0(d_ff2_Y[21]), .A1(n2971), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .B1(n2079), .Y(n2078) );
AOI22X1TS U3132 ( .A0(n2900), .A1(d_ff2_Z[21]), .B0(n2972), .B1(d_ff2_X[21]),
.Y(n2077) );
NAND2X1TS U3133 ( .A(n2078), .B(n2077), .Y(n1232) );
AOI22X1TS U3134 ( .A0(d_ff2_Y[23]), .A1(n2971), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .B1(n2079), .Y(n2081) );
AOI22X1TS U3135 ( .A0(n2894), .A1(d_ff2_Z[23]), .B0(n2972), .B1(d_ff2_X[23]),
.Y(n2080) );
NAND2X1TS U3136 ( .A(n2081), .B(n2080), .Y(n1228) );
AOI22X1TS U3137 ( .A0(d_ff2_Y[27]), .A1(n2971), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .B1(n2975), .Y(n2083) );
AOI22X1TS U3138 ( .A0(n2889), .A1(d_ff2_Z[27]), .B0(n2972), .B1(d_ff2_X[27]),
.Y(n2082) );
NAND2X1TS U3139 ( .A(n2083), .B(n2082), .Y(n1220) );
BUFX3TS U3140 ( .A(n2084), .Y(n3204) );
BUFX3TS U3141 ( .A(n2084), .Y(n3203) );
BUFX3TS U3142 ( .A(n2084), .Y(n3202) );
BUFX3TS U3143 ( .A(n3227), .Y(n3200) );
BUFX3TS U3144 ( .A(n3227), .Y(n3196) );
BUFX3TS U3145 ( .A(n3227), .Y(n3193) );
BUFX3TS U3146 ( .A(n3227), .Y(n3207) );
BUFX3TS U3147 ( .A(n3227), .Y(n3192) );
BUFX3TS U3148 ( .A(n2084), .Y(n3208) );
AOI22X1TS U3149 ( .A0(n1646), .A1(d_ff2_Y[23]), .B0(d_ff3_sh_y_out[23]),
.B1(n2866), .Y(n2085) );
AOI22X1TS U3150 ( .A0(n1646), .A1(d_ff2_X[23]), .B0(d_ff3_sh_x_out[23]),
.B1(n2868), .Y(n2086) );
AOI22X1TS U3151 ( .A0(n2842), .A1(n2839), .B0(d_ff3_LUT_out[21]), .B1(n2834),
.Y(n2087) );
INVX2TS U3152 ( .A(n2195), .Y(n2838) );
NAND2X1TS U3153 ( .A(n2196), .B(n2838), .Y(n2161) );
AOI22X1TS U3154 ( .A0(n1646), .A1(n2195), .B0(d_ff3_LUT_out[23]), .B1(n2834),
.Y(n2088) );
NAND2X1TS U3155 ( .A(n2196), .B(n2830), .Y(n2835) );
AOI21X1TS U3156 ( .A0(d_ff3_LUT_out[25]), .A1(n2840), .B0(n2089), .Y(n2090)
);
OAI31X1TS U3157 ( .A0(cont_iter_out[3]), .A1(n2190), .A2(n2835), .B0(n2090),
.Y(n1612) );
INVX2TS U3158 ( .A(n2874), .Y(n2112) );
NAND4X1TS U3159 ( .A(n3098), .B(n2827), .C(n3072), .D(intadd_356_B_1_), .Y(
n2092) );
NOR2X2TS U3160 ( .A(n2135), .B(n2092), .Y(n2102) );
BUFX3TS U3161 ( .A(n2102), .Y(n2114) );
BUFX3TS U3162 ( .A(n2906), .Y(n2104) );
INVX2TS U3163 ( .A(n2094), .Y(n1237) );
INVX2TS U3164 ( .A(n2095), .Y(n1241) );
INVX2TS U3165 ( .A(n2096), .Y(n1245) );
INVX2TS U3166 ( .A(n2097), .Y(n1239) );
INVX2TS U3167 ( .A(n2098), .Y(n1247) );
INVX2TS U3168 ( .A(n2099), .Y(n1243) );
INVX2TS U3169 ( .A(n2100), .Y(n1235) );
INVX2TS U3170 ( .A(n2101), .Y(n1233) );
BUFX3TS U3171 ( .A(n2102), .Y(n2108) );
BUFX3TS U3172 ( .A(n2108), .Y(n2134) );
INVX2TS U3173 ( .A(n2103), .Y(n1231) );
INVX2TS U3174 ( .A(n2105), .Y(n1253) );
NAND2X1TS U3175 ( .A(n1698), .B(n2838), .Y(n2191) );
AOI22X1TS U3176 ( .A0(n1698), .A1(n2161), .B0(d_ff3_LUT_out[24]), .B1(n2834),
.Y(n2106) );
OAI31X1TS U3177 ( .A0(n2195), .A1(n2827), .A2(n2190), .B0(n2106), .Y(n1611)
);
INVX2TS U3178 ( .A(n2915), .Y(n2986) );
BUFX4TS U3179 ( .A(n2906), .Y(n2922) );
BUFX3TS U3180 ( .A(n2922), .Y(n2133) );
INVX2TS U3181 ( .A(n2107), .Y(n1275) );
BUFX3TS U3182 ( .A(n2922), .Y(n2987) );
INVX2TS U3183 ( .A(n2109), .Y(n1273) );
INVX2TS U3184 ( .A(n2110), .Y(n1269) );
BUFX3TS U3185 ( .A(n2922), .Y(n2122) );
INVX2TS U3186 ( .A(n2111), .Y(n1263) );
INVX2TS U3187 ( .A(n2113), .Y(n1249) );
INVX2TS U3188 ( .A(n2115), .Y(n1251) );
INVX2TS U3189 ( .A(n2116), .Y(n1265) );
INVX2TS U3190 ( .A(n2117), .Y(n1259) );
INVX2TS U3191 ( .A(n2118), .Y(n1267) );
INVX2TS U3192 ( .A(n2119), .Y(n1271) );
INVX2TS U3193 ( .A(n2120), .Y(n1261) );
INVX2TS U3194 ( .A(n2121), .Y(n1257) );
INVX2TS U3195 ( .A(n2124), .Y(n1255) );
INVX2TS U3196 ( .A(n2125), .Y(n1215) );
INVX2TS U3197 ( .A(n2126), .Y(n1221) );
INVX2TS U3198 ( .A(n2127), .Y(n1225) );
INVX2TS U3199 ( .A(n2128), .Y(n1214) );
INVX2TS U3200 ( .A(n2129), .Y(n1219) );
INVX2TS U3201 ( .A(n2130), .Y(n1227) );
INVX2TS U3202 ( .A(n2131), .Y(n1217) );
INVX2TS U3203 ( .A(n2132), .Y(n1229) );
INVX2TS U3204 ( .A(n2136), .Y(n1223) );
AOI21X1TS U3205 ( .A0(n3139), .A1(n3088), .B0(n2137), .Y(n2147) );
NOR2BX1TS U3206 ( .AN(n2139), .B(n2138), .Y(n2142) );
OAI22X1TS U3207 ( .A0(n3073), .A1(n2140), .B0(n2174), .B1(n1634), .Y(n2141)
);
BUFX3TS U3208 ( .A(n2349), .Y(n2398) );
AOI32X1TS U3209 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[2]),
.A1(n2947), .A2(n2821), .B0(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]), .B1(n2398), .Y(
n2144) );
NAND2X1TS U3210 ( .A(n2357), .B(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[2]), .Y(n2145) );
INVX2TS U3211 ( .A(n2147), .Y(n2148) );
OAI211XLTS U3212 ( .A0(n2151), .A1(n2150), .B0(n2149), .C0(n2148), .Y(n2156)
);
INVX2TS U3213 ( .A(n2152), .Y(n2154) );
OAI31X1TS U3214 ( .A0(n2174), .A1(n2154), .A2(n1645), .B0(n2153), .Y(n2155)
);
AOI211X1TS U3215 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]),
.A1(n2157), .B0(n2156), .C0(n2155), .Y(n2160) );
NAND2X1TS U3216 ( .A(n2357), .B(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[3]), .Y(n2158) );
AOI32X1TS U3217 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[3]),
.A1(n2947), .A2(n2824), .B0(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]), .B1(n2398), .Y(
n2159) );
NOR2BX1TS U3218 ( .AN(n2161), .B(n2183), .Y(n2194) );
NAND2X1TS U3219 ( .A(d_ff3_LUT_out[10]), .B(n2840), .Y(n2163) );
NAND3X1TS U3220 ( .A(inst_CORDIC_FSM_v3_state_reg[0]), .B(n2164), .C(n3077),
.Y(n2810) );
NOR3BX1TS U3221 ( .AN(inst_CORDIC_FSM_v3_state_reg[1]), .B(
inst_CORDIC_FSM_v3_state_reg[2]), .C(n2165), .Y(n2811) );
NOR2BX1TS U3222 ( .AN(n2810), .B(n2811), .Y(n2166) );
INVX2TS U3223 ( .A(n2166), .Y(n2851) );
BUFX3TS U3224 ( .A(n2851), .Y(n2845) );
INVX2TS U3225 ( .A(n2845), .Y(n2846) );
NOR4X1TS U3226 ( .A(n2828), .B(n2874), .C(n2940), .D(n2167), .Y(n2168) );
AOI32X1TS U3227 ( .A0(n2846), .A1(n2816), .A2(n2168), .B0(ready_cordic),
.B1(ack_cordic), .Y(n2169) );
NAND2X1TS U3228 ( .A(n1698), .B(n3072), .Y(n2836) );
NOR3X1TS U3229 ( .A(n2830), .B(n2827), .C(n2190), .Y(n2182) );
AOI21X1TS U3230 ( .A0(d_ff3_LUT_out[2]), .A1(n2979), .B0(n2182), .Y(n2170)
);
AOI22X1TS U3231 ( .A0(n2173), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .B0(n2172), .B1(
n2171), .Y(n2175) );
AOI32X1TS U3232 ( .A0(n1645), .A1(n2175), .A2(n3229), .B0(n2174), .B1(n2175),
.Y(n2176) );
AOI211X1TS U3233 ( .A0(n2178), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .B0(n2177), .C0(
n2176), .Y(n2181) );
NAND2X1TS U3234 ( .A(n2357), .B(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[4]), .Y(n2179) );
AOI21X1TS U3235 ( .A0(d_ff3_LUT_out[6]), .A1(n2866), .B0(n2182), .Y(n2185)
);
OAI211XLTS U3236 ( .A0(cont_iter_out[1]), .A1(n2196), .B0(n2842), .C0(n2183),
.Y(n2184) );
NAND2X1TS U3237 ( .A(n2186), .B(n2838), .Y(n2843) );
INVX2TS U3238 ( .A(n2836), .Y(n2188) );
AOI22X1TS U3239 ( .A0(n2188), .A1(n2835), .B0(d_ff3_LUT_out[4]), .B1(n2868),
.Y(n2189) );
NAND2X1TS U3240 ( .A(d_ff3_LUT_out[5]), .B(n2979), .Y(n2192) );
XNOR2X1TS U3241 ( .A(n2201), .B(d_ff_Xn[31]), .Y(n2204) );
NOR2X4TS U3242 ( .A(ready_cordic), .B(n2197), .Y(n2216) );
BUFX3TS U3243 ( .A(n2216), .Y(n2254) );
XNOR2X1TS U3244 ( .A(d_ff1_shift_region_flag_out[1]), .B(d_ff1_operation_out), .Y(n2198) );
XNOR2X1TS U3245 ( .A(d_ff1_shift_region_flag_out[0]), .B(n2198), .Y(n2200)
);
NOR2X2TS U3246 ( .A(n2216), .B(n2200), .Y(n2199) );
INVX2TS U3247 ( .A(n2199), .Y(n2205) );
BUFX3TS U3248 ( .A(n2255), .Y(n2292) );
XOR2X1TS U3249 ( .A(d_ff_Yn[31]), .B(n2201), .Y(n2202) );
AOI22X1TS U3250 ( .A0(n2254), .A1(data_output[31]), .B0(n2292), .B1(n2202),
.Y(n2203) );
INVX2TS U3251 ( .A(n2205), .Y(n2206) );
INVX2TS U3252 ( .A(n2207), .Y(n1175) );
INVX2TS U3253 ( .A(n2983), .Y(n2916) );
AOI222X1TS U3254 ( .A0(n2943), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[31]), .B0(n2243), .B1(
d_ff3_sh_x_out[31]), .C0(d_ff3_sh_y_out[31]), .C1(n2062), .Y(n2208) );
INVX2TS U3255 ( .A(n2208), .Y(n1207) );
BUFX3TS U3256 ( .A(n2209), .Y(n2250) );
AOI22X1TS U3257 ( .A0(n2250), .A1(d_ff3_sh_y_out[30]), .B0(n2030), .B1(
d_ff3_sh_x_out[30]), .Y(n2210) );
BUFX3TS U3258 ( .A(n2216), .Y(n2289) );
BUFX3TS U3259 ( .A(n2255), .Y(n2288) );
INVX2TS U3260 ( .A(n2211), .Y(n1196) );
INVX2TS U3261 ( .A(n2212), .Y(n1205) );
INVX2TS U3262 ( .A(n2213), .Y(n1197) );
INVX2TS U3263 ( .A(n2214), .Y(n1201) );
INVX2TS U3264 ( .A(n2215), .Y(n1203) );
INVX2TS U3265 ( .A(n2217), .Y(n1204) );
INVX2TS U3266 ( .A(n2218), .Y(n1198) );
INVX2TS U3267 ( .A(n2219), .Y(n1200) );
INVX2TS U3268 ( .A(n2220), .Y(n1199) );
INVX2TS U3269 ( .A(n2221), .Y(n1202) );
BUFX3TS U3270 ( .A(n2209), .Y(n2909) );
AOI22X1TS U3271 ( .A0(n2909), .A1(d_ff3_sh_y_out[11]), .B0(n2243), .B1(
d_ff3_sh_x_out[11]), .Y(n2222) );
BUFX3TS U3272 ( .A(n2889), .Y(n2900) );
NAND2X1TS U3273 ( .A(n2900), .B(d_ff3_LUT_out[7]), .Y(n2235) );
BUFX3TS U3274 ( .A(n2243), .Y(n2249) );
AOI22X1TS U3275 ( .A0(n2250), .A1(d_ff3_sh_y_out[18]), .B0(n2249), .B1(
d_ff3_sh_x_out[18]), .Y(n2224) );
NAND2X1TS U3276 ( .A(n2900), .B(d_ff3_LUT_out[13]), .Y(n2238) );
AOI22X1TS U3277 ( .A0(n2250), .A1(d_ff3_sh_y_out[17]), .B0(n2249), .B1(
d_ff3_sh_x_out[17]), .Y(n2226) );
NAND2X1TS U3278 ( .A(n2889), .B(d_ff3_LUT_out[15]), .Y(n2251) );
AOI22X1TS U3279 ( .A0(n2250), .A1(d_ff3_sh_y_out[29]), .B0(n2243), .B1(
d_ff3_sh_x_out[29]), .Y(n2228) );
NAND2X1TS U3280 ( .A(n2889), .B(d_ff3_LUT_out[27]), .Y(n2241) );
AOI22X1TS U3281 ( .A0(n2250), .A1(d_ff3_sh_y_out[19]), .B0(n2249), .B1(
d_ff3_sh_x_out[19]), .Y(n2230) );
NAND2X1TS U3282 ( .A(n2889), .B(d_ff3_LUT_out[19]), .Y(n2231) );
AOI22X1TS U3283 ( .A0(n2250), .A1(d_ff3_sh_y_out[22]), .B0(n2249), .B1(
d_ff3_sh_x_out[22]), .Y(n2232) );
AOI22X1TS U3284 ( .A0(n2250), .A1(d_ff3_sh_y_out[28]), .B0(n2249), .B1(
d_ff3_sh_x_out[28]), .Y(n2234) );
AOI22X1TS U3285 ( .A0(n2909), .A1(d_ff3_sh_y_out[7]), .B0(n2243), .B1(
d_ff3_sh_x_out[7]), .Y(n2236) );
AOI22X1TS U3286 ( .A0(n2909), .A1(d_ff3_sh_y_out[14]), .B0(n2249), .B1(
d_ff3_sh_x_out[14]), .Y(n2237) );
NAND2X1TS U3287 ( .A(n2889), .B(d_ff3_LUT_out[5]), .Y(n2244) );
AOI22X1TS U3288 ( .A0(n2909), .A1(d_ff3_sh_y_out[13]), .B0(n2249), .B1(
d_ff3_sh_x_out[13]), .Y(n2239) );
AOI22X1TS U3289 ( .A0(n2250), .A1(d_ff3_sh_y_out[16]), .B0(n2249), .B1(
d_ff3_sh_x_out[16]), .Y(n2240) );
NAND2X1TS U3290 ( .A(n2889), .B(d_ff3_LUT_out[3]), .Y(n2247) );
AOI22X1TS U3291 ( .A0(n2250), .A1(d_ff3_sh_y_out[27]), .B0(n2249), .B1(
d_ff3_sh_x_out[27]), .Y(n2242) );
AOI22X1TS U3292 ( .A0(n2909), .A1(d_ff3_sh_y_out[5]), .B0(n2243), .B1(
d_ff3_sh_x_out[5]), .Y(n2245) );
AOI22X1TS U3293 ( .A0(n2909), .A1(d_ff3_sh_y_out[15]), .B0(n2066), .B1(
d_ff3_sh_x_out[15]), .Y(n2246) );
AOI22X1TS U3294 ( .A0(n2909), .A1(d_ff3_sh_y_out[3]), .B0(n2243), .B1(
d_ff3_sh_x_out[3]), .Y(n2248) );
AOI22X1TS U3295 ( .A0(n2250), .A1(d_ff3_sh_y_out[20]), .B0(n2249), .B1(
d_ff3_sh_x_out[20]), .Y(n2252) );
BUFX3TS U3296 ( .A(n2254), .Y(n2285) );
BUFX3TS U3297 ( .A(n2255), .Y(n2284) );
INVX2TS U3298 ( .A(n2256), .Y(n1190) );
INVX2TS U3299 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(
n2301) );
INVX2TS U3300 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(
n2297) );
NOR2BX1TS U3301 ( .AN(n2259), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[6]), .Y(n2260) );
INVX2TS U3302 ( .A(n3015), .Y(n2266) );
AND4X1TS U3303 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[0]), .D(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n2262) );
AND4X1TS U3304 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(n2262), .Y(n2263) );
INVX4TS U3305 ( .A(n2265), .Y(n3016) );
INVX2TS U3306 ( .A(n2268), .Y(n1184) );
INVX2TS U3307 ( .A(n2269), .Y(n1182) );
INVX2TS U3308 ( .A(n2270), .Y(n1185) );
INVX2TS U3309 ( .A(n2271), .Y(n1176) );
INVX2TS U3310 ( .A(n2272), .Y(n1177) );
INVX2TS U3311 ( .A(n2273), .Y(n1181) );
INVX2TS U3312 ( .A(n2274), .Y(n1180) );
INVX2TS U3313 ( .A(n2275), .Y(n1178) );
INVX2TS U3314 ( .A(n2276), .Y(n1179) );
INVX2TS U3315 ( .A(n2277), .Y(n1194) );
INVX2TS U3316 ( .A(n2278), .Y(n1187) );
INVX2TS U3317 ( .A(n2279), .Y(n1192) );
INVX2TS U3318 ( .A(n2280), .Y(n1193) );
INVX2TS U3319 ( .A(n2281), .Y(n1191) );
INVX2TS U3320 ( .A(n2282), .Y(n1188) );
INVX2TS U3321 ( .A(n2283), .Y(n1186) );
INVX2TS U3322 ( .A(n2286), .Y(n1189) );
INVX2TS U3323 ( .A(n2290), .Y(n1195) );
INVX2TS U3324 ( .A(n2293), .Y(n1183) );
BUFX3TS U3325 ( .A(n1638), .Y(n3055) );
NAND2X1TS U3326 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[4]), .B(
n1684), .Y(n2294) );
NAND2X1TS U3327 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[5]), .B(
n1684), .Y(n2295) );
NAND2X1TS U3328 ( .A(n3055), .B(result_add_subt[25]), .Y(n2296) );
NAND2X1TS U3329 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[0]), .B(
n1684), .Y(n2298) );
NAND2X1TS U3330 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[1]), .B(
n1684), .Y(n2299) );
NAND2X1TS U3331 ( .A(n3055), .B(result_add_subt[26]), .Y(n2300) );
NAND2X1TS U3332 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
n1684), .Y(n2302) );
AOI22X1TS U3333 ( .A0(n2398), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]), .B0(n1673), .B1(n2399), .Y(n2304) );
AOI22X1TS U3334 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[0]), .A1(n1823),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[0]), .B1(n2306), .Y(n2307) );
AOI22X1TS U3335 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .A1(n1823),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[1]), .B1(n2447), .Y(n2308) );
AOI22X1TS U3336 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .A1(n1823),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[2]), .B1(n2306), .Y(n2309) );
AOI22X1TS U3337 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[7]), .A1(n1823),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[7]), .B1(n2306), .Y(n2310) );
NAND2X1TS U3338 ( .A(n2406), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n2313) );
NAND2X1TS U3339 ( .A(n2361), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n2312) );
NAND2X1TS U3340 ( .A(n2357), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n2311) );
AOI22X1TS U3341 ( .A0(n2421), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[0]), .B1(n2398), .Y(n2322)
);
NAND2X1TS U3342 ( .A(n2417), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .Y(n2320) );
NAND2X1TS U3343 ( .A(n2361), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n2319) );
NAND2X1TS U3344 ( .A(n2357), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[1]), .Y(n2318) );
OAI2BB2X1TS U3345 ( .B0(n2423), .B1(n1645), .A0N(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]), .A1N(n2421), .Y(
n2342) );
AOI21X1TS U3346 ( .A0(n1694), .A1(n2381), .B0(n2342), .Y(n2321) );
NAND2X1TS U3347 ( .A(n2417), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n2325) );
NAND2X1TS U3348 ( .A(n2361), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .Y(n2324) );
NAND2X1TS U3349 ( .A(n2330), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n2323) );
NAND3X1TS U3350 ( .A(n2325), .B(n2324), .C(n2323), .Y(n2353) );
INVX2TS U3351 ( .A(n2353), .Y(n2391) );
AOI22X1TS U3352 ( .A0(n2406), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[18]), .B1(n3053), .Y(
n2326) );
AOI22X1TS U3353 ( .A0(n2398), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[18]), .B0(n1690), .B1(n2388), .Y(n2335) );
AOI22X1TS U3354 ( .A0(n2421), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[16]), .B1(n2330), .Y(
n2328) );
NAND2X1TS U3355 ( .A(n2361), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(n2332) );
NAND2X1TS U3356 ( .A(n2330), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n2331) );
NAND3X1TS U3357 ( .A(n2333), .B(n2332), .C(n2331), .Y(n2387) );
AOI22X1TS U3358 ( .A0(n1662), .A1(n2418), .B0(n1694), .B1(n2387), .Y(n2334)
);
AOI22X1TS U3359 ( .A0(n2421), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[2]), .B1(n3053), .Y(n2336) );
AOI22X1TS U3360 ( .A0(n2349), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[2]), .B0(n1690), .B1(n2383),
.Y(n2341) );
NAND2X1TS U3361 ( .A(n2406), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .Y(n2339) );
NAND2X1TS U3362 ( .A(n2361), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n2338) );
NAND2X1TS U3363 ( .A(n2357), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n2337) );
NAND3X1TS U3364 ( .A(n2339), .B(n2338), .C(n2337), .Y(n2382) );
AOI22X1TS U3365 ( .A0(n1673), .A1(n2381), .B0(n1693), .B1(n2382), .Y(n2340)
);
AOI22X1TS U3366 ( .A0(n2398), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[1]), .B0(n1690), .B1(n2381),
.Y(n2344) );
AOI22X1TS U3367 ( .A0(n1662), .A1(n2342), .B0(n1693), .B1(n2383), .Y(n2343)
);
NAND2X1TS U3368 ( .A(n2406), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n2348) );
NAND2X1TS U3369 ( .A(n2361), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n2347) );
NAND2X1TS U3370 ( .A(n2357), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n2346) );
NAND3X1TS U3371 ( .A(n2348), .B(n2347), .C(n2346), .Y(n2438) );
INVX2TS U3372 ( .A(n2438), .Y(n2356) );
BUFX3TS U3373 ( .A(n2349), .Y(n2437) );
AOI22X1TS U3374 ( .A0(n2437), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]), .B0(n1690), .B1(n2353), .Y(n2351) );
AOI22X1TS U3375 ( .A0(n1673), .A1(n2418), .B0(n1694), .B1(n2388), .Y(n2350)
);
AOI22X1TS U3376 ( .A0(n2437), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]), .B0(n1691), .B1(n2418), .Y(n2355) );
AOI22X1TS U3377 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .A1(
n2421), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[14]), .B1(
n2821), .Y(n2352) );
AOI22X1TS U3378 ( .A0(n1662), .A1(n2436), .B0(n1694), .B1(n2353), .Y(n2354)
);
NAND2X1TS U3379 ( .A(n2417), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .Y(n2360) );
NAND2X1TS U3380 ( .A(n2361), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]), .Y(n2359) );
NAND2X1TS U3381 ( .A(n2357), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n2358) );
NAND3X1TS U3382 ( .A(n2360), .B(n2359), .C(n2358), .Y(n2392) );
INVX2TS U3383 ( .A(n2392), .Y(n2380) );
AOI22X1TS U3384 ( .A0(n2361), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[6]), .B1(n3053), .Y(n2362) );
AOI22X1TS U3385 ( .A0(n2349), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[6]), .B0(n1691), .B1(n2413),
.Y(n2365) );
AOI22X1TS U3386 ( .A0(n2421), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[4]), .B1(n3053), .Y(n2363) );
AOI222X4TS U3387 ( .A0(n2821), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[7]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n2406), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(n2404), .Y(
n2416) );
INVX2TS U3388 ( .A(n2416), .Y(n2375) );
AOI22X1TS U3389 ( .A0(n1662), .A1(n2393), .B0(n1695), .B1(n2375), .Y(n2364)
);
INVX2TS U3390 ( .A(n2387), .Y(n2374) );
AOI22X1TS U3391 ( .A0(n2417), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[20]), .B1(n2824), .Y(
n2366) );
AOI22X1TS U3392 ( .A0(n2398), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[20]), .B0(n1690), .B1(n2397), .Y(n2368) );
AOI22X1TS U3393 ( .A0(n1662), .A1(n2388), .B0(n1695), .B1(n2371), .Y(n2367)
);
INVX2TS U3394 ( .A(n2382), .Y(n2396) );
AOI22X1TS U3395 ( .A0(n2349), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[4]), .B0(n1690), .B1(n2393),
.Y(n2370) );
AOI22X1TS U3396 ( .A0(n1662), .A1(n2383), .B0(n1694), .B1(n2392), .Y(n2369)
);
AOI22X1TS U3397 ( .A0(n2437), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]), .B0(n1690), .B1(n2371), .Y(n2373) );
AOI22X1TS U3398 ( .A0(n1673), .A1(n2397), .B0(n1695), .B1(n2400), .Y(n2372)
);
AOI22X1TS U3399 ( .A0(n2349), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[7]), .B0(n1689), .B1(n2375),
.Y(n2379) );
AOI22X1TS U3400 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]),
.A1(n2417), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[8]), .B1(
n2821), .Y(n2376) );
AOI22X1TS U3401 ( .A0(n1673), .A1(n2413), .B0(n1694), .B1(n2411), .Y(n2378)
);
INVX2TS U3402 ( .A(n2381), .Y(n2386) );
AOI22X1TS U3403 ( .A0(n2349), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[3]), .B0(n1689), .B1(n2382),
.Y(n2385) );
AOI22X1TS U3404 ( .A0(n1673), .A1(n2383), .B0(n1694), .B1(n2393), .Y(n2384)
);
AOI22X1TS U3405 ( .A0(n2398), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[19]), .B0(n1691), .B1(n2387), .Y(n2390) );
AOI22X1TS U3406 ( .A0(n1673), .A1(n2388), .B0(n1695), .B1(n2397), .Y(n2389)
);
AOI22X1TS U3407 ( .A0(n2349), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[5]), .B0(n1691), .B1(n2392),
.Y(n2395) );
AOI22X1TS U3408 ( .A0(n1673), .A1(n2393), .B0(n1695), .B1(n2413), .Y(n2394)
);
AOI22X1TS U3409 ( .A0(n2398), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]), .B0(n1662), .B1(n2397), .Y(n2402) );
AOI22X1TS U3410 ( .A0(n1689), .A1(n2400), .B0(n1695), .B1(n2399), .Y(n2401)
);
AOI222X4TS U3411 ( .A0(n2821), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[9]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]), .B1(n2417), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[14]), .C1(n2404), .Y(
n2435) );
AOI22X1TS U3412 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]),
.A1(n2421), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[10]),
.B1(n2821), .Y(n2405) );
AOI22X1TS U3413 ( .A0(n2437), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[10]), .B0(n1691), .B1(n2431), .Y(n2408) );
AOI222X4TS U3414 ( .A0(n3053), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[11]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .B1(n2406), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .C1(n2421), .Y(
n2429) );
INVX2TS U3415 ( .A(n2429), .Y(n2430) );
AOI22X1TS U3416 ( .A0(n2327), .A1(n2411), .B0(n1693), .B1(n2430), .Y(n2407)
);
INVX2TS U3417 ( .A(n2435), .Y(n2412) );
AOI22X1TS U3418 ( .A0(n2437), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[9]), .B0(n1690), .B1(n2412),
.Y(n2410) );
AOI22X1TS U3419 ( .A0(n1673), .A1(n2411), .B0(n1694), .B1(n2431), .Y(n2409)
);
AOI22X1TS U3420 ( .A0(n2349), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[8]), .B0(n1689), .B1(n2411),
.Y(n2415) );
AOI22X1TS U3421 ( .A0(n1669), .A1(n2413), .B0(n1695), .B1(n2412), .Y(n2414)
);
AOI222X4TS U3422 ( .A0(n2821), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]), .B1(n2421), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]), .C1(n2417), .Y(
n2442) );
AOI22X1TS U3423 ( .A0(n2437), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]), .B0(n1689), .B1(n2438), .Y(n2420) );
AOI22X1TS U3424 ( .A0(n1751), .A1(n2436), .B0(n1693), .B1(n2418), .Y(n2419)
);
INVX2TS U3425 ( .A(n2442), .Y(n2426) );
AOI22X1TS U3426 ( .A0(n2437), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]), .B0(n1689), .B1(n2426), .Y(n2425) );
AOI22X1TS U3427 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]),
.A1(n2421), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[12]),
.B1(n2821), .Y(n2422) );
AOI22X1TS U3428 ( .A0(n1751), .A1(n2439), .B0(n1693), .B1(n2436), .Y(n2424)
);
AOI22X1TS U3429 ( .A0(n2437), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]), .B0(n1689), .B1(n2439), .Y(n2428) );
AOI22X1TS U3430 ( .A0(n1662), .A1(n2431), .B0(n1693), .B1(n2426), .Y(n2427)
);
AOI22X1TS U3431 ( .A0(n2437), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[11]), .B0(n1691), .B1(n2430), .Y(n2433) );
AOI22X1TS U3432 ( .A0(n1673), .A1(n2431), .B0(n1695), .B1(n2439), .Y(n2432)
);
AOI22X1TS U3433 ( .A0(n2437), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]), .B0(n1689), .B1(n2436), .Y(n2441) );
AOI22X1TS U3434 ( .A0(n1662), .A1(n2439), .B0(n1693), .B1(n2438), .Y(n2440)
);
AOI22X1TS U3435 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .A1(n2458), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[10]), .B1(n2502), .Y(n2443) );
BUFX3TS U3436 ( .A(n2447), .Y(n2473) );
AOI22X1TS U3437 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .A1(n2458),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[6]), .B1(n2473), .Y(n2444) );
AOI22X1TS U3438 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .A1(n2513), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[20]), .B1(n2502), .Y(n2445) );
AOI22X1TS U3439 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .A1(n2458),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[4]), .B1(n2473), .Y(n2446) );
BUFX3TS U3440 ( .A(n2447), .Y(n2507) );
AOI22X1TS U3441 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .A1(n2458), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[12]), .B1(n2507), .Y(n2448) );
AOI22X1TS U3442 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]), .A1(n2458),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[8]), .B1(n2502), .Y(n2449) );
AOI22X1TS U3443 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .A1(n2513), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[19]), .B1(n2473), .Y(n2450) );
AOI22X1TS U3444 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .A1(n2513), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[21]), .B1(n2473), .Y(n2452) );
AOI22X1TS U3445 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .A1(n2513), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[15]), .B1(n2473), .Y(n2453) );
AOI22X1TS U3446 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .A1(n2458), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[16]), .B1(n2473), .Y(n2454) );
AOI22X1TS U3447 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .A1(n2458),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[3]), .B1(n2502), .Y(n2455) );
AOI22X1TS U3448 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]), .A1(n2458), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[14]), .B1(n2502), .Y(n2456) );
AOI22X1TS U3449 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .A1(n2458), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[13]), .B1(n2502), .Y(n2459) );
INVX2TS U3450 ( .A(n1825), .Y(n2465) );
AOI22X1TS U3451 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]), .A1(n2513), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[22]), .B1(n2473), .Y(n2460) );
AOI22X1TS U3452 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]), .A1(n2513), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[17]), .B1(n2473), .Y(n2461) );
AOI22X1TS U3453 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]), .A1(n2513), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[18]), .B1(n2473), .Y(n2462) );
AOI22X1TS U3454 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[28]), .A1(n2505), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[28]), .B1(n3039), .Y(n2464) );
AOI22X1TS U3455 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[31]), .A1(n2466), .B0(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_EXP), .B1(n2502), .Y(n2467) );
INVX2TS U3456 ( .A(n2475), .Y(n2501) );
AOI22X1TS U3457 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]), .A1(n2514), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[18]), .B1(n2820), .Y(n2470) );
AOI22X1TS U3458 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]), .A1(n2496), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[11]), .B1(n2507), .Y(n2471) );
AOI22X1TS U3459 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .A1(n2514), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[21]), .B1(n2820), .Y(n2472) );
AOI22X1TS U3460 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]), .A1(n2505), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[29]), .B1(n2473), .Y(n2474) );
AOI22X1TS U3461 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .A1(n2496), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[12]), .B1(n2507), .Y(n2476) );
AOI22X1TS U3462 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .A1(n2514), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[20]), .B1(n2820), .Y(n2477) );
AOI22X1TS U3463 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[30]), .A1(n2505), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[30]), .B1(n3039), .Y(n2478) );
AOI22X1TS U3464 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .A1(n2496),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[9]), .B1(n1714), .Y(n2479) );
AOI22X1TS U3465 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[0]), .A1(n2496),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[0]), .B1(n2306), .Y(n2480) );
AOI22X1TS U3466 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .A1(n2496),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[1]), .B1(n2447), .Y(n2481) );
AOI22X1TS U3467 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .A1(n2496),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[2]), .B1(n2306), .Y(n2483) );
AOI22X1TS U3468 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .A1(n2496), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[10]), .B1(n2507), .Y(n2484) );
AOI22X1TS U3469 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .A1(n2514),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[6]), .B1(n2820), .Y(n2485) );
AOI22X1TS U3470 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .A1(n2514),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[4]), .B1(n2820), .Y(n2486) );
AOI22X1TS U3471 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .A1(n2514), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[19]), .B1(n2820), .Y(n2487) );
AOI22X1TS U3472 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .A1(n2514), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[13]), .B1(n2507), .Y(n2488) );
AOI22X1TS U3473 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]), .A1(n2496), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[14]), .B1(n2507), .Y(n2490) );
AOI22X1TS U3474 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[7]), .A1(n2496),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[7]), .B1(n2306), .Y(n2492) );
AOI22X1TS U3475 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .A1(n2505), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[16]), .B1(n2507), .Y(n2493) );
AOI22X1TS U3476 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]), .A1(n2514), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[17]), .B1(n2820), .Y(n2495) );
AOI22X1TS U3477 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]), .A1(n2496), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[22]), .B1(n2502), .Y(n2497) );
AOI22X1TS U3478 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]), .A1(n2505),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[8]), .B1(n2507), .Y(n2498) );
AOI22X1TS U3479 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .A1(n2505), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[27]), .B1(n3039), .Y(n2500) );
AOI22X1TS U3480 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .A1(n2505),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[3]), .B1(n2502), .Y(n2503) );
AOI22X1TS U3481 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .A1(n1823),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[5]), .B1(n2507), .Y(n2506) );
AOI22X1TS U3482 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[5]), .A1(n1823),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[5]), .B1(n2507), .Y(n2508) );
AOI22X1TS U3483 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .A1(n1823),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[9]), .B1(n1714), .Y(n2509) );
AOI22X1TS U3484 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .A1(n2513), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[27]), .B1(n3039), .Y(n2510) );
AOI222X1TS U3485 ( .A0(n2513), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[23]), .B1(n3039), .C0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .C1(n1825), .Y(n2512) );
INVX2TS U3486 ( .A(n2512), .Y(n1110) );
AOI222X1TS U3487 ( .A0(n2514), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[23]), .B1(n3039), .C0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .C1(n2513), .Y(n2515) );
INVX2TS U3488 ( .A(n2515), .Y(n1158) );
INVX2TS U3489 ( .A(n2833), .Y(n2832) );
OAI21XLTS U3490 ( .A0(n2832), .A1(n3097), .B0(cont_var_out[1]), .Y(n2516) );
NOR2BX1TS U3491 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[4]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2518) );
XOR2X1TS U3492 ( .A(n3094), .B(n2518), .Y(DP_OP_33J115_122_2179_n14) );
NOR2BX1TS U3493 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[3]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2519) );
XOR2X1TS U3494 ( .A(n3094), .B(n2519), .Y(DP_OP_33J115_122_2179_n15) );
NOR2BX1TS U3495 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[2]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2520) );
XOR2X1TS U3496 ( .A(n3094), .B(n2520), .Y(DP_OP_33J115_122_2179_n16) );
NOR2BX1TS U3497 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[1]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2521) );
XOR2X1TS U3498 ( .A(n3094), .B(n2521), .Y(DP_OP_33J115_122_2179_n17) );
XOR2X1TS U3499 ( .A(n3094), .B(n1708), .Y(DP_OP_33J115_122_2179_n18) );
OAI33X4TS U3500 ( .A0(n3132), .A1(n3266), .A2(n1643), .B0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B1(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B2(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(
n2823) );
MXI2X1TS U3501 ( .A(n2522), .B(n2802), .S0(n2823), .Y(n1623) );
BUFX3TS U3502 ( .A(n2524), .Y(n3009) );
INVX2TS U3503 ( .A(n2545), .Y(n2553) );
OAI33X1TS U3504 ( .A0(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]),
.A1(n3082), .A2(n3068), .B0(n3067), .B1(n3128), .B2(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n2525) );
AOI22X1TS U3505 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[8]), .A1(
n1680), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[0]), .B1(n1682),
.Y(n2527) );
AOI22X1TS U3506 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]), .A1(
n1676), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[4]), .B1(n1678),
.Y(n2526) );
OAI211X1TS U3507 ( .A0(n2588), .A1(n1639), .B0(n2527), .C0(n2526), .Y(n2621)
);
NOR2X2TS U3508 ( .A(n2553), .B(n1649), .Y(n2543) );
AOI21X1TS U3509 ( .A0(n2528), .A1(n2534), .B0(n2558), .Y(n2529) );
AOI221X1TS U3510 ( .A0(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]),
.A1(n3081), .B0(n3068), .B1(n3127), .C0(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n2530) );
AOI22X1TS U3511 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]), .A1(
n1675), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[5]), .B1(n1678),
.Y(n2533) );
AOI22X1TS U3512 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[9]), .A1(
n1679), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[1]), .B1(n1681),
.Y(n2532) );
OAI211X1TS U3513 ( .A0(n2593), .A1(n1639), .B0(n2533), .C0(n2532), .Y(n2614)
);
AOI211X1TS U3514 ( .A0(n2620), .A1(n2614), .B0(n2572), .C0(n2535), .Y(n3017)
);
MXI2X1TS U3515 ( .A(n3017), .B(n3158), .S0(n2558), .Y(n867) );
AOI22X1TS U3516 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[10]), .A1(
n1679), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[2]), .B1(n1681),
.Y(n2538) );
AOI22X1TS U3517 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]), .A1(
n1675), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[6]), .B1(n1677),
.Y(n2537) );
OAI211X1TS U3518 ( .A0(n1696), .A1(n1639), .B0(n2538), .C0(n2537), .Y(n2611)
);
AOI211X1TS U3519 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(
n2611), .B0(n2572), .C0(n2539), .Y(n3021) );
MXI2X1TS U3520 ( .A(n3021), .B(n3146), .S0(n2558), .Y(n868) );
AOI22X1TS U3521 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[11]), .A1(
n1679), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[3]), .B1(n1681),
.Y(n2542) );
AOI22X1TS U3522 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]), .A1(
n1675), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[7]), .B1(n1677),
.Y(n2541) );
OAI211X1TS U3523 ( .A0(n2598), .A1(n1639), .B0(n2542), .C0(n2541), .Y(n2608)
);
AOI21X1TS U3524 ( .A0(n2553), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]), .B0(n2543), .Y(n2606)
);
AOI211X1TS U3525 ( .A0(n1686), .A1(n2608), .B0(n2572), .C0(n2544), .Y(n3023)
);
MXI2X1TS U3526 ( .A(n3023), .B(n3159), .S0(n2558), .Y(n869) );
AOI22X1TS U3527 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]), .A1(
n1679), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[4]), .B1(n1681),
.Y(n2549) );
AOI22X1TS U3528 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]), .A1(
n1675), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[8]), .B1(n1677),
.Y(n2548) );
OAI211X1TS U3529 ( .A0(n1697), .A1(n1639), .B0(n2549), .C0(n2548), .Y(n2605)
);
OAI21X1TS U3530 ( .A0(n3081), .A1(n2551), .B0(n2550), .Y(n2552) );
AOI211X1TS U3531 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(
n2605), .B0(n2572), .C0(n2554), .Y(n3022) );
MXI2X1TS U3532 ( .A(n3022), .B(n3147), .S0(n2558), .Y(n870) );
AOI22X1TS U3533 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]), .A1(
n1679), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[5]), .B1(n1681),
.Y(n2556) );
AOI22X1TS U3534 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]), .A1(
n1675), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[9]), .B1(n1677),
.Y(n2555) );
OAI211X1TS U3535 ( .A0(n2603), .A1(n1639), .B0(n2556), .C0(n2555), .Y(n2602)
);
AOI211X1TS U3536 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(
n2602), .B0(n2572), .C0(n2557), .Y(n3019) );
MXI2X1TS U3537 ( .A(n3019), .B(n3160), .S0(n2558), .Y(n871) );
AOI22X1TS U3538 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[18]), .A1(
n1676), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[10]), .B1(n1678), .Y(n2560) );
AOI22X1TS U3539 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]), .A1(
n1680), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[6]), .B1(n1682),
.Y(n2559) );
AOI211X1TS U3540 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(
n2600), .B0(n2572), .C0(n2561), .Y(n3024) );
MXI2X1TS U3541 ( .A(n3024), .B(n3148), .S0(n2585), .Y(n872) );
AOI22X1TS U3542 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[19]), .A1(
n1675), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[11]), .B1(n1678), .Y(n2563) );
AOI22X1TS U3543 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]), .A1(
n1679), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[7]), .B1(n1681),
.Y(n2562) );
OAI211X1TS U3544 ( .A0(n2609), .A1(n1639), .B0(n2563), .C0(n2562), .Y(n2597)
);
AOI211X1TS U3545 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(
n2597), .B0(n2572), .C0(n2564), .Y(n3030) );
MXI2X1TS U3546 ( .A(n3030), .B(n3161), .S0(n2585), .Y(n873) );
AOI22X1TS U3547 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[20]), .A1(
n1676), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]), .B1(n1678), .Y(n2566) );
AOI22X1TS U3548 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]), .A1(
n1679), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[8]), .B1(n1681),
.Y(n2565) );
OAI211X1TS U3549 ( .A0(n1647), .A1(n1639), .B0(n2566), .C0(n2565), .Y(n2595)
);
AOI211X1TS U3550 ( .A0(n1686), .A1(n2595), .B0(n2572), .C0(n2567), .Y(n3018)
);
MXI2X1TS U3551 ( .A(n3018), .B(n3149), .S0(n2585), .Y(n874) );
AOI22X1TS U3552 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]), .A1(
n1675), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]), .B1(n1678), .Y(n2569) );
AOI22X1TS U3553 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]), .A1(
n1679), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[9]), .B1(n1681),
.Y(n2568) );
OAI211X1TS U3554 ( .A0(n2616), .A1(n1639), .B0(n2569), .C0(n2568), .Y(n2592)
);
AOI211X1TS U3555 ( .A0(n1686), .A1(n2592), .B0(n2572), .C0(n2571), .Y(n3034)
);
MXI2X1TS U3556 ( .A(n3034), .B(n3162), .S0(n2585), .Y(n875) );
AOI22X1TS U3557 ( .A0(n1686), .A1(n2574), .B0(n2573), .B1(n1705), .Y(n3028)
);
MXI2X1TS U3558 ( .A(n3028), .B(n3150), .S0(n2585), .Y(n876) );
AOI21X1TS U3559 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]), .A1(
n1678), .B0(n2590), .Y(n2576) );
AOI22X1TS U3560 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]), .A1(
n1676), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[11]), .B1(n1682), .Y(n2575) );
OAI211X1TS U3561 ( .A0(n3130), .A1(n1636), .B0(n2576), .C0(n2575), .Y(n2586)
);
AOI22X1TS U3562 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]), .A1(
n1680), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]), .B1(n1682), .Y(n2577) );
OAI211X1TS U3563 ( .A0(n3131), .A1(n1909), .B0(n2578), .C0(n2577), .Y(n2587)
);
AOI22X1TS U3564 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(
n2586), .B0(n2587), .B1(n1704), .Y(n3036) );
MXI2X1TS U3565 ( .A(n3036), .B(n3163), .S0(n2612), .Y(n877) );
AOI22X1TS U3566 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[20]), .A1(
n1680), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]), .B1(n1682), .Y(n2580) );
AOI22X1TS U3567 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]), .A1(
n1677), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]), .B1(n1676), .Y(n2579) );
NAND2X1TS U3568 ( .A(n2580), .B(n2579), .Y(n2583) );
AOI22X1TS U3569 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]), .A1(
n1680), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]), .B1(n1682), .Y(n2582) );
AOI22X1TS U3570 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]), .A1(
n1677), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[25]), .B1(n1676), .Y(n2581) );
NAND2X1TS U3571 ( .A(n2582), .B(n2581), .Y(n2584) );
AOI221X1TS U3572 ( .A0(n1686), .A1(n2583), .B0(n1704), .B1(n2584), .C0(n2590), .Y(n3032) );
MXI2X1TS U3573 ( .A(n3032), .B(n3151), .S0(n2585), .Y(n878) );
AOI221X1TS U3574 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(
n2584), .B0(n1705), .B1(n2583), .C0(n2590), .Y(n3035) );
MXI2X1TS U3575 ( .A(n3035), .B(n3152), .S0(n2585), .Y(n879) );
AOI22X1TS U3576 ( .A0(n2620), .A1(n2587), .B0(n2586), .B1(n1705), .Y(n3048)
);
MXI2X1TS U3577 ( .A(n3048), .B(n1707), .S0(n2612), .Y(n880) );
NAND2X4TS U3578 ( .A(n1686), .B(n1668), .Y(n2617) );
AOI211X1TS U3579 ( .A0(n2592), .A1(n1704), .B0(n2591), .C0(n2618), .Y(n3044)
);
BUFX3TS U3580 ( .A(n2612), .Y(n2622) );
MXI2X1TS U3581 ( .A(n3044), .B(n3153), .S0(n2622), .Y(n882) );
AOI211X1TS U3582 ( .A0(n2595), .A1(n1705), .B0(n2594), .C0(n2618), .Y(n3027)
);
MXI2X1TS U3583 ( .A(n3027), .B(n3143), .S0(n2612), .Y(n883) );
AOI211X1TS U3584 ( .A0(n2597), .A1(n1637), .B0(n2596), .C0(n2618), .Y(n3050)
);
MXI2X1TS U3585 ( .A(n3050), .B(n3154), .S0(n2622), .Y(n884) );
AOI211X1TS U3586 ( .A0(n2600), .A1(n1705), .B0(n2599), .C0(n2618), .Y(n3026)
);
MXI2X1TS U3587 ( .A(n3026), .B(n3144), .S0(n2622), .Y(n885) );
AOI211X1TS U3588 ( .A0(n2602), .A1(n1704), .B0(n2601), .C0(n2618), .Y(n3042)
);
MXI2X1TS U3589 ( .A(n3042), .B(n3155), .S0(n2622), .Y(n886) );
AOI211X1TS U3590 ( .A0(n2605), .A1(n1705), .B0(n2604), .C0(n2618), .Y(n3043)
);
MXI2X1TS U3591 ( .A(n3043), .B(n3145), .S0(n2622), .Y(n887) );
AOI211X1TS U3592 ( .A0(n2608), .A1(n1704), .B0(n2607), .C0(n2618), .Y(n3047)
);
MXI2X1TS U3593 ( .A(n3047), .B(n3156), .S0(n2622), .Y(n888) );
AOI211X1TS U3594 ( .A0(n2611), .A1(n1705), .B0(n2610), .C0(n2618), .Y(n3045)
);
MXI2X1TS U3595 ( .A(n3045), .B(n3157), .S0(n2612), .Y(n889) );
AOI211X1TS U3596 ( .A0(n2614), .A1(n1704), .B0(n2613), .C0(n2618), .Y(n2615)
);
MXI2X1TS U3597 ( .A(n2615), .B(n3089), .S0(n2622), .Y(n890) );
AOI211X1TS U3598 ( .A0(n2621), .A1(n1705), .B0(n2619), .C0(n2618), .Y(n2623)
);
MXI2X1TS U3599 ( .A(n2623), .B(n2767), .S0(n2622), .Y(n891) );
NAND2X1TS U3600 ( .A(n2626), .B(n2625), .Y(n2629) );
INVX2TS U3601 ( .A(n2629), .Y(n2627) );
XOR2X1TS U3602 ( .A(n2630), .B(n2629), .Y(n2631) );
AOI22X1TS U3603 ( .A0(n2631), .A1(n1944), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]), .B1(n2822), .Y(
n2632) );
OAI2BB1X1TS U3604 ( .A0N(n2701), .A1N(n2633), .B0(n2632), .Y(n1027) );
NAND2X1TS U3605 ( .A(n2635), .B(n2634), .Y(n2638) );
INVX2TS U3606 ( .A(n2638), .Y(n2636) );
XNOR2X1TS U3607 ( .A(n2637), .B(n2636), .Y(n2642) );
XNOR2X1TS U3608 ( .A(n2639), .B(n2638), .Y(n2640) );
AOI22X1TS U3609 ( .A0(n2640), .A1(n1944), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]), .B1(n2822), .Y(
n2641) );
OAI2BB1X1TS U3610 ( .A0N(n2701), .A1N(n2642), .B0(n2641), .Y(n1026) );
INVX2TS U3611 ( .A(n2643), .Y(n2645) );
NAND2X1TS U3612 ( .A(n2645), .B(n2644), .Y(n2648) );
INVX2TS U3613 ( .A(n2648), .Y(n2646) );
XOR2X1TS U3614 ( .A(n2649), .B(n2648), .Y(n2650) );
AOI22X1TS U3615 ( .A0(n2650), .A1(n1944), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]), .B1(n2822), .Y(
n2651) );
OAI2BB1X1TS U3616 ( .A0N(n2701), .A1N(n2652), .B0(n2651), .Y(n1025) );
INVX2TS U3617 ( .A(n2653), .Y(n2655) );
NAND2X1TS U3618 ( .A(n2655), .B(n2654), .Y(n2658) );
INVX2TS U3619 ( .A(n2658), .Y(n2656) );
XOR2X1TS U3620 ( .A(n2659), .B(n2658), .Y(n2660) );
BUFX3TS U3621 ( .A(n3008), .Y(n2768) );
AOI22X1TS U3622 ( .A0(n2660), .A1(n2744), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .B1(n2768), .Y(
n2661) );
OAI2BB1X1TS U3623 ( .A0N(n2701), .A1N(n2662), .B0(n2661), .Y(n1009) );
NAND2X1TS U3624 ( .A(n2664), .B(n2663), .Y(n2667) );
INVX2TS U3625 ( .A(n2667), .Y(n2665) );
XNOR2X1TS U3626 ( .A(n2666), .B(n2665), .Y(n2671) );
XNOR2X1TS U3627 ( .A(n2668), .B(n2667), .Y(n2669) );
AOI22X1TS U3628 ( .A0(n2669), .A1(n2744), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .B1(n2822), .Y(
n2670) );
OAI2BB1X1TS U3629 ( .A0N(n2701), .A1N(n2671), .B0(n2670), .Y(n1010) );
INVX2TS U3630 ( .A(n2672), .Y(n2674) );
NAND2X1TS U3631 ( .A(n2674), .B(n2673), .Y(n2677) );
INVX2TS U3632 ( .A(n2677), .Y(n2675) );
XOR2X1TS U3633 ( .A(n2678), .B(n2677), .Y(n2679) );
AOI22X1TS U3634 ( .A0(n2679), .A1(n2744), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .B1(n2822), .Y(
n2680) );
OAI2BB1X1TS U3635 ( .A0N(n2701), .A1N(n2681), .B0(n2680), .Y(n1014) );
NAND2X1TS U3636 ( .A(n2683), .B(n2682), .Y(n2686) );
INVX2TS U3637 ( .A(n2686), .Y(n2684) );
XNOR2X1TS U3638 ( .A(n2685), .B(n2684), .Y(n2690) );
XNOR2X1TS U3639 ( .A(n2687), .B(n2686), .Y(n2688) );
AOI22X1TS U3640 ( .A0(n2688), .A1(n2744), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .B1(n2768), .Y(
n2689) );
OAI2BB1X1TS U3641 ( .A0N(n2701), .A1N(n2690), .B0(n2689), .Y(n1013) );
INVX2TS U3642 ( .A(n2691), .Y(n2693) );
NAND2X1TS U3643 ( .A(n2693), .B(n2692), .Y(n2696) );
INVX2TS U3644 ( .A(n2696), .Y(n2694) );
XOR2X1TS U3645 ( .A(n2697), .B(n2696), .Y(n2698) );
AOI22X1TS U3646 ( .A0(n2698), .A1(n2744), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .B1(n2768), .Y(
n2699) );
OAI2BB1X1TS U3647 ( .A0N(n2701), .A1N(n2700), .B0(n2699), .Y(n1012) );
BUFX3TS U3648 ( .A(n2702), .Y(n2807) );
NAND2X1TS U3649 ( .A(n2704), .B(n2703), .Y(n2707) );
INVX2TS U3650 ( .A(n2707), .Y(n2705) );
XNOR2X1TS U3651 ( .A(n2706), .B(n2705), .Y(n2711) );
XNOR2X1TS U3652 ( .A(n2708), .B(n2707), .Y(n2709) );
AOI22X1TS U3653 ( .A0(n2709), .A1(n2744), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]), .B1(n2768), .Y(
n2710) );
OAI2BB1X1TS U3654 ( .A0N(n2807), .A1N(n2711), .B0(n2710), .Y(n1024) );
NAND2X1TS U3655 ( .A(n2713), .B(n2712), .Y(n2716) );
INVX2TS U3656 ( .A(n2716), .Y(n2714) );
XNOR2X1TS U3657 ( .A(n2715), .B(n2714), .Y(n2720) );
XNOR2X1TS U3658 ( .A(n2717), .B(n2716), .Y(n2718) );
AOI22X1TS U3659 ( .A0(n2718), .A1(n2744), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[14]), .B1(n2768), .Y(
n2719) );
OAI2BB1X1TS U3660 ( .A0N(n2807), .A1N(n2720), .B0(n2719), .Y(n1028) );
NAND2X1TS U3661 ( .A(n2723), .B(n2722), .Y(n2726) );
INVX2TS U3662 ( .A(n2726), .Y(n2724) );
XOR2X1TS U3663 ( .A(n2727), .B(n2726), .Y(n2728) );
AOI22X1TS U3664 ( .A0(n2728), .A1(n2744), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .B1(n2768), .Y(
n2729) );
OAI2BB1X1TS U3665 ( .A0N(n2807), .A1N(n2730), .B0(n2729), .Y(n1029) );
INVX2TS U3666 ( .A(n2731), .Y(n2796) );
INVX2TS U3667 ( .A(n2733), .Y(n2734) );
NAND2X1TS U3668 ( .A(n2737), .B(n2736), .Y(n2742) );
INVX2TS U3669 ( .A(n2742), .Y(n2738) );
XNOR2X1TS U3670 ( .A(n2739), .B(n2738), .Y(n2747) );
XNOR2X1TS U3671 ( .A(n2743), .B(n2742), .Y(n2745) );
AOI22X1TS U3672 ( .A0(n2745), .A1(n2744), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]), .B1(n2768), .Y(
n2746) );
OAI2BB1X1TS U3673 ( .A0N(n2807), .A1N(n2747), .B0(n2746), .Y(n1031) );
NAND2X1TS U3674 ( .A(n2751), .B(n2750), .Y(n2754) );
INVX2TS U3675 ( .A(n2754), .Y(n2752) );
XNOR2X1TS U3676 ( .A(n2753), .B(n2752), .Y(n2757) );
XOR2X1TS U3677 ( .A(n2786), .B(n2754), .Y(n2755) );
AOI22X1TS U3678 ( .A0(n2755), .A1(n2803), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]), .B1(n2768), .Y(
n2756) );
OAI2BB1X1TS U3679 ( .A0N(n2807), .A1N(n2757), .B0(n2756), .Y(n1032) );
MXI2X1TS U3680 ( .A(n3229), .B(n3172), .S0(n1674), .Y(n1042) );
INVX2TS U3681 ( .A(n2758), .Y(n2760) );
NAND2X1TS U3682 ( .A(n2760), .B(n2759), .Y(n2763) );
INVX2TS U3683 ( .A(n2763), .Y(n2761) );
XOR2X1TS U3684 ( .A(n2763), .B(n2771), .Y(n2764) );
AOI22X1TS U3685 ( .A0(n2764), .A1(n2803), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .B1(n2768), .Y(n2765) );
OAI2BB1X1TS U3686 ( .A0N(n2807), .A1N(n2766), .B0(n2765), .Y(n1039) );
XNOR2X1TS U3687 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[1]), .B(
n2767), .Y(n2770) );
AOI22X1TS U3688 ( .A0(n2803), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[1]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[1]), .B1(n2768), .Y(n2769) );
OAI2BB1X1TS U3689 ( .A0N(n2807), .A1N(n2770), .B0(n2769), .Y(n1041) );
OR2X1TS U3690 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[2]), .Y(n2772) );
AOI22X1TS U3691 ( .A0(n2774), .A1(n2803), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .B1(n2802), .Y(n2775) );
OAI2BB1X1TS U3692 ( .A0N(n2807), .A1N(n2776), .B0(n2775), .Y(n1040) );
OAI21XLTS U3693 ( .A0(n2796), .A1(n2778), .B0(n2777), .Y(n2783) );
NAND2X1TS U3694 ( .A(n2781), .B(n2780), .Y(n2787) );
INVX2TS U3695 ( .A(n2787), .Y(n2782) );
XNOR2X1TS U3696 ( .A(n2783), .B(n2782), .Y(n2791) );
XNOR2X1TS U3697 ( .A(n2788), .B(n2787), .Y(n2789) );
AOI22X1TS U3698 ( .A0(n2789), .A1(n2803), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .B1(n2802), .Y(
n2790) );
OAI2BB1X1TS U3699 ( .A0N(n2807), .A1N(n2791), .B0(n2790), .Y(n1030) );
INVX2TS U3700 ( .A(n2792), .Y(n2794) );
NAND2X1TS U3701 ( .A(n2794), .B(n2793), .Y(n2800) );
INVX2TS U3702 ( .A(n2800), .Y(n2795) );
XNOR2X1TS U3703 ( .A(n2801), .B(n2800), .Y(n2804) );
AOI22X1TS U3704 ( .A0(n2804), .A1(n2803), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n2802), .Y(n2805) );
OAI2BB1X1TS U3705 ( .A0N(n2807), .A1N(n2806), .B0(n2805), .Y(n1033) );
AOI22X1TS U3706 ( .A0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(
n2818), .B1(n3266), .Y(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_) );
NOR2BX1TS U3707 ( .AN(beg_fsm_cordic), .B(n2810), .Y(
inst_CORDIC_FSM_v3_state_next[1]) );
INVX2TS U3708 ( .A(n2862), .Y(n2857) );
OAI22X1TS U3709 ( .A0(n2857), .A1(n2814), .B0(n2813), .B1(n2812), .Y(
inst_CORDIC_FSM_v3_state_next[5]) );
OAI22X1TS U3710 ( .A0(ack_cordic), .A1(n2816), .B0(n2826), .B1(n2815), .Y(
inst_CORDIC_FSM_v3_state_next[7]) );
NAND2X1TS U3711 ( .A(n2818), .B(n2817), .Y(n1629) );
INVX2TS U3712 ( .A(n2823), .Y(n2825) );
AOI22X1TS U3713 ( .A0(n2825), .A1(n2820), .B0(n3061), .B1(n2823), .Y(n1626)
);
AOI22X1TS U3714 ( .A0(n2825), .A1(n3061), .B0(n3066), .B1(n2823), .Y(n1625)
);
AOI22X1TS U3715 ( .A0(n2825), .A1(n2822), .B0(n2821), .B1(n2823), .Y(n1622)
);
AOI22X1TS U3716 ( .A0(n2825), .A1(n2824), .B0(n3055), .B1(n2823), .Y(n1621)
);
AOI22X1TS U3717 ( .A0(n2828), .A1(n1709), .B0(n2827), .B1(n2826), .Y(n1620)
);
NAND2X1TS U3718 ( .A(n2830), .B(n2829), .Y(n2831) );
XNOR2X1TS U3719 ( .A(cont_iter_out[3]), .B(n2831), .Y(n1617) );
AOI22X1TS U3720 ( .A0(cont_var_out[0]), .A1(n2833), .B0(n2832), .B1(n3097),
.Y(n1616) );
NAND2X1TS U3721 ( .A(n2837), .B(n2836), .Y(n1613) );
BUFX3TS U3722 ( .A(n2867), .Y(n2980) );
INVX2TS U3723 ( .A(n2869), .Y(n2866) );
AOI22X1TS U3724 ( .A0(n2842), .A1(n2841), .B0(d_ff3_LUT_out[7]), .B1(n2866),
.Y(n2844) );
NAND2X1TS U3725 ( .A(n2844), .B(n2843), .Y(n1601) );
BUFX3TS U3726 ( .A(n2851), .Y(n2852) );
BUFX3TS U3727 ( .A(n2851), .Y(n2847) );
INVX2TS U3728 ( .A(n2852), .Y(n2848) );
BUFX3TS U3729 ( .A(n2852), .Y(n2849) );
INVX2TS U3730 ( .A(n2852), .Y(n2850) );
INVX2TS U3731 ( .A(n2852), .Y(n2853) );
BUFX3TS U3732 ( .A(n2863), .Y(n2954) );
OR3X2TS U3733 ( .A(cont_var_out[1]), .B(n3097), .C(n3267), .Y(n2861) );
BUFX3TS U3734 ( .A(n2856), .Y(n2955) );
INVX2TS U3735 ( .A(n2955), .Y(n2985) );
INVX2TS U3736 ( .A(n2856), .Y(n2886) );
BUFX3TS U3737 ( .A(n2855), .Y(n2990) );
INVX2TS U3738 ( .A(n2855), .Y(n2859) );
BUFX3TS U3739 ( .A(n2855), .Y(n2860) );
INVX2TS U3740 ( .A(n2954), .Y(n2864) );
INVX2TS U3741 ( .A(n2856), .Y(n2952) );
INVX2TS U3742 ( .A(n2855), .Y(n2865) );
BUFX3TS U3743 ( .A(n2861), .Y(n2984) );
BUFX3TS U3744 ( .A(n2855), .Y(n2950) );
BUFX3TS U3745 ( .A(n2863), .Y(n2951) );
INVX2TS U3746 ( .A(n2954), .Y(n2953) );
INVX2TS U3747 ( .A(n2990), .Y(n2991) );
OA22X1TS U3748 ( .A0(d_ff_Xn[1]), .A1(n2093), .B0(n2915), .B1(d_ff2_X[1]),
.Y(n1482) );
OA22X1TS U3749 ( .A0(d_ff_Xn[2]), .A1(n2875), .B0(n2915), .B1(d_ff2_X[2]),
.Y(n1480) );
OA22X1TS U3750 ( .A0(d_ff_Xn[3]), .A1(n2093), .B0(n2874), .B1(d_ff2_X[3]),
.Y(n1478) );
INVX2TS U3751 ( .A(n2915), .Y(n2871) );
INVX2TS U3752 ( .A(n2869), .Y(n2868) );
OA22X1TS U3753 ( .A0(d_ff_Xn[5]), .A1(n2875), .B0(n2874), .B1(d_ff2_X[5]),
.Y(n1474) );
OA22X1TS U3754 ( .A0(d_ff_Xn[6]), .A1(n2093), .B0(n2874), .B1(d_ff2_X[6]),
.Y(n1472) );
OA22X1TS U3755 ( .A0(d_ff_Xn[7]), .A1(n2875), .B0(n2874), .B1(d_ff2_X[7]),
.Y(n1470) );
OA22X1TS U3756 ( .A0(d_ff_Xn[10]), .A1(n2875), .B0(n2091), .B1(d_ff2_X[10]),
.Y(n1464) );
BUFX3TS U3757 ( .A(n2867), .Y(n2989) );
BUFX3TS U3758 ( .A(n2915), .Y(n2873) );
OA22X1TS U3759 ( .A0(d_ff_Xn[12]), .A1(n2875), .B0(n2873), .B1(d_ff2_X[12]),
.Y(n1460) );
OA22X1TS U3760 ( .A0(d_ff_Xn[13]), .A1(n2093), .B0(n2873), .B1(d_ff2_X[13]),
.Y(n1458) );
OA22X1TS U3761 ( .A0(d_ff_Xn[14]), .A1(n2875), .B0(n2873), .B1(d_ff2_X[14]),
.Y(n1456) );
OA22X1TS U3762 ( .A0(d_ff_Xn[16]), .A1(n2093), .B0(n2873), .B1(d_ff2_X[16]),
.Y(n1452) );
OA22X1TS U3763 ( .A0(d_ff_Xn[17]), .A1(n2875), .B0(n2873), .B1(d_ff2_X[17]),
.Y(n1450) );
OA22X1TS U3764 ( .A0(d_ff_Xn[19]), .A1(n2093), .B0(n2873), .B1(d_ff2_X[19]),
.Y(n1446) );
OA22X1TS U3765 ( .A0(d_ff_Xn[20]), .A1(n2875), .B0(n2873), .B1(d_ff2_X[20]),
.Y(n1444) );
INVX2TS U3766 ( .A(n2915), .Y(n2897) );
OA22X1TS U3767 ( .A0(d_ff_Xn[24]), .A1(n2093), .B0(n2873), .B1(d_ff2_X[24]),
.Y(n1437) );
OA22X1TS U3768 ( .A0(d_ff_Xn[25]), .A1(n1688), .B0(n2873), .B1(d_ff2_X[25]),
.Y(n1436) );
OA22X1TS U3769 ( .A0(d_ff_Xn[26]), .A1(n2093), .B0(n2873), .B1(d_ff2_X[26]),
.Y(n1435) );
OA22X1TS U3770 ( .A0(d_ff_Xn[27]), .A1(n1688), .B0(n2874), .B1(d_ff2_X[27]),
.Y(n1434) );
OA22X1TS U3771 ( .A0(n2915), .A1(d_ff2_X[28]), .B0(d_ff_Xn[28]), .B1(n1688),
.Y(n1433) );
OA22X1TS U3772 ( .A0(d_ff_Xn[29]), .A1(n2875), .B0(n2874), .B1(d_ff2_X[29]),
.Y(n1432) );
NOR2X1TS U3773 ( .A(d_ff2_X[27]), .B(intadd_357_n1), .Y(n2877) );
AOI21X1TS U3774 ( .A0(intadd_357_n1), .A1(d_ff2_X[27]), .B0(n2877), .Y(n2876) );
OR3X1TS U3775 ( .A(d_ff2_X[27]), .B(d_ff2_X[28]), .C(intadd_357_n1), .Y(
n2880) );
NOR2X1TS U3776 ( .A(d_ff2_X[29]), .B(n2880), .Y(n2882) );
AOI21X1TS U3777 ( .A0(d_ff2_X[29]), .A1(n2880), .B0(n2882), .Y(n2881) );
XOR2X1TS U3778 ( .A(d_ff2_X[30]), .B(n2882), .Y(n2883) );
AOI22X1TS U3779 ( .A0(d_ff2_Y[31]), .A1(n2976), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[31]), .B1(n2975), .Y(n2885) );
AOI22X1TS U3780 ( .A0(d_ff2_Z[31]), .A1(n2900), .B0(n2062), .B1(d_ff2_X[31]),
.Y(n2884) );
NAND2X1TS U3781 ( .A(n2885), .B(n2884), .Y(n1420) );
OA22X1TS U3782 ( .A0(n2856), .A1(result_add_subt[31]), .B0(d_ff_Yn[31]),
.B1(n2886), .Y(n1418) );
AOI22X1TS U3783 ( .A0(d_ff3_sh_x_out[0]), .A1(n2976), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]), .B1(n2981), .Y(n2888) );
AOI22X1TS U3784 ( .A0(n2900), .A1(d_ff3_LUT_out[0]), .B0(n2062), .B1(
d_ff3_sh_y_out[0]), .Y(n2887) );
NAND2X1TS U3785 ( .A(n2888), .B(n2887), .Y(n1415) );
AOI22X1TS U3786 ( .A0(d_ff3_sh_x_out[1]), .A1(n2976), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[1]), .B1(n2916), .Y(n2891) );
AOI22X1TS U3787 ( .A0(n2889), .A1(d_ff3_LUT_out[1]), .B0(n2931), .B1(
d_ff3_sh_y_out[1]), .Y(n2890) );
NAND2X1TS U3788 ( .A(n2891), .B(n2890), .Y(n1412) );
AOI22X1TS U3789 ( .A0(d_ff3_sh_x_out[2]), .A1(n2976), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .B1(n2916), .Y(n2893) );
AOI22X1TS U3790 ( .A0(n2900), .A1(d_ff3_LUT_out[2]), .B0(n2931), .B1(
d_ff3_sh_y_out[2]), .Y(n2892) );
NAND2X1TS U3791 ( .A(n2893), .B(n2892), .Y(n1409) );
BUFX3TS U3792 ( .A(n2906), .Y(n2913) );
INVX2TS U3793 ( .A(n2903), .Y(n2912) );
AOI22X1TS U3794 ( .A0(d_ff3_sh_x_out[4]), .A1(n2976), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[4]), .B1(n2943), .Y(n2896) );
BUFX3TS U3795 ( .A(n2894), .Y(n2944) );
AOI22X1TS U3796 ( .A0(n2944), .A1(d_ff3_LUT_out[4]), .B0(n2931), .B1(
d_ff3_sh_y_out[4]), .Y(n2895) );
NAND2X1TS U3797 ( .A(n2896), .B(n2895), .Y(n1403) );
INVX2TS U3798 ( .A(n2915), .Y(n2914) );
AOI22X1TS U3799 ( .A0(d_ff3_sh_x_out[6]), .A1(n2976), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .B1(n2981), .Y(n2899) );
AOI22X1TS U3800 ( .A0(n2900), .A1(d_ff3_LUT_out[6]), .B0(n2931), .B1(
d_ff3_sh_y_out[6]), .Y(n2898) );
NAND2X1TS U3801 ( .A(n2899), .B(n2898), .Y(n1397) );
AOI22X1TS U3802 ( .A0(d_ff3_sh_x_out[8]), .A1(n2976), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]), .B1(n2916), .Y(n2902) );
AOI22X1TS U3803 ( .A0(n2900), .A1(d_ff3_LUT_out[8]), .B0(n2909), .B1(
d_ff3_sh_y_out[8]), .Y(n2901) );
NAND2X1TS U3804 ( .A(n2902), .B(n2901), .Y(n1391) );
AOI22X1TS U3805 ( .A0(d_ff3_sh_x_out[9]), .A1(n2976), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .B1(n2943), .Y(n2905) );
AOI22X1TS U3806 ( .A0(n2944), .A1(d_ff3_LUT_out[9]), .B0(n2909), .B1(
d_ff3_sh_y_out[9]), .Y(n2904) );
NAND2X1TS U3807 ( .A(n2905), .B(n2904), .Y(n1388) );
BUFX3TS U3808 ( .A(n2906), .Y(n2920) );
AOI22X1TS U3809 ( .A0(d_ff3_sh_x_out[10]), .A1(n2971), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .B1(n2981), .Y(n2908) );
AOI22X1TS U3810 ( .A0(n2944), .A1(d_ff3_LUT_out[10]), .B0(n2931), .B1(
d_ff3_sh_y_out[10]), .Y(n2907) );
NAND2X1TS U3811 ( .A(n2908), .B(n2907), .Y(n1385) );
AOI22X1TS U3812 ( .A0(d_ff3_sh_x_out[12]), .A1(n2971), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .B1(n2943), .Y(n2911) );
AOI22X1TS U3813 ( .A0(n2944), .A1(d_ff3_LUT_out[12]), .B0(n2909), .B1(
d_ff3_sh_y_out[12]), .Y(n2910) );
NAND2X1TS U3814 ( .A(n2911), .B(n2910), .Y(n1379) );
INVX2TS U3815 ( .A(n2915), .Y(n2921) );
AOI22X1TS U3816 ( .A0(d_ff3_sh_x_out[21]), .A1(n2930), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .B1(n2981), .Y(n2918) );
AOI22X1TS U3817 ( .A0(n2944), .A1(d_ff3_LUT_out[21]), .B0(n2931), .B1(
d_ff3_sh_y_out[21]), .Y(n2917) );
NAND2X1TS U3818 ( .A(n2918), .B(n2917), .Y(n1352) );
AOI22X1TS U3819 ( .A0(d_ff3_sh_x_out[23]), .A1(n2930), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .B1(n2981), .Y(n2924) );
AOI22X1TS U3820 ( .A0(n2944), .A1(d_ff3_LUT_out[23]), .B0(n2931), .B1(
d_ff3_sh_y_out[23]), .Y(n2923) );
NAND2X1TS U3821 ( .A(n2924), .B(n2923), .Y(n1339) );
AOI22X1TS U3822 ( .A0(d_ff3_sh_x_out[24]), .A1(n2930), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .B1(n2916), .Y(n2926) );
AOI22X1TS U3823 ( .A0(n2944), .A1(d_ff3_LUT_out[24]), .B0(n2931), .B1(
d_ff3_sh_y_out[24]), .Y(n2925) );
NAND2X1TS U3824 ( .A(n2926), .B(n2925), .Y(n1337) );
AOI22X1TS U3825 ( .A0(d_ff3_sh_x_out[25]), .A1(n2930), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]), .B1(n2916), .Y(n2928) );
AOI22X1TS U3826 ( .A0(n2944), .A1(d_ff3_LUT_out[25]), .B0(n2931), .B1(
d_ff3_sh_y_out[25]), .Y(n2927) );
NAND2X1TS U3827 ( .A(n2928), .B(n2927), .Y(n1335) );
AOI22X1TS U3828 ( .A0(d_ff3_sh_x_out[26]), .A1(n2930), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]), .B1(n2943), .Y(n2933) );
AOI22X1TS U3829 ( .A0(n2944), .A1(d_ff3_LUT_out[26]), .B0(n2931), .B1(
d_ff3_sh_y_out[26]), .Y(n2932) );
NAND2X1TS U3830 ( .A(n2933), .B(n2932), .Y(n1333) );
NOR2X1TS U3831 ( .A(d_ff2_Y[27]), .B(intadd_356_n1), .Y(n2935) );
AOI21X1TS U3832 ( .A0(intadd_356_n1), .A1(d_ff2_Y[27]), .B0(n2935), .Y(n2934) );
OR3X1TS U3833 ( .A(d_ff2_Y[27]), .B(d_ff2_Y[28]), .C(intadd_356_n1), .Y(
n2937) );
NOR2X1TS U3834 ( .A(d_ff2_Y[29]), .B(n2937), .Y(n2941) );
AOI21X1TS U3835 ( .A0(d_ff2_Y[29]), .A1(n2937), .B0(n2941), .Y(n2939) );
XOR2X1TS U3836 ( .A(d_ff2_Y[30]), .B(n2941), .Y(n2942) );
AOI22X1TS U3837 ( .A0(d_ff2_Y[30]), .A1(n2961), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[30]), .B1(n2943), .Y(n2946) );
AOI22X1TS U3838 ( .A0(n2944), .A1(d_ff2_Z[30]), .B0(n2209), .B1(d_ff2_X[30]),
.Y(n2945) );
NAND2X1TS U3839 ( .A(n2946), .B(n2945), .Y(n1324) );
OAI22X1TS U3840 ( .A0(n2949), .A1(n2948), .B0(n2947), .B1(n3081), .Y(n1323)
);
INVX2TS U3841 ( .A(n2954), .Y(n2956) );
AOI22X1TS U3842 ( .A0(d_ff2_Y[5]), .A1(n2961), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[5]), .B1(n2965), .Y(n2958) );
AOI22X1TS U3843 ( .A0(n2962), .A1(d_ff2_Z[5]), .B0(n2209), .B1(d_ff2_X[5]),
.Y(n2957) );
NAND2X1TS U3844 ( .A(n2958), .B(n2957), .Y(n1264) );
AOI22X1TS U3845 ( .A0(d_ff2_Y[6]), .A1(n2961), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .B1(n2965), .Y(n2960) );
AOI22X1TS U3846 ( .A0(n2962), .A1(d_ff2_Z[6]), .B0(n2209), .B1(d_ff2_X[6]),
.Y(n2959) );
NAND2X1TS U3847 ( .A(n2960), .B(n2959), .Y(n1262) );
AOI22X1TS U3848 ( .A0(d_ff2_Y[7]), .A1(n2961), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[7]), .B1(n2965), .Y(n2964) );
AOI22X1TS U3849 ( .A0(n2962), .A1(d_ff2_Z[7]), .B0(n2062), .B1(d_ff2_X[7]),
.Y(n2963) );
NAND2X1TS U3850 ( .A(n2964), .B(n2963), .Y(n1260) );
AOI22X1TS U3851 ( .A0(d_ff2_Y[10]), .A1(n2066), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .B1(n2965), .Y(n2968) );
AOI22X1TS U3852 ( .A0(n2966), .A1(d_ff2_Z[10]), .B0(n2062), .B1(d_ff2_X[10]),
.Y(n2967) );
NAND2X1TS U3853 ( .A(n2968), .B(n2967), .Y(n1254) );
AOI22X1TS U3854 ( .A0(d_ff2_Y[24]), .A1(n2971), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .B1(n2975), .Y(n2970) );
AOI22X1TS U3855 ( .A0(n2889), .A1(d_ff2_Z[24]), .B0(n2972), .B1(d_ff2_X[24]),
.Y(n2969) );
NAND2X1TS U3856 ( .A(n2970), .B(n2969), .Y(n1226) );
AOI22X1TS U3857 ( .A0(d_ff2_Y[25]), .A1(n2971), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[25]), .B1(n2975), .Y(n2974) );
AOI22X1TS U3858 ( .A0(n2032), .A1(d_ff2_Z[25]), .B0(n2972), .B1(d_ff2_X[25]),
.Y(n2973) );
NAND2X1TS U3859 ( .A(n2974), .B(n2973), .Y(n1224) );
AOI22X1TS U3860 ( .A0(d_ff2_Y[28]), .A1(n2976), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[28]), .B1(n2975), .Y(n2978) );
AOI22X1TS U3861 ( .A0(n2032), .A1(d_ff2_Z[28]), .B0(n2033), .B1(d_ff2_X[28]),
.Y(n2977) );
NAND2X1TS U3862 ( .A(n2978), .B(n2977), .Y(n1218) );
INVX2TS U3863 ( .A(n2983), .Y(n2981) );
AOI22X1TS U3864 ( .A0(n2991), .A1(n3090), .B0(n3173), .B1(n2990), .Y(n1206)
);
XNOR2X1TS U3865 ( .A(n2994), .B(n2993), .Y(n2995) );
CLKBUFX2TS U3866 ( .A(n3057), .Y(n3007) );
AOI21X1TS U3867 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[24]), .A1(
n1657), .B0(n2996), .Y(n2997) );
XNOR2X1TS U3868 ( .A(n2998), .B(n2997), .Y(n2999) );
OAI22X1TS U3869 ( .A0(n3003), .A1(n3002), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[26]), .B1(n3135), .Y(n3005)
);
XNOR2X1TS U3870 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[27]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[27]), .Y(n3004) );
XOR2X1TS U3871 ( .A(n3005), .B(n3004), .Y(n3006) );
BUFX3TS U3872 ( .A(n3057), .Y(n3020) );
INVX2TS U3873 ( .A(n1660), .Y(n3059) );
INVX2TS U3874 ( .A(n3061), .Y(n3025) );
OAI222X1TS U3875 ( .A0(n3013), .A1(n3134), .B0(n1657), .B1(n3012), .C0(n3069), .C1(n3011), .Y(n1109) );
OAI222X1TS U3876 ( .A0(n3013), .A1(n3086), .B0(n3136), .B1(n3012), .C0(n3118), .C1(n3011), .Y(n1108) );
OAI222X1TS U3877 ( .A0(n3013), .A1(n3087), .B0(n1658), .B1(n3012), .C0(n3117), .C1(n3011), .Y(n1107) );
OAI2BB2XLTS U3878 ( .B0(n3017), .B1(n1664), .A0N(n3055), .A1N(
result_add_subt[22]), .Y(n1101) );
BUFX3TS U3879 ( .A(n1683), .Y(n3029) );
OAI2BB2XLTS U3880 ( .B0(n3018), .B1(n1664), .A0N(n3029), .A1N(
result_add_subt[15]), .Y(n1098) );
OAI2BB2XLTS U3881 ( .B0(n3019), .B1(n1664), .A0N(n3029), .A1N(
result_add_subt[18]), .Y(n1095) );
OAI2BB2XLTS U3882 ( .B0(n3021), .B1(n1664), .A0N(n3029), .A1N(
result_add_subt[21]), .Y(n1092) );
BUFX3TS U3883 ( .A(n3057), .Y(n3033) );
OAI2BB2XLTS U3884 ( .B0(n3022), .B1(n1664), .A0N(n3029), .A1N(
result_add_subt[19]), .Y(n1089) );
OAI2BB2XLTS U3885 ( .B0(n3023), .B1(n1664), .A0N(n3029), .A1N(
result_add_subt[20]), .Y(n1086) );
OAI2BB2XLTS U3886 ( .B0(n3024), .B1(n1663), .A0N(n3029), .A1N(
result_add_subt[17]), .Y(n1083) );
OAI2BB2XLTS U3887 ( .B0(n3026), .B1(n1663), .A0N(n3029), .A1N(
result_add_subt[4]), .Y(n1080) );
INVX2TS U3888 ( .A(n3061), .Y(n3041) );
OAI2BB2XLTS U3889 ( .B0(n3027), .B1(n1663), .A0N(n3029), .A1N(
result_add_subt[6]), .Y(n1077) );
OAI2BB2XLTS U3890 ( .B0(n3028), .B1(n1663), .A0N(n3029), .A1N(
result_add_subt[13]), .Y(n1074) );
OAI2BB2XLTS U3891 ( .B0(n3030), .B1(n1663), .A0N(n3029), .A1N(
result_add_subt[16]), .Y(n1071) );
BUFX3TS U3892 ( .A(n1683), .Y(n3046) );
OAI2BB2XLTS U3893 ( .B0(n3031), .B1(n1663), .A0N(n3046), .A1N(
result_add_subt[8]), .Y(n1068) );
OAI2BB2XLTS U3894 ( .B0(n3032), .B1(n3049), .A0N(n3046), .A1N(
result_add_subt[11]), .Y(n1065) );
OAI2BB2XLTS U3895 ( .B0(n3034), .B1(n1664), .A0N(n3046), .A1N(
result_add_subt[14]), .Y(n1062) );
OAI2BB2XLTS U3896 ( .B0(n3035), .B1(n3049), .A0N(n3046), .A1N(
result_add_subt[10]), .Y(n1059) );
OAI2BB2XLTS U3897 ( .B0(n3036), .B1(n3049), .A0N(n3046), .A1N(
result_add_subt[12]), .Y(n1056) );
OAI2BB2XLTS U3898 ( .B0(n3042), .B1(n3049), .A0N(n3046), .A1N(
result_add_subt[3]), .Y(n1022) );
OAI2BB2XLTS U3899 ( .B0(n3043), .B1(n3049), .A0N(n3046), .A1N(
result_add_subt[2]), .Y(n1006) );
OAI2BB2XLTS U3900 ( .B0(n3044), .B1(n3049), .A0N(n3046), .A1N(
result_add_subt[7]), .Y(n999) );
OAI2BB2XLTS U3901 ( .B0(n3045), .B1(n3049), .A0N(n3046), .A1N(
result_add_subt[0]), .Y(n992) );
OAI2BB2XLTS U3902 ( .B0(n3047), .B1(n3049), .A0N(n3046), .A1N(
result_add_subt[1]), .Y(n985) );
OAI2BB2XLTS U3903 ( .B0(n3048), .B1(n3049), .A0N(n1638), .A1N(
result_add_subt[9]), .Y(n978) );
INVX2TS U3904 ( .A(n3064), .Y(n3058) );
OAI2BB2XLTS U3905 ( .B0(n3050), .B1(n1663), .A0N(n3055), .A1N(
result_add_subt[5]), .Y(n971) );
BUFX3TS U3906 ( .A(n3057), .Y(n3060) );
INVX2TS U3907 ( .A(n1660), .Y(n3063) );
INVX2TS U3908 ( .A(n3064), .Y(n3062) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk10.tcl_syn.sdf");
endmodule
|
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
RAM64X1D #(
.INIT(64'b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000010)
) ram3 (
.WCLK (clk),
.A5 (sw[5]),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.DPRA5 (sw[11]),
.DPRA4 (sw[10]),
.DPRA3 (sw[9]),
.DPRA2 (sw[8]),
.DPRA1 (sw[7]),
.DPRA0 (sw[6]),
.SPO (led[0]),
.DPO (led[1]),
.D (sw[13]),
.WE (sw[15])
);
RAM64X1D #(
.INIT(64'b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000010)
) ram4 (
.WCLK (clk),
.A5 (sw[5]),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.DPRA5 (sw[11]),
.DPRA4 (sw[10]),
.DPRA3 (sw[9]),
.DPRA2 (sw[8]),
.DPRA1 (sw[7]),
.DPRA0 (sw[6]),
.SPO (led[2]),
.DPO (led[3]),
.D (sw[12]),
.WE (sw[15])
);
assign led[15:4] = sw[15:4];
assign tx = rx;
endmodule
|
//megafunction wizard: %Altera SOPC Builder%
//GENERATION: STANDARD
//VERSION: WM1.0
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_jtag_debug_module_arbitrator (
// inputs:
clk,
cpu_data_master_address_to_slave,
cpu_data_master_byteenable,
cpu_data_master_debugaccess,
cpu_data_master_read,
cpu_data_master_waitrequest,
cpu_data_master_write,
cpu_data_master_writedata,
cpu_instruction_master_address_to_slave,
cpu_instruction_master_latency_counter,
cpu_instruction_master_read,
cpu_jtag_debug_module_readdata,
cpu_jtag_debug_module_resetrequest,
reset_n,
// outputs:
cpu_data_master_granted_cpu_jtag_debug_module,
cpu_data_master_qualified_request_cpu_jtag_debug_module,
cpu_data_master_read_data_valid_cpu_jtag_debug_module,
cpu_data_master_requests_cpu_jtag_debug_module,
cpu_instruction_master_granted_cpu_jtag_debug_module,
cpu_instruction_master_qualified_request_cpu_jtag_debug_module,
cpu_instruction_master_read_data_valid_cpu_jtag_debug_module,
cpu_instruction_master_requests_cpu_jtag_debug_module,
cpu_jtag_debug_module_address,
cpu_jtag_debug_module_begintransfer,
cpu_jtag_debug_module_byteenable,
cpu_jtag_debug_module_chipselect,
cpu_jtag_debug_module_debugaccess,
cpu_jtag_debug_module_readdata_from_sa,
cpu_jtag_debug_module_reset_n,
cpu_jtag_debug_module_resetrequest_from_sa,
cpu_jtag_debug_module_write,
cpu_jtag_debug_module_writedata,
d1_cpu_jtag_debug_module_end_xfer
)
;
output cpu_data_master_granted_cpu_jtag_debug_module;
output cpu_data_master_qualified_request_cpu_jtag_debug_module;
output cpu_data_master_read_data_valid_cpu_jtag_debug_module;
output cpu_data_master_requests_cpu_jtag_debug_module;
output cpu_instruction_master_granted_cpu_jtag_debug_module;
output cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
output cpu_instruction_master_read_data_valid_cpu_jtag_debug_module;
output cpu_instruction_master_requests_cpu_jtag_debug_module;
output [ 8: 0] cpu_jtag_debug_module_address;
output cpu_jtag_debug_module_begintransfer;
output [ 3: 0] cpu_jtag_debug_module_byteenable;
output cpu_jtag_debug_module_chipselect;
output cpu_jtag_debug_module_debugaccess;
output [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
output cpu_jtag_debug_module_reset_n;
output cpu_jtag_debug_module_resetrequest_from_sa;
output cpu_jtag_debug_module_write;
output [ 31: 0] cpu_jtag_debug_module_writedata;
output d1_cpu_jtag_debug_module_end_xfer;
input clk;
input [ 23: 0] cpu_data_master_address_to_slave;
input [ 3: 0] cpu_data_master_byteenable;
input cpu_data_master_debugaccess;
input cpu_data_master_read;
input cpu_data_master_waitrequest;
input cpu_data_master_write;
input [ 31: 0] cpu_data_master_writedata;
input [ 23: 0] cpu_instruction_master_address_to_slave;
input [ 1: 0] cpu_instruction_master_latency_counter;
input cpu_instruction_master_read;
input [ 31: 0] cpu_jtag_debug_module_readdata;
input cpu_jtag_debug_module_resetrequest;
input reset_n;
wire cpu_data_master_arbiterlock;
wire cpu_data_master_arbiterlock2;
wire cpu_data_master_continuerequest;
wire cpu_data_master_granted_cpu_jtag_debug_module;
wire cpu_data_master_qualified_request_cpu_jtag_debug_module;
wire cpu_data_master_read_data_valid_cpu_jtag_debug_module;
wire cpu_data_master_requests_cpu_jtag_debug_module;
wire cpu_data_master_saved_grant_cpu_jtag_debug_module;
wire cpu_instruction_master_arbiterlock;
wire cpu_instruction_master_arbiterlock2;
wire cpu_instruction_master_continuerequest;
wire cpu_instruction_master_granted_cpu_jtag_debug_module;
wire cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
wire cpu_instruction_master_read_data_valid_cpu_jtag_debug_module;
wire cpu_instruction_master_requests_cpu_jtag_debug_module;
wire cpu_instruction_master_saved_grant_cpu_jtag_debug_module;
wire [ 8: 0] cpu_jtag_debug_module_address;
wire cpu_jtag_debug_module_allgrants;
wire cpu_jtag_debug_module_allow_new_arb_cycle;
wire cpu_jtag_debug_module_any_bursting_master_saved_grant;
wire cpu_jtag_debug_module_any_continuerequest;
reg [ 1: 0] cpu_jtag_debug_module_arb_addend;
wire cpu_jtag_debug_module_arb_counter_enable;
reg [ 2: 0] cpu_jtag_debug_module_arb_share_counter;
wire [ 2: 0] cpu_jtag_debug_module_arb_share_counter_next_value;
wire [ 2: 0] cpu_jtag_debug_module_arb_share_set_values;
wire [ 1: 0] cpu_jtag_debug_module_arb_winner;
wire cpu_jtag_debug_module_arbitration_holdoff_internal;
wire cpu_jtag_debug_module_beginbursttransfer_internal;
wire cpu_jtag_debug_module_begins_xfer;
wire cpu_jtag_debug_module_begintransfer;
wire [ 3: 0] cpu_jtag_debug_module_byteenable;
wire cpu_jtag_debug_module_chipselect;
wire [ 3: 0] cpu_jtag_debug_module_chosen_master_double_vector;
wire [ 1: 0] cpu_jtag_debug_module_chosen_master_rot_left;
wire cpu_jtag_debug_module_debugaccess;
wire cpu_jtag_debug_module_end_xfer;
wire cpu_jtag_debug_module_firsttransfer;
wire [ 1: 0] cpu_jtag_debug_module_grant_vector;
wire cpu_jtag_debug_module_in_a_read_cycle;
wire cpu_jtag_debug_module_in_a_write_cycle;
wire [ 1: 0] cpu_jtag_debug_module_master_qreq_vector;
wire cpu_jtag_debug_module_non_bursting_master_requests;
wire [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
reg cpu_jtag_debug_module_reg_firsttransfer;
wire cpu_jtag_debug_module_reset_n;
wire cpu_jtag_debug_module_resetrequest_from_sa;
reg [ 1: 0] cpu_jtag_debug_module_saved_chosen_master_vector;
reg cpu_jtag_debug_module_slavearbiterlockenable;
wire cpu_jtag_debug_module_slavearbiterlockenable2;
wire cpu_jtag_debug_module_unreg_firsttransfer;
wire cpu_jtag_debug_module_waits_for_read;
wire cpu_jtag_debug_module_waits_for_write;
wire cpu_jtag_debug_module_write;
wire [ 31: 0] cpu_jtag_debug_module_writedata;
reg d1_cpu_jtag_debug_module_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_cpu_jtag_debug_module;
wire in_a_read_cycle;
wire in_a_write_cycle;
reg last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module;
reg last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module;
wire [ 23: 0] shifted_address_to_cpu_jtag_debug_module_from_cpu_data_master;
wire [ 23: 0] shifted_address_to_cpu_jtag_debug_module_from_cpu_instruction_master;
wire wait_for_cpu_jtag_debug_module_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~cpu_jtag_debug_module_end_xfer;
end
assign cpu_jtag_debug_module_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_cpu_jtag_debug_module | cpu_instruction_master_qualified_request_cpu_jtag_debug_module));
//assign cpu_jtag_debug_module_readdata_from_sa = cpu_jtag_debug_module_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign cpu_jtag_debug_module_readdata_from_sa = cpu_jtag_debug_module_readdata;
assign cpu_data_master_requests_cpu_jtag_debug_module = ({cpu_data_master_address_to_slave[23 : 11] , 11'b0} == 24'hb03000) & (cpu_data_master_read | cpu_data_master_write);
//cpu_jtag_debug_module_arb_share_counter set values, which is an e_mux
assign cpu_jtag_debug_module_arb_share_set_values = 1;
//cpu_jtag_debug_module_non_bursting_master_requests mux, which is an e_mux
assign cpu_jtag_debug_module_non_bursting_master_requests = cpu_data_master_requests_cpu_jtag_debug_module |
cpu_instruction_master_requests_cpu_jtag_debug_module |
cpu_data_master_requests_cpu_jtag_debug_module |
cpu_instruction_master_requests_cpu_jtag_debug_module;
//cpu_jtag_debug_module_any_bursting_master_saved_grant mux, which is an e_mux
assign cpu_jtag_debug_module_any_bursting_master_saved_grant = 0;
//cpu_jtag_debug_module_arb_share_counter_next_value assignment, which is an e_assign
assign cpu_jtag_debug_module_arb_share_counter_next_value = cpu_jtag_debug_module_firsttransfer ? (cpu_jtag_debug_module_arb_share_set_values - 1) : |cpu_jtag_debug_module_arb_share_counter ? (cpu_jtag_debug_module_arb_share_counter - 1) : 0;
//cpu_jtag_debug_module_allgrants all slave grants, which is an e_mux
assign cpu_jtag_debug_module_allgrants = (|cpu_jtag_debug_module_grant_vector) |
(|cpu_jtag_debug_module_grant_vector) |
(|cpu_jtag_debug_module_grant_vector) |
(|cpu_jtag_debug_module_grant_vector);
//cpu_jtag_debug_module_end_xfer assignment, which is an e_assign
assign cpu_jtag_debug_module_end_xfer = ~(cpu_jtag_debug_module_waits_for_read | cpu_jtag_debug_module_waits_for_write);
//end_xfer_arb_share_counter_term_cpu_jtag_debug_module arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_cpu_jtag_debug_module = cpu_jtag_debug_module_end_xfer & (~cpu_jtag_debug_module_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//cpu_jtag_debug_module_arb_share_counter arbitration counter enable, which is an e_assign
assign cpu_jtag_debug_module_arb_counter_enable = (end_xfer_arb_share_counter_term_cpu_jtag_debug_module & cpu_jtag_debug_module_allgrants) | (end_xfer_arb_share_counter_term_cpu_jtag_debug_module & ~cpu_jtag_debug_module_non_bursting_master_requests);
//cpu_jtag_debug_module_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_jtag_debug_module_arb_share_counter <= 0;
else if (cpu_jtag_debug_module_arb_counter_enable)
cpu_jtag_debug_module_arb_share_counter <= cpu_jtag_debug_module_arb_share_counter_next_value;
end
//cpu_jtag_debug_module_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_jtag_debug_module_slavearbiterlockenable <= 0;
else if ((|cpu_jtag_debug_module_master_qreq_vector & end_xfer_arb_share_counter_term_cpu_jtag_debug_module) | (end_xfer_arb_share_counter_term_cpu_jtag_debug_module & ~cpu_jtag_debug_module_non_bursting_master_requests))
cpu_jtag_debug_module_slavearbiterlockenable <= |cpu_jtag_debug_module_arb_share_counter_next_value;
end
//cpu/data_master cpu/jtag_debug_module arbiterlock, which is an e_assign
assign cpu_data_master_arbiterlock = cpu_jtag_debug_module_slavearbiterlockenable & cpu_data_master_continuerequest;
//cpu_jtag_debug_module_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign cpu_jtag_debug_module_slavearbiterlockenable2 = |cpu_jtag_debug_module_arb_share_counter_next_value;
//cpu/data_master cpu/jtag_debug_module arbiterlock2, which is an e_assign
assign cpu_data_master_arbiterlock2 = cpu_jtag_debug_module_slavearbiterlockenable2 & cpu_data_master_continuerequest;
//cpu/instruction_master cpu/jtag_debug_module arbiterlock, which is an e_assign
assign cpu_instruction_master_arbiterlock = cpu_jtag_debug_module_slavearbiterlockenable & cpu_instruction_master_continuerequest;
//cpu/instruction_master cpu/jtag_debug_module arbiterlock2, which is an e_assign
assign cpu_instruction_master_arbiterlock2 = cpu_jtag_debug_module_slavearbiterlockenable2 & cpu_instruction_master_continuerequest;
//cpu/instruction_master granted cpu/jtag_debug_module last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module <= 0;
else
last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module <= cpu_instruction_master_saved_grant_cpu_jtag_debug_module ? 1 : (cpu_jtag_debug_module_arbitration_holdoff_internal | ~cpu_instruction_master_requests_cpu_jtag_debug_module) ? 0 : last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module;
end
//cpu_instruction_master_continuerequest continued request, which is an e_mux
assign cpu_instruction_master_continuerequest = last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module & cpu_instruction_master_requests_cpu_jtag_debug_module;
//cpu_jtag_debug_module_any_continuerequest at least one master continues requesting, which is an e_mux
assign cpu_jtag_debug_module_any_continuerequest = cpu_instruction_master_continuerequest |
cpu_data_master_continuerequest;
assign cpu_data_master_qualified_request_cpu_jtag_debug_module = cpu_data_master_requests_cpu_jtag_debug_module & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write) | cpu_instruction_master_arbiterlock);
//cpu_jtag_debug_module_writedata mux, which is an e_mux
assign cpu_jtag_debug_module_writedata = cpu_data_master_writedata;
assign cpu_instruction_master_requests_cpu_jtag_debug_module = (({cpu_instruction_master_address_to_slave[23 : 11] , 11'b0} == 24'hb03000) & (cpu_instruction_master_read)) & cpu_instruction_master_read;
//cpu/data_master granted cpu/jtag_debug_module last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module <= 0;
else
last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module <= cpu_data_master_saved_grant_cpu_jtag_debug_module ? 1 : (cpu_jtag_debug_module_arbitration_holdoff_internal | ~cpu_data_master_requests_cpu_jtag_debug_module) ? 0 : last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module;
end
//cpu_data_master_continuerequest continued request, which is an e_mux
assign cpu_data_master_continuerequest = last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module & cpu_data_master_requests_cpu_jtag_debug_module;
assign cpu_instruction_master_qualified_request_cpu_jtag_debug_module = cpu_instruction_master_requests_cpu_jtag_debug_module & ~((cpu_instruction_master_read & ((cpu_instruction_master_latency_counter != 0))) | cpu_data_master_arbiterlock);
//local readdatavalid cpu_instruction_master_read_data_valid_cpu_jtag_debug_module, which is an e_mux
assign cpu_instruction_master_read_data_valid_cpu_jtag_debug_module = cpu_instruction_master_granted_cpu_jtag_debug_module & cpu_instruction_master_read & ~cpu_jtag_debug_module_waits_for_read;
//allow new arb cycle for cpu/jtag_debug_module, which is an e_assign
assign cpu_jtag_debug_module_allow_new_arb_cycle = ~cpu_data_master_arbiterlock & ~cpu_instruction_master_arbiterlock;
//cpu/instruction_master assignment into master qualified-requests vector for cpu/jtag_debug_module, which is an e_assign
assign cpu_jtag_debug_module_master_qreq_vector[0] = cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
//cpu/instruction_master grant cpu/jtag_debug_module, which is an e_assign
assign cpu_instruction_master_granted_cpu_jtag_debug_module = cpu_jtag_debug_module_grant_vector[0];
//cpu/instruction_master saved-grant cpu/jtag_debug_module, which is an e_assign
assign cpu_instruction_master_saved_grant_cpu_jtag_debug_module = cpu_jtag_debug_module_arb_winner[0] && cpu_instruction_master_requests_cpu_jtag_debug_module;
//cpu/data_master assignment into master qualified-requests vector for cpu/jtag_debug_module, which is an e_assign
assign cpu_jtag_debug_module_master_qreq_vector[1] = cpu_data_master_qualified_request_cpu_jtag_debug_module;
//cpu/data_master grant cpu/jtag_debug_module, which is an e_assign
assign cpu_data_master_granted_cpu_jtag_debug_module = cpu_jtag_debug_module_grant_vector[1];
//cpu/data_master saved-grant cpu/jtag_debug_module, which is an e_assign
assign cpu_data_master_saved_grant_cpu_jtag_debug_module = cpu_jtag_debug_module_arb_winner[1] && cpu_data_master_requests_cpu_jtag_debug_module;
//cpu/jtag_debug_module chosen-master double-vector, which is an e_assign
assign cpu_jtag_debug_module_chosen_master_double_vector = {cpu_jtag_debug_module_master_qreq_vector, cpu_jtag_debug_module_master_qreq_vector} & ({~cpu_jtag_debug_module_master_qreq_vector, ~cpu_jtag_debug_module_master_qreq_vector} + cpu_jtag_debug_module_arb_addend);
//stable onehot encoding of arb winner
assign cpu_jtag_debug_module_arb_winner = (cpu_jtag_debug_module_allow_new_arb_cycle & | cpu_jtag_debug_module_grant_vector) ? cpu_jtag_debug_module_grant_vector : cpu_jtag_debug_module_saved_chosen_master_vector;
//saved cpu_jtag_debug_module_grant_vector, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_jtag_debug_module_saved_chosen_master_vector <= 0;
else if (cpu_jtag_debug_module_allow_new_arb_cycle)
cpu_jtag_debug_module_saved_chosen_master_vector <= |cpu_jtag_debug_module_grant_vector ? cpu_jtag_debug_module_grant_vector : cpu_jtag_debug_module_saved_chosen_master_vector;
end
//onehot encoding of chosen master
assign cpu_jtag_debug_module_grant_vector = {(cpu_jtag_debug_module_chosen_master_double_vector[1] | cpu_jtag_debug_module_chosen_master_double_vector[3]),
(cpu_jtag_debug_module_chosen_master_double_vector[0] | cpu_jtag_debug_module_chosen_master_double_vector[2])};
//cpu/jtag_debug_module chosen master rotated left, which is an e_assign
assign cpu_jtag_debug_module_chosen_master_rot_left = (cpu_jtag_debug_module_arb_winner << 1) ? (cpu_jtag_debug_module_arb_winner << 1) : 1;
//cpu/jtag_debug_module's addend for next-master-grant
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_jtag_debug_module_arb_addend <= 1;
else if (|cpu_jtag_debug_module_grant_vector)
cpu_jtag_debug_module_arb_addend <= cpu_jtag_debug_module_end_xfer? cpu_jtag_debug_module_chosen_master_rot_left : cpu_jtag_debug_module_grant_vector;
end
assign cpu_jtag_debug_module_begintransfer = cpu_jtag_debug_module_begins_xfer;
//cpu_jtag_debug_module_reset_n assignment, which is an e_assign
assign cpu_jtag_debug_module_reset_n = reset_n;
//assign cpu_jtag_debug_module_resetrequest_from_sa = cpu_jtag_debug_module_resetrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
assign cpu_jtag_debug_module_resetrequest_from_sa = cpu_jtag_debug_module_resetrequest;
assign cpu_jtag_debug_module_chipselect = cpu_data_master_granted_cpu_jtag_debug_module | cpu_instruction_master_granted_cpu_jtag_debug_module;
//cpu_jtag_debug_module_firsttransfer first transaction, which is an e_assign
assign cpu_jtag_debug_module_firsttransfer = cpu_jtag_debug_module_begins_xfer ? cpu_jtag_debug_module_unreg_firsttransfer : cpu_jtag_debug_module_reg_firsttransfer;
//cpu_jtag_debug_module_unreg_firsttransfer first transaction, which is an e_assign
assign cpu_jtag_debug_module_unreg_firsttransfer = ~(cpu_jtag_debug_module_slavearbiterlockenable & cpu_jtag_debug_module_any_continuerequest);
//cpu_jtag_debug_module_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_jtag_debug_module_reg_firsttransfer <= 1'b1;
else if (cpu_jtag_debug_module_begins_xfer)
cpu_jtag_debug_module_reg_firsttransfer <= cpu_jtag_debug_module_unreg_firsttransfer;
end
//cpu_jtag_debug_module_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign cpu_jtag_debug_module_beginbursttransfer_internal = cpu_jtag_debug_module_begins_xfer;
//cpu_jtag_debug_module_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
assign cpu_jtag_debug_module_arbitration_holdoff_internal = cpu_jtag_debug_module_begins_xfer & cpu_jtag_debug_module_firsttransfer;
//cpu_jtag_debug_module_write assignment, which is an e_mux
assign cpu_jtag_debug_module_write = cpu_data_master_granted_cpu_jtag_debug_module & cpu_data_master_write;
assign shifted_address_to_cpu_jtag_debug_module_from_cpu_data_master = cpu_data_master_address_to_slave;
//cpu_jtag_debug_module_address mux, which is an e_mux
assign cpu_jtag_debug_module_address = (cpu_data_master_granted_cpu_jtag_debug_module)? (shifted_address_to_cpu_jtag_debug_module_from_cpu_data_master >> 2) :
(shifted_address_to_cpu_jtag_debug_module_from_cpu_instruction_master >> 2);
assign shifted_address_to_cpu_jtag_debug_module_from_cpu_instruction_master = cpu_instruction_master_address_to_slave;
//d1_cpu_jtag_debug_module_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_cpu_jtag_debug_module_end_xfer <= 1;
else
d1_cpu_jtag_debug_module_end_xfer <= cpu_jtag_debug_module_end_xfer;
end
//cpu_jtag_debug_module_waits_for_read in a cycle, which is an e_mux
assign cpu_jtag_debug_module_waits_for_read = cpu_jtag_debug_module_in_a_read_cycle & cpu_jtag_debug_module_begins_xfer;
//cpu_jtag_debug_module_in_a_read_cycle assignment, which is an e_assign
assign cpu_jtag_debug_module_in_a_read_cycle = (cpu_data_master_granted_cpu_jtag_debug_module & cpu_data_master_read) | (cpu_instruction_master_granted_cpu_jtag_debug_module & cpu_instruction_master_read);
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = cpu_jtag_debug_module_in_a_read_cycle;
//cpu_jtag_debug_module_waits_for_write in a cycle, which is an e_mux
assign cpu_jtag_debug_module_waits_for_write = cpu_jtag_debug_module_in_a_write_cycle & 0;
//cpu_jtag_debug_module_in_a_write_cycle assignment, which is an e_assign
assign cpu_jtag_debug_module_in_a_write_cycle = cpu_data_master_granted_cpu_jtag_debug_module & cpu_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = cpu_jtag_debug_module_in_a_write_cycle;
assign wait_for_cpu_jtag_debug_module_counter = 0;
//cpu_jtag_debug_module_byteenable byte enable port mux, which is an e_mux
assign cpu_jtag_debug_module_byteenable = (cpu_data_master_granted_cpu_jtag_debug_module)? cpu_data_master_byteenable :
-1;
//debugaccess mux, which is an e_mux
assign cpu_jtag_debug_module_debugaccess = (cpu_data_master_granted_cpu_jtag_debug_module)? cpu_data_master_debugaccess :
0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//cpu/jtag_debug_module enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_data_master_granted_cpu_jtag_debug_module + cpu_instruction_master_granted_cpu_jtag_debug_module > 1)
begin
$write("%0d ns: > 1 of grant signals are active simultaneously", $time);
$stop;
end
end
//saved_grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_data_master_saved_grant_cpu_jtag_debug_module + cpu_instruction_master_saved_grant_cpu_jtag_debug_module > 1)
begin
$write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_data_master_arbitrator (
// inputs:
cfi_flash_s1_wait_counter_eq_0,
cfi_flash_s1_wait_counter_eq_1,
clk,
cpu_data_master_address,
cpu_data_master_byteenable_cfi_flash_s1,
cpu_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0,
cpu_data_master_granted_cfi_flash_s1,
cpu_data_master_granted_cpu_jtag_debug_module,
cpu_data_master_granted_epcs_flash_controller_epcs_control_port,
cpu_data_master_granted_gpio_s1,
cpu_data_master_granted_hardmodle_s1,
cpu_data_master_granted_jtag_uart_avalon_jtag_slave,
cpu_data_master_granted_kernel_clock_0_in,
cpu_data_master_granted_key_s1,
cpu_data_master_granted_lcd_0_control_slave,
cpu_data_master_granted_onchip_memory_s1,
cpu_data_master_granted_pll_pll_slave,
cpu_data_master_granted_sram_16bit_512k_0_avalon_slave_0,
cpu_data_master_granted_timer_s1,
cpu_data_master_qualified_request_cfi_flash_s1,
cpu_data_master_qualified_request_cpu_jtag_debug_module,
cpu_data_master_qualified_request_epcs_flash_controller_epcs_control_port,
cpu_data_master_qualified_request_gpio_s1,
cpu_data_master_qualified_request_hardmodle_s1,
cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave,
cpu_data_master_qualified_request_kernel_clock_0_in,
cpu_data_master_qualified_request_key_s1,
cpu_data_master_qualified_request_lcd_0_control_slave,
cpu_data_master_qualified_request_onchip_memory_s1,
cpu_data_master_qualified_request_pll_pll_slave,
cpu_data_master_qualified_request_sram_16bit_512k_0_avalon_slave_0,
cpu_data_master_qualified_request_timer_s1,
cpu_data_master_read,
cpu_data_master_read_data_valid_cfi_flash_s1,
cpu_data_master_read_data_valid_cpu_jtag_debug_module,
cpu_data_master_read_data_valid_epcs_flash_controller_epcs_control_port,
cpu_data_master_read_data_valid_gpio_s1,
cpu_data_master_read_data_valid_hardmodle_s1,
cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave,
cpu_data_master_read_data_valid_kernel_clock_0_in,
cpu_data_master_read_data_valid_key_s1,
cpu_data_master_read_data_valid_lcd_0_control_slave,
cpu_data_master_read_data_valid_onchip_memory_s1,
cpu_data_master_read_data_valid_pll_pll_slave,
cpu_data_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0,
cpu_data_master_read_data_valid_timer_s1,
cpu_data_master_requests_cfi_flash_s1,
cpu_data_master_requests_cpu_jtag_debug_module,
cpu_data_master_requests_epcs_flash_controller_epcs_control_port,
cpu_data_master_requests_gpio_s1,
cpu_data_master_requests_hardmodle_s1,
cpu_data_master_requests_jtag_uart_avalon_jtag_slave,
cpu_data_master_requests_kernel_clock_0_in,
cpu_data_master_requests_key_s1,
cpu_data_master_requests_lcd_0_control_slave,
cpu_data_master_requests_onchip_memory_s1,
cpu_data_master_requests_pll_pll_slave,
cpu_data_master_requests_sram_16bit_512k_0_avalon_slave_0,
cpu_data_master_requests_timer_s1,
cpu_data_master_write,
cpu_data_master_writedata,
cpu_jtag_debug_module_readdata_from_sa,
d1_cpu_jtag_debug_module_end_xfer,
d1_epcs_flash_controller_epcs_control_port_end_xfer,
d1_gpio_s1_end_xfer,
d1_hardmodle_s1_end_xfer,
d1_jtag_uart_avalon_jtag_slave_end_xfer,
d1_kernel_clock_0_in_end_xfer,
d1_key_s1_end_xfer,
d1_lcd_0_control_slave_end_xfer,
d1_onchip_memory_s1_end_xfer,
d1_pll_pll_slave_end_xfer,
d1_sram_16bit_512k_0_avalon_slave_0_end_xfer,
d1_timer_s1_end_xfer,
d1_tri_state_bridge_avalon_slave_end_xfer,
epcs_flash_controller_epcs_control_port_irq_from_sa,
epcs_flash_controller_epcs_control_port_readdata_from_sa,
gpio_s1_irq_from_sa,
gpio_s1_readdata_from_sa,
hardmodle_s1_readdata_from_sa,
incoming_tri_state_bridge_data_with_Xs_converted_to_0,
jtag_uart_avalon_jtag_slave_irq_from_sa,
jtag_uart_avalon_jtag_slave_readdata_from_sa,
jtag_uart_avalon_jtag_slave_waitrequest_from_sa,
kernel_clock_0_in_readdata_from_sa,
kernel_clock_0_in_waitrequest_from_sa,
key_s1_irq_from_sa,
key_s1_readdata_from_sa,
lcd_0_control_slave_readdata_from_sa,
lcd_0_control_slave_wait_counter_eq_0,
lcd_0_control_slave_wait_counter_eq_1,
onchip_memory_s1_readdata_from_sa,
pll_pll_slave_readdata_from_sa,
registered_cpu_data_master_read_data_valid_cfi_flash_s1,
registered_cpu_data_master_read_data_valid_onchip_memory_s1,
reset_n,
sram_16bit_512k_0_avalon_slave_0_readdata_from_sa,
sram_16bit_512k_0_avalon_slave_0_wait_counter_eq_0,
timer_s1_irq_from_sa,
timer_s1_readdata_from_sa,
// outputs:
cpu_data_master_address_to_slave,
cpu_data_master_dbs_address,
cpu_data_master_dbs_write_16,
cpu_data_master_dbs_write_8,
cpu_data_master_irq,
cpu_data_master_no_byte_enables_and_last_term,
cpu_data_master_readdata,
cpu_data_master_waitrequest
)
;
output [ 23: 0] cpu_data_master_address_to_slave;
output [ 1: 0] cpu_data_master_dbs_address;
output [ 15: 0] cpu_data_master_dbs_write_16;
output [ 7: 0] cpu_data_master_dbs_write_8;
output [ 31: 0] cpu_data_master_irq;
output cpu_data_master_no_byte_enables_and_last_term;
output [ 31: 0] cpu_data_master_readdata;
output cpu_data_master_waitrequest;
input cfi_flash_s1_wait_counter_eq_0;
input cfi_flash_s1_wait_counter_eq_1;
input clk;
input [ 23: 0] cpu_data_master_address;
input cpu_data_master_byteenable_cfi_flash_s1;
input [ 1: 0] cpu_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0;
input cpu_data_master_granted_cfi_flash_s1;
input cpu_data_master_granted_cpu_jtag_debug_module;
input cpu_data_master_granted_epcs_flash_controller_epcs_control_port;
input cpu_data_master_granted_gpio_s1;
input cpu_data_master_granted_hardmodle_s1;
input cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
input cpu_data_master_granted_kernel_clock_0_in;
input cpu_data_master_granted_key_s1;
input cpu_data_master_granted_lcd_0_control_slave;
input cpu_data_master_granted_onchip_memory_s1;
input cpu_data_master_granted_pll_pll_slave;
input cpu_data_master_granted_sram_16bit_512k_0_avalon_slave_0;
input cpu_data_master_granted_timer_s1;
input cpu_data_master_qualified_request_cfi_flash_s1;
input cpu_data_master_qualified_request_cpu_jtag_debug_module;
input cpu_data_master_qualified_request_epcs_flash_controller_epcs_control_port;
input cpu_data_master_qualified_request_gpio_s1;
input cpu_data_master_qualified_request_hardmodle_s1;
input cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
input cpu_data_master_qualified_request_kernel_clock_0_in;
input cpu_data_master_qualified_request_key_s1;
input cpu_data_master_qualified_request_lcd_0_control_slave;
input cpu_data_master_qualified_request_onchip_memory_s1;
input cpu_data_master_qualified_request_pll_pll_slave;
input cpu_data_master_qualified_request_sram_16bit_512k_0_avalon_slave_0;
input cpu_data_master_qualified_request_timer_s1;
input cpu_data_master_read;
input cpu_data_master_read_data_valid_cfi_flash_s1;
input cpu_data_master_read_data_valid_cpu_jtag_debug_module;
input cpu_data_master_read_data_valid_epcs_flash_controller_epcs_control_port;
input cpu_data_master_read_data_valid_gpio_s1;
input cpu_data_master_read_data_valid_hardmodle_s1;
input cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
input cpu_data_master_read_data_valid_kernel_clock_0_in;
input cpu_data_master_read_data_valid_key_s1;
input cpu_data_master_read_data_valid_lcd_0_control_slave;
input cpu_data_master_read_data_valid_onchip_memory_s1;
input cpu_data_master_read_data_valid_pll_pll_slave;
input cpu_data_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0;
input cpu_data_master_read_data_valid_timer_s1;
input cpu_data_master_requests_cfi_flash_s1;
input cpu_data_master_requests_cpu_jtag_debug_module;
input cpu_data_master_requests_epcs_flash_controller_epcs_control_port;
input cpu_data_master_requests_gpio_s1;
input cpu_data_master_requests_hardmodle_s1;
input cpu_data_master_requests_jtag_uart_avalon_jtag_slave;
input cpu_data_master_requests_kernel_clock_0_in;
input cpu_data_master_requests_key_s1;
input cpu_data_master_requests_lcd_0_control_slave;
input cpu_data_master_requests_onchip_memory_s1;
input cpu_data_master_requests_pll_pll_slave;
input cpu_data_master_requests_sram_16bit_512k_0_avalon_slave_0;
input cpu_data_master_requests_timer_s1;
input cpu_data_master_write;
input [ 31: 0] cpu_data_master_writedata;
input [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
input d1_cpu_jtag_debug_module_end_xfer;
input d1_epcs_flash_controller_epcs_control_port_end_xfer;
input d1_gpio_s1_end_xfer;
input d1_hardmodle_s1_end_xfer;
input d1_jtag_uart_avalon_jtag_slave_end_xfer;
input d1_kernel_clock_0_in_end_xfer;
input d1_key_s1_end_xfer;
input d1_lcd_0_control_slave_end_xfer;
input d1_onchip_memory_s1_end_xfer;
input d1_pll_pll_slave_end_xfer;
input d1_sram_16bit_512k_0_avalon_slave_0_end_xfer;
input d1_timer_s1_end_xfer;
input d1_tri_state_bridge_avalon_slave_end_xfer;
input epcs_flash_controller_epcs_control_port_irq_from_sa;
input [ 31: 0] epcs_flash_controller_epcs_control_port_readdata_from_sa;
input gpio_s1_irq_from_sa;
input [ 31: 0] gpio_s1_readdata_from_sa;
input [ 31: 0] hardmodle_s1_readdata_from_sa;
input [ 7: 0] incoming_tri_state_bridge_data_with_Xs_converted_to_0;
input jtag_uart_avalon_jtag_slave_irq_from_sa;
input [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
input jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
input [ 15: 0] kernel_clock_0_in_readdata_from_sa;
input kernel_clock_0_in_waitrequest_from_sa;
input key_s1_irq_from_sa;
input [ 31: 0] key_s1_readdata_from_sa;
input [ 7: 0] lcd_0_control_slave_readdata_from_sa;
input lcd_0_control_slave_wait_counter_eq_0;
input lcd_0_control_slave_wait_counter_eq_1;
input [ 31: 0] onchip_memory_s1_readdata_from_sa;
input [ 31: 0] pll_pll_slave_readdata_from_sa;
input registered_cpu_data_master_read_data_valid_cfi_flash_s1;
input registered_cpu_data_master_read_data_valid_onchip_memory_s1;
input reset_n;
input [ 15: 0] sram_16bit_512k_0_avalon_slave_0_readdata_from_sa;
input sram_16bit_512k_0_avalon_slave_0_wait_counter_eq_0;
input timer_s1_irq_from_sa;
input [ 15: 0] timer_s1_readdata_from_sa;
wire [ 23: 0] cpu_data_master_address_to_slave;
reg [ 1: 0] cpu_data_master_dbs_address;
wire [ 1: 0] cpu_data_master_dbs_increment;
wire [ 15: 0] cpu_data_master_dbs_write_16;
wire [ 7: 0] cpu_data_master_dbs_write_8;
wire [ 31: 0] cpu_data_master_irq;
reg cpu_data_master_no_byte_enables_and_last_term;
wire [ 31: 0] cpu_data_master_readdata;
wire cpu_data_master_run;
reg cpu_data_master_waitrequest;
reg [ 15: 0] dbs_16_reg_segment_0;
reg [ 7: 0] dbs_8_reg_segment_0;
reg [ 7: 0] dbs_8_reg_segment_1;
reg [ 7: 0] dbs_8_reg_segment_2;
wire dbs_count_enable;
wire dbs_counter_overflow;
wire last_dbs_term_and_run;
wire [ 1: 0] next_dbs_address;
wire [ 15: 0] p1_dbs_16_reg_segment_0;
wire [ 7: 0] p1_dbs_8_reg_segment_0;
wire [ 7: 0] p1_dbs_8_reg_segment_1;
wire [ 7: 0] p1_dbs_8_reg_segment_2;
wire [ 31: 0] p1_registered_cpu_data_master_readdata;
wire pre_dbs_count_enable;
wire r_0;
wire r_1;
wire r_2;
reg [ 31: 0] registered_cpu_data_master_readdata;
//r_0 master_run cascaded wait assignment, which is an e_assign
assign r_0 = 1 & (cpu_data_master_qualified_request_cpu_jtag_debug_module | ~cpu_data_master_requests_cpu_jtag_debug_module) & (cpu_data_master_granted_cpu_jtag_debug_module | ~cpu_data_master_qualified_request_cpu_jtag_debug_module) & ((~cpu_data_master_qualified_request_cpu_jtag_debug_module | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_cpu_jtag_debug_module | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_epcs_flash_controller_epcs_control_port | ~cpu_data_master_requests_epcs_flash_controller_epcs_control_port) & (cpu_data_master_granted_epcs_flash_controller_epcs_control_port | ~cpu_data_master_qualified_request_epcs_flash_controller_epcs_control_port) & ((~cpu_data_master_qualified_request_epcs_flash_controller_epcs_control_port | ~(cpu_data_master_read | cpu_data_master_write) | (1 & 1 & (cpu_data_master_read | cpu_data_master_write)))) & ((~cpu_data_master_qualified_request_epcs_flash_controller_epcs_control_port | ~(cpu_data_master_read | cpu_data_master_write) | (1 & 1 & (cpu_data_master_read | cpu_data_master_write)))) & 1 & (cpu_data_master_qualified_request_gpio_s1 | ~cpu_data_master_requests_gpio_s1) & ((~cpu_data_master_qualified_request_gpio_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_gpio_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & ((~cpu_data_master_qualified_request_hardmodle_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_hardmodle_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~cpu_data_master_requests_jtag_uart_avalon_jtag_slave) & ((~cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~(cpu_data_master_read | cpu_data_master_write) | (1 & ~jtag_uart_avalon_jtag_slave_waitrequest_from_sa & (cpu_data_master_read | cpu_data_master_write))));
//cascaded wait assignment, which is an e_assign
assign cpu_data_master_run = r_0 & r_1 & r_2;
//r_1 master_run cascaded wait assignment, which is an e_assign
assign r_1 = ((~cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~(cpu_data_master_read | cpu_data_master_write) | (1 & ~jtag_uart_avalon_jtag_slave_waitrequest_from_sa & (cpu_data_master_read | cpu_data_master_write)))) & 1 & (cpu_data_master_qualified_request_kernel_clock_0_in | ~cpu_data_master_requests_kernel_clock_0_in) & ((~cpu_data_master_qualified_request_kernel_clock_0_in | ~(cpu_data_master_read | cpu_data_master_write) | (1 & ~kernel_clock_0_in_waitrequest_from_sa & (cpu_data_master_read | cpu_data_master_write)))) & ((~cpu_data_master_qualified_request_kernel_clock_0_in | ~(cpu_data_master_read | cpu_data_master_write) | (1 & ~kernel_clock_0_in_waitrequest_from_sa & (cpu_data_master_read | cpu_data_master_write)))) & 1 & (cpu_data_master_qualified_request_key_s1 | ~cpu_data_master_requests_key_s1) & ((~cpu_data_master_qualified_request_key_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_key_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & ((~cpu_data_master_qualified_request_lcd_0_control_slave | ~cpu_data_master_read | (1 & lcd_0_control_slave_wait_counter_eq_1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_lcd_0_control_slave | ~cpu_data_master_write | (1 & lcd_0_control_slave_wait_counter_eq_1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_onchip_memory_s1 | registered_cpu_data_master_read_data_valid_onchip_memory_s1 | ~cpu_data_master_requests_onchip_memory_s1) & (cpu_data_master_granted_onchip_memory_s1 | ~cpu_data_master_qualified_request_onchip_memory_s1) & ((~cpu_data_master_qualified_request_onchip_memory_s1 | ~cpu_data_master_read | (registered_cpu_data_master_read_data_valid_onchip_memory_s1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_onchip_memory_s1 | ~(cpu_data_master_read | cpu_data_master_write) | (1 & (cpu_data_master_read | cpu_data_master_write)))) & 1 & (cpu_data_master_qualified_request_pll_pll_slave | ~cpu_data_master_requests_pll_pll_slave) & ((~cpu_data_master_qualified_request_pll_pll_slave | ~(cpu_data_master_read | cpu_data_master_write) | (1 & (cpu_data_master_read | cpu_data_master_write))));
//r_2 master_run cascaded wait assignment, which is an e_assign
assign r_2 = ((~cpu_data_master_qualified_request_pll_pll_slave | ~(cpu_data_master_read | cpu_data_master_write) | (1 & (cpu_data_master_read | cpu_data_master_write)))) & 1 & (cpu_data_master_qualified_request_sram_16bit_512k_0_avalon_slave_0 | (cpu_data_master_write & !cpu_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0 & cpu_data_master_dbs_address[1]) | ~cpu_data_master_requests_sram_16bit_512k_0_avalon_slave_0) & (cpu_data_master_granted_sram_16bit_512k_0_avalon_slave_0 | ~cpu_data_master_qualified_request_sram_16bit_512k_0_avalon_slave_0) & ((~cpu_data_master_qualified_request_sram_16bit_512k_0_avalon_slave_0 | ~cpu_data_master_read | (1 & 1 & (cpu_data_master_dbs_address[1]) & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_sram_16bit_512k_0_avalon_slave_0 | ~cpu_data_master_write | (1 & ~d1_sram_16bit_512k_0_avalon_slave_0_end_xfer & (cpu_data_master_dbs_address[1]) & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_timer_s1 | ~cpu_data_master_requests_timer_s1) & ((~cpu_data_master_qualified_request_timer_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_timer_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & ((cpu_data_master_qualified_request_cfi_flash_s1 | (registered_cpu_data_master_read_data_valid_cfi_flash_s1 & cpu_data_master_dbs_address[1] & cpu_data_master_dbs_address[0]) | ((cpu_data_master_write & !cpu_data_master_byteenable_cfi_flash_s1 & cpu_data_master_dbs_address[1] & cpu_data_master_dbs_address[0])) | ~cpu_data_master_requests_cfi_flash_s1)) & (cpu_data_master_granted_cfi_flash_s1 | ~cpu_data_master_qualified_request_cfi_flash_s1) & ((~cpu_data_master_qualified_request_cfi_flash_s1 | ~cpu_data_master_read | (registered_cpu_data_master_read_data_valid_cfi_flash_s1 & (cpu_data_master_dbs_address[1] & cpu_data_master_dbs_address[0]) & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_cfi_flash_s1 | ~cpu_data_master_write | (1 & cfi_flash_s1_wait_counter_eq_1 & (cpu_data_master_dbs_address[1] & cpu_data_master_dbs_address[0]) & cpu_data_master_write)));
//optimize select-logic by passing only those address bits which matter.
assign cpu_data_master_address_to_slave = cpu_data_master_address[23 : 0];
//cpu/data_master readdata mux, which is an e_mux
assign cpu_data_master_readdata = ({32 {~cpu_data_master_requests_cpu_jtag_debug_module}} | cpu_jtag_debug_module_readdata_from_sa) &
({32 {~cpu_data_master_requests_epcs_flash_controller_epcs_control_port}} | epcs_flash_controller_epcs_control_port_readdata_from_sa) &
({32 {~cpu_data_master_requests_gpio_s1}} | gpio_s1_readdata_from_sa) &
({32 {~cpu_data_master_requests_hardmodle_s1}} | hardmodle_s1_readdata_from_sa) &
({32 {~cpu_data_master_requests_jtag_uart_avalon_jtag_slave}} | registered_cpu_data_master_readdata) &
({32 {~cpu_data_master_requests_kernel_clock_0_in}} | registered_cpu_data_master_readdata) &
({32 {~cpu_data_master_requests_key_s1}} | key_s1_readdata_from_sa) &
({32 {~cpu_data_master_requests_lcd_0_control_slave}} | lcd_0_control_slave_readdata_from_sa) &
({32 {~cpu_data_master_requests_onchip_memory_s1}} | onchip_memory_s1_readdata_from_sa) &
({32 {~cpu_data_master_requests_pll_pll_slave}} | registered_cpu_data_master_readdata) &
({32 {~cpu_data_master_requests_sram_16bit_512k_0_avalon_slave_0}} | {sram_16bit_512k_0_avalon_slave_0_readdata_from_sa[15 : 0],
dbs_16_reg_segment_0}) &
({32 {~cpu_data_master_requests_timer_s1}} | timer_s1_readdata_from_sa) &
({32 {~cpu_data_master_requests_cfi_flash_s1}} | {incoming_tri_state_bridge_data_with_Xs_converted_to_0[7 : 0],
dbs_8_reg_segment_2,
dbs_8_reg_segment_1,
dbs_8_reg_segment_0});
//actual waitrequest port, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_data_master_waitrequest <= ~0;
else
cpu_data_master_waitrequest <= ~((~(cpu_data_master_read | cpu_data_master_write))? 0: (cpu_data_master_run & cpu_data_master_waitrequest));
end
//irq assign, which is an e_assign
assign cpu_data_master_irq = {1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
gpio_s1_irq_from_sa,
key_s1_irq_from_sa,
timer_s1_irq_from_sa,
epcs_flash_controller_epcs_control_port_irq_from_sa,
jtag_uart_avalon_jtag_slave_irq_from_sa};
//unpredictable registered wait state incoming data, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
registered_cpu_data_master_readdata <= 0;
else
registered_cpu_data_master_readdata <= p1_registered_cpu_data_master_readdata;
end
//registered readdata mux, which is an e_mux
assign p1_registered_cpu_data_master_readdata = ({32 {~cpu_data_master_requests_jtag_uart_avalon_jtag_slave}} | jtag_uart_avalon_jtag_slave_readdata_from_sa) &
({32 {~cpu_data_master_requests_kernel_clock_0_in}} | kernel_clock_0_in_readdata_from_sa) &
({32 {~cpu_data_master_requests_pll_pll_slave}} | pll_pll_slave_readdata_from_sa);
//no_byte_enables_and_last_term, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_data_master_no_byte_enables_and_last_term <= 0;
else
cpu_data_master_no_byte_enables_and_last_term <= last_dbs_term_and_run;
end
//compute the last dbs term, which is an e_mux
assign last_dbs_term_and_run = (cpu_data_master_requests_sram_16bit_512k_0_avalon_slave_0)? (((cpu_data_master_dbs_address == 2'b10) & cpu_data_master_write & !cpu_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0)) :
(((cpu_data_master_dbs_address == 2'b11) & cpu_data_master_write & !cpu_data_master_byteenable_cfi_flash_s1));
//pre dbs count enable, which is an e_mux
assign pre_dbs_count_enable = (((~cpu_data_master_no_byte_enables_and_last_term) & cpu_data_master_requests_sram_16bit_512k_0_avalon_slave_0 & cpu_data_master_write & !cpu_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0)) |
(cpu_data_master_granted_sram_16bit_512k_0_avalon_slave_0 & cpu_data_master_read & 1 & 1 & ~d1_sram_16bit_512k_0_avalon_slave_0_end_xfer) |
((cpu_data_master_granted_sram_16bit_512k_0_avalon_slave_0 & cpu_data_master_write & 1 & 1 & ({sram_16bit_512k_0_avalon_slave_0_wait_counter_eq_0 & ~d1_sram_16bit_512k_0_avalon_slave_0_end_xfer}))) |
(((~cpu_data_master_no_byte_enables_and_last_term) & cpu_data_master_requests_cfi_flash_s1 & cpu_data_master_write & !cpu_data_master_byteenable_cfi_flash_s1)) |
cpu_data_master_read_data_valid_cfi_flash_s1 |
((cpu_data_master_granted_cfi_flash_s1 & cpu_data_master_write & 1 & 1 & ({cfi_flash_s1_wait_counter_eq_0 & ~d1_tri_state_bridge_avalon_slave_end_xfer})));
//input to dbs-16 stored 0, which is an e_mux
assign p1_dbs_16_reg_segment_0 = sram_16bit_512k_0_avalon_slave_0_readdata_from_sa;
//dbs register for dbs-16 segment 0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbs_16_reg_segment_0 <= 0;
else if (dbs_count_enable & ((cpu_data_master_dbs_address[1]) == 0))
dbs_16_reg_segment_0 <= p1_dbs_16_reg_segment_0;
end
//mux write dbs 1, which is an e_mux
assign cpu_data_master_dbs_write_16 = (cpu_data_master_dbs_address[1])? cpu_data_master_writedata[31 : 16] :
cpu_data_master_writedata[15 : 0];
//dbs count increment, which is an e_mux
assign cpu_data_master_dbs_increment = (cpu_data_master_requests_sram_16bit_512k_0_avalon_slave_0)? 2 :
(cpu_data_master_requests_cfi_flash_s1)? 1 :
0;
//dbs counter overflow, which is an e_assign
assign dbs_counter_overflow = cpu_data_master_dbs_address[1] & !(next_dbs_address[1]);
//next master address, which is an e_assign
assign next_dbs_address = cpu_data_master_dbs_address + cpu_data_master_dbs_increment;
//dbs count enable, which is an e_mux
assign dbs_count_enable = pre_dbs_count_enable;
//dbs counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_data_master_dbs_address <= 0;
else if (dbs_count_enable)
cpu_data_master_dbs_address <= next_dbs_address;
end
//input to dbs-8 stored 0, which is an e_mux
assign p1_dbs_8_reg_segment_0 = incoming_tri_state_bridge_data_with_Xs_converted_to_0;
//dbs register for dbs-8 segment 0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbs_8_reg_segment_0 <= 0;
else if (dbs_count_enable & ((cpu_data_master_dbs_address[1 : 0]) == 0))
dbs_8_reg_segment_0 <= p1_dbs_8_reg_segment_0;
end
//input to dbs-8 stored 1, which is an e_mux
assign p1_dbs_8_reg_segment_1 = incoming_tri_state_bridge_data_with_Xs_converted_to_0;
//dbs register for dbs-8 segment 1, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbs_8_reg_segment_1 <= 0;
else if (dbs_count_enable & ((cpu_data_master_dbs_address[1 : 0]) == 1))
dbs_8_reg_segment_1 <= p1_dbs_8_reg_segment_1;
end
//input to dbs-8 stored 2, which is an e_mux
assign p1_dbs_8_reg_segment_2 = incoming_tri_state_bridge_data_with_Xs_converted_to_0;
//dbs register for dbs-8 segment 2, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbs_8_reg_segment_2 <= 0;
else if (dbs_count_enable & ((cpu_data_master_dbs_address[1 : 0]) == 2))
dbs_8_reg_segment_2 <= p1_dbs_8_reg_segment_2;
end
//mux write dbs 2, which is an e_mux
assign cpu_data_master_dbs_write_8 = ((cpu_data_master_dbs_address[1 : 0] == 0))? cpu_data_master_writedata[7 : 0] :
((cpu_data_master_dbs_address[1 : 0] == 1))? cpu_data_master_writedata[15 : 8] :
((cpu_data_master_dbs_address[1 : 0] == 2))? cpu_data_master_writedata[23 : 16] :
cpu_data_master_writedata[31 : 24];
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_instruction_master_arbitrator (
// inputs:
cfi_flash_s1_wait_counter_eq_0,
cfi_flash_s1_wait_counter_eq_1,
clk,
cpu_instruction_master_address,
cpu_instruction_master_granted_cfi_flash_s1,
cpu_instruction_master_granted_cpu_jtag_debug_module,
cpu_instruction_master_granted_epcs_flash_controller_epcs_control_port,
cpu_instruction_master_granted_onchip_memory_s1,
cpu_instruction_master_granted_sram_16bit_512k_0_avalon_slave_0,
cpu_instruction_master_qualified_request_cfi_flash_s1,
cpu_instruction_master_qualified_request_cpu_jtag_debug_module,
cpu_instruction_master_qualified_request_epcs_flash_controller_epcs_control_port,
cpu_instruction_master_qualified_request_onchip_memory_s1,
cpu_instruction_master_qualified_request_sram_16bit_512k_0_avalon_slave_0,
cpu_instruction_master_read,
cpu_instruction_master_read_data_valid_cfi_flash_s1,
cpu_instruction_master_read_data_valid_cpu_jtag_debug_module,
cpu_instruction_master_read_data_valid_epcs_flash_controller_epcs_control_port,
cpu_instruction_master_read_data_valid_onchip_memory_s1,
cpu_instruction_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0,
cpu_instruction_master_requests_cfi_flash_s1,
cpu_instruction_master_requests_cpu_jtag_debug_module,
cpu_instruction_master_requests_epcs_flash_controller_epcs_control_port,
cpu_instruction_master_requests_onchip_memory_s1,
cpu_instruction_master_requests_sram_16bit_512k_0_avalon_slave_0,
cpu_jtag_debug_module_readdata_from_sa,
d1_cpu_jtag_debug_module_end_xfer,
d1_epcs_flash_controller_epcs_control_port_end_xfer,
d1_onchip_memory_s1_end_xfer,
d1_sram_16bit_512k_0_avalon_slave_0_end_xfer,
d1_tri_state_bridge_avalon_slave_end_xfer,
epcs_flash_controller_epcs_control_port_readdata_from_sa,
incoming_tri_state_bridge_data,
onchip_memory_s1_readdata_from_sa,
reset_n,
sram_16bit_512k_0_avalon_slave_0_readdata_from_sa,
sram_16bit_512k_0_avalon_slave_0_wait_counter_eq_0,
// outputs:
cpu_instruction_master_address_to_slave,
cpu_instruction_master_dbs_address,
cpu_instruction_master_latency_counter,
cpu_instruction_master_readdata,
cpu_instruction_master_readdatavalid,
cpu_instruction_master_waitrequest
)
;
output [ 23: 0] cpu_instruction_master_address_to_slave;
output [ 1: 0] cpu_instruction_master_dbs_address;
output [ 1: 0] cpu_instruction_master_latency_counter;
output [ 31: 0] cpu_instruction_master_readdata;
output cpu_instruction_master_readdatavalid;
output cpu_instruction_master_waitrequest;
input cfi_flash_s1_wait_counter_eq_0;
input cfi_flash_s1_wait_counter_eq_1;
input clk;
input [ 23: 0] cpu_instruction_master_address;
input cpu_instruction_master_granted_cfi_flash_s1;
input cpu_instruction_master_granted_cpu_jtag_debug_module;
input cpu_instruction_master_granted_epcs_flash_controller_epcs_control_port;
input cpu_instruction_master_granted_onchip_memory_s1;
input cpu_instruction_master_granted_sram_16bit_512k_0_avalon_slave_0;
input cpu_instruction_master_qualified_request_cfi_flash_s1;
input cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
input cpu_instruction_master_qualified_request_epcs_flash_controller_epcs_control_port;
input cpu_instruction_master_qualified_request_onchip_memory_s1;
input cpu_instruction_master_qualified_request_sram_16bit_512k_0_avalon_slave_0;
input cpu_instruction_master_read;
input cpu_instruction_master_read_data_valid_cfi_flash_s1;
input cpu_instruction_master_read_data_valid_cpu_jtag_debug_module;
input cpu_instruction_master_read_data_valid_epcs_flash_controller_epcs_control_port;
input cpu_instruction_master_read_data_valid_onchip_memory_s1;
input cpu_instruction_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0;
input cpu_instruction_master_requests_cfi_flash_s1;
input cpu_instruction_master_requests_cpu_jtag_debug_module;
input cpu_instruction_master_requests_epcs_flash_controller_epcs_control_port;
input cpu_instruction_master_requests_onchip_memory_s1;
input cpu_instruction_master_requests_sram_16bit_512k_0_avalon_slave_0;
input [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
input d1_cpu_jtag_debug_module_end_xfer;
input d1_epcs_flash_controller_epcs_control_port_end_xfer;
input d1_onchip_memory_s1_end_xfer;
input d1_sram_16bit_512k_0_avalon_slave_0_end_xfer;
input d1_tri_state_bridge_avalon_slave_end_xfer;
input [ 31: 0] epcs_flash_controller_epcs_control_port_readdata_from_sa;
input [ 7: 0] incoming_tri_state_bridge_data;
input [ 31: 0] onchip_memory_s1_readdata_from_sa;
input reset_n;
input [ 15: 0] sram_16bit_512k_0_avalon_slave_0_readdata_from_sa;
input sram_16bit_512k_0_avalon_slave_0_wait_counter_eq_0;
reg active_and_waiting_last_time;
reg [ 23: 0] cpu_instruction_master_address_last_time;
wire [ 23: 0] cpu_instruction_master_address_to_slave;
reg [ 1: 0] cpu_instruction_master_dbs_address;
wire [ 1: 0] cpu_instruction_master_dbs_increment;
reg [ 1: 0] cpu_instruction_master_dbs_rdv_counter;
wire [ 1: 0] cpu_instruction_master_dbs_rdv_counter_inc;
wire cpu_instruction_master_is_granted_some_slave;
reg [ 1: 0] cpu_instruction_master_latency_counter;
wire [ 1: 0] cpu_instruction_master_next_dbs_rdv_counter;
reg cpu_instruction_master_read_but_no_slave_selected;
reg cpu_instruction_master_read_last_time;
wire [ 31: 0] cpu_instruction_master_readdata;
wire cpu_instruction_master_readdatavalid;
wire cpu_instruction_master_run;
wire cpu_instruction_master_waitrequest;
reg [ 15: 0] dbs_16_reg_segment_0;
wire dbs_count_enable;
wire dbs_counter_overflow;
reg [ 7: 0] dbs_latent_8_reg_segment_0;
reg [ 7: 0] dbs_latent_8_reg_segment_1;
reg [ 7: 0] dbs_latent_8_reg_segment_2;
wire dbs_rdv_count_enable;
wire dbs_rdv_counter_overflow;
wire [ 1: 0] latency_load_value;
wire [ 1: 0] next_dbs_address;
wire [ 1: 0] p1_cpu_instruction_master_latency_counter;
wire [ 15: 0] p1_dbs_16_reg_segment_0;
wire [ 7: 0] p1_dbs_latent_8_reg_segment_0;
wire [ 7: 0] p1_dbs_latent_8_reg_segment_1;
wire [ 7: 0] p1_dbs_latent_8_reg_segment_2;
wire pre_dbs_count_enable;
wire pre_flush_cpu_instruction_master_readdatavalid;
wire r_0;
wire r_1;
wire r_2;
//r_0 master_run cascaded wait assignment, which is an e_assign
assign r_0 = 1 & (cpu_instruction_master_qualified_request_cpu_jtag_debug_module | ~cpu_instruction_master_requests_cpu_jtag_debug_module) & (cpu_instruction_master_granted_cpu_jtag_debug_module | ~cpu_instruction_master_qualified_request_cpu_jtag_debug_module) & ((~cpu_instruction_master_qualified_request_cpu_jtag_debug_module | ~cpu_instruction_master_read | (1 & ~d1_cpu_jtag_debug_module_end_xfer & cpu_instruction_master_read))) & 1 & (cpu_instruction_master_qualified_request_epcs_flash_controller_epcs_control_port | ~cpu_instruction_master_requests_epcs_flash_controller_epcs_control_port) & (cpu_instruction_master_granted_epcs_flash_controller_epcs_control_port | ~cpu_instruction_master_qualified_request_epcs_flash_controller_epcs_control_port) & ((~cpu_instruction_master_qualified_request_epcs_flash_controller_epcs_control_port | ~(cpu_instruction_master_read) | (1 & ~d1_epcs_flash_controller_epcs_control_port_end_xfer & (cpu_instruction_master_read))));
//cascaded wait assignment, which is an e_assign
assign cpu_instruction_master_run = r_0 & r_1 & r_2;
//r_1 master_run cascaded wait assignment, which is an e_assign
assign r_1 = 1 & (cpu_instruction_master_qualified_request_onchip_memory_s1 | ~cpu_instruction_master_requests_onchip_memory_s1) & (cpu_instruction_master_granted_onchip_memory_s1 | ~cpu_instruction_master_qualified_request_onchip_memory_s1) & ((~cpu_instruction_master_qualified_request_onchip_memory_s1 | ~cpu_instruction_master_read | (1 & cpu_instruction_master_read)));
//r_2 master_run cascaded wait assignment, which is an e_assign
assign r_2 = 1 & (cpu_instruction_master_qualified_request_sram_16bit_512k_0_avalon_slave_0 | ~cpu_instruction_master_requests_sram_16bit_512k_0_avalon_slave_0) & (cpu_instruction_master_granted_sram_16bit_512k_0_avalon_slave_0 | ~cpu_instruction_master_qualified_request_sram_16bit_512k_0_avalon_slave_0) & ((~cpu_instruction_master_qualified_request_sram_16bit_512k_0_avalon_slave_0 | ~cpu_instruction_master_read | (1 & ~d1_sram_16bit_512k_0_avalon_slave_0_end_xfer & (cpu_instruction_master_dbs_address[1]) & cpu_instruction_master_read))) & 1 & (cpu_instruction_master_qualified_request_cfi_flash_s1 | ~cpu_instruction_master_requests_cfi_flash_s1) & (cpu_instruction_master_granted_cfi_flash_s1 | ~cpu_instruction_master_qualified_request_cfi_flash_s1) & ((~cpu_instruction_master_qualified_request_cfi_flash_s1 | ~cpu_instruction_master_read | (1 & ((cfi_flash_s1_wait_counter_eq_0 & ~d1_tri_state_bridge_avalon_slave_end_xfer)) & (cpu_instruction_master_dbs_address[1] & cpu_instruction_master_dbs_address[0]) & cpu_instruction_master_read)));
//optimize select-logic by passing only those address bits which matter.
assign cpu_instruction_master_address_to_slave = cpu_instruction_master_address[23 : 0];
//cpu_instruction_master_read_but_no_slave_selected assignment, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_instruction_master_read_but_no_slave_selected <= 0;
else
cpu_instruction_master_read_but_no_slave_selected <= cpu_instruction_master_read & cpu_instruction_master_run & ~cpu_instruction_master_is_granted_some_slave;
end
//some slave is getting selected, which is an e_mux
assign cpu_instruction_master_is_granted_some_slave = cpu_instruction_master_granted_cpu_jtag_debug_module |
cpu_instruction_master_granted_epcs_flash_controller_epcs_control_port |
cpu_instruction_master_granted_onchip_memory_s1 |
cpu_instruction_master_granted_sram_16bit_512k_0_avalon_slave_0 |
cpu_instruction_master_granted_cfi_flash_s1;
//latent slave read data valids which may be flushed, which is an e_mux
assign pre_flush_cpu_instruction_master_readdatavalid = cpu_instruction_master_read_data_valid_onchip_memory_s1 |
(cpu_instruction_master_read_data_valid_cfi_flash_s1 & dbs_rdv_counter_overflow);
//latent slave read data valid which is not flushed, which is an e_mux
assign cpu_instruction_master_readdatavalid = cpu_instruction_master_read_but_no_slave_selected |
pre_flush_cpu_instruction_master_readdatavalid |
cpu_instruction_master_read_data_valid_cpu_jtag_debug_module |
cpu_instruction_master_read_but_no_slave_selected |
pre_flush_cpu_instruction_master_readdatavalid |
cpu_instruction_master_read_data_valid_epcs_flash_controller_epcs_control_port |
cpu_instruction_master_read_but_no_slave_selected |
pre_flush_cpu_instruction_master_readdatavalid |
cpu_instruction_master_read_but_no_slave_selected |
pre_flush_cpu_instruction_master_readdatavalid |
(cpu_instruction_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0 & dbs_counter_overflow) |
cpu_instruction_master_read_but_no_slave_selected |
pre_flush_cpu_instruction_master_readdatavalid;
//cpu/instruction_master readdata mux, which is an e_mux
assign cpu_instruction_master_readdata = ({32 {~(cpu_instruction_master_qualified_request_cpu_jtag_debug_module & cpu_instruction_master_read)}} | cpu_jtag_debug_module_readdata_from_sa) &
({32 {~(cpu_instruction_master_qualified_request_epcs_flash_controller_epcs_control_port & cpu_instruction_master_read)}} | epcs_flash_controller_epcs_control_port_readdata_from_sa) &
({32 {~cpu_instruction_master_read_data_valid_onchip_memory_s1}} | onchip_memory_s1_readdata_from_sa) &
({32 {~(cpu_instruction_master_qualified_request_sram_16bit_512k_0_avalon_slave_0 & cpu_instruction_master_read)}} | {sram_16bit_512k_0_avalon_slave_0_readdata_from_sa[15 : 0],
dbs_16_reg_segment_0}) &
({32 {~cpu_instruction_master_read_data_valid_cfi_flash_s1}} | {incoming_tri_state_bridge_data[7 : 0],
dbs_latent_8_reg_segment_2,
dbs_latent_8_reg_segment_1,
dbs_latent_8_reg_segment_0});
//actual waitrequest port, which is an e_assign
assign cpu_instruction_master_waitrequest = ~cpu_instruction_master_run;
//latent max counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_instruction_master_latency_counter <= 0;
else
cpu_instruction_master_latency_counter <= p1_cpu_instruction_master_latency_counter;
end
//latency counter load mux, which is an e_mux
assign p1_cpu_instruction_master_latency_counter = ((cpu_instruction_master_run & cpu_instruction_master_read))? latency_load_value :
(cpu_instruction_master_latency_counter)? cpu_instruction_master_latency_counter - 1 :
0;
//read latency load values, which is an e_mux
assign latency_load_value = ({2 {cpu_instruction_master_requests_onchip_memory_s1}} & 1) |
({2 {cpu_instruction_master_requests_cfi_flash_s1}} & 2);
//input to dbs-16 stored 0, which is an e_mux
assign p1_dbs_16_reg_segment_0 = sram_16bit_512k_0_avalon_slave_0_readdata_from_sa;
//dbs register for dbs-16 segment 0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbs_16_reg_segment_0 <= 0;
else if (dbs_count_enable & ((cpu_instruction_master_dbs_address[1]) == 0))
dbs_16_reg_segment_0 <= p1_dbs_16_reg_segment_0;
end
//dbs count increment, which is an e_mux
assign cpu_instruction_master_dbs_increment = (cpu_instruction_master_requests_sram_16bit_512k_0_avalon_slave_0)? 2 :
(cpu_instruction_master_requests_cfi_flash_s1)? 1 :
0;
//dbs counter overflow, which is an e_assign
assign dbs_counter_overflow = cpu_instruction_master_dbs_address[1] & !(next_dbs_address[1]);
//next master address, which is an e_assign
assign next_dbs_address = cpu_instruction_master_dbs_address + cpu_instruction_master_dbs_increment;
//dbs count enable, which is an e_mux
assign dbs_count_enable = pre_dbs_count_enable;
//dbs counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_instruction_master_dbs_address <= 0;
else if (dbs_count_enable)
cpu_instruction_master_dbs_address <= next_dbs_address;
end
//pre dbs count enable, which is an e_mux
assign pre_dbs_count_enable = (cpu_instruction_master_granted_sram_16bit_512k_0_avalon_slave_0 & cpu_instruction_master_read & 1 & 1 & ~d1_sram_16bit_512k_0_avalon_slave_0_end_xfer) |
((cpu_instruction_master_granted_cfi_flash_s1 & cpu_instruction_master_read & 1 & 1 & ({cfi_flash_s1_wait_counter_eq_0 & ~d1_tri_state_bridge_avalon_slave_end_xfer})));
//input to latent dbs-8 stored 0, which is an e_mux
assign p1_dbs_latent_8_reg_segment_0 = incoming_tri_state_bridge_data;
//dbs register for latent dbs-8 segment 0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbs_latent_8_reg_segment_0 <= 0;
else if (dbs_rdv_count_enable & ((cpu_instruction_master_dbs_rdv_counter[1 : 0]) == 0))
dbs_latent_8_reg_segment_0 <= p1_dbs_latent_8_reg_segment_0;
end
//input to latent dbs-8 stored 1, which is an e_mux
assign p1_dbs_latent_8_reg_segment_1 = incoming_tri_state_bridge_data;
//dbs register for latent dbs-8 segment 1, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbs_latent_8_reg_segment_1 <= 0;
else if (dbs_rdv_count_enable & ((cpu_instruction_master_dbs_rdv_counter[1 : 0]) == 1))
dbs_latent_8_reg_segment_1 <= p1_dbs_latent_8_reg_segment_1;
end
//input to latent dbs-8 stored 2, which is an e_mux
assign p1_dbs_latent_8_reg_segment_2 = incoming_tri_state_bridge_data;
//dbs register for latent dbs-8 segment 2, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbs_latent_8_reg_segment_2 <= 0;
else if (dbs_rdv_count_enable & ((cpu_instruction_master_dbs_rdv_counter[1 : 0]) == 2))
dbs_latent_8_reg_segment_2 <= p1_dbs_latent_8_reg_segment_2;
end
//p1 dbs rdv counter, which is an e_assign
assign cpu_instruction_master_next_dbs_rdv_counter = cpu_instruction_master_dbs_rdv_counter + cpu_instruction_master_dbs_rdv_counter_inc;
//cpu_instruction_master_rdv_inc_mux, which is an e_mux
assign cpu_instruction_master_dbs_rdv_counter_inc = 1;
//master any slave rdv, which is an e_mux
assign dbs_rdv_count_enable = cpu_instruction_master_read_data_valid_cfi_flash_s1;
//dbs rdv counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_instruction_master_dbs_rdv_counter <= 0;
else if (dbs_rdv_count_enable)
cpu_instruction_master_dbs_rdv_counter <= cpu_instruction_master_next_dbs_rdv_counter;
end
//dbs rdv counter overflow, which is an e_assign
assign dbs_rdv_counter_overflow = cpu_instruction_master_dbs_rdv_counter[1] & ~cpu_instruction_master_next_dbs_rdv_counter[1];
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//cpu_instruction_master_address check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_instruction_master_address_last_time <= 0;
else
cpu_instruction_master_address_last_time <= cpu_instruction_master_address;
end
//cpu/instruction_master waited last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
active_and_waiting_last_time <= 0;
else
active_and_waiting_last_time <= cpu_instruction_master_waitrequest & (cpu_instruction_master_read);
end
//cpu_instruction_master_address matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (cpu_instruction_master_address != cpu_instruction_master_address_last_time))
begin
$write("%0d ns: cpu_instruction_master_address did not heed wait!!!", $time);
$stop;
end
end
//cpu_instruction_master_read check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_instruction_master_read_last_time <= 0;
else
cpu_instruction_master_read_last_time <= cpu_instruction_master_read;
end
//cpu_instruction_master_read matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (cpu_instruction_master_read != cpu_instruction_master_read_last_time))
begin
$write("%0d ns: cpu_instruction_master_read did not heed wait!!!", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module epcs_flash_controller_epcs_control_port_arbitrator (
// inputs:
clk,
cpu_data_master_address_to_slave,
cpu_data_master_read,
cpu_data_master_write,
cpu_data_master_writedata,
cpu_instruction_master_address_to_slave,
cpu_instruction_master_latency_counter,
cpu_instruction_master_read,
epcs_flash_controller_epcs_control_port_dataavailable,
epcs_flash_controller_epcs_control_port_endofpacket,
epcs_flash_controller_epcs_control_port_irq,
epcs_flash_controller_epcs_control_port_readdata,
epcs_flash_controller_epcs_control_port_readyfordata,
reset_n,
// outputs:
cpu_data_master_granted_epcs_flash_controller_epcs_control_port,
cpu_data_master_qualified_request_epcs_flash_controller_epcs_control_port,
cpu_data_master_read_data_valid_epcs_flash_controller_epcs_control_port,
cpu_data_master_requests_epcs_flash_controller_epcs_control_port,
cpu_instruction_master_granted_epcs_flash_controller_epcs_control_port,
cpu_instruction_master_qualified_request_epcs_flash_controller_epcs_control_port,
cpu_instruction_master_read_data_valid_epcs_flash_controller_epcs_control_port,
cpu_instruction_master_requests_epcs_flash_controller_epcs_control_port,
d1_epcs_flash_controller_epcs_control_port_end_xfer,
epcs_flash_controller_epcs_control_port_address,
epcs_flash_controller_epcs_control_port_chipselect,
epcs_flash_controller_epcs_control_port_dataavailable_from_sa,
epcs_flash_controller_epcs_control_port_endofpacket_from_sa,
epcs_flash_controller_epcs_control_port_irq_from_sa,
epcs_flash_controller_epcs_control_port_read_n,
epcs_flash_controller_epcs_control_port_readdata_from_sa,
epcs_flash_controller_epcs_control_port_readyfordata_from_sa,
epcs_flash_controller_epcs_control_port_reset_n,
epcs_flash_controller_epcs_control_port_write_n,
epcs_flash_controller_epcs_control_port_writedata
)
;
output cpu_data_master_granted_epcs_flash_controller_epcs_control_port;
output cpu_data_master_qualified_request_epcs_flash_controller_epcs_control_port;
output cpu_data_master_read_data_valid_epcs_flash_controller_epcs_control_port;
output cpu_data_master_requests_epcs_flash_controller_epcs_control_port;
output cpu_instruction_master_granted_epcs_flash_controller_epcs_control_port;
output cpu_instruction_master_qualified_request_epcs_flash_controller_epcs_control_port;
output cpu_instruction_master_read_data_valid_epcs_flash_controller_epcs_control_port;
output cpu_instruction_master_requests_epcs_flash_controller_epcs_control_port;
output d1_epcs_flash_controller_epcs_control_port_end_xfer;
output [ 8: 0] epcs_flash_controller_epcs_control_port_address;
output epcs_flash_controller_epcs_control_port_chipselect;
output epcs_flash_controller_epcs_control_port_dataavailable_from_sa;
output epcs_flash_controller_epcs_control_port_endofpacket_from_sa;
output epcs_flash_controller_epcs_control_port_irq_from_sa;
output epcs_flash_controller_epcs_control_port_read_n;
output [ 31: 0] epcs_flash_controller_epcs_control_port_readdata_from_sa;
output epcs_flash_controller_epcs_control_port_readyfordata_from_sa;
output epcs_flash_controller_epcs_control_port_reset_n;
output epcs_flash_controller_epcs_control_port_write_n;
output [ 31: 0] epcs_flash_controller_epcs_control_port_writedata;
input clk;
input [ 23: 0] cpu_data_master_address_to_slave;
input cpu_data_master_read;
input cpu_data_master_write;
input [ 31: 0] cpu_data_master_writedata;
input [ 23: 0] cpu_instruction_master_address_to_slave;
input [ 1: 0] cpu_instruction_master_latency_counter;
input cpu_instruction_master_read;
input epcs_flash_controller_epcs_control_port_dataavailable;
input epcs_flash_controller_epcs_control_port_endofpacket;
input epcs_flash_controller_epcs_control_port_irq;
input [ 31: 0] epcs_flash_controller_epcs_control_port_readdata;
input epcs_flash_controller_epcs_control_port_readyfordata;
input reset_n;
wire cpu_data_master_arbiterlock;
wire cpu_data_master_arbiterlock2;
wire cpu_data_master_continuerequest;
wire cpu_data_master_granted_epcs_flash_controller_epcs_control_port;
wire cpu_data_master_qualified_request_epcs_flash_controller_epcs_control_port;
wire cpu_data_master_read_data_valid_epcs_flash_controller_epcs_control_port;
wire cpu_data_master_requests_epcs_flash_controller_epcs_control_port;
wire cpu_data_master_saved_grant_epcs_flash_controller_epcs_control_port;
wire cpu_instruction_master_arbiterlock;
wire cpu_instruction_master_arbiterlock2;
wire cpu_instruction_master_continuerequest;
wire cpu_instruction_master_granted_epcs_flash_controller_epcs_control_port;
wire cpu_instruction_master_qualified_request_epcs_flash_controller_epcs_control_port;
wire cpu_instruction_master_read_data_valid_epcs_flash_controller_epcs_control_port;
wire cpu_instruction_master_requests_epcs_flash_controller_epcs_control_port;
wire cpu_instruction_master_saved_grant_epcs_flash_controller_epcs_control_port;
reg d1_epcs_flash_controller_epcs_control_port_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_epcs_flash_controller_epcs_control_port;
wire [ 8: 0] epcs_flash_controller_epcs_control_port_address;
wire epcs_flash_controller_epcs_control_port_allgrants;
wire epcs_flash_controller_epcs_control_port_allow_new_arb_cycle;
wire epcs_flash_controller_epcs_control_port_any_bursting_master_saved_grant;
wire epcs_flash_controller_epcs_control_port_any_continuerequest;
reg [ 1: 0] epcs_flash_controller_epcs_control_port_arb_addend;
wire epcs_flash_controller_epcs_control_port_arb_counter_enable;
reg [ 2: 0] epcs_flash_controller_epcs_control_port_arb_share_counter;
wire [ 2: 0] epcs_flash_controller_epcs_control_port_arb_share_counter_next_value;
wire [ 2: 0] epcs_flash_controller_epcs_control_port_arb_share_set_values;
wire [ 1: 0] epcs_flash_controller_epcs_control_port_arb_winner;
wire epcs_flash_controller_epcs_control_port_arbitration_holdoff_internal;
wire epcs_flash_controller_epcs_control_port_beginbursttransfer_internal;
wire epcs_flash_controller_epcs_control_port_begins_xfer;
wire epcs_flash_controller_epcs_control_port_chipselect;
wire [ 3: 0] epcs_flash_controller_epcs_control_port_chosen_master_double_vector;
wire [ 1: 0] epcs_flash_controller_epcs_control_port_chosen_master_rot_left;
wire epcs_flash_controller_epcs_control_port_dataavailable_from_sa;
wire epcs_flash_controller_epcs_control_port_end_xfer;
wire epcs_flash_controller_epcs_control_port_endofpacket_from_sa;
wire epcs_flash_controller_epcs_control_port_firsttransfer;
wire [ 1: 0] epcs_flash_controller_epcs_control_port_grant_vector;
wire epcs_flash_controller_epcs_control_port_in_a_read_cycle;
wire epcs_flash_controller_epcs_control_port_in_a_write_cycle;
wire epcs_flash_controller_epcs_control_port_irq_from_sa;
wire [ 1: 0] epcs_flash_controller_epcs_control_port_master_qreq_vector;
wire epcs_flash_controller_epcs_control_port_non_bursting_master_requests;
wire epcs_flash_controller_epcs_control_port_read_n;
wire [ 31: 0] epcs_flash_controller_epcs_control_port_readdata_from_sa;
wire epcs_flash_controller_epcs_control_port_readyfordata_from_sa;
reg epcs_flash_controller_epcs_control_port_reg_firsttransfer;
wire epcs_flash_controller_epcs_control_port_reset_n;
reg [ 1: 0] epcs_flash_controller_epcs_control_port_saved_chosen_master_vector;
reg epcs_flash_controller_epcs_control_port_slavearbiterlockenable;
wire epcs_flash_controller_epcs_control_port_slavearbiterlockenable2;
wire epcs_flash_controller_epcs_control_port_unreg_firsttransfer;
wire epcs_flash_controller_epcs_control_port_waits_for_read;
wire epcs_flash_controller_epcs_control_port_waits_for_write;
wire epcs_flash_controller_epcs_control_port_write_n;
wire [ 31: 0] epcs_flash_controller_epcs_control_port_writedata;
wire in_a_read_cycle;
wire in_a_write_cycle;
reg last_cycle_cpu_data_master_granted_slave_epcs_flash_controller_epcs_control_port;
reg last_cycle_cpu_instruction_master_granted_slave_epcs_flash_controller_epcs_control_port;
wire [ 23: 0] shifted_address_to_epcs_flash_controller_epcs_control_port_from_cpu_data_master;
wire [ 23: 0] shifted_address_to_epcs_flash_controller_epcs_control_port_from_cpu_instruction_master;
wire wait_for_epcs_flash_controller_epcs_control_port_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~epcs_flash_controller_epcs_control_port_end_xfer;
end
assign epcs_flash_controller_epcs_control_port_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_epcs_flash_controller_epcs_control_port | cpu_instruction_master_qualified_request_epcs_flash_controller_epcs_control_port));
//assign epcs_flash_controller_epcs_control_port_readdata_from_sa = epcs_flash_controller_epcs_control_port_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign epcs_flash_controller_epcs_control_port_readdata_from_sa = epcs_flash_controller_epcs_control_port_readdata;
assign cpu_data_master_requests_epcs_flash_controller_epcs_control_port = ({cpu_data_master_address_to_slave[23 : 11] , 11'b0} == 24'hb03800) & (cpu_data_master_read | cpu_data_master_write);
//assign epcs_flash_controller_epcs_control_port_dataavailable_from_sa = epcs_flash_controller_epcs_control_port_dataavailable so that symbol knows where to group signals which may go to master only, which is an e_assign
assign epcs_flash_controller_epcs_control_port_dataavailable_from_sa = epcs_flash_controller_epcs_control_port_dataavailable;
//assign epcs_flash_controller_epcs_control_port_readyfordata_from_sa = epcs_flash_controller_epcs_control_port_readyfordata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign epcs_flash_controller_epcs_control_port_readyfordata_from_sa = epcs_flash_controller_epcs_control_port_readyfordata;
//epcs_flash_controller_epcs_control_port_arb_share_counter set values, which is an e_mux
assign epcs_flash_controller_epcs_control_port_arb_share_set_values = 1;
//epcs_flash_controller_epcs_control_port_non_bursting_master_requests mux, which is an e_mux
assign epcs_flash_controller_epcs_control_port_non_bursting_master_requests = cpu_data_master_requests_epcs_flash_controller_epcs_control_port |
cpu_instruction_master_requests_epcs_flash_controller_epcs_control_port |
cpu_data_master_requests_epcs_flash_controller_epcs_control_port |
cpu_instruction_master_requests_epcs_flash_controller_epcs_control_port;
//epcs_flash_controller_epcs_control_port_any_bursting_master_saved_grant mux, which is an e_mux
assign epcs_flash_controller_epcs_control_port_any_bursting_master_saved_grant = 0;
//epcs_flash_controller_epcs_control_port_arb_share_counter_next_value assignment, which is an e_assign
assign epcs_flash_controller_epcs_control_port_arb_share_counter_next_value = epcs_flash_controller_epcs_control_port_firsttransfer ? (epcs_flash_controller_epcs_control_port_arb_share_set_values - 1) : |epcs_flash_controller_epcs_control_port_arb_share_counter ? (epcs_flash_controller_epcs_control_port_arb_share_counter - 1) : 0;
//epcs_flash_controller_epcs_control_port_allgrants all slave grants, which is an e_mux
assign epcs_flash_controller_epcs_control_port_allgrants = (|epcs_flash_controller_epcs_control_port_grant_vector) |
(|epcs_flash_controller_epcs_control_port_grant_vector) |
(|epcs_flash_controller_epcs_control_port_grant_vector) |
(|epcs_flash_controller_epcs_control_port_grant_vector);
//epcs_flash_controller_epcs_control_port_end_xfer assignment, which is an e_assign
assign epcs_flash_controller_epcs_control_port_end_xfer = ~(epcs_flash_controller_epcs_control_port_waits_for_read | epcs_flash_controller_epcs_control_port_waits_for_write);
//end_xfer_arb_share_counter_term_epcs_flash_controller_epcs_control_port arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_epcs_flash_controller_epcs_control_port = epcs_flash_controller_epcs_control_port_end_xfer & (~epcs_flash_controller_epcs_control_port_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//epcs_flash_controller_epcs_control_port_arb_share_counter arbitration counter enable, which is an e_assign
assign epcs_flash_controller_epcs_control_port_arb_counter_enable = (end_xfer_arb_share_counter_term_epcs_flash_controller_epcs_control_port & epcs_flash_controller_epcs_control_port_allgrants) | (end_xfer_arb_share_counter_term_epcs_flash_controller_epcs_control_port & ~epcs_flash_controller_epcs_control_port_non_bursting_master_requests);
//epcs_flash_controller_epcs_control_port_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
epcs_flash_controller_epcs_control_port_arb_share_counter <= 0;
else if (epcs_flash_controller_epcs_control_port_arb_counter_enable)
epcs_flash_controller_epcs_control_port_arb_share_counter <= epcs_flash_controller_epcs_control_port_arb_share_counter_next_value;
end
//epcs_flash_controller_epcs_control_port_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
epcs_flash_controller_epcs_control_port_slavearbiterlockenable <= 0;
else if ((|epcs_flash_controller_epcs_control_port_master_qreq_vector & end_xfer_arb_share_counter_term_epcs_flash_controller_epcs_control_port) | (end_xfer_arb_share_counter_term_epcs_flash_controller_epcs_control_port & ~epcs_flash_controller_epcs_control_port_non_bursting_master_requests))
epcs_flash_controller_epcs_control_port_slavearbiterlockenable <= |epcs_flash_controller_epcs_control_port_arb_share_counter_next_value;
end
//cpu/data_master epcs_flash_controller/epcs_control_port arbiterlock, which is an e_assign
assign cpu_data_master_arbiterlock = epcs_flash_controller_epcs_control_port_slavearbiterlockenable & cpu_data_master_continuerequest;
//epcs_flash_controller_epcs_control_port_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign epcs_flash_controller_epcs_control_port_slavearbiterlockenable2 = |epcs_flash_controller_epcs_control_port_arb_share_counter_next_value;
//cpu/data_master epcs_flash_controller/epcs_control_port arbiterlock2, which is an e_assign
assign cpu_data_master_arbiterlock2 = epcs_flash_controller_epcs_control_port_slavearbiterlockenable2 & cpu_data_master_continuerequest;
//cpu/instruction_master epcs_flash_controller/epcs_control_port arbiterlock, which is an e_assign
assign cpu_instruction_master_arbiterlock = epcs_flash_controller_epcs_control_port_slavearbiterlockenable & cpu_instruction_master_continuerequest;
//cpu/instruction_master epcs_flash_controller/epcs_control_port arbiterlock2, which is an e_assign
assign cpu_instruction_master_arbiterlock2 = epcs_flash_controller_epcs_control_port_slavearbiterlockenable2 & cpu_instruction_master_continuerequest;
//cpu/instruction_master granted epcs_flash_controller/epcs_control_port last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_instruction_master_granted_slave_epcs_flash_controller_epcs_control_port <= 0;
else
last_cycle_cpu_instruction_master_granted_slave_epcs_flash_controller_epcs_control_port <= cpu_instruction_master_saved_grant_epcs_flash_controller_epcs_control_port ? 1 : (epcs_flash_controller_epcs_control_port_arbitration_holdoff_internal | ~cpu_instruction_master_requests_epcs_flash_controller_epcs_control_port) ? 0 : last_cycle_cpu_instruction_master_granted_slave_epcs_flash_controller_epcs_control_port;
end
//cpu_instruction_master_continuerequest continued request, which is an e_mux
assign cpu_instruction_master_continuerequest = last_cycle_cpu_instruction_master_granted_slave_epcs_flash_controller_epcs_control_port & cpu_instruction_master_requests_epcs_flash_controller_epcs_control_port;
//epcs_flash_controller_epcs_control_port_any_continuerequest at least one master continues requesting, which is an e_mux
assign epcs_flash_controller_epcs_control_port_any_continuerequest = cpu_instruction_master_continuerequest |
cpu_data_master_continuerequest;
assign cpu_data_master_qualified_request_epcs_flash_controller_epcs_control_port = cpu_data_master_requests_epcs_flash_controller_epcs_control_port & ~(cpu_instruction_master_arbiterlock);
//epcs_flash_controller_epcs_control_port_writedata mux, which is an e_mux
assign epcs_flash_controller_epcs_control_port_writedata = cpu_data_master_writedata;
//assign epcs_flash_controller_epcs_control_port_endofpacket_from_sa = epcs_flash_controller_epcs_control_port_endofpacket so that symbol knows where to group signals which may go to master only, which is an e_assign
assign epcs_flash_controller_epcs_control_port_endofpacket_from_sa = epcs_flash_controller_epcs_control_port_endofpacket;
assign cpu_instruction_master_requests_epcs_flash_controller_epcs_control_port = (({cpu_instruction_master_address_to_slave[23 : 11] , 11'b0} == 24'hb03800) & (cpu_instruction_master_read)) & cpu_instruction_master_read;
//cpu/data_master granted epcs_flash_controller/epcs_control_port last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_data_master_granted_slave_epcs_flash_controller_epcs_control_port <= 0;
else
last_cycle_cpu_data_master_granted_slave_epcs_flash_controller_epcs_control_port <= cpu_data_master_saved_grant_epcs_flash_controller_epcs_control_port ? 1 : (epcs_flash_controller_epcs_control_port_arbitration_holdoff_internal | ~cpu_data_master_requests_epcs_flash_controller_epcs_control_port) ? 0 : last_cycle_cpu_data_master_granted_slave_epcs_flash_controller_epcs_control_port;
end
//cpu_data_master_continuerequest continued request, which is an e_mux
assign cpu_data_master_continuerequest = last_cycle_cpu_data_master_granted_slave_epcs_flash_controller_epcs_control_port & cpu_data_master_requests_epcs_flash_controller_epcs_control_port;
assign cpu_instruction_master_qualified_request_epcs_flash_controller_epcs_control_port = cpu_instruction_master_requests_epcs_flash_controller_epcs_control_port & ~((cpu_instruction_master_read & ((cpu_instruction_master_latency_counter != 0))) | cpu_data_master_arbiterlock);
//local readdatavalid cpu_instruction_master_read_data_valid_epcs_flash_controller_epcs_control_port, which is an e_mux
assign cpu_instruction_master_read_data_valid_epcs_flash_controller_epcs_control_port = cpu_instruction_master_granted_epcs_flash_controller_epcs_control_port & cpu_instruction_master_read & ~epcs_flash_controller_epcs_control_port_waits_for_read;
//allow new arb cycle for epcs_flash_controller/epcs_control_port, which is an e_assign
assign epcs_flash_controller_epcs_control_port_allow_new_arb_cycle = ~cpu_data_master_arbiterlock & ~cpu_instruction_master_arbiterlock;
//cpu/instruction_master assignment into master qualified-requests vector for epcs_flash_controller/epcs_control_port, which is an e_assign
assign epcs_flash_controller_epcs_control_port_master_qreq_vector[0] = cpu_instruction_master_qualified_request_epcs_flash_controller_epcs_control_port;
//cpu/instruction_master grant epcs_flash_controller/epcs_control_port, which is an e_assign
assign cpu_instruction_master_granted_epcs_flash_controller_epcs_control_port = epcs_flash_controller_epcs_control_port_grant_vector[0];
//cpu/instruction_master saved-grant epcs_flash_controller/epcs_control_port, which is an e_assign
assign cpu_instruction_master_saved_grant_epcs_flash_controller_epcs_control_port = epcs_flash_controller_epcs_control_port_arb_winner[0] && cpu_instruction_master_requests_epcs_flash_controller_epcs_control_port;
//cpu/data_master assignment into master qualified-requests vector for epcs_flash_controller/epcs_control_port, which is an e_assign
assign epcs_flash_controller_epcs_control_port_master_qreq_vector[1] = cpu_data_master_qualified_request_epcs_flash_controller_epcs_control_port;
//cpu/data_master grant epcs_flash_controller/epcs_control_port, which is an e_assign
assign cpu_data_master_granted_epcs_flash_controller_epcs_control_port = epcs_flash_controller_epcs_control_port_grant_vector[1];
//cpu/data_master saved-grant epcs_flash_controller/epcs_control_port, which is an e_assign
assign cpu_data_master_saved_grant_epcs_flash_controller_epcs_control_port = epcs_flash_controller_epcs_control_port_arb_winner[1] && cpu_data_master_requests_epcs_flash_controller_epcs_control_port;
//epcs_flash_controller/epcs_control_port chosen-master double-vector, which is an e_assign
assign epcs_flash_controller_epcs_control_port_chosen_master_double_vector = {epcs_flash_controller_epcs_control_port_master_qreq_vector, epcs_flash_controller_epcs_control_port_master_qreq_vector} & ({~epcs_flash_controller_epcs_control_port_master_qreq_vector, ~epcs_flash_controller_epcs_control_port_master_qreq_vector} + epcs_flash_controller_epcs_control_port_arb_addend);
//stable onehot encoding of arb winner
assign epcs_flash_controller_epcs_control_port_arb_winner = (epcs_flash_controller_epcs_control_port_allow_new_arb_cycle & | epcs_flash_controller_epcs_control_port_grant_vector) ? epcs_flash_controller_epcs_control_port_grant_vector : epcs_flash_controller_epcs_control_port_saved_chosen_master_vector;
//saved epcs_flash_controller_epcs_control_port_grant_vector, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
epcs_flash_controller_epcs_control_port_saved_chosen_master_vector <= 0;
else if (epcs_flash_controller_epcs_control_port_allow_new_arb_cycle)
epcs_flash_controller_epcs_control_port_saved_chosen_master_vector <= |epcs_flash_controller_epcs_control_port_grant_vector ? epcs_flash_controller_epcs_control_port_grant_vector : epcs_flash_controller_epcs_control_port_saved_chosen_master_vector;
end
//onehot encoding of chosen master
assign epcs_flash_controller_epcs_control_port_grant_vector = {(epcs_flash_controller_epcs_control_port_chosen_master_double_vector[1] | epcs_flash_controller_epcs_control_port_chosen_master_double_vector[3]),
(epcs_flash_controller_epcs_control_port_chosen_master_double_vector[0] | epcs_flash_controller_epcs_control_port_chosen_master_double_vector[2])};
//epcs_flash_controller/epcs_control_port chosen master rotated left, which is an e_assign
assign epcs_flash_controller_epcs_control_port_chosen_master_rot_left = (epcs_flash_controller_epcs_control_port_arb_winner << 1) ? (epcs_flash_controller_epcs_control_port_arb_winner << 1) : 1;
//epcs_flash_controller/epcs_control_port's addend for next-master-grant
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
epcs_flash_controller_epcs_control_port_arb_addend <= 1;
else if (|epcs_flash_controller_epcs_control_port_grant_vector)
epcs_flash_controller_epcs_control_port_arb_addend <= epcs_flash_controller_epcs_control_port_end_xfer? epcs_flash_controller_epcs_control_port_chosen_master_rot_left : epcs_flash_controller_epcs_control_port_grant_vector;
end
//epcs_flash_controller_epcs_control_port_reset_n assignment, which is an e_assign
assign epcs_flash_controller_epcs_control_port_reset_n = reset_n;
assign epcs_flash_controller_epcs_control_port_chipselect = cpu_data_master_granted_epcs_flash_controller_epcs_control_port | cpu_instruction_master_granted_epcs_flash_controller_epcs_control_port;
//epcs_flash_controller_epcs_control_port_firsttransfer first transaction, which is an e_assign
assign epcs_flash_controller_epcs_control_port_firsttransfer = epcs_flash_controller_epcs_control_port_begins_xfer ? epcs_flash_controller_epcs_control_port_unreg_firsttransfer : epcs_flash_controller_epcs_control_port_reg_firsttransfer;
//epcs_flash_controller_epcs_control_port_unreg_firsttransfer first transaction, which is an e_assign
assign epcs_flash_controller_epcs_control_port_unreg_firsttransfer = ~(epcs_flash_controller_epcs_control_port_slavearbiterlockenable & epcs_flash_controller_epcs_control_port_any_continuerequest);
//epcs_flash_controller_epcs_control_port_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
epcs_flash_controller_epcs_control_port_reg_firsttransfer <= 1'b1;
else if (epcs_flash_controller_epcs_control_port_begins_xfer)
epcs_flash_controller_epcs_control_port_reg_firsttransfer <= epcs_flash_controller_epcs_control_port_unreg_firsttransfer;
end
//epcs_flash_controller_epcs_control_port_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign epcs_flash_controller_epcs_control_port_beginbursttransfer_internal = epcs_flash_controller_epcs_control_port_begins_xfer;
//epcs_flash_controller_epcs_control_port_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
assign epcs_flash_controller_epcs_control_port_arbitration_holdoff_internal = epcs_flash_controller_epcs_control_port_begins_xfer & epcs_flash_controller_epcs_control_port_firsttransfer;
//~epcs_flash_controller_epcs_control_port_read_n assignment, which is an e_mux
assign epcs_flash_controller_epcs_control_port_read_n = ~((cpu_data_master_granted_epcs_flash_controller_epcs_control_port & cpu_data_master_read) | (cpu_instruction_master_granted_epcs_flash_controller_epcs_control_port & cpu_instruction_master_read));
//~epcs_flash_controller_epcs_control_port_write_n assignment, which is an e_mux
assign epcs_flash_controller_epcs_control_port_write_n = ~(cpu_data_master_granted_epcs_flash_controller_epcs_control_port & cpu_data_master_write);
assign shifted_address_to_epcs_flash_controller_epcs_control_port_from_cpu_data_master = cpu_data_master_address_to_slave;
//epcs_flash_controller_epcs_control_port_address mux, which is an e_mux
assign epcs_flash_controller_epcs_control_port_address = (cpu_data_master_granted_epcs_flash_controller_epcs_control_port)? (shifted_address_to_epcs_flash_controller_epcs_control_port_from_cpu_data_master >> 2) :
(shifted_address_to_epcs_flash_controller_epcs_control_port_from_cpu_instruction_master >> 2);
assign shifted_address_to_epcs_flash_controller_epcs_control_port_from_cpu_instruction_master = cpu_instruction_master_address_to_slave;
//d1_epcs_flash_controller_epcs_control_port_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_epcs_flash_controller_epcs_control_port_end_xfer <= 1;
else
d1_epcs_flash_controller_epcs_control_port_end_xfer <= epcs_flash_controller_epcs_control_port_end_xfer;
end
//epcs_flash_controller_epcs_control_port_waits_for_read in a cycle, which is an e_mux
assign epcs_flash_controller_epcs_control_port_waits_for_read = epcs_flash_controller_epcs_control_port_in_a_read_cycle & epcs_flash_controller_epcs_control_port_begins_xfer;
//epcs_flash_controller_epcs_control_port_in_a_read_cycle assignment, which is an e_assign
assign epcs_flash_controller_epcs_control_port_in_a_read_cycle = (cpu_data_master_granted_epcs_flash_controller_epcs_control_port & cpu_data_master_read) | (cpu_instruction_master_granted_epcs_flash_controller_epcs_control_port & cpu_instruction_master_read);
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = epcs_flash_controller_epcs_control_port_in_a_read_cycle;
//epcs_flash_controller_epcs_control_port_waits_for_write in a cycle, which is an e_mux
assign epcs_flash_controller_epcs_control_port_waits_for_write = epcs_flash_controller_epcs_control_port_in_a_write_cycle & epcs_flash_controller_epcs_control_port_begins_xfer;
//epcs_flash_controller_epcs_control_port_in_a_write_cycle assignment, which is an e_assign
assign epcs_flash_controller_epcs_control_port_in_a_write_cycle = cpu_data_master_granted_epcs_flash_controller_epcs_control_port & cpu_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = epcs_flash_controller_epcs_control_port_in_a_write_cycle;
assign wait_for_epcs_flash_controller_epcs_control_port_counter = 0;
//assign epcs_flash_controller_epcs_control_port_irq_from_sa = epcs_flash_controller_epcs_control_port_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
assign epcs_flash_controller_epcs_control_port_irq_from_sa = epcs_flash_controller_epcs_control_port_irq;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//epcs_flash_controller/epcs_control_port enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_data_master_granted_epcs_flash_controller_epcs_control_port + cpu_instruction_master_granted_epcs_flash_controller_epcs_control_port > 1)
begin
$write("%0d ns: > 1 of grant signals are active simultaneously", $time);
$stop;
end
end
//saved_grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_data_master_saved_grant_epcs_flash_controller_epcs_control_port + cpu_instruction_master_saved_grant_epcs_flash_controller_epcs_control_port > 1)
begin
$write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module gpio_s1_arbitrator (
// inputs:
clk,
cpu_data_master_address_to_slave,
cpu_data_master_read,
cpu_data_master_waitrequest,
cpu_data_master_write,
cpu_data_master_writedata,
gpio_s1_irq,
gpio_s1_readdata,
reset_n,
// outputs:
cpu_data_master_granted_gpio_s1,
cpu_data_master_qualified_request_gpio_s1,
cpu_data_master_read_data_valid_gpio_s1,
cpu_data_master_requests_gpio_s1,
d1_gpio_s1_end_xfer,
gpio_s1_address,
gpio_s1_chipselect,
gpio_s1_irq_from_sa,
gpio_s1_readdata_from_sa,
gpio_s1_reset_n,
gpio_s1_write_n,
gpio_s1_writedata
)
;
output cpu_data_master_granted_gpio_s1;
output cpu_data_master_qualified_request_gpio_s1;
output cpu_data_master_read_data_valid_gpio_s1;
output cpu_data_master_requests_gpio_s1;
output d1_gpio_s1_end_xfer;
output [ 1: 0] gpio_s1_address;
output gpio_s1_chipselect;
output gpio_s1_irq_from_sa;
output [ 31: 0] gpio_s1_readdata_from_sa;
output gpio_s1_reset_n;
output gpio_s1_write_n;
output [ 31: 0] gpio_s1_writedata;
input clk;
input [ 23: 0] cpu_data_master_address_to_slave;
input cpu_data_master_read;
input cpu_data_master_waitrequest;
input cpu_data_master_write;
input [ 31: 0] cpu_data_master_writedata;
input gpio_s1_irq;
input [ 31: 0] gpio_s1_readdata;
input reset_n;
wire cpu_data_master_arbiterlock;
wire cpu_data_master_arbiterlock2;
wire cpu_data_master_continuerequest;
wire cpu_data_master_granted_gpio_s1;
wire cpu_data_master_qualified_request_gpio_s1;
wire cpu_data_master_read_data_valid_gpio_s1;
wire cpu_data_master_requests_gpio_s1;
wire cpu_data_master_saved_grant_gpio_s1;
reg d1_gpio_s1_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_gpio_s1;
wire [ 1: 0] gpio_s1_address;
wire gpio_s1_allgrants;
wire gpio_s1_allow_new_arb_cycle;
wire gpio_s1_any_bursting_master_saved_grant;
wire gpio_s1_any_continuerequest;
wire gpio_s1_arb_counter_enable;
reg [ 2: 0] gpio_s1_arb_share_counter;
wire [ 2: 0] gpio_s1_arb_share_counter_next_value;
wire [ 2: 0] gpio_s1_arb_share_set_values;
wire gpio_s1_beginbursttransfer_internal;
wire gpio_s1_begins_xfer;
wire gpio_s1_chipselect;
wire gpio_s1_end_xfer;
wire gpio_s1_firsttransfer;
wire gpio_s1_grant_vector;
wire gpio_s1_in_a_read_cycle;
wire gpio_s1_in_a_write_cycle;
wire gpio_s1_irq_from_sa;
wire gpio_s1_master_qreq_vector;
wire gpio_s1_non_bursting_master_requests;
wire [ 31: 0] gpio_s1_readdata_from_sa;
reg gpio_s1_reg_firsttransfer;
wire gpio_s1_reset_n;
reg gpio_s1_slavearbiterlockenable;
wire gpio_s1_slavearbiterlockenable2;
wire gpio_s1_unreg_firsttransfer;
wire gpio_s1_waits_for_read;
wire gpio_s1_waits_for_write;
wire gpio_s1_write_n;
wire [ 31: 0] gpio_s1_writedata;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 23: 0] shifted_address_to_gpio_s1_from_cpu_data_master;
wire wait_for_gpio_s1_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~gpio_s1_end_xfer;
end
assign gpio_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_gpio_s1));
//assign gpio_s1_readdata_from_sa = gpio_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign gpio_s1_readdata_from_sa = gpio_s1_readdata;
assign cpu_data_master_requests_gpio_s1 = ({cpu_data_master_address_to_slave[23 : 4] , 4'b0} == 24'hb04030) & (cpu_data_master_read | cpu_data_master_write);
//gpio_s1_arb_share_counter set values, which is an e_mux
assign gpio_s1_arb_share_set_values = 1;
//gpio_s1_non_bursting_master_requests mux, which is an e_mux
assign gpio_s1_non_bursting_master_requests = cpu_data_master_requests_gpio_s1;
//gpio_s1_any_bursting_master_saved_grant mux, which is an e_mux
assign gpio_s1_any_bursting_master_saved_grant = 0;
//gpio_s1_arb_share_counter_next_value assignment, which is an e_assign
assign gpio_s1_arb_share_counter_next_value = gpio_s1_firsttransfer ? (gpio_s1_arb_share_set_values - 1) : |gpio_s1_arb_share_counter ? (gpio_s1_arb_share_counter - 1) : 0;
//gpio_s1_allgrants all slave grants, which is an e_mux
assign gpio_s1_allgrants = |gpio_s1_grant_vector;
//gpio_s1_end_xfer assignment, which is an e_assign
assign gpio_s1_end_xfer = ~(gpio_s1_waits_for_read | gpio_s1_waits_for_write);
//end_xfer_arb_share_counter_term_gpio_s1 arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_gpio_s1 = gpio_s1_end_xfer & (~gpio_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//gpio_s1_arb_share_counter arbitration counter enable, which is an e_assign
assign gpio_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_gpio_s1 & gpio_s1_allgrants) | (end_xfer_arb_share_counter_term_gpio_s1 & ~gpio_s1_non_bursting_master_requests);
//gpio_s1_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
gpio_s1_arb_share_counter <= 0;
else if (gpio_s1_arb_counter_enable)
gpio_s1_arb_share_counter <= gpio_s1_arb_share_counter_next_value;
end
//gpio_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
gpio_s1_slavearbiterlockenable <= 0;
else if ((|gpio_s1_master_qreq_vector & end_xfer_arb_share_counter_term_gpio_s1) | (end_xfer_arb_share_counter_term_gpio_s1 & ~gpio_s1_non_bursting_master_requests))
gpio_s1_slavearbiterlockenable <= |gpio_s1_arb_share_counter_next_value;
end
//cpu/data_master gpio/s1 arbiterlock, which is an e_assign
assign cpu_data_master_arbiterlock = gpio_s1_slavearbiterlockenable & cpu_data_master_continuerequest;
//gpio_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign gpio_s1_slavearbiterlockenable2 = |gpio_s1_arb_share_counter_next_value;
//cpu/data_master gpio/s1 arbiterlock2, which is an e_assign
assign cpu_data_master_arbiterlock2 = gpio_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;
//gpio_s1_any_continuerequest at least one master continues requesting, which is an e_assign
assign gpio_s1_any_continuerequest = 1;
//cpu_data_master_continuerequest continued request, which is an e_assign
assign cpu_data_master_continuerequest = 1;
assign cpu_data_master_qualified_request_gpio_s1 = cpu_data_master_requests_gpio_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
//gpio_s1_writedata mux, which is an e_mux
assign gpio_s1_writedata = cpu_data_master_writedata;
//master is always granted when requested
assign cpu_data_master_granted_gpio_s1 = cpu_data_master_qualified_request_gpio_s1;
//cpu/data_master saved-grant gpio/s1, which is an e_assign
assign cpu_data_master_saved_grant_gpio_s1 = cpu_data_master_requests_gpio_s1;
//allow new arb cycle for gpio/s1, which is an e_assign
assign gpio_s1_allow_new_arb_cycle = 1;
//placeholder chosen master
assign gpio_s1_grant_vector = 1;
//placeholder vector of master qualified-requests
assign gpio_s1_master_qreq_vector = 1;
//gpio_s1_reset_n assignment, which is an e_assign
assign gpio_s1_reset_n = reset_n;
assign gpio_s1_chipselect = cpu_data_master_granted_gpio_s1;
//gpio_s1_firsttransfer first transaction, which is an e_assign
assign gpio_s1_firsttransfer = gpio_s1_begins_xfer ? gpio_s1_unreg_firsttransfer : gpio_s1_reg_firsttransfer;
//gpio_s1_unreg_firsttransfer first transaction, which is an e_assign
assign gpio_s1_unreg_firsttransfer = ~(gpio_s1_slavearbiterlockenable & gpio_s1_any_continuerequest);
//gpio_s1_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
gpio_s1_reg_firsttransfer <= 1'b1;
else if (gpio_s1_begins_xfer)
gpio_s1_reg_firsttransfer <= gpio_s1_unreg_firsttransfer;
end
//gpio_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign gpio_s1_beginbursttransfer_internal = gpio_s1_begins_xfer;
//~gpio_s1_write_n assignment, which is an e_mux
assign gpio_s1_write_n = ~(cpu_data_master_granted_gpio_s1 & cpu_data_master_write);
assign shifted_address_to_gpio_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
//gpio_s1_address mux, which is an e_mux
assign gpio_s1_address = shifted_address_to_gpio_s1_from_cpu_data_master >> 2;
//d1_gpio_s1_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_gpio_s1_end_xfer <= 1;
else
d1_gpio_s1_end_xfer <= gpio_s1_end_xfer;
end
//gpio_s1_waits_for_read in a cycle, which is an e_mux
assign gpio_s1_waits_for_read = gpio_s1_in_a_read_cycle & gpio_s1_begins_xfer;
//gpio_s1_in_a_read_cycle assignment, which is an e_assign
assign gpio_s1_in_a_read_cycle = cpu_data_master_granted_gpio_s1 & cpu_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = gpio_s1_in_a_read_cycle;
//gpio_s1_waits_for_write in a cycle, which is an e_mux
assign gpio_s1_waits_for_write = gpio_s1_in_a_write_cycle & 0;
//gpio_s1_in_a_write_cycle assignment, which is an e_assign
assign gpio_s1_in_a_write_cycle = cpu_data_master_granted_gpio_s1 & cpu_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = gpio_s1_in_a_write_cycle;
assign wait_for_gpio_s1_counter = 0;
//assign gpio_s1_irq_from_sa = gpio_s1_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
assign gpio_s1_irq_from_sa = gpio_s1_irq;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//gpio/s1 enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module hardmodle_s1_arbitrator (
// inputs:
clk,
cpu_data_master_address_to_slave,
cpu_data_master_read,
cpu_data_master_write,
hardmodle_s1_readdata,
reset_n,
// outputs:
cpu_data_master_granted_hardmodle_s1,
cpu_data_master_qualified_request_hardmodle_s1,
cpu_data_master_read_data_valid_hardmodle_s1,
cpu_data_master_requests_hardmodle_s1,
d1_hardmodle_s1_end_xfer,
hardmodle_s1_address,
hardmodle_s1_readdata_from_sa,
hardmodle_s1_reset_n
)
;
output cpu_data_master_granted_hardmodle_s1;
output cpu_data_master_qualified_request_hardmodle_s1;
output cpu_data_master_read_data_valid_hardmodle_s1;
output cpu_data_master_requests_hardmodle_s1;
output d1_hardmodle_s1_end_xfer;
output [ 1: 0] hardmodle_s1_address;
output [ 31: 0] hardmodle_s1_readdata_from_sa;
output hardmodle_s1_reset_n;
input clk;
input [ 23: 0] cpu_data_master_address_to_slave;
input cpu_data_master_read;
input cpu_data_master_write;
input [ 31: 0] hardmodle_s1_readdata;
input reset_n;
wire cpu_data_master_arbiterlock;
wire cpu_data_master_arbiterlock2;
wire cpu_data_master_continuerequest;
wire cpu_data_master_granted_hardmodle_s1;
wire cpu_data_master_qualified_request_hardmodle_s1;
wire cpu_data_master_read_data_valid_hardmodle_s1;
wire cpu_data_master_requests_hardmodle_s1;
wire cpu_data_master_saved_grant_hardmodle_s1;
reg d1_hardmodle_s1_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_hardmodle_s1;
wire [ 1: 0] hardmodle_s1_address;
wire hardmodle_s1_allgrants;
wire hardmodle_s1_allow_new_arb_cycle;
wire hardmodle_s1_any_bursting_master_saved_grant;
wire hardmodle_s1_any_continuerequest;
wire hardmodle_s1_arb_counter_enable;
reg [ 2: 0] hardmodle_s1_arb_share_counter;
wire [ 2: 0] hardmodle_s1_arb_share_counter_next_value;
wire [ 2: 0] hardmodle_s1_arb_share_set_values;
wire hardmodle_s1_beginbursttransfer_internal;
wire hardmodle_s1_begins_xfer;
wire hardmodle_s1_end_xfer;
wire hardmodle_s1_firsttransfer;
wire hardmodle_s1_grant_vector;
wire hardmodle_s1_in_a_read_cycle;
wire hardmodle_s1_in_a_write_cycle;
wire hardmodle_s1_master_qreq_vector;
wire hardmodle_s1_non_bursting_master_requests;
wire [ 31: 0] hardmodle_s1_readdata_from_sa;
reg hardmodle_s1_reg_firsttransfer;
wire hardmodle_s1_reset_n;
reg hardmodle_s1_slavearbiterlockenable;
wire hardmodle_s1_slavearbiterlockenable2;
wire hardmodle_s1_unreg_firsttransfer;
wire hardmodle_s1_waits_for_read;
wire hardmodle_s1_waits_for_write;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 23: 0] shifted_address_to_hardmodle_s1_from_cpu_data_master;
wire wait_for_hardmodle_s1_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~hardmodle_s1_end_xfer;
end
assign hardmodle_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_hardmodle_s1));
//assign hardmodle_s1_readdata_from_sa = hardmodle_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign hardmodle_s1_readdata_from_sa = hardmodle_s1_readdata;
assign cpu_data_master_requests_hardmodle_s1 = (({cpu_data_master_address_to_slave[23 : 4] , 4'b0} == 24'hb04060) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_read;
//hardmodle_s1_arb_share_counter set values, which is an e_mux
assign hardmodle_s1_arb_share_set_values = 1;
//hardmodle_s1_non_bursting_master_requests mux, which is an e_mux
assign hardmodle_s1_non_bursting_master_requests = cpu_data_master_requests_hardmodle_s1;
//hardmodle_s1_any_bursting_master_saved_grant mux, which is an e_mux
assign hardmodle_s1_any_bursting_master_saved_grant = 0;
//hardmodle_s1_arb_share_counter_next_value assignment, which is an e_assign
assign hardmodle_s1_arb_share_counter_next_value = hardmodle_s1_firsttransfer ? (hardmodle_s1_arb_share_set_values - 1) : |hardmodle_s1_arb_share_counter ? (hardmodle_s1_arb_share_counter - 1) : 0;
//hardmodle_s1_allgrants all slave grants, which is an e_mux
assign hardmodle_s1_allgrants = |hardmodle_s1_grant_vector;
//hardmodle_s1_end_xfer assignment, which is an e_assign
assign hardmodle_s1_end_xfer = ~(hardmodle_s1_waits_for_read | hardmodle_s1_waits_for_write);
//end_xfer_arb_share_counter_term_hardmodle_s1 arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_hardmodle_s1 = hardmodle_s1_end_xfer & (~hardmodle_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//hardmodle_s1_arb_share_counter arbitration counter enable, which is an e_assign
assign hardmodle_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_hardmodle_s1 & hardmodle_s1_allgrants) | (end_xfer_arb_share_counter_term_hardmodle_s1 & ~hardmodle_s1_non_bursting_master_requests);
//hardmodle_s1_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hardmodle_s1_arb_share_counter <= 0;
else if (hardmodle_s1_arb_counter_enable)
hardmodle_s1_arb_share_counter <= hardmodle_s1_arb_share_counter_next_value;
end
//hardmodle_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hardmodle_s1_slavearbiterlockenable <= 0;
else if ((|hardmodle_s1_master_qreq_vector & end_xfer_arb_share_counter_term_hardmodle_s1) | (end_xfer_arb_share_counter_term_hardmodle_s1 & ~hardmodle_s1_non_bursting_master_requests))
hardmodle_s1_slavearbiterlockenable <= |hardmodle_s1_arb_share_counter_next_value;
end
//cpu/data_master hardmodle/s1 arbiterlock, which is an e_assign
assign cpu_data_master_arbiterlock = hardmodle_s1_slavearbiterlockenable & cpu_data_master_continuerequest;
//hardmodle_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign hardmodle_s1_slavearbiterlockenable2 = |hardmodle_s1_arb_share_counter_next_value;
//cpu/data_master hardmodle/s1 arbiterlock2, which is an e_assign
assign cpu_data_master_arbiterlock2 = hardmodle_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;
//hardmodle_s1_any_continuerequest at least one master continues requesting, which is an e_assign
assign hardmodle_s1_any_continuerequest = 1;
//cpu_data_master_continuerequest continued request, which is an e_assign
assign cpu_data_master_continuerequest = 1;
assign cpu_data_master_qualified_request_hardmodle_s1 = cpu_data_master_requests_hardmodle_s1;
//master is always granted when requested
assign cpu_data_master_granted_hardmodle_s1 = cpu_data_master_qualified_request_hardmodle_s1;
//cpu/data_master saved-grant hardmodle/s1, which is an e_assign
assign cpu_data_master_saved_grant_hardmodle_s1 = cpu_data_master_requests_hardmodle_s1;
//allow new arb cycle for hardmodle/s1, which is an e_assign
assign hardmodle_s1_allow_new_arb_cycle = 1;
//placeholder chosen master
assign hardmodle_s1_grant_vector = 1;
//placeholder vector of master qualified-requests
assign hardmodle_s1_master_qreq_vector = 1;
//hardmodle_s1_reset_n assignment, which is an e_assign
assign hardmodle_s1_reset_n = reset_n;
//hardmodle_s1_firsttransfer first transaction, which is an e_assign
assign hardmodle_s1_firsttransfer = hardmodle_s1_begins_xfer ? hardmodle_s1_unreg_firsttransfer : hardmodle_s1_reg_firsttransfer;
//hardmodle_s1_unreg_firsttransfer first transaction, which is an e_assign
assign hardmodle_s1_unreg_firsttransfer = ~(hardmodle_s1_slavearbiterlockenable & hardmodle_s1_any_continuerequest);
//hardmodle_s1_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hardmodle_s1_reg_firsttransfer <= 1'b1;
else if (hardmodle_s1_begins_xfer)
hardmodle_s1_reg_firsttransfer <= hardmodle_s1_unreg_firsttransfer;
end
//hardmodle_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign hardmodle_s1_beginbursttransfer_internal = hardmodle_s1_begins_xfer;
assign shifted_address_to_hardmodle_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
//hardmodle_s1_address mux, which is an e_mux
assign hardmodle_s1_address = shifted_address_to_hardmodle_s1_from_cpu_data_master >> 2;
//d1_hardmodle_s1_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_hardmodle_s1_end_xfer <= 1;
else
d1_hardmodle_s1_end_xfer <= hardmodle_s1_end_xfer;
end
//hardmodle_s1_waits_for_read in a cycle, which is an e_mux
assign hardmodle_s1_waits_for_read = hardmodle_s1_in_a_read_cycle & hardmodle_s1_begins_xfer;
//hardmodle_s1_in_a_read_cycle assignment, which is an e_assign
assign hardmodle_s1_in_a_read_cycle = cpu_data_master_granted_hardmodle_s1 & cpu_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = hardmodle_s1_in_a_read_cycle;
//hardmodle_s1_waits_for_write in a cycle, which is an e_mux
assign hardmodle_s1_waits_for_write = hardmodle_s1_in_a_write_cycle & 0;
//hardmodle_s1_in_a_write_cycle assignment, which is an e_assign
assign hardmodle_s1_in_a_write_cycle = cpu_data_master_granted_hardmodle_s1 & cpu_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = hardmodle_s1_in_a_write_cycle;
assign wait_for_hardmodle_s1_counter = 0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//hardmodle/s1 enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jtag_uart_avalon_jtag_slave_arbitrator (
// inputs:
clk,
cpu_data_master_address_to_slave,
cpu_data_master_read,
cpu_data_master_waitrequest,
cpu_data_master_write,
cpu_data_master_writedata,
jtag_uart_avalon_jtag_slave_dataavailable,
jtag_uart_avalon_jtag_slave_irq,
jtag_uart_avalon_jtag_slave_readdata,
jtag_uart_avalon_jtag_slave_readyfordata,
jtag_uart_avalon_jtag_slave_waitrequest,
reset_n,
// outputs:
cpu_data_master_granted_jtag_uart_avalon_jtag_slave,
cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave,
cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave,
cpu_data_master_requests_jtag_uart_avalon_jtag_slave,
d1_jtag_uart_avalon_jtag_slave_end_xfer,
jtag_uart_avalon_jtag_slave_address,
jtag_uart_avalon_jtag_slave_chipselect,
jtag_uart_avalon_jtag_slave_dataavailable_from_sa,
jtag_uart_avalon_jtag_slave_irq_from_sa,
jtag_uart_avalon_jtag_slave_read_n,
jtag_uart_avalon_jtag_slave_readdata_from_sa,
jtag_uart_avalon_jtag_slave_readyfordata_from_sa,
jtag_uart_avalon_jtag_slave_reset_n,
jtag_uart_avalon_jtag_slave_waitrequest_from_sa,
jtag_uart_avalon_jtag_slave_write_n,
jtag_uart_avalon_jtag_slave_writedata
)
;
output cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
output cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
output cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
output cpu_data_master_requests_jtag_uart_avalon_jtag_slave;
output d1_jtag_uart_avalon_jtag_slave_end_xfer;
output jtag_uart_avalon_jtag_slave_address;
output jtag_uart_avalon_jtag_slave_chipselect;
output jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
output jtag_uart_avalon_jtag_slave_irq_from_sa;
output jtag_uart_avalon_jtag_slave_read_n;
output [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
output jtag_uart_avalon_jtag_slave_readyfordata_from_sa;
output jtag_uart_avalon_jtag_slave_reset_n;
output jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
output jtag_uart_avalon_jtag_slave_write_n;
output [ 31: 0] jtag_uart_avalon_jtag_slave_writedata;
input clk;
input [ 23: 0] cpu_data_master_address_to_slave;
input cpu_data_master_read;
input cpu_data_master_waitrequest;
input cpu_data_master_write;
input [ 31: 0] cpu_data_master_writedata;
input jtag_uart_avalon_jtag_slave_dataavailable;
input jtag_uart_avalon_jtag_slave_irq;
input [ 31: 0] jtag_uart_avalon_jtag_slave_readdata;
input jtag_uart_avalon_jtag_slave_readyfordata;
input jtag_uart_avalon_jtag_slave_waitrequest;
input reset_n;
wire cpu_data_master_arbiterlock;
wire cpu_data_master_arbiterlock2;
wire cpu_data_master_continuerequest;
wire cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
wire cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
wire cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
wire cpu_data_master_requests_jtag_uart_avalon_jtag_slave;
wire cpu_data_master_saved_grant_jtag_uart_avalon_jtag_slave;
reg d1_jtag_uart_avalon_jtag_slave_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire jtag_uart_avalon_jtag_slave_address;
wire jtag_uart_avalon_jtag_slave_allgrants;
wire jtag_uart_avalon_jtag_slave_allow_new_arb_cycle;
wire jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant;
wire jtag_uart_avalon_jtag_slave_any_continuerequest;
wire jtag_uart_avalon_jtag_slave_arb_counter_enable;
reg [ 2: 0] jtag_uart_avalon_jtag_slave_arb_share_counter;
wire [ 2: 0] jtag_uart_avalon_jtag_slave_arb_share_counter_next_value;
wire [ 2: 0] jtag_uart_avalon_jtag_slave_arb_share_set_values;
wire jtag_uart_avalon_jtag_slave_beginbursttransfer_internal;
wire jtag_uart_avalon_jtag_slave_begins_xfer;
wire jtag_uart_avalon_jtag_slave_chipselect;
wire jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
wire jtag_uart_avalon_jtag_slave_end_xfer;
wire jtag_uart_avalon_jtag_slave_firsttransfer;
wire jtag_uart_avalon_jtag_slave_grant_vector;
wire jtag_uart_avalon_jtag_slave_in_a_read_cycle;
wire jtag_uart_avalon_jtag_slave_in_a_write_cycle;
wire jtag_uart_avalon_jtag_slave_irq_from_sa;
wire jtag_uart_avalon_jtag_slave_master_qreq_vector;
wire jtag_uart_avalon_jtag_slave_non_bursting_master_requests;
wire jtag_uart_avalon_jtag_slave_read_n;
wire [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
wire jtag_uart_avalon_jtag_slave_readyfordata_from_sa;
reg jtag_uart_avalon_jtag_slave_reg_firsttransfer;
wire jtag_uart_avalon_jtag_slave_reset_n;
reg jtag_uart_avalon_jtag_slave_slavearbiterlockenable;
wire jtag_uart_avalon_jtag_slave_slavearbiterlockenable2;
wire jtag_uart_avalon_jtag_slave_unreg_firsttransfer;
wire jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
wire jtag_uart_avalon_jtag_slave_waits_for_read;
wire jtag_uart_avalon_jtag_slave_waits_for_write;
wire jtag_uart_avalon_jtag_slave_write_n;
wire [ 31: 0] jtag_uart_avalon_jtag_slave_writedata;
wire [ 23: 0] shifted_address_to_jtag_uart_avalon_jtag_slave_from_cpu_data_master;
wire wait_for_jtag_uart_avalon_jtag_slave_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~jtag_uart_avalon_jtag_slave_end_xfer;
end
assign jtag_uart_avalon_jtag_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave));
//assign jtag_uart_avalon_jtag_slave_readdata_from_sa = jtag_uart_avalon_jtag_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign jtag_uart_avalon_jtag_slave_readdata_from_sa = jtag_uart_avalon_jtag_slave_readdata;
assign cpu_data_master_requests_jtag_uart_avalon_jtag_slave = ({cpu_data_master_address_to_slave[23 : 3] , 3'b0} == 24'hb04070) & (cpu_data_master_read | cpu_data_master_write);
//assign jtag_uart_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_avalon_jtag_slave_dataavailable so that symbol knows where to group signals which may go to master only, which is an e_assign
assign jtag_uart_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_avalon_jtag_slave_dataavailable;
//assign jtag_uart_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_avalon_jtag_slave_readyfordata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign jtag_uart_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_avalon_jtag_slave_readyfordata;
//assign jtag_uart_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_avalon_jtag_slave_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
assign jtag_uart_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_avalon_jtag_slave_waitrequest;
//jtag_uart_avalon_jtag_slave_arb_share_counter set values, which is an e_mux
assign jtag_uart_avalon_jtag_slave_arb_share_set_values = 1;
//jtag_uart_avalon_jtag_slave_non_bursting_master_requests mux, which is an e_mux
assign jtag_uart_avalon_jtag_slave_non_bursting_master_requests = cpu_data_master_requests_jtag_uart_avalon_jtag_slave;
//jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant mux, which is an e_mux
assign jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant = 0;
//jtag_uart_avalon_jtag_slave_arb_share_counter_next_value assignment, which is an e_assign
assign jtag_uart_avalon_jtag_slave_arb_share_counter_next_value = jtag_uart_avalon_jtag_slave_firsttransfer ? (jtag_uart_avalon_jtag_slave_arb_share_set_values - 1) : |jtag_uart_avalon_jtag_slave_arb_share_counter ? (jtag_uart_avalon_jtag_slave_arb_share_counter - 1) : 0;
//jtag_uart_avalon_jtag_slave_allgrants all slave grants, which is an e_mux
assign jtag_uart_avalon_jtag_slave_allgrants = |jtag_uart_avalon_jtag_slave_grant_vector;
//jtag_uart_avalon_jtag_slave_end_xfer assignment, which is an e_assign
assign jtag_uart_avalon_jtag_slave_end_xfer = ~(jtag_uart_avalon_jtag_slave_waits_for_read | jtag_uart_avalon_jtag_slave_waits_for_write);
//end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave = jtag_uart_avalon_jtag_slave_end_xfer & (~jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//jtag_uart_avalon_jtag_slave_arb_share_counter arbitration counter enable, which is an e_assign
assign jtag_uart_avalon_jtag_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave & jtag_uart_avalon_jtag_slave_allgrants) | (end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave & ~jtag_uart_avalon_jtag_slave_non_bursting_master_requests);
//jtag_uart_avalon_jtag_slave_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
jtag_uart_avalon_jtag_slave_arb_share_counter <= 0;
else if (jtag_uart_avalon_jtag_slave_arb_counter_enable)
jtag_uart_avalon_jtag_slave_arb_share_counter <= jtag_uart_avalon_jtag_slave_arb_share_counter_next_value;
end
//jtag_uart_avalon_jtag_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
jtag_uart_avalon_jtag_slave_slavearbiterlockenable <= 0;
else if ((|jtag_uart_avalon_jtag_slave_master_qreq_vector & end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave) | (end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave & ~jtag_uart_avalon_jtag_slave_non_bursting_master_requests))
jtag_uart_avalon_jtag_slave_slavearbiterlockenable <= |jtag_uart_avalon_jtag_slave_arb_share_counter_next_value;
end
//cpu/data_master jtag_uart/avalon_jtag_slave arbiterlock, which is an e_assign
assign cpu_data_master_arbiterlock = jtag_uart_avalon_jtag_slave_slavearbiterlockenable & cpu_data_master_continuerequest;
//jtag_uart_avalon_jtag_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign jtag_uart_avalon_jtag_slave_slavearbiterlockenable2 = |jtag_uart_avalon_jtag_slave_arb_share_counter_next_value;
//cpu/data_master jtag_uart/avalon_jtag_slave arbiterlock2, which is an e_assign
assign cpu_data_master_arbiterlock2 = jtag_uart_avalon_jtag_slave_slavearbiterlockenable2 & cpu_data_master_continuerequest;
//jtag_uart_avalon_jtag_slave_any_continuerequest at least one master continues requesting, which is an e_assign
assign jtag_uart_avalon_jtag_slave_any_continuerequest = 1;
//cpu_data_master_continuerequest continued request, which is an e_assign
assign cpu_data_master_continuerequest = 1;
assign cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave = cpu_data_master_requests_jtag_uart_avalon_jtag_slave & ~((cpu_data_master_read & (~cpu_data_master_waitrequest)) | ((~cpu_data_master_waitrequest) & cpu_data_master_write));
//jtag_uart_avalon_jtag_slave_writedata mux, which is an e_mux
assign jtag_uart_avalon_jtag_slave_writedata = cpu_data_master_writedata;
//master is always granted when requested
assign cpu_data_master_granted_jtag_uart_avalon_jtag_slave = cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
//cpu/data_master saved-grant jtag_uart/avalon_jtag_slave, which is an e_assign
assign cpu_data_master_saved_grant_jtag_uart_avalon_jtag_slave = cpu_data_master_requests_jtag_uart_avalon_jtag_slave;
//allow new arb cycle for jtag_uart/avalon_jtag_slave, which is an e_assign
assign jtag_uart_avalon_jtag_slave_allow_new_arb_cycle = 1;
//placeholder chosen master
assign jtag_uart_avalon_jtag_slave_grant_vector = 1;
//placeholder vector of master qualified-requests
assign jtag_uart_avalon_jtag_slave_master_qreq_vector = 1;
//jtag_uart_avalon_jtag_slave_reset_n assignment, which is an e_assign
assign jtag_uart_avalon_jtag_slave_reset_n = reset_n;
assign jtag_uart_avalon_jtag_slave_chipselect = cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
//jtag_uart_avalon_jtag_slave_firsttransfer first transaction, which is an e_assign
assign jtag_uart_avalon_jtag_slave_firsttransfer = jtag_uart_avalon_jtag_slave_begins_xfer ? jtag_uart_avalon_jtag_slave_unreg_firsttransfer : jtag_uart_avalon_jtag_slave_reg_firsttransfer;
//jtag_uart_avalon_jtag_slave_unreg_firsttransfer first transaction, which is an e_assign
assign jtag_uart_avalon_jtag_slave_unreg_firsttransfer = ~(jtag_uart_avalon_jtag_slave_slavearbiterlockenable & jtag_uart_avalon_jtag_slave_any_continuerequest);
//jtag_uart_avalon_jtag_slave_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
jtag_uart_avalon_jtag_slave_reg_firsttransfer <= 1'b1;
else if (jtag_uart_avalon_jtag_slave_begins_xfer)
jtag_uart_avalon_jtag_slave_reg_firsttransfer <= jtag_uart_avalon_jtag_slave_unreg_firsttransfer;
end
//jtag_uart_avalon_jtag_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign jtag_uart_avalon_jtag_slave_beginbursttransfer_internal = jtag_uart_avalon_jtag_slave_begins_xfer;
//~jtag_uart_avalon_jtag_slave_read_n assignment, which is an e_mux
assign jtag_uart_avalon_jtag_slave_read_n = ~(cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_read);
//~jtag_uart_avalon_jtag_slave_write_n assignment, which is an e_mux
assign jtag_uart_avalon_jtag_slave_write_n = ~(cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_write);
assign shifted_address_to_jtag_uart_avalon_jtag_slave_from_cpu_data_master = cpu_data_master_address_to_slave;
//jtag_uart_avalon_jtag_slave_address mux, which is an e_mux
assign jtag_uart_avalon_jtag_slave_address = shifted_address_to_jtag_uart_avalon_jtag_slave_from_cpu_data_master >> 2;
//d1_jtag_uart_avalon_jtag_slave_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_jtag_uart_avalon_jtag_slave_end_xfer <= 1;
else
d1_jtag_uart_avalon_jtag_slave_end_xfer <= jtag_uart_avalon_jtag_slave_end_xfer;
end
//jtag_uart_avalon_jtag_slave_waits_for_read in a cycle, which is an e_mux
assign jtag_uart_avalon_jtag_slave_waits_for_read = jtag_uart_avalon_jtag_slave_in_a_read_cycle & jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
//jtag_uart_avalon_jtag_slave_in_a_read_cycle assignment, which is an e_assign
assign jtag_uart_avalon_jtag_slave_in_a_read_cycle = cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = jtag_uart_avalon_jtag_slave_in_a_read_cycle;
//jtag_uart_avalon_jtag_slave_waits_for_write in a cycle, which is an e_mux
assign jtag_uart_avalon_jtag_slave_waits_for_write = jtag_uart_avalon_jtag_slave_in_a_write_cycle & jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
//jtag_uart_avalon_jtag_slave_in_a_write_cycle assignment, which is an e_assign
assign jtag_uart_avalon_jtag_slave_in_a_write_cycle = cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = jtag_uart_avalon_jtag_slave_in_a_write_cycle;
assign wait_for_jtag_uart_avalon_jtag_slave_counter = 0;
//assign jtag_uart_avalon_jtag_slave_irq_from_sa = jtag_uart_avalon_jtag_slave_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
assign jtag_uart_avalon_jtag_slave_irq_from_sa = jtag_uart_avalon_jtag_slave_irq;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//jtag_uart/avalon_jtag_slave enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module kernel_clock_0_in_arbitrator (
// inputs:
clk,
cpu_data_master_address_to_slave,
cpu_data_master_byteenable,
cpu_data_master_read,
cpu_data_master_waitrequest,
cpu_data_master_write,
cpu_data_master_writedata,
kernel_clock_0_in_endofpacket,
kernel_clock_0_in_readdata,
kernel_clock_0_in_waitrequest,
reset_n,
// outputs:
cpu_data_master_granted_kernel_clock_0_in,
cpu_data_master_qualified_request_kernel_clock_0_in,
cpu_data_master_read_data_valid_kernel_clock_0_in,
cpu_data_master_requests_kernel_clock_0_in,
d1_kernel_clock_0_in_end_xfer,
kernel_clock_0_in_address,
kernel_clock_0_in_byteenable,
kernel_clock_0_in_endofpacket_from_sa,
kernel_clock_0_in_nativeaddress,
kernel_clock_0_in_read,
kernel_clock_0_in_readdata_from_sa,
kernel_clock_0_in_reset_n,
kernel_clock_0_in_waitrequest_from_sa,
kernel_clock_0_in_write,
kernel_clock_0_in_writedata
)
;
output cpu_data_master_granted_kernel_clock_0_in;
output cpu_data_master_qualified_request_kernel_clock_0_in;
output cpu_data_master_read_data_valid_kernel_clock_0_in;
output cpu_data_master_requests_kernel_clock_0_in;
output d1_kernel_clock_0_in_end_xfer;
output [ 19: 0] kernel_clock_0_in_address;
output [ 1: 0] kernel_clock_0_in_byteenable;
output kernel_clock_0_in_endofpacket_from_sa;
output [ 18: 0] kernel_clock_0_in_nativeaddress;
output kernel_clock_0_in_read;
output [ 15: 0] kernel_clock_0_in_readdata_from_sa;
output kernel_clock_0_in_reset_n;
output kernel_clock_0_in_waitrequest_from_sa;
output kernel_clock_0_in_write;
output [ 15: 0] kernel_clock_0_in_writedata;
input clk;
input [ 23: 0] cpu_data_master_address_to_slave;
input [ 3: 0] cpu_data_master_byteenable;
input cpu_data_master_read;
input cpu_data_master_waitrequest;
input cpu_data_master_write;
input [ 31: 0] cpu_data_master_writedata;
input kernel_clock_0_in_endofpacket;
input [ 15: 0] kernel_clock_0_in_readdata;
input kernel_clock_0_in_waitrequest;
input reset_n;
wire cpu_data_master_arbiterlock;
wire cpu_data_master_arbiterlock2;
wire cpu_data_master_continuerequest;
wire cpu_data_master_granted_kernel_clock_0_in;
wire cpu_data_master_qualified_request_kernel_clock_0_in;
wire cpu_data_master_read_data_valid_kernel_clock_0_in;
wire cpu_data_master_requests_kernel_clock_0_in;
wire cpu_data_master_saved_grant_kernel_clock_0_in;
reg d1_kernel_clock_0_in_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_kernel_clock_0_in;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 19: 0] kernel_clock_0_in_address;
wire kernel_clock_0_in_allgrants;
wire kernel_clock_0_in_allow_new_arb_cycle;
wire kernel_clock_0_in_any_bursting_master_saved_grant;
wire kernel_clock_0_in_any_continuerequest;
wire kernel_clock_0_in_arb_counter_enable;
reg [ 2: 0] kernel_clock_0_in_arb_share_counter;
wire [ 2: 0] kernel_clock_0_in_arb_share_counter_next_value;
wire [ 2: 0] kernel_clock_0_in_arb_share_set_values;
wire kernel_clock_0_in_beginbursttransfer_internal;
wire kernel_clock_0_in_begins_xfer;
wire [ 1: 0] kernel_clock_0_in_byteenable;
wire kernel_clock_0_in_end_xfer;
wire kernel_clock_0_in_endofpacket_from_sa;
wire kernel_clock_0_in_firsttransfer;
wire kernel_clock_0_in_grant_vector;
wire kernel_clock_0_in_in_a_read_cycle;
wire kernel_clock_0_in_in_a_write_cycle;
wire kernel_clock_0_in_master_qreq_vector;
wire [ 18: 0] kernel_clock_0_in_nativeaddress;
wire kernel_clock_0_in_non_bursting_master_requests;
wire kernel_clock_0_in_read;
wire [ 15: 0] kernel_clock_0_in_readdata_from_sa;
reg kernel_clock_0_in_reg_firsttransfer;
wire kernel_clock_0_in_reset_n;
reg kernel_clock_0_in_slavearbiterlockenable;
wire kernel_clock_0_in_slavearbiterlockenable2;
wire kernel_clock_0_in_unreg_firsttransfer;
wire kernel_clock_0_in_waitrequest_from_sa;
wire kernel_clock_0_in_waits_for_read;
wire kernel_clock_0_in_waits_for_write;
wire kernel_clock_0_in_write;
wire [ 15: 0] kernel_clock_0_in_writedata;
wire [ 23: 0] shifted_address_to_kernel_clock_0_in_from_cpu_data_master;
wire wait_for_kernel_clock_0_in_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~kernel_clock_0_in_end_xfer;
end
assign kernel_clock_0_in_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_kernel_clock_0_in));
//assign kernel_clock_0_in_readdata_from_sa = kernel_clock_0_in_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign kernel_clock_0_in_readdata_from_sa = kernel_clock_0_in_readdata;
assign cpu_data_master_requests_kernel_clock_0_in = ({cpu_data_master_address_to_slave[23 : 21] , 21'b0} == 24'h800000) & (cpu_data_master_read | cpu_data_master_write);
//assign kernel_clock_0_in_waitrequest_from_sa = kernel_clock_0_in_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
assign kernel_clock_0_in_waitrequest_from_sa = kernel_clock_0_in_waitrequest;
//kernel_clock_0_in_arb_share_counter set values, which is an e_mux
assign kernel_clock_0_in_arb_share_set_values = 1;
//kernel_clock_0_in_non_bursting_master_requests mux, which is an e_mux
assign kernel_clock_0_in_non_bursting_master_requests = cpu_data_master_requests_kernel_clock_0_in;
//kernel_clock_0_in_any_bursting_master_saved_grant mux, which is an e_mux
assign kernel_clock_0_in_any_bursting_master_saved_grant = 0;
//kernel_clock_0_in_arb_share_counter_next_value assignment, which is an e_assign
assign kernel_clock_0_in_arb_share_counter_next_value = kernel_clock_0_in_firsttransfer ? (kernel_clock_0_in_arb_share_set_values - 1) : |kernel_clock_0_in_arb_share_counter ? (kernel_clock_0_in_arb_share_counter - 1) : 0;
//kernel_clock_0_in_allgrants all slave grants, which is an e_mux
assign kernel_clock_0_in_allgrants = |kernel_clock_0_in_grant_vector;
//kernel_clock_0_in_end_xfer assignment, which is an e_assign
assign kernel_clock_0_in_end_xfer = ~(kernel_clock_0_in_waits_for_read | kernel_clock_0_in_waits_for_write);
//end_xfer_arb_share_counter_term_kernel_clock_0_in arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_kernel_clock_0_in = kernel_clock_0_in_end_xfer & (~kernel_clock_0_in_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//kernel_clock_0_in_arb_share_counter arbitration counter enable, which is an e_assign
assign kernel_clock_0_in_arb_counter_enable = (end_xfer_arb_share_counter_term_kernel_clock_0_in & kernel_clock_0_in_allgrants) | (end_xfer_arb_share_counter_term_kernel_clock_0_in & ~kernel_clock_0_in_non_bursting_master_requests);
//kernel_clock_0_in_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
kernel_clock_0_in_arb_share_counter <= 0;
else if (kernel_clock_0_in_arb_counter_enable)
kernel_clock_0_in_arb_share_counter <= kernel_clock_0_in_arb_share_counter_next_value;
end
//kernel_clock_0_in_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
kernel_clock_0_in_slavearbiterlockenable <= 0;
else if ((|kernel_clock_0_in_master_qreq_vector & end_xfer_arb_share_counter_term_kernel_clock_0_in) | (end_xfer_arb_share_counter_term_kernel_clock_0_in & ~kernel_clock_0_in_non_bursting_master_requests))
kernel_clock_0_in_slavearbiterlockenable <= |kernel_clock_0_in_arb_share_counter_next_value;
end
//cpu/data_master kernel_clock_0/in arbiterlock, which is an e_assign
assign cpu_data_master_arbiterlock = kernel_clock_0_in_slavearbiterlockenable & cpu_data_master_continuerequest;
//kernel_clock_0_in_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign kernel_clock_0_in_slavearbiterlockenable2 = |kernel_clock_0_in_arb_share_counter_next_value;
//cpu/data_master kernel_clock_0/in arbiterlock2, which is an e_assign
assign cpu_data_master_arbiterlock2 = kernel_clock_0_in_slavearbiterlockenable2 & cpu_data_master_continuerequest;
//kernel_clock_0_in_any_continuerequest at least one master continues requesting, which is an e_assign
assign kernel_clock_0_in_any_continuerequest = 1;
//cpu_data_master_continuerequest continued request, which is an e_assign
assign cpu_data_master_continuerequest = 1;
assign cpu_data_master_qualified_request_kernel_clock_0_in = cpu_data_master_requests_kernel_clock_0_in & ~((cpu_data_master_read & (~cpu_data_master_waitrequest)) | ((~cpu_data_master_waitrequest) & cpu_data_master_write));
//kernel_clock_0_in_writedata mux, which is an e_mux
assign kernel_clock_0_in_writedata = cpu_data_master_writedata;
//assign kernel_clock_0_in_endofpacket_from_sa = kernel_clock_0_in_endofpacket so that symbol knows where to group signals which may go to master only, which is an e_assign
assign kernel_clock_0_in_endofpacket_from_sa = kernel_clock_0_in_endofpacket;
//master is always granted when requested
assign cpu_data_master_granted_kernel_clock_0_in = cpu_data_master_qualified_request_kernel_clock_0_in;
//cpu/data_master saved-grant kernel_clock_0/in, which is an e_assign
assign cpu_data_master_saved_grant_kernel_clock_0_in = cpu_data_master_requests_kernel_clock_0_in;
//allow new arb cycle for kernel_clock_0/in, which is an e_assign
assign kernel_clock_0_in_allow_new_arb_cycle = 1;
//placeholder chosen master
assign kernel_clock_0_in_grant_vector = 1;
//placeholder vector of master qualified-requests
assign kernel_clock_0_in_master_qreq_vector = 1;
//kernel_clock_0_in_reset_n assignment, which is an e_assign
assign kernel_clock_0_in_reset_n = reset_n;
//kernel_clock_0_in_firsttransfer first transaction, which is an e_assign
assign kernel_clock_0_in_firsttransfer = kernel_clock_0_in_begins_xfer ? kernel_clock_0_in_unreg_firsttransfer : kernel_clock_0_in_reg_firsttransfer;
//kernel_clock_0_in_unreg_firsttransfer first transaction, which is an e_assign
assign kernel_clock_0_in_unreg_firsttransfer = ~(kernel_clock_0_in_slavearbiterlockenable & kernel_clock_0_in_any_continuerequest);
//kernel_clock_0_in_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
kernel_clock_0_in_reg_firsttransfer <= 1'b1;
else if (kernel_clock_0_in_begins_xfer)
kernel_clock_0_in_reg_firsttransfer <= kernel_clock_0_in_unreg_firsttransfer;
end
//kernel_clock_0_in_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign kernel_clock_0_in_beginbursttransfer_internal = kernel_clock_0_in_begins_xfer;
//kernel_clock_0_in_read assignment, which is an e_mux
assign kernel_clock_0_in_read = cpu_data_master_granted_kernel_clock_0_in & cpu_data_master_read;
//kernel_clock_0_in_write assignment, which is an e_mux
assign kernel_clock_0_in_write = cpu_data_master_granted_kernel_clock_0_in & cpu_data_master_write;
assign shifted_address_to_kernel_clock_0_in_from_cpu_data_master = cpu_data_master_address_to_slave;
//kernel_clock_0_in_address mux, which is an e_mux
assign kernel_clock_0_in_address = shifted_address_to_kernel_clock_0_in_from_cpu_data_master >> 2;
//slaveid kernel_clock_0_in_nativeaddress nativeaddress mux, which is an e_mux
assign kernel_clock_0_in_nativeaddress = cpu_data_master_address_to_slave >> 2;
//d1_kernel_clock_0_in_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_kernel_clock_0_in_end_xfer <= 1;
else
d1_kernel_clock_0_in_end_xfer <= kernel_clock_0_in_end_xfer;
end
//kernel_clock_0_in_waits_for_read in a cycle, which is an e_mux
assign kernel_clock_0_in_waits_for_read = kernel_clock_0_in_in_a_read_cycle & kernel_clock_0_in_waitrequest_from_sa;
//kernel_clock_0_in_in_a_read_cycle assignment, which is an e_assign
assign kernel_clock_0_in_in_a_read_cycle = cpu_data_master_granted_kernel_clock_0_in & cpu_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = kernel_clock_0_in_in_a_read_cycle;
//kernel_clock_0_in_waits_for_write in a cycle, which is an e_mux
assign kernel_clock_0_in_waits_for_write = kernel_clock_0_in_in_a_write_cycle & kernel_clock_0_in_waitrequest_from_sa;
//kernel_clock_0_in_in_a_write_cycle assignment, which is an e_assign
assign kernel_clock_0_in_in_a_write_cycle = cpu_data_master_granted_kernel_clock_0_in & cpu_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = kernel_clock_0_in_in_a_write_cycle;
assign wait_for_kernel_clock_0_in_counter = 0;
//kernel_clock_0_in_byteenable byte enable port mux, which is an e_mux
assign kernel_clock_0_in_byteenable = (cpu_data_master_granted_kernel_clock_0_in)? cpu_data_master_byteenable :
-1;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//kernel_clock_0/in enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module kernel_clock_0_out_arbitrator (
// inputs:
clk,
d1_vga_0_avalon_slave_0_end_xfer,
kernel_clock_0_out_address,
kernel_clock_0_out_byteenable,
kernel_clock_0_out_granted_vga_0_avalon_slave_0,
kernel_clock_0_out_qualified_request_vga_0_avalon_slave_0,
kernel_clock_0_out_read,
kernel_clock_0_out_read_data_valid_vga_0_avalon_slave_0,
kernel_clock_0_out_requests_vga_0_avalon_slave_0,
kernel_clock_0_out_write,
kernel_clock_0_out_writedata,
reset_n,
vga_0_avalon_slave_0_readdata_from_sa,
vga_0_avalon_slave_0_wait_counter_eq_0,
// outputs:
kernel_clock_0_out_address_to_slave,
kernel_clock_0_out_readdata,
kernel_clock_0_out_reset_n,
kernel_clock_0_out_waitrequest
)
;
output [ 19: 0] kernel_clock_0_out_address_to_slave;
output [ 15: 0] kernel_clock_0_out_readdata;
output kernel_clock_0_out_reset_n;
output kernel_clock_0_out_waitrequest;
input clk;
input d1_vga_0_avalon_slave_0_end_xfer;
input [ 19: 0] kernel_clock_0_out_address;
input [ 1: 0] kernel_clock_0_out_byteenable;
input kernel_clock_0_out_granted_vga_0_avalon_slave_0;
input kernel_clock_0_out_qualified_request_vga_0_avalon_slave_0;
input kernel_clock_0_out_read;
input kernel_clock_0_out_read_data_valid_vga_0_avalon_slave_0;
input kernel_clock_0_out_requests_vga_0_avalon_slave_0;
input kernel_clock_0_out_write;
input [ 15: 0] kernel_clock_0_out_writedata;
input reset_n;
input [ 15: 0] vga_0_avalon_slave_0_readdata_from_sa;
input vga_0_avalon_slave_0_wait_counter_eq_0;
reg active_and_waiting_last_time;
reg [ 19: 0] kernel_clock_0_out_address_last_time;
wire [ 19: 0] kernel_clock_0_out_address_to_slave;
reg [ 1: 0] kernel_clock_0_out_byteenable_last_time;
reg kernel_clock_0_out_read_last_time;
wire [ 15: 0] kernel_clock_0_out_readdata;
wire kernel_clock_0_out_reset_n;
wire kernel_clock_0_out_run;
wire kernel_clock_0_out_waitrequest;
reg kernel_clock_0_out_write_last_time;
reg [ 15: 0] kernel_clock_0_out_writedata_last_time;
wire r_2;
//r_2 master_run cascaded wait assignment, which is an e_assign
assign r_2 = 1 & ((~kernel_clock_0_out_qualified_request_vga_0_avalon_slave_0 | ~kernel_clock_0_out_read | (1 & ~d1_vga_0_avalon_slave_0_end_xfer & kernel_clock_0_out_read))) & ((~kernel_clock_0_out_qualified_request_vga_0_avalon_slave_0 | ~kernel_clock_0_out_write | (1 & ((vga_0_avalon_slave_0_wait_counter_eq_0 & ~d1_vga_0_avalon_slave_0_end_xfer)) & kernel_clock_0_out_write)));
//cascaded wait assignment, which is an e_assign
assign kernel_clock_0_out_run = r_2;
//optimize select-logic by passing only those address bits which matter.
assign kernel_clock_0_out_address_to_slave = kernel_clock_0_out_address;
//kernel_clock_0/out readdata mux, which is an e_mux
assign kernel_clock_0_out_readdata = vga_0_avalon_slave_0_readdata_from_sa;
//actual waitrequest port, which is an e_assign
assign kernel_clock_0_out_waitrequest = ~kernel_clock_0_out_run;
//kernel_clock_0_out_reset_n assignment, which is an e_assign
assign kernel_clock_0_out_reset_n = reset_n;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//kernel_clock_0_out_address check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
kernel_clock_0_out_address_last_time <= 0;
else
kernel_clock_0_out_address_last_time <= kernel_clock_0_out_address;
end
//kernel_clock_0/out waited last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
active_and_waiting_last_time <= 0;
else
active_and_waiting_last_time <= kernel_clock_0_out_waitrequest & (kernel_clock_0_out_read | kernel_clock_0_out_write);
end
//kernel_clock_0_out_address matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (kernel_clock_0_out_address != kernel_clock_0_out_address_last_time))
begin
$write("%0d ns: kernel_clock_0_out_address did not heed wait!!!", $time);
$stop;
end
end
//kernel_clock_0_out_byteenable check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
kernel_clock_0_out_byteenable_last_time <= 0;
else
kernel_clock_0_out_byteenable_last_time <= kernel_clock_0_out_byteenable;
end
//kernel_clock_0_out_byteenable matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (kernel_clock_0_out_byteenable != kernel_clock_0_out_byteenable_last_time))
begin
$write("%0d ns: kernel_clock_0_out_byteenable did not heed wait!!!", $time);
$stop;
end
end
//kernel_clock_0_out_read check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
kernel_clock_0_out_read_last_time <= 0;
else
kernel_clock_0_out_read_last_time <= kernel_clock_0_out_read;
end
//kernel_clock_0_out_read matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (kernel_clock_0_out_read != kernel_clock_0_out_read_last_time))
begin
$write("%0d ns: kernel_clock_0_out_read did not heed wait!!!", $time);
$stop;
end
end
//kernel_clock_0_out_write check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
kernel_clock_0_out_write_last_time <= 0;
else
kernel_clock_0_out_write_last_time <= kernel_clock_0_out_write;
end
//kernel_clock_0_out_write matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (kernel_clock_0_out_write != kernel_clock_0_out_write_last_time))
begin
$write("%0d ns: kernel_clock_0_out_write did not heed wait!!!", $time);
$stop;
end
end
//kernel_clock_0_out_writedata check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
kernel_clock_0_out_writedata_last_time <= 0;
else
kernel_clock_0_out_writedata_last_time <= kernel_clock_0_out_writedata;
end
//kernel_clock_0_out_writedata matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (kernel_clock_0_out_writedata != kernel_clock_0_out_writedata_last_time) & kernel_clock_0_out_write)
begin
$write("%0d ns: kernel_clock_0_out_writedata did not heed wait!!!", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module key_s1_arbitrator (
// inputs:
clk,
cpu_data_master_address_to_slave,
cpu_data_master_read,
cpu_data_master_waitrequest,
cpu_data_master_write,
cpu_data_master_writedata,
key_s1_irq,
key_s1_readdata,
reset_n,
// outputs:
cpu_data_master_granted_key_s1,
cpu_data_master_qualified_request_key_s1,
cpu_data_master_read_data_valid_key_s1,
cpu_data_master_requests_key_s1,
d1_key_s1_end_xfer,
key_s1_address,
key_s1_chipselect,
key_s1_irq_from_sa,
key_s1_readdata_from_sa,
key_s1_reset_n,
key_s1_write_n,
key_s1_writedata
)
;
output cpu_data_master_granted_key_s1;
output cpu_data_master_qualified_request_key_s1;
output cpu_data_master_read_data_valid_key_s1;
output cpu_data_master_requests_key_s1;
output d1_key_s1_end_xfer;
output [ 1: 0] key_s1_address;
output key_s1_chipselect;
output key_s1_irq_from_sa;
output [ 31: 0] key_s1_readdata_from_sa;
output key_s1_reset_n;
output key_s1_write_n;
output [ 31: 0] key_s1_writedata;
input clk;
input [ 23: 0] cpu_data_master_address_to_slave;
input cpu_data_master_read;
input cpu_data_master_waitrequest;
input cpu_data_master_write;
input [ 31: 0] cpu_data_master_writedata;
input key_s1_irq;
input [ 31: 0] key_s1_readdata;
input reset_n;
wire cpu_data_master_arbiterlock;
wire cpu_data_master_arbiterlock2;
wire cpu_data_master_continuerequest;
wire cpu_data_master_granted_key_s1;
wire cpu_data_master_qualified_request_key_s1;
wire cpu_data_master_read_data_valid_key_s1;
wire cpu_data_master_requests_key_s1;
wire cpu_data_master_saved_grant_key_s1;
reg d1_key_s1_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_key_s1;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 1: 0] key_s1_address;
wire key_s1_allgrants;
wire key_s1_allow_new_arb_cycle;
wire key_s1_any_bursting_master_saved_grant;
wire key_s1_any_continuerequest;
wire key_s1_arb_counter_enable;
reg [ 2: 0] key_s1_arb_share_counter;
wire [ 2: 0] key_s1_arb_share_counter_next_value;
wire [ 2: 0] key_s1_arb_share_set_values;
wire key_s1_beginbursttransfer_internal;
wire key_s1_begins_xfer;
wire key_s1_chipselect;
wire key_s1_end_xfer;
wire key_s1_firsttransfer;
wire key_s1_grant_vector;
wire key_s1_in_a_read_cycle;
wire key_s1_in_a_write_cycle;
wire key_s1_irq_from_sa;
wire key_s1_master_qreq_vector;
wire key_s1_non_bursting_master_requests;
wire [ 31: 0] key_s1_readdata_from_sa;
reg key_s1_reg_firsttransfer;
wire key_s1_reset_n;
reg key_s1_slavearbiterlockenable;
wire key_s1_slavearbiterlockenable2;
wire key_s1_unreg_firsttransfer;
wire key_s1_waits_for_read;
wire key_s1_waits_for_write;
wire key_s1_write_n;
wire [ 31: 0] key_s1_writedata;
wire [ 23: 0] shifted_address_to_key_s1_from_cpu_data_master;
wire wait_for_key_s1_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~key_s1_end_xfer;
end
assign key_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_key_s1));
//assign key_s1_readdata_from_sa = key_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign key_s1_readdata_from_sa = key_s1_readdata;
assign cpu_data_master_requests_key_s1 = ({cpu_data_master_address_to_slave[23 : 4] , 4'b0} == 24'hb04020) & (cpu_data_master_read | cpu_data_master_write);
//key_s1_arb_share_counter set values, which is an e_mux
assign key_s1_arb_share_set_values = 1;
//key_s1_non_bursting_master_requests mux, which is an e_mux
assign key_s1_non_bursting_master_requests = cpu_data_master_requests_key_s1;
//key_s1_any_bursting_master_saved_grant mux, which is an e_mux
assign key_s1_any_bursting_master_saved_grant = 0;
//key_s1_arb_share_counter_next_value assignment, which is an e_assign
assign key_s1_arb_share_counter_next_value = key_s1_firsttransfer ? (key_s1_arb_share_set_values - 1) : |key_s1_arb_share_counter ? (key_s1_arb_share_counter - 1) : 0;
//key_s1_allgrants all slave grants, which is an e_mux
assign key_s1_allgrants = |key_s1_grant_vector;
//key_s1_end_xfer assignment, which is an e_assign
assign key_s1_end_xfer = ~(key_s1_waits_for_read | key_s1_waits_for_write);
//end_xfer_arb_share_counter_term_key_s1 arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_key_s1 = key_s1_end_xfer & (~key_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//key_s1_arb_share_counter arbitration counter enable, which is an e_assign
assign key_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_key_s1 & key_s1_allgrants) | (end_xfer_arb_share_counter_term_key_s1 & ~key_s1_non_bursting_master_requests);
//key_s1_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
key_s1_arb_share_counter <= 0;
else if (key_s1_arb_counter_enable)
key_s1_arb_share_counter <= key_s1_arb_share_counter_next_value;
end
//key_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
key_s1_slavearbiterlockenable <= 0;
else if ((|key_s1_master_qreq_vector & end_xfer_arb_share_counter_term_key_s1) | (end_xfer_arb_share_counter_term_key_s1 & ~key_s1_non_bursting_master_requests))
key_s1_slavearbiterlockenable <= |key_s1_arb_share_counter_next_value;
end
//cpu/data_master key/s1 arbiterlock, which is an e_assign
assign cpu_data_master_arbiterlock = key_s1_slavearbiterlockenable & cpu_data_master_continuerequest;
//key_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign key_s1_slavearbiterlockenable2 = |key_s1_arb_share_counter_next_value;
//cpu/data_master key/s1 arbiterlock2, which is an e_assign
assign cpu_data_master_arbiterlock2 = key_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;
//key_s1_any_continuerequest at least one master continues requesting, which is an e_assign
assign key_s1_any_continuerequest = 1;
//cpu_data_master_continuerequest continued request, which is an e_assign
assign cpu_data_master_continuerequest = 1;
assign cpu_data_master_qualified_request_key_s1 = cpu_data_master_requests_key_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
//key_s1_writedata mux, which is an e_mux
assign key_s1_writedata = cpu_data_master_writedata;
//master is always granted when requested
assign cpu_data_master_granted_key_s1 = cpu_data_master_qualified_request_key_s1;
//cpu/data_master saved-grant key/s1, which is an e_assign
assign cpu_data_master_saved_grant_key_s1 = cpu_data_master_requests_key_s1;
//allow new arb cycle for key/s1, which is an e_assign
assign key_s1_allow_new_arb_cycle = 1;
//placeholder chosen master
assign key_s1_grant_vector = 1;
//placeholder vector of master qualified-requests
assign key_s1_master_qreq_vector = 1;
//key_s1_reset_n assignment, which is an e_assign
assign key_s1_reset_n = reset_n;
assign key_s1_chipselect = cpu_data_master_granted_key_s1;
//key_s1_firsttransfer first transaction, which is an e_assign
assign key_s1_firsttransfer = key_s1_begins_xfer ? key_s1_unreg_firsttransfer : key_s1_reg_firsttransfer;
//key_s1_unreg_firsttransfer first transaction, which is an e_assign
assign key_s1_unreg_firsttransfer = ~(key_s1_slavearbiterlockenable & key_s1_any_continuerequest);
//key_s1_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
key_s1_reg_firsttransfer <= 1'b1;
else if (key_s1_begins_xfer)
key_s1_reg_firsttransfer <= key_s1_unreg_firsttransfer;
end
//key_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign key_s1_beginbursttransfer_internal = key_s1_begins_xfer;
//~key_s1_write_n assignment, which is an e_mux
assign key_s1_write_n = ~(cpu_data_master_granted_key_s1 & cpu_data_master_write);
assign shifted_address_to_key_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
//key_s1_address mux, which is an e_mux
assign key_s1_address = shifted_address_to_key_s1_from_cpu_data_master >> 2;
//d1_key_s1_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_key_s1_end_xfer <= 1;
else
d1_key_s1_end_xfer <= key_s1_end_xfer;
end
//key_s1_waits_for_read in a cycle, which is an e_mux
assign key_s1_waits_for_read = key_s1_in_a_read_cycle & key_s1_begins_xfer;
//key_s1_in_a_read_cycle assignment, which is an e_assign
assign key_s1_in_a_read_cycle = cpu_data_master_granted_key_s1 & cpu_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = key_s1_in_a_read_cycle;
//key_s1_waits_for_write in a cycle, which is an e_mux
assign key_s1_waits_for_write = key_s1_in_a_write_cycle & 0;
//key_s1_in_a_write_cycle assignment, which is an e_assign
assign key_s1_in_a_write_cycle = cpu_data_master_granted_key_s1 & cpu_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = key_s1_in_a_write_cycle;
assign wait_for_key_s1_counter = 0;
//assign key_s1_irq_from_sa = key_s1_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
assign key_s1_irq_from_sa = key_s1_irq;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//key/s1 enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lcd_0_control_slave_arbitrator (
// inputs:
clk,
cpu_data_master_address_to_slave,
cpu_data_master_byteenable,
cpu_data_master_read,
cpu_data_master_write,
cpu_data_master_writedata,
lcd_0_control_slave_readdata,
reset_n,
// outputs:
cpu_data_master_granted_lcd_0_control_slave,
cpu_data_master_qualified_request_lcd_0_control_slave,
cpu_data_master_read_data_valid_lcd_0_control_slave,
cpu_data_master_requests_lcd_0_control_slave,
d1_lcd_0_control_slave_end_xfer,
lcd_0_control_slave_address,
lcd_0_control_slave_begintransfer,
lcd_0_control_slave_read,
lcd_0_control_slave_readdata_from_sa,
lcd_0_control_slave_reset_n,
lcd_0_control_slave_wait_counter_eq_0,
lcd_0_control_slave_wait_counter_eq_1,
lcd_0_control_slave_write,
lcd_0_control_slave_writedata
)
;
output cpu_data_master_granted_lcd_0_control_slave;
output cpu_data_master_qualified_request_lcd_0_control_slave;
output cpu_data_master_read_data_valid_lcd_0_control_slave;
output cpu_data_master_requests_lcd_0_control_slave;
output d1_lcd_0_control_slave_end_xfer;
output [ 1: 0] lcd_0_control_slave_address;
output lcd_0_control_slave_begintransfer;
output lcd_0_control_slave_read;
output [ 7: 0] lcd_0_control_slave_readdata_from_sa;
output lcd_0_control_slave_reset_n;
output lcd_0_control_slave_wait_counter_eq_0;
output lcd_0_control_slave_wait_counter_eq_1;
output lcd_0_control_slave_write;
output [ 7: 0] lcd_0_control_slave_writedata;
input clk;
input [ 23: 0] cpu_data_master_address_to_slave;
input [ 3: 0] cpu_data_master_byteenable;
input cpu_data_master_read;
input cpu_data_master_write;
input [ 31: 0] cpu_data_master_writedata;
input [ 7: 0] lcd_0_control_slave_readdata;
input reset_n;
wire cpu_data_master_arbiterlock;
wire cpu_data_master_arbiterlock2;
wire cpu_data_master_continuerequest;
wire cpu_data_master_granted_lcd_0_control_slave;
wire cpu_data_master_qualified_request_lcd_0_control_slave;
wire cpu_data_master_read_data_valid_lcd_0_control_slave;
wire cpu_data_master_requests_lcd_0_control_slave;
wire cpu_data_master_saved_grant_lcd_0_control_slave;
reg d1_lcd_0_control_slave_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_lcd_0_control_slave;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 1: 0] lcd_0_control_slave_address;
wire lcd_0_control_slave_allgrants;
wire lcd_0_control_slave_allow_new_arb_cycle;
wire lcd_0_control_slave_any_bursting_master_saved_grant;
wire lcd_0_control_slave_any_continuerequest;
wire lcd_0_control_slave_arb_counter_enable;
reg [ 2: 0] lcd_0_control_slave_arb_share_counter;
wire [ 2: 0] lcd_0_control_slave_arb_share_counter_next_value;
wire [ 2: 0] lcd_0_control_slave_arb_share_set_values;
wire lcd_0_control_slave_beginbursttransfer_internal;
wire lcd_0_control_slave_begins_xfer;
wire lcd_0_control_slave_begintransfer;
wire [ 5: 0] lcd_0_control_slave_counter_load_value;
wire lcd_0_control_slave_end_xfer;
wire lcd_0_control_slave_firsttransfer;
wire lcd_0_control_slave_grant_vector;
wire lcd_0_control_slave_in_a_read_cycle;
wire lcd_0_control_slave_in_a_write_cycle;
wire lcd_0_control_slave_master_qreq_vector;
wire lcd_0_control_slave_non_bursting_master_requests;
wire lcd_0_control_slave_pretend_byte_enable;
wire lcd_0_control_slave_read;
wire [ 7: 0] lcd_0_control_slave_readdata_from_sa;
reg lcd_0_control_slave_reg_firsttransfer;
wire lcd_0_control_slave_reset_n;
reg lcd_0_control_slave_slavearbiterlockenable;
wire lcd_0_control_slave_slavearbiterlockenable2;
wire lcd_0_control_slave_unreg_firsttransfer;
reg [ 5: 0] lcd_0_control_slave_wait_counter;
wire lcd_0_control_slave_wait_counter_eq_0;
wire lcd_0_control_slave_wait_counter_eq_1;
wire lcd_0_control_slave_waits_for_read;
wire lcd_0_control_slave_waits_for_write;
wire lcd_0_control_slave_write;
wire [ 7: 0] lcd_0_control_slave_writedata;
wire [ 23: 0] shifted_address_to_lcd_0_control_slave_from_cpu_data_master;
wire wait_for_lcd_0_control_slave_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~lcd_0_control_slave_end_xfer;
end
assign lcd_0_control_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_lcd_0_control_slave));
//assign lcd_0_control_slave_readdata_from_sa = lcd_0_control_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign lcd_0_control_slave_readdata_from_sa = lcd_0_control_slave_readdata;
assign cpu_data_master_requests_lcd_0_control_slave = ({cpu_data_master_address_to_slave[23 : 4] , 4'b0} == 24'hb04040) & (cpu_data_master_read | cpu_data_master_write);
//lcd_0_control_slave_arb_share_counter set values, which is an e_mux
assign lcd_0_control_slave_arb_share_set_values = 1;
//lcd_0_control_slave_non_bursting_master_requests mux, which is an e_mux
assign lcd_0_control_slave_non_bursting_master_requests = cpu_data_master_requests_lcd_0_control_slave;
//lcd_0_control_slave_any_bursting_master_saved_grant mux, which is an e_mux
assign lcd_0_control_slave_any_bursting_master_saved_grant = 0;
//lcd_0_control_slave_arb_share_counter_next_value assignment, which is an e_assign
assign lcd_0_control_slave_arb_share_counter_next_value = lcd_0_control_slave_firsttransfer ? (lcd_0_control_slave_arb_share_set_values - 1) : |lcd_0_control_slave_arb_share_counter ? (lcd_0_control_slave_arb_share_counter - 1) : 0;
//lcd_0_control_slave_allgrants all slave grants, which is an e_mux
assign lcd_0_control_slave_allgrants = |lcd_0_control_slave_grant_vector;
//lcd_0_control_slave_end_xfer assignment, which is an e_assign
assign lcd_0_control_slave_end_xfer = ~(lcd_0_control_slave_waits_for_read | lcd_0_control_slave_waits_for_write);
//end_xfer_arb_share_counter_term_lcd_0_control_slave arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_lcd_0_control_slave = lcd_0_control_slave_end_xfer & (~lcd_0_control_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//lcd_0_control_slave_arb_share_counter arbitration counter enable, which is an e_assign
assign lcd_0_control_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_lcd_0_control_slave & lcd_0_control_slave_allgrants) | (end_xfer_arb_share_counter_term_lcd_0_control_slave & ~lcd_0_control_slave_non_bursting_master_requests);
//lcd_0_control_slave_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
lcd_0_control_slave_arb_share_counter <= 0;
else if (lcd_0_control_slave_arb_counter_enable)
lcd_0_control_slave_arb_share_counter <= lcd_0_control_slave_arb_share_counter_next_value;
end
//lcd_0_control_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
lcd_0_control_slave_slavearbiterlockenable <= 0;
else if ((|lcd_0_control_slave_master_qreq_vector & end_xfer_arb_share_counter_term_lcd_0_control_slave) | (end_xfer_arb_share_counter_term_lcd_0_control_slave & ~lcd_0_control_slave_non_bursting_master_requests))
lcd_0_control_slave_slavearbiterlockenable <= |lcd_0_control_slave_arb_share_counter_next_value;
end
//cpu/data_master lcd_0/control_slave arbiterlock, which is an e_assign
assign cpu_data_master_arbiterlock = lcd_0_control_slave_slavearbiterlockenable & cpu_data_master_continuerequest;
//lcd_0_control_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign lcd_0_control_slave_slavearbiterlockenable2 = |lcd_0_control_slave_arb_share_counter_next_value;
//cpu/data_master lcd_0/control_slave arbiterlock2, which is an e_assign
assign cpu_data_master_arbiterlock2 = lcd_0_control_slave_slavearbiterlockenable2 & cpu_data_master_continuerequest;
//lcd_0_control_slave_any_continuerequest at least one master continues requesting, which is an e_assign
assign lcd_0_control_slave_any_continuerequest = 1;
//cpu_data_master_continuerequest continued request, which is an e_assign
assign cpu_data_master_continuerequest = 1;
assign cpu_data_master_qualified_request_lcd_0_control_slave = cpu_data_master_requests_lcd_0_control_slave;
//lcd_0_control_slave_writedata mux, which is an e_mux
assign lcd_0_control_slave_writedata = cpu_data_master_writedata;
//master is always granted when requested
assign cpu_data_master_granted_lcd_0_control_slave = cpu_data_master_qualified_request_lcd_0_control_slave;
//cpu/data_master saved-grant lcd_0/control_slave, which is an e_assign
assign cpu_data_master_saved_grant_lcd_0_control_slave = cpu_data_master_requests_lcd_0_control_slave;
//allow new arb cycle for lcd_0/control_slave, which is an e_assign
assign lcd_0_control_slave_allow_new_arb_cycle = 1;
//placeholder chosen master
assign lcd_0_control_slave_grant_vector = 1;
//placeholder vector of master qualified-requests
assign lcd_0_control_slave_master_qreq_vector = 1;
assign lcd_0_control_slave_begintransfer = lcd_0_control_slave_begins_xfer;
//lcd_0_control_slave_reset_n assignment, which is an e_assign
assign lcd_0_control_slave_reset_n = reset_n;
//lcd_0_control_slave_firsttransfer first transaction, which is an e_assign
assign lcd_0_control_slave_firsttransfer = lcd_0_control_slave_begins_xfer ? lcd_0_control_slave_unreg_firsttransfer : lcd_0_control_slave_reg_firsttransfer;
//lcd_0_control_slave_unreg_firsttransfer first transaction, which is an e_assign
assign lcd_0_control_slave_unreg_firsttransfer = ~(lcd_0_control_slave_slavearbiterlockenable & lcd_0_control_slave_any_continuerequest);
//lcd_0_control_slave_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
lcd_0_control_slave_reg_firsttransfer <= 1'b1;
else if (lcd_0_control_slave_begins_xfer)
lcd_0_control_slave_reg_firsttransfer <= lcd_0_control_slave_unreg_firsttransfer;
end
//lcd_0_control_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign lcd_0_control_slave_beginbursttransfer_internal = lcd_0_control_slave_begins_xfer;
//lcd_0_control_slave_read assignment, which is an e_mux
assign lcd_0_control_slave_read = ((cpu_data_master_granted_lcd_0_control_slave & cpu_data_master_read))& ~lcd_0_control_slave_begins_xfer & (lcd_0_control_slave_wait_counter < 13);
//lcd_0_control_slave_write assignment, which is an e_mux
assign lcd_0_control_slave_write = ((cpu_data_master_granted_lcd_0_control_slave & cpu_data_master_write)) & ~lcd_0_control_slave_begins_xfer & (lcd_0_control_slave_wait_counter >= 13) & (lcd_0_control_slave_wait_counter < 26) & lcd_0_control_slave_pretend_byte_enable;
assign shifted_address_to_lcd_0_control_slave_from_cpu_data_master = cpu_data_master_address_to_slave;
//lcd_0_control_slave_address mux, which is an e_mux
assign lcd_0_control_slave_address = shifted_address_to_lcd_0_control_slave_from_cpu_data_master >> 2;
//d1_lcd_0_control_slave_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_lcd_0_control_slave_end_xfer <= 1;
else
d1_lcd_0_control_slave_end_xfer <= lcd_0_control_slave_end_xfer;
end
//lcd_0_control_slave_wait_counter_eq_1 assignment, which is an e_assign
assign lcd_0_control_slave_wait_counter_eq_1 = lcd_0_control_slave_wait_counter == 1;
//lcd_0_control_slave_waits_for_read in a cycle, which is an e_mux
assign lcd_0_control_slave_waits_for_read = lcd_0_control_slave_in_a_read_cycle & wait_for_lcd_0_control_slave_counter;
//lcd_0_control_slave_in_a_read_cycle assignment, which is an e_assign
assign lcd_0_control_slave_in_a_read_cycle = cpu_data_master_granted_lcd_0_control_slave & cpu_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = lcd_0_control_slave_in_a_read_cycle;
//lcd_0_control_slave_waits_for_write in a cycle, which is an e_mux
assign lcd_0_control_slave_waits_for_write = lcd_0_control_slave_in_a_write_cycle & wait_for_lcd_0_control_slave_counter;
//lcd_0_control_slave_in_a_write_cycle assignment, which is an e_assign
assign lcd_0_control_slave_in_a_write_cycle = cpu_data_master_granted_lcd_0_control_slave & cpu_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = lcd_0_control_slave_in_a_write_cycle;
assign lcd_0_control_slave_wait_counter_eq_0 = lcd_0_control_slave_wait_counter == 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
lcd_0_control_slave_wait_counter <= 0;
else
lcd_0_control_slave_wait_counter <= lcd_0_control_slave_counter_load_value;
end
assign lcd_0_control_slave_counter_load_value = ((lcd_0_control_slave_in_a_read_cycle & lcd_0_control_slave_begins_xfer))? 24 :
((lcd_0_control_slave_in_a_write_cycle & lcd_0_control_slave_begins_xfer))? 37 :
(~lcd_0_control_slave_wait_counter_eq_0)? lcd_0_control_slave_wait_counter - 1 :
0;
assign wait_for_lcd_0_control_slave_counter = lcd_0_control_slave_begins_xfer | ~lcd_0_control_slave_wait_counter_eq_0;
//lcd_0_control_slave_pretend_byte_enable byte enable port mux, which is an e_mux
assign lcd_0_control_slave_pretend_byte_enable = (cpu_data_master_granted_lcd_0_control_slave)? cpu_data_master_byteenable :
-1;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//lcd_0/control_slave enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module onchip_memory_s1_arbitrator (
// inputs:
clk,
cpu_data_master_address_to_slave,
cpu_data_master_byteenable,
cpu_data_master_read,
cpu_data_master_waitrequest,
cpu_data_master_write,
cpu_data_master_writedata,
cpu_instruction_master_address_to_slave,
cpu_instruction_master_latency_counter,
cpu_instruction_master_read,
onchip_memory_s1_readdata,
reset_n,
// outputs:
cpu_data_master_granted_onchip_memory_s1,
cpu_data_master_qualified_request_onchip_memory_s1,
cpu_data_master_read_data_valid_onchip_memory_s1,
cpu_data_master_requests_onchip_memory_s1,
cpu_instruction_master_granted_onchip_memory_s1,
cpu_instruction_master_qualified_request_onchip_memory_s1,
cpu_instruction_master_read_data_valid_onchip_memory_s1,
cpu_instruction_master_requests_onchip_memory_s1,
d1_onchip_memory_s1_end_xfer,
onchip_memory_s1_address,
onchip_memory_s1_byteenable,
onchip_memory_s1_chipselect,
onchip_memory_s1_clken,
onchip_memory_s1_readdata_from_sa,
onchip_memory_s1_reset,
onchip_memory_s1_write,
onchip_memory_s1_writedata,
registered_cpu_data_master_read_data_valid_onchip_memory_s1
)
;
output cpu_data_master_granted_onchip_memory_s1;
output cpu_data_master_qualified_request_onchip_memory_s1;
output cpu_data_master_read_data_valid_onchip_memory_s1;
output cpu_data_master_requests_onchip_memory_s1;
output cpu_instruction_master_granted_onchip_memory_s1;
output cpu_instruction_master_qualified_request_onchip_memory_s1;
output cpu_instruction_master_read_data_valid_onchip_memory_s1;
output cpu_instruction_master_requests_onchip_memory_s1;
output d1_onchip_memory_s1_end_xfer;
output [ 9: 0] onchip_memory_s1_address;
output [ 3: 0] onchip_memory_s1_byteenable;
output onchip_memory_s1_chipselect;
output onchip_memory_s1_clken;
output [ 31: 0] onchip_memory_s1_readdata_from_sa;
output onchip_memory_s1_reset;
output onchip_memory_s1_write;
output [ 31: 0] onchip_memory_s1_writedata;
output registered_cpu_data_master_read_data_valid_onchip_memory_s1;
input clk;
input [ 23: 0] cpu_data_master_address_to_slave;
input [ 3: 0] cpu_data_master_byteenable;
input cpu_data_master_read;
input cpu_data_master_waitrequest;
input cpu_data_master_write;
input [ 31: 0] cpu_data_master_writedata;
input [ 23: 0] cpu_instruction_master_address_to_slave;
input [ 1: 0] cpu_instruction_master_latency_counter;
input cpu_instruction_master_read;
input [ 31: 0] onchip_memory_s1_readdata;
input reset_n;
wire cpu_data_master_arbiterlock;
wire cpu_data_master_arbiterlock2;
wire cpu_data_master_continuerequest;
wire cpu_data_master_granted_onchip_memory_s1;
wire cpu_data_master_qualified_request_onchip_memory_s1;
wire cpu_data_master_read_data_valid_onchip_memory_s1;
reg cpu_data_master_read_data_valid_onchip_memory_s1_shift_register;
wire cpu_data_master_read_data_valid_onchip_memory_s1_shift_register_in;
wire cpu_data_master_requests_onchip_memory_s1;
wire cpu_data_master_saved_grant_onchip_memory_s1;
wire cpu_instruction_master_arbiterlock;
wire cpu_instruction_master_arbiterlock2;
wire cpu_instruction_master_continuerequest;
wire cpu_instruction_master_granted_onchip_memory_s1;
wire cpu_instruction_master_qualified_request_onchip_memory_s1;
wire cpu_instruction_master_read_data_valid_onchip_memory_s1;
reg cpu_instruction_master_read_data_valid_onchip_memory_s1_shift_register;
wire cpu_instruction_master_read_data_valid_onchip_memory_s1_shift_register_in;
wire cpu_instruction_master_requests_onchip_memory_s1;
wire cpu_instruction_master_saved_grant_onchip_memory_s1;
reg d1_onchip_memory_s1_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_onchip_memory_s1;
wire in_a_read_cycle;
wire in_a_write_cycle;
reg last_cycle_cpu_data_master_granted_slave_onchip_memory_s1;
reg last_cycle_cpu_instruction_master_granted_slave_onchip_memory_s1;
wire [ 9: 0] onchip_memory_s1_address;
wire onchip_memory_s1_allgrants;
wire onchip_memory_s1_allow_new_arb_cycle;
wire onchip_memory_s1_any_bursting_master_saved_grant;
wire onchip_memory_s1_any_continuerequest;
reg [ 1: 0] onchip_memory_s1_arb_addend;
wire onchip_memory_s1_arb_counter_enable;
reg [ 2: 0] onchip_memory_s1_arb_share_counter;
wire [ 2: 0] onchip_memory_s1_arb_share_counter_next_value;
wire [ 2: 0] onchip_memory_s1_arb_share_set_values;
wire [ 1: 0] onchip_memory_s1_arb_winner;
wire onchip_memory_s1_arbitration_holdoff_internal;
wire onchip_memory_s1_beginbursttransfer_internal;
wire onchip_memory_s1_begins_xfer;
wire [ 3: 0] onchip_memory_s1_byteenable;
wire onchip_memory_s1_chipselect;
wire [ 3: 0] onchip_memory_s1_chosen_master_double_vector;
wire [ 1: 0] onchip_memory_s1_chosen_master_rot_left;
wire onchip_memory_s1_clken;
wire onchip_memory_s1_end_xfer;
wire onchip_memory_s1_firsttransfer;
wire [ 1: 0] onchip_memory_s1_grant_vector;
wire onchip_memory_s1_in_a_read_cycle;
wire onchip_memory_s1_in_a_write_cycle;
wire [ 1: 0] onchip_memory_s1_master_qreq_vector;
wire onchip_memory_s1_non_bursting_master_requests;
wire [ 31: 0] onchip_memory_s1_readdata_from_sa;
reg onchip_memory_s1_reg_firsttransfer;
wire onchip_memory_s1_reset;
reg [ 1: 0] onchip_memory_s1_saved_chosen_master_vector;
reg onchip_memory_s1_slavearbiterlockenable;
wire onchip_memory_s1_slavearbiterlockenable2;
wire onchip_memory_s1_unreg_firsttransfer;
wire onchip_memory_s1_waits_for_read;
wire onchip_memory_s1_waits_for_write;
wire onchip_memory_s1_write;
wire [ 31: 0] onchip_memory_s1_writedata;
wire p1_cpu_data_master_read_data_valid_onchip_memory_s1_shift_register;
wire p1_cpu_instruction_master_read_data_valid_onchip_memory_s1_shift_register;
wire registered_cpu_data_master_read_data_valid_onchip_memory_s1;
wire [ 23: 0] shifted_address_to_onchip_memory_s1_from_cpu_data_master;
wire [ 23: 0] shifted_address_to_onchip_memory_s1_from_cpu_instruction_master;
wire wait_for_onchip_memory_s1_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~onchip_memory_s1_end_xfer;
end
assign onchip_memory_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_onchip_memory_s1 | cpu_instruction_master_qualified_request_onchip_memory_s1));
//assign onchip_memory_s1_readdata_from_sa = onchip_memory_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign onchip_memory_s1_readdata_from_sa = onchip_memory_s1_readdata;
assign cpu_data_master_requests_onchip_memory_s1 = ({cpu_data_master_address_to_slave[23 : 12] , 12'b0} == 24'hb01000) & (cpu_data_master_read | cpu_data_master_write);
//registered rdv signal_name registered_cpu_data_master_read_data_valid_onchip_memory_s1 assignment, which is an e_assign
assign registered_cpu_data_master_read_data_valid_onchip_memory_s1 = cpu_data_master_read_data_valid_onchip_memory_s1_shift_register_in;
//onchip_memory_s1_arb_share_counter set values, which is an e_mux
assign onchip_memory_s1_arb_share_set_values = 1;
//onchip_memory_s1_non_bursting_master_requests mux, which is an e_mux
assign onchip_memory_s1_non_bursting_master_requests = cpu_data_master_requests_onchip_memory_s1 |
cpu_instruction_master_requests_onchip_memory_s1 |
cpu_data_master_requests_onchip_memory_s1 |
cpu_instruction_master_requests_onchip_memory_s1;
//onchip_memory_s1_any_bursting_master_saved_grant mux, which is an e_mux
assign onchip_memory_s1_any_bursting_master_saved_grant = 0;
//onchip_memory_s1_arb_share_counter_next_value assignment, which is an e_assign
assign onchip_memory_s1_arb_share_counter_next_value = onchip_memory_s1_firsttransfer ? (onchip_memory_s1_arb_share_set_values - 1) : |onchip_memory_s1_arb_share_counter ? (onchip_memory_s1_arb_share_counter - 1) : 0;
//onchip_memory_s1_allgrants all slave grants, which is an e_mux
assign onchip_memory_s1_allgrants = (|onchip_memory_s1_grant_vector) |
(|onchip_memory_s1_grant_vector) |
(|onchip_memory_s1_grant_vector) |
(|onchip_memory_s1_grant_vector);
//onchip_memory_s1_end_xfer assignment, which is an e_assign
assign onchip_memory_s1_end_xfer = ~(onchip_memory_s1_waits_for_read | onchip_memory_s1_waits_for_write);
//end_xfer_arb_share_counter_term_onchip_memory_s1 arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_onchip_memory_s1 = onchip_memory_s1_end_xfer & (~onchip_memory_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//onchip_memory_s1_arb_share_counter arbitration counter enable, which is an e_assign
assign onchip_memory_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_onchip_memory_s1 & onchip_memory_s1_allgrants) | (end_xfer_arb_share_counter_term_onchip_memory_s1 & ~onchip_memory_s1_non_bursting_master_requests);
//onchip_memory_s1_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
onchip_memory_s1_arb_share_counter <= 0;
else if (onchip_memory_s1_arb_counter_enable)
onchip_memory_s1_arb_share_counter <= onchip_memory_s1_arb_share_counter_next_value;
end
//onchip_memory_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
onchip_memory_s1_slavearbiterlockenable <= 0;
else if ((|onchip_memory_s1_master_qreq_vector & end_xfer_arb_share_counter_term_onchip_memory_s1) | (end_xfer_arb_share_counter_term_onchip_memory_s1 & ~onchip_memory_s1_non_bursting_master_requests))
onchip_memory_s1_slavearbiterlockenable <= |onchip_memory_s1_arb_share_counter_next_value;
end
//cpu/data_master onchip_memory/s1 arbiterlock, which is an e_assign
assign cpu_data_master_arbiterlock = onchip_memory_s1_slavearbiterlockenable & cpu_data_master_continuerequest;
//onchip_memory_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign onchip_memory_s1_slavearbiterlockenable2 = |onchip_memory_s1_arb_share_counter_next_value;
//cpu/data_master onchip_memory/s1 arbiterlock2, which is an e_assign
assign cpu_data_master_arbiterlock2 = onchip_memory_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;
//cpu/instruction_master onchip_memory/s1 arbiterlock, which is an e_assign
assign cpu_instruction_master_arbiterlock = onchip_memory_s1_slavearbiterlockenable & cpu_instruction_master_continuerequest;
//cpu/instruction_master onchip_memory/s1 arbiterlock2, which is an e_assign
assign cpu_instruction_master_arbiterlock2 = onchip_memory_s1_slavearbiterlockenable2 & cpu_instruction_master_continuerequest;
//cpu/instruction_master granted onchip_memory/s1 last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_instruction_master_granted_slave_onchip_memory_s1 <= 0;
else
last_cycle_cpu_instruction_master_granted_slave_onchip_memory_s1 <= cpu_instruction_master_saved_grant_onchip_memory_s1 ? 1 : (onchip_memory_s1_arbitration_holdoff_internal | ~cpu_instruction_master_requests_onchip_memory_s1) ? 0 : last_cycle_cpu_instruction_master_granted_slave_onchip_memory_s1;
end
//cpu_instruction_master_continuerequest continued request, which is an e_mux
assign cpu_instruction_master_continuerequest = last_cycle_cpu_instruction_master_granted_slave_onchip_memory_s1 & cpu_instruction_master_requests_onchip_memory_s1;
//onchip_memory_s1_any_continuerequest at least one master continues requesting, which is an e_mux
assign onchip_memory_s1_any_continuerequest = cpu_instruction_master_continuerequest |
cpu_data_master_continuerequest;
assign cpu_data_master_qualified_request_onchip_memory_s1 = cpu_data_master_requests_onchip_memory_s1 & ~((cpu_data_master_read & ((|cpu_data_master_read_data_valid_onchip_memory_s1_shift_register))) | ((~cpu_data_master_waitrequest) & cpu_data_master_write) | cpu_instruction_master_arbiterlock);
//cpu_data_master_read_data_valid_onchip_memory_s1_shift_register_in mux for readlatency shift register, which is an e_mux
assign cpu_data_master_read_data_valid_onchip_memory_s1_shift_register_in = cpu_data_master_granted_onchip_memory_s1 & cpu_data_master_read & ~onchip_memory_s1_waits_for_read & ~(|cpu_data_master_read_data_valid_onchip_memory_s1_shift_register);
//shift register p1 cpu_data_master_read_data_valid_onchip_memory_s1_shift_register in if flush, otherwise shift left, which is an e_mux
assign p1_cpu_data_master_read_data_valid_onchip_memory_s1_shift_register = {cpu_data_master_read_data_valid_onchip_memory_s1_shift_register, cpu_data_master_read_data_valid_onchip_memory_s1_shift_register_in};
//cpu_data_master_read_data_valid_onchip_memory_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_data_master_read_data_valid_onchip_memory_s1_shift_register <= 0;
else
cpu_data_master_read_data_valid_onchip_memory_s1_shift_register <= p1_cpu_data_master_read_data_valid_onchip_memory_s1_shift_register;
end
//local readdatavalid cpu_data_master_read_data_valid_onchip_memory_s1, which is an e_mux
assign cpu_data_master_read_data_valid_onchip_memory_s1 = cpu_data_master_read_data_valid_onchip_memory_s1_shift_register;
//onchip_memory_s1_writedata mux, which is an e_mux
assign onchip_memory_s1_writedata = cpu_data_master_writedata;
//mux onchip_memory_s1_clken, which is an e_mux
assign onchip_memory_s1_clken = 1'b1;
assign cpu_instruction_master_requests_onchip_memory_s1 = (({cpu_instruction_master_address_to_slave[23 : 12] , 12'b0} == 24'hb01000) & (cpu_instruction_master_read)) & cpu_instruction_master_read;
//cpu/data_master granted onchip_memory/s1 last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_data_master_granted_slave_onchip_memory_s1 <= 0;
else
last_cycle_cpu_data_master_granted_slave_onchip_memory_s1 <= cpu_data_master_saved_grant_onchip_memory_s1 ? 1 : (onchip_memory_s1_arbitration_holdoff_internal | ~cpu_data_master_requests_onchip_memory_s1) ? 0 : last_cycle_cpu_data_master_granted_slave_onchip_memory_s1;
end
//cpu_data_master_continuerequest continued request, which is an e_mux
assign cpu_data_master_continuerequest = last_cycle_cpu_data_master_granted_slave_onchip_memory_s1 & cpu_data_master_requests_onchip_memory_s1;
assign cpu_instruction_master_qualified_request_onchip_memory_s1 = cpu_instruction_master_requests_onchip_memory_s1 & ~((cpu_instruction_master_read & ((1 < cpu_instruction_master_latency_counter))) | cpu_data_master_arbiterlock);
//cpu_instruction_master_read_data_valid_onchip_memory_s1_shift_register_in mux for readlatency shift register, which is an e_mux
assign cpu_instruction_master_read_data_valid_onchip_memory_s1_shift_register_in = cpu_instruction_master_granted_onchip_memory_s1 & cpu_instruction_master_read & ~onchip_memory_s1_waits_for_read;
//shift register p1 cpu_instruction_master_read_data_valid_onchip_memory_s1_shift_register in if flush, otherwise shift left, which is an e_mux
assign p1_cpu_instruction_master_read_data_valid_onchip_memory_s1_shift_register = {cpu_instruction_master_read_data_valid_onchip_memory_s1_shift_register, cpu_instruction_master_read_data_valid_onchip_memory_s1_shift_register_in};
//cpu_instruction_master_read_data_valid_onchip_memory_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_instruction_master_read_data_valid_onchip_memory_s1_shift_register <= 0;
else
cpu_instruction_master_read_data_valid_onchip_memory_s1_shift_register <= p1_cpu_instruction_master_read_data_valid_onchip_memory_s1_shift_register;
end
//local readdatavalid cpu_instruction_master_read_data_valid_onchip_memory_s1, which is an e_mux
assign cpu_instruction_master_read_data_valid_onchip_memory_s1 = cpu_instruction_master_read_data_valid_onchip_memory_s1_shift_register;
//allow new arb cycle for onchip_memory/s1, which is an e_assign
assign onchip_memory_s1_allow_new_arb_cycle = ~cpu_data_master_arbiterlock & ~cpu_instruction_master_arbiterlock;
//cpu/instruction_master assignment into master qualified-requests vector for onchip_memory/s1, which is an e_assign
assign onchip_memory_s1_master_qreq_vector[0] = cpu_instruction_master_qualified_request_onchip_memory_s1;
//cpu/instruction_master grant onchip_memory/s1, which is an e_assign
assign cpu_instruction_master_granted_onchip_memory_s1 = onchip_memory_s1_grant_vector[0];
//cpu/instruction_master saved-grant onchip_memory/s1, which is an e_assign
assign cpu_instruction_master_saved_grant_onchip_memory_s1 = onchip_memory_s1_arb_winner[0] && cpu_instruction_master_requests_onchip_memory_s1;
//cpu/data_master assignment into master qualified-requests vector for onchip_memory/s1, which is an e_assign
assign onchip_memory_s1_master_qreq_vector[1] = cpu_data_master_qualified_request_onchip_memory_s1;
//cpu/data_master grant onchip_memory/s1, which is an e_assign
assign cpu_data_master_granted_onchip_memory_s1 = onchip_memory_s1_grant_vector[1];
//cpu/data_master saved-grant onchip_memory/s1, which is an e_assign
assign cpu_data_master_saved_grant_onchip_memory_s1 = onchip_memory_s1_arb_winner[1] && cpu_data_master_requests_onchip_memory_s1;
//onchip_memory/s1 chosen-master double-vector, which is an e_assign
assign onchip_memory_s1_chosen_master_double_vector = {onchip_memory_s1_master_qreq_vector, onchip_memory_s1_master_qreq_vector} & ({~onchip_memory_s1_master_qreq_vector, ~onchip_memory_s1_master_qreq_vector} + onchip_memory_s1_arb_addend);
//stable onehot encoding of arb winner
assign onchip_memory_s1_arb_winner = (onchip_memory_s1_allow_new_arb_cycle & | onchip_memory_s1_grant_vector) ? onchip_memory_s1_grant_vector : onchip_memory_s1_saved_chosen_master_vector;
//saved onchip_memory_s1_grant_vector, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
onchip_memory_s1_saved_chosen_master_vector <= 0;
else if (onchip_memory_s1_allow_new_arb_cycle)
onchip_memory_s1_saved_chosen_master_vector <= |onchip_memory_s1_grant_vector ? onchip_memory_s1_grant_vector : onchip_memory_s1_saved_chosen_master_vector;
end
//onehot encoding of chosen master
assign onchip_memory_s1_grant_vector = {(onchip_memory_s1_chosen_master_double_vector[1] | onchip_memory_s1_chosen_master_double_vector[3]),
(onchip_memory_s1_chosen_master_double_vector[0] | onchip_memory_s1_chosen_master_double_vector[2])};
//onchip_memory/s1 chosen master rotated left, which is an e_assign
assign onchip_memory_s1_chosen_master_rot_left = (onchip_memory_s1_arb_winner << 1) ? (onchip_memory_s1_arb_winner << 1) : 1;
//onchip_memory/s1's addend for next-master-grant
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
onchip_memory_s1_arb_addend <= 1;
else if (|onchip_memory_s1_grant_vector)
onchip_memory_s1_arb_addend <= onchip_memory_s1_end_xfer? onchip_memory_s1_chosen_master_rot_left : onchip_memory_s1_grant_vector;
end
//~onchip_memory_s1_reset assignment, which is an e_assign
assign onchip_memory_s1_reset = ~reset_n;
assign onchip_memory_s1_chipselect = cpu_data_master_granted_onchip_memory_s1 | cpu_instruction_master_granted_onchip_memory_s1;
//onchip_memory_s1_firsttransfer first transaction, which is an e_assign
assign onchip_memory_s1_firsttransfer = onchip_memory_s1_begins_xfer ? onchip_memory_s1_unreg_firsttransfer : onchip_memory_s1_reg_firsttransfer;
//onchip_memory_s1_unreg_firsttransfer first transaction, which is an e_assign
assign onchip_memory_s1_unreg_firsttransfer = ~(onchip_memory_s1_slavearbiterlockenable & onchip_memory_s1_any_continuerequest);
//onchip_memory_s1_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
onchip_memory_s1_reg_firsttransfer <= 1'b1;
else if (onchip_memory_s1_begins_xfer)
onchip_memory_s1_reg_firsttransfer <= onchip_memory_s1_unreg_firsttransfer;
end
//onchip_memory_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign onchip_memory_s1_beginbursttransfer_internal = onchip_memory_s1_begins_xfer;
//onchip_memory_s1_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
assign onchip_memory_s1_arbitration_holdoff_internal = onchip_memory_s1_begins_xfer & onchip_memory_s1_firsttransfer;
//onchip_memory_s1_write assignment, which is an e_mux
assign onchip_memory_s1_write = cpu_data_master_granted_onchip_memory_s1 & cpu_data_master_write;
assign shifted_address_to_onchip_memory_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
//onchip_memory_s1_address mux, which is an e_mux
assign onchip_memory_s1_address = (cpu_data_master_granted_onchip_memory_s1)? (shifted_address_to_onchip_memory_s1_from_cpu_data_master >> 2) :
(shifted_address_to_onchip_memory_s1_from_cpu_instruction_master >> 2);
assign shifted_address_to_onchip_memory_s1_from_cpu_instruction_master = cpu_instruction_master_address_to_slave;
//d1_onchip_memory_s1_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_onchip_memory_s1_end_xfer <= 1;
else
d1_onchip_memory_s1_end_xfer <= onchip_memory_s1_end_xfer;
end
//onchip_memory_s1_waits_for_read in a cycle, which is an e_mux
assign onchip_memory_s1_waits_for_read = onchip_memory_s1_in_a_read_cycle & 0;
//onchip_memory_s1_in_a_read_cycle assignment, which is an e_assign
assign onchip_memory_s1_in_a_read_cycle = (cpu_data_master_granted_onchip_memory_s1 & cpu_data_master_read) | (cpu_instruction_master_granted_onchip_memory_s1 & cpu_instruction_master_read);
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = onchip_memory_s1_in_a_read_cycle;
//onchip_memory_s1_waits_for_write in a cycle, which is an e_mux
assign onchip_memory_s1_waits_for_write = onchip_memory_s1_in_a_write_cycle & 0;
//onchip_memory_s1_in_a_write_cycle assignment, which is an e_assign
assign onchip_memory_s1_in_a_write_cycle = cpu_data_master_granted_onchip_memory_s1 & cpu_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = onchip_memory_s1_in_a_write_cycle;
assign wait_for_onchip_memory_s1_counter = 0;
//onchip_memory_s1_byteenable byte enable port mux, which is an e_mux
assign onchip_memory_s1_byteenable = (cpu_data_master_granted_onchip_memory_s1)? cpu_data_master_byteenable :
-1;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//onchip_memory/s1 enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_data_master_granted_onchip_memory_s1 + cpu_instruction_master_granted_onchip_memory_s1 > 1)
begin
$write("%0d ns: > 1 of grant signals are active simultaneously", $time);
$stop;
end
end
//saved_grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_data_master_saved_grant_onchip_memory_s1 + cpu_instruction_master_saved_grant_onchip_memory_s1 > 1)
begin
$write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module pll_pll_slave_arbitrator (
// inputs:
clk,
cpu_data_master_address_to_slave,
cpu_data_master_read,
cpu_data_master_waitrequest,
cpu_data_master_write,
cpu_data_master_writedata,
pll_pll_slave_readdata,
reset_n,
// outputs:
cpu_data_master_granted_pll_pll_slave,
cpu_data_master_qualified_request_pll_pll_slave,
cpu_data_master_read_data_valid_pll_pll_slave,
cpu_data_master_requests_pll_pll_slave,
d1_pll_pll_slave_end_xfer,
pll_pll_slave_address,
pll_pll_slave_read,
pll_pll_slave_readdata_from_sa,
pll_pll_slave_reset,
pll_pll_slave_write,
pll_pll_slave_writedata
)
;
output cpu_data_master_granted_pll_pll_slave;
output cpu_data_master_qualified_request_pll_pll_slave;
output cpu_data_master_read_data_valid_pll_pll_slave;
output cpu_data_master_requests_pll_pll_slave;
output d1_pll_pll_slave_end_xfer;
output [ 1: 0] pll_pll_slave_address;
output pll_pll_slave_read;
output [ 31: 0] pll_pll_slave_readdata_from_sa;
output pll_pll_slave_reset;
output pll_pll_slave_write;
output [ 31: 0] pll_pll_slave_writedata;
input clk;
input [ 23: 0] cpu_data_master_address_to_slave;
input cpu_data_master_read;
input cpu_data_master_waitrequest;
input cpu_data_master_write;
input [ 31: 0] cpu_data_master_writedata;
input [ 31: 0] pll_pll_slave_readdata;
input reset_n;
wire cpu_data_master_arbiterlock;
wire cpu_data_master_arbiterlock2;
wire cpu_data_master_continuerequest;
wire cpu_data_master_granted_pll_pll_slave;
wire cpu_data_master_qualified_request_pll_pll_slave;
wire cpu_data_master_read_data_valid_pll_pll_slave;
wire cpu_data_master_requests_pll_pll_slave;
wire cpu_data_master_saved_grant_pll_pll_slave;
reg d1_pll_pll_slave_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_pll_pll_slave;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 1: 0] pll_pll_slave_address;
wire pll_pll_slave_allgrants;
wire pll_pll_slave_allow_new_arb_cycle;
wire pll_pll_slave_any_bursting_master_saved_grant;
wire pll_pll_slave_any_continuerequest;
wire pll_pll_slave_arb_counter_enable;
reg [ 2: 0] pll_pll_slave_arb_share_counter;
wire [ 2: 0] pll_pll_slave_arb_share_counter_next_value;
wire [ 2: 0] pll_pll_slave_arb_share_set_values;
wire pll_pll_slave_beginbursttransfer_internal;
wire pll_pll_slave_begins_xfer;
wire pll_pll_slave_end_xfer;
wire pll_pll_slave_firsttransfer;
wire pll_pll_slave_grant_vector;
wire pll_pll_slave_in_a_read_cycle;
wire pll_pll_slave_in_a_write_cycle;
wire pll_pll_slave_master_qreq_vector;
wire pll_pll_slave_non_bursting_master_requests;
wire pll_pll_slave_read;
wire [ 31: 0] pll_pll_slave_readdata_from_sa;
reg pll_pll_slave_reg_firsttransfer;
wire pll_pll_slave_reset;
reg pll_pll_slave_slavearbiterlockenable;
wire pll_pll_slave_slavearbiterlockenable2;
wire pll_pll_slave_unreg_firsttransfer;
wire pll_pll_slave_waits_for_read;
wire pll_pll_slave_waits_for_write;
wire pll_pll_slave_write;
wire [ 31: 0] pll_pll_slave_writedata;
wire [ 23: 0] shifted_address_to_pll_pll_slave_from_cpu_data_master;
wire wait_for_pll_pll_slave_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~pll_pll_slave_end_xfer;
end
assign pll_pll_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_pll_pll_slave));
//assign pll_pll_slave_readdata_from_sa = pll_pll_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign pll_pll_slave_readdata_from_sa = pll_pll_slave_readdata;
assign cpu_data_master_requests_pll_pll_slave = ({cpu_data_master_address_to_slave[23 : 4] , 4'b0} == 24'hb04050) & (cpu_data_master_read | cpu_data_master_write);
//pll_pll_slave_arb_share_counter set values, which is an e_mux
assign pll_pll_slave_arb_share_set_values = 1;
//pll_pll_slave_non_bursting_master_requests mux, which is an e_mux
assign pll_pll_slave_non_bursting_master_requests = cpu_data_master_requests_pll_pll_slave;
//pll_pll_slave_any_bursting_master_saved_grant mux, which is an e_mux
assign pll_pll_slave_any_bursting_master_saved_grant = 0;
//pll_pll_slave_arb_share_counter_next_value assignment, which is an e_assign
assign pll_pll_slave_arb_share_counter_next_value = pll_pll_slave_firsttransfer ? (pll_pll_slave_arb_share_set_values - 1) : |pll_pll_slave_arb_share_counter ? (pll_pll_slave_arb_share_counter - 1) : 0;
//pll_pll_slave_allgrants all slave grants, which is an e_mux
assign pll_pll_slave_allgrants = |pll_pll_slave_grant_vector;
//pll_pll_slave_end_xfer assignment, which is an e_assign
assign pll_pll_slave_end_xfer = ~(pll_pll_slave_waits_for_read | pll_pll_slave_waits_for_write);
//end_xfer_arb_share_counter_term_pll_pll_slave arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_pll_pll_slave = pll_pll_slave_end_xfer & (~pll_pll_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//pll_pll_slave_arb_share_counter arbitration counter enable, which is an e_assign
assign pll_pll_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_pll_pll_slave & pll_pll_slave_allgrants) | (end_xfer_arb_share_counter_term_pll_pll_slave & ~pll_pll_slave_non_bursting_master_requests);
//pll_pll_slave_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
pll_pll_slave_arb_share_counter <= 0;
else if (pll_pll_slave_arb_counter_enable)
pll_pll_slave_arb_share_counter <= pll_pll_slave_arb_share_counter_next_value;
end
//pll_pll_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
pll_pll_slave_slavearbiterlockenable <= 0;
else if ((|pll_pll_slave_master_qreq_vector & end_xfer_arb_share_counter_term_pll_pll_slave) | (end_xfer_arb_share_counter_term_pll_pll_slave & ~pll_pll_slave_non_bursting_master_requests))
pll_pll_slave_slavearbiterlockenable <= |pll_pll_slave_arb_share_counter_next_value;
end
//cpu/data_master pll/pll_slave arbiterlock, which is an e_assign
assign cpu_data_master_arbiterlock = pll_pll_slave_slavearbiterlockenable & cpu_data_master_continuerequest;
//pll_pll_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign pll_pll_slave_slavearbiterlockenable2 = |pll_pll_slave_arb_share_counter_next_value;
//cpu/data_master pll/pll_slave arbiterlock2, which is an e_assign
assign cpu_data_master_arbiterlock2 = pll_pll_slave_slavearbiterlockenable2 & cpu_data_master_continuerequest;
//pll_pll_slave_any_continuerequest at least one master continues requesting, which is an e_assign
assign pll_pll_slave_any_continuerequest = 1;
//cpu_data_master_continuerequest continued request, which is an e_assign
assign cpu_data_master_continuerequest = 1;
assign cpu_data_master_qualified_request_pll_pll_slave = cpu_data_master_requests_pll_pll_slave & ~((cpu_data_master_read & (~cpu_data_master_waitrequest)) | ((~cpu_data_master_waitrequest) & cpu_data_master_write));
//pll_pll_slave_writedata mux, which is an e_mux
assign pll_pll_slave_writedata = cpu_data_master_writedata;
//master is always granted when requested
assign cpu_data_master_granted_pll_pll_slave = cpu_data_master_qualified_request_pll_pll_slave;
//cpu/data_master saved-grant pll/pll_slave, which is an e_assign
assign cpu_data_master_saved_grant_pll_pll_slave = cpu_data_master_requests_pll_pll_slave;
//allow new arb cycle for pll/pll_slave, which is an e_assign
assign pll_pll_slave_allow_new_arb_cycle = 1;
//placeholder chosen master
assign pll_pll_slave_grant_vector = 1;
//placeholder vector of master qualified-requests
assign pll_pll_slave_master_qreq_vector = 1;
//~pll_pll_slave_reset assignment, which is an e_assign
assign pll_pll_slave_reset = ~reset_n;
//pll_pll_slave_firsttransfer first transaction, which is an e_assign
assign pll_pll_slave_firsttransfer = pll_pll_slave_begins_xfer ? pll_pll_slave_unreg_firsttransfer : pll_pll_slave_reg_firsttransfer;
//pll_pll_slave_unreg_firsttransfer first transaction, which is an e_assign
assign pll_pll_slave_unreg_firsttransfer = ~(pll_pll_slave_slavearbiterlockenable & pll_pll_slave_any_continuerequest);
//pll_pll_slave_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
pll_pll_slave_reg_firsttransfer <= 1'b1;
else if (pll_pll_slave_begins_xfer)
pll_pll_slave_reg_firsttransfer <= pll_pll_slave_unreg_firsttransfer;
end
//pll_pll_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign pll_pll_slave_beginbursttransfer_internal = pll_pll_slave_begins_xfer;
//pll_pll_slave_read assignment, which is an e_mux
assign pll_pll_slave_read = cpu_data_master_granted_pll_pll_slave & cpu_data_master_read;
//pll_pll_slave_write assignment, which is an e_mux
assign pll_pll_slave_write = cpu_data_master_granted_pll_pll_slave & cpu_data_master_write;
assign shifted_address_to_pll_pll_slave_from_cpu_data_master = cpu_data_master_address_to_slave;
//pll_pll_slave_address mux, which is an e_mux
assign pll_pll_slave_address = shifted_address_to_pll_pll_slave_from_cpu_data_master >> 2;
//d1_pll_pll_slave_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_pll_pll_slave_end_xfer <= 1;
else
d1_pll_pll_slave_end_xfer <= pll_pll_slave_end_xfer;
end
//pll_pll_slave_waits_for_read in a cycle, which is an e_mux
assign pll_pll_slave_waits_for_read = pll_pll_slave_in_a_read_cycle & 0;
//pll_pll_slave_in_a_read_cycle assignment, which is an e_assign
assign pll_pll_slave_in_a_read_cycle = cpu_data_master_granted_pll_pll_slave & cpu_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = pll_pll_slave_in_a_read_cycle;
//pll_pll_slave_waits_for_write in a cycle, which is an e_mux
assign pll_pll_slave_waits_for_write = pll_pll_slave_in_a_write_cycle & 0;
//pll_pll_slave_in_a_write_cycle assignment, which is an e_assign
assign pll_pll_slave_in_a_write_cycle = cpu_data_master_granted_pll_pll_slave & cpu_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = pll_pll_slave_in_a_write_cycle;
assign wait_for_pll_pll_slave_counter = 0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//pll/pll_slave enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sram_16bit_512k_0_avalon_slave_0_arbitrator (
// inputs:
clk,
cpu_data_master_address_to_slave,
cpu_data_master_byteenable,
cpu_data_master_dbs_address,
cpu_data_master_dbs_write_16,
cpu_data_master_no_byte_enables_and_last_term,
cpu_data_master_read,
cpu_data_master_write,
cpu_instruction_master_address_to_slave,
cpu_instruction_master_dbs_address,
cpu_instruction_master_latency_counter,
cpu_instruction_master_read,
reset_n,
sram_16bit_512k_0_avalon_slave_0_readdata,
// outputs:
cpu_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0,
cpu_data_master_granted_sram_16bit_512k_0_avalon_slave_0,
cpu_data_master_qualified_request_sram_16bit_512k_0_avalon_slave_0,
cpu_data_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0,
cpu_data_master_requests_sram_16bit_512k_0_avalon_slave_0,
cpu_instruction_master_granted_sram_16bit_512k_0_avalon_slave_0,
cpu_instruction_master_qualified_request_sram_16bit_512k_0_avalon_slave_0,
cpu_instruction_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0,
cpu_instruction_master_requests_sram_16bit_512k_0_avalon_slave_0,
d1_sram_16bit_512k_0_avalon_slave_0_end_xfer,
sram_16bit_512k_0_avalon_slave_0_address,
sram_16bit_512k_0_avalon_slave_0_byteenable_n,
sram_16bit_512k_0_avalon_slave_0_chipselect_n,
sram_16bit_512k_0_avalon_slave_0_read_n,
sram_16bit_512k_0_avalon_slave_0_readdata_from_sa,
sram_16bit_512k_0_avalon_slave_0_reset_n,
sram_16bit_512k_0_avalon_slave_0_wait_counter_eq_0,
sram_16bit_512k_0_avalon_slave_0_write_n,
sram_16bit_512k_0_avalon_slave_0_writedata
)
;
output [ 1: 0] cpu_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0;
output cpu_data_master_granted_sram_16bit_512k_0_avalon_slave_0;
output cpu_data_master_qualified_request_sram_16bit_512k_0_avalon_slave_0;
output cpu_data_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0;
output cpu_data_master_requests_sram_16bit_512k_0_avalon_slave_0;
output cpu_instruction_master_granted_sram_16bit_512k_0_avalon_slave_0;
output cpu_instruction_master_qualified_request_sram_16bit_512k_0_avalon_slave_0;
output cpu_instruction_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0;
output cpu_instruction_master_requests_sram_16bit_512k_0_avalon_slave_0;
output d1_sram_16bit_512k_0_avalon_slave_0_end_xfer;
output [ 17: 0] sram_16bit_512k_0_avalon_slave_0_address;
output [ 1: 0] sram_16bit_512k_0_avalon_slave_0_byteenable_n;
output sram_16bit_512k_0_avalon_slave_0_chipselect_n;
output sram_16bit_512k_0_avalon_slave_0_read_n;
output [ 15: 0] sram_16bit_512k_0_avalon_slave_0_readdata_from_sa;
output sram_16bit_512k_0_avalon_slave_0_reset_n;
output sram_16bit_512k_0_avalon_slave_0_wait_counter_eq_0;
output sram_16bit_512k_0_avalon_slave_0_write_n;
output [ 15: 0] sram_16bit_512k_0_avalon_slave_0_writedata;
input clk;
input [ 23: 0] cpu_data_master_address_to_slave;
input [ 3: 0] cpu_data_master_byteenable;
input [ 1: 0] cpu_data_master_dbs_address;
input [ 15: 0] cpu_data_master_dbs_write_16;
input cpu_data_master_no_byte_enables_and_last_term;
input cpu_data_master_read;
input cpu_data_master_write;
input [ 23: 0] cpu_instruction_master_address_to_slave;
input [ 1: 0] cpu_instruction_master_dbs_address;
input [ 1: 0] cpu_instruction_master_latency_counter;
input cpu_instruction_master_read;
input reset_n;
input [ 15: 0] sram_16bit_512k_0_avalon_slave_0_readdata;
wire cpu_data_master_arbiterlock;
wire cpu_data_master_arbiterlock2;
wire [ 1: 0] cpu_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0;
wire [ 1: 0] cpu_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0_segment_0;
wire [ 1: 0] cpu_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0_segment_1;
wire cpu_data_master_continuerequest;
wire cpu_data_master_granted_sram_16bit_512k_0_avalon_slave_0;
wire cpu_data_master_qualified_request_sram_16bit_512k_0_avalon_slave_0;
wire cpu_data_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0;
wire cpu_data_master_requests_sram_16bit_512k_0_avalon_slave_0;
wire cpu_data_master_saved_grant_sram_16bit_512k_0_avalon_slave_0;
wire cpu_instruction_master_arbiterlock;
wire cpu_instruction_master_arbiterlock2;
wire cpu_instruction_master_continuerequest;
wire cpu_instruction_master_granted_sram_16bit_512k_0_avalon_slave_0;
wire cpu_instruction_master_qualified_request_sram_16bit_512k_0_avalon_slave_0;
wire cpu_instruction_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0;
wire cpu_instruction_master_requests_sram_16bit_512k_0_avalon_slave_0;
wire cpu_instruction_master_saved_grant_sram_16bit_512k_0_avalon_slave_0;
reg d1_reasons_to_wait;
reg d1_sram_16bit_512k_0_avalon_slave_0_end_xfer;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_sram_16bit_512k_0_avalon_slave_0;
wire in_a_read_cycle;
wire in_a_write_cycle;
reg last_cycle_cpu_data_master_granted_slave_sram_16bit_512k_0_avalon_slave_0;
reg last_cycle_cpu_instruction_master_granted_slave_sram_16bit_512k_0_avalon_slave_0;
wire [ 23: 0] shifted_address_to_sram_16bit_512k_0_avalon_slave_0_from_cpu_data_master;
wire [ 23: 0] shifted_address_to_sram_16bit_512k_0_avalon_slave_0_from_cpu_instruction_master;
wire [ 17: 0] sram_16bit_512k_0_avalon_slave_0_address;
wire sram_16bit_512k_0_avalon_slave_0_allgrants;
wire sram_16bit_512k_0_avalon_slave_0_allow_new_arb_cycle;
wire sram_16bit_512k_0_avalon_slave_0_any_bursting_master_saved_grant;
wire sram_16bit_512k_0_avalon_slave_0_any_continuerequest;
reg [ 1: 0] sram_16bit_512k_0_avalon_slave_0_arb_addend;
wire sram_16bit_512k_0_avalon_slave_0_arb_counter_enable;
reg [ 2: 0] sram_16bit_512k_0_avalon_slave_0_arb_share_counter;
wire [ 2: 0] sram_16bit_512k_0_avalon_slave_0_arb_share_counter_next_value;
wire [ 2: 0] sram_16bit_512k_0_avalon_slave_0_arb_share_set_values;
wire [ 1: 0] sram_16bit_512k_0_avalon_slave_0_arb_winner;
wire sram_16bit_512k_0_avalon_slave_0_arbitration_holdoff_internal;
wire sram_16bit_512k_0_avalon_slave_0_beginbursttransfer_internal;
wire sram_16bit_512k_0_avalon_slave_0_begins_xfer;
wire [ 1: 0] sram_16bit_512k_0_avalon_slave_0_byteenable_n;
wire sram_16bit_512k_0_avalon_slave_0_chipselect_n;
wire [ 3: 0] sram_16bit_512k_0_avalon_slave_0_chosen_master_double_vector;
wire [ 1: 0] sram_16bit_512k_0_avalon_slave_0_chosen_master_rot_left;
wire sram_16bit_512k_0_avalon_slave_0_counter_load_value;
wire sram_16bit_512k_0_avalon_slave_0_end_xfer;
wire sram_16bit_512k_0_avalon_slave_0_firsttransfer;
wire [ 1: 0] sram_16bit_512k_0_avalon_slave_0_grant_vector;
wire sram_16bit_512k_0_avalon_slave_0_in_a_read_cycle;
wire sram_16bit_512k_0_avalon_slave_0_in_a_write_cycle;
wire [ 1: 0] sram_16bit_512k_0_avalon_slave_0_master_qreq_vector;
wire sram_16bit_512k_0_avalon_slave_0_non_bursting_master_requests;
wire sram_16bit_512k_0_avalon_slave_0_read_n;
wire [ 15: 0] sram_16bit_512k_0_avalon_slave_0_readdata_from_sa;
reg sram_16bit_512k_0_avalon_slave_0_reg_firsttransfer;
wire sram_16bit_512k_0_avalon_slave_0_reset_n;
reg [ 1: 0] sram_16bit_512k_0_avalon_slave_0_saved_chosen_master_vector;
reg sram_16bit_512k_0_avalon_slave_0_slavearbiterlockenable;
wire sram_16bit_512k_0_avalon_slave_0_slavearbiterlockenable2;
wire sram_16bit_512k_0_avalon_slave_0_unreg_firsttransfer;
reg sram_16bit_512k_0_avalon_slave_0_wait_counter;
wire sram_16bit_512k_0_avalon_slave_0_wait_counter_eq_0;
wire sram_16bit_512k_0_avalon_slave_0_waits_for_read;
wire sram_16bit_512k_0_avalon_slave_0_waits_for_write;
wire sram_16bit_512k_0_avalon_slave_0_write_n;
wire [ 15: 0] sram_16bit_512k_0_avalon_slave_0_writedata;
wire wait_for_sram_16bit_512k_0_avalon_slave_0_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~sram_16bit_512k_0_avalon_slave_0_end_xfer;
end
assign sram_16bit_512k_0_avalon_slave_0_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_sram_16bit_512k_0_avalon_slave_0 | cpu_instruction_master_qualified_request_sram_16bit_512k_0_avalon_slave_0));
//assign sram_16bit_512k_0_avalon_slave_0_readdata_from_sa = sram_16bit_512k_0_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign sram_16bit_512k_0_avalon_slave_0_readdata_from_sa = sram_16bit_512k_0_avalon_slave_0_readdata;
assign cpu_data_master_requests_sram_16bit_512k_0_avalon_slave_0 = ({cpu_data_master_address_to_slave[23 : 19] , 19'b0} == 24'ha80000) & (cpu_data_master_read | cpu_data_master_write);
//sram_16bit_512k_0_avalon_slave_0_arb_share_counter set values, which is an e_mux
assign sram_16bit_512k_0_avalon_slave_0_arb_share_set_values = (cpu_data_master_granted_sram_16bit_512k_0_avalon_slave_0)? 2 :
(cpu_instruction_master_granted_sram_16bit_512k_0_avalon_slave_0)? 2 :
(cpu_data_master_granted_sram_16bit_512k_0_avalon_slave_0)? 2 :
(cpu_instruction_master_granted_sram_16bit_512k_0_avalon_slave_0)? 2 :
1;
//sram_16bit_512k_0_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
assign sram_16bit_512k_0_avalon_slave_0_non_bursting_master_requests = cpu_data_master_requests_sram_16bit_512k_0_avalon_slave_0 |
cpu_instruction_master_requests_sram_16bit_512k_0_avalon_slave_0 |
cpu_data_master_requests_sram_16bit_512k_0_avalon_slave_0 |
cpu_instruction_master_requests_sram_16bit_512k_0_avalon_slave_0;
//sram_16bit_512k_0_avalon_slave_0_any_bursting_master_saved_grant mux, which is an e_mux
assign sram_16bit_512k_0_avalon_slave_0_any_bursting_master_saved_grant = 0;
//sram_16bit_512k_0_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
assign sram_16bit_512k_0_avalon_slave_0_arb_share_counter_next_value = sram_16bit_512k_0_avalon_slave_0_firsttransfer ? (sram_16bit_512k_0_avalon_slave_0_arb_share_set_values - 1) : |sram_16bit_512k_0_avalon_slave_0_arb_share_counter ? (sram_16bit_512k_0_avalon_slave_0_arb_share_counter - 1) : 0;
//sram_16bit_512k_0_avalon_slave_0_allgrants all slave grants, which is an e_mux
assign sram_16bit_512k_0_avalon_slave_0_allgrants = (|sram_16bit_512k_0_avalon_slave_0_grant_vector) |
(|sram_16bit_512k_0_avalon_slave_0_grant_vector) |
(|sram_16bit_512k_0_avalon_slave_0_grant_vector) |
(|sram_16bit_512k_0_avalon_slave_0_grant_vector);
//sram_16bit_512k_0_avalon_slave_0_end_xfer assignment, which is an e_assign
assign sram_16bit_512k_0_avalon_slave_0_end_xfer = ~(sram_16bit_512k_0_avalon_slave_0_waits_for_read | sram_16bit_512k_0_avalon_slave_0_waits_for_write);
//end_xfer_arb_share_counter_term_sram_16bit_512k_0_avalon_slave_0 arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_sram_16bit_512k_0_avalon_slave_0 = sram_16bit_512k_0_avalon_slave_0_end_xfer & (~sram_16bit_512k_0_avalon_slave_0_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//sram_16bit_512k_0_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
assign sram_16bit_512k_0_avalon_slave_0_arb_counter_enable = (end_xfer_arb_share_counter_term_sram_16bit_512k_0_avalon_slave_0 & sram_16bit_512k_0_avalon_slave_0_allgrants) | (end_xfer_arb_share_counter_term_sram_16bit_512k_0_avalon_slave_0 & ~sram_16bit_512k_0_avalon_slave_0_non_bursting_master_requests);
//sram_16bit_512k_0_avalon_slave_0_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sram_16bit_512k_0_avalon_slave_0_arb_share_counter <= 0;
else if (sram_16bit_512k_0_avalon_slave_0_arb_counter_enable)
sram_16bit_512k_0_avalon_slave_0_arb_share_counter <= sram_16bit_512k_0_avalon_slave_0_arb_share_counter_next_value;
end
//sram_16bit_512k_0_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sram_16bit_512k_0_avalon_slave_0_slavearbiterlockenable <= 0;
else if ((|sram_16bit_512k_0_avalon_slave_0_master_qreq_vector & end_xfer_arb_share_counter_term_sram_16bit_512k_0_avalon_slave_0) | (end_xfer_arb_share_counter_term_sram_16bit_512k_0_avalon_slave_0 & ~sram_16bit_512k_0_avalon_slave_0_non_bursting_master_requests))
sram_16bit_512k_0_avalon_slave_0_slavearbiterlockenable <= |sram_16bit_512k_0_avalon_slave_0_arb_share_counter_next_value;
end
//cpu/data_master sram_16bit_512k_0/avalon_slave_0 arbiterlock, which is an e_assign
assign cpu_data_master_arbiterlock = sram_16bit_512k_0_avalon_slave_0_slavearbiterlockenable & cpu_data_master_continuerequest;
//sram_16bit_512k_0_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign sram_16bit_512k_0_avalon_slave_0_slavearbiterlockenable2 = |sram_16bit_512k_0_avalon_slave_0_arb_share_counter_next_value;
//cpu/data_master sram_16bit_512k_0/avalon_slave_0 arbiterlock2, which is an e_assign
assign cpu_data_master_arbiterlock2 = sram_16bit_512k_0_avalon_slave_0_slavearbiterlockenable2 & cpu_data_master_continuerequest;
//cpu/instruction_master sram_16bit_512k_0/avalon_slave_0 arbiterlock, which is an e_assign
assign cpu_instruction_master_arbiterlock = sram_16bit_512k_0_avalon_slave_0_slavearbiterlockenable & cpu_instruction_master_continuerequest;
//cpu/instruction_master sram_16bit_512k_0/avalon_slave_0 arbiterlock2, which is an e_assign
assign cpu_instruction_master_arbiterlock2 = sram_16bit_512k_0_avalon_slave_0_slavearbiterlockenable2 & cpu_instruction_master_continuerequest;
//cpu/instruction_master granted sram_16bit_512k_0/avalon_slave_0 last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_instruction_master_granted_slave_sram_16bit_512k_0_avalon_slave_0 <= 0;
else
last_cycle_cpu_instruction_master_granted_slave_sram_16bit_512k_0_avalon_slave_0 <= cpu_instruction_master_saved_grant_sram_16bit_512k_0_avalon_slave_0 ? 1 : (sram_16bit_512k_0_avalon_slave_0_arbitration_holdoff_internal | ~cpu_instruction_master_requests_sram_16bit_512k_0_avalon_slave_0) ? 0 : last_cycle_cpu_instruction_master_granted_slave_sram_16bit_512k_0_avalon_slave_0;
end
//cpu_instruction_master_continuerequest continued request, which is an e_mux
assign cpu_instruction_master_continuerequest = last_cycle_cpu_instruction_master_granted_slave_sram_16bit_512k_0_avalon_slave_0 & cpu_instruction_master_requests_sram_16bit_512k_0_avalon_slave_0;
//sram_16bit_512k_0_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_mux
assign sram_16bit_512k_0_avalon_slave_0_any_continuerequest = cpu_instruction_master_continuerequest |
cpu_data_master_continuerequest;
assign cpu_data_master_qualified_request_sram_16bit_512k_0_avalon_slave_0 = cpu_data_master_requests_sram_16bit_512k_0_avalon_slave_0 & ~(((cpu_data_master_no_byte_enables_and_last_term | !cpu_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0) & cpu_data_master_write) | cpu_instruction_master_arbiterlock);
//sram_16bit_512k_0_avalon_slave_0_writedata mux, which is an e_mux
assign sram_16bit_512k_0_avalon_slave_0_writedata = cpu_data_master_dbs_write_16;
assign cpu_instruction_master_requests_sram_16bit_512k_0_avalon_slave_0 = (({cpu_instruction_master_address_to_slave[23 : 19] , 19'b0} == 24'ha80000) & (cpu_instruction_master_read)) & cpu_instruction_master_read;
//cpu/data_master granted sram_16bit_512k_0/avalon_slave_0 last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_data_master_granted_slave_sram_16bit_512k_0_avalon_slave_0 <= 0;
else
last_cycle_cpu_data_master_granted_slave_sram_16bit_512k_0_avalon_slave_0 <= cpu_data_master_saved_grant_sram_16bit_512k_0_avalon_slave_0 ? 1 : (sram_16bit_512k_0_avalon_slave_0_arbitration_holdoff_internal | ~cpu_data_master_requests_sram_16bit_512k_0_avalon_slave_0) ? 0 : last_cycle_cpu_data_master_granted_slave_sram_16bit_512k_0_avalon_slave_0;
end
//cpu_data_master_continuerequest continued request, which is an e_mux
assign cpu_data_master_continuerequest = last_cycle_cpu_data_master_granted_slave_sram_16bit_512k_0_avalon_slave_0 & cpu_data_master_requests_sram_16bit_512k_0_avalon_slave_0;
assign cpu_instruction_master_qualified_request_sram_16bit_512k_0_avalon_slave_0 = cpu_instruction_master_requests_sram_16bit_512k_0_avalon_slave_0 & ~((cpu_instruction_master_read & ((cpu_instruction_master_latency_counter != 0))) | cpu_data_master_arbiterlock);
//local readdatavalid cpu_instruction_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0, which is an e_mux
assign cpu_instruction_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0 = cpu_instruction_master_granted_sram_16bit_512k_0_avalon_slave_0 & cpu_instruction_master_read & ~sram_16bit_512k_0_avalon_slave_0_waits_for_read;
//allow new arb cycle for sram_16bit_512k_0/avalon_slave_0, which is an e_assign
assign sram_16bit_512k_0_avalon_slave_0_allow_new_arb_cycle = ~cpu_data_master_arbiterlock & ~cpu_instruction_master_arbiterlock;
//cpu/instruction_master assignment into master qualified-requests vector for sram_16bit_512k_0/avalon_slave_0, which is an e_assign
assign sram_16bit_512k_0_avalon_slave_0_master_qreq_vector[0] = cpu_instruction_master_qualified_request_sram_16bit_512k_0_avalon_slave_0;
//cpu/instruction_master grant sram_16bit_512k_0/avalon_slave_0, which is an e_assign
assign cpu_instruction_master_granted_sram_16bit_512k_0_avalon_slave_0 = sram_16bit_512k_0_avalon_slave_0_grant_vector[0];
//cpu/instruction_master saved-grant sram_16bit_512k_0/avalon_slave_0, which is an e_assign
assign cpu_instruction_master_saved_grant_sram_16bit_512k_0_avalon_slave_0 = sram_16bit_512k_0_avalon_slave_0_arb_winner[0] && cpu_instruction_master_requests_sram_16bit_512k_0_avalon_slave_0;
//cpu/data_master assignment into master qualified-requests vector for sram_16bit_512k_0/avalon_slave_0, which is an e_assign
assign sram_16bit_512k_0_avalon_slave_0_master_qreq_vector[1] = cpu_data_master_qualified_request_sram_16bit_512k_0_avalon_slave_0;
//cpu/data_master grant sram_16bit_512k_0/avalon_slave_0, which is an e_assign
assign cpu_data_master_granted_sram_16bit_512k_0_avalon_slave_0 = sram_16bit_512k_0_avalon_slave_0_grant_vector[1];
//cpu/data_master saved-grant sram_16bit_512k_0/avalon_slave_0, which is an e_assign
assign cpu_data_master_saved_grant_sram_16bit_512k_0_avalon_slave_0 = sram_16bit_512k_0_avalon_slave_0_arb_winner[1] && cpu_data_master_requests_sram_16bit_512k_0_avalon_slave_0;
//sram_16bit_512k_0/avalon_slave_0 chosen-master double-vector, which is an e_assign
assign sram_16bit_512k_0_avalon_slave_0_chosen_master_double_vector = {sram_16bit_512k_0_avalon_slave_0_master_qreq_vector, sram_16bit_512k_0_avalon_slave_0_master_qreq_vector} & ({~sram_16bit_512k_0_avalon_slave_0_master_qreq_vector, ~sram_16bit_512k_0_avalon_slave_0_master_qreq_vector} + sram_16bit_512k_0_avalon_slave_0_arb_addend);
//stable onehot encoding of arb winner
assign sram_16bit_512k_0_avalon_slave_0_arb_winner = (sram_16bit_512k_0_avalon_slave_0_allow_new_arb_cycle & | sram_16bit_512k_0_avalon_slave_0_grant_vector) ? sram_16bit_512k_0_avalon_slave_0_grant_vector : sram_16bit_512k_0_avalon_slave_0_saved_chosen_master_vector;
//saved sram_16bit_512k_0_avalon_slave_0_grant_vector, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sram_16bit_512k_0_avalon_slave_0_saved_chosen_master_vector <= 0;
else if (sram_16bit_512k_0_avalon_slave_0_allow_new_arb_cycle)
sram_16bit_512k_0_avalon_slave_0_saved_chosen_master_vector <= |sram_16bit_512k_0_avalon_slave_0_grant_vector ? sram_16bit_512k_0_avalon_slave_0_grant_vector : sram_16bit_512k_0_avalon_slave_0_saved_chosen_master_vector;
end
//onehot encoding of chosen master
assign sram_16bit_512k_0_avalon_slave_0_grant_vector = {(sram_16bit_512k_0_avalon_slave_0_chosen_master_double_vector[1] | sram_16bit_512k_0_avalon_slave_0_chosen_master_double_vector[3]),
(sram_16bit_512k_0_avalon_slave_0_chosen_master_double_vector[0] | sram_16bit_512k_0_avalon_slave_0_chosen_master_double_vector[2])};
//sram_16bit_512k_0/avalon_slave_0 chosen master rotated left, which is an e_assign
assign sram_16bit_512k_0_avalon_slave_0_chosen_master_rot_left = (sram_16bit_512k_0_avalon_slave_0_arb_winner << 1) ? (sram_16bit_512k_0_avalon_slave_0_arb_winner << 1) : 1;
//sram_16bit_512k_0/avalon_slave_0's addend for next-master-grant
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sram_16bit_512k_0_avalon_slave_0_arb_addend <= 1;
else if (|sram_16bit_512k_0_avalon_slave_0_grant_vector)
sram_16bit_512k_0_avalon_slave_0_arb_addend <= sram_16bit_512k_0_avalon_slave_0_end_xfer? sram_16bit_512k_0_avalon_slave_0_chosen_master_rot_left : sram_16bit_512k_0_avalon_slave_0_grant_vector;
end
//sram_16bit_512k_0_avalon_slave_0_reset_n assignment, which is an e_assign
assign sram_16bit_512k_0_avalon_slave_0_reset_n = reset_n;
assign sram_16bit_512k_0_avalon_slave_0_chipselect_n = ~(cpu_data_master_granted_sram_16bit_512k_0_avalon_slave_0 | cpu_instruction_master_granted_sram_16bit_512k_0_avalon_slave_0);
//sram_16bit_512k_0_avalon_slave_0_firsttransfer first transaction, which is an e_assign
assign sram_16bit_512k_0_avalon_slave_0_firsttransfer = sram_16bit_512k_0_avalon_slave_0_begins_xfer ? sram_16bit_512k_0_avalon_slave_0_unreg_firsttransfer : sram_16bit_512k_0_avalon_slave_0_reg_firsttransfer;
//sram_16bit_512k_0_avalon_slave_0_unreg_firsttransfer first transaction, which is an e_assign
assign sram_16bit_512k_0_avalon_slave_0_unreg_firsttransfer = ~(sram_16bit_512k_0_avalon_slave_0_slavearbiterlockenable & sram_16bit_512k_0_avalon_slave_0_any_continuerequest);
//sram_16bit_512k_0_avalon_slave_0_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sram_16bit_512k_0_avalon_slave_0_reg_firsttransfer <= 1'b1;
else if (sram_16bit_512k_0_avalon_slave_0_begins_xfer)
sram_16bit_512k_0_avalon_slave_0_reg_firsttransfer <= sram_16bit_512k_0_avalon_slave_0_unreg_firsttransfer;
end
//sram_16bit_512k_0_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign sram_16bit_512k_0_avalon_slave_0_beginbursttransfer_internal = sram_16bit_512k_0_avalon_slave_0_begins_xfer;
//sram_16bit_512k_0_avalon_slave_0_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
assign sram_16bit_512k_0_avalon_slave_0_arbitration_holdoff_internal = sram_16bit_512k_0_avalon_slave_0_begins_xfer & sram_16bit_512k_0_avalon_slave_0_firsttransfer;
//~sram_16bit_512k_0_avalon_slave_0_read_n assignment, which is an e_mux
assign sram_16bit_512k_0_avalon_slave_0_read_n = ~(((cpu_data_master_granted_sram_16bit_512k_0_avalon_slave_0 & cpu_data_master_read) | (cpu_instruction_master_granted_sram_16bit_512k_0_avalon_slave_0 & cpu_instruction_master_read))& ~sram_16bit_512k_0_avalon_slave_0_begins_xfer);
//~sram_16bit_512k_0_avalon_slave_0_write_n assignment, which is an e_mux
assign sram_16bit_512k_0_avalon_slave_0_write_n = ~(((cpu_data_master_granted_sram_16bit_512k_0_avalon_slave_0 & cpu_data_master_write)) & ~sram_16bit_512k_0_avalon_slave_0_begins_xfer & (sram_16bit_512k_0_avalon_slave_0_wait_counter >= 1));
assign shifted_address_to_sram_16bit_512k_0_avalon_slave_0_from_cpu_data_master = {cpu_data_master_address_to_slave >> 2,
cpu_data_master_dbs_address[1],
{1 {1'b0}}};
//sram_16bit_512k_0_avalon_slave_0_address mux, which is an e_mux
assign sram_16bit_512k_0_avalon_slave_0_address = (cpu_data_master_granted_sram_16bit_512k_0_avalon_slave_0)? (shifted_address_to_sram_16bit_512k_0_avalon_slave_0_from_cpu_data_master >> 1) :
(shifted_address_to_sram_16bit_512k_0_avalon_slave_0_from_cpu_instruction_master >> 1);
assign shifted_address_to_sram_16bit_512k_0_avalon_slave_0_from_cpu_instruction_master = {cpu_instruction_master_address_to_slave >> 2,
cpu_instruction_master_dbs_address[1],
{1 {1'b0}}};
//d1_sram_16bit_512k_0_avalon_slave_0_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_sram_16bit_512k_0_avalon_slave_0_end_xfer <= 1;
else
d1_sram_16bit_512k_0_avalon_slave_0_end_xfer <= sram_16bit_512k_0_avalon_slave_0_end_xfer;
end
//sram_16bit_512k_0_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
assign sram_16bit_512k_0_avalon_slave_0_waits_for_read = sram_16bit_512k_0_avalon_slave_0_in_a_read_cycle & sram_16bit_512k_0_avalon_slave_0_begins_xfer;
//sram_16bit_512k_0_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
assign sram_16bit_512k_0_avalon_slave_0_in_a_read_cycle = (cpu_data_master_granted_sram_16bit_512k_0_avalon_slave_0 & cpu_data_master_read) | (cpu_instruction_master_granted_sram_16bit_512k_0_avalon_slave_0 & cpu_instruction_master_read);
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = sram_16bit_512k_0_avalon_slave_0_in_a_read_cycle;
//sram_16bit_512k_0_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
assign sram_16bit_512k_0_avalon_slave_0_waits_for_write = sram_16bit_512k_0_avalon_slave_0_in_a_write_cycle & wait_for_sram_16bit_512k_0_avalon_slave_0_counter;
//sram_16bit_512k_0_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
assign sram_16bit_512k_0_avalon_slave_0_in_a_write_cycle = cpu_data_master_granted_sram_16bit_512k_0_avalon_slave_0 & cpu_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = sram_16bit_512k_0_avalon_slave_0_in_a_write_cycle;
assign sram_16bit_512k_0_avalon_slave_0_wait_counter_eq_0 = sram_16bit_512k_0_avalon_slave_0_wait_counter == 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sram_16bit_512k_0_avalon_slave_0_wait_counter <= 0;
else
sram_16bit_512k_0_avalon_slave_0_wait_counter <= sram_16bit_512k_0_avalon_slave_0_counter_load_value;
end
assign sram_16bit_512k_0_avalon_slave_0_counter_load_value = ((sram_16bit_512k_0_avalon_slave_0_in_a_write_cycle & sram_16bit_512k_0_avalon_slave_0_begins_xfer))? 1 :
(~sram_16bit_512k_0_avalon_slave_0_wait_counter_eq_0)? sram_16bit_512k_0_avalon_slave_0_wait_counter - 1 :
0;
assign wait_for_sram_16bit_512k_0_avalon_slave_0_counter = sram_16bit_512k_0_avalon_slave_0_begins_xfer | ~sram_16bit_512k_0_avalon_slave_0_wait_counter_eq_0;
//~sram_16bit_512k_0_avalon_slave_0_byteenable_n byte enable port mux, which is an e_mux
assign sram_16bit_512k_0_avalon_slave_0_byteenable_n = ~((cpu_data_master_granted_sram_16bit_512k_0_avalon_slave_0)? cpu_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0 :
-1);
assign {cpu_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0_segment_1,
cpu_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0_segment_0} = cpu_data_master_byteenable;
assign cpu_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0 = ((cpu_data_master_dbs_address[1] == 0))? cpu_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0_segment_0 :
cpu_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0_segment_1;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//sram_16bit_512k_0/avalon_slave_0 enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_data_master_granted_sram_16bit_512k_0_avalon_slave_0 + cpu_instruction_master_granted_sram_16bit_512k_0_avalon_slave_0 > 1)
begin
$write("%0d ns: > 1 of grant signals are active simultaneously", $time);
$stop;
end
end
//saved_grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_data_master_saved_grant_sram_16bit_512k_0_avalon_slave_0 + cpu_instruction_master_saved_grant_sram_16bit_512k_0_avalon_slave_0 > 1)
begin
$write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module timer_s1_arbitrator (
// inputs:
clk,
cpu_data_master_address_to_slave,
cpu_data_master_read,
cpu_data_master_waitrequest,
cpu_data_master_write,
cpu_data_master_writedata,
reset_n,
timer_s1_irq,
timer_s1_readdata,
// outputs:
cpu_data_master_granted_timer_s1,
cpu_data_master_qualified_request_timer_s1,
cpu_data_master_read_data_valid_timer_s1,
cpu_data_master_requests_timer_s1,
d1_timer_s1_end_xfer,
timer_s1_address,
timer_s1_chipselect,
timer_s1_irq_from_sa,
timer_s1_readdata_from_sa,
timer_s1_reset_n,
timer_s1_write_n,
timer_s1_writedata
)
;
output cpu_data_master_granted_timer_s1;
output cpu_data_master_qualified_request_timer_s1;
output cpu_data_master_read_data_valid_timer_s1;
output cpu_data_master_requests_timer_s1;
output d1_timer_s1_end_xfer;
output [ 2: 0] timer_s1_address;
output timer_s1_chipselect;
output timer_s1_irq_from_sa;
output [ 15: 0] timer_s1_readdata_from_sa;
output timer_s1_reset_n;
output timer_s1_write_n;
output [ 15: 0] timer_s1_writedata;
input clk;
input [ 23: 0] cpu_data_master_address_to_slave;
input cpu_data_master_read;
input cpu_data_master_waitrequest;
input cpu_data_master_write;
input [ 31: 0] cpu_data_master_writedata;
input reset_n;
input timer_s1_irq;
input [ 15: 0] timer_s1_readdata;
wire cpu_data_master_arbiterlock;
wire cpu_data_master_arbiterlock2;
wire cpu_data_master_continuerequest;
wire cpu_data_master_granted_timer_s1;
wire cpu_data_master_qualified_request_timer_s1;
wire cpu_data_master_read_data_valid_timer_s1;
wire cpu_data_master_requests_timer_s1;
wire cpu_data_master_saved_grant_timer_s1;
reg d1_reasons_to_wait;
reg d1_timer_s1_end_xfer;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_timer_s1;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 23: 0] shifted_address_to_timer_s1_from_cpu_data_master;
wire [ 2: 0] timer_s1_address;
wire timer_s1_allgrants;
wire timer_s1_allow_new_arb_cycle;
wire timer_s1_any_bursting_master_saved_grant;
wire timer_s1_any_continuerequest;
wire timer_s1_arb_counter_enable;
reg [ 2: 0] timer_s1_arb_share_counter;
wire [ 2: 0] timer_s1_arb_share_counter_next_value;
wire [ 2: 0] timer_s1_arb_share_set_values;
wire timer_s1_beginbursttransfer_internal;
wire timer_s1_begins_xfer;
wire timer_s1_chipselect;
wire timer_s1_end_xfer;
wire timer_s1_firsttransfer;
wire timer_s1_grant_vector;
wire timer_s1_in_a_read_cycle;
wire timer_s1_in_a_write_cycle;
wire timer_s1_irq_from_sa;
wire timer_s1_master_qreq_vector;
wire timer_s1_non_bursting_master_requests;
wire [ 15: 0] timer_s1_readdata_from_sa;
reg timer_s1_reg_firsttransfer;
wire timer_s1_reset_n;
reg timer_s1_slavearbiterlockenable;
wire timer_s1_slavearbiterlockenable2;
wire timer_s1_unreg_firsttransfer;
wire timer_s1_waits_for_read;
wire timer_s1_waits_for_write;
wire timer_s1_write_n;
wire [ 15: 0] timer_s1_writedata;
wire wait_for_timer_s1_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~timer_s1_end_xfer;
end
assign timer_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_timer_s1));
//assign timer_s1_readdata_from_sa = timer_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign timer_s1_readdata_from_sa = timer_s1_readdata;
assign cpu_data_master_requests_timer_s1 = ({cpu_data_master_address_to_slave[23 : 5] , 5'b0} == 24'hb04000) & (cpu_data_master_read | cpu_data_master_write);
//timer_s1_arb_share_counter set values, which is an e_mux
assign timer_s1_arb_share_set_values = 1;
//timer_s1_non_bursting_master_requests mux, which is an e_mux
assign timer_s1_non_bursting_master_requests = cpu_data_master_requests_timer_s1;
//timer_s1_any_bursting_master_saved_grant mux, which is an e_mux
assign timer_s1_any_bursting_master_saved_grant = 0;
//timer_s1_arb_share_counter_next_value assignment, which is an e_assign
assign timer_s1_arb_share_counter_next_value = timer_s1_firsttransfer ? (timer_s1_arb_share_set_values - 1) : |timer_s1_arb_share_counter ? (timer_s1_arb_share_counter - 1) : 0;
//timer_s1_allgrants all slave grants, which is an e_mux
assign timer_s1_allgrants = |timer_s1_grant_vector;
//timer_s1_end_xfer assignment, which is an e_assign
assign timer_s1_end_xfer = ~(timer_s1_waits_for_read | timer_s1_waits_for_write);
//end_xfer_arb_share_counter_term_timer_s1 arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_timer_s1 = timer_s1_end_xfer & (~timer_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//timer_s1_arb_share_counter arbitration counter enable, which is an e_assign
assign timer_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_timer_s1 & timer_s1_allgrants) | (end_xfer_arb_share_counter_term_timer_s1 & ~timer_s1_non_bursting_master_requests);
//timer_s1_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timer_s1_arb_share_counter <= 0;
else if (timer_s1_arb_counter_enable)
timer_s1_arb_share_counter <= timer_s1_arb_share_counter_next_value;
end
//timer_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timer_s1_slavearbiterlockenable <= 0;
else if ((|timer_s1_master_qreq_vector & end_xfer_arb_share_counter_term_timer_s1) | (end_xfer_arb_share_counter_term_timer_s1 & ~timer_s1_non_bursting_master_requests))
timer_s1_slavearbiterlockenable <= |timer_s1_arb_share_counter_next_value;
end
//cpu/data_master timer/s1 arbiterlock, which is an e_assign
assign cpu_data_master_arbiterlock = timer_s1_slavearbiterlockenable & cpu_data_master_continuerequest;
//timer_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign timer_s1_slavearbiterlockenable2 = |timer_s1_arb_share_counter_next_value;
//cpu/data_master timer/s1 arbiterlock2, which is an e_assign
assign cpu_data_master_arbiterlock2 = timer_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;
//timer_s1_any_continuerequest at least one master continues requesting, which is an e_assign
assign timer_s1_any_continuerequest = 1;
//cpu_data_master_continuerequest continued request, which is an e_assign
assign cpu_data_master_continuerequest = 1;
assign cpu_data_master_qualified_request_timer_s1 = cpu_data_master_requests_timer_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
//timer_s1_writedata mux, which is an e_mux
assign timer_s1_writedata = cpu_data_master_writedata;
//master is always granted when requested
assign cpu_data_master_granted_timer_s1 = cpu_data_master_qualified_request_timer_s1;
//cpu/data_master saved-grant timer/s1, which is an e_assign
assign cpu_data_master_saved_grant_timer_s1 = cpu_data_master_requests_timer_s1;
//allow new arb cycle for timer/s1, which is an e_assign
assign timer_s1_allow_new_arb_cycle = 1;
//placeholder chosen master
assign timer_s1_grant_vector = 1;
//placeholder vector of master qualified-requests
assign timer_s1_master_qreq_vector = 1;
//timer_s1_reset_n assignment, which is an e_assign
assign timer_s1_reset_n = reset_n;
assign timer_s1_chipselect = cpu_data_master_granted_timer_s1;
//timer_s1_firsttransfer first transaction, which is an e_assign
assign timer_s1_firsttransfer = timer_s1_begins_xfer ? timer_s1_unreg_firsttransfer : timer_s1_reg_firsttransfer;
//timer_s1_unreg_firsttransfer first transaction, which is an e_assign
assign timer_s1_unreg_firsttransfer = ~(timer_s1_slavearbiterlockenable & timer_s1_any_continuerequest);
//timer_s1_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timer_s1_reg_firsttransfer <= 1'b1;
else if (timer_s1_begins_xfer)
timer_s1_reg_firsttransfer <= timer_s1_unreg_firsttransfer;
end
//timer_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign timer_s1_beginbursttransfer_internal = timer_s1_begins_xfer;
//~timer_s1_write_n assignment, which is an e_mux
assign timer_s1_write_n = ~(cpu_data_master_granted_timer_s1 & cpu_data_master_write);
assign shifted_address_to_timer_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
//timer_s1_address mux, which is an e_mux
assign timer_s1_address = shifted_address_to_timer_s1_from_cpu_data_master >> 2;
//d1_timer_s1_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_timer_s1_end_xfer <= 1;
else
d1_timer_s1_end_xfer <= timer_s1_end_xfer;
end
//timer_s1_waits_for_read in a cycle, which is an e_mux
assign timer_s1_waits_for_read = timer_s1_in_a_read_cycle & timer_s1_begins_xfer;
//timer_s1_in_a_read_cycle assignment, which is an e_assign
assign timer_s1_in_a_read_cycle = cpu_data_master_granted_timer_s1 & cpu_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = timer_s1_in_a_read_cycle;
//timer_s1_waits_for_write in a cycle, which is an e_mux
assign timer_s1_waits_for_write = timer_s1_in_a_write_cycle & 0;
//timer_s1_in_a_write_cycle assignment, which is an e_assign
assign timer_s1_in_a_write_cycle = cpu_data_master_granted_timer_s1 & cpu_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = timer_s1_in_a_write_cycle;
assign wait_for_timer_s1_counter = 0;
//assign timer_s1_irq_from_sa = timer_s1_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
assign timer_s1_irq_from_sa = timer_s1_irq;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//timer/s1 enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module tri_state_bridge_avalon_slave_arbitrator (
// inputs:
clk,
cpu_data_master_address_to_slave,
cpu_data_master_byteenable,
cpu_data_master_dbs_address,
cpu_data_master_dbs_write_8,
cpu_data_master_no_byte_enables_and_last_term,
cpu_data_master_read,
cpu_data_master_write,
cpu_instruction_master_address_to_slave,
cpu_instruction_master_dbs_address,
cpu_instruction_master_latency_counter,
cpu_instruction_master_read,
reset_n,
// outputs:
cfi_flash_s1_wait_counter_eq_0,
cfi_flash_s1_wait_counter_eq_1,
cpu_data_master_byteenable_cfi_flash_s1,
cpu_data_master_granted_cfi_flash_s1,
cpu_data_master_qualified_request_cfi_flash_s1,
cpu_data_master_read_data_valid_cfi_flash_s1,
cpu_data_master_requests_cfi_flash_s1,
cpu_instruction_master_granted_cfi_flash_s1,
cpu_instruction_master_qualified_request_cfi_flash_s1,
cpu_instruction_master_read_data_valid_cfi_flash_s1,
cpu_instruction_master_requests_cfi_flash_s1,
d1_tri_state_bridge_avalon_slave_end_xfer,
incoming_tri_state_bridge_data,
incoming_tri_state_bridge_data_with_Xs_converted_to_0,
registered_cpu_data_master_read_data_valid_cfi_flash_s1,
select_n_to_the_cfi_flash,
tri_state_bridge_address,
tri_state_bridge_data,
tri_state_bridge_readn,
write_n_to_the_cfi_flash
)
;
output cfi_flash_s1_wait_counter_eq_0;
output cfi_flash_s1_wait_counter_eq_1;
output cpu_data_master_byteenable_cfi_flash_s1;
output cpu_data_master_granted_cfi_flash_s1;
output cpu_data_master_qualified_request_cfi_flash_s1;
output cpu_data_master_read_data_valid_cfi_flash_s1;
output cpu_data_master_requests_cfi_flash_s1;
output cpu_instruction_master_granted_cfi_flash_s1;
output cpu_instruction_master_qualified_request_cfi_flash_s1;
output cpu_instruction_master_read_data_valid_cfi_flash_s1;
output cpu_instruction_master_requests_cfi_flash_s1;
output d1_tri_state_bridge_avalon_slave_end_xfer;
output [ 7: 0] incoming_tri_state_bridge_data;
output [ 7: 0] incoming_tri_state_bridge_data_with_Xs_converted_to_0;
output registered_cpu_data_master_read_data_valid_cfi_flash_s1;
output select_n_to_the_cfi_flash;
output [ 21: 0] tri_state_bridge_address;
inout [ 7: 0] tri_state_bridge_data;
output tri_state_bridge_readn;
output write_n_to_the_cfi_flash;
input clk;
input [ 23: 0] cpu_data_master_address_to_slave;
input [ 3: 0] cpu_data_master_byteenable;
input [ 1: 0] cpu_data_master_dbs_address;
input [ 7: 0] cpu_data_master_dbs_write_8;
input cpu_data_master_no_byte_enables_and_last_term;
input cpu_data_master_read;
input cpu_data_master_write;
input [ 23: 0] cpu_instruction_master_address_to_slave;
input [ 1: 0] cpu_instruction_master_dbs_address;
input [ 1: 0] cpu_instruction_master_latency_counter;
input cpu_instruction_master_read;
input reset_n;
wire [ 2: 0] cfi_flash_s1_counter_load_value;
wire cfi_flash_s1_in_a_read_cycle;
wire cfi_flash_s1_in_a_write_cycle;
wire cfi_flash_s1_pretend_byte_enable;
reg [ 2: 0] cfi_flash_s1_wait_counter;
wire cfi_flash_s1_wait_counter_eq_0;
wire cfi_flash_s1_wait_counter_eq_1;
wire cfi_flash_s1_waits_for_read;
wire cfi_flash_s1_waits_for_write;
wire cfi_flash_s1_with_write_latency;
wire cpu_data_master_arbiterlock;
wire cpu_data_master_arbiterlock2;
wire cpu_data_master_byteenable_cfi_flash_s1;
wire cpu_data_master_byteenable_cfi_flash_s1_segment_0;
wire cpu_data_master_byteenable_cfi_flash_s1_segment_1;
wire cpu_data_master_byteenable_cfi_flash_s1_segment_2;
wire cpu_data_master_byteenable_cfi_flash_s1_segment_3;
wire cpu_data_master_continuerequest;
wire cpu_data_master_granted_cfi_flash_s1;
wire cpu_data_master_qualified_request_cfi_flash_s1;
wire cpu_data_master_read_data_valid_cfi_flash_s1;
reg [ 1: 0] cpu_data_master_read_data_valid_cfi_flash_s1_shift_register;
wire cpu_data_master_read_data_valid_cfi_flash_s1_shift_register_in;
wire cpu_data_master_requests_cfi_flash_s1;
wire cpu_data_master_saved_grant_cfi_flash_s1;
wire cpu_instruction_master_arbiterlock;
wire cpu_instruction_master_arbiterlock2;
wire cpu_instruction_master_continuerequest;
wire cpu_instruction_master_granted_cfi_flash_s1;
wire cpu_instruction_master_qualified_request_cfi_flash_s1;
wire cpu_instruction_master_read_data_valid_cfi_flash_s1;
reg [ 1: 0] cpu_instruction_master_read_data_valid_cfi_flash_s1_shift_register;
wire cpu_instruction_master_read_data_valid_cfi_flash_s1_shift_register_in;
wire cpu_instruction_master_requests_cfi_flash_s1;
wire cpu_instruction_master_saved_grant_cfi_flash_s1;
reg d1_in_a_write_cycle /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON" */;
reg [ 7: 0] d1_outgoing_tri_state_bridge_data /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg d1_reasons_to_wait;
reg d1_tri_state_bridge_avalon_slave_end_xfer;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_tri_state_bridge_avalon_slave;
wire in_a_read_cycle;
wire in_a_write_cycle;
reg [ 7: 0] incoming_tri_state_bridge_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON" */;
wire incoming_tri_state_bridge_data_bit_0_is_x;
wire incoming_tri_state_bridge_data_bit_1_is_x;
wire incoming_tri_state_bridge_data_bit_2_is_x;
wire incoming_tri_state_bridge_data_bit_3_is_x;
wire incoming_tri_state_bridge_data_bit_4_is_x;
wire incoming_tri_state_bridge_data_bit_5_is_x;
wire incoming_tri_state_bridge_data_bit_6_is_x;
wire incoming_tri_state_bridge_data_bit_7_is_x;
wire [ 7: 0] incoming_tri_state_bridge_data_with_Xs_converted_to_0;
reg last_cycle_cpu_data_master_granted_slave_cfi_flash_s1;
reg last_cycle_cpu_instruction_master_granted_slave_cfi_flash_s1;
wire [ 7: 0] outgoing_tri_state_bridge_data;
wire [ 1: 0] p1_cpu_data_master_read_data_valid_cfi_flash_s1_shift_register;
wire [ 1: 0] p1_cpu_instruction_master_read_data_valid_cfi_flash_s1_shift_register;
wire p1_select_n_to_the_cfi_flash;
wire [ 21: 0] p1_tri_state_bridge_address;
wire p1_tri_state_bridge_readn;
wire p1_write_n_to_the_cfi_flash;
wire registered_cpu_data_master_read_data_valid_cfi_flash_s1;
reg select_n_to_the_cfi_flash /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
wire time_to_write;
reg [ 21: 0] tri_state_bridge_address /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
wire tri_state_bridge_avalon_slave_allgrants;
wire tri_state_bridge_avalon_slave_allow_new_arb_cycle;
wire tri_state_bridge_avalon_slave_any_bursting_master_saved_grant;
wire tri_state_bridge_avalon_slave_any_continuerequest;
reg [ 1: 0] tri_state_bridge_avalon_slave_arb_addend;
wire tri_state_bridge_avalon_slave_arb_counter_enable;
reg [ 2: 0] tri_state_bridge_avalon_slave_arb_share_counter;
wire [ 2: 0] tri_state_bridge_avalon_slave_arb_share_counter_next_value;
wire [ 2: 0] tri_state_bridge_avalon_slave_arb_share_set_values;
wire [ 1: 0] tri_state_bridge_avalon_slave_arb_winner;
wire tri_state_bridge_avalon_slave_arbitration_holdoff_internal;
wire tri_state_bridge_avalon_slave_beginbursttransfer_internal;
wire tri_state_bridge_avalon_slave_begins_xfer;
wire [ 3: 0] tri_state_bridge_avalon_slave_chosen_master_double_vector;
wire [ 1: 0] tri_state_bridge_avalon_slave_chosen_master_rot_left;
wire tri_state_bridge_avalon_slave_end_xfer;
wire tri_state_bridge_avalon_slave_firsttransfer;
wire [ 1: 0] tri_state_bridge_avalon_slave_grant_vector;
wire [ 1: 0] tri_state_bridge_avalon_slave_master_qreq_vector;
wire tri_state_bridge_avalon_slave_non_bursting_master_requests;
wire tri_state_bridge_avalon_slave_read_pending;
reg tri_state_bridge_avalon_slave_reg_firsttransfer;
reg [ 1: 0] tri_state_bridge_avalon_slave_saved_chosen_master_vector;
reg tri_state_bridge_avalon_slave_slavearbiterlockenable;
wire tri_state_bridge_avalon_slave_slavearbiterlockenable2;
wire tri_state_bridge_avalon_slave_unreg_firsttransfer;
wire tri_state_bridge_avalon_slave_write_pending;
wire [ 7: 0] tri_state_bridge_data;
reg tri_state_bridge_readn /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
wire wait_for_cfi_flash_s1_counter;
reg write_n_to_the_cfi_flash /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~tri_state_bridge_avalon_slave_end_xfer;
end
assign tri_state_bridge_avalon_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_cfi_flash_s1 | cpu_instruction_master_qualified_request_cfi_flash_s1));
assign cpu_data_master_requests_cfi_flash_s1 = ({cpu_data_master_address_to_slave[23 : 22] , 22'b0} == 24'h400000) & (cpu_data_master_read | cpu_data_master_write);
//~select_n_to_the_cfi_flash of type chipselect to ~p1_select_n_to_the_cfi_flash, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
select_n_to_the_cfi_flash <= ~0;
else
select_n_to_the_cfi_flash <= p1_select_n_to_the_cfi_flash;
end
assign tri_state_bridge_avalon_slave_write_pending = 0;
//tri_state_bridge/avalon_slave read pending calc, which is an e_assign
assign tri_state_bridge_avalon_slave_read_pending = 0;
//registered rdv signal_name registered_cpu_data_master_read_data_valid_cfi_flash_s1 assignment, which is an e_assign
assign registered_cpu_data_master_read_data_valid_cfi_flash_s1 = cpu_data_master_read_data_valid_cfi_flash_s1_shift_register[0];
//tri_state_bridge_avalon_slave_arb_share_counter set values, which is an e_mux
assign tri_state_bridge_avalon_slave_arb_share_set_values = (cpu_data_master_granted_cfi_flash_s1)? 4 :
(cpu_instruction_master_granted_cfi_flash_s1)? 4 :
(cpu_data_master_granted_cfi_flash_s1)? 4 :
(cpu_instruction_master_granted_cfi_flash_s1)? 4 :
1;
//tri_state_bridge_avalon_slave_non_bursting_master_requests mux, which is an e_mux
assign tri_state_bridge_avalon_slave_non_bursting_master_requests = cpu_data_master_requests_cfi_flash_s1 |
cpu_instruction_master_requests_cfi_flash_s1 |
cpu_data_master_requests_cfi_flash_s1 |
cpu_instruction_master_requests_cfi_flash_s1;
//tri_state_bridge_avalon_slave_any_bursting_master_saved_grant mux, which is an e_mux
assign tri_state_bridge_avalon_slave_any_bursting_master_saved_grant = 0;
//tri_state_bridge_avalon_slave_arb_share_counter_next_value assignment, which is an e_assign
assign tri_state_bridge_avalon_slave_arb_share_counter_next_value = tri_state_bridge_avalon_slave_firsttransfer ? (tri_state_bridge_avalon_slave_arb_share_set_values - 1) : |tri_state_bridge_avalon_slave_arb_share_counter ? (tri_state_bridge_avalon_slave_arb_share_counter - 1) : 0;
//tri_state_bridge_avalon_slave_allgrants all slave grants, which is an e_mux
assign tri_state_bridge_avalon_slave_allgrants = (|tri_state_bridge_avalon_slave_grant_vector) |
(|tri_state_bridge_avalon_slave_grant_vector) |
(|tri_state_bridge_avalon_slave_grant_vector) |
(|tri_state_bridge_avalon_slave_grant_vector);
//tri_state_bridge_avalon_slave_end_xfer assignment, which is an e_assign
assign tri_state_bridge_avalon_slave_end_xfer = ~(cfi_flash_s1_waits_for_read | cfi_flash_s1_waits_for_write);
//end_xfer_arb_share_counter_term_tri_state_bridge_avalon_slave arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_tri_state_bridge_avalon_slave = tri_state_bridge_avalon_slave_end_xfer & (~tri_state_bridge_avalon_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//tri_state_bridge_avalon_slave_arb_share_counter arbitration counter enable, which is an e_assign
assign tri_state_bridge_avalon_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_tri_state_bridge_avalon_slave & tri_state_bridge_avalon_slave_allgrants) | (end_xfer_arb_share_counter_term_tri_state_bridge_avalon_slave & ~tri_state_bridge_avalon_slave_non_bursting_master_requests);
//tri_state_bridge_avalon_slave_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tri_state_bridge_avalon_slave_arb_share_counter <= 0;
else if (tri_state_bridge_avalon_slave_arb_counter_enable)
tri_state_bridge_avalon_slave_arb_share_counter <= tri_state_bridge_avalon_slave_arb_share_counter_next_value;
end
//tri_state_bridge_avalon_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tri_state_bridge_avalon_slave_slavearbiterlockenable <= 0;
else if ((|tri_state_bridge_avalon_slave_master_qreq_vector & end_xfer_arb_share_counter_term_tri_state_bridge_avalon_slave) | (end_xfer_arb_share_counter_term_tri_state_bridge_avalon_slave & ~tri_state_bridge_avalon_slave_non_bursting_master_requests))
tri_state_bridge_avalon_slave_slavearbiterlockenable <= |tri_state_bridge_avalon_slave_arb_share_counter_next_value;
end
//cpu/data_master tri_state_bridge/avalon_slave arbiterlock, which is an e_assign
assign cpu_data_master_arbiterlock = tri_state_bridge_avalon_slave_slavearbiterlockenable & cpu_data_master_continuerequest;
//tri_state_bridge_avalon_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign tri_state_bridge_avalon_slave_slavearbiterlockenable2 = |tri_state_bridge_avalon_slave_arb_share_counter_next_value;
//cpu/data_master tri_state_bridge/avalon_slave arbiterlock2, which is an e_assign
assign cpu_data_master_arbiterlock2 = tri_state_bridge_avalon_slave_slavearbiterlockenable2 & cpu_data_master_continuerequest;
//cpu/instruction_master tri_state_bridge/avalon_slave arbiterlock, which is an e_assign
assign cpu_instruction_master_arbiterlock = tri_state_bridge_avalon_slave_slavearbiterlockenable & cpu_instruction_master_continuerequest;
//cpu/instruction_master tri_state_bridge/avalon_slave arbiterlock2, which is an e_assign
assign cpu_instruction_master_arbiterlock2 = tri_state_bridge_avalon_slave_slavearbiterlockenable2 & cpu_instruction_master_continuerequest;
//cpu/instruction_master granted cfi_flash/s1 last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_instruction_master_granted_slave_cfi_flash_s1 <= 0;
else
last_cycle_cpu_instruction_master_granted_slave_cfi_flash_s1 <= cpu_instruction_master_saved_grant_cfi_flash_s1 ? 1 : (tri_state_bridge_avalon_slave_arbitration_holdoff_internal | ~cpu_instruction_master_requests_cfi_flash_s1) ? 0 : last_cycle_cpu_instruction_master_granted_slave_cfi_flash_s1;
end
//cpu_instruction_master_continuerequest continued request, which is an e_mux
assign cpu_instruction_master_continuerequest = last_cycle_cpu_instruction_master_granted_slave_cfi_flash_s1 & cpu_instruction_master_requests_cfi_flash_s1;
//tri_state_bridge_avalon_slave_any_continuerequest at least one master continues requesting, which is an e_mux
assign tri_state_bridge_avalon_slave_any_continuerequest = cpu_instruction_master_continuerequest |
cpu_data_master_continuerequest;
assign cpu_data_master_qualified_request_cfi_flash_s1 = cpu_data_master_requests_cfi_flash_s1 & ~((cpu_data_master_read & (tri_state_bridge_avalon_slave_write_pending | (tri_state_bridge_avalon_slave_read_pending) | (|cpu_data_master_read_data_valid_cfi_flash_s1_shift_register))) | ((tri_state_bridge_avalon_slave_read_pending | cpu_data_master_no_byte_enables_and_last_term | !cpu_data_master_byteenable_cfi_flash_s1) & cpu_data_master_write) | cpu_instruction_master_arbiterlock);
//cpu_data_master_read_data_valid_cfi_flash_s1_shift_register_in mux for readlatency shift register, which is an e_mux
assign cpu_data_master_read_data_valid_cfi_flash_s1_shift_register_in = cpu_data_master_granted_cfi_flash_s1 & cpu_data_master_read & ~cfi_flash_s1_waits_for_read & ~(|cpu_data_master_read_data_valid_cfi_flash_s1_shift_register);
//shift register p1 cpu_data_master_read_data_valid_cfi_flash_s1_shift_register in if flush, otherwise shift left, which is an e_mux
assign p1_cpu_data_master_read_data_valid_cfi_flash_s1_shift_register = {cpu_data_master_read_data_valid_cfi_flash_s1_shift_register, cpu_data_master_read_data_valid_cfi_flash_s1_shift_register_in};
//cpu_data_master_read_data_valid_cfi_flash_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_data_master_read_data_valid_cfi_flash_s1_shift_register <= 0;
else
cpu_data_master_read_data_valid_cfi_flash_s1_shift_register <= p1_cpu_data_master_read_data_valid_cfi_flash_s1_shift_register;
end
//local readdatavalid cpu_data_master_read_data_valid_cfi_flash_s1, which is an e_mux
assign cpu_data_master_read_data_valid_cfi_flash_s1 = cpu_data_master_read_data_valid_cfi_flash_s1_shift_register[1];
//tri_state_bridge_data register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
incoming_tri_state_bridge_data <= 0;
else
incoming_tri_state_bridge_data <= tri_state_bridge_data;
end
//cfi_flash_s1_with_write_latency assignment, which is an e_assign
assign cfi_flash_s1_with_write_latency = in_a_write_cycle & (cpu_data_master_qualified_request_cfi_flash_s1 | cpu_instruction_master_qualified_request_cfi_flash_s1);
//time to write the data, which is an e_mux
assign time_to_write = (cfi_flash_s1_with_write_latency)? 1 :
0;
//d1_outgoing_tri_state_bridge_data register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_outgoing_tri_state_bridge_data <= 0;
else
d1_outgoing_tri_state_bridge_data <= outgoing_tri_state_bridge_data;
end
//write cycle delayed by 1, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_in_a_write_cycle <= 0;
else
d1_in_a_write_cycle <= time_to_write;
end
//d1_outgoing_tri_state_bridge_data tristate driver, which is an e_assign
assign tri_state_bridge_data = (d1_in_a_write_cycle)? d1_outgoing_tri_state_bridge_data:{8{1'bz}};
//outgoing_tri_state_bridge_data mux, which is an e_mux
assign outgoing_tri_state_bridge_data = cpu_data_master_dbs_write_8;
assign cpu_instruction_master_requests_cfi_flash_s1 = (({cpu_instruction_master_address_to_slave[23 : 22] , 22'b0} == 24'h400000) & (cpu_instruction_master_read)) & cpu_instruction_master_read;
//cpu/data_master granted cfi_flash/s1 last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_data_master_granted_slave_cfi_flash_s1 <= 0;
else
last_cycle_cpu_data_master_granted_slave_cfi_flash_s1 <= cpu_data_master_saved_grant_cfi_flash_s1 ? 1 : (tri_state_bridge_avalon_slave_arbitration_holdoff_internal | ~cpu_data_master_requests_cfi_flash_s1) ? 0 : last_cycle_cpu_data_master_granted_slave_cfi_flash_s1;
end
//cpu_data_master_continuerequest continued request, which is an e_mux
assign cpu_data_master_continuerequest = last_cycle_cpu_data_master_granted_slave_cfi_flash_s1 & cpu_data_master_requests_cfi_flash_s1;
assign cpu_instruction_master_qualified_request_cfi_flash_s1 = cpu_instruction_master_requests_cfi_flash_s1 & ~((cpu_instruction_master_read & (tri_state_bridge_avalon_slave_write_pending | (tri_state_bridge_avalon_slave_read_pending) | (2 < cpu_instruction_master_latency_counter))) | cpu_data_master_arbiterlock);
//cpu_instruction_master_read_data_valid_cfi_flash_s1_shift_register_in mux for readlatency shift register, which is an e_mux
assign cpu_instruction_master_read_data_valid_cfi_flash_s1_shift_register_in = cpu_instruction_master_granted_cfi_flash_s1 & cpu_instruction_master_read & ~cfi_flash_s1_waits_for_read;
//shift register p1 cpu_instruction_master_read_data_valid_cfi_flash_s1_shift_register in if flush, otherwise shift left, which is an e_mux
assign p1_cpu_instruction_master_read_data_valid_cfi_flash_s1_shift_register = {cpu_instruction_master_read_data_valid_cfi_flash_s1_shift_register, cpu_instruction_master_read_data_valid_cfi_flash_s1_shift_register_in};
//cpu_instruction_master_read_data_valid_cfi_flash_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_instruction_master_read_data_valid_cfi_flash_s1_shift_register <= 0;
else
cpu_instruction_master_read_data_valid_cfi_flash_s1_shift_register <= p1_cpu_instruction_master_read_data_valid_cfi_flash_s1_shift_register;
end
//local readdatavalid cpu_instruction_master_read_data_valid_cfi_flash_s1, which is an e_mux
assign cpu_instruction_master_read_data_valid_cfi_flash_s1 = cpu_instruction_master_read_data_valid_cfi_flash_s1_shift_register[1];
//allow new arb cycle for tri_state_bridge/avalon_slave, which is an e_assign
assign tri_state_bridge_avalon_slave_allow_new_arb_cycle = ~cpu_data_master_arbiterlock & ~cpu_instruction_master_arbiterlock;
//cpu/instruction_master assignment into master qualified-requests vector for cfi_flash/s1, which is an e_assign
assign tri_state_bridge_avalon_slave_master_qreq_vector[0] = cpu_instruction_master_qualified_request_cfi_flash_s1;
//cpu/instruction_master grant cfi_flash/s1, which is an e_assign
assign cpu_instruction_master_granted_cfi_flash_s1 = tri_state_bridge_avalon_slave_grant_vector[0];
//cpu/instruction_master saved-grant cfi_flash/s1, which is an e_assign
assign cpu_instruction_master_saved_grant_cfi_flash_s1 = tri_state_bridge_avalon_slave_arb_winner[0] && cpu_instruction_master_requests_cfi_flash_s1;
//cpu/data_master assignment into master qualified-requests vector for cfi_flash/s1, which is an e_assign
assign tri_state_bridge_avalon_slave_master_qreq_vector[1] = cpu_data_master_qualified_request_cfi_flash_s1;
//cpu/data_master grant cfi_flash/s1, which is an e_assign
assign cpu_data_master_granted_cfi_flash_s1 = tri_state_bridge_avalon_slave_grant_vector[1];
//cpu/data_master saved-grant cfi_flash/s1, which is an e_assign
assign cpu_data_master_saved_grant_cfi_flash_s1 = tri_state_bridge_avalon_slave_arb_winner[1] && cpu_data_master_requests_cfi_flash_s1;
//tri_state_bridge/avalon_slave chosen-master double-vector, which is an e_assign
assign tri_state_bridge_avalon_slave_chosen_master_double_vector = {tri_state_bridge_avalon_slave_master_qreq_vector, tri_state_bridge_avalon_slave_master_qreq_vector} & ({~tri_state_bridge_avalon_slave_master_qreq_vector, ~tri_state_bridge_avalon_slave_master_qreq_vector} + tri_state_bridge_avalon_slave_arb_addend);
//stable onehot encoding of arb winner
assign tri_state_bridge_avalon_slave_arb_winner = (tri_state_bridge_avalon_slave_allow_new_arb_cycle & | tri_state_bridge_avalon_slave_grant_vector) ? tri_state_bridge_avalon_slave_grant_vector : tri_state_bridge_avalon_slave_saved_chosen_master_vector;
//saved tri_state_bridge_avalon_slave_grant_vector, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tri_state_bridge_avalon_slave_saved_chosen_master_vector <= 0;
else if (tri_state_bridge_avalon_slave_allow_new_arb_cycle)
tri_state_bridge_avalon_slave_saved_chosen_master_vector <= |tri_state_bridge_avalon_slave_grant_vector ? tri_state_bridge_avalon_slave_grant_vector : tri_state_bridge_avalon_slave_saved_chosen_master_vector;
end
//onehot encoding of chosen master
assign tri_state_bridge_avalon_slave_grant_vector = {(tri_state_bridge_avalon_slave_chosen_master_double_vector[1] | tri_state_bridge_avalon_slave_chosen_master_double_vector[3]),
(tri_state_bridge_avalon_slave_chosen_master_double_vector[0] | tri_state_bridge_avalon_slave_chosen_master_double_vector[2])};
//tri_state_bridge/avalon_slave chosen master rotated left, which is an e_assign
assign tri_state_bridge_avalon_slave_chosen_master_rot_left = (tri_state_bridge_avalon_slave_arb_winner << 1) ? (tri_state_bridge_avalon_slave_arb_winner << 1) : 1;
//tri_state_bridge/avalon_slave's addend for next-master-grant
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tri_state_bridge_avalon_slave_arb_addend <= 1;
else if (|tri_state_bridge_avalon_slave_grant_vector)
tri_state_bridge_avalon_slave_arb_addend <= tri_state_bridge_avalon_slave_end_xfer? tri_state_bridge_avalon_slave_chosen_master_rot_left : tri_state_bridge_avalon_slave_grant_vector;
end
assign p1_select_n_to_the_cfi_flash = ~(cpu_data_master_granted_cfi_flash_s1 | cpu_instruction_master_granted_cfi_flash_s1);
//tri_state_bridge_avalon_slave_firsttransfer first transaction, which is an e_assign
assign tri_state_bridge_avalon_slave_firsttransfer = tri_state_bridge_avalon_slave_begins_xfer ? tri_state_bridge_avalon_slave_unreg_firsttransfer : tri_state_bridge_avalon_slave_reg_firsttransfer;
//tri_state_bridge_avalon_slave_unreg_firsttransfer first transaction, which is an e_assign
assign tri_state_bridge_avalon_slave_unreg_firsttransfer = ~(tri_state_bridge_avalon_slave_slavearbiterlockenable & tri_state_bridge_avalon_slave_any_continuerequest);
//tri_state_bridge_avalon_slave_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tri_state_bridge_avalon_slave_reg_firsttransfer <= 1'b1;
else if (tri_state_bridge_avalon_slave_begins_xfer)
tri_state_bridge_avalon_slave_reg_firsttransfer <= tri_state_bridge_avalon_slave_unreg_firsttransfer;
end
//tri_state_bridge_avalon_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign tri_state_bridge_avalon_slave_beginbursttransfer_internal = tri_state_bridge_avalon_slave_begins_xfer;
//tri_state_bridge_avalon_slave_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
assign tri_state_bridge_avalon_slave_arbitration_holdoff_internal = tri_state_bridge_avalon_slave_begins_xfer & tri_state_bridge_avalon_slave_firsttransfer;
//~tri_state_bridge_readn of type read to ~p1_tri_state_bridge_readn, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tri_state_bridge_readn <= ~0;
else
tri_state_bridge_readn <= p1_tri_state_bridge_readn;
end
//~p1_tri_state_bridge_readn assignment, which is an e_mux
assign p1_tri_state_bridge_readn = ~(((cpu_data_master_granted_cfi_flash_s1 & cpu_data_master_read) | (cpu_instruction_master_granted_cfi_flash_s1 & cpu_instruction_master_read))& ~tri_state_bridge_avalon_slave_begins_xfer & (cfi_flash_s1_wait_counter < 5));
//~write_n_to_the_cfi_flash of type write to ~p1_write_n_to_the_cfi_flash, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
write_n_to_the_cfi_flash <= ~0;
else
write_n_to_the_cfi_flash <= p1_write_n_to_the_cfi_flash;
end
//~p1_write_n_to_the_cfi_flash assignment, which is an e_mux
assign p1_write_n_to_the_cfi_flash = ~(((cpu_data_master_granted_cfi_flash_s1 & cpu_data_master_write)) & ~tri_state_bridge_avalon_slave_begins_xfer & (cfi_flash_s1_wait_counter >= 2) & (cfi_flash_s1_wait_counter < 7) & cfi_flash_s1_pretend_byte_enable);
//tri_state_bridge_address of type address to p1_tri_state_bridge_address, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tri_state_bridge_address <= 0;
else
tri_state_bridge_address <= p1_tri_state_bridge_address;
end
//p1_tri_state_bridge_address mux, which is an e_mux
assign p1_tri_state_bridge_address = (cpu_data_master_granted_cfi_flash_s1)? ({cpu_data_master_address_to_slave >> 2,
cpu_data_master_dbs_address[1 : 0]}) :
({cpu_instruction_master_address_to_slave >> 2,
cpu_instruction_master_dbs_address[1 : 0]});
//d1_tri_state_bridge_avalon_slave_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_tri_state_bridge_avalon_slave_end_xfer <= 1;
else
d1_tri_state_bridge_avalon_slave_end_xfer <= tri_state_bridge_avalon_slave_end_xfer;
end
//cfi_flash_s1_wait_counter_eq_1 assignment, which is an e_assign
assign cfi_flash_s1_wait_counter_eq_1 = cfi_flash_s1_wait_counter == 1;
//cfi_flash_s1_waits_for_read in a cycle, which is an e_mux
assign cfi_flash_s1_waits_for_read = cfi_flash_s1_in_a_read_cycle & wait_for_cfi_flash_s1_counter;
//cfi_flash_s1_in_a_read_cycle assignment, which is an e_assign
assign cfi_flash_s1_in_a_read_cycle = (cpu_data_master_granted_cfi_flash_s1 & cpu_data_master_read) | (cpu_instruction_master_granted_cfi_flash_s1 & cpu_instruction_master_read);
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = cfi_flash_s1_in_a_read_cycle;
//cfi_flash_s1_waits_for_write in a cycle, which is an e_mux
assign cfi_flash_s1_waits_for_write = cfi_flash_s1_in_a_write_cycle & wait_for_cfi_flash_s1_counter;
//cfi_flash_s1_in_a_write_cycle assignment, which is an e_assign
assign cfi_flash_s1_in_a_write_cycle = cpu_data_master_granted_cfi_flash_s1 & cpu_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = cfi_flash_s1_in_a_write_cycle;
assign cfi_flash_s1_wait_counter_eq_0 = cfi_flash_s1_wait_counter == 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cfi_flash_s1_wait_counter <= 0;
else
cfi_flash_s1_wait_counter <= cfi_flash_s1_counter_load_value;
end
assign cfi_flash_s1_counter_load_value = ((cfi_flash_s1_in_a_read_cycle & tri_state_bridge_avalon_slave_begins_xfer))? 5 :
((cfi_flash_s1_in_a_write_cycle & tri_state_bridge_avalon_slave_begins_xfer))? 7 :
(~cfi_flash_s1_wait_counter_eq_0)? cfi_flash_s1_wait_counter - 1 :
0;
assign wait_for_cfi_flash_s1_counter = tri_state_bridge_avalon_slave_begins_xfer | ~cfi_flash_s1_wait_counter_eq_0;
//cfi_flash_s1_pretend_byte_enable byte enable port mux, which is an e_mux
assign cfi_flash_s1_pretend_byte_enable = (cpu_data_master_granted_cfi_flash_s1)? cpu_data_master_byteenable_cfi_flash_s1 :
-1;
assign {cpu_data_master_byteenable_cfi_flash_s1_segment_3,
cpu_data_master_byteenable_cfi_flash_s1_segment_2,
cpu_data_master_byteenable_cfi_flash_s1_segment_1,
cpu_data_master_byteenable_cfi_flash_s1_segment_0} = cpu_data_master_byteenable;
assign cpu_data_master_byteenable_cfi_flash_s1 = ((cpu_data_master_dbs_address[1 : 0] == 0))? cpu_data_master_byteenable_cfi_flash_s1_segment_0 :
((cpu_data_master_dbs_address[1 : 0] == 1))? cpu_data_master_byteenable_cfi_flash_s1_segment_1 :
((cpu_data_master_dbs_address[1 : 0] == 2))? cpu_data_master_byteenable_cfi_flash_s1_segment_2 :
cpu_data_master_byteenable_cfi_flash_s1_segment_3;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//incoming_tri_state_bridge_data_bit_0_is_x x check, which is an e_assign_is_x
assign incoming_tri_state_bridge_data_bit_0_is_x = ^(incoming_tri_state_bridge_data[0]) === 1'bx;
//Crush incoming_tri_state_bridge_data_with_Xs_converted_to_0[0] Xs to 0, which is an e_assign
assign incoming_tri_state_bridge_data_with_Xs_converted_to_0[0] = incoming_tri_state_bridge_data_bit_0_is_x ? 1'b0 : incoming_tri_state_bridge_data[0];
//incoming_tri_state_bridge_data_bit_1_is_x x check, which is an e_assign_is_x
assign incoming_tri_state_bridge_data_bit_1_is_x = ^(incoming_tri_state_bridge_data[1]) === 1'bx;
//Crush incoming_tri_state_bridge_data_with_Xs_converted_to_0[1] Xs to 0, which is an e_assign
assign incoming_tri_state_bridge_data_with_Xs_converted_to_0[1] = incoming_tri_state_bridge_data_bit_1_is_x ? 1'b0 : incoming_tri_state_bridge_data[1];
//incoming_tri_state_bridge_data_bit_2_is_x x check, which is an e_assign_is_x
assign incoming_tri_state_bridge_data_bit_2_is_x = ^(incoming_tri_state_bridge_data[2]) === 1'bx;
//Crush incoming_tri_state_bridge_data_with_Xs_converted_to_0[2] Xs to 0, which is an e_assign
assign incoming_tri_state_bridge_data_with_Xs_converted_to_0[2] = incoming_tri_state_bridge_data_bit_2_is_x ? 1'b0 : incoming_tri_state_bridge_data[2];
//incoming_tri_state_bridge_data_bit_3_is_x x check, which is an e_assign_is_x
assign incoming_tri_state_bridge_data_bit_3_is_x = ^(incoming_tri_state_bridge_data[3]) === 1'bx;
//Crush incoming_tri_state_bridge_data_with_Xs_converted_to_0[3] Xs to 0, which is an e_assign
assign incoming_tri_state_bridge_data_with_Xs_converted_to_0[3] = incoming_tri_state_bridge_data_bit_3_is_x ? 1'b0 : incoming_tri_state_bridge_data[3];
//incoming_tri_state_bridge_data_bit_4_is_x x check, which is an e_assign_is_x
assign incoming_tri_state_bridge_data_bit_4_is_x = ^(incoming_tri_state_bridge_data[4]) === 1'bx;
//Crush incoming_tri_state_bridge_data_with_Xs_converted_to_0[4] Xs to 0, which is an e_assign
assign incoming_tri_state_bridge_data_with_Xs_converted_to_0[4] = incoming_tri_state_bridge_data_bit_4_is_x ? 1'b0 : incoming_tri_state_bridge_data[4];
//incoming_tri_state_bridge_data_bit_5_is_x x check, which is an e_assign_is_x
assign incoming_tri_state_bridge_data_bit_5_is_x = ^(incoming_tri_state_bridge_data[5]) === 1'bx;
//Crush incoming_tri_state_bridge_data_with_Xs_converted_to_0[5] Xs to 0, which is an e_assign
assign incoming_tri_state_bridge_data_with_Xs_converted_to_0[5] = incoming_tri_state_bridge_data_bit_5_is_x ? 1'b0 : incoming_tri_state_bridge_data[5];
//incoming_tri_state_bridge_data_bit_6_is_x x check, which is an e_assign_is_x
assign incoming_tri_state_bridge_data_bit_6_is_x = ^(incoming_tri_state_bridge_data[6]) === 1'bx;
//Crush incoming_tri_state_bridge_data_with_Xs_converted_to_0[6] Xs to 0, which is an e_assign
assign incoming_tri_state_bridge_data_with_Xs_converted_to_0[6] = incoming_tri_state_bridge_data_bit_6_is_x ? 1'b0 : incoming_tri_state_bridge_data[6];
//incoming_tri_state_bridge_data_bit_7_is_x x check, which is an e_assign_is_x
assign incoming_tri_state_bridge_data_bit_7_is_x = ^(incoming_tri_state_bridge_data[7]) === 1'bx;
//Crush incoming_tri_state_bridge_data_with_Xs_converted_to_0[7] Xs to 0, which is an e_assign
assign incoming_tri_state_bridge_data_with_Xs_converted_to_0[7] = incoming_tri_state_bridge_data_bit_7_is_x ? 1'b0 : incoming_tri_state_bridge_data[7];
//cfi_flash/s1 enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_data_master_granted_cfi_flash_s1 + cpu_instruction_master_granted_cfi_flash_s1 > 1)
begin
$write("%0d ns: > 1 of grant signals are active simultaneously", $time);
$stop;
end
end
//saved_grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_data_master_saved_grant_cfi_flash_s1 + cpu_instruction_master_saved_grant_cfi_flash_s1 > 1)
begin
$write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign incoming_tri_state_bridge_data_with_Xs_converted_to_0 = incoming_tri_state_bridge_data;
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module tri_state_bridge_bridge_arbitrator
;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module vga_0_avalon_slave_0_arbitrator (
// inputs:
clk,
kernel_clock_0_out_address_to_slave,
kernel_clock_0_out_nativeaddress,
kernel_clock_0_out_read,
kernel_clock_0_out_write,
kernel_clock_0_out_writedata,
reset_n,
vga_0_avalon_slave_0_readdata,
// outputs:
d1_vga_0_avalon_slave_0_end_xfer,
kernel_clock_0_out_granted_vga_0_avalon_slave_0,
kernel_clock_0_out_qualified_request_vga_0_avalon_slave_0,
kernel_clock_0_out_read_data_valid_vga_0_avalon_slave_0,
kernel_clock_0_out_requests_vga_0_avalon_slave_0,
vga_0_avalon_slave_0_address,
vga_0_avalon_slave_0_chipselect,
vga_0_avalon_slave_0_read,
vga_0_avalon_slave_0_readdata_from_sa,
vga_0_avalon_slave_0_reset_n,
vga_0_avalon_slave_0_wait_counter_eq_0,
vga_0_avalon_slave_0_write,
vga_0_avalon_slave_0_writedata
)
;
output d1_vga_0_avalon_slave_0_end_xfer;
output kernel_clock_0_out_granted_vga_0_avalon_slave_0;
output kernel_clock_0_out_qualified_request_vga_0_avalon_slave_0;
output kernel_clock_0_out_read_data_valid_vga_0_avalon_slave_0;
output kernel_clock_0_out_requests_vga_0_avalon_slave_0;
output [ 18: 0] vga_0_avalon_slave_0_address;
output vga_0_avalon_slave_0_chipselect;
output vga_0_avalon_slave_0_read;
output [ 15: 0] vga_0_avalon_slave_0_readdata_from_sa;
output vga_0_avalon_slave_0_reset_n;
output vga_0_avalon_slave_0_wait_counter_eq_0;
output vga_0_avalon_slave_0_write;
output [ 15: 0] vga_0_avalon_slave_0_writedata;
input clk;
input [ 19: 0] kernel_clock_0_out_address_to_slave;
input [ 18: 0] kernel_clock_0_out_nativeaddress;
input kernel_clock_0_out_read;
input kernel_clock_0_out_write;
input [ 15: 0] kernel_clock_0_out_writedata;
input reset_n;
input [ 15: 0] vga_0_avalon_slave_0_readdata;
reg d1_reasons_to_wait;
reg d1_vga_0_avalon_slave_0_end_xfer;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_vga_0_avalon_slave_0;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire kernel_clock_0_out_arbiterlock;
wire kernel_clock_0_out_arbiterlock2;
wire kernel_clock_0_out_continuerequest;
wire kernel_clock_0_out_granted_vga_0_avalon_slave_0;
wire kernel_clock_0_out_qualified_request_vga_0_avalon_slave_0;
wire kernel_clock_0_out_read_data_valid_vga_0_avalon_slave_0;
wire kernel_clock_0_out_requests_vga_0_avalon_slave_0;
wire kernel_clock_0_out_saved_grant_vga_0_avalon_slave_0;
wire [ 18: 0] vga_0_avalon_slave_0_address;
wire vga_0_avalon_slave_0_allgrants;
wire vga_0_avalon_slave_0_allow_new_arb_cycle;
wire vga_0_avalon_slave_0_any_bursting_master_saved_grant;
wire vga_0_avalon_slave_0_any_continuerequest;
wire vga_0_avalon_slave_0_arb_counter_enable;
reg vga_0_avalon_slave_0_arb_share_counter;
wire vga_0_avalon_slave_0_arb_share_counter_next_value;
wire vga_0_avalon_slave_0_arb_share_set_values;
wire vga_0_avalon_slave_0_beginbursttransfer_internal;
wire vga_0_avalon_slave_0_begins_xfer;
wire vga_0_avalon_slave_0_chipselect;
wire vga_0_avalon_slave_0_counter_load_value;
wire vga_0_avalon_slave_0_end_xfer;
wire vga_0_avalon_slave_0_firsttransfer;
wire vga_0_avalon_slave_0_grant_vector;
wire vga_0_avalon_slave_0_in_a_read_cycle;
wire vga_0_avalon_slave_0_in_a_write_cycle;
wire vga_0_avalon_slave_0_master_qreq_vector;
wire vga_0_avalon_slave_0_non_bursting_master_requests;
wire vga_0_avalon_slave_0_read;
wire [ 15: 0] vga_0_avalon_slave_0_readdata_from_sa;
reg vga_0_avalon_slave_0_reg_firsttransfer;
wire vga_0_avalon_slave_0_reset_n;
reg vga_0_avalon_slave_0_slavearbiterlockenable;
wire vga_0_avalon_slave_0_slavearbiterlockenable2;
wire vga_0_avalon_slave_0_unreg_firsttransfer;
reg vga_0_avalon_slave_0_wait_counter;
wire vga_0_avalon_slave_0_wait_counter_eq_0;
wire vga_0_avalon_slave_0_waits_for_read;
wire vga_0_avalon_slave_0_waits_for_write;
wire vga_0_avalon_slave_0_write;
wire [ 15: 0] vga_0_avalon_slave_0_writedata;
wire wait_for_vga_0_avalon_slave_0_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~vga_0_avalon_slave_0_end_xfer;
end
assign vga_0_avalon_slave_0_begins_xfer = ~d1_reasons_to_wait & ((kernel_clock_0_out_qualified_request_vga_0_avalon_slave_0));
//assign vga_0_avalon_slave_0_readdata_from_sa = vga_0_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign vga_0_avalon_slave_0_readdata_from_sa = vga_0_avalon_slave_0_readdata;
assign kernel_clock_0_out_requests_vga_0_avalon_slave_0 = (1) & (kernel_clock_0_out_read | kernel_clock_0_out_write);
//vga_0_avalon_slave_0_arb_share_counter set values, which is an e_mux
assign vga_0_avalon_slave_0_arb_share_set_values = 1;
//vga_0_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
assign vga_0_avalon_slave_0_non_bursting_master_requests = kernel_clock_0_out_requests_vga_0_avalon_slave_0;
//vga_0_avalon_slave_0_any_bursting_master_saved_grant mux, which is an e_mux
assign vga_0_avalon_slave_0_any_bursting_master_saved_grant = 0;
//vga_0_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
assign vga_0_avalon_slave_0_arb_share_counter_next_value = vga_0_avalon_slave_0_firsttransfer ? (vga_0_avalon_slave_0_arb_share_set_values - 1) : |vga_0_avalon_slave_0_arb_share_counter ? (vga_0_avalon_slave_0_arb_share_counter - 1) : 0;
//vga_0_avalon_slave_0_allgrants all slave grants, which is an e_mux
assign vga_0_avalon_slave_0_allgrants = |vga_0_avalon_slave_0_grant_vector;
//vga_0_avalon_slave_0_end_xfer assignment, which is an e_assign
assign vga_0_avalon_slave_0_end_xfer = ~(vga_0_avalon_slave_0_waits_for_read | vga_0_avalon_slave_0_waits_for_write);
//end_xfer_arb_share_counter_term_vga_0_avalon_slave_0 arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_vga_0_avalon_slave_0 = vga_0_avalon_slave_0_end_xfer & (~vga_0_avalon_slave_0_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//vga_0_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
assign vga_0_avalon_slave_0_arb_counter_enable = (end_xfer_arb_share_counter_term_vga_0_avalon_slave_0 & vga_0_avalon_slave_0_allgrants) | (end_xfer_arb_share_counter_term_vga_0_avalon_slave_0 & ~vga_0_avalon_slave_0_non_bursting_master_requests);
//vga_0_avalon_slave_0_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
vga_0_avalon_slave_0_arb_share_counter <= 0;
else if (vga_0_avalon_slave_0_arb_counter_enable)
vga_0_avalon_slave_0_arb_share_counter <= vga_0_avalon_slave_0_arb_share_counter_next_value;
end
//vga_0_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
vga_0_avalon_slave_0_slavearbiterlockenable <= 0;
else if ((|vga_0_avalon_slave_0_master_qreq_vector & end_xfer_arb_share_counter_term_vga_0_avalon_slave_0) | (end_xfer_arb_share_counter_term_vga_0_avalon_slave_0 & ~vga_0_avalon_slave_0_non_bursting_master_requests))
vga_0_avalon_slave_0_slavearbiterlockenable <= |vga_0_avalon_slave_0_arb_share_counter_next_value;
end
//kernel_clock_0/out vga_0/avalon_slave_0 arbiterlock, which is an e_assign
assign kernel_clock_0_out_arbiterlock = vga_0_avalon_slave_0_slavearbiterlockenable & kernel_clock_0_out_continuerequest;
//vga_0_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign vga_0_avalon_slave_0_slavearbiterlockenable2 = |vga_0_avalon_slave_0_arb_share_counter_next_value;
//kernel_clock_0/out vga_0/avalon_slave_0 arbiterlock2, which is an e_assign
assign kernel_clock_0_out_arbiterlock2 = vga_0_avalon_slave_0_slavearbiterlockenable2 & kernel_clock_0_out_continuerequest;
//vga_0_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_assign
assign vga_0_avalon_slave_0_any_continuerequest = 1;
//kernel_clock_0_out_continuerequest continued request, which is an e_assign
assign kernel_clock_0_out_continuerequest = 1;
assign kernel_clock_0_out_qualified_request_vga_0_avalon_slave_0 = kernel_clock_0_out_requests_vga_0_avalon_slave_0;
//vga_0_avalon_slave_0_writedata mux, which is an e_mux
assign vga_0_avalon_slave_0_writedata = kernel_clock_0_out_writedata;
//master is always granted when requested
assign kernel_clock_0_out_granted_vga_0_avalon_slave_0 = kernel_clock_0_out_qualified_request_vga_0_avalon_slave_0;
//kernel_clock_0/out saved-grant vga_0/avalon_slave_0, which is an e_assign
assign kernel_clock_0_out_saved_grant_vga_0_avalon_slave_0 = kernel_clock_0_out_requests_vga_0_avalon_slave_0;
//allow new arb cycle for vga_0/avalon_slave_0, which is an e_assign
assign vga_0_avalon_slave_0_allow_new_arb_cycle = 1;
//placeholder chosen master
assign vga_0_avalon_slave_0_grant_vector = 1;
//placeholder vector of master qualified-requests
assign vga_0_avalon_slave_0_master_qreq_vector = 1;
//vga_0_avalon_slave_0_reset_n assignment, which is an e_assign
assign vga_0_avalon_slave_0_reset_n = reset_n;
assign vga_0_avalon_slave_0_chipselect = kernel_clock_0_out_granted_vga_0_avalon_slave_0;
//vga_0_avalon_slave_0_firsttransfer first transaction, which is an e_assign
assign vga_0_avalon_slave_0_firsttransfer = vga_0_avalon_slave_0_begins_xfer ? vga_0_avalon_slave_0_unreg_firsttransfer : vga_0_avalon_slave_0_reg_firsttransfer;
//vga_0_avalon_slave_0_unreg_firsttransfer first transaction, which is an e_assign
assign vga_0_avalon_slave_0_unreg_firsttransfer = ~(vga_0_avalon_slave_0_slavearbiterlockenable & vga_0_avalon_slave_0_any_continuerequest);
//vga_0_avalon_slave_0_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
vga_0_avalon_slave_0_reg_firsttransfer <= 1'b1;
else if (vga_0_avalon_slave_0_begins_xfer)
vga_0_avalon_slave_0_reg_firsttransfer <= vga_0_avalon_slave_0_unreg_firsttransfer;
end
//vga_0_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign vga_0_avalon_slave_0_beginbursttransfer_internal = vga_0_avalon_slave_0_begins_xfer;
//vga_0_avalon_slave_0_read assignment, which is an e_mux
assign vga_0_avalon_slave_0_read = ((kernel_clock_0_out_granted_vga_0_avalon_slave_0 & kernel_clock_0_out_read))& ~vga_0_avalon_slave_0_begins_xfer;
//vga_0_avalon_slave_0_write assignment, which is an e_mux
assign vga_0_avalon_slave_0_write = ((kernel_clock_0_out_granted_vga_0_avalon_slave_0 & kernel_clock_0_out_write)) & ~vga_0_avalon_slave_0_begins_xfer & (vga_0_avalon_slave_0_wait_counter >= 1);
//vga_0_avalon_slave_0_address mux, which is an e_mux
assign vga_0_avalon_slave_0_address = kernel_clock_0_out_nativeaddress;
//d1_vga_0_avalon_slave_0_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_vga_0_avalon_slave_0_end_xfer <= 1;
else
d1_vga_0_avalon_slave_0_end_xfer <= vga_0_avalon_slave_0_end_xfer;
end
//vga_0_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
assign vga_0_avalon_slave_0_waits_for_read = vga_0_avalon_slave_0_in_a_read_cycle & vga_0_avalon_slave_0_begins_xfer;
//vga_0_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
assign vga_0_avalon_slave_0_in_a_read_cycle = kernel_clock_0_out_granted_vga_0_avalon_slave_0 & kernel_clock_0_out_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = vga_0_avalon_slave_0_in_a_read_cycle;
//vga_0_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
assign vga_0_avalon_slave_0_waits_for_write = vga_0_avalon_slave_0_in_a_write_cycle & wait_for_vga_0_avalon_slave_0_counter;
//vga_0_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
assign vga_0_avalon_slave_0_in_a_write_cycle = kernel_clock_0_out_granted_vga_0_avalon_slave_0 & kernel_clock_0_out_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = vga_0_avalon_slave_0_in_a_write_cycle;
assign vga_0_avalon_slave_0_wait_counter_eq_0 = vga_0_avalon_slave_0_wait_counter == 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
vga_0_avalon_slave_0_wait_counter <= 0;
else
vga_0_avalon_slave_0_wait_counter <= vga_0_avalon_slave_0_counter_load_value;
end
assign vga_0_avalon_slave_0_counter_load_value = ((vga_0_avalon_slave_0_in_a_write_cycle & vga_0_avalon_slave_0_begins_xfer))? 1 :
(~vga_0_avalon_slave_0_wait_counter_eq_0)? vga_0_avalon_slave_0_wait_counter - 1 :
0;
assign wait_for_vga_0_avalon_slave_0_counter = vga_0_avalon_slave_0_begins_xfer | ~vga_0_avalon_slave_0_wait_counter_eq_0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//vga_0/avalon_slave_0 enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module kernel_reset_clk_50_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
)
;
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_in_d1 <= 0;
else
data_in_d1 <= data_in;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else
data_out <= data_in_d1;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module kernel_reset_pll_c0_out_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
)
;
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_in_d1 <= 0;
else
data_in_d1 <= data_in;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else
data_out <= data_in_d1;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module kernel (
// 1) global signals:
clk_50,
pll_c0_out,
reset_n,
// the_gpio
in_port_to_the_gpio,
// the_hardmodle
in_port_to_the_hardmodle,
// the_key
in_port_to_the_key,
// the_lcd_0
LCD_E_from_the_lcd_0,
LCD_RS_from_the_lcd_0,
LCD_RW_from_the_lcd_0,
LCD_data_to_and_from_the_lcd_0,
// the_pll
areset_to_the_pll,
locked_from_the_pll,
phasedone_from_the_pll,
// the_sram_16bit_512k_0
SRAM_ADDR_from_the_sram_16bit_512k_0,
SRAM_CE_N_from_the_sram_16bit_512k_0,
SRAM_DQ_to_and_from_the_sram_16bit_512k_0,
SRAM_LB_N_from_the_sram_16bit_512k_0,
SRAM_OE_N_from_the_sram_16bit_512k_0,
SRAM_UB_N_from_the_sram_16bit_512k_0,
SRAM_WE_N_from_the_sram_16bit_512k_0,
// the_tri_state_bridge_avalon_slave
select_n_to_the_cfi_flash,
tri_state_bridge_address,
tri_state_bridge_data,
tri_state_bridge_readn,
write_n_to_the_cfi_flash,
// the_vga_0
VGA_BLANK_from_the_vga_0,
VGA_B_from_the_vga_0,
VGA_CLK_from_the_vga_0,
VGA_G_from_the_vga_0,
VGA_HS_from_the_vga_0,
VGA_R_from_the_vga_0,
VGA_SYNC_from_the_vga_0,
VGA_VS_from_the_vga_0,
iCLK_25_to_the_vga_0
)
;
output LCD_E_from_the_lcd_0;
output LCD_RS_from_the_lcd_0;
output LCD_RW_from_the_lcd_0;
inout [ 7: 0] LCD_data_to_and_from_the_lcd_0;
output [ 17: 0] SRAM_ADDR_from_the_sram_16bit_512k_0;
output SRAM_CE_N_from_the_sram_16bit_512k_0;
inout [ 15: 0] SRAM_DQ_to_and_from_the_sram_16bit_512k_0;
output SRAM_LB_N_from_the_sram_16bit_512k_0;
output SRAM_OE_N_from_the_sram_16bit_512k_0;
output SRAM_UB_N_from_the_sram_16bit_512k_0;
output SRAM_WE_N_from_the_sram_16bit_512k_0;
output VGA_BLANK_from_the_vga_0;
output [ 9: 0] VGA_B_from_the_vga_0;
output VGA_CLK_from_the_vga_0;
output [ 9: 0] VGA_G_from_the_vga_0;
output VGA_HS_from_the_vga_0;
output [ 9: 0] VGA_R_from_the_vga_0;
output VGA_SYNC_from_the_vga_0;
output VGA_VS_from_the_vga_0;
output locked_from_the_pll;
output phasedone_from_the_pll;
output pll_c0_out;
output select_n_to_the_cfi_flash;
output [ 21: 0] tri_state_bridge_address;
inout [ 7: 0] tri_state_bridge_data;
output tri_state_bridge_readn;
output write_n_to_the_cfi_flash;
input areset_to_the_pll;
input clk_50;
input iCLK_25_to_the_vga_0;
input in_port_to_the_gpio;
input [ 3: 0] in_port_to_the_hardmodle;
input in_port_to_the_key;
input reset_n;
wire LCD_E_from_the_lcd_0;
wire LCD_RS_from_the_lcd_0;
wire LCD_RW_from_the_lcd_0;
wire [ 7: 0] LCD_data_to_and_from_the_lcd_0;
wire [ 17: 0] SRAM_ADDR_from_the_sram_16bit_512k_0;
wire SRAM_CE_N_from_the_sram_16bit_512k_0;
wire [ 15: 0] SRAM_DQ_to_and_from_the_sram_16bit_512k_0;
wire SRAM_LB_N_from_the_sram_16bit_512k_0;
wire SRAM_OE_N_from_the_sram_16bit_512k_0;
wire SRAM_UB_N_from_the_sram_16bit_512k_0;
wire SRAM_WE_N_from_the_sram_16bit_512k_0;
wire VGA_BLANK_from_the_vga_0;
wire [ 9: 0] VGA_B_from_the_vga_0;
wire VGA_CLK_from_the_vga_0;
wire [ 9: 0] VGA_G_from_the_vga_0;
wire VGA_HS_from_the_vga_0;
wire [ 9: 0] VGA_R_from_the_vga_0;
wire VGA_SYNC_from_the_vga_0;
wire VGA_VS_from_the_vga_0;
wire cfi_flash_s1_wait_counter_eq_0;
wire cfi_flash_s1_wait_counter_eq_1;
wire clk_50_reset_n;
wire [ 23: 0] cpu_data_master_address;
wire [ 23: 0] cpu_data_master_address_to_slave;
wire [ 3: 0] cpu_data_master_byteenable;
wire cpu_data_master_byteenable_cfi_flash_s1;
wire [ 1: 0] cpu_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0;
wire [ 1: 0] cpu_data_master_dbs_address;
wire [ 15: 0] cpu_data_master_dbs_write_16;
wire [ 7: 0] cpu_data_master_dbs_write_8;
wire cpu_data_master_debugaccess;
wire cpu_data_master_granted_cfi_flash_s1;
wire cpu_data_master_granted_cpu_jtag_debug_module;
wire cpu_data_master_granted_epcs_flash_controller_epcs_control_port;
wire cpu_data_master_granted_gpio_s1;
wire cpu_data_master_granted_hardmodle_s1;
wire cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
wire cpu_data_master_granted_kernel_clock_0_in;
wire cpu_data_master_granted_key_s1;
wire cpu_data_master_granted_lcd_0_control_slave;
wire cpu_data_master_granted_onchip_memory_s1;
wire cpu_data_master_granted_pll_pll_slave;
wire cpu_data_master_granted_sram_16bit_512k_0_avalon_slave_0;
wire cpu_data_master_granted_timer_s1;
wire [ 31: 0] cpu_data_master_irq;
wire cpu_data_master_no_byte_enables_and_last_term;
wire cpu_data_master_qualified_request_cfi_flash_s1;
wire cpu_data_master_qualified_request_cpu_jtag_debug_module;
wire cpu_data_master_qualified_request_epcs_flash_controller_epcs_control_port;
wire cpu_data_master_qualified_request_gpio_s1;
wire cpu_data_master_qualified_request_hardmodle_s1;
wire cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
wire cpu_data_master_qualified_request_kernel_clock_0_in;
wire cpu_data_master_qualified_request_key_s1;
wire cpu_data_master_qualified_request_lcd_0_control_slave;
wire cpu_data_master_qualified_request_onchip_memory_s1;
wire cpu_data_master_qualified_request_pll_pll_slave;
wire cpu_data_master_qualified_request_sram_16bit_512k_0_avalon_slave_0;
wire cpu_data_master_qualified_request_timer_s1;
wire cpu_data_master_read;
wire cpu_data_master_read_data_valid_cfi_flash_s1;
wire cpu_data_master_read_data_valid_cpu_jtag_debug_module;
wire cpu_data_master_read_data_valid_epcs_flash_controller_epcs_control_port;
wire cpu_data_master_read_data_valid_gpio_s1;
wire cpu_data_master_read_data_valid_hardmodle_s1;
wire cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
wire cpu_data_master_read_data_valid_kernel_clock_0_in;
wire cpu_data_master_read_data_valid_key_s1;
wire cpu_data_master_read_data_valid_lcd_0_control_slave;
wire cpu_data_master_read_data_valid_onchip_memory_s1;
wire cpu_data_master_read_data_valid_pll_pll_slave;
wire cpu_data_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0;
wire cpu_data_master_read_data_valid_timer_s1;
wire [ 31: 0] cpu_data_master_readdata;
wire cpu_data_master_requests_cfi_flash_s1;
wire cpu_data_master_requests_cpu_jtag_debug_module;
wire cpu_data_master_requests_epcs_flash_controller_epcs_control_port;
wire cpu_data_master_requests_gpio_s1;
wire cpu_data_master_requests_hardmodle_s1;
wire cpu_data_master_requests_jtag_uart_avalon_jtag_slave;
wire cpu_data_master_requests_kernel_clock_0_in;
wire cpu_data_master_requests_key_s1;
wire cpu_data_master_requests_lcd_0_control_slave;
wire cpu_data_master_requests_onchip_memory_s1;
wire cpu_data_master_requests_pll_pll_slave;
wire cpu_data_master_requests_sram_16bit_512k_0_avalon_slave_0;
wire cpu_data_master_requests_timer_s1;
wire cpu_data_master_waitrequest;
wire cpu_data_master_write;
wire [ 31: 0] cpu_data_master_writedata;
wire [ 23: 0] cpu_instruction_master_address;
wire [ 23: 0] cpu_instruction_master_address_to_slave;
wire [ 1: 0] cpu_instruction_master_dbs_address;
wire cpu_instruction_master_granted_cfi_flash_s1;
wire cpu_instruction_master_granted_cpu_jtag_debug_module;
wire cpu_instruction_master_granted_epcs_flash_controller_epcs_control_port;
wire cpu_instruction_master_granted_onchip_memory_s1;
wire cpu_instruction_master_granted_sram_16bit_512k_0_avalon_slave_0;
wire [ 1: 0] cpu_instruction_master_latency_counter;
wire cpu_instruction_master_qualified_request_cfi_flash_s1;
wire cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
wire cpu_instruction_master_qualified_request_epcs_flash_controller_epcs_control_port;
wire cpu_instruction_master_qualified_request_onchip_memory_s1;
wire cpu_instruction_master_qualified_request_sram_16bit_512k_0_avalon_slave_0;
wire cpu_instruction_master_read;
wire cpu_instruction_master_read_data_valid_cfi_flash_s1;
wire cpu_instruction_master_read_data_valid_cpu_jtag_debug_module;
wire cpu_instruction_master_read_data_valid_epcs_flash_controller_epcs_control_port;
wire cpu_instruction_master_read_data_valid_onchip_memory_s1;
wire cpu_instruction_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0;
wire [ 31: 0] cpu_instruction_master_readdata;
wire cpu_instruction_master_readdatavalid;
wire cpu_instruction_master_requests_cfi_flash_s1;
wire cpu_instruction_master_requests_cpu_jtag_debug_module;
wire cpu_instruction_master_requests_epcs_flash_controller_epcs_control_port;
wire cpu_instruction_master_requests_onchip_memory_s1;
wire cpu_instruction_master_requests_sram_16bit_512k_0_avalon_slave_0;
wire cpu_instruction_master_waitrequest;
wire [ 8: 0] cpu_jtag_debug_module_address;
wire cpu_jtag_debug_module_begintransfer;
wire [ 3: 0] cpu_jtag_debug_module_byteenable;
wire cpu_jtag_debug_module_chipselect;
wire cpu_jtag_debug_module_debugaccess;
wire [ 31: 0] cpu_jtag_debug_module_readdata;
wire [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
wire cpu_jtag_debug_module_reset_n;
wire cpu_jtag_debug_module_resetrequest;
wire cpu_jtag_debug_module_resetrequest_from_sa;
wire cpu_jtag_debug_module_write;
wire [ 31: 0] cpu_jtag_debug_module_writedata;
wire d1_cpu_jtag_debug_module_end_xfer;
wire d1_epcs_flash_controller_epcs_control_port_end_xfer;
wire d1_gpio_s1_end_xfer;
wire d1_hardmodle_s1_end_xfer;
wire d1_jtag_uart_avalon_jtag_slave_end_xfer;
wire d1_kernel_clock_0_in_end_xfer;
wire d1_key_s1_end_xfer;
wire d1_lcd_0_control_slave_end_xfer;
wire d1_onchip_memory_s1_end_xfer;
wire d1_pll_pll_slave_end_xfer;
wire d1_sram_16bit_512k_0_avalon_slave_0_end_xfer;
wire d1_timer_s1_end_xfer;
wire d1_tri_state_bridge_avalon_slave_end_xfer;
wire d1_vga_0_avalon_slave_0_end_xfer;
wire [ 8: 0] epcs_flash_controller_epcs_control_port_address;
wire epcs_flash_controller_epcs_control_port_chipselect;
wire epcs_flash_controller_epcs_control_port_dataavailable;
wire epcs_flash_controller_epcs_control_port_dataavailable_from_sa;
wire epcs_flash_controller_epcs_control_port_endofpacket;
wire epcs_flash_controller_epcs_control_port_endofpacket_from_sa;
wire epcs_flash_controller_epcs_control_port_irq;
wire epcs_flash_controller_epcs_control_port_irq_from_sa;
wire epcs_flash_controller_epcs_control_port_read_n;
wire [ 31: 0] epcs_flash_controller_epcs_control_port_readdata;
wire [ 31: 0] epcs_flash_controller_epcs_control_port_readdata_from_sa;
wire epcs_flash_controller_epcs_control_port_readyfordata;
wire epcs_flash_controller_epcs_control_port_readyfordata_from_sa;
wire epcs_flash_controller_epcs_control_port_reset_n;
wire epcs_flash_controller_epcs_control_port_write_n;
wire [ 31: 0] epcs_flash_controller_epcs_control_port_writedata;
wire [ 1: 0] gpio_s1_address;
wire gpio_s1_chipselect;
wire gpio_s1_irq;
wire gpio_s1_irq_from_sa;
wire [ 31: 0] gpio_s1_readdata;
wire [ 31: 0] gpio_s1_readdata_from_sa;
wire gpio_s1_reset_n;
wire gpio_s1_write_n;
wire [ 31: 0] gpio_s1_writedata;
wire [ 1: 0] hardmodle_s1_address;
wire [ 31: 0] hardmodle_s1_readdata;
wire [ 31: 0] hardmodle_s1_readdata_from_sa;
wire hardmodle_s1_reset_n;
wire [ 7: 0] incoming_tri_state_bridge_data;
wire [ 7: 0] incoming_tri_state_bridge_data_with_Xs_converted_to_0;
wire jtag_uart_avalon_jtag_slave_address;
wire jtag_uart_avalon_jtag_slave_chipselect;
wire jtag_uart_avalon_jtag_slave_dataavailable;
wire jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
wire jtag_uart_avalon_jtag_slave_irq;
wire jtag_uart_avalon_jtag_slave_irq_from_sa;
wire jtag_uart_avalon_jtag_slave_read_n;
wire [ 31: 0] jtag_uart_avalon_jtag_slave_readdata;
wire [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
wire jtag_uart_avalon_jtag_slave_readyfordata;
wire jtag_uart_avalon_jtag_slave_readyfordata_from_sa;
wire jtag_uart_avalon_jtag_slave_reset_n;
wire jtag_uart_avalon_jtag_slave_waitrequest;
wire jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
wire jtag_uart_avalon_jtag_slave_write_n;
wire [ 31: 0] jtag_uart_avalon_jtag_slave_writedata;
wire [ 19: 0] kernel_clock_0_in_address;
wire [ 1: 0] kernel_clock_0_in_byteenable;
wire kernel_clock_0_in_endofpacket;
wire kernel_clock_0_in_endofpacket_from_sa;
wire [ 18: 0] kernel_clock_0_in_nativeaddress;
wire kernel_clock_0_in_read;
wire [ 15: 0] kernel_clock_0_in_readdata;
wire [ 15: 0] kernel_clock_0_in_readdata_from_sa;
wire kernel_clock_0_in_reset_n;
wire kernel_clock_0_in_waitrequest;
wire kernel_clock_0_in_waitrequest_from_sa;
wire kernel_clock_0_in_write;
wire [ 15: 0] kernel_clock_0_in_writedata;
wire [ 19: 0] kernel_clock_0_out_address;
wire [ 19: 0] kernel_clock_0_out_address_to_slave;
wire [ 1: 0] kernel_clock_0_out_byteenable;
wire kernel_clock_0_out_endofpacket;
wire kernel_clock_0_out_granted_vga_0_avalon_slave_0;
wire [ 18: 0] kernel_clock_0_out_nativeaddress;
wire kernel_clock_0_out_qualified_request_vga_0_avalon_slave_0;
wire kernel_clock_0_out_read;
wire kernel_clock_0_out_read_data_valid_vga_0_avalon_slave_0;
wire [ 15: 0] kernel_clock_0_out_readdata;
wire kernel_clock_0_out_requests_vga_0_avalon_slave_0;
wire kernel_clock_0_out_reset_n;
wire kernel_clock_0_out_waitrequest;
wire kernel_clock_0_out_write;
wire [ 15: 0] kernel_clock_0_out_writedata;
wire [ 1: 0] key_s1_address;
wire key_s1_chipselect;
wire key_s1_irq;
wire key_s1_irq_from_sa;
wire [ 31: 0] key_s1_readdata;
wire [ 31: 0] key_s1_readdata_from_sa;
wire key_s1_reset_n;
wire key_s1_write_n;
wire [ 31: 0] key_s1_writedata;
wire [ 1: 0] lcd_0_control_slave_address;
wire lcd_0_control_slave_begintransfer;
wire lcd_0_control_slave_read;
wire [ 7: 0] lcd_0_control_slave_readdata;
wire [ 7: 0] lcd_0_control_slave_readdata_from_sa;
wire lcd_0_control_slave_reset_n;
wire lcd_0_control_slave_wait_counter_eq_0;
wire lcd_0_control_slave_wait_counter_eq_1;
wire lcd_0_control_slave_write;
wire [ 7: 0] lcd_0_control_slave_writedata;
wire locked_from_the_pll;
wire [ 9: 0] onchip_memory_s1_address;
wire [ 3: 0] onchip_memory_s1_byteenable;
wire onchip_memory_s1_chipselect;
wire onchip_memory_s1_clken;
wire [ 31: 0] onchip_memory_s1_readdata;
wire [ 31: 0] onchip_memory_s1_readdata_from_sa;
wire onchip_memory_s1_reset;
wire onchip_memory_s1_write;
wire [ 31: 0] onchip_memory_s1_writedata;
wire out_clk_pll_c0;
wire phasedone_from_the_pll;
wire pll_c0_out;
wire pll_c0_out_reset_n;
wire [ 1: 0] pll_pll_slave_address;
wire pll_pll_slave_read;
wire [ 31: 0] pll_pll_slave_readdata;
wire [ 31: 0] pll_pll_slave_readdata_from_sa;
wire pll_pll_slave_reset;
wire pll_pll_slave_write;
wire [ 31: 0] pll_pll_slave_writedata;
wire registered_cpu_data_master_read_data_valid_cfi_flash_s1;
wire registered_cpu_data_master_read_data_valid_onchip_memory_s1;
wire reset_n_sources;
wire select_n_to_the_cfi_flash;
wire [ 17: 0] sram_16bit_512k_0_avalon_slave_0_address;
wire [ 1: 0] sram_16bit_512k_0_avalon_slave_0_byteenable_n;
wire sram_16bit_512k_0_avalon_slave_0_chipselect_n;
wire sram_16bit_512k_0_avalon_slave_0_read_n;
wire [ 15: 0] sram_16bit_512k_0_avalon_slave_0_readdata;
wire [ 15: 0] sram_16bit_512k_0_avalon_slave_0_readdata_from_sa;
wire sram_16bit_512k_0_avalon_slave_0_reset_n;
wire sram_16bit_512k_0_avalon_slave_0_wait_counter_eq_0;
wire sram_16bit_512k_0_avalon_slave_0_write_n;
wire [ 15: 0] sram_16bit_512k_0_avalon_slave_0_writedata;
wire [ 2: 0] timer_s1_address;
wire timer_s1_chipselect;
wire timer_s1_irq;
wire timer_s1_irq_from_sa;
wire [ 15: 0] timer_s1_readdata;
wire [ 15: 0] timer_s1_readdata_from_sa;
wire timer_s1_reset_n;
wire timer_s1_write_n;
wire [ 15: 0] timer_s1_writedata;
wire [ 21: 0] tri_state_bridge_address;
wire [ 7: 0] tri_state_bridge_data;
wire tri_state_bridge_readn;
wire [ 18: 0] vga_0_avalon_slave_0_address;
wire vga_0_avalon_slave_0_chipselect;
wire vga_0_avalon_slave_0_read;
wire [ 15: 0] vga_0_avalon_slave_0_readdata;
wire [ 15: 0] vga_0_avalon_slave_0_readdata_from_sa;
wire vga_0_avalon_slave_0_reset_n;
wire vga_0_avalon_slave_0_wait_counter_eq_0;
wire vga_0_avalon_slave_0_write;
wire [ 15: 0] vga_0_avalon_slave_0_writedata;
wire write_n_to_the_cfi_flash;
cpu_jtag_debug_module_arbitrator the_cpu_jtag_debug_module
(
.clk (clk_50),
.cpu_data_master_address_to_slave (cpu_data_master_address_to_slave),
.cpu_data_master_byteenable (cpu_data_master_byteenable),
.cpu_data_master_debugaccess (cpu_data_master_debugaccess),
.cpu_data_master_granted_cpu_jtag_debug_module (cpu_data_master_granted_cpu_jtag_debug_module),
.cpu_data_master_qualified_request_cpu_jtag_debug_module (cpu_data_master_qualified_request_cpu_jtag_debug_module),
.cpu_data_master_read (cpu_data_master_read),
.cpu_data_master_read_data_valid_cpu_jtag_debug_module (cpu_data_master_read_data_valid_cpu_jtag_debug_module),
.cpu_data_master_requests_cpu_jtag_debug_module (cpu_data_master_requests_cpu_jtag_debug_module),
.cpu_data_master_waitrequest (cpu_data_master_waitrequest),
.cpu_data_master_write (cpu_data_master_write),
.cpu_data_master_writedata (cpu_data_master_writedata),
.cpu_instruction_master_address_to_slave (cpu_instruction_master_address_to_slave),
.cpu_instruction_master_granted_cpu_jtag_debug_module (cpu_instruction_master_granted_cpu_jtag_debug_module),
.cpu_instruction_master_latency_counter (cpu_instruction_master_latency_counter),
.cpu_instruction_master_qualified_request_cpu_jtag_debug_module (cpu_instruction_master_qualified_request_cpu_jtag_debug_module),
.cpu_instruction_master_read (cpu_instruction_master_read),
.cpu_instruction_master_read_data_valid_cpu_jtag_debug_module (cpu_instruction_master_read_data_valid_cpu_jtag_debug_module),
.cpu_instruction_master_requests_cpu_jtag_debug_module (cpu_instruction_master_requests_cpu_jtag_debug_module),
.cpu_jtag_debug_module_address (cpu_jtag_debug_module_address),
.cpu_jtag_debug_module_begintransfer (cpu_jtag_debug_module_begintransfer),
.cpu_jtag_debug_module_byteenable (cpu_jtag_debug_module_byteenable),
.cpu_jtag_debug_module_chipselect (cpu_jtag_debug_module_chipselect),
.cpu_jtag_debug_module_debugaccess (cpu_jtag_debug_module_debugaccess),
.cpu_jtag_debug_module_readdata (cpu_jtag_debug_module_readdata),
.cpu_jtag_debug_module_readdata_from_sa (cpu_jtag_debug_module_readdata_from_sa),
.cpu_jtag_debug_module_reset_n (cpu_jtag_debug_module_reset_n),
.cpu_jtag_debug_module_resetrequest (cpu_jtag_debug_module_resetrequest),
.cpu_jtag_debug_module_resetrequest_from_sa (cpu_jtag_debug_module_resetrequest_from_sa),
.cpu_jtag_debug_module_write (cpu_jtag_debug_module_write),
.cpu_jtag_debug_module_writedata (cpu_jtag_debug_module_writedata),
.d1_cpu_jtag_debug_module_end_xfer (d1_cpu_jtag_debug_module_end_xfer),
.reset_n (clk_50_reset_n)
);
cpu_data_master_arbitrator the_cpu_data_master
(
.cfi_flash_s1_wait_counter_eq_0 (cfi_flash_s1_wait_counter_eq_0),
.cfi_flash_s1_wait_counter_eq_1 (cfi_flash_s1_wait_counter_eq_1),
.clk (clk_50),
.cpu_data_master_address (cpu_data_master_address),
.cpu_data_master_address_to_slave (cpu_data_master_address_to_slave),
.cpu_data_master_byteenable_cfi_flash_s1 (cpu_data_master_byteenable_cfi_flash_s1),
.cpu_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0 (cpu_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0),
.cpu_data_master_dbs_address (cpu_data_master_dbs_address),
.cpu_data_master_dbs_write_16 (cpu_data_master_dbs_write_16),
.cpu_data_master_dbs_write_8 (cpu_data_master_dbs_write_8),
.cpu_data_master_granted_cfi_flash_s1 (cpu_data_master_granted_cfi_flash_s1),
.cpu_data_master_granted_cpu_jtag_debug_module (cpu_data_master_granted_cpu_jtag_debug_module),
.cpu_data_master_granted_epcs_flash_controller_epcs_control_port (cpu_data_master_granted_epcs_flash_controller_epcs_control_port),
.cpu_data_master_granted_gpio_s1 (cpu_data_master_granted_gpio_s1),
.cpu_data_master_granted_hardmodle_s1 (cpu_data_master_granted_hardmodle_s1),
.cpu_data_master_granted_jtag_uart_avalon_jtag_slave (cpu_data_master_granted_jtag_uart_avalon_jtag_slave),
.cpu_data_master_granted_kernel_clock_0_in (cpu_data_master_granted_kernel_clock_0_in),
.cpu_data_master_granted_key_s1 (cpu_data_master_granted_key_s1),
.cpu_data_master_granted_lcd_0_control_slave (cpu_data_master_granted_lcd_0_control_slave),
.cpu_data_master_granted_onchip_memory_s1 (cpu_data_master_granted_onchip_memory_s1),
.cpu_data_master_granted_pll_pll_slave (cpu_data_master_granted_pll_pll_slave),
.cpu_data_master_granted_sram_16bit_512k_0_avalon_slave_0 (cpu_data_master_granted_sram_16bit_512k_0_avalon_slave_0),
.cpu_data_master_granted_timer_s1 (cpu_data_master_granted_timer_s1),
.cpu_data_master_irq (cpu_data_master_irq),
.cpu_data_master_no_byte_enables_and_last_term (cpu_data_master_no_byte_enables_and_last_term),
.cpu_data_master_qualified_request_cfi_flash_s1 (cpu_data_master_qualified_request_cfi_flash_s1),
.cpu_data_master_qualified_request_cpu_jtag_debug_module (cpu_data_master_qualified_request_cpu_jtag_debug_module),
.cpu_data_master_qualified_request_epcs_flash_controller_epcs_control_port (cpu_data_master_qualified_request_epcs_flash_controller_epcs_control_port),
.cpu_data_master_qualified_request_gpio_s1 (cpu_data_master_qualified_request_gpio_s1),
.cpu_data_master_qualified_request_hardmodle_s1 (cpu_data_master_qualified_request_hardmodle_s1),
.cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave (cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave),
.cpu_data_master_qualified_request_kernel_clock_0_in (cpu_data_master_qualified_request_kernel_clock_0_in),
.cpu_data_master_qualified_request_key_s1 (cpu_data_master_qualified_request_key_s1),
.cpu_data_master_qualified_request_lcd_0_control_slave (cpu_data_master_qualified_request_lcd_0_control_slave),
.cpu_data_master_qualified_request_onchip_memory_s1 (cpu_data_master_qualified_request_onchip_memory_s1),
.cpu_data_master_qualified_request_pll_pll_slave (cpu_data_master_qualified_request_pll_pll_slave),
.cpu_data_master_qualified_request_sram_16bit_512k_0_avalon_slave_0 (cpu_data_master_qualified_request_sram_16bit_512k_0_avalon_slave_0),
.cpu_data_master_qualified_request_timer_s1 (cpu_data_master_qualified_request_timer_s1),
.cpu_data_master_read (cpu_data_master_read),
.cpu_data_master_read_data_valid_cfi_flash_s1 (cpu_data_master_read_data_valid_cfi_flash_s1),
.cpu_data_master_read_data_valid_cpu_jtag_debug_module (cpu_data_master_read_data_valid_cpu_jtag_debug_module),
.cpu_data_master_read_data_valid_epcs_flash_controller_epcs_control_port (cpu_data_master_read_data_valid_epcs_flash_controller_epcs_control_port),
.cpu_data_master_read_data_valid_gpio_s1 (cpu_data_master_read_data_valid_gpio_s1),
.cpu_data_master_read_data_valid_hardmodle_s1 (cpu_data_master_read_data_valid_hardmodle_s1),
.cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave (cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave),
.cpu_data_master_read_data_valid_kernel_clock_0_in (cpu_data_master_read_data_valid_kernel_clock_0_in),
.cpu_data_master_read_data_valid_key_s1 (cpu_data_master_read_data_valid_key_s1),
.cpu_data_master_read_data_valid_lcd_0_control_slave (cpu_data_master_read_data_valid_lcd_0_control_slave),
.cpu_data_master_read_data_valid_onchip_memory_s1 (cpu_data_master_read_data_valid_onchip_memory_s1),
.cpu_data_master_read_data_valid_pll_pll_slave (cpu_data_master_read_data_valid_pll_pll_slave),
.cpu_data_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0 (cpu_data_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0),
.cpu_data_master_read_data_valid_timer_s1 (cpu_data_master_read_data_valid_timer_s1),
.cpu_data_master_readdata (cpu_data_master_readdata),
.cpu_data_master_requests_cfi_flash_s1 (cpu_data_master_requests_cfi_flash_s1),
.cpu_data_master_requests_cpu_jtag_debug_module (cpu_data_master_requests_cpu_jtag_debug_module),
.cpu_data_master_requests_epcs_flash_controller_epcs_control_port (cpu_data_master_requests_epcs_flash_controller_epcs_control_port),
.cpu_data_master_requests_gpio_s1 (cpu_data_master_requests_gpio_s1),
.cpu_data_master_requests_hardmodle_s1 (cpu_data_master_requests_hardmodle_s1),
.cpu_data_master_requests_jtag_uart_avalon_jtag_slave (cpu_data_master_requests_jtag_uart_avalon_jtag_slave),
.cpu_data_master_requests_kernel_clock_0_in (cpu_data_master_requests_kernel_clock_0_in),
.cpu_data_master_requests_key_s1 (cpu_data_master_requests_key_s1),
.cpu_data_master_requests_lcd_0_control_slave (cpu_data_master_requests_lcd_0_control_slave),
.cpu_data_master_requests_onchip_memory_s1 (cpu_data_master_requests_onchip_memory_s1),
.cpu_data_master_requests_pll_pll_slave (cpu_data_master_requests_pll_pll_slave),
.cpu_data_master_requests_sram_16bit_512k_0_avalon_slave_0 (cpu_data_master_requests_sram_16bit_512k_0_avalon_slave_0),
.cpu_data_master_requests_timer_s1 (cpu_data_master_requests_timer_s1),
.cpu_data_master_waitrequest (cpu_data_master_waitrequest),
.cpu_data_master_write (cpu_data_master_write),
.cpu_data_master_writedata (cpu_data_master_writedata),
.cpu_jtag_debug_module_readdata_from_sa (cpu_jtag_debug_module_readdata_from_sa),
.d1_cpu_jtag_debug_module_end_xfer (d1_cpu_jtag_debug_module_end_xfer),
.d1_epcs_flash_controller_epcs_control_port_end_xfer (d1_epcs_flash_controller_epcs_control_port_end_xfer),
.d1_gpio_s1_end_xfer (d1_gpio_s1_end_xfer),
.d1_hardmodle_s1_end_xfer (d1_hardmodle_s1_end_xfer),
.d1_jtag_uart_avalon_jtag_slave_end_xfer (d1_jtag_uart_avalon_jtag_slave_end_xfer),
.d1_kernel_clock_0_in_end_xfer (d1_kernel_clock_0_in_end_xfer),
.d1_key_s1_end_xfer (d1_key_s1_end_xfer),
.d1_lcd_0_control_slave_end_xfer (d1_lcd_0_control_slave_end_xfer),
.d1_onchip_memory_s1_end_xfer (d1_onchip_memory_s1_end_xfer),
.d1_pll_pll_slave_end_xfer (d1_pll_pll_slave_end_xfer),
.d1_sram_16bit_512k_0_avalon_slave_0_end_xfer (d1_sram_16bit_512k_0_avalon_slave_0_end_xfer),
.d1_timer_s1_end_xfer (d1_timer_s1_end_xfer),
.d1_tri_state_bridge_avalon_slave_end_xfer (d1_tri_state_bridge_avalon_slave_end_xfer),
.epcs_flash_controller_epcs_control_port_irq_from_sa (epcs_flash_controller_epcs_control_port_irq_from_sa),
.epcs_flash_controller_epcs_control_port_readdata_from_sa (epcs_flash_controller_epcs_control_port_readdata_from_sa),
.gpio_s1_irq_from_sa (gpio_s1_irq_from_sa),
.gpio_s1_readdata_from_sa (gpio_s1_readdata_from_sa),
.hardmodle_s1_readdata_from_sa (hardmodle_s1_readdata_from_sa),
.incoming_tri_state_bridge_data_with_Xs_converted_to_0 (incoming_tri_state_bridge_data_with_Xs_converted_to_0),
.jtag_uart_avalon_jtag_slave_irq_from_sa (jtag_uart_avalon_jtag_slave_irq_from_sa),
.jtag_uart_avalon_jtag_slave_readdata_from_sa (jtag_uart_avalon_jtag_slave_readdata_from_sa),
.jtag_uart_avalon_jtag_slave_waitrequest_from_sa (jtag_uart_avalon_jtag_slave_waitrequest_from_sa),
.kernel_clock_0_in_readdata_from_sa (kernel_clock_0_in_readdata_from_sa),
.kernel_clock_0_in_waitrequest_from_sa (kernel_clock_0_in_waitrequest_from_sa),
.key_s1_irq_from_sa (key_s1_irq_from_sa),
.key_s1_readdata_from_sa (key_s1_readdata_from_sa),
.lcd_0_control_slave_readdata_from_sa (lcd_0_control_slave_readdata_from_sa),
.lcd_0_control_slave_wait_counter_eq_0 (lcd_0_control_slave_wait_counter_eq_0),
.lcd_0_control_slave_wait_counter_eq_1 (lcd_0_control_slave_wait_counter_eq_1),
.onchip_memory_s1_readdata_from_sa (onchip_memory_s1_readdata_from_sa),
.pll_pll_slave_readdata_from_sa (pll_pll_slave_readdata_from_sa),
.registered_cpu_data_master_read_data_valid_cfi_flash_s1 (registered_cpu_data_master_read_data_valid_cfi_flash_s1),
.registered_cpu_data_master_read_data_valid_onchip_memory_s1 (registered_cpu_data_master_read_data_valid_onchip_memory_s1),
.reset_n (clk_50_reset_n),
.sram_16bit_512k_0_avalon_slave_0_readdata_from_sa (sram_16bit_512k_0_avalon_slave_0_readdata_from_sa),
.sram_16bit_512k_0_avalon_slave_0_wait_counter_eq_0 (sram_16bit_512k_0_avalon_slave_0_wait_counter_eq_0),
.timer_s1_irq_from_sa (timer_s1_irq_from_sa),
.timer_s1_readdata_from_sa (timer_s1_readdata_from_sa)
);
cpu_instruction_master_arbitrator the_cpu_instruction_master
(
.cfi_flash_s1_wait_counter_eq_0 (cfi_flash_s1_wait_counter_eq_0),
.cfi_flash_s1_wait_counter_eq_1 (cfi_flash_s1_wait_counter_eq_1),
.clk (clk_50),
.cpu_instruction_master_address (cpu_instruction_master_address),
.cpu_instruction_master_address_to_slave (cpu_instruction_master_address_to_slave),
.cpu_instruction_master_dbs_address (cpu_instruction_master_dbs_address),
.cpu_instruction_master_granted_cfi_flash_s1 (cpu_instruction_master_granted_cfi_flash_s1),
.cpu_instruction_master_granted_cpu_jtag_debug_module (cpu_instruction_master_granted_cpu_jtag_debug_module),
.cpu_instruction_master_granted_epcs_flash_controller_epcs_control_port (cpu_instruction_master_granted_epcs_flash_controller_epcs_control_port),
.cpu_instruction_master_granted_onchip_memory_s1 (cpu_instruction_master_granted_onchip_memory_s1),
.cpu_instruction_master_granted_sram_16bit_512k_0_avalon_slave_0 (cpu_instruction_master_granted_sram_16bit_512k_0_avalon_slave_0),
.cpu_instruction_master_latency_counter (cpu_instruction_master_latency_counter),
.cpu_instruction_master_qualified_request_cfi_flash_s1 (cpu_instruction_master_qualified_request_cfi_flash_s1),
.cpu_instruction_master_qualified_request_cpu_jtag_debug_module (cpu_instruction_master_qualified_request_cpu_jtag_debug_module),
.cpu_instruction_master_qualified_request_epcs_flash_controller_epcs_control_port (cpu_instruction_master_qualified_request_epcs_flash_controller_epcs_control_port),
.cpu_instruction_master_qualified_request_onchip_memory_s1 (cpu_instruction_master_qualified_request_onchip_memory_s1),
.cpu_instruction_master_qualified_request_sram_16bit_512k_0_avalon_slave_0 (cpu_instruction_master_qualified_request_sram_16bit_512k_0_avalon_slave_0),
.cpu_instruction_master_read (cpu_instruction_master_read),
.cpu_instruction_master_read_data_valid_cfi_flash_s1 (cpu_instruction_master_read_data_valid_cfi_flash_s1),
.cpu_instruction_master_read_data_valid_cpu_jtag_debug_module (cpu_instruction_master_read_data_valid_cpu_jtag_debug_module),
.cpu_instruction_master_read_data_valid_epcs_flash_controller_epcs_control_port (cpu_instruction_master_read_data_valid_epcs_flash_controller_epcs_control_port),
.cpu_instruction_master_read_data_valid_onchip_memory_s1 (cpu_instruction_master_read_data_valid_onchip_memory_s1),
.cpu_instruction_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0 (cpu_instruction_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0),
.cpu_instruction_master_readdata (cpu_instruction_master_readdata),
.cpu_instruction_master_readdatavalid (cpu_instruction_master_readdatavalid),
.cpu_instruction_master_requests_cfi_flash_s1 (cpu_instruction_master_requests_cfi_flash_s1),
.cpu_instruction_master_requests_cpu_jtag_debug_module (cpu_instruction_master_requests_cpu_jtag_debug_module),
.cpu_instruction_master_requests_epcs_flash_controller_epcs_control_port (cpu_instruction_master_requests_epcs_flash_controller_epcs_control_port),
.cpu_instruction_master_requests_onchip_memory_s1 (cpu_instruction_master_requests_onchip_memory_s1),
.cpu_instruction_master_requests_sram_16bit_512k_0_avalon_slave_0 (cpu_instruction_master_requests_sram_16bit_512k_0_avalon_slave_0),
.cpu_instruction_master_waitrequest (cpu_instruction_master_waitrequest),
.cpu_jtag_debug_module_readdata_from_sa (cpu_jtag_debug_module_readdata_from_sa),
.d1_cpu_jtag_debug_module_end_xfer (d1_cpu_jtag_debug_module_end_xfer),
.d1_epcs_flash_controller_epcs_control_port_end_xfer (d1_epcs_flash_controller_epcs_control_port_end_xfer),
.d1_onchip_memory_s1_end_xfer (d1_onchip_memory_s1_end_xfer),
.d1_sram_16bit_512k_0_avalon_slave_0_end_xfer (d1_sram_16bit_512k_0_avalon_slave_0_end_xfer),
.d1_tri_state_bridge_avalon_slave_end_xfer (d1_tri_state_bridge_avalon_slave_end_xfer),
.epcs_flash_controller_epcs_control_port_readdata_from_sa (epcs_flash_controller_epcs_control_port_readdata_from_sa),
.incoming_tri_state_bridge_data (incoming_tri_state_bridge_data),
.onchip_memory_s1_readdata_from_sa (onchip_memory_s1_readdata_from_sa),
.reset_n (clk_50_reset_n),
.sram_16bit_512k_0_avalon_slave_0_readdata_from_sa (sram_16bit_512k_0_avalon_slave_0_readdata_from_sa),
.sram_16bit_512k_0_avalon_slave_0_wait_counter_eq_0 (sram_16bit_512k_0_avalon_slave_0_wait_counter_eq_0)
);
cpu the_cpu
(
.clk (clk_50),
.d_address (cpu_data_master_address),
.d_byteenable (cpu_data_master_byteenable),
.d_irq (cpu_data_master_irq),
.d_read (cpu_data_master_read),
.d_readdata (cpu_data_master_readdata),
.d_waitrequest (cpu_data_master_waitrequest),
.d_write (cpu_data_master_write),
.d_writedata (cpu_data_master_writedata),
.i_address (cpu_instruction_master_address),
.i_read (cpu_instruction_master_read),
.i_readdata (cpu_instruction_master_readdata),
.i_readdatavalid (cpu_instruction_master_readdatavalid),
.i_waitrequest (cpu_instruction_master_waitrequest),
.jtag_debug_module_address (cpu_jtag_debug_module_address),
.jtag_debug_module_begintransfer (cpu_jtag_debug_module_begintransfer),
.jtag_debug_module_byteenable (cpu_jtag_debug_module_byteenable),
.jtag_debug_module_debugaccess (cpu_jtag_debug_module_debugaccess),
.jtag_debug_module_debugaccess_to_roms (cpu_data_master_debugaccess),
.jtag_debug_module_readdata (cpu_jtag_debug_module_readdata),
.jtag_debug_module_resetrequest (cpu_jtag_debug_module_resetrequest),
.jtag_debug_module_select (cpu_jtag_debug_module_chipselect),
.jtag_debug_module_write (cpu_jtag_debug_module_write),
.jtag_debug_module_writedata (cpu_jtag_debug_module_writedata),
.reset_n (cpu_jtag_debug_module_reset_n)
);
epcs_flash_controller_epcs_control_port_arbitrator the_epcs_flash_controller_epcs_control_port
(
.clk (clk_50),
.cpu_data_master_address_to_slave (cpu_data_master_address_to_slave),
.cpu_data_master_granted_epcs_flash_controller_epcs_control_port (cpu_data_master_granted_epcs_flash_controller_epcs_control_port),
.cpu_data_master_qualified_request_epcs_flash_controller_epcs_control_port (cpu_data_master_qualified_request_epcs_flash_controller_epcs_control_port),
.cpu_data_master_read (cpu_data_master_read),
.cpu_data_master_read_data_valid_epcs_flash_controller_epcs_control_port (cpu_data_master_read_data_valid_epcs_flash_controller_epcs_control_port),
.cpu_data_master_requests_epcs_flash_controller_epcs_control_port (cpu_data_master_requests_epcs_flash_controller_epcs_control_port),
.cpu_data_master_write (cpu_data_master_write),
.cpu_data_master_writedata (cpu_data_master_writedata),
.cpu_instruction_master_address_to_slave (cpu_instruction_master_address_to_slave),
.cpu_instruction_master_granted_epcs_flash_controller_epcs_control_port (cpu_instruction_master_granted_epcs_flash_controller_epcs_control_port),
.cpu_instruction_master_latency_counter (cpu_instruction_master_latency_counter),
.cpu_instruction_master_qualified_request_epcs_flash_controller_epcs_control_port (cpu_instruction_master_qualified_request_epcs_flash_controller_epcs_control_port),
.cpu_instruction_master_read (cpu_instruction_master_read),
.cpu_instruction_master_read_data_valid_epcs_flash_controller_epcs_control_port (cpu_instruction_master_read_data_valid_epcs_flash_controller_epcs_control_port),
.cpu_instruction_master_requests_epcs_flash_controller_epcs_control_port (cpu_instruction_master_requests_epcs_flash_controller_epcs_control_port),
.d1_epcs_flash_controller_epcs_control_port_end_xfer (d1_epcs_flash_controller_epcs_control_port_end_xfer),
.epcs_flash_controller_epcs_control_port_address (epcs_flash_controller_epcs_control_port_address),
.epcs_flash_controller_epcs_control_port_chipselect (epcs_flash_controller_epcs_control_port_chipselect),
.epcs_flash_controller_epcs_control_port_dataavailable (epcs_flash_controller_epcs_control_port_dataavailable),
.epcs_flash_controller_epcs_control_port_dataavailable_from_sa (epcs_flash_controller_epcs_control_port_dataavailable_from_sa),
.epcs_flash_controller_epcs_control_port_endofpacket (epcs_flash_controller_epcs_control_port_endofpacket),
.epcs_flash_controller_epcs_control_port_endofpacket_from_sa (epcs_flash_controller_epcs_control_port_endofpacket_from_sa),
.epcs_flash_controller_epcs_control_port_irq (epcs_flash_controller_epcs_control_port_irq),
.epcs_flash_controller_epcs_control_port_irq_from_sa (epcs_flash_controller_epcs_control_port_irq_from_sa),
.epcs_flash_controller_epcs_control_port_read_n (epcs_flash_controller_epcs_control_port_read_n),
.epcs_flash_controller_epcs_control_port_readdata (epcs_flash_controller_epcs_control_port_readdata),
.epcs_flash_controller_epcs_control_port_readdata_from_sa (epcs_flash_controller_epcs_control_port_readdata_from_sa),
.epcs_flash_controller_epcs_control_port_readyfordata (epcs_flash_controller_epcs_control_port_readyfordata),
.epcs_flash_controller_epcs_control_port_readyfordata_from_sa (epcs_flash_controller_epcs_control_port_readyfordata_from_sa),
.epcs_flash_controller_epcs_control_port_reset_n (epcs_flash_controller_epcs_control_port_reset_n),
.epcs_flash_controller_epcs_control_port_write_n (epcs_flash_controller_epcs_control_port_write_n),
.epcs_flash_controller_epcs_control_port_writedata (epcs_flash_controller_epcs_control_port_writedata),
.reset_n (clk_50_reset_n)
);
epcs_flash_controller the_epcs_flash_controller
(
.address (epcs_flash_controller_epcs_control_port_address),
.chipselect (epcs_flash_controller_epcs_control_port_chipselect),
.clk (clk_50),
.dataavailable (epcs_flash_controller_epcs_control_port_dataavailable),
.endofpacket (epcs_flash_controller_epcs_control_port_endofpacket),
.irq (epcs_flash_controller_epcs_control_port_irq),
.read_n (epcs_flash_controller_epcs_control_port_read_n),
.readdata (epcs_flash_controller_epcs_control_port_readdata),
.readyfordata (epcs_flash_controller_epcs_control_port_readyfordata),
.reset_n (epcs_flash_controller_epcs_control_port_reset_n),
.write_n (epcs_flash_controller_epcs_control_port_write_n),
.writedata (epcs_flash_controller_epcs_control_port_writedata)
);
gpio_s1_arbitrator the_gpio_s1
(
.clk (clk_50),
.cpu_data_master_address_to_slave (cpu_data_master_address_to_slave),
.cpu_data_master_granted_gpio_s1 (cpu_data_master_granted_gpio_s1),
.cpu_data_master_qualified_request_gpio_s1 (cpu_data_master_qualified_request_gpio_s1),
.cpu_data_master_read (cpu_data_master_read),
.cpu_data_master_read_data_valid_gpio_s1 (cpu_data_master_read_data_valid_gpio_s1),
.cpu_data_master_requests_gpio_s1 (cpu_data_master_requests_gpio_s1),
.cpu_data_master_waitrequest (cpu_data_master_waitrequest),
.cpu_data_master_write (cpu_data_master_write),
.cpu_data_master_writedata (cpu_data_master_writedata),
.d1_gpio_s1_end_xfer (d1_gpio_s1_end_xfer),
.gpio_s1_address (gpio_s1_address),
.gpio_s1_chipselect (gpio_s1_chipselect),
.gpio_s1_irq (gpio_s1_irq),
.gpio_s1_irq_from_sa (gpio_s1_irq_from_sa),
.gpio_s1_readdata (gpio_s1_readdata),
.gpio_s1_readdata_from_sa (gpio_s1_readdata_from_sa),
.gpio_s1_reset_n (gpio_s1_reset_n),
.gpio_s1_write_n (gpio_s1_write_n),
.gpio_s1_writedata (gpio_s1_writedata),
.reset_n (clk_50_reset_n)
);
gpio the_gpio
(
.address (gpio_s1_address),
.chipselect (gpio_s1_chipselect),
.clk (clk_50),
.in_port (in_port_to_the_gpio),
.irq (gpio_s1_irq),
.readdata (gpio_s1_readdata),
.reset_n (gpio_s1_reset_n),
.write_n (gpio_s1_write_n),
.writedata (gpio_s1_writedata)
);
hardmodle_s1_arbitrator the_hardmodle_s1
(
.clk (clk_50),
.cpu_data_master_address_to_slave (cpu_data_master_address_to_slave),
.cpu_data_master_granted_hardmodle_s1 (cpu_data_master_granted_hardmodle_s1),
.cpu_data_master_qualified_request_hardmodle_s1 (cpu_data_master_qualified_request_hardmodle_s1),
.cpu_data_master_read (cpu_data_master_read),
.cpu_data_master_read_data_valid_hardmodle_s1 (cpu_data_master_read_data_valid_hardmodle_s1),
.cpu_data_master_requests_hardmodle_s1 (cpu_data_master_requests_hardmodle_s1),
.cpu_data_master_write (cpu_data_master_write),
.d1_hardmodle_s1_end_xfer (d1_hardmodle_s1_end_xfer),
.hardmodle_s1_address (hardmodle_s1_address),
.hardmodle_s1_readdata (hardmodle_s1_readdata),
.hardmodle_s1_readdata_from_sa (hardmodle_s1_readdata_from_sa),
.hardmodle_s1_reset_n (hardmodle_s1_reset_n),
.reset_n (clk_50_reset_n)
);
hardmodle the_hardmodle
(
.address (hardmodle_s1_address),
.clk (clk_50),
.in_port (in_port_to_the_hardmodle),
.readdata (hardmodle_s1_readdata),
.reset_n (hardmodle_s1_reset_n)
);
jtag_uart_avalon_jtag_slave_arbitrator the_jtag_uart_avalon_jtag_slave
(
.clk (clk_50),
.cpu_data_master_address_to_slave (cpu_data_master_address_to_slave),
.cpu_data_master_granted_jtag_uart_avalon_jtag_slave (cpu_data_master_granted_jtag_uart_avalon_jtag_slave),
.cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave (cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave),
.cpu_data_master_read (cpu_data_master_read),
.cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave (cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave),
.cpu_data_master_requests_jtag_uart_avalon_jtag_slave (cpu_data_master_requests_jtag_uart_avalon_jtag_slave),
.cpu_data_master_waitrequest (cpu_data_master_waitrequest),
.cpu_data_master_write (cpu_data_master_write),
.cpu_data_master_writedata (cpu_data_master_writedata),
.d1_jtag_uart_avalon_jtag_slave_end_xfer (d1_jtag_uart_avalon_jtag_slave_end_xfer),
.jtag_uart_avalon_jtag_slave_address (jtag_uart_avalon_jtag_slave_address),
.jtag_uart_avalon_jtag_slave_chipselect (jtag_uart_avalon_jtag_slave_chipselect),
.jtag_uart_avalon_jtag_slave_dataavailable (jtag_uart_avalon_jtag_slave_dataavailable),
.jtag_uart_avalon_jtag_slave_dataavailable_from_sa (jtag_uart_avalon_jtag_slave_dataavailable_from_sa),
.jtag_uart_avalon_jtag_slave_irq (jtag_uart_avalon_jtag_slave_irq),
.jtag_uart_avalon_jtag_slave_irq_from_sa (jtag_uart_avalon_jtag_slave_irq_from_sa),
.jtag_uart_avalon_jtag_slave_read_n (jtag_uart_avalon_jtag_slave_read_n),
.jtag_uart_avalon_jtag_slave_readdata (jtag_uart_avalon_jtag_slave_readdata),
.jtag_uart_avalon_jtag_slave_readdata_from_sa (jtag_uart_avalon_jtag_slave_readdata_from_sa),
.jtag_uart_avalon_jtag_slave_readyfordata (jtag_uart_avalon_jtag_slave_readyfordata),
.jtag_uart_avalon_jtag_slave_readyfordata_from_sa (jtag_uart_avalon_jtag_slave_readyfordata_from_sa),
.jtag_uart_avalon_jtag_slave_reset_n (jtag_uart_avalon_jtag_slave_reset_n),
.jtag_uart_avalon_jtag_slave_waitrequest (jtag_uart_avalon_jtag_slave_waitrequest),
.jtag_uart_avalon_jtag_slave_waitrequest_from_sa (jtag_uart_avalon_jtag_slave_waitrequest_from_sa),
.jtag_uart_avalon_jtag_slave_write_n (jtag_uart_avalon_jtag_slave_write_n),
.jtag_uart_avalon_jtag_slave_writedata (jtag_uart_avalon_jtag_slave_writedata),
.reset_n (clk_50_reset_n)
);
jtag_uart the_jtag_uart
(
.av_address (jtag_uart_avalon_jtag_slave_address),
.av_chipselect (jtag_uart_avalon_jtag_slave_chipselect),
.av_irq (jtag_uart_avalon_jtag_slave_irq),
.av_read_n (jtag_uart_avalon_jtag_slave_read_n),
.av_readdata (jtag_uart_avalon_jtag_slave_readdata),
.av_waitrequest (jtag_uart_avalon_jtag_slave_waitrequest),
.av_write_n (jtag_uart_avalon_jtag_slave_write_n),
.av_writedata (jtag_uart_avalon_jtag_slave_writedata),
.clk (clk_50),
.dataavailable (jtag_uart_avalon_jtag_slave_dataavailable),
.readyfordata (jtag_uart_avalon_jtag_slave_readyfordata),
.rst_n (jtag_uart_avalon_jtag_slave_reset_n)
);
kernel_clock_0_in_arbitrator the_kernel_clock_0_in
(
.clk (clk_50),
.cpu_data_master_address_to_slave (cpu_data_master_address_to_slave),
.cpu_data_master_byteenable (cpu_data_master_byteenable),
.cpu_data_master_granted_kernel_clock_0_in (cpu_data_master_granted_kernel_clock_0_in),
.cpu_data_master_qualified_request_kernel_clock_0_in (cpu_data_master_qualified_request_kernel_clock_0_in),
.cpu_data_master_read (cpu_data_master_read),
.cpu_data_master_read_data_valid_kernel_clock_0_in (cpu_data_master_read_data_valid_kernel_clock_0_in),
.cpu_data_master_requests_kernel_clock_0_in (cpu_data_master_requests_kernel_clock_0_in),
.cpu_data_master_waitrequest (cpu_data_master_waitrequest),
.cpu_data_master_write (cpu_data_master_write),
.cpu_data_master_writedata (cpu_data_master_writedata),
.d1_kernel_clock_0_in_end_xfer (d1_kernel_clock_0_in_end_xfer),
.kernel_clock_0_in_address (kernel_clock_0_in_address),
.kernel_clock_0_in_byteenable (kernel_clock_0_in_byteenable),
.kernel_clock_0_in_endofpacket (kernel_clock_0_in_endofpacket),
.kernel_clock_0_in_endofpacket_from_sa (kernel_clock_0_in_endofpacket_from_sa),
.kernel_clock_0_in_nativeaddress (kernel_clock_0_in_nativeaddress),
.kernel_clock_0_in_read (kernel_clock_0_in_read),
.kernel_clock_0_in_readdata (kernel_clock_0_in_readdata),
.kernel_clock_0_in_readdata_from_sa (kernel_clock_0_in_readdata_from_sa),
.kernel_clock_0_in_reset_n (kernel_clock_0_in_reset_n),
.kernel_clock_0_in_waitrequest (kernel_clock_0_in_waitrequest),
.kernel_clock_0_in_waitrequest_from_sa (kernel_clock_0_in_waitrequest_from_sa),
.kernel_clock_0_in_write (kernel_clock_0_in_write),
.kernel_clock_0_in_writedata (kernel_clock_0_in_writedata),
.reset_n (clk_50_reset_n)
);
kernel_clock_0_out_arbitrator the_kernel_clock_0_out
(
.clk (pll_c0_out),
.d1_vga_0_avalon_slave_0_end_xfer (d1_vga_0_avalon_slave_0_end_xfer),
.kernel_clock_0_out_address (kernel_clock_0_out_address),
.kernel_clock_0_out_address_to_slave (kernel_clock_0_out_address_to_slave),
.kernel_clock_0_out_byteenable (kernel_clock_0_out_byteenable),
.kernel_clock_0_out_granted_vga_0_avalon_slave_0 (kernel_clock_0_out_granted_vga_0_avalon_slave_0),
.kernel_clock_0_out_qualified_request_vga_0_avalon_slave_0 (kernel_clock_0_out_qualified_request_vga_0_avalon_slave_0),
.kernel_clock_0_out_read (kernel_clock_0_out_read),
.kernel_clock_0_out_read_data_valid_vga_0_avalon_slave_0 (kernel_clock_0_out_read_data_valid_vga_0_avalon_slave_0),
.kernel_clock_0_out_readdata (kernel_clock_0_out_readdata),
.kernel_clock_0_out_requests_vga_0_avalon_slave_0 (kernel_clock_0_out_requests_vga_0_avalon_slave_0),
.kernel_clock_0_out_reset_n (kernel_clock_0_out_reset_n),
.kernel_clock_0_out_waitrequest (kernel_clock_0_out_waitrequest),
.kernel_clock_0_out_write (kernel_clock_0_out_write),
.kernel_clock_0_out_writedata (kernel_clock_0_out_writedata),
.reset_n (pll_c0_out_reset_n),
.vga_0_avalon_slave_0_readdata_from_sa (vga_0_avalon_slave_0_readdata_from_sa),
.vga_0_avalon_slave_0_wait_counter_eq_0 (vga_0_avalon_slave_0_wait_counter_eq_0)
);
kernel_clock_0 the_kernel_clock_0
(
.master_address (kernel_clock_0_out_address),
.master_byteenable (kernel_clock_0_out_byteenable),
.master_clk (pll_c0_out),
.master_endofpacket (kernel_clock_0_out_endofpacket),
.master_nativeaddress (kernel_clock_0_out_nativeaddress),
.master_read (kernel_clock_0_out_read),
.master_readdata (kernel_clock_0_out_readdata),
.master_reset_n (kernel_clock_0_out_reset_n),
.master_waitrequest (kernel_clock_0_out_waitrequest),
.master_write (kernel_clock_0_out_write),
.master_writedata (kernel_clock_0_out_writedata),
.slave_address (kernel_clock_0_in_address),
.slave_byteenable (kernel_clock_0_in_byteenable),
.slave_clk (clk_50),
.slave_endofpacket (kernel_clock_0_in_endofpacket),
.slave_nativeaddress (kernel_clock_0_in_nativeaddress),
.slave_read (kernel_clock_0_in_read),
.slave_readdata (kernel_clock_0_in_readdata),
.slave_reset_n (kernel_clock_0_in_reset_n),
.slave_waitrequest (kernel_clock_0_in_waitrequest),
.slave_write (kernel_clock_0_in_write),
.slave_writedata (kernel_clock_0_in_writedata)
);
key_s1_arbitrator the_key_s1
(
.clk (clk_50),
.cpu_data_master_address_to_slave (cpu_data_master_address_to_slave),
.cpu_data_master_granted_key_s1 (cpu_data_master_granted_key_s1),
.cpu_data_master_qualified_request_key_s1 (cpu_data_master_qualified_request_key_s1),
.cpu_data_master_read (cpu_data_master_read),
.cpu_data_master_read_data_valid_key_s1 (cpu_data_master_read_data_valid_key_s1),
.cpu_data_master_requests_key_s1 (cpu_data_master_requests_key_s1),
.cpu_data_master_waitrequest (cpu_data_master_waitrequest),
.cpu_data_master_write (cpu_data_master_write),
.cpu_data_master_writedata (cpu_data_master_writedata),
.d1_key_s1_end_xfer (d1_key_s1_end_xfer),
.key_s1_address (key_s1_address),
.key_s1_chipselect (key_s1_chipselect),
.key_s1_irq (key_s1_irq),
.key_s1_irq_from_sa (key_s1_irq_from_sa),
.key_s1_readdata (key_s1_readdata),
.key_s1_readdata_from_sa (key_s1_readdata_from_sa),
.key_s1_reset_n (key_s1_reset_n),
.key_s1_write_n (key_s1_write_n),
.key_s1_writedata (key_s1_writedata),
.reset_n (clk_50_reset_n)
);
key the_key
(
.address (key_s1_address),
.chipselect (key_s1_chipselect),
.clk (clk_50),
.in_port (in_port_to_the_key),
.irq (key_s1_irq),
.readdata (key_s1_readdata),
.reset_n (key_s1_reset_n),
.write_n (key_s1_write_n),
.writedata (key_s1_writedata)
);
lcd_0_control_slave_arbitrator the_lcd_0_control_slave
(
.clk (clk_50),
.cpu_data_master_address_to_slave (cpu_data_master_address_to_slave),
.cpu_data_master_byteenable (cpu_data_master_byteenable),
.cpu_data_master_granted_lcd_0_control_slave (cpu_data_master_granted_lcd_0_control_slave),
.cpu_data_master_qualified_request_lcd_0_control_slave (cpu_data_master_qualified_request_lcd_0_control_slave),
.cpu_data_master_read (cpu_data_master_read),
.cpu_data_master_read_data_valid_lcd_0_control_slave (cpu_data_master_read_data_valid_lcd_0_control_slave),
.cpu_data_master_requests_lcd_0_control_slave (cpu_data_master_requests_lcd_0_control_slave),
.cpu_data_master_write (cpu_data_master_write),
.cpu_data_master_writedata (cpu_data_master_writedata),
.d1_lcd_0_control_slave_end_xfer (d1_lcd_0_control_slave_end_xfer),
.lcd_0_control_slave_address (lcd_0_control_slave_address),
.lcd_0_control_slave_begintransfer (lcd_0_control_slave_begintransfer),
.lcd_0_control_slave_read (lcd_0_control_slave_read),
.lcd_0_control_slave_readdata (lcd_0_control_slave_readdata),
.lcd_0_control_slave_readdata_from_sa (lcd_0_control_slave_readdata_from_sa),
.lcd_0_control_slave_reset_n (lcd_0_control_slave_reset_n),
.lcd_0_control_slave_wait_counter_eq_0 (lcd_0_control_slave_wait_counter_eq_0),
.lcd_0_control_slave_wait_counter_eq_1 (lcd_0_control_slave_wait_counter_eq_1),
.lcd_0_control_slave_write (lcd_0_control_slave_write),
.lcd_0_control_slave_writedata (lcd_0_control_slave_writedata),
.reset_n (clk_50_reset_n)
);
lcd_0 the_lcd_0
(
.LCD_E (LCD_E_from_the_lcd_0),
.LCD_RS (LCD_RS_from_the_lcd_0),
.LCD_RW (LCD_RW_from_the_lcd_0),
.LCD_data (LCD_data_to_and_from_the_lcd_0),
.address (lcd_0_control_slave_address),
.begintransfer (lcd_0_control_slave_begintransfer),
.clk (clk_50),
.read (lcd_0_control_slave_read),
.readdata (lcd_0_control_slave_readdata),
.reset_n (lcd_0_control_slave_reset_n),
.write (lcd_0_control_slave_write),
.writedata (lcd_0_control_slave_writedata)
);
onchip_memory_s1_arbitrator the_onchip_memory_s1
(
.clk (clk_50),
.cpu_data_master_address_to_slave (cpu_data_master_address_to_slave),
.cpu_data_master_byteenable (cpu_data_master_byteenable),
.cpu_data_master_granted_onchip_memory_s1 (cpu_data_master_granted_onchip_memory_s1),
.cpu_data_master_qualified_request_onchip_memory_s1 (cpu_data_master_qualified_request_onchip_memory_s1),
.cpu_data_master_read (cpu_data_master_read),
.cpu_data_master_read_data_valid_onchip_memory_s1 (cpu_data_master_read_data_valid_onchip_memory_s1),
.cpu_data_master_requests_onchip_memory_s1 (cpu_data_master_requests_onchip_memory_s1),
.cpu_data_master_waitrequest (cpu_data_master_waitrequest),
.cpu_data_master_write (cpu_data_master_write),
.cpu_data_master_writedata (cpu_data_master_writedata),
.cpu_instruction_master_address_to_slave (cpu_instruction_master_address_to_slave),
.cpu_instruction_master_granted_onchip_memory_s1 (cpu_instruction_master_granted_onchip_memory_s1),
.cpu_instruction_master_latency_counter (cpu_instruction_master_latency_counter),
.cpu_instruction_master_qualified_request_onchip_memory_s1 (cpu_instruction_master_qualified_request_onchip_memory_s1),
.cpu_instruction_master_read (cpu_instruction_master_read),
.cpu_instruction_master_read_data_valid_onchip_memory_s1 (cpu_instruction_master_read_data_valid_onchip_memory_s1),
.cpu_instruction_master_requests_onchip_memory_s1 (cpu_instruction_master_requests_onchip_memory_s1),
.d1_onchip_memory_s1_end_xfer (d1_onchip_memory_s1_end_xfer),
.onchip_memory_s1_address (onchip_memory_s1_address),
.onchip_memory_s1_byteenable (onchip_memory_s1_byteenable),
.onchip_memory_s1_chipselect (onchip_memory_s1_chipselect),
.onchip_memory_s1_clken (onchip_memory_s1_clken),
.onchip_memory_s1_readdata (onchip_memory_s1_readdata),
.onchip_memory_s1_readdata_from_sa (onchip_memory_s1_readdata_from_sa),
.onchip_memory_s1_reset (onchip_memory_s1_reset),
.onchip_memory_s1_write (onchip_memory_s1_write),
.onchip_memory_s1_writedata (onchip_memory_s1_writedata),
.registered_cpu_data_master_read_data_valid_onchip_memory_s1 (registered_cpu_data_master_read_data_valid_onchip_memory_s1),
.reset_n (clk_50_reset_n)
);
onchip_memory the_onchip_memory
(
.address (onchip_memory_s1_address),
.byteenable (onchip_memory_s1_byteenable),
.chipselect (onchip_memory_s1_chipselect),
.clk (clk_50),
.clken (onchip_memory_s1_clken),
.readdata (onchip_memory_s1_readdata),
.reset (onchip_memory_s1_reset),
.write (onchip_memory_s1_write),
.writedata (onchip_memory_s1_writedata)
);
pll_pll_slave_arbitrator the_pll_pll_slave
(
.clk (clk_50),
.cpu_data_master_address_to_slave (cpu_data_master_address_to_slave),
.cpu_data_master_granted_pll_pll_slave (cpu_data_master_granted_pll_pll_slave),
.cpu_data_master_qualified_request_pll_pll_slave (cpu_data_master_qualified_request_pll_pll_slave),
.cpu_data_master_read (cpu_data_master_read),
.cpu_data_master_read_data_valid_pll_pll_slave (cpu_data_master_read_data_valid_pll_pll_slave),
.cpu_data_master_requests_pll_pll_slave (cpu_data_master_requests_pll_pll_slave),
.cpu_data_master_waitrequest (cpu_data_master_waitrequest),
.cpu_data_master_write (cpu_data_master_write),
.cpu_data_master_writedata (cpu_data_master_writedata),
.d1_pll_pll_slave_end_xfer (d1_pll_pll_slave_end_xfer),
.pll_pll_slave_address (pll_pll_slave_address),
.pll_pll_slave_read (pll_pll_slave_read),
.pll_pll_slave_readdata (pll_pll_slave_readdata),
.pll_pll_slave_readdata_from_sa (pll_pll_slave_readdata_from_sa),
.pll_pll_slave_reset (pll_pll_slave_reset),
.pll_pll_slave_write (pll_pll_slave_write),
.pll_pll_slave_writedata (pll_pll_slave_writedata),
.reset_n (clk_50_reset_n)
);
//pll_c0_out out_clk assignment, which is an e_assign
assign pll_c0_out = out_clk_pll_c0;
pll the_pll
(
.address (pll_pll_slave_address),
.areset (areset_to_the_pll),
.c0 (out_clk_pll_c0),
.clk (clk_50),
.locked (locked_from_the_pll),
.phasedone (phasedone_from_the_pll),
.read (pll_pll_slave_read),
.readdata (pll_pll_slave_readdata),
.reset (pll_pll_slave_reset),
.write (pll_pll_slave_write),
.writedata (pll_pll_slave_writedata)
);
sram_16bit_512k_0_avalon_slave_0_arbitrator the_sram_16bit_512k_0_avalon_slave_0
(
.clk (clk_50),
.cpu_data_master_address_to_slave (cpu_data_master_address_to_slave),
.cpu_data_master_byteenable (cpu_data_master_byteenable),
.cpu_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0 (cpu_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0),
.cpu_data_master_dbs_address (cpu_data_master_dbs_address),
.cpu_data_master_dbs_write_16 (cpu_data_master_dbs_write_16),
.cpu_data_master_granted_sram_16bit_512k_0_avalon_slave_0 (cpu_data_master_granted_sram_16bit_512k_0_avalon_slave_0),
.cpu_data_master_no_byte_enables_and_last_term (cpu_data_master_no_byte_enables_and_last_term),
.cpu_data_master_qualified_request_sram_16bit_512k_0_avalon_slave_0 (cpu_data_master_qualified_request_sram_16bit_512k_0_avalon_slave_0),
.cpu_data_master_read (cpu_data_master_read),
.cpu_data_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0 (cpu_data_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0),
.cpu_data_master_requests_sram_16bit_512k_0_avalon_slave_0 (cpu_data_master_requests_sram_16bit_512k_0_avalon_slave_0),
.cpu_data_master_write (cpu_data_master_write),
.cpu_instruction_master_address_to_slave (cpu_instruction_master_address_to_slave),
.cpu_instruction_master_dbs_address (cpu_instruction_master_dbs_address),
.cpu_instruction_master_granted_sram_16bit_512k_0_avalon_slave_0 (cpu_instruction_master_granted_sram_16bit_512k_0_avalon_slave_0),
.cpu_instruction_master_latency_counter (cpu_instruction_master_latency_counter),
.cpu_instruction_master_qualified_request_sram_16bit_512k_0_avalon_slave_0 (cpu_instruction_master_qualified_request_sram_16bit_512k_0_avalon_slave_0),
.cpu_instruction_master_read (cpu_instruction_master_read),
.cpu_instruction_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0 (cpu_instruction_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0),
.cpu_instruction_master_requests_sram_16bit_512k_0_avalon_slave_0 (cpu_instruction_master_requests_sram_16bit_512k_0_avalon_slave_0),
.d1_sram_16bit_512k_0_avalon_slave_0_end_xfer (d1_sram_16bit_512k_0_avalon_slave_0_end_xfer),
.reset_n (clk_50_reset_n),
.sram_16bit_512k_0_avalon_slave_0_address (sram_16bit_512k_0_avalon_slave_0_address),
.sram_16bit_512k_0_avalon_slave_0_byteenable_n (sram_16bit_512k_0_avalon_slave_0_byteenable_n),
.sram_16bit_512k_0_avalon_slave_0_chipselect_n (sram_16bit_512k_0_avalon_slave_0_chipselect_n),
.sram_16bit_512k_0_avalon_slave_0_read_n (sram_16bit_512k_0_avalon_slave_0_read_n),
.sram_16bit_512k_0_avalon_slave_0_readdata (sram_16bit_512k_0_avalon_slave_0_readdata),
.sram_16bit_512k_0_avalon_slave_0_readdata_from_sa (sram_16bit_512k_0_avalon_slave_0_readdata_from_sa),
.sram_16bit_512k_0_avalon_slave_0_reset_n (sram_16bit_512k_0_avalon_slave_0_reset_n),
.sram_16bit_512k_0_avalon_slave_0_wait_counter_eq_0 (sram_16bit_512k_0_avalon_slave_0_wait_counter_eq_0),
.sram_16bit_512k_0_avalon_slave_0_write_n (sram_16bit_512k_0_avalon_slave_0_write_n),
.sram_16bit_512k_0_avalon_slave_0_writedata (sram_16bit_512k_0_avalon_slave_0_writedata)
);
sram_16bit_512k_0 the_sram_16bit_512k_0
(
.SRAM_ADDR (SRAM_ADDR_from_the_sram_16bit_512k_0),
.SRAM_CE_N (SRAM_CE_N_from_the_sram_16bit_512k_0),
.SRAM_DQ (SRAM_DQ_to_and_from_the_sram_16bit_512k_0),
.SRAM_LB_N (SRAM_LB_N_from_the_sram_16bit_512k_0),
.SRAM_OE_N (SRAM_OE_N_from_the_sram_16bit_512k_0),
.SRAM_UB_N (SRAM_UB_N_from_the_sram_16bit_512k_0),
.SRAM_WE_N (SRAM_WE_N_from_the_sram_16bit_512k_0),
.iADDR (sram_16bit_512k_0_avalon_slave_0_address),
.iBE_N (sram_16bit_512k_0_avalon_slave_0_byteenable_n),
.iCE_N (sram_16bit_512k_0_avalon_slave_0_chipselect_n),
.iCLK (clk_50),
.iDATA (sram_16bit_512k_0_avalon_slave_0_writedata),
.iOE_N (sram_16bit_512k_0_avalon_slave_0_read_n),
.iRST_N (sram_16bit_512k_0_avalon_slave_0_reset_n),
.iWE_N (sram_16bit_512k_0_avalon_slave_0_write_n),
.oDATA (sram_16bit_512k_0_avalon_slave_0_readdata)
);
timer_s1_arbitrator the_timer_s1
(
.clk (clk_50),
.cpu_data_master_address_to_slave (cpu_data_master_address_to_slave),
.cpu_data_master_granted_timer_s1 (cpu_data_master_granted_timer_s1),
.cpu_data_master_qualified_request_timer_s1 (cpu_data_master_qualified_request_timer_s1),
.cpu_data_master_read (cpu_data_master_read),
.cpu_data_master_read_data_valid_timer_s1 (cpu_data_master_read_data_valid_timer_s1),
.cpu_data_master_requests_timer_s1 (cpu_data_master_requests_timer_s1),
.cpu_data_master_waitrequest (cpu_data_master_waitrequest),
.cpu_data_master_write (cpu_data_master_write),
.cpu_data_master_writedata (cpu_data_master_writedata),
.d1_timer_s1_end_xfer (d1_timer_s1_end_xfer),
.reset_n (clk_50_reset_n),
.timer_s1_address (timer_s1_address),
.timer_s1_chipselect (timer_s1_chipselect),
.timer_s1_irq (timer_s1_irq),
.timer_s1_irq_from_sa (timer_s1_irq_from_sa),
.timer_s1_readdata (timer_s1_readdata),
.timer_s1_readdata_from_sa (timer_s1_readdata_from_sa),
.timer_s1_reset_n (timer_s1_reset_n),
.timer_s1_write_n (timer_s1_write_n),
.timer_s1_writedata (timer_s1_writedata)
);
timer the_timer
(
.address (timer_s1_address),
.chipselect (timer_s1_chipselect),
.clk (clk_50),
.irq (timer_s1_irq),
.readdata (timer_s1_readdata),
.reset_n (timer_s1_reset_n),
.write_n (timer_s1_write_n),
.writedata (timer_s1_writedata)
);
tri_state_bridge_avalon_slave_arbitrator the_tri_state_bridge_avalon_slave
(
.cfi_flash_s1_wait_counter_eq_0 (cfi_flash_s1_wait_counter_eq_0),
.cfi_flash_s1_wait_counter_eq_1 (cfi_flash_s1_wait_counter_eq_1),
.clk (clk_50),
.cpu_data_master_address_to_slave (cpu_data_master_address_to_slave),
.cpu_data_master_byteenable (cpu_data_master_byteenable),
.cpu_data_master_byteenable_cfi_flash_s1 (cpu_data_master_byteenable_cfi_flash_s1),
.cpu_data_master_dbs_address (cpu_data_master_dbs_address),
.cpu_data_master_dbs_write_8 (cpu_data_master_dbs_write_8),
.cpu_data_master_granted_cfi_flash_s1 (cpu_data_master_granted_cfi_flash_s1),
.cpu_data_master_no_byte_enables_and_last_term (cpu_data_master_no_byte_enables_and_last_term),
.cpu_data_master_qualified_request_cfi_flash_s1 (cpu_data_master_qualified_request_cfi_flash_s1),
.cpu_data_master_read (cpu_data_master_read),
.cpu_data_master_read_data_valid_cfi_flash_s1 (cpu_data_master_read_data_valid_cfi_flash_s1),
.cpu_data_master_requests_cfi_flash_s1 (cpu_data_master_requests_cfi_flash_s1),
.cpu_data_master_write (cpu_data_master_write),
.cpu_instruction_master_address_to_slave (cpu_instruction_master_address_to_slave),
.cpu_instruction_master_dbs_address (cpu_instruction_master_dbs_address),
.cpu_instruction_master_granted_cfi_flash_s1 (cpu_instruction_master_granted_cfi_flash_s1),
.cpu_instruction_master_latency_counter (cpu_instruction_master_latency_counter),
.cpu_instruction_master_qualified_request_cfi_flash_s1 (cpu_instruction_master_qualified_request_cfi_flash_s1),
.cpu_instruction_master_read (cpu_instruction_master_read),
.cpu_instruction_master_read_data_valid_cfi_flash_s1 (cpu_instruction_master_read_data_valid_cfi_flash_s1),
.cpu_instruction_master_requests_cfi_flash_s1 (cpu_instruction_master_requests_cfi_flash_s1),
.d1_tri_state_bridge_avalon_slave_end_xfer (d1_tri_state_bridge_avalon_slave_end_xfer),
.incoming_tri_state_bridge_data (incoming_tri_state_bridge_data),
.incoming_tri_state_bridge_data_with_Xs_converted_to_0 (incoming_tri_state_bridge_data_with_Xs_converted_to_0),
.registered_cpu_data_master_read_data_valid_cfi_flash_s1 (registered_cpu_data_master_read_data_valid_cfi_flash_s1),
.reset_n (clk_50_reset_n),
.select_n_to_the_cfi_flash (select_n_to_the_cfi_flash),
.tri_state_bridge_address (tri_state_bridge_address),
.tri_state_bridge_data (tri_state_bridge_data),
.tri_state_bridge_readn (tri_state_bridge_readn),
.write_n_to_the_cfi_flash (write_n_to_the_cfi_flash)
);
vga_0_avalon_slave_0_arbitrator the_vga_0_avalon_slave_0
(
.clk (pll_c0_out),
.d1_vga_0_avalon_slave_0_end_xfer (d1_vga_0_avalon_slave_0_end_xfer),
.kernel_clock_0_out_address_to_slave (kernel_clock_0_out_address_to_slave),
.kernel_clock_0_out_granted_vga_0_avalon_slave_0 (kernel_clock_0_out_granted_vga_0_avalon_slave_0),
.kernel_clock_0_out_nativeaddress (kernel_clock_0_out_nativeaddress),
.kernel_clock_0_out_qualified_request_vga_0_avalon_slave_0 (kernel_clock_0_out_qualified_request_vga_0_avalon_slave_0),
.kernel_clock_0_out_read (kernel_clock_0_out_read),
.kernel_clock_0_out_read_data_valid_vga_0_avalon_slave_0 (kernel_clock_0_out_read_data_valid_vga_0_avalon_slave_0),
.kernel_clock_0_out_requests_vga_0_avalon_slave_0 (kernel_clock_0_out_requests_vga_0_avalon_slave_0),
.kernel_clock_0_out_write (kernel_clock_0_out_write),
.kernel_clock_0_out_writedata (kernel_clock_0_out_writedata),
.reset_n (pll_c0_out_reset_n),
.vga_0_avalon_slave_0_address (vga_0_avalon_slave_0_address),
.vga_0_avalon_slave_0_chipselect (vga_0_avalon_slave_0_chipselect),
.vga_0_avalon_slave_0_read (vga_0_avalon_slave_0_read),
.vga_0_avalon_slave_0_readdata (vga_0_avalon_slave_0_readdata),
.vga_0_avalon_slave_0_readdata_from_sa (vga_0_avalon_slave_0_readdata_from_sa),
.vga_0_avalon_slave_0_reset_n (vga_0_avalon_slave_0_reset_n),
.vga_0_avalon_slave_0_wait_counter_eq_0 (vga_0_avalon_slave_0_wait_counter_eq_0),
.vga_0_avalon_slave_0_write (vga_0_avalon_slave_0_write),
.vga_0_avalon_slave_0_writedata (vga_0_avalon_slave_0_writedata)
);
vga_0 the_vga_0
(
.VGA_B (VGA_B_from_the_vga_0),
.VGA_BLANK (VGA_BLANK_from_the_vga_0),
.VGA_CLK (VGA_CLK_from_the_vga_0),
.VGA_G (VGA_G_from_the_vga_0),
.VGA_HS (VGA_HS_from_the_vga_0),
.VGA_R (VGA_R_from_the_vga_0),
.VGA_SYNC (VGA_SYNC_from_the_vga_0),
.VGA_VS (VGA_VS_from_the_vga_0),
.iADDR (vga_0_avalon_slave_0_address),
.iCLK (pll_c0_out),
.iCLK_25 (iCLK_25_to_the_vga_0),
.iCS (vga_0_avalon_slave_0_chipselect),
.iDATA (vga_0_avalon_slave_0_writedata),
.iRD (vga_0_avalon_slave_0_read),
.iRST_N (vga_0_avalon_slave_0_reset_n),
.iWR (vga_0_avalon_slave_0_write),
.oDATA (vga_0_avalon_slave_0_readdata)
);
//reset is asserted asynchronously and deasserted synchronously
kernel_reset_clk_50_domain_synch_module kernel_reset_clk_50_domain_synch
(
.clk (clk_50),
.data_in (1'b1),
.data_out (clk_50_reset_n),
.reset_n (reset_n_sources)
);
//reset sources mux, which is an e_mux
assign reset_n_sources = ~(~reset_n |
0 |
cpu_jtag_debug_module_resetrequest_from_sa |
cpu_jtag_debug_module_resetrequest_from_sa |
0);
//reset is asserted asynchronously and deasserted synchronously
kernel_reset_pll_c0_out_domain_synch_module kernel_reset_pll_c0_out_domain_synch
(
.clk (pll_c0_out),
.data_in (1'b1),
.data_out (pll_c0_out_reset_n),
.reset_n (reset_n_sources)
);
//kernel_clock_0_out_endofpacket of type endofpacket does not connect to anything so wire it to default (0)
assign kernel_clock_0_out_endofpacket = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cfi_flash_lane0_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
)
;
output [ 7: 0] q;
input [ 7: 0] data;
input [ 21: 0] rdaddress;
input rdclken;
input [ 21: 0] wraddress;
input wrclock;
input wren;
reg [ 7: 0] mem_array [4194303: 0];
wire [ 7: 0] q;
reg [ 21: 0] read_address;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(rdaddress)
begin
read_address = rdaddress;
end
// Data read is asynchronous.
assign q = mem_array[read_address];
initial
$readmemh("cfi_flash.dat", mem_array);
always @(posedge wrclock)
begin
// Write data
if (wren)
mem_array[wraddress] <= data;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// always @(rdaddress)
// begin
// read_address = rdaddress;
// end
//
//
// lpm_ram_dp lpm_ram_dp_component
// (
// .data (data),
// .q (q),
// .rdaddress (read_address),
// .rdclken (rdclken),
// .wraddress (wraddress),
// .wrclock (wrclock),
// .wren (wren)
// );
//
// defparam lpm_ram_dp_component.lpm_file = "cfi_flash.mif",
// lpm_ram_dp_component.lpm_hint = "USE_EAB=ON",
// lpm_ram_dp_component.lpm_indata = "REGISTERED",
// lpm_ram_dp_component.lpm_outdata = "UNREGISTERED",
// lpm_ram_dp_component.lpm_rdaddress_control = "UNREGISTERED",
// lpm_ram_dp_component.lpm_width = 8,
// lpm_ram_dp_component.lpm_widthad = 22,
// lpm_ram_dp_component.lpm_wraddress_control = "REGISTERED",
// lpm_ram_dp_component.suppress_memory_conversion_warnings = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cfi_flash (
// inputs:
address,
read_n,
select_n,
write_n,
// outputs:
data
)
;
inout [ 7: 0] data;
input [ 21: 0] address;
input read_n;
input select_n;
input write_n;
wire [ 7: 0] data;
wire [ 7: 0] data_0;
wire [ 7: 0] logic_vector_gasket;
wire [ 7: 0] q_0;
//s1, which is an e_ptf_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign logic_vector_gasket = data;
assign data_0 = logic_vector_gasket[7 : 0];
//cfi_flash_lane0, which is an e_ram
cfi_flash_lane0_module cfi_flash_lane0
(
.data (data_0),
.q (q_0),
.rdaddress (address),
.rdclken (1'b1),
.wraddress (address),
.wrclock (write_n),
.wren (~select_n)
);
assign data = (~select_n & ~read_n)? q_0: {8{1'bz}};
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
//synthesis translate_off
// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
// AND HERE WILL BE PRESERVED </ALTERA_NOTE>
// If user logic components use Altsync_Ram with convert_hex2ver.dll,
// set USE_convert_hex2ver in the user comments section above
// `ifdef USE_convert_hex2ver
// `else
// `define NO_PLI 1
// `endif
`include "c:/altera/12.0/quartus/eda/sim_lib/altera_mf.v"
`include "c:/altera/12.0/quartus/eda/sim_lib/220model.v"
`include "c:/altera/12.0/quartus/eda/sim_lib/sgate.v"
`include "pll.vo"
`include "ip/SRAM_16Bit_512K/hdl/SRAM_16Bit_512K.v"
`include "sram_16bit_512k_0.v"
`include "ip/Binary_VGA_Controller/hdl/Img_RAM.v"
`include "ip/Binary_VGA_Controller/hdl/VGA_Controller.v"
`include "ip/Binary_VGA_Controller/hdl/VGA_NIOS_CTRL.v"
`include "ip/Binary_VGA_Controller/hdl/VGA_OSD_RAM.v"
`include "vga_0.v"
`include "lcd_0.v"
`include "epcs_flash_controller.v"
`include "onchip_memory.v"
`include "cpu_test_bench.v"
`include "cpu_mult_cell.v"
`include "cpu_oci_test_bench.v"
`include "cpu_jtag_debug_module_tck.v"
`include "cpu_jtag_debug_module_sysclk.v"
`include "cpu_jtag_debug_module_wrapper.v"
`include "cpu.v"
`include "hardmodle.v"
`include "kernel_clock_0.v"
`include "timer.v"
`include "key.v"
`include "gpio.v"
`include "jtag_uart.v"
`timescale 1ns / 1ps
module test_bench
;
wire LCD_E_from_the_lcd_0;
wire LCD_RS_from_the_lcd_0;
wire LCD_RW_from_the_lcd_0;
wire [ 7: 0] LCD_data_to_and_from_the_lcd_0;
wire [ 17: 0] SRAM_ADDR_from_the_sram_16bit_512k_0;
wire SRAM_CE_N_from_the_sram_16bit_512k_0;
wire [ 15: 0] SRAM_DQ_to_and_from_the_sram_16bit_512k_0;
wire SRAM_LB_N_from_the_sram_16bit_512k_0;
wire SRAM_OE_N_from_the_sram_16bit_512k_0;
wire SRAM_UB_N_from_the_sram_16bit_512k_0;
wire SRAM_WE_N_from_the_sram_16bit_512k_0;
wire VGA_BLANK_from_the_vga_0;
wire [ 9: 0] VGA_B_from_the_vga_0;
wire VGA_CLK_from_the_vga_0;
wire [ 9: 0] VGA_G_from_the_vga_0;
wire VGA_HS_from_the_vga_0;
wire [ 9: 0] VGA_R_from_the_vga_0;
wire VGA_SYNC_from_the_vga_0;
wire VGA_VS_from_the_vga_0;
wire areset_to_the_pll;
wire clk;
reg clk_50;
wire epcs_flash_controller_epcs_control_port_dataavailable_from_sa;
wire epcs_flash_controller_epcs_control_port_endofpacket_from_sa;
wire epcs_flash_controller_epcs_control_port_readyfordata_from_sa;
wire iCLK_25_to_the_vga_0;
wire in_port_to_the_gpio;
wire [ 3: 0] in_port_to_the_hardmodle;
wire in_port_to_the_key;
wire jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
wire jtag_uart_avalon_jtag_slave_readyfordata_from_sa;
wire kernel_clock_0_in_endofpacket_from_sa;
wire kernel_clock_0_out_endofpacket;
wire locked_from_the_pll;
wire phasedone_from_the_pll;
wire pll_c0_out;
reg reset_n;
wire select_n_to_the_cfi_flash;
wire [ 21: 0] tri_state_bridge_address;
wire [ 7: 0] tri_state_bridge_data;
wire tri_state_bridge_readn;
wire write_n_to_the_cfi_flash;
// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
// add your signals and additional architecture here
// AND HERE WILL BE PRESERVED </ALTERA_NOTE>
//Set us up the Dut
kernel DUT
(
.LCD_E_from_the_lcd_0 (LCD_E_from_the_lcd_0),
.LCD_RS_from_the_lcd_0 (LCD_RS_from_the_lcd_0),
.LCD_RW_from_the_lcd_0 (LCD_RW_from_the_lcd_0),
.LCD_data_to_and_from_the_lcd_0 (LCD_data_to_and_from_the_lcd_0),
.SRAM_ADDR_from_the_sram_16bit_512k_0 (SRAM_ADDR_from_the_sram_16bit_512k_0),
.SRAM_CE_N_from_the_sram_16bit_512k_0 (SRAM_CE_N_from_the_sram_16bit_512k_0),
.SRAM_DQ_to_and_from_the_sram_16bit_512k_0 (SRAM_DQ_to_and_from_the_sram_16bit_512k_0),
.SRAM_LB_N_from_the_sram_16bit_512k_0 (SRAM_LB_N_from_the_sram_16bit_512k_0),
.SRAM_OE_N_from_the_sram_16bit_512k_0 (SRAM_OE_N_from_the_sram_16bit_512k_0),
.SRAM_UB_N_from_the_sram_16bit_512k_0 (SRAM_UB_N_from_the_sram_16bit_512k_0),
.SRAM_WE_N_from_the_sram_16bit_512k_0 (SRAM_WE_N_from_the_sram_16bit_512k_0),
.VGA_BLANK_from_the_vga_0 (VGA_BLANK_from_the_vga_0),
.VGA_B_from_the_vga_0 (VGA_B_from_the_vga_0),
.VGA_CLK_from_the_vga_0 (VGA_CLK_from_the_vga_0),
.VGA_G_from_the_vga_0 (VGA_G_from_the_vga_0),
.VGA_HS_from_the_vga_0 (VGA_HS_from_the_vga_0),
.VGA_R_from_the_vga_0 (VGA_R_from_the_vga_0),
.VGA_SYNC_from_the_vga_0 (VGA_SYNC_from_the_vga_0),
.VGA_VS_from_the_vga_0 (VGA_VS_from_the_vga_0),
.areset_to_the_pll (areset_to_the_pll),
.clk_50 (clk_50),
.iCLK_25_to_the_vga_0 (iCLK_25_to_the_vga_0),
.in_port_to_the_gpio (in_port_to_the_gpio),
.in_port_to_the_hardmodle (in_port_to_the_hardmodle),
.in_port_to_the_key (in_port_to_the_key),
.locked_from_the_pll (locked_from_the_pll),
.phasedone_from_the_pll (phasedone_from_the_pll),
.pll_c0_out (pll_c0_out),
.reset_n (reset_n),
.select_n_to_the_cfi_flash (select_n_to_the_cfi_flash),
.tri_state_bridge_address (tri_state_bridge_address),
.tri_state_bridge_data (tri_state_bridge_data),
.tri_state_bridge_readn (tri_state_bridge_readn),
.write_n_to_the_cfi_flash (write_n_to_the_cfi_flash)
);
cfi_flash the_cfi_flash
(
.address (tri_state_bridge_address),
.data (tri_state_bridge_data),
.read_n (tri_state_bridge_readn),
.select_n (select_n_to_the_cfi_flash),
.write_n (write_n_to_the_cfi_flash)
);
initial
clk_50 = 1'b0;
always
#10 clk_50 <= ~clk_50;
initial
begin
reset_n <= 0;
#200 reset_n <= 1;
end
endmodule
//synthesis translate_on |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXBP_SYMBOL_V
`define SKY130_FD_SC_LS__DLXBP_SYMBOL_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXBP_SYMBOL_V
|
(* Copyright (c) 2011-2012, 2015, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import FunctionalExtensionality List.
Require Import Cpdt.CpdtTactics Cpdt.DepList.
Set Implicit Arguments.
Set Asymmetric Patterns.
(* end hide *)
(** %\chapter{A Taste of Reasoning About Programming Language Syntax}% *)
(**
(** Reasoning about the syntax and semantics of programming languages is a popular application of proof assistants. Before proving the first theorem of this kind, it is necessary to choose a formal encoding of the informal notions of syntax, dealing with such issues as %\index{variable binding}%variable binding conventions. I believe the pragmatic questions in this domain are far from settled and remain as important open research problems. However, in this chapter, I will demonstrate two underused encoding approaches. Note that I am not recommending either approach as a silver bullet! Mileage will vary across concrete problems, and I expect there to be significant future advances in our knowledge of encoding techniques. For a broader introduction to programming language formalization, using more elementary techniques, see %\emph{%{{http://www.cis.upenn.edu/~bcpierce/sf/}Software Foundations}%}% by Pierce et al.
This chapter is also meant as a case study, bringing together what we have learned in the previous chapters. We will see a concrete example of the importance of representation choices; translating mathematics from paper to Coq is not a deterministic process, and different creative choices can have big impacts. We will also see dependent types and scripted proof automation in action, applied to solve a particular problem as well as possible, rather than to demonstrate new Coq concepts.
I apologize in advance to those readers not familiar with the theory of programming language semantics. I will make a few remarks intended to relate the material here with common ideas in semantics, but these remarks should be safe for others to skip.
We will define a small programming language and reason about its semantics, expressed as an interpreter into Coq terms, much as we have done in examples throughout the book. It will be helpful to build a slight extension of [crush] that tries to apply %\index{functional extensionality}%functional extensionality, an axiom we met in Chapter 12, which says that two functions are equal if they map equal inputs to equal outputs. We also use [f_equal] to simplify goals of a particular form that will come up with the term denotation function that we define shortly. *)
*)
(**
プログラミング言語のシンタックスやセマンティクスについて推論することは証明支援器のよく用いられる応用です。
Before proving the first theorem of this kind, it is necessary to choose a formal encoding of the informal notions of syntax, dealing with such issues as %\index{variable binding}%variable binding conventions.
この種のことの最初の定理を証明する前に、シンタックスの非形式的な概念の形式的な表現を選ぶ必要があります。
この分野での実践的な問いは解決にはほど遠く、研究として重要な未解決問題であると強く思います。
しかし、この章では、二つの十分活用されていない表現手法を実演します。
ただし、どちらの方法も問題解決への特効薬として勧めるわけではありません。
有用性は具体的な問題ごとに大きく異なり、著者は未来の重大な発展がこれらの表現技法の知識にあると期待します。
For a broader introduction to programming language formalization, using more elementary techniques, see %\emph{%{{http://www.cis.upenn.edu/~bcpierce/sf/}Software Foundations}%}% by Pierce et al.
より初等的なテクニックを使った、プログラミング言語の形式化へのより広範囲な入門としては、Pierceらの %\emph{%{{http://www.cis.upenn.edu/~bcpierce/sf/}Software Foundations}%}% を参照してください。
この章はこれまでの章で学んだことを一度に使ったケーススタディとしての意味もあります。
数学を紙からCoqに翻訳することは一つに決まったプロセスではなく、異なる創造的な選択が大きな影響を持たらすかもしれないといった、表現の選択の重要性についての具体例を見ます。
また、新しいCoqの概念を説明するよりもむしろ、依存型とスクリプトによる証明の自動化が可能な限りうまく具体的な問題を解くことに応用されることも見ていきます。
プログラミング言語のセマンティクスの理論に詳しくない読者には予め謝らなければいけません。
本章をセマンティクスのありふれた概念に結びつけるためのいくつかの注意を起きますが、それらの注意は他の読者は飛ばしても構いません。
この本を通した例で行ったように、小さいプログラミング言語を定義し、Coqの項へのインタプリタとして表されたセマンティクスについて推論します。
[crush]を%\index{関数外延性}%関数外延性を適用するように少し拡張すると便利です。
関数外延性は、第12章で見た公理で、もし二つの関数が同じ入力を同じ出力に写像するならばその二つの関数は等しいという主張です。
また、この後すぐに定義する項の表示関数と共に現れる特別な形のゴールを簡約するために[f_equal]も使います。
*)
Ltac ext := let x := fresh "x" in extensionality x.
Ltac pl := crush; repeat (match goal with
| [ |- (fun x => _) = (fun y => _) ] => ext
| [ |- _ _ _ ?E _ = _ _ _ ?E _ ] => f_equal
| [ |- ?E ::: _ = ?E ::: _ ] => f_equal
| [ |- hmap _ ?E = hmap _ ?E ] => f_equal
end; crush).
(** (** At this point in the book source, some auxiliary proofs also appear. *)
*)
(**
本書のこの時点では、補助的な証明も現れます。
*)
(* begin hide *)
Section hmap.
Variable A : Type.
Variables B1 B2 B3 : A -> Type.
Variable f1 : forall x, B1 x -> B2 x.
Variable f2 : forall x, B2 x -> B3 x.
Theorem hmap_hmap : forall ls (hl : hlist B1 ls), hmap f2 (hmap f1 hl) = hmap (fun i (x : B1 i) => f2 (f1 x)) hl.
induction hl; crush.
Qed.
End hmap.
Section Forall.
Variable A : Type.
Variable P : A -> Prop.
Theorem Forall_In : forall ls, Forall P ls -> forall x, In x ls -> P x.
induction 1; crush.
Qed.
Theorem Forall_In' : forall ls, (forall x, In x ls -> P x) -> Forall P ls.
induction ls; crush.
Qed.
Variable P' : A -> Prop.
Theorem Forall_weaken : forall ls, Forall P ls
-> (forall x, P x -> P' x)
-> Forall P' ls.
induction 1; crush.
Qed.
End Forall.
(* end hide *)
(**
(** Here is a definition of the type system we will use throughout the chapter. It is for simply typed lambda calculus with natural numbers as the base type. *)*)
(**
以下にこの章を通して扱う型システムを定義します。
これは基礎型として自然数を持った単順型付きラムダ計算です。
*)
Inductive type : Type :=
| Nat : type
| Func : type -> type -> type.
Fixpoint typeDenote (t : type) : Type :=
match t with
| Nat => nat
| Func t1 t2 => typeDenote t1 -> typeDenote t2
end.
(**
(** Now we have some choices as to how we represent the syntax of programs. The two sections of the chapter explore two such choices, demonstrating the effect the choice has on proof complexity. *)*)
(**
プログラムのシンタックスの表現の仕方は複数あります。
この章の二つの節では、証明の複雑性についてどのような効果があるかを実証しながら二つの選択肢を見ていきます。
*)
(** * Dependent de Bruijn Indices *)
(**
(** The first encoding is one we met first in Chapter 9, the _dependent de Bruijn index_ encoding. We represent program syntax terms in a type family parameterized by a list of types, representing the _typing context_, or information on which free variables are in scope and what their types are. Variables are represented in a way isomorphic to the natural numbers, where number 0 represents the first element in the context, number 1 the second element, and so on. Actually, instead of numbers, we use the [member] dependent type family from Chapter 9. *)*)
(**
最初の表現は第9章で最初に見た、_dependent de Bruijn index_表現です。
We represent program syntax terms in a type family parameterized by a list of types, representing the _typing context_, or information on which free variables are in scope and what their types are.
プログラムシンタックスの項は型のリストをパラメータに持つ型族で表現します。
自然数0は文脈の最初の要素を、自然数1は二番目の要素を表現するというように、変数は自然数と同型になるような方法で表現されます。
実際には、自然数の代わりに、第9章で扱った依存型族[member]を使います。
*)
Module FirstOrder.
(** (** Here is the definition of the [term] type, including variables, constants, addition, function abstraction and application, and let binding of local variables. *)*)
(**
変数、定数、加算、関数抽象・適用、局所変数のlet束縛を含む[term]型を定義します。
*)
Inductive term : list type -> type -> Type :=
| Var : forall G t, member t G -> term G t
| Const : forall G, nat -> term G Nat
| Plus : forall G, term G Nat -> term G Nat -> term G Nat
| Abs : forall G dom ran, term (dom :: G) ran -> term G (Func dom ran)
| App : forall G dom ran, term G (Func dom ran) -> term G dom -> term G ran
| Let : forall G t1 t2, term G t1 -> term (t1 :: G) t2 -> term G t2.
Arguments Const [G] _.
(** (** Here are two example term encodings, the first of addition packaged as a two-argument curried function, and the second of a sample application of addition to constants. *)*)
(**
Here are two example term encodings, the first of addition packaged as a two-argument curried function, and the second of a sample application of addition to constants.
項の表現の二つの例を挙げます。
一つ目はカリー化された二引数関数として作られた加算で、
*)
Example add : term nil (Func Nat (Func Nat Nat)) :=
Abs (Abs (Plus (Var (HNext HFirst)) (Var HFirst))).
Example three_the_hard_way : term nil Nat :=
App (App add (Const 1)) (Const 2).
(** Since dependent typing ensures that any term is well-formed in its context and has a particular type, it is easy to translate syntactic terms into Coq values. *)
Fixpoint termDenote G t (e : term G t) : hlist typeDenote G -> typeDenote t :=
match e with
| Var _ _ x => fun s => hget s x
| Const _ n => fun _ => n
| Plus _ e1 e2 => fun s => termDenote e1 s + termDenote e2 s
| Abs _ _ _ e1 => fun s => fun x => termDenote e1 (x ::: s)
| App _ _ _ e1 e2 => fun s => (termDenote e1 s) (termDenote e2 s)
| Let _ _ _ e1 e2 => fun s => termDenote e2 (termDenote e1 s ::: s)
end.
(** With this term representation, some program transformations are easy to implement and prove correct. Certainly we would be worried if this were not the the case for the _identity_ transformation, which takes a term apart and reassembles it. *)
Fixpoint ident G t (e : term G t) : term G t :=
match e with
| Var _ _ x => Var x
| Const _ n => Const n
| Plus _ e1 e2 => Plus (ident e1) (ident e2)
| Abs _ _ _ e1 => Abs (ident e1)
| App _ _ _ e1 e2 => App (ident e1) (ident e2)
| Let _ _ _ e1 e2 => Let (ident e1) (ident e2)
end.
Theorem identSound : forall G t (e : term G t) s,
termDenote (ident e) s = termDenote e s.
induction e; pl.
Qed.
(** A slightly more ambitious transformation belongs to the family of _constant folding_ optimizations we have used as examples in other chapters. *)
Fixpoint cfold G t (e : term G t) : term G t :=
match e with
| Plus G e1 e2 =>
let e1' := cfold e1 in
let e2' := cfold e2 in
let maybeOpt := match e1' return _ with
| Const _ n1 =>
match e2' return _ with
| Const _ n2 => Some (Const (n1 + n2))
| _ => None
end
| _ => None
end in
match maybeOpt with
| None => Plus e1' e2'
| Some e' => e'
end
| Abs _ _ _ e1 => Abs (cfold e1)
| App _ _ _ e1 e2 => App (cfold e1) (cfold e2)
| Let _ _ _ e1 e2 => Let (cfold e1) (cfold e2)
| e => e
end.
(** The correctness proof is more complex, but only slightly so. *)
Theorem cfoldSound : forall G t (e : term G t) s,
termDenote (cfold e) s = termDenote e s.
induction e; pl;
repeat (match goal with
| [ |- context[match ?E with Var _ _ _ => _ | _ => _ end] ] =>
dep_destruct E
end; pl).
Qed.
(** The transformations we have tried so far have been straightforward because they do not have interesting effects on the variable binding structure of terms. The dependent de Bruijn representation is called%\index{first-order syntax}% _first-order_ because it encodes variable identity explicitly; all such representations incur bookkeeping overheads in transformations that rearrange binding structure.
As an example of a tricky transformation, consider one that removes all uses of "[let x = e1 in e2]" by substituting [e1] for [x] in [e2]. We will implement the translation by pairing the "compile-time" typing environment with a "run-time" value environment or _substitution_, mapping each variable to a value to be substituted for it. Such a substitute term may be placed within a program in a position with a larger typing environment than applied at the point where the substitute term was chosen. To support such context transplantation, we need _lifting_, a standard de Bruijn indices operation. With dependent typing, lifting corresponds to weakening for typing judgments.
The fundamental goal of lifting is to add a new variable to a typing context, maintaining the validity of a term in the expanded context. To express the operation of adding a type to a context, we use a helper function [insertAt]. *)
Fixpoint insertAt (t : type) (G : list type) (n : nat) {struct n} : list type :=
match n with
| O => t :: G
| S n' => match G with
| nil => t :: G
| t' :: G' => t' :: insertAt t G' n'
end
end.
(** Another function lifts bound variable instances, which we represent with [member] values. *)
Fixpoint liftVar t G (x : member t G) t' n : member t (insertAt t' G n) :=
match x with
| HFirst G' => match n return member t (insertAt t' (t :: G') n) with
| O => HNext HFirst
| _ => HFirst
end
| HNext t'' G' x' => match n return member t (insertAt t' (t'' :: G') n) with
| O => HNext (HNext x')
| S n' => HNext (liftVar x' t' n')
end
end.
(** The final helper function for lifting allows us to insert a new variable anywhere in a typing context. *)
Fixpoint lift' G t' n t (e : term G t) : term (insertAt t' G n) t :=
match e with
| Var _ _ x => Var (liftVar x t' n)
| Const _ n => Const n
| Plus _ e1 e2 => Plus (lift' t' n e1) (lift' t' n e2)
| Abs _ _ _ e1 => Abs (lift' t' (S n) e1)
| App _ _ _ e1 e2 => App (lift' t' n e1) (lift' t' n e2)
| Let _ _ _ e1 e2 => Let (lift' t' n e1) (lift' t' (S n) e2)
end.
(** In the [Let] removal transformation, we only need to apply lifting to add a new variable at the _beginning_ of a typing context, so we package lifting into this final, simplified form. *)
Definition lift G t' t (e : term G t) : term (t' :: G) t :=
lift' t' O e.
(** Finally, we can implement [Let] removal. The argument of type [hlist (term G') G] represents a substitution mapping each variable from context [G] into a term that is valid in context [G']. Note how the [Abs] case (1) extends via lifting the substitution [s] to hold in the broader context of the abstraction body [e1] and (2) maps the new first variable to itself. It is only the [Let] case that maps a variable to any substitute beside itself. *)
Fixpoint unlet G t (e : term G t) G' : hlist (term G') G -> term G' t :=
match e with
| Var _ _ x => fun s => hget s x
| Const _ n => fun _ => Const n
| Plus _ e1 e2 => fun s => Plus (unlet e1 s) (unlet e2 s)
| Abs _ _ _ e1 => fun s => Abs (unlet e1 (Var HFirst ::: hmap (lift _) s))
| App _ _ _ e1 e2 => fun s => App (unlet e1 s) (unlet e2 s)
| Let _ t1 _ e1 e2 => fun s => unlet e2 (unlet e1 s ::: s)
end.
(** We have finished defining the transformation, but the parade of helper functions is not over. To prove correctness, we will use one more helper function and a few lemmas. First, we need an operation to insert a new value into a substitution at a particular position. *)
Fixpoint insertAtS (t : type) (x : typeDenote t) (G : list type) (n : nat) {struct n}
: hlist typeDenote G -> hlist typeDenote (insertAt t G n) :=
match n with
| O => fun s => x ::: s
| S n' => match G return hlist typeDenote G
-> hlist typeDenote (insertAt t G (S n')) with
| nil => fun s => x ::: s
| t' :: G' => fun s => hhd s ::: insertAtS t x n' (htl s)
end
end.
Arguments insertAtS [t] x [G] n _.
(** Next we prove that [liftVar] is correct. That is, a lifted variable retains its value with respect to a substitution when we perform an analogue to lifting by inserting a new mapping into the substitution. *)
Lemma liftVarSound : forall t' (x : typeDenote t') t G (m : member t G) s n,
hget s m = hget (insertAtS x n s) (liftVar m t' n).
induction m; destruct n; dep_destruct s; pl.
Qed.
Hint Resolve liftVarSound.
(** An analogous lemma establishes correctness of [lift']. *)
Lemma lift'Sound : forall G t' (x : typeDenote t') t (e : term G t) n s,
termDenote e s = termDenote (lift' t' n e) (insertAtS x n s).
induction e; pl;
repeat match goal with
| [ IH : forall n s, _ = termDenote (lift' _ n ?E) _
|- context[lift' _ (S ?N) ?E] ] => specialize (IH (S N))
end; pl.
Qed.
(** Correctness of [lift] itself is an easy corollary. *)
Lemma liftSound : forall G t' (x : typeDenote t') t (e : term G t) s,
termDenote (lift t' e) (x ::: s) = termDenote e s.
unfold lift; intros; rewrite (lift'Sound _ x e O); trivial.
Qed.
Hint Rewrite hget_hmap hmap_hmap liftSound.
(** Finally, we can prove correctness of [unletSound] for terms in arbitrary typing environments. *)
Lemma unletSound' : forall G t (e : term G t) G' (s : hlist (term G') G) s1,
termDenote (unlet e s) s1
= termDenote e (hmap (fun t' (e' : term G' t') => termDenote e' s1) s).
induction e; pl.
Qed.
(** The lemma statement is a mouthful, with all its details of typing contexts and substitutions. It is usually prudent to state a final theorem in as simple a way as possible, to help your readers believe that you have proved what they expect. We follow that advice here for the simple case of terms with empty typing contexts. *)
Theorem unletSound : forall t (e : term nil t),
termDenote (unlet e HNil) HNil = termDenote e HNil.
intros; apply unletSound'.
Qed.
End FirstOrder.
(** The [Let] removal optimization is a good case study of a simple transformation that may turn out to be much more work than expected, based on representation choices. In the second part of this chapter, we consider an alternate choice that produces a more pleasant experience. *)
(** * Parametric Higher-Order Abstract Syntax *)
(** In contrast to first-order encodings,%\index{higher-order syntax}% _higher-order_ encodings avoid explicit modeling of variable identity. Instead, the binding constructs of an%\index{object language}% _object language_ (the language being formalized) can be represented using the binding constructs of the%\index{meta language}% _meta language_ (the language in which the formalization is done). The best known higher-order encoding is called%\index{higher-order abstract syntax}% _higher-order abstract syntax_ (HOAS) %\cite{HOAS}%, and we can start by attempting to apply it directly in Coq. *)
Module HigherOrder.
(** With HOAS, each object language binding construct is represented with a _function_ of the meta language. Here is what we get if we apply that idea within an inductive definition of term syntax. *)
(** %\vspace{-.15in}%[[
Inductive term : type -> Type :=
| Const : nat -> term Nat
| Plus : term Nat -> term Nat -> term Nat
| Abs : forall dom ran, (term dom -> term ran) -> term (Func dom ran)
| App : forall dom ran, term (Func dom ran) -> term dom -> term ran
| Let : forall t1 t2, term t1 -> (term t1 -> term t2) -> term t2.
]]
However, Coq rejects this definition for failing to meet the %\index{strict positivity requirement}%strict positivity restriction. For instance, the constructor [Abs] takes an argument that is a function over the same type family [term] that we are defining. Inductive definitions of this kind can be used to write non-terminating Gallina programs, which breaks the consistency of Coq's logic.
An alternate higher-order encoding is%\index{parametric higher-order abstract syntax}\index{PHOAS|see{parametric higher-order abstract syntax}}% _parametric HOAS_, as introduced by Washburn and Weirich%~\cite{BGB}% for Haskell and tweaked by me%~\cite{PhoasICFP08}% for use in Coq. Here the idea is to parameterize the syntax type by a type family standing for a _representation of variables_. *)
Section var.
Variable var : type -> Type.
Inductive term : type -> Type :=
| Var : forall t, var t -> term t
| Const : nat -> term Nat
| Plus : term Nat -> term Nat -> term Nat
| Abs : forall dom ran, (var dom -> term ran) -> term (Func dom ran)
| App : forall dom ran, term (Func dom ran) -> term dom -> term ran
| Let : forall t1 t2, term t1 -> (var t1 -> term t2) -> term t2.
End var.
Arguments Var [var t] _.
Arguments Const [var] _.
Arguments Abs [var dom ran] _.
(** Coq accepts this definition because our embedded functions now merely take _variables_ as arguments, instead of arbitrary terms. One might wonder whether there is an easy loophole to exploit here, instantiating the parameter [var] as [term] itself. However, to do that, we would need to choose a variable representation for this nested mention of [term], and so on through an infinite descent into [term] arguments.
We write the final type of a closed term using polymorphic quantification over all possible choices of [var] type family. *)
Definition Term t := forall var, term var t.
(** Here are the new representations of the example terms from the last section. Note how each is written as a function over a [var] choice, such that the specific choice has no impact on the _structure_ of the term. *)
Example add : Term (Func Nat (Func Nat Nat)) := fun var =>
Abs (fun x => Abs (fun y => Plus (Var x) (Var y))).
Example three_the_hard_way : Term Nat := fun var =>
App (App (add var) (Const 1)) (Const 2).
(** The argument [var] does not even appear in the function body for [add]. How can that be? By giving our terms expressive types, we allow Coq to infer many arguments for us. In fact, we do not even need to name the [var] argument! *)
Example add' : Term (Func Nat (Func Nat Nat)) := fun _ =>
Abs (fun x => Abs (fun y => Plus (Var x) (Var y))).
Example three_the_hard_way' : Term Nat := fun _ =>
App (App (add' _) (Const 1)) (Const 2).
(** Even though the [var] formal parameters appear as underscores, they _are_ mentioned in the function bodies that type inference calculates. *)
(** ** Functional Programming with PHOAS *)
(** It may not be at all obvious that the PHOAS representation admits the crucial computable operations. The key to effective deconstruction of PHOAS terms is one principle: treat the [var] parameter as an unconstrained choice of _which data should be annotated on each variable_. We will begin with a simple example, that of counting how many variable nodes appear in a PHOAS term. This operation requires no data annotated on variables, so we simply annotate variables with [unit] values. Note that, when we go under binders in the cases for [Abs] and [Let], we must provide the data value to annotate on the new variable we pass beneath. For our current choice of [unit] data, we always pass [tt]. *)
Fixpoint countVars t (e : term (fun _ => unit) t) : nat :=
match e with
| Var _ _ => 1
| Const _ => 0
| Plus e1 e2 => countVars e1 + countVars e2
| Abs _ _ e1 => countVars (e1 tt)
| App _ _ e1 e2 => countVars e1 + countVars e2
| Let _ _ e1 e2 => countVars e1 + countVars (e2 tt)
end.
(** The above definition may seem a bit peculiar. What gave us the right to represent variables as [unit] values? Recall that our final representation of closed terms is as polymorphic functions. We merely specialize a closed term to exactly the right variable representation for the transformation we wish to perform. *)
Definition CountVars t (E : Term t) := countVars (E (fun _ => unit)).
(** It is easy to test that [CountVars] operates properly. *)
Eval compute in CountVars three_the_hard_way.
(** %\vspace{-.15in}%[[
= 2
]]
*)
(** In fact, PHOAS can be used anywhere that first-order representations can. We will not go into all the details here, but the intuition is that it is possible to interconvert between PHOAS and any reasonable first-order representation. Here is a suggestive example, translating PHOAS terms into strings giving a first-order rendering. To implement this translation, the key insight is to tag variables with strings, giving their names. The function takes as an additional input a string giving the name to be assigned to the next variable introduced. We evolve this name by adding a prime to its end. To avoid getting bogged down in orthogonal details, we render all constants as the string ["N"]. *)
Require Import String.
Open Scope string_scope.
Fixpoint pretty t (e : term (fun _ => string) t) (x : string) : string :=
match e with
| Var _ s => s
| Const _ => "N"
| Plus e1 e2 => "(" ++ pretty e1 x ++ " + " ++ pretty e2 x ++ ")"
| Abs _ _ e1 => "(fun " ++ x ++ " => " ++ pretty (e1 x) (x ++ "'") ++ ")"
| App _ _ e1 e2 => "(" ++ pretty e1 x ++ " " ++ pretty e2 x ++ ")"
| Let _ _ e1 e2 => "(let " ++ x ++ " = " ++ pretty e1 x ++ " in "
++ pretty (e2 x) (x ++ "'") ++ ")"
end.
Definition Pretty t (E : Term t) := pretty (E (fun _ => string)) "x".
Eval compute in Pretty three_the_hard_way.
(** %\vspace{-.15in}%[[
= "(((fun x => (fun x' => (x + x'))) N) N)"
]]
*)
(** However, it is not necessary to convert to first-order form to support many common operations on terms. For instance, we can implement substitution of terms for variables. The key insight here is to _tag variables with terms_, so that, on encountering a variable, we can simply replace it by the term in its tag. We will call this function initially on a term with exactly one free variable, tagged with the appropriate substitute. During recursion, new variables are added, but they are only tagged with their own term equivalents. Note that this function [squash] is parameterized over a specific [var] choice. *)
Fixpoint squash var t (e : term (term var) t) : term var t :=
match e with
| Var _ e1 => e1
| Const n => Const n
| Plus e1 e2 => Plus (squash e1) (squash e2)
| Abs _ _ e1 => Abs (fun x => squash (e1 (Var x)))
| App _ _ e1 e2 => App (squash e1) (squash e2)
| Let _ _ e1 e2 => Let (squash e1) (fun x => squash (e2 (Var x)))
end.
(** To define the final substitution function over terms with single free variables, we define [Term1], an analogue to [Term] that we defined before for closed terms. *)
Definition Term1 (t1 t2 : type) := forall var, var t1 -> term var t2.
(** Substitution is defined by (1) instantiating a [Term1] to tag variables with terms and (2) applying the result to a specific term to be substituted. Note how the parameter [var] of [squash] is instantiated: the body of [Subst] is itself a polymorphic quantification over [var], standing for a variable tag choice in the output term; and we use that input to compute a tag choice for the input term. *)
Definition Subst (t1 t2 : type) (E : Term1 t1 t2) (E' : Term t1) : Term t2 :=
fun var => squash (E (term var) (E' var)).
Eval compute in Subst (fun _ x => Plus (Var x) (Const 3)) three_the_hard_way.
(** %\vspace{-.15in}%[[
= fun var : type -> Type =>
Plus
(App
(App
(Abs
(fun x : var Nat =>
Abs (fun y : var Nat => Plus (Var x) (Var y))))
(Const 1)) (Const 2)) (Const 3)
]]
One further development, which may seem surprising at first, is that we can also implement a usual term denotation function, when we _tag variables with their denotations_. *)
Fixpoint termDenote t (e : term typeDenote t) : typeDenote t :=
match e with
| Var _ v => v
| Const n => n
| Plus e1 e2 => termDenote e1 + termDenote e2
| Abs _ _ e1 => fun x => termDenote (e1 x)
| App _ _ e1 e2 => (termDenote e1) (termDenote e2)
| Let _ _ e1 e2 => termDenote (e2 (termDenote e1))
end.
Definition TermDenote t (E : Term t) : typeDenote t :=
termDenote (E typeDenote).
Eval compute in TermDenote three_the_hard_way.
(** %\vspace{-.15in}%[[
= 3
]]
To summarize, the PHOAS representation has all the expressive power of more standard first-order encodings, and a variety of translations are actually much more pleasant to implement than usual, thanks to the novel ability to tag variables with data. *)
(** ** Verifying Program Transformations *)
(** Let us now revisit the three example program transformations from the last section. Each is easy to implement with PHOAS, and the last is substantially easier than with first-order representations.
First, we have the recursive identity function, following the same pattern as in the previous subsection, with a helper function, polymorphic in a tag choice; and a final function that instantiates the choice appropriately. *)
Fixpoint ident var t (e : term var t) : term var t :=
match e with
| Var _ x => Var x
| Const n => Const n
| Plus e1 e2 => Plus (ident e1) (ident e2)
| Abs _ _ e1 => Abs (fun x => ident (e1 x))
| App _ _ e1 e2 => App (ident e1) (ident e2)
| Let _ _ e1 e2 => Let (ident e1) (fun x => ident (e2 x))
end.
Definition Ident t (E : Term t) : Term t := fun var =>
ident (E var).
(** Proving correctness is both easier and harder than in the last section, easier because we do not need to manipulate substitutions, and harder because we do the induction in an extra lemma about [ident], to establish the correctness theorem for [Ident]. *)
Lemma identSound : forall t (e : term typeDenote t),
termDenote (ident e) = termDenote e.
induction e; pl.
Qed.
Theorem IdentSound : forall t (E : Term t),
TermDenote (Ident E) = TermDenote E.
intros; apply identSound.
Qed.
(** The translation of the constant-folding function and its proof work more or less the same way. *)
Fixpoint cfold var t (e : term var t) : term var t :=
match e with
| Plus e1 e2 =>
let e1' := cfold e1 in
let e2' := cfold e2 in
match e1', e2' with
| Const n1, Const n2 => Const (n1 + n2)
| _, _ => Plus e1' e2'
end
| Abs _ _ e1 => Abs (fun x => cfold (e1 x))
| App _ _ e1 e2 => App (cfold e1) (cfold e2)
| Let _ _ e1 e2 => Let (cfold e1) (fun x => cfold (e2 x))
| e => e
end.
Definition Cfold t (E : Term t) : Term t := fun var =>
cfold (E var).
Lemma cfoldSound : forall t (e : term typeDenote t),
termDenote (cfold e) = termDenote e.
induction e; pl;
repeat (match goal with
| [ |- context[match ?E with Var _ _ => _ | _ => _ end] ] =>
dep_destruct E
end; pl).
Qed.
Theorem CfoldSound : forall t (E : Term t),
TermDenote (Cfold E) = TermDenote E.
intros; apply cfoldSound.
Qed.
(** Things get more interesting in the [Let]-removal optimization. Our recursive helper function adapts the key idea from our earlier definitions of [squash] and [Subst]: tag variables with terms. We have a straightforward generalization of [squash], where only the [Let] case has changed, to tag the new variable with the term it is bound to, rather than just tagging the variable with itself as a term. *)
Fixpoint unlet var t (e : term (term var) t) : term var t :=
match e with
| Var _ e1 => e1
| Const n => Const n
| Plus e1 e2 => Plus (unlet e1) (unlet e2)
| Abs _ _ e1 => Abs (fun x => unlet (e1 (Var x)))
| App _ _ e1 e2 => App (unlet e1) (unlet e2)
| Let _ _ e1 e2 => unlet (e2 (unlet e1))
end.
Definition Unlet t (E : Term t) : Term t := fun var =>
unlet (E (term var)).
(** We can test [Unlet] first on an uninteresting example, [three_the_hard_way], which does not use [Let]. *)
Eval compute in Unlet three_the_hard_way.
(** %\vspace{-.15in}%[[
= fun var : type -> Type =>
App
(App
(Abs
(fun x : var Nat =>
Abs (fun x0 : var Nat => Plus (Var x) (Var x0))))
(Const 1)) (Const 2)
]]
Next, we try a more interesting example, with some extra [Let]s introduced in [three_the_hard_way]. *)
Definition three_a_harder_way : Term Nat := fun _ =>
Let (Const 1) (fun x => Let (Const 2) (fun y => App (App (add _) (Var x)) (Var y))).
Eval compute in Unlet three_a_harder_way.
(** %\vspace{-.15in}%[[
= fun var : type -> Type =>
App
(App
(Abs
(fun x : var Nat =>
Abs (fun x0 : var Nat => Plus (Var x) (Var x0))))
(Const 1)) (Const 2)
]]
The output is the same as in the previous test, confirming that [Unlet] operates properly here.
Now we need to state a correctness theorem for [Unlet], based on an inductively proved lemma about [unlet]. It is not at all obvious how to arrive at a proper induction principle for the lemma. The problem is that we want to relate two instantiations of the same [Term], in a way where we know they share the same structure. Note that, while [Unlet] is defined to consider all possible [var] choices in the output term, the correctness proof conveniently only depends on the case of [var := typeDenote]. Thus, one parallel instantiation will set [var := typeDenote], to take the denotation of the original term. The other parallel instantiation will set [var := term typeDenote], to perform the [unlet] transformation in the original term.
Here is a relation formalizing the idea that two terms are structurally the same, differing only by replacing the variable data of one with another isomorphic set of variable data in some possibly different type family. *)
Section wf.
Variables var1 var2 : type -> Type.
(** To formalize the tag isomorphism, we will use lists of values with the following record type. Each entry has an object language type and an appropriate tag for that type, in each of the two tag families [var1] and [var2]. *)
Record varEntry := {
Ty : type;
First : var1 Ty;
Second : var2 Ty
}.
(** Here is the inductive relation definition. An instance [wf G e1 e2] asserts that terms [e1] and [e2] are equivalent up to the variable tag isomorphism [G]. Note how the [Var] rule looks up an entry in [G], and the [Abs] and [Let] rules include recursive [wf] invocations inside the scopes of quantifiers to introduce parallel tag values to be considered as isomorphic. *)
Inductive wf : list varEntry -> forall t, term var1 t -> term var2 t -> Prop :=
| WfVar : forall G t x x', In {| Ty := t; First := x; Second := x' |} G
-> wf G (Var x) (Var x')
| WfConst : forall G n, wf G (Const n) (Const n)
| WfPlus : forall G e1 e2 e1' e2', wf G e1 e1'
-> wf G e2 e2'
-> wf G (Plus e1 e2) (Plus e1' e2')
| WfAbs : forall G dom ran (e1 : _ dom -> term _ ran) e1',
(forall x1 x2, wf ({| First := x1; Second := x2 |} :: G) (e1 x1) (e1' x2))
-> wf G (Abs e1) (Abs e1')
| WfApp : forall G dom ran (e1 : term _ (Func dom ran)) (e2 : term _ dom) e1' e2',
wf G e1 e1'
-> wf G e2 e2'
-> wf G (App e1 e2) (App e1' e2')
| WfLet : forall G t1 t2 e1 e1' (e2 : _ t1 -> term _ t2) e2', wf G e1 e1'
-> (forall x1 x2, wf ({| First := x1; Second := x2 |} :: G) (e2 x1) (e2' x2))
-> wf G (Let e1 e2) (Let e1' e2').
End wf.
(** We can state a well-formedness condition for closed terms: for any two choices of tag type families, the parallel instantiations belong to the [wf] relation, starting from an empty variable isomorphism. *)
Definition Wf t (E : Term t) := forall var1 var2, wf nil (E var1) (E var2).
(** After digesting the syntactic details of [Wf], it is probably not hard to see that reasonable term encodings will satisfy it. For example: *)
Theorem three_the_hard_way_Wf : Wf three_the_hard_way.
red; intros; repeat match goal with
| [ |- wf _ _ _ ] => constructor; intros
end; intuition.
Qed.
(** Now we are ready to give a nice simple proof of correctness for [unlet]. First, we add one hint to apply a small variant of a standard library theorem connecting [Forall], a higher-order predicate asserting that every element of a list satisfies some property; and [In], the list membership predicate. *)
Hint Extern 1 => match goal with
| [ H1 : Forall _ _, H2 : In _ _ |- _ ] => apply (Forall_In H1 _ H2)
end.
(** The rest of the proof is about as automated as we could hope for. *)
Lemma unletSound : forall G t (e1 : term _ t) e2,
wf G e1 e2
-> Forall (fun ve => termDenote (First ve) = Second ve) G
-> termDenote (unlet e1) = termDenote e2.
induction 1; pl.
Qed.
Theorem UnletSound : forall t (E : Term t), Wf E
-> TermDenote (Unlet E) = TermDenote E.
intros; eapply unletSound; eauto.
Qed.
(** With this example, it is not obvious that the PHOAS encoding is more tractable than dependent de Bruijn. Where the de Bruijn version had [lift] and its helper functions, here we have [Wf] and its auxiliary definitions. In practice, [Wf] is defined once per object language, while such operations as [lift] often need to operate differently for different examples, forcing new implementations for new transformations.
The reader may also have come up with another objection: via Curry-Howard, [wf] proofs may be thought of as first-order encodings of term syntax! For instance, the [In] hypothesis of rule [WfVar] is equivalent to a [member] value. There is some merit to this objection. However, as the proofs above show, we are able to reason about transformations using first-order representation only for their inputs, not their outputs. Furthermore, explicit numbering of variables remains absent from the proofs.
Have we really avoided first-order reasoning about the output terms of translations? The answer depends on some subtle issues, which deserve a subsection of their own. *)
(** ** Establishing Term Well-Formedness *)
(** Can there be values of type [Term t] that are not well-formed according to [Wf]? We expect that Gallina satisfies key%\index{parametricity}% _parametricity_ %\cite{parametricity}% properties, which indicate how polymorphic types may only be inhabited by specific values. We omit details of parametricity theorems here, but [forall t (E : Term t), Wf E] follows the flavor of such theorems. One option would be to assert that fact as an axiom, "proving" that any output of any of our translations is well-formed. We could even prove the soundness of the theorem on paper meta-theoretically, say by considering some particular model of CIC.
To be more cautious, we could prove [Wf] for every term that interests us, threading such proofs through all transformations. Here is an example exercise of that kind, for [Unlet].
First, we prove that [wf] is _monotone_, in that a given instance continues to hold as we add new variable pairs to the variable isomorphism. *)
Hint Constructors wf.
Hint Extern 1 (In _ _) => simpl; tauto.
Hint Extern 1 (Forall _ _) => eapply Forall_weaken; [ eassumption | simpl ].
Lemma wf_monotone : forall var1 var2 G t (e1 : term var1 t) (e2 : term var2 t),
wf G e1 e2
-> forall G', Forall (fun x => In x G') G
-> wf G' e1 e2.
induction 1; pl; auto 6.
Qed.
Hint Resolve wf_monotone Forall_In'.
(** Now we are ready to prove that [unlet] preserves any [wf] instance. The key invariant has to do with the parallel execution of [unlet] on two different [var] instantiations of a particular term. Since [unlet] uses [term] as the type of variable data, our variable isomorphism context [G] contains pairs of terms, which, conveniently enough, allows us to state the invariant that any pair of terms in the context is also related by [wf]. *)
Hint Extern 1 (wf _ _ _) => progress simpl.
Lemma unletWf : forall var1 var2 G t (e1 : term (term var1) t) (e2 : term (term var2) t),
wf G e1 e2
-> forall G', Forall (fun ve => wf G' (First ve) (Second ve)) G
-> wf G' (unlet e1) (unlet e2).
induction 1; pl; eauto 9.
Qed.
(** Repackaging [unletWf] into a theorem about [Wf] and [Unlet] is straightforward. *)
Theorem UnletWf : forall t (E : Term t), Wf E
-> Wf (Unlet E).
red; intros; apply unletWf with nil; auto.
Qed.
(** This example demonstrates how we may need to use reasoning reminiscent of that associated with first-order representations, though the bookkeeping details are generally easier to manage, and bookkeeping theorems may generally be proved separately from the independently interesting theorems about program transformations. *)
(** ** A Few More Remarks *)
(** Higher-order encodings derive their strength from reuse of the meta language's binding constructs. As a result, we can write encoded terms so that they look very similar to their informal counterparts, without variable numbering schemes like for de Bruijn indices. The example encodings above have demonstrated this fact, but modulo the clunkiness of explicit use of the constructors of [term]. After defining a few new Coq syntax notations, we can work with terms in an even more standard form. *)
Infix "-->" := Func (right associativity, at level 52).
Notation "^" := Var.
Notation "#" := Const.
Infix "@" := App (left associativity, at level 50).
Infix "@+" := Plus (left associativity, at level 50).
Notation "\ x : t , e" := (Abs (dom := t) (fun x => e))
(no associativity, at level 51, x at level 0).
Notation "[ e ]" := (fun _ => e).
Example Add : Term (Nat --> Nat --> Nat) :=
[\x : Nat, \y : Nat, ^x @+ ^y].
Example Three_the_hard_way : Term Nat :=
[Add _ @ #1 @ #2].
Eval compute in TermDenote Three_the_hard_way.
(** %\vspace{-.15in}%[[
= 3
]]
*)
End HigherOrder.
(** The PHOAS approach shines here because we are working with an object language that has an easy embedding into Coq. That is, there is a straightforward recursive function translating object terms into terms of Gallina. All Gallina programs terminate, so clearly we cannot hope to find such embeddings for Turing-complete languages; and non-Turing-complete languages may still require much more involved translations. I have some work%~\cite{CompilerPOPL10}% on modeling semantics of Turing-complete languages with PHOAS, but my impression is that there are many more advances left to be made in this field, possibly with completely new term representations that we have not yet been clever enough to think up. *)
|
// ----------------------------------------------------------------------
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// modification, are permitted provided that the following conditions are
// met:
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// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: riffa_wrapper_de5.v
// Version: 1.00a
// Verilog Standard: Verilog-2001
// Description: Wrapper file for all riffa logic for Altera DE5 boards
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "riffa.vh"
`include "altera.vh"
`include "ultrascale.vh"
`include "functions.vh"
`timescale 1ps / 1ps
module riffa_wrapper_de5
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Bit-Width from Quartus IP Generator
parameter C_PCI_DATA_WIDTH = 128,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5
)
(
// Interface: Altera RX
input [C_PCI_DATA_WIDTH-1:0] RX_ST_DATA,
input [0:0] RX_ST_EOP, // TODO: Should be 2 bits wide in 256-bit interface
input [0:0] RX_ST_SOP, // TODO: Should be 2 bits wide in 256-bit interface
input [0:0] RX_ST_VALID,
output RX_ST_READY,
input [0:0] RX_ST_EMPTY,
// Interface: Altera TX
output [C_PCI_DATA_WIDTH-1:0] TX_ST_DATA,
output [0:0] TX_ST_VALID,
input TX_ST_READY,
output [0:0] TX_ST_EOP,
output [0:0] TX_ST_SOP,
output [0:0] TX_ST_EMPTY,
// Interface: Altera Config
input [`SIG_CFG_CTL_W-1:0] TL_CFG_CTL,
input [`SIG_CFG_ADD_W-1:0] TL_CFG_ADD,
input [`SIG_CFG_STS_W-1:0] TL_CFG_STS,
// Interface: Altera Flow Control
input [`SIG_KO_CPLH_W-1:0] KO_CPL_SPC_HEADER,
input [`SIG_KO_CPLD_W-1:0] KO_CPL_SPC_DATA,
// Interface: Altera Interrupt
input APP_MSI_ACK,
output APP_MSI_REQ,
// Interface: Altera CLK/RESET
input PLD_CLK,
input RESET_STATUS,
// RIFFA Interface Signals
output RST_OUT,
input [C_NUM_CHNL-1:0] CHNL_RX_CLK, // Channel read clock
output [C_NUM_CHNL-1:0] CHNL_RX, // Channel read receive signal
input [C_NUM_CHNL-1:0] CHNL_RX_ACK, // Channel read received signal
output [C_NUM_CHNL-1:0] CHNL_RX_LAST, // Channel last read
output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA, // Channel read data
output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID, // Channel read data valid
input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN, // Channel read data has been recieved
input [C_NUM_CHNL-1:0] CHNL_TX_CLK, // Channel write clock
input [C_NUM_CHNL-1:0] CHNL_TX, // Channel write receive signal
output [C_NUM_CHNL-1:0] CHNL_TX_ACK, // Channel write acknowledgement signal
input [C_NUM_CHNL-1:0] CHNL_TX_LAST, // Channel last write
input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_TX_OFF, // Channel write offset
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA, // Channel write data
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN // Channel write data has been recieved
);
localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver
localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2;
localparam C_VENDOR = "ALTERA";
localparam C_ALTERA_TX_READY_LATENCY = 2;
localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
localparam C_PIPELINE_OUTPUT = 1;
localparam C_PIPELINE_INPUT = 1;
wire clk;
wire rst_in;
// Interface: RXC Engine
wire [C_PCI_DATA_WIDTH-1:0] rxc_data;
wire rxc_data_valid;
wire rxc_data_start_flag;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_word_enable;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset;
wire [`SIG_FBE_W-1:0] rxc_meta_fdwbe;
wire rxc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset;
wire [`SIG_LBE_W-1:0] rxc_meta_ldwbe;
wire [`SIG_TAG_W-1:0] rxc_meta_tag;
wire [`SIG_LOWADDR_W-1:0] rxc_meta_addr;
wire [`SIG_TYPE_W-1:0] rxc_meta_type;
wire [`SIG_LEN_W-1:0] rxc_meta_length;
wire [`SIG_BYTECNT_W-1:0] rxc_meta_bytes_remaining;
wire [`SIG_CPLID_W-1:0] rxc_meta_completer_id;
wire rxc_meta_ep;
// Interface: RXR Engine
wire [C_PCI_DATA_WIDTH-1:0] rxr_data;
wire rxr_data_valid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_word_enable;
wire rxr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset;
wire [`SIG_FBE_W-1:0] rxr_meta_fdwbe;
wire rxr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset;
wire [`SIG_LBE_W-1:0] rxr_meta_ldwbe;
wire [`SIG_TC_W-1:0] rxr_meta_tc;
wire [`SIG_ATTR_W-1:0] rxr_meta_attr;
wire [`SIG_TAG_W-1:0] rxr_meta_tag;
wire [`SIG_TYPE_W-1:0] rxr_meta_type;
wire [`SIG_ADDR_W-1:0] rxr_meta_addr;
wire [`SIG_BARDECODE_W-1:0] rxr_meta_bar_decoded;
wire [`SIG_REQID_W-1:0] rxr_meta_requester_id;
wire [`SIG_LEN_W-1:0] rxr_meta_length;
wire rxr_meta_ep;
// interface: TXC Engine
wire txc_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txc_data;
wire txc_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset;
wire txc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset;
wire txc_data_ready;
wire txc_meta_valid;
wire [`SIG_FBE_W-1:0] txc_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txc_meta_ldwbe;
wire [`SIG_LOWADDR_W-1:0] txc_meta_addr;
wire [`SIG_TYPE_W-1:0] txc_meta_type;
wire [`SIG_LEN_W-1:0] txc_meta_length;
wire [`SIG_BYTECNT_W-1:0] txc_meta_byte_count;
wire [`SIG_TAG_W-1:0] txc_meta_tag;
wire [`SIG_REQID_W-1:0] txc_meta_requester_id;
wire [`SIG_TC_W-1:0] txc_meta_tc;
wire [`SIG_ATTR_W-1:0] txc_meta_attr;
wire txc_meta_ep;
wire txc_meta_ready;
wire txc_sent;
// Interface: TXR Engine
wire txr_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txr_data;
wire txr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset;
wire txr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset;
wire txr_data_ready;
wire txr_meta_valid;
wire [`SIG_FBE_W-1:0] txr_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txr_meta_ldwbe;
wire [`SIG_ADDR_W-1:0] txr_meta_addr;
wire [`SIG_LEN_W-1:0] txr_meta_length;
wire [`SIG_TAG_W-1:0] txr_meta_tag;
wire [`SIG_TC_W-1:0] txr_meta_tc;
wire [`SIG_ATTR_W-1:0] txr_meta_attr;
wire [`SIG_TYPE_W-1:0] txr_meta_type;
wire txr_meta_ep;
wire txr_meta_ready;
wire txr_sent;
// Classic Interface Wires
wire wRxTlpReady;
wire [C_PCI_DATA_WIDTH-1:0] wRxTlp;
wire wRxTlpEndFlag;
wire [`SIG_OFFSET_W-1:0] wRxTlpEndOffset;
wire wRxTlpStartFlag;
wire [`SIG_OFFSET_W-1:0] wRxTlpStartOffset;
wire wRxTlpValid;
wire [`SIG_BARDECODE_W-1:0] wRxTlpBarDecode;
wire wTxTlpReady;
wire [C_PCI_DATA_WIDTH-1:0] wTxTlp;
wire wTxTlpEndFlag;
wire [`SIG_OFFSET_W-1:0] wTxTlpEndOffset;
wire wTxTlpStartFlag;
wire [`SIG_OFFSET_W-1:0] wTxTlpStartOffset;
wire wTxTlpValid;
// Unconnected Wires (Used in ultrascale interface)
// Interface: RQ (TXC)
wire s_axis_rq_tlast_nc;
wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata_nc;
wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser_nc;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep_nc;
wire s_axis_rq_tready_nc = 0;
wire s_axis_rq_tvalid_nc;
// Interface: RC (RXC)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata_nc = 0;
wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser_nc = 0;
wire m_axis_rc_tlast_nc = 0;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep_nc = 0;
wire m_axis_rc_tvalid_nc = 0;
wire m_axis_rc_tready_nc;
// Interface: CQ (RXR)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata_nc = 0;
wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser_nc = 0;
wire m_axis_cq_tlast_nc = 0;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep_nc = 0;
wire m_axis_cq_tvalid_nc = 0;
wire m_axis_cq_tready_nc = 0;
// Interface: CC (TXC)
wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata_nc;
wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser_nc;
wire s_axis_cc_tlast_nc;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep_nc;
wire s_axis_cc_tvalid_nc;
wire s_axis_cc_tready_nc = 0;
// Interface: Configuration
wire config_bus_master_enable;
wire [`SIG_CPLID_W-1:0] config_completer_id;
wire config_cpl_boundary_sel;
wire config_interrupt_msienable;
wire [`SIG_LINKRATE_W-1:0] config_link_rate;
wire [`SIG_LINKWIDTH_W-1:0] config_link_width;
wire [`SIG_MAXPAYLOAD_W-1:0] config_max_payload_size;
wire [`SIG_MAXREAD_W-1:0] config_max_read_request_size;
wire [`SIG_FC_CPLD_W-1:0] config_max_cpl_data;
wire [`SIG_FC_CPLH_W-1:0] config_max_cpl_hdr;
wire intr_msi_request;
wire intr_msi_rdy;
genvar chnl;
assign clk = PLD_CLK;
assign rst_in = RESET_STATUS;
translation_altera
#(
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH))
trans
(
// Outputs
.RX_TLP (wRxTlp[C_PCI_DATA_WIDTH-1:0]),
.RX_TLP_VALID (wRxTlpValid),
.RX_TLP_START_FLAG (wRxTlpStartFlag),
.RX_TLP_START_OFFSET (wRxTlpStartOffset[`SIG_OFFSET_W-1:0]),
.RX_TLP_END_FLAG (wRxTlpEndFlag),
.RX_TLP_END_OFFSET (wRxTlpEndOffset[`SIG_OFFSET_W-1:0]),
.RX_TLP_BAR_DECODE (wRxTlpBarDecode[`SIG_BARDECODE_W-1:0]),
.TX_TLP_READY (wTxTlpReady),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
// Inputs
.CLK (clk),
.RST_IN (rst_in),
.RX_TLP_READY (wRxTlpReady),
.TX_TLP (wTxTlp[C_PCI_DATA_WIDTH-1:0]),
.TX_TLP_VALID (wTxTlpValid),
.TX_TLP_START_FLAG (wTxTlpStartFlag),
.TX_TLP_START_OFFSET (wTxTlpStartOffset[`SIG_OFFSET_W-1:0]),
.TX_TLP_END_FLAG (wTxTlpEndFlag),
.TX_TLP_END_OFFSET (wTxTlpEndOffset[`SIG_OFFSET_W-1:0]),
.INTR_MSI_REQUEST (intr_msi_request),
/*AUTOINST*/
// Outputs
.RX_ST_READY (RX_ST_READY),
.TX_ST_DATA (TX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
.TX_ST_VALID (TX_ST_VALID[0:0]),
.TX_ST_EOP (TX_ST_EOP[0:0]),
.TX_ST_SOP (TX_ST_SOP[0:0]),
.TX_ST_EMPTY (TX_ST_EMPTY[0:0]),
.APP_MSI_REQ (APP_MSI_REQ),
// Inputs
.RX_ST_DATA (RX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
.RX_ST_EOP (RX_ST_EOP[0:0]),
.RX_ST_SOP (RX_ST_SOP[0:0]),
.RX_ST_VALID (RX_ST_VALID[0:0]),
.RX_ST_EMPTY (RX_ST_EMPTY[0:0]),
.TX_ST_READY (TX_ST_READY),
.TL_CFG_CTL (TL_CFG_CTL[`SIG_CFG_CTL_W-1:0]),
.TL_CFG_ADD (TL_CFG_ADD[`SIG_CFG_ADD_W-1:0]),
.TL_CFG_STS (TL_CFG_STS[`SIG_CFG_STS_W-1:0]),
.KO_CPL_SPC_HEADER (KO_CPL_SPC_HEADER[`SIG_FC_CPLH_W-1:0]),
.KO_CPL_SPC_DATA (KO_CPL_SPC_DATA[`SIG_FC_CPLD_W-1:0]),
.APP_MSI_ACK (APP_MSI_ACK));
engine_layer
#(// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_BYTES/4),
.C_VENDOR (C_VENDOR))
engine_layer_inst
(// Outputs
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
// Unconnected Outputs
.TX_TLP (wTxTlp),
.TX_TLP_VALID (wTxTlpValid),
.TX_TLP_START_FLAG (wTxTlpStartFlag),
.TX_TLP_START_OFFSET (wTxTlpStartOffset),
.TX_TLP_END_FLAG (wTxTlpEndFlag),
.TX_TLP_END_OFFSET (wTxTlpEndOffset),
.RX_TLP_READY (wRxTlpReady),
// Inputs
.CLK (clk),
.RST_IN (rst_in),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
// Unconnected Inputs
.RX_TLP (wRxTlp),
.RX_TLP_VALID (wRxTlpValid),
.RX_TLP_START_FLAG (wRxTlpStartFlag),
.RX_TLP_START_OFFSET (wRxTlpStartOffset),
.RX_TLP_END_FLAG (wRxTlpEndFlag),
.RX_TLP_END_OFFSET (wRxTlpEndOffset),
.RX_TLP_BAR_DECODE (wRxTlpBarDecode),
.TX_TLP_READY (wTxTlpReady),
// Outputs
.M_AXIS_CQ_TREADY (m_axis_cq_tready_nc),
.M_AXIS_RC_TREADY (m_axis_rc_tready_nc),
.S_AXIS_CC_TVALID (s_axis_cc_tvalid_nc),
.S_AXIS_CC_TLAST (s_axis_cc_tlast_nc),
.S_AXIS_CC_TDATA (s_axis_cc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (s_axis_cc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (s_axis_cc_tuser_nc[`SIG_CC_TUSER_W-1:0]),
.S_AXIS_RQ_TVALID (s_axis_rq_tvalid_nc),
.S_AXIS_RQ_TLAST (s_axis_rq_tlast_nc),
.S_AXIS_RQ_TDATA (s_axis_rq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (s_axis_rq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (s_axis_rq_tuser_nc[`SIG_RQ_TUSER_W-1:0]),
// Inputs
.M_AXIS_CQ_TVALID (m_axis_cq_tvalid_nc),
.M_AXIS_CQ_TLAST (m_axis_cq_tlast_nc),
.M_AXIS_CQ_TDATA (m_axis_cq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (m_axis_cq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (m_axis_cq_tuser_nc[`SIG_CQ_TUSER_W-1:0]),
.M_AXIS_RC_TVALID (m_axis_rc_tvalid_nc),
.M_AXIS_RC_TLAST (m_axis_rc_tlast_nc),
.M_AXIS_RC_TDATA (m_axis_rc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (m_axis_rc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (m_axis_rc_tuser_nc[`SIG_RC_TUSER_W-1:0]),
.S_AXIS_CC_TREADY (s_axis_cc_tready_nc),
.S_AXIS_RQ_TREADY (s_axis_rq_tready_nc)
/*AUTOINST*/);
riffa
#(.C_TAG_WIDTH (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES (C_MAX_READ_REQ_BYTES),
.C_VENDOR (C_VENDOR),
.C_FPGA_NAME (C_FPGA_NAME))
riffa_inst
(// Outputs
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
.INTR_MSI_REQUEST (intr_msi_request),
// Inputs
.CLK (clk),
.RST_IN (rst_in),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
/*AUTOINST*/
// Outputs
.RST_OUT (RST_OUT),
.CHNL_RX (CHNL_RX[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (CHNL_RX_LAST[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_RX_OFF (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_RX_DATA (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (CHNL_TX_ACK[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]),
// Inputs
.CHNL_RX_CLK (CHNL_RX_CLK[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (CHNL_RX_ACK[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (CHNL_TX_CLK[C_NUM_CHNL-1:0]),
.CHNL_TX (CHNL_TX[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (CHNL_TX_LAST[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_TX_OFF (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_TX_DATA (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0]));
endmodule
// Local Variables:
// verilog-library-directories:("../../engine/" "../../riffa/" "../../trans")
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A32OI_FUNCTIONAL_V
`define SKY130_FD_SC_HS__A32OI_FUNCTIONAL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a32oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
// Local signals
wire B1 nand0_out ;
wire B1 nand1_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A32OI_FUNCTIONAL_V |
//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the N64 RGB/YPbPr DAC project.
//
// Copyright (C) 2015-2021 by Peter Bartmann <[email protected]>
//
// N64 RGB/YPbPr DAC is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//////////////////////////////////////////////////////////////////////////////////
//
// Company: Circuit-Board.de
// Engineer: borti4938
//
// Module Name: gamma_table
// Project Name: N64 Advanced RGB/YPbPr DAC Mod
// Target Devices: universial
// Tool versions: Altera Quartus Prime
// Description:
//
// Features: ip independent implementation of gamma rom
//
// This file is auto generated by script/gamma2rom.m
//
//////////////////////////////////////////////////////////////////////////////////
module gamma_table(
VCLK,
nRST,
gamma_val,
vdata_in,
nbypass,
vdata_out
);
`include "vh/n64adv_vparams.vh"
input VCLK;
input nRST;
input [ 2:0] gamma_val;
input [color_width_i-1:0] vdata_in;
input nbypass;
output reg [color_width_i-1:0] vdata_out = {color_width_i{1'b0}};
reg [color_width_i+2:0] addr_r = {(color_width_i+3){1'b0}};
reg nbypass_r = 1'b0;
always @(posedge VCLK or negedge nRST)
if (!nRST) begin
vdata_out <= {(color_width_i){1'b0}};
addr_r <= {(color_width_i+3){1'b0}};
nbypass_r <= 1'b0;
end else begin
addr_r <= {gamma_val,vdata_in};
nbypass_r <= nbypass;
case (addr_r)
0000: vdata_out <= 000;
0001: vdata_out <= 003;
0002: vdata_out <= 006;
0003: vdata_out <= 008;
0004: vdata_out <= 009;
0005: vdata_out <= 011;
0006: vdata_out <= 013;
0007: vdata_out <= 014;
0008: vdata_out <= 016;
0009: vdata_out <= 017;
0010: vdata_out <= 019;
0011: vdata_out <= 020;
0012: vdata_out <= 022;
0013: vdata_out <= 023;
0014: vdata_out <= 024;
0015: vdata_out <= 026;
0016: vdata_out <= 027;
0017: vdata_out <= 028;
0018: vdata_out <= 029;
0019: vdata_out <= 031;
0020: vdata_out <= 032;
0021: vdata_out <= 033;
0022: vdata_out <= 034;
0023: vdata_out <= 035;
0024: vdata_out <= 036;
0025: vdata_out <= 038;
0026: vdata_out <= 039;
0027: vdata_out <= 040;
0028: vdata_out <= 041;
0029: vdata_out <= 042;
0030: vdata_out <= 043;
0031: vdata_out <= 044;
0032: vdata_out <= 045;
0033: vdata_out <= 046;
0034: vdata_out <= 047;
0035: vdata_out <= 048;
0036: vdata_out <= 049;
0037: vdata_out <= 050;
0038: vdata_out <= 051;
0039: vdata_out <= 052;
0040: vdata_out <= 053;
0041: vdata_out <= 054;
0042: vdata_out <= 055;
0043: vdata_out <= 056;
0044: vdata_out <= 057;
0045: vdata_out <= 058;
0046: vdata_out <= 059;
0047: vdata_out <= 060;
0048: vdata_out <= 061;
0049: vdata_out <= 062;
0050: vdata_out <= 063;
0051: vdata_out <= 064;
0052: vdata_out <= 065;
0053: vdata_out <= 066;
0054: vdata_out <= 067;
0055: vdata_out <= 068;
0056: vdata_out <= 069;
0057: vdata_out <= 070;
0058: vdata_out <= 071;
0059: vdata_out <= 071;
0060: vdata_out <= 072;
0061: vdata_out <= 073;
0062: vdata_out <= 074;
0063: vdata_out <= 075;
0064: vdata_out <= 076;
0065: vdata_out <= 077;
0066: vdata_out <= 078;
0067: vdata_out <= 079;
0068: vdata_out <= 079;
0069: vdata_out <= 080;
0070: vdata_out <= 081;
0071: vdata_out <= 082;
0072: vdata_out <= 083;
0073: vdata_out <= 084;
0074: vdata_out <= 085;
0075: vdata_out <= 086;
0076: vdata_out <= 086;
0077: vdata_out <= 087;
0078: vdata_out <= 088;
0079: vdata_out <= 089;
0080: vdata_out <= 090;
0081: vdata_out <= 091;
0082: vdata_out <= 091;
0083: vdata_out <= 092;
0084: vdata_out <= 093;
0085: vdata_out <= 094;
0086: vdata_out <= 095;
0087: vdata_out <= 096;
0088: vdata_out <= 096;
0089: vdata_out <= 097;
0090: vdata_out <= 098;
0091: vdata_out <= 099;
0092: vdata_out <= 100;
0093: vdata_out <= 101;
0094: vdata_out <= 101;
0095: vdata_out <= 102;
0096: vdata_out <= 103;
0097: vdata_out <= 104;
0098: vdata_out <= 105;
0099: vdata_out <= 105;
0100: vdata_out <= 106;
0101: vdata_out <= 107;
0102: vdata_out <= 108;
0103: vdata_out <= 109;
0104: vdata_out <= 109;
0105: vdata_out <= 110;
0106: vdata_out <= 111;
0107: vdata_out <= 112;
0108: vdata_out <= 112;
0109: vdata_out <= 113;
0110: vdata_out <= 114;
0111: vdata_out <= 115;
0112: vdata_out <= 116;
0113: vdata_out <= 116;
0114: vdata_out <= 117;
0115: vdata_out <= 118;
0116: vdata_out <= 119;
0117: vdata_out <= 119;
0118: vdata_out <= 120;
0119: vdata_out <= 121;
0120: vdata_out <= 122;
0121: vdata_out <= 122;
0122: vdata_out <= 123;
0123: vdata_out <= 124;
0124: vdata_out <= 125;
0125: vdata_out <= 125;
0126: vdata_out <= 126;
0127: vdata_out <= 127;
0128: vdata_out <= 000;
0129: vdata_out <= 003;
0130: vdata_out <= 005;
0131: vdata_out <= 006;
0132: vdata_out <= 008;
0133: vdata_out <= 010;
0134: vdata_out <= 011;
0135: vdata_out <= 012;
0136: vdata_out <= 014;
0137: vdata_out <= 015;
0138: vdata_out <= 017;
0139: vdata_out <= 018;
0140: vdata_out <= 019;
0141: vdata_out <= 021;
0142: vdata_out <= 022;
0143: vdata_out <= 023;
0144: vdata_out <= 024;
0145: vdata_out <= 025;
0146: vdata_out <= 027;
0147: vdata_out <= 028;
0148: vdata_out <= 029;
0149: vdata_out <= 030;
0150: vdata_out <= 031;
0151: vdata_out <= 032;
0152: vdata_out <= 033;
0153: vdata_out <= 035;
0154: vdata_out <= 036;
0155: vdata_out <= 037;
0156: vdata_out <= 038;
0157: vdata_out <= 039;
0158: vdata_out <= 040;
0159: vdata_out <= 041;
0160: vdata_out <= 042;
0161: vdata_out <= 043;
0162: vdata_out <= 044;
0163: vdata_out <= 045;
0164: vdata_out <= 046;
0165: vdata_out <= 047;
0166: vdata_out <= 048;
0167: vdata_out <= 049;
0168: vdata_out <= 050;
0169: vdata_out <= 051;
0170: vdata_out <= 052;
0171: vdata_out <= 053;
0172: vdata_out <= 054;
0173: vdata_out <= 055;
0174: vdata_out <= 056;
0175: vdata_out <= 057;
0176: vdata_out <= 058;
0177: vdata_out <= 059;
0178: vdata_out <= 060;
0179: vdata_out <= 061;
0180: vdata_out <= 062;
0181: vdata_out <= 063;
0182: vdata_out <= 064;
0183: vdata_out <= 065;
0184: vdata_out <= 066;
0185: vdata_out <= 067;
0186: vdata_out <= 068;
0187: vdata_out <= 069;
0188: vdata_out <= 070;
0189: vdata_out <= 071;
0190: vdata_out <= 072;
0191: vdata_out <= 072;
0192: vdata_out <= 073;
0193: vdata_out <= 074;
0194: vdata_out <= 075;
0195: vdata_out <= 076;
0196: vdata_out <= 077;
0197: vdata_out <= 078;
0198: vdata_out <= 079;
0199: vdata_out <= 080;
0200: vdata_out <= 081;
0201: vdata_out <= 082;
0202: vdata_out <= 082;
0203: vdata_out <= 083;
0204: vdata_out <= 084;
0205: vdata_out <= 085;
0206: vdata_out <= 086;
0207: vdata_out <= 087;
0208: vdata_out <= 088;
0209: vdata_out <= 089;
0210: vdata_out <= 089;
0211: vdata_out <= 090;
0212: vdata_out <= 091;
0213: vdata_out <= 092;
0214: vdata_out <= 093;
0215: vdata_out <= 094;
0216: vdata_out <= 095;
0217: vdata_out <= 096;
0218: vdata_out <= 096;
0219: vdata_out <= 097;
0220: vdata_out <= 098;
0221: vdata_out <= 099;
0222: vdata_out <= 100;
0223: vdata_out <= 101;
0224: vdata_out <= 102;
0225: vdata_out <= 102;
0226: vdata_out <= 103;
0227: vdata_out <= 104;
0228: vdata_out <= 105;
0229: vdata_out <= 106;
0230: vdata_out <= 107;
0231: vdata_out <= 107;
0232: vdata_out <= 108;
0233: vdata_out <= 109;
0234: vdata_out <= 110;
0235: vdata_out <= 111;
0236: vdata_out <= 112;
0237: vdata_out <= 112;
0238: vdata_out <= 113;
0239: vdata_out <= 114;
0240: vdata_out <= 115;
0241: vdata_out <= 116;
0242: vdata_out <= 116;
0243: vdata_out <= 117;
0244: vdata_out <= 118;
0245: vdata_out <= 119;
0246: vdata_out <= 120;
0247: vdata_out <= 121;
0248: vdata_out <= 121;
0249: vdata_out <= 122;
0250: vdata_out <= 123;
0251: vdata_out <= 124;
0252: vdata_out <= 125;
0253: vdata_out <= 125;
0254: vdata_out <= 126;
0255: vdata_out <= 127;
0256: vdata_out <= 000;
0257: vdata_out <= 002;
0258: vdata_out <= 004;
0259: vdata_out <= 005;
0260: vdata_out <= 007;
0261: vdata_out <= 008;
0262: vdata_out <= 009;
0263: vdata_out <= 011;
0264: vdata_out <= 012;
0265: vdata_out <= 013;
0266: vdata_out <= 015;
0267: vdata_out <= 016;
0268: vdata_out <= 017;
0269: vdata_out <= 018;
0270: vdata_out <= 019;
0271: vdata_out <= 021;
0272: vdata_out <= 022;
0273: vdata_out <= 023;
0274: vdata_out <= 024;
0275: vdata_out <= 025;
0276: vdata_out <= 026;
0277: vdata_out <= 028;
0278: vdata_out <= 029;
0279: vdata_out <= 030;
0280: vdata_out <= 031;
0281: vdata_out <= 032;
0282: vdata_out <= 033;
0283: vdata_out <= 034;
0284: vdata_out <= 035;
0285: vdata_out <= 036;
0286: vdata_out <= 037;
0287: vdata_out <= 038;
0288: vdata_out <= 039;
0289: vdata_out <= 040;
0290: vdata_out <= 041;
0291: vdata_out <= 042;
0292: vdata_out <= 043;
0293: vdata_out <= 045;
0294: vdata_out <= 046;
0295: vdata_out <= 047;
0296: vdata_out <= 048;
0297: vdata_out <= 049;
0298: vdata_out <= 050;
0299: vdata_out <= 051;
0300: vdata_out <= 052;
0301: vdata_out <= 053;
0302: vdata_out <= 054;
0303: vdata_out <= 055;
0304: vdata_out <= 056;
0305: vdata_out <= 057;
0306: vdata_out <= 058;
0307: vdata_out <= 058;
0308: vdata_out <= 059;
0309: vdata_out <= 060;
0310: vdata_out <= 061;
0311: vdata_out <= 062;
0312: vdata_out <= 063;
0313: vdata_out <= 064;
0314: vdata_out <= 065;
0315: vdata_out <= 066;
0316: vdata_out <= 067;
0317: vdata_out <= 068;
0318: vdata_out <= 069;
0319: vdata_out <= 070;
0320: vdata_out <= 071;
0321: vdata_out <= 072;
0322: vdata_out <= 073;
0323: vdata_out <= 074;
0324: vdata_out <= 075;
0325: vdata_out <= 076;
0326: vdata_out <= 077;
0327: vdata_out <= 077;
0328: vdata_out <= 078;
0329: vdata_out <= 079;
0330: vdata_out <= 080;
0331: vdata_out <= 081;
0332: vdata_out <= 082;
0333: vdata_out <= 083;
0334: vdata_out <= 084;
0335: vdata_out <= 085;
0336: vdata_out <= 086;
0337: vdata_out <= 087;
0338: vdata_out <= 088;
0339: vdata_out <= 088;
0340: vdata_out <= 089;
0341: vdata_out <= 090;
0342: vdata_out <= 091;
0343: vdata_out <= 092;
0344: vdata_out <= 093;
0345: vdata_out <= 094;
0346: vdata_out <= 095;
0347: vdata_out <= 096;
0348: vdata_out <= 097;
0349: vdata_out <= 097;
0350: vdata_out <= 098;
0351: vdata_out <= 099;
0352: vdata_out <= 100;
0353: vdata_out <= 101;
0354: vdata_out <= 102;
0355: vdata_out <= 103;
0356: vdata_out <= 104;
0357: vdata_out <= 105;
0358: vdata_out <= 105;
0359: vdata_out <= 106;
0360: vdata_out <= 107;
0361: vdata_out <= 108;
0362: vdata_out <= 109;
0363: vdata_out <= 110;
0364: vdata_out <= 111;
0365: vdata_out <= 112;
0366: vdata_out <= 112;
0367: vdata_out <= 113;
0368: vdata_out <= 114;
0369: vdata_out <= 115;
0370: vdata_out <= 116;
0371: vdata_out <= 117;
0372: vdata_out <= 118;
0373: vdata_out <= 118;
0374: vdata_out <= 119;
0375: vdata_out <= 120;
0376: vdata_out <= 121;
0377: vdata_out <= 122;
0378: vdata_out <= 123;
0379: vdata_out <= 124;
0380: vdata_out <= 124;
0381: vdata_out <= 125;
0382: vdata_out <= 126;
0383: vdata_out <= 127;
0384: vdata_out <= 000;
0385: vdata_out <= 002;
0386: vdata_out <= 003;
0387: vdata_out <= 004;
0388: vdata_out <= 006;
0389: vdata_out <= 007;
0390: vdata_out <= 008;
0391: vdata_out <= 009;
0392: vdata_out <= 011;
0393: vdata_out <= 012;
0394: vdata_out <= 013;
0395: vdata_out <= 014;
0396: vdata_out <= 015;
0397: vdata_out <= 016;
0398: vdata_out <= 017;
0399: vdata_out <= 019;
0400: vdata_out <= 020;
0401: vdata_out <= 021;
0402: vdata_out <= 022;
0403: vdata_out <= 023;
0404: vdata_out <= 024;
0405: vdata_out <= 025;
0406: vdata_out <= 026;
0407: vdata_out <= 027;
0408: vdata_out <= 028;
0409: vdata_out <= 029;
0410: vdata_out <= 030;
0411: vdata_out <= 032;
0412: vdata_out <= 033;
0413: vdata_out <= 034;
0414: vdata_out <= 035;
0415: vdata_out <= 036;
0416: vdata_out <= 037;
0417: vdata_out <= 038;
0418: vdata_out <= 039;
0419: vdata_out <= 040;
0420: vdata_out <= 041;
0421: vdata_out <= 042;
0422: vdata_out <= 043;
0423: vdata_out <= 044;
0424: vdata_out <= 045;
0425: vdata_out <= 046;
0426: vdata_out <= 047;
0427: vdata_out <= 048;
0428: vdata_out <= 049;
0429: vdata_out <= 050;
0430: vdata_out <= 051;
0431: vdata_out <= 052;
0432: vdata_out <= 053;
0433: vdata_out <= 054;
0434: vdata_out <= 055;
0435: vdata_out <= 056;
0436: vdata_out <= 057;
0437: vdata_out <= 058;
0438: vdata_out <= 059;
0439: vdata_out <= 060;
0440: vdata_out <= 061;
0441: vdata_out <= 062;
0442: vdata_out <= 063;
0443: vdata_out <= 064;
0444: vdata_out <= 065;
0445: vdata_out <= 066;
0446: vdata_out <= 067;
0447: vdata_out <= 068;
0448: vdata_out <= 069;
0449: vdata_out <= 070;
0450: vdata_out <= 070;
0451: vdata_out <= 071;
0452: vdata_out <= 072;
0453: vdata_out <= 073;
0454: vdata_out <= 074;
0455: vdata_out <= 075;
0456: vdata_out <= 076;
0457: vdata_out <= 077;
0458: vdata_out <= 078;
0459: vdata_out <= 079;
0460: vdata_out <= 080;
0461: vdata_out <= 081;
0462: vdata_out <= 082;
0463: vdata_out <= 083;
0464: vdata_out <= 084;
0465: vdata_out <= 085;
0466: vdata_out <= 086;
0467: vdata_out <= 087;
0468: vdata_out <= 088;
0469: vdata_out <= 088;
0470: vdata_out <= 089;
0471: vdata_out <= 090;
0472: vdata_out <= 091;
0473: vdata_out <= 092;
0474: vdata_out <= 093;
0475: vdata_out <= 094;
0476: vdata_out <= 095;
0477: vdata_out <= 096;
0478: vdata_out <= 097;
0479: vdata_out <= 098;
0480: vdata_out <= 099;
0481: vdata_out <= 100;
0482: vdata_out <= 101;
0483: vdata_out <= 101;
0484: vdata_out <= 102;
0485: vdata_out <= 103;
0486: vdata_out <= 104;
0487: vdata_out <= 105;
0488: vdata_out <= 106;
0489: vdata_out <= 107;
0490: vdata_out <= 108;
0491: vdata_out <= 109;
0492: vdata_out <= 110;
0493: vdata_out <= 111;
0494: vdata_out <= 112;
0495: vdata_out <= 113;
0496: vdata_out <= 113;
0497: vdata_out <= 114;
0498: vdata_out <= 115;
0499: vdata_out <= 116;
0500: vdata_out <= 117;
0501: vdata_out <= 118;
0502: vdata_out <= 119;
0503: vdata_out <= 120;
0504: vdata_out <= 121;
0505: vdata_out <= 122;
0506: vdata_out <= 122;
0507: vdata_out <= 123;
0508: vdata_out <= 124;
0509: vdata_out <= 125;
0510: vdata_out <= 126;
0511: vdata_out <= 127;
0512: vdata_out <= 000;
0513: vdata_out <= 001;
0514: vdata_out <= 002;
0515: vdata_out <= 004;
0516: vdata_out <= 005;
0517: vdata_out <= 006;
0518: vdata_out <= 007;
0519: vdata_out <= 008;
0520: vdata_out <= 009;
0521: vdata_out <= 010;
0522: vdata_out <= 011;
0523: vdata_out <= 012;
0524: vdata_out <= 014;
0525: vdata_out <= 015;
0526: vdata_out <= 016;
0527: vdata_out <= 017;
0528: vdata_out <= 018;
0529: vdata_out <= 019;
0530: vdata_out <= 020;
0531: vdata_out <= 021;
0532: vdata_out <= 022;
0533: vdata_out <= 023;
0534: vdata_out <= 024;
0535: vdata_out <= 025;
0536: vdata_out <= 026;
0537: vdata_out <= 027;
0538: vdata_out <= 028;
0539: vdata_out <= 029;
0540: vdata_out <= 030;
0541: vdata_out <= 031;
0542: vdata_out <= 032;
0543: vdata_out <= 033;
0544: vdata_out <= 034;
0545: vdata_out <= 035;
0546: vdata_out <= 036;
0547: vdata_out <= 037;
0548: vdata_out <= 038;
0549: vdata_out <= 039;
0550: vdata_out <= 040;
0551: vdata_out <= 041;
0552: vdata_out <= 042;
0553: vdata_out <= 043;
0554: vdata_out <= 044;
0555: vdata_out <= 045;
0556: vdata_out <= 046;
0557: vdata_out <= 047;
0558: vdata_out <= 048;
0559: vdata_out <= 049;
0560: vdata_out <= 050;
0561: vdata_out <= 051;
0562: vdata_out <= 052;
0563: vdata_out <= 053;
0564: vdata_out <= 054;
0565: vdata_out <= 055;
0566: vdata_out <= 056;
0567: vdata_out <= 057;
0568: vdata_out <= 058;
0569: vdata_out <= 059;
0570: vdata_out <= 060;
0571: vdata_out <= 061;
0572: vdata_out <= 062;
0573: vdata_out <= 063;
0574: vdata_out <= 064;
0575: vdata_out <= 065;
0576: vdata_out <= 066;
0577: vdata_out <= 067;
0578: vdata_out <= 068;
0579: vdata_out <= 069;
0580: vdata_out <= 070;
0581: vdata_out <= 071;
0582: vdata_out <= 072;
0583: vdata_out <= 073;
0584: vdata_out <= 074;
0585: vdata_out <= 075;
0586: vdata_out <= 076;
0587: vdata_out <= 077;
0588: vdata_out <= 078;
0589: vdata_out <= 079;
0590: vdata_out <= 080;
0591: vdata_out <= 081;
0592: vdata_out <= 082;
0593: vdata_out <= 083;
0594: vdata_out <= 084;
0595: vdata_out <= 085;
0596: vdata_out <= 086;
0597: vdata_out <= 087;
0598: vdata_out <= 088;
0599: vdata_out <= 089;
0600: vdata_out <= 090;
0601: vdata_out <= 091;
0602: vdata_out <= 092;
0603: vdata_out <= 093;
0604: vdata_out <= 093;
0605: vdata_out <= 094;
0606: vdata_out <= 095;
0607: vdata_out <= 096;
0608: vdata_out <= 097;
0609: vdata_out <= 098;
0610: vdata_out <= 099;
0611: vdata_out <= 100;
0612: vdata_out <= 101;
0613: vdata_out <= 102;
0614: vdata_out <= 103;
0615: vdata_out <= 104;
0616: vdata_out <= 105;
0617: vdata_out <= 106;
0618: vdata_out <= 107;
0619: vdata_out <= 108;
0620: vdata_out <= 109;
0621: vdata_out <= 110;
0622: vdata_out <= 111;
0623: vdata_out <= 112;
0624: vdata_out <= 113;
0625: vdata_out <= 114;
0626: vdata_out <= 115;
0627: vdata_out <= 116;
0628: vdata_out <= 117;
0629: vdata_out <= 117;
0630: vdata_out <= 118;
0631: vdata_out <= 119;
0632: vdata_out <= 120;
0633: vdata_out <= 121;
0634: vdata_out <= 122;
0635: vdata_out <= 123;
0636: vdata_out <= 124;
0637: vdata_out <= 125;
0638: vdata_out <= 126;
0639: vdata_out <= 127;
0640: vdata_out <= 000;
0641: vdata_out <= 001;
0642: vdata_out <= 002;
0643: vdata_out <= 002;
0644: vdata_out <= 003;
0645: vdata_out <= 004;
0646: vdata_out <= 005;
0647: vdata_out <= 006;
0648: vdata_out <= 007;
0649: vdata_out <= 008;
0650: vdata_out <= 009;
0651: vdata_out <= 010;
0652: vdata_out <= 011;
0653: vdata_out <= 012;
0654: vdata_out <= 013;
0655: vdata_out <= 013;
0656: vdata_out <= 014;
0657: vdata_out <= 015;
0658: vdata_out <= 016;
0659: vdata_out <= 017;
0660: vdata_out <= 018;
0661: vdata_out <= 019;
0662: vdata_out <= 020;
0663: vdata_out <= 021;
0664: vdata_out <= 022;
0665: vdata_out <= 023;
0666: vdata_out <= 024;
0667: vdata_out <= 025;
0668: vdata_out <= 026;
0669: vdata_out <= 027;
0670: vdata_out <= 028;
0671: vdata_out <= 029;
0672: vdata_out <= 030;
0673: vdata_out <= 031;
0674: vdata_out <= 032;
0675: vdata_out <= 033;
0676: vdata_out <= 034;
0677: vdata_out <= 035;
0678: vdata_out <= 036;
0679: vdata_out <= 037;
0680: vdata_out <= 038;
0681: vdata_out <= 039;
0682: vdata_out <= 040;
0683: vdata_out <= 041;
0684: vdata_out <= 042;
0685: vdata_out <= 043;
0686: vdata_out <= 044;
0687: vdata_out <= 045;
0688: vdata_out <= 046;
0689: vdata_out <= 047;
0690: vdata_out <= 048;
0691: vdata_out <= 049;
0692: vdata_out <= 050;
0693: vdata_out <= 051;
0694: vdata_out <= 052;
0695: vdata_out <= 053;
0696: vdata_out <= 054;
0697: vdata_out <= 055;
0698: vdata_out <= 056;
0699: vdata_out <= 057;
0700: vdata_out <= 058;
0701: vdata_out <= 059;
0702: vdata_out <= 060;
0703: vdata_out <= 061;
0704: vdata_out <= 062;
0705: vdata_out <= 063;
0706: vdata_out <= 064;
0707: vdata_out <= 065;
0708: vdata_out <= 066;
0709: vdata_out <= 067;
0710: vdata_out <= 068;
0711: vdata_out <= 069;
0712: vdata_out <= 070;
0713: vdata_out <= 071;
0714: vdata_out <= 072;
0715: vdata_out <= 073;
0716: vdata_out <= 074;
0717: vdata_out <= 075;
0718: vdata_out <= 076;
0719: vdata_out <= 077;
0720: vdata_out <= 078;
0721: vdata_out <= 079;
0722: vdata_out <= 080;
0723: vdata_out <= 081;
0724: vdata_out <= 082;
0725: vdata_out <= 083;
0726: vdata_out <= 084;
0727: vdata_out <= 085;
0728: vdata_out <= 086;
0729: vdata_out <= 087;
0730: vdata_out <= 088;
0731: vdata_out <= 089;
0732: vdata_out <= 091;
0733: vdata_out <= 092;
0734: vdata_out <= 093;
0735: vdata_out <= 094;
0736: vdata_out <= 095;
0737: vdata_out <= 096;
0738: vdata_out <= 097;
0739: vdata_out <= 098;
0740: vdata_out <= 099;
0741: vdata_out <= 100;
0742: vdata_out <= 101;
0743: vdata_out <= 102;
0744: vdata_out <= 103;
0745: vdata_out <= 104;
0746: vdata_out <= 105;
0747: vdata_out <= 106;
0748: vdata_out <= 107;
0749: vdata_out <= 108;
0750: vdata_out <= 109;
0751: vdata_out <= 110;
0752: vdata_out <= 111;
0753: vdata_out <= 112;
0754: vdata_out <= 113;
0755: vdata_out <= 114;
0756: vdata_out <= 115;
0757: vdata_out <= 117;
0758: vdata_out <= 118;
0759: vdata_out <= 119;
0760: vdata_out <= 120;
0761: vdata_out <= 121;
0762: vdata_out <= 122;
0763: vdata_out <= 123;
0764: vdata_out <= 124;
0765: vdata_out <= 125;
0766: vdata_out <= 126;
0767: vdata_out <= 127;
0768: vdata_out <= 000;
0769: vdata_out <= 001;
0770: vdata_out <= 001;
0771: vdata_out <= 002;
0772: vdata_out <= 003;
0773: vdata_out <= 004;
0774: vdata_out <= 004;
0775: vdata_out <= 005;
0776: vdata_out <= 006;
0777: vdata_out <= 007;
0778: vdata_out <= 008;
0779: vdata_out <= 009;
0780: vdata_out <= 009;
0781: vdata_out <= 010;
0782: vdata_out <= 011;
0783: vdata_out <= 012;
0784: vdata_out <= 013;
0785: vdata_out <= 014;
0786: vdata_out <= 015;
0787: vdata_out <= 016;
0788: vdata_out <= 017;
0789: vdata_out <= 018;
0790: vdata_out <= 018;
0791: vdata_out <= 019;
0792: vdata_out <= 020;
0793: vdata_out <= 021;
0794: vdata_out <= 022;
0795: vdata_out <= 023;
0796: vdata_out <= 024;
0797: vdata_out <= 025;
0798: vdata_out <= 026;
0799: vdata_out <= 027;
0800: vdata_out <= 028;
0801: vdata_out <= 029;
0802: vdata_out <= 030;
0803: vdata_out <= 031;
0804: vdata_out <= 032;
0805: vdata_out <= 033;
0806: vdata_out <= 034;
0807: vdata_out <= 035;
0808: vdata_out <= 036;
0809: vdata_out <= 037;
0810: vdata_out <= 038;
0811: vdata_out <= 039;
0812: vdata_out <= 040;
0813: vdata_out <= 041;
0814: vdata_out <= 042;
0815: vdata_out <= 043;
0816: vdata_out <= 044;
0817: vdata_out <= 045;
0818: vdata_out <= 046;
0819: vdata_out <= 047;
0820: vdata_out <= 048;
0821: vdata_out <= 049;
0822: vdata_out <= 050;
0823: vdata_out <= 051;
0824: vdata_out <= 052;
0825: vdata_out <= 053;
0826: vdata_out <= 054;
0827: vdata_out <= 055;
0828: vdata_out <= 056;
0829: vdata_out <= 057;
0830: vdata_out <= 058;
0831: vdata_out <= 059;
0832: vdata_out <= 060;
0833: vdata_out <= 061;
0834: vdata_out <= 062;
0835: vdata_out <= 063;
0836: vdata_out <= 064;
0837: vdata_out <= 065;
0838: vdata_out <= 066;
0839: vdata_out <= 067;
0840: vdata_out <= 068;
0841: vdata_out <= 069;
0842: vdata_out <= 070;
0843: vdata_out <= 071;
0844: vdata_out <= 072;
0845: vdata_out <= 073;
0846: vdata_out <= 074;
0847: vdata_out <= 075;
0848: vdata_out <= 076;
0849: vdata_out <= 077;
0850: vdata_out <= 078;
0851: vdata_out <= 080;
0852: vdata_out <= 081;
0853: vdata_out <= 082;
0854: vdata_out <= 083;
0855: vdata_out <= 084;
0856: vdata_out <= 085;
0857: vdata_out <= 086;
0858: vdata_out <= 087;
0859: vdata_out <= 088;
0860: vdata_out <= 089;
0861: vdata_out <= 090;
0862: vdata_out <= 091;
0863: vdata_out <= 092;
0864: vdata_out <= 093;
0865: vdata_out <= 094;
0866: vdata_out <= 095;
0867: vdata_out <= 097;
0868: vdata_out <= 098;
0869: vdata_out <= 099;
0870: vdata_out <= 100;
0871: vdata_out <= 101;
0872: vdata_out <= 102;
0873: vdata_out <= 103;
0874: vdata_out <= 104;
0875: vdata_out <= 105;
0876: vdata_out <= 106;
0877: vdata_out <= 107;
0878: vdata_out <= 108;
0879: vdata_out <= 110;
0880: vdata_out <= 111;
0881: vdata_out <= 112;
0882: vdata_out <= 113;
0883: vdata_out <= 114;
0884: vdata_out <= 115;
0885: vdata_out <= 116;
0886: vdata_out <= 117;
0887: vdata_out <= 118;
0888: vdata_out <= 119;
0889: vdata_out <= 120;
0890: vdata_out <= 122;
0891: vdata_out <= 123;
0892: vdata_out <= 124;
0893: vdata_out <= 125;
0894: vdata_out <= 126;
0895: vdata_out <= 127;
0896: vdata_out <= 000;
0897: vdata_out <= 000;
0898: vdata_out <= 001;
0899: vdata_out <= 002;
0900: vdata_out <= 002;
0901: vdata_out <= 003;
0902: vdata_out <= 004;
0903: vdata_out <= 005;
0904: vdata_out <= 005;
0905: vdata_out <= 006;
0906: vdata_out <= 007;
0907: vdata_out <= 008;
0908: vdata_out <= 008;
0909: vdata_out <= 009;
0910: vdata_out <= 010;
0911: vdata_out <= 011;
0912: vdata_out <= 012;
0913: vdata_out <= 013;
0914: vdata_out <= 013;
0915: vdata_out <= 014;
0916: vdata_out <= 015;
0917: vdata_out <= 016;
0918: vdata_out <= 017;
0919: vdata_out <= 018;
0920: vdata_out <= 019;
0921: vdata_out <= 020;
0922: vdata_out <= 020;
0923: vdata_out <= 021;
0924: vdata_out <= 022;
0925: vdata_out <= 023;
0926: vdata_out <= 024;
0927: vdata_out <= 025;
0928: vdata_out <= 026;
0929: vdata_out <= 027;
0930: vdata_out <= 028;
0931: vdata_out <= 029;
0932: vdata_out <= 030;
0933: vdata_out <= 031;
0934: vdata_out <= 032;
0935: vdata_out <= 033;
0936: vdata_out <= 034;
0937: vdata_out <= 035;
0938: vdata_out <= 036;
0939: vdata_out <= 037;
0940: vdata_out <= 038;
0941: vdata_out <= 039;
0942: vdata_out <= 040;
0943: vdata_out <= 040;
0944: vdata_out <= 041;
0945: vdata_out <= 042;
0946: vdata_out <= 043;
0947: vdata_out <= 044;
0948: vdata_out <= 045;
0949: vdata_out <= 046;
0950: vdata_out <= 047;
0951: vdata_out <= 049;
0952: vdata_out <= 050;
0953: vdata_out <= 051;
0954: vdata_out <= 052;
0955: vdata_out <= 053;
0956: vdata_out <= 054;
0957: vdata_out <= 055;
0958: vdata_out <= 056;
0959: vdata_out <= 057;
0960: vdata_out <= 058;
0961: vdata_out <= 059;
0962: vdata_out <= 060;
0963: vdata_out <= 061;
0964: vdata_out <= 062;
0965: vdata_out <= 063;
0966: vdata_out <= 064;
0967: vdata_out <= 065;
0968: vdata_out <= 066;
0969: vdata_out <= 067;
0970: vdata_out <= 068;
0971: vdata_out <= 069;
0972: vdata_out <= 070;
0973: vdata_out <= 071;
0974: vdata_out <= 073;
0975: vdata_out <= 074;
0976: vdata_out <= 075;
0977: vdata_out <= 076;
0978: vdata_out <= 077;
0979: vdata_out <= 078;
0980: vdata_out <= 079;
0981: vdata_out <= 080;
0982: vdata_out <= 081;
0983: vdata_out <= 082;
0984: vdata_out <= 083;
0985: vdata_out <= 084;
0986: vdata_out <= 085;
0987: vdata_out <= 087;
0988: vdata_out <= 088;
0989: vdata_out <= 089;
0990: vdata_out <= 090;
0991: vdata_out <= 091;
0992: vdata_out <= 092;
0993: vdata_out <= 093;
0994: vdata_out <= 094;
0995: vdata_out <= 095;
0996: vdata_out <= 096;
0997: vdata_out <= 098;
0998: vdata_out <= 099;
0999: vdata_out <= 100;
1000: vdata_out <= 101;
1001: vdata_out <= 102;
1002: vdata_out <= 103;
1003: vdata_out <= 104;
1004: vdata_out <= 105;
1005: vdata_out <= 107;
1006: vdata_out <= 108;
1007: vdata_out <= 109;
1008: vdata_out <= 110;
1009: vdata_out <= 111;
1010: vdata_out <= 112;
1011: vdata_out <= 113;
1012: vdata_out <= 114;
1013: vdata_out <= 116;
1014: vdata_out <= 117;
1015: vdata_out <= 118;
1016: vdata_out <= 119;
1017: vdata_out <= 120;
1018: vdata_out <= 121;
1019: vdata_out <= 122;
1020: vdata_out <= 124;
1021: vdata_out <= 125;
1022: vdata_out <= 126;
1023: vdata_out <= 127;
endcase
if (!nbypass_r)
vdata_out <= {addr_r[color_width_i-1:0],{0{vdata_in[color_width_i-1]}}};
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.0
// \ \ Filename: serdes_1_to_n_clk_ddr_s8_diff.v
// / / Date Last Modified: November 5 2009
// /___/ /\ Date Created: September 1 2009
// \ \ / \
// \___\/\___\
//
//Device: Spartan 6
//Purpose: 1-bit generic 1:n DDR clock receiver module for serdes factors
// from 2 to 8 with differential inputs
// Instantiates necessary BUFIO2 clock buffers
//Reference:
//
//Revision History:
// Rev 1.0 - First created (nicks)
///////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
//
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to you
// by Xilinx, and to the maximum extent permitted by applicable law:
// (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
// AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
// FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
// or tort, including negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these materials,
// including for any direct, or any indirect, special, incidental, or consequential loss
// or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
// as a result of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// Critical Applications:
//
// Xilinx products are not designed or intended to be fail-safe, or for use in any application
// requiring fail-safe performance, such as life-support or safety devices or systems,
// Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
// or any other applications that could lead to death, personal injury, or severe property or
// environmental damage (individually and collectively, "Critical Applications"). Customer assumes
// the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
// to applicable laws and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//////////////////////////////////////////////////////////////////////////////
/*
* Author:
* Description:
*
* Changes:
*/
`define SWAP_CLK 0
module sd_dev_platform_spartan6 #(
parameter OUTPUT_DELAY = 63,
parameter INPUT_DELAY = 63
)(
input rst,
input clk,
//SD Stack Interfface
output o_locked,
output o_sd_clk,
// output o_sd_clk_x2,
input i_sd_cmd_dir,
input i_sd_cmd_out,
output o_sd_cmd_in,
input i_sd_data_dir,
input [7:0] i_sd_data_out,
output [7:0] o_sd_data_in,
input i_phy_clk,
inout io_phy_sd_cmd,
inout [3:0] io_phy_sd_data
);
//local parameters
//registes/wires
wire [7:0] sd_data_out;
wire pll_sd_clk;
wire ddr_clk_predelay;
wire ddr_clk_delay;
wire ddr_clk;
wire sd_cmd_tristate_dly;
wire sd_cmd_out_delay;
wire sd_cmd_in_delay;
wire [3:0] pin_data_out;
wire [3:0] pin_data_in;
wire [3:0] pin_data_tristate;
wire [3:0] pin_data_out_delay;
wire [3:0] pin_data_in_predelay;
wire [3:0] pin_data_tristate_predelay;
wire serdes_strobe;
wire phy_clk_s;
wire pll_phy_clk;
wire clkfb;
wire fb_locked;
wire serdes_clk_fb;
`ifdef SIMULATION
pullup (io_phy_sd_data[0]);
pullup (io_phy_sd_data[1]);
pullup (io_phy_sd_data[2]);
pullup (io_phy_sd_data[3]);
`endif
//assign fb_locked = o_locked && pll_locked;
//assign o_locked = 1;
assign fb_locked = 1;
assign o_locked = !rst;
//submodules
//Read in the clock
wire buf_clk;
wire buf_phy_clk;
wire buf_phy_clk_n;
wire predelay_clk_p;
wire predelay_clk_n;
wire clock_delay_p;
wire clock_delay_n;
IBUFG input_clock_buffer_p(
.I (i_phy_clk ),
//.O (buf_phy_clk )
.O (o_sd_clk )
);
/*
assign predelay_clk_p = buf_phy_clk ^ `SWAP_CLK;
//assign predelay_clk_n = ~buf_phy_clk ^ `SWAP_CLK;
IODELAY2 # (
.DATA_RATE ("SDR" ),
.SIM_TAPDELAY_VALUE (49 ),
.IDELAY_VALUE (0 ),
.IDELAY2_VALUE (0 ),
.ODELAY_VALUE (0 ),
.IDELAY_MODE ("NORMAL" ),
//.SERDES_MODE ("MASTER" ),
.SERDES_MODE ("NONE" ),
.IDELAY_TYPE ("FIXED" ),
.COUNTER_WRAPAROUND ("STAY_AT_LIMIT" ),
.DELAY_SRC ("IDATAIN" )
) clock_iodelay_m (
.IDATAIN (predelay_clk_p ),
.TOUT ( ),
.DOUT ( ),
.T (1'b1 ),
.ODATAIN (1'b0 ),
.DATAOUT (clock_delay_p ),
.DATAOUT2 ( ),
.IOCLK0 (1'b0 ),
.IOCLK1 (1'b0 ),
.CLK (1'b0 ),
.CAL (1'b0 ),
.INC (1'b0 ),
.CE (1'b0 ),
.RST (1'b0 ),
.BUSY ( )
);
BUFG pos_clk_buf (
.I (clock_delay_p ),
.O (o_sd_clk )
);
*/
//Control Line
IOBUF
#(
.IOSTANDARD ("LVCMOS33" )
)
cmd_iobuf(
.T (sd_cmd_tristate_dly ),
.O (sd_cmd_in_delay ),
.I (sd_cmd_out_delay ),
.IO (io_phy_sd_cmd )
);
`ifdef SIMULATION
pullup (io_phy_sd_cmd);
`endif
IODELAY2 #(
.DATA_RATE ("SDR" ),
.IDELAY_VALUE (INPUT_DELAY ),
.ODELAY_VALUE (OUTPUT_DELAY ),
.IDELAY_TYPE ("FIXED" ),
.COUNTER_WRAPAROUND ("STAY_AT_LIMIT" ),
.DELAY_SRC ("IO" ),
.SERDES_MODE ("NONE" ),
.SIM_TAPDELAY_VALUE (75 )
) cmd_delay (
.T (!i_sd_cmd_dir ),
.ODATAIN (i_sd_cmd_out ),
//.DATAOUT (o_sd_cmd_in ),
.DATAOUT2 (o_sd_cmd_in ),
//FPGA Fabric
//IOB
.TOUT (sd_cmd_tristate_dly ),
.IDATAIN (sd_cmd_in_delay ),
.DOUT (sd_cmd_out_delay ),
.IOCLK0 (1'b0 ), //XXX: This one is not SERDESized.. Do I need to add a clock??
.IOCLK1 (1'b0 ),
.CLK (1'b0 ),
.CAL (1'b0 ),
.INC (1'b0 ),
.CE (1'b0 ),
.BUSY ( ),
.RST (1'b0 )
);
//DATA Lines
genvar pcnt;
generate
for (pcnt = 0; pcnt < 4; pcnt = pcnt + 1) begin: sgen
IOBUF #(
.IOSTANDARD ("LVCMOS33" )
) io_data_buffer (
.T (pin_data_tristate[pcnt]),
.I (pin_data_out[pcnt] ),
.O (pin_data_in[pcnt] ),
.IO (io_phy_sd_data[pcnt] )
);
IODELAY2 #(
.DATA_RATE ("SDR" ),
.IDELAY_VALUE (INPUT_DELAY ),
.ODELAY_VALUE (OUTPUT_DELAY ),
.IDELAY_TYPE ("FIXED" ),
.COUNTER_WRAPAROUND ("STAY_AT_LIMIT" ),
.DELAY_SRC ("IO" ),
.SERDES_MODE ("NONE" ),
.SIM_TAPDELAY_VALUE (75 )
)sd_data_delay(
//IOSerdes
//.T (pin_data_tristate_predelay[pcnt] ),
.T (!i_sd_data_dir ),
.ODATAIN (pin_data_in_predelay[pcnt] ),
.DATAOUT (pin_data_out_delay[pcnt] ),
//To/From IO Buffer
.TOUT (pin_data_tristate[pcnt] ),
.IDATAIN (pin_data_in[pcnt] ),
.DOUT (pin_data_out[pcnt] ),
.DATAOUT2 ( ),
.IOCLK0 (1'b0 ), //This one is not SERDESized.. Do I need to add a clock??
.IOCLK1 (1'b0 ),
.CLK (1'b0 ),
.CAL (1'b0 ),
.INC (1'b0 ),
.CE (1'b0 ),
.BUSY ( ),
.RST (1'b0 )
);
IDDR2 #(
.DDR_ALIGNMENT ("NONE" ),
.INIT_Q0 (0 ),
.INIT_Q1 (0 ),
.SRTYPE ("SYNC" )
) data_in_ddr (
.C0 (o_sd_clk ),
//.C1 (neg_sd_clk ),
.C1 (!o_sd_clk ),
.CE (1'b1 ),
.S (1'b0 ),
.R (1'b0 ),
.D (pin_data_out_delay[pcnt] ),
.Q0 (o_sd_data_in[pcnt] ),
.Q1 (o_sd_data_in[pcnt + 4] )
);
ODDR2 #(
.DDR_ALIGNMENT ("C0" ),
.INIT (0 ),
.SRTYPE ("ASYNC" )
) data_out_ddr (
.C0 (o_sd_clk ),
.C1 (!o_sd_clk ),
//.C1 (neg_sd_clk ),
.CE (1'b1 ),
.S (1'b0 ),
.R (1'b0 ),
.D0 (sd_data_out[pcnt + 4] ),
.D1 (sd_data_out[pcnt] ),
.Q (pin_data_in_predelay[pcnt] )
);
end
endgenerate
//asynchronous logic
assign sd_data_out = i_sd_data_out;
//Synchronous Logic
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFBBP_FUNCTIONAL_V
`define SKY130_FD_SC_LS__SDFBBP_FUNCTIONAL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr/sky130_fd_sc_ls__udp_dff_nsr.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ls__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFBBP_FUNCTIONAL_V |
`timescale 1ns/10ps
module audio_pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(1),
.output_clock_frequency0("11.288888 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFSBP_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__SDFSBP_PP_SYMBOL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFSBP_PP_SYMBOL_V
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7:5.3
// IP Revision: 1
(* X_CORE_INFO = "processing_system7_v5_3_processing_system7,Vivado 2013.4" *)
(* CHECK_LICENSE_TYPE = "design_1_processing_system7_0_1,processing_system7_v5_3_processing_system7,{}" *)
(* CORE_GENERATION_INFO = "design_1_processing_system7_0_1,processing_system7_v5_3_processing_system7,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.3,x_ipCoreRevision=1,x_ipLanguage=VERILOG,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CHECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=true,C_FCLK_CLK1_BUF=false,C_FCLK_CLK2_BUF=false,C_FCLK_CLK3_BUF=false,C_PACKAGE_NAME=clg400}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_processing_system7_0_1 (
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
SDIO0_WP,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_I" *)
input wire I2C0_SDA_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_O" *)
output wire I2C0_SDA_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_T" *)
output wire I2C0_SDA_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_I" *)
input wire I2C0_SCL_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_O" *)
output wire I2C0_SCL_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_T" *)
output wire I2C0_SCL_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 WP" *)
input wire SDIO0_WP;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *)
output wire [1 : 0] USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *)
output wire USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *)
input wire USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
output wire FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
output wire FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
inout wire [53 : 0] MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
inout wire DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
inout wire DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
inout wire DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
inout wire DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
inout wire DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
inout wire DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
inout wire DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
inout wire DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
inout wire DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
inout wire [2 : 0] DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
inout wire [14 : 0] DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
inout wire DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
inout wire DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
inout wire [3 : 0] DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
inout wire [31 : 0] DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
inout wire [3 : 0] DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
inout wire [3 : 0] DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
inout wire PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
inout wire PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
inout wire PS_PORB;
processing_system7_v5_3_processing_system7 #(
.C_EN_EMIO_ENET0(0),
.C_EN_EMIO_ENET1(0),
.C_EN_EMIO_TRACE(0),
.C_INCLUDE_TRACE_BUFFER(0),
.C_TRACE_BUFFER_FIFO_SIZE(128),
.USE_TRACE_DATA_EDGE_DETECTOR(0),
.C_TRACE_BUFFER_CLOCK_DELAY(12),
.C_EMIO_GPIO_WIDTH(64),
.C_INCLUDE_ACP_TRANS_CHECK(0),
.C_USE_DEFAULT_ACP_USER_VAL(0),
.C_S_AXI_ACP_ARUSER_VAL(31),
.C_S_AXI_ACP_AWUSER_VAL(31),
.C_M_AXI_GP0_ID_WIDTH(12),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ID_WIDTH(12),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_S_AXI_GP0_ID_WIDTH(6),
.C_S_AXI_GP1_ID_WIDTH(6),
.C_S_AXI_ACP_ID_WIDTH(3),
.C_S_AXI_HP0_ID_WIDTH(6),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_ID_WIDTH(6),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_ID_WIDTH(6),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_ID_WIDTH(6),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
.C_NUM_F2P_INTR_INPUTS(1),
.C_DQ_WIDTH(32),
.C_DQS_WIDTH(4),
.C_DM_WIDTH(4),
.C_MIO_PRIMITIVE(54),
.C_PS7_SI_REV("PRODUCTION"),
.C_FCLK_CLK0_BUF("true"),
.C_FCLK_CLK1_BUF("false"),
.C_FCLK_CLK2_BUF("false"),
.C_FCLK_CLK3_BUF("false"),
.C_PACKAGE_NAME("clg400")
) inst (
.CAN0_PHY_TX(),
.CAN0_PHY_RX(1'B0),
.CAN1_PHY_TX(),
.CAN1_PHY_RX(1'B0),
.ENET0_GMII_TX_EN(),
.ENET0_GMII_TX_ER(),
.ENET0_MDIO_MDC(),
.ENET0_MDIO_O(),
.ENET0_MDIO_T(),
.ENET0_PTP_DELAY_REQ_RX(),
.ENET0_PTP_DELAY_REQ_TX(),
.ENET0_PTP_PDELAY_REQ_RX(),
.ENET0_PTP_PDELAY_REQ_TX(),
.ENET0_PTP_PDELAY_RESP_RX(),
.ENET0_PTP_PDELAY_RESP_TX(),
.ENET0_PTP_SYNC_FRAME_RX(),
.ENET0_PTP_SYNC_FRAME_TX(),
.ENET0_SOF_RX(),
.ENET0_SOF_TX(),
.ENET0_GMII_TXD(),
.ENET0_GMII_COL(1'B0),
.ENET0_GMII_CRS(1'B0),
.ENET0_GMII_RX_CLK(1'B0),
.ENET0_GMII_RX_DV(1'B0),
.ENET0_GMII_RX_ER(1'B0),
.ENET0_GMII_TX_CLK(1'B0),
.ENET0_MDIO_I(1'B0),
.ENET0_EXT_INTIN(1'B0),
.ENET0_GMII_RXD(8'B0),
.ENET1_GMII_TX_EN(),
.ENET1_GMII_TX_ER(),
.ENET1_MDIO_MDC(),
.ENET1_MDIO_O(),
.ENET1_MDIO_T(),
.ENET1_PTP_DELAY_REQ_RX(),
.ENET1_PTP_DELAY_REQ_TX(),
.ENET1_PTP_PDELAY_REQ_RX(),
.ENET1_PTP_PDELAY_REQ_TX(),
.ENET1_PTP_PDELAY_RESP_RX(),
.ENET1_PTP_PDELAY_RESP_TX(),
.ENET1_PTP_SYNC_FRAME_RX(),
.ENET1_PTP_SYNC_FRAME_TX(),
.ENET1_SOF_RX(),
.ENET1_SOF_TX(),
.ENET1_GMII_TXD(),
.ENET1_GMII_COL(1'B0),
.ENET1_GMII_CRS(1'B0),
.ENET1_GMII_RX_CLK(1'B0),
.ENET1_GMII_RX_DV(1'B0),
.ENET1_GMII_RX_ER(1'B0),
.ENET1_GMII_TX_CLK(1'B0),
.ENET1_MDIO_I(1'B0),
.ENET1_EXT_INTIN(1'B0),
.ENET1_GMII_RXD(8'B0),
.GPIO_I(64'B0),
.GPIO_O(),
.GPIO_T(),
.I2C0_SDA_I(I2C0_SDA_I),
.I2C0_SDA_O(I2C0_SDA_O),
.I2C0_SDA_T(I2C0_SDA_T),
.I2C0_SCL_I(I2C0_SCL_I),
.I2C0_SCL_O(I2C0_SCL_O),
.I2C0_SCL_T(I2C0_SCL_T),
.I2C1_SDA_I(1'B0),
.I2C1_SDA_O(),
.I2C1_SDA_T(),
.I2C1_SCL_I(1'B0),
.I2C1_SCL_O(),
.I2C1_SCL_T(),
.PJTAG_TCK(1'B0),
.PJTAG_TMS(1'B0),
.PJTAG_TD_I(1'B0),
.PJTAG_TD_T(),
.PJTAG_TD_O(),
.SDIO0_CLK(),
.SDIO0_CLK_FB(1'B0),
.SDIO0_CMD_O(),
.SDIO0_CMD_I(1'B0),
.SDIO0_CMD_T(),
.SDIO0_DATA_I(4'B0),
.SDIO0_DATA_O(),
.SDIO0_DATA_T(),
.SDIO0_LED(),
.SDIO0_CDN(1'B0),
.SDIO0_WP(SDIO0_WP),
.SDIO0_BUSPOW(),
.SDIO0_BUSVOLT(),
.SDIO1_CLK(),
.SDIO1_CLK_FB(1'B0),
.SDIO1_CMD_O(),
.SDIO1_CMD_I(1'B0),
.SDIO1_CMD_T(),
.SDIO1_DATA_I(4'B0),
.SDIO1_DATA_O(),
.SDIO1_DATA_T(),
.SDIO1_LED(),
.SDIO1_CDN(1'B0),
.SDIO1_WP(1'B0),
.SDIO1_BUSPOW(),
.SDIO1_BUSVOLT(),
.SPI0_SCLK_I(1'B0),
.SPI0_SCLK_O(),
.SPI0_SCLK_T(),
.SPI0_MOSI_I(1'B0),
.SPI0_MOSI_O(),
.SPI0_MOSI_T(),
.SPI0_MISO_I(1'B0),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_SS_I(1'B0),
.SPI0_SS_O(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_T(),
.SPI1_SCLK_I(1'B0),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_MOSI_I(1'B0),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_MISO_I(1'B0),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_SS_I(1'B0),
.SPI1_SS_O(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_T(),
.UART0_DTRN(),
.UART0_RTSN(),
.UART0_TX(),
.UART0_CTSN(1'B0),
.UART0_DCDN(1'B0),
.UART0_DSRN(1'B0),
.UART0_RIN(1'B0),
.UART0_RX(1'B0),
.UART1_DTRN(),
.UART1_RTSN(),
.UART1_TX(),
.UART1_CTSN(1'B0),
.UART1_DCDN(1'B0),
.UART1_DSRN(1'B0),
.UART1_RIN(1'B0),
.UART1_RX(1'B0),
.TTC0_WAVE0_OUT(),
.TTC0_WAVE1_OUT(),
.TTC0_WAVE2_OUT(),
.TTC0_CLK0_IN(1'B0),
.TTC0_CLK1_IN(1'B0),
.TTC0_CLK2_IN(1'B0),
.TTC1_WAVE0_OUT(),
.TTC1_WAVE1_OUT(),
.TTC1_WAVE2_OUT(),
.TTC1_CLK0_IN(1'B0),
.TTC1_CLK1_IN(1'B0),
.TTC1_CLK2_IN(1'B0),
.WDT_CLK_IN(1'B0),
.WDT_RST_OUT(),
.TRACE_CLK(1'B0),
.TRACE_CTL(),
.TRACE_DATA(),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB1_PORT_INDCTL(),
.USB1_VBUS_PWRSELECT(),
.USB1_VBUS_PWRFAULT(1'B0),
.SRAM_INTIN(1'B0),
.M_AXI_GP0_ARVALID(),
.M_AXI_GP0_AWVALID(),
.M_AXI_GP0_BREADY(),
.M_AXI_GP0_RREADY(),
.M_AXI_GP0_WLAST(),
.M_AXI_GP0_WVALID(),
.M_AXI_GP0_ARID(),
.M_AXI_GP0_AWID(),
.M_AXI_GP0_WID(),
.M_AXI_GP0_ARBURST(),
.M_AXI_GP0_ARLOCK(),
.M_AXI_GP0_ARSIZE(),
.M_AXI_GP0_AWBURST(),
.M_AXI_GP0_AWLOCK(),
.M_AXI_GP0_AWSIZE(),
.M_AXI_GP0_ARPROT(),
.M_AXI_GP0_AWPROT(),
.M_AXI_GP0_ARADDR(),
.M_AXI_GP0_AWADDR(),
.M_AXI_GP0_WDATA(),
.M_AXI_GP0_ARCACHE(),
.M_AXI_GP0_ARLEN(),
.M_AXI_GP0_ARQOS(),
.M_AXI_GP0_AWCACHE(),
.M_AXI_GP0_AWLEN(),
.M_AXI_GP0_AWQOS(),
.M_AXI_GP0_WSTRB(),
.M_AXI_GP0_ACLK(1'B0),
.M_AXI_GP0_ARREADY(1'B0),
.M_AXI_GP0_AWREADY(1'B0),
.M_AXI_GP0_BVALID(1'B0),
.M_AXI_GP0_RLAST(1'B0),
.M_AXI_GP0_RVALID(1'B0),
.M_AXI_GP0_WREADY(1'B0),
.M_AXI_GP0_BID(12'B0),
.M_AXI_GP0_RID(12'B0),
.M_AXI_GP0_BRESP(2'B0),
.M_AXI_GP0_RRESP(2'B0),
.M_AXI_GP0_RDATA(32'B0),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_RCOUNT(),
.S_AXI_HP0_WCOUNT(),
.S_AXI_HP0_RACOUNT(),
.S_AXI_HP0_WACOUNT(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RDISSUECAP1_EN(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WRISSUECAP1_EN(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_RCOUNT(),
.S_AXI_HP1_WCOUNT(),
.S_AXI_HP1_RACOUNT(),
.S_AXI_HP1_WACOUNT(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RDISSUECAP1_EN(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WRISSUECAP1_EN(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_RCOUNT(),
.S_AXI_HP2_WCOUNT(),
.S_AXI_HP2_RACOUNT(),
.S_AXI_HP2_WACOUNT(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RDISSUECAP1_EN(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WRISSUECAP1_EN(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_RCOUNT(),
.S_AXI_HP3_WCOUNT(),
.S_AXI_HP3_RACOUNT(),
.S_AXI_HP3_WACOUNT(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RDISSUECAP1_EN(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WRISSUECAP1_EN(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.IRQ_P2F_DMAC_ABORT(),
.IRQ_P2F_DMAC0(),
.IRQ_P2F_DMAC1(),
.IRQ_P2F_DMAC2(),
.IRQ_P2F_DMAC3(),
.IRQ_P2F_DMAC4(),
.IRQ_P2F_DMAC5(),
.IRQ_P2F_DMAC6(),
.IRQ_P2F_DMAC7(),
.IRQ_P2F_SMC(),
.IRQ_P2F_QSPI(),
.IRQ_P2F_CTI(),
.IRQ_P2F_GPIO(),
.IRQ_P2F_USB0(),
.IRQ_P2F_ENET0(),
.IRQ_P2F_ENET_WAKE0(),
.IRQ_P2F_SDIO0(),
.IRQ_P2F_I2C0(),
.IRQ_P2F_SPI0(),
.IRQ_P2F_UART0(),
.IRQ_P2F_CAN0(),
.IRQ_P2F_USB1(),
.IRQ_P2F_ENET1(),
.IRQ_P2F_ENET_WAKE1(),
.IRQ_P2F_SDIO1(),
.IRQ_P2F_I2C1(),
.IRQ_P2F_SPI1(),
.IRQ_P2F_UART1(),
.IRQ_P2F_CAN1(),
.IRQ_F2P(1'B0),
.Core0_nFIQ(1'B0),
.Core0_nIRQ(1'B0),
.Core1_nFIQ(1'B0),
.Core1_nIRQ(1'B0),
.DMA0_DATYPE(),
.DMA0_DAVALID(),
.DMA0_DRREADY(),
.DMA1_DATYPE(),
.DMA1_DAVALID(),
.DMA1_DRREADY(),
.DMA2_DATYPE(),
.DMA2_DAVALID(),
.DMA2_DRREADY(),
.DMA3_DATYPE(),
.DMA3_DAVALID(),
.DMA3_DRREADY(),
.DMA0_ACLK(1'B0),
.DMA0_DAREADY(1'B0),
.DMA0_DRLAST(1'B0),
.DMA0_DRVALID(1'B0),
.DMA1_ACLK(1'B0),
.DMA1_DAREADY(1'B0),
.DMA1_DRLAST(1'B0),
.DMA1_DRVALID(1'B0),
.DMA2_ACLK(1'B0),
.DMA2_DAREADY(1'B0),
.DMA2_DRLAST(1'B0),
.DMA2_DRVALID(1'B0),
.DMA3_ACLK(1'B0),
.DMA3_DAREADY(1'B0),
.DMA3_DRLAST(1'B0),
.DMA3_DRVALID(1'B0),
.DMA0_DRTYPE(2'B0),
.DMA1_DRTYPE(2'B0),
.DMA2_DRTYPE(2'B0),
.DMA3_DRTYPE(2'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_CLKTRIG0_N(1'B0),
.FCLK_CLKTRIG1_N(1'B0),
.FCLK_CLKTRIG2_N(1'B0),
.FCLK_CLKTRIG3_N(1'B0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.FTMD_TRACEIN_DATA(32'B0),
.FTMD_TRACEIN_VALID(1'B0),
.FTMD_TRACEIN_CLK(1'B0),
.FTMD_TRACEIN_ATID(4'B0),
.FTMT_F2P_TRIG(4'B0),
.FTMT_F2P_TRIGACK(),
.FTMT_F2P_DEBUG(32'B0),
.FTMT_P2F_TRIGACK(4'B0),
.FTMT_P2F_TRIG(),
.FTMT_P2F_DEBUG(),
.FPGA_IDLE_N(1'B0),
.EVENT_EVENTO(),
.EVENT_STANDBYWFE(),
.EVENT_STANDBYWFI(),
.EVENT_EVENTI(1'B0),
.DDR_ARB(4'B0),
.MIO(MIO),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_Clk_n(DDR_Clk_n),
.DDR_Clk(DDR_Clk),
.DDR_CS_n(DDR_CS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_WEB(DDR_WEB),
.DDR_BankAddr(DDR_BankAddr),
.DDR_Addr(DDR_Addr),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DQS(DDR_DQS),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2BB2O_2_V
`define SKY130_FD_SC_HS__A2BB2O_2_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a2bb2o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a2bb2o_2 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a2bb2o_2 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2BB2O_2_V
|
module spi_ctrl(
clk,rst_n,sck,mosi,miso,cs_n,spi_tx_en,spi_rx_en,mode_select_CPHA,mode_select_CPOL,receive_status
);
input clk,rst_n,miso;
input mode_select_CPHA;
input mode_select_CPOL;
output sck,mosi,cs_n;
output receive_status;
input spi_tx_en;
input spi_rx_en;
wire spi_over;
wire receive_status;
reg spi_clk;
reg cs_n;
reg[7:0] clk_count;
reg[7:0] rst_count;
reg rst_flag;
/*
spi baud rate is calculated by clk / 100 / 3
as we count 3 sck change to be a full period
*/
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
clk_count <= 8'h0;
spi_clk <= 1'b0;
end
else begin
if(clk_count < 8'd100)
clk_count <= clk_count + 1'b1;
else begin
clk_count <= 8'h0;
spi_clk <= ~spi_clk;
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cs_n <= 1'b1;
else begin
if(spi_over || ((spi_tx_en == 1'b0) && (spi_rx_en == 1'b0)))
cs_n <= 1'b1;
else
cs_n <= 1'b0;
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)begin
rst_flag <= 1'b0;
rst_count <= 'h0;
end
else begin
if(rst_count<8'd20)
rst_count <= rst_count + 1'b1;
else
rst_flag <= 1'b1;
end
end
spi_master spi_master_instance(
.clk(spi_clk),
.rst_n(rst_flag),
.spi_miso(miso),
.spi_mosi(mosi),
.spi_clk(sck),
.spi_tx_en(spi_tx_en),
.spi_over(spi_over),
.spi_rx_en(spi_rx_en),
.mode_select_CPHA(mode_select_CPHA),
.mode_select_CPOL(mode_select_CPOL),
.receive_status(receive_status)
);
endmodule |
`include "Definitions_VGA.v"
module VGA_controller
(
input wire pixel_Clock, // 25 MHz
input wire pixel_reset,
output reg oVGA_HSYNC,
output reg oVGA_VSYNC,
output reg[2:0] oVGA_RGB
);
reg[10:0] rHorizontal_counter;
reg[10:0] rVertical_counter;
always @ (posedge pixel_Clock)
begin
oVGA_RGB <= {1'b1, 1'b0, 1'b1};
oVGA_RGB <= {1'b1, 1b'0, 1b'1};
UPCOUNTER_POSEDGE # ( 10 ) contador_columnas (
.Clock( pixel_Clock ),
.Reset( pixel_reset ),
.Initial( 10'b0 ),
.Enable( 1'b1 ),
.Q( rHorizontal_counter)
);
UPCOUNTER_POSEDGE # ( 10 ) contador_filas (
.Clock( pixel_Clock ),
.Reset( pixel_reset ),
.Initial( 10'b0 ),
.Enable( 1'b1 ),
.Q( rVertical_counter)
);
if(rVertical_counter == 10'd479) //ultima fila
begin
oVGA_VSYNC = 1'b0;
#`Tpw_h oVGA_VSYNC = 1'b1;
end
else if(rHorizontal_counter == 10'd639) //ultima columna
begin
assign rHorizontal_counter = 10'd0;
oVGA_HSYNC = 1'b0;
#`Tpw_v oVGA_HSYNC = 1'b1;
rVertical_counter = rVertical_counter + 10'd1;
end
else //en medio
begin
oVGA_HSYNC = 1'b1;
oVGA_VSYNC = 1'b1;
end
end
endmodule
module UPCOUNTER_POSEDGE # (parameter SIZE=16)
(
input wire Clock, Reset,
input wire [SIZE-1:0] Initial,
input wire Enable,
output reg [SIZE-1:0] Q
);
always @(posedge Clock )
begin
if (Reset)
Q = Initial;
else
begin
if (Enable)
Q = Q + 1;
end
end
endmodule
|
// megafunction wizard: %ALTFP_CONVERT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTFP_CONVERT
// ============================================================
// File Name: int_to_fp.v
// Megafunction Name(s):
// ALTFP_CONVERT
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 8.1 Build 163 10/28/2008 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2008 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altfp_convert CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix III" OPERATION="INT2FLOAT" ROUNDING="TO_NEAREST" WIDTH_DATA=32 WIDTH_EXP_INPUT=8 WIDTH_EXP_OUTPUT=11 WIDTH_INT=32 WIDTH_MAN_INPUT=23 WIDTH_MAN_OUTPUT=52 WIDTH_RESULT=64 clk_en clock dataa result
//VERSION_BEGIN 8.1 cbx_altbarrel_shift 2008:05:19:10:20:21:SJ cbx_altfp_convert 2008:09:12:02:26:36:SJ cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_altsyncram 2008:08:26:11:57:11:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_abs 2008:05:19:10:51:43:SJ cbx_lpm_add_sub 2008:05:19:10:49:01:SJ cbx_lpm_compare 2008:09:01:07:44:05:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_lpm_divide 2008:05:21:18:11:28:SJ cbx_lpm_mux 2008:05:19:10:30:36:SJ cbx_mgl 2008:08:08:15:16:18:SJ cbx_stratix 2008:08:05:17:10:23:SJ cbx_stratixii 2008:08:07:13:54:47:SJ cbx_stratixiii 2008:07:11:13:32:02:SJ cbx_util_mgl 2008:07:18:09:58:54:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix III" PIPELINE=2 SHIFTDIR="LEFT" SHIFTTYPE="LOGICAL" WIDTH=32 WIDTHDIST=5 aclr clk_en clock data distance result
//VERSION_BEGIN 8.1 cbx_altbarrel_shift 2008:05:19:10:20:21:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//synthesis_resources = reg 66
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altbarrel_shift_mvf
(
aclr,
clk_en,
clock,
data,
distance,
result) ;
input aclr;
input clk_en;
input clock;
input [31:0] data;
input [4:0] distance;
output [31:0] result;
reg [31:0] pipe_wl1c;
reg [31:0] pipe_wl2c;
reg sel_pipel3d1c;
reg sel_pipel4d1c;
wire direction_w;
wire [15:0] pad_w;
wire [191:0] sbit_w;
wire [4:0] sel_w;
// synopsys translate_off
initial
pipe_wl1c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) pipe_wl1c <= 32'b0;
else if (clk_en == 1'b1) pipe_wl1c <= ((({32{(sel_w[2] & (~ direction_w))}} & {sbit_w[91:64], pad_w[3:0]}) | ({32{(sel_w[2] & direction_w)}} & {pad_w[3:0], sbit_w[95:68]})) | ({32{(~ sel_w[2])}} & sbit_w[95:64]));
// synopsys translate_off
initial
pipe_wl2c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) pipe_wl2c <= 32'b0;
else if (clk_en == 1'b1) pipe_wl2c <= ((({32{(sel_w[4] & (~ direction_w))}} & {sbit_w[143:128], pad_w[15:0]}) | ({32{(sel_w[4] & direction_w)}} & {pad_w[15:0], sbit_w[159:144]})) | ({32{(~ sel_w[4])}} & sbit_w[159:128]));
// synopsys translate_off
initial
sel_pipel3d1c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipel3d1c <= 1'b0;
else if (clk_en == 1'b1) sel_pipel3d1c <= distance[3];
// synopsys translate_off
initial
sel_pipel4d1c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipel4d1c <= 1'b0;
else if (clk_en == 1'b1) sel_pipel4d1c <= distance[4];
assign
direction_w = 1'b0,
pad_w = {16{1'b0}},
result = sbit_w[191:160],
sbit_w = {pipe_wl2c, ((({32{(sel_w[3] & (~ direction_w))}} & {sbit_w[119:96], pad_w[7:0]}) | ({32{(sel_w[3] & direction_w)}} & {pad_w[7:0], sbit_w[127:104]})) | ({32{(~ sel_w[3])}} & sbit_w[127:96])), pipe_wl1c, ((({32{(sel_w[1] & (~ direction_w))}} & {sbit_w[61:32], pad_w[1:0]}) | ({32{(sel_w[1] & direction_w)}} & {pad_w[1:0], sbit_w[63:34]})) | ({32{(~ sel_w[1])}} & sbit_w[63:32])), ((({32{(sel_w[0] & (~ direction_w))}} & {sbit_w[30:0], pad_w[0]}) | ({32{(sel_w[0] & direction_w)}} & {pad_w[0], sbit_w[31:1]})) | ({32{(~ sel_w[0])}} & sbit_w[31:0])), data},
sel_w = {sel_pipel4d1c, sel_pipel3d1c, distance[2:0]};
endmodule //int_to_fp_altbarrel_shift_mvf
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" WIDTH=32 WIDTHAD=5 data q
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_3v7
(
data,
q) ;
input [1:0] data;
output [0:0] q;
assign
q = {data[1]};
endmodule //int_to_fp_altpriority_encoder_3v7
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_3e8
(
data,
q,
zero) ;
input [1:0] data;
output [0:0] q;
output zero;
assign
q = {data[1]},
zero = (~ (data[0] | data[1]));
endmodule //int_to_fp_altpriority_encoder_3e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_6v7
(
data,
q) ;
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder12_q;
wire [0:0] wire_altpriority_encoder13_q;
wire wire_altpriority_encoder13_zero;
int_to_fp_altpriority_encoder_3v7 altpriority_encoder12
(
.data(data[1:0]),
.q(wire_altpriority_encoder12_q));
int_to_fp_altpriority_encoder_3e8 altpriority_encoder13
(
.data(data[3:2]),
.q(wire_altpriority_encoder13_q),
.zero(wire_altpriority_encoder13_zero));
assign
q = {(~ wire_altpriority_encoder13_zero), ((wire_altpriority_encoder13_zero & wire_altpriority_encoder12_q) | ((~ wire_altpriority_encoder13_zero) & wire_altpriority_encoder13_q))};
endmodule //int_to_fp_altpriority_encoder_6v7
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_6e8
(
data,
q,
zero) ;
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder14_q;
wire wire_altpriority_encoder14_zero;
wire [0:0] wire_altpriority_encoder15_q;
wire wire_altpriority_encoder15_zero;
int_to_fp_altpriority_encoder_3e8 altpriority_encoder14
(
.data(data[1:0]),
.q(wire_altpriority_encoder14_q),
.zero(wire_altpriority_encoder14_zero));
int_to_fp_altpriority_encoder_3e8 altpriority_encoder15
(
.data(data[3:2]),
.q(wire_altpriority_encoder15_q),
.zero(wire_altpriority_encoder15_zero));
assign
q = {(~ wire_altpriority_encoder15_zero), ((wire_altpriority_encoder15_zero & wire_altpriority_encoder14_q) | ((~ wire_altpriority_encoder15_zero) & wire_altpriority_encoder15_q))},
zero = (wire_altpriority_encoder14_zero & wire_altpriority_encoder15_zero);
endmodule //int_to_fp_altpriority_encoder_6e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_bv7
(
data,
q) ;
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder10_q;
wire [1:0] wire_altpriority_encoder11_q;
wire wire_altpriority_encoder11_zero;
int_to_fp_altpriority_encoder_6v7 altpriority_encoder10
(
.data(data[3:0]),
.q(wire_altpriority_encoder10_q));
int_to_fp_altpriority_encoder_6e8 altpriority_encoder11
(
.data(data[7:4]),
.q(wire_altpriority_encoder11_q),
.zero(wire_altpriority_encoder11_zero));
assign
q = {(~ wire_altpriority_encoder11_zero), (({2{wire_altpriority_encoder11_zero}} & wire_altpriority_encoder10_q) | ({2{(~ wire_altpriority_encoder11_zero)}} & wire_altpriority_encoder11_q))};
endmodule //int_to_fp_altpriority_encoder_bv7
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_be8
(
data,
q,
zero) ;
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder16_q;
wire wire_altpriority_encoder16_zero;
wire [1:0] wire_altpriority_encoder17_q;
wire wire_altpriority_encoder17_zero;
int_to_fp_altpriority_encoder_6e8 altpriority_encoder16
(
.data(data[3:0]),
.q(wire_altpriority_encoder16_q),
.zero(wire_altpriority_encoder16_zero));
int_to_fp_altpriority_encoder_6e8 altpriority_encoder17
(
.data(data[7:4]),
.q(wire_altpriority_encoder17_q),
.zero(wire_altpriority_encoder17_zero));
assign
q = {(~ wire_altpriority_encoder17_zero), (({2{wire_altpriority_encoder17_zero}} & wire_altpriority_encoder16_q) | ({2{(~ wire_altpriority_encoder17_zero)}} & wire_altpriority_encoder17_q))},
zero = (wire_altpriority_encoder16_zero & wire_altpriority_encoder17_zero);
endmodule //int_to_fp_altpriority_encoder_be8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_r08
(
data,
q) ;
input [15:0] data;
output [3:0] q;
wire [2:0] wire_altpriority_encoder8_q;
wire [2:0] wire_altpriority_encoder9_q;
wire wire_altpriority_encoder9_zero;
int_to_fp_altpriority_encoder_bv7 altpriority_encoder8
(
.data(data[7:0]),
.q(wire_altpriority_encoder8_q));
int_to_fp_altpriority_encoder_be8 altpriority_encoder9
(
.data(data[15:8]),
.q(wire_altpriority_encoder9_q),
.zero(wire_altpriority_encoder9_zero));
assign
q = {(~ wire_altpriority_encoder9_zero), (({3{wire_altpriority_encoder9_zero}} & wire_altpriority_encoder8_q) | ({3{(~ wire_altpriority_encoder9_zero)}} & wire_altpriority_encoder9_q))};
endmodule //int_to_fp_altpriority_encoder_r08
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q zero
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_rf8
(
data,
q,
zero) ;
input [15:0] data;
output [3:0] q;
output zero;
wire [2:0] wire_altpriority_encoder18_q;
wire wire_altpriority_encoder18_zero;
wire [2:0] wire_altpriority_encoder19_q;
wire wire_altpriority_encoder19_zero;
int_to_fp_altpriority_encoder_be8 altpriority_encoder18
(
.data(data[7:0]),
.q(wire_altpriority_encoder18_q),
.zero(wire_altpriority_encoder18_zero));
int_to_fp_altpriority_encoder_be8 altpriority_encoder19
(
.data(data[15:8]),
.q(wire_altpriority_encoder19_q),
.zero(wire_altpriority_encoder19_zero));
assign
q = {(~ wire_altpriority_encoder19_zero), (({3{wire_altpriority_encoder19_zero}} & wire_altpriority_encoder18_q) | ({3{(~ wire_altpriority_encoder19_zero)}} & wire_altpriority_encoder19_q))},
zero = (wire_altpriority_encoder18_zero & wire_altpriority_encoder19_zero);
endmodule //int_to_fp_altpriority_encoder_rf8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_qb6
(
data,
q) ;
input [31:0] data;
output [4:0] q;
wire [3:0] wire_altpriority_encoder6_q;
wire [3:0] wire_altpriority_encoder7_q;
wire wire_altpriority_encoder7_zero;
int_to_fp_altpriority_encoder_r08 altpriority_encoder6
(
.data(data[15:0]),
.q(wire_altpriority_encoder6_q));
int_to_fp_altpriority_encoder_rf8 altpriority_encoder7
(
.data(data[31:16]),
.q(wire_altpriority_encoder7_q),
.zero(wire_altpriority_encoder7_zero));
assign
q = {(~ wire_altpriority_encoder7_zero), (({4{wire_altpriority_encoder7_zero}} & wire_altpriority_encoder6_q) | ({4{(~ wire_altpriority_encoder7_zero)}} & wire_altpriority_encoder7_q))};
endmodule //int_to_fp_altpriority_encoder_qb6
//synthesis_resources = lpm_add_sub 2 lpm_compare 1 reg 288
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altfp_convert_bnn
(
clk_en,
clock,
dataa,
result) ;
input clk_en;
input clock;
input [31:0] dataa;
output [63:0] result;
wire [31:0] wire_altbarrel_shift5_result;
wire [4:0] wire_altpriority_encoder2_q;
reg [10:0] exponent_bus_pre_reg;
reg [10:0] exponent_bus_pre_reg2;
reg [10:0] exponent_bus_pre_reg3;
reg [30:0] mag_int_a_reg;
reg [30:0] mag_int_a_reg2;
reg [52:0] mantissa_pre_round_reg;
reg [4:0] priority_encoder_reg;
reg [63:0] result_reg;
reg sign_int_a_reg1;
reg sign_int_a_reg2;
reg sign_int_a_reg3;
reg sign_int_a_reg4;
reg sign_int_a_reg5;
wire [30:0] wire_add_sub1_result;
wire [10:0] wire_add_sub3_result;
wire wire_cmpr4_alb;
wire aclr;
wire [10:0] bias_value_w;
wire [10:0] const_bias_value_add_width_int_w;
wire [10:0] exceptions_value;
wire [10:0] exponent_bus;
wire [10:0] exponent_bus_pre;
wire [10:0] exponent_output_w;
wire [10:0] exponent_rounded;
wire [10:0] exponent_zero_w;
wire [30:0] int_a;
wire [30:0] int_a_2s;
wire [30:0] invert_int_a;
wire [4:0] leading_zeroes;
wire [30:0] mag_int_a;
wire [51:0] mantissa_bus;
wire [52:0] mantissa_pre_round;
wire [52:0] mantissa_rounded;
wire max_neg_value_selector;
wire [10:0] max_neg_value_w;
wire [10:0] minus_leading_zero;
wire [31:0] prio_mag_int_a;
wire [63:0] result_w;
wire [30:0] shifted_mag_int_a;
wire sign_bus;
wire sign_int_a;
wire [5:0] zero_padding_w;
int_to_fp_altbarrel_shift_mvf altbarrel_shift5
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({1'b0, mag_int_a_reg2}),
.distance(leading_zeroes),
.result(wire_altbarrel_shift5_result));
int_to_fp_altpriority_encoder_qb6 altpriority_encoder2
(
.data(prio_mag_int_a),
.q(wire_altpriority_encoder2_q));
// synopsys translate_off
initial
exponent_bus_pre_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg <= 11'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg <= exponent_bus_pre_reg2;
// synopsys translate_off
initial
exponent_bus_pre_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg2 <= 11'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg2 <= exponent_bus_pre_reg3;
// synopsys translate_off
initial
exponent_bus_pre_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg3 <= 11'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg3 <= exponent_bus_pre;
// synopsys translate_off
initial
mag_int_a_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mag_int_a_reg <= 31'b0;
else if (clk_en == 1'b1) mag_int_a_reg <= mag_int_a;
// synopsys translate_off
initial
mag_int_a_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mag_int_a_reg2 <= 31'b0;
else if (clk_en == 1'b1) mag_int_a_reg2 <= mag_int_a_reg;
// synopsys translate_off
initial
mantissa_pre_round_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mantissa_pre_round_reg <= 53'b0;
else if (clk_en == 1'b1) mantissa_pre_round_reg <= mantissa_pre_round;
// synopsys translate_off
initial
priority_encoder_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) priority_encoder_reg <= 5'b0;
else if (clk_en == 1'b1) priority_encoder_reg <= wire_altpriority_encoder2_q;
// synopsys translate_off
initial
result_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) result_reg <= 64'b0;
else if (clk_en == 1'b1) result_reg <= result_w;
// synopsys translate_off
initial
sign_int_a_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg1 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg1 <= sign_int_a;
// synopsys translate_off
initial
sign_int_a_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg2 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg2 <= sign_int_a_reg1;
// synopsys translate_off
initial
sign_int_a_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg3 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg3 <= sign_int_a_reg2;
// synopsys translate_off
initial
sign_int_a_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg4 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg4 <= sign_int_a_reg3;
// synopsys translate_off
initial
sign_int_a_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg5 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg5 <= sign_int_a_reg4;
lpm_add_sub add_sub1
(
.cout(),
.dataa(invert_int_a),
.datab(31'b0000000000000000000000000000001),
.overflow(),
.result(wire_add_sub1_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
add_sub1.lpm_direction = "ADD",
add_sub1.lpm_width = 31,
add_sub1.lpm_type = "lpm_add_sub",
add_sub1.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_add_sub add_sub3
(
.cout(),
.dataa(const_bias_value_add_width_int_w),
.datab(minus_leading_zero),
.overflow(),
.result(wire_add_sub3_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
add_sub3.lpm_direction = "SUB",
add_sub3.lpm_width = 11,
add_sub3.lpm_type = "lpm_add_sub",
add_sub3.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_compare cmpr4
(
.aeb(),
.agb(),
.ageb(),
.alb(wire_cmpr4_alb),
.aleb(),
.aneb(),
.dataa(exponent_output_w),
.datab(bias_value_w)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
cmpr4.lpm_representation = "UNSIGNED",
cmpr4.lpm_width = 11,
cmpr4.lpm_type = "lpm_compare";
assign
aclr = 1'b0,
bias_value_w = 11'b01111111111,
const_bias_value_add_width_int_w = 11'b10000011101,
exceptions_value = (({11{(~ max_neg_value_selector)}} & exponent_zero_w) | ({11{max_neg_value_selector}} & max_neg_value_w)),
exponent_bus = exponent_rounded,
exponent_bus_pre = (({11{(~ wire_cmpr4_alb)}} & exponent_output_w) | ({11{wire_cmpr4_alb}} & exceptions_value)),
exponent_output_w = wire_add_sub3_result,
exponent_rounded = exponent_bus_pre_reg,
exponent_zero_w = {11{1'b0}},
int_a = dataa[30:0],
int_a_2s = wire_add_sub1_result,
invert_int_a = (~ int_a),
leading_zeroes = (~ priority_encoder_reg),
mag_int_a = (({31{(~ sign_int_a)}} & int_a) | ({31{sign_int_a}} & int_a_2s)),
mantissa_bus = mantissa_rounded[51:0],
mantissa_pre_round = {shifted_mag_int_a[30:0], 22'b0000000000000000000000},
mantissa_rounded = mantissa_pre_round_reg,
max_neg_value_selector = (wire_cmpr4_alb & sign_int_a_reg2),
max_neg_value_w = 11'b10000011110,
minus_leading_zero = {zero_padding_w, leading_zeroes},
prio_mag_int_a = {mag_int_a_reg, 1'b1},
result = result_reg,
result_w = {sign_bus, exponent_bus, mantissa_bus},
shifted_mag_int_a = wire_altbarrel_shift5_result[30:0],
sign_bus = sign_int_a_reg5,
sign_int_a = dataa[31],
zero_padding_w = {6{1'b0}};
endmodule //int_to_fp_altfp_convert_bnn
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module int_to_fp (
clk_en,
clock,
dataa,
result);
input clk_en;
input clock;
input [31:0] dataa;
output [63:0] result;
wire [63:0] sub_wire0;
wire [63:0] result = sub_wire0[63:0];
int_to_fp_altfp_convert_bnn int_to_fp_altfp_convert_bnn_component (
.dataa (dataa),
.clk_en (clk_en),
.clock (clock),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_convert"
// Retrieval info: CONSTANT: OPERATION STRING "INT2FLOAT"
// Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
// Retrieval info: CONSTANT: WIDTH_DATA NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_EXP_INPUT NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_EXP_OUTPUT NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_INT NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_MAN_INPUT NUMERIC "23"
// Retrieval info: CONSTANT: WIDTH_MAN_OUTPUT NUMERIC "52"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "64"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT GND "clk_en"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND "clock"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT GND "dataa[31..0]"
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
// Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT GND "result[63..0]"
// Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL int_to_fp.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL int_to_fp.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL int_to_fp.bsf FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL int_to_fp_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL int_to_fp_bb.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL int_to_fp.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL int_to_fp.cmp FALSE TRUE
// Retrieval info: LIB_FILE: lpm
|
/*
In this test a single IOBUF is controlled by switches. There is also one
input (connected to a LED) and one oputput (controlled by a switch) that.
can be used for verification of 3-state I/O.
This test requires a physical jumper to be installed on the Basys3 board.
Depending on which pins are connected we have different truth tables of
LED output w.r.t. switch input.
Truth table. When JC.1 is connected to JC.2:
SW2 SW1 SW0 | LED1 LED0
0 0 0 | 0 0
0 0 1 | 1 1
0 1 0 | x x
0 1 1 | x x
1 0 0 | 0 0
1 0 1 | 1 1
1 1 0 | x x
1 1 1 | x x
Truth table. When JC.3 is connected to JC.2:
SW2 SW1 SW0 | LED1 LED0
0 0 0 | x 0
0 0 1 | x 1
0 1 0 | x 0
0 1 1 | x 0
1 0 0 | x 0
1 0 1 | x 1
1 1 0 | x 1
1 1 1 | x 1
*/
`default_nettype none
// ============================================================================
module top
(
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led,
input wire jc1,
inout wire jc2,
output wire jc3,
input wire jc4 // unused
);
// ============================================================================
// IOBUF (to be swferred)
wire io_i;
wire io_o;
wire io_t;
assign io_o = jc2;
assign jc2 = (io_t == 1'b0) ? io_i : 1'bz;
// ============================================================================
// SW0 controls IOBUF.I
assign io_i = sw[0];
// SW1 controls IOBUF.T
assign io_t = sw[1];
// SW2 controls OBUF.I (JC.3)
assign jc3 = sw[2];
// LED0 swdicates IOBUF.O
assign led[0] = io_o;
// LED1 is connected to JC.1
assign led[1] = jc1;
// Unused IOs - SW->LED passthrough.
assign led[15:2] = {sw[15:3], 1'd0};
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file k7_sfifo_15x128.v when simulating
// the core, k7_sfifo_15x128. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module k7_sfifo_15x128(
clk,
rst,
din,
wr_en,
rd_en,
dout,
full,
empty,
prog_full,
prog_empty
);
input clk;
input rst;
input [127 : 0] din;
input wr_en;
input rd_en;
output [127 : 0] dout;
output full;
output empty;
output prog_full;
output prog_empty;
// synthesis translate_off
FIFO_GENERATOR_V9_3 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(4),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(128),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(128),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("kintex7"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(3),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(1),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(12),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(11),
.C_PROG_FULL_TYPE(1),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(4),
.C_RD_DEPTH(16),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(4),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(4),
.C_WR_DEPTH(16),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(4),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.CLK(clk),
.RST(rst),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.PROG_FULL(prog_full),
.PROG_EMPTY(prog_empty),
.BACKUP(),
.BACKUP_MARKER(),
.SRST(),
.WR_CLK(),
.WR_RST(),
.RD_CLK(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_AW_PROG_FULL(),
.AXI_AW_PROG_EMPTY(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_W_PROG_FULL(),
.AXI_W_PROG_EMPTY(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_B_PROG_FULL(),
.AXI_B_PROG_EMPTY(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_AR_PROG_FULL(),
.AXI_AR_PROG_EMPTY(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXI_R_PROG_FULL(),
.AXI_R_PROG_EMPTY(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW(),
.AXIS_PROG_FULL(),
.AXIS_PROG_EMPTY()
);
// synthesis translate_on
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA core logic
*/
module fpga_core #
(
parameter TARGET = "GENERIC"
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire [3:0] btn,
input wire [3:0] sw,
output wire led0_r,
output wire led0_g,
output wire led0_b,
output wire led1_r,
output wire led1_g,
output wire led1_b,
output wire led2_r,
output wire led2_g,
output wire led2_b,
output wire led3_r,
output wire led3_g,
output wire led3_b,
output wire led4,
output wire led5,
output wire led6,
output wire led7,
/*
* Ethernet: 100BASE-T MII
*/
input wire phy_rx_clk,
input wire [3:0] phy_rxd,
input wire phy_rx_dv,
input wire phy_rx_er,
input wire phy_tx_clk,
output wire [3:0] phy_txd,
output wire phy_tx_en,
input wire phy_col,
input wire phy_crs,
output wire phy_reset_n,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
// AXI between MAC and Ethernet modules
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [7:0] tx_axis_tdata;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [7:0] rx_eth_payload_axis_tdata;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [7:0] tx_eth_payload_axis_tdata;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [7:0] rx_ip_payload_axis_tdata;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [7:0] tx_ip_payload_axis_tdata;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [7:0] rx_udp_payload_axis_tdata;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [7:0] tx_udp_payload_axis_tdata;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [7:0] rx_fifo_udp_payload_axis_tdata;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [7:0] tx_fifo_udp_payload_axis_tdata;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (rst) begin
led_reg <= 0;
end else begin
if (tx_udp_payload_axis_tvalid) begin
if (!valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
valid_last <= 1'b1;
end
if (tx_udp_payload_axis_tlast) begin
valid_last <= 1'b0;
end
end
end
end
//assign led = sw;
assign {led0_g, led1_g, led2_g, led3_g, led4, led5, led6, led7} = led_reg;
assign phy_reset_n = !rst;
assign uart_txd = 0;
eth_mac_mii_fifo #(
.TARGET(TARGET),
.CLOCK_INPUT_STYLE("BUFR"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.rst(rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.mii_rx_clk(phy_rx_clk),
.mii_rxd(phy_rxd),
.mii_rx_dv(phy_rx_dv),
.mii_rx_er(phy_rx_er),
.mii_tx_clk(phy_tx_clk),
.mii_txd(phy_txd),
.mii_tx_en(phy_tx_en),
.mii_tx_er(),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(12)
);
eth_axis_rx
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
`resetall
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ff_dram_sc_bank3.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//////////////////////////////////////////////////////////////////////
// Flop repeater for L2<-> dram controller signals.
// This repeter block has
// 8 row of data flops and 4 rows of ctl/addr flops.
// The 8 data rows are placed in one column ( 39 bits wide )
// the 4 addr/ctl rows are placed in one column ( 13 bits wide )
//////////////////////////////////////////////////////////////////////
module ff_dram_sc_bank3(/*AUTOARG*/
// Outputs
dram_scbuf_data_r2_d1, dram_scbuf_ecc_r2_d1,
scbuf_dram_wr_data_r5_d1, scbuf_dram_data_vld_r5_d1,
scbuf_dram_data_mecc_r5_d1, sctag_dram_rd_req_d1,
sctag_dram_rd_dummy_req_d1, sctag_dram_rd_req_id_d1,
sctag_dram_addr_d1, sctag_dram_wr_req_d1, dram_sctag_rd_ack_d1,
dram_sctag_wr_ack_d1, dram_sctag_chunk_id_r0_d1,
dram_sctag_data_vld_r0_d1, dram_sctag_rd_req_id_r0_d1,
dram_sctag_secc_err_r2_d1, dram_sctag_mecc_err_r2_d1,
dram_sctag_scb_mecc_err_d1, dram_sctag_scb_secc_err_d1, so,
// Inputs
dram_scbuf_data_r2, dram_scbuf_ecc_r2, scbuf_dram_wr_data_r5,
scbuf_dram_data_vld_r5, scbuf_dram_data_mecc_r5,
sctag_dram_rd_req, sctag_dram_rd_dummy_req, sctag_dram_rd_req_id,
sctag_dram_addr, sctag_dram_wr_req, dram_sctag_rd_ack,
dram_sctag_wr_ack, dram_sctag_chunk_id_r0, dram_sctag_data_vld_r0,
dram_sctag_rd_req_id_r0, dram_sctag_secc_err_r2,
dram_sctag_mecc_err_r2, dram_sctag_scb_mecc_err,
dram_sctag_scb_secc_err, rclk, si, se
);
// dram-scbuf TOP
input [127:0] dram_scbuf_data_r2;
input [27:0] dram_scbuf_ecc_r2;
// BOTTOM
output [127:0] dram_scbuf_data_r2_d1;
output [27:0] dram_scbuf_ecc_r2_d1;
// scbuf to dram BOTTOM
input [63:0] scbuf_dram_wr_data_r5;
input scbuf_dram_data_vld_r5;
input scbuf_dram_data_mecc_r5;
// TOP
output [63:0] scbuf_dram_wr_data_r5_d1;
output scbuf_dram_data_vld_r5_d1;
output scbuf_dram_data_mecc_r5_d1;
// sctag_dram-sctag signals INputs
// @ the bottom.
// Outputs @ the top.
input sctag_dram_rd_req;
input sctag_dram_rd_dummy_req;
input [2:0] sctag_dram_rd_req_id;
input [39:5] sctag_dram_addr;
input sctag_dram_wr_req;
//
output sctag_dram_rd_req_d1;
output sctag_dram_rd_dummy_req_d1;
output [2:0] sctag_dram_rd_req_id_d1;
output [39:5] sctag_dram_addr_d1;
output sctag_dram_wr_req_d1;
// dram-sctag signals. Outputs @ bottom
// and Input pins on top.
input dram_sctag_rd_ack;
input dram_sctag_wr_ack;
input [1:0] dram_sctag_chunk_id_r0;
input dram_sctag_data_vld_r0;
input [2:0] dram_sctag_rd_req_id_r0;
input dram_sctag_secc_err_r2 ;
input dram_sctag_mecc_err_r2 ;
input dram_sctag_scb_mecc_err;
input dram_sctag_scb_secc_err;
//
output dram_sctag_rd_ack_d1;
output dram_sctag_wr_ack_d1;
output [1:0] dram_sctag_chunk_id_r0_d1;
output dram_sctag_data_vld_r0_d1;
output [2:0] dram_sctag_rd_req_id_r0_d1;
output dram_sctag_secc_err_r2_d1 ;
output dram_sctag_mecc_err_r2_d1 ;
output dram_sctag_scb_mecc_err_d1;
output dram_sctag_scb_secc_err_d1;
input rclk;
input si, se;
output so;
// dram-scbuf signals. 8 rows of flops.
// Input at the top and output at the bottom.
dff_s #(39) ff_flop_bank0_row_0 (.q({dram_scbuf_data_r2_d1[127],
dram_scbuf_data_r2_d1[123],
dram_scbuf_data_r2_d1[119],
dram_scbuf_data_r2_d1[115],
dram_scbuf_data_r2_d1[111],
dram_scbuf_data_r2_d1[107],
dram_scbuf_data_r2_d1[103],
dram_scbuf_data_r2_d1[99],
dram_scbuf_data_r2_d1[95],
dram_scbuf_data_r2_d1[91],
dram_scbuf_data_r2_d1[87],
dram_scbuf_data_r2_d1[83],
dram_scbuf_data_r2_d1[79],
dram_scbuf_data_r2_d1[75],
dram_scbuf_data_r2_d1[71],
dram_scbuf_data_r2_d1[67],
dram_scbuf_data_r2_d1[63],
dram_scbuf_data_r2_d1[59],
dram_scbuf_data_r2_d1[55],
dram_scbuf_data_r2_d1[51],
dram_scbuf_data_r2_d1[47],
dram_scbuf_data_r2_d1[43],
dram_scbuf_data_r2_d1[39],
dram_scbuf_data_r2_d1[35],
dram_scbuf_data_r2_d1[31],
dram_scbuf_data_r2_d1[27],
dram_scbuf_data_r2_d1[23],
dram_scbuf_data_r2_d1[19],
dram_scbuf_data_r2_d1[15],
dram_scbuf_data_r2_d1[11],
dram_scbuf_data_r2_d1[7],
dram_scbuf_data_r2_d1[3],
dram_scbuf_ecc_r2_d1[27],
dram_scbuf_ecc_r2_d1[23],
dram_scbuf_ecc_r2_d1[19],
dram_scbuf_ecc_r2_d1[15],
dram_scbuf_ecc_r2_d1[11],
dram_scbuf_ecc_r2_d1[7],
dram_scbuf_ecc_r2_d1[3] }),
.din({dram_scbuf_data_r2[127],
dram_scbuf_data_r2[123],
dram_scbuf_data_r2[119],
dram_scbuf_data_r2[115],
dram_scbuf_data_r2[111],
dram_scbuf_data_r2[107],
dram_scbuf_data_r2[103],
dram_scbuf_data_r2[99],
dram_scbuf_data_r2[95],
dram_scbuf_data_r2[91],
dram_scbuf_data_r2[87],
dram_scbuf_data_r2[83],
dram_scbuf_data_r2[79],
dram_scbuf_data_r2[75],
dram_scbuf_data_r2[71],
dram_scbuf_data_r2[67],
dram_scbuf_data_r2[63],
dram_scbuf_data_r2[59],
dram_scbuf_data_r2[55],
dram_scbuf_data_r2[51],
dram_scbuf_data_r2[47],
dram_scbuf_data_r2[43],
dram_scbuf_data_r2[39],
dram_scbuf_data_r2[35],
dram_scbuf_data_r2[31],
dram_scbuf_data_r2[27],
dram_scbuf_data_r2[23],
dram_scbuf_data_r2[19],
dram_scbuf_data_r2[15],
dram_scbuf_data_r2[11],
dram_scbuf_data_r2[7],
dram_scbuf_data_r2[3],
dram_scbuf_ecc_r2[27],
dram_scbuf_ecc_r2[23],
dram_scbuf_ecc_r2[19],
dram_scbuf_ecc_r2[15],
dram_scbuf_ecc_r2[11],
dram_scbuf_ecc_r2[7],
dram_scbuf_ecc_r2[3]}),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(39) ff_flop_bank0_row_1 (.q({dram_scbuf_data_r2_d1[126],
dram_scbuf_data_r2_d1[122],
dram_scbuf_data_r2_d1[118],
dram_scbuf_data_r2_d1[114],
dram_scbuf_data_r2_d1[110],
dram_scbuf_data_r2_d1[106],
dram_scbuf_data_r2_d1[102],
dram_scbuf_data_r2_d1[98],
dram_scbuf_data_r2_d1[94],
dram_scbuf_data_r2_d1[90],
dram_scbuf_data_r2_d1[86],
dram_scbuf_data_r2_d1[82],
dram_scbuf_data_r2_d1[78],
dram_scbuf_data_r2_d1[74],
dram_scbuf_data_r2_d1[70],
dram_scbuf_data_r2_d1[66],
dram_scbuf_data_r2_d1[62],
dram_scbuf_data_r2_d1[58],
dram_scbuf_data_r2_d1[54],
dram_scbuf_data_r2_d1[50],
dram_scbuf_data_r2_d1[46],
dram_scbuf_data_r2_d1[42],
dram_scbuf_data_r2_d1[38],
dram_scbuf_data_r2_d1[34],
dram_scbuf_data_r2_d1[30],
dram_scbuf_data_r2_d1[26],
dram_scbuf_data_r2_d1[22],
dram_scbuf_data_r2_d1[18],
dram_scbuf_data_r2_d1[14],
dram_scbuf_data_r2_d1[10],
dram_scbuf_data_r2_d1[6],
dram_scbuf_data_r2_d1[2],
dram_scbuf_ecc_r2_d1[26],
dram_scbuf_ecc_r2_d1[22],
dram_scbuf_ecc_r2_d1[18],
dram_scbuf_ecc_r2_d1[14],
dram_scbuf_ecc_r2_d1[10],
dram_scbuf_ecc_r2_d1[6],
dram_scbuf_ecc_r2_d1[2] }),
.din({dram_scbuf_data_r2[126],
dram_scbuf_data_r2[122],
dram_scbuf_data_r2[118],
dram_scbuf_data_r2[114],
dram_scbuf_data_r2[110],
dram_scbuf_data_r2[106],
dram_scbuf_data_r2[102],
dram_scbuf_data_r2[98],
dram_scbuf_data_r2[94],
dram_scbuf_data_r2[90],
dram_scbuf_data_r2[86],
dram_scbuf_data_r2[82],
dram_scbuf_data_r2[78],
dram_scbuf_data_r2[74],
dram_scbuf_data_r2[70],
dram_scbuf_data_r2[66],
dram_scbuf_data_r2[62],
dram_scbuf_data_r2[58],
dram_scbuf_data_r2[54],
dram_scbuf_data_r2[50],
dram_scbuf_data_r2[46],
dram_scbuf_data_r2[42],
dram_scbuf_data_r2[38],
dram_scbuf_data_r2[34],
dram_scbuf_data_r2[30],
dram_scbuf_data_r2[26],
dram_scbuf_data_r2[22],
dram_scbuf_data_r2[18],
dram_scbuf_data_r2[14],
dram_scbuf_data_r2[10],
dram_scbuf_data_r2[6],
dram_scbuf_data_r2[2],
dram_scbuf_ecc_r2[26],
dram_scbuf_ecc_r2[22],
dram_scbuf_ecc_r2[18],
dram_scbuf_ecc_r2[14],
dram_scbuf_ecc_r2[10],
dram_scbuf_ecc_r2[6],
dram_scbuf_ecc_r2[2]}),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(39) ff_flop_bank0_row_2 (.q({dram_scbuf_data_r2_d1[125],
dram_scbuf_data_r2_d1[121],
dram_scbuf_data_r2_d1[117],
dram_scbuf_data_r2_d1[113],
dram_scbuf_data_r2_d1[109],
dram_scbuf_data_r2_d1[105],
dram_scbuf_data_r2_d1[101],
dram_scbuf_data_r2_d1[97],
dram_scbuf_data_r2_d1[93],
dram_scbuf_data_r2_d1[89],
dram_scbuf_data_r2_d1[85],
dram_scbuf_data_r2_d1[81],
dram_scbuf_data_r2_d1[77],
dram_scbuf_data_r2_d1[73],
dram_scbuf_data_r2_d1[69],
dram_scbuf_data_r2_d1[65],
dram_scbuf_data_r2_d1[61],
dram_scbuf_data_r2_d1[57],
dram_scbuf_data_r2_d1[53],
dram_scbuf_data_r2_d1[49],
dram_scbuf_data_r2_d1[45],
dram_scbuf_data_r2_d1[41],
dram_scbuf_data_r2_d1[37],
dram_scbuf_data_r2_d1[33],
dram_scbuf_data_r2_d1[29],
dram_scbuf_data_r2_d1[25],
dram_scbuf_data_r2_d1[21],
dram_scbuf_data_r2_d1[17],
dram_scbuf_data_r2_d1[13],
dram_scbuf_data_r2_d1[9],
dram_scbuf_data_r2_d1[5],
dram_scbuf_data_r2_d1[1],
dram_scbuf_ecc_r2_d1[25],
dram_scbuf_ecc_r2_d1[21],
dram_scbuf_ecc_r2_d1[17],
dram_scbuf_ecc_r2_d1[13],
dram_scbuf_ecc_r2_d1[9],
dram_scbuf_ecc_r2_d1[5],
dram_scbuf_ecc_r2_d1[1] }),
.din({dram_scbuf_data_r2[125],
dram_scbuf_data_r2[121],
dram_scbuf_data_r2[117],
dram_scbuf_data_r2[113],
dram_scbuf_data_r2[109],
dram_scbuf_data_r2[105],
dram_scbuf_data_r2[101],
dram_scbuf_data_r2[97],
dram_scbuf_data_r2[93],
dram_scbuf_data_r2[89],
dram_scbuf_data_r2[85],
dram_scbuf_data_r2[81],
dram_scbuf_data_r2[77],
dram_scbuf_data_r2[73],
dram_scbuf_data_r2[69],
dram_scbuf_data_r2[65],
dram_scbuf_data_r2[61],
dram_scbuf_data_r2[57],
dram_scbuf_data_r2[53],
dram_scbuf_data_r2[49],
dram_scbuf_data_r2[45],
dram_scbuf_data_r2[41],
dram_scbuf_data_r2[37],
dram_scbuf_data_r2[33],
dram_scbuf_data_r2[29],
dram_scbuf_data_r2[25],
dram_scbuf_data_r2[21],
dram_scbuf_data_r2[17],
dram_scbuf_data_r2[13],
dram_scbuf_data_r2[9],
dram_scbuf_data_r2[5],
dram_scbuf_data_r2[1],
dram_scbuf_ecc_r2[25],
dram_scbuf_ecc_r2[21],
dram_scbuf_ecc_r2[17],
dram_scbuf_ecc_r2[13],
dram_scbuf_ecc_r2[9],
dram_scbuf_ecc_r2[5],
dram_scbuf_ecc_r2[1]}),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(39) ff_flop_bank0_row_3 (.q({dram_scbuf_data_r2_d1[124],
dram_scbuf_data_r2_d1[120],
dram_scbuf_data_r2_d1[116],
dram_scbuf_data_r2_d1[112],
dram_scbuf_data_r2_d1[108],
dram_scbuf_data_r2_d1[104],
dram_scbuf_data_r2_d1[100],
dram_scbuf_data_r2_d1[96],
dram_scbuf_data_r2_d1[92],
dram_scbuf_data_r2_d1[88],
dram_scbuf_data_r2_d1[84],
dram_scbuf_data_r2_d1[80],
dram_scbuf_data_r2_d1[76],
dram_scbuf_data_r2_d1[72],
dram_scbuf_data_r2_d1[68],
dram_scbuf_data_r2_d1[64],
dram_scbuf_data_r2_d1[60],
dram_scbuf_data_r2_d1[56],
dram_scbuf_data_r2_d1[52],
dram_scbuf_data_r2_d1[48],
dram_scbuf_data_r2_d1[44],
dram_scbuf_data_r2_d1[40],
dram_scbuf_data_r2_d1[36],
dram_scbuf_data_r2_d1[32],
dram_scbuf_data_r2_d1[28],
dram_scbuf_data_r2_d1[24],
dram_scbuf_data_r2_d1[20],
dram_scbuf_data_r2_d1[16],
dram_scbuf_data_r2_d1[12],
dram_scbuf_data_r2_d1[8],
dram_scbuf_data_r2_d1[4],
dram_scbuf_data_r2_d1[0],
dram_scbuf_ecc_r2_d1[24],
dram_scbuf_ecc_r2_d1[20],
dram_scbuf_ecc_r2_d1[16],
dram_scbuf_ecc_r2_d1[12],
dram_scbuf_ecc_r2_d1[8],
dram_scbuf_ecc_r2_d1[4],
dram_scbuf_ecc_r2_d1[0] }),
.din({dram_scbuf_data_r2[124],
dram_scbuf_data_r2[120],
dram_scbuf_data_r2[116],
dram_scbuf_data_r2[112],
dram_scbuf_data_r2[108],
dram_scbuf_data_r2[104],
dram_scbuf_data_r2[100],
dram_scbuf_data_r2[96],
dram_scbuf_data_r2[92],
dram_scbuf_data_r2[88],
dram_scbuf_data_r2[84],
dram_scbuf_data_r2[80],
dram_scbuf_data_r2[76],
dram_scbuf_data_r2[72],
dram_scbuf_data_r2[68],
dram_scbuf_data_r2[64],
dram_scbuf_data_r2[60],
dram_scbuf_data_r2[56],
dram_scbuf_data_r2[52],
dram_scbuf_data_r2[48],
dram_scbuf_data_r2[44],
dram_scbuf_data_r2[40],
dram_scbuf_data_r2[36],
dram_scbuf_data_r2[32],
dram_scbuf_data_r2[28],
dram_scbuf_data_r2[24],
dram_scbuf_data_r2[20],
dram_scbuf_data_r2[16],
dram_scbuf_data_r2[12],
dram_scbuf_data_r2[8],
dram_scbuf_data_r2[4],
dram_scbuf_data_r2[0],
dram_scbuf_ecc_r2[24],
dram_scbuf_ecc_r2[20],
dram_scbuf_ecc_r2[16],
dram_scbuf_ecc_r2[12],
dram_scbuf_ecc_r2[8],
dram_scbuf_ecc_r2[4],
dram_scbuf_ecc_r2[0]}),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(32) ff_bank0_row_4 (.q({scbuf_dram_wr_data_r5_d1[63],
scbuf_dram_wr_data_r5_d1[61],
scbuf_dram_wr_data_r5_d1[59],
scbuf_dram_wr_data_r5_d1[57],
scbuf_dram_wr_data_r5_d1[55],
scbuf_dram_wr_data_r5_d1[53],
scbuf_dram_wr_data_r5_d1[51],
scbuf_dram_wr_data_r5_d1[49],
scbuf_dram_wr_data_r5_d1[47],
scbuf_dram_wr_data_r5_d1[45],
scbuf_dram_wr_data_r5_d1[43],
scbuf_dram_wr_data_r5_d1[41],
scbuf_dram_wr_data_r5_d1[39],
scbuf_dram_wr_data_r5_d1[37],
scbuf_dram_wr_data_r5_d1[35],
scbuf_dram_wr_data_r5_d1[33],
scbuf_dram_wr_data_r5_d1[31],
scbuf_dram_wr_data_r5_d1[29],
scbuf_dram_wr_data_r5_d1[27],
scbuf_dram_wr_data_r5_d1[25],
scbuf_dram_wr_data_r5_d1[23],
scbuf_dram_wr_data_r5_d1[21],
scbuf_dram_wr_data_r5_d1[19],
scbuf_dram_wr_data_r5_d1[17],
scbuf_dram_wr_data_r5_d1[15],
scbuf_dram_wr_data_r5_d1[13],
scbuf_dram_wr_data_r5_d1[11],
scbuf_dram_wr_data_r5_d1[9],
scbuf_dram_wr_data_r5_d1[7],
scbuf_dram_wr_data_r5_d1[5],
scbuf_dram_wr_data_r5_d1[3],
scbuf_dram_wr_data_r5_d1[1]} ),
.din({scbuf_dram_wr_data_r5[63],
scbuf_dram_wr_data_r5[61],
scbuf_dram_wr_data_r5[59],
scbuf_dram_wr_data_r5[57],
scbuf_dram_wr_data_r5[55],
scbuf_dram_wr_data_r5[53],
scbuf_dram_wr_data_r5[51],
scbuf_dram_wr_data_r5[49],
scbuf_dram_wr_data_r5[47],
scbuf_dram_wr_data_r5[45],
scbuf_dram_wr_data_r5[43],
scbuf_dram_wr_data_r5[41],
scbuf_dram_wr_data_r5[39],
scbuf_dram_wr_data_r5[37],
scbuf_dram_wr_data_r5[35],
scbuf_dram_wr_data_r5[33],
scbuf_dram_wr_data_r5[31],
scbuf_dram_wr_data_r5[29],
scbuf_dram_wr_data_r5[27],
scbuf_dram_wr_data_r5[25],
scbuf_dram_wr_data_r5[23],
scbuf_dram_wr_data_r5[21],
scbuf_dram_wr_data_r5[19],
scbuf_dram_wr_data_r5[17],
scbuf_dram_wr_data_r5[15],
scbuf_dram_wr_data_r5[13],
scbuf_dram_wr_data_r5[11],
scbuf_dram_wr_data_r5[9],
scbuf_dram_wr_data_r5[7],
scbuf_dram_wr_data_r5[5],
scbuf_dram_wr_data_r5[3],
scbuf_dram_wr_data_r5[1]} ),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(34) ff_bank0_row_5 (.q({scbuf_dram_wr_data_r5_d1[62],
scbuf_dram_wr_data_r5_d1[60],
scbuf_dram_wr_data_r5_d1[58],
scbuf_dram_wr_data_r5_d1[56],
scbuf_dram_wr_data_r5_d1[54],
scbuf_dram_wr_data_r5_d1[52],
scbuf_dram_wr_data_r5_d1[50],
scbuf_dram_wr_data_r5_d1[48],
scbuf_dram_wr_data_r5_d1[46],
scbuf_dram_wr_data_r5_d1[44],
scbuf_dram_wr_data_r5_d1[42],
scbuf_dram_wr_data_r5_d1[40],
scbuf_dram_wr_data_r5_d1[38],
scbuf_dram_wr_data_r5_d1[36],
scbuf_dram_wr_data_r5_d1[34],
scbuf_dram_wr_data_r5_d1[32],
scbuf_dram_wr_data_r5_d1[30],
scbuf_dram_wr_data_r5_d1[28],
scbuf_dram_wr_data_r5_d1[26],
scbuf_dram_wr_data_r5_d1[24],
scbuf_dram_wr_data_r5_d1[22],
scbuf_dram_wr_data_r5_d1[20],
scbuf_dram_wr_data_r5_d1[18],
scbuf_dram_wr_data_r5_d1[16],
scbuf_dram_wr_data_r5_d1[14],
scbuf_dram_wr_data_r5_d1[12],
scbuf_dram_wr_data_r5_d1[10],
scbuf_dram_wr_data_r5_d1[8],
scbuf_dram_wr_data_r5_d1[6],
scbuf_dram_wr_data_r5_d1[4],
scbuf_dram_wr_data_r5_d1[2],
scbuf_dram_wr_data_r5_d1[0],
scbuf_dram_data_mecc_r5_d1,
scbuf_dram_data_vld_r5_d1
} ),
.din({scbuf_dram_wr_data_r5[62],
scbuf_dram_wr_data_r5[60],
scbuf_dram_wr_data_r5[58],
scbuf_dram_wr_data_r5[56],
scbuf_dram_wr_data_r5[54],
scbuf_dram_wr_data_r5[52],
scbuf_dram_wr_data_r5[50],
scbuf_dram_wr_data_r5[48],
scbuf_dram_wr_data_r5[46],
scbuf_dram_wr_data_r5[44],
scbuf_dram_wr_data_r5[42],
scbuf_dram_wr_data_r5[40],
scbuf_dram_wr_data_r5[38],
scbuf_dram_wr_data_r5[36],
scbuf_dram_wr_data_r5[34],
scbuf_dram_wr_data_r5[32],
scbuf_dram_wr_data_r5[30],
scbuf_dram_wr_data_r5[28],
scbuf_dram_wr_data_r5[26],
scbuf_dram_wr_data_r5[24],
scbuf_dram_wr_data_r5[22],
scbuf_dram_wr_data_r5[20],
scbuf_dram_wr_data_r5[18],
scbuf_dram_wr_data_r5[16],
scbuf_dram_wr_data_r5[14],
scbuf_dram_wr_data_r5[12],
scbuf_dram_wr_data_r5[10],
scbuf_dram_wr_data_r5[8],
scbuf_dram_wr_data_r5[6],
scbuf_dram_wr_data_r5[4],
scbuf_dram_wr_data_r5[2],
scbuf_dram_wr_data_r5[0],
scbuf_dram_data_mecc_r5,
scbuf_dram_data_vld_r5 }),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(41) ff_flop_bank0_col1_row012 (.q({sctag_dram_addr_d1[39:5],
sctag_dram_rd_req_id_d1[2:0],
sctag_dram_wr_req_d1,
sctag_dram_rd_dummy_req_d1,
sctag_dram_rd_req_d1}),
.din({sctag_dram_addr[39:5],
sctag_dram_rd_req_id[2:0],
sctag_dram_wr_req,
sctag_dram_rd_dummy_req,
sctag_dram_rd_req}),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(12) ff_flop_bank0_col1_row3 (.q({dram_sctag_rd_ack_d1,
dram_sctag_wr_ack_d1,
dram_sctag_chunk_id_r0_d1[1:0],
dram_sctag_data_vld_r0_d1,
dram_sctag_rd_req_id_r0_d1[2:0],
dram_sctag_secc_err_r2_d1,
dram_sctag_mecc_err_r2_d1,
dram_sctag_scb_mecc_err_d1,
dram_sctag_scb_secc_err_d1}),
.din({dram_sctag_rd_ack,
dram_sctag_wr_ack,
dram_sctag_chunk_id_r0[1:0],
dram_sctag_data_vld_r0,
dram_sctag_rd_req_id_r0[2:0],
dram_sctag_secc_err_r2,
dram_sctag_mecc_err_r2,
dram_sctag_scb_mecc_err,
dram_sctag_scb_secc_err}),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * CNRS-Ecole Polytechnique-INRIA Futurs-Universite Paris Sud *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(*i $Id$ i*)
(** * Int31 numbers defines indeed a cyclic structure : Z/(2^31)Z *)
(**
Author: Arnaud Spiwack (+ Pierre Letouzey)
*)
Require Import List.
Require Import Min.
Require Export Int31.
Require Import Znumtheory.
Require Import Zgcd_alt.
Require Import Zpow_facts.
Require Import BigNumPrelude.
Require Import CyclicAxioms.
Require Import ROmega.
Open Scope nat_scope.
Open Scope int31_scope.
Section Basics.
(** * Basic results about [iszero], [shiftl], [shiftr] *)
Lemma iszero_eq0 : forall x, iszero x = true -> x=0.
Proof.
destruct x; simpl; intros.
repeat
match goal with H:(if ?d then _ else _) = true |- _ =>
destruct d; try discriminate
end.
reflexivity.
Qed.
Lemma iszero_not_eq0 : forall x, iszero x = false -> x<>0.
Proof.
intros x H Eq; rewrite Eq in H; simpl in *; discriminate.
Qed.
Lemma sneakl_shiftr : forall x,
x = sneakl (firstr x) (shiftr x).
Proof.
destruct x; simpl; auto.
Qed.
Lemma sneakr_shiftl : forall x,
x = sneakr (firstl x) (shiftl x).
Proof.
destruct x; simpl; auto.
Qed.
Lemma twice_zero : forall x,
twice x = 0 <-> twice_plus_one x = 1.
Proof.
destruct x; simpl in *; split;
intro H; injection H; intros; subst; auto.
Qed.
Lemma twice_or_twice_plus_one : forall x,
x = twice (shiftr x) \/ x = twice_plus_one (shiftr x).
Proof.
intros; case_eq (firstr x); intros.
destruct x; simpl in *; rewrite H; auto.
destruct x; simpl in *; rewrite H; auto.
Qed.
(** * Iterated shift to the right *)
Definition nshiftr n x := iter_nat n _ shiftr x.
Lemma nshiftr_S :
forall n x, nshiftr (S n) x = shiftr (nshiftr n x).
Proof.
reflexivity.
Qed.
Lemma nshiftr_S_tail :
forall n x, nshiftr (S n) x = nshiftr n (shiftr x).
Proof.
induction n; simpl; auto.
intros; rewrite nshiftr_S, IHn, nshiftr_S; auto.
Qed.
Lemma nshiftr_n_0 : forall n, nshiftr n 0 = 0.
Proof.
induction n; simpl; auto.
rewrite nshiftr_S, IHn; auto.
Qed.
Lemma nshiftr_size : forall x, nshiftr size x = 0.
Proof.
destruct x; simpl; auto.
Qed.
Lemma nshiftr_above_size : forall k x, size<=k ->
nshiftr k x = 0.
Proof.
intros.
replace k with ((k-size)+size)%nat by omega.
induction (k-size)%nat; auto.
rewrite nshiftr_size; auto.
simpl; rewrite nshiftr_S, IHn; auto.
Qed.
(** * Iterated shift to the left *)
Definition nshiftl n x := iter_nat n _ shiftl x.
Lemma nshiftl_S :
forall n x, nshiftl (S n) x = shiftl (nshiftl n x).
Proof.
reflexivity.
Qed.
Lemma nshiftl_S_tail :
forall n x, nshiftl (S n) x = nshiftl n (shiftl x).
Proof.
induction n; simpl; auto.
intros; rewrite nshiftl_S, IHn, nshiftl_S; auto.
Qed.
Lemma nshiftl_n_0 : forall n, nshiftl n 0 = 0.
Proof.
induction n; simpl; auto.
rewrite nshiftl_S, IHn; auto.
Qed.
Lemma nshiftl_size : forall x, nshiftl size x = 0.
Proof.
destruct x; simpl; auto.
Qed.
Lemma nshiftl_above_size : forall k x, size<=k ->
nshiftl k x = 0.
Proof.
intros.
replace k with ((k-size)+size)%nat by omega.
induction (k-size)%nat; auto.
rewrite nshiftl_size; auto.
simpl; rewrite nshiftl_S, IHn; auto.
Qed.
Lemma firstr_firstl :
forall x, firstr x = firstl (nshiftl (pred size) x).
Proof.
destruct x; simpl; auto.
Qed.
Lemma firstl_firstr :
forall x, firstl x = firstr (nshiftr (pred size) x).
Proof.
destruct x; simpl; auto.
Qed.
(** More advanced results about [nshiftr] *)
Lemma nshiftr_predsize_0_firstl : forall x,
nshiftr (pred size) x = 0 -> firstl x = D0.
Proof.
destruct x; compute; intros H; injection H; intros; subst; auto.
Qed.
Lemma nshiftr_0_propagates : forall n p x, n <= p ->
nshiftr n x = 0 -> nshiftr p x = 0.
Proof.
intros.
replace p with ((p-n)+n)%nat by omega.
induction (p-n)%nat.
simpl; auto.
simpl; rewrite nshiftr_S; rewrite IHn0; auto.
Qed.
Lemma nshiftr_0_firstl : forall n x, n < size ->
nshiftr n x = 0 -> firstl x = D0.
Proof.
intros.
apply nshiftr_predsize_0_firstl.
apply nshiftr_0_propagates with n; auto; omega.
Qed.
(** * Some induction principles over [int31] *)
(** Not used for the moment. Are they really useful ? *)
Lemma int31_ind_sneakl : forall P : int31->Prop,
P 0 ->
(forall x d, P x -> P (sneakl d x)) ->
forall x, P x.
Proof.
intros.
assert (forall n, n<=size -> P (nshiftr (size - n) x)).
induction n; intros.
rewrite nshiftr_size; auto.
rewrite sneakl_shiftr.
apply H0.
change (P (nshiftr (S (size - S n)) x)).
replace (S (size - S n))%nat with (size - n)%nat by omega.
apply IHn; omega.
change x with (nshiftr (size-size) x); auto.
Qed.
Lemma int31_ind_twice : forall P : int31->Prop,
P 0 ->
(forall x, P x -> P (twice x)) ->
(forall x, P x -> P (twice_plus_one x)) ->
forall x, P x.
Proof.
induction x using int31_ind_sneakl; auto.
destruct d; auto.
Qed.
(** * Some generic results about [recr] *)
Section Recr.
(** [recr] satisfies the fixpoint equation used for its definition. *)
Variable (A:Type)(case0:A)(caserec:digits->int31->A->A).
Lemma recr_aux_eqn : forall n x, iszero x = false ->
recr_aux (S n) A case0 caserec x =
caserec (firstr x) (shiftr x) (recr_aux n A case0 caserec (shiftr x)).
Proof.
intros; simpl; rewrite H; auto.
Qed.
Lemma recr_aux_converges :
forall n p x, n <= size -> n <= p ->
recr_aux n A case0 caserec (nshiftr (size - n) x) =
recr_aux p A case0 caserec (nshiftr (size - n) x).
Proof.
induction n.
simpl; intros.
rewrite nshiftr_size; destruct p; simpl; auto.
intros.
destruct p.
inversion H0.
unfold recr_aux; fold recr_aux.
destruct (iszero (nshiftr (size - S n) x)); auto.
f_equal.
change (shiftr (nshiftr (size - S n) x)) with (nshiftr (S (size - S n)) x).
replace (S (size - S n))%nat with (size - n)%nat by omega.
apply IHn; auto with arith.
Qed.
Lemma recr_eqn : forall x, iszero x = false ->
recr A case0 caserec x =
caserec (firstr x) (shiftr x) (recr A case0 caserec (shiftr x)).
Proof.
intros.
unfold recr.
change x with (nshiftr (size - size) x).
rewrite (recr_aux_converges size (S size)); auto with arith.
rewrite recr_aux_eqn; auto.
Qed.
(** [recr] is usually equivalent to a variant [recrbis]
written without [iszero] check. *)
Fixpoint recrbis_aux (n:nat)(A:Type)(case0:A)(caserec:digits->int31->A->A)
(i:int31) : A :=
match n with
| O => case0
| S next =>
let si := shiftr i in
caserec (firstr i) si (recrbis_aux next A case0 caserec si)
end.
Definition recrbis := recrbis_aux size.
Hypothesis case0_caserec : caserec D0 0 case0 = case0.
Lemma recrbis_aux_equiv : forall n x,
recrbis_aux n A case0 caserec x = recr_aux n A case0 caserec x.
Proof.
induction n; simpl; auto; intros.
case_eq (iszero x); intros; [ | f_equal; auto ].
rewrite (iszero_eq0 _ H); simpl; auto.
replace (recrbis_aux n A case0 caserec 0) with case0; auto.
clear H IHn; induction n; simpl; congruence.
Qed.
Lemma recrbis_equiv : forall x,
recrbis A case0 caserec x = recr A case0 caserec x.
Proof.
intros; apply recrbis_aux_equiv; auto.
Qed.
End Recr.
(** * Incrementation *)
Section Incr.
(** Variant of [incr] via [recrbis] *)
Let Incr (b : digits) (si rec : int31) :=
match b with
| D0 => sneakl D1 si
| D1 => sneakl D0 rec
end.
Definition incrbis_aux n x := recrbis_aux n _ In Incr x.
Lemma incrbis_aux_equiv : forall x, incrbis_aux size x = incr x.
Proof.
unfold incr, recr, incrbis_aux; fold Incr; intros.
apply recrbis_aux_equiv; auto.
Qed.
(** Recursive equations satisfied by [incr] *)
Lemma incr_eqn1 :
forall x, firstr x = D0 -> incr x = twice_plus_one (shiftr x).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0); simpl; auto.
unfold incr; rewrite recr_eqn; fold incr; auto.
rewrite H; auto.
Qed.
Lemma incr_eqn2 :
forall x, firstr x = D1 -> incr x = twice (incr (shiftr x)).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0) in H; simpl in H; discriminate.
unfold incr; rewrite recr_eqn; fold incr; auto.
rewrite H; auto.
Qed.
Lemma incr_twice : forall x, incr (twice x) = twice_plus_one x.
Proof.
intros.
rewrite incr_eqn1; destruct x; simpl; auto.
Qed.
Lemma incr_twice_plus_one_firstl :
forall x, firstl x = D0 -> incr (twice_plus_one x) = twice (incr x).
Proof.
intros.
rewrite incr_eqn2; [ | destruct x; simpl; auto ].
f_equal; f_equal.
destruct x; simpl in *; rewrite H; auto.
Qed.
(** The previous result is actually true even without the
constraint on [firstl], but this is harder to prove
(see later). *)
End Incr.
(** * Conversion to [Z] : the [phi] function *)
Section Phi.
(** Variant of [phi] via [recrbis] *)
Let Phi := fun b (_:int31) =>
match b with D0 => Zdouble | D1 => Zdouble_plus_one end.
Definition phibis_aux n x := recrbis_aux n _ Z0 Phi x.
Lemma phibis_aux_equiv : forall x, phibis_aux size x = phi x.
Proof.
unfold phi, recr, phibis_aux; fold Phi; intros.
apply recrbis_aux_equiv; auto.
Qed.
(** Recursive equations satisfied by [phi] *)
Lemma phi_eqn1 : forall x, firstr x = D0 ->
phi x = Zdouble (phi (shiftr x)).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0); simpl; auto.
intros; unfold phi; rewrite recr_eqn; fold phi; auto.
rewrite H; auto.
Qed.
Lemma phi_eqn2 : forall x, firstr x = D1 ->
phi x = Zdouble_plus_one (phi (shiftr x)).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0) in H; simpl in H; discriminate.
intros; unfold phi; rewrite recr_eqn; fold phi; auto.
rewrite H; auto.
Qed.
Lemma phi_twice_firstl : forall x, firstl x = D0 ->
phi (twice x) = Zdouble (phi x).
Proof.
intros.
rewrite phi_eqn1; auto; [ | destruct x; auto ].
f_equal; f_equal.
destruct x; simpl in *; rewrite H; auto.
Qed.
Lemma phi_twice_plus_one_firstl : forall x, firstl x = D0 ->
phi (twice_plus_one x) = Zdouble_plus_one (phi x).
Proof.
intros.
rewrite phi_eqn2; auto; [ | destruct x; auto ].
f_equal; f_equal.
destruct x; simpl in *; rewrite H; auto.
Qed.
End Phi.
(** [phi x] is positive and lower than [2^31] *)
Lemma phibis_aux_pos : forall n x, (0 <= phibis_aux n x)%Z.
Proof.
induction n.
simpl; unfold phibis_aux; simpl; auto with zarith.
intros.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux n (shiftr x)).
destruct (firstr x).
specialize IHn with (shiftr x); rewrite Zdouble_mult; omega.
specialize IHn with (shiftr x); rewrite Zdouble_plus_one_mult; omega.
Qed.
Lemma phibis_aux_bounded :
forall n x, n <= size ->
(phibis_aux n (nshiftr (size-n) x) < 2 ^ (Z_of_nat n))%Z.
Proof.
induction n.
simpl; unfold phibis_aux; simpl; auto with zarith.
intros.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux n (shiftr (nshiftr (size - S n) x))).
assert (shiftr (nshiftr (size - S n) x) = nshiftr (size-n) x).
replace (size - n)%nat with (S (size - (S n))) by omega.
simpl; auto.
rewrite H0.
assert (H1 : n <= size) by omega.
specialize (IHn x H1).
set (y:=phibis_aux n (nshiftr (size - n) x)) in *.
rewrite inj_S, Zpower_Zsucc; auto with zarith.
case_eq (firstr (nshiftr (size - S n) x)); intros.
rewrite Zdouble_mult; auto with zarith.
rewrite Zdouble_plus_one_mult; auto with zarith.
Qed.
Lemma phi_bounded : forall x, (0 <= phi x < 2 ^ (Z_of_nat size))%Z.
Proof.
intros.
rewrite <- phibis_aux_equiv.
split.
apply phibis_aux_pos.
change x with (nshiftr (size-size) x).
apply phibis_aux_bounded; auto.
Qed.
Lemma phibis_aux_lowerbound :
forall n x, firstr (nshiftr n x) = D1 ->
(2 ^ Z_of_nat n <= phibis_aux (S n) x)%Z.
Proof.
induction n.
intros.
unfold nshiftr in H; simpl in *.
unfold phibis_aux, recrbis_aux.
rewrite H, Zdouble_plus_one_mult; omega.
intros.
remember (S n) as m.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux m (shiftr x)).
subst m.
rewrite inj_S, Zpower_Zsucc; auto with zarith.
assert (2^(Z_of_nat n) <= phibis_aux (S n) (shiftr x))%Z.
apply IHn.
rewrite <- nshiftr_S_tail; auto.
destruct (firstr x).
change (Zdouble (phibis_aux (S n) (shiftr x))) with
(2*(phibis_aux (S n) (shiftr x)))%Z.
omega.
rewrite Zdouble_plus_one_mult; omega.
Qed.
Lemma phi_lowerbound :
forall x, firstl x = D1 -> (2^(Z_of_nat (pred size)) <= phi x)%Z.
Proof.
intros.
generalize (phibis_aux_lowerbound (pred size) x).
rewrite <- firstl_firstr.
change (S (pred size)) with size; auto.
rewrite phibis_aux_equiv; auto.
Qed.
(** * Equivalence modulo [2^n] *)
Section EqShiftL.
(** After killing [n] bits at the left, are the numbers equal ?*)
Definition EqShiftL n x y :=
nshiftl n x = nshiftl n y.
Lemma EqShiftL_zero : forall x y, EqShiftL O x y <-> x = y.
Proof.
unfold EqShiftL; intros; unfold nshiftl; simpl; split; auto.
Qed.
Lemma EqShiftL_size : forall k x y, size<=k -> EqShiftL k x y.
Proof.
red; intros; rewrite 2 nshiftl_above_size; auto.
Qed.
Lemma EqShiftL_le : forall k k' x y, k <= k' ->
EqShiftL k x y -> EqShiftL k' x y.
Proof.
unfold EqShiftL; intros.
replace k' with ((k'-k)+k)%nat by omega.
remember (k'-k)%nat as n.
clear Heqn H k'.
induction n; simpl; auto.
rewrite 2 nshiftl_S; f_equal; auto.
Qed.
Lemma EqShiftL_firstr : forall k x y, k < size ->
EqShiftL k x y -> firstr x = firstr y.
Proof.
intros.
rewrite 2 firstr_firstl.
f_equal.
apply EqShiftL_le with k; auto.
unfold size.
auto with arith.
Qed.
Lemma EqShiftL_twice : forall k x y,
EqShiftL k (twice x) (twice y) <-> EqShiftL (S k) x y.
Proof.
intros; unfold EqShiftL.
rewrite 2 nshiftl_S_tail; split; auto.
Qed.
(** * From int31 to list of digits. *)
(** Lower (=rightmost) bits comes first. *)
Definition i2l := recrbis _ nil (fun d _ rec => d::rec).
Lemma i2l_length : forall x, length (i2l x) = size.
Proof.
intros; reflexivity.
Qed.
Fixpoint lshiftl l x :=
match l with
| nil => x
| d::l => sneakl d (lshiftl l x)
end.
Definition l2i l := lshiftl l On.
Lemma l2i_i2l : forall x, l2i (i2l x) = x.
Proof.
destruct x; compute; auto.
Qed.
Lemma i2l_sneakr : forall x d,
i2l (sneakr d x) = tail (i2l x) ++ d::nil.
Proof.
destruct x; compute; auto.
Qed.
Lemma i2l_sneakl : forall x d,
i2l (sneakl d x) = d :: removelast (i2l x).
Proof.
destruct x; compute; auto.
Qed.
Lemma i2l_l2i : forall l, length l = size ->
i2l (l2i l) = l.
Proof.
repeat (destruct l as [ |? l]; [intros; discriminate | ]).
destruct l; [ | intros; discriminate].
intros _; compute; auto.
Qed.
Fixpoint cstlist (A:Type)(a:A) n :=
match n with
| O => nil
| S n => a::cstlist _ a n
end.
Lemma i2l_nshiftl : forall n x, n<=size ->
i2l (nshiftl n x) = cstlist _ D0 n ++ firstn (size-n) (i2l x).
Proof.
induction n.
intros.
assert (firstn (size-0) (i2l x) = i2l x).
rewrite <- minus_n_O, <- (i2l_length x).
induction (i2l x); simpl; f_equal; auto.
rewrite H0; clear H0.
reflexivity.
intros.
rewrite nshiftl_S.
unfold shiftl; rewrite i2l_sneakl.
simpl cstlist.
rewrite <- app_comm_cons; f_equal.
rewrite IHn; [ | omega].
rewrite removelast_app.
f_equal.
replace (size-n)%nat with (S (size - S n))%nat by omega.
rewrite removelast_firstn; auto.
rewrite i2l_length; omega.
generalize (firstn_length (size-n) (i2l x)).
rewrite i2l_length.
intros H0 H1; rewrite H1 in H0.
rewrite min_l in H0 by omega.
simpl length in H0.
omega.
Qed.
(** [i2l] can be used to define a relation equivalent to [EqShiftL] *)
Lemma EqShiftL_i2l : forall k x y,
EqShiftL k x y <-> firstn (size-k) (i2l x) = firstn (size-k) (i2l y).
Proof.
intros.
destruct (le_lt_dec size k).
split; intros.
replace (size-k)%nat with O by omega.
unfold firstn; auto.
apply EqShiftL_size; auto.
unfold EqShiftL.
assert (k <= size) by omega.
split; intros.
assert (i2l (nshiftl k x) = i2l (nshiftl k y)) by (f_equal; auto).
rewrite 2 i2l_nshiftl in H1; auto.
eapply app_inv_head; eauto.
assert (i2l (nshiftl k x) = i2l (nshiftl k y)).
rewrite 2 i2l_nshiftl; auto.
f_equal; auto.
rewrite <- (l2i_i2l (nshiftl k x)), <- (l2i_i2l (nshiftl k y)).
f_equal; auto.
Qed.
(** This equivalence allows to prove easily the following delicate
result *)
Lemma EqShiftL_twice_plus_one : forall k x y,
EqShiftL k (twice_plus_one x) (twice_plus_one y) <-> EqShiftL (S k) x y.
Proof.
intros.
destruct (le_lt_dec size k).
split; intros; apply EqShiftL_size; auto.
rewrite 2 EqShiftL_i2l.
unfold twice_plus_one.
rewrite 2 i2l_sneakl.
replace (size-k)%nat with (S (size - S k))%nat by omega.
remember (size - S k)%nat as n.
remember (i2l x) as lx.
remember (i2l y) as ly.
simpl.
rewrite 2 firstn_removelast.
split; intros.
injection H; auto.
f_equal; auto.
subst ly n; rewrite i2l_length; omega.
subst lx n; rewrite i2l_length; omega.
Qed.
Lemma EqShiftL_shiftr : forall k x y, EqShiftL k x y ->
EqShiftL (S k) (shiftr x) (shiftr y).
Proof.
intros.
destruct (le_lt_dec size (S k)).
apply EqShiftL_size; auto.
case_eq (firstr x); intros.
rewrite <- EqShiftL_twice.
unfold twice; rewrite <- H0.
rewrite <- sneakl_shiftr.
rewrite (EqShiftL_firstr k x y); auto.
rewrite <- sneakl_shiftr; auto.
omega.
rewrite <- EqShiftL_twice_plus_one.
unfold twice_plus_one; rewrite <- H0.
rewrite <- sneakl_shiftr.
rewrite (EqShiftL_firstr k x y); auto.
rewrite <- sneakl_shiftr; auto.
omega.
Qed.
Lemma EqShiftL_incrbis : forall n k x y, n<=size ->
(n+k=S size)%nat ->
EqShiftL k x y ->
EqShiftL k (incrbis_aux n x) (incrbis_aux n y).
Proof.
induction n; simpl; intros.
red; auto.
destruct (eq_nat_dec k size).
subst k; apply EqShiftL_size; auto.
unfold incrbis_aux; simpl;
fold (incrbis_aux n (shiftr x)); fold (incrbis_aux n (shiftr y)).
rewrite (EqShiftL_firstr k x y); auto; try omega.
case_eq (firstr y); intros.
rewrite EqShiftL_twice_plus_one.
apply EqShiftL_shiftr; auto.
rewrite EqShiftL_twice.
apply IHn; try omega.
apply EqShiftL_shiftr; auto.
Qed.
Lemma EqShiftL_incr : forall x y,
EqShiftL 1 x y -> EqShiftL 1 (incr x) (incr y).
Proof.
intros.
rewrite <- 2 incrbis_aux_equiv.
apply EqShiftL_incrbis; auto.
Qed.
End EqShiftL.
(** * More equations about [incr] *)
Lemma incr_twice_plus_one :
forall x, incr (twice_plus_one x) = twice (incr x).
Proof.
intros.
rewrite incr_eqn2; [ | destruct x; simpl; auto].
apply EqShiftL_incr.
red; destruct x; simpl; auto.
Qed.
Lemma incr_firstr : forall x, firstr (incr x) <> firstr x.
Proof.
intros.
case_eq (firstr x); intros.
rewrite incr_eqn1; auto.
destruct (shiftr x); simpl; discriminate.
rewrite incr_eqn2; auto.
destruct (incr (shiftr x)); simpl; discriminate.
Qed.
Lemma incr_inv : forall x y,
incr x = twice_plus_one y -> x = twice y.
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0) in *; simpl in *.
change (incr 0) with 1 in H.
symmetry; rewrite twice_zero; auto.
case_eq (firstr x); intros.
rewrite incr_eqn1 in H; auto.
clear H0; destruct x; destruct y; simpl in *.
injection H; intros; subst; auto.
elim (incr_firstr x).
rewrite H1, H; destruct y; simpl; auto.
Qed.
(** * Conversion from [Z] : the [phi_inv] function *)
(** First, recursive equations *)
Lemma phi_inv_double_plus_one : forall z,
phi_inv (Zdouble_plus_one z) = twice_plus_one (phi_inv z).
Proof.
destruct z; simpl; auto.
induction p; simpl.
rewrite 2 incr_twice; auto.
rewrite incr_twice, incr_twice_plus_one.
f_equal.
apply incr_inv; auto.
auto.
Qed.
Lemma phi_inv_double : forall z,
phi_inv (Zdouble z) = twice (phi_inv z).
Proof.
destruct z; simpl; auto.
rewrite incr_twice_plus_one; auto.
Qed.
Lemma phi_inv_incr : forall z,
phi_inv (Zsucc z) = incr (phi_inv z).
Proof.
destruct z.
simpl; auto.
simpl; auto.
induction p; simpl; auto.
rewrite Pplus_one_succ_r, IHp, incr_twice_plus_one; auto.
rewrite incr_twice; auto.
simpl; auto.
destruct p; simpl; auto.
rewrite incr_twice; auto.
f_equal.
rewrite incr_twice_plus_one; auto.
induction p; simpl; auto.
rewrite incr_twice; auto.
f_equal.
rewrite incr_twice_plus_one; auto.
Qed.
(** [phi_inv o inv], the always-exact and easy-to-prove trip :
from int31 to Z and then back to int31. *)
Lemma phi_inv_phi_aux :
forall n x, n <= size ->
phi_inv (phibis_aux n (nshiftr (size-n) x)) =
nshiftr (size-n) x.
Proof.
induction n.
intros; simpl.
rewrite nshiftr_size; auto.
intros.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux n (shiftr (nshiftr (size-S n) x))).
assert (shiftr (nshiftr (size - S n) x) = nshiftr (size-n) x).
replace (size - n)%nat with (S (size - (S n))); auto; omega.
rewrite H0.
case_eq (firstr (nshiftr (size - S n) x)); intros.
rewrite phi_inv_double.
rewrite IHn by omega.
rewrite <- H0.
remember (nshiftr (size - S n) x) as y.
destruct y; simpl in H1; rewrite H1; auto.
rewrite phi_inv_double_plus_one.
rewrite IHn by omega.
rewrite <- H0.
remember (nshiftr (size - S n) x) as y.
destruct y; simpl in H1; rewrite H1; auto.
Qed.
Lemma phi_inv_phi : forall x, phi_inv (phi x) = x.
Proof.
intros.
rewrite <- phibis_aux_equiv.
replace x with (nshiftr (size - size) x) by auto.
apply phi_inv_phi_aux; auto.
Qed.
(** The other composition [phi o phi_inv] is harder to prove correct.
In particular, an overflow can happen, so a modulo is needed.
For the moment, we proceed via several steps, the first one
being a detour to [positive_to_in31]. *)
(** * [positive_to_int31] *)
(** A variant of [p2i] with [twice] and [twice_plus_one] instead of
[2*i] and [2*i+1] *)
Fixpoint p2ibis n p : (N*int31)%type :=
match n with
| O => (Npos p, On)
| S n => match p with
| xO p => let (r,i) := p2ibis n p in (r, twice i)
| xI p => let (r,i) := p2ibis n p in (r, twice_plus_one i)
| xH => (N0, In)
end
end.
Lemma p2ibis_bounded : forall n p,
nshiftr n (snd (p2ibis n p)) = 0.
Proof.
induction n.
simpl; intros; auto.
simpl; intros.
destruct p; simpl.
specialize IHn with p.
destruct (p2ibis n p); simpl in *.
rewrite nshiftr_S_tail.
destruct (le_lt_dec size n).
rewrite nshiftr_above_size; auto.
assert (H:=nshiftr_0_firstl _ _ l IHn).
replace (shiftr (twice_plus_one i)) with i; auto.
destruct i; simpl in *; rewrite H; auto.
specialize IHn with p.
destruct (p2ibis n p); simpl in *.
rewrite nshiftr_S_tail.
destruct (le_lt_dec size n).
rewrite nshiftr_above_size; auto.
assert (H:=nshiftr_0_firstl _ _ l IHn).
replace (shiftr (twice i)) with i; auto.
destruct i; simpl in *; rewrite H; auto.
rewrite nshiftr_S_tail; auto.
replace (shiftr In) with 0; auto.
apply nshiftr_n_0.
Qed.
Lemma p2ibis_spec : forall n p, n<=size ->
Zpos p = ((Z_of_N (fst (p2ibis n p)))*2^(Z_of_nat n) +
phi (snd (p2ibis n p)))%Z.
Proof.
induction n; intros.
simpl; rewrite Pmult_1_r; auto.
replace (2^(Z_of_nat (S n)))%Z with (2*2^(Z_of_nat n))%Z by
(rewrite <- Zpower_Zsucc, <- Zpos_P_of_succ_nat;
auto with zarith).
rewrite (Zmult_comm 2).
assert (n<=size) by omega.
destruct p; simpl; [ | | auto];
specialize (IHn p H0);
generalize (p2ibis_bounded n p);
destruct (p2ibis n p) as (r,i); simpl in *; intros.
change (Zpos p~1) with (2*Zpos p + 1)%Z.
rewrite phi_twice_plus_one_firstl, Zdouble_plus_one_mult.
rewrite IHn; ring.
apply (nshiftr_0_firstl n); auto; try omega.
change (Zpos p~0) with (2*Zpos p)%Z.
rewrite phi_twice_firstl.
change (Zdouble (phi i)) with (2*(phi i))%Z.
rewrite IHn; ring.
apply (nshiftr_0_firstl n); auto; try omega.
Qed.
(** We now prove that this [p2ibis] is related to [phi_inv_positive] *)
Lemma phi_inv_positive_p2ibis : forall n p, (n<=size)%nat ->
EqShiftL (size-n) (phi_inv_positive p) (snd (p2ibis n p)).
Proof.
induction n.
intros.
apply EqShiftL_size; auto.
intros.
simpl p2ibis; destruct p; [ | | red; auto];
specialize IHn with p;
destruct (p2ibis n p); simpl snd in *; simpl phi_inv_positive;
rewrite ?EqShiftL_twice_plus_one, ?EqShiftL_twice;
replace (S (size - S n))%nat with (size - n)%nat by omega;
apply IHn; omega.
Qed.
(** This gives the expected result about [phi o phi_inv], at least
for the positive case. *)
Lemma phi_phi_inv_positive : forall p,
phi (phi_inv_positive p) = (Zpos p) mod (2^(Z_of_nat size)).
Proof.
intros.
replace (phi_inv_positive p) with (snd (p2ibis size p)).
rewrite (p2ibis_spec size p) by auto.
rewrite Zplus_comm, Z_mod_plus.
symmetry; apply Zmod_small.
apply phi_bounded.
auto with zarith.
symmetry.
rewrite <- EqShiftL_zero.
apply (phi_inv_positive_p2ibis size p); auto.
Qed.
(** Moreover, [p2ibis] is also related with [p2i] and hence with
[positive_to_int31]. *)
Lemma double_twice_firstl : forall x, firstl x = D0 -> Twon*x = twice x.
Proof.
intros.
unfold mul31.
rewrite <- Zdouble_mult, <- phi_twice_firstl, phi_inv_phi; auto.
Qed.
Lemma double_twice_plus_one_firstl : forall x, firstl x = D0 ->
Twon*x+In = twice_plus_one x.
Proof.
intros.
rewrite double_twice_firstl; auto.
unfold add31.
rewrite phi_twice_firstl, <- Zdouble_plus_one_mult,
<- phi_twice_plus_one_firstl, phi_inv_phi; auto.
Qed.
Lemma p2i_p2ibis : forall n p, (n<=size)%nat ->
p2i n p = p2ibis n p.
Proof.
induction n; simpl; auto; intros.
destruct p; auto; specialize IHn with p;
generalize (p2ibis_bounded n p);
rewrite IHn; try omega; destruct (p2ibis n p); simpl; intros;
f_equal; auto.
apply double_twice_plus_one_firstl.
apply (nshiftr_0_firstl n); auto; omega.
apply double_twice_firstl.
apply (nshiftr_0_firstl n); auto; omega.
Qed.
Lemma positive_to_int31_phi_inv_positive : forall p,
snd (positive_to_int31 p) = phi_inv_positive p.
Proof.
intros; unfold positive_to_int31.
rewrite p2i_p2ibis; auto.
symmetry.
rewrite <- EqShiftL_zero.
apply (phi_inv_positive_p2ibis size); auto.
Qed.
Lemma positive_to_int31_spec : forall p,
Zpos p = ((Z_of_N (fst (positive_to_int31 p)))*2^(Z_of_nat size) +
phi (snd (positive_to_int31 p)))%Z.
Proof.
unfold positive_to_int31.
intros; rewrite p2i_p2ibis; auto.
apply p2ibis_spec; auto.
Qed.
(** Thanks to the result about [phi o phi_inv_positive], we can
now establish easily the most general results about
[phi o twice] and so one. *)
Lemma phi_twice : forall x,
phi (twice x) = (Zdouble (phi x)) mod 2^(Z_of_nat size).
Proof.
intros.
pattern x at 1; rewrite <- (phi_inv_phi x).
rewrite <- phi_inv_double.
assert (0 <= Zdouble (phi x))%Z.
rewrite Zdouble_mult; generalize (phi_bounded x); omega.
destruct (Zdouble (phi x)).
simpl; auto.
apply phi_phi_inv_positive.
compute in H; elim H; auto.
Qed.
Lemma phi_twice_plus_one : forall x,
phi (twice_plus_one x) = (Zdouble_plus_one (phi x)) mod 2^(Z_of_nat size).
Proof.
intros.
pattern x at 1; rewrite <- (phi_inv_phi x).
rewrite <- phi_inv_double_plus_one.
assert (0 <= Zdouble_plus_one (phi x))%Z.
rewrite Zdouble_plus_one_mult; generalize (phi_bounded x); omega.
destruct (Zdouble_plus_one (phi x)).
simpl; auto.
apply phi_phi_inv_positive.
compute in H; elim H; auto.
Qed.
Lemma phi_incr : forall x,
phi (incr x) = (Zsucc (phi x)) mod 2^(Z_of_nat size).
Proof.
intros.
pattern x at 1; rewrite <- (phi_inv_phi x).
rewrite <- phi_inv_incr.
assert (0 <= Zsucc (phi x))%Z.
change (Zsucc (phi x)) with ((phi x)+1)%Z;
generalize (phi_bounded x); omega.
destruct (Zsucc (phi x)).
simpl; auto.
apply phi_phi_inv_positive.
compute in H; elim H; auto.
Qed.
(** With the previous results, we can deal with [phi o phi_inv] even
in the negative case *)
Lemma phi_phi_inv_negative :
forall p, phi (incr (complement_negative p)) = (Zneg p) mod 2^(Z_of_nat size).
Proof.
induction p.
simpl complement_negative.
rewrite phi_incr in IHp.
rewrite incr_twice, phi_twice_plus_one.
remember (phi (complement_negative p)) as q.
rewrite Zdouble_plus_one_mult.
replace (2*q+1)%Z with (2*(Zsucc q)-1)%Z by omega.
rewrite <- Zminus_mod_idemp_l, <- Zmult_mod_idemp_r, IHp.
rewrite Zmult_mod_idemp_r, Zminus_mod_idemp_l; auto with zarith.
simpl complement_negative.
rewrite incr_twice_plus_one, phi_twice.
remember (phi (incr (complement_negative p))) as q.
rewrite Zdouble_mult, IHp, Zmult_mod_idemp_r; auto with zarith.
simpl; auto.
Qed.
Lemma phi_phi_inv :
forall z, phi (phi_inv z) = z mod 2 ^ (Z_of_nat size).
Proof.
destruct z.
simpl; auto.
apply phi_phi_inv_positive.
apply phi_phi_inv_negative.
Qed.
End Basics.
Section Int31_Op.
(** Nullity test *)
Let w_iszero i := match i ?= 0 with Eq => true | _ => false end.
(** Modulo [2^p] *)
Let w_pos_mod p i :=
match compare31 p 31 with
| Lt => addmuldiv31 p 0 (addmuldiv31 (31-p) i 0)
| _ => i
end.
(** Parity test *)
Let w_iseven i :=
let (_,r) := i/2 in
match r ?= 0 with Eq => true | _ => false end.
Definition int31_op := (mk_znz_op
31%positive (* number of digits *)
31 (* number of digits *)
phi (* conversion to Z *)
positive_to_int31 (* positive -> N*int31 : p => N,i where p = N*2^31+phi i *)
head031 (* number of head 0 *)
tail031 (* number of tail 0 *)
(* Basic constructors *)
0
1
Tn (* 2^31 - 1 *)
(* Comparison *)
compare31
w_iszero
(* Basic arithmetic operations *)
(fun i => 0 -c i)
(fun i => 0 - i)
(fun i => 0-i-1)
(fun i => i +c 1)
add31c
add31carryc
(fun i => i + 1)
add31
(fun i j => i + j + 1)
(fun i => i -c 1)
sub31c
sub31carryc
(fun i => i - 1)
sub31
(fun i j => i - j - 1)
mul31c
mul31
(fun x => x *c x)
(* special (euclidian) division operations *)
div3121
div31 (* this is supposed to be the special case of division a/b where a > b *)
div31
(* euclidian division remainder *)
(* again special case for a > b *)
(fun i j => let (_,r) := i/j in r)
(fun i j => let (_,r) := i/j in r)
gcd31 (*gcd_gt*)
gcd31 (*gcd*)
(* shift operations *)
addmuldiv31 (*add_mul_div *)
(* modulo 2^p *)
w_pos_mod
(* is i even ? *)
w_iseven
(* square root operations *)
sqrt312 (* sqrt2 *)
sqrt31 (* sqrt *)
).
End Int31_Op.
Section Int31_Spec.
Open Local Scope Z_scope.
Notation "[| x |]" := (phi x) (at level 0, x at level 99).
Notation Local wB := (2 ^ (Z_of_nat size)).
Lemma wB_pos : wB > 0.
Proof.
auto with zarith.
Qed.
Notation "[+| c |]" :=
(interp_carry 1 wB phi c) (at level 0, x at level 99).
Notation "[-| c |]" :=
(interp_carry (-1) wB phi c) (at level 0, x at level 99).
Notation "[|| x ||]" :=
(zn2z_to_Z wB phi x) (at level 0, x at level 99).
Lemma spec_zdigits : [| 31 |] = 31.
Proof.
reflexivity.
Qed.
Lemma spec_more_than_1_digit: 1 < 31.
Proof.
auto with zarith.
Qed.
Lemma spec_0 : [| 0 |] = 0.
Proof.
reflexivity.
Qed.
Lemma spec_1 : [| 1 |] = 1.
Proof.
reflexivity.
Qed.
Lemma spec_Bm1 : [| Tn |] = wB - 1.
Proof.
reflexivity.
Qed.
Lemma spec_compare : forall x y,
match (x ?= y)%int31 with
| Eq => [|x|] = [|y|]
| Lt => [|x|] < [|y|]
| Gt => [|x|] > [|y|]
end.
Proof.
clear; unfold compare31; simpl; intros.
case_eq ([|x|] ?= [|y|]); auto.
intros; apply Zcompare_Eq_eq; auto.
Qed.
(** Addition *)
Lemma spec_add_c : forall x y, [+|add31c x y|] = [|x|] + [|y|].
Proof.
intros; unfold add31c, add31, interp_carry; rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X+Y) mod wB ?= X+Y <> Eq -> [+|C1 (phi_inv (X+Y))|] = X+Y).
unfold interp_carry; rewrite phi_phi_inv, Zcompare_Eq_iff_eq; intros.
destruct (Z_lt_le_dec (X+Y) wB).
contradict H1; auto using Zmod_small with zarith.
rewrite <- (Z_mod_plus_full (X+Y) (-1) wB).
rewrite Zmod_small; romega.
generalize (Zcompare_Eq_eq ((X+Y) mod wB) (X+Y)); intros Heq.
destruct Zcompare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_succ_c : forall x, [+|add31c x 1|] = [|x|] + 1.
Proof.
intros; apply spec_add_c.
Qed.
Lemma spec_add_carry_c : forall x y, [+|add31carryc x y|] = [|x|] + [|y|] + 1.
Proof.
intros.
unfold add31carryc, interp_carry; rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X+Y+1) mod wB ?= X+Y+1 <> Eq -> [+|C1 (phi_inv (X+Y+1))|] = X+Y+1).
unfold interp_carry; rewrite phi_phi_inv, Zcompare_Eq_iff_eq; intros.
destruct (Z_lt_le_dec (X+Y+1) wB).
contradict H1; auto using Zmod_small with zarith.
rewrite <- (Z_mod_plus_full (X+Y+1) (-1) wB).
rewrite Zmod_small; romega.
generalize (Zcompare_Eq_eq ((X+Y+1) mod wB) (X+Y+1)); intros Heq.
destruct Zcompare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_add : forall x y, [|x+y|] = ([|x|] + [|y|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_add_carry :
forall x y, [|x+y+1|] = ([|x|] + [|y|] + 1) mod wB.
Proof.
unfold add31; intros.
repeat rewrite phi_phi_inv.
apply Zplus_mod_idemp_l.
Qed.
Lemma spec_succ : forall x, [|x+1|] = ([|x|] + 1) mod wB.
Proof.
intros; rewrite <- spec_1; apply spec_add.
Qed.
(** Substraction *)
Lemma spec_sub_c : forall x y, [-|sub31c x y|] = [|x|] - [|y|].
Proof.
unfold sub31c, sub31, interp_carry; intros.
rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X-Y) mod wB ?= X-Y <> Eq -> [-|C1 (phi_inv (X-Y))|] = X-Y).
unfold interp_carry; rewrite phi_phi_inv, Zcompare_Eq_iff_eq; intros.
destruct (Z_lt_le_dec (X-Y) 0).
rewrite <- (Z_mod_plus_full (X-Y) 1 wB).
rewrite Zmod_small; romega.
contradict H1; apply Zmod_small; romega.
generalize (Zcompare_Eq_eq ((X-Y) mod wB) (X-Y)); intros Heq.
destruct Zcompare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_sub_carry_c : forall x y, [-|sub31carryc x y|] = [|x|] - [|y|] - 1.
Proof.
unfold sub31carryc, sub31, interp_carry; intros.
rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X-Y-1) mod wB ?= X-Y-1 <> Eq -> [-|C1 (phi_inv (X-Y-1))|] = X-Y-1).
unfold interp_carry; rewrite phi_phi_inv, Zcompare_Eq_iff_eq; intros.
destruct (Z_lt_le_dec (X-Y-1) 0).
rewrite <- (Z_mod_plus_full (X-Y-1) 1 wB).
rewrite Zmod_small; romega.
contradict H1; apply Zmod_small; romega.
generalize (Zcompare_Eq_eq ((X-Y-1) mod wB) (X-Y-1)); intros Heq.
destruct Zcompare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_sub : forall x y, [|x-y|] = ([|x|] - [|y|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_sub_carry :
forall x y, [|x-y-1|] = ([|x|] - [|y|] - 1) mod wB.
Proof.
unfold sub31; intros.
repeat rewrite phi_phi_inv.
apply Zminus_mod_idemp_l.
Qed.
Lemma spec_opp_c : forall x, [-|sub31c 0 x|] = -[|x|].
Proof.
intros; apply spec_sub_c.
Qed.
Lemma spec_opp : forall x, [|0 - x|] = (-[|x|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_opp_carry : forall x, [|0 - x - 1|] = wB - [|x|] - 1.
Proof.
unfold sub31; intros.
repeat rewrite phi_phi_inv.
change [|1|] with 1; change [|0|] with 0.
rewrite <- (Z_mod_plus_full (0-[|x|]) 1 wB).
rewrite Zminus_mod_idemp_l.
rewrite Zmod_small; generalize (phi_bounded x); romega.
Qed.
Lemma spec_pred_c : forall x, [-|sub31c x 1|] = [|x|] - 1.
Proof.
intros; apply spec_sub_c.
Qed.
Lemma spec_pred : forall x, [|x-1|] = ([|x|] - 1) mod wB.
Proof.
intros; apply spec_sub.
Qed.
(** Multiplication *)
Lemma phi2_phi_inv2 : forall x, [||phi_inv2 x||] = x mod (wB^2).
Proof.
assert (forall z, (z / wB) mod wB * wB + z mod wB = z mod wB ^ 2).
intros.
assert ((z/wB) mod wB = z/wB - (z/wB/wB)*wB).
rewrite (Z_div_mod_eq (z/wB) wB wB_pos) at 2; ring.
assert (z mod wB = z - (z/wB)*wB).
rewrite (Z_div_mod_eq z wB wB_pos) at 2; ring.
rewrite H.
rewrite H0 at 1.
ring_simplify.
rewrite Zdiv_Zdiv; auto with zarith.
rewrite (Z_div_mod_eq z (wB*wB)) at 2; auto with zarith.
change (wB*wB) with (wB^2); ring.
unfold phi_inv2.
destruct x; unfold zn2z_to_Z; rewrite ?phi_phi_inv;
change base with wB; auto.
Qed.
Lemma spec_mul_c : forall x y, [|| mul31c x y ||] = [|x|] * [|y|].
Proof.
unfold mul31c; intros.
rewrite phi2_phi_inv2.
apply Zmod_small.
generalize (phi_bounded x)(phi_bounded y); intros.
change (wB^2) with (wB * wB).
auto using Zmult_lt_compat with zarith.
Qed.
Lemma spec_mul : forall x y, [|x*y|] = ([|x|] * [|y|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_square_c : forall x, [|| mul31c x x ||] = [|x|] * [|x|].
Proof.
intros; apply spec_mul_c.
Qed.
(** Division *)
Lemma spec_div21 : forall a1 a2 b,
wB/2 <= [|b|] ->
[|a1|] < [|b|] ->
let (q,r) := div3121 a1 a2 b in
[|a1|] *wB+ [|a2|] = [|q|] * [|b|] + [|r|] /\
0 <= [|r|] < [|b|].
Proof.
unfold div3121; intros.
generalize (phi_bounded a1)(phi_bounded a2)(phi_bounded b); intros.
assert ([|b|]>0) by (auto with zarith).
generalize (Z_div_mod (phi2 a1 a2) [|b|] H4) (Z_div_pos (phi2 a1 a2) [|b|] H4).
unfold Zdiv; destruct (Zdiv_eucl (phi2 a1 a2) [|b|]); simpl.
rewrite ?phi_phi_inv.
destruct 1; intros.
unfold phi2 in *.
change base with wB; change base with wB in H5.
change (Zpower_pos 2 31) with wB; change (Zpower_pos 2 31) with wB in H.
rewrite H5, Zmult_comm.
replace (z0 mod wB) with z0 by (symmetry; apply Zmod_small; omega).
replace (z mod wB) with z; auto with zarith.
symmetry; apply Zmod_small.
split.
apply H7; change base with wB; auto with zarith.
apply Zmult_gt_0_lt_reg_r with [|b|].
omega.
rewrite Zmult_comm.
apply Zle_lt_trans with ([|b|]*z+z0).
omega.
rewrite <- H5.
apply Zle_lt_trans with ([|a1|]*wB+(wB-1)).
omega.
replace ([|a1|]*wB+(wB-1)) with (wB*([|a1|]+1)-1) by ring.
assert (wB*([|a1|]+1) <= wB*[|b|]); try omega.
apply Zmult_le_compat; omega.
Qed.
Lemma spec_div : forall a b, 0 < [|b|] ->
let (q,r) := div31 a b in
[|a|] = [|q|] * [|b|] + [|r|] /\
0 <= [|r|] < [|b|].
Proof.
unfold div31; intros.
assert ([|b|]>0) by (auto with zarith).
generalize (Z_div_mod [|a|] [|b|] H0) (Z_div_pos [|a|] [|b|] H0).
unfold Zdiv; destruct (Zdiv_eucl [|a|] [|b|]); simpl.
rewrite ?phi_phi_inv.
destruct 1; intros.
rewrite H1, Zmult_comm.
generalize (phi_bounded a)(phi_bounded b); intros.
replace (z0 mod wB) with z0 by (symmetry; apply Zmod_small; omega).
replace (z mod wB) with z; auto with zarith.
symmetry; apply Zmod_small.
split; auto with zarith.
apply Zle_lt_trans with [|a|]; auto with zarith.
rewrite H1.
apply Zle_trans with ([|b|]*z); try omega.
rewrite <- (Zmult_1_l z) at 1.
apply Zmult_le_compat; auto with zarith.
Qed.
Lemma spec_mod : forall a b, 0 < [|b|] ->
[|let (_,r) := (a/b)%int31 in r|] = [|a|] mod [|b|].
Proof.
unfold div31; intros.
assert ([|b|]>0) by (auto with zarith).
unfold Zmod.
generalize (Z_div_mod [|a|] [|b|] H0).
destruct (Zdiv_eucl [|a|] [|b|]); simpl.
rewrite ?phi_phi_inv.
destruct 1; intros.
generalize (phi_bounded b); intros.
apply Zmod_small; omega.
Qed.
Lemma phi_gcd : forall i j,
[|gcd31 i j|] = Zgcdn (2*size) [|j|] [|i|].
Proof.
unfold gcd31.
induction (2*size)%nat; intros.
reflexivity.
simpl.
unfold compare31.
change [|On|] with 0.
generalize (phi_bounded j)(phi_bounded i); intros.
case_eq [|j|]; intros.
simpl; intros.
generalize (Zabs_spec [|i|]); omega.
simpl.
rewrite IHn, H1; f_equal.
rewrite spec_mod, H1; auto.
rewrite H1; compute; auto.
rewrite H1 in H; destruct H as [H _]; compute in H; elim H; auto.
Qed.
Lemma spec_gcd : forall a b, Zis_gcd [|a|] [|b|] [|gcd31 a b|].
Proof.
intros.
rewrite phi_gcd.
apply Zis_gcd_sym.
apply Zgcdn_is_gcd.
unfold Zgcd_bound.
generalize (phi_bounded b).
destruct [|b|].
unfold size; auto with zarith.
intros (_,H).
cut (Psize p <= size)%nat; [ omega | rewrite <- Zpower2_Psize; auto].
intros (H,_); compute in H; elim H; auto.
Qed.
Lemma iter_int31_iter_nat : forall A f i a,
iter_int31 i A f a = iter_nat (Zabs_nat [|i|]) A f a.
Proof.
intros.
unfold iter_int31.
rewrite <- recrbis_equiv; auto; unfold recrbis.
rewrite <- phibis_aux_equiv.
revert i a; induction size.
simpl; auto.
simpl; intros.
case_eq (firstr i); intros H; rewrite 2 IHn;
unfold phibis_aux; simpl; rewrite H; fold (phibis_aux n (shiftr i));
generalize (phibis_aux_pos n (shiftr i)); intros;
set (z := phibis_aux n (shiftr i)) in *; clearbody z;
rewrite <- iter_nat_plus.
f_equal.
rewrite Zdouble_mult, Zmult_comm, <- Zplus_diag_eq_mult_2.
symmetry; apply Zabs_nat_Zplus; auto with zarith.
change (iter_nat (S (Zabs_nat z + Zabs_nat z)) A f a =
iter_nat (Zabs_nat (Zdouble_plus_one z)) A f a); f_equal.
rewrite Zdouble_plus_one_mult, Zmult_comm, <- Zplus_diag_eq_mult_2.
rewrite Zabs_nat_Zplus; auto with zarith.
rewrite Zabs_nat_Zplus; auto with zarith.
change (Zabs_nat 1) with 1%nat; omega.
Qed.
Fixpoint addmuldiv31_alt n i j :=
match n with
| O => i
| S n => addmuldiv31_alt n (sneakl (firstl j) i) (shiftl j)
end.
Lemma addmuldiv31_equiv : forall p x y,
addmuldiv31 p x y = addmuldiv31_alt (Zabs_nat [|p|]) x y.
Proof.
intros.
unfold addmuldiv31.
rewrite iter_int31_iter_nat.
set (n:=Zabs_nat [|p|]); clearbody n; clear p.
revert x y; induction n.
simpl; auto.
intros.
simpl addmuldiv31_alt.
replace (S n) with (n+1)%nat by (rewrite plus_comm; auto).
rewrite iter_nat_plus; simpl; auto.
Qed.
Lemma spec_add_mul_div : forall x y p, [|p|] <= Zpos 31 ->
[| addmuldiv31 p x y |] =
([|x|] * (2 ^ [|p|]) + [|y|] / (2 ^ ((Zpos 31) - [|p|]))) mod wB.
Proof.
intros.
rewrite addmuldiv31_equiv.
assert ([|p|] = Z_of_nat (Zabs_nat [|p|])).
rewrite inj_Zabs_nat; symmetry; apply Zabs_eq.
destruct (phi_bounded p); auto.
rewrite H0; rewrite H0 in H; clear H0; rewrite Zabs_nat_Z_of_nat.
set (n := Zabs_nat [|p|]) in *; clearbody n.
assert (n <= 31)%nat.
rewrite inj_le_iff; auto with zarith.
clear p H; revert x y.
induction n.
simpl; intros.
change (Zpower_pos 2 31) with (2^31).
rewrite Zmult_1_r.
replace ([|y|] / 2^31) with 0.
rewrite Zplus_0_r.
symmetry; apply Zmod_small; apply phi_bounded.
symmetry; apply Zdiv_small; apply phi_bounded.
simpl addmuldiv31_alt; intros.
rewrite IHn; [ | omega ].
case_eq (firstl y); intros.
rewrite phi_twice, Zdouble_mult.
rewrite phi_twice_firstl; auto.
change (Zdouble [|y|]) with (2*[|y|]).
rewrite inj_S, Zpower_Zsucc; auto with zarith.
rewrite Zplus_mod; rewrite Zmult_mod_idemp_l; rewrite <- Zplus_mod.
f_equal.
apply Zplus_eq_compat.
ring.
replace (31-Z_of_nat n) with (Zsucc(31-Zsucc(Z_of_nat n))) by ring.
rewrite Zpower_Zsucc, <- Zdiv_Zdiv; auto with zarith.
rewrite Zmult_comm, Z_div_mult; auto with zarith.
rewrite phi_twice_plus_one, Zdouble_plus_one_mult.
rewrite phi_twice; auto.
change (Zdouble [|y|]) with (2*[|y|]).
rewrite inj_S, Zpower_Zsucc; auto with zarith.
rewrite Zplus_mod; rewrite Zmult_mod_idemp_l; rewrite <- Zplus_mod.
rewrite Zmult_plus_distr_l, Zmult_1_l, <- Zplus_assoc.
f_equal.
apply Zplus_eq_compat.
ring.
assert ((2*[|y|]) mod wB = 2*[|y|] - wB).
admit.
rewrite H1.
replace wB with (2^(Z_of_nat n)*2^(31-Z_of_nat n)) by
(rewrite <- Zpower_exp; auto with zarith; f_equal; unfold size; ring).
unfold Zminus; rewrite Zopp_mult_distr_l.
rewrite Z_div_plus; auto with zarith.
ring_simplify.
replace (31+-Z_of_nat n) with (Zsucc(31-Zsucc(Z_of_nat n))) by ring.
rewrite Zpower_Zsucc, <- Zdiv_Zdiv; auto with zarith.
rewrite Zmult_comm, Z_div_mult; auto with zarith.
Qed.
Let w_pos_mod := int31_op.(znz_pos_mod).
Lemma spec_pos_mod : forall w p,
[|w_pos_mod p w|] = [|w|] mod (2 ^ [|p|]).
Proof.
unfold w_pos_mod, znz_pos_mod, int31_op, compare31.
change [|31|] with 31%Z.
assert (forall w p, 31<=p -> [|w|] = [|w|] mod 2^p).
intros.
generalize (phi_bounded w).
symmetry; apply Zmod_small.
split; auto with zarith.
apply Zlt_le_trans with wB; auto with zarith.
apply Zpower_le_monotone; auto with zarith.
intros.
case_eq ([|p|] ?= 31); intros;
[ apply H; rewrite (Zcompare_Eq_eq _ _ H0); auto with zarith | |
apply H; change ([|p|]>31)%Z in H0; auto with zarith ].
change ([|p|]<31) in H0.
rewrite spec_add_mul_div by auto with zarith.
change [|0|] with 0%Z; rewrite Zmult_0_l, Zplus_0_l.
generalize (phi_bounded p)(phi_bounded w); intros.
assert (31-[|p|]<wB).
apply Zle_lt_trans with 31%Z; auto with zarith.
compute; auto.
assert ([|31-p|]=31-[|p|]).
unfold sub31; rewrite phi_phi_inv.
change [|31|] with 31%Z.
apply Zmod_small; auto with zarith.
rewrite spec_add_mul_div by (rewrite H4; auto with zarith).
change [|0|] with 0%Z; rewrite Zdiv_0_l, Zplus_0_r.
rewrite H4.
apply shift_unshift_mod_2; auto with zarith.
Qed.
(** Shift operations *)
Lemma spec_head00: forall x, [|x|] = 0 -> [|head031 x|] = Zpos 31.
Proof.
intros.
generalize (phi_inv_phi x).
rewrite H; simpl.
intros H'; rewrite <- H'.
simpl; auto.
Qed.
Fixpoint head031_alt n x :=
match n with
| O => 0%nat
| S n => match firstl x with
| D0 => S (head031_alt n (shiftl x))
| D1 => 0%nat
end
end.
Lemma head031_equiv :
forall x, [|head031 x|] = Z_of_nat (head031_alt size x).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H).
simpl; auto.
unfold head031, recl.
change On with (phi_inv (Z_of_nat (31-size))).
replace (head031_alt size x) with
(head031_alt size x + (31 - size))%nat by (apply plus_0_r; auto).
assert (size <= 31)%nat by auto with arith.
revert x H; induction size; intros.
simpl; auto.
unfold recl_aux; fold recl_aux.
unfold head031_alt; fold head031_alt.
rewrite H.
assert ([|phi_inv (Z_of_nat (31-S n))|] = Z_of_nat (31 - S n)).
rewrite phi_phi_inv.
apply Zmod_small.
split.
change 0 with (Z_of_nat O); apply inj_le; omega.
apply Zle_lt_trans with (Z_of_nat 31).
apply inj_le; omega.
compute; auto.
case_eq (firstl x); intros; auto.
rewrite plus_Sn_m, plus_n_Sm.
replace (S (31 - S n)) with (31 - n)%nat by omega.
rewrite <- IHn; [ | omega | ].
f_equal; f_equal.
unfold add31.
rewrite H1.
f_equal.
change [|In|] with 1.
replace (31-n)%nat with (S (31 - S n))%nat by omega.
rewrite inj_S; ring.
clear - H H2.
rewrite (sneakr_shiftl x) in H.
rewrite H2 in H.
case_eq (iszero (shiftl x)); intros; auto.
rewrite (iszero_eq0 _ H0) in H; discriminate.
Qed.
Lemma phi_nz : forall x, 0 < [|x|] <-> x <> 0%int31.
Proof.
split; intros.
red; intro; subst x; discriminate.
assert ([|x|]<>0%Z).
contradict H.
rewrite <- (phi_inv_phi x); rewrite H; auto.
generalize (phi_bounded x); auto with zarith.
Qed.
Lemma spec_head0 : forall x, 0 < [|x|] ->
wB/ 2 <= 2 ^ ([|head031 x|]) * [|x|] < wB.
Proof.
intros.
rewrite head031_equiv.
assert (nshiftl size x = 0%int31).
apply nshiftl_size.
revert x H H0.
unfold size at 2 5.
induction size.
simpl Z_of_nat.
intros.
compute in H0; rewrite H0 in H; discriminate.
intros.
simpl head031_alt.
case_eq (firstl x); intros.
rewrite (inj_S (head031_alt n (shiftl x))), Zpower_Zsucc; auto with zarith.
rewrite <- Zmult_assoc, Zmult_comm, <- Zmult_assoc, <-(Zmult_comm 2).
rewrite <- Zdouble_mult, <- (phi_twice_firstl _ H1).
apply IHn.
rewrite phi_nz; rewrite phi_nz in H; contradict H.
change twice with shiftl in H.
rewrite (sneakr_shiftl x), H1, H; auto.
rewrite <- nshiftl_S_tail; auto.
change (2^(Z_of_nat 0)) with 1; rewrite Zmult_1_l.
generalize (phi_bounded x); unfold size; split; auto with zarith.
change (2^(Z_of_nat 31)/2) with (2^(Z_of_nat (pred size))).
apply phi_lowerbound; auto.
Qed.
Lemma spec_tail00: forall x, [|x|] = 0 -> [|tail031 x|] = Zpos 31.
Proof.
intros.
generalize (phi_inv_phi x).
rewrite H; simpl.
intros H'; rewrite <- H'.
simpl; auto.
Qed.
Fixpoint tail031_alt n x :=
match n with
| O => 0%nat
| S n => match firstr x with
| D0 => S (tail031_alt n (shiftr x))
| D1 => 0%nat
end
end.
Lemma tail031_equiv :
forall x, [|tail031 x|] = Z_of_nat (tail031_alt size x).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H).
simpl; auto.
unfold tail031, recr.
change On with (phi_inv (Z_of_nat (31-size))).
replace (tail031_alt size x) with
(tail031_alt size x + (31 - size))%nat by (apply plus_0_r; auto).
assert (size <= 31)%nat by auto with arith.
revert x H; induction size; intros.
simpl; auto.
unfold recr_aux; fold recr_aux.
unfold tail031_alt; fold tail031_alt.
rewrite H.
assert ([|phi_inv (Z_of_nat (31-S n))|] = Z_of_nat (31 - S n)).
rewrite phi_phi_inv.
apply Zmod_small.
split.
change 0 with (Z_of_nat O); apply inj_le; omega.
apply Zle_lt_trans with (Z_of_nat 31).
apply inj_le; omega.
compute; auto.
case_eq (firstr x); intros; auto.
rewrite plus_Sn_m, plus_n_Sm.
replace (S (31 - S n)) with (31 - n)%nat by omega.
rewrite <- IHn; [ | omega | ].
f_equal; f_equal.
unfold add31.
rewrite H1.
f_equal.
change [|In|] with 1.
replace (31-n)%nat with (S (31 - S n))%nat by omega.
rewrite inj_S; ring.
clear - H H2.
rewrite (sneakl_shiftr x) in H.
rewrite H2 in H.
case_eq (iszero (shiftr x)); intros; auto.
rewrite (iszero_eq0 _ H0) in H; discriminate.
Qed.
Lemma spec_tail0 : forall x, 0 < [|x|] ->
exists y, 0 <= y /\ [|x|] = (2 * y + 1) * (2 ^ [|tail031 x|]).
Proof.
intros.
rewrite tail031_equiv.
assert (nshiftr size x = 0%int31).
apply nshiftr_size.
revert x H H0.
induction size.
simpl Z_of_nat.
intros.
compute in H0; rewrite H0 in H; discriminate.
intros.
simpl tail031_alt.
case_eq (firstr x); intros.
rewrite (inj_S (tail031_alt n (shiftr x))), Zpower_Zsucc; auto with zarith.
destruct (IHn (shiftr x)) as (y & Hy1 & Hy2).
rewrite phi_nz; rewrite phi_nz in H; contradict H.
rewrite (sneakl_shiftr x), H1, H; auto.
rewrite <- nshiftr_S_tail; auto.
exists y; split; auto.
rewrite phi_eqn1; auto.
rewrite Zdouble_mult, Hy2; ring.
exists [|shiftr x|].
split.
generalize (phi_bounded (shiftr x)); auto with zarith.
rewrite phi_eqn2; auto.
rewrite Zdouble_plus_one_mult; simpl; ring.
Qed.
(* Sqrt *)
(* Direct transcription of an old proof
of a fortran program in boyer-moore *)
Lemma quotient_by_2 a: a - 1 <= (a/2) + (a/2).
Proof.
intros a; case (Z_mod_lt a 2); auto with zarith.
intros H1; rewrite Zmod_eq_full; auto with zarith.
Qed.
Lemma sqrt_main_trick j k: 0 <= j -> 0 <= k ->
(j * k) + j <= ((j + k)/2 + 1) ^ 2.
Proof.
intros j k Hj; generalize Hj k; pattern j; apply natlike_ind;
auto; clear k j Hj.
intros _ k Hk; repeat rewrite Zplus_0_l.
apply Zmult_le_0_compat; generalize (Z_div_pos k 2); auto with zarith.
intros j Hj Hrec _ k Hk; pattern k; apply natlike_ind; auto; clear k Hk.
rewrite Zmult_0_r, Zplus_0_r, Zplus_0_l.
generalize (sqr_pos (Zsucc j / 2)) (quotient_by_2 (Zsucc j));
unfold Zsucc.
rewrite Zpower_2, Zmult_plus_distr_l; repeat rewrite Zmult_plus_distr_r.
auto with zarith.
intros k Hk _.
replace ((Zsucc j + Zsucc k) / 2) with ((j + k)/2 + 1).
generalize (Hrec Hj k Hk) (quotient_by_2 (j + k)).
unfold Zsucc; repeat rewrite Zpower_2;
repeat rewrite Zmult_plus_distr_l; repeat rewrite Zmult_plus_distr_r.
repeat rewrite Zmult_1_l; repeat rewrite Zmult_1_r.
auto with zarith.
rewrite Zplus_comm, <- Z_div_plus_full_l; auto with zarith.
apply f_equal2 with (f := Zdiv); auto with zarith.
Qed.
Lemma sqrt_main i j: 0 <= i -> 0 < j -> i < ((j + (i/j))/2 + 1) ^ 2.
Proof.
intros i j Hi Hj.
assert (Hij: 0 <= i/j) by (apply Z_div_pos; auto with zarith).
apply Zlt_le_trans with (2 := sqrt_main_trick _ _ (Zlt_le_weak _ _ Hj) Hij).
pattern i at 1; rewrite (Z_div_mod_eq i j); case (Z_mod_lt i j); auto with zarith.
Qed.
Lemma sqrt_init i: 1 < i -> i < (i/2 + 1) ^ 2.
Proof.
intros i Hi.
assert (H1: 0 <= i - 2) by auto with zarith.
assert (H2: 1 <= (i / 2) ^ 2); auto with zarith.
replace i with (1* 2 + (i - 2)); auto with zarith.
rewrite Zpower_2, Z_div_plus_full_l; auto with zarith.
generalize (sqr_pos ((i - 2)/ 2)) (Z_div_pos (i - 2) 2).
rewrite Zmult_plus_distr_l; repeat rewrite Zmult_plus_distr_r.
auto with zarith.
generalize (quotient_by_2 i).
rewrite Zpower_2 in H2 |- *;
repeat (rewrite Zmult_plus_distr_l ||
rewrite Zmult_plus_distr_r ||
rewrite Zmult_1_l || rewrite Zmult_1_r).
auto with zarith.
Qed.
Lemma sqrt_test_true i j: 0 <= i -> 0 < j -> i/j >= j -> j ^ 2 <= i.
Proof.
intros i j Hi Hj Hd; rewrite Zpower_2.
apply Zle_trans with (j * (i/j)); auto with zarith.
apply Z_mult_div_ge; auto with zarith.
Qed.
Lemma sqrt_test_false i j: 0 <= i -> 0 < j -> i/j < j -> (j + (i/j))/2 < j.
Proof.
intros i j Hi Hj H; case (Zle_or_lt j ((j + (i/j))/2)); auto.
intros H1; contradict H; apply Zle_not_lt.
assert (2 * j <= j + (i/j)); auto with zarith.
apply Zle_trans with (2 * ((j + (i/j))/2)); auto with zarith.
apply Z_mult_div_ge; auto with zarith.
Qed.
(* George's trick *)
Inductive ZcompareSpec (i j: Z): comparison -> Prop :=
ZcompareSpecEq: i = j -> ZcompareSpec i j Eq
| ZcompareSpecLt: i < j -> ZcompareSpec i j Lt
| ZcompareSpecGt: j < i -> ZcompareSpec i j Gt.
Lemma Zcompare_spec i j: ZcompareSpec i j (i ?= j).
Proof.
intros i j; case_eq (Zcompare i j); intros H.
apply ZcompareSpecEq; apply Zcompare_Eq_eq; auto.
apply ZcompareSpecLt; auto.
apply ZcompareSpecGt; apply Zgt_lt; auto.
Qed.
Lemma sqrt31_step_def rec i j:
sqrt31_step rec i j =
match (fst (i/j) ?= j)%int31 with
Lt => rec i (fst ((j + fst(i/j))/2))%int31
| _ => j
end.
Proof.
intros rec i j; unfold sqrt31_step; case div31; intros.
simpl; case compare31; auto.
Qed.
Lemma div31_phi i j: 0 < [|j|] -> [|fst (i/j)%int31|] = [|i|]/[|j|].
intros i j Hj; generalize (spec_div i j Hj).
case div31; intros q r; simpl fst.
intros (H1,H2); apply Zdiv_unique with [|r|]; auto with zarith.
rewrite H1; ring.
Qed.
Lemma sqrt31_step_correct rec i j:
0 < [|i|] -> 0 < [|j|] -> [|i|] < ([|j|] + 1) ^ 2 ->
2 * [|j|] < wB ->
(forall j1 : int31,
0 < [|j1|] < [|j|] -> [|i|] < ([|j1|] + 1) ^ 2 ->
[|rec i j1|] ^ 2 <= [|i|] < ([|rec i j1|] + 1) ^ 2) ->
[|sqrt31_step rec i j|] ^ 2 <= [|i|] < ([|sqrt31_step rec i j|] + 1) ^ 2.
Proof.
assert (Hp2: 0 < [|2|]) by exact (refl_equal Lt).
intros rec i j Hi Hj Hij H31 Hrec; rewrite sqrt31_step_def.
generalize (spec_compare (fst (i/j)%int31) j); case compare31;
rewrite div31_phi; auto; intros Hc;
try (split; auto; apply sqrt_test_true; auto with zarith; fail).
apply Hrec; repeat rewrite div31_phi; auto with zarith.
replace [|(j + fst (i / j)%int31)|] with ([|j|] + [|i|] / [|j|]).
split.
case (Zle_lt_or_eq 1 [|j|]); auto with zarith; intros Hj1.
replace ([|j|] + [|i|]/[|j|]) with
(1 * 2 + (([|j|] - 2) + [|i|] / [|j|])); try ring.
rewrite Z_div_plus_full_l; auto with zarith.
assert (0 <= [|i|]/ [|j|]) by (apply Z_div_pos; auto with zarith).
assert (0 <= ([|j|] - 2 + [|i|] / [|j|]) / [|2|]) ; auto with zarith.
rewrite <- Hj1, Zdiv_1_r.
replace (1 + [|i|])%Z with (1 * 2 + ([|i|] - 1))%Z; try ring.
rewrite Z_div_plus_full_l; auto with zarith.
assert (0 <= ([|i|] - 1) /2)%Z by (apply Z_div_pos; auto with zarith).
change ([|2|]) with 2%Z; auto with zarith.
apply sqrt_test_false; auto with zarith.
rewrite spec_add, div31_phi; auto.
apply sym_equal; apply Zmod_small.
split; auto with zarith.
replace [|j + fst (i / j)%int31|] with ([|j|] + [|i|] / [|j|]).
apply sqrt_main; auto with zarith.
rewrite spec_add, div31_phi; auto.
apply sym_equal; apply Zmod_small.
split; auto with zarith.
Qed.
Lemma iter31_sqrt_correct n rec i j: 0 < [|i|] -> 0 < [|j|] ->
[|i|] < ([|j|] + 1) ^ 2 -> 2 * [|j|] < 2 ^ (Z_of_nat size) ->
(forall j1, 0 < [|j1|] -> 2^(Z_of_nat n) + [|j1|] <= [|j|] ->
[|i|] < ([|j1|] + 1) ^ 2 -> 2 * [|j1|] < 2 ^ (Z_of_nat size) ->
[|rec i j1|] ^ 2 <= [|i|] < ([|rec i j1|] + 1) ^ 2) ->
[|iter31_sqrt n rec i j|] ^ 2 <= [|i|] < ([|iter31_sqrt n rec i j|] + 1) ^ 2.
Proof.
intros n; elim n; unfold iter31_sqrt; fold iter31_sqrt; clear n.
intros rec i j Hi Hj Hij H31 Hrec; apply sqrt31_step_correct; auto with zarith.
intros; apply Hrec; auto with zarith.
rewrite Zpower_0_r; auto with zarith.
intros n Hrec rec i j Hi Hj Hij H31 HHrec.
apply sqrt31_step_correct; auto.
intros j1 Hj1 Hjp1; apply Hrec; auto with zarith.
intros j2 Hj2 H2j2 Hjp2 Hj31; apply Hrec; auto with zarith.
intros j3 Hj3 Hpj3.
apply HHrec; auto.
rewrite inj_S, Zpower_Zsucc.
apply Zle_trans with (2 ^Z_of_nat n + [|j2|]); auto with zarith.
apply Zle_0_nat.
Qed.
Lemma spec_sqrt : forall x,
[|sqrt31 x|] ^ 2 <= [|x|] < ([|sqrt31 x|] + 1) ^ 2.
Proof.
intros i; unfold sqrt31.
generalize (spec_compare 1 i); case compare31; change [|1|] with 1;
intros Hi; auto with zarith.
repeat rewrite Zpower_2; auto with zarith.
apply iter31_sqrt_correct; auto with zarith.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
replace ([|i|]) with (1 * 2 + ([|i|] - 2))%Z; try ring.
assert (0 <= ([|i|] - 2)/2)%Z by (apply Z_div_pos; auto with zarith).
rewrite Z_div_plus_full_l; auto with zarith.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
apply sqrt_init; auto.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
apply Zle_lt_trans with ([|i|]).
apply Z_mult_div_ge; auto with zarith.
case (phi_bounded i); auto.
intros j2 H1 H2; contradict H2; apply Zlt_not_le.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
apply Zle_lt_trans with ([|i|]); auto with zarith.
assert (0 <= [|i|]/2)%Z by (apply Z_div_pos; auto with zarith).
apply Zle_trans with (2 * ([|i|]/2)); auto with zarith.
apply Z_mult_div_ge; auto with zarith.
case (phi_bounded i); unfold size; auto with zarith.
change [|0|] with 0; auto with zarith.
case (phi_bounded i); repeat rewrite Zpower_2; auto with zarith.
Qed.
Lemma sqrt312_step_def rec ih il j:
sqrt312_step rec ih il j =
match (ih ?= j)%int31 with
Eq => j
| Gt => j
| _ =>
match (fst (div3121 ih il j) ?= j)%int31 with
Lt => let m := match j +c fst (div3121 ih il j) with
C0 m1 => fst (m1/2)%int31
| C1 m1 => (fst (m1/2) + v30)%int31
end in rec ih il m
| _ => j
end
end.
Proof.
intros rec ih il j; unfold sqrt312_step; case div3121; intros.
simpl; case compare31; auto.
Qed.
Lemma sqrt312_lower_bound ih il j:
phi2 ih il < ([|j|] + 1) ^ 2 -> [|ih|] <= [|j|].
Proof.
intros ih il j H1.
case (phi_bounded j); intros Hbj _.
case (phi_bounded il); intros Hbil _.
case (phi_bounded ih); intros Hbih Hbih1.
assert (([|ih|] < [|j|] + 1)%Z); auto with zarith.
apply Zlt_square_simpl; auto with zarith.
repeat rewrite <-Zpower_2; apply Zle_lt_trans with (2 := H1).
apply Zle_trans with ([|ih|] * base)%Z; unfold phi2, base;
try rewrite Zpower_2; auto with zarith.
Qed.
Lemma div312_phi ih il j: (2^30 <= [|j|] -> [|ih|] < [|j|] ->
[|fst (div3121 ih il j)|] = phi2 ih il/[|j|])%Z.
Proof.
intros ih il j Hj Hj1.
generalize (spec_div21 ih il j Hj Hj1).
case div3121; intros q r (Hq, Hr).
apply Zdiv_unique with (phi r); auto with zarith.
simpl fst; apply trans_equal with (1 := Hq); ring.
Qed.
Lemma sqrt312_step_correct rec ih il j:
2 ^ 29 <= [|ih|] -> 0 < [|j|] -> phi2 ih il < ([|j|] + 1) ^ 2 ->
(forall j1, 0 < [|j1|] < [|j|] -> phi2 ih il < ([|j1|] + 1) ^ 2 ->
[|rec ih il j1|] ^ 2 <= phi2 ih il < ([|rec ih il j1|] + 1) ^ 2) ->
[|sqrt312_step rec ih il j|] ^ 2 <= phi2 ih il
< ([|sqrt312_step rec ih il j|] + 1) ^ 2.
Proof.
assert (Hp2: (0 < [|2|])%Z) by exact (refl_equal Lt).
intros rec ih il j Hih Hj Hij Hrec; rewrite sqrt312_step_def.
assert (H1: ([|ih|] <= [|j|])%Z) by (apply sqrt312_lower_bound with il; auto).
case (phi_bounded ih); intros Hih1 _.
case (phi_bounded il); intros Hil1 _.
case (phi_bounded j); intros _ Hj1.
assert (Hp3: (0 < phi2 ih il)).
unfold phi2; apply Zlt_le_trans with ([|ih|] * base)%Z; auto with zarith.
apply Zmult_lt_0_compat; auto with zarith.
apply Zlt_le_trans with (2:= Hih); auto with zarith.
generalize (spec_compare ih j); case compare31; intros Hc1.
split; auto.
apply sqrt_test_true; auto.
unfold phi2, base; auto with zarith.
unfold phi2; rewrite Hc1.
assert (0 <= [|il|]/[|j|]) by (apply Z_div_pos; auto with zarith).
rewrite Zmult_comm, Z_div_plus_full_l; unfold base; auto with zarith.
unfold Zpower, Zpower_pos in Hj1; simpl in Hj1; auto with zarith.
case (Zle_or_lt (2 ^ 30) [|j|]); intros Hjj.
generalize (spec_compare (fst (div3121 ih il j)) j); case compare31;
rewrite div312_phi; auto; intros Hc;
try (split; auto; apply sqrt_test_true; auto with zarith; fail).
apply Hrec.
assert (Hf1: 0 <= phi2 ih il/ [|j|]) by (apply Z_div_pos; auto with zarith).
case (Zle_lt_or_eq 1 ([|j|])); auto with zarith; intros Hf2.
2: contradict Hc; apply Zle_not_lt; rewrite <- Hf2, Zdiv_1_r; auto with zarith.
assert (Hf3: 0 < ([|j|] + phi2 ih il / [|j|]) / 2).
replace ([|j|] + phi2 ih il/ [|j|])%Z with
(1 * 2 + (([|j|] - 2) + phi2 ih il / [|j|])); try ring.
rewrite Z_div_plus_full_l; auto with zarith.
assert (0 <= ([|j|] - 2 + phi2 ih il / [|j|]) / 2) ; auto with zarith.
assert (Hf4: ([|j|] + phi2 ih il / [|j|]) / 2 < [|j|]).
apply sqrt_test_false; auto with zarith.
generalize (spec_add_c j (fst (div3121 ih il j))).
unfold interp_carry; case add31c; intros r;
rewrite div312_phi; auto with zarith.
rewrite div31_phi; change [|2|] with 2%Z; auto with zarith.
intros HH; rewrite HH; clear HH; auto with zarith.
rewrite spec_add, div31_phi; change [|2|] with 2%Z; auto.
rewrite Zmult_1_l; intros HH.
rewrite Zplus_comm, <- Z_div_plus_full_l; auto with zarith.
change (phi v30 * 2) with (2 ^ Z_of_nat size).
rewrite HH, Zmod_small; auto with zarith.
replace (phi
match j +c fst (div3121 ih il j) with
| C0 m1 => fst (m1 / 2)%int31
| C1 m1 => fst (m1 / 2)%int31 + v30
end) with ((([|j|] + (phi2 ih il)/([|j|]))/2)).
apply sqrt_main; auto with zarith.
generalize (spec_add_c j (fst (div3121 ih il j))).
unfold interp_carry; case add31c; intros r;
rewrite div312_phi; auto with zarith.
rewrite div31_phi; auto with zarith.
intros HH; rewrite HH; auto with zarith.
intros HH; rewrite <- HH.
change (1 * 2 ^ Z_of_nat size) with (phi (v30) * 2).
rewrite Z_div_plus_full_l; auto with zarith.
rewrite Zplus_comm.
rewrite spec_add, Zmod_small.
rewrite div31_phi; auto.
split; auto with zarith.
case (phi_bounded (fst (r/2)%int31));
case (phi_bounded v30); auto with zarith.
rewrite div31_phi; change (phi 2) with 2%Z; auto.
change (2 ^Z_of_nat size) with (base/2 + phi v30).
assert (phi r / 2 < base/2); auto with zarith.
apply Zmult_gt_0_lt_reg_r with 2; auto with zarith.
change (base/2 * 2) with base.
apply Zle_lt_trans with (phi r).
rewrite Zmult_comm; apply Z_mult_div_ge; auto with zarith.
case (phi_bounded r); auto with zarith.
contradict Hij; apply Zle_not_lt.
assert ((1 + [|j|]) <= 2 ^ 30); auto with zarith.
apply Zle_trans with ((2 ^ 30) * (2 ^ 30)); auto with zarith.
assert (0 <= 1 + [|j|]); auto with zarith.
apply Zmult_le_compat; auto with zarith.
change ((2 ^ 30) * (2 ^ 30)) with ((2 ^ 29) * base).
apply Zle_trans with ([|ih|] * base); auto with zarith.
unfold phi2, base; auto with zarith.
split; auto.
apply sqrt_test_true; auto.
unfold phi2, base; auto with zarith.
apply Zle_ge; apply Zle_trans with (([|j|] * base)/[|j|]).
rewrite Zmult_comm, Z_div_mult; auto with zarith.
apply Zge_le; apply Z_div_ge; auto with zarith.
Qed.
Lemma iter312_sqrt_correct n rec ih il j:
2^29 <= [|ih|] -> 0 < [|j|] -> phi2 ih il < ([|j|] + 1) ^ 2 ->
(forall j1, 0 < [|j1|] -> 2^(Z_of_nat n) + [|j1|] <= [|j|] ->
phi2 ih il < ([|j1|] + 1) ^ 2 ->
[|rec ih il j1|] ^ 2 <= phi2 ih il < ([|rec ih il j1|] + 1) ^ 2) ->
[|iter312_sqrt n rec ih il j|] ^ 2 <= phi2 ih il
< ([|iter312_sqrt n rec ih il j|] + 1) ^ 2.
Proof.
intros n; elim n; unfold iter312_sqrt; fold iter312_sqrt; clear n.
intros rec ih il j Hi Hj Hij Hrec; apply sqrt312_step_correct; auto with zarith.
intros; apply Hrec; auto with zarith.
rewrite Zpower_0_r; auto with zarith.
intros n Hrec rec ih il j Hi Hj Hij HHrec.
apply sqrt312_step_correct; auto.
intros j1 Hj1 Hjp1; apply Hrec; auto with zarith.
intros j2 Hj2 H2j2 Hjp2; apply Hrec; auto with zarith.
intros j3 Hj3 Hpj3.
apply HHrec; auto.
rewrite inj_S, Zpower_Zsucc.
apply Zle_trans with (2 ^Z_of_nat n + [|j2|])%Z; auto with zarith.
apply Zle_0_nat.
Qed.
Lemma spec_sqrt2 : forall x y,
wB/ 4 <= [|x|] ->
let (s,r) := sqrt312 x y in
[||WW x y||] = [|s|] ^ 2 + [+|r|] /\
[+|r|] <= 2 * [|s|].
Proof.
intros ih il Hih; unfold sqrt312.
change [||WW ih il||] with (phi2 ih il).
assert (Hbin: forall s, s * s + 2* s + 1 = (s + 1) ^ 2) by
(intros s; ring).
assert (Hb: 0 <= base) by (red; intros HH; discriminate).
assert (Hi2: phi2 ih il < (phi Tn + 1) ^ 2).
change ((phi Tn + 1) ^ 2) with (2^62).
apply Zle_lt_trans with ((2^31 -1) * base + (2^31 - 1)); auto with zarith.
2: simpl; unfold Zpower_pos; simpl; auto with zarith.
case (phi_bounded ih); case (phi_bounded il); intros H1 H2 H3 H4.
unfold base, Zpower, Zpower_pos in H2,H4; simpl in H2,H4.
unfold phi2,Zpower, Zpower_pos; simpl iter_pos; auto with zarith.
case (iter312_sqrt_correct 31 (fun _ _ j => j) ih il Tn); auto with zarith.
change [|Tn|] with 2147483647; auto with zarith.
intros j1 _ HH; contradict HH.
apply Zlt_not_le.
change [|Tn|] with 2147483647; auto with zarith.
change (2 ^ Z_of_nat 31) with 2147483648; auto with zarith.
case (phi_bounded j1); auto with zarith.
set (s := iter312_sqrt 31 (fun _ _ j : int31 => j) ih il Tn).
intros Hs1 Hs2.
generalize (spec_mul_c s s); case mul31c.
simpl zn2z_to_Z; intros HH.
assert ([|s|] = 0).
case (Zmult_integral _ _ (sym_equal HH)); auto.
contradict Hs2; apply Zle_not_lt; rewrite H.
change ((0 + 1) ^ 2) with 1.
apply Zle_trans with (2 ^ Z_of_nat size / 4 * base).
simpl; auto with zarith.
apply Zle_trans with ([|ih|] * base); auto with zarith.
unfold phi2; case (phi_bounded il); auto with zarith.
intros ih1 il1.
change [||WW ih1 il1||] with (phi2 ih1 il1).
intros Hihl1.
generalize (spec_sub_c il il1).
case sub31c; intros il2 Hil2.
simpl interp_carry in Hil2.
generalize (spec_compare ih ih1); case compare31.
unfold interp_carry.
intros H1; split.
rewrite Zpower_2, <- Hihl1.
unfold phi2; ring[Hil2 H1].
replace [|il2|] with (phi2 ih il - phi2 ih1 il1).
rewrite Hihl1.
rewrite <-Hbin in Hs2; auto with zarith.
unfold phi2; rewrite H1, Hil2; ring.
unfold interp_carry.
intros H1; contradict Hs1.
apply Zlt_not_le; rewrite Zpower_2, <-Hihl1.
unfold phi2.
case (phi_bounded il); intros _ H2.
apply Zlt_le_trans with (([|ih|] + 1) * base + 0).
rewrite Zmult_plus_distr_l, Zplus_0_r; auto with zarith.
case (phi_bounded il1); intros H3 _.
apply Zplus_le_compat; auto with zarith.
unfold interp_carry; change (1 * 2 ^ Z_of_nat size) with base.
rewrite Zpower_2, <- Hihl1, Hil2.
intros H1.
case (Zle_lt_or_eq ([|ih1|] + 1) ([|ih|])); auto with zarith.
intros H2; contradict Hs2; apply Zle_not_lt.
replace (([|s|] + 1) ^ 2) with (phi2 ih1 il1 + 2 * [|s|] + 1).
unfold phi2.
case (phi_bounded il); intros Hpil _.
assert (Hl1l: [|il1|] <= [|il|]).
case (phi_bounded il2); rewrite Hil2; auto with zarith.
assert ([|ih1|] * base + 2 * [|s|] + 1 <= [|ih|] * base); auto with zarith.
case (phi_bounded s); change (2 ^ Z_of_nat size) with base; intros _ Hps.
case (phi_bounded ih1); intros Hpih1 _; auto with zarith.
apply Zle_trans with (([|ih1|] + 2) * base); auto with zarith.
rewrite Zmult_plus_distr_l.
assert (2 * [|s|] + 1 <= 2 * base); auto with zarith.
rewrite Hihl1, Hbin; auto.
intros H2; split.
unfold phi2; rewrite <- H2; ring.
replace (base + ([|il|] - [|il1|])) with (phi2 ih il - ([|s|] * [|s|])).
rewrite <-Hbin in Hs2; auto with zarith.
rewrite <- Hihl1; unfold phi2; rewrite <- H2; ring.
unfold interp_carry in Hil2 |- *.
unfold interp_carry; change (1 * 2 ^ Z_of_nat size) with base.
assert (Hsih: [|ih - 1|] = [|ih|] - 1).
rewrite spec_sub, Zmod_small; auto; change [|1|] with 1.
case (phi_bounded ih); intros H1 H2.
generalize Hih; change (2 ^ Z_of_nat size / 4) with 536870912.
split; auto with zarith.
generalize (spec_compare (ih - 1) ih1); case compare31.
rewrite Hsih.
intros H1; split.
rewrite Zpower_2, <- Hihl1.
unfold phi2; rewrite <-H1.
apply trans_equal with ([|ih|] * base + [|il1|] + ([|il|] - [|il1|])).
ring.
rewrite <-Hil2.
change (2 ^ Z_of_nat size) with base; ring.
replace [|il2|] with (phi2 ih il - phi2 ih1 il1).
rewrite Hihl1.
rewrite <-Hbin in Hs2; auto with zarith.
unfold phi2.
rewrite <-H1.
ring_simplify.
apply trans_equal with (base + ([|il|] - [|il1|])).
ring.
rewrite <-Hil2.
change (2 ^ Z_of_nat size) with base; ring.
rewrite Hsih; intros H1.
assert (He: [|ih|] = [|ih1|]).
apply Zle_antisym; auto with zarith.
case (Zle_or_lt [|ih1|] [|ih|]); auto; intros H2.
contradict Hs1; apply Zlt_not_le; rewrite Zpower_2, <-Hihl1.
unfold phi2.
case (phi_bounded il); change (2 ^ Z_of_nat size) with base;
intros _ Hpil1.
apply Zlt_le_trans with (([|ih|] + 1) * base).
rewrite Zmult_plus_distr_l, Zmult_1_l; auto with zarith.
case (phi_bounded il1); intros Hpil2 _.
apply Zle_trans with (([|ih1|]) * base); auto with zarith.
rewrite Zpower_2, <-Hihl1; unfold phi2; rewrite <-He.
contradict Hs1; apply Zlt_not_le; rewrite Zpower_2, <-Hihl1.
unfold phi2; rewrite He.
assert (phi il - phi il1 < 0); auto with zarith.
rewrite <-Hil2.
case (phi_bounded il2); auto with zarith.
intros H1.
rewrite Zpower_2, <-Hihl1.
case (Zle_lt_or_eq ([|ih1|] + 2) [|ih|]); auto with zarith.
intros H2; contradict Hs2; apply Zle_not_lt.
replace (([|s|] + 1) ^ 2) with (phi2 ih1 il1 + 2 * [|s|] + 1).
unfold phi2.
assert ([|ih1|] * base + 2 * phi s + 1 <= [|ih|] * base + ([|il|] - [|il1|]));
auto with zarith.
rewrite <-Hil2.
change (-1 * 2 ^ Z_of_nat size) with (-base).
case (phi_bounded il2); intros Hpil2 _.
apply Zle_trans with ([|ih|] * base + - base); auto with zarith.
case (phi_bounded s); change (2 ^ Z_of_nat size) with base; intros _ Hps.
assert (2 * [|s|] + 1 <= 2 * base); auto with zarith.
apply Zle_trans with ([|ih1|] * base + 2 * base); auto with zarith.
assert (Hi: ([|ih1|] + 3) * base <= [|ih|] * base); auto with zarith.
rewrite Zmult_plus_distr_l in Hi; auto with zarith.
rewrite Hihl1, Hbin; auto.
intros H2; unfold phi2; rewrite <-H2.
split.
replace [|il|] with (([|il|] - [|il1|]) + [|il1|]); try ring.
rewrite <-Hil2.
change (-1 * 2 ^ Z_of_nat size) with (-base); ring.
replace (base + [|il2|]) with (phi2 ih il - phi2 ih1 il1).
rewrite Hihl1.
rewrite <-Hbin in Hs2; auto with zarith.
unfold phi2; rewrite <-H2.
replace [|il|] with (([|il|] - [|il1|]) + [|il1|]); try ring.
rewrite <-Hil2.
change (-1 * 2 ^ Z_of_nat size) with (-base); ring.
Qed.
(** [iszero] *)
Let w_eq0 := int31_op.(znz_eq0).
Lemma spec_eq0 : forall x, w_eq0 x = true -> [|x|] = 0.
Proof.
clear; unfold w_eq0, znz_eq0; simpl.
unfold compare31; simpl; intros.
change [|0|] with 0 in H.
apply Zcompare_Eq_eq.
now destruct ([|x|] ?= 0).
Qed.
(* Even *)
Let w_is_even := int31_op.(znz_is_even).
Lemma spec_is_even : forall x,
if w_is_even x then [|x|] mod 2 = 0 else [|x|] mod 2 = 1.
Proof.
unfold w_is_even; simpl; intros.
generalize (spec_div x 2).
destruct (x/2)%int31 as (q,r); intros.
unfold compare31.
change [|2|] with 2 in H.
change [|0|] with 0.
destruct H; auto with zarith.
replace ([|x|] mod 2) with [|r|].
destruct H; auto with zarith.
case_eq ([|r|] ?= 0)%Z; intros.
apply Zcompare_Eq_eq; auto.
change ([|r|] < 0)%Z in H; auto with zarith.
change ([|r|] > 0)%Z in H; auto with zarith.
apply Zmod_unique with [|q|]; auto with zarith.
Qed.
Definition int31_spec : znz_spec int31_op.
split.
exact phi_bounded.
exact positive_to_int31_spec.
exact spec_zdigits.
exact spec_more_than_1_digit.
exact spec_0.
exact spec_1.
exact spec_Bm1.
exact spec_compare.
exact spec_eq0.
exact spec_opp_c.
exact spec_opp.
exact spec_opp_carry.
exact spec_succ_c.
exact spec_add_c.
exact spec_add_carry_c.
exact spec_succ.
exact spec_add.
exact spec_add_carry.
exact spec_pred_c.
exact spec_sub_c.
exact spec_sub_carry_c.
exact spec_pred.
exact spec_sub.
exact spec_sub_carry.
exact spec_mul_c.
exact spec_mul.
exact spec_square_c.
exact spec_div21.
intros; apply spec_div; auto.
exact spec_div.
intros; unfold int31_op; simpl; apply spec_mod; auto.
exact spec_mod.
intros; apply spec_gcd; auto.
exact spec_gcd.
exact spec_head00.
exact spec_head0.
exact spec_tail00.
exact spec_tail0.
exact spec_add_mul_div.
exact spec_pos_mod.
exact spec_is_even.
exact spec_sqrt2.
exact spec_sqrt.
Qed.
End Int31_Spec.
Module Int31Cyclic <: CyclicType.
Definition w := int31.
Definition w_op := int31_op.
Definition w_spec := int31_spec.
End Int31Cyclic.
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4BB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__NOR4BB_FUNCTIONAL_PP_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nor4bb (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , nor0_out, C_N, D_N );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4BB_FUNCTIONAL_PP_V |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : 16 by 32 dual port RAM
// File : ram_16x32_dp.v
// Author : Jim Macleod
// Created : 06-April-2005
// RCS File : $Source: /u/Maxwell/hdl/vga/RCS/ram_16x32_dp.v,v $
// Status : $Id: ram_16x32_dp.v,v 1.1 2005/10/11 21:14:15 fbruno Exp fbruno $
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
/////////////////////////////////////////////////////////////////////////////////
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log: ram_16x32_dp.v,v $
// Revision 1.1 2005/10/11 21:14:15 fbruno
// Initial revision
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module ram_16x32_dp
(
input [15:0] data,
input wren,
input [4:0] wraddress,
input [4:0] rdaddress,
input wrclock,
input rdclock,
output reg [15:0] q
);
reg [15:0] mem_a [0:31];
always @(posedge wrclock) if(wren) mem_a[wraddress] <= data;
always @(posedge rdclock) q <= mem_a[rdaddress];
endmodule
|
/*
* Copyright (c) 2013, Quan Nguyen
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`include "consts.vh"
module branch_jump (
output branch_taken,
output [31:0] branch_target,
output jump,
output [31:0] jump_target,
input [31:0] inst,
input [31:0] pc,
input [31:0] rd1,
input [31:0] alu_out
);
wire [6:0] opcode = inst[6:0];
wire [2:0] funct3 = inst[9:7];
wire [11:0] split_imm = {inst[31:27], inst[16:10]};
wire [31:0] sext_split_imm = split_imm[11] ? {20'hFFFFF, split_imm} : {20'h0, split_imm};
assign jump = (opcode == `OPCODE_J ||
opcode == `OPCODE_JAL ||
opcode == `OPCODE_JALR);
wire [31:0] j_offset = inst[31] ? {6'h3F, inst[31:7], 1'b0} : {6'h0, inst[31:7], 1'b0};
assign jump_target = (opcode == `OPCODE_J || opcode == `OPCODE_JAL) ? j_offset + pc : rd1;
/* branch */
assign branch_target = pc + ($signed(sext_split_imm) << 1);
reg branch_sat;
always @ (*) begin
case (funct3)
`F3_BEQ: branch_sat = (alu_out == 0);
`F3_BNE: branch_sat = (alu_out != 0);
`F3_BLT: branch_sat = (alu_out == 1);
`F3_BGE: branch_sat = (alu_out != 1);
`F3_BLTU: branch_sat = (alu_out == 1);
`F3_BGEU: branch_sat = (alu_out != 1);
default: branch_sat = 0;
endcase
end
assign branch_taken = branch_sat && (opcode == `OPCODE_BRANCH);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DECAP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__DECAP_BEHAVIORAL_PP_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__decap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DECAP_BEHAVIORAL_PP_V |
module pong16 (sys_clk,
rst_n,
dm_sel,
ramadr,
ramwe,
ramre,
dbus_in,
vid_sync_o,
vid_o,
audio_o
);
//INPUTS
input logic sys_clk;
input logic rst_n;
input wire dm_sel;
input wire ramwe;
input wire ramre;
input wire [7:0] ramadr;
input [7:0] dbus_in;
//OUTPUTS
output vid_sync_o;
output vid_o;
output audio_o;
`include "xb_adr_pack.vh"
//localparam PAD0_ADDR = 8'hE0;
//localparam PAD1_ADDR = 8'hE1;
//localparam PNGCR_ADDR = 8'hE2;
wire vid_sync;
wire vid;
reg vid_sync_o;
reg vid_o;
reg rst_clk=0;
always @(posedge sys_clk) begin
rst_clk <= ~rst_clk;
end
reg[7:0] PAD0;
reg[7:0] PAD1;
reg DEMO_MODE;
wire serv_ball;
wire game_rst;
reg[3:0] serv_ball_cnt;
reg[3:0] game_rst_cnt;
reg[1:0] ball_speed;
assign pad0_sel = (dm_sel && ramadr == PAD0_ADDR);
assign pad1_sel = (dm_sel && ramadr == PAD1_ADDR);
assign pngcr_sel = (dm_sel && ramadr == PNGCR_ADDR);
assign pad0_we = pad0_sel & ramwe;
assign pad1_we = pad1_sel & ramwe;
assign pngcr_we = pngcr_sel & ramwe;
always @(posedge sys_clk) begin
if(!rst_n) begin
PAD0 <= 100;
end else if( pad0_we) begin
PAD0 <= dbus_in ;
end
end
always @(posedge sys_clk) begin
if(!rst_n) begin
PAD1 <= 100;
end else if( pad1_we) begin
PAD1 <= dbus_in ;
end
end
//Serve the Ball
assign serv_ball = | serv_ball_cnt;
always @(posedge sys_clk) begin
if(!rst_n) begin
serv_ball_cnt <= 0;
end else begin
serv_ball_cnt <= (pngcr_we && dbus_in[1] ) ? 10 : (serv_ball_cnt != 0) ? serv_ball_cnt-1 : 0;
end
end
//Game reset
assign game_rst = | game_rst_cnt;
always @(posedge sys_clk) begin
if(!rst_n) begin
game_rst_cnt <= 0;
end else begin
game_rst_cnt <= (pngcr_we && dbus_in[0] ) ? 10 : (game_rst_cnt != 0) ? game_rst_cnt-1 : 0;
end
end
//Ball Speed PNGCR[4] sets ball speed to 2 to 1
always @(posedge sys_clk) begin
if(!rst_n) begin
ball_speed <= 2'b01;
end else if( pngcr_we) begin
ball_speed <= (dbus_in[4]==1) ? 2'b10 : 2'b01;
end
end
// DEMO MODE
always @(posedge sys_clk) begin
if(!rst_n) begin
DEMO_MODE <= 1;
end else if( pngcr_we) begin
DEMO_MODE <= dbus_in[7];
end
end
reg[23:0] cntr;
reg rst_na;
always @(posedge rst_clk) begin
if(~rst_n) begin
cntr <= 400;
end else begin
cntr <= (cntr!=0) ? cntr-1 : 0;
end
end
always @(negedge rst_clk) begin
if(~rst_n) begin
rst_na <= 1'b1;
end else begin
rst_na <= (cntr>10 && cntr <200) ? 1'b0 : 1'b1;
end
end
always @(posedge sys_clk) begin
vid_sync_o <= vid_sync;
vid_o <= vid;
end
wire[8:0] x,y;
wire vid_time;
//Video timing logic
//
vid_timer16 v_timer(.clk (sys_clk),
.rst_n (rst_na),
.vid_sync (vid_sync),
.vid_time (vid_time),
.x (x),
.y (y)
);
//Video driver
//
vid_driver v_drvr(.clk (sys_clk),
.rst_n (rst_na),
.vid_time (vid_time),
.x (x),
.y (y[8:1]),
.vid (vid),
.audio_o (audio_o),
.padl0 (PAD0),
.padl1 (PAD1),
.DEMO_MODE (DEMO_MODE),
.serv_ball (serv_ball),
.game_rst (game_rst),
.ball_speed (ball_speed)
);
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file WR_FLASH_FIFO.v when simulating
// the core, WR_FLASH_FIFO. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module WR_FLASH_FIFO(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
prog_full
);
input rst;
input wr_clk;
input rd_clk;
input [255 : 0] din;
input wr_en;
input rd_en;
output [31 : 0] dout;
output full;
output empty;
output prog_full;
// synthesis translate_off
FIFO_GENERATOR_V8_4 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(256),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(32),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(2),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(2),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(2),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(385),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(384),
.C_PROG_FULL_TYPE(1),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(12),
.C_RD_DEPTH(4096),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(12),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(9),
.C_WR_DEPTH(512),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(9),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.PROG_FULL(prog_full),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
// soc_system_mm_interconnect_6.v
// This file was auto-generated from altera_merlin_interconnect_wrapper_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 13.1 162 at 2014.12.19.15:55:08
`timescale 1 ps / 1 ps
module soc_system_mm_interconnect_6 (
input wire sdram_pll_outclk0_clk, // sdram_pll_outclk0.clk
input wire sdram_clockCrossing_Bridge_m0_reset_reset_bridge_in_reset_reset, // sdram_clockCrossing_Bridge_m0_reset_reset_bridge_in_reset.reset
input wire [25:0] sdram_clockCrossing_Bridge_m0_address, // sdram_clockCrossing_Bridge_m0.address
output wire sdram_clockCrossing_Bridge_m0_waitrequest, // .waitrequest
input wire [3:0] sdram_clockCrossing_Bridge_m0_burstcount, // .burstcount
input wire [3:0] sdram_clockCrossing_Bridge_m0_byteenable, // .byteenable
input wire sdram_clockCrossing_Bridge_m0_read, // .read
output wire [31:0] sdram_clockCrossing_Bridge_m0_readdata, // .readdata
output wire sdram_clockCrossing_Bridge_m0_readdatavalid, // .readdatavalid
input wire sdram_clockCrossing_Bridge_m0_write, // .write
input wire [31:0] sdram_clockCrossing_Bridge_m0_writedata, // .writedata
input wire sdram_clockCrossing_Bridge_m0_debugaccess, // .debugaccess
output wire [24:0] sdram_s1_address, // sdram_s1.address
output wire sdram_s1_write, // .write
output wire sdram_s1_read, // .read
input wire [15:0] sdram_s1_readdata, // .readdata
output wire [15:0] sdram_s1_writedata, // .writedata
output wire [1:0] sdram_s1_byteenable, // .byteenable
input wire sdram_s1_readdatavalid, // .readdatavalid
input wire sdram_s1_waitrequest, // .waitrequest
output wire sdram_s1_chipselect // .chipselect
);
wire sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_waitrequest; // sdram_clockCrossing_Bridge_m0_translator_avalon_universal_master_0_agent:av_waitrequest -> sdram_clockCrossing_Bridge_m0_translator:uav_waitrequest
wire [5:0] sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_burstcount; // sdram_clockCrossing_Bridge_m0_translator:uav_burstcount -> sdram_clockCrossing_Bridge_m0_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_writedata; // sdram_clockCrossing_Bridge_m0_translator:uav_writedata -> sdram_clockCrossing_Bridge_m0_translator_avalon_universal_master_0_agent:av_writedata
wire [25:0] sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_address; // sdram_clockCrossing_Bridge_m0_translator:uav_address -> sdram_clockCrossing_Bridge_m0_translator_avalon_universal_master_0_agent:av_address
wire sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_lock; // sdram_clockCrossing_Bridge_m0_translator:uav_lock -> sdram_clockCrossing_Bridge_m0_translator_avalon_universal_master_0_agent:av_lock
wire sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_write; // sdram_clockCrossing_Bridge_m0_translator:uav_write -> sdram_clockCrossing_Bridge_m0_translator_avalon_universal_master_0_agent:av_write
wire sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_read; // sdram_clockCrossing_Bridge_m0_translator:uav_read -> sdram_clockCrossing_Bridge_m0_translator_avalon_universal_master_0_agent:av_read
wire [31:0] sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_readdata; // sdram_clockCrossing_Bridge_m0_translator_avalon_universal_master_0_agent:av_readdata -> sdram_clockCrossing_Bridge_m0_translator:uav_readdata
wire sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_debugaccess; // sdram_clockCrossing_Bridge_m0_translator:uav_debugaccess -> sdram_clockCrossing_Bridge_m0_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_byteenable; // sdram_clockCrossing_Bridge_m0_translator:uav_byteenable -> sdram_clockCrossing_Bridge_m0_translator_avalon_universal_master_0_agent:av_byteenable
wire sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_readdatavalid; // sdram_clockCrossing_Bridge_m0_translator_avalon_universal_master_0_agent:av_readdatavalid -> sdram_clockCrossing_Bridge_m0_translator:uav_readdatavalid
wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> sdram_clockCrossing_Bridge_m0_translator_avalon_universal_master_0_agent:rp_endofpacket
wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> sdram_clockCrossing_Bridge_m0_translator_avalon_universal_master_0_agent:rp_valid
wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> sdram_clockCrossing_Bridge_m0_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [98:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> sdram_clockCrossing_Bridge_m0_translator_avalon_universal_master_0_agent:rp_data
wire [0:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> sdram_clockCrossing_Bridge_m0_translator_avalon_universal_master_0_agent:rp_channel
wire rsp_xbar_mux_src_ready; // sdram_clockCrossing_Bridge_m0_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready
wire sdram_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sdram_s1_translator:uav_waitrequest -> sdram_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [1:0] sdram_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // sdram_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> sdram_s1_translator:uav_burstcount
wire [15:0] sdram_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // sdram_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> sdram_s1_translator:uav_writedata
wire [25:0] sdram_s1_translator_avalon_universal_slave_0_agent_m0_address; // sdram_s1_translator_avalon_universal_slave_0_agent:m0_address -> sdram_s1_translator:uav_address
wire sdram_s1_translator_avalon_universal_slave_0_agent_m0_write; // sdram_s1_translator_avalon_universal_slave_0_agent:m0_write -> sdram_s1_translator:uav_write
wire sdram_s1_translator_avalon_universal_slave_0_agent_m0_lock; // sdram_s1_translator_avalon_universal_slave_0_agent:m0_lock -> sdram_s1_translator:uav_lock
wire sdram_s1_translator_avalon_universal_slave_0_agent_m0_read; // sdram_s1_translator_avalon_universal_slave_0_agent:m0_read -> sdram_s1_translator:uav_read
wire [15:0] sdram_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // sdram_s1_translator:uav_readdata -> sdram_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire sdram_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sdram_s1_translator:uav_readdatavalid -> sdram_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sdram_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sdram_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sdram_s1_translator:uav_debugaccess
wire [1:0] sdram_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // sdram_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> sdram_s1_translator:uav_byteenable
wire sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sdram_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // sdram_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sdram_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [81:0] sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // sdram_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sdram_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sdram_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sdram_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sdram_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [81:0] sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sdram_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sdram_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sdram_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
wire [17:0] sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sdram_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
wire sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> sdram_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid; // sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> sdram_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [17:0] sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data; // sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> sdram_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready; // sdram_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
wire sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_endofpacket; // sdram_clockCrossing_Bridge_m0_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
wire sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_valid; // sdram_clockCrossing_Bridge_m0_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
wire sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_startofpacket; // sdram_clockCrossing_Bridge_m0_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
wire [98:0] sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_data; // sdram_clockCrossing_Bridge_m0_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
wire sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> sdram_clockCrossing_Bridge_m0_translator_avalon_universal_master_0_agent:cp_ready
wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket
wire addr_router_src_valid; // addr_router:src_valid -> cmd_xbar_demux:sink_valid
wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket
wire [98:0] addr_router_src_data; // addr_router:src_data -> cmd_xbar_demux:sink_data
wire [0:0] addr_router_src_channel; // addr_router:src_channel -> cmd_xbar_demux:sink_channel
wire addr_router_src_ready; // cmd_xbar_demux:sink_ready -> addr_router:src_ready
wire sdram_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sdram_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
wire sdram_s1_translator_avalon_universal_slave_0_agent_rp_valid; // sdram_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
wire sdram_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sdram_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
wire [80:0] sdram_s1_translator_avalon_universal_slave_0_agent_rp_data; // sdram_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
wire sdram_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> sdram_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire burst_adapter_source0_endofpacket; // burst_adapter:source0_endofpacket -> sdram_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire burst_adapter_source0_valid; // burst_adapter:source0_valid -> sdram_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire burst_adapter_source0_startofpacket; // burst_adapter:source0_startofpacket -> sdram_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [80:0] burst_adapter_source0_data; // burst_adapter:source0_data -> sdram_s1_translator_avalon_universal_slave_0_agent:cp_data
wire burst_adapter_source0_ready; // sdram_s1_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready
wire [0:0] burst_adapter_source0_channel; // burst_adapter:source0_channel -> sdram_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
wire [98:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
wire [0:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
wire [98:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
wire [0:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
wire id_router_src_endofpacket; // id_router:src_endofpacket -> width_adapter:in_endofpacket
wire id_router_src_valid; // id_router:src_valid -> width_adapter:in_valid
wire id_router_src_startofpacket; // id_router:src_startofpacket -> width_adapter:in_startofpacket
wire [80:0] id_router_src_data; // id_router:src_data -> width_adapter:in_data
wire [0:0] id_router_src_channel; // id_router:src_channel -> width_adapter:in_channel
wire id_router_src_ready; // width_adapter:in_ready -> id_router:src_ready
wire width_adapter_src_endofpacket; // width_adapter:out_endofpacket -> rsp_xbar_demux:sink_endofpacket
wire width_adapter_src_valid; // width_adapter:out_valid -> rsp_xbar_demux:sink_valid
wire width_adapter_src_startofpacket; // width_adapter:out_startofpacket -> rsp_xbar_demux:sink_startofpacket
wire [98:0] width_adapter_src_data; // width_adapter:out_data -> rsp_xbar_demux:sink_data
wire width_adapter_src_ready; // rsp_xbar_demux:sink_ready -> width_adapter:out_ready
wire [0:0] width_adapter_src_channel; // width_adapter:out_channel -> rsp_xbar_demux:sink_channel
wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> width_adapter_001:in_endofpacket
wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> width_adapter_001:in_valid
wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> width_adapter_001:in_startofpacket
wire [98:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> width_adapter_001:in_data
wire [0:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> width_adapter_001:in_channel
wire cmd_xbar_mux_src_ready; // width_adapter_001:in_ready -> cmd_xbar_mux:src_ready
wire width_adapter_001_src_endofpacket; // width_adapter_001:out_endofpacket -> burst_adapter:sink0_endofpacket
wire width_adapter_001_src_valid; // width_adapter_001:out_valid -> burst_adapter:sink0_valid
wire width_adapter_001_src_startofpacket; // width_adapter_001:out_startofpacket -> burst_adapter:sink0_startofpacket
wire [80:0] width_adapter_001_src_data; // width_adapter_001:out_data -> burst_adapter:sink0_data
wire width_adapter_001_src_ready; // burst_adapter:sink0_ready -> width_adapter_001:out_ready
wire [0:0] width_adapter_001_src_channel; // width_adapter_001:out_channel -> burst_adapter:sink0_channel
altera_merlin_master_translator #(
.AV_ADDRESS_W (26),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (4),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (26),
.UAV_BURSTCOUNT_W (6),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (1),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) sdram_clockcrossing_bridge_m0_translator (
.clk (sdram_pll_outclk0_clk), // clk.clk
.reset (sdram_clockCrossing_Bridge_m0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (sdram_clockCrossing_Bridge_m0_address), // avalon_anti_master_0.address
.av_waitrequest (sdram_clockCrossing_Bridge_m0_waitrequest), // .waitrequest
.av_burstcount (sdram_clockCrossing_Bridge_m0_burstcount), // .burstcount
.av_byteenable (sdram_clockCrossing_Bridge_m0_byteenable), // .byteenable
.av_read (sdram_clockCrossing_Bridge_m0_read), // .read
.av_readdata (sdram_clockCrossing_Bridge_m0_readdata), // .readdata
.av_readdatavalid (sdram_clockCrossing_Bridge_m0_readdatavalid), // .readdatavalid
.av_write (sdram_clockCrossing_Bridge_m0_write), // .write
.av_writedata (sdram_clockCrossing_Bridge_m0_writedata), // .writedata
.av_debugaccess (sdram_clockCrossing_Bridge_m0_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (25),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (26),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sdram_s1_translator (
.clk (sdram_pll_outclk0_clk), // clk.clk
.reset (sdram_clockCrossing_Bridge_m0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sdram_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sdram_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sdram_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sdram_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sdram_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sdram_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sdram_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sdram_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sdram_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sdram_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sdram_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sdram_s1_address), // avalon_anti_slave_0.address
.av_write (sdram_s1_write), // .write
.av_read (sdram_s1_read), // .read
.av_readdata (sdram_s1_readdata), // .readdata
.av_writedata (sdram_s1_writedata), // .writedata
.av_byteenable (sdram_s1_byteenable), // .byteenable
.av_readdatavalid (sdram_s1_readdatavalid), // .readdatavalid
.av_waitrequest (sdram_s1_waitrequest), // .waitrequest
.av_chipselect (sdram_s1_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BEGIN_BURST (82),
.PKT_BURSTWRAP_H (74),
.PKT_BURSTWRAP_L (74),
.PKT_BURST_SIZE_H (77),
.PKT_BURST_SIZE_L (75),
.PKT_BURST_TYPE_H (79),
.PKT_BURST_TYPE_L (78),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (68),
.PKT_ADDR_H (61),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (62),
.PKT_TRANS_POSTED (63),
.PKT_TRANS_WRITE (64),
.PKT_TRANS_READ (65),
.PKT_TRANS_LOCK (66),
.PKT_TRANS_EXCLUSIVE (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (84),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (85),
.PKT_THREAD_ID_H (86),
.PKT_THREAD_ID_L (86),
.PKT_CACHE_H (93),
.PKT_CACHE_L (90),
.PKT_DATA_SIDEBAND_H (81),
.PKT_DATA_SIDEBAND_L (81),
.PKT_QOS_H (83),
.PKT_QOS_L (83),
.PKT_ADDR_SIDEBAND_H (80),
.PKT_ADDR_SIDEBAND_L (80),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_ORI_BURST_SIZE_H (98),
.ST_DATA_W (99),
.ST_CHANNEL_W (1),
.AV_BURSTCOUNT_W (6),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_agent (
.clk (sdram_pll_outclk0_clk), // clk.clk
.reset (sdram_clockCrossing_Bridge_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_address), // av.address
.av_write (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_write), // .write
.av_read (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_read), // .read
.av_writedata (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (rsp_xbar_mux_src_valid), // rp.valid
.rp_data (rsp_xbar_mux_src_data), // .data
.rp_channel (rsp_xbar_mux_src_channel), // .channel
.rp_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_xbar_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (64),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_ADDR_H (43),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (44),
.PKT_TRANS_POSTED (45),
.PKT_TRANS_WRITE (46),
.PKT_TRANS_READ (47),
.PKT_TRANS_LOCK (48),
.PKT_SRC_ID_H (66),
.PKT_SRC_ID_L (66),
.PKT_DEST_ID_H (67),
.PKT_DEST_ID_L (67),
.PKT_BURSTWRAP_H (56),
.PKT_BURSTWRAP_L (56),
.PKT_BYTE_CNT_H (55),
.PKT_BYTE_CNT_L (50),
.PKT_PROTECTION_H (71),
.PKT_PROTECTION_L (69),
.PKT_RESPONSE_STATUS_H (77),
.PKT_RESPONSE_STATUS_L (76),
.PKT_BURST_SIZE_H (59),
.PKT_BURST_SIZE_L (57),
.PKT_ORI_BURST_SIZE_L (78),
.PKT_ORI_BURST_SIZE_H (80),
.ST_CHANNEL_W (1),
.ST_DATA_W (81),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sdram_s1_translator_avalon_universal_slave_0_agent (
.clk (sdram_pll_outclk0_clk), // clk.clk
.reset (sdram_clockCrossing_Bridge_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sdram_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sdram_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sdram_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sdram_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sdram_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sdram_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sdram_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sdram_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sdram_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sdram_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sdram_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sdram_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sdram_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sdram_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sdram_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sdram_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (burst_adapter_source0_ready), // cp.ready
.cp_valid (burst_adapter_source0_valid), // .valid
.cp_data (burst_adapter_source0_data), // .data
.cp_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (burst_adapter_source0_channel), // .channel
.rf_sink_ready (sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (82),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (sdram_pll_outclk0_clk), // clk.clk
.reset (sdram_clockCrossing_Bridge_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (18),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo (
.clk (sdram_pll_outclk0_clk), // clk.clk
.reset (sdram_clockCrossing_Bridge_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // in.data
.in_valid (sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.in_ready (sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // .ready
.out_data (sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // out.data
.out_valid (sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.out_ready (sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
soc_system_mm_interconnect_6_addr_router addr_router (
.sink_ready (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (sdram_clockcrossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (sdram_pll_outclk0_clk), // clk.clk
.reset (sdram_clockCrossing_Bridge_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (addr_router_src_ready), // src.ready
.src_valid (addr_router_src_valid), // .valid
.src_data (addr_router_src_data), // .data
.src_channel (addr_router_src_channel), // .channel
.src_startofpacket (addr_router_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_6_id_router id_router (
.sink_ready (sdram_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sdram_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sdram_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sdram_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sdram_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (sdram_pll_outclk0_clk), // clk.clk
.reset (sdram_clockCrossing_Bridge_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (id_router_src_ready), // src.ready
.src_valid (id_router_src_valid), // .valid
.src_data (id_router_src_data), // .data
.src_channel (id_router_src_channel), // .channel
.src_startofpacket (id_router_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_src_endofpacket) // .endofpacket
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (43),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (64),
.PKT_BYTE_CNT_H (55),
.PKT_BYTE_CNT_L (50),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (59),
.PKT_BURST_SIZE_L (57),
.PKT_BURST_TYPE_H (61),
.PKT_BURST_TYPE_L (60),
.PKT_BURSTWRAP_H (56),
.PKT_BURSTWRAP_L (56),
.PKT_TRANS_COMPRESSED_READ (44),
.PKT_TRANS_WRITE (46),
.PKT_TRANS_READ (47),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (81),
.ST_CHANNEL_W (1),
.OUT_BYTE_CNT_H (51),
.OUT_BURSTWRAP_H (56),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (1),
.BURSTWRAP_CONST_VALUE (1)
) burst_adapter (
.clk (sdram_pll_outclk0_clk), // cr0.clk
.reset (sdram_clockCrossing_Bridge_m0_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (width_adapter_001_src_valid), // sink0.valid
.sink0_data (width_adapter_001_src_data), // .data
.sink0_channel (width_adapter_001_src_channel), // .channel
.sink0_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket
.sink0_endofpacket (width_adapter_001_src_endofpacket), // .endofpacket
.sink0_ready (width_adapter_001_src_ready), // .ready
.source0_valid (burst_adapter_source0_valid), // source0.valid
.source0_data (burst_adapter_source0_data), // .data
.source0_channel (burst_adapter_source0_channel), // .channel
.source0_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (burst_adapter_source0_ready) // .ready
);
soc_system_mm_interconnect_6_cmd_xbar_demux cmd_xbar_demux (
.clk (sdram_pll_outclk0_clk), // clk.clk
.reset (sdram_clockCrossing_Bridge_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (addr_router_src_ready), // sink.ready
.sink_channel (addr_router_src_channel), // .channel
.sink_data (addr_router_src_data), // .data
.sink_startofpacket (addr_router_src_startofpacket), // .startofpacket
.sink_endofpacket (addr_router_src_endofpacket), // .endofpacket
.sink_valid (addr_router_src_valid), // .valid
.src0_ready (cmd_xbar_demux_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_src0_valid), // .valid
.src0_data (cmd_xbar_demux_src0_data), // .data
.src0_channel (cmd_xbar_demux_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_6_cmd_xbar_mux cmd_xbar_mux (
.clk (sdram_pll_outclk0_clk), // clk.clk
.reset (sdram_clockCrossing_Bridge_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_src_ready), // src.ready
.src_valid (cmd_xbar_mux_src_valid), // .valid
.src_data (cmd_xbar_mux_src_data), // .data
.src_channel (cmd_xbar_mux_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src0_valid), // .valid
.sink0_channel (cmd_xbar_demux_src0_channel), // .channel
.sink0_data (cmd_xbar_demux_src0_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_6_cmd_xbar_demux rsp_xbar_demux (
.clk (sdram_pll_outclk0_clk), // clk.clk
.reset (sdram_clockCrossing_Bridge_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (width_adapter_src_ready), // sink.ready
.sink_channel (width_adapter_src_channel), // .channel
.sink_data (width_adapter_src_data), // .data
.sink_startofpacket (width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (width_adapter_src_endofpacket), // .endofpacket
.sink_valid (width_adapter_src_valid), // .valid
.src0_ready (rsp_xbar_demux_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_src0_valid), // .valid
.src0_data (rsp_xbar_demux_src0_data), // .data
.src0_channel (rsp_xbar_demux_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_6_rsp_xbar_mux rsp_xbar_mux (
.clk (sdram_pll_outclk0_clk), // clk.clk
.reset (sdram_clockCrossing_Bridge_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_src_ready), // src.ready
.src_valid (rsp_xbar_mux_src_valid), // .valid
.src_data (rsp_xbar_mux_src_data), // .data
.src_channel (rsp_xbar_mux_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src0_valid), // .valid
.sink0_channel (rsp_xbar_demux_src0_channel), // .channel
.sink0_data (rsp_xbar_demux_src0_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (43),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (55),
.IN_PKT_BYTE_CNT_L (50),
.IN_PKT_TRANS_COMPRESSED_READ (44),
.IN_PKT_BURSTWRAP_H (56),
.IN_PKT_BURSTWRAP_L (56),
.IN_PKT_BURST_SIZE_H (59),
.IN_PKT_BURST_SIZE_L (57),
.IN_PKT_RESPONSE_STATUS_H (77),
.IN_PKT_RESPONSE_STATUS_L (76),
.IN_PKT_TRANS_EXCLUSIVE (49),
.IN_PKT_BURST_TYPE_H (61),
.IN_PKT_BURST_TYPE_L (60),
.IN_PKT_ORI_BURST_SIZE_L (78),
.IN_PKT_ORI_BURST_SIZE_H (80),
.IN_ST_DATA_W (81),
.OUT_PKT_ADDR_H (61),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (73),
.OUT_PKT_BYTE_CNT_L (68),
.OUT_PKT_TRANS_COMPRESSED_READ (62),
.OUT_PKT_BURST_SIZE_H (77),
.OUT_PKT_BURST_SIZE_L (75),
.OUT_PKT_RESPONSE_STATUS_H (95),
.OUT_PKT_RESPONSE_STATUS_L (94),
.OUT_PKT_TRANS_EXCLUSIVE (67),
.OUT_PKT_BURST_TYPE_H (79),
.OUT_PKT_BURST_TYPE_L (78),
.OUT_PKT_ORI_BURST_SIZE_L (96),
.OUT_PKT_ORI_BURST_SIZE_H (98),
.OUT_ST_DATA_W (99),
.ST_CHANNEL_W (1),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1)
) width_adapter (
.clk (sdram_pll_outclk0_clk), // clk.clk
.reset (sdram_clockCrossing_Bridge_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (id_router_src_valid), // sink.valid
.in_channel (id_router_src_channel), // .channel
.in_startofpacket (id_router_src_startofpacket), // .startofpacket
.in_endofpacket (id_router_src_endofpacket), // .endofpacket
.in_ready (id_router_src_ready), // .ready
.in_data (id_router_src_data), // .data
.out_endofpacket (width_adapter_src_endofpacket), // src.endofpacket
.out_data (width_adapter_src_data), // .data
.out_channel (width_adapter_src_channel), // .channel
.out_valid (width_adapter_src_valid), // .valid
.out_ready (width_adapter_src_ready), // .ready
.out_startofpacket (width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (61),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (73),
.IN_PKT_BYTE_CNT_L (68),
.IN_PKT_TRANS_COMPRESSED_READ (62),
.IN_PKT_BURSTWRAP_H (74),
.IN_PKT_BURSTWRAP_L (74),
.IN_PKT_BURST_SIZE_H (77),
.IN_PKT_BURST_SIZE_L (75),
.IN_PKT_RESPONSE_STATUS_H (95),
.IN_PKT_RESPONSE_STATUS_L (94),
.IN_PKT_TRANS_EXCLUSIVE (67),
.IN_PKT_BURST_TYPE_H (79),
.IN_PKT_BURST_TYPE_L (78),
.IN_PKT_ORI_BURST_SIZE_L (96),
.IN_PKT_ORI_BURST_SIZE_H (98),
.IN_ST_DATA_W (99),
.OUT_PKT_ADDR_H (43),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (55),
.OUT_PKT_BYTE_CNT_L (50),
.OUT_PKT_TRANS_COMPRESSED_READ (44),
.OUT_PKT_BURST_SIZE_H (59),
.OUT_PKT_BURST_SIZE_L (57),
.OUT_PKT_RESPONSE_STATUS_H (77),
.OUT_PKT_RESPONSE_STATUS_L (76),
.OUT_PKT_TRANS_EXCLUSIVE (49),
.OUT_PKT_BURST_TYPE_H (61),
.OUT_PKT_BURST_TYPE_L (60),
.OUT_PKT_ORI_BURST_SIZE_L (78),
.OUT_PKT_ORI_BURST_SIZE_H (80),
.OUT_ST_DATA_W (81),
.ST_CHANNEL_W (1),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1)
) width_adapter_001 (
.clk (sdram_pll_outclk0_clk), // clk.clk
.reset (sdram_clockCrossing_Bridge_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_xbar_mux_src_valid), // sink.valid
.in_channel (cmd_xbar_mux_src_channel), // .channel
.in_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.in_ready (cmd_xbar_mux_src_ready), // .ready
.in_data (cmd_xbar_mux_src_data), // .data
.out_endofpacket (width_adapter_001_src_endofpacket), // src.endofpacket
.out_data (width_adapter_001_src_data), // .data
.out_channel (width_adapter_001_src_channel), // .channel
.out_valid (width_adapter_001_src_valid), // .valid
.out_ready (width_adapter_001_src_ready), // .ready
.out_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
endmodule
|
module TOP(CLK, RSTN, UP_ENABLE, UP_ENABLE2, CLEAR);
input CLK,RSTN,UP_ENABLE,UP_ENABLE2,CLEAR;
reg [2:0] up_cnt;
wire is_cnt_four = up_cnt == 4;
always @(posedge CLK or negedge RSTN) begin
if(!RSTN) begin
up_cnt <= 0;
end else if(up_cnt >= 3'd5) begin
up_cnt <= 0;
end else if(CLEAR) begin
up_cnt <= 0;
end else if(UP_ENABLE) begin
up_cnt <= up_cnt + 3'd1;
end else if(UP_ENABLE2) begin
up_cnt <= up_cnt + 3'd1;
end else begin
up_cnt <= up_cnt;
end
end
reg [2:0] up_cnt2;
always @(posedge CLK or negedge RSTN) begin
if(!RSTN) begin
up_cnt2 <= 0;
end else if(up_cnt2 != 3'd5 && up_cnt == 3'd5) begin
up_cnt2 <= up_cnt2 + 3'd1;
end else begin
up_cnt2 <= 0;
end
end
reg [2:0] down_cnt;
always @(posedge CLK or negedge RSTN) begin
if(!RSTN) begin
down_cnt <= 0;
end else if(down_cnt != 3'd0) begin
down_cnt <= down_cnt - 3'd1;
end else begin
down_cnt <= 3'd5;
end
end
reg now;
always @(posedge CLK or negedge RSTN) begin
if(!RSTN) begin
now <= 0;
end else if(up_cnt == 3'd4) begin
now <= 0;
end else if(up_cnt == 3'd2) begin
now <= 1;
end else if((up_cnt == 2) && (up_cnt2 == 2)) begin
now <= 1;
end
end
endmodule
|
//==================================================================================================
// Filename : dlx_de2_115.v
// Created On : 2014-06-27 09:44:21
// Last Modified : 2014-07-22 08:30:36
// Revision :
// Author : Linton Esteves
// Company : LSITEC
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
`include "dlx_de2_115_defines.v"
module dlx_de2_115 (
input CLOCK_50,
input CLOCK_27,
input [3:0] KEY,
input [17:0] SW,
//UART
input UART_RXD,
output UART_TXD,
//LED
output [17:0] LEDR,
output [8:0] LEDG,
//7SEG
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
output [6:0] HEX6,
output [6:0] HEX7,
//LCD
output LCD_RW,
output LCD_EN,
output LCD_RS,
output [7:0] LCD_DATA,
output LCD_ON,
output LCD_BLON,
//GPIO
inout [33:0] GPIO,
// output [35:0] GPIO_0,
// input [35:0] GPIO_1,
//SRAM
`ifdef EXTERNAL_SRAM
output [19:0] SRAM_ADDR,
output SRAM_CE_N,
inout [15:0] SRAM_DQ,
output SRAM_LB_N,
output SRAM_OE_N,
output SRAM_UB_N,
output SRAM_WE_N,
`endif
//SDRAM
inout [31:0] DRAM_DQ, // SDRAM Data bus 16 Bits
output [12:0] DRAM_ADDR, // SDRAM Address bus 12 Bits
output [3:0] DRAM_DQM, // SDRAM Data Mask
output DRAM_WE_N, // SDRAM Write Enable
output DRAM_CAS_N, // SDRAM Column Address Strobe
output DRAM_RAS_N, // SDRAM Row Address Strobe
output DRAM_CS_N, // SDRAM Chip Select
output [1:0] DRAM_BA, // SDRAM Bank Address
output DRAM_CLK, // SDRAM Clock
output DRAM_CKE//, // SDRAM Clock Enable
);
parameter DATA_WIDTH = 32;
parameter DATA_ADDR_WIDTH = 32;
parameter INST_ADDR_WIDTH = 20;
parameter DQM_WIDTH = 4;
parameter BA_WIDTH = 2;
wire boot_rom_rd_en;
wire [INST_ADDR_WIDTH-1:0] boot_rom_addr;
wire [DATA_WIDTH-1:0] boot_rom_rd_data;
//clk rst manager
wire rst_sync_n;
wire clk_out;
wire clk_div2;
wire clk_div4;
wire clk_div8;
wire clk_40;
wire rst_n;
reg [6:0] display_1,
display_2,
display_3,
display_4,
display_5,
display_6,
display_7,
display_8;
`ifndef EXTERNAL_SRAM
wire SRAM_UB_N;
wire SRAM_LB_N;
wire SRAM_CE_N;
wire SRAM_WE_N;
wire SRAM_OE_N;
wire [INST_ADDR_WIDTH-1:0] SRAM_ADDR;
`endif
wire [DATA_WIDTH-1:0] SRAM_WR_DATA;
wire [DATA_WIDTH-1:0] SRAM_RD_DATA;
wire we_gpio;
wire [DATA_WIDTH-1:0] dram_dq_in; // sdram data bus in 32 bits
wire [DATA_WIDTH-1:0] dram_dq_out; // sdram data bus out 32 bits
reg [31:0] count;
wire clk_1;
assign rst_n = KEY[0];
`ifdef EXTERNAL_SRAM
assign SRAM_DQ = !SRAM_OE_N ? {DATA_WIDTH {1'bZ}} : SRAM_WR_DATA;
assign SRAM_RD_DATA = SRAM_DQ;
`endif
assign DRAM_DQ = &DRAM_DQM ? {DATA_WIDTH {1'bZ}} : dram_dq_out;
assign dram_dq_in = DRAM_DQ;
wire [3:0] mode;
`ifdef USE_SDRAM
assign mode = 'ha;
`else
assign mode = 'hb;
`endif
`ifdef TEST_ONLY_SRAM
reg [DATA_WIDTH-1:0] gpio_o;
reg sram_mem_wr_en;
reg sram_mem_rd_en;
reg [DATA_WIDTH-1:0] sram_mem_wr_data;
wire [DATA_WIDTH-1:0] sram_mem_rd_data;
reg [INST_ADDR_WIDTH-1:0] sram_mem_addr;
reg [20:0] sram_count;
reg sram_mem_rd_en_reg;
always @(posedge clk_div8 or negedge rst_n) begin
if (!rst_n) begin
sram_count <= 32'd0;
end
else begin
sram_count <= sram_count + 1'b1;
if(sram_count == 50)begin
sram_mem_wr_en = 1;
sram_mem_rd_en = 0;
sram_mem_addr = count;
sram_mem_wr_data = count + 32'd1;
end
else if (sram_count == 55) begin
sram_mem_wr_en = 0;
sram_mem_rd_en = 1;
sram_mem_addr = count;
sram_mem_wr_data = 32'd0;
end
else if (sram_count == 56) begin
sram_mem_wr_en = 0;
sram_mem_rd_en = 0;
sram_mem_addr = 0;
sram_mem_wr_data = 32'd0;
end
end
end
assign LEDR[0] = sram_mem_rd_en;
assign LEDR[1] = sram_mem_wr_en;
assign we_gpio = 1'b1;
always @(posedge clk_div8 or negedge rst_n) begin
if (!rst_n) begin
gpio_o <= 32'd0;
sram_mem_rd_en_reg <= 0;
end
else begin
sram_mem_rd_en_reg <= sram_mem_rd_en;
if (sram_mem_rd_en_reg)
gpio_o <= sram_mem_rd_data;
end
end
always @(posedge clk_div8 or negedge rst_n) begin
if (!rst_n) begin
count <= 0;
end
else begin
if (sram_count[20] && (sram_count[19:0] == 0))
count <= count + 4;
end
end
sram_ctrl
sram_ctrl_u0
(
.clk(clk_out),
.rst_n(rst_n),
.wr_en(sram_mem_wr_en),
.rd_en(sram_mem_rd_en),
.wr_data(sram_mem_wr_data),
.addr({1'b0,sram_mem_addr[19:0]}),
.rd_data(sram_mem_rd_data),
.sram_ub_n(SRAM_UB_N),
.sram_lb_n(SRAM_LB_N),
.sram_ce_n(SRAM_CE_N),
.sram_we_n(SRAM_WE_N),
.sram_oe_n(SRAM_OE_N),
.sram_addr(SRAM_ADDR),
.sram_wr_data(SRAM_WR_DATA),
.sram_rd_data(SRAM_RD_DATA)
);
// clk_rst_mngr
// clk_rst_mngr_u0
// (
// .clk_in(clk_10),
// .rst_async_n(rst_n),
// .en_clk_div8(0),
// .rst_sync_n(rst_sync_n),
// .clk_out(clk_out),
// .clk_div2(clk_div2),
// .clk_div4(clk_div4),
// .clk_div8(clk_div8),
// .clk_div8_proc(clk_div8_proc)
// );
`else
wire [DATA_WIDTH-1:0] gpio_o;
top
#(
.DATA_WIDTH(DATA_WIDTH),
.DATA_ADDR_WIDTH(DATA_ADDR_WIDTH),
.INST_ADDR_WIDTH(INST_ADDR_WIDTH)
)
top_u0
(/*autoport*/
.clk(clk_10),
.clk_proc(clk_1),
.rst_n(rst_n),
//boot rom memory interface
.boot_rom_rd_en(boot_rom_rd_en),
.boot_rom_addr(boot_rom_addr),
.boot_rom_rd_data(boot_rom_rd_data),
//sram interface
.sram_ub_n(SRAM_UB_N),
.sram_lb_n(SRAM_LB_N),
.sram_ce_n(SRAM_CE_N),
.sram_we_n(SRAM_WE_N),
.sram_oe_n(SRAM_OE_N),
.sram_addr(SRAM_ADDR),
.sram_wr_data(SRAM_WR_DATA),
.sram_rd_data(SRAM_RD_DATA),
//SPRAM interface
.dram_dq_in(dram_dq_in), // sdram data bus in 32 bits
.dram_dq_out(dram_dq_out), // sdram data bus out 32 bits
.dram_addr(DRAM_ADDR), // sdram address bus 12 bits
.dram_dqm(DRAM_DQM), // sdram data mask
.dram_we_n(DRAM_WE_N), // sdram write enable
.dram_cas_n(DRAM_CAS_N), // sdram column address strobe
.dram_ras_n(DRAM_RAS_N), // sdram row address strobe
.dram_cs_n(DRAM_CS_N), // sdram chip select
.dram_ba(DRAM_BA), // sdram bank address
.dram_clk(), // sdram clock
.dram_cke(DRAM_CKE),
// .rst_sync_n(rst_sync_n),
// .clk_out(clk_out),
// .clk_div2(clk_div2),
// .clk_div4(clk_div4),
// .clk_div8(clk_div8),
.gpio_o(gpio_o),
.we_gpio(we_gpio)
);
assign DRAM_CLK = clk_10_3ns_dly;
boot_rom
rom_u0
(
.clk(clk_1),
.rst_n(rst_n),
.rd_ena(boot_rom_rd_en),
.address(boot_rom_addr),
.data(boot_rom_rd_data)
);
`endif
clk_40
clk_10_3ns_delay_u0 (
.inclk0(CLOCK_50),
.c0(clk_10_3ns_dly)
);
clk_10mhz
clk_10_u0 (
.inclk0(CLOCK_50),
.c0(clk_10)
);
clk_1mhz
clk_1_u0 (
.inclk0(CLOCK_50),
.c0(clk_1)
);
// rom
// rom_u0
// (
// .address(boot_rom_addr),
// .clock(clk_div4),
// .data(32'd0),
// .rden(boot_rom_rd_en),
// .wren(1'b0),
// .q(boot_rom_rd_data)
// );
`ifndef EXTERNAL_SRAM
sp_ram
#(
.DATA_WIDTH(16),
.ADDR_WIDTH(10)
)
sp_ram_u0
(
.clk(clk_out),
.rd_ena(!SRAM_CE_N&SRAM_WE_N),
.wr_ena(!SRAM_CE_N&!SRAM_WE_N),
.address(SRAM_ADDR),
.wr_data(SRAM_WR_DATA),
.rd_data(SRAM_RD_DATA)
);
`endif
assign HEX0 = rst_n ? display_1 : 7'd0;
assign HEX1 = rst_n ? display_2 : 7'd0;
assign HEX2 = rst_n ? display_3 : 7'd0;
assign HEX3 = rst_n ? display_4 : 7'd0;
assign HEX4 = rst_n ? display_5 : 7'd0;
assign HEX5 = rst_n ? display_6 : 7'd0;
assign HEX6 = rst_n ? display_7 : 7'd0;
assign HEX7 = rst_n ? display_8 : 7'd0;
always @(posedge clk_1 or negedge rst_n) begin
if (!rst_n) begin
display_1 = 7'b1000000;
display_2 = 7'b1000000;
display_3 = 7'b1000000;
display_4 = 7'b1000000;
display_5 = 7'b1000000;
display_6 = 7'b1000000;
display_7 = 7'b1000000;
display_8 = 7'b1000000;
end
else if (we_gpio) begin
case (gpio_o[3:0])
4'h0: display_1 = 7'b1000000;
4'h1: display_1 = 7'b1111001;
4'h2: display_1 = 7'b0100100;
4'h3: display_1 = 7'b0110000;
4'h4: display_1 = 7'b0011001;
4'h5: display_1 = 7'b0010010;
4'h6: display_1 = 7'b0000010;
4'h7: display_1 = 7'b1111000;
4'h8: display_1 = 7'b0000000;
4'h9: display_1 = 7'b0011000;
4'hA: display_1 = 7'b0001000;
4'hB: display_1 = 7'b0000011;
4'hC: display_1 = 7'b1000110;
4'hD: display_1 = 7'b0100001;
4'hE: display_1 = 7'b0000110;
4'hF: display_1 = 7'b0001110;
default: display_1 = 7'b0110110;
endcase
case (gpio_o[7:4])
4'h0: display_2 = 7'b1000000;
4'h1: display_2 = 7'b1111001;
4'h2: display_2 = 7'b0100100;
4'h3: display_2 = 7'b0110000;
4'h4: display_2 = 7'b0011001;
4'h5: display_2 = 7'b0010010;
4'h6: display_2 = 7'b0000010;
4'h7: display_2 = 7'b1111000;
4'h8: display_2 = 7'b0000000;
4'h9: display_2 = 7'b0011000;
4'hA: display_2 = 7'b0001000;
4'hB: display_2 = 7'b0000011;
4'hC: display_2 = 7'b1000110;
4'hD: display_2 = 7'b0100001;
4'hE: display_2 = 7'b0000110;
4'hF: display_2 = 7'b0001110;
default: display_2 = 7'b0110110;
endcase
case (gpio_o[11:8])
4'h0: display_3 = 7'b1000000;
4'h1: display_3 = 7'b1111001;
4'h2: display_3 = 7'b0100100;
4'h3: display_3 = 7'b0110000;
4'h4: display_3 = 7'b0011001;
4'h5: display_3 = 7'b0010010;
4'h6: display_3 = 7'b0000010;
4'h7: display_3 = 7'b1111000;
4'h8: display_3 = 7'b0000000;
4'h9: display_3 = 7'b0011000;
4'hA: display_3 = 7'b0001000;
4'hB: display_3 = 7'b0000011;
4'hC: display_3 = 7'b1000110;
4'hD: display_3 = 7'b0100001;
4'hE: display_3 = 7'b0000110;
4'hF: display_3 = 7'b0001110;
default: display_3 = 7'b0110110;
endcase
case (gpio_o[15:12])
4'h0: display_4 = 7'b1000000;
4'h1: display_4 = 7'b1111001;
4'h2: display_4 = 7'b0100100;
4'h3: display_4 = 7'b0110000;
4'h4: display_4 = 7'b0011001;
4'h5: display_4 = 7'b0010010;
4'h6: display_4 = 7'b0000010;
4'h7: display_4 = 7'b1111000;
4'h8: display_4 = 7'b0000000;
4'h9: display_4 = 7'b0011000;
4'hA: display_4 = 7'b0001000;
4'hB: display_4 = 7'b0000011;
4'hC: display_4 = 7'b1000110;
4'hD: display_4 = 7'b0100001;
4'hE: display_4 = 7'b0000110;
4'hF: display_4 = 7'b0001110;
default: display_4 = 7'b0110110;
endcase
case (gpio_o[19:16])
4'h0: display_5 = 7'b1000000;
4'h1: display_5 = 7'b1111001;
4'h2: display_5 = 7'b0100100;
4'h3: display_5 = 7'b0110000;
4'h4: display_5 = 7'b0011001;
4'h5: display_5 = 7'b0010010;
4'h6: display_5 = 7'b0000010;
4'h7: display_5 = 7'b1111000;
4'h8: display_5 = 7'b0000000;
4'h9: display_5 = 7'b0011000;
4'hA: display_5 = 7'b0001000;
4'hB: display_5 = 7'b0000011;
4'hC: display_5 = 7'b1000110;
4'hD: display_5 = 7'b0100001;
4'hE: display_5 = 7'b0000110;
4'hF: display_5 = 7'b0001110;
default: display_5 = 7'b0110110;
endcase
case (gpio_o[23:20])
4'h0: display_6 = 7'b1000000;
4'h1: display_6 = 7'b1111001;
4'h2: display_6 = 7'b0100100;
4'h3: display_6 = 7'b0110000;
4'h4: display_6 = 7'b0011001;
4'h5: display_6 = 7'b0010010;
4'h6: display_6 = 7'b0000010;
4'h7: display_6 = 7'b1111000;
4'h8: display_6 = 7'b0000000;
4'h9: display_6 = 7'b0011000;
4'hA: display_6 = 7'b0001000;
4'hB: display_6 = 7'b0000011;
4'hC: display_6 = 7'b1000110;
4'hD: display_6 = 7'b0100001;
4'hE: display_6 = 7'b0000110;
4'hF: display_6 = 7'b0001110;
default: display_6 = 7'b0110110;
endcase
case (gpio_o[27:24])
4'h0: display_7 = 7'b1000000;
4'h1: display_7 = 7'b1111001;
4'h2: display_7 = 7'b0100100;
4'h3: display_7 = 7'b0110000;
4'h4: display_7 = 7'b0011001;
4'h5: display_7 = 7'b0010010;
4'h6: display_7 = 7'b0000010;
4'h7: display_7 = 7'b1111000;
4'h8: display_7 = 7'b0000000;
4'h9: display_7 = 7'b0011000;
4'hA: display_7 = 7'b0001000;
4'hB: display_7 = 7'b0000011;
4'hC: display_7 = 7'b1000110;
4'hD: display_7 = 7'b0100001;
4'hE: display_7 = 7'b0000110;
4'hF: display_7 = 7'b0001110;
default: display_7 = 7'b0110110;
endcase
case (gpio_o[31:28])//mode[3:0])
4'h0: display_8 = 7'b1000000;
4'h1: display_8 = 7'b1111001;
4'h2: display_8 = 7'b0100100;
4'h3: display_8 = 7'b0110000;
4'h4: display_8 = 7'b0011001;
4'h5: display_8 = 7'b0010010;
4'h6: display_8 = 7'b0000010;
4'h7: display_8 = 7'b1111000;
4'h8: display_8 = 7'b0000000;
4'h9: display_8 = 7'b0011000;
4'hA: display_8 = 7'b0001000;
4'hB: display_8 = 7'b0000011;
4'hC: display_8 = 7'b1000110;
4'hD: display_8 = 7'b0100001;
4'hE: display_8 = 7'b0000110;
4'hF: display_8 = 7'b0001110;
default: display_8 = 7'b0110110;
endcase
end
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build 2018833 Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 14:49:55 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ DemoInterconnect_axi_spi_master_0_0_sim_netlist.v
// Design : DemoInterconnect_axi_spi_master_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "DemoInterconnect_axi_spi_master_0_0,axi_spi_master_v1_0,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_spi_master_v1_0,Vivado 2017.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(m_spi_mosi,
m_spi_miso,
m_spi_ss,
m_spi_sclk,
s00_axi_awaddr,
s00_axi_awprot,
s00_axi_awvalid,
s00_axi_awready,
s00_axi_wdata,
s00_axi_wstrb,
s00_axi_wvalid,
s00_axi_wready,
s00_axi_bresp,
s00_axi_bvalid,
s00_axi_bready,
s00_axi_araddr,
s00_axi_arprot,
s00_axi_arvalid,
s00_axi_arready,
s00_axi_rdata,
s00_axi_rresp,
s00_axi_rvalid,
s00_axi_rready,
s00_axi_aclk,
s00_axi_aresetn);
(* x_interface_info = "xilinx.com:signal:data:1.0 m_spi_mosi DATA" *) (* x_interface_parameter = "XIL_INTERFACENAME m_spi_mosi, LAYERED_METADATA undef" *) output m_spi_mosi;
(* x_interface_info = "xilinx.com:signal:data:1.0 m_spi_miso DATA" *) (* x_interface_parameter = "XIL_INTERFACENAME m_spi_miso, LAYERED_METADATA undef" *) input m_spi_miso;
(* x_interface_info = "xilinx.com:signal:clockenable:1.0 m_spi_ss CE" *) (* x_interface_parameter = "XIL_INTERFACENAME m_spi_ss, FREQ_HZ 100000000, PHASE 0, POLARITY ACTIVE_LOW" *) output m_spi_ss;
(* x_interface_info = "xilinx.com:signal:clock:1.0 m_spi_sclk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME m_spi_sclk, ASSOCIATED_CLKEN m_spi_ss, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN DemoInterconnect_axi_spi_master_0_0_m_spi_sclk" *) output m_spi_sclk;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [3:0]s00_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) input [2:0]s00_axi_awprot;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) input s00_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) output s00_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) input [31:0]s00_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) input [3:0]s00_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) input s00_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) output s00_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) output [1:0]s00_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) output s00_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) input s00_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) input [3:0]s00_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) input [2:0]s00_axi_arprot;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) input s00_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) output s00_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) output [31:0]s00_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output [1:0]s00_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output s00_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) input s00_axi_rready;
(* x_interface_info = "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK, xilinx.com:signal:clock:1.0 s00_axi_aclk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, XIL_INTERFACENAME s00_axi_aclk, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF S00_AXI" *) input s00_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 S00_AXI_RST RST, xilinx.com:signal:reset:1.0 s00_axi_aresetn RST" *) (* x_interface_parameter = "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, XIL_INTERFACENAME s00_axi_aresetn, POLARITY ACTIVE_LOW" *) input s00_axi_aresetn;
wire \<const0> ;
wire m_spi_miso;
wire m_spi_mosi;
wire m_spi_sclk;
wire m_spi_ss;
wire s00_axi_aclk;
wire s00_axi_aresetn;
wire s00_axi_arready;
wire s00_axi_arvalid;
wire s00_axi_awready;
wire s00_axi_awvalid;
wire s00_axi_bready;
wire s00_axi_bvalid;
wire [31:0]s00_axi_rdata;
wire s00_axi_rready;
wire s00_axi_rvalid;
wire [31:0]s00_axi_wdata;
wire s00_axi_wready;
wire [3:0]s00_axi_wstrb;
wire s00_axi_wvalid;
assign s00_axi_bresp[1] = \<const0> ;
assign s00_axi_bresp[0] = \<const0> ;
assign s00_axi_rresp[1] = \<const0> ;
assign s00_axi_rresp[0] = \<const0> ;
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_spi_master_v1_0 U0
(.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_WREADY(s00_axi_wready),
.m_spi_miso(m_spi_miso),
.m_spi_mosi(m_spi_mosi),
.m_spi_sclk(m_spi_sclk),
.m_spi_ss(m_spi_ss),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn),
.s00_axi_arvalid(s00_axi_arvalid),
.s00_axi_awready(s00_axi_awready),
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_bready(s00_axi_bready),
.s00_axi_bvalid(s00_axi_bvalid),
.s00_axi_rdata(s00_axi_rdata),
.s00_axi_rready(s00_axi_rready),
.s00_axi_rvalid(s00_axi_rvalid),
.s00_axi_wdata(s00_axi_wdata),
.s00_axi_wstrb(s00_axi_wstrb),
.s00_axi_wvalid(s00_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_spi_master_v1_0
(s00_axi_awready,
m_spi_ss,
S_AXI_WREADY,
S_AXI_ARREADY,
s00_axi_rdata,
m_spi_sclk,
s00_axi_rvalid,
s00_axi_bvalid,
m_spi_mosi,
s00_axi_awvalid,
s00_axi_wvalid,
s00_axi_wstrb,
s00_axi_aclk,
s00_axi_aresetn,
s00_axi_wdata,
s00_axi_arvalid,
m_spi_miso,
s00_axi_bready,
s00_axi_rready);
output s00_axi_awready;
output m_spi_ss;
output S_AXI_WREADY;
output S_AXI_ARREADY;
output [31:0]s00_axi_rdata;
output m_spi_sclk;
output s00_axi_rvalid;
output s00_axi_bvalid;
output m_spi_mosi;
input s00_axi_awvalid;
input s00_axi_wvalid;
input [3:0]s00_axi_wstrb;
input s00_axi_aclk;
input s00_axi_aresetn;
input [31:0]s00_axi_wdata;
input s00_axi_arvalid;
input m_spi_miso;
input s00_axi_bready;
input s00_axi_rready;
wire S_AXI_ARREADY;
wire S_AXI_WREADY;
wire m_spi_miso;
wire m_spi_mosi;
wire m_spi_sclk;
wire m_spi_ss;
wire s00_axi_aclk;
wire s00_axi_aresetn;
wire s00_axi_arvalid;
wire s00_axi_awready;
wire s00_axi_awvalid;
wire s00_axi_bready;
wire s00_axi_bvalid;
wire [31:0]s00_axi_rdata;
wire s00_axi_rready;
wire s00_axi_rvalid;
wire [31:0]s00_axi_wdata;
wire [3:0]s00_axi_wstrb;
wire s00_axi_wvalid;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_spi_master_v1_0_S00_AXI axi_spi_master_v1_0_S00_AXI_inst
(.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_WREADY(S_AXI_WREADY),
.m_spi_miso(m_spi_miso),
.m_spi_mosi(m_spi_mosi),
.m_spi_sclk(m_spi_sclk),
.m_spi_ss(m_spi_ss),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn),
.s00_axi_arvalid(s00_axi_arvalid),
.s00_axi_awready(s00_axi_awready),
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_bready(s00_axi_bready),
.s00_axi_bvalid(s00_axi_bvalid),
.s00_axi_rdata(s00_axi_rdata),
.s00_axi_rready(s00_axi_rready),
.s00_axi_rvalid(s00_axi_rvalid),
.s00_axi_wdata(s00_axi_wdata),
.s00_axi_wstrb(s00_axi_wstrb),
.s00_axi_wvalid(s00_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_spi_master_v1_0_S00_AXI
(s00_axi_awready,
m_spi_ss,
S_AXI_WREADY,
S_AXI_ARREADY,
s00_axi_rdata,
m_spi_sclk,
s00_axi_rvalid,
s00_axi_bvalid,
m_spi_mosi,
s00_axi_awvalid,
s00_axi_wvalid,
s00_axi_wstrb,
s00_axi_aclk,
s00_axi_aresetn,
s00_axi_wdata,
s00_axi_arvalid,
m_spi_miso,
s00_axi_bready,
s00_axi_rready);
output s00_axi_awready;
output m_spi_ss;
output S_AXI_WREADY;
output S_AXI_ARREADY;
output [31:0]s00_axi_rdata;
output m_spi_sclk;
output s00_axi_rvalid;
output s00_axi_bvalid;
output m_spi_mosi;
input s00_axi_awvalid;
input s00_axi_wvalid;
input [3:0]s00_axi_wstrb;
input s00_axi_aclk;
input s00_axi_aresetn;
input [31:0]s00_axi_wdata;
input s00_axi_arvalid;
input m_spi_miso;
input s00_axi_bready;
input s00_axi_rready;
wire S_AXI_ARREADY;
wire S_AXI_WREADY;
wire axi_arready0;
wire axi_awready_i_2_n_0;
wire axi_bvalid_i_1_n_0;
wire axi_rdata;
wire axi_rvalid_i_1_n_0;
wire axi_wready0;
wire busy_o;
wire init_rx_ff;
wire m_spi_miso;
wire m_spi_mosi;
wire m_spi_sclk;
wire m_spi_ss;
wire o_tx_rx_busy;
wire p2s_load;
wire p2s_load0;
wire \packet_byte_cnt[0]_i_1_n_0 ;
wire \packet_byte_cnt[1]_i_1_n_0 ;
wire \packet_byte_cnt[2]_i_2_n_0 ;
wire \packet_byte_cnt_reg_n_0_[0] ;
wire \packet_byte_cnt_reg_n_0_[1] ;
wire \packet_byte_cnt_reg_n_0_[2] ;
wire s00_axi_aclk;
wire s00_axi_aresetn;
wire s00_axi_arvalid;
wire s00_axi_awready;
wire s00_axi_awvalid;
wire s00_axi_bready;
wire s00_axi_bvalid;
wire [31:0]s00_axi_rdata;
wire s00_axi_rready;
wire s00_axi_rvalid;
wire [31:0]s00_axi_wdata;
wire [3:0]s00_axi_wstrb;
wire s00_axi_wvalid;
wire [31:0]shift_data;
wire [7:0]shift_o;
wire [31:0]slv_wdata;
wire slv_wdata_0;
wire spi_master_inst_n_13;
wire [7:0]spi_rx_byte;
wire spi_tx_rx_start;
wire ss_o;
wire word2byte_inst_n_1;
FDRE axi_arready_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(axi_arready0),
.Q(S_AXI_ARREADY),
.R(word2byte_inst_n_1));
LUT3 #(
.INIT(8'h08))
axi_awready_i_2
(.I0(s00_axi_awvalid),
.I1(s00_axi_wvalid),
.I2(s00_axi_awready),
.O(axi_awready_i_2_n_0));
FDRE axi_awready_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(axi_awready_i_2_n_0),
.Q(s00_axi_awready),
.R(word2byte_inst_n_1));
LUT6 #(
.INIT(64'h0000FFFF80008000))
axi_bvalid_i_1
(.I0(S_AXI_WREADY),
.I1(s00_axi_awvalid),
.I2(s00_axi_wvalid),
.I3(s00_axi_awready),
.I4(s00_axi_bready),
.I5(s00_axi_bvalid),
.O(axi_bvalid_i_1_n_0));
FDRE axi_bvalid_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(axi_bvalid_i_1_n_0),
.Q(s00_axi_bvalid),
.R(word2byte_inst_n_1));
LUT4 #(
.INIT(16'h0080))
\axi_rdata[31]_i_1
(.I0(s00_axi_aresetn),
.I1(S_AXI_ARREADY),
.I2(s00_axi_arvalid),
.I3(s00_axi_rvalid),
.O(axi_rdata));
FDRE \axi_rdata_reg[0]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[0]),
.Q(s00_axi_rdata[0]),
.R(1'b0));
FDRE \axi_rdata_reg[10]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[10]),
.Q(s00_axi_rdata[10]),
.R(1'b0));
FDRE \axi_rdata_reg[11]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[11]),
.Q(s00_axi_rdata[11]),
.R(1'b0));
FDRE \axi_rdata_reg[12]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[12]),
.Q(s00_axi_rdata[12]),
.R(1'b0));
FDRE \axi_rdata_reg[13]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[13]),
.Q(s00_axi_rdata[13]),
.R(1'b0));
FDRE \axi_rdata_reg[14]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[14]),
.Q(s00_axi_rdata[14]),
.R(1'b0));
FDRE \axi_rdata_reg[15]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[15]),
.Q(s00_axi_rdata[15]),
.R(1'b0));
FDRE \axi_rdata_reg[16]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[16]),
.Q(s00_axi_rdata[16]),
.R(1'b0));
FDRE \axi_rdata_reg[17]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[17]),
.Q(s00_axi_rdata[17]),
.R(1'b0));
FDRE \axi_rdata_reg[18]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[18]),
.Q(s00_axi_rdata[18]),
.R(1'b0));
FDRE \axi_rdata_reg[19]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[19]),
.Q(s00_axi_rdata[19]),
.R(1'b0));
FDRE \axi_rdata_reg[1]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[1]),
.Q(s00_axi_rdata[1]),
.R(1'b0));
FDRE \axi_rdata_reg[20]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[20]),
.Q(s00_axi_rdata[20]),
.R(1'b0));
FDRE \axi_rdata_reg[21]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[21]),
.Q(s00_axi_rdata[21]),
.R(1'b0));
FDRE \axi_rdata_reg[22]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[22]),
.Q(s00_axi_rdata[22]),
.R(1'b0));
FDRE \axi_rdata_reg[23]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[23]),
.Q(s00_axi_rdata[23]),
.R(1'b0));
FDRE \axi_rdata_reg[24]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[24]),
.Q(s00_axi_rdata[24]),
.R(1'b0));
FDRE \axi_rdata_reg[25]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[25]),
.Q(s00_axi_rdata[25]),
.R(1'b0));
FDRE \axi_rdata_reg[26]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[26]),
.Q(s00_axi_rdata[26]),
.R(1'b0));
FDRE \axi_rdata_reg[27]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[27]),
.Q(s00_axi_rdata[27]),
.R(1'b0));
FDRE \axi_rdata_reg[28]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[28]),
.Q(s00_axi_rdata[28]),
.R(1'b0));
FDRE \axi_rdata_reg[29]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[29]),
.Q(s00_axi_rdata[29]),
.R(1'b0));
FDRE \axi_rdata_reg[2]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[2]),
.Q(s00_axi_rdata[2]),
.R(1'b0));
FDRE \axi_rdata_reg[30]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[30]),
.Q(s00_axi_rdata[30]),
.R(1'b0));
FDRE \axi_rdata_reg[31]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[31]),
.Q(s00_axi_rdata[31]),
.R(1'b0));
FDRE \axi_rdata_reg[3]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[3]),
.Q(s00_axi_rdata[3]),
.R(1'b0));
FDRE \axi_rdata_reg[4]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[4]),
.Q(s00_axi_rdata[4]),
.R(1'b0));
FDRE \axi_rdata_reg[5]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[5]),
.Q(s00_axi_rdata[5]),
.R(1'b0));
FDRE \axi_rdata_reg[6]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[6]),
.Q(s00_axi_rdata[6]),
.R(1'b0));
FDRE \axi_rdata_reg[7]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[7]),
.Q(s00_axi_rdata[7]),
.R(1'b0));
FDRE \axi_rdata_reg[8]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[8]),
.Q(s00_axi_rdata[8]),
.R(1'b0));
FDRE \axi_rdata_reg[9]
(.C(s00_axi_aclk),
.CE(axi_rdata),
.D(shift_data[9]),
.Q(s00_axi_rdata[9]),
.R(1'b0));
LUT4 #(
.INIT(16'h08F8))
axi_rvalid_i_1
(.I0(S_AXI_ARREADY),
.I1(s00_axi_arvalid),
.I2(s00_axi_rvalid),
.I3(s00_axi_rready),
.O(axi_rvalid_i_1_n_0));
FDRE axi_rvalid_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(axi_rvalid_i_1_n_0),
.Q(s00_axi_rvalid),
.R(word2byte_inst_n_1));
FDRE axi_wready_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(axi_wready0),
.Q(S_AXI_WREADY),
.R(word2byte_inst_n_1));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_byte2word byte2word_inst
(.Q({\packet_byte_cnt_reg_n_0_[2] ,\packet_byte_cnt_reg_n_0_[1] ,\packet_byte_cnt_reg_n_0_[0] }),
.axi_arready0(axi_arready0),
.axi_arready_reg(S_AXI_ARREADY),
.\axi_rdata_reg[31] (shift_data),
.init_rx_ff(init_rx_ff),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn),
.s00_axi_aresetn_0(word2byte_inst_n_1),
.s00_axi_arvalid(s00_axi_arvalid),
.spi_done_reg(spi_master_inst_n_13),
.\tx_rx_buffer_reg[7] (spi_rx_byte));
FDRE #(
.INIT(1'b0))
p2s_load_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(p2s_load0),
.Q(p2s_load),
.R(word2byte_inst_n_1));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h4004))
\packet_byte_cnt[0]_i_1
(.I0(s00_axi_wstrb[3]),
.I1(s00_axi_wstrb[0]),
.I2(s00_axi_wstrb[1]),
.I3(s00_axi_wstrb[2]),
.O(\packet_byte_cnt[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'h40))
\packet_byte_cnt[1]_i_1
(.I0(s00_axi_wstrb[3]),
.I1(s00_axi_wstrb[0]),
.I2(s00_axi_wstrb[1]),
.O(\packet_byte_cnt[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'hFF5D))
\packet_byte_cnt[2]_i_2
(.I0(s00_axi_wstrb[0]),
.I1(s00_axi_wstrb[2]),
.I2(s00_axi_wstrb[1]),
.I3(s00_axi_wstrb[3]),
.O(\packet_byte_cnt[2]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\packet_byte_cnt_reg[0]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(\packet_byte_cnt[0]_i_1_n_0 ),
.Q(\packet_byte_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\packet_byte_cnt_reg[1]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(\packet_byte_cnt[1]_i_1_n_0 ),
.Q(\packet_byte_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\packet_byte_cnt_reg[2]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(\packet_byte_cnt[2]_i_2_n_0 ),
.Q(\packet_byte_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \slv_wdata_reg[0]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[0]),
.Q(slv_wdata[0]),
.R(1'b0));
FDRE \slv_wdata_reg[10]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[10]),
.Q(slv_wdata[10]),
.R(1'b0));
FDRE \slv_wdata_reg[11]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[11]),
.Q(slv_wdata[11]),
.R(1'b0));
FDRE \slv_wdata_reg[12]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[12]),
.Q(slv_wdata[12]),
.R(1'b0));
FDRE \slv_wdata_reg[13]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[13]),
.Q(slv_wdata[13]),
.R(1'b0));
FDRE \slv_wdata_reg[14]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[14]),
.Q(slv_wdata[14]),
.R(1'b0));
FDRE \slv_wdata_reg[15]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[15]),
.Q(slv_wdata[15]),
.R(1'b0));
FDRE \slv_wdata_reg[16]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[16]),
.Q(slv_wdata[16]),
.R(1'b0));
FDRE \slv_wdata_reg[17]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[17]),
.Q(slv_wdata[17]),
.R(1'b0));
FDRE \slv_wdata_reg[18]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[18]),
.Q(slv_wdata[18]),
.R(1'b0));
FDRE \slv_wdata_reg[19]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[19]),
.Q(slv_wdata[19]),
.R(1'b0));
FDRE \slv_wdata_reg[1]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[1]),
.Q(slv_wdata[1]),
.R(1'b0));
FDRE \slv_wdata_reg[20]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[20]),
.Q(slv_wdata[20]),
.R(1'b0));
FDRE \slv_wdata_reg[21]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[21]),
.Q(slv_wdata[21]),
.R(1'b0));
FDRE \slv_wdata_reg[22]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[22]),
.Q(slv_wdata[22]),
.R(1'b0));
FDRE \slv_wdata_reg[23]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[23]),
.Q(slv_wdata[23]),
.R(1'b0));
FDRE \slv_wdata_reg[24]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[24]),
.Q(slv_wdata[24]),
.R(1'b0));
FDRE \slv_wdata_reg[25]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[25]),
.Q(slv_wdata[25]),
.R(1'b0));
FDRE \slv_wdata_reg[26]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[26]),
.Q(slv_wdata[26]),
.R(1'b0));
FDRE \slv_wdata_reg[27]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[27]),
.Q(slv_wdata[27]),
.R(1'b0));
FDRE \slv_wdata_reg[28]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[28]),
.Q(slv_wdata[28]),
.R(1'b0));
FDRE \slv_wdata_reg[29]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[29]),
.Q(slv_wdata[29]),
.R(1'b0));
FDRE \slv_wdata_reg[2]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[2]),
.Q(slv_wdata[2]),
.R(1'b0));
FDRE \slv_wdata_reg[30]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[30]),
.Q(slv_wdata[30]),
.R(1'b0));
FDRE \slv_wdata_reg[31]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[31]),
.Q(slv_wdata[31]),
.R(1'b0));
FDRE \slv_wdata_reg[3]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[3]),
.Q(slv_wdata[3]),
.R(1'b0));
FDRE \slv_wdata_reg[4]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[4]),
.Q(slv_wdata[4]),
.R(1'b0));
FDRE \slv_wdata_reg[5]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[5]),
.Q(slv_wdata[5]),
.R(1'b0));
FDRE \slv_wdata_reg[6]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[6]),
.Q(slv_wdata[6]),
.R(1'b0));
FDRE \slv_wdata_reg[7]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[7]),
.Q(slv_wdata[7]),
.R(1'b0));
FDRE \slv_wdata_reg[8]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[8]),
.Q(slv_wdata[8]),
.R(1'b0));
FDRE \slv_wdata_reg[9]
(.C(s00_axi_aclk),
.CE(slv_wdata_0),
.D(s00_axi_wdata[9]),
.Q(slv_wdata[9]),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_spi_master spi_master_inst
(.D(shift_o),
.E(spi_tx_rx_start),
.Q(spi_rx_byte),
.axi_wready0(axi_wready0),
.axi_wready_reg(S_AXI_WREADY),
.busy_o(busy_o),
.init_rx_ff(init_rx_ff),
.init_rx_ff_reg(spi_master_inst_n_13),
.m_spi_miso(m_spi_miso),
.m_spi_mosi(m_spi_mosi),
.m_spi_sclk(m_spi_sclk),
.m_spi_ss(m_spi_ss),
.o_tx_rx_busy(o_tx_rx_busy),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn),
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_wvalid(s00_axi_wvalid),
.ss_o(ss_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_word2byte word2byte_inst
(.D(shift_o),
.E(slv_wdata_0),
.Q({\packet_byte_cnt_reg_n_0_[2] ,\packet_byte_cnt_reg_n_0_[1] ,\packet_byte_cnt_reg_n_0_[0] }),
.axi_wready_reg(S_AXI_WREADY),
.busy_o(busy_o),
.\load_buffer_val_reg[7] (spi_tx_rx_start),
.o_tx_rx_busy(o_tx_rx_busy),
.p2s_load(p2s_load),
.p2s_load0(p2s_load0),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn),
.s00_axi_arvalid(s00_axi_arvalid),
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_bvalid(s00_axi_bvalid),
.s00_axi_wvalid(s00_axi_wvalid),
.\send_data_reg[0]_0 (word2byte_inst_n_1),
.\slv_wdata_reg[31] (slv_wdata),
.ss_o(ss_o));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_byte2word
(init_rx_ff,
axi_arready0,
\axi_rdata_reg[31] ,
spi_done_reg,
s00_axi_aclk,
s00_axi_aresetn_0,
Q,
axi_arready_reg,
s00_axi_arvalid,
s00_axi_aresetn,
\tx_rx_buffer_reg[7] );
output init_rx_ff;
output axi_arready0;
output [31:0]\axi_rdata_reg[31] ;
input spi_done_reg;
input s00_axi_aclk;
input s00_axi_aresetn_0;
input [2:0]Q;
input axi_arready_reg;
input s00_axi_arvalid;
input s00_axi_aresetn;
input [7:0]\tx_rx_buffer_reg[7] ;
wire [2:0]Q;
wire axi_arready0;
wire axi_arready_reg;
wire [31:0]\axi_rdata_reg[31] ;
wire done_o;
wire init_rx_ff;
wire init_rx_ff2;
wire init_rx_ff2_i_1_n_0;
wire rx_done_i_1_n_0;
wire rx_en;
wire rx_en_i_1_n_0;
wire s00_axi_aclk;
wire s00_axi_aresetn;
wire s00_axi_aresetn_0;
wire s00_axi_arvalid;
wire shift_count0__3;
wire \shift_count[0]_i_1_n_0 ;
wire \shift_count[1]_i_1_n_0 ;
wire \shift_count[2]_i_1_n_0 ;
wire \shift_count_reg_n_0_[0] ;
wire \shift_count_reg_n_0_[1] ;
wire \shift_count_reg_n_0_[2] ;
wire \shift_data[31]_i_1_n_0 ;
wire spi_done_reg;
wire [7:0]\tx_rx_buffer_reg[7] ;
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h40))
axi_arready_i_1
(.I0(axi_arready_reg),
.I1(s00_axi_arvalid),
.I2(done_o),
.O(axi_arready0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hB8))
init_rx_ff2_i_1
(.I0(init_rx_ff),
.I1(s00_axi_aresetn),
.I2(init_rx_ff2),
.O(init_rx_ff2_i_1_n_0));
FDRE #(
.INIT(1'b0))
init_rx_ff2_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(init_rx_ff2_i_1_n_0),
.Q(init_rx_ff2),
.R(1'b0));
FDRE #(
.INIT(1'b0))
init_rx_ff_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(spi_done_reg),
.Q(init_rx_ff),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h20))
rx_done_i_1
(.I0(shift_count0__3),
.I1(done_o),
.I2(rx_en),
.O(rx_done_i_1_n_0));
FDRE #(
.INIT(1'b0))
rx_done_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(rx_done_i_1_n_0),
.Q(done_o),
.R(s00_axi_aresetn_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h2F20))
rx_en_i_1
(.I0(init_rx_ff),
.I1(init_rx_ff2),
.I2(s00_axi_aresetn),
.I3(rx_en),
.O(rx_en_i_1_n_0));
FDRE #(
.INIT(1'b0))
rx_en_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(rx_en_i_1_n_0),
.Q(rx_en),
.R(1'b0));
LUT5 #(
.INIT(32'h80888488))
\shift_count[0]_i_1
(.I0(\shift_count_reg_n_0_[0] ),
.I1(s00_axi_aresetn),
.I2(done_o),
.I3(rx_en),
.I4(shift_count0__3),
.O(\shift_count[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hA000A0A0A060A0A0))
\shift_count[1]_i_1
(.I0(\shift_count_reg_n_0_[1] ),
.I1(\shift_count_reg_n_0_[0] ),
.I2(s00_axi_aresetn),
.I3(done_o),
.I4(rx_en),
.I5(shift_count0__3),
.O(\shift_count[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000AA006A00AA00))
\shift_count[2]_i_1
(.I0(\shift_count_reg_n_0_[2] ),
.I1(\shift_count_reg_n_0_[1] ),
.I2(\shift_count_reg_n_0_[0] ),
.I3(s00_axi_aresetn),
.I4(\shift_data[31]_i_1_n_0 ),
.I5(shift_count0__3),
.O(\shift_count[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0042001084002100))
\shift_count[2]_i_2
(.I0(\shift_count_reg_n_0_[1] ),
.I1(\shift_count_reg_n_0_[2] ),
.I2(Q[1]),
.I3(Q[0]),
.I4(Q[2]),
.I5(\shift_count_reg_n_0_[0] ),
.O(shift_count0__3));
FDRE #(
.INIT(1'b0))
\shift_count_reg[0]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\shift_count[0]_i_1_n_0 ),
.Q(\shift_count_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_count_reg[1]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\shift_count[1]_i_1_n_0 ),
.Q(\shift_count_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_count_reg[2]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\shift_count[2]_i_1_n_0 ),
.Q(\shift_count_reg_n_0_[2] ),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\shift_data[31]_i_1
(.I0(rx_en),
.I1(done_o),
.O(\shift_data[31]_i_1_n_0 ));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[0]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\tx_rx_buffer_reg[7] [0]),
.Q(\axi_rdata_reg[31] [0]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[10]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\axi_rdata_reg[31] [2]),
.Q(\axi_rdata_reg[31] [10]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[11]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\axi_rdata_reg[31] [3]),
.Q(\axi_rdata_reg[31] [11]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[12]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\axi_rdata_reg[31] [4]),
.Q(\axi_rdata_reg[31] [12]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[13]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\axi_rdata_reg[31] [5]),
.Q(\axi_rdata_reg[31] [13]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[14]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\axi_rdata_reg[31] [6]),
.Q(\axi_rdata_reg[31] [14]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[15]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\axi_rdata_reg[31] [7]),
.Q(\axi_rdata_reg[31] [15]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[16]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\axi_rdata_reg[31] [8]),
.Q(\axi_rdata_reg[31] [16]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[17]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\axi_rdata_reg[31] [9]),
.Q(\axi_rdata_reg[31] [17]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[18]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\axi_rdata_reg[31] [10]),
.Q(\axi_rdata_reg[31] [18]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[19]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\axi_rdata_reg[31] [11]),
.Q(\axi_rdata_reg[31] [19]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[1]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\tx_rx_buffer_reg[7] [1]),
.Q(\axi_rdata_reg[31] [1]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[20]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\axi_rdata_reg[31] [12]),
.Q(\axi_rdata_reg[31] [20]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[21]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\axi_rdata_reg[31] [13]),
.Q(\axi_rdata_reg[31] [21]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[22]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\axi_rdata_reg[31] [14]),
.Q(\axi_rdata_reg[31] [22]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[23]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\axi_rdata_reg[31] [15]),
.Q(\axi_rdata_reg[31] [23]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[24]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\axi_rdata_reg[31] [16]),
.Q(\axi_rdata_reg[31] [24]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[25]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\axi_rdata_reg[31] [17]),
.Q(\axi_rdata_reg[31] [25]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[26]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\axi_rdata_reg[31] [18]),
.Q(\axi_rdata_reg[31] [26]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[27]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\axi_rdata_reg[31] [19]),
.Q(\axi_rdata_reg[31] [27]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[28]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\axi_rdata_reg[31] [20]),
.Q(\axi_rdata_reg[31] [28]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[29]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\axi_rdata_reg[31] [21]),
.Q(\axi_rdata_reg[31] [29]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[2]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\tx_rx_buffer_reg[7] [2]),
.Q(\axi_rdata_reg[31] [2]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[30]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\axi_rdata_reg[31] [22]),
.Q(\axi_rdata_reg[31] [30]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[31]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\axi_rdata_reg[31] [23]),
.Q(\axi_rdata_reg[31] [31]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[3]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\tx_rx_buffer_reg[7] [3]),
.Q(\axi_rdata_reg[31] [3]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[4]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\tx_rx_buffer_reg[7] [4]),
.Q(\axi_rdata_reg[31] [4]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[5]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\tx_rx_buffer_reg[7] [5]),
.Q(\axi_rdata_reg[31] [5]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[6]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\tx_rx_buffer_reg[7] [6]),
.Q(\axi_rdata_reg[31] [6]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[7]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\tx_rx_buffer_reg[7] [7]),
.Q(\axi_rdata_reg[31] [7]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[8]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\axi_rdata_reg[31] [0]),
.Q(\axi_rdata_reg[31] [8]),
.R(s00_axi_aresetn_0));
(* SHREG_EXTRACT = "yes" *)
FDRE #(
.INIT(1'b0))
\shift_data_reg[9]
(.C(s00_axi_aclk),
.CE(\shift_data[31]_i_1_n_0 ),
.D(\axi_rdata_reg[31] [1]),
.Q(\axi_rdata_reg[31] [9]),
.R(s00_axi_aresetn_0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_spi_master
(m_spi_mosi,
m_spi_ss,
m_spi_sclk,
o_tx_rx_busy,
axi_wready0,
Q,
init_rx_ff_reg,
s00_axi_aclk,
ss_o,
axi_wready_reg,
s00_axi_wvalid,
s00_axi_awvalid,
busy_o,
m_spi_miso,
s00_axi_aresetn,
init_rx_ff,
E,
D);
output m_spi_mosi;
output m_spi_ss;
output m_spi_sclk;
output o_tx_rx_busy;
output axi_wready0;
output [7:0]Q;
output init_rx_ff_reg;
input s00_axi_aclk;
input ss_o;
input axi_wready_reg;
input s00_axi_wvalid;
input s00_axi_awvalid;
input busy_o;
input m_spi_miso;
input s00_axi_aresetn;
input init_rx_ff;
input [0:0]E;
input [7:0]D;
wire [7:0]D;
wire [0:0]E;
wire [7:0]Q;
wire axi_wready0;
wire axi_wready_reg;
wire buffer_ready;
wire buffer_ready_i_1_n_0;
wire busy_o;
wire init_rx_ff;
wire init_rx_ff_reg;
wire load_buffer;
wire load_buffer_i_1_n_0;
wire [7:0]load_buffer_val;
wire m_spi_miso;
wire m_spi_mosi;
wire m_spi_sclk;
wire m_spi_ss;
wire mosi_i_1_n_0;
wire o_sclk_i_1_n_0;
wire o_sclk_i_2_n_0;
wire o_tx_rx_busy;
wire o_tx_rx_end;
wire s00_axi_aclk;
wire s00_axi_aresetn;
wire s00_axi_awvalid;
wire s00_axi_wvalid;
wire sclk;
wire sclk_i_1_n_0;
wire [3:0]spi_bit_counter;
wire \spi_bit_counter[0]_i_1_n_0 ;
wire \spi_bit_counter[1]_i_1_n_0 ;
wire \spi_bit_counter[2]_i_1_n_0 ;
wire \spi_bit_counter[3]_i_1_n_0 ;
wire \spi_bit_counter[3]_i_2_n_0 ;
wire spi_busy_i_1_n_0;
wire [2:0]spi_clock_counter;
wire \spi_clock_counter[0]_i_1_n_0 ;
wire \spi_clock_counter[1]_i_1_n_0 ;
wire \spi_clock_counter[2]_i_1_n_0 ;
wire spi_done_i_1_n_0;
wire spi_en_i_1_n_0;
wire spi_en_reg_n_0;
wire ss_i_1_n_0;
wire ss_o;
wire \tx_rx_buffer[0]_i_1_n_0 ;
wire \tx_rx_buffer[1]_i_1_n_0 ;
wire \tx_rx_buffer[2]_i_1_n_0 ;
wire \tx_rx_buffer[3]_i_1_n_0 ;
wire \tx_rx_buffer[4]_i_1_n_0 ;
wire \tx_rx_buffer[5]_i_1_n_0 ;
wire \tx_rx_buffer[6]_i_1_n_0 ;
wire \tx_rx_buffer[7]_i_1_n_0 ;
wire \tx_rx_buffer[7]_i_2_n_0 ;
LUT5 #(
.INIT(32'h00001000))
axi_wready_i_1
(.I0(o_tx_rx_busy),
.I1(axi_wready_reg),
.I2(s00_axi_wvalid),
.I3(s00_axi_awvalid),
.I4(busy_o),
.O(axi_wready0));
LUT2 #(
.INIT(4'h4))
buffer_ready_i_1
(.I0(buffer_ready),
.I1(load_buffer),
.O(buffer_ready_i_1_n_0));
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b1))
buffer_ready_reg
(.C(sclk),
.CE(1'b1),
.D(buffer_ready_i_1_n_0),
.Q(buffer_ready),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
init_rx_ff_i_1
(.I0(o_tx_rx_end),
.I1(s00_axi_aresetn),
.I2(init_rx_ff),
.O(init_rx_ff_reg));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h4F))
load_buffer_i_1
(.I0(buffer_ready),
.I1(load_buffer),
.I2(ss_o),
.O(load_buffer_i_1_n_0));
FDRE #(
.INIT(1'b0))
load_buffer_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(load_buffer_i_1_n_0),
.Q(load_buffer),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\load_buffer_val_reg[0]
(.C(s00_axi_aclk),
.CE(E),
.D(D[0]),
.Q(load_buffer_val[0]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\load_buffer_val_reg[1]
(.C(s00_axi_aclk),
.CE(E),
.D(D[1]),
.Q(load_buffer_val[1]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\load_buffer_val_reg[2]
(.C(s00_axi_aclk),
.CE(E),
.D(D[2]),
.Q(load_buffer_val[2]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\load_buffer_val_reg[3]
(.C(s00_axi_aclk),
.CE(E),
.D(D[3]),
.Q(load_buffer_val[3]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\load_buffer_val_reg[4]
(.C(s00_axi_aclk),
.CE(E),
.D(D[4]),
.Q(load_buffer_val[4]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\load_buffer_val_reg[5]
(.C(s00_axi_aclk),
.CE(E),
.D(D[5]),
.Q(load_buffer_val[5]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\load_buffer_val_reg[6]
(.C(s00_axi_aclk),
.CE(E),
.D(D[6]),
.Q(load_buffer_val[6]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\load_buffer_val_reg[7]
(.C(s00_axi_aclk),
.CE(E),
.D(D[7]),
.Q(load_buffer_val[7]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hFFFB))
mosi_i_1
(.I0(Q[7]),
.I1(spi_en_reg_n_0),
.I2(m_spi_ss),
.I3(load_buffer),
.O(mosi_i_1_n_0));
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b1))
mosi_reg
(.C(sclk),
.CE(1'b1),
.D(mosi_i_1_n_0),
.Q(m_spi_mosi),
.R(1'b0));
LUT6 #(
.INIT(64'hAAAACFAAAAAAAAAA))
o_sclk_i_1
(.I0(m_spi_sclk),
.I1(sclk),
.I2(o_sclk_i_2_n_0),
.I3(spi_clock_counter[0]),
.I4(spi_clock_counter[1]),
.I5(spi_clock_counter[2]),
.O(o_sclk_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h2))
o_sclk_i_2
(.I0(spi_en_reg_n_0),
.I1(m_spi_ss),
.O(o_sclk_i_2_n_0));
FDRE #(
.INIT(1'b1))
o_sclk_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(o_sclk_i_1_n_0),
.Q(m_spi_sclk),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'hF708))
sclk_i_1
(.I0(spi_clock_counter[2]),
.I1(spi_clock_counter[0]),
.I2(spi_clock_counter[1]),
.I3(sclk),
.O(sclk_i_1_n_0));
FDRE #(
.INIT(1'b1))
sclk_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(sclk_i_1_n_0),
.Q(sclk),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT1 #(
.INIT(2'h1))
\spi_bit_counter[0]_i_1
(.I0(spi_bit_counter[0]),
.O(\spi_bit_counter[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'h6))
\spi_bit_counter[1]_i_1
(.I0(spi_bit_counter[0]),
.I1(spi_bit_counter[1]),
.O(\spi_bit_counter[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h78))
\spi_bit_counter[2]_i_1
(.I0(spi_bit_counter[0]),
.I1(spi_bit_counter[1]),
.I2(spi_bit_counter[2]),
.O(\spi_bit_counter[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00020000))
\spi_bit_counter[3]_i_1
(.I0(spi_en_reg_n_0),
.I1(spi_bit_counter[2]),
.I2(spi_bit_counter[0]),
.I3(spi_bit_counter[1]),
.I4(spi_bit_counter[3]),
.O(\spi_bit_counter[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7F80))
\spi_bit_counter[3]_i_2
(.I0(spi_bit_counter[1]),
.I1(spi_bit_counter[0]),
.I2(spi_bit_counter[2]),
.I3(spi_bit_counter[3]),
.O(\spi_bit_counter[3]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\spi_bit_counter_reg[0]
(.C(sclk),
.CE(spi_en_reg_n_0),
.D(\spi_bit_counter[0]_i_1_n_0 ),
.Q(spi_bit_counter[0]),
.R(\spi_bit_counter[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\spi_bit_counter_reg[1]
(.C(sclk),
.CE(spi_en_reg_n_0),
.D(\spi_bit_counter[1]_i_1_n_0 ),
.Q(spi_bit_counter[1]),
.R(\spi_bit_counter[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\spi_bit_counter_reg[2]
(.C(sclk),
.CE(spi_en_reg_n_0),
.D(\spi_bit_counter[2]_i_1_n_0 ),
.Q(spi_bit_counter[2]),
.R(\spi_bit_counter[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\spi_bit_counter_reg[3]
(.C(sclk),
.CE(spi_en_reg_n_0),
.D(\spi_bit_counter[3]_i_2_n_0 ),
.Q(spi_bit_counter[3]),
.R(\spi_bit_counter[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFE00FFFF))
spi_busy_i_1
(.I0(spi_en_reg_n_0),
.I1(load_buffer),
.I2(o_tx_rx_end),
.I3(o_tx_rx_busy),
.I4(ss_o),
.O(spi_busy_i_1_n_0));
FDRE #(
.INIT(1'b0))
spi_busy_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(spi_busy_i_1_n_0),
.Q(o_tx_rx_busy),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT1 #(
.INIT(2'h1))
\spi_clock_counter[0]_i_1
(.I0(spi_clock_counter[0]),
.O(\spi_clock_counter[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h52))
\spi_clock_counter[1]_i_1
(.I0(spi_clock_counter[0]),
.I1(spi_clock_counter[2]),
.I2(spi_clock_counter[1]),
.O(\spi_clock_counter[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h64))
\spi_clock_counter[2]_i_1
(.I0(spi_clock_counter[0]),
.I1(spi_clock_counter[2]),
.I2(spi_clock_counter[1]),
.O(\spi_clock_counter[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\spi_clock_counter_reg[0]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\spi_clock_counter[0]_i_1_n_0 ),
.Q(spi_clock_counter[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\spi_clock_counter_reg[1]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\spi_clock_counter[1]_i_1_n_0 ),
.Q(spi_clock_counter[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\spi_clock_counter_reg[2]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\spi_clock_counter[2]_i_1_n_0 ),
.Q(spi_clock_counter[2]),
.R(1'b0));
LUT6 #(
.INIT(64'h0000010000000000))
spi_done_i_1
(.I0(o_tx_rx_end),
.I1(spi_bit_counter[0]),
.I2(spi_bit_counter[2]),
.I3(spi_bit_counter[3]),
.I4(spi_bit_counter[1]),
.I5(spi_en_reg_n_0),
.O(spi_done_i_1_n_0));
FDRE #(
.INIT(1'b0))
spi_done_reg
(.C(sclk),
.CE(1'b1),
.D(spi_done_i_1_n_0),
.Q(o_tx_rx_end),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0EAA))
spi_en_i_1
(.I0(spi_en_reg_n_0),
.I1(buffer_ready),
.I2(o_tx_rx_end),
.I3(ss_o),
.O(spi_en_i_1_n_0));
FDRE #(
.INIT(1'b0))
spi_en_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(spi_en_i_1_n_0),
.Q(spi_en_reg_n_0),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
ss_i_1
(.I0(spi_en_reg_n_0),
.O(ss_i_1_n_0));
FDRE #(
.INIT(1'b1))
ss_reg
(.C(sclk),
.CE(1'b1),
.D(ss_i_1_n_0),
.Q(m_spi_ss),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\tx_rx_buffer[0]_i_1
(.I0(load_buffer_val[0]),
.I1(load_buffer),
.I2(m_spi_miso),
.O(\tx_rx_buffer[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\tx_rx_buffer[1]_i_1
(.I0(load_buffer_val[1]),
.I1(load_buffer),
.I2(Q[0]),
.O(\tx_rx_buffer[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\tx_rx_buffer[2]_i_1
(.I0(load_buffer_val[2]),
.I1(load_buffer),
.I2(Q[1]),
.O(\tx_rx_buffer[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\tx_rx_buffer[3]_i_1
(.I0(load_buffer_val[3]),
.I1(load_buffer),
.I2(Q[2]),
.O(\tx_rx_buffer[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\tx_rx_buffer[4]_i_1
(.I0(load_buffer_val[4]),
.I1(load_buffer),
.I2(Q[3]),
.O(\tx_rx_buffer[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\tx_rx_buffer[5]_i_1
(.I0(load_buffer_val[5]),
.I1(load_buffer),
.I2(Q[4]),
.O(\tx_rx_buffer[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\tx_rx_buffer[6]_i_1
(.I0(load_buffer_val[6]),
.I1(load_buffer),
.I2(Q[5]),
.O(\tx_rx_buffer[6]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\tx_rx_buffer[7]_i_1
(.I0(load_buffer),
.I1(m_spi_ss),
.I2(spi_en_reg_n_0),
.O(\tx_rx_buffer[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\tx_rx_buffer[7]_i_2
(.I0(load_buffer_val[7]),
.I1(load_buffer),
.I2(Q[6]),
.O(\tx_rx_buffer[7]_i_2_n_0 ));
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b1))
\tx_rx_buffer_reg[0]
(.C(sclk),
.CE(\tx_rx_buffer[7]_i_1_n_0 ),
.D(\tx_rx_buffer[0]_i_1_n_0 ),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b1))
\tx_rx_buffer_reg[1]
(.C(sclk),
.CE(\tx_rx_buffer[7]_i_1_n_0 ),
.D(\tx_rx_buffer[1]_i_1_n_0 ),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b1))
\tx_rx_buffer_reg[2]
(.C(sclk),
.CE(\tx_rx_buffer[7]_i_1_n_0 ),
.D(\tx_rx_buffer[2]_i_1_n_0 ),
.Q(Q[2]),
.R(1'b0));
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b1))
\tx_rx_buffer_reg[3]
(.C(sclk),
.CE(\tx_rx_buffer[7]_i_1_n_0 ),
.D(\tx_rx_buffer[3]_i_1_n_0 ),
.Q(Q[3]),
.R(1'b0));
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b1))
\tx_rx_buffer_reg[4]
(.C(sclk),
.CE(\tx_rx_buffer[7]_i_1_n_0 ),
.D(\tx_rx_buffer[4]_i_1_n_0 ),
.Q(Q[4]),
.R(1'b0));
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b1))
\tx_rx_buffer_reg[5]
(.C(sclk),
.CE(\tx_rx_buffer[7]_i_1_n_0 ),
.D(\tx_rx_buffer[5]_i_1_n_0 ),
.Q(Q[5]),
.R(1'b0));
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b1))
\tx_rx_buffer_reg[6]
(.C(sclk),
.CE(\tx_rx_buffer[7]_i_1_n_0 ),
.D(\tx_rx_buffer[6]_i_1_n_0 ),
.Q(Q[6]),
.R(1'b0));
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b1))
\tx_rx_buffer_reg[7]
(.C(sclk),
.CE(\tx_rx_buffer[7]_i_1_n_0 ),
.D(\tx_rx_buffer[7]_i_2_n_0 ),
.Q(Q[7]),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_word2byte
(ss_o,
\send_data_reg[0]_0 ,
busy_o,
E,
\load_buffer_val_reg[7] ,
p2s_load0,
D,
s00_axi_aclk,
p2s_load,
s00_axi_aresetn,
s00_axi_awvalid,
s00_axi_wvalid,
axi_wready_reg,
o_tx_rx_busy,
Q,
s00_axi_bvalid,
s00_axi_arvalid,
\slv_wdata_reg[31] );
output ss_o;
output \send_data_reg[0]_0 ;
output busy_o;
output [0:0]E;
output [0:0]\load_buffer_val_reg[7] ;
output p2s_load0;
output [7:0]D;
input s00_axi_aclk;
input p2s_load;
input s00_axi_aresetn;
input s00_axi_awvalid;
input s00_axi_wvalid;
input axi_wready_reg;
input o_tx_rx_busy;
input [2:0]Q;
input s00_axi_bvalid;
input s00_axi_arvalid;
input [31:0]\slv_wdata_reg[31] ;
wire [7:0]D;
wire [0:0]E;
wire [2:0]Q;
wire axi_wready_reg;
wire busy_o;
wire [7:0]data1;
wire [7:0]data2;
wire [7:0]data3;
wire [0:0]\load_buffer_val_reg[7] ;
wire o_tx_rx_busy;
wire p2s_load;
wire p2s_load0;
wire s00_axi_aclk;
wire s00_axi_aresetn;
wire s00_axi_arvalid;
wire s00_axi_awvalid;
wire s00_axi_bvalid;
wire s00_axi_wvalid;
wire \send_data[31]_i_1_n_0 ;
wire \send_data_reg[0]_0 ;
wire \send_data_reg_n_0_[0] ;
wire \send_data_reg_n_0_[1] ;
wire \send_data_reg_n_0_[2] ;
wire \send_data_reg_n_0_[3] ;
wire \send_data_reg_n_0_[4] ;
wire \send_data_reg_n_0_[5] ;
wire \send_data_reg_n_0_[6] ;
wire \send_data_reg_n_0_[7] ;
wire sending_i_1_n_0;
wire [2:0]shift_count;
wire \shift_count[0]_i_1_n_0 ;
wire \shift_count[1]_i_1_n_0 ;
wire \shift_count[1]_i_2_n_0 ;
wire \shift_count[2]_i_1_n_0 ;
wire \shift_count[2]_i_2__0_n_0 ;
wire \shift_o[0]_i_1_n_0 ;
wire \shift_o[1]_i_1_n_0 ;
wire \shift_o[2]_i_1_n_0 ;
wire \shift_o[3]_i_1_n_0 ;
wire \shift_o[4]_i_1_n_0 ;
wire \shift_o[5]_i_1_n_0 ;
wire \shift_o[6]_i_1_n_0 ;
wire \shift_o[7]_i_1_n_0 ;
wire [31:0]\slv_wdata_reg[31] ;
wire ss_o;
wire ss_o1;
wire ss_o_i_1_n_0;
wire tx_done_i_1_n_0;
wire tx_done_reg_n_0;
LUT1 #(
.INIT(2'h1))
axi_awready_i_1
(.I0(s00_axi_aresetn),
.O(\send_data_reg[0]_0 ));
LUT1 #(
.INIT(2'h1))
\load_buffer_val[7]_i_1
(.I0(ss_o),
.O(\load_buffer_val_reg[7] ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h0054))
p2s_load_i_1
(.I0(p2s_load),
.I1(s00_axi_bvalid),
.I2(s00_axi_arvalid),
.I3(busy_o),
.O(p2s_load0));
LUT6 #(
.INIT(64'h0000000000002000))
\packet_byte_cnt[2]_i_1
(.I0(s00_axi_aresetn),
.I1(busy_o),
.I2(s00_axi_awvalid),
.I3(s00_axi_wvalid),
.I4(axi_wready_reg),
.I5(o_tx_rx_busy),
.O(E));
LUT2 #(
.INIT(4'h2))
\send_data[31]_i_1
(.I0(p2s_load),
.I1(busy_o),
.O(\send_data[31]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[0]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [0]),
.Q(\send_data_reg_n_0_[0] ),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[10]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [10]),
.Q(data1[2]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[11]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [11]),
.Q(data1[3]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[12]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [12]),
.Q(data1[4]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[13]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [13]),
.Q(data1[5]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[14]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [14]),
.Q(data1[6]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[15]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [15]),
.Q(data1[7]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[16]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [16]),
.Q(data2[0]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[17]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [17]),
.Q(data2[1]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[18]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [18]),
.Q(data2[2]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[19]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [19]),
.Q(data2[3]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[1]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [1]),
.Q(\send_data_reg_n_0_[1] ),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[20]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [20]),
.Q(data2[4]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[21]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [21]),
.Q(data2[5]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[22]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [22]),
.Q(data2[6]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[23]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [23]),
.Q(data2[7]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[24]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [24]),
.Q(data3[0]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[25]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [25]),
.Q(data3[1]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[26]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [26]),
.Q(data3[2]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[27]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [27]),
.Q(data3[3]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[28]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [28]),
.Q(data3[4]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[29]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [29]),
.Q(data3[5]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[2]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [2]),
.Q(\send_data_reg_n_0_[2] ),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[30]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [30]),
.Q(data3[6]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[31]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [31]),
.Q(data3[7]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[3]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [3]),
.Q(\send_data_reg_n_0_[3] ),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[4]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [4]),
.Q(\send_data_reg_n_0_[4] ),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[5]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [5]),
.Q(\send_data_reg_n_0_[5] ),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[6]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [6]),
.Q(\send_data_reg_n_0_[6] ),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[7]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [7]),
.Q(\send_data_reg_n_0_[7] ),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[8]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [8]),
.Q(data1[0]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\send_data_reg[9]
(.C(s00_axi_aclk),
.CE(\send_data[31]_i_1_n_0 ),
.D(\slv_wdata_reg[31] [9]),
.Q(data1[1]),
.R(\send_data_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'h3A))
sending_i_1
(.I0(p2s_load),
.I1(tx_done_reg_n_0),
.I2(busy_o),
.O(sending_i_1_n_0));
FDRE #(
.INIT(1'b0))
sending_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(sending_i_1_n_0),
.Q(busy_o),
.R(\send_data_reg[0]_0 ));
LUT6 #(
.INIT(64'h0F0C55550F0CF0F0))
\shift_count[0]_i_1
(.I0(Q[0]),
.I1(shift_count[1]),
.I2(shift_count[0]),
.I3(shift_count[2]),
.I4(ss_o1),
.I5(\send_data[31]_i_1_n_0 ),
.O(\shift_count[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hC3C05555C3C0CCCC))
\shift_count[1]_i_1
(.I0(\shift_count[1]_i_2_n_0 ),
.I1(shift_count[1]),
.I2(shift_count[0]),
.I3(shift_count[2]),
.I4(ss_o1),
.I5(\send_data[31]_i_1_n_0 ),
.O(\shift_count[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h6))
\shift_count[1]_i_2
(.I0(Q[0]),
.I1(Q[1]),
.O(\shift_count[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFC005555FC00FF00))
\shift_count[2]_i_1
(.I0(\shift_count[2]_i_2__0_n_0 ),
.I1(shift_count[1]),
.I2(shift_count[0]),
.I3(shift_count[2]),
.I4(ss_o1),
.I5(\send_data[31]_i_1_n_0 ),
.O(\shift_count[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h1E))
\shift_count[2]_i_2__0
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(\shift_count[2]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h0040))
\shift_count[2]_i_3
(.I0(tx_done_reg_n_0),
.I1(busy_o),
.I2(ss_o),
.I3(o_tx_rx_busy),
.O(ss_o1));
FDRE #(
.INIT(1'b0))
\shift_count_reg[0]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\shift_count[0]_i_1_n_0 ),
.Q(shift_count[0]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\shift_count_reg[1]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\shift_count[1]_i_1_n_0 ),
.Q(shift_count[1]),
.R(\send_data_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\shift_count_reg[2]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\shift_count[2]_i_1_n_0 ),
.Q(shift_count[2]),
.R(\send_data_reg[0]_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\shift_o[0]_i_1
(.I0(data3[0]),
.I1(data2[0]),
.I2(shift_count[1]),
.I3(data1[0]),
.I4(shift_count[0]),
.I5(\send_data_reg_n_0_[0] ),
.O(\shift_o[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\shift_o[1]_i_1
(.I0(data3[1]),
.I1(data2[1]),
.I2(shift_count[1]),
.I3(data1[1]),
.I4(shift_count[0]),
.I5(\send_data_reg_n_0_[1] ),
.O(\shift_o[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\shift_o[2]_i_1
(.I0(data3[2]),
.I1(data2[2]),
.I2(shift_count[1]),
.I3(data1[2]),
.I4(shift_count[0]),
.I5(\send_data_reg_n_0_[2] ),
.O(\shift_o[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\shift_o[3]_i_1
(.I0(data3[3]),
.I1(data2[3]),
.I2(shift_count[1]),
.I3(data1[3]),
.I4(shift_count[0]),
.I5(\send_data_reg_n_0_[3] ),
.O(\shift_o[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\shift_o[4]_i_1
(.I0(data3[4]),
.I1(data2[4]),
.I2(shift_count[1]),
.I3(data1[4]),
.I4(shift_count[0]),
.I5(\send_data_reg_n_0_[4] ),
.O(\shift_o[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\shift_o[5]_i_1
(.I0(data3[5]),
.I1(data2[5]),
.I2(shift_count[1]),
.I3(data1[5]),
.I4(shift_count[0]),
.I5(\send_data_reg_n_0_[5] ),
.O(\shift_o[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\shift_o[6]_i_1
(.I0(data3[6]),
.I1(data2[6]),
.I2(shift_count[1]),
.I3(data1[6]),
.I4(shift_count[0]),
.I5(\send_data_reg_n_0_[6] ),
.O(\shift_o[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\shift_o[7]_i_1
(.I0(data3[7]),
.I1(data2[7]),
.I2(shift_count[1]),
.I3(data1[7]),
.I4(shift_count[0]),
.I5(\send_data_reg_n_0_[7] ),
.O(\shift_o[7]_i_1_n_0 ));
FDRE \shift_o_reg[0]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\shift_o[0]_i_1_n_0 ),
.Q(D[0]),
.R(shift_count[2]));
FDRE \shift_o_reg[1]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\shift_o[1]_i_1_n_0 ),
.Q(D[1]),
.R(shift_count[2]));
FDRE \shift_o_reg[2]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\shift_o[2]_i_1_n_0 ),
.Q(D[2]),
.R(shift_count[2]));
FDRE \shift_o_reg[3]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\shift_o[3]_i_1_n_0 ),
.Q(D[3]),
.R(shift_count[2]));
FDRE \shift_o_reg[4]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\shift_o[4]_i_1_n_0 ),
.Q(D[4]),
.R(shift_count[2]));
FDRE \shift_o_reg[5]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\shift_o[5]_i_1_n_0 ),
.Q(D[5]),
.R(shift_count[2]));
FDRE \shift_o_reg[6]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\shift_o[6]_i_1_n_0 ),
.Q(D[6]),
.R(shift_count[2]));
FDRE \shift_o_reg[7]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\shift_o[7]_i_1_n_0 ),
.Q(D[7]),
.R(shift_count[2]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'hFFBF))
ss_o_i_1
(.I0(o_tx_rx_busy),
.I1(ss_o),
.I2(busy_o),
.I3(tx_done_reg_n_0),
.O(ss_o_i_1_n_0));
FDSE ss_o_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(ss_o_i_1_n_0),
.Q(ss_o),
.S(\send_data_reg[0]_0 ));
LUT5 #(
.INIT(32'hAAAA0002))
tx_done_i_1
(.I0(ss_o1),
.I1(shift_count[2]),
.I2(shift_count[0]),
.I3(shift_count[1]),
.I4(tx_done_reg_n_0),
.O(tx_done_i_1_n_0));
FDRE #(
.INIT(1'b0))
tx_done_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(tx_done_i_1_n_0),
.Q(tx_done_reg_n_0),
.R(\send_data_reg[0]_0 ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05.10.2017 13:19:42
// Design Name:
// Module Name: memoria_datos
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module memoria_datos(clk,EscrMem,Direc,Datain,LeerMem,Dataout);
input clk;
input EscrMem;//bit
input [31:0] Direc;
input [31:0] Datain;
input LeerMem;//bit
output reg [31:0] Dataout;
wire CSram1;
wire CSram2;
wire [2:0] CS;
wire [31:0] Dataout1;
wire [31:0] Dataout2;
wire [31:0] Dataout3;
wire CSrom;
sram sram1(.clk(clk),
.CSram(CSram1),
.Direc(Direc[7:0]),
.Datain(Datain),
.LeerMem(LeerMem),
.Dataout(Dataout1),
.EscrMem(EscrMem)
);
sram sram2(.clk(clk),
.CSram(CSram2),
.Direc(Direc[7:0]),
.Datain(Datain),
.LeerMem(LeerMem),
.Dataout(Dataout2),
.EscrMem(EscrMem)
);
sram ROM(
.clk(clk),
.CSram(CSrom),
.Direc(Direc[7:0]),
.Datain(Datain),
.LeerMem(LeerMem),
.Dataout(Dataout3),
.EscrMem(EscrMem)
);
assign CSrom = (Direc[31:8]==24'b0000_0000_0000_0000_0000_0100) ? 1 : 0 ;
assign CSram1 = ((Direc[31:8]==24'b0000_0000_0000_0000_0000_0000)|(Direc[31:8]==24'b0000_0000_0000_0000_0000_0001)) ? 1 : 0 ;
assign CSram2 = ((Direc[31:8]==24'b0000_0000_0000_0000_0000_0010)|(Direc[31:8]==24'b0000_0000_0000_0000_0000_0011)) ? 1 : 0 ;
assign CS = {CSrom,CSram1,CSram2};
always @ (*)
begin
case(CS)
3'b100:Dataout = Dataout3;
3'b010:Dataout = Dataout1;
3'b001:Dataout = Dataout2;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2111O_BLACKBOX_V
`define SKY130_FD_SC_HS__A2111O_BLACKBOX_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a2111o (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2111O_BLACKBOX_V
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module mvs_prog(
input nSDROE, RMPX,
input [23:20] RA_U,
input [9:8] RA_L,
input nSDPOE, PMPX,
input [11:8] PA,
input nSLOTCS,
input nPORTADRS, nPORTWEL, nPORTWEU, nPORTOEL, nPORTOEU,
input nROMOEL, nROMOEU,
input nAS, M68K_RW,
inout [15:0] M68K_DATA,
input [19:1] M68K_ADDR,
input CLK_68KCLKB,
output nROMWAIT, nPWAIT0, nPWAIT1, PDTACK,
input nROMOE,
input CLK_4MB, nRESET,
inout [7:0] PAD,
inout [7:0] RAD
);
//wire nPORTOE;
reg [23:0] V1_ADDR;
reg [23:0] V2_ADDR;
wire [23:0] V_ADDR;
wire [7:0] V_DATA;
//assign nPORTOE = nPORTOEL & nPORTOEU;
// Waitstate configuration
assign nROMWAIT = 1'b1;
assign nPWAIT0 = 1'b1;
assign nPWAIT1 = 1'b1;
assign PDTACK = 1'b1;
// Joy Joy Kid doesn't use PCM
pcm PCM(CLK_68KCLKB, nSDROE, RMPX, nSDPOE, PMPX, RAD, RA_L, RA_U, PAD, PA, V_DATA, V_ADDR);
// Joy Joy Kid:
//rom_p1 P1(M68K_ADDR[18:1], M68K_DATA, M68K_ADDR[19], nROMOE);
// Metal Slug:
rom_p1 P1({nPORTADRS, M68K_ADDR[19:1]}, M68K_DATA, 1'b0, nP1OE);
// Metal Slug: LS08s to enable P1
assign nPORTOE = nPORTOEL & nPORTOEU;
assign nP1OE = nROMOE & nPORTOE;
// Joy Joy Kid doesn't have a P2
//rom_p2 P2(M68K_ADDR[16:0], M68K_DATA, nPORTOE);
// Joy Joy Kid:
//rom_v1 V1(V1_ADDR[18:0], RAD, nROE);
//rom_v2 V2(V2_ADDR[18:0], PAD, nPOE);
// Metal Slug:
rom_v1 V1(V_ADDR[21:0], V_DATA, nV1_OE);
rom_v2 V2(V_ADDR[21:0], V_DATA, nV2_OE);
// Metal Slug: LS139 to switch V ROMs
assign nV1_OE = (V_ADDR[22:21] == 2'b00) ? 1'b0 : 1'b1;
assign nV2_OE = (V_ADDR[22:21] == 2'b01) ? 1'b0 : 1'b1;
// V ROMs address latches (discrete)
/*always @(posedge RMPX)
V1_ADDR[9:0] <= {RA_L[9:8], RAD};
always @(negedge RMPX)
V1_ADDR[23:10] <= {RA_U[23:20], RA_L[9:8], RAD};
always @(posedge PMPX)
V2_ADDR[11:0] <= {PA[11:8], PAD};
always @(negedge PMPX)
V2_ADDR[23:12] <= {PA[11:8], PAD};*/
endmodule
|
/*
Copyright (c) 2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for fpga_core
*/
module test_fpga_core;
// Parameters
parameter TARGET = "SIM";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg btnu = 0;
reg btnl = 0;
reg btnd = 0;
reg btnr = 0;
reg btnc = 0;
reg [7:0] sw = 0;
reg phy_rx_clk = 0;
reg [7:0] phy_rxd = 0;
reg phy_rx_dv = 0;
reg phy_rx_er = 0;
reg phy_tx_clk = 0;
reg uart_rxd = 1;
// Outputs
wire [7:0] led;
wire phy_gtx_clk;
wire [7:0] phy_txd;
wire phy_tx_en;
wire phy_tx_er;
wire phy_reset_n;
wire uart_txd;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
btnu,
btnl,
btnd,
btnr,
btnc,
sw,
phy_rx_clk,
phy_rxd,
phy_rx_dv,
phy_rx_er,
phy_tx_clk,
uart_rxd
);
$to_myhdl(
led,
phy_gtx_clk,
phy_txd,
phy_tx_en,
phy_tx_er,
phy_reset_n,
uart_txd
);
// dump file
$dumpfile("test_fpga_core.lxt");
$dumpvars(0, test_fpga_core);
end
fpga_core #(
.TARGET(TARGET)
)
UUT (
.clk(clk),
.rst(rst),
.btnu(btnu),
.btnl(btnl),
.btnd(btnd),
.btnr(btnr),
.btnc(btnc),
.sw(sw),
.led(led),
.phy_rx_clk(phy_rx_clk),
.phy_rxd(phy_rxd),
.phy_rx_dv(phy_rx_dv),
.phy_rx_er(phy_rx_er),
.phy_gtx_clk(phy_gtx_clk),
.phy_tx_clk(phy_tx_clk),
.phy_txd(phy_txd),
.phy_tx_en(phy_tx_en),
.phy_tx_er(phy_tx_er),
.phy_reset_n(phy_reset_n),
.uart_rxd(uart_rxd),
.uart_txd(uart_txd)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDLCLKP_4_V
`define SKY130_FD_SC_LS__SDLCLKP_4_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog wrapper for sdlclkp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdlclkp_4 (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdlclkp_4 (
GCLK,
SCE ,
GATE,
CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDLCLKP_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A31O_TB_V
`define SKY130_FD_SC_HDLL__A31O_TB_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a31o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 A3 = 1'b1;
#240 B1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 A3 = 1'b0;
#400 B1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B1 = 1'b1;
#600 A3 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B1 = 1'bx;
#760 A3 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hdll__a31o dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A31O_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41A_SYMBOL_V
`define SKY130_FD_SC_LS__O41A_SYMBOL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o41a (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41A_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O41AI_SYMBOL_V
`define SKY130_FD_SC_MS__O41AI_SYMBOL_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o41ai (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O41AI_SYMBOL_V
|
`include "config.inc"
module DCxPlus(
input wire clock54,
input wire clock74_175824,
input wire _hsync,
input wire _vsync,
input wire [11:0] data,
input wire HDMI_INT_N,
inout wire video_mode_480p_n,
output wire clock54_out,
inout wire SDAT,
inout wire SCLK,
output wire HSYNC,
output wire VSYNC,
output wire DE,
output wire CLOCK,
output wire [23:0] VIDEO,
output wire [3:0] S,
inout ESP_SDA,
input ESP_SCL,
input MAPLE_PIN1,
input MAPLE_PIN5,
inout wire status_led_nreset,
inout wire DC_NRESET
);
wire clock54_net;
wire pll54_locked;
// hdmi pll
wire hdmi_clock;
wire pll_hdmi_areset;
wire pll_hdmi_scanclk;
wire pll_hdmi_scandata;
wire pll_hdmi_scanclkena;
wire pll_hdmi_configupdate;
wire pll_hdmi_locked;
wire pll_hdmi_scandataout;
wire pll_hdmi_scandone;
// hdmi pll reconfig
wire pll_hdmi_reconfig;
wire pll_hdmi_write_from_rom;
wire pll_hdmi_rom_data_in;
wire [7:0] pll_hdmi_rom_address_out;
wire pll_hdmi_write_rom_ena;
// hdmi pll_reconf rom
wire reconf_fifo_rdempty;
wire [7:0] reconf_fifo_q;
wire reconf_fifo_rdreq;
wire reconf_fifo_wrreq;
wire reconf_fifo_wrfull;
wire [7:0] reconf_data;
// ---------------------------
wire [11:0] data_in_counter_x;
wire [11:0] data_in_counter_y;
wire [7:0] dc_blue;
wire [7:0] dc_green;
wire [7:0] dc_red;
wire ram_wren;
wire [`RAM_WIDTH-1:0] ram_wraddress;
wire [23:0] ram_wrdata;
wire [`RAM_WIDTH-1:0] ram_rdaddress;
wire [23:0] ram_rddata;
wire buffer_ready_trigger;
wire output_trigger;
wire _240p_480i_mode;
wire add_line_mode;
wire is_pal_mode;
//wire ram2video_ready;
wire [9:0] text_rdaddr;
wire [7:0] text_rddata;
wire [9:0] text_wraddr;
wire [7:0] text_wrdata;
wire text_wren;
wire enable_osd;
wire enable_osd_out;
wire [7:0] highlight_line;
//DebugData debugData;
ControllerData controller_data;
KeyboardData keyboard_data;
HDMIVideoConfig hdmiVideoConfig;
DCVideoConfig _dcVideoConfig;
DCVideoConfig dcVideoConfig;
Scanline scanline;
wire forceVGAMode;
wire resync;
wire [23:0] pinok;
wire [23:0] pinok_out;
wire [23:0] timingInfo;
wire [23:0] timingInfo_out;
wire [23:0] rgbData;
wire [23:0] rgbData_out;
wire [23:0] conf240p;
wire [23:0] conf240p_out;
wire force_generate;
wire generate_video;
wire generate_timing;
wire [7:0] video_gen_data;
wire activateHDMIoutput;
wire hq2x;
wire [1:0] colorspace;
wire [1:0] colorspace_data;
wire hq2x_out;
wire r2v_f;
wire fullcycle;
wire reset_dc;
wire reset_opt;
wire [7:0] reset_conf;
wire control_clock;
//wire control_clock_2;
wire hdmi_int_reg;
wire hpd_detected;
wire _config_changed;
wire config_changed;
wire _nonBlackPixelReset;
wire nonBlackPixelReset;
wire [11:0] nonBlackPos1;
wire [11:0] nonBlackPos2;
wire [11:0] nonBlackPos1_out;
wire [11:0] nonBlackPos2_out;
wire [23:0] color_space_explorer;
wire [23:0] color_space_explorer_out;
wire [7:0] color_config_data;
wire [7:0] color_config_data_out;
wire resetpll;
assign clock54_out = clock54_net;
// DC config in, ics config out
configuration configurator(
.clock(control_clock),
// inputs
.dcVideoConfig(_dcVideoConfig),
.forceVGAMode(forceVGAMode),
.force_generate(control_force_generate_out /*force_generate*/),
// output
.config_changed(_config_changed),
.line_doubler(line_doubler_sync2 /*_240p_480i_mode*/),
// output pins
.clock_config_S(S),
._480p_active_n(video_mode_480p_n)
);
/////////////////////////////////
// PLLs
pll54 pll54(
.inclk0(clock54),
.areset(resetpll),
.c0(clock54_net),
.locked(pll54_locked)
);
pll_hdmi pll_hdmi(
.inclk0(clock74_175824),
.c0(hdmi_clock),
.c1(CLOCK),
.locked(pll_hdmi_locked),
.areset(pll_hdmi_areset),
.scanclk(pll_hdmi_scanclk),
.scandata(pll_hdmi_scandata),
.scanclkena(pll_hdmi_scanclkena),
.configupdate(pll_hdmi_configupdate),
.scandataout(pll_hdmi_scandataout),
.scandone(pll_hdmi_scandone)
);
wire pll_reconf_busy;
pll_hdmi_reconf pll_hdmi_reconf(
.clock(control_clock),
.reconfig(pll_hdmi_reconfig),
.busy(pll_reconf_busy),
.data_in(9'b0),
.counter_type(4'b0),
.counter_param(3'b0),
.pll_areset_in(pll54_lockloss /*|| pll_hdmi_lockloss*/),
.pll_scandataout(pll_hdmi_scandataout),
.pll_scandone(pll_hdmi_scandone),
.pll_areset(pll_hdmi_areset),
.pll_configupdate(pll_hdmi_configupdate),
.pll_scanclk(pll_hdmi_scanclk),
.pll_scanclkena(pll_hdmi_scanclkena),
.pll_scandata(pll_hdmi_scandata),
.write_from_rom(pll_hdmi_write_from_rom),
.rom_data_in(pll_hdmi_rom_data_in),
.rom_address_out(pll_hdmi_rom_address_out),
.write_rom_ena(pll_hdmi_write_rom_ena)
);
wire is_pll54_locked;
wire is_pll_hdmi_locked;
Signal_CrossDomain isPll54Locked(.SignalIn_clkA(pll54_locked), .clkB(control_clock), .SignalOut_clkB(is_pll54_locked));
Signal_CrossDomain isPllHdmiLocked(.SignalIn_clkA(pll_hdmi_locked), .clkB(control_clock), .SignalOut_clkB(is_pll_hdmi_locked));
pll_hdmi_reconfig reconf_rom(
.clock(control_clock),
.address(pll_hdmi_rom_address_out),
.read_ena(pll_hdmi_write_rom_ena),
.pll_reconf_busy(pll_reconf_busy || ~is_pll54_locked || ~is_pll_hdmi_locked),
.data(reconf_data/*reconf_data_clock54*/),
.q(pll_hdmi_rom_data_in),
.reconfig(pll_hdmi_reconfig),
.trigger_read(pll_hdmi_write_from_rom)
);
/////////////////////////////////
// 54/27 MHz area
wire [7:0] reconf_data_clock54;
data_cross #(
.WIDTH($bits(DCVideoConfig) + 3 + $bits(conf240p) + $bits(video_gen_data) + $bits(color_config_data))
) dcVideoConfig_cross(
.clkIn(control_clock),
.clkOut(clock54_net),
.dataIn({ _dcVideoConfig, _config_changed, line_doubler_sync2, _nonBlackPixelReset, conf240p, video_gen_data, color_config_data }),
.dataOut({ dcVideoConfig, config_changed, _240p_480i_mode, nonBlackPixelReset, conf240p_out, { 6'bzzzzzz, generate_video, generate_timing }, color_config_data_out })
);
dc_video_reconfig dc_video_configurator(
.clock(control_clock),
.data_in(reconf_data),
.dcVideoConfig(_dcVideoConfig),
.forceVGAMode(forceVGAMode)
);
data video_input(
.clock(clock54_net),
.reset(~pll54_locked || config_changed),
._hsync(_hsync),
._vsync(_vsync),
.line_doubler(_240p_480i_mode),
.generate_video(generate_video),
.generate_timing(generate_timing),
.indata(data),
.add_line(add_line_mode),
.is_pal(is_pal_mode),
.resync(resync),
.force_generate(force_generate),
.blue(dc_blue),
.counterX(data_in_counter_x),
.counterY(data_in_counter_y),
.green(dc_green),
.red(dc_red),
.pinok(pinok),
.timingInfo(timingInfo),
.rgbData(rgbData),
.conf240p(conf240p_out),
.nonBlackPos1(nonBlackPos1),
.nonBlackPos2(nonBlackPos2),
.nonBlackPixelReset(nonBlackPixelReset),
.color_space_explorer(color_space_explorer)
);
video2ram video2ram(
.clock(clock54_net),
.nreset(~resync),
.line_doubler(_240p_480i_mode),
.is_pal(is_pal_mode),
.B(dc_blue),
.counterX(data_in_counter_x),
.counterY(data_in_counter_y),
.G(dc_green),
.R(dc_red),
.wren(ram_wren),
.starttrigger(buffer_ready_trigger),
.wraddr(ram_wraddress),
.wrdata(ram_wrdata),
.dcVideoConfig(dcVideoConfig),
.color_config_data(color_config_data_out)
);
/////////////////////////////////
// clock domain crossing
ram video_buffer(
.wrclock(clock54_net),
.wren(ram_wren),
.wraddress(ram_wraddress),
.data(ram_wrdata),
.rdclock(hdmi_clock),
.rdaddress(ram_rdaddress),
.q(ram_rddata)
);
Flag_CrossDomain trigger(
.clkA(clock54_net),
.FlagIn_clkA(buffer_ready_trigger),
.clkB(hdmi_clock),
.FlagOut_clkB(output_trigger)
);
/////////////////////////////////
// HDMI clock area
reg prev_resync_out = 0;
reg resync_out = 0;
reg resync_signal = 1;
wire line_doubler_sync;
wire line_doubler_sync2;
wire add_line_sync;
wire is_pal_sync;
wire [7:0] reconf_data_hdmi;
wire is_interlaced;
Flag_CrossDomain #(
.INIT_STATE(1'b1)
) rsync_trigger (
.clkA(clock54_net),
.FlagIn_clkA(resync),
.clkB(hdmi_clock),
.FlagOut_clkB(resync_out)
);
always @(posedge hdmi_clock) begin
if (~prev_resync_out && resync_out) begin
resync_signal <= 1'b1;
end else if (prev_resync_out && ~resync_out) begin
resync_signal <= 1'b0;
end
prev_resync_out <= resync_out;
end
Signal_CrossDomain lineDoubler(
.SignalIn_clkA(_240p_480i_mode),
.clkB(hdmi_clock),
.SignalOut_clkB(line_doubler_sync)
);
data_cross reconfDataHdmi(
.clkIn(control_clock),
.clkOut(hdmi_clock),
.dataIn(reconf_data),
.dataOut(reconf_data_hdmi)
);
hdmi_video_reconfig hdmi_video_configurator(
.clock(hdmi_clock),
.data_in(reconf_data_hdmi),
.r2v_f(r2v_f),
.hdmiVideoConfig(hdmiVideoConfig)
);
Flag_CrossDomain enable_osd_cross(
.clkA(control_clock),
.FlagIn_clkA(enable_osd),
.clkB(hdmi_clock),
.FlagOut_clkB(enable_osd_out)
);
Flag_CrossDomain enable_hq2x_cross(
.clkA(control_clock),
.FlagIn_clkA(hq2x),
.clkB(hdmi_clock),
.FlagOut_clkB(hq2x_out)
);
Signal_CrossDomain isInterlacedSig(
.SignalIn_clkA(~add_line_mode && _240p_480i_mode),
.clkB(hdmi_clock),
.SignalOut_clkB(is_interlaced)
);
`ifdef std
`include "DCxPlus-std.v"
`elsif hq2x
`include "DCxPlus-hq2x.v"
`endif
text_ram text_ram_inst(
.rdclock(hdmi_clock),
.rdaddress(text_rdaddr),
.q(text_rddata),
.wrclock(control_clock),
.wraddress(text_wraddr),
.data(text_wrdata),
.wren(text_wren)
);
////////////////////////////////////////////////////////////////////////
// dreamcast reset and control, also ADV7513 I2C control
////////////////////////////////////////////////////////////////////////
// reset clock circuit
osc control_clock_gen(
.oscena(1'b1),
.clkout(control_clock)
);
////////////////////////////////////////////////////////
reg pll54_lockloss;
reg pll_hdmi_lockloss;
edge_detect pll54_lockloss_check(
.async_sig(~pll54_locked),
.clk(control_clock),
.rise(pll54_lockloss)
);
edge_detect pll_hdmi_lockloss_check(
.async_sig(~pll_hdmi_locked),
.clk(control_clock),
.rise(pll_hdmi_lockloss)
);
data_cross #(
.WIDTH(24 + 24 + 24 + 12 + 12 + 24)
) pinok_cross(
.clkIn(clock54_net),
.clkOut(control_clock),
.dataIn({ pinok, timingInfo, rgbData, nonBlackPos1, nonBlackPos2, color_space_explorer }),
.dataOut({ pinok_out, timingInfo_out, rgbData_out, nonBlackPos1_out, nonBlackPos2_out, color_space_explorer_out })
);
Signal_CrossDomain addLine(
.SignalIn_clkA(add_line_mode),
.clkB(control_clock),
.SignalOut_clkB(add_line_sync)
);
Signal_CrossDomain isPAL(
.SignalIn_clkA(is_pal_mode),
.clkB(control_clock),
.SignalOut_clkB(is_pal_sync)
);
reg[31:0] counter = 0;
reg[31:0] counter2 = 0;
reg dc_nreset_reg = 1'b1;
reg opt_nreset_reg = 1'b1;
reg status_led_nreset_reg = 1'bz;
reg control_resync_out;
reg control_force_generate_out;
assign DC_NRESET = (dc_nreset_reg ? 1'bz : 1'b0);
assign status_led_nreset = status_led_nreset_reg;
wire slowGlow_out;
wire fastGlow_out;
wire dim_out;
LEDglow #(
.BITPOS(26)
) slowGlow (
.clk(control_clock),
.LED(slowGlow_out)
);
LEDglow #(
.BITPOS(22)
) fastGlow (
.clk(control_clock),
.LED(fastGlow_out)
);
LEDdim dimled (
.clk(control_clock),
.LED(dim_out)
);
Flag_CrossDomain #(
.INIT_STATE(1'b1)
) control_rsync (
.clkA(clock54_net),
.FlagIn_clkA(resync),
.clkB(control_clock),
.FlagOut_clkB(control_resync_out)
);
Flag_CrossDomain control_force_generate(
.clkA(clock54_net),
.FlagIn_clkA(force_generate),
.clkB(control_clock),
.FlagOut_clkB(control_force_generate_out)
);
reg [31:0] led_counter = 0;
`ifdef DIAG_MODE
always @(posedge control_clock) begin
if (adv_i2c_working) begin
status_led_nreset_reg <= ~slowGlow_out;
end else if (~pll_ready) begin
status_led_nreset_reg <= ~dim_out;
end else begin
status_led_nreset_reg <= ~fastGlow_out;
end
end
`else
always @(posedge control_clock) begin
if (reset_conf == 2'd0) begin // LED
if (~pll_ready) begin
status_led_nreset_reg <= ~dim_out;
end else if (control_resync_out) begin
status_led_nreset_reg <= ~fastGlow_out;
end else if (control_force_generate_out) begin
if (led_counter[24]) begin
status_led_nreset_reg <= ~fastGlow_out;
end else begin
status_led_nreset_reg <= 1'b1;
end
end else begin
if (adv7513_ready) begin
status_led_nreset_reg <= 1'b0;
end else begin
status_led_nreset_reg <= ~slowGlow_out;
end
end
end else if (reset_conf == 2'd1 || reset_conf == 2'd3) begin // GDEMU || MODE
status_led_nreset_reg <= (opt_nreset_reg ? 1'bz : 1'b0);
end else if (reset_conf == 2'd2) begin // USBGDROM
status_led_nreset_reg <= (dc_nreset_reg ? 1'bz : 1'b0);
end else begin
status_led_nreset_reg <= 1'bz;
end
led_counter <= led_counter + 1'b1;
end
`endif
localparam RESET_HOLD_TIME = 32'd32_000_000;
always @(posedge control_clock) begin
if (reset_dc) begin
counter <= 0;
dc_nreset_reg <= 1'b0;
end else begin
counter <= counter + 1;
if (counter == RESET_HOLD_TIME) begin
dc_nreset_reg <= 1'b1;
end
end
end
always @(posedge control_clock) begin
if (reset_opt) begin
counter2 <= 0;
opt_nreset_reg <= 1'b0;
end else begin
counter2 <= counter2 + 1;
if (counter2 == RESET_HOLD_TIME) begin
opt_nreset_reg <= 1'b1;
end
end
end
wire [7:0] highlight_line_in;
Scanline scanline_in;
data_cross highlight_line_cross(
.clkIn(control_clock),
.clkOut(hdmi_clock),
.dataIn(highlight_line_in),
.dataOut(highlight_line)
);
data_cross #(
.WIDTH($bits(Scanline))
) scanline_cross(
.clkIn(control_clock),
.clkOut(hdmi_clock),
.dataIn(scanline_in),
.dataOut(scanline)
);
i2cSlave i2cSlave(
.clk(control_clock),
.rst(1'b0),
.sda(ESP_SDA),
.scl(ESP_SCL),
.ram_dataIn(text_wrdata),
.ram_wraddress(text_wraddr),
.ram_wren(text_wren),
.enable_osd(enable_osd),
//.debugData(debugData),
.highlight_line(highlight_line_in),
.reconf_data(reconf_data),
.scanline(scanline_in),
.controller_data(controller_data),
.keyboard_data(keyboard_data),
.reset_dc(reset_dc),
.reset_opt(reset_opt),
.reset_conf(reset_conf),
.pinok(pinok_out),
.timingInfo(timingInfo_out),
.rgbData(rgbData_out),
.conf240p(conf240p),
.add_line(add_line_sync),
.line_doubler(line_doubler_sync2),
.is_pal(is_pal_sync),
.video_gen_data(video_gen_data),
.activateHDMIoutput(activateHDMIoutput),
.hq2x(hq2x),
.colorspace(colorspace_data),
.force_generate(control_force_generate_out),
.pll_adv_lockloss_count(pll_adv_lockloss_count),
.hpd_low_count(hpd_low_count),
.pll54_lockloss_count(pll54_lockloss_count),
.pll_hdmi_lockloss_count(pll_hdmi_lockloss_count),
.control_resync_out_count(control_resync_out_count),
.monitor_sense_low_count(monitor_sense_low_count),
.testdata({
HDMI_INT_N,
adv7513_reconf,
startup_ready,
pll_ready,
ram2video_fullcycle,
status_led_nreset,
is_pll54_locked,
is_pll_hdmi_locked,
_config_changed,
line_doubler_sync2,
control_resync_out,
forceVGAMode,
video_mode_480p_n,
3'b0
}),
.clock_config_data(clock_config_data),
.color_config_data(color_config_data),
.nonBlackPos1(nonBlackPos1_out),
.nonBlackPos2(nonBlackPos2_out),
.nonBlackPixelReset(_nonBlackPixelReset),
.color_space_explorer(color_space_explorer_out),
.resetpll(resetpll)
);
maple mapleBus(
.clk(control_clock),
.reset(1'b0),
.pin1(MAPLE_PIN1),
.pin5(MAPLE_PIN5),
.controller_data(controller_data),
.keyboard_data(keyboard_data)
);
////////////////////////////////////////////////////////////////////////
wire [31:0] pll_adv_lockloss_count;
wire [31:0] hpd_low_count;
wire [31:0] monitor_sense_low_count;
reg [31:0] pll54_lockloss_count = 0;
reg [31:0] pll_hdmi_lockloss_count = 0;
reg [31:0] control_resync_out_count = 0;
reg prev_control_resync_out = 0;
always @(posedge control_clock) begin
if (pll54_lockloss) begin
pll54_lockloss_count <= pll54_lockloss_count + 1'b1;
end
if (pll_hdmi_lockloss) begin
pll_hdmi_lockloss_count <= pll_hdmi_lockloss_count + 1'b1;
end
prev_control_resync_out <= control_resync_out;
if (~prev_control_resync_out && control_resync_out) begin
control_resync_out_count <= control_resync_out_count + 1'b1;
end
end
////////////////////////////////////////////////////////////////////////
// // I2C master clock divisions
// // divider = (pixel_clock / bus_clk) / 4; bus_clk = 400_000
// // divider[31:24] = div4
// // divider[23:16] = div3
// // divider[15:8] = div2
// // divider[7:0] = div1
// reg [31:0] divider;
wire startup_ready;
wire adv7513_ready;
ADV7513Config adv7513Config;
wire reconf_fifo2_rdempty;
wire [7:0] reconf_fifo2_q;
wire reconf_fifo2_rdreq;
wire pll_ready;
wire ram2video_fullcycle;
Signal_CrossDomain pll_hdmi_locked_check_adv(
.SignalIn_clkA(pll54_locked),
.clkB(control_clock),
.SignalOut_clkB(pll_ready)
);
Signal_CrossDomain ram2video_fullcycle_check_adv(
.SignalIn_clkA(fullcycle),
.clkB(control_clock),
.SignalOut_clkB(ram2video_fullcycle)
);
startup adv7513_startup_delay(
.clock(control_clock),
.nreset(1'b1),
.ready(startup_ready),
.startup_delay(32'd_64_000_000)
);
wire adv_i2c_working;
wire adv7513_reconf;
wire [7:0] clock_config_data;
wire [7:0] clock_data;
adv7513_reconfig reconf_adv(
.clock(control_clock),
.data_in(reconf_data),
.clock_config_data(clock_config_data),
.colorspace_in(colorspace_data),
.adv7513Config(adv7513Config),
.clock_data_out(clock_data),
.colorspace_out(colorspace),
.adv7513_reconf(adv7513_reconf)
);
ADV7513 adv7513(
.clk(control_clock),
.reset(startup_ready),
.hdmi_int(HDMI_INT_N & ~adv7513_reconf),
.output_ready(startup_ready & pll_ready & ram2video_fullcycle & ~adv7513_reconf),
.sda(SDAT),
.scl(SCLK),
.ready(adv7513_ready),
.adv7513Config(adv7513Config),
.clock_data(clock_data),
.colorspace(colorspace),
.hdmi_int_reg(hdmi_int_reg),
.hpd_detected(hpd_detected),
.pll_adv_lockloss_count(pll_adv_lockloss_count),
.hpd_low_count(hpd_low_count),
.monitor_sense_low_count(monitor_sense_low_count),
.i2c_working(adv_i2c_working)
);
endmodule
|
//**********************************************************************
// Reset
// ______ _______ ______ _______ _______
// (_____ \(_______)/ _____|_______|_______)
// _____) )_____ ( (____ _____ _
// | __ /| ___) \____ \| ___) | |
// | | \ \| |_____ _____) ) |_____ | |
// |_| |_|_______|______/|_______) |_|
//
//**********************************************************************
`include "bsg_defines.v"
module bsg_nonsynth_reset_gen #(parameter num_clocks_p=1
, parameter `BSG_INV_PARAM(reset_cycles_lo_p)
, parameter `BSG_INV_PARAM(reset_cycles_hi_p))
(input bit [num_clocks_p-1:0] clk_i
, output bit async_reset_o);
genvar i;
// This module relies on the input clock wires starting at 0 at
// time 0 and not transitioning from X to 0 at time 0, and causing
// a spurious negedge. To accomplish this in > VCS 2020, the input
// must be declared as a bit. Moreover, the expectation is that
// this module's input comes from a clock generation module that
// uses bit, such as bsg_nonsynth_clk_gen, AND that the wire
// between them is a bit.
// use bit instead of logic to default to 0 initialization value
// this makes it non-synthesizeable, but also allows X prop mode to work
bit [num_clocks_p-1:0][$clog2(reset_cycles_lo_p+1)-1:0] ctr_lo_r;
bit [num_clocks_p-1:0][$clog2(reset_cycles_hi_p+1)-1:0] ctr_hi_r;
bit [num_clocks_p-1:0] phase_lo_r;
bit [num_clocks_p-1:0] phase_hi_r;
wire in_phase_1 = & phase_lo_r;
wire in_phase_2 = & phase_hi_r;
for (i = 0; i < num_clocks_p; i=i+1)
begin : rof
assign phase_lo_r[i] = (ctr_lo_r[i] == reset_cycles_lo_p);
assign phase_hi_r[i] = (ctr_hi_r[i] == reset_cycles_hi_p);
always @(negedge clk_i[i])
if (~phase_lo_r[i])
ctr_lo_r[i] <= ctr_lo_r[i] + 1;
else if (~phase_hi_r[i])
ctr_hi_r[i] <= ctr_hi_r[i] + in_phase_1;
end
assign async_reset_o = (in_phase_1 ^ in_phase_2);
always @(negedge async_reset_o)
begin
$display("__________ ___________ _______________________________");
$display("\\______ \\\\_ _____/ / _____/\\_ _____/\\__ ___/");
$display(" | _/ | __)_ \\_____ \\ | __)_ | | ");
$display(" | | \\ | \\ / \\ | \\ | | 1->0 time = ",$stime);
$display(" |____|_ //_______ //_______ //_______ / |____| ");
$display(" ASYNC \\/ \\/ \\/ \\/ ");
end
always @(posedge async_reset_o)
begin
$display("__________ ___________ _______________________________");
$display("\\______ \\\\_ _____/ / _____/\\_ _____/\\__ ___/");
$display(" | _/ | __)_ \\_____ \\ | __)_ | | ");
$display(" | | \\ | \\ / \\ | \\ | | 0->1 time = ",$stime);
$display(" |____|_ //_______ //_______ //_______ / |____| ");
$display(" ASYNC \\/ \\/ \\/ \\/ ");
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_nonsynth_reset_gen)
|
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