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//////////////////////////////////////////////////////////////////////
//// ////
//// File name "ge_1000baseX_an.v" ////
//// ////
//// This file is part of the : ////
//// ////
//// "1000BASE-X IEEE 802.3-2008 Clause 36 - PCS project" ////
//// ////
//// http://opencores.org/project,1000base-x ////
//// ////
//// Author(s): ////
//// - D.W.Pegler Cambridge Broadband Networks Ltd ////
//// ////
//// { [email protected], [email protected] } ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// This module is based on the coding method described in ////
//// IEEE Std 802.3-2008 Clause 37" Auto-Negotiation function, ////
//// type 1000BASE-X"; see : ////
//// ////
//// http://standards.ieee.org/about/get/802/802.3.html ////
//// and ////
//// doc/802.3-2008_section3.pdf, Clause 37. ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "ge_1000baseX_constants.v"
`include "timescale.v"
module ge_1000baseX_an #(
parameter BASEX_AN_MODE = 0
) (
// --- clocks and reset ---
input ck,
input reset,
// --- Startup interface. ---
input startup_enable,
// --- Auto-negotiation ctrl parameter ---
output reg [2:0] xmit,
output reg [15:0] tx_config,
input [15:0] rx_config,
input rx_config_set,
input ability_match,
input acknowledge_match,
input consistency_match,
input idle_match,
// --- RX_UNITDATA.indicate messages from RX state machine ---
input [2:0] rudi,
// --- Synchronisation Status ---
input sync_status,
// --- GMII Register 0 - AN Basic Control register ---
input mr_main_reset,
input mr_loopback,
input mr_restart_an,
input mr_an_enable,
// --- GMII Register 1 - AN Basic Status register ---
output reg mr_an_complete,
// --- GMII register 4 - AN Advertisement
input [15:0] mr_adv_ability,
// --- GMII register 5 - AN Link Partner Ability
output reg [15:0] mr_lp_adv_ability,
// --- GMII register 6 - AN Expansion
output reg mr_np_abl,
output reg mr_page_rx,
// --- GMII register 7 - AN Next Page
input [15:0] mr_np_tx,
// --- GMII register 8 - AN Link Partner Next Page
output reg [15:0] mr_lp_np_rx,
// --- DEBUG
output [3:0] debug_pcs_an_present,
output [17:0] debug_linktimer,
output reg debug_an_restart_state
);
//////////////////////////////////////////////////////////////////////////////
//
//////////////////////////////////////////////////////////////////////////////
reg mr_np_loaded;
//////////////////////////////////////////////////////////////////////////////
//
//////////////////////////////////////////////////////////////////////////////
`ifdef MODEL_TECH
enum logic [3:0] {
`else
localparam
`endif
S_PCS_AN_STARTUP_RUN = 0,
S_PCS_AN_ENABLE = 1,
S_PCS_AN_RESTART = 2,
S_PCS_AN_DISABLE_LINK_OK = 3,
S_PCS_AN_ABILITY_DETECT = 4,
S_PCS_AN_ACKNOWLEDGE_DETECT = 5,
S_PCS_AN_COMPLETE_ACKNOWLEDGE = 6,
S_PCS_AN_IDLE_DETECT = 7,
S_PCS_AN_LINK_OK = 8,
S_PCS_AN_NEXT_PAGE_WAIT = 9
`ifdef MODEL_TECH
} pcs_an_present, pcs_an_next;
`else
; reg [3:0] pcs_an_present, pcs_an_next;
`endif
assign debug_pcs_an_present = pcs_an_present;
//////////////////////////////////////////////////////////////////////////////
// rx configuration
//////////////////////////////////////////////////////////////////////////////
wire rx_config_clr = ~rx_config_set;
//////////////////////////////////////////////////////////////////////////////
// Link timer
//////////////////////////////////////////////////////////////////////////////
`ifdef MODEL_TECH // if Modelsim
`define LINK_TIMER_DONE 2000
`else
`ifdef _VCP // if Aldec Riviera
`define LINK_TIMER_DONE 2000
`else
`define LINK_TIMER_DONE 200000
`endif
`endif
reg [17:0] link_timer_cnt;
reg link_timer_m_start, link_timer_m_inc;
wire link_timer_done;
always @(posedge ck, posedge reset)
if (reset)
begin
link_timer_cnt <= 0;
end
else
begin
if (link_timer_m_start) link_timer_cnt <= 0;
else if (link_timer_m_inc) link_timer_cnt <= link_timer_cnt + 1;
end
assign link_timer_done = (link_timer_cnt >= `LINK_TIMER_DONE);
assign debug_linktimer = link_timer_cnt;
//////////////////////////////////////////////////////////////////////////////
// xmit - set to tell TX state machine state of AN
//////////////////////////////////////////////////////////////////////////////
reg xmit_CONFIGURATION_m_set, xmit_DATA_m_set, xmit_IDLE_m_set;
always @(posedge ck, posedge reset)
if (reset)
xmit <= `XMIT_IDLE;
else
begin
if (~mr_an_enable & rudi != `RUDI_INVALID) xmit <= `XMIT_DATA;
else if (xmit_CONFIGURATION_m_set) xmit <= `XMIT_CONFIGURATION;
else if (xmit_DATA_m_set) xmit <= `XMIT_DATA;
else if (xmit_IDLE_m_set) xmit <= `XMIT_IDLE;
end
//////////////////////////////////////////////////////////////////////////////
// mr_lp_adv_ability - variable to store Link partner capabilities
//////////////////////////////////////////////////////////////////////////////
reg mr_lp_adv_ability_set, mr_lp_adv_ability_clr;
always @(posedge ck, posedge reset)
if (reset)
mr_lp_adv_ability <= 16'h0;
else
begin
if (mr_lp_adv_ability_set) mr_lp_adv_ability <= rx_config;
else if (mr_lp_adv_ability_clr) mr_lp_adv_ability <= 16'h00;
end
//////////////////////////////////////////////////////////////////////////////
// mr_np_loaded - variable to indicate if the next page has been loaded
//////////////////////////////////////////////////////////////////////////////
reg mr_np_loaded_m_set, mr_np_loaded_m_clr;
always @(posedge ck, posedge reset)
if (reset)
mr_np_loaded <= 0;
else
begin
if (mr_np_loaded_m_set) mr_np_loaded <= 1;
else if (mr_np_loaded_m_clr) mr_np_loaded <= 0;
end
//////////////////////////////////////////////////////////////////////////////
// mr_page_rx_m_clr
//////////////////////////////////////////////////////////////////////////////
reg mr_page_rx_m_set, mr_page_rx_m_clr;
always @(posedge ck, posedge reset)
if (reset)
mr_page_rx <= 0;
else
begin
if (mr_page_rx_m_set) mr_page_rx <= 1;
else if (mr_page_rx_m_clr) mr_page_rx <= 0;
end
//////////////////////////////////////////////////////////////////////////////
// mr_an_complete
//////////////////////////////////////////////////////////////////////////////
reg mr_an_complete_m_set, mr_an_complete_m_clr;
always @(posedge ck, posedge reset)
if (reset)
mr_an_complete <= 0;
else
begin
if (mr_an_complete_m_set) mr_an_complete <= 1;
else if (mr_an_complete_m_clr) mr_an_complete <= 0;
end
//////////////////////////////////////////////////////////////////////////////
// toggle_tx
//////////////////////////////////////////////////////////////////////////////
reg toggle_tx, toggle_tx_adv_m_set, toggle_tx_toggle_m_set;
always @(posedge ck, posedge reset)
if (reset)
toggle_tx <= 0;
else
begin
if (toggle_tx_adv_m_set) toggle_tx <= mr_adv_ability[12];
else if (toggle_tx_toggle_m_set) toggle_tx <= ~toggle_tx;
end
//////////////////////////////////////////////////////////////////////////////
// toggle_rx
//////////////////////////////////////////////////////////////////////////////
reg toggle_rx, toggle_rx_m_set;
always @(posedge ck, posedge reset)
if (reset)
toggle_rx <= 0;
else
begin
if (toggle_rx_m_set) toggle_rx <= rx_config[11];
end
//////////////////////////////////////////////////////////////////////////////
// tx_config register ctrl
//////////////////////////////////////////////////////////////////////////////
reg tx_config_m_clr, tx_config_ABILITY_m_set, tx_config_ACK_m_set, tx_config_NP_m_set;
always @(posedge ck, posedge reset)
if (reset)
tx_config <= 0;
else
begin
if (tx_config_m_clr) tx_config <= 0;
else if (tx_config_ACK_m_set) tx_config[14] <= 1;
else if (tx_config_ABILITY_m_set) tx_config <= { mr_adv_ability[15],1'b0, mr_adv_ability[13:0] };
else if (tx_config_NP_m_set) tx_config <= { mr_np_tx[15], 1'b0, mr_np_tx[13:12], toggle_tx,mr_np_tx[10:0] };
end
//////////////////////////////////////////////////////////////////////////////
// np_rx
//////////////////////////////////////////////////////////////////////////////
reg np_rx, np_rx_m_set;
always @(posedge ck, posedge reset)
if (reset)
np_rx <= 0;
else
begin
if (np_rx_m_set) np_rx <= rx_config[15];
end
//////////////////////////////////////////////////////////////////////////////
// mr_lp_np_rx
//////////////////////////////////////////////////////////////////////////////
reg mr_lp_np_rx_m_set;
always @(posedge ck, posedge reset)
if (reset)
mr_lp_np_rx <= 0;
else
begin
if (mr_lp_np_rx_m_set) mr_lp_np_rx <= rx_config[15];
end
//////////////////////////////////////////////////////////////////////////////
// np_page_rx
//////////////////////////////////////////////////////////////////////////////
reg np_page_rx, np_page_rx_m_set;
always @(posedge ck, posedge reset)
if (reset)
np_page_rx <= 0;
else
begin
if (np_page_rx_m_set) np_page_rx <= 1;
end
//////////////////////////////////////////////////////////////////////////////
// resolve_priority
//////////////////////////////////////////////////////////////////////////////
reg resolve_priority, resolve_priority_m_set;
always @(posedge ck, posedge reset)
if (reset)
resolve_priority <= 0;
else
begin
if (resolve_priority_m_set) resolve_priority <= 1;
end
//////////////////////////////////////////////////////////////////////////////
// autonegotiation state machine registered part
//////////////////////////////////////////////////////////////////////////////
always @(posedge ck, posedge reset)
pcs_an_present <= (reset) ? S_PCS_AN_STARTUP_RUN : pcs_an_next;
//////////////////////////////////////////////////////////////////////////////
// autonegotiation state machine - IEEE 802.3-2008 Clause 36
//////////////////////////////////////////////////////////////////////////////
always @*
begin
pcs_an_next = pcs_an_present;
xmit_CONFIGURATION_m_set = 0; xmit_DATA_m_set = 0; xmit_IDLE_m_set = 0;
mr_np_loaded_m_set = 0; mr_np_loaded_m_clr = 0;
mr_page_rx_m_set = 0; mr_page_rx_m_clr = 0;
mr_an_complete_m_set = 0; mr_an_complete_m_clr = 0;
mr_lp_adv_ability_set = 0; mr_lp_adv_ability_clr = 0;
tx_config_m_clr = 0; tx_config_ABILITY_m_set = 0;tx_config_ACK_m_set = 0;tx_config_NP_m_set = 0;
link_timer_m_start = 0; link_timer_m_inc = 0;
toggle_tx_adv_m_set = 0; toggle_tx_toggle_m_set = 0;
toggle_rx_m_set = 0; mr_lp_np_rx_m_set = 0; np_rx_m_set = 0; np_page_rx_m_set = 0;
resolve_priority_m_set = 0;
debug_an_restart_state = 0;
case (pcs_an_present)
S_PCS_AN_STARTUP_RUN:
begin
pcs_an_next = startup_enable ? S_PCS_AN_ENABLE: S_PCS_AN_STARTUP_RUN;
end
S_PCS_AN_ENABLE:
begin
mr_page_rx_m_clr = 1; mr_lp_adv_ability_clr = 1; mr_an_complete_m_clr = 1;
if (mr_an_enable)
begin
xmit_CONFIGURATION_m_set = 1; tx_config_m_clr = 1;
end
else xmit_IDLE_m_set = 1;
pcs_an_next = (mr_an_enable) ? S_PCS_AN_RESTART : S_PCS_AN_DISABLE_LINK_OK;
link_timer_m_start = mr_an_enable;
end
S_PCS_AN_RESTART:
begin
mr_np_loaded_m_clr = 1; tx_config_m_clr = 1; xmit_CONFIGURATION_m_set = 1;
pcs_an_next = (link_timer_done) ? S_PCS_AN_ABILITY_DETECT : S_PCS_AN_RESTART;
debug_an_restart_state = 1;
link_timer_m_inc = ~link_timer_done;
end
S_PCS_AN_DISABLE_LINK_OK:
begin
xmit_DATA_m_set = 1;
pcs_an_next = S_PCS_AN_DISABLE_LINK_OK;
end
S_PCS_AN_ABILITY_DETECT:
begin
toggle_tx_adv_m_set = 1; tx_config_ABILITY_m_set = 1;
pcs_an_next = (ability_match & rx_config_set) ? S_PCS_AN_ACKNOWLEDGE_DETECT : S_PCS_AN_ABILITY_DETECT;
mr_lp_adv_ability_set = (ability_match & rx_config_set);
end
S_PCS_AN_ACKNOWLEDGE_DETECT:
begin
tx_config_ACK_m_set = 1;
pcs_an_next = (acknowledge_match & consistency_match) ? S_PCS_AN_COMPLETE_ACKNOWLEDGE :
(acknowledge_match & ~consistency_match) ? S_PCS_AN_ENABLE :
(ability_match & rx_config_clr) ? S_PCS_AN_ENABLE : S_PCS_AN_ACKNOWLEDGE_DETECT;
link_timer_m_start = (acknowledge_match & consistency_match);
end
S_PCS_AN_COMPLETE_ACKNOWLEDGE:
begin
toggle_tx_toggle_m_set = 1; toggle_rx_m_set = 1; np_rx_m_set = 1; mr_page_rx_m_set = 1;
if (ability_match & rx_config_clr) pcs_an_next = S_PCS_AN_ENABLE;
else if (link_timer_done & (~ability_match | rx_config_set))
begin
link_timer_m_start = 1; pcs_an_next = S_PCS_AN_IDLE_DETECT;
end
else link_timer_m_inc = ~link_timer_done;
end
S_PCS_AN_IDLE_DETECT:
begin
xmit_IDLE_m_set = 1; resolve_priority_m_set = 1;
pcs_an_next = (ability_match & rx_config_clr) ? S_PCS_AN_ENABLE :
(idle_match & link_timer_done) ? S_PCS_AN_LINK_OK : S_PCS_AN_IDLE_DETECT;
link_timer_m_inc = ~link_timer_done;
end
S_PCS_AN_LINK_OK:
begin
xmit_DATA_m_set = 1; mr_an_complete_m_set = 1; resolve_priority_m_set = 1;
pcs_an_next = (ability_match | mr_restart_an) ? S_PCS_AN_ENABLE : S_PCS_AN_LINK_OK;
end
endcase
if (~sync_status) pcs_an_next = S_PCS_AN_ENABLE;
else if (mr_main_reset) pcs_an_next = S_PCS_AN_ENABLE;
else if (mr_restart_an) pcs_an_next = S_PCS_AN_ENABLE;
else if (rudi == `RUDI_INVALID) pcs_an_next = S_PCS_AN_ENABLE;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2A_1_V
`define SKY130_FD_SC_HDLL__O2BB2A_1_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o2bb2a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o2bb2a_1 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o2bb2a_1 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2A_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A2BB2O_FUNCTIONAL_PP_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
or or0 (or0_out_X , nor0_out, and0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2O_FUNCTIONAL_PP_V |
`include "Definition.v"
`include "ProcessProperty.v"
// 1. input and output should be combined together into inout
// 2. look up table should be research more elaborate skill
module ColorImageProcess
(
input Clock,
input Reset,
input[ `size_char - 1 : 0 ]R,
input[ `size_char - 1 : 0 ]G,
input[ `size_char - 1 : 0 ]B,
output[ `size_char - 1 : 0 ]R_out,
output[ `size_char - 1 : 0 ]G_out,
output[ `size_char - 1 : 0 ]B_out
);
// scale rgb
reg[ `size_int - 1 : 0 ]ScaleR;
reg[ `size_int - 1 : 0 ]ScaleG;
reg[ `size_int - 1 : 0 ]ScaleB;
reg[ `size_int - 1 : 0 ]ScaleRTemp;
reg[ `size_int - 1 : 0 ]ScaleGTemp;
reg[ `size_int - 1 : 0 ]ScaleBTemp;
// counter
integer PixelCount;
// Auto Level
reg[ `size_int - 1 : 0 ]ALR;
reg[ `size_int - 1 : 0 ]ALG;
reg[ `size_int - 1 : 0 ]ALB;
// CTC
reg[ `size_int - 1 : 0 ]WBR;
reg[ `size_int - 1 : 0 ]WBG;
reg[ `size_int - 1 : 0 ]WBB;
reg[ `size_int - 1 : 0 ]RFactor;
reg[ `size_int - 1 : 0 ]BFactor;
reg[ `size_int + `size_int - 1 : 0 ]RLongTotal;
reg[ `size_int + `size_int - 1 : 0 ]GLongTotal;
reg[ `size_int + `size_int - 1 : 0 ]BLongTotal;
reg[ `size_int - 1 : 0 ]RTotal;
reg[ `size_int - 1 : 0 ]GTotal;
reg[ `size_int - 1 : 0 ]BTotal;
// divider usage
reg[ `size_int - 1 : 0 ]GRIndex;
reg[ `size_int - 1 : 0 ]GBIndex;
// color correction
reg[ `size_int - 1 : 0 ]CCR;
reg[ `size_int - 1 : 0 ]CCG;
reg[ `size_int - 1 : 0 ]CCB;
// color space
reg[ `size_int - 1 : 0 ]CIEL;
// declaration is signed type, a or b maybe negative value
reg signed[ `size_int - 1 : 0 ]CIEa;
reg signed[ `size_int - 1 : 0 ]CIEb;
reg signed[ `size_int - 1 : 0 ]CIEa_input;
reg signed[ `size_int - 1 : 0 ]CIEb_input;
reg[ `size_int - 1 : 0 ]X;
reg[ `size_int - 1 : 0 ]Y;
reg[ `size_int - 1 : 0 ]Z;
reg[ `size_int - 1 : 0 ]fX;
reg[ `size_int - 1 : 0 ]fY;
reg[ `size_int - 1 : 0 ]fZ;
// gamma correction
reg[ `size_int - 1 : 0 ]GCR;
reg[ `size_int - 1 : 0 ]GCG;
reg[ `size_int - 1 : 0 ]GCB;
reg[ 1 : 0 ]State;
reg[ 1 : 0 ]NextState;
// state declaration
parameter InitialState = 0; // initialization
parameter WBFactorState = 1; // calculate white balance factor
parameter ProcessState = 2; // implement all process
parameter FinishState = 3; // image process is complete
// sequential state register
always@( posedge Clock )
begin
if( Reset == 1 )
State = InitialState;
else
State = NextState;
end
////////////////
// read raw data
always@( posedge Clock )
begin
ScaleR = R << `ScaleBit;
ScaleG = G << `ScaleBit;
ScaleB = B << `ScaleBit;
end
/////////////
// auto level
always@( posedge Clock )
begin
if( ( ScaleR > `LowThreshold ) && ( ScaleR < `HighThreshold ) )
ALR = `ALFactor * ( ScaleR - `LowThreshold );
else if( ScaleR <= `LowThreshold )
ALR = `MinThreshold;
else // ScaleR >= `HighThreshold
ALR = `MaxThreshold;
if( ( ScaleG > `LowThreshold ) && ( ScaleG < `HighThreshold ) )
ALG = `ALFactor * ( ScaleG - `LowThreshold );
else if( ScaleG <= `LowThreshold )
ALG = `MinThreshold;
else // ScaleG >= `HighThreshold
ALG = `MaxThreshold;
if( ( ScaleB > `LowThreshold ) && ( ScaleB < `HighThreshold ) )
ALB = `ALFactor * ( ScaleB - `LowThreshold );
else if( ScaleB <= `LowThreshold )
ALB = `MinThreshold;
else // ScaleB >= `HighThreshold
ALB = `MaxThreshold;
end
// next state and outputs, combinational always block
always@( posedge Clock )
begin
case( State )
/////////////////
// initialization
InitialState :
begin
RLongTotal = 0;
GLongTotal = 0;
BLongTotal = 0;
PixelCount = 0;
NextState = WBFactorState;
end
/////////////////////////////////
// calculate white balance factor
WBFactorState :
begin
if( PixelCount == `SumPixel )
begin
NextState = ProcessState;
PixelCount = 0;
end
else
begin
PixelCount = PixelCount + 1;
RLongTotal = RLongTotal + ALR;
GLongTotal = GLongTotal + ALG;
BLongTotal = BLongTotal + ALB;
RTotal = RLongTotal >> `ScaleHalfBit;
GTotal = GLongTotal >> `ScaleHalfBit;
BTotal = BLongTotal >> `ScaleHalfBit;
// GR ratio, scale = 16
GRIndex = Divider( GTotal, RTotal >> `ScaleHalfBit );
// GB ratio, scale = 16
GBIndex = Divider( GTotal, BTotal >> `ScaleHalfBit );
if( ( GRIndex >= 16 ) && ( GRIndex <= 40 ) )
GRIndex = GRIndex - 16;
else if( GRIndex < 16 )
GRIndex = 0;
else
GRIndex = 23;
if( ( GBIndex >= 16 ) && ( GBIndex <= 40 ) )
GBIndex = GBIndex - 16;
else if( GBIndex < 16 )
GBIndex = 0;
else
GBIndex = 23;
LUTCTCFactor( GRIndex * 24 + GBIndex, RFactor, BFactor );
// RFactor = ( RFactor * `WBRCorrection ) >> `ScaleBit;
// BFactor = ( BFactor * `WBBCorrection ) >> `ScaleBit;
end
end
ProcessState :
begin
// delay twice total pixel count
// wait for writing file into file during testbench simulation
if( PixelCount == ( `SumPixel << 2 ) )
begin
NextState = FinishState;
PixelCount = 0;
end
else
begin
PixelCount = PixelCount + 1;
////////////////
// white balance
WBR = ( ALR * RFactor ) >> `ScaleBit;
WBG = ALG;
WBB = ( ALB * BFactor ) >> `ScaleBit;
if( WBR[ 16 ] == 1 )
WBR = `MaxThreshold;
if( WBB[ 16 ] == 1 )
WBB = `MaxThreshold;
///////////////////
// color correction
CCR = ( WBR * `CC1 - WBG * `CC2 - WBB * `CC3 ) >> `ScaleBit;
CCG = ( -WBR * `CC4 + WBG * `CC5 - WBB * `CC6 ) >> `ScaleBit;
CCB = ( WBR * `CC7 - WBG * `CC8 + WBB * `CC9 ) >> `ScaleBit;
CCR = ( CCR[ 17 : 16 ] == 2'b00 ) ? CCR : ( CCR[ 17 ] == 1'b1 ) ? `MinThreshold : `MaxThreshold;
CCG = ( CCG[ 17 : 16 ] == 2'b00 ) ? CCG : ( CCG[ 17 ] == 1'b1 ) ? `MinThreshold : `MaxThreshold;
CCB = ( CCB[ 17 : 16 ] == 2'b00 ) ? CCB : ( CCB[ 17 ] == 1'b1 ) ? `MinThreshold : `MaxThreshold;
////////////////
// forward space
// 256 * 0.950456 * 256
X = ( CCR * `RGB2XYZ1 + CCG * `RGB2XYZ2 + CCB * `RGB2XYZ3 ) >> ( `ScaleBit + `ScaleBit );
X = ( X * 269 ) >> `ScaleBit; // 256 / 0.950456 = 269.34439
Y = ( CCR * `RGB2XYZ4 + CCG * `RGB2XYZ5 + CCB * `RGB2XYZ6 ) >> ( `ScaleBit + `ScaleBit );
// 256 * 1.088754 * 256
Z = ( CCR * `RGB2XYZ7 + CCG * `RGB2XYZ8 + CCB * `RGB2XYZ9 ) >> ( `ScaleBit + `ScaleBit );
Z = ( Z * 235 ) >> `ScaleBit; // 256 / 1.088754 = 235.13116
// avoid extreme case of Y
if( Y < `RGB2LabLimit )
Y = `RGB2LabLimit;
// avoid extreme case of X
if( X < `RGB2LabLimit )
X = `RGB2LabLimit;
// avoid extreme case of Z
if( Z < `RGB2LabLimit )
Z = `RGB2LabLimit;
fX = LUTPow033( X );
fY = LUTPow033( Y );
fZ = LUTPow033( Z );
CIEL = 116 * fY - `pow_16_256_1_3;
CIEa_input = 500 * ( fX - fY );
CIEb_input = 200 * ( fY - fZ );
/////////////////////////
// saturation enhancement
CIEa = ( CIEa_input * `SE_a ) >>> `ScaleBit;
CIEb = ( CIEb_input * `SE_b ) >>> `ScaleBit;
// operator <<<, >>>
// If operand is signed, the right shift fills the vacated bit positions with the MSB.
// If it is unsigned, the vacated bit positions are filled with zeros.
// The left shift fills vacated positions with zeros.
/////////////////
// backward space
// proto type formulation
// fY = ( CIEL + pow_16_256_1_3 ) / 116;
// fX = CIEa / 500 + fY;
// fZ = fY - CIEb / 200;
// fY = ( ( CIEL + pow_16_256_1_3 ) / 116 ) << ( `ScaleBit + `ScaleBit );
// fX = ( ( CIEa / 500 ) << ( `ScaleBit + `ScaleBit ) ) + fY;
// fZ = fY - ( CIEb / 200 ) << ( `ScaleBit + `ScaleBit );
// avoid usage of the division
fY = ( CIEL + `pow_16_256_1_3 ) * 565;
fX = CIEa * 131 + fY;
fZ = fY - CIEb * 328;
// avoid extreme case of fY
if( fY < `Lab2RGBLimit )
fY = `Lab2RGBLimit;
// avoid extreme case of fX
if( fX < `Lab2RGBLimit )
fX = `Lab2RGBLimit;
// avoid extreme case of fZ
if( fZ < `Lab2RGBLimit )
fZ = `Lab2RGBLimit;
// in case of over-range of power 3 operation later
// fY = fY >> `ScaleHalfBit;
fY = fY >> ( `ScaleHalfBit + `ScaleBit + `ScaleBit );
Y = fY * fY * fY;
Y = ( Y * 256 ) >> `ScaleBit;
// in case of over-range of power 3 operation later
// fX = fX >> `ScaleHalfBit;
fX = fX >> ( `ScaleHalfBit + `ScaleBit + `ScaleBit );
X = fX * fX * fX;
X = ( X * 243 ) >> `ScaleBit; // 256 * 0.950456 = 243.316736
// in case of over-range of power 3 operation later
// fZ = fZ >> `ScaleHalfBit;
fZ = fZ >> ( `ScaleHalfBit + `ScaleBit + `ScaleBit );
Z = fZ * fZ * fZ;
Z = ( Z * 279 ) >> `ScaleBit; // 256 * 1.088754 = 278.721024
ScaleRTemp = ( `XYZ2RGB1 * X - `XYZ2RGB2 * Y - `XYZ2RGB3 * Z )
>> ( `ScaleBit + `ScaleHalfBit );
ScaleGTemp = ( -`XYZ2RGB4 * X + `XYZ2RGB5 * Y + `XYZ2RGB6 * Z )
>> ( `ScaleBit + `ScaleHalfBit );
ScaleBTemp = ( `XYZ2RGB7 * X - `XYZ2RGB8 * Y + `XYZ2RGB9 * Z )
>> ( `ScaleBit + `ScaleHalfBit );
ScaleRTemp = ( ScaleRTemp[ 17 : 16 ] == 2'b00 ) ? ScaleRTemp : ( ScaleRTemp[ 17 ] == 1'b1 ) ? `MinThreshold : `MaxThreshold;
ScaleGTemp = ( ScaleGTemp[ 17 : 16 ] == 2'b00 ) ? ScaleGTemp : ( ScaleGTemp[ 17 ] == 1'b1 ) ? `MinThreshold : `MaxThreshold;
ScaleBTemp = ( ScaleBTemp[ 17 : 16 ] == 2'b00 ) ? ScaleBTemp : ( ScaleBTemp[ 17 ] == 1'b1 ) ? `MinThreshold : `MaxThreshold;
///////////////////
// gamma correction
GCR = LUTPow045( ScaleRTemp >> `ScaleBit );
GCG = LUTPow045( ScaleGTemp >> `ScaleBit );
GCB = LUTPow045( ScaleBTemp >> `ScaleBit );
end
end
// finish the work
FinishState :
begin
// nothing to do, usage in the future
end
endcase
end
assign R_out = GCR >> `ScaleBit;
assign G_out = GCG >> `ScaleBit;
assign B_out = GCB >> `ScaleBit;
//////////////////////////////////////////////////////////////////
function[ `size_int - 1 : 0 ]Divider
(
input[ `size_int - 1 : 0 ]Dividend,
input[ `size_int - 1 : 0 ]Divisor
);
// counter
integer i;
reg[ `size_int - 1 : 0 ]Quotient; // Quotient
reg[ `size_int - 1 : 0 ]Remainder; // Remainder
reg[ `size_int : 0 ]Partial;
reg[ `size_int - 1 : 0 ]div;
begin
Quotient = Dividend;
div = Divisor;
Partial = { `size_int'h00, 1'b0 };
for( i = 0; i < `size_int; i = i + 1 )
begin
Partial = { Partial[ `size_int - 1 : 0 ], Quotient[ `size_int - 1 ] };
Quotient = { Quotient[ `size_int - 2 : 0 ], 1'b0 };
Partial = Partial + { ~{ 1'b0, div } + 1'b1 }; // subtraction
if( Partial[ `size_int ] == 1'b0 )
Quotient[ 0 ] = 1'b1;
else
begin
Partial = Partial + div;
Quotient[ 0 ] = 1'b0;
end
end
Remainder = Partial[ `size_int - 1 : 0 ];
//to round up or down
if( Remainder * 10 >= Divisor * 5 )
Divider = Quotient + 1;
else
Divider = Quotient;
end
endfunction
// ratio = 1.0 ~ 2.5
// scale = 16
// ratio * 16 = 16 ~ 40
// every layer size = 40 - 16 = 24
// every step : ( 2.5 - 1.0 ) / 24 = 0.0625
// it needed to be modified
task LUTCTCFactor
(
input[ `size_int - 1 : 0 ]Index,
output[ `size_int - 1 : 0 ]RFactor,
output[ `size_int - 1 : 0 ]BFactor
);
begin
case( Index )
0 : begin RFactor = 417; BFactor = 414; end // GR = 1.00, GB = 1.00
1 : begin RFactor = 405; BFactor = 427; end // GR = 1.00, GB = 1.06
2 : begin RFactor = 394; BFactor = 440; end // GR = 1.00, GB = 1.12
3 : begin RFactor = 383; BFactor = 452; end // GR = 1.00, GB = 1.19
4 : begin RFactor = 373; BFactor = 464; end // GR = 1.00, GB = 1.25
5 : begin RFactor = 364; BFactor = 476; end // GR = 1.00, GB = 1.31
6 : begin RFactor = 356; BFactor = 487; end // GR = 1.00, GB = 1.38
7 : begin RFactor = 348; BFactor = 498; end // GR = 1.00, GB = 1.44
8 : begin RFactor = 341; BFactor = 509; end // GR = 1.00, GB = 1.50
9 : begin RFactor = 334; BFactor = 520; end // GR = 1.00, GB = 1.56
10 : begin RFactor = 327; BFactor = 530; end // GR = 1.00, GB = 1.62
11 : begin RFactor = 321; BFactor = 540; end // GR = 1.00, GB = 1.69
12 : begin RFactor = 315; BFactor = 551; end // GR = 1.00, GB = 1.75
13 : begin RFactor = 310; BFactor = 560; end // GR = 1.00, GB = 1.81
14 : begin RFactor = 305; BFactor = 570; end // GR = 1.00, GB = 1.88
15 : begin RFactor = 300; BFactor = 580; end // GR = 1.00, GB = 1.94
16 : begin RFactor = 295; BFactor = 589; end // GR = 1.00, GB = 2.00
17 : begin RFactor = 291; BFactor = 599; end // GR = 1.00, GB = 2.06
18 : begin RFactor = 286; BFactor = 608; end // GR = 1.00, GB = 2.12
19 : begin RFactor = 282; BFactor = 617; end // GR = 1.00, GB = 2.19
20 : begin RFactor = 278; BFactor = 626; end // GR = 1.00, GB = 2.25
21 : begin RFactor = 274; BFactor = 634; end // GR = 1.00, GB = 2.31
22 : begin RFactor = 271; BFactor = 643; end // GR = 1.00, GB = 2.38
23 : begin RFactor = 267; BFactor = 652; end // GR = 1.00, GB = 2.44
24 : begin RFactor = 430; BFactor = 402; end // GR = 1.06, GB = 1.00
25 : begin RFactor = 417; BFactor = 414; end // GR = 1.06, GB = 1.06
26 : begin RFactor = 405; BFactor = 427; end // GR = 1.06, GB = 1.12
27 : begin RFactor = 395; BFactor = 438; end // GR = 1.06, GB = 1.19
28 : begin RFactor = 385; BFactor = 450; end // GR = 1.06, GB = 1.25
29 : begin RFactor = 375; BFactor = 461; end // GR = 1.06, GB = 1.31
30 : begin RFactor = 367; BFactor = 472; end // GR = 1.06, GB = 1.38
31 : begin RFactor = 359; BFactor = 483; end // GR = 1.06, GB = 1.44
32 : begin RFactor = 351; BFactor = 494; end // GR = 1.06, GB = 1.50
33 : begin RFactor = 344; BFactor = 504; end // GR = 1.06, GB = 1.56
34 : begin RFactor = 337; BFactor = 514; end // GR = 1.06, GB = 1.62
35 : begin RFactor = 331; BFactor = 524; end // GR = 1.06, GB = 1.69
36 : begin RFactor = 325; BFactor = 534; end // GR = 1.06, GB = 1.75
37 : begin RFactor = 319; BFactor = 544; end // GR = 1.06, GB = 1.81
38 : begin RFactor = 314; BFactor = 553; end // GR = 1.06, GB = 1.88
39 : begin RFactor = 309; BFactor = 562; end // GR = 1.06, GB = 1.94
40 : begin RFactor = 304; BFactor = 572; end // GR = 1.06, GB = 2.00
41 : begin RFactor = 299; BFactor = 581; end // GR = 1.06, GB = 2.06
42 : begin RFactor = 295; BFactor = 590; end // GR = 1.06, GB = 2.12
43 : begin RFactor = 291; BFactor = 598; end // GR = 1.06, GB = 2.19
44 : begin RFactor = 287; BFactor = 607; end // GR = 1.06, GB = 2.25
45 : begin RFactor = 283; BFactor = 615; end // GR = 1.06, GB = 2.31
46 : begin RFactor = 279; BFactor = 624; end // GR = 1.06, GB = 2.38
47 : begin RFactor = 275; BFactor = 632; end // GR = 1.06, GB = 2.44
48 : begin RFactor = 442; BFactor = 390; end // GR = 1.12, GB = 1.00
49 : begin RFactor = 429; BFactor = 403; end // GR = 1.12, GB = 1.06
50 : begin RFactor = 417; BFactor = 415; end // GR = 1.12, GB = 1.12
51 : begin RFactor = 406; BFactor = 426; end // GR = 1.12, GB = 1.19
52 : begin RFactor = 396; BFactor = 437; end // GR = 1.12, GB = 1.25
53 : begin RFactor = 386; BFactor = 448; end // GR = 1.12, GB = 1.31
54 : begin RFactor = 377; BFactor = 459; end // GR = 1.12, GB = 1.38
55 : begin RFactor = 369; BFactor = 470; end // GR = 1.12, GB = 1.44
56 : begin RFactor = 361; BFactor = 480; end // GR = 1.12, GB = 1.50
57 : begin RFactor = 354; BFactor = 490; end // GR = 1.12, GB = 1.56
58 : begin RFactor = 347; BFactor = 500; end // GR = 1.12, GB = 1.62
59 : begin RFactor = 340; BFactor = 510; end // GR = 1.12, GB = 1.69
60 : begin RFactor = 334; BFactor = 519; end // GR = 1.12, GB = 1.75
61 : begin RFactor = 328; BFactor = 528; end // GR = 1.12, GB = 1.81
62 : begin RFactor = 323; BFactor = 538; end // GR = 1.12, GB = 1.88
63 : begin RFactor = 318; BFactor = 547; end // GR = 1.12, GB = 1.94
64 : begin RFactor = 313; BFactor = 555; end // GR = 1.12, GB = 2.00
65 : begin RFactor = 308; BFactor = 564; end // GR = 1.12, GB = 2.06
66 : begin RFactor = 303; BFactor = 573; end // GR = 1.12, GB = 2.12
67 : begin RFactor = 299; BFactor = 581; end // GR = 1.12, GB = 2.19
68 : begin RFactor = 295; BFactor = 590; end // GR = 1.12, GB = 2.25
69 : begin RFactor = 291; BFactor = 598; end // GR = 1.12, GB = 2.31
70 : begin RFactor = 287; BFactor = 606; end // GR = 1.12, GB = 2.38
71 : begin RFactor = 283; BFactor = 614; end // GR = 1.12, GB = 2.44
72 : begin RFactor = 454; BFactor = 380; end // GR = 1.19, GB = 1.00
73 : begin RFactor = 441; BFactor = 392; end // GR = 1.19, GB = 1.06
74 : begin RFactor = 428; BFactor = 403; end // GR = 1.19, GB = 1.12
75 : begin RFactor = 417; BFactor = 415; end // GR = 1.19, GB = 1.19
76 : begin RFactor = 406; BFactor = 426; end // GR = 1.19, GB = 1.25
77 : begin RFactor = 396; BFactor = 436; end // GR = 1.19, GB = 1.31
78 : begin RFactor = 387; BFactor = 447; end // GR = 1.19, GB = 1.38
79 : begin RFactor = 379; BFactor = 457; end // GR = 1.19, GB = 1.44
80 : begin RFactor = 371; BFactor = 467; end // GR = 1.19, GB = 1.50
81 : begin RFactor = 363; BFactor = 477; end // GR = 1.19, GB = 1.56
82 : begin RFactor = 356; BFactor = 486; end // GR = 1.19, GB = 1.62
83 : begin RFactor = 350; BFactor = 496; end // GR = 1.19, GB = 1.69
84 : begin RFactor = 343; BFactor = 505; end // GR = 1.19, GB = 1.75
85 : begin RFactor = 337; BFactor = 514; end // GR = 1.19, GB = 1.81
86 : begin RFactor = 332; BFactor = 523; end // GR = 1.19, GB = 1.88
87 : begin RFactor = 326; BFactor = 532; end // GR = 1.19, GB = 1.94
88 : begin RFactor = 321; BFactor = 541; end // GR = 1.19, GB = 2.00
89 : begin RFactor = 316; BFactor = 549; end // GR = 1.19, GB = 2.06
90 : begin RFactor = 312; BFactor = 558; end // GR = 1.19, GB = 2.12
91 : begin RFactor = 307; BFactor = 566; end // GR = 1.19, GB = 2.19
92 : begin RFactor = 303; BFactor = 574; end // GR = 1.19, GB = 2.25
93 : begin RFactor = 299; BFactor = 582; end // GR = 1.19, GB = 2.31
94 : begin RFactor = 295; BFactor = 590; end // GR = 1.19, GB = 2.38
95 : begin RFactor = 291; BFactor = 598; end // GR = 1.19, GB = 2.44
96 : begin RFactor = 466; BFactor = 370; end // GR = 1.25, GB = 1.00
97 : begin RFactor = 452; BFactor = 382; end // GR = 1.25, GB = 1.06
98 : begin RFactor = 439; BFactor = 393; end // GR = 1.25, GB = 1.12
99 : begin RFactor = 428; BFactor = 404; end // GR = 1.25, GB = 1.19
100 : begin RFactor = 417; BFactor = 415; end // GR = 1.25, GB = 1.25
101 : begin RFactor = 407; BFactor = 425; end // GR = 1.25, GB = 1.31
102 : begin RFactor = 397; BFactor = 436; end // GR = 1.25, GB = 1.38
103 : begin RFactor = 389; BFactor = 445; end // GR = 1.25, GB = 1.44
104 : begin RFactor = 380; BFactor = 455; end // GR = 1.25, GB = 1.50
105 : begin RFactor = 373; BFactor = 465; end // GR = 1.25, GB = 1.56
106 : begin RFactor = 365; BFactor = 474; end // GR = 1.25, GB = 1.62
107 : begin RFactor = 359; BFactor = 483; end // GR = 1.25, GB = 1.69
108 : begin RFactor = 352; BFactor = 492; end // GR = 1.25, GB = 1.75
109 : begin RFactor = 346; BFactor = 501; end // GR = 1.25, GB = 1.81
110 : begin RFactor = 340; BFactor = 510; end // GR = 1.25, GB = 1.88
111 : begin RFactor = 335; BFactor = 519; end // GR = 1.25, GB = 1.94
112 : begin RFactor = 329; BFactor = 527; end // GR = 1.25, GB = 2.00
113 : begin RFactor = 324; BFactor = 535; end // GR = 1.25, GB = 2.06
114 : begin RFactor = 319; BFactor = 543; end // GR = 1.25, GB = 2.12
115 : begin RFactor = 315; BFactor = 552; end // GR = 1.25, GB = 2.19
116 : begin RFactor = 310; BFactor = 559; end // GR = 1.25, GB = 2.25
117 : begin RFactor = 306; BFactor = 567; end // GR = 1.25, GB = 2.31
118 : begin RFactor = 302; BFactor = 575; end // GR = 1.25, GB = 2.38
119 : begin RFactor = 298; BFactor = 583; end // GR = 1.25, GB = 2.44
120 : begin RFactor = 477; BFactor = 361; end // GR = 1.31, GB = 1.00
121 : begin RFactor = 463; BFactor = 373; end // GR = 1.31, GB = 1.06
122 : begin RFactor = 450; BFactor = 384; end // GR = 1.31, GB = 1.12
123 : begin RFactor = 438; BFactor = 394; end // GR = 1.31, GB = 1.19
124 : begin RFactor = 427; BFactor = 405; end // GR = 1.31, GB = 1.25
125 : begin RFactor = 417; BFactor = 415; end // GR = 1.31, GB = 1.31
126 : begin RFactor = 407; BFactor = 425; end // GR = 1.31, GB = 1.38
127 : begin RFactor = 398; BFactor = 435; end // GR = 1.31, GB = 1.44
128 : begin RFactor = 390; BFactor = 444; end // GR = 1.31, GB = 1.50
129 : begin RFactor = 382; BFactor = 454; end // GR = 1.31, GB = 1.56
130 : begin RFactor = 374; BFactor = 463; end // GR = 1.31, GB = 1.62
131 : begin RFactor = 367; BFactor = 472; end // GR = 1.31, GB = 1.69
132 : begin RFactor = 361; BFactor = 480; end // GR = 1.31, GB = 1.75
133 : begin RFactor = 354; BFactor = 489; end // GR = 1.31, GB = 1.81
134 : begin RFactor = 348; BFactor = 498; end // GR = 1.31, GB = 1.88
135 : begin RFactor = 343; BFactor = 506; end // GR = 1.31, GB = 1.94
136 : begin RFactor = 337; BFactor = 514; end // GR = 1.31, GB = 2.00
137 : begin RFactor = 332; BFactor = 522; end // GR = 1.31, GB = 2.06
138 : begin RFactor = 327; BFactor = 530; end // GR = 1.31, GB = 2.12
139 : begin RFactor = 323; BFactor = 538; end // GR = 1.31, GB = 2.19
140 : begin RFactor = 318; BFactor = 546; end // GR = 1.31, GB = 2.25
141 : begin RFactor = 314; BFactor = 554; end // GR = 1.31, GB = 2.31
142 : begin RFactor = 310; BFactor = 561; end // GR = 1.31, GB = 2.38
143 : begin RFactor = 306; BFactor = 569; end // GR = 1.31, GB = 2.44
144 : begin RFactor = 488; BFactor = 353; end // GR = 1.38, GB = 1.00
145 : begin RFactor = 474; BFactor = 364; end // GR = 1.38, GB = 1.06
146 : begin RFactor = 460; BFactor = 375; end // GR = 1.38, GB = 1.12
147 : begin RFactor = 448; BFactor = 385; end // GR = 1.38, GB = 1.19
148 : begin RFactor = 437; BFactor = 396; end // GR = 1.38, GB = 1.25
149 : begin RFactor = 426; BFactor = 406; end // GR = 1.38, GB = 1.31
150 : begin RFactor = 416; BFactor = 415; end // GR = 1.38, GB = 1.38
151 : begin RFactor = 407; BFactor = 425; end // GR = 1.38, GB = 1.44
152 : begin RFactor = 399; BFactor = 434; end // GR = 1.38, GB = 1.50
153 : begin RFactor = 391; BFactor = 443; end // GR = 1.38, GB = 1.56
154 : begin RFactor = 383; BFactor = 452; end // GR = 1.38, GB = 1.62
155 : begin RFactor = 376; BFactor = 461; end // GR = 1.38, GB = 1.69
156 : begin RFactor = 369; BFactor = 469; end // GR = 1.38, GB = 1.75
157 : begin RFactor = 363; BFactor = 478; end // GR = 1.38, GB = 1.81
158 : begin RFactor = 356; BFactor = 486; end // GR = 1.38, GB = 1.88
159 : begin RFactor = 351; BFactor = 494; end // GR = 1.38, GB = 1.94
160 : begin RFactor = 345; BFactor = 502; end // GR = 1.38, GB = 2.00
161 : begin RFactor = 340; BFactor = 510; end // GR = 1.38, GB = 2.06
162 : begin RFactor = 335; BFactor = 518; end // GR = 1.38, GB = 2.12
163 : begin RFactor = 330; BFactor = 526; end // GR = 1.38, GB = 2.19
164 : begin RFactor = 325; BFactor = 533; end // GR = 1.38, GB = 2.25
165 : begin RFactor = 321; BFactor = 541; end // GR = 1.38, GB = 2.31
166 : begin RFactor = 317; BFactor = 548; end // GR = 1.38, GB = 2.38
167 : begin RFactor = 313; BFactor = 556; end // GR = 1.38, GB = 2.44
168 : begin RFactor = 499; BFactor = 345; end // GR = 1.44, GB = 1.00
169 : begin RFactor = 484; BFactor = 356; end // GR = 1.44, GB = 1.06
170 : begin RFactor = 471; BFactor = 367; end // GR = 1.44, GB = 1.12
171 : begin RFactor = 458; BFactor = 377; end // GR = 1.44, GB = 1.19
172 : begin RFactor = 446; BFactor = 387; end // GR = 1.44, GB = 1.25
173 : begin RFactor = 436; BFactor = 397; end // GR = 1.44, GB = 1.31
174 : begin RFactor = 426; BFactor = 406; end // GR = 1.44, GB = 1.38
175 : begin RFactor = 416; BFactor = 415; end // GR = 1.44, GB = 1.44
176 : begin RFactor = 407; BFactor = 424; end // GR = 1.44, GB = 1.50
177 : begin RFactor = 399; BFactor = 433; end // GR = 1.44, GB = 1.56
178 : begin RFactor = 391; BFactor = 442; end // GR = 1.44, GB = 1.62
179 : begin RFactor = 384; BFactor = 451; end // GR = 1.44, GB = 1.69
180 : begin RFactor = 377; BFactor = 459; end // GR = 1.44, GB = 1.75
181 : begin RFactor = 371; BFactor = 467; end // GR = 1.44, GB = 1.81
182 : begin RFactor = 364; BFactor = 476; end // GR = 1.44, GB = 1.88
183 : begin RFactor = 358; BFactor = 484; end // GR = 1.44, GB = 1.94
184 : begin RFactor = 353; BFactor = 491; end // GR = 1.44, GB = 2.00
185 : begin RFactor = 347; BFactor = 499; end // GR = 1.44, GB = 2.06
186 : begin RFactor = 342; BFactor = 507; end // GR = 1.44, GB = 2.12
187 : begin RFactor = 337; BFactor = 514; end // GR = 1.44, GB = 2.19
188 : begin RFactor = 333; BFactor = 522; end // GR = 1.44, GB = 2.25
189 : begin RFactor = 328; BFactor = 529; end // GR = 1.44, GB = 2.31
190 : begin RFactor = 324; BFactor = 536; end // GR = 1.44, GB = 2.38
191 : begin RFactor = 320; BFactor = 543; end // GR = 1.44, GB = 2.44
192 : begin RFactor = 510; BFactor = 338; end // GR = 1.50, GB = 1.00
193 : begin RFactor = 494; BFactor = 349; end // GR = 1.50, GB = 1.06
194 : begin RFactor = 481; BFactor = 359; end // GR = 1.50, GB = 1.12
195 : begin RFactor = 468; BFactor = 369; end // GR = 1.50, GB = 1.19
196 : begin RFactor = 456; BFactor = 379; end // GR = 1.50, GB = 1.25
197 : begin RFactor = 445; BFactor = 388; end // GR = 1.50, GB = 1.31
198 : begin RFactor = 435; BFactor = 398; end // GR = 1.50, GB = 1.38
199 : begin RFactor = 425; BFactor = 407; end // GR = 1.50, GB = 1.44
200 : begin RFactor = 416; BFactor = 416; end // GR = 1.50, GB = 1.50
201 : begin RFactor = 408; BFactor = 424; end // GR = 1.50, GB = 1.56
202 : begin RFactor = 400; BFactor = 433; end // GR = 1.50, GB = 1.62
203 : begin RFactor = 392; BFactor = 441; end // GR = 1.50, GB = 1.69
204 : begin RFactor = 385; BFactor = 449; end // GR = 1.50, GB = 1.75
205 : begin RFactor = 378; BFactor = 458; end // GR = 1.50, GB = 1.81
206 : begin RFactor = 372; BFactor = 465; end // GR = 1.50, GB = 1.88
207 : begin RFactor = 366; BFactor = 473; end // GR = 1.50, GB = 1.94
208 : begin RFactor = 360; BFactor = 481; end // GR = 1.50, GB = 2.00
209 : begin RFactor = 355; BFactor = 489; end // GR = 1.50, GB = 2.06
210 : begin RFactor = 350; BFactor = 496; end // GR = 1.50, GB = 2.12
211 : begin RFactor = 344; BFactor = 503; end // GR = 1.50, GB = 2.19
212 : begin RFactor = 340; BFactor = 511; end // GR = 1.50, GB = 2.25
213 : begin RFactor = 335; BFactor = 518; end // GR = 1.50, GB = 2.31
214 : begin RFactor = 331; BFactor = 525; end // GR = 1.50, GB = 2.38
215 : begin RFactor = 326; BFactor = 532; end // GR = 1.50, GB = 2.44
216 : begin RFactor = 520; BFactor = 331; end // GR = 1.56, GB = 1.00
217 : begin RFactor = 505; BFactor = 342; end // GR = 1.56, GB = 1.06
218 : begin RFactor = 490; BFactor = 352; end // GR = 1.56, GB = 1.12
219 : begin RFactor = 477; BFactor = 362; end // GR = 1.56, GB = 1.19
220 : begin RFactor = 465; BFactor = 371; end // GR = 1.56, GB = 1.25
221 : begin RFactor = 454; BFactor = 380; end // GR = 1.56, GB = 1.31
222 : begin RFactor = 443; BFactor = 390; end // GR = 1.56, GB = 1.38
223 : begin RFactor = 434; BFactor = 398; end // GR = 1.56, GB = 1.44
224 : begin RFactor = 425; BFactor = 407; end // GR = 1.56, GB = 1.50
225 : begin RFactor = 416; BFactor = 416; end // GR = 1.56, GB = 1.56
226 : begin RFactor = 408; BFactor = 424; end // GR = 1.56, GB = 1.62
227 : begin RFactor = 400; BFactor = 432; end // GR = 1.56, GB = 1.69
228 : begin RFactor = 393; BFactor = 440; end // GR = 1.56, GB = 1.75
229 : begin RFactor = 386; BFactor = 448; end // GR = 1.56, GB = 1.81
230 : begin RFactor = 380; BFactor = 456; end // GR = 1.56, GB = 1.88
231 : begin RFactor = 373; BFactor = 464; end // GR = 1.56, GB = 1.94
232 : begin RFactor = 368; BFactor = 471; end // GR = 1.56, GB = 2.00
233 : begin RFactor = 362; BFactor = 479; end // GR = 1.56, GB = 2.06
234 : begin RFactor = 357; BFactor = 486; end // GR = 1.56, GB = 2.12
235 : begin RFactor = 351; BFactor = 493; end // GR = 1.56, GB = 2.19
236 : begin RFactor = 347; BFactor = 500; end // GR = 1.56, GB = 2.25
237 : begin RFactor = 342; BFactor = 507; end // GR = 1.56, GB = 2.31
238 : begin RFactor = 337; BFactor = 514; end // GR = 1.56, GB = 2.38
239 : begin RFactor = 333; BFactor = 521; end // GR = 1.56, GB = 2.44
240 : begin RFactor = 530; BFactor = 325; end // GR = 1.62, GB = 1.00
241 : begin RFactor = 514; BFactor = 335; end // GR = 1.62, GB = 1.06
242 : begin RFactor = 500; BFactor = 345; end // GR = 1.62, GB = 1.12
243 : begin RFactor = 486; BFactor = 354; end // GR = 1.62, GB = 1.19
244 : begin RFactor = 474; BFactor = 364; end // GR = 1.62, GB = 1.25
245 : begin RFactor = 463; BFactor = 373; end // GR = 1.62, GB = 1.31
246 : begin RFactor = 452; BFactor = 382; end // GR = 1.62, GB = 1.38
247 : begin RFactor = 442; BFactor = 391; end // GR = 1.62, GB = 1.44
248 : begin RFactor = 433; BFactor = 399; end // GR = 1.62, GB = 1.50
249 : begin RFactor = 424; BFactor = 408; end // GR = 1.62, GB = 1.56
250 : begin RFactor = 416; BFactor = 416; end // GR = 1.62, GB = 1.62
251 : begin RFactor = 408; BFactor = 424; end // GR = 1.62, GB = 1.69
252 : begin RFactor = 401; BFactor = 432; end // GR = 1.62, GB = 1.75
253 : begin RFactor = 394; BFactor = 440; end // GR = 1.62, GB = 1.81
254 : begin RFactor = 387; BFactor = 447; end // GR = 1.62, GB = 1.88
255 : begin RFactor = 381; BFactor = 455; end // GR = 1.62, GB = 1.94
256 : begin RFactor = 375; BFactor = 462; end // GR = 1.62, GB = 2.00
257 : begin RFactor = 369; BFactor = 469; end // GR = 1.62, GB = 2.06
258 : begin RFactor = 364; BFactor = 477; end // GR = 1.62, GB = 2.12
259 : begin RFactor = 358; BFactor = 484; end // GR = 1.62, GB = 2.19
260 : begin RFactor = 353; BFactor = 491; end // GR = 1.62, GB = 2.25
261 : begin RFactor = 348; BFactor = 498; end // GR = 1.62, GB = 2.31
262 : begin RFactor = 344; BFactor = 504; end // GR = 1.62, GB = 2.38
263 : begin RFactor = 339; BFactor = 511; end // GR = 1.62, GB = 2.44
264 : begin RFactor = 540; BFactor = 319; end // GR = 1.69, GB = 1.00
265 : begin RFactor = 524; BFactor = 329; end // GR = 1.69, GB = 1.06
266 : begin RFactor = 509; BFactor = 338; end // GR = 1.69, GB = 1.12
267 : begin RFactor = 496; BFactor = 348; end // GR = 1.69, GB = 1.19
268 : begin RFactor = 483; BFactor = 357; end // GR = 1.69, GB = 1.25
269 : begin RFactor = 471; BFactor = 366; end // GR = 1.69, GB = 1.31
270 : begin RFactor = 461; BFactor = 375; end // GR = 1.69, GB = 1.38
271 : begin RFactor = 450; BFactor = 383; end // GR = 1.69, GB = 1.44
272 : begin RFactor = 441; BFactor = 392; end // GR = 1.69, GB = 1.50
273 : begin RFactor = 432; BFactor = 400; end // GR = 1.69, GB = 1.56
274 : begin RFactor = 424; BFactor = 408; end // GR = 1.69, GB = 1.62
275 : begin RFactor = 416; BFactor = 416; end // GR = 1.69, GB = 1.69
276 : begin RFactor = 408; BFactor = 424; end // GR = 1.69, GB = 1.75
277 : begin RFactor = 401; BFactor = 431; end // GR = 1.69, GB = 1.81
278 : begin RFactor = 394; BFactor = 439; end // GR = 1.69, GB = 1.88
279 : begin RFactor = 388; BFactor = 446; end // GR = 1.69, GB = 1.94
280 : begin RFactor = 382; BFactor = 453; end // GR = 1.69, GB = 2.00
281 : begin RFactor = 376; BFactor = 461; end // GR = 1.69, GB = 2.06
282 : begin RFactor = 370; BFactor = 468; end // GR = 1.69, GB = 2.12
283 : begin RFactor = 365; BFactor = 475; end // GR = 1.69, GB = 2.19
284 : begin RFactor = 360; BFactor = 481; end // GR = 1.69, GB = 2.25
285 : begin RFactor = 355; BFactor = 488; end // GR = 1.69, GB = 2.31
286 : begin RFactor = 350; BFactor = 495; end // GR = 1.69, GB = 2.38
287 : begin RFactor = 346; BFactor = 501; end // GR = 1.69, GB = 2.44
288 : begin RFactor = 550; BFactor = 313; end // GR = 1.75, GB = 1.00
289 : begin RFactor = 533; BFactor = 323; end // GR = 1.75, GB = 1.06
290 : begin RFactor = 518; BFactor = 332; end // GR = 1.75, GB = 1.12
291 : begin RFactor = 505; BFactor = 342; end // GR = 1.75, GB = 1.19
292 : begin RFactor = 492; BFactor = 351; end // GR = 1.75, GB = 1.25
293 : begin RFactor = 480; BFactor = 359; end // GR = 1.75, GB = 1.31
294 : begin RFactor = 469; BFactor = 368; end // GR = 1.75, GB = 1.38
295 : begin RFactor = 459; BFactor = 376; end // GR = 1.75, GB = 1.44
296 : begin RFactor = 449; BFactor = 385; end // GR = 1.75, GB = 1.50
297 : begin RFactor = 440; BFactor = 393; end // GR = 1.75, GB = 1.56
298 : begin RFactor = 431; BFactor = 401; end // GR = 1.75, GB = 1.62
299 : begin RFactor = 423; BFactor = 408; end // GR = 1.75, GB = 1.69
300 : begin RFactor = 416; BFactor = 416; end // GR = 1.75, GB = 1.75
301 : begin RFactor = 408; BFactor = 424; end // GR = 1.75, GB = 1.81
302 : begin RFactor = 401; BFactor = 431; end // GR = 1.75, GB = 1.88
303 : begin RFactor = 395; BFactor = 438; end // GR = 1.75, GB = 1.94
304 : begin RFactor = 389; BFactor = 445; end // GR = 1.75, GB = 2.00
305 : begin RFactor = 383; BFactor = 452; end // GR = 1.75, GB = 2.06
306 : begin RFactor = 377; BFactor = 459; end // GR = 1.75, GB = 2.12
307 : begin RFactor = 372; BFactor = 466; end // GR = 1.75, GB = 2.19
308 : begin RFactor = 366; BFactor = 473; end // GR = 1.75, GB = 2.25
309 : begin RFactor = 361; BFactor = 479; end // GR = 1.75, GB = 2.31
310 : begin RFactor = 357; BFactor = 486; end // GR = 1.75, GB = 2.38
311 : begin RFactor = 352; BFactor = 492; end // GR = 1.75, GB = 2.44
312 : begin RFactor = 559; BFactor = 308; end // GR = 1.81, GB = 1.00
313 : begin RFactor = 543; BFactor = 317; end // GR = 1.81, GB = 1.06
314 : begin RFactor = 527; BFactor = 327; end // GR = 1.81, GB = 1.12
315 : begin RFactor = 513; BFactor = 336; end // GR = 1.81, GB = 1.19
316 : begin RFactor = 500; BFactor = 344; end // GR = 1.81, GB = 1.25
317 : begin RFactor = 488; BFactor = 353; end // GR = 1.81, GB = 1.31
318 : begin RFactor = 477; BFactor = 362; end // GR = 1.81, GB = 1.38
319 : begin RFactor = 467; BFactor = 370; end // GR = 1.81, GB = 1.44
320 : begin RFactor = 457; BFactor = 378; end // GR = 1.81, GB = 1.50
321 : begin RFactor = 447; BFactor = 386; end // GR = 1.81, GB = 1.56
322 : begin RFactor = 439; BFactor = 394; end // GR = 1.81, GB = 1.62
323 : begin RFactor = 431; BFactor = 401; end // GR = 1.81, GB = 1.69
324 : begin RFactor = 423; BFactor = 409; end // GR = 1.81, GB = 1.75
325 : begin RFactor = 415; BFactor = 416; end // GR = 1.81, GB = 1.81
326 : begin RFactor = 408; BFactor = 423; end // GR = 1.81, GB = 1.88
327 : begin RFactor = 402; BFactor = 431; end // GR = 1.81, GB = 1.94
328 : begin RFactor = 395; BFactor = 438; end // GR = 1.81, GB = 2.00
329 : begin RFactor = 389; BFactor = 444; end // GR = 1.81, GB = 2.06
330 : begin RFactor = 384; BFactor = 451; end // GR = 1.81, GB = 2.12
331 : begin RFactor = 378; BFactor = 458; end // GR = 1.81, GB = 2.19
332 : begin RFactor = 373; BFactor = 465; end // GR = 1.81, GB = 2.25
333 : begin RFactor = 368; BFactor = 471; end // GR = 1.81, GB = 2.31
334 : begin RFactor = 363; BFactor = 478; end // GR = 1.81, GB = 2.38
335 : begin RFactor = 358; BFactor = 484; end // GR = 1.81, GB = 2.44
336 : begin RFactor = 569; BFactor = 302; end // GR = 1.88, GB = 1.00
337 : begin RFactor = 552; BFactor = 312; end // GR = 1.88, GB = 1.06
338 : begin RFactor = 536; BFactor = 321; end // GR = 1.88, GB = 1.12
339 : begin RFactor = 522; BFactor = 330; end // GR = 1.88, GB = 1.19
340 : begin RFactor = 509; BFactor = 339; end // GR = 1.88, GB = 1.25
341 : begin RFactor = 497; BFactor = 347; end // GR = 1.88, GB = 1.31
342 : begin RFactor = 485; BFactor = 356; end // GR = 1.88, GB = 1.38
343 : begin RFactor = 474; BFactor = 364; end // GR = 1.88, GB = 1.44
344 : begin RFactor = 464; BFactor = 372; end // GR = 1.88, GB = 1.50
345 : begin RFactor = 455; BFactor = 379; end // GR = 1.88, GB = 1.56
346 : begin RFactor = 446; BFactor = 387; end // GR = 1.88, GB = 1.62
347 : begin RFactor = 438; BFactor = 395; end // GR = 1.88, GB = 1.69
348 : begin RFactor = 430; BFactor = 402; end // GR = 1.88, GB = 1.75
349 : begin RFactor = 422; BFactor = 409; end // GR = 1.88, GB = 1.81
350 : begin RFactor = 415; BFactor = 416; end // GR = 1.88, GB = 1.88
351 : begin RFactor = 409; BFactor = 423; end // GR = 1.88, GB = 1.94
352 : begin RFactor = 402; BFactor = 430; end // GR = 1.88, GB = 2.00
353 : begin RFactor = 396; BFactor = 437; end // GR = 1.88, GB = 2.06
354 : begin RFactor = 390; BFactor = 444; end // GR = 1.88, GB = 2.12
355 : begin RFactor = 384; BFactor = 450; end // GR = 1.88, GB = 2.19
356 : begin RFactor = 379; BFactor = 457; end // GR = 1.88, GB = 2.25
357 : begin RFactor = 374; BFactor = 463; end // GR = 1.88, GB = 2.31
358 : begin RFactor = 369; BFactor = 469; end // GR = 1.88, GB = 2.38
359 : begin RFactor = 364; BFactor = 476; end // GR = 1.88, GB = 2.44
360 : begin RFactor = 578; BFactor = 297; end // GR = 1.94, GB = 1.00
361 : begin RFactor = 561; BFactor = 307; end // GR = 1.94, GB = 1.06
362 : begin RFactor = 545; BFactor = 316; end // GR = 1.94, GB = 1.12
363 : begin RFactor = 531; BFactor = 325; end // GR = 1.94, GB = 1.19
364 : begin RFactor = 517; BFactor = 333; end // GR = 1.94, GB = 1.25
365 : begin RFactor = 505; BFactor = 342; end // GR = 1.94, GB = 1.31
366 : begin RFactor = 493; BFactor = 350; end // GR = 1.94, GB = 1.38
367 : begin RFactor = 482; BFactor = 358; end // GR = 1.94, GB = 1.44
368 : begin RFactor = 472; BFactor = 366; end // GR = 1.94, GB = 1.50
369 : begin RFactor = 462; BFactor = 373; end // GR = 1.94, GB = 1.56
370 : begin RFactor = 453; BFactor = 381; end // GR = 1.94, GB = 1.62
371 : begin RFactor = 445; BFactor = 388; end // GR = 1.94, GB = 1.69
372 : begin RFactor = 437; BFactor = 395; end // GR = 1.94, GB = 1.75
373 : begin RFactor = 429; BFactor = 403; end // GR = 1.94, GB = 1.81
374 : begin RFactor = 422; BFactor = 410; end // GR = 1.94, GB = 1.88
375 : begin RFactor = 415; BFactor = 416; end // GR = 1.94, GB = 1.94
376 : begin RFactor = 409; BFactor = 423; end // GR = 1.94, GB = 2.00
377 : begin RFactor = 402; BFactor = 430; end // GR = 1.94, GB = 2.06
378 : begin RFactor = 396; BFactor = 436; end // GR = 1.94, GB = 2.12
379 : begin RFactor = 391; BFactor = 443; end // GR = 1.94, GB = 2.19
380 : begin RFactor = 385; BFactor = 449; end // GR = 1.94, GB = 2.25
381 : begin RFactor = 380; BFactor = 456; end // GR = 1.94, GB = 2.31
382 : begin RFactor = 375; BFactor = 462; end // GR = 1.94, GB = 2.38
383 : begin RFactor = 370; BFactor = 468; end // GR = 1.94, GB = 2.44
384 : begin RFactor = 587; BFactor = 293; end // GR = 2.00, GB = 1.00
385 : begin RFactor = 570; BFactor = 302; end // GR = 2.00, GB = 1.06
386 : begin RFactor = 554; BFactor = 311; end // GR = 2.00, GB = 1.12
387 : begin RFactor = 539; BFactor = 319; end // GR = 2.00, GB = 1.19
388 : begin RFactor = 525; BFactor = 328; end // GR = 2.00, GB = 1.25
389 : begin RFactor = 513; BFactor = 336; end // GR = 2.00, GB = 1.31
390 : begin RFactor = 501; BFactor = 344; end // GR = 2.00, GB = 1.38
391 : begin RFactor = 490; BFactor = 352; end // GR = 2.00, GB = 1.44
392 : begin RFactor = 479; BFactor = 360; end // GR = 2.00, GB = 1.50
393 : begin RFactor = 470; BFactor = 367; end // GR = 2.00, GB = 1.56
394 : begin RFactor = 461; BFactor = 375; end // GR = 2.00, GB = 1.62
395 : begin RFactor = 452; BFactor = 382; end // GR = 2.00, GB = 1.69
396 : begin RFactor = 444; BFactor = 389; end // GR = 2.00, GB = 1.75
397 : begin RFactor = 436; BFactor = 396; end // GR = 2.00, GB = 1.81
398 : begin RFactor = 429; BFactor = 403; end // GR = 2.00, GB = 1.88
399 : begin RFactor = 422; BFactor = 410; end // GR = 2.00, GB = 1.94
400 : begin RFactor = 415; BFactor = 417; end // GR = 2.00, GB = 2.00
401 : begin RFactor = 409; BFactor = 423; end // GR = 2.00, GB = 2.06
402 : begin RFactor = 403; BFactor = 430; end // GR = 2.00, GB = 2.12
403 : begin RFactor = 397; BFactor = 436; end // GR = 2.00, GB = 2.19
404 : begin RFactor = 391; BFactor = 442; end // GR = 2.00, GB = 2.25
405 : begin RFactor = 386; BFactor = 448; end // GR = 2.00, GB = 2.31
406 : begin RFactor = 381; BFactor = 455; end // GR = 2.00, GB = 2.38
407 : begin RFactor = 376; BFactor = 461; end // GR = 2.00, GB = 2.44
408 : begin RFactor = 596; BFactor = 288; end // GR = 2.06, GB = 1.00
409 : begin RFactor = 578; BFactor = 297; end // GR = 2.06, GB = 1.06
410 : begin RFactor = 562; BFactor = 306; end // GR = 2.06, GB = 1.12
411 : begin RFactor = 547; BFactor = 315; end // GR = 2.06, GB = 1.19
412 : begin RFactor = 533; BFactor = 323; end // GR = 2.06, GB = 1.25
413 : begin RFactor = 520; BFactor = 331; end // GR = 2.06, GB = 1.31
414 : begin RFactor = 508; BFactor = 339; end // GR = 2.06, GB = 1.38
415 : begin RFactor = 497; BFactor = 347; end // GR = 2.06, GB = 1.44
416 : begin RFactor = 487; BFactor = 354; end // GR = 2.06, GB = 1.50
417 : begin RFactor = 477; BFactor = 362; end // GR = 2.06, GB = 1.56
418 : begin RFactor = 468; BFactor = 369; end // GR = 2.06, GB = 1.62
419 : begin RFactor = 459; BFactor = 376; end // GR = 2.06, GB = 1.69
420 : begin RFactor = 451; BFactor = 383; end // GR = 2.06, GB = 1.75
421 : begin RFactor = 443; BFactor = 390; end // GR = 2.06, GB = 1.81
422 : begin RFactor = 435; BFactor = 397; end // GR = 2.06, GB = 1.88
423 : begin RFactor = 428; BFactor = 404; end // GR = 2.06, GB = 1.94
424 : begin RFactor = 421; BFactor = 410; end // GR = 2.06, GB = 2.00
425 : begin RFactor = 415; BFactor = 417; end // GR = 2.06, GB = 2.06
426 : begin RFactor = 409; BFactor = 423; end // GR = 2.06, GB = 2.12
427 : begin RFactor = 403; BFactor = 429; end // GR = 2.06, GB = 2.19
428 : begin RFactor = 397; BFactor = 435; end // GR = 2.06, GB = 2.25
429 : begin RFactor = 392; BFactor = 442; end // GR = 2.06, GB = 2.31
430 : begin RFactor = 387; BFactor = 448; end // GR = 2.06, GB = 2.38
431 : begin RFactor = 382; BFactor = 454; end // GR = 2.06, GB = 2.44
432 : begin RFactor = 605; BFactor = 284; end // GR = 2.12, GB = 1.00
433 : begin RFactor = 587; BFactor = 293; end // GR = 2.12, GB = 1.06
434 : begin RFactor = 570; BFactor = 302; end // GR = 2.12, GB = 1.12
435 : begin RFactor = 555; BFactor = 310; end // GR = 2.12, GB = 1.19
436 : begin RFactor = 541; BFactor = 318; end // GR = 2.12, GB = 1.25
437 : begin RFactor = 528; BFactor = 326; end // GR = 2.12, GB = 1.31
438 : begin RFactor = 516; BFactor = 334; end // GR = 2.12, GB = 1.38
439 : begin RFactor = 505; BFactor = 342; end // GR = 2.12, GB = 1.44
440 : begin RFactor = 494; BFactor = 349; end // GR = 2.12, GB = 1.50
441 : begin RFactor = 484; BFactor = 356; end // GR = 2.12, GB = 1.56
442 : begin RFactor = 475; BFactor = 364; end // GR = 2.12, GB = 1.62
443 : begin RFactor = 466; BFactor = 371; end // GR = 2.12, GB = 1.69
444 : begin RFactor = 457; BFactor = 378; end // GR = 2.12, GB = 1.75
445 : begin RFactor = 449; BFactor = 384; end // GR = 2.12, GB = 1.81
446 : begin RFactor = 442; BFactor = 391; end // GR = 2.12, GB = 1.88
447 : begin RFactor = 435; BFactor = 398; end // GR = 2.12, GB = 1.94
448 : begin RFactor = 428; BFactor = 404; end // GR = 2.12, GB = 2.00
449 : begin RFactor = 421; BFactor = 410; end // GR = 2.12, GB = 2.06
450 : begin RFactor = 415; BFactor = 417; end // GR = 2.12, GB = 2.12
451 : begin RFactor = 409; BFactor = 423; end // GR = 2.12, GB = 2.19
452 : begin RFactor = 403; BFactor = 429; end // GR = 2.12, GB = 2.25
453 : begin RFactor = 398; BFactor = 435; end // GR = 2.12, GB = 2.31
454 : begin RFactor = 392; BFactor = 441; end // GR = 2.12, GB = 2.38
455 : begin RFactor = 387; BFactor = 447; end // GR = 2.12, GB = 2.44
456 : begin RFactor = 614; BFactor = 280; end // GR = 2.19, GB = 1.00
457 : begin RFactor = 595; BFactor = 289; end // GR = 2.19, GB = 1.06
458 : begin RFactor = 579; BFactor = 297; end // GR = 2.19, GB = 1.12
459 : begin RFactor = 563; BFactor = 305; end // GR = 2.19, GB = 1.19
460 : begin RFactor = 549; BFactor = 314; end // GR = 2.19, GB = 1.25
461 : begin RFactor = 536; BFactor = 321; end // GR = 2.19, GB = 1.31
462 : begin RFactor = 523; BFactor = 329; end // GR = 2.19, GB = 1.38
463 : begin RFactor = 512; BFactor = 337; end // GR = 2.19, GB = 1.44
464 : begin RFactor = 501; BFactor = 344; end // GR = 2.19, GB = 1.50
465 : begin RFactor = 491; BFactor = 351; end // GR = 2.19, GB = 1.56
466 : begin RFactor = 481; BFactor = 358; end // GR = 2.19, GB = 1.62
467 : begin RFactor = 472; BFactor = 365; end // GR = 2.19, GB = 1.69
468 : begin RFactor = 464; BFactor = 372; end // GR = 2.19, GB = 1.75
469 : begin RFactor = 456; BFactor = 379; end // GR = 2.19, GB = 1.81
470 : begin RFactor = 448; BFactor = 385; end // GR = 2.19, GB = 1.88
471 : begin RFactor = 441; BFactor = 392; end // GR = 2.19, GB = 1.94
472 : begin RFactor = 434; BFactor = 398; end // GR = 2.19, GB = 2.00
473 : begin RFactor = 427; BFactor = 405; end // GR = 2.19, GB = 2.06
474 : begin RFactor = 421; BFactor = 411; end // GR = 2.19, GB = 2.12
475 : begin RFactor = 415; BFactor = 417; end // GR = 2.19, GB = 2.19
476 : begin RFactor = 409; BFactor = 423; end // GR = 2.19, GB = 2.25
477 : begin RFactor = 403; BFactor = 429; end // GR = 2.19, GB = 2.31
478 : begin RFactor = 398; BFactor = 435; end // GR = 2.19, GB = 2.38
479 : begin RFactor = 393; BFactor = 440; end // GR = 2.19, GB = 2.44
480 : begin RFactor = 622; BFactor = 276; end // GR = 2.25, GB = 1.00
481 : begin RFactor = 604; BFactor = 285; end // GR = 2.25, GB = 1.06
482 : begin RFactor = 587; BFactor = 293; end // GR = 2.25, GB = 1.12
483 : begin RFactor = 571; BFactor = 301; end // GR = 2.25, GB = 1.19
484 : begin RFactor = 557; BFactor = 309; end // GR = 2.25, GB = 1.25
485 : begin RFactor = 543; BFactor = 317; end // GR = 2.25, GB = 1.31
486 : begin RFactor = 531; BFactor = 325; end // GR = 2.25, GB = 1.38
487 : begin RFactor = 519; BFactor = 332; end // GR = 2.25, GB = 1.44
488 : begin RFactor = 508; BFactor = 339; end // GR = 2.25, GB = 1.50
489 : begin RFactor = 498; BFactor = 346; end // GR = 2.25, GB = 1.56
490 : begin RFactor = 488; BFactor = 353; end // GR = 2.25, GB = 1.62
491 : begin RFactor = 479; BFactor = 360; end // GR = 2.25, GB = 1.69
492 : begin RFactor = 470; BFactor = 367; end // GR = 2.25, GB = 1.75
493 : begin RFactor = 462; BFactor = 373; end // GR = 2.25, GB = 1.81
494 : begin RFactor = 454; BFactor = 380; end // GR = 2.25, GB = 1.88
495 : begin RFactor = 447; BFactor = 386; end // GR = 2.25, GB = 1.94
496 : begin RFactor = 440; BFactor = 393; end // GR = 2.25, GB = 2.00
497 : begin RFactor = 433; BFactor = 399; end // GR = 2.25, GB = 2.06
498 : begin RFactor = 427; BFactor = 405; end // GR = 2.25, GB = 2.12
499 : begin RFactor = 421; BFactor = 411; end // GR = 2.25, GB = 2.19
500 : begin RFactor = 415; BFactor = 417; end // GR = 2.25, GB = 2.25
501 : begin RFactor = 409; BFactor = 423; end // GR = 2.25, GB = 2.31
502 : begin RFactor = 404; BFactor = 429; end // GR = 2.25, GB = 2.38
503 : begin RFactor = 398; BFactor = 434; end // GR = 2.25, GB = 2.44
504 : begin RFactor = 631; BFactor = 272; end // GR = 2.31, GB = 1.00
505 : begin RFactor = 612; BFactor = 281; end // GR = 2.31, GB = 1.06
506 : begin RFactor = 595; BFactor = 289; end // GR = 2.31, GB = 1.12
507 : begin RFactor = 579; BFactor = 297; end // GR = 2.31, GB = 1.19
508 : begin RFactor = 564; BFactor = 305; end // GR = 2.31, GB = 1.25
509 : begin RFactor = 551; BFactor = 313; end // GR = 2.31, GB = 1.31
510 : begin RFactor = 538; BFactor = 320; end // GR = 2.31, GB = 1.38
511 : begin RFactor = 526; BFactor = 327; end // GR = 2.31, GB = 1.44
512 : begin RFactor = 515; BFactor = 335; end // GR = 2.31, GB = 1.50
513 : begin RFactor = 505; BFactor = 342; end // GR = 2.31, GB = 1.56
514 : begin RFactor = 495; BFactor = 348; end // GR = 2.31, GB = 1.62
515 : begin RFactor = 485; BFactor = 355; end // GR = 2.31, GB = 1.69
516 : begin RFactor = 477; BFactor = 362; end // GR = 2.31, GB = 1.75
517 : begin RFactor = 468; BFactor = 368; end // GR = 2.31, GB = 1.81
518 : begin RFactor = 461; BFactor = 375; end // GR = 2.31, GB = 1.88
519 : begin RFactor = 453; BFactor = 381; end // GR = 2.31, GB = 1.94
520 : begin RFactor = 446; BFactor = 387; end // GR = 2.31, GB = 2.00
521 : begin RFactor = 439; BFactor = 393; end // GR = 2.31, GB = 2.06
522 : begin RFactor = 433; BFactor = 399; end // GR = 2.31, GB = 2.12
523 : begin RFactor = 426; BFactor = 405; end // GR = 2.31, GB = 2.19
524 : begin RFactor = 420; BFactor = 411; end // GR = 2.31, GB = 2.25
525 : begin RFactor = 415; BFactor = 417; end // GR = 2.31, GB = 2.31
526 : begin RFactor = 409; BFactor = 423; end // GR = 2.31, GB = 2.38
527 : begin RFactor = 404; BFactor = 428; end // GR = 2.31, GB = 2.44
528 : begin RFactor = 639; BFactor = 269; end // GR = 2.38, GB = 1.00
529 : begin RFactor = 620; BFactor = 277; end // GR = 2.38, GB = 1.06
530 : begin RFactor = 603; BFactor = 285; end // GR = 2.38, GB = 1.12
531 : begin RFactor = 586; BFactor = 293; end // GR = 2.38, GB = 1.19
532 : begin RFactor = 572; BFactor = 301; end // GR = 2.38, GB = 1.25
533 : begin RFactor = 558; BFactor = 308; end // GR = 2.38, GB = 1.31
534 : begin RFactor = 545; BFactor = 316; end // GR = 2.38, GB = 1.38
535 : begin RFactor = 533; BFactor = 323; end // GR = 2.38, GB = 1.44
536 : begin RFactor = 522; BFactor = 330; end // GR = 2.38, GB = 1.50
537 : begin RFactor = 511; BFactor = 337; end // GR = 2.38, GB = 1.56
538 : begin RFactor = 501; BFactor = 344; end // GR = 2.38, GB = 1.62
539 : begin RFactor = 492; BFactor = 351; end // GR = 2.38, GB = 1.69
540 : begin RFactor = 483; BFactor = 357; end // GR = 2.38, GB = 1.75
541 : begin RFactor = 475; BFactor = 364; end // GR = 2.38, GB = 1.81
542 : begin RFactor = 467; BFactor = 370; end // GR = 2.38, GB = 1.88
543 : begin RFactor = 459; BFactor = 376; end // GR = 2.38, GB = 1.94
544 : begin RFactor = 452; BFactor = 382; end // GR = 2.38, GB = 2.00
545 : begin RFactor = 445; BFactor = 388; end // GR = 2.38, GB = 2.06
546 : begin RFactor = 438; BFactor = 394; end // GR = 2.38, GB = 2.12
547 : begin RFactor = 432; BFactor = 400; end // GR = 2.38, GB = 2.19
548 : begin RFactor = 426; BFactor = 406; end // GR = 2.38, GB = 2.25
549 : begin RFactor = 420; BFactor = 411; end // GR = 2.38, GB = 2.31
550 : begin RFactor = 415; BFactor = 417; end // GR = 2.38, GB = 2.38
551 : begin RFactor = 409; BFactor = 423; end // GR = 2.38, GB = 2.44
552 : begin RFactor = 647; BFactor = 265; end // GR = 2.44, GB = 1.00
553 : begin RFactor = 628; BFactor = 273; end // GR = 2.44, GB = 1.06
554 : begin RFactor = 610; BFactor = 281; end // GR = 2.44, GB = 1.12
555 : begin RFactor = 594; BFactor = 289; end // GR = 2.44, GB = 1.19
556 : begin RFactor = 579; BFactor = 297; end // GR = 2.44, GB = 1.25
557 : begin RFactor = 565; BFactor = 304; end // GR = 2.44, GB = 1.31
558 : begin RFactor = 552; BFactor = 312; end // GR = 2.44, GB = 1.38
559 : begin RFactor = 540; BFactor = 319; end // GR = 2.44, GB = 1.44
560 : begin RFactor = 528; BFactor = 326; end // GR = 2.44, GB = 1.50
561 : begin RFactor = 518; BFactor = 333; end // GR = 2.44, GB = 1.56
562 : begin RFactor = 508; BFactor = 339; end // GR = 2.44, GB = 1.62
563 : begin RFactor = 498; BFactor = 346; end // GR = 2.44, GB = 1.69
564 : begin RFactor = 489; BFactor = 352; end // GR = 2.44, GB = 1.75
565 : begin RFactor = 481; BFactor = 359; end // GR = 2.44, GB = 1.81
566 : begin RFactor = 473; BFactor = 365; end // GR = 2.44, GB = 1.88
567 : begin RFactor = 465; BFactor = 371; end // GR = 2.44, GB = 1.94
568 : begin RFactor = 458; BFactor = 377; end // GR = 2.44, GB = 2.00
569 : begin RFactor = 451; BFactor = 383; end // GR = 2.44, GB = 2.06
570 : begin RFactor = 444; BFactor = 389; end // GR = 2.44, GB = 2.12
571 : begin RFactor = 438; BFactor = 395; end // GR = 2.44, GB = 2.19
572 : begin RFactor = 431; BFactor = 401; end // GR = 2.44, GB = 2.25
573 : begin RFactor = 426; BFactor = 406; end // GR = 2.44, GB = 2.31
574 : begin RFactor = 420; BFactor = 412; end // GR = 2.44, GB = 2.38
575 : begin RFactor = 414; BFactor = 417; end // GR = 2.44, GB = 2.44
endcase
end
endtask
function[ `size_int - 1 : 0 ]LUTPow033( input[ `size_int - 1 : 0 ]Index );
begin
case( Index )
0 : LUTPow033 = 0;
1 : LUTPow033 = 256;
2 : LUTPow033 = 322;
3 : LUTPow033 = 369;
4 : LUTPow033 = 406;
5 : LUTPow033 = 437;
6 : LUTPow033 = 465;
7 : LUTPow033 = 489;
8 : LUTPow033 = 511;
9 : LUTPow033 = 532;
10 : LUTPow033 = 551;
11 : LUTPow033 = 569;
12 : LUTPow033 = 586;
13 : LUTPow033 = 601;
14 : LUTPow033 = 616;
15 : LUTPow033 = 631;
16 : LUTPow033 = 645;
17 : LUTPow033 = 658;
18 : LUTPow033 = 670;
19 : LUTPow033 = 683;
20 : LUTPow033 = 694;
21 : LUTPow033 = 706;
22 : LUTPow033 = 717;
23 : LUTPow033 = 728;
24 : LUTPow033 = 738;
25 : LUTPow033 = 748;
26 : LUTPow033 = 758;
27 : LUTPow033 = 767;
28 : LUTPow033 = 777;
29 : LUTPow033 = 786;
30 : LUTPow033 = 795;
31 : LUTPow033 = 804;
32 : LUTPow033 = 812;
33 : LUTPow033 = 821;
34 : LUTPow033 = 829;
35 : LUTPow033 = 837;
36 : LUTPow033 = 845;
37 : LUTPow033 = 853;
38 : LUTPow033 = 860;
39 : LUTPow033 = 868;
40 : LUTPow033 = 875;
41 : LUTPow033 = 882;
42 : LUTPow033 = 889;
43 : LUTPow033 = 896;
44 : LUTPow033 = 903;
45 : LUTPow033 = 910;
46 : LUTPow033 = 917;
47 : LUTPow033 = 923;
48 : LUTPow033 = 930;
49 : LUTPow033 = 936;
50 : LUTPow033 = 943;
51 : LUTPow033 = 949;
52 : LUTPow033 = 955;
53 : LUTPow033 = 961;
54 : LUTPow033 = 967;
55 : LUTPow033 = 973;
56 : LUTPow033 = 979;
57 : LUTPow033 = 985;
58 : LUTPow033 = 990;
59 : LUTPow033 = 996;
60 : LUTPow033 = 1002;
61 : LUTPow033 = 1007;
62 : LUTPow033 = 1013;
63 : LUTPow033 = 1018;
64 : LUTPow033 = 1023;
65 : LUTPow033 = 1029;
66 : LUTPow033 = 1034;
67 : LUTPow033 = 1039;
68 : LUTPow033 = 1044;
69 : LUTPow033 = 1050;
70 : LUTPow033 = 1055;
71 : LUTPow033 = 1060;
72 : LUTPow033 = 1065;
73 : LUTPow033 = 1069;
74 : LUTPow033 = 1074;
75 : LUTPow033 = 1079;
76 : LUTPow033 = 1084;
77 : LUTPow033 = 1089;
78 : LUTPow033 = 1093;
79 : LUTPow033 = 1098;
80 : LUTPow033 = 1103;
81 : LUTPow033 = 1107;
82 : LUTPow033 = 1112;
83 : LUTPow033 = 1116;
84 : LUTPow033 = 1121;
85 : LUTPow033 = 1125;
86 : LUTPow033 = 1129;
87 : LUTPow033 = 1134;
88 : LUTPow033 = 1138;
89 : LUTPow033 = 1142;
90 : LUTPow033 = 1147;
91 : LUTPow033 = 1151;
92 : LUTPow033 = 1155;
93 : LUTPow033 = 1159;
94 : LUTPow033 = 1163;
95 : LUTPow033 = 1168;
96 : LUTPow033 = 1172;
97 : LUTPow033 = 1176;
98 : LUTPow033 = 1180;
99 : LUTPow033 = 1184;
100 : LUTPow033 = 1188;
101 : LUTPow033 = 1192;
102 : LUTPow033 = 1196;
103 : LUTPow033 = 1200;
104 : LUTPow033 = 1203;
105 : LUTPow033 = 1207;
106 : LUTPow033 = 1211;
107 : LUTPow033 = 1215;
108 : LUTPow033 = 1219;
109 : LUTPow033 = 1222;
110 : LUTPow033 = 1226;
111 : LUTPow033 = 1230;
112 : LUTPow033 = 1233;
113 : LUTPow033 = 1237;
114 : LUTPow033 = 1241;
115 : LUTPow033 = 1244;
116 : LUTPow033 = 1248;
117 : LUTPow033 = 1252;
118 : LUTPow033 = 1255;
119 : LUTPow033 = 1259;
120 : LUTPow033 = 1262;
121 : LUTPow033 = 1266;
122 : LUTPow033 = 1269;
123 : LUTPow033 = 1273;
124 : LUTPow033 = 1276;
125 : LUTPow033 = 1279;
126 : LUTPow033 = 1283;
127 : LUTPow033 = 1286;
128 : LUTPow033 = 1290;
129 : LUTPow033 = 1293;
130 : LUTPow033 = 1296;
131 : LUTPow033 = 1300;
132 : LUTPow033 = 1303;
133 : LUTPow033 = 1306;
134 : LUTPow033 = 1310;
135 : LUTPow033 = 1313;
136 : LUTPow033 = 1316;
137 : LUTPow033 = 1319;
138 : LUTPow033 = 1322;
139 : LUTPow033 = 1326;
140 : LUTPow033 = 1329;
141 : LUTPow033 = 1332;
142 : LUTPow033 = 1335;
143 : LUTPow033 = 1338;
144 : LUTPow033 = 1341;
145 : LUTPow033 = 1344;
146 : LUTPow033 = 1348;
147 : LUTPow033 = 1351;
148 : LUTPow033 = 1354;
149 : LUTPow033 = 1357;
150 : LUTPow033 = 1360;
151 : LUTPow033 = 1363;
152 : LUTPow033 = 1366;
153 : LUTPow033 = 1369;
154 : LUTPow033 = 1372;
155 : LUTPow033 = 1375;
156 : LUTPow033 = 1378;
157 : LUTPow033 = 1381;
158 : LUTPow033 = 1383;
159 : LUTPow033 = 1386;
160 : LUTPow033 = 1389;
161 : LUTPow033 = 1392;
162 : LUTPow033 = 1395;
163 : LUTPow033 = 1398;
164 : LUTPow033 = 1401;
165 : LUTPow033 = 1404;
166 : LUTPow033 = 1406;
167 : LUTPow033 = 1409;
168 : LUTPow033 = 1412;
169 : LUTPow033 = 1415;
170 : LUTPow033 = 1418;
171 : LUTPow033 = 1420;
172 : LUTPow033 = 1423;
173 : LUTPow033 = 1426;
174 : LUTPow033 = 1429;
175 : LUTPow033 = 1431;
176 : LUTPow033 = 1434;
177 : LUTPow033 = 1437;
178 : LUTPow033 = 1440;
179 : LUTPow033 = 1442;
180 : LUTPow033 = 1445;
181 : LUTPow033 = 1448;
182 : LUTPow033 = 1450;
183 : LUTPow033 = 1453;
184 : LUTPow033 = 1456;
185 : LUTPow033 = 1458;
186 : LUTPow033 = 1461;
187 : LUTPow033 = 1463;
188 : LUTPow033 = 1466;
189 : LUTPow033 = 1469;
190 : LUTPow033 = 1471;
191 : LUTPow033 = 1474;
192 : LUTPow033 = 1476;
193 : LUTPow033 = 1479;
194 : LUTPow033 = 1481;
195 : LUTPow033 = 1484;
196 : LUTPow033 = 1487;
197 : LUTPow033 = 1489;
198 : LUTPow033 = 1492;
199 : LUTPow033 = 1494;
200 : LUTPow033 = 1497;
201 : LUTPow033 = 1499;
202 : LUTPow033 = 1502;
203 : LUTPow033 = 1504;
204 : LUTPow033 = 1507;
205 : LUTPow033 = 1509;
206 : LUTPow033 = 1511;
207 : LUTPow033 = 1514;
208 : LUTPow033 = 1516;
209 : LUTPow033 = 1519;
210 : LUTPow033 = 1521;
211 : LUTPow033 = 1524;
212 : LUTPow033 = 1526;
213 : LUTPow033 = 1528;
214 : LUTPow033 = 1531;
215 : LUTPow033 = 1533;
216 : LUTPow033 = 1535;
217 : LUTPow033 = 1538;
218 : LUTPow033 = 1540;
219 : LUTPow033 = 1543;
220 : LUTPow033 = 1545;
221 : LUTPow033 = 1547;
222 : LUTPow033 = 1550;
223 : LUTPow033 = 1552;
224 : LUTPow033 = 1554;
225 : LUTPow033 = 1557;
226 : LUTPow033 = 1559;
227 : LUTPow033 = 1561;
228 : LUTPow033 = 1563;
229 : LUTPow033 = 1566;
230 : LUTPow033 = 1568;
231 : LUTPow033 = 1570;
232 : LUTPow033 = 1573;
233 : LUTPow033 = 1575;
234 : LUTPow033 = 1577;
235 : LUTPow033 = 1579;
236 : LUTPow033 = 1582;
237 : LUTPow033 = 1584;
238 : LUTPow033 = 1586;
239 : LUTPow033 = 1588;
240 : LUTPow033 = 1590;
241 : LUTPow033 = 1593;
242 : LUTPow033 = 1595;
243 : LUTPow033 = 1597;
244 : LUTPow033 = 1599;
245 : LUTPow033 = 1601;
246 : LUTPow033 = 1604;
247 : LUTPow033 = 1606;
248 : LUTPow033 = 1608;
249 : LUTPow033 = 1610;
250 : LUTPow033 = 1612;
251 : LUTPow033 = 1614;
252 : LUTPow033 = 1616;
253 : LUTPow033 = 1619;
254 : LUTPow033 = 1621;
255 : LUTPow033 = 1623;
256 : LUTPow033 = 1625;
endcase
end
endfunction
function[ `size_int - 1 : 0 ]LUTPow045( input[ `size_int - 1 : 0 ]source );
begin
case( source )
// ( ( RGB / 256 ) ^ 0.45 ) * 256 * 256
0 : LUTPow045 = 0;
1 : LUTPow045 = 5404;
2 : LUTPow045 = 7383;
3 : LUTPow045 = 8860;
4 : LUTPow045 = 10085;
5 : LUTPow045 = 11150;
6 : LUTPow045 = 12104;
7 : LUTPow045 = 12973;
8 : LUTPow045 = 13777;
9 : LUTPow045 = 14527;
10 : LUTPow045 = 15232;
11 : LUTPow045 = 15900;
12 : LUTPow045 = 16534;
13 : LUTPow045 = 17141;
14 : LUTPow045 = 17722;
15 : LUTPow045 = 18281;
16 : LUTPow045 = 18820;
17 : LUTPow045 = 19340;
18 : LUTPow045 = 19844;
19 : LUTPow045 = 20333;
20 : LUTPow045 = 20808;
21 : LUTPow045 = 21270;
22 : LUTPow045 = 21720;
23 : LUTPow045 = 22158;
24 : LUTPow045 = 22587;
25 : LUTPow045 = 23006;
26 : LUTPow045 = 23415;
27 : LUTPow045 = 23816;
28 : LUTPow045 = 24209;
29 : LUTPow045 = 24595;
30 : LUTPow045 = 24973;
31 : LUTPow045 = 25344;
32 : LUTPow045 = 25709;
33 : LUTPow045 = 26067;
34 : LUTPow045 = 26420;
35 : LUTPow045 = 26767;
36 : LUTPow045 = 27108;
37 : LUTPow045 = 27444;
38 : LUTPow045 = 27776;
39 : LUTPow045 = 28102;
40 : LUTPow045 = 28424;
41 : LUTPow045 = 28742;
42 : LUTPow045 = 29055;
43 : LUTPow045 = 29365;
44 : LUTPow045 = 29670;
45 : LUTPow045 = 29972;
46 : LUTPow045 = 30270;
47 : LUTPow045 = 30564;
48 : LUTPow045 = 30855;
49 : LUTPow045 = 31142;
50 : LUTPow045 = 31427;
51 : LUTPow045 = 31708;
52 : LUTPow045 = 31986;
53 : LUTPow045 = 32262;
54 : LUTPow045 = 32534;
55 : LUTPow045 = 32804;
56 : LUTPow045 = 33071;
57 : LUTPow045 = 33336;
58 : LUTPow045 = 33598;
59 : LUTPow045 = 33857;
60 : LUTPow045 = 34114;
61 : LUTPow045 = 34369;
62 : LUTPow045 = 34621;
63 : LUTPow045 = 34871;
64 : LUTPow045 = 35119;
65 : LUTPow045 = 35365;
66 : LUTPow045 = 35609;
67 : LUTPow045 = 35851;
68 : LUTPow045 = 36091;
69 : LUTPow045 = 36329;
70 : LUTPow045 = 36565;
71 : LUTPow045 = 36799;
72 : LUTPow045 = 37031;
73 : LUTPow045 = 37262;
74 : LUTPow045 = 37490;
75 : LUTPow045 = 37718;
76 : LUTPow045 = 37943;
77 : LUTPow045 = 38167;
78 : LUTPow045 = 38389;
79 : LUTPow045 = 38610;
80 : LUTPow045 = 38829;
81 : LUTPow045 = 39047;
82 : LUTPow045 = 39263;
83 : LUTPow045 = 39478;
84 : LUTPow045 = 39691;
85 : LUTPow045 = 39903;
86 : LUTPow045 = 40114;
87 : LUTPow045 = 40323;
88 : LUTPow045 = 40531;
89 : LUTPow045 = 40737;
90 : LUTPow045 = 40943;
91 : LUTPow045 = 41147;
92 : LUTPow045 = 41350;
93 : LUTPow045 = 41551;
94 : LUTPow045 = 41752;
95 : LUTPow045 = 41951;
96 : LUTPow045 = 42149;
97 : LUTPow045 = 42346;
98 : LUTPow045 = 42542;
99 : LUTPow045 = 42737;
100 : LUTPow045 = 42931;
101 : LUTPow045 = 43123;
102 : LUTPow045 = 43315;
103 : LUTPow045 = 43505;
104 : LUTPow045 = 43695;
105 : LUTPow045 = 43884;
106 : LUTPow045 = 44071;
107 : LUTPow045 = 44258;
108 : LUTPow045 = 44443;
109 : LUTPow045 = 44628;
110 : LUTPow045 = 44812;
111 : LUTPow045 = 44995;
112 : LUTPow045 = 45177;
113 : LUTPow045 = 45358;
114 : LUTPow045 = 45538;
115 : LUTPow045 = 45717;
116 : LUTPow045 = 45896;
117 : LUTPow045 = 46073;
118 : LUTPow045 = 46250;
119 : LUTPow045 = 46426;
120 : LUTPow045 = 46601;
121 : LUTPow045 = 46776;
122 : LUTPow045 = 46949;
123 : LUTPow045 = 47122;
124 : LUTPow045 = 47294;
125 : LUTPow045 = 47465;
126 : LUTPow045 = 47636;
127 : LUTPow045 = 47806;
128 : LUTPow045 = 47975;
129 : LUTPow045 = 48143;
130 : LUTPow045 = 48311;
131 : LUTPow045 = 48477;
132 : LUTPow045 = 48644;
133 : LUTPow045 = 48809;
134 : LUTPow045 = 48974;
135 : LUTPow045 = 49138;
136 : LUTPow045 = 49301;
137 : LUTPow045 = 49464;
138 : LUTPow045 = 49626;
139 : LUTPow045 = 49788;
140 : LUTPow045 = 49949;
141 : LUTPow045 = 50109;
142 : LUTPow045 = 50269;
143 : LUTPow045 = 50428;
144 : LUTPow045 = 50586;
145 : LUTPow045 = 50744;
146 : LUTPow045 = 50901;
147 : LUTPow045 = 51058;
148 : LUTPow045 = 51214;
149 : LUTPow045 = 51369;
150 : LUTPow045 = 51524;
151 : LUTPow045 = 51678;
152 : LUTPow045 = 51832;
153 : LUTPow045 = 51985;
154 : LUTPow045 = 52138;
155 : LUTPow045 = 52290;
156 : LUTPow045 = 52441;
157 : LUTPow045 = 52592;
158 : LUTPow045 = 52743;
159 : LUTPow045 = 52893;
160 : LUTPow045 = 53042;
161 : LUTPow045 = 53191;
162 : LUTPow045 = 53340;
163 : LUTPow045 = 53488;
164 : LUTPow045 = 53635;
165 : LUTPow045 = 53782;
166 : LUTPow045 = 53928;
167 : LUTPow045 = 54074;
168 : LUTPow045 = 54220;
169 : LUTPow045 = 54365;
170 : LUTPow045 = 54509;
171 : LUTPow045 = 54653;
172 : LUTPow045 = 54797;
173 : LUTPow045 = 54940;
174 : LUTPow045 = 55083;
175 : LUTPow045 = 55225;
176 : LUTPow045 = 55367;
177 : LUTPow045 = 55508;
178 : LUTPow045 = 55649;
179 : LUTPow045 = 55789;
180 : LUTPow045 = 55929;
181 : LUTPow045 = 56069;
182 : LUTPow045 = 56208;
183 : LUTPow045 = 56347;
184 : LUTPow045 = 56485;
185 : LUTPow045 = 56623;
186 : LUTPow045 = 56761;
187 : LUTPow045 = 56898;
188 : LUTPow045 = 57035;
189 : LUTPow045 = 57171;
190 : LUTPow045 = 57307;
191 : LUTPow045 = 57442;
192 : LUTPow045 = 57578;
193 : LUTPow045 = 57712;
194 : LUTPow045 = 57847;
195 : LUTPow045 = 57981;
196 : LUTPow045 = 58114;
197 : LUTPow045 = 58248;
198 : LUTPow045 = 58380;
199 : LUTPow045 = 58513;
200 : LUTPow045 = 58645;
201 : LUTPow045 = 58777;
202 : LUTPow045 = 58908;
203 : LUTPow045 = 59039;
204 : LUTPow045 = 59170;
205 : LUTPow045 = 59300;
206 : LUTPow045 = 59430;
207 : LUTPow045 = 59560;
208 : LUTPow045 = 59689;
209 : LUTPow045 = 59818;
210 : LUTPow045 = 59947;
211 : LUTPow045 = 60075;
212 : LUTPow045 = 60203;
213 : LUTPow045 = 60331;
214 : LUTPow045 = 60458;
215 : LUTPow045 = 60585;
216 : LUTPow045 = 60712;
217 : LUTPow045 = 60838;
218 : LUTPow045 = 60964;
219 : LUTPow045 = 61090;
220 : LUTPow045 = 61215;
221 : LUTPow045 = 61340;
222 : LUTPow045 = 61465;
223 : LUTPow045 = 61589;
224 : LUTPow045 = 61713;
225 : LUTPow045 = 61837;
226 : LUTPow045 = 61961;
227 : LUTPow045 = 62084;
228 : LUTPow045 = 62207;
229 : LUTPow045 = 62330;
230 : LUTPow045 = 62452;
231 : LUTPow045 = 62574;
232 : LUTPow045 = 62696;
233 : LUTPow045 = 62817;
234 : LUTPow045 = 62938;
235 : LUTPow045 = 63059;
236 : LUTPow045 = 63180;
237 : LUTPow045 = 63300;
238 : LUTPow045 = 63420;
239 : LUTPow045 = 63540;
240 : LUTPow045 = 63660;
241 : LUTPow045 = 63779;
242 : LUTPow045 = 63898;
243 : LUTPow045 = 64016;
244 : LUTPow045 = 64135;
245 : LUTPow045 = 64253;
246 : LUTPow045 = 64371;
247 : LUTPow045 = 64488;
248 : LUTPow045 = 64606;
249 : LUTPow045 = 64723;
250 : LUTPow045 = 64840;
251 : LUTPow045 = 64956;
252 : LUTPow045 = 65073;
253 : LUTPow045 = 65189;
254 : LUTPow045 = 65305;
255 : LUTPow045 = 65420;
endcase
end
endfunction
endmodule
module ColorImageProcess_testbench;
// Signal declaration
reg Clock;
reg Reset;
reg[ `size_char - 1 : 0 ]R;
reg[ `size_char - 1 : 0 ]G;
reg[ `size_char - 1 : 0 ]B;
wire[ `size_char - 1 : 0 ]R_out;
wire[ `size_char - 1 : 0 ]G_out;
wire[ `size_char - 1 : 0 ]B_out;
integer i;
integer InputFile;
integer OutputFile;
reg[ `size_char - 1 : 0 ]ImageDataBlock[ 0 : `SumPixel * 3 ];
ColorImageProcess ColorImageProcess_test
(
Clock,
Reset,
R,
G,
B,
R_out,
G_out,
B_out
);
initial
begin
#2
begin
Clock = 0;
// open data for input file
InputFile = $fopen( "data/IM000565_RAW_20x15.BMP", "rb" );
//InputFile = $fopen( "data/IM000565_RAW_320x240.BMP", "rb" );
// open data for output file
OutputFile = $fopen( "data/TEST.BMP", "wb" );
end
//$fread( BitMapHeader, InputFile, 0, `BitMapHeaderLength );
for( i = 0; i < `BitMapHeaderLength; i = i + 1 )
#2 $fwriteb( OutputFile, "%c", $fgetc( InputFile ) );
for( i = 0; i < `SumPixel * 3; i = i + 1 )
#2 ImageDataBlock[ i ] = $fgetc( InputFile );
#2 Reset = 1;
// #2 Reset = 0;
// Apply Stimulus in order to
for( i = 0; i < `SumPixel * 3; i = i + 3 )
begin
#2
begin
Reset = 0;
B = ImageDataBlock[ i + 0 ];
G = ImageDataBlock[ i + 1 ];
R = ImageDataBlock[ i + 2 ];
end
end
for( i = 0; i < `SumPixel * 3; i = i + 3 )
begin
#2
begin
B = ImageDataBlock[ i + 0 ];
G = ImageDataBlock[ i + 1 ];
R = ImageDataBlock[ i + 2 ];
end
#4
#2
begin
// display information on the screen
//$display( "R = %X, G = %X, B = %X\t\tR = %X, G = %X, B = %X",
//ImageDataBlock[ i + 2 ], ImageDataBlock[ i + 1 ], ImageDataBlock[ i + 0 ], R_out, G_out, B_out );
$fwriteb( OutputFile, "%c", B_out );
$fwriteb( OutputFile, "%c", G_out );
$fwriteb( OutputFile, "%c", R_out );
end
end
$fclose( InputFile );
#100000 $stop;
#100000 $finish;
end
always #1 Clock = ~Clock; //Toggle Clock
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2_2_V
`define SKY130_FD_SC_HDLL__NOR2_2_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor2_2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor2_2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21A_PP_SYMBOL_V
`define SKY130_FD_SC_MS__O21A_PP_SYMBOL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o21a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21A_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_V
`define SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_V
/**
* probec_p: Virtual current probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__probec_p (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__MUX4_BEHAVIORAL_PP_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_4to2/sky130_fd_sc_ms__udp_mux_4to2.v"
`celldefine
module sky130_fd_sc_ms__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_4to20_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_4to2 mux_4to20 (mux_4to20_out_X , A0, A1, A2, A3, S0, S1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX4_BEHAVIORAL_PP_V |
// megafunction wizard: %ALTECC%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altecc_decoder
// ============================================================
// File Name: alt_mem_ddrx_ecc_decoder_64.v
// Megafunction Name(s):
// altecc_decoder
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altecc_decoder device_family="Stratix III" lpm_pipeline=0 width_codeword=72 width_dataword=64 data err_corrected err_detected err_fatal q
//VERSION_BEGIN 10.0SP1 cbx_altecc_decoder 2010:08:18:21:16:35:SJ cbx_cycloneii 2010:08:18:21:16:35:SJ cbx_lpm_add_sub 2010:08:18:21:16:35:SJ cbx_lpm_compare 2010:08:18:21:16:35:SJ cbx_lpm_decode 2010:08:18:21:16:35:SJ cbx_mgl 2010:08:18:21:20:44:SJ cbx_stratix 2010:08:18:21:16:35:SJ cbx_stratixii 2010:08:18:21:16:35:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//lpm_decode DEVICE_FAMILY="Stratix III" LPM_DECODES=128 LPM_WIDTH=7 data eq
//VERSION_BEGIN 10.0SP1 cbx_cycloneii 2010:08:18:21:16:35:SJ cbx_lpm_add_sub 2010:08:18:21:16:35:SJ cbx_lpm_compare 2010:08:18:21:16:35:SJ cbx_lpm_decode 2010:08:18:21:16:35:SJ cbx_mgl 2010:08:18:21:20:44:SJ cbx_stratix 2010:08:18:21:16:35:SJ cbx_stratixii 2010:08:18:21:16:35:SJ VERSION_END
//synthesis_resources = lut 144
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_decoder_64_decode
(
data,
eq) /* synthesis synthesis_clearbox=1 */;
input [6:0] data;
output [127:0] eq;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [6:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [5:0] data_wire;
wire enable_wire1;
wire enable_wire2;
wire [127:0] eq_node;
wire [63:0] eq_wire1;
wire [63:0] eq_wire2;
wire [3:0] w_anode1006w;
wire [3:0] w_anode1018w;
wire [3:0] w_anode1029w;
wire [3:0] w_anode1040w;
wire [3:0] w_anode1050w;
wire [3:0] w_anode1060w;
wire [3:0] w_anode1070w;
wire [3:0] w_anode1080w;
wire [3:0] w_anode1090w;
wire [3:0] w_anode1100w;
wire [3:0] w_anode1111w;
wire [3:0] w_anode1122w;
wire [3:0] w_anode1133w;
wire [3:0] w_anode1143w;
wire [3:0] w_anode1153w;
wire [3:0] w_anode1163w;
wire [3:0] w_anode1173w;
wire [3:0] w_anode1183w;
wire [3:0] w_anode1193w;
wire [3:0] w_anode1204w;
wire [3:0] w_anode1215w;
wire [3:0] w_anode1226w;
wire [3:0] w_anode1236w;
wire [3:0] w_anode1246w;
wire [3:0] w_anode1256w;
wire [3:0] w_anode1266w;
wire [3:0] w_anode1276w;
wire [3:0] w_anode1286w;
wire [3:0] w_anode1297w;
wire [3:0] w_anode1308w;
wire [3:0] w_anode1319w;
wire [3:0] w_anode1329w;
wire [3:0] w_anode1339w;
wire [3:0] w_anode1349w;
wire [3:0] w_anode1359w;
wire [3:0] w_anode1369w;
wire [3:0] w_anode1379w;
wire [3:0] w_anode1390w;
wire [3:0] w_anode1401w;
wire [3:0] w_anode1412w;
wire [3:0] w_anode1422w;
wire [3:0] w_anode1432w;
wire [3:0] w_anode1442w;
wire [3:0] w_anode1452w;
wire [3:0] w_anode1462w;
wire [3:0] w_anode1472w;
wire [3:0] w_anode1483w;
wire [3:0] w_anode1494w;
wire [3:0] w_anode1505w;
wire [3:0] w_anode1515w;
wire [3:0] w_anode1525w;
wire [3:0] w_anode1535w;
wire [3:0] w_anode1545w;
wire [3:0] w_anode1555w;
wire [3:0] w_anode1565w;
wire [3:0] w_anode1576w;
wire [3:0] w_anode1587w;
wire [3:0] w_anode1598w;
wire [3:0] w_anode1608w;
wire [3:0] w_anode1618w;
wire [3:0] w_anode1628w;
wire [3:0] w_anode1638w;
wire [3:0] w_anode1648w;
wire [3:0] w_anode1658w;
wire [3:0] w_anode1670w;
wire [3:0] w_anode1681w;
wire [3:0] w_anode1698w;
wire [3:0] w_anode1708w;
wire [3:0] w_anode1718w;
wire [3:0] w_anode1728w;
wire [3:0] w_anode1738w;
wire [3:0] w_anode1748w;
wire [3:0] w_anode1758w;
wire [3:0] w_anode1770w;
wire [3:0] w_anode1781w;
wire [3:0] w_anode1792w;
wire [3:0] w_anode1802w;
wire [3:0] w_anode1812w;
wire [3:0] w_anode1822w;
wire [3:0] w_anode1832w;
wire [3:0] w_anode1842w;
wire [3:0] w_anode1852w;
wire [3:0] w_anode1863w;
wire [3:0] w_anode1874w;
wire [3:0] w_anode1885w;
wire [3:0] w_anode1895w;
wire [3:0] w_anode1905w;
wire [3:0] w_anode1915w;
wire [3:0] w_anode1925w;
wire [3:0] w_anode1935w;
wire [3:0] w_anode1945w;
wire [3:0] w_anode1956w;
wire [3:0] w_anode1967w;
wire [3:0] w_anode1978w;
wire [3:0] w_anode1988w;
wire [3:0] w_anode1998w;
wire [3:0] w_anode2008w;
wire [3:0] w_anode2018w;
wire [3:0] w_anode2028w;
wire [3:0] w_anode2038w;
wire [3:0] w_anode2049w;
wire [3:0] w_anode2060w;
wire [3:0] w_anode2071w;
wire [3:0] w_anode2081w;
wire [3:0] w_anode2091w;
wire [3:0] w_anode2101w;
wire [3:0] w_anode2111w;
wire [3:0] w_anode2121w;
wire [3:0] w_anode2131w;
wire [3:0] w_anode2142w;
wire [3:0] w_anode2153w;
wire [3:0] w_anode2164w;
wire [3:0] w_anode2174w;
wire [3:0] w_anode2184w;
wire [3:0] w_anode2194w;
wire [3:0] w_anode2204w;
wire [3:0] w_anode2214w;
wire [3:0] w_anode2224w;
wire [3:0] w_anode2235w;
wire [3:0] w_anode2246w;
wire [3:0] w_anode2257w;
wire [3:0] w_anode2267w;
wire [3:0] w_anode2277w;
wire [3:0] w_anode2287w;
wire [3:0] w_anode2297w;
wire [3:0] w_anode2307w;
wire [3:0] w_anode2317w;
wire [3:0] w_anode2328w;
wire [3:0] w_anode2339w;
wire [3:0] w_anode2350w;
wire [3:0] w_anode2360w;
wire [3:0] w_anode2370w;
wire [3:0] w_anode2380w;
wire [3:0] w_anode2390w;
wire [3:0] w_anode2400w;
wire [3:0] w_anode2410w;
wire [3:0] w_anode912w;
wire [3:0] w_anode929w;
wire [3:0] w_anode946w;
wire [3:0] w_anode956w;
wire [3:0] w_anode966w;
wire [3:0] w_anode976w;
wire [3:0] w_anode986w;
wire [3:0] w_anode996w;
wire [2:0] w_data1669w;
wire [2:0] w_data910w;
assign
data_wire = data[5:0],
enable_wire1 = (~ data[6]),
enable_wire2 = data[6],
eq = eq_node,
eq_node = {eq_wire2[63:0], eq_wire1},
eq_wire1 = {{w_anode1658w[3], w_anode1648w[3], w_anode1638w[3], w_anode1628w[3], w_anode1618w[3], w_anode1608w[3], w_anode1598w[3], w_anode1587w[3]}, {w_anode1565w[3], w_anode1555w[3], w_anode1545w[3], w_anode1535w[3], w_anode1525w[3], w_anode1515w[3], w_anode1505w[3], w_anode1494w[3]}, {w_anode1472w[3], w_anode1462w[3], w_anode1452w[3], w_anode1442w[3], w_anode1432w[3], w_anode1422w[3], w_anode1412w[3], w_anode1401w[3]}, {w_anode1379w[3], w_anode1369w[3], w_anode1359w[3], w_anode1349w[3], w_anode1339w[3], w_anode1329w[3], w_anode1319w[3], w_anode1308w[3]}, {w_anode1286w[3], w_anode1276w[3], w_anode1266w[3], w_anode1256w[3], w_anode1246w[3], w_anode1236w[3], w_anode1226w[3], w_anode1215w[3]}, {w_anode1193w[3], w_anode1183w[3], w_anode1173w[3], w_anode1163w[3], w_anode1153w[3], w_anode1143w[3], w_anode1133w[3], w_anode1122w[3]}, {w_anode1100w[3], w_anode1090w[3], w_anode1080w[3], w_anode1070w[3], w_anode1060w[3], w_anode1050w[3], w_anode1040w[3], w_anode1029w[3]}, {w_anode1006w[3], w_anode996w[3], w_anode986w[3], w_anode976w[3], w_anode966w[3], w_anode956w[3], w_anode946w[3], w_anode929w[3]}},
eq_wire2 = {{w_anode2410w[3], w_anode2400w[3], w_anode2390w[3], w_anode2380w[3], w_anode2370w[3], w_anode2360w[3], w_anode2350w[3], w_anode2339w[3]}, {w_anode2317w[3], w_anode2307w[3], w_anode2297w[3], w_anode2287w[3], w_anode2277w[3], w_anode2267w[3], w_anode2257w[3], w_anode2246w[3]}, {w_anode2224w[3], w_anode2214w[3], w_anode2204w[3], w_anode2194w[3], w_anode2184w[3], w_anode2174w[3], w_anode2164w[3], w_anode2153w[3]}, {w_anode2131w[3], w_anode2121w[3], w_anode2111w[3], w_anode2101w[3], w_anode2091w[3], w_anode2081w[3], w_anode2071w[3], w_anode2060w[3]}, {w_anode2038w[3], w_anode2028w[3], w_anode2018w[3], w_anode2008w[3], w_anode1998w[3], w_anode1988w[3], w_anode1978w[3], w_anode1967w[3]}, {w_anode1945w[3], w_anode1935w[3], w_anode1925w[3], w_anode1915w[3], w_anode1905w[3], w_anode1895w[3], w_anode1885w[3], w_anode1874w[3]}, {w_anode1852w[3], w_anode1842w[3], w_anode1832w[3], w_anode1822w[3], w_anode1812w[3], w_anode1802w[3], w_anode1792w[3], w_anode1781w[3]}, {w_anode1758w[3], w_anode1748w[3], w_anode1738w[3], w_anode1728w[3], w_anode1718w[3], w_anode1708w[3], w_anode1698w[3], w_anode1681w[3]}},
w_anode1006w = {(w_anode1006w[2] & w_data910w[2]), (w_anode1006w[1] & w_data910w[1]), (w_anode1006w[0] & w_data910w[0]), w_anode912w[3]},
w_anode1018w = {(w_anode1018w[2] & (~ data_wire[5])), (w_anode1018w[1] & (~ data_wire[4])), (w_anode1018w[0] & data_wire[3]), enable_wire1},
w_anode1029w = {(w_anode1029w[2] & (~ w_data910w[2])), (w_anode1029w[1] & (~ w_data910w[1])), (w_anode1029w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1040w = {(w_anode1040w[2] & (~ w_data910w[2])), (w_anode1040w[1] & (~ w_data910w[1])), (w_anode1040w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1050w = {(w_anode1050w[2] & (~ w_data910w[2])), (w_anode1050w[1] & w_data910w[1]), (w_anode1050w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1060w = {(w_anode1060w[2] & (~ w_data910w[2])), (w_anode1060w[1] & w_data910w[1]), (w_anode1060w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1070w = {(w_anode1070w[2] & w_data910w[2]), (w_anode1070w[1] & (~ w_data910w[1])), (w_anode1070w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1080w = {(w_anode1080w[2] & w_data910w[2]), (w_anode1080w[1] & (~ w_data910w[1])), (w_anode1080w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1090w = {(w_anode1090w[2] & w_data910w[2]), (w_anode1090w[1] & w_data910w[1]), (w_anode1090w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1100w = {(w_anode1100w[2] & w_data910w[2]), (w_anode1100w[1] & w_data910w[1]), (w_anode1100w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1111w = {(w_anode1111w[2] & (~ data_wire[5])), (w_anode1111w[1] & data_wire[4]), (w_anode1111w[0] & (~ data_wire[3])), enable_wire1},
w_anode1122w = {(w_anode1122w[2] & (~ w_data910w[2])), (w_anode1122w[1] & (~ w_data910w[1])), (w_anode1122w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1133w = {(w_anode1133w[2] & (~ w_data910w[2])), (w_anode1133w[1] & (~ w_data910w[1])), (w_anode1133w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1143w = {(w_anode1143w[2] & (~ w_data910w[2])), (w_anode1143w[1] & w_data910w[1]), (w_anode1143w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1153w = {(w_anode1153w[2] & (~ w_data910w[2])), (w_anode1153w[1] & w_data910w[1]), (w_anode1153w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1163w = {(w_anode1163w[2] & w_data910w[2]), (w_anode1163w[1] & (~ w_data910w[1])), (w_anode1163w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1173w = {(w_anode1173w[2] & w_data910w[2]), (w_anode1173w[1] & (~ w_data910w[1])), (w_anode1173w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1183w = {(w_anode1183w[2] & w_data910w[2]), (w_anode1183w[1] & w_data910w[1]), (w_anode1183w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1193w = {(w_anode1193w[2] & w_data910w[2]), (w_anode1193w[1] & w_data910w[1]), (w_anode1193w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1204w = {(w_anode1204w[2] & (~ data_wire[5])), (w_anode1204w[1] & data_wire[4]), (w_anode1204w[0] & data_wire[3]), enable_wire1},
w_anode1215w = {(w_anode1215w[2] & (~ w_data910w[2])), (w_anode1215w[1] & (~ w_data910w[1])), (w_anode1215w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1226w = {(w_anode1226w[2] & (~ w_data910w[2])), (w_anode1226w[1] & (~ w_data910w[1])), (w_anode1226w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1236w = {(w_anode1236w[2] & (~ w_data910w[2])), (w_anode1236w[1] & w_data910w[1]), (w_anode1236w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1246w = {(w_anode1246w[2] & (~ w_data910w[2])), (w_anode1246w[1] & w_data910w[1]), (w_anode1246w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1256w = {(w_anode1256w[2] & w_data910w[2]), (w_anode1256w[1] & (~ w_data910w[1])), (w_anode1256w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1266w = {(w_anode1266w[2] & w_data910w[2]), (w_anode1266w[1] & (~ w_data910w[1])), (w_anode1266w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1276w = {(w_anode1276w[2] & w_data910w[2]), (w_anode1276w[1] & w_data910w[1]), (w_anode1276w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1286w = {(w_anode1286w[2] & w_data910w[2]), (w_anode1286w[1] & w_data910w[1]), (w_anode1286w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1297w = {(w_anode1297w[2] & data_wire[5]), (w_anode1297w[1] & (~ data_wire[4])), (w_anode1297w[0] & (~ data_wire[3])), enable_wire1},
w_anode1308w = {(w_anode1308w[2] & (~ w_data910w[2])), (w_anode1308w[1] & (~ w_data910w[1])), (w_anode1308w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1319w = {(w_anode1319w[2] & (~ w_data910w[2])), (w_anode1319w[1] & (~ w_data910w[1])), (w_anode1319w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1329w = {(w_anode1329w[2] & (~ w_data910w[2])), (w_anode1329w[1] & w_data910w[1]), (w_anode1329w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1339w = {(w_anode1339w[2] & (~ w_data910w[2])), (w_anode1339w[1] & w_data910w[1]), (w_anode1339w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1349w = {(w_anode1349w[2] & w_data910w[2]), (w_anode1349w[1] & (~ w_data910w[1])), (w_anode1349w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1359w = {(w_anode1359w[2] & w_data910w[2]), (w_anode1359w[1] & (~ w_data910w[1])), (w_anode1359w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1369w = {(w_anode1369w[2] & w_data910w[2]), (w_anode1369w[1] & w_data910w[1]), (w_anode1369w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1379w = {(w_anode1379w[2] & w_data910w[2]), (w_anode1379w[1] & w_data910w[1]), (w_anode1379w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1390w = {(w_anode1390w[2] & data_wire[5]), (w_anode1390w[1] & (~ data_wire[4])), (w_anode1390w[0] & data_wire[3]), enable_wire1},
w_anode1401w = {(w_anode1401w[2] & (~ w_data910w[2])), (w_anode1401w[1] & (~ w_data910w[1])), (w_anode1401w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1412w = {(w_anode1412w[2] & (~ w_data910w[2])), (w_anode1412w[1] & (~ w_data910w[1])), (w_anode1412w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1422w = {(w_anode1422w[2] & (~ w_data910w[2])), (w_anode1422w[1] & w_data910w[1]), (w_anode1422w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1432w = {(w_anode1432w[2] & (~ w_data910w[2])), (w_anode1432w[1] & w_data910w[1]), (w_anode1432w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1442w = {(w_anode1442w[2] & w_data910w[2]), (w_anode1442w[1] & (~ w_data910w[1])), (w_anode1442w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1452w = {(w_anode1452w[2] & w_data910w[2]), (w_anode1452w[1] & (~ w_data910w[1])), (w_anode1452w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1462w = {(w_anode1462w[2] & w_data910w[2]), (w_anode1462w[1] & w_data910w[1]), (w_anode1462w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1472w = {(w_anode1472w[2] & w_data910w[2]), (w_anode1472w[1] & w_data910w[1]), (w_anode1472w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1483w = {(w_anode1483w[2] & data_wire[5]), (w_anode1483w[1] & data_wire[4]), (w_anode1483w[0] & (~ data_wire[3])), enable_wire1},
w_anode1494w = {(w_anode1494w[2] & (~ w_data910w[2])), (w_anode1494w[1] & (~ w_data910w[1])), (w_anode1494w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1505w = {(w_anode1505w[2] & (~ w_data910w[2])), (w_anode1505w[1] & (~ w_data910w[1])), (w_anode1505w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1515w = {(w_anode1515w[2] & (~ w_data910w[2])), (w_anode1515w[1] & w_data910w[1]), (w_anode1515w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1525w = {(w_anode1525w[2] & (~ w_data910w[2])), (w_anode1525w[1] & w_data910w[1]), (w_anode1525w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1535w = {(w_anode1535w[2] & w_data910w[2]), (w_anode1535w[1] & (~ w_data910w[1])), (w_anode1535w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1545w = {(w_anode1545w[2] & w_data910w[2]), (w_anode1545w[1] & (~ w_data910w[1])), (w_anode1545w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1555w = {(w_anode1555w[2] & w_data910w[2]), (w_anode1555w[1] & w_data910w[1]), (w_anode1555w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1565w = {(w_anode1565w[2] & w_data910w[2]), (w_anode1565w[1] & w_data910w[1]), (w_anode1565w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1576w = {(w_anode1576w[2] & data_wire[5]), (w_anode1576w[1] & data_wire[4]), (w_anode1576w[0] & data_wire[3]), enable_wire1},
w_anode1587w = {(w_anode1587w[2] & (~ w_data910w[2])), (w_anode1587w[1] & (~ w_data910w[1])), (w_anode1587w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1598w = {(w_anode1598w[2] & (~ w_data910w[2])), (w_anode1598w[1] & (~ w_data910w[1])), (w_anode1598w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1608w = {(w_anode1608w[2] & (~ w_data910w[2])), (w_anode1608w[1] & w_data910w[1]), (w_anode1608w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1618w = {(w_anode1618w[2] & (~ w_data910w[2])), (w_anode1618w[1] & w_data910w[1]), (w_anode1618w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1628w = {(w_anode1628w[2] & w_data910w[2]), (w_anode1628w[1] & (~ w_data910w[1])), (w_anode1628w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1638w = {(w_anode1638w[2] & w_data910w[2]), (w_anode1638w[1] & (~ w_data910w[1])), (w_anode1638w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1648w = {(w_anode1648w[2] & w_data910w[2]), (w_anode1648w[1] & w_data910w[1]), (w_anode1648w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1658w = {(w_anode1658w[2] & w_data910w[2]), (w_anode1658w[1] & w_data910w[1]), (w_anode1658w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1670w = {(w_anode1670w[2] & (~ data_wire[5])), (w_anode1670w[1] & (~ data_wire[4])), (w_anode1670w[0] & (~ data_wire[3])), enable_wire2},
w_anode1681w = {(w_anode1681w[2] & (~ w_data1669w[2])), (w_anode1681w[1] & (~ w_data1669w[1])), (w_anode1681w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1698w = {(w_anode1698w[2] & (~ w_data1669w[2])), (w_anode1698w[1] & (~ w_data1669w[1])), (w_anode1698w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1708w = {(w_anode1708w[2] & (~ w_data1669w[2])), (w_anode1708w[1] & w_data1669w[1]), (w_anode1708w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1718w = {(w_anode1718w[2] & (~ w_data1669w[2])), (w_anode1718w[1] & w_data1669w[1]), (w_anode1718w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1728w = {(w_anode1728w[2] & w_data1669w[2]), (w_anode1728w[1] & (~ w_data1669w[1])), (w_anode1728w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1738w = {(w_anode1738w[2] & w_data1669w[2]), (w_anode1738w[1] & (~ w_data1669w[1])), (w_anode1738w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1748w = {(w_anode1748w[2] & w_data1669w[2]), (w_anode1748w[1] & w_data1669w[1]), (w_anode1748w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1758w = {(w_anode1758w[2] & w_data1669w[2]), (w_anode1758w[1] & w_data1669w[1]), (w_anode1758w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1770w = {(w_anode1770w[2] & (~ data_wire[5])), (w_anode1770w[1] & (~ data_wire[4])), (w_anode1770w[0] & data_wire[3]), enable_wire2},
w_anode1781w = {(w_anode1781w[2] & (~ w_data1669w[2])), (w_anode1781w[1] & (~ w_data1669w[1])), (w_anode1781w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1792w = {(w_anode1792w[2] & (~ w_data1669w[2])), (w_anode1792w[1] & (~ w_data1669w[1])), (w_anode1792w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1802w = {(w_anode1802w[2] & (~ w_data1669w[2])), (w_anode1802w[1] & w_data1669w[1]), (w_anode1802w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1812w = {(w_anode1812w[2] & (~ w_data1669w[2])), (w_anode1812w[1] & w_data1669w[1]), (w_anode1812w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1822w = {(w_anode1822w[2] & w_data1669w[2]), (w_anode1822w[1] & (~ w_data1669w[1])), (w_anode1822w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1832w = {(w_anode1832w[2] & w_data1669w[2]), (w_anode1832w[1] & (~ w_data1669w[1])), (w_anode1832w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1842w = {(w_anode1842w[2] & w_data1669w[2]), (w_anode1842w[1] & w_data1669w[1]), (w_anode1842w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1852w = {(w_anode1852w[2] & w_data1669w[2]), (w_anode1852w[1] & w_data1669w[1]), (w_anode1852w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1863w = {(w_anode1863w[2] & (~ data_wire[5])), (w_anode1863w[1] & data_wire[4]), (w_anode1863w[0] & (~ data_wire[3])), enable_wire2},
w_anode1874w = {(w_anode1874w[2] & (~ w_data1669w[2])), (w_anode1874w[1] & (~ w_data1669w[1])), (w_anode1874w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1885w = {(w_anode1885w[2] & (~ w_data1669w[2])), (w_anode1885w[1] & (~ w_data1669w[1])), (w_anode1885w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1895w = {(w_anode1895w[2] & (~ w_data1669w[2])), (w_anode1895w[1] & w_data1669w[1]), (w_anode1895w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1905w = {(w_anode1905w[2] & (~ w_data1669w[2])), (w_anode1905w[1] & w_data1669w[1]), (w_anode1905w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1915w = {(w_anode1915w[2] & w_data1669w[2]), (w_anode1915w[1] & (~ w_data1669w[1])), (w_anode1915w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1925w = {(w_anode1925w[2] & w_data1669w[2]), (w_anode1925w[1] & (~ w_data1669w[1])), (w_anode1925w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1935w = {(w_anode1935w[2] & w_data1669w[2]), (w_anode1935w[1] & w_data1669w[1]), (w_anode1935w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1945w = {(w_anode1945w[2] & w_data1669w[2]), (w_anode1945w[1] & w_data1669w[1]), (w_anode1945w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1956w = {(w_anode1956w[2] & (~ data_wire[5])), (w_anode1956w[1] & data_wire[4]), (w_anode1956w[0] & data_wire[3]), enable_wire2},
w_anode1967w = {(w_anode1967w[2] & (~ w_data1669w[2])), (w_anode1967w[1] & (~ w_data1669w[1])), (w_anode1967w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode1978w = {(w_anode1978w[2] & (~ w_data1669w[2])), (w_anode1978w[1] & (~ w_data1669w[1])), (w_anode1978w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode1988w = {(w_anode1988w[2] & (~ w_data1669w[2])), (w_anode1988w[1] & w_data1669w[1]), (w_anode1988w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode1998w = {(w_anode1998w[2] & (~ w_data1669w[2])), (w_anode1998w[1] & w_data1669w[1]), (w_anode1998w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode2008w = {(w_anode2008w[2] & w_data1669w[2]), (w_anode2008w[1] & (~ w_data1669w[1])), (w_anode2008w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode2018w = {(w_anode2018w[2] & w_data1669w[2]), (w_anode2018w[1] & (~ w_data1669w[1])), (w_anode2018w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode2028w = {(w_anode2028w[2] & w_data1669w[2]), (w_anode2028w[1] & w_data1669w[1]), (w_anode2028w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode2038w = {(w_anode2038w[2] & w_data1669w[2]), (w_anode2038w[1] & w_data1669w[1]), (w_anode2038w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode2049w = {(w_anode2049w[2] & data_wire[5]), (w_anode2049w[1] & (~ data_wire[4])), (w_anode2049w[0] & (~ data_wire[3])), enable_wire2},
w_anode2060w = {(w_anode2060w[2] & (~ w_data1669w[2])), (w_anode2060w[1] & (~ w_data1669w[1])), (w_anode2060w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2071w = {(w_anode2071w[2] & (~ w_data1669w[2])), (w_anode2071w[1] & (~ w_data1669w[1])), (w_anode2071w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2081w = {(w_anode2081w[2] & (~ w_data1669w[2])), (w_anode2081w[1] & w_data1669w[1]), (w_anode2081w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2091w = {(w_anode2091w[2] & (~ w_data1669w[2])), (w_anode2091w[1] & w_data1669w[1]), (w_anode2091w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2101w = {(w_anode2101w[2] & w_data1669w[2]), (w_anode2101w[1] & (~ w_data1669w[1])), (w_anode2101w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2111w = {(w_anode2111w[2] & w_data1669w[2]), (w_anode2111w[1] & (~ w_data1669w[1])), (w_anode2111w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2121w = {(w_anode2121w[2] & w_data1669w[2]), (w_anode2121w[1] & w_data1669w[1]), (w_anode2121w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2131w = {(w_anode2131w[2] & w_data1669w[2]), (w_anode2131w[1] & w_data1669w[1]), (w_anode2131w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2142w = {(w_anode2142w[2] & data_wire[5]), (w_anode2142w[1] & (~ data_wire[4])), (w_anode2142w[0] & data_wire[3]), enable_wire2},
w_anode2153w = {(w_anode2153w[2] & (~ w_data1669w[2])), (w_anode2153w[1] & (~ w_data1669w[1])), (w_anode2153w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2164w = {(w_anode2164w[2] & (~ w_data1669w[2])), (w_anode2164w[1] & (~ w_data1669w[1])), (w_anode2164w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2174w = {(w_anode2174w[2] & (~ w_data1669w[2])), (w_anode2174w[1] & w_data1669w[1]), (w_anode2174w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2184w = {(w_anode2184w[2] & (~ w_data1669w[2])), (w_anode2184w[1] & w_data1669w[1]), (w_anode2184w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2194w = {(w_anode2194w[2] & w_data1669w[2]), (w_anode2194w[1] & (~ w_data1669w[1])), (w_anode2194w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2204w = {(w_anode2204w[2] & w_data1669w[2]), (w_anode2204w[1] & (~ w_data1669w[1])), (w_anode2204w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2214w = {(w_anode2214w[2] & w_data1669w[2]), (w_anode2214w[1] & w_data1669w[1]), (w_anode2214w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2224w = {(w_anode2224w[2] & w_data1669w[2]), (w_anode2224w[1] & w_data1669w[1]), (w_anode2224w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2235w = {(w_anode2235w[2] & data_wire[5]), (w_anode2235w[1] & data_wire[4]), (w_anode2235w[0] & (~ data_wire[3])), enable_wire2},
w_anode2246w = {(w_anode2246w[2] & (~ w_data1669w[2])), (w_anode2246w[1] & (~ w_data1669w[1])), (w_anode2246w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2257w = {(w_anode2257w[2] & (~ w_data1669w[2])), (w_anode2257w[1] & (~ w_data1669w[1])), (w_anode2257w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2267w = {(w_anode2267w[2] & (~ w_data1669w[2])), (w_anode2267w[1] & w_data1669w[1]), (w_anode2267w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2277w = {(w_anode2277w[2] & (~ w_data1669w[2])), (w_anode2277w[1] & w_data1669w[1]), (w_anode2277w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2287w = {(w_anode2287w[2] & w_data1669w[2]), (w_anode2287w[1] & (~ w_data1669w[1])), (w_anode2287w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2297w = {(w_anode2297w[2] & w_data1669w[2]), (w_anode2297w[1] & (~ w_data1669w[1])), (w_anode2297w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2307w = {(w_anode2307w[2] & w_data1669w[2]), (w_anode2307w[1] & w_data1669w[1]), (w_anode2307w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2317w = {(w_anode2317w[2] & w_data1669w[2]), (w_anode2317w[1] & w_data1669w[1]), (w_anode2317w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2328w = {(w_anode2328w[2] & data_wire[5]), (w_anode2328w[1] & data_wire[4]), (w_anode2328w[0] & data_wire[3]), enable_wire2},
w_anode2339w = {(w_anode2339w[2] & (~ w_data1669w[2])), (w_anode2339w[1] & (~ w_data1669w[1])), (w_anode2339w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2350w = {(w_anode2350w[2] & (~ w_data1669w[2])), (w_anode2350w[1] & (~ w_data1669w[1])), (w_anode2350w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode2360w = {(w_anode2360w[2] & (~ w_data1669w[2])), (w_anode2360w[1] & w_data1669w[1]), (w_anode2360w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2370w = {(w_anode2370w[2] & (~ w_data1669w[2])), (w_anode2370w[1] & w_data1669w[1]), (w_anode2370w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode2380w = {(w_anode2380w[2] & w_data1669w[2]), (w_anode2380w[1] & (~ w_data1669w[1])), (w_anode2380w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2390w = {(w_anode2390w[2] & w_data1669w[2]), (w_anode2390w[1] & (~ w_data1669w[1])), (w_anode2390w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode2400w = {(w_anode2400w[2] & w_data1669w[2]), (w_anode2400w[1] & w_data1669w[1]), (w_anode2400w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2410w = {(w_anode2410w[2] & w_data1669w[2]), (w_anode2410w[1] & w_data1669w[1]), (w_anode2410w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode912w = {(w_anode912w[2] & (~ data_wire[5])), (w_anode912w[1] & (~ data_wire[4])), (w_anode912w[0] & (~ data_wire[3])), enable_wire1},
w_anode929w = {(w_anode929w[2] & (~ w_data910w[2])), (w_anode929w[1] & (~ w_data910w[1])), (w_anode929w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_anode946w = {(w_anode946w[2] & (~ w_data910w[2])), (w_anode946w[1] & (~ w_data910w[1])), (w_anode946w[0] & w_data910w[0]), w_anode912w[3]},
w_anode956w = {(w_anode956w[2] & (~ w_data910w[2])), (w_anode956w[1] & w_data910w[1]), (w_anode956w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_anode966w = {(w_anode966w[2] & (~ w_data910w[2])), (w_anode966w[1] & w_data910w[1]), (w_anode966w[0] & w_data910w[0]), w_anode912w[3]},
w_anode976w = {(w_anode976w[2] & w_data910w[2]), (w_anode976w[1] & (~ w_data910w[1])), (w_anode976w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_anode986w = {(w_anode986w[2] & w_data910w[2]), (w_anode986w[1] & (~ w_data910w[1])), (w_anode986w[0] & w_data910w[0]), w_anode912w[3]},
w_anode996w = {(w_anode996w[2] & w_data910w[2]), (w_anode996w[1] & w_data910w[1]), (w_anode996w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_data1669w = data_wire[2:0],
w_data910w = data_wire[2:0];
endmodule //alt_mem_ddrx_ecc_decoder_64_decode
//synthesis_resources = lut 144 mux21 64
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_decoder_64_altecc_decoder
(
data,
err_corrected,
err_detected,
err_fatal,
q) /* synthesis synthesis_clearbox=1 */;
input [71:0] data;
output err_corrected;
output err_detected;
output err_fatal;
output [63:0] q;
wire [127:0] wire_error_bit_decoder_eq;
wire wire_mux21_0_dataout;
wire wire_mux21_1_dataout;
wire wire_mux21_10_dataout;
wire wire_mux21_11_dataout;
wire wire_mux21_12_dataout;
wire wire_mux21_13_dataout;
wire wire_mux21_14_dataout;
wire wire_mux21_15_dataout;
wire wire_mux21_16_dataout;
wire wire_mux21_17_dataout;
wire wire_mux21_18_dataout;
wire wire_mux21_19_dataout;
wire wire_mux21_2_dataout;
wire wire_mux21_20_dataout;
wire wire_mux21_21_dataout;
wire wire_mux21_22_dataout;
wire wire_mux21_23_dataout;
wire wire_mux21_24_dataout;
wire wire_mux21_25_dataout;
wire wire_mux21_26_dataout;
wire wire_mux21_27_dataout;
wire wire_mux21_28_dataout;
wire wire_mux21_29_dataout;
wire wire_mux21_3_dataout;
wire wire_mux21_30_dataout;
wire wire_mux21_31_dataout;
wire wire_mux21_32_dataout;
wire wire_mux21_33_dataout;
wire wire_mux21_34_dataout;
wire wire_mux21_35_dataout;
wire wire_mux21_36_dataout;
wire wire_mux21_37_dataout;
wire wire_mux21_38_dataout;
wire wire_mux21_39_dataout;
wire wire_mux21_4_dataout;
wire wire_mux21_40_dataout;
wire wire_mux21_41_dataout;
wire wire_mux21_42_dataout;
wire wire_mux21_43_dataout;
wire wire_mux21_44_dataout;
wire wire_mux21_45_dataout;
wire wire_mux21_46_dataout;
wire wire_mux21_47_dataout;
wire wire_mux21_48_dataout;
wire wire_mux21_49_dataout;
wire wire_mux21_5_dataout;
wire wire_mux21_50_dataout;
wire wire_mux21_51_dataout;
wire wire_mux21_52_dataout;
wire wire_mux21_53_dataout;
wire wire_mux21_54_dataout;
wire wire_mux21_55_dataout;
wire wire_mux21_56_dataout;
wire wire_mux21_57_dataout;
wire wire_mux21_58_dataout;
wire wire_mux21_59_dataout;
wire wire_mux21_6_dataout;
wire wire_mux21_60_dataout;
wire wire_mux21_61_dataout;
wire wire_mux21_62_dataout;
wire wire_mux21_63_dataout;
wire wire_mux21_7_dataout;
wire wire_mux21_8_dataout;
wire wire_mux21_9_dataout;
wire data_bit;
wire [63:0] data_t;
wire [71:0] data_wire;
wire [127:0] decode_output;
wire err_corrected_wire;
wire err_detected_wire;
wire err_fatal_wire;
wire [35:0] parity_01_wire;
wire [17:0] parity_02_wire;
wire [8:0] parity_03_wire;
wire [3:0] parity_04_wire;
wire [1:0] parity_05_wire;
wire [30:0] parity_06_wire;
wire [6:0] parity_07_wire;
wire parity_bit;
wire [70:0] parity_final_wire;
wire [6:0] parity_t;
wire [63:0] q_wire;
wire syn_bit;
wire syn_e;
wire [5:0] syn_t;
wire [7:0] syndrome;
alt_mem_ddrx_ecc_decoder_64_decode error_bit_decoder
(
.data(syndrome[6:0]),
.eq(wire_error_bit_decoder_eq));
assign wire_mux21_0_dataout = (syndrome[7] == 1'b1) ? (decode_output[3] ^ data_wire[0]) : data_wire[0];
assign wire_mux21_1_dataout = (syndrome[7] == 1'b1) ? (decode_output[5] ^ data_wire[1]) : data_wire[1];
assign wire_mux21_10_dataout = (syndrome[7] == 1'b1) ? (decode_output[15] ^ data_wire[10]) : data_wire[10];
assign wire_mux21_11_dataout = (syndrome[7] == 1'b1) ? (decode_output[17] ^ data_wire[11]) : data_wire[11];
assign wire_mux21_12_dataout = (syndrome[7] == 1'b1) ? (decode_output[18] ^ data_wire[12]) : data_wire[12];
assign wire_mux21_13_dataout = (syndrome[7] == 1'b1) ? (decode_output[19] ^ data_wire[13]) : data_wire[13];
assign wire_mux21_14_dataout = (syndrome[7] == 1'b1) ? (decode_output[20] ^ data_wire[14]) : data_wire[14];
assign wire_mux21_15_dataout = (syndrome[7] == 1'b1) ? (decode_output[21] ^ data_wire[15]) : data_wire[15];
assign wire_mux21_16_dataout = (syndrome[7] == 1'b1) ? (decode_output[22] ^ data_wire[16]) : data_wire[16];
assign wire_mux21_17_dataout = (syndrome[7] == 1'b1) ? (decode_output[23] ^ data_wire[17]) : data_wire[17];
assign wire_mux21_18_dataout = (syndrome[7] == 1'b1) ? (decode_output[24] ^ data_wire[18]) : data_wire[18];
assign wire_mux21_19_dataout = (syndrome[7] == 1'b1) ? (decode_output[25] ^ data_wire[19]) : data_wire[19];
assign wire_mux21_2_dataout = (syndrome[7] == 1'b1) ? (decode_output[6] ^ data_wire[2]) : data_wire[2];
assign wire_mux21_20_dataout = (syndrome[7] == 1'b1) ? (decode_output[26] ^ data_wire[20]) : data_wire[20];
assign wire_mux21_21_dataout = (syndrome[7] == 1'b1) ? (decode_output[27] ^ data_wire[21]) : data_wire[21];
assign wire_mux21_22_dataout = (syndrome[7] == 1'b1) ? (decode_output[28] ^ data_wire[22]) : data_wire[22];
assign wire_mux21_23_dataout = (syndrome[7] == 1'b1) ? (decode_output[29] ^ data_wire[23]) : data_wire[23];
assign wire_mux21_24_dataout = (syndrome[7] == 1'b1) ? (decode_output[30] ^ data_wire[24]) : data_wire[24];
assign wire_mux21_25_dataout = (syndrome[7] == 1'b1) ? (decode_output[31] ^ data_wire[25]) : data_wire[25];
assign wire_mux21_26_dataout = (syndrome[7] == 1'b1) ? (decode_output[33] ^ data_wire[26]) : data_wire[26];
assign wire_mux21_27_dataout = (syndrome[7] == 1'b1) ? (decode_output[34] ^ data_wire[27]) : data_wire[27];
assign wire_mux21_28_dataout = (syndrome[7] == 1'b1) ? (decode_output[35] ^ data_wire[28]) : data_wire[28];
assign wire_mux21_29_dataout = (syndrome[7] == 1'b1) ? (decode_output[36] ^ data_wire[29]) : data_wire[29];
assign wire_mux21_3_dataout = (syndrome[7] == 1'b1) ? (decode_output[7] ^ data_wire[3]) : data_wire[3];
assign wire_mux21_30_dataout = (syndrome[7] == 1'b1) ? (decode_output[37] ^ data_wire[30]) : data_wire[30];
assign wire_mux21_31_dataout = (syndrome[7] == 1'b1) ? (decode_output[38] ^ data_wire[31]) : data_wire[31];
assign wire_mux21_32_dataout = (syndrome[7] == 1'b1) ? (decode_output[39] ^ data_wire[32]) : data_wire[32];
assign wire_mux21_33_dataout = (syndrome[7] == 1'b1) ? (decode_output[40] ^ data_wire[33]) : data_wire[33];
assign wire_mux21_34_dataout = (syndrome[7] == 1'b1) ? (decode_output[41] ^ data_wire[34]) : data_wire[34];
assign wire_mux21_35_dataout = (syndrome[7] == 1'b1) ? (decode_output[42] ^ data_wire[35]) : data_wire[35];
assign wire_mux21_36_dataout = (syndrome[7] == 1'b1) ? (decode_output[43] ^ data_wire[36]) : data_wire[36];
assign wire_mux21_37_dataout = (syndrome[7] == 1'b1) ? (decode_output[44] ^ data_wire[37]) : data_wire[37];
assign wire_mux21_38_dataout = (syndrome[7] == 1'b1) ? (decode_output[45] ^ data_wire[38]) : data_wire[38];
assign wire_mux21_39_dataout = (syndrome[7] == 1'b1) ? (decode_output[46] ^ data_wire[39]) : data_wire[39];
assign wire_mux21_4_dataout = (syndrome[7] == 1'b1) ? (decode_output[9] ^ data_wire[4]) : data_wire[4];
assign wire_mux21_40_dataout = (syndrome[7] == 1'b1) ? (decode_output[47] ^ data_wire[40]) : data_wire[40];
assign wire_mux21_41_dataout = (syndrome[7] == 1'b1) ? (decode_output[48] ^ data_wire[41]) : data_wire[41];
assign wire_mux21_42_dataout = (syndrome[7] == 1'b1) ? (decode_output[49] ^ data_wire[42]) : data_wire[42];
assign wire_mux21_43_dataout = (syndrome[7] == 1'b1) ? (decode_output[50] ^ data_wire[43]) : data_wire[43];
assign wire_mux21_44_dataout = (syndrome[7] == 1'b1) ? (decode_output[51] ^ data_wire[44]) : data_wire[44];
assign wire_mux21_45_dataout = (syndrome[7] == 1'b1) ? (decode_output[52] ^ data_wire[45]) : data_wire[45];
assign wire_mux21_46_dataout = (syndrome[7] == 1'b1) ? (decode_output[53] ^ data_wire[46]) : data_wire[46];
assign wire_mux21_47_dataout = (syndrome[7] == 1'b1) ? (decode_output[54] ^ data_wire[47]) : data_wire[47];
assign wire_mux21_48_dataout = (syndrome[7] == 1'b1) ? (decode_output[55] ^ data_wire[48]) : data_wire[48];
assign wire_mux21_49_dataout = (syndrome[7] == 1'b1) ? (decode_output[56] ^ data_wire[49]) : data_wire[49];
assign wire_mux21_5_dataout = (syndrome[7] == 1'b1) ? (decode_output[10] ^ data_wire[5]) : data_wire[5];
assign wire_mux21_50_dataout = (syndrome[7] == 1'b1) ? (decode_output[57] ^ data_wire[50]) : data_wire[50];
assign wire_mux21_51_dataout = (syndrome[7] == 1'b1) ? (decode_output[58] ^ data_wire[51]) : data_wire[51];
assign wire_mux21_52_dataout = (syndrome[7] == 1'b1) ? (decode_output[59] ^ data_wire[52]) : data_wire[52];
assign wire_mux21_53_dataout = (syndrome[7] == 1'b1) ? (decode_output[60] ^ data_wire[53]) : data_wire[53];
assign wire_mux21_54_dataout = (syndrome[7] == 1'b1) ? (decode_output[61] ^ data_wire[54]) : data_wire[54];
assign wire_mux21_55_dataout = (syndrome[7] == 1'b1) ? (decode_output[62] ^ data_wire[55]) : data_wire[55];
assign wire_mux21_56_dataout = (syndrome[7] == 1'b1) ? (decode_output[63] ^ data_wire[56]) : data_wire[56];
assign wire_mux21_57_dataout = (syndrome[7] == 1'b1) ? (decode_output[65] ^ data_wire[57]) : data_wire[57];
assign wire_mux21_58_dataout = (syndrome[7] == 1'b1) ? (decode_output[66] ^ data_wire[58]) : data_wire[58];
assign wire_mux21_59_dataout = (syndrome[7] == 1'b1) ? (decode_output[67] ^ data_wire[59]) : data_wire[59];
assign wire_mux21_6_dataout = (syndrome[7] == 1'b1) ? (decode_output[11] ^ data_wire[6]) : data_wire[6];
assign wire_mux21_60_dataout = (syndrome[7] == 1'b1) ? (decode_output[68] ^ data_wire[60]) : data_wire[60];
assign wire_mux21_61_dataout = (syndrome[7] == 1'b1) ? (decode_output[69] ^ data_wire[61]) : data_wire[61];
assign wire_mux21_62_dataout = (syndrome[7] == 1'b1) ? (decode_output[70] ^ data_wire[62]) : data_wire[62];
assign wire_mux21_63_dataout = (syndrome[7] == 1'b1) ? (decode_output[71] ^ data_wire[63]) : data_wire[63];
assign wire_mux21_7_dataout = (syndrome[7] == 1'b1) ? (decode_output[12] ^ data_wire[7]) : data_wire[7];
assign wire_mux21_8_dataout = (syndrome[7] == 1'b1) ? (decode_output[13] ^ data_wire[8]) : data_wire[8];
assign wire_mux21_9_dataout = (syndrome[7] == 1'b1) ? (decode_output[14] ^ data_wire[9]) : data_wire[9];
assign
data_bit = data_t[63],
data_t = {(data_t[62] | decode_output[71]), (data_t[61] | decode_output[70]), (data_t[60] | decode_output[69]), (data_t[59] | decode_output[68]), (data_t[58] | decode_output[67]), (data_t[57] | decode_output[66]), (data_t[56] | decode_output[65]), (data_t[55] | decode_output[63]), (data_t[54] | decode_output[62]), (data_t[53] | decode_output[61]), (data_t[52] | decode_output[60]), (data_t[51] | decode_output[59]), (data_t[50] | decode_output[58]), (data_t[49] | decode_output[57]), (data_t[48] | decode_output[56]), (data_t[47] | decode_output[55]), (data_t[46] | decode_output[54]), (data_t[45] | decode_output[53]), (data_t[44] | decode_output[52]), (data_t[43] | decode_output[51]), (data_t[42] | decode_output[50]), (data_t[41] | decode_output[49]), (data_t[40] | decode_output[48]), (data_t[39] | decode_output[47]), (data_t[38] | decode_output[46]), (data_t[37] | decode_output[45]), (data_t[36] | decode_output[44]), (data_t[35] | decode_output[43]), (data_t[34] | decode_output[42]), (data_t[33] | decode_output[41]), (data_t[32] | decode_output[40]), (data_t[31] | decode_output[39]), (data_t[30] | decode_output[38]), (data_t[29] | decode_output[37]), (data_t[28] | decode_output[36]), (data_t[27] | decode_output[35]), (data_t[26] | decode_output[34]), (data_t[25] | decode_output[33]), (data_t[24] | decode_output[31]), (data_t[23] | decode_output[30]), (data_t[22] | decode_output[29]), (data_t[21] | decode_output[28]), (data_t[20] | decode_output[27]), (data_t[19] | decode_output[26]), (data_t[18] | decode_output[25]), (data_t[17] | decode_output[24]), (data_t[16] | decode_output[23]), (data_t[15] | decode_output[22]), (data_t[14] | decode_output[21]), (data_t[13] | decode_output[20]), (data_t[12] | decode_output[19]), (data_t[11] | decode_output[18]), (data_t[10] | decode_output[17]), (data_t[9] | decode_output[15]), (data_t[8] | decode_output[14]), (data_t[7] | decode_output[13]), (data_t[6] | decode_output[12]), (data_t[5] | decode_output[11]), (data_t[4] | decode_output[10]), (data_t[3] | decode_output[9]), (data_t[2]
| decode_output[7]), (data_t[1] | decode_output[6]), (data_t[0] | decode_output[5]), decode_output[3]},
data_wire = data,
decode_output = wire_error_bit_decoder_eq,
err_corrected = err_corrected_wire,
err_corrected_wire = ((syn_bit & syn_e) & data_bit),
err_detected = err_detected_wire,
err_detected_wire = (syn_bit & (~ (syn_e & parity_bit))),
err_fatal = err_fatal_wire,
err_fatal_wire = (err_detected_wire & (~ err_corrected_wire)),
parity_01_wire = {(data_wire[63] ^ parity_01_wire[34]), (data_wire[61] ^ parity_01_wire[33]), (data_wire[59] ^ parity_01_wire[32]), (data_wire[57] ^ parity_01_wire[31]), (data_wire[56] ^ parity_01_wire[30]), (data_wire[54] ^ parity_01_wire[29]), (data_wire[52] ^ parity_01_wire[28]), (data_wire[50] ^ parity_01_wire[27]), (data_wire[48] ^ parity_01_wire[26]), (data_wire[46] ^ parity_01_wire[25]), (data_wire[44] ^ parity_01_wire[24]), (data_wire[42] ^ parity_01_wire[23]), (data_wire[40] ^ parity_01_wire[22]), (data_wire[38] ^ parity_01_wire[21]), (data_wire[36] ^ parity_01_wire[20]), (data_wire[34] ^ parity_01_wire[19]), (data_wire[32] ^ parity_01_wire[18]), (data_wire[30] ^ parity_01_wire[17]), (data_wire[28] ^ parity_01_wire[16]), (data_wire[26] ^ parity_01_wire[15]), (data_wire[25] ^ parity_01_wire[14]), (data_wire[23] ^ parity_01_wire[13]), (data_wire[21] ^ parity_01_wire[12]), (data_wire[19] ^ parity_01_wire[11]), (data_wire[17] ^ parity_01_wire[10]), (data_wire[15] ^ parity_01_wire[9]), (data_wire[13] ^ parity_01_wire[8]), (data_wire[11] ^ parity_01_wire[7]), (data_wire[10] ^ parity_01_wire[6]), (data_wire[8] ^ parity_01_wire[5]), (data_wire[6] ^ parity_01_wire[4]), (data_wire[4] ^ parity_01_wire[3]), (data_wire[3] ^ parity_01_wire[2]), (data_wire[1] ^ parity_01_wire[1]), (data_wire[0] ^ parity_01_wire[0]), data_wire[64]},
parity_02_wire = {((data_wire[62] ^ data_wire[63]) ^ parity_02_wire[16]), ((data_wire[58] ^ data_wire[59]) ^ parity_02_wire[15]), ((data_wire[55] ^ data_wire[56]) ^ parity_02_wire[14]), ((data_wire[51] ^ data_wire[52]) ^ parity_02_wire[13]), ((data_wire[47] ^ data_wire[48]) ^ parity_02_wire[12]), ((data_wire[43] ^ data_wire[44]) ^ parity_02_wire[11]), ((data_wire[39] ^ data_wire[40]) ^ parity_02_wire[10]), ((data_wire[35] ^ data_wire[36]) ^ parity_02_wire[9]), ((data_wire[31] ^ data_wire[32]) ^ parity_02_wire[8]), ((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]), ((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]), ((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]), ((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]), ((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]), ((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]), ((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]), ((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]), (data_wire[65] ^ data_wire[0])},
parity_03_wire = {((((data_wire[60] ^ data_wire[61]) ^ data_wire[62]) ^ data_wire[63]) ^ parity_03_wire[7]), ((((data_wire[53] ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_03_wire[6]), ((((data_wire[45] ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ parity_03_wire[5]), ((((data_wire[37] ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_03_wire[4]), ((((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ data_wire[32]) ^ parity_03_wire[3]), ((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]), ((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]), ((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]), (((data_wire[66] ^ data_wire[1]) ^ data_wire[2]) ^ data_wire[3])},
parity_04_wire = {((((((((data_wire[49] ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_04_wire[2]), ((((((((data_wire[33] ^ data_wire[34]) ^ data_wire[35]) ^ data_wire[36]) ^ data_wire[37]) ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_04_wire[1]), ((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]), (((((((data_wire[67] ^ data_wire[4]) ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])},
parity_05_wire = {((((((((((((((((data_wire[41] ^ data_wire[42]) ^ data_wire[43]) ^ data_wire[44]) ^ data_wire[45]) ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ data_wire[49]) ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_05_wire[0]), (((((((((((((((data_wire[68] ^ data_wire[11]) ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])},
parity_06_wire = {(data_wire[56] ^ parity_06_wire[29]), (data_wire[55] ^ parity_06_wire[28]), (data_wire[54] ^ parity_06_wire[27]), (data_wire[53] ^ parity_06_wire[26]), (data_wire[52] ^ parity_06_wire[25]), (data_wire[51] ^ parity_06_wire[24]), (data_wire[50] ^ parity_06_wire[23]), (data_wire[49] ^ parity_06_wire[22]), (data_wire[48] ^ parity_06_wire[21]), (data_wire[47] ^ parity_06_wire[20]), (data_wire[46] ^ parity_06_wire[19]), (data_wire[45] ^ parity_06_wire[18]), (data_wire[44] ^ parity_06_wire[17]), (data_wire[43] ^ parity_06_wire[16]), (data_wire[42] ^ parity_06_wire[15]), (data_wire[41] ^ parity_06_wire[14]), (data_wire[40] ^ parity_06_wire[13]), (data_wire[39] ^ parity_06_wire[12]), (data_wire[38] ^ parity_06_wire[11]), (data_wire[37] ^ parity_06_wire[10]), (data_wire[36] ^ parity_06_wire[9]), (data_wire[35] ^ parity_06_wire[8]), (data_wire[34] ^ parity_06_wire[7]), (data_wire[33] ^ parity_06_wire[6]), (data_wire[32] ^ parity_06_wire[5]), (data_wire[31] ^ parity_06_wire[4]), (data_wire[30] ^ parity_06_wire[3]), (data_wire[29] ^ parity_06_wire[2]), (data_wire[28] ^ parity_06_wire[1]), (data_wire[27] ^ parity_06_wire[0]), (data_wire[69] ^ data_wire[26])},
parity_07_wire = {(data_wire[63] ^ parity_07_wire[5]), (data_wire[62] ^ parity_07_wire[4]), (data_wire[61] ^ parity_07_wire[3]), (data_wire[60] ^ parity_07_wire[2]), (data_wire[59] ^ parity_07_wire[1]), (data_wire[58] ^ parity_07_wire[0]), (data_wire[70] ^ data_wire[57])},
parity_bit = parity_t[6],
parity_final_wire = {(data_wire[70] ^ parity_final_wire[69]), (data_wire[69] ^ parity_final_wire[68]), (data_wire[68] ^ parity_final_wire[67]), (data_wire[67] ^ parity_final_wire[66]), (data_wire[66] ^ parity_final_wire[65]), (data_wire[65] ^ parity_final_wire[64]), (data_wire[64] ^ parity_final_wire[63]), (data_wire[63] ^ parity_final_wire[62]), (data_wire[62] ^ parity_final_wire[61]), (data_wire[61] ^ parity_final_wire[60]), (data_wire[60] ^ parity_final_wire[59]), (data_wire[59] ^ parity_final_wire[58]), (data_wire[58] ^ parity_final_wire[57]), (data_wire[57] ^ parity_final_wire[56]), (data_wire[56] ^ parity_final_wire[55]), (data_wire[55] ^ parity_final_wire[54]), (data_wire[54] ^ parity_final_wire[53]), (data_wire[53] ^ parity_final_wire[52]), (data_wire[52] ^ parity_final_wire[51]), (data_wire[51] ^ parity_final_wire[50]), (data_wire[50] ^ parity_final_wire[49]), (data_wire[49] ^ parity_final_wire[48]), (data_wire[48] ^ parity_final_wire[47]), (data_wire[47] ^ parity_final_wire[46]), (data_wire[46] ^ parity_final_wire[45]), (data_wire[45] ^ parity_final_wire[44]), (data_wire[44] ^ parity_final_wire[43]), (data_wire[43] ^ parity_final_wire[42]), (data_wire[42] ^ parity_final_wire[41]), (data_wire[41] ^ parity_final_wire[40]), (data_wire[40] ^ parity_final_wire[39]), (data_wire[39] ^ parity_final_wire[38]), (data_wire[38] ^ parity_final_wire[37]), (data_wire[37] ^ parity_final_wire[36]), (data_wire[36] ^ parity_final_wire[35]), (data_wire[35] ^ parity_final_wire[34]), (data_wire[34] ^ parity_final_wire[33]), (data_wire[33] ^ parity_final_wire[32]), (data_wire[32] ^ parity_final_wire[31]), (data_wire[31] ^ parity_final_wire[30]), (data_wire[30] ^ parity_final_wire[29]), (data_wire[29] ^ parity_final_wire[28]), (data_wire[28] ^ parity_final_wire[27]), (data_wire[27] ^ parity_final_wire[26]), (data_wire[26] ^ parity_final_wire[25]), (data_wire[25] ^ parity_final_wire[24]), (data_wire[24] ^ parity_final_wire[23]), (data_wire[23] ^ parity_final_wire[22]), (data_wire[22] ^ parity_final_wire[21]), (data_wire[21] ^
parity_final_wire[20]), (data_wire[20] ^ parity_final_wire[19]), (data_wire[19] ^ parity_final_wire[18]), (data_wire[18] ^ parity_final_wire[17]), (data_wire[17] ^ parity_final_wire[16]), (data_wire[16] ^ parity_final_wire[15]), (data_wire[15] ^ parity_final_wire[14]), (data_wire[14] ^ parity_final_wire[13]), (data_wire[13] ^ parity_final_wire[12]), (data_wire[12] ^ parity_final_wire[11]), (data_wire[11] ^ parity_final_wire[10]), (data_wire[10] ^ parity_final_wire[9]), (data_wire[9] ^ parity_final_wire[8]), (data_wire[8] ^ parity_final_wire[7]), (data_wire[7] ^ parity_final_wire[6]), (data_wire[6] ^ parity_final_wire[5]), (data_wire[5] ^ parity_final_wire[4]), (data_wire[4] ^ parity_final_wire[3]), (data_wire[3] ^ parity_final_wire[2]), (data_wire[2] ^ parity_final_wire[1]), (data_wire[1] ^ parity_final_wire[0]), (data_wire[71] ^ data_wire[0])},
parity_t = {(parity_t[5] | decode_output[64]), (parity_t[4] | decode_output[32]), (parity_t[3] | decode_output[16]), (parity_t[2] | decode_output[8]), (parity_t[1] | decode_output[4]), (parity_t[0] | decode_output[2]), decode_output[1]},
q = q_wire,
q_wire = {wire_mux21_63_dataout, wire_mux21_62_dataout, wire_mux21_61_dataout, wire_mux21_60_dataout, wire_mux21_59_dataout, wire_mux21_58_dataout, wire_mux21_57_dataout, wire_mux21_56_dataout, wire_mux21_55_dataout, wire_mux21_54_dataout, wire_mux21_53_dataout, wire_mux21_52_dataout, wire_mux21_51_dataout, wire_mux21_50_dataout, wire_mux21_49_dataout, wire_mux21_48_dataout, wire_mux21_47_dataout, wire_mux21_46_dataout, wire_mux21_45_dataout, wire_mux21_44_dataout, wire_mux21_43_dataout, wire_mux21_42_dataout, wire_mux21_41_dataout, wire_mux21_40_dataout, wire_mux21_39_dataout, wire_mux21_38_dataout, wire_mux21_37_dataout, wire_mux21_36_dataout, wire_mux21_35_dataout, wire_mux21_34_dataout, wire_mux21_33_dataout, wire_mux21_32_dataout, wire_mux21_31_dataout, wire_mux21_30_dataout, wire_mux21_29_dataout, wire_mux21_28_dataout, wire_mux21_27_dataout, wire_mux21_26_dataout, wire_mux21_25_dataout, wire_mux21_24_dataout, wire_mux21_23_dataout, wire_mux21_22_dataout, wire_mux21_21_dataout, wire_mux21_20_dataout, wire_mux21_19_dataout, wire_mux21_18_dataout, wire_mux21_17_dataout, wire_mux21_16_dataout, wire_mux21_15_dataout, wire_mux21_14_dataout, wire_mux21_13_dataout, wire_mux21_12_dataout, wire_mux21_11_dataout, wire_mux21_10_dataout, wire_mux21_9_dataout, wire_mux21_8_dataout, wire_mux21_7_dataout, wire_mux21_6_dataout, wire_mux21_5_dataout, wire_mux21_4_dataout, wire_mux21_3_dataout, wire_mux21_2_dataout, wire_mux21_1_dataout, wire_mux21_0_dataout},
syn_bit = syn_t[5],
syn_e = syndrome[7],
syn_t = {(syn_t[4] | syndrome[6]), (syn_t[3] | syndrome[5]), (syn_t[2] | syndrome[4]), (syn_t[1] | syndrome[3]), (syn_t[0] | syndrome[2]), (syndrome[0] | syndrome[1])},
syndrome = {parity_final_wire[70], parity_07_wire[6], parity_06_wire[30], parity_05_wire[1], parity_04_wire[3], parity_03_wire[8], parity_02_wire[17], parity_01_wire[35]};
endmodule //alt_mem_ddrx_ecc_decoder_64_altecc_decoder
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_mem_ddrx_ecc_decoder_64 (
data,
err_corrected,
err_detected,
err_fatal,
q)/* synthesis synthesis_clearbox = 1 */;
input [71:0] data;
output err_corrected;
output err_detected;
output err_fatal;
output [63:0] q;
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [63:0] sub_wire3;
wire err_detected = sub_wire0;
wire err_fatal = sub_wire1;
wire err_corrected = sub_wire2;
wire [63:0] q = sub_wire3[63:0];
alt_mem_ddrx_ecc_decoder_64_altecc_decoder alt_mem_ddrx_ecc_decoder_64_altecc_decoder_component (
.data (data),
.err_detected (sub_wire0),
.err_fatal (sub_wire1),
.err_corrected (sub_wire2),
.q (sub_wire3));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: lpm_pipeline NUMERIC "0"
// Retrieval info: CONSTANT: width_codeword NUMERIC "72"
// Retrieval info: CONSTANT: width_dataword NUMERIC "64"
// Retrieval info: USED_PORT: data 0 0 72 0 INPUT NODEFVAL "data[71..0]"
// Retrieval info: USED_PORT: err_corrected 0 0 0 0 OUTPUT NODEFVAL "err_corrected"
// Retrieval info: USED_PORT: err_detected 0 0 0 0 OUTPUT NODEFVAL "err_detected"
// Retrieval info: USED_PORT: err_fatal 0 0 0 0 OUTPUT NODEFVAL "err_fatal"
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]"
// Retrieval info: CONNECT: @data 0 0 72 0 data 0 0 72 0
// Retrieval info: CONNECT: err_corrected 0 0 0 0 @err_corrected 0 0 0 0
// Retrieval info: CONNECT: err_detected 0 0 0 0 @err_detected 0 0 0 0
// Retrieval info: CONNECT: err_fatal 0 0 0 0 @err_fatal 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_syn.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64_syn.v TRUE
// Retrieval info: LIB_FILE: lpm
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKBUF_4_V
`define SKY130_FD_SC_HDLL__CLKBUF_4_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkbuf_4 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkbuf_4 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKBUF_4_V
|
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
/*
This logic recieves Avalon Memory Mapped read data and translates it into
the Avalon Streaming format. The ST format requires all data to be packed
until the final transfer when packet support is enabled. As a result when
you enable unaligned acceses the data from two sucessive reads must be
combined to form a single word of data. If you disable packet support
and unaligned access support this block will synthesize into wires.
This block does not provide any read throttling as it simply acts as a format
adapter between the read master port and the read master FIFO. All throttling
should be provided by the read master to prevent overflow. Since this logic
sits on the MM side of the FIFO the bytes are in 'little endian' format and
will get swapped around on the other side of the FIFO (symbol size can be adjusted
there too).
Revision History:
1.0 Initial version
2.0 Removed 'bytes_to_next_boundary' and using the address and length signals
instead to determine how much out of alignment the master begins.
2.1 Changed the extra last access logic to be based on the descriptor address
and length as apposed to the counter values. Created a new 'length_counter'
input to determine when the last read has arrived.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module MM_to_ST_Adapter (
clk,
reset,
length,
length_counter,
address,
reads_pending,
start,
readdata,
readdatavalid,
fifo_data,
fifo_write,
fifo_empty,
fifo_sop,
fifo_eop
);
parameter DATA_WIDTH = 32; // 8, 16, 32, 64, 128, or 256 are valid values (if 8 is used then disable unaligned accesses and turn on full word only accesses)
parameter LENGTH_WIDTH = 32;
parameter ADDRESS_WIDTH = 32;
parameter BYTE_ADDRESS_WIDTH = 2; // log2(DATA_WIDTH/8)
parameter READS_PENDING_WIDTH = 5;
parameter EMPTY_WIDTH = 2; // log2(DATA_WIDTH/8)
parameter PACKET_SUPPORT = 1; // when set to 1 eop, sop, and empty will be driven, otherwise they will be grounded
// only set one of these at a time
parameter UNALIGNED_ACCESS_ENABLE = 1; // when set to 1 this block will support packets and starting/ending on any boundary, do not use this if DATA_WIDTH is 8 (use 'FULL_WORD_ACCESS_ONLY')
parameter FULL_WORD_ACCESS_ONLY = 0; // when set to 1 this block will assume only full words are arriving (must start and stop on a word boundary).
input clk;
input reset;
input [LENGTH_WIDTH-1:0] length;
input [LENGTH_WIDTH-1:0] length_counter;
input [ADDRESS_WIDTH-1:0] address;
input [READS_PENDING_WIDTH-1:0] reads_pending;
input start; // one cycle strobe at the start of a transfer used to capture bytes_to_transfer
input [DATA_WIDTH-1:0] readdata;
input readdatavalid;
output wire [DATA_WIDTH-1:0] fifo_data;
output wire fifo_write;
output wire [EMPTY_WIDTH-1:0] fifo_empty;
output wire fifo_sop;
output wire fifo_eop;
// internal registers and wires
reg [DATA_WIDTH-1:0] readdata_d1;
reg readdatavalid_d1;
wire [DATA_WIDTH-1:0] data_in; // data_in will either be readdata or a pipelined copy of readdata depending on whether unaligned access support is enabled
wire valid_in; // valid in will either be readdatavalid or a pipelined copy of readdatavalid depending on whether unaligned access support is enabled
reg valid_in_d1;
wire [DATA_WIDTH-1:0] barrelshifter_A; // shifted current read data
wire [DATA_WIDTH-1:0] barrelshifter_B;
reg [DATA_WIDTH-1:0] barrelshifter_B_d1; // shifted previously read data
wire [DATA_WIDTH-1:0] combined_word; // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap)
wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_A inputs
wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_B inputs
wire extra_access_enable;
reg extra_access;
wire last_unaligned_fifo_write;
reg first_access_seen;
reg second_access_seen;
wire first_access_seen_rising_edge;
wire second_access_seen_rising_edge;
reg [BYTE_ADDRESS_WIDTH-1:0] byte_address;
reg [EMPTY_WIDTH-1:0] last_empty; // only the last word written into the FIFO can have empty bytes
reg start_and_end_same_cycle; // when the amount of data to transfer is only a full word or less
generate
if (UNALIGNED_ACCESS_ENABLE == 1) // unaligned so using a pipelined input
begin
assign data_in = readdata_d1;
assign valid_in = readdatavalid_d1;
end
else
begin
assign data_in = readdata; // no barrelshifters in this case so pipelining is not necessary
assign valid_in = readdatavalid;
end
endgenerate
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
readdata_d1 <= 0;
end
else
begin
if (readdatavalid == 1)
begin
readdata_d1 <= readdata;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
readdatavalid_d1 <= 0;
valid_in_d1 <= 0;
end
else
begin
readdatavalid_d1 <= readdatavalid;
valid_in_d1 <= valid_in; // used to flush the pipeline (extra fifo write) and prolong eop for one additional clock cycle
end
end
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
barrelshifter_B_d1 <= 0;
end
else
begin
if (valid_in == 1)
begin
barrelshifter_B_d1 <= barrelshifter_B;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
first_access_seen <= 0;
end
else
begin
if (start == 1)
begin
first_access_seen <= 0;
end
else if (valid_in == 1)
begin
first_access_seen <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
second_access_seen <= 0;
end
else
begin
if (start == 1)
begin
second_access_seen <= 0;
end
else if ((first_access_seen == 1) & (valid_in == 1))
begin
second_access_seen <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
byte_address <= 0;
end
else if (start == 1)
begin
byte_address <= address[BYTE_ADDRESS_WIDTH-1:0];
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
last_empty <= 0;
end
else if (start == 1)
begin
last_empty <= ((DATA_WIDTH/8) - length[EMPTY_WIDTH-1:0]) & {EMPTY_WIDTH{1'b1}}; // if length isn't a multiple of the word size then we'll have some empty symbols/bytes during the last fifo write
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
extra_access <= 0;
end
else if (start == 1)
begin
extra_access <= extra_access_enable; // when set the number of reads and fifo writes are equal, otherwise there will be 1 less fifo write than reads (unaligned accesses only)
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
start_and_end_same_cycle <= 0;
end
else if (start == 1)
begin
start_and_end_same_cycle <= (length <= (DATA_WIDTH/8));
end
end
/* These barrelshifters will take the unaligned data coming into this block and shift the byte lanes appropriately to form a single packed word.
Zeros are shifted into the byte lanes that do not contain valid data for the combined word that will be buffered. This allows both barrelshifters
to be logically OR'ed together to form a single packed word. Shifter A is used to shift the current read data towards the upper bytes of the
combined word (since those are the upper addresses of the combined word). Shifter B after the pipeline stage called 'barrelshifter_B_d1' contains
the previously read data shifted towards the lower bytes (since those are the lower addresses of the combined word).
*/
generate
genvar input_offset;
for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1)
begin: barrel_shifter_inputs
assign barrelshifter_input_A[input_offset] = data_in << (8 * ((DATA_WIDTH/8) - input_offset));
assign barrelshifter_input_B[input_offset] = data_in >> (8 * input_offset);
end
endgenerate
assign barrelshifter_A = barrelshifter_input_A[byte_address]; // upper portion of the packed word
assign barrelshifter_B = barrelshifter_input_B[byte_address]; // lower portion of the packed word (will be pipelined so it will be the previous word read by the master)
assign combined_word = (barrelshifter_A | barrelshifter_B_d1); // barrelshifters shift in zeros so we can just OR the words together here to create a packed word
assign first_access_seen_rising_edge = (valid_in == 1) & (first_access_seen == 0);
assign second_access_seen_rising_edge = ((first_access_seen == 1) & (valid_in == 1)) & (second_access_seen == 0);
assign extra_access_enable = (((DATA_WIDTH/8) - length[EMPTY_WIDTH-1:0]) & {EMPTY_WIDTH{1'b1}}) >= address[BYTE_ADDRESS_WIDTH-1:0]; // enable when empty >= byte address
/* Need to keep track of the last write to the FIFO so that we can fire EOP correctly as well as flush the pipeline when unaligned accesses
is enabled. The first read is filtered since it is considered to be only a partial word to be written into the FIFO but there are cases
when there is extra data that is buffered in 'barrelshifter_B_d1' but the transfer is done so we need to issue an additional write.
In general for every 'N' Avalon-MM reads 'N-1' writes to the FIFO will occur unless there is data still buffered in which one more write
to the FIFO will immediately follow the last read.
*/
assign last_unaligned_fifo_write = (reads_pending == 0) & (length_counter == 0) &
( ((extra_access == 0) & (valid_in == 1)) | // don't need a pipeline flush
((extra_access == 1) & (valid_in_d1 == 1) & (valid_in == 0)) ); // last write to flush the pipeline (need to make sure valid_in isn't asserted to make sure the last data is indeed coming since valid_in is pipelined)
// This block should be optimized down depending on the packet support or access type settings. In the case where packet support is off
// and only full accesses are used this block should become zero logic elements.
generate
if (PACKET_SUPPORT == 1)
begin
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_sop = (second_access_seen_rising_edge == 1) | ((start_and_end_same_cycle == 1) & (last_unaligned_fifo_write == 1));
assign fifo_eop = last_unaligned_fifo_write;
assign fifo_empty = (fifo_eop == 1)? last_empty : 0; // always full accesses until the last word
end
else
begin
assign fifo_sop = first_access_seen_rising_edge;
assign fifo_eop = (length_counter == 0) & (reads_pending == 1) & (valid_in == 1); // not using last_unaligned_fifo_write since it's pipelined and when unaligned accesses are disabled the input is not pipelined
if (FULL_WORD_ACCESS_ONLY == 1)
begin
assign fifo_empty = 0; // full accesses so no empty symbols throughout the transfer
end
else
begin
assign fifo_empty = (fifo_eop == 1)? last_empty : 0; // always full accesses until the last word
end
end
end
else
begin
assign fifo_eop = 0;
assign fifo_sop = 0;
assign fifo_empty = 0;
end
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_data = combined_word;
assign fifo_write = (first_access_seen == 1) & ((valid_in == 1) | (last_unaligned_fifo_write == 1)); // last_unaligned_fifo_write will inject an extra pulse right after the last read occurs when flushing of the pipeline is needed
end
else
begin // don't need to pipeline since the data will not go through the barrel shifters
assign fifo_data = data_in; // don't need to barrelshift when aligned accesses are used
assign fifo_write = valid_in; // the number of writes to the fifo needs to always equal the number of reads from memory
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module altera_mem_if_ddr3_phy_0001_altdqdqs (
core_clock_in,
reset_n_core_clock_in,
fr_clock_in,
hr_clock_in,
write_strobe_clock_in,
strobe_ena_hr_clock_in,
strobe_ena_clock_in,
capture_strobe_ena,
read_write_data_io,
write_oe_in,
strobe_io,
output_strobe_ena,
strobe_n_io,
oct_ena_in,
read_data_out,
capture_strobe_out,
write_data_in,
extra_write_data_in,
extra_write_data_out,
parallelterminationcontrol_in,
seriesterminationcontrol_in,
config_data_in,
config_update,
config_dqs_ena,
config_io_ena,
config_extra_io_ena,
config_dqs_io_ena,
config_clock_in,
dll_delayctrl_in
);
input [6-1:0] dll_delayctrl_in;
input core_clock_in;
input reset_n_core_clock_in;
input fr_clock_in;
input hr_clock_in;
input write_strobe_clock_in;
input strobe_ena_hr_clock_in;
input strobe_ena_clock_in;
input [2-1:0] capture_strobe_ena;
inout [8-1:0] read_write_data_io;
input [2*8-1:0] write_oe_in;
inout strobe_io;
input [2-1:0] output_strobe_ena;
inout strobe_n_io;
input [2-1:0] oct_ena_in;
output [2 * 1 * 8-1:0] read_data_out;
output capture_strobe_out;
input [2 * 2 * 8-1:0] write_data_in;
input [2 * 2 * 1-1:0] extra_write_data_in;
output [1-1:0] extra_write_data_out;
input [14-1:0] parallelterminationcontrol_in;
input [14-1:0] seriesterminationcontrol_in;
input config_data_in;
input config_update;
input config_dqs_ena;
input [8-1:0] config_io_ena;
input [1-1:0] config_extra_io_ena;
input config_dqs_io_ena;
input config_clock_in;
`ifndef ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL
`define ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL 1
`endif
parameter ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = `ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL;
generate
if (ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL)
begin
altdq_dqs2_abstract altdq_dqs2_inst (
.core_clock_in( core_clock_in),
.reset_n_core_clock_in (reset_n_core_clock_in),
.fr_clock_in( fr_clock_in),
.hr_clock_in( hr_clock_in),
.write_strobe_clock_in (write_strobe_clock_in),
.strobe_ena_hr_clock_in( strobe_ena_hr_clock_in),
.strobe_ena_clock_in( strobe_ena_clock_in),
.capture_strobe_ena( capture_strobe_ena),
.read_write_data_io( read_write_data_io),
.write_oe_in( write_oe_in),
.strobe_io( strobe_io),
.output_strobe_ena( output_strobe_ena),
.strobe_n_io( strobe_n_io),
.oct_ena_in( oct_ena_in),
.read_data_out( read_data_out),
.capture_strobe_out( capture_strobe_out),
.write_data_in( write_data_in),
.extra_write_data_in( extra_write_data_in),
.extra_write_data_out( extra_write_data_out),
.parallelterminationcontrol_in( parallelterminationcontrol_in),
.seriesterminationcontrol_in( seriesterminationcontrol_in),
.config_data_in( config_data_in),
.config_update( config_update),
.config_dqs_ena( config_dqs_ena),
.config_io_ena( config_io_ena),
.config_extra_io_ena( config_extra_io_ena),
.config_dqs_io_ena( config_dqs_io_ena),
.config_clock_in( config_clock_in),
.dll_delayctrl_in(dll_delayctrl_in)
);
defparam altdq_dqs2_inst.PIN_WIDTH = 8;
defparam altdq_dqs2_inst.PIN_TYPE = "bidir";
defparam altdq_dqs2_inst.USE_INPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_OUTPUT_PHASE_ALIGNMENT = "true";
defparam altdq_dqs2_inst.USE_LDC_AS_LOW_SKEW_CLOCK = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_INPUT = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_OUTPUT = "true";
defparam altdq_dqs2_inst.DIFFERENTIAL_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SEPARATE_CAPTURE_STROBE = "false";
defparam altdq_dqs2_inst.INPUT_FREQ = 533;
defparam altdq_dqs2_inst.INPUT_FREQ_PS = "1876 ps";
defparam altdq_dqs2_inst.DELAY_CHAIN_BUFFER_MODE = "HIGH";
defparam altdq_dqs2_inst.DQS_PHASE_SETTING = 2;
defparam altdq_dqs2_inst.DQS_PHASE_SHIFT = 9000;
defparam altdq_dqs2_inst.DQS_ENABLE_PHASE_SETTING = 0;
defparam altdq_dqs2_inst.USE_DYNAMIC_CONFIG = "true";
defparam altdq_dqs2_inst.INVERT_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.USE_TERMINATION_CONTROL = "true";
defparam altdq_dqs2_inst.USE_DQS_ENABLE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE_RESET = "false";
defparam altdq_dqs2_inst.DIFFERENTIAL_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_BIDIR_STROBE = "true";
defparam altdq_dqs2_inst.REVERSE_READ_WORDS = "false";
defparam altdq_dqs2_inst.EXTRA_OUTPUT_WIDTH = 1;
defparam altdq_dqs2_inst.DYNAMIC_MODE = "dynamic";
defparam altdq_dqs2_inst.OCT_SERIES_TERM_CONTROL_WIDTH = 14;
defparam altdq_dqs2_inst.OCT_PARALLEL_TERM_CONTROL_WIDTH = 14;
defparam altdq_dqs2_inst.DLL_WIDTH = 6;
defparam altdq_dqs2_inst.USE_DATA_OE_FOR_OCT = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_WIDTH = 2;
defparam altdq_dqs2_inst.USE_OCT_ENA_IN_FOR_OCT = "true";
defparam altdq_dqs2_inst.PREAMBLE_TYPE = "high";
defparam altdq_dqs2_inst.USE_OFFSET_CTRL = "false";
defparam altdq_dqs2_inst.HR_DDIO_OUT_HAS_THREE_REGS = "true";
defparam altdq_dqs2_inst.DQS_ENABLE_PHASECTRL = "true";
defparam altdq_dqs2_inst.USE_2X_FF = "false";
defparam altdq_dqs2_inst.DLL_USE_2X_CLK = "false";
defparam altdq_dqs2_inst.USE_DQS_TRACKING = "false";
defparam altdq_dqs2_inst.CALIBRATION_SUPPORT = "false";
end
else
begin
altdq_dqs2_ddio_3reg_stratixiv altdq_dqs2_inst (
.reset_n_core_clock_in(reset_n_core_clock_in),
.core_clock_in( core_clock_in),
.fr_clock_in( fr_clock_in),
.hr_clock_in( hr_clock_in),
.write_strobe_clock_in (write_strobe_clock_in),
.strobe_ena_hr_clock_in( strobe_ena_hr_clock_in),
.strobe_ena_clock_in( strobe_ena_clock_in),
.capture_strobe_ena( capture_strobe_ena),
.read_write_data_io( read_write_data_io),
.write_oe_in( write_oe_in),
.strobe_io( strobe_io),
.output_strobe_ena( output_strobe_ena),
.strobe_n_io( strobe_n_io),
.oct_ena_in( oct_ena_in),
.read_data_out( read_data_out),
.capture_strobe_out( capture_strobe_out),
.write_data_in( write_data_in),
.extra_write_data_in( extra_write_data_in),
.extra_write_data_out( extra_write_data_out),
.parallelterminationcontrol_in( parallelterminationcontrol_in),
.seriesterminationcontrol_in( seriesterminationcontrol_in),
.config_data_in( config_data_in),
.config_update( config_update),
.config_dqs_ena( config_dqs_ena),
.config_io_ena( config_io_ena),
.config_extra_io_ena( config_extra_io_ena),
.config_dqs_io_ena( config_dqs_io_ena),
.config_clock_in( config_clock_in),
.dll_delayctrl_in(dll_delayctrl_in)
);
defparam altdq_dqs2_inst.PIN_WIDTH = 8;
defparam altdq_dqs2_inst.PIN_TYPE = "bidir";
defparam altdq_dqs2_inst.USE_INPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_OUTPUT_PHASE_ALIGNMENT = "true";
defparam altdq_dqs2_inst.USE_LDC_AS_LOW_SKEW_CLOCK = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_INPUT = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_OUTPUT = "true";
defparam altdq_dqs2_inst.DIFFERENTIAL_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SEPARATE_CAPTURE_STROBE = "false";
defparam altdq_dqs2_inst.INPUT_FREQ = 533;
defparam altdq_dqs2_inst.INPUT_FREQ_PS = "1876 ps";
defparam altdq_dqs2_inst.DELAY_CHAIN_BUFFER_MODE = "HIGH";
defparam altdq_dqs2_inst.DQS_PHASE_SETTING = 2;
defparam altdq_dqs2_inst.DQS_PHASE_SHIFT = 9000;
defparam altdq_dqs2_inst.DQS_ENABLE_PHASE_SETTING = 0;
defparam altdq_dqs2_inst.USE_DYNAMIC_CONFIG = "true";
defparam altdq_dqs2_inst.INVERT_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.USE_TERMINATION_CONTROL = "true";
defparam altdq_dqs2_inst.USE_DQS_ENABLE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE_RESET = "false";
defparam altdq_dqs2_inst.DIFFERENTIAL_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_BIDIR_STROBE = "true";
defparam altdq_dqs2_inst.REVERSE_READ_WORDS = "false";
defparam altdq_dqs2_inst.EXTRA_OUTPUT_WIDTH = 1;
defparam altdq_dqs2_inst.DYNAMIC_MODE = "dynamic";
defparam altdq_dqs2_inst.OCT_SERIES_TERM_CONTROL_WIDTH = 14;
defparam altdq_dqs2_inst.OCT_PARALLEL_TERM_CONTROL_WIDTH = 14;
defparam altdq_dqs2_inst.DLL_WIDTH = 6;
defparam altdq_dqs2_inst.USE_DATA_OE_FOR_OCT = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_WIDTH = 2;
defparam altdq_dqs2_inst.USE_OCT_ENA_IN_FOR_OCT = "true";
defparam altdq_dqs2_inst.PREAMBLE_TYPE = "high";
defparam altdq_dqs2_inst.USE_OFFSET_CTRL = "false";
defparam altdq_dqs2_inst.HR_DDIO_OUT_HAS_THREE_REGS = "true";
defparam altdq_dqs2_inst.REGULAR_WRITE_BUS_ORDERING = "true";
defparam altdq_dqs2_inst.DQS_ENABLE_PHASECTRL = "true";
defparam altdq_dqs2_inst.USE_2X_FF = "false";
defparam altdq_dqs2_inst.DLL_USE_2X_CLK = "false";
defparam altdq_dqs2_inst.USE_DQS_TRACKING = "false";
defparam altdq_dqs2_inst.CALIBRATION_SUPPORT = "false";
end
endgenerate
endmodule
|
// part of NeoGS project (c) 2007-2008 NedoPC
//
// memmap is memory mapper for NGS. Physical memory divided in 16kb pages.
// At (a15=0,a14=0) there is always zero page of MEM, at (a15=0,a14=1) there is
// always third page of RAM, at (a15=1,a14=0) there is page of MEM determined by
// mode_pg0 input bus, at (a15=1,a14=1) - page of MEM determined by mode_pg1 input.
// When mode_norom=0, MEM is ROM, otherwise MEM is RAM.
// When mode_ramro=1, zero and first pages of RAM are read-only.
// Memory addressed by mema14..mema18 (total 512kb) and then by either
// romcs_n (only 512kb of ROM) or ram0cs_n..ram3cs_n (2Mb of RAM).
// Memory decoding is static - it depends on only a14,a15 and mode_pg0,1 inputs.
// memoe_n and memwe_n generated from only mreq_n, rd_n and wr_n with the
// exception of read-only page of RAM (no memwe_n). ROM is always read/write (flash).
module memmap(
a15,a14, // Z80 address signals
mreq_n, // Z80 bus control signals
rd_n, //
wr_n, //
mema14,mema15, // memory addresses
mema16,mema17, //
mema18,mema21, //
ram0cs_n, // four RAM /CS'es
ram1cs_n, //
ram2cs_n, //
ram3cs_n, // (total 512kb * 4 = 2Mb)
romcs_n, // ROM (flash) /CS
memoe_n, // memory /OE and /WE
memwe_n, //
mode_ramro, // 1 - zero page (32k) of ram is R/O
mode_norom, // 0 - ROM instead of RAM at everything except $4000-$7FFF
mode_pg0, // page at $0000-$3FFF
mode_pg1, // page at $4000-$7FFF
mode_pg2, // page at $8000-$BFFF
mode_pg3 // page at $C000-$FFFF
);
// inputs and outputs
input a15,a14;
input mreq_n,rd_n,wr_n;
output reg mema14, mema15, mema16, mema17, mema18, mema21;
output reg ram0cs_n,ram1cs_n,ram2cs_n,ram3cs_n;
output reg romcs_n;
output reg memoe_n,memwe_n;
input mode_ramro,mode_norom;
input [7:0] mode_pg0,mode_pg1,mode_pg2,mode_pg3;
// internal vars and regs
reg [7:0] high_addr;
// addresses mapping
always @*
begin
case( {a15,a14} )
2'b00: // $0000-$3FFF
high_addr <= mode_pg0;
2'b01: // $4000-$7FFF
high_addr <= mode_pg1;
2'b10: // $8000-$BFFF
high_addr <= mode_pg2;
2'b11: // $C000-$FFFF
high_addr <= mode_pg3;
endcase
end
// memory addresses
always @*
begin
{ mema21, mema18, mema17, mema16, mema15, mema14 } <= { high_addr[7], high_addr[4:0] };
end
// memory chip selects
always @*
begin
if( (mode_norom==1'b0) && ( {a15,a14}!=2'b01 ) ) // ROM selected
begin
romcs_n <= 1'b0;
ram0cs_n <= 1'b1;
ram1cs_n <= 1'b1;
ram2cs_n <= 1'b1;
ram3cs_n <= 1'b1;
end
else // RAM
begin
romcs_n <= 1'b1;
ram0cs_n <= ( high_addr[6:5]==2'b00 ) ? 1'b0 : 1'b1;
ram1cs_n <= ( high_addr[6:5]==2'b01 ) ? 1'b0 : 1'b1;
ram2cs_n <= ( high_addr[6:5]==2'b10 ) ? 1'b0 : 1'b1;
ram3cs_n <= ( high_addr[6:5]==2'b11 ) ? 1'b0 : 1'b1;
end
end
// memory /OE and /WE
always @*
begin
memoe_n <= mreq_n | rd_n;
if( (high_addr[6:1] == 6'd0) && (mode_ramro==1'b1) && (mode_norom==1'b1) ) // R/O
memwe_n <= 1'b1;
else // no R/O
memwe_n <= mreq_n | wr_n;
end
endmodule
|
//-----------------------------------------------------------------------------
// The FPGA is responsible for interfacing between the A/D, the coil drivers,
// and the ARM. In the low-frequency modes it passes the data straight
// through, so that the ARM gets raw A/D samples over the SSP. In the high-
// frequency modes, the FPGA might perform some demodulation first, to
// reduce the amount of data that we must send to the ARM.
//
// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
// could be improved.
//
// Jonathan Westhues, March 2006
// Added ISO14443-A support by Gerhard de Koning Gans, April 2008
//-----------------------------------------------------------------------------
`include "hi_iso14443a.v"
`include "relay.v"
`include "relay_test.v"
`include "util.v"
`define SNIFFER 3'b000
`define TAGSIM_LISTEN 3'b001
`define TAGSIM_MOD 3'b010
`define READER_LISTEN 3'b011
`define READER_MOD 3'b100
`define FAKE_READER 3'b101
`define FAKE_TAG 3'b110
module fpga(
spck, miso, mosi, ncs,
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk, adc_noe,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg
);
input spck, mosi, ncs;
output miso;
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk, adc_noe;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
input dbg;
//-----------------------------------------------------------------------------
// The SPI receiver. This sets up the configuration word, which the rest of
// the logic looks at to determine how to connect the A/D and the coil
// drivers (i.e., which section gets it). Also assign some symbolic names
// to the configuration bits, for use below.
//-----------------------------------------------------------------------------
reg [15:0] shift_reg = 16'b0;
reg [7:0] divisor = 8'b0;
reg [7:0] conf_word = 8'b0;
// We switch modes between transmitting to the 13.56 MHz tag and receiving
// from it, which means that we must make sure that we can do so without
// glitching, or else we will glitch the transmitted carrier.
always @(posedge ncs)
begin
case(shift_reg[15:12])
4'b0001: conf_word <= shift_reg[7:0]; // FPGA_CMD_SET_CONFREG
4'b0010: divisor <= shift_reg[7:0]; // FPGA_CMD_SET_DIVISOR
endcase
end
always @(posedge spck)
begin
if(~ncs)
begin
shift_reg[15:1] <= shift_reg[14:0];
shift_reg[0] <= mosi;
end
end
wire major_mode;
assign major_mode = conf_word[5];
// For the high-frequency simulated tag: what kind of modulation to use.
wire [2:0] hi_simulate_mod_type;
assign hi_simulate_mod_type = conf_word[2:0];
wire [2:0] relay_mod_type;
wire [2:0] mod_type;
wire hisn_ssp_dout;
wire relay_out;
wire relay_active = (hi_simulate_mod_type == `FAKE_READER || hi_simulate_mod_type == `FAKE_TAG || hi_simulate_mod_type == 3'b111);
//-----------------------------------------------------------------------------
// And then we instantiate the modules corresponding to each of the FPGA's
// major modes, and use muxes to connect the outputs of the active mode to
// the output pins.
//-----------------------------------------------------------------------------
hi_iso14443a hisn(
pck0, ck_1356meg, ck_1356megb,
, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
adc_d, hisn_adc_clk,
hisn_ssp_frame, hisn_ssp_din, hisn_ssp_dout, hisn_ssp_clk,
cross_hi, cross_lo,
,
mod_type
);
relay r(
ck_1356meg,
~relay_active,
dbg,
hi_simulate_mod_type,
relay_mod_type,
relay_out,
hisn_ssp_din,
relay_relay
);
relay_test rt(
pck0, ck_1356meg, ck_1356megb,
rt_ssp_frame, rt_ssp_din, ssp_dout, rt_ssp_clk,
dbg, rt_data_out,
hi_simulate_mod_type
);
mux2 mux_ssp_clk (major_mode, ssp_clk, hisn_ssp_clk, rt_ssp_clk);
mux2 mux_ssp_din (major_mode, ssp_din, hisn_ssp_din, rt_ssp_din);
mux2 mux_ssp_frame (major_mode, ssp_frame, hisn_ssp_frame, rt_ssp_frame);
mux2 mux_pwr_oe1 (major_mode, pwr_oe1, hisn_pwr_oe1, 1'b0);
mux2 mux_pwr_oe2 (major_mode, pwr_oe2, hisn_pwr_oe2, 1'b0);
mux2 mux_pwr_oe3 (major_mode, pwr_oe3, hisn_pwr_oe3, 1'b0);
mux2 mux_pwr_oe4 (major_mode, pwr_oe4, hisn_pwr_oe4, 1'b0);
mux2 mux_pwr_lo (major_mode, pwr_lo, relay_relay, rt_data_out);
mux2 mux_pwr_hi (major_mode, pwr_hi, hisn_pwr_hi, 1'b0);
mux2 mux_adc_clk (major_mode, adc_clk, hisn_adc_clk, 1'b0);
assign mod_type = relay_active ? relay_mod_type : hi_simulate_mod_type;
assign hisn_ssp_dout = relay_active ? relay_out : ssp_dout;
// In all modes, let the ADC's outputs be enabled.
assign adc_noe = 1'b0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2111O_SYMBOL_V
`define SKY130_FD_SC_LS__A2111O_SYMBOL_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a2111o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2111O_SYMBOL_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
//
// This file is part of Descrypt Ztex Bruteforcer
// Copyright (C) 2014 Alexey Osipov <giftsungiv3n at gmail dot com>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////
module SP_block(
input [47:0] Din,
output [31:0] P_S
);
wire [31:0] S_B;
S_combined S_combined_instance(
Din,
S_B);
S_permutation S_permutation_instance(
S_B,
P_S
);
endmodule
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <[email protected]>
* 2019 Eddie Hung <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// The purpose of these mapping rules is to allow preserve all (sufficiently
// wide) $shiftx cells during 'techmap' so that they can be mapped to hard
// resources, rather than being bit-blasted to gates during 'techmap'
// execution
module \$shiftx (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] Y;
parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
generate
if (B_SIGNED) begin
if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && (_TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0 || _TECHMAP_CONSTVAL_B_[B_WIDTH-1] === 1'bx))
// Optimisation to remove B_SIGNED if sign bit of B is constant-0
\$shiftx #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(0),
.A_WIDTH(A_WIDTH),
.B_WIDTH(B_WIDTH-1'd1),
.Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ (
.A(A), .B(B[B_WIDTH-2:0]), .Y(Y)
);
else
wire _TECHMAP_FAIL_ = 1;
end
else begin
if (((A_WIDTH + Y_WIDTH - 1) / Y_WIDTH) < `MIN_MUX_INPUTS)
wire _TECHMAP_FAIL_ = 1;
else
\$__XILINX_SHIFTX #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH),
.B_WIDTH(B_WIDTH),
.Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ (
.A(A), .B(B), .Y(Y)
);
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVGND_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__TAPVGND_PP_BLACKBOX_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__tapvgnd (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVGND_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:11:24 02/22/2015
// Design Name:
// Module Name: AllignAdder
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module AllignAdder(
input idle_Special,
input [35:0] cout_Special,
input [35:0] zout_Special,
input [31:0] sout_Special,
input [7:0] difference_Special,
input clock,
output reg idle_Allign,
output reg [35:0] cout_Allign,
output reg [35:0] zout_Allign,
output reg [31:0] sout_Allign
);
parameter no_idle = 1'b01,
put_idle = 1'b1;
wire z_sign;
wire [7:0] z_exponent;
wire [26:0] z_mantissa;
wire c_sign;
wire [7:0] c_exponent;
wire [26:0] c_mantissa;
assign z_sign = zout_Special[35];
assign z_exponent = zout_Special[34:27] - 127;
assign z_mantissa = {zout_Special[26:0]};
assign c_sign = cout_Special[35];
assign c_exponent = cout_Special[34:27] - 127;
assign c_mantissa = {cout_Special[26:0]};
always @ (posedge clock)
begin
idle_Allign <= idle_Special;
sout_Allign <= sout_Special;
if (idle_Special != put_idle) begin
if ($signed(c_exponent) > $signed(z_exponent)) begin
zout_Allign[35] <= zout_Special[35];
zout_Allign[34:27] <= z_exponent + difference_Special + 127;
zout_Allign[26:0] <= z_mantissa >> difference_Special;
zout_Allign[0] <= z_mantissa[0] | z_mantissa[1];
cout_Allign <= cout_Special;
end else if ($signed(c_exponent) <= $signed(z_exponent)) begin
cout_Allign[35] <= cout_Special[35];
cout_Allign[34:27] <= c_exponent + difference_Special + 127;
cout_Allign[26:0] <= c_mantissa >> difference_Special;
cout_Allign[0] <= c_mantissa[0] | c_mantissa[1];
zout_Allign <= zout_Special;
end
end
else begin
zout_Allign <= zout_Special;
cout_Allign <= cout_Special;
end
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: nco_e.v
// /___/ /\ Timestamp: Tue Nov 19 22:30:47 2013
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog "C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Proyecto Final/CON SOLO NCO/tec-drums/ipcore_dir/tmp/_cg/nco_e.ngc" "C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Proyecto Final/CON SOLO NCO/tec-drums/ipcore_dir/tmp/_cg/nco_e.v"
// Device : 6slx16csg324-3
// Input file : C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Proyecto Final/CON SOLO NCO/tec-drums/ipcore_dir/tmp/_cg/nco_e.ngc
// Output file : C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Proyecto Final/CON SOLO NCO/tec-drums/ipcore_dir/tmp/_cg/nco_e.v
// # of Modules : 1
// Design Name : nco_e
// Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module nco_e (
clk, sine
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
output [15 : 0] sine;
// synthesis translate_off
wire sig00000001;
wire sig00000002;
wire sig00000003;
wire sig00000004;
wire sig00000005;
wire sig00000006;
wire sig00000007;
wire sig00000008;
wire sig00000009;
wire sig0000000a;
wire sig0000000b;
wire sig0000000c;
wire sig0000000d;
wire sig0000000e;
wire sig0000000f;
wire sig00000010;
wire sig00000011;
wire sig00000012;
wire sig00000013;
wire sig00000014;
wire sig00000015;
wire sig00000016;
wire sig00000017;
wire sig00000018;
wire sig00000019;
wire sig0000001a;
wire sig0000001b;
wire sig0000001c;
wire sig0000001d;
wire sig0000001e;
wire sig0000001f;
wire sig00000020;
wire sig00000021;
wire sig00000022;
wire sig00000023;
wire sig00000024;
wire sig00000025;
wire sig00000026;
wire sig00000027;
wire sig00000028;
wire sig00000029;
wire sig0000002a;
wire sig0000002b;
wire sig0000002c;
wire sig0000002d;
wire sig0000002e;
wire sig0000002f;
wire sig00000030;
wire sig00000031;
wire sig00000032;
wire sig00000033;
wire sig00000034;
wire sig00000035;
wire sig00000036;
wire sig00000037;
wire sig00000038;
wire sig00000039;
wire sig0000003a;
wire sig0000003b;
wire sig0000003c;
wire sig0000003d;
wire sig0000003e;
wire sig0000003f;
wire sig00000040;
wire sig00000041;
wire sig00000042;
wire sig00000043;
wire sig00000044;
wire sig00000045;
wire sig00000046;
wire sig00000047;
wire sig00000048;
wire sig00000049;
wire sig0000004a;
wire sig0000004b;
wire sig0000004c;
wire sig0000004d;
wire sig0000004e;
wire sig0000004f;
wire sig00000050;
wire sig00000051;
wire sig00000052;
wire sig00000053;
wire sig00000054;
wire sig00000055;
wire sig00000056;
wire sig00000057;
wire sig00000058;
wire sig00000059;
wire sig0000005a;
wire sig0000005b;
wire sig0000005c;
wire sig0000005d;
wire sig0000005e;
wire sig0000005f;
wire sig00000060;
wire sig00000061;
wire sig00000062;
wire sig00000063;
wire sig00000064;
wire sig00000065;
wire sig00000066;
wire sig00000067;
wire sig00000068;
wire sig00000069;
wire sig0000006a;
wire sig0000006b;
wire sig0000006c;
wire sig0000006d;
wire sig0000006e;
wire sig0000006f;
wire sig00000070;
wire sig00000071;
wire sig00000072;
wire sig00000073;
wire sig00000074;
wire sig00000075;
wire sig00000076;
wire sig00000077;
wire sig00000078;
wire sig00000079;
wire sig0000007a;
wire sig0000007b;
wire sig0000007c;
wire sig0000007d;
wire sig0000007e;
wire sig0000007f;
wire sig00000080;
wire sig00000081;
wire sig00000082;
wire sig00000083;
wire sig00000084;
wire sig00000085;
wire sig00000086;
wire sig00000087;
wire sig00000088;
wire sig00000089;
wire sig0000008a;
wire sig0000008b;
wire sig0000008c;
wire sig0000008d;
wire sig0000008e;
wire sig0000008f;
wire sig00000090;
wire sig00000091;
wire sig00000092;
wire sig00000093;
wire sig00000094;
wire sig00000095;
wire sig00000096;
wire sig00000097;
wire sig00000098;
wire sig00000099;
wire sig0000009a;
wire sig0000009b;
wire sig0000009c;
wire sig0000009d;
wire sig0000009e;
wire sig0000009f;
wire sig000000a0;
wire sig000000a1;
wire sig000000a2;
wire sig000000a3;
wire sig000000a4;
wire sig000000a5;
wire sig000000a6;
wire sig000000a7;
wire sig000000a8;
wire sig000000a9;
wire sig000000aa;
wire sig000000ab;
wire sig000000ac;
wire sig000000ad;
wire sig000000ae;
wire sig000000af;
wire sig000000b0;
wire sig000000b1;
wire sig000000b2;
wire sig000000b3;
wire sig000000b4;
wire sig000000b5;
wire sig000000b6;
wire sig000000b7;
wire sig000000b8;
wire sig000000b9;
wire sig000000ba;
wire sig000000bb;
wire sig000000bc;
wire sig000000bd;
wire sig000000be;
wire sig000000bf;
wire sig000000c0;
wire sig000000c1;
wire sig000000c2;
wire sig000000c3;
wire sig000000c4;
wire sig000000c5;
wire sig000000c6;
wire sig000000c7;
wire sig000000c8;
wire sig000000c9;
wire sig000000ca;
wire sig000000cb;
wire sig000000cc;
wire sig000000cd;
wire sig000000ce;
wire sig000000cf;
wire sig000000d0;
wire sig000000d1;
wire sig000000d2;
wire sig000000d3;
wire sig000000d4;
wire sig000000d5;
wire sig000000d6;
wire sig000000d7;
wire sig000000d8;
wire sig000000d9;
wire sig000000da;
wire sig000000db;
wire sig000000dc;
wire sig000000dd;
wire sig000000de;
wire sig000000df;
wire sig000000e0;
wire sig000000e1;
wire sig000000e2;
wire sig000000e3;
wire sig000000e4;
wire sig000000e5;
wire sig000000e6;
wire sig000000e7;
wire sig000000e8;
wire sig000000e9;
wire sig000000ea;
wire sig000000eb;
wire sig000000ec;
wire sig000000ed;
wire sig000000ee;
wire sig000000ef;
wire sig000000f0;
wire sig000000f1;
wire sig000000f2;
wire sig000000f3;
wire sig000000f4;
wire sig000000f5;
wire sig000000f6;
wire sig000000f7;
wire sig000000f8;
wire sig000000f9;
wire sig000000fa;
wire sig000000fb;
wire sig000000fc;
wire sig000000fd;
wire sig000000fe;
wire sig000000ff;
wire sig00000100;
wire sig00000101;
wire sig00000102;
wire sig00000103;
wire sig00000104;
wire sig00000105;
wire sig00000106;
wire sig00000107;
wire sig00000108;
wire sig00000109;
wire sig0000010a;
wire sig0000010b;
wire sig0000010c;
wire sig0000010d;
wire sig0000010e;
wire sig0000010f;
wire sig00000110;
wire sig00000111;
wire sig00000112;
wire sig00000113;
wire sig00000114;
wire sig00000115;
wire sig00000116;
wire sig00000117;
wire sig00000118;
wire sig00000119;
wire sig0000011a;
wire sig0000011b;
wire sig0000011c;
wire sig0000011d;
wire sig0000011e;
wire sig0000011f;
wire sig00000120;
wire sig00000121;
wire sig00000122;
wire sig00000123;
wire sig00000124;
wire sig00000125;
wire sig00000126;
wire sig00000127;
wire sig00000128;
wire sig00000129;
wire sig0000012a;
wire sig0000012b;
wire sig0000012c;
wire sig0000012d;
wire sig0000012e;
wire sig0000012f;
wire sig00000130;
wire sig00000131;
wire sig00000132;
wire sig00000133;
wire sig00000134;
wire sig00000135;
wire sig00000136;
wire sig00000137;
wire sig00000138;
wire sig00000139;
wire sig0000013a;
wire sig0000013b;
wire sig0000013c;
wire sig0000013d;
wire sig0000013e;
wire sig0000013f;
wire sig00000140;
wire sig00000141;
wire sig00000142;
wire sig00000143;
wire sig00000144;
wire sig00000145;
wire sig00000146;
wire sig00000147;
wire sig00000148;
wire \blk00000025/sig00000198 ;
wire \blk00000025/sig00000197 ;
wire \blk00000025/sig00000196 ;
wire \blk00000025/sig00000195 ;
wire \blk00000025/sig00000194 ;
wire \blk00000025/sig00000193 ;
wire \blk00000025/sig00000192 ;
wire \blk00000025/sig00000191 ;
wire \blk00000025/sig00000190 ;
wire \blk00000025/sig0000018f ;
wire \blk00000025/sig0000018e ;
wire \blk00000025/sig0000018d ;
wire \blk00000025/sig0000018c ;
wire \blk00000025/sig0000018b ;
wire \blk00000025/sig0000018a ;
wire \blk00000025/sig00000189 ;
wire \blk00000025/sig00000188 ;
wire \blk00000025/sig00000187 ;
wire \blk00000025/sig00000186 ;
wire \blk00000025/sig00000185 ;
wire \blk00000025/sig00000184 ;
wire \blk00000025/sig00000183 ;
wire \blk00000025/sig00000182 ;
wire \blk00000025/sig00000181 ;
wire \blk00000025/sig00000180 ;
wire \blk00000025/sig0000017f ;
wire \blk00000025/sig0000017e ;
wire \blk00000025/sig0000017d ;
wire \blk00000025/sig0000017c ;
wire \blk00000025/sig0000017b ;
wire \blk00000025/sig0000017a ;
wire \blk00000056/sig000001e9 ;
wire \blk00000056/sig000001e8 ;
wire \blk00000056/sig000001e7 ;
wire \blk00000056/sig000001e6 ;
wire \blk00000056/sig000001e5 ;
wire \blk00000056/sig000001e4 ;
wire \blk00000056/sig000001e3 ;
wire \blk00000056/sig000001e2 ;
wire \blk00000056/sig000001e1 ;
wire \blk00000056/sig000001e0 ;
wire \blk00000056/sig000001df ;
wire \blk00000056/sig000001de ;
wire \blk00000056/sig000001dd ;
wire \blk00000056/sig000001dc ;
wire \blk00000056/sig000001db ;
wire \blk00000056/sig000001da ;
wire \blk00000056/sig000001d9 ;
wire \blk00000056/sig000001d8 ;
wire \blk00000056/sig000001d7 ;
wire \blk00000056/sig000001d6 ;
wire \blk00000056/sig000001d5 ;
wire \blk00000056/sig000001d4 ;
wire \blk00000056/sig000001d3 ;
wire \blk00000056/sig000001d2 ;
wire \blk00000056/sig000001d1 ;
wire \blk00000056/sig000001d0 ;
wire \blk00000056/sig000001cf ;
wire \blk00000056/sig000001ce ;
wire \blk00000056/sig000001cd ;
wire \blk00000056/sig000001cc ;
wire \blk00000056/sig000001cb ;
wire \blk00000087/sig000001ff ;
wire \blk00000087/sig000001fe ;
wire \blk00000087/sig000001fd ;
wire \blk00000087/sig000001fc ;
wire \blk00000087/sig000001fb ;
wire \blk00000087/sig000001fa ;
wire \blk00000087/sig000001f9 ;
wire \blk00000087/sig000001f8 ;
wire \blk00000087/sig000001f7 ;
wire \blk00000087/sig000001f6 ;
wire \blk00000087/sig000001f2 ;
wire \blk00000087/sig000001f1 ;
wire \blk00000087/sig000001f0 ;
wire \blk00000087/sig000001ef ;
wire \blk00000087/sig000001ee ;
wire \blk00000087/sig000001ed ;
wire \blk00000087/sig000001ec ;
wire \NLW_blk0000014d_DIPA<3>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPA<2>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPA<1>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPA<0>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<31>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<30>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<29>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<28>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<27>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<26>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<25>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<24>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<23>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<22>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<21>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<20>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<19>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<18>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<17>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<16>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<15>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<14>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<13>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<12>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<11>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<10>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<9>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<8>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<7>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<6>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<5>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<4>_UNCONNECTED ;
wire \NLW_blk0000014d_ADDRA<1>_UNCONNECTED ;
wire \NLW_blk0000014d_ADDRA<0>_UNCONNECTED ;
wire \NLW_blk0000014d_ADDRB<1>_UNCONNECTED ;
wire \NLW_blk0000014d_ADDRB<0>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<31>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<30>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<29>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<28>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<27>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<26>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<25>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<24>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<23>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<22>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<21>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<20>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<19>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<18>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<17>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<16>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<15>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<14>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<13>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<12>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<11>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<10>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<9>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<8>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<7>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<6>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<5>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<4>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<3>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<2>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<1>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<0>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPA<3>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPA<2>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPA<1>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPA<0>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPB<3>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPB<2>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPB<1>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPB<0>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPB<3>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPB<2>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPB<1>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPB<0>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<31>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<30>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<29>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<28>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<27>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<26>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<25>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<24>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<23>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<22>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<21>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<20>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<19>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<18>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<17>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<16>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<15>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<14>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<13>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<12>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<11>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<10>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<9>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<8>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<7>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<6>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<5>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<4>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<31>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<30>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<29>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<28>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<27>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<26>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<25>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<24>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<23>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<22>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<21>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<20>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<19>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<18>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<17>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<16>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<15>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<14>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<13>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<12>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<11>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<10>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<9>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<8>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<7>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<6>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<5>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<4>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPA<3>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPA<2>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPA<1>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPA<0>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<31>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<30>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<29>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<28>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<27>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<26>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<25>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<24>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<23>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<22>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<21>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<20>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<19>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<18>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<17>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<16>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<15>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<14>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<13>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<12>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<11>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<10>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<9>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<8>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<7>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<6>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<5>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<4>_UNCONNECTED ;
wire \NLW_blk0000014e_ADDRA<1>_UNCONNECTED ;
wire \NLW_blk0000014e_ADDRA<0>_UNCONNECTED ;
wire \NLW_blk0000014e_ADDRB<1>_UNCONNECTED ;
wire \NLW_blk0000014e_ADDRB<0>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<31>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<30>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<29>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<28>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<27>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<26>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<25>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<24>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<23>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<22>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<21>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<20>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<19>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<18>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<17>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<16>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<15>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<14>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<13>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<12>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<11>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<10>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<9>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<8>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<7>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<6>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<5>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<4>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<3>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<2>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<1>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<0>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPA<3>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPA<2>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPA<1>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPA<0>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPB<3>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPB<2>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPB<1>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPB<0>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPB<3>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPB<2>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPB<1>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPB<0>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<31>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<30>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<29>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<28>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<27>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<26>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<25>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<24>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<23>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<22>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<21>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<20>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<19>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<18>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<17>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<16>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<15>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<14>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<13>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<12>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<11>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<10>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<9>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<8>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<7>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<6>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<5>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<4>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<31>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<30>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<29>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<28>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<27>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<26>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<25>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<24>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<23>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<22>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<21>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<20>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<19>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<18>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<17>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<16>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<15>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<14>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<13>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<12>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<11>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<10>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<9>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<8>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<7>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<6>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<5>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<4>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPA<3>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPA<2>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPA<1>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPA<0>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<31>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<30>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<29>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<28>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<27>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<26>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<25>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<24>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<23>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<22>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<21>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<20>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<19>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<18>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<17>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<16>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<15>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<14>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<13>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<12>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<11>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<10>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<9>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<8>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<7>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<6>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<5>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<4>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<3>_UNCONNECTED ;
wire \NLW_blk0000014f_ADDRA<1>_UNCONNECTED ;
wire \NLW_blk0000014f_ADDRA<0>_UNCONNECTED ;
wire \NLW_blk0000014f_ADDRB<1>_UNCONNECTED ;
wire \NLW_blk0000014f_ADDRB<0>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<31>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<30>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<29>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<28>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<27>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<26>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<25>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<24>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<23>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<22>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<21>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<20>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<19>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<18>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<17>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<16>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<15>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<14>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<13>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<12>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<11>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<10>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<9>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<8>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<7>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<6>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<5>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<4>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<3>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<2>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<1>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<0>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPA<3>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPA<2>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPA<1>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPA<0>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPB<3>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPB<2>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPB<1>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPB<0>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPB<3>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPB<2>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPB<1>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPB<0>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<31>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<30>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<29>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<28>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<27>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<26>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<25>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<24>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<23>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<22>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<21>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<20>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<19>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<18>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<17>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<16>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<15>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<14>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<13>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<12>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<11>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<10>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<9>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<8>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<7>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<6>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<5>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<4>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<3>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<31>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<30>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<29>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<28>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<27>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<26>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<25>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<24>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<23>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<22>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<21>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<20>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<19>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<18>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<17>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<16>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<15>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<14>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<13>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<12>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<11>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<10>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<9>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<8>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<7>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<6>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<5>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<4>_UNCONNECTED ;
wire \NLW_blk00000150_DIPA<3>_UNCONNECTED ;
wire \NLW_blk00000150_DIPA<2>_UNCONNECTED ;
wire \NLW_blk00000150_DIPA<1>_UNCONNECTED ;
wire \NLW_blk00000150_DIPA<0>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<31>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<30>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<29>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<28>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<27>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<26>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<25>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<24>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<23>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<22>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<21>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<20>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<19>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<18>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<17>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<16>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<15>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<14>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<13>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<12>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<11>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<10>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<9>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<8>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<7>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<6>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<5>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<4>_UNCONNECTED ;
wire \NLW_blk00000150_ADDRA<1>_UNCONNECTED ;
wire \NLW_blk00000150_ADDRA<0>_UNCONNECTED ;
wire \NLW_blk00000150_ADDRB<1>_UNCONNECTED ;
wire \NLW_blk00000150_ADDRB<0>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<31>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<30>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<29>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<28>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<27>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<26>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<25>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<24>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<23>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<22>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<21>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<20>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<19>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<18>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<17>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<16>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<15>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<14>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<13>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<12>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<11>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<10>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<9>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<8>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<7>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<6>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<5>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<4>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<3>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<2>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<1>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<0>_UNCONNECTED ;
wire \NLW_blk00000150_DOPA<3>_UNCONNECTED ;
wire \NLW_blk00000150_DOPA<2>_UNCONNECTED ;
wire \NLW_blk00000150_DOPA<1>_UNCONNECTED ;
wire \NLW_blk00000150_DOPA<0>_UNCONNECTED ;
wire \NLW_blk00000150_DIPB<3>_UNCONNECTED ;
wire \NLW_blk00000150_DIPB<2>_UNCONNECTED ;
wire \NLW_blk00000150_DIPB<1>_UNCONNECTED ;
wire \NLW_blk00000150_DIPB<0>_UNCONNECTED ;
wire \NLW_blk00000150_DOPB<3>_UNCONNECTED ;
wire \NLW_blk00000150_DOPB<2>_UNCONNECTED ;
wire \NLW_blk00000150_DOPB<1>_UNCONNECTED ;
wire \NLW_blk00000150_DOPB<0>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<31>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<30>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<29>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<28>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<27>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<26>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<25>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<24>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<23>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<22>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<21>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<20>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<19>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<18>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<17>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<16>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<15>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<14>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<13>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<12>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<11>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<10>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<9>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<8>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<7>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<6>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<5>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<4>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<31>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<30>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<29>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<28>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<27>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<26>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<25>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<24>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<23>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<22>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<21>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<20>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<19>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<18>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<17>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<16>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<15>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<14>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<13>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<12>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<11>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<10>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<9>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<8>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<7>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<6>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<5>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<4>_UNCONNECTED ;
wire NLW_blk00000151_Q15_UNCONNECTED;
wire NLW_blk00000153_Q15_UNCONNECTED;
wire NLW_blk00000155_Q15_UNCONNECTED;
wire NLW_blk00000157_Q15_UNCONNECTED;
wire NLW_blk00000159_Q15_UNCONNECTED;
wire NLW_blk0000015b_Q15_UNCONNECTED;
wire NLW_blk0000015d_Q15_UNCONNECTED;
wire NLW_blk0000015f_Q15_UNCONNECTED;
wire NLW_blk00000161_Q15_UNCONNECTED;
wire NLW_blk00000163_Q15_UNCONNECTED;
wire NLW_blk00000165_Q15_UNCONNECTED;
wire NLW_blk00000167_Q15_UNCONNECTED;
wire NLW_blk00000169_Q15_UNCONNECTED;
wire NLW_blk0000016b_Q15_UNCONNECTED;
wire NLW_blk0000016d_Q15_UNCONNECTED;
wire NLW_blk0000016f_Q15_UNCONNECTED;
wire NLW_blk00000171_Q15_UNCONNECTED;
wire NLW_blk00000173_Q15_UNCONNECTED;
wire NLW_blk00000175_Q15_UNCONNECTED;
wire NLW_blk00000177_Q15_UNCONNECTED;
wire NLW_blk00000179_Q15_UNCONNECTED;
wire NLW_blk0000017b_Q15_UNCONNECTED;
wire NLW_blk0000017d_Q15_UNCONNECTED;
wire NLW_blk0000017f_Q15_UNCONNECTED;
wire NLW_blk00000181_Q15_UNCONNECTED;
wire NLW_blk00000183_Q15_UNCONNECTED;
wire NLW_blk00000185_Q15_UNCONNECTED;
wire NLW_blk00000187_Q15_UNCONNECTED;
wire NLW_blk00000189_Q15_UNCONNECTED;
wire NLW_blk0000018b_Q15_UNCONNECTED;
wire NLW_blk0000018d_Q15_UNCONNECTED;
wire NLW_blk0000018f_Q15_UNCONNECTED;
wire [7 : 0] \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q ;
wire [7 : 0] \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q ;
assign
sine[15] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [7],
sine[14] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [6],
sine[13] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [5],
sine[12] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [4],
sine[11] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [3],
sine[10] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [2],
sine[9] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [1],
sine[8] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [0],
sine[7] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [7],
sine[6] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [6],
sine[5] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [5],
sine[4] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [4],
sine[3] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [3],
sine[2] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [2],
sine[1] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [1],
sine[0] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [0];
VCC blk00000001 (
.P(sig00000001)
);
GND blk00000002 (
.G(sig00000002)
);
FD #(
.INIT ( 1'b0 ))
blk00000003 (
.C(clk),
.D(sig00000003),
.Q(sig00000046)
);
FD #(
.INIT ( 1'b0 ))
blk00000004 (
.C(clk),
.D(sig00000004),
.Q(sig00000045)
);
FD #(
.INIT ( 1'b0 ))
blk00000005 (
.C(clk),
.D(sig00000005),
.Q(sig00000044)
);
FD #(
.INIT ( 1'b0 ))
blk00000006 (
.C(clk),
.D(sig00000006),
.Q(sig00000043)
);
FD #(
.INIT ( 1'b0 ))
blk00000007 (
.C(clk),
.D(sig00000007),
.Q(sig00000042)
);
FD #(
.INIT ( 1'b0 ))
blk00000008 (
.C(clk),
.D(sig00000008),
.Q(sig00000041)
);
FD #(
.INIT ( 1'b0 ))
blk00000009 (
.C(clk),
.D(sig00000009),
.Q(sig00000040)
);
FD #(
.INIT ( 1'b0 ))
blk0000000a (
.C(clk),
.D(sig0000000a),
.Q(sig0000003f)
);
FD #(
.INIT ( 1'b0 ))
blk0000000b (
.C(clk),
.D(sig0000000b),
.Q(sig0000003e)
);
FD #(
.INIT ( 1'b0 ))
blk0000000c (
.C(clk),
.D(sig0000000c),
.Q(sig0000003d)
);
FD #(
.INIT ( 1'b0 ))
blk0000000d (
.C(clk),
.D(sig0000000d),
.Q(sig0000003c)
);
FD #(
.INIT ( 1'b0 ))
blk0000000e (
.C(clk),
.D(sig0000000e),
.Q(sig0000003b)
);
FD #(
.INIT ( 1'b0 ))
blk0000000f (
.C(clk),
.D(sig0000000f),
.Q(sig0000003a)
);
FD #(
.INIT ( 1'b0 ))
blk00000010 (
.C(clk),
.D(sig00000010),
.Q(sig00000039)
);
FD #(
.INIT ( 1'b0 ))
blk00000011 (
.C(clk),
.D(sig00000011),
.Q(sig00000038)
);
FD #(
.INIT ( 1'b0 ))
blk00000012 (
.C(clk),
.D(sig00000012),
.Q(sig00000037)
);
FD #(
.INIT ( 1'b0 ))
blk00000013 (
.C(clk),
.D(sig00000013),
.Q(sig00000036)
);
FD #(
.INIT ( 1'b0 ))
blk00000014 (
.C(clk),
.D(sig00000024),
.Q(sig00000049)
);
FD #(
.INIT ( 1'b0 ))
blk00000015 (
.C(clk),
.D(sig00000023),
.Q(sig00000032)
);
FD #(
.INIT ( 1'b0 ))
blk00000016 (
.C(clk),
.D(sig00000022),
.Q(sig00000031)
);
FD #(
.INIT ( 1'b0 ))
blk00000017 (
.C(clk),
.D(sig00000021),
.Q(sig00000030)
);
FD #(
.INIT ( 1'b0 ))
blk00000018 (
.C(clk),
.D(sig00000020),
.Q(sig0000002f)
);
FD #(
.INIT ( 1'b0 ))
blk00000019 (
.C(clk),
.D(sig0000001f),
.Q(sig0000002e)
);
FD #(
.INIT ( 1'b0 ))
blk0000001a (
.C(clk),
.D(sig0000001e),
.Q(sig0000002d)
);
FD #(
.INIT ( 1'b0 ))
blk0000001b (
.C(clk),
.D(sig0000001d),
.Q(sig0000002c)
);
FD #(
.INIT ( 1'b0 ))
blk0000001c (
.C(clk),
.D(sig0000001c),
.Q(sig0000002b)
);
FD #(
.INIT ( 1'b0 ))
blk0000001d (
.C(clk),
.D(sig0000001b),
.Q(sig0000002a)
);
FD #(
.INIT ( 1'b0 ))
blk0000001e (
.C(clk),
.D(sig0000001a),
.Q(sig00000029)
);
FD #(
.INIT ( 1'b0 ))
blk0000001f (
.C(clk),
.D(sig00000019),
.Q(sig00000028)
);
FD #(
.INIT ( 1'b0 ))
blk00000020 (
.C(clk),
.D(sig00000018),
.Q(sig00000027)
);
FD #(
.INIT ( 1'b0 ))
blk00000021 (
.C(clk),
.D(sig00000017),
.Q(sig00000026)
);
FD #(
.INIT ( 1'b0 ))
blk00000022 (
.C(clk),
.D(sig00000016),
.Q(sig00000025)
);
FD #(
.INIT ( 1'b0 ))
blk00000023 (
.C(clk),
.D(sig00000015),
.Q(sig00000048)
);
FD #(
.INIT ( 1'b0 ))
blk00000024 (
.C(clk),
.D(sig00000014),
.Q(sig00000047)
);
XORCY blk0000009c (
.CI(sig0000005d),
.LI(sig0000007d),
.O(sig00000075)
);
MUXCY blk0000009d (
.CI(sig0000005d),
.DI(sig00000002),
.S(sig0000007d),
.O(sig0000005c)
);
XORCY blk0000009e (
.CI(sig0000005e),
.LI(sig0000007c),
.O(sig00000074)
);
MUXCY blk0000009f (
.CI(sig0000005e),
.DI(sig00000002),
.S(sig0000007c),
.O(sig0000005d)
);
XORCY blk000000a0 (
.CI(sig0000005f),
.LI(sig0000007b),
.O(sig00000073)
);
MUXCY blk000000a1 (
.CI(sig0000005f),
.DI(sig00000002),
.S(sig0000007b),
.O(sig0000005e)
);
XORCY blk000000a2 (
.CI(sig00000060),
.LI(sig0000007a),
.O(sig00000072)
);
MUXCY blk000000a3 (
.CI(sig00000060),
.DI(sig00000002),
.S(sig0000007a),
.O(sig0000005f)
);
XORCY blk000000a4 (
.CI(sig00000061),
.LI(sig00000079),
.O(sig00000071)
);
MUXCY blk000000a5 (
.CI(sig00000061),
.DI(sig00000002),
.S(sig00000079),
.O(sig00000060)
);
XORCY blk000000a6 (
.CI(sig00000062),
.LI(sig00000078),
.O(sig00000070)
);
MUXCY blk000000a7 (
.CI(sig00000062),
.DI(sig00000002),
.S(sig00000078),
.O(sig00000061)
);
XORCY blk000000a8 (
.CI(sig00000063),
.LI(sig00000077),
.O(sig0000006f)
);
MUXCY blk000000a9 (
.CI(sig00000063),
.DI(sig00000002),
.S(sig00000077),
.O(sig00000062)
);
XORCY blk000000aa (
.CI(sig00000064),
.LI(sig00000076),
.O(sig0000006e)
);
MUXCY blk000000ab (
.CI(sig00000064),
.DI(sig00000002),
.S(sig00000076),
.O(sig00000063)
);
MUXCY blk000000ac (
.CI(sig00000002),
.DI(sig00000001),
.S(sig00000065),
.O(sig00000064)
);
XORCY blk000000ad (
.CI(sig00000067),
.LI(sig00000094),
.O(sig0000008d)
);
MUXCY blk000000ae (
.CI(sig00000067),
.DI(sig00000002),
.S(sig00000094),
.O(sig00000066)
);
XORCY blk000000af (
.CI(sig00000068),
.LI(sig00000093),
.O(sig0000008c)
);
MUXCY blk000000b0 (
.CI(sig00000068),
.DI(sig00000002),
.S(sig00000093),
.O(sig00000067)
);
XORCY blk000000b1 (
.CI(sig00000069),
.LI(sig00000092),
.O(sig0000008b)
);
MUXCY blk000000b2 (
.CI(sig00000069),
.DI(sig00000002),
.S(sig00000092),
.O(sig00000068)
);
XORCY blk000000b3 (
.CI(sig0000006a),
.LI(sig00000091),
.O(sig0000008a)
);
MUXCY blk000000b4 (
.CI(sig0000006a),
.DI(sig00000002),
.S(sig00000091),
.O(sig00000069)
);
XORCY blk000000b5 (
.CI(sig0000006b),
.LI(sig00000090),
.O(sig00000089)
);
MUXCY blk000000b6 (
.CI(sig0000006b),
.DI(sig00000002),
.S(sig00000090),
.O(sig0000006a)
);
XORCY blk000000b7 (
.CI(sig0000006c),
.LI(sig0000008f),
.O(sig00000088)
);
MUXCY blk000000b8 (
.CI(sig0000006c),
.DI(sig00000002),
.S(sig0000008f),
.O(sig0000006b)
);
XORCY blk000000b9 (
.CI(sig0000006d),
.LI(sig0000008e),
.O(sig00000087)
);
MUXCY blk000000ba (
.CI(sig0000006d),
.DI(sig00000002),
.S(sig0000008e),
.O(sig0000006c)
);
XORCY blk000000bb (
.CI(sig00000002),
.LI(sig00000127),
.O(sig00000086)
);
MUXCY blk000000bc (
.CI(sig00000002),
.DI(sig0000009c),
.S(sig00000127),
.O(sig0000006d)
);
FD #(
.INIT ( 1'b0 ))
blk000000bd (
.C(clk),
.D(sig000000b6),
.Q(sig000000c2)
);
FD #(
.INIT ( 1'b0 ))
blk000000be (
.C(clk),
.D(sig000000b5),
.Q(sig000000c1)
);
FD #(
.INIT ( 1'b0 ))
blk000000bf (
.C(clk),
.D(sig000000b4),
.Q(sig000000c0)
);
FD #(
.INIT ( 1'b0 ))
blk000000c0 (
.C(clk),
.D(sig000000b3),
.Q(sig000000bf)
);
FD #(
.INIT ( 1'b0 ))
blk000000c1 (
.C(clk),
.D(sig000000b2),
.Q(sig000000be)
);
FD #(
.INIT ( 1'b0 ))
blk000000c2 (
.C(clk),
.D(sig000000b1),
.Q(sig000000bd)
);
FD #(
.INIT ( 1'b0 ))
blk000000c3 (
.C(clk),
.D(sig000000b0),
.Q(sig000000bc)
);
FD #(
.INIT ( 1'b0 ))
blk000000c4 (
.C(clk),
.D(sig000000af),
.Q(sig000000bb)
);
FD #(
.INIT ( 1'b0 ))
blk000000c5 (
.C(clk),
.D(sig000000ae),
.Q(sig000000ba)
);
FD #(
.INIT ( 1'b0 ))
blk000000c6 (
.C(clk),
.D(sig000000ad),
.Q(sig000000b9)
);
FD #(
.INIT ( 1'b0 ))
blk000000c7 (
.C(clk),
.D(sig000000ac),
.Q(sig000000b8)
);
FD #(
.INIT ( 1'b0 ))
blk000000c8 (
.C(clk),
.D(sig000000ab),
.Q(sig000000b7)
);
FD #(
.INIT ( 1'b0 ))
blk000000c9 (
.C(clk),
.D(sig00000124),
.Q(sig0000009c)
);
FD #(
.INIT ( 1'b0 ))
blk000000ca (
.C(clk),
.D(sig00000032),
.Q(sig00000126)
);
FD #(
.INIT ( 1'b0 ))
blk000000cb (
.C(clk),
.D(sig00000031),
.Q(sig00000125)
);
FD #(
.INIT ( 1'b0 ))
blk000000cc (
.C(clk),
.D(sig000000f8),
.Q(sig000000e8)
);
FD #(
.INIT ( 1'b0 ))
blk000000cd (
.C(clk),
.D(sig000000f7),
.Q(sig000000e7)
);
FD #(
.INIT ( 1'b0 ))
blk000000ce (
.C(clk),
.D(sig000000f6),
.Q(sig000000e6)
);
FD #(
.INIT ( 1'b0 ))
blk000000cf (
.C(clk),
.D(sig000000f5),
.Q(sig000000e5)
);
FD #(
.INIT ( 1'b0 ))
blk000000d0 (
.C(clk),
.D(sig000000f4),
.Q(sig000000e4)
);
FD #(
.INIT ( 1'b0 ))
blk000000d1 (
.C(clk),
.D(sig000000f3),
.Q(sig000000e3)
);
FD #(
.INIT ( 1'b0 ))
blk000000d2 (
.C(clk),
.D(sig000000f2),
.Q(sig000000e2)
);
FD #(
.INIT ( 1'b0 ))
blk000000d3 (
.C(clk),
.D(sig000000f1),
.Q(sig000000e1)
);
FD #(
.INIT ( 1'b0 ))
blk000000d4 (
.C(clk),
.D(sig000000a3),
.Q(sig000000f0)
);
FD #(
.INIT ( 1'b0 ))
blk000000d5 (
.C(clk),
.D(sig000000a2),
.Q(sig000000ef)
);
FD #(
.INIT ( 1'b0 ))
blk000000d6 (
.C(clk),
.D(sig000000a1),
.Q(sig000000ee)
);
FD #(
.INIT ( 1'b0 ))
blk000000d7 (
.C(clk),
.D(sig000000a0),
.Q(sig000000ed)
);
FD #(
.INIT ( 1'b0 ))
blk000000d8 (
.C(clk),
.D(sig0000009f),
.Q(sig000000ec)
);
FD #(
.INIT ( 1'b0 ))
blk000000d9 (
.C(clk),
.D(sig0000009e),
.Q(sig000000eb)
);
FD #(
.INIT ( 1'b0 ))
blk000000da (
.C(clk),
.D(sig0000009d),
.Q(sig000000ea)
);
FD #(
.INIT ( 1'b0 ))
blk000000db (
.C(clk),
.D(sig00000053),
.Q(sig000000e9)
);
FD #(
.INIT ( 1'b0 ))
blk000000dc (
.C(clk),
.D(sig00000102),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [7])
);
FD #(
.INIT ( 1'b0 ))
blk000000dd (
.C(clk),
.D(sig00000101),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [6])
);
FD #(
.INIT ( 1'b0 ))
blk000000de (
.C(clk),
.D(sig00000100),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [5])
);
FD #(
.INIT ( 1'b0 ))
blk000000df (
.C(clk),
.D(sig000000ff),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [4])
);
FD #(
.INIT ( 1'b0 ))
blk000000e0 (
.C(clk),
.D(sig000000fe),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [3])
);
FD #(
.INIT ( 1'b0 ))
blk000000e1 (
.C(clk),
.D(sig000000fd),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [2])
);
FD #(
.INIT ( 1'b0 ))
blk000000e2 (
.C(clk),
.D(sig000000fc),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [1])
);
FD #(
.INIT ( 1'b0 ))
blk000000e3 (
.C(clk),
.D(sig000000fb),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [0])
);
FD #(
.INIT ( 1'b0 ))
blk000000e4 (
.C(clk),
.D(sig000000aa),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [7])
);
FD #(
.INIT ( 1'b0 ))
blk000000e5 (
.C(clk),
.D(sig000000a9),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [6])
);
FD #(
.INIT ( 1'b0 ))
blk000000e6 (
.C(clk),
.D(sig000000a8),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [5])
);
FD #(
.INIT ( 1'b0 ))
blk000000e7 (
.C(clk),
.D(sig000000a7),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [4])
);
FD #(
.INIT ( 1'b0 ))
blk000000e8 (
.C(clk),
.D(sig000000a6),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [3])
);
FD #(
.INIT ( 1'b0 ))
blk000000e9 (
.C(clk),
.D(sig000000a5),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [2])
);
FD #(
.INIT ( 1'b0 ))
blk000000ea (
.C(clk),
.D(sig000000a4),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [1])
);
FD #(
.INIT ( 1'b0 ))
blk000000eb (
.C(clk),
.D(sig0000005b),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [0])
);
FD #(
.INIT ( 1'b0 ))
blk000000ec (
.C(clk),
.D(sig00000085),
.Q(sig0000004c)
);
FD #(
.INIT ( 1'b0 ))
blk000000ed (
.C(clk),
.D(sig00000084),
.Q(sig0000004d)
);
FD #(
.INIT ( 1'b0 ))
blk000000ee (
.C(clk),
.D(sig00000083),
.Q(sig0000004e)
);
FD #(
.INIT ( 1'b0 ))
blk000000ef (
.C(clk),
.D(sig00000082),
.Q(sig0000004f)
);
FD #(
.INIT ( 1'b0 ))
blk000000f0 (
.C(clk),
.D(sig00000081),
.Q(sig00000050)
);
FD #(
.INIT ( 1'b0 ))
blk000000f1 (
.C(clk),
.D(sig00000080),
.Q(sig00000051)
);
FD #(
.INIT ( 1'b0 ))
blk000000f2 (
.C(clk),
.D(sig0000007f),
.Q(sig00000052)
);
FD #(
.INIT ( 1'b0 ))
blk000000f3 (
.C(clk),
.D(sig0000007e),
.Q(sig000000fa)
);
FD #(
.INIT ( 1'b0 ))
blk000000f4 (
.C(clk),
.D(sig0000009c),
.Q(sig00000054)
);
FD #(
.INIT ( 1'b0 ))
blk000000f5 (
.C(clk),
.D(sig0000009b),
.Q(sig00000055)
);
FD #(
.INIT ( 1'b0 ))
blk000000f6 (
.C(clk),
.D(sig0000009a),
.Q(sig00000056)
);
FD #(
.INIT ( 1'b0 ))
blk000000f7 (
.C(clk),
.D(sig00000099),
.Q(sig00000057)
);
FD #(
.INIT ( 1'b0 ))
blk000000f8 (
.C(clk),
.D(sig00000098),
.Q(sig00000058)
);
FD #(
.INIT ( 1'b0 ))
blk000000f9 (
.C(clk),
.D(sig00000097),
.Q(sig00000059)
);
FD #(
.INIT ( 1'b0 ))
blk000000fa (
.C(clk),
.D(sig00000096),
.Q(sig0000005a)
);
FD #(
.INIT ( 1'b0 ))
blk000000fb (
.C(clk),
.D(sig00000095),
.Q(sig00000104)
);
FD #(
.INIT ( 1'b0 ))
blk000000fc (
.C(clk),
.D(sig0000005c),
.Q(sig000000f9)
);
FD #(
.INIT ( 1'b0 ))
blk000000fd (
.C(clk),
.D(sig00000075),
.Q(sig000000f8)
);
FD #(
.INIT ( 1'b0 ))
blk000000fe (
.C(clk),
.D(sig00000074),
.Q(sig000000f7)
);
FD #(
.INIT ( 1'b0 ))
blk000000ff (
.C(clk),
.D(sig00000073),
.Q(sig000000f6)
);
FD #(
.INIT ( 1'b0 ))
blk00000100 (
.C(clk),
.D(sig00000072),
.Q(sig000000f5)
);
FD #(
.INIT ( 1'b0 ))
blk00000101 (
.C(clk),
.D(sig00000071),
.Q(sig000000f4)
);
FD #(
.INIT ( 1'b0 ))
blk00000102 (
.C(clk),
.D(sig00000070),
.Q(sig000000f3)
);
FD #(
.INIT ( 1'b0 ))
blk00000103 (
.C(clk),
.D(sig0000006f),
.Q(sig000000f2)
);
FD #(
.INIT ( 1'b0 ))
blk00000104 (
.C(clk),
.D(sig0000006e),
.Q(sig000000f1)
);
FD #(
.INIT ( 1'b0 ))
blk00000105 (
.C(clk),
.D(sig00000066),
.Q(sig00000103)
);
FD #(
.INIT ( 1'b0 ))
blk00000106 (
.C(clk),
.D(sig0000008d),
.Q(sig00000102)
);
FD #(
.INIT ( 1'b0 ))
blk00000107 (
.C(clk),
.D(sig0000008c),
.Q(sig00000101)
);
FD #(
.INIT ( 1'b0 ))
blk00000108 (
.C(clk),
.D(sig0000008b),
.Q(sig00000100)
);
FD #(
.INIT ( 1'b0 ))
blk00000109 (
.C(clk),
.D(sig0000008a),
.Q(sig000000ff)
);
FD #(
.INIT ( 1'b0 ))
blk0000010a (
.C(clk),
.D(sig00000089),
.Q(sig000000fe)
);
FD #(
.INIT ( 1'b0 ))
blk0000010b (
.C(clk),
.D(sig00000088),
.Q(sig000000fd)
);
FD #(
.INIT ( 1'b0 ))
blk0000010c (
.C(clk),
.D(sig00000087),
.Q(sig000000fc)
);
FD #(
.INIT ( 1'b0 ))
blk0000010d (
.C(clk),
.D(sig00000086),
.Q(sig000000fb)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000010e (
.I0(sig00000056),
.I1(sig0000004a),
.O(sig000000a8)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000010f (
.I0(sig0000004e),
.I1(sig0000004b),
.O(sig000000a1)
);
LUT3 #(
.INIT ( 8'hA6 ))
blk00000110 (
.I0(sig00000055),
.I1(sig00000056),
.I2(sig0000004a),
.O(sig000000a9)
);
LUT3 #(
.INIT ( 8'hA6 ))
blk00000111 (
.I0(sig0000004d),
.I1(sig0000004e),
.I2(sig0000004b),
.O(sig000000a2)
);
LUT4 #(
.INIT ( 16'hAA6A ))
blk00000112 (
.I0(sig00000054),
.I1(sig00000055),
.I2(sig00000056),
.I3(sig0000004a),
.O(sig000000aa)
);
LUT4 #(
.INIT ( 16'hAA6A ))
blk00000113 (
.I0(sig0000004c),
.I1(sig0000004d),
.I2(sig0000004e),
.I3(sig0000004b),
.O(sig000000a3)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000114 (
.I0(sig00000115),
.I1(sig00000128),
.O(sig0000008e)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000115 (
.I0(sig00000116),
.I1(sig00000128),
.O(sig0000008f)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000116 (
.I0(sig00000117),
.I1(sig00000128),
.O(sig00000090)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000117 (
.I0(sig00000118),
.I1(sig00000128),
.O(sig00000091)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000118 (
.I0(sig00000119),
.I1(sig00000128),
.O(sig00000092)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000119 (
.I0(sig0000011a),
.I1(sig0000009c),
.O(sig00000093)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000011a (
.I0(sig0000011b),
.I1(sig0000009c),
.O(sig00000094)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000011b (
.I0(sig0000011c),
.I1(sig0000009c),
.O(sig00000095)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000011c (
.I0(sig0000011d),
.I1(sig0000009c),
.O(sig00000096)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000011d (
.I0(sig0000011e),
.I1(sig0000009c),
.O(sig00000097)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000011e (
.I0(sig0000011f),
.I1(sig0000009c),
.O(sig00000098)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000011f (
.I0(sig00000120),
.I1(sig0000009c),
.O(sig00000099)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000120 (
.I0(sig00000121),
.I1(sig0000009c),
.O(sig0000009a)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000121 (
.I0(sig00000122),
.I1(sig0000009c),
.O(sig0000009b)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000122 (
.I0(sig00000025),
.I1(sig00000031),
.O(sig000000ab)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000123 (
.I0(sig0000002f),
.I1(sig00000031),
.O(sig000000b5)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000124 (
.I0(sig00000030),
.I1(sig00000031),
.O(sig000000b6)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000125 (
.I0(sig00000026),
.I1(sig00000031),
.O(sig000000ac)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000126 (
.I0(sig00000027),
.I1(sig00000031),
.O(sig000000ad)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000127 (
.I0(sig00000028),
.I1(sig00000031),
.O(sig000000ae)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000128 (
.I0(sig00000029),
.I1(sig00000031),
.O(sig000000af)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000129 (
.I0(sig0000002a),
.I1(sig00000031),
.O(sig000000b0)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000012a (
.I0(sig0000002b),
.I1(sig00000031),
.O(sig000000b1)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000012b (
.I0(sig0000002c),
.I1(sig00000031),
.O(sig000000b2)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000012c (
.I0(sig0000002d),
.I1(sig00000031),
.O(sig000000b3)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000012d (
.I0(sig0000002e),
.I1(sig00000031),
.O(sig000000b4)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000012e (
.I0(sig00000123),
.I1(sig0000009c),
.O(sig00000085)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000012f (
.I0(sig000000fa),
.I1(sig000000f9),
.O(sig00000053)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000130 (
.I0(sig00000104),
.I1(sig00000103),
.O(sig0000005b)
);
LUT6 #(
.INIT ( 64'h7FFFFFFFFFFFFFFF ))
blk00000131 (
.I0(sig00000057),
.I1(sig00000058),
.I2(sig00000059),
.I3(sig0000005a),
.I4(sig00000103),
.I5(sig00000104),
.O(sig0000004a)
);
LUT6 #(
.INIT ( 64'h7FFFFFFFFFFFFFFF ))
blk00000132 (
.I0(sig0000004f),
.I1(sig00000050),
.I2(sig00000051),
.I3(sig00000052),
.I4(sig000000f9),
.I5(sig000000fa),
.O(sig0000004b)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000133 (
.I0(sig00000128),
.I1(sig00000123),
.O(sig00000065)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000134 (
.I0(sig00000105),
.I1(sig00000128),
.I2(sig00000123),
.O(sig00000076)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000135 (
.I0(sig00000106),
.I1(sig00000128),
.I2(sig00000123),
.O(sig00000077)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000136 (
.I0(sig00000107),
.I1(sig00000128),
.I2(sig00000123),
.O(sig00000078)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000137 (
.I0(sig00000108),
.I1(sig00000128),
.I2(sig00000123),
.O(sig00000079)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000138 (
.I0(sig00000109),
.I1(sig00000128),
.I2(sig00000123),
.O(sig0000007a)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000139 (
.I0(sig0000010a),
.I1(sig00000128),
.I2(sig00000123),
.O(sig0000007b)
);
LUT3 #(
.INIT ( 8'h96 ))
blk0000013a (
.I0(sig0000010b),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig0000007c)
);
LUT3 #(
.INIT ( 8'h96 ))
blk0000013b (
.I0(sig0000010c),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig0000007d)
);
LUT5 #(
.INIT ( 32'h6AAAAAAA ))
blk0000013c (
.I0(sig00000058),
.I1(sig00000104),
.I2(sig00000103),
.I3(sig0000005a),
.I4(sig00000059),
.O(sig000000a6)
);
LUT6 #(
.INIT ( 64'h6AAAAAAAAAAAAAAA ))
blk0000013d (
.I0(sig00000057),
.I1(sig00000104),
.I2(sig00000103),
.I3(sig0000005a),
.I4(sig00000059),
.I5(sig00000058),
.O(sig000000a7)
);
LUT4 #(
.INIT ( 16'h6AAA ))
blk0000013e (
.I0(sig00000059),
.I1(sig00000104),
.I2(sig00000103),
.I3(sig0000005a),
.O(sig000000a5)
);
LUT5 #(
.INIT ( 32'h6AAAAAAA ))
blk0000013f (
.I0(sig00000050),
.I1(sig000000fa),
.I2(sig000000f9),
.I3(sig00000052),
.I4(sig00000051),
.O(sig0000009f)
);
LUT6 #(
.INIT ( 64'h6AAAAAAAAAAAAAAA ))
blk00000140 (
.I0(sig0000004f),
.I1(sig000000fa),
.I2(sig000000f9),
.I3(sig00000052),
.I4(sig00000051),
.I5(sig00000050),
.O(sig000000a0)
);
LUT4 #(
.INIT ( 16'h6AAA ))
blk00000141 (
.I0(sig00000051),
.I1(sig000000fa),
.I2(sig000000f9),
.I3(sig00000052),
.O(sig0000009e)
);
LUT3 #(
.INIT ( 8'h6A ))
blk00000142 (
.I0(sig00000052),
.I1(sig000000fa),
.I2(sig000000f9),
.O(sig0000009d)
);
LUT3 #(
.INIT ( 8'h6A ))
blk00000143 (
.I0(sig0000005a),
.I1(sig00000104),
.I2(sig00000103),
.O(sig000000a4)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000144 (
.I0(sig0000010d),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig0000007e)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000145 (
.I0(sig0000010e),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig0000007f)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000146 (
.I0(sig0000010f),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig00000080)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000147 (
.I0(sig00000110),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig00000081)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000148 (
.I0(sig00000111),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig00000082)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000149 (
.I0(sig00000112),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig00000083)
);
LUT3 #(
.INIT ( 8'h96 ))
blk0000014a (
.I0(sig00000113),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig00000084)
);
LUT1 #(
.INIT ( 2'h2 ))
blk0000014b (
.I0(sig00000114),
.O(sig00000127)
);
FD #(
.INIT ( 1'b0 ))
blk0000014c (
.C(clk),
.D(sig00000124),
.Q(sig00000128)
);
RAMB16BWER #(
.INIT_00 ( 256'h3332222222222222222222211111111111111111111100000000000000000000 ),
.INIT_01 ( 256'h6666665555555555555555555544444444444444444444433333333333333333 ),
.INIT_02 ( 256'h9999999998888888888888888888877777777777777777777666666666666666 ),
.INIT_03 ( 256'hCCCCCCCCCCCBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAA999999999999 ),
.INIT_04 ( 256'hFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDDDDDDCCCCCCCCC ),
.INIT_05 ( 256'h222222222222222211111111111111111111100000000000000000000FFFFFFF ),
.INIT_06 ( 256'h5555555555555555554444444444444444444443333333333333333333332222 ),
.INIT_07 ( 256'h8888888888888888888877777777777777777777766666666666666666666655 ),
.INIT_08 ( 256'hCBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAAA999999999999999999998 ),
.INIT_09 ( 256'hFFEEEEEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDDDDDDCCCCCCCCCCCCCCCCCCCC ),
.INIT_0A ( 256'h222111111111111111111111000000000000000000000FFFFFFFFFFFFFFFFFFF ),
.INIT_0B ( 256'h5554444444444444444444444333333333333333333333222222222222222222 ),
.INIT_0C ( 256'h8887777777777777777777777666666666666666666666555555555555555555 ),
.INIT_0D ( 256'hBBBAAAAAAAAAAAAAAAAAAAAA9999999999999999999999888888888888888888 ),
.INIT_0E ( 256'hEDDDDDDDDDDDDDDDDDDDDDDCCCCCCCCCCCCCCCCCCCCCCBBBBBBBBBBBBBBBBBBB ),
.INIT_0F ( 256'h0000000000000000000000FFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEEEEE ),
.INIT_10 ( 256'h3333333333333333333222222222222222222222221111111111111111111111 ),
.INIT_11 ( 256'h6666666666666666555555555555555555555554444444444444444444444333 ),
.INIT_12 ( 256'h9999999999998888888888888888888888877777777777777777777777666666 ),
.INIT_13 ( 256'hCCCCCCCCBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAAAAA9999999999 ),
.INIT_14 ( 256'hFFEEEEEEEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDDDDDDDDDCCCCCCCCCCCCCCC ),
.INIT_15 ( 256'h1111111111111111111000000000000000000000000FFFFFFFFFFFFFFFFFFFFF ),
.INIT_16 ( 256'h4444444444433333333333333333333333322222222222222222222222211111 ),
.INIT_17 ( 256'h7776666666666666666666666665555555555555555555555554444444444444 ),
.INIT_18 ( 256'h9999999999999999988888888888888888888888887777777777777777777777 ),
.INIT_19 ( 256'hCCCCCCBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAAAAAAAA9999999 ),
.INIT_1A ( 256'hEEEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDDDDDDDDDDDCCCCCCCCCCCCCCCCCCC ),
.INIT_1B ( 256'h1111100000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEE ),
.INIT_1C ( 256'h3333333333333333222222222222222222222222222111111111111111111111 ),
.INIT_1D ( 256'h5555555555555555555555555544444444444444444444444444433333333333 ),
.INIT_1E ( 256'h8888888777777777777777777777777777766666666666666666666666666665 ),
.INIT_1F ( 256'hAAAAAAAAAAAAAAA9999999999999999999999999999888888888888888888888 ),
.INIT_20 ( 256'hCCCCCCCCCCCCCCCCCCCCCBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAA ),
.INIT_21 ( 256'hEEEEEEEEEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDCCCCCCCCC ),
.INIT_22 ( 256'h0000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEEEEE ),
.INIT_23 ( 256'h2222222222222222222222222222221111111111111111111111111111111000 ),
.INIT_24 ( 256'h4444444444444444444444444444443333333333333333333333333333333322 ),
.INIT_25 ( 256'h6666666666666666666666666665555555555555555555555555555555555444 ),
.INIT_26 ( 256'h8888888888888888888888877777777777777777777777777777777776666666 ),
.INIT_27 ( 256'hAAAAAAAAAAAAAAA9999999999999999999999999999999999998888888888888 ),
.INIT_28 ( 256'hCCCCCBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAAA ),
.INIT_29 ( 256'hDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC ),
.INIT_2A ( 256'hFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEDDDDDDDDD ),
.INIT_2B ( 256'h00000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2C ( 256'h2222222222222221111111111111111111111111111111111111111111100000 ),
.INIT_2D ( 256'h3333333333333333333333333333333332222222222222222222222222222222 ),
.INIT_2E ( 256'h5444444444444444444444444444444444444444444444444433333333333333 ),
.INIT_2F ( 256'h6666666666666555555555555555555555555555555555555555555555555555 ),
.INIT_30 ( 256'h7777777777777777777777766666666666666666666666666666666666666666 ),
.INIT_31 ( 256'h8888888888888888888888888888887777777777777777777777777777777777 ),
.INIT_32 ( 256'h9999999999999999999999999999999999888888888888888888888888888888 ),
.INIT_33 ( 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA9999999999999999999999999999999 ),
.INIT_34 ( 256'hBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ),
.INIT_35 ( 256'hCCCCCCCCCCCCCBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB ),
.INIT_36 ( 256'hCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC ),
.INIT_37 ( 256'hDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDCCCCCCCCCCC ),
.INIT_38 ( 256'hEEEEEEEEEEEEEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD ),
.INIT_39 ( 256'hEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE ),
.INIT_3A ( 256'hFFFFFEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE ),
.INIT_3B ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3C ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3E ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 4 ),
.DATA_WIDTH_B ( 4 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
blk0000014d (
.REGCEA(sig00000002),
.CLKA(clk),
.ENB(sig00000001),
.RSTB(sig00000002),
.CLKB(clk),
.REGCEB(sig00000002),
.RSTA(sig00000002),
.ENA(sig00000001),
.DIPA({\NLW_blk0000014d_DIPA<3>_UNCONNECTED , \NLW_blk0000014d_DIPA<2>_UNCONNECTED , \NLW_blk0000014d_DIPA<1>_UNCONNECTED ,
\NLW_blk0000014d_DIPA<0>_UNCONNECTED }),
.WEA({sig00000002, sig00000002, sig00000002, sig00000002}),
.DOA({\NLW_blk0000014d_DOA<31>_UNCONNECTED , \NLW_blk0000014d_DOA<30>_UNCONNECTED , \NLW_blk0000014d_DOA<29>_UNCONNECTED ,
\NLW_blk0000014d_DOA<28>_UNCONNECTED , \NLW_blk0000014d_DOA<27>_UNCONNECTED , \NLW_blk0000014d_DOA<26>_UNCONNECTED ,
\NLW_blk0000014d_DOA<25>_UNCONNECTED , \NLW_blk0000014d_DOA<24>_UNCONNECTED , \NLW_blk0000014d_DOA<23>_UNCONNECTED ,
\NLW_blk0000014d_DOA<22>_UNCONNECTED , \NLW_blk0000014d_DOA<21>_UNCONNECTED , \NLW_blk0000014d_DOA<20>_UNCONNECTED ,
\NLW_blk0000014d_DOA<19>_UNCONNECTED , \NLW_blk0000014d_DOA<18>_UNCONNECTED , \NLW_blk0000014d_DOA<17>_UNCONNECTED ,
\NLW_blk0000014d_DOA<16>_UNCONNECTED , \NLW_blk0000014d_DOA<15>_UNCONNECTED , \NLW_blk0000014d_DOA<14>_UNCONNECTED ,
\NLW_blk0000014d_DOA<13>_UNCONNECTED , \NLW_blk0000014d_DOA<12>_UNCONNECTED , \NLW_blk0000014d_DOA<11>_UNCONNECTED ,
\NLW_blk0000014d_DOA<10>_UNCONNECTED , \NLW_blk0000014d_DOA<9>_UNCONNECTED , \NLW_blk0000014d_DOA<8>_UNCONNECTED ,
\NLW_blk0000014d_DOA<7>_UNCONNECTED , \NLW_blk0000014d_DOA<6>_UNCONNECTED , \NLW_blk0000014d_DOA<5>_UNCONNECTED , \NLW_blk0000014d_DOA<4>_UNCONNECTED
, sig000000dd, sig000000dc, sig000000db, sig000000da}),
.ADDRA({sig000000c2, sig000000c1, sig000000c0, sig000000bf, sig000000be, sig000000bd, sig000000bc, sig000000bb, sig000000ba, sig000000b9,
sig000000b8, sig000000b7, \NLW_blk0000014d_ADDRA<1>_UNCONNECTED , \NLW_blk0000014d_ADDRA<0>_UNCONNECTED }),
.ADDRB({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, \NLW_blk0000014d_ADDRB<1>_UNCONNECTED , \NLW_blk0000014d_ADDRB<0>_UNCONNECTED }),
.DIB({\NLW_blk0000014d_DIB<31>_UNCONNECTED , \NLW_blk0000014d_DIB<30>_UNCONNECTED , \NLW_blk0000014d_DIB<29>_UNCONNECTED ,
\NLW_blk0000014d_DIB<28>_UNCONNECTED , \NLW_blk0000014d_DIB<27>_UNCONNECTED , \NLW_blk0000014d_DIB<26>_UNCONNECTED ,
\NLW_blk0000014d_DIB<25>_UNCONNECTED , \NLW_blk0000014d_DIB<24>_UNCONNECTED , \NLW_blk0000014d_DIB<23>_UNCONNECTED ,
\NLW_blk0000014d_DIB<22>_UNCONNECTED , \NLW_blk0000014d_DIB<21>_UNCONNECTED , \NLW_blk0000014d_DIB<20>_UNCONNECTED ,
\NLW_blk0000014d_DIB<19>_UNCONNECTED , \NLW_blk0000014d_DIB<18>_UNCONNECTED , \NLW_blk0000014d_DIB<17>_UNCONNECTED ,
\NLW_blk0000014d_DIB<16>_UNCONNECTED , \NLW_blk0000014d_DIB<15>_UNCONNECTED , \NLW_blk0000014d_DIB<14>_UNCONNECTED ,
\NLW_blk0000014d_DIB<13>_UNCONNECTED , \NLW_blk0000014d_DIB<12>_UNCONNECTED , \NLW_blk0000014d_DIB<11>_UNCONNECTED ,
\NLW_blk0000014d_DIB<10>_UNCONNECTED , \NLW_blk0000014d_DIB<9>_UNCONNECTED , \NLW_blk0000014d_DIB<8>_UNCONNECTED ,
\NLW_blk0000014d_DIB<7>_UNCONNECTED , \NLW_blk0000014d_DIB<6>_UNCONNECTED , \NLW_blk0000014d_DIB<5>_UNCONNECTED , \NLW_blk0000014d_DIB<4>_UNCONNECTED
, \NLW_blk0000014d_DIB<3>_UNCONNECTED , \NLW_blk0000014d_DIB<2>_UNCONNECTED , \NLW_blk0000014d_DIB<1>_UNCONNECTED ,
\NLW_blk0000014d_DIB<0>_UNCONNECTED }),
.DOPA({\NLW_blk0000014d_DOPA<3>_UNCONNECTED , \NLW_blk0000014d_DOPA<2>_UNCONNECTED , \NLW_blk0000014d_DOPA<1>_UNCONNECTED ,
\NLW_blk0000014d_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk0000014d_DIPB<3>_UNCONNECTED , \NLW_blk0000014d_DIPB<2>_UNCONNECTED , \NLW_blk0000014d_DIPB<1>_UNCONNECTED ,
\NLW_blk0000014d_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk0000014d_DOPB<3>_UNCONNECTED , \NLW_blk0000014d_DOPB<2>_UNCONNECTED , \NLW_blk0000014d_DOPB<1>_UNCONNECTED ,
\NLW_blk0000014d_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk0000014d_DOB<31>_UNCONNECTED , \NLW_blk0000014d_DOB<30>_UNCONNECTED , \NLW_blk0000014d_DOB<29>_UNCONNECTED ,
\NLW_blk0000014d_DOB<28>_UNCONNECTED , \NLW_blk0000014d_DOB<27>_UNCONNECTED , \NLW_blk0000014d_DOB<26>_UNCONNECTED ,
\NLW_blk0000014d_DOB<25>_UNCONNECTED , \NLW_blk0000014d_DOB<24>_UNCONNECTED , \NLW_blk0000014d_DOB<23>_UNCONNECTED ,
\NLW_blk0000014d_DOB<22>_UNCONNECTED , \NLW_blk0000014d_DOB<21>_UNCONNECTED , \NLW_blk0000014d_DOB<20>_UNCONNECTED ,
\NLW_blk0000014d_DOB<19>_UNCONNECTED , \NLW_blk0000014d_DOB<18>_UNCONNECTED , \NLW_blk0000014d_DOB<17>_UNCONNECTED ,
\NLW_blk0000014d_DOB<16>_UNCONNECTED , \NLW_blk0000014d_DOB<15>_UNCONNECTED , \NLW_blk0000014d_DOB<14>_UNCONNECTED ,
\NLW_blk0000014d_DOB<13>_UNCONNECTED , \NLW_blk0000014d_DOB<12>_UNCONNECTED , \NLW_blk0000014d_DOB<11>_UNCONNECTED ,
\NLW_blk0000014d_DOB<10>_UNCONNECTED , \NLW_blk0000014d_DOB<9>_UNCONNECTED , \NLW_blk0000014d_DOB<8>_UNCONNECTED ,
\NLW_blk0000014d_DOB<7>_UNCONNECTED , \NLW_blk0000014d_DOB<6>_UNCONNECTED , \NLW_blk0000014d_DOB<5>_UNCONNECTED , \NLW_blk0000014d_DOB<4>_UNCONNECTED
, sig000000ce, sig000000cd, sig000000cc, sig000000cb}),
.WEB({sig00000002, sig00000002, sig00000002, sig00000002}),
.DIA({\NLW_blk0000014d_DIA<31>_UNCONNECTED , \NLW_blk0000014d_DIA<30>_UNCONNECTED , \NLW_blk0000014d_DIA<29>_UNCONNECTED ,
\NLW_blk0000014d_DIA<28>_UNCONNECTED , \NLW_blk0000014d_DIA<27>_UNCONNECTED , \NLW_blk0000014d_DIA<26>_UNCONNECTED ,
\NLW_blk0000014d_DIA<25>_UNCONNECTED , \NLW_blk0000014d_DIA<24>_UNCONNECTED , \NLW_blk0000014d_DIA<23>_UNCONNECTED ,
\NLW_blk0000014d_DIA<22>_UNCONNECTED , \NLW_blk0000014d_DIA<21>_UNCONNECTED , \NLW_blk0000014d_DIA<20>_UNCONNECTED ,
\NLW_blk0000014d_DIA<19>_UNCONNECTED , \NLW_blk0000014d_DIA<18>_UNCONNECTED , \NLW_blk0000014d_DIA<17>_UNCONNECTED ,
\NLW_blk0000014d_DIA<16>_UNCONNECTED , \NLW_blk0000014d_DIA<15>_UNCONNECTED , \NLW_blk0000014d_DIA<14>_UNCONNECTED ,
\NLW_blk0000014d_DIA<13>_UNCONNECTED , \NLW_blk0000014d_DIA<12>_UNCONNECTED , \NLW_blk0000014d_DIA<11>_UNCONNECTED ,
\NLW_blk0000014d_DIA<10>_UNCONNECTED , \NLW_blk0000014d_DIA<9>_UNCONNECTED , \NLW_blk0000014d_DIA<8>_UNCONNECTED ,
\NLW_blk0000014d_DIA<7>_UNCONNECTED , \NLW_blk0000014d_DIA<6>_UNCONNECTED , \NLW_blk0000014d_DIA<5>_UNCONNECTED , \NLW_blk0000014d_DIA<4>_UNCONNECTED
, sig00000002, sig00000002, sig00000002, sig00000002})
);
RAMB16BWER #(
.INIT_00 ( 256'h110FEDDCBAA987665432210FFEDCBBA9877654432100FEDCCBA9987655432110 ),
.INIT_01 ( 256'h432100FEDDCBA9987665432210FEEDCBBA9877654332100FEDCCBA9887655432 ),
.INIT_02 ( 256'h654332100FEDCCBA9887655432110FEEDCBAA987665433210FFEDCBBA9887654 ),
.INIT_03 ( 256'h87665432210FEEDCBBA9877654432100FEDCCBA9987655432210FEEDCBAA9877 ),
.INIT_04 ( 256'hA9877654432100FEDDCBA9987665432210FFEDCBBA9877654432100FEDDCBA99 ),
.INIT_05 ( 256'hCBA9987655432210FEEDCBBA9877654432100FEDDCBA9987665432210FEEDCBB ),
.INIT_06 ( 256'hDCCBA9987665432210FFEDCBBA9887654432110FEDDCBAA9877654332100FEDC ),
.INIT_07 ( 256'hFEDCCBA9987655432210FEEDCBBA9887654432110FEDDCBAA9877654332100FE ),
.INIT_08 ( 256'h0FEEDCBAA9877654432110FEDDCBAA9877654332100FEDDCBA9987665433210F ),
.INIT_09 ( 256'h10FEEDCBBA9887655432110FEEDCBBA9887655432110FEEDCBBA987765443211 ),
.INIT_0A ( 256'h110FEEDCBBA9887654432110FEEDCBBA9887655432110FEEDCBBA98876554322 ),
.INIT_0B ( 256'h210FFEDCCBA99876654332100FEDDCBAA9877654332100FEDDCBAA9877654432 ),
.INIT_0C ( 256'h210FFEDCCBA99876654332100FEDDCBAA9877654432110FEEDCBBA9887655432 ),
.INIT_0D ( 256'h100FEDDCBAA9877654432210FFEDCCBA99876654332100FEDDCBAA9887655432 ),
.INIT_0E ( 256'h0FFEDDCBAA9877654432210FFEDCCBA99876654432110FEEDCBBA98876654332 ),
.INIT_0F ( 256'hFEDDCBBA98876554332100FEDDCBAA98876554322100FEDDCBAA988765543221 ),
.INIT_10 ( 256'hDCCBA99877654432210FFEDDCBAA98776554322100FEDDCBAA98876554322100 ),
.INIT_11 ( 256'hBA99876654432210FFEDDCBAA98876554332100FEEDCBBA99876654432110FEE ),
.INIT_12 ( 256'h877654432210FFEDDCBBA98876654432110FFEDCCBAA98876554332100FEEDCB ),
.INIT_13 ( 256'h54322100FEEDCCBA998776554322100FEEDCCBA998776554322100FEEDCBBA99 ),
.INIT_14 ( 256'h10FFEDCCBAA98876654432210FFEDDCBBA998776544322100FEEDCBBA9987765 ),
.INIT_15 ( 256'hCBBA998776554332110FFEDCCBAA988766544322100FEEDCBBA9987765543321 ),
.INIT_16 ( 256'h76554332110FFEEDCCBAA98876654332110FFEDDCBBA998776554332110FFEDD ),
.INIT_17 ( 256'h100FEEDCCBAA988766554332110FFEDDCBBA998776554332110FFEDDCBBA9987 ),
.INIT_18 ( 256'hAA988776554332110FFEEDCCBAA988766544332110FFEDDCBBA9987766544322 ),
.INIT_19 ( 256'h332110FFEDDCCBAA988766554332110FFEEDCCBAA9887765543321100FEEDCCB ),
.INIT_1A ( 256'hBBA9987766544322110FFEDDCCBAA9887765543322100FEEDDCBBA9988766544 ),
.INIT_1B ( 256'h22110FFEEDCCBAA9987766544332110FFEEDCCBBA9987766544332110FFEEDCC ),
.INIT_1C ( 256'h9887665543322110FFEEDCCBBA99887665543322100FEEDDCBBAA98877655443 ),
.INIT_1D ( 256'hFEDDCCBAA99887665543322100FFEEDCCBBA99887665544322110FFEEDCCBBA9 ),
.INIT_1E ( 256'h3322100FFEEDCCBBAA98877665443322100FFEEDCCBBAA98877655443321100F ),
.INIT_1F ( 256'h776655433221100FEEDDCCBAA998877655443321100FFEEDCCBBAA9887766544 ),
.INIT_20 ( 256'hAA9988776654433221100FEEDDCCBBAA988776655433221100FFEDDCCBBAA988 ),
.INIT_21 ( 256'hDCCBBA9988776655443322100FFEEDDCCBBAA988776655443321100FFEEDDCCB ),
.INIT_22 ( 256'hEDDCCBBAA9988776655443322110FFEEDDCCBBAA9988776655433221100FFEED ),
.INIT_23 ( 256'hEEDDCCBBAA99887766554433221100FFEEDDCCBBAA9988776655443322110FFE ),
.INIT_24 ( 256'hEDDCCBBAA998877665544433221100FFEEDDCCBBAA99887766554433221100FF ),
.INIT_25 ( 256'hCCBBAA998877766554433221100FFEEEDDCCBBAA998877665544433221100FFE ),
.INIT_26 ( 256'hA9988776665544332211100FFEEDDCCBBBAA998877665554433221100FFFEEDD ),
.INIT_27 ( 256'h665544333221100FFFEEDDCCCBBAA9988877665544433221100FFFEEDDCCBBBA ),
.INIT_28 ( 256'h11100FFFEEDDCCCBBAA999887766655443332211000FFEEDDDCCBBAAA9988776 ),
.INIT_29 ( 256'hCBBBAA9998877766555443322211000FFEEEDDCCBBBAA9998877766554443322 ),
.INIT_2A ( 256'h554443322211100FFFEEDDDCCBBBAA9998877766555443332211100FFFEEDDDC ),
.INIT_2B ( 256'hDDDCCCBBAAA999887776665544433322111000FFEEEDDCCCBBBAA99988777666 ),
.INIT_2C ( 256'h544433222111000FFFEEDDDCCCBBBAA9998887776655544433322111000FFFEE ),
.INIT_2D ( 256'hBAAA99988877766655544433222111000FFFEEEDDDCCCBBBAA99988877766655 ),
.INIT_2E ( 256'h0FFFEEEDDDCCCBBBAAA9998888777666555444333222111000FFFEEEDDDCCCBB ),
.INIT_2F ( 256'h3332222111000FFFFEEEDDDCCCBBBBAAA9998887776666555444333222111100 ),
.INIT_30 ( 256'h66555544433332221111000FFFFEEEDDDDCCCBBBBAAA99988887776665555444 ),
.INIT_31 ( 256'h877776665555444433322221111000FFFFEEEEDDDCCCCBBBBAAA999988877776 ),
.INIT_32 ( 256'h8877776666555544443333222211110000FFFFEEEEDDDDCCCCBBBAAAA9999888 ),
.INIT_33 ( 256'h777666665555444433332222211110000FFFFEEEEEDDDDCCCCBBBBAAAA999988 ),
.INIT_34 ( 256'h555444443333322222111100000FFFFEEEEEDDDDDCCCCBBBBBAAAA9999888887 ),
.INIT_35 ( 256'h2221111100000FFFFFEEEEEDDDDDCCCCCBBBBBAAAAA999998888877777666665 ),
.INIT_36 ( 256'hEDDDDDDCCCCCBBBBBBAAAAAA9999988888877777666666555554444433333322 ),
.INIT_37 ( 256'h88887777776666665555555444444333333222222111111000000FFFFFFEEEEE ),
.INIT_38 ( 256'h1111110000000FFFFFFFEEEEEEEDDDDDDDCCCCCCCBBBBBBBAAAAAA9999999888 ),
.INIT_39 ( 256'h9999998888888887777777766666666555555554444444433333333222222211 ),
.INIT_3A ( 256'h00000FFFFFFFFFFEEEEEEEEEEDDDDDDDDDDCCCCCCCCCBBBBBBBBBAAAAAAAAA99 ),
.INIT_3B ( 256'h6555555555555444444444444333333333333222222222221111111111100000 ),
.INIT_3C ( 256'hAAAAAA9999999999999999888888888888888777777777777776666666666666 ),
.INIT_3D ( 256'hDDDDDDDDDDDCCCCCCCCCCCCCCCCCCCCCCBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAA ),
.INIT_3E ( 256'hFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDD ),
.INIT_3F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 4 ),
.DATA_WIDTH_B ( 4 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
blk0000014e (
.REGCEA(sig00000002),
.CLKA(clk),
.ENB(sig00000001),
.RSTB(sig00000002),
.CLKB(clk),
.REGCEB(sig00000002),
.RSTA(sig00000002),
.ENA(sig00000001),
.DIPA({\NLW_blk0000014e_DIPA<3>_UNCONNECTED , \NLW_blk0000014e_DIPA<2>_UNCONNECTED , \NLW_blk0000014e_DIPA<1>_UNCONNECTED ,
\NLW_blk0000014e_DIPA<0>_UNCONNECTED }),
.WEA({sig00000002, sig00000002, sig00000002, sig00000002}),
.DOA({\NLW_blk0000014e_DOA<31>_UNCONNECTED , \NLW_blk0000014e_DOA<30>_UNCONNECTED , \NLW_blk0000014e_DOA<29>_UNCONNECTED ,
\NLW_blk0000014e_DOA<28>_UNCONNECTED , \NLW_blk0000014e_DOA<27>_UNCONNECTED , \NLW_blk0000014e_DOA<26>_UNCONNECTED ,
\NLW_blk0000014e_DOA<25>_UNCONNECTED , \NLW_blk0000014e_DOA<24>_UNCONNECTED , \NLW_blk0000014e_DOA<23>_UNCONNECTED ,
\NLW_blk0000014e_DOA<22>_UNCONNECTED , \NLW_blk0000014e_DOA<21>_UNCONNECTED , \NLW_blk0000014e_DOA<20>_UNCONNECTED ,
\NLW_blk0000014e_DOA<19>_UNCONNECTED , \NLW_blk0000014e_DOA<18>_UNCONNECTED , \NLW_blk0000014e_DOA<17>_UNCONNECTED ,
\NLW_blk0000014e_DOA<16>_UNCONNECTED , \NLW_blk0000014e_DOA<15>_UNCONNECTED , \NLW_blk0000014e_DOA<14>_UNCONNECTED ,
\NLW_blk0000014e_DOA<13>_UNCONNECTED , \NLW_blk0000014e_DOA<12>_UNCONNECTED , \NLW_blk0000014e_DOA<11>_UNCONNECTED ,
\NLW_blk0000014e_DOA<10>_UNCONNECTED , \NLW_blk0000014e_DOA<9>_UNCONNECTED , \NLW_blk0000014e_DOA<8>_UNCONNECTED ,
\NLW_blk0000014e_DOA<7>_UNCONNECTED , \NLW_blk0000014e_DOA<6>_UNCONNECTED , \NLW_blk0000014e_DOA<5>_UNCONNECTED , \NLW_blk0000014e_DOA<4>_UNCONNECTED
, sig000000d9, sig000000d8, sig000000d7, sig000000d6}),
.ADDRA({sig000000c2, sig000000c1, sig000000c0, sig000000bf, sig000000be, sig000000bd, sig000000bc, sig000000bb, sig000000ba, sig000000b9,
sig000000b8, sig000000b7, \NLW_blk0000014e_ADDRA<1>_UNCONNECTED , \NLW_blk0000014e_ADDRA<0>_UNCONNECTED }),
.ADDRB({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, \NLW_blk0000014e_ADDRB<1>_UNCONNECTED , \NLW_blk0000014e_ADDRB<0>_UNCONNECTED }),
.DIB({\NLW_blk0000014e_DIB<31>_UNCONNECTED , \NLW_blk0000014e_DIB<30>_UNCONNECTED , \NLW_blk0000014e_DIB<29>_UNCONNECTED ,
\NLW_blk0000014e_DIB<28>_UNCONNECTED , \NLW_blk0000014e_DIB<27>_UNCONNECTED , \NLW_blk0000014e_DIB<26>_UNCONNECTED ,
\NLW_blk0000014e_DIB<25>_UNCONNECTED , \NLW_blk0000014e_DIB<24>_UNCONNECTED , \NLW_blk0000014e_DIB<23>_UNCONNECTED ,
\NLW_blk0000014e_DIB<22>_UNCONNECTED , \NLW_blk0000014e_DIB<21>_UNCONNECTED , \NLW_blk0000014e_DIB<20>_UNCONNECTED ,
\NLW_blk0000014e_DIB<19>_UNCONNECTED , \NLW_blk0000014e_DIB<18>_UNCONNECTED , \NLW_blk0000014e_DIB<17>_UNCONNECTED ,
\NLW_blk0000014e_DIB<16>_UNCONNECTED , \NLW_blk0000014e_DIB<15>_UNCONNECTED , \NLW_blk0000014e_DIB<14>_UNCONNECTED ,
\NLW_blk0000014e_DIB<13>_UNCONNECTED , \NLW_blk0000014e_DIB<12>_UNCONNECTED , \NLW_blk0000014e_DIB<11>_UNCONNECTED ,
\NLW_blk0000014e_DIB<10>_UNCONNECTED , \NLW_blk0000014e_DIB<9>_UNCONNECTED , \NLW_blk0000014e_DIB<8>_UNCONNECTED ,
\NLW_blk0000014e_DIB<7>_UNCONNECTED , \NLW_blk0000014e_DIB<6>_UNCONNECTED , \NLW_blk0000014e_DIB<5>_UNCONNECTED , \NLW_blk0000014e_DIB<4>_UNCONNECTED
, \NLW_blk0000014e_DIB<3>_UNCONNECTED , \NLW_blk0000014e_DIB<2>_UNCONNECTED , \NLW_blk0000014e_DIB<1>_UNCONNECTED ,
\NLW_blk0000014e_DIB<0>_UNCONNECTED }),
.DOPA({\NLW_blk0000014e_DOPA<3>_UNCONNECTED , \NLW_blk0000014e_DOPA<2>_UNCONNECTED , \NLW_blk0000014e_DOPA<1>_UNCONNECTED ,
\NLW_blk0000014e_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk0000014e_DIPB<3>_UNCONNECTED , \NLW_blk0000014e_DIPB<2>_UNCONNECTED , \NLW_blk0000014e_DIPB<1>_UNCONNECTED ,
\NLW_blk0000014e_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk0000014e_DOPB<3>_UNCONNECTED , \NLW_blk0000014e_DOPB<2>_UNCONNECTED , \NLW_blk0000014e_DOPB<1>_UNCONNECTED ,
\NLW_blk0000014e_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk0000014e_DOB<31>_UNCONNECTED , \NLW_blk0000014e_DOB<30>_UNCONNECTED , \NLW_blk0000014e_DOB<29>_UNCONNECTED ,
\NLW_blk0000014e_DOB<28>_UNCONNECTED , \NLW_blk0000014e_DOB<27>_UNCONNECTED , \NLW_blk0000014e_DOB<26>_UNCONNECTED ,
\NLW_blk0000014e_DOB<25>_UNCONNECTED , \NLW_blk0000014e_DOB<24>_UNCONNECTED , \NLW_blk0000014e_DOB<23>_UNCONNECTED ,
\NLW_blk0000014e_DOB<22>_UNCONNECTED , \NLW_blk0000014e_DOB<21>_UNCONNECTED , \NLW_blk0000014e_DOB<20>_UNCONNECTED ,
\NLW_blk0000014e_DOB<19>_UNCONNECTED , \NLW_blk0000014e_DOB<18>_UNCONNECTED , \NLW_blk0000014e_DOB<17>_UNCONNECTED ,
\NLW_blk0000014e_DOB<16>_UNCONNECTED , \NLW_blk0000014e_DOB<15>_UNCONNECTED , \NLW_blk0000014e_DOB<14>_UNCONNECTED ,
\NLW_blk0000014e_DOB<13>_UNCONNECTED , \NLW_blk0000014e_DOB<12>_UNCONNECTED , \NLW_blk0000014e_DOB<11>_UNCONNECTED ,
\NLW_blk0000014e_DOB<10>_UNCONNECTED , \NLW_blk0000014e_DOB<9>_UNCONNECTED , \NLW_blk0000014e_DOB<8>_UNCONNECTED ,
\NLW_blk0000014e_DOB<7>_UNCONNECTED , \NLW_blk0000014e_DOB<6>_UNCONNECTED , \NLW_blk0000014e_DOB<5>_UNCONNECTED , \NLW_blk0000014e_DOB<4>_UNCONNECTED
, sig000000ca, sig000000c9, sig000000c8, sig000000c7}),
.WEB({sig00000002, sig00000002, sig00000002, sig00000002}),
.DIA({\NLW_blk0000014e_DIA<31>_UNCONNECTED , \NLW_blk0000014e_DIA<30>_UNCONNECTED , \NLW_blk0000014e_DIA<29>_UNCONNECTED ,
\NLW_blk0000014e_DIA<28>_UNCONNECTED , \NLW_blk0000014e_DIA<27>_UNCONNECTED , \NLW_blk0000014e_DIA<26>_UNCONNECTED ,
\NLW_blk0000014e_DIA<25>_UNCONNECTED , \NLW_blk0000014e_DIA<24>_UNCONNECTED , \NLW_blk0000014e_DIA<23>_UNCONNECTED ,
\NLW_blk0000014e_DIA<22>_UNCONNECTED , \NLW_blk0000014e_DIA<21>_UNCONNECTED , \NLW_blk0000014e_DIA<20>_UNCONNECTED ,
\NLW_blk0000014e_DIA<19>_UNCONNECTED , \NLW_blk0000014e_DIA<18>_UNCONNECTED , \NLW_blk0000014e_DIA<17>_UNCONNECTED ,
\NLW_blk0000014e_DIA<16>_UNCONNECTED , \NLW_blk0000014e_DIA<15>_UNCONNECTED , \NLW_blk0000014e_DIA<14>_UNCONNECTED ,
\NLW_blk0000014e_DIA<13>_UNCONNECTED , \NLW_blk0000014e_DIA<12>_UNCONNECTED , \NLW_blk0000014e_DIA<11>_UNCONNECTED ,
\NLW_blk0000014e_DIA<10>_UNCONNECTED , \NLW_blk0000014e_DIA<9>_UNCONNECTED , \NLW_blk0000014e_DIA<8>_UNCONNECTED ,
\NLW_blk0000014e_DIA<7>_UNCONNECTED , \NLW_blk0000014e_DIA<6>_UNCONNECTED , \NLW_blk0000014e_DIA<5>_UNCONNECTED , \NLW_blk0000014e_DIA<4>_UNCONNECTED
, sig00000002, sig00000002, sig00000002, sig00000002})
);
RAMB16BWER #(
.INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_05 ( 256'h1111111111111111111111111111111111111111111111111111111110000000 ),
.INIT_06 ( 256'h1111111111111111111111111111111111111111111111111111111111111111 ),
.INIT_07 ( 256'h1111111111111111111111111111111111111111111111111111111111111111 ),
.INIT_08 ( 256'h1111111111111111111111111111111111111111111111111111111111111111 ),
.INIT_09 ( 256'h1111111111111111111111111111111111111111111111111111111111111111 ),
.INIT_0A ( 256'h2222222222222222222222222222222222222222222221111111111111111111 ),
.INIT_0B ( 256'h2222222222222222222222222222222222222222222222222222222222222222 ),
.INIT_0C ( 256'h2222222222222222222222222222222222222222222222222222222222222222 ),
.INIT_0D ( 256'h2222222222222222222222222222222222222222222222222222222222222222 ),
.INIT_0E ( 256'h2222222222222222222222222222222222222222222222222222222222222222 ),
.INIT_0F ( 256'h3333333333333333333333222222222222222222222222222222222222222222 ),
.INIT_10 ( 256'h3333333333333333333333333333333333333333333333333333333333333333 ),
.INIT_11 ( 256'h3333333333333333333333333333333333333333333333333333333333333333 ),
.INIT_12 ( 256'h3333333333333333333333333333333333333333333333333333333333333333 ),
.INIT_13 ( 256'h3333333333333333333333333333333333333333333333333333333333333333 ),
.INIT_14 ( 256'h3333333333333333333333333333333333333333333333333333333333333333 ),
.INIT_15 ( 256'h4444444444444444444444444444444444444444444333333333333333333333 ),
.INIT_16 ( 256'h4444444444444444444444444444444444444444444444444444444444444444 ),
.INIT_17 ( 256'h4444444444444444444444444444444444444444444444444444444444444444 ),
.INIT_18 ( 256'h4444444444444444444444444444444444444444444444444444444444444444 ),
.INIT_19 ( 256'h4444444444444444444444444444444444444444444444444444444444444444 ),
.INIT_1A ( 256'h4444444444444444444444444444444444444444444444444444444444444444 ),
.INIT_1B ( 256'h5555555555555555555555555555555444444444444444444444444444444444 ),
.INIT_1C ( 256'h5555555555555555555555555555555555555555555555555555555555555555 ),
.INIT_1D ( 256'h5555555555555555555555555555555555555555555555555555555555555555 ),
.INIT_1E ( 256'h5555555555555555555555555555555555555555555555555555555555555555 ),
.INIT_1F ( 256'h5555555555555555555555555555555555555555555555555555555555555555 ),
.INIT_20 ( 256'h5555555555555555555555555555555555555555555555555555555555555555 ),
.INIT_21 ( 256'h5555555555555555555555555555555555555555555555555555555555555555 ),
.INIT_22 ( 256'h6666666666666666666666666666555555555555555555555555555555555555 ),
.INIT_23 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_24 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_25 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_26 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_27 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_28 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_29 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_2A ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_2B ( 256'h7777777777777777777777777777777777777766666666666666666666666666 ),
.INIT_2C ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_2D ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_2E ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_2F ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_30 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_31 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_32 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_33 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_34 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_35 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_36 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_37 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_38 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_39 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_3A ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_3B ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_3C ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_3D ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_3E ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_3F ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_A ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 4 ),
.DATA_WIDTH_B ( 4 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_B ( 36'h000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
blk0000014f (
.REGCEA(sig00000002),
.CLKA(clk),
.ENB(sig00000001),
.RSTB(sig00000002),
.CLKB(clk),
.REGCEB(sig00000002),
.RSTA(sig00000002),
.ENA(sig00000001),
.DIPA({\NLW_blk0000014f_DIPA<3>_UNCONNECTED , \NLW_blk0000014f_DIPA<2>_UNCONNECTED , \NLW_blk0000014f_DIPA<1>_UNCONNECTED ,
\NLW_blk0000014f_DIPA<0>_UNCONNECTED }),
.WEA({sig00000002, sig00000002, sig00000002, sig00000002}),
.DOA({\NLW_blk0000014f_DOA<31>_UNCONNECTED , \NLW_blk0000014f_DOA<30>_UNCONNECTED , \NLW_blk0000014f_DOA<29>_UNCONNECTED ,
\NLW_blk0000014f_DOA<28>_UNCONNECTED , \NLW_blk0000014f_DOA<27>_UNCONNECTED , \NLW_blk0000014f_DOA<26>_UNCONNECTED ,
\NLW_blk0000014f_DOA<25>_UNCONNECTED , \NLW_blk0000014f_DOA<24>_UNCONNECTED , \NLW_blk0000014f_DOA<23>_UNCONNECTED ,
\NLW_blk0000014f_DOA<22>_UNCONNECTED , \NLW_blk0000014f_DOA<21>_UNCONNECTED , \NLW_blk0000014f_DOA<20>_UNCONNECTED ,
\NLW_blk0000014f_DOA<19>_UNCONNECTED , \NLW_blk0000014f_DOA<18>_UNCONNECTED , \NLW_blk0000014f_DOA<17>_UNCONNECTED ,
\NLW_blk0000014f_DOA<16>_UNCONNECTED , \NLW_blk0000014f_DOA<15>_UNCONNECTED , \NLW_blk0000014f_DOA<14>_UNCONNECTED ,
\NLW_blk0000014f_DOA<13>_UNCONNECTED , \NLW_blk0000014f_DOA<12>_UNCONNECTED , \NLW_blk0000014f_DOA<11>_UNCONNECTED ,
\NLW_blk0000014f_DOA<10>_UNCONNECTED , \NLW_blk0000014f_DOA<9>_UNCONNECTED , \NLW_blk0000014f_DOA<8>_UNCONNECTED ,
\NLW_blk0000014f_DOA<7>_UNCONNECTED , \NLW_blk0000014f_DOA<6>_UNCONNECTED , \NLW_blk0000014f_DOA<5>_UNCONNECTED , \NLW_blk0000014f_DOA<4>_UNCONNECTED
, \NLW_blk0000014f_DOA<3>_UNCONNECTED , sig000000e0, sig000000df, sig000000de}),
.ADDRA({sig000000c2, sig000000c1, sig000000c0, sig000000bf, sig000000be, sig000000bd, sig000000bc, sig000000bb, sig000000ba, sig000000b9,
sig000000b8, sig000000b7, \NLW_blk0000014f_ADDRA<1>_UNCONNECTED , \NLW_blk0000014f_ADDRA<0>_UNCONNECTED }),
.ADDRB({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, \NLW_blk0000014f_ADDRB<1>_UNCONNECTED , \NLW_blk0000014f_ADDRB<0>_UNCONNECTED }),
.DIB({\NLW_blk0000014f_DIB<31>_UNCONNECTED , \NLW_blk0000014f_DIB<30>_UNCONNECTED , \NLW_blk0000014f_DIB<29>_UNCONNECTED ,
\NLW_blk0000014f_DIB<28>_UNCONNECTED , \NLW_blk0000014f_DIB<27>_UNCONNECTED , \NLW_blk0000014f_DIB<26>_UNCONNECTED ,
\NLW_blk0000014f_DIB<25>_UNCONNECTED , \NLW_blk0000014f_DIB<24>_UNCONNECTED , \NLW_blk0000014f_DIB<23>_UNCONNECTED ,
\NLW_blk0000014f_DIB<22>_UNCONNECTED , \NLW_blk0000014f_DIB<21>_UNCONNECTED , \NLW_blk0000014f_DIB<20>_UNCONNECTED ,
\NLW_blk0000014f_DIB<19>_UNCONNECTED , \NLW_blk0000014f_DIB<18>_UNCONNECTED , \NLW_blk0000014f_DIB<17>_UNCONNECTED ,
\NLW_blk0000014f_DIB<16>_UNCONNECTED , \NLW_blk0000014f_DIB<15>_UNCONNECTED , \NLW_blk0000014f_DIB<14>_UNCONNECTED ,
\NLW_blk0000014f_DIB<13>_UNCONNECTED , \NLW_blk0000014f_DIB<12>_UNCONNECTED , \NLW_blk0000014f_DIB<11>_UNCONNECTED ,
\NLW_blk0000014f_DIB<10>_UNCONNECTED , \NLW_blk0000014f_DIB<9>_UNCONNECTED , \NLW_blk0000014f_DIB<8>_UNCONNECTED ,
\NLW_blk0000014f_DIB<7>_UNCONNECTED , \NLW_blk0000014f_DIB<6>_UNCONNECTED , \NLW_blk0000014f_DIB<5>_UNCONNECTED , \NLW_blk0000014f_DIB<4>_UNCONNECTED
, \NLW_blk0000014f_DIB<3>_UNCONNECTED , \NLW_blk0000014f_DIB<2>_UNCONNECTED , \NLW_blk0000014f_DIB<1>_UNCONNECTED ,
\NLW_blk0000014f_DIB<0>_UNCONNECTED }),
.DOPA({\NLW_blk0000014f_DOPA<3>_UNCONNECTED , \NLW_blk0000014f_DOPA<2>_UNCONNECTED , \NLW_blk0000014f_DOPA<1>_UNCONNECTED ,
\NLW_blk0000014f_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk0000014f_DIPB<3>_UNCONNECTED , \NLW_blk0000014f_DIPB<2>_UNCONNECTED , \NLW_blk0000014f_DIPB<1>_UNCONNECTED ,
\NLW_blk0000014f_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk0000014f_DOPB<3>_UNCONNECTED , \NLW_blk0000014f_DOPB<2>_UNCONNECTED , \NLW_blk0000014f_DOPB<1>_UNCONNECTED ,
\NLW_blk0000014f_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk0000014f_DOB<31>_UNCONNECTED , \NLW_blk0000014f_DOB<30>_UNCONNECTED , \NLW_blk0000014f_DOB<29>_UNCONNECTED ,
\NLW_blk0000014f_DOB<28>_UNCONNECTED , \NLW_blk0000014f_DOB<27>_UNCONNECTED , \NLW_blk0000014f_DOB<26>_UNCONNECTED ,
\NLW_blk0000014f_DOB<25>_UNCONNECTED , \NLW_blk0000014f_DOB<24>_UNCONNECTED , \NLW_blk0000014f_DOB<23>_UNCONNECTED ,
\NLW_blk0000014f_DOB<22>_UNCONNECTED , \NLW_blk0000014f_DOB<21>_UNCONNECTED , \NLW_blk0000014f_DOB<20>_UNCONNECTED ,
\NLW_blk0000014f_DOB<19>_UNCONNECTED , \NLW_blk0000014f_DOB<18>_UNCONNECTED , \NLW_blk0000014f_DOB<17>_UNCONNECTED ,
\NLW_blk0000014f_DOB<16>_UNCONNECTED , \NLW_blk0000014f_DOB<15>_UNCONNECTED , \NLW_blk0000014f_DOB<14>_UNCONNECTED ,
\NLW_blk0000014f_DOB<13>_UNCONNECTED , \NLW_blk0000014f_DOB<12>_UNCONNECTED , \NLW_blk0000014f_DOB<11>_UNCONNECTED ,
\NLW_blk0000014f_DOB<10>_UNCONNECTED , \NLW_blk0000014f_DOB<9>_UNCONNECTED , \NLW_blk0000014f_DOB<8>_UNCONNECTED ,
\NLW_blk0000014f_DOB<7>_UNCONNECTED , \NLW_blk0000014f_DOB<6>_UNCONNECTED , \NLW_blk0000014f_DOB<5>_UNCONNECTED , \NLW_blk0000014f_DOB<4>_UNCONNECTED
, \NLW_blk0000014f_DOB<3>_UNCONNECTED , sig000000d1, sig000000d0, sig000000cf}),
.WEB({sig00000002, sig00000002, sig00000002, sig00000002}),
.DIA({\NLW_blk0000014f_DIA<31>_UNCONNECTED , \NLW_blk0000014f_DIA<30>_UNCONNECTED , \NLW_blk0000014f_DIA<29>_UNCONNECTED ,
\NLW_blk0000014f_DIA<28>_UNCONNECTED , \NLW_blk0000014f_DIA<27>_UNCONNECTED , \NLW_blk0000014f_DIA<26>_UNCONNECTED ,
\NLW_blk0000014f_DIA<25>_UNCONNECTED , \NLW_blk0000014f_DIA<24>_UNCONNECTED , \NLW_blk0000014f_DIA<23>_UNCONNECTED ,
\NLW_blk0000014f_DIA<22>_UNCONNECTED , \NLW_blk0000014f_DIA<21>_UNCONNECTED , \NLW_blk0000014f_DIA<20>_UNCONNECTED ,
\NLW_blk0000014f_DIA<19>_UNCONNECTED , \NLW_blk0000014f_DIA<18>_UNCONNECTED , \NLW_blk0000014f_DIA<17>_UNCONNECTED ,
\NLW_blk0000014f_DIA<16>_UNCONNECTED , \NLW_blk0000014f_DIA<15>_UNCONNECTED , \NLW_blk0000014f_DIA<14>_UNCONNECTED ,
\NLW_blk0000014f_DIA<13>_UNCONNECTED , \NLW_blk0000014f_DIA<12>_UNCONNECTED , \NLW_blk0000014f_DIA<11>_UNCONNECTED ,
\NLW_blk0000014f_DIA<10>_UNCONNECTED , \NLW_blk0000014f_DIA<9>_UNCONNECTED , \NLW_blk0000014f_DIA<8>_UNCONNECTED ,
\NLW_blk0000014f_DIA<7>_UNCONNECTED , \NLW_blk0000014f_DIA<6>_UNCONNECTED , \NLW_blk0000014f_DIA<5>_UNCONNECTED , \NLW_blk0000014f_DIA<4>_UNCONNECTED
, sig00000002, sig00000002, sig00000002, sig00000002})
);
RAMB16BWER #(
.INIT_00 ( 256'hE158CF269D047BE158CF369D047BE258CF36AD047BE258CF36AD147BE259CF36 ),
.INIT_01 ( 256'h158CF36AD147BE259C036AD148BF259C037AE148BF269C037AE158BF269D047A ),
.INIT_02 ( 256'h48BF259C037AE158CF369D047BE259C036AD148BF269C037AE158CF269D047BE ),
.INIT_03 ( 256'h59C037AE158CF36AD148BF269D047BE158CF36AD148BF269D047BE158CF36AD1 ),
.INIT_04 ( 256'h58CF36AD148BF26AD148BF269D047BE259C037AE158CF36AD148BF269D047BE2 ),
.INIT_05 ( 256'h259C037BE259C037BE259C037BE259C037BE259C037AE259C037AE158CF37AE1 ),
.INIT_06 ( 256'hCF36AE158C037BE259D047BF269D148BF36AD148CF36AE158C037AE159C037AE ),
.INIT_07 ( 256'h26AD158C037BE269D148BF36AE159C047BF26AD148CF37AE259C047BF269D148 ),
.INIT_08 ( 256'h59C048BF37AE259D148C037BE26AD158C037BF26AD158C047BF26AD158C037BE ),
.INIT_09 ( 256'h37BF36AE269D159C048CF37BF26AE159D148C037BF26AE159D048CF37BE26AD1 ),
.INIT_0A ( 256'hD159D048C048C037BF37BE26AE269D159D148C048BF37BF26AE269D159D048C0 ),
.INIT_0B ( 256'h159D159D159D159D159D159D048C048C048C048BF37BF37BF36AE26AE26AD159 ),
.INIT_0C ( 256'h048C049D159D159D159D159D159D159E26AE26AE26AE26AE26AE26AE26AE26AD ),
.INIT_0D ( 256'h9D159D26AE26BF37BF38C048C049D159D15AE26AE26AE37BF37BF37B048C048C ),
.INIT_0E ( 256'hAF37C048D159E26AF37B048C159D16AE27BF37C048D159D26AE26BF37B048C04 ),
.INIT_0F ( 256'h5AE27B048D15AE27B048D15AE27BF48C159E26BF38C059D26AE37B048C159E26 ),
.INIT_10 ( 256'h8D16AF38C15AE37C059E27B049D16AF38C15AE27B049D16AF38C059E26BF48C1 ),
.INIT_11 ( 256'h48D26BF49D27B049E27B059E27C059E27C059E27C059E27B059E27B049D26BF4 ),
.INIT_12 ( 256'h6B059E38C16BF49E27C15AF48D26B059E37C16AF48D26B049E27C05AE38C16AF ),
.INIT_13 ( 256'h05AF49E38C16B05AF48D27C16AF49E38C16B059E38D26B05AE38D26B05AE38D2 ),
.INIT_14 ( 256'h16B05AF49E38D28D27C16B05AF49E38D27C16B05AF48D27C16B05AF49E38D16B ),
.INIT_15 ( 256'h8D27D27C17C16B16B05A05AF49F49E38E38D27C17C16B05AF5AF49E38D27D27C ),
.INIT_16 ( 256'h4AF5AF5AF5AF5A05A05A05A05A05AF5AF5AF5AF4AF4AF49F49E49E39E38E38D2 ),
.INIT_17 ( 256'h7C27D28D38E39F4AF5A05B06B16B16C17C27D28D28D38E39E39E49E49F49F4AF ),
.INIT_18 ( 256'hE49F5A06C17D28E39F4A05B16C27D38E49F4A05B16C17D28D39E49F5A05B06B1 ),
.INIT_19 ( 256'hA05B17D39F5A06C28E39F5B17C28E4AF5B17C28E49F5B16C28D39F4A06B17D28 ),
.INIT_1A ( 256'hA06C28E4A07D39F5B17D39F5B17D39F5B17D39F5B17D39F5B17D38E4A06C28E4 ),
.INIT_1B ( 256'hE4A17D3A06C39F5C28E5B17D4A06C39F5B28E4A07D39F5C28E4A07D39F5B17E4 ),
.INIT_1C ( 256'h5C29F5C29F6C3906C3906D3906D3906D3906C3906C39F6C29F5C28F5B28E5B17 ),
.INIT_1D ( 256'h06D4A18E5C2906D4A18E5B29F6C3A07D4B18E5B29F6C3906D3A17E4B18E5B28F ),
.INIT_1E ( 256'hD4B28F6D4B29F6D4B29F6D4B28F6D4A18F6C3A17E5C2907D4B28F6D3A17E5C29 ),
.INIT_1F ( 256'hD4B2907E5C4B2907E5C3A18F6D4B2907E6D3A18F6D4B2907E5C3A18F6D3A18F6 ),
.INIT_20 ( 256'hE6D4C3A2908F6D5C3B2908F6D5C3A2907E6D4B3A18F6E5C3A2907E5C4B2907E6 ),
.INIT_21 ( 256'h291808F7E6D5C4B3A291807F6E5D4C3A291807E6D5C4B2A1907F6D5C4B2A1807 ),
.INIT_22 ( 256'h7E6E6E5D5D4C4C3B3B2A29191808F7F6E6D5D4C4B3B2A291808F7E6E5D4C4B3A ),
.INIT_23 ( 256'hC4D5D5D5D5D5D5C4C4C4C4C4C4C4C4C4B3B3B3B3B2A2A2A29191919080807F7F ),
.INIT_24 ( 256'h3B4C4C5D5D6E6E6F7F7F808081919192A2A2A2B3B3B3B3B3C4C4C4C4C4C4C4C4 ),
.INIT_25 ( 256'hA3B4C5D6E7F808192A3B4C5D5E6F7F809192A2B3C4C5D5E6E7F70809191A2A3B ),
.INIT_26 ( 256'h1A3C4D6F7092A3C4D6E7091A3B4D5E6F8092A3C4D5E7F8091A3B4C5D6E708192 ),
.INIT_27 ( 256'h81A3C5E7092B4D6F81A3C5E7092A3C5E7092A3C5E7081A3C5D6F81A2B4D6E709 ),
.INIT_28 ( 256'hF82B4D7092C5E71A3C5F81A3D6F81A4D6F81A4D6F81A3C5F81A3C5E7092B4D6F ),
.INIT_29 ( 256'h5F82B5E81B4E71A4D70A3C6F92C5F81B4E70A3D6F92B5E71A4D6092B5E71A3D6 ),
.INIT_2A ( 256'hA4E81B5F82C6093D70A4D71B4E81B5E82B5F82C5F92C6F92C6F92C6F92C5F82C ),
.INIT_2B ( 256'hE82C60A4F93D71B5F93D71B5F93D60A4E82C60A4E81B5F93D71A4E82C5F93D70 ),
.INIT_2C ( 256'h1B50A4F93E82C71B60A4F93D82C61B5FA4E82D71B5FA4E82C61B5F93D72C60A4 ),
.INIT_2D ( 256'h1C71C61C61B61B60B50B50A5FA4F94E93E83D82D71C61B60A5FA4E93E82D71C6 ),
.INIT_2E ( 256'h0B61C72D82D83E94E94FA4FA50B50B60B61B61C61C71C71C72C72C72C72C72C7 ),
.INIT_2F ( 256'hD94FA50C72D83FA50B61C73E94FA50B61C72D83E94FA50B61C72D83E94FA50B6 ),
.INIT_30 ( 256'h84FB62D84FB62D84FB61D84FA61C83EA50C72E940B61D83FA50C72D94FA51C72 ),
.INIT_31 ( 256'h1C840B73EA62D950C84FB72EA51D84FB72E951C83FB62D940C73EA51C83FA61D ),
.INIT_32 ( 256'h62EA62FB73FB73FB73FB62EA62EA62EA62E951D951D840C840B73FB62EA61D95 ),
.INIT_33 ( 256'h962EB730C851D962EB73FC840D951DA62EB73FB740C840D951D951DA62EA62EA ),
.INIT_34 ( 256'h963FC952EB841DA730C952FB841DA63FC851EA730C851EA730C851EA63FB841D ),
.INIT_35 ( 256'h730DA741EB852EB852FC852FC952FC962FC952FC952FC852EB851EB741DA730D ),
.INIT_36 ( 256'h0EB8530DA752FC9741EB8630DA741FC9630DA741FC9630DA741EB852FC9630DA ),
.INIT_37 ( 256'h7520DB8631EC9742FDA8530DB8631EB9641EC9741FC9741FC9741FC9641EB963 ),
.INIT_38 ( 256'hB86420EB97530ECA8531FCA8631FCA8631FCA8531ECA7530EB9742FDB8631FCA ),
.INIT_39 ( 256'hA97531FDCA86420ECA86531FDB97531FDB97531FDB97530ECA86420EC97531FD ),
.INIT_3A ( 256'h75421FDCA976421FECA975420FDBA865310ECB975420EDB976420EDB975420EC ),
.INIT_3B ( 256'h0EDCB98764320FEDBA9765321FEDBA8764310FDCA9865320FDCA9764310EDBA8 ),
.INIT_3C ( 256'h543210FEDCBA9876543210FEDCBA987654210FEDCBA87654320FEDCB98765321 ),
.INIT_3D ( 256'h66544322100FEEDCCBAA9877655432110FEEDCBAA987655432100FEDCBA98876 ),
.INIT_3E ( 256'h44333222111000FFEEEDDCCCBBAA998887766554433221100FEEDDCCBAA99877 ),
.INIT_3F ( 256'hEEEEEEEEEEEEEEDDDDDDDDDDDCCCCCCCBBBBBBAAAAA999998888777766655554 ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 4 ),
.DATA_WIDTH_B ( 4 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
blk00000150 (
.REGCEA(sig00000002),
.CLKA(clk),
.ENB(sig00000001),
.RSTB(sig00000002),
.CLKB(clk),
.REGCEB(sig00000002),
.RSTA(sig00000002),
.ENA(sig00000001),
.DIPA({\NLW_blk00000150_DIPA<3>_UNCONNECTED , \NLW_blk00000150_DIPA<2>_UNCONNECTED , \NLW_blk00000150_DIPA<1>_UNCONNECTED ,
\NLW_blk00000150_DIPA<0>_UNCONNECTED }),
.WEA({sig00000002, sig00000002, sig00000002, sig00000002}),
.DOA({\NLW_blk00000150_DOA<31>_UNCONNECTED , \NLW_blk00000150_DOA<30>_UNCONNECTED , \NLW_blk00000150_DOA<29>_UNCONNECTED ,
\NLW_blk00000150_DOA<28>_UNCONNECTED , \NLW_blk00000150_DOA<27>_UNCONNECTED , \NLW_blk00000150_DOA<26>_UNCONNECTED ,
\NLW_blk00000150_DOA<25>_UNCONNECTED , \NLW_blk00000150_DOA<24>_UNCONNECTED , \NLW_blk00000150_DOA<23>_UNCONNECTED ,
\NLW_blk00000150_DOA<22>_UNCONNECTED , \NLW_blk00000150_DOA<21>_UNCONNECTED , \NLW_blk00000150_DOA<20>_UNCONNECTED ,
\NLW_blk00000150_DOA<19>_UNCONNECTED , \NLW_blk00000150_DOA<18>_UNCONNECTED , \NLW_blk00000150_DOA<17>_UNCONNECTED ,
\NLW_blk00000150_DOA<16>_UNCONNECTED , \NLW_blk00000150_DOA<15>_UNCONNECTED , \NLW_blk00000150_DOA<14>_UNCONNECTED ,
\NLW_blk00000150_DOA<13>_UNCONNECTED , \NLW_blk00000150_DOA<12>_UNCONNECTED , \NLW_blk00000150_DOA<11>_UNCONNECTED ,
\NLW_blk00000150_DOA<10>_UNCONNECTED , \NLW_blk00000150_DOA<9>_UNCONNECTED , \NLW_blk00000150_DOA<8>_UNCONNECTED ,
\NLW_blk00000150_DOA<7>_UNCONNECTED , \NLW_blk00000150_DOA<6>_UNCONNECTED , \NLW_blk00000150_DOA<5>_UNCONNECTED , \NLW_blk00000150_DOA<4>_UNCONNECTED
, sig000000d5, sig000000d4, sig000000d3, sig000000d2}),
.ADDRA({sig000000c2, sig000000c1, sig000000c0, sig000000bf, sig000000be, sig000000bd, sig000000bc, sig000000bb, sig000000ba, sig000000b9,
sig000000b8, sig000000b7, \NLW_blk00000150_ADDRA<1>_UNCONNECTED , \NLW_blk00000150_ADDRA<0>_UNCONNECTED }),
.ADDRB({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, \NLW_blk00000150_ADDRB<1>_UNCONNECTED , \NLW_blk00000150_ADDRB<0>_UNCONNECTED }),
.DIB({\NLW_blk00000150_DIB<31>_UNCONNECTED , \NLW_blk00000150_DIB<30>_UNCONNECTED , \NLW_blk00000150_DIB<29>_UNCONNECTED ,
\NLW_blk00000150_DIB<28>_UNCONNECTED , \NLW_blk00000150_DIB<27>_UNCONNECTED , \NLW_blk00000150_DIB<26>_UNCONNECTED ,
\NLW_blk00000150_DIB<25>_UNCONNECTED , \NLW_blk00000150_DIB<24>_UNCONNECTED , \NLW_blk00000150_DIB<23>_UNCONNECTED ,
\NLW_blk00000150_DIB<22>_UNCONNECTED , \NLW_blk00000150_DIB<21>_UNCONNECTED , \NLW_blk00000150_DIB<20>_UNCONNECTED ,
\NLW_blk00000150_DIB<19>_UNCONNECTED , \NLW_blk00000150_DIB<18>_UNCONNECTED , \NLW_blk00000150_DIB<17>_UNCONNECTED ,
\NLW_blk00000150_DIB<16>_UNCONNECTED , \NLW_blk00000150_DIB<15>_UNCONNECTED , \NLW_blk00000150_DIB<14>_UNCONNECTED ,
\NLW_blk00000150_DIB<13>_UNCONNECTED , \NLW_blk00000150_DIB<12>_UNCONNECTED , \NLW_blk00000150_DIB<11>_UNCONNECTED ,
\NLW_blk00000150_DIB<10>_UNCONNECTED , \NLW_blk00000150_DIB<9>_UNCONNECTED , \NLW_blk00000150_DIB<8>_UNCONNECTED ,
\NLW_blk00000150_DIB<7>_UNCONNECTED , \NLW_blk00000150_DIB<6>_UNCONNECTED , \NLW_blk00000150_DIB<5>_UNCONNECTED , \NLW_blk00000150_DIB<4>_UNCONNECTED
, \NLW_blk00000150_DIB<3>_UNCONNECTED , \NLW_blk00000150_DIB<2>_UNCONNECTED , \NLW_blk00000150_DIB<1>_UNCONNECTED ,
\NLW_blk00000150_DIB<0>_UNCONNECTED }),
.DOPA({\NLW_blk00000150_DOPA<3>_UNCONNECTED , \NLW_blk00000150_DOPA<2>_UNCONNECTED , \NLW_blk00000150_DOPA<1>_UNCONNECTED ,
\NLW_blk00000150_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk00000150_DIPB<3>_UNCONNECTED , \NLW_blk00000150_DIPB<2>_UNCONNECTED , \NLW_blk00000150_DIPB<1>_UNCONNECTED ,
\NLW_blk00000150_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk00000150_DOPB<3>_UNCONNECTED , \NLW_blk00000150_DOPB<2>_UNCONNECTED , \NLW_blk00000150_DOPB<1>_UNCONNECTED ,
\NLW_blk00000150_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk00000150_DOB<31>_UNCONNECTED , \NLW_blk00000150_DOB<30>_UNCONNECTED , \NLW_blk00000150_DOB<29>_UNCONNECTED ,
\NLW_blk00000150_DOB<28>_UNCONNECTED , \NLW_blk00000150_DOB<27>_UNCONNECTED , \NLW_blk00000150_DOB<26>_UNCONNECTED ,
\NLW_blk00000150_DOB<25>_UNCONNECTED , \NLW_blk00000150_DOB<24>_UNCONNECTED , \NLW_blk00000150_DOB<23>_UNCONNECTED ,
\NLW_blk00000150_DOB<22>_UNCONNECTED , \NLW_blk00000150_DOB<21>_UNCONNECTED , \NLW_blk00000150_DOB<20>_UNCONNECTED ,
\NLW_blk00000150_DOB<19>_UNCONNECTED , \NLW_blk00000150_DOB<18>_UNCONNECTED , \NLW_blk00000150_DOB<17>_UNCONNECTED ,
\NLW_blk00000150_DOB<16>_UNCONNECTED , \NLW_blk00000150_DOB<15>_UNCONNECTED , \NLW_blk00000150_DOB<14>_UNCONNECTED ,
\NLW_blk00000150_DOB<13>_UNCONNECTED , \NLW_blk00000150_DOB<12>_UNCONNECTED , \NLW_blk00000150_DOB<11>_UNCONNECTED ,
\NLW_blk00000150_DOB<10>_UNCONNECTED , \NLW_blk00000150_DOB<9>_UNCONNECTED , \NLW_blk00000150_DOB<8>_UNCONNECTED ,
\NLW_blk00000150_DOB<7>_UNCONNECTED , \NLW_blk00000150_DOB<6>_UNCONNECTED , \NLW_blk00000150_DOB<5>_UNCONNECTED , \NLW_blk00000150_DOB<4>_UNCONNECTED
, sig000000c6, sig000000c5, sig000000c4, sig000000c3}),
.WEB({sig00000002, sig00000002, sig00000002, sig00000002}),
.DIA({\NLW_blk00000150_DIA<31>_UNCONNECTED , \NLW_blk00000150_DIA<30>_UNCONNECTED , \NLW_blk00000150_DIA<29>_UNCONNECTED ,
\NLW_blk00000150_DIA<28>_UNCONNECTED , \NLW_blk00000150_DIA<27>_UNCONNECTED , \NLW_blk00000150_DIA<26>_UNCONNECTED ,
\NLW_blk00000150_DIA<25>_UNCONNECTED , \NLW_blk00000150_DIA<24>_UNCONNECTED , \NLW_blk00000150_DIA<23>_UNCONNECTED ,
\NLW_blk00000150_DIA<22>_UNCONNECTED , \NLW_blk00000150_DIA<21>_UNCONNECTED , \NLW_blk00000150_DIA<20>_UNCONNECTED ,
\NLW_blk00000150_DIA<19>_UNCONNECTED , \NLW_blk00000150_DIA<18>_UNCONNECTED , \NLW_blk00000150_DIA<17>_UNCONNECTED ,
\NLW_blk00000150_DIA<16>_UNCONNECTED , \NLW_blk00000150_DIA<15>_UNCONNECTED , \NLW_blk00000150_DIA<14>_UNCONNECTED ,
\NLW_blk00000150_DIA<13>_UNCONNECTED , \NLW_blk00000150_DIA<12>_UNCONNECTED , \NLW_blk00000150_DIA<11>_UNCONNECTED ,
\NLW_blk00000150_DIA<10>_UNCONNECTED , \NLW_blk00000150_DIA<9>_UNCONNECTED , \NLW_blk00000150_DIA<8>_UNCONNECTED ,
\NLW_blk00000150_DIA<7>_UNCONNECTED , \NLW_blk00000150_DIA<6>_UNCONNECTED , \NLW_blk00000150_DIA<5>_UNCONNECTED , \NLW_blk00000150_DIA<4>_UNCONNECTED
, sig00000002, sig00000002, sig00000002, sig00000002})
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000151 (
.A0(sig00000001),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig00000125),
.Q(sig00000129),
.Q15(NLW_blk00000151_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000152 (
.C(clk),
.CE(sig00000001),
.D(sig00000129),
.Q(sig00000123)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000153 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig00000126),
.Q(sig0000012a),
.Q15(NLW_blk00000153_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000154 (
.C(clk),
.CE(sig00000001),
.D(sig0000012a),
.Q(sig00000124)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000155 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d1),
.Q(sig0000012b),
.Q15(NLW_blk00000155_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000156 (
.C(clk),
.CE(sig00000001),
.D(sig0000012b),
.Q(sig00000113)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000157 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d0),
.Q(sig0000012c),
.Q15(NLW_blk00000157_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000158 (
.C(clk),
.CE(sig00000001),
.D(sig0000012c),
.Q(sig00000112)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000159 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000cf),
.Q(sig0000012d),
.Q15(NLW_blk00000159_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015a (
.C(clk),
.CE(sig00000001),
.D(sig0000012d),
.Q(sig00000111)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000015b (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000ce),
.Q(sig0000012e),
.Q15(NLW_blk0000015b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015c (
.C(clk),
.CE(sig00000001),
.D(sig0000012e),
.Q(sig00000110)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000015d (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000cd),
.Q(sig0000012f),
.Q15(NLW_blk0000015d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015e (
.C(clk),
.CE(sig00000001),
.D(sig0000012f),
.Q(sig0000010f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000015f (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000cc),
.Q(sig00000130),
.Q15(NLW_blk0000015f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000160 (
.C(clk),
.CE(sig00000001),
.D(sig00000130),
.Q(sig0000010e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000161 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000cb),
.Q(sig00000131),
.Q15(NLW_blk00000161_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000162 (
.C(clk),
.CE(sig00000001),
.D(sig00000131),
.Q(sig0000010d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000163 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000ca),
.Q(sig00000132),
.Q15(NLW_blk00000163_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000164 (
.C(clk),
.CE(sig00000001),
.D(sig00000132),
.Q(sig0000010c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000165 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c9),
.Q(sig00000133),
.Q15(NLW_blk00000165_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000166 (
.C(clk),
.CE(sig00000001),
.D(sig00000133),
.Q(sig0000010b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000167 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c8),
.Q(sig00000134),
.Q15(NLW_blk00000167_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000168 (
.C(clk),
.CE(sig00000001),
.D(sig00000134),
.Q(sig0000010a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000169 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c7),
.Q(sig00000135),
.Q15(NLW_blk00000169_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016a (
.C(clk),
.CE(sig00000001),
.D(sig00000135),
.Q(sig00000109)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000016b (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c6),
.Q(sig00000136),
.Q15(NLW_blk0000016b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016c (
.C(clk),
.CE(sig00000001),
.D(sig00000136),
.Q(sig00000108)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000016d (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c5),
.Q(sig00000137),
.Q15(NLW_blk0000016d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016e (
.C(clk),
.CE(sig00000001),
.D(sig00000137),
.Q(sig00000107)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000016f (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c4),
.Q(sig00000138),
.Q15(NLW_blk0000016f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000170 (
.C(clk),
.CE(sig00000001),
.D(sig00000138),
.Q(sig00000106)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000171 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c3),
.Q(sig00000139),
.Q15(NLW_blk00000171_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000172 (
.C(clk),
.CE(sig00000001),
.D(sig00000139),
.Q(sig00000105)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000173 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000e0),
.Q(sig0000013a),
.Q15(NLW_blk00000173_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000174 (
.C(clk),
.CE(sig00000001),
.D(sig0000013a),
.Q(sig00000122)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000175 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000df),
.Q(sig0000013b),
.Q15(NLW_blk00000175_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000176 (
.C(clk),
.CE(sig00000001),
.D(sig0000013b),
.Q(sig00000121)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000177 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000de),
.Q(sig0000013c),
.Q15(NLW_blk00000177_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000178 (
.C(clk),
.CE(sig00000001),
.D(sig0000013c),
.Q(sig00000120)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000179 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000dd),
.Q(sig0000013d),
.Q15(NLW_blk00000179_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000017a (
.C(clk),
.CE(sig00000001),
.D(sig0000013d),
.Q(sig0000011f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000017b (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000dc),
.Q(sig0000013e),
.Q15(NLW_blk0000017b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000017c (
.C(clk),
.CE(sig00000001),
.D(sig0000013e),
.Q(sig0000011e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000017d (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000db),
.Q(sig0000013f),
.Q15(NLW_blk0000017d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000017e (
.C(clk),
.CE(sig00000001),
.D(sig0000013f),
.Q(sig0000011d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000017f (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000da),
.Q(sig00000140),
.Q15(NLW_blk0000017f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000180 (
.C(clk),
.CE(sig00000001),
.D(sig00000140),
.Q(sig0000011c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000181 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d9),
.Q(sig00000141),
.Q15(NLW_blk00000181_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000182 (
.C(clk),
.CE(sig00000001),
.D(sig00000141),
.Q(sig0000011b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000183 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d8),
.Q(sig00000142),
.Q15(NLW_blk00000183_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000184 (
.C(clk),
.CE(sig00000001),
.D(sig00000142),
.Q(sig0000011a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000185 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d7),
.Q(sig00000143),
.Q15(NLW_blk00000185_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000186 (
.C(clk),
.CE(sig00000001),
.D(sig00000143),
.Q(sig00000119)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000187 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d6),
.Q(sig00000144),
.Q15(NLW_blk00000187_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000188 (
.C(clk),
.CE(sig00000001),
.D(sig00000144),
.Q(sig00000118)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000189 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d5),
.Q(sig00000145),
.Q15(NLW_blk00000189_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000018a (
.C(clk),
.CE(sig00000001),
.D(sig00000145),
.Q(sig00000117)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000018b (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d4),
.Q(sig00000146),
.Q15(NLW_blk0000018b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000018c (
.C(clk),
.CE(sig00000001),
.D(sig00000146),
.Q(sig00000116)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000018d (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d3),
.Q(sig00000147),
.Q15(NLW_blk0000018d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000018e (
.C(clk),
.CE(sig00000001),
.D(sig00000147),
.Q(sig00000115)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000018f (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d2),
.Q(sig00000148),
.Q15(NLW_blk0000018f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000190 (
.C(clk),
.CE(sig00000001),
.D(sig00000148),
.Q(sig00000114)
);
XORCY \blk00000025/blk00000055 (
.CI(\blk00000025/sig00000197 ),
.LI(\blk00000025/sig00000198 ),
.O(sig00000004)
);
MUXCY \blk00000025/blk00000054 (
.CI(\blk00000025/sig00000197 ),
.DI(sig00000045),
.S(\blk00000025/sig00000198 ),
.O(sig00000003)
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000053 (
.I0(sig00000045),
.I1(sig00000002),
.O(\blk00000025/sig00000198 )
);
XORCY \blk00000025/blk00000052 (
.CI(\blk00000025/sig00000195 ),
.LI(\blk00000025/sig00000196 ),
.O(sig00000005)
);
MUXCY \blk00000025/blk00000051 (
.CI(\blk00000025/sig00000195 ),
.DI(sig00000044),
.S(\blk00000025/sig00000196 ),
.O(\blk00000025/sig00000197 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000050 (
.I0(sig00000044),
.I1(sig00000002),
.O(\blk00000025/sig00000196 )
);
XORCY \blk00000025/blk0000004f (
.CI(\blk00000025/sig00000193 ),
.LI(\blk00000025/sig00000194 ),
.O(sig00000006)
);
MUXCY \blk00000025/blk0000004e (
.CI(\blk00000025/sig00000193 ),
.DI(sig00000043),
.S(\blk00000025/sig00000194 ),
.O(\blk00000025/sig00000195 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk0000004d (
.I0(sig00000043),
.I1(sig00000002),
.O(\blk00000025/sig00000194 )
);
XORCY \blk00000025/blk0000004c (
.CI(\blk00000025/sig00000191 ),
.LI(\blk00000025/sig00000192 ),
.O(sig00000007)
);
MUXCY \blk00000025/blk0000004b (
.CI(\blk00000025/sig00000191 ),
.DI(sig00000042),
.S(\blk00000025/sig00000192 ),
.O(\blk00000025/sig00000193 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk0000004a (
.I0(sig00000042),
.I1(sig00000002),
.O(\blk00000025/sig00000192 )
);
XORCY \blk00000025/blk00000049 (
.CI(\blk00000025/sig0000018f ),
.LI(\blk00000025/sig00000190 ),
.O(sig00000008)
);
MUXCY \blk00000025/blk00000048 (
.CI(\blk00000025/sig0000018f ),
.DI(sig00000041),
.S(\blk00000025/sig00000190 ),
.O(\blk00000025/sig00000191 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000047 (
.I0(sig00000041),
.I1(sig00000002),
.O(\blk00000025/sig00000190 )
);
XORCY \blk00000025/blk00000046 (
.CI(\blk00000025/sig0000018d ),
.LI(\blk00000025/sig0000018e ),
.O(sig00000009)
);
MUXCY \blk00000025/blk00000045 (
.CI(\blk00000025/sig0000018d ),
.DI(sig00000040),
.S(\blk00000025/sig0000018e ),
.O(\blk00000025/sig0000018f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000044 (
.I0(sig00000040),
.I1(sig00000002),
.O(\blk00000025/sig0000018e )
);
XORCY \blk00000025/blk00000043 (
.CI(\blk00000025/sig0000018b ),
.LI(\blk00000025/sig0000018c ),
.O(sig0000000a)
);
MUXCY \blk00000025/blk00000042 (
.CI(\blk00000025/sig0000018b ),
.DI(sig0000003f),
.S(\blk00000025/sig0000018c ),
.O(\blk00000025/sig0000018d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000041 (
.I0(sig0000003f),
.I1(sig00000002),
.O(\blk00000025/sig0000018c )
);
XORCY \blk00000025/blk00000040 (
.CI(\blk00000025/sig00000189 ),
.LI(\blk00000025/sig0000018a ),
.O(sig0000000b)
);
MUXCY \blk00000025/blk0000003f (
.CI(\blk00000025/sig00000189 ),
.DI(sig0000003e),
.S(\blk00000025/sig0000018a ),
.O(\blk00000025/sig0000018b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk0000003e (
.I0(sig0000003e),
.I1(sig00000001),
.O(\blk00000025/sig0000018a )
);
XORCY \blk00000025/blk0000003d (
.CI(\blk00000025/sig00000187 ),
.LI(\blk00000025/sig00000188 ),
.O(sig0000000c)
);
MUXCY \blk00000025/blk0000003c (
.CI(\blk00000025/sig00000187 ),
.DI(sig0000003d),
.S(\blk00000025/sig00000188 ),
.O(\blk00000025/sig00000189 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk0000003b (
.I0(sig0000003d),
.I1(sig00000001),
.O(\blk00000025/sig00000188 )
);
XORCY \blk00000025/blk0000003a (
.CI(\blk00000025/sig00000185 ),
.LI(\blk00000025/sig00000186 ),
.O(sig0000000d)
);
MUXCY \blk00000025/blk00000039 (
.CI(\blk00000025/sig00000185 ),
.DI(sig0000003c),
.S(\blk00000025/sig00000186 ),
.O(\blk00000025/sig00000187 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000038 (
.I0(sig0000003c),
.I1(sig00000002),
.O(\blk00000025/sig00000186 )
);
XORCY \blk00000025/blk00000037 (
.CI(\blk00000025/sig00000183 ),
.LI(\blk00000025/sig00000184 ),
.O(sig0000000e)
);
MUXCY \blk00000025/blk00000036 (
.CI(\blk00000025/sig00000183 ),
.DI(sig0000003b),
.S(\blk00000025/sig00000184 ),
.O(\blk00000025/sig00000185 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000035 (
.I0(sig0000003b),
.I1(sig00000001),
.O(\blk00000025/sig00000184 )
);
XORCY \blk00000025/blk00000034 (
.CI(\blk00000025/sig00000181 ),
.LI(\blk00000025/sig00000182 ),
.O(sig0000000f)
);
MUXCY \blk00000025/blk00000033 (
.CI(\blk00000025/sig00000181 ),
.DI(sig0000003a),
.S(\blk00000025/sig00000182 ),
.O(\blk00000025/sig00000183 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000032 (
.I0(sig00000001),
.I1(sig0000003a),
.O(\blk00000025/sig00000182 )
);
XORCY \blk00000025/blk00000031 (
.CI(\blk00000025/sig0000017f ),
.LI(\blk00000025/sig00000180 ),
.O(sig00000010)
);
MUXCY \blk00000025/blk00000030 (
.CI(\blk00000025/sig0000017f ),
.DI(sig00000039),
.S(\blk00000025/sig00000180 ),
.O(\blk00000025/sig00000181 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk0000002f (
.I0(sig00000001),
.I1(sig00000039),
.O(\blk00000025/sig00000180 )
);
XORCY \blk00000025/blk0000002e (
.CI(\blk00000025/sig0000017d ),
.LI(\blk00000025/sig0000017e ),
.O(sig00000011)
);
MUXCY \blk00000025/blk0000002d (
.CI(\blk00000025/sig0000017d ),
.DI(sig00000038),
.S(\blk00000025/sig0000017e ),
.O(\blk00000025/sig0000017f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk0000002c (
.I0(sig00000002),
.I1(sig00000038),
.O(\blk00000025/sig0000017e )
);
XORCY \blk00000025/blk0000002b (
.CI(\blk00000025/sig0000017b ),
.LI(\blk00000025/sig0000017c ),
.O(sig00000012)
);
MUXCY \blk00000025/blk0000002a (
.CI(\blk00000025/sig0000017b ),
.DI(sig00000037),
.S(\blk00000025/sig0000017c ),
.O(\blk00000025/sig0000017d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000029 (
.I0(sig00000001),
.I1(sig00000037),
.O(\blk00000025/sig0000017c )
);
XORCY \blk00000025/blk00000028 (
.CI(sig00000002),
.LI(\blk00000025/sig0000017a ),
.O(sig00000013)
);
MUXCY \blk00000025/blk00000027 (
.CI(sig00000002),
.DI(sig00000036),
.S(\blk00000025/sig0000017a ),
.O(\blk00000025/sig0000017b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000026 (
.I0(sig00000002),
.I1(sig00000036),
.O(\blk00000025/sig0000017a )
);
XORCY \blk00000056/blk00000086 (
.CI(\blk00000056/sig000001e8 ),
.LI(\blk00000056/sig000001e9 ),
.O(sig00000023)
);
MUXCY \blk00000056/blk00000085 (
.CI(\blk00000056/sig000001e8 ),
.DI(sig00000045),
.S(\blk00000056/sig000001e9 ),
.O(sig00000024)
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000084 (
.I0(sig00000045),
.I1(sig00000035),
.O(\blk00000056/sig000001e9 )
);
XORCY \blk00000056/blk00000083 (
.CI(\blk00000056/sig000001e6 ),
.LI(\blk00000056/sig000001e7 ),
.O(sig00000022)
);
MUXCY \blk00000056/blk00000082 (
.CI(\blk00000056/sig000001e6 ),
.DI(sig00000044),
.S(\blk00000056/sig000001e7 ),
.O(\blk00000056/sig000001e8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000081 (
.I0(sig00000044),
.I1(sig00000035),
.O(\blk00000056/sig000001e7 )
);
XORCY \blk00000056/blk00000080 (
.CI(\blk00000056/sig000001e4 ),
.LI(\blk00000056/sig000001e5 ),
.O(sig00000021)
);
MUXCY \blk00000056/blk0000007f (
.CI(\blk00000056/sig000001e4 ),
.DI(sig00000043),
.S(\blk00000056/sig000001e5 ),
.O(\blk00000056/sig000001e6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk0000007e (
.I0(sig00000043),
.I1(sig00000035),
.O(\blk00000056/sig000001e5 )
);
XORCY \blk00000056/blk0000007d (
.CI(\blk00000056/sig000001e2 ),
.LI(\blk00000056/sig000001e3 ),
.O(sig00000020)
);
MUXCY \blk00000056/blk0000007c (
.CI(\blk00000056/sig000001e2 ),
.DI(sig00000042),
.S(\blk00000056/sig000001e3 ),
.O(\blk00000056/sig000001e4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk0000007b (
.I0(sig00000042),
.I1(sig00000035),
.O(\blk00000056/sig000001e3 )
);
XORCY \blk00000056/blk0000007a (
.CI(\blk00000056/sig000001e0 ),
.LI(\blk00000056/sig000001e1 ),
.O(sig0000001f)
);
MUXCY \blk00000056/blk00000079 (
.CI(\blk00000056/sig000001e0 ),
.DI(sig00000041),
.S(\blk00000056/sig000001e1 ),
.O(\blk00000056/sig000001e2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000078 (
.I0(sig00000041),
.I1(sig00000035),
.O(\blk00000056/sig000001e1 )
);
XORCY \blk00000056/blk00000077 (
.CI(\blk00000056/sig000001de ),
.LI(\blk00000056/sig000001df ),
.O(sig0000001e)
);
MUXCY \blk00000056/blk00000076 (
.CI(\blk00000056/sig000001de ),
.DI(sig00000040),
.S(\blk00000056/sig000001df ),
.O(\blk00000056/sig000001e0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000075 (
.I0(sig00000040),
.I1(sig00000035),
.O(\blk00000056/sig000001df )
);
XORCY \blk00000056/blk00000074 (
.CI(\blk00000056/sig000001dc ),
.LI(\blk00000056/sig000001dd ),
.O(sig0000001d)
);
MUXCY \blk00000056/blk00000073 (
.CI(\blk00000056/sig000001dc ),
.DI(sig0000003f),
.S(\blk00000056/sig000001dd ),
.O(\blk00000056/sig000001de )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000072 (
.I0(sig0000003f),
.I1(sig00000035),
.O(\blk00000056/sig000001dd )
);
XORCY \blk00000056/blk00000071 (
.CI(\blk00000056/sig000001da ),
.LI(\blk00000056/sig000001db ),
.O(sig0000001c)
);
MUXCY \blk00000056/blk00000070 (
.CI(\blk00000056/sig000001da ),
.DI(sig0000003e),
.S(\blk00000056/sig000001db ),
.O(\blk00000056/sig000001dc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk0000006f (
.I0(sig0000003e),
.I1(sig00000035),
.O(\blk00000056/sig000001db )
);
XORCY \blk00000056/blk0000006e (
.CI(\blk00000056/sig000001d8 ),
.LI(\blk00000056/sig000001d9 ),
.O(sig0000001b)
);
MUXCY \blk00000056/blk0000006d (
.CI(\blk00000056/sig000001d8 ),
.DI(sig0000003d),
.S(\blk00000056/sig000001d9 ),
.O(\blk00000056/sig000001da )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk0000006c (
.I0(sig0000003d),
.I1(sig00000035),
.O(\blk00000056/sig000001d9 )
);
XORCY \blk00000056/blk0000006b (
.CI(\blk00000056/sig000001d6 ),
.LI(\blk00000056/sig000001d7 ),
.O(sig0000001a)
);
MUXCY \blk00000056/blk0000006a (
.CI(\blk00000056/sig000001d6 ),
.DI(sig0000003c),
.S(\blk00000056/sig000001d7 ),
.O(\blk00000056/sig000001d8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000069 (
.I0(sig0000003c),
.I1(sig00000035),
.O(\blk00000056/sig000001d7 )
);
XORCY \blk00000056/blk00000068 (
.CI(\blk00000056/sig000001d4 ),
.LI(\blk00000056/sig000001d5 ),
.O(sig00000019)
);
MUXCY \blk00000056/blk00000067 (
.CI(\blk00000056/sig000001d4 ),
.DI(sig0000003b),
.S(\blk00000056/sig000001d5 ),
.O(\blk00000056/sig000001d6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000066 (
.I0(sig0000003b),
.I1(sig00000035),
.O(\blk00000056/sig000001d5 )
);
XORCY \blk00000056/blk00000065 (
.CI(\blk00000056/sig000001d2 ),
.LI(\blk00000056/sig000001d3 ),
.O(sig00000018)
);
MUXCY \blk00000056/blk00000064 (
.CI(\blk00000056/sig000001d2 ),
.DI(sig0000003a),
.S(\blk00000056/sig000001d3 ),
.O(\blk00000056/sig000001d4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000063 (
.I0(sig0000003a),
.I1(sig00000035),
.O(\blk00000056/sig000001d3 )
);
XORCY \blk00000056/blk00000062 (
.CI(\blk00000056/sig000001d0 ),
.LI(\blk00000056/sig000001d1 ),
.O(sig00000017)
);
MUXCY \blk00000056/blk00000061 (
.CI(\blk00000056/sig000001d0 ),
.DI(sig00000039),
.S(\blk00000056/sig000001d1 ),
.O(\blk00000056/sig000001d2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000060 (
.I0(sig00000039),
.I1(sig00000035),
.O(\blk00000056/sig000001d1 )
);
XORCY \blk00000056/blk0000005f (
.CI(\blk00000056/sig000001ce ),
.LI(\blk00000056/sig000001cf ),
.O(sig00000016)
);
MUXCY \blk00000056/blk0000005e (
.CI(\blk00000056/sig000001ce ),
.DI(sig00000038),
.S(\blk00000056/sig000001cf ),
.O(\blk00000056/sig000001d0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk0000005d (
.I0(sig00000038),
.I1(sig00000035),
.O(\blk00000056/sig000001cf )
);
XORCY \blk00000056/blk0000005c (
.CI(\blk00000056/sig000001cc ),
.LI(\blk00000056/sig000001cd ),
.O(sig00000015)
);
MUXCY \blk00000056/blk0000005b (
.CI(\blk00000056/sig000001cc ),
.DI(sig00000037),
.S(\blk00000056/sig000001cd ),
.O(\blk00000056/sig000001ce )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk0000005a (
.I0(sig00000037),
.I1(sig00000034),
.O(\blk00000056/sig000001cd )
);
XORCY \blk00000056/blk00000059 (
.CI(sig00000002),
.LI(\blk00000056/sig000001cb ),
.O(sig00000014)
);
MUXCY \blk00000056/blk00000058 (
.CI(sig00000002),
.DI(sig00000036),
.S(\blk00000056/sig000001cb ),
.O(\blk00000056/sig000001cc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000057 (
.I0(sig00000036),
.I1(sig00000033),
.O(\blk00000056/sig000001cb )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk0000009b (
.I0(\blk00000087/sig000001f1 ),
.I1(\blk00000087/sig000001f0 ),
.O(\blk00000087/sig000001ff )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000087/blk0000009a (
.I0(sig00000033),
.I1(\blk00000087/sig000001f1 ),
.I2(\blk00000087/sig000001f0 ),
.O(\blk00000087/sig000001f8 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk00000099 (
.I0(\blk00000087/sig000001ef ),
.I1(\blk00000087/sig000001ee ),
.O(\blk00000087/sig000001fe )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000087/blk00000098 (
.I0(sig00000034),
.I1(\blk00000087/sig000001ef ),
.I2(\blk00000087/sig000001ee ),
.O(\blk00000087/sig000001f7 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk00000097 (
.I0(\blk00000087/sig000001ec ),
.I1(\blk00000087/sig000001ed ),
.O(\blk00000087/sig000001fd )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000087/blk00000096 (
.I0(sig00000035),
.I1(\blk00000087/sig000001ec ),
.I2(\blk00000087/sig000001ed ),
.O(\blk00000087/sig000001f6 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk00000095 (
.I0(sig00000033),
.I1(\blk00000087/sig000001f2 ),
.O(\blk00000087/sig000001fc )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk00000094 (
.I0(sig00000035),
.I1(\blk00000087/sig000001ef ),
.O(\blk00000087/sig000001fa )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk00000093 (
.I0(\blk00000087/sig000001f2 ),
.I1(\blk00000087/sig000001ed ),
.O(\blk00000087/sig000001f9 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk00000092 (
.I0(sig00000034),
.I1(\blk00000087/sig000001f1 ),
.O(\blk00000087/sig000001fb )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk00000091 (
.C(clk),
.D(\blk00000087/sig000001fd ),
.Q(\blk00000087/sig000001ec )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk00000090 (
.C(clk),
.D(\blk00000087/sig000001fe ),
.Q(\blk00000087/sig000001ee )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk0000008f (
.C(clk),
.D(\blk00000087/sig000001ff ),
.Q(\blk00000087/sig000001f0 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk0000008e (
.C(clk),
.D(\blk00000087/sig000001f9 ),
.Q(\blk00000087/sig000001ed )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk0000008d (
.C(clk),
.D(\blk00000087/sig000001fa ),
.Q(\blk00000087/sig000001ef )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk0000008c (
.C(clk),
.D(\blk00000087/sig000001fb ),
.Q(\blk00000087/sig000001f1 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk0000008b (
.C(clk),
.D(\blk00000087/sig000001fc ),
.Q(\blk00000087/sig000001f2 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk0000008a (
.C(clk),
.D(\blk00000087/sig000001f6 ),
.Q(sig00000035)
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk00000089 (
.C(clk),
.D(\blk00000087/sig000001f7 ),
.Q(sig00000034)
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk00000088 (
.C(clk),
.D(\blk00000087/sig000001f8 ),
.Q(sig00000033)
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
module wb_rom
#(//Wishbone parameters
parameter dw = 32,
//Memory parameters
parameter depth = 256,
parameter aw = $clog2(depth),
parameter memfile = "")
(input wb_clk_i,
input wb_rst_i,
input [aw-1:0] wb_adr_i,
input [dw-1:0] wb_dat_i,
input [3:0] wb_sel_i,
// input wb_we_i,
input [1:0] wb_bte_i,
input [2:0] wb_cti_i,
input wb_cyc_i,
input wb_stb_i,
output reg wb_ack_o,
output wb_err_o,
output [dw-1:0] wb_dat_o);
`include "wb_common.v"
reg [aw-1:0] adr_r;
wire [aw-1:0] next_adr;
wire valid = wb_cyc_i & wb_stb_i;
reg valid_r;
reg is_last_r;
always @(posedge wb_clk_i)
is_last_r <= wb_is_last(wb_cti_i);
wire new_cycle = (valid & !valid_r) | is_last_r;
assign next_adr = wb_next_adr(adr_r, wb_cti_i, wb_bte_i, dw);
wire [aw-1:0] adr = new_cycle ? wb_adr_i : next_adr;
always@(posedge wb_clk_i) begin
adr_r <= adr;
valid_r <= valid;
//Ack generation
wb_ack_o <= valid & (!((wb_cti_i == 3'b000) | (wb_cti_i == 3'b111)) | !wb_ack_o);
if(wb_rst_i) begin
adr_r <= {aw{1'b0}};
valid_r <= 1'b0;
wb_ack_o <= 1'b0;
end
end
wire ram_we = 1'b0;
//TODO:ck for burst address errors
assign wb_err_o = 1'b0;
`ifdef RTL
initial begin
$display("RTL ROM: %s" % memfile);
end
wb_ram_generic
#(.depth(depth/4),
.memfile (memfile))
ram0
(.clk (wb_clk_i),
.we (4'b0),
.din (wb_dat_i),
.waddr(adr_r[aw-1:2]),
.raddr (adr[aw-1:2]),
.dout (wb_dat_o));
`else // !`ifdef RTL
`ifdef XILINX
initial begin
$display("XILINX ROM");
end
wb_ram_xilinx ram0(
.clk (wb_clk_i),
.rst (wb_rst_i),
.we ({4{ram_we}} & wb_sel_i),
.din (wb_dat_i),
.waddr({2'b00, adr_r[aw-1:2]}),
.raddr ({2'b00, adr[aw-1:2]}),
.dout (wb_dat_o)
);
`else // !`ifdef XILINX
`ifdef ALTERA
initial begin
$display("ALTERA ROM");
end
wb_rom_32x8192 ram0(
.address(adr_r),
.clock(wb_clk_i),
.q(wb_dat_o)
);
`endif
`endif // !`ifdef XILINX
initial begin
$error("NO ROM!");
end
`endif // !`ifdef RTL
endmodule
|
`include "assert.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("i64.eqz2.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("i64.eqz2_tb.vcd");
$dumpvars(0, cpu_tb);
#18
`assert(result, 0);
`assert(result_empty, 0);
$finish;
end
endmodule
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:16:16 02/06/2014
// Design Name:
// Module Name: zxuno
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module zxuno(
input wire clk,
input wire wssclk,
output wire [2:0] r,
output wire [2:0] g,
output wire [2:0] b,
output wire csync
);
wire [8:0] h;
wire [8:0] v;
reg [2:0] rojo;
reg [2:0] verde;
reg [2:0] azul;
always @* begin
if (h>=0 && h<256 && v>=0 && v<192) begin
if (v>=0 && v<64) begin
rojo = h[7:5];
verde = 3'b000;
azul = 3'b000;
end
else if (v>=64 && v<128) begin
rojo = 3'b000;
verde = h[7:5];
azul = 3'b000;
end
else begin
rojo = 3'b000;
verde = 3'b000;
azul = h[7:5];
end
end
else begin
rojo = 3'b100;
verde = 3'b100;
azul = 3'b100;
end
end
pal_sync_generator_progressive syncs (
.clk(clk),
.wssclk(wssclk),
.ri(rojo),
.gi(verde),
.bi(azul),
.hcnt(h),
.vcnt(v),
.ro(r),
.go(g),
.bo(b),
.csync(csync)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FILL_SYMBOL_V
`define SKY130_FD_SC_LP__FILL_SYMBOL_V
/**
* fill: Fill cell.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__fill ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__FILL_SYMBOL_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:40:17 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_auto_pc_1_sim_netlist.v
// Design : zynq_design_1_auto_pc_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_READ = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "0" *) (* C_M_AXI_PROTOCOL = "0" *) (* C_S_AXI_PROTOCOL = "1" *)
(* C_TRANSLATION_MODE = "2" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* P_AXI3 = "1" *)
(* P_AXI4 = "0" *) (* P_AXILITE = "2" *) (* P_AXILITE_SIZE = "3'b010" *)
(* P_CONVERSION = "2" *) (* P_DECERR = "2'b11" *) (* P_INCR = "2'b01" *)
(* P_PROTECTION = "1" *) (* P_SLVERR = "2'b10" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [11:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [11:0]m_axi_wid;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [11:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
output [11:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [11:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
wire \<const0> ;
wire m_axi_arready;
wire m_axi_awready;
wire [11:0]m_axi_bid;
wire [1:0]m_axi_bresp;
wire [0:0]m_axi_buser;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire [11:0]m_axi_rid;
wire m_axi_rlast;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_ruser;
wire m_axi_rvalid;
wire m_axi_wready;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [1:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_aruser;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [1:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awuser;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_rready;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire [3:0]s_axi_wstrb;
wire [0:0]s_axi_wuser;
wire s_axi_wvalid;
assign m_axi_araddr[31:0] = s_axi_araddr;
assign m_axi_arburst[1:0] = s_axi_arburst;
assign m_axi_arcache[3:0] = s_axi_arcache;
assign m_axi_arid[11:0] = s_axi_arid;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3:0] = s_axi_arlen;
assign m_axi_arlock[0] = s_axi_arlock[0];
assign m_axi_arprot[2:0] = s_axi_arprot;
assign m_axi_arqos[3:0] = s_axi_arqos;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2:0] = s_axi_arsize;
assign m_axi_aruser[0] = s_axi_aruser;
assign m_axi_arvalid = s_axi_arvalid;
assign m_axi_awaddr[31:0] = s_axi_awaddr;
assign m_axi_awburst[1:0] = s_axi_awburst;
assign m_axi_awcache[3:0] = s_axi_awcache;
assign m_axi_awid[11:0] = s_axi_awid;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3:0] = s_axi_awlen;
assign m_axi_awlock[0] = s_axi_awlock[0];
assign m_axi_awprot[2:0] = s_axi_awprot;
assign m_axi_awqos[3:0] = s_axi_awqos;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2:0] = s_axi_awsize;
assign m_axi_awuser[0] = s_axi_awuser;
assign m_axi_awvalid = s_axi_awvalid;
assign m_axi_bready = s_axi_bready;
assign m_axi_rready = s_axi_rready;
assign m_axi_wdata[31:0] = s_axi_wdata;
assign m_axi_wid[11] = \<const0> ;
assign m_axi_wid[10] = \<const0> ;
assign m_axi_wid[9] = \<const0> ;
assign m_axi_wid[8] = \<const0> ;
assign m_axi_wid[7] = \<const0> ;
assign m_axi_wid[6] = \<const0> ;
assign m_axi_wid[5] = \<const0> ;
assign m_axi_wid[4] = \<const0> ;
assign m_axi_wid[3] = \<const0> ;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = s_axi_wlast;
assign m_axi_wstrb[3:0] = s_axi_wstrb;
assign m_axi_wuser[0] = s_axi_wuser;
assign m_axi_wvalid = s_axi_wvalid;
assign s_axi_arready = m_axi_arready;
assign s_axi_awready = m_axi_awready;
assign s_axi_bid[11:0] = m_axi_bid;
assign s_axi_bresp[1:0] = m_axi_bresp;
assign s_axi_buser[0] = m_axi_buser;
assign s_axi_bvalid = m_axi_bvalid;
assign s_axi_rdata[31:0] = m_axi_rdata;
assign s_axi_rid[11:0] = m_axi_rid;
assign s_axi_rlast = m_axi_rlast;
assign s_axi_rresp[1:0] = m_axi_rresp;
assign s_axi_ruser[0] = m_axi_ruser;
assign s_axi_rvalid = m_axi_rvalid;
assign s_axi_wready = m_axi_wready;
GND GND
(.G(\<const0> ));
endmodule
(* CHECK_LICENSE_TYPE = "zynq_design_1_auto_pc_1,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [11:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [3:0]s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input [1:0]s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input [3:0]s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *) input [11:0]s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [11:0]s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [11:0]s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [3:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [1:0]s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [11:0]s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *) output [11:0]m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [31:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) output [7:0]m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *) output [2:0]m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *) output [1:0]m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *) output [0:0]m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *) output [3:0]m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *) output [3:0]m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *) output [3:0]m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [31:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [3:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) output m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *) input [11:0]m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *) output [11:0]m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [31:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) output [7:0]m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *) output [2:0]m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *) output [1:0]m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *) output [0:0]m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *) output [3:0]m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *) output [3:0]m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *) output [3:0]m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *) input [11:0]m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [31:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) input m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) output m_axi_rready;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [1:0]m_axi_arburst;
wire [3:0]m_axi_arcache;
wire [11:0]m_axi_arid;
wire [7:0]m_axi_arlen;
wire [0:0]m_axi_arlock;
wire [2:0]m_axi_arprot;
wire [3:0]m_axi_arqos;
wire m_axi_arready;
wire [3:0]m_axi_arregion;
wire [2:0]m_axi_arsize;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [1:0]m_axi_awburst;
wire [3:0]m_axi_awcache;
wire [11:0]m_axi_awid;
wire [7:0]m_axi_awlen;
wire [0:0]m_axi_awlock;
wire [2:0]m_axi_awprot;
wire [3:0]m_axi_awqos;
wire m_axi_awready;
wire [3:0]m_axi_awregion;
wire [2:0]m_axi_awsize;
wire m_axi_awvalid;
wire [11:0]m_axi_bid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire [11:0]m_axi_rid;
wire m_axi_rlast;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [31:0]m_axi_wdata;
wire m_axi_wlast;
wire m_axi_wready;
wire [3:0]m_axi_wstrb;
wire m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [1:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [1:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [11:0]s_axi_wid;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_READ = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "0" *)
(* C_M_AXI_PROTOCOL = "0" *)
(* C_S_AXI_PROTOCOL = "1" *)
(* C_TRANSLATION_MODE = "2" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_CONVERSION = "2" *)
(* P_DECERR = "2'b11" *)
(* P_INCR = "2'b01" *)
(* P_PROTECTION = "1" *)
(* P_SLVERR = "2'b10" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(m_axi_arburst),
.m_axi_arcache(m_axi_arcache),
.m_axi_arid(m_axi_arid),
.m_axi_arlen(m_axi_arlen),
.m_axi_arlock(m_axi_arlock),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(m_axi_arqos),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(m_axi_arregion),
.m_axi_arsize(m_axi_arsize),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(m_axi_awburst),
.m_axi_awcache(m_axi_awcache),
.m_axi_awid(m_axi_awid),
.m_axi_awlen(m_axi_awlen),
.m_axi_awlock(m_axi_awlock),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(m_axi_awqos),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(m_axi_awregion),
.m_axi_awsize(m_axi_awsize),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser(1'b0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[11:0]),
.m_axi_wlast(m_axi_wlast),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid(s_axi_wid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4BB_PP_SYMBOL_V
`define SKY130_FD_SC_HS__OR4BB_PP_SYMBOL_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or4bb (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
input D_N ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4BB_PP_SYMBOL_V
|
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// result_valid O 1
// result_value O 128 reg
// CLK I 1 clock
// RST_N I 1 reset
// put_args_x_is_signed I 1
// put_args_x I 64
// put_args_y_is_signed I 1
// put_args_y I 64
// EN_put_args I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkIntMul_64(CLK,
RST_N,
put_args_x_is_signed,
put_args_x,
put_args_y_is_signed,
put_args_y,
EN_put_args,
result_valid,
result_value);
input CLK;
input RST_N;
// action method put_args
input put_args_x_is_signed;
input [63 : 0] put_args_x;
input put_args_y_is_signed;
input [63 : 0] put_args_y;
input EN_put_args;
// value method result_valid
output result_valid;
// value method result_value
output [127 : 0] result_value;
// signals for module outputs
wire [127 : 0] result_value;
wire result_valid;
// register m_rg_isNeg
reg m_rg_isNeg;
wire m_rg_isNeg$D_IN, m_rg_isNeg$EN;
// register m_rg_signed
reg m_rg_signed;
wire m_rg_signed$D_IN, m_rg_signed$EN;
// register m_rg_state
reg [1 : 0] m_rg_state;
wire [1 : 0] m_rg_state$D_IN;
wire m_rg_state$EN;
// register m_rg_x
reg [127 : 0] m_rg_x;
wire [127 : 0] m_rg_x$D_IN;
wire m_rg_x$EN;
// register m_rg_xy
reg [127 : 0] m_rg_xy;
wire [127 : 0] m_rg_xy$D_IN;
wire m_rg_xy$EN;
// register m_rg_y
reg [63 : 0] m_rg_y;
wire [63 : 0] m_rg_y$D_IN;
wire m_rg_y$EN;
// rule scheduling signals
wire CAN_FIRE_RL_m_compute,
CAN_FIRE_put_args,
WILL_FIRE_RL_m_compute,
WILL_FIRE_put_args;
// inputs to muxes for submodule ports
wire [127 : 0] MUX_m_rg_x$write_1__VAL_1,
MUX_m_rg_x$write_1__VAL_2,
MUX_m_rg_xy$write_1__VAL_2;
wire [63 : 0] MUX_m_rg_y$write_1__VAL_1, MUX_m_rg_y$write_1__VAL_2;
// remaining internal signals
wire [127 : 0] x__h236, x__h338, xy___1__h262;
wire [63 : 0] _theResult___fst__h506,
_theResult___fst__h509,
_theResult___fst__h560,
_theResult___fst__h563,
_theResult___snd_fst__h555;
wire IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d34;
// action method put_args
assign CAN_FIRE_put_args = 1'd1 ;
assign WILL_FIRE_put_args = EN_put_args ;
// value method result_valid
assign result_valid = m_rg_state == 2'd2 ;
// value method result_value
assign result_value = m_rg_xy ;
// rule RL_m_compute
assign CAN_FIRE_RL_m_compute = m_rg_state == 2'd1 ;
assign WILL_FIRE_RL_m_compute = CAN_FIRE_RL_m_compute ;
// inputs to muxes for submodule ports
assign MUX_m_rg_x$write_1__VAL_1 = { 64'd0, _theResult___fst__h506 } ;
assign MUX_m_rg_x$write_1__VAL_2 = { m_rg_x[126:0], 1'd0 } ;
assign MUX_m_rg_xy$write_1__VAL_2 = (m_rg_y == 64'd0) ? x__h236 : x__h338 ;
assign MUX_m_rg_y$write_1__VAL_1 =
(put_args_x_is_signed && put_args_y_is_signed) ?
_theResult___fst__h563 :
_theResult___snd_fst__h555 ;
assign MUX_m_rg_y$write_1__VAL_2 = { 1'd0, m_rg_y[63:1] } ;
// register m_rg_isNeg
assign m_rg_isNeg$D_IN =
(put_args_x_is_signed && put_args_y_is_signed) ?
put_args_x[63] != put_args_y[63] :
IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d34 ;
assign m_rg_isNeg$EN = EN_put_args ;
// register m_rg_signed
assign m_rg_signed$D_IN = 1'b0 ;
assign m_rg_signed$EN = 1'b0 ;
// register m_rg_state
assign m_rg_state$D_IN = EN_put_args ? 2'd1 : 2'd2 ;
assign m_rg_state$EN =
WILL_FIRE_RL_m_compute && m_rg_y == 64'd0 || EN_put_args ;
// register m_rg_x
assign m_rg_x$D_IN =
EN_put_args ?
MUX_m_rg_x$write_1__VAL_1 :
MUX_m_rg_x$write_1__VAL_2 ;
assign m_rg_x$EN =
WILL_FIRE_RL_m_compute && m_rg_y != 64'd0 || EN_put_args ;
// register m_rg_xy
assign m_rg_xy$D_IN = EN_put_args ? 128'd0 : MUX_m_rg_xy$write_1__VAL_2 ;
assign m_rg_xy$EN =
WILL_FIRE_RL_m_compute && (m_rg_y == 64'd0 || m_rg_y[0]) ||
EN_put_args ;
// register m_rg_y
assign m_rg_y$D_IN =
EN_put_args ?
MUX_m_rg_y$write_1__VAL_1 :
MUX_m_rg_y$write_1__VAL_2 ;
assign m_rg_y$EN =
WILL_FIRE_RL_m_compute && m_rg_y != 64'd0 || EN_put_args ;
// remaining internal signals
assign IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d34 =
put_args_x_is_signed ?
put_args_x[63] :
put_args_y_is_signed && put_args_y[63] ;
assign _theResult___fst__h506 =
put_args_x_is_signed ? _theResult___fst__h509 : put_args_x ;
assign _theResult___fst__h509 = put_args_x[63] ? -put_args_x : put_args_x ;
assign _theResult___fst__h560 =
put_args_y_is_signed ? _theResult___fst__h563 : put_args_y ;
assign _theResult___fst__h563 = put_args_y[63] ? -put_args_y : put_args_y ;
assign _theResult___snd_fst__h555 =
put_args_x_is_signed ? put_args_y : _theResult___fst__h560 ;
assign x__h236 = m_rg_isNeg ? xy___1__h262 : m_rg_xy ;
assign x__h338 = m_rg_xy + m_rg_x ;
assign xy___1__h262 = -m_rg_xy ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
m_rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
end
else
begin
if (m_rg_state$EN)
m_rg_state <= `BSV_ASSIGNMENT_DELAY m_rg_state$D_IN;
end
if (m_rg_isNeg$EN) m_rg_isNeg <= `BSV_ASSIGNMENT_DELAY m_rg_isNeg$D_IN;
if (m_rg_signed$EN) m_rg_signed <= `BSV_ASSIGNMENT_DELAY m_rg_signed$D_IN;
if (m_rg_x$EN) m_rg_x <= `BSV_ASSIGNMENT_DELAY m_rg_x$D_IN;
if (m_rg_xy$EN) m_rg_xy <= `BSV_ASSIGNMENT_DELAY m_rg_xy$D_IN;
if (m_rg_y$EN) m_rg_y <= `BSV_ASSIGNMENT_DELAY m_rg_y$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
m_rg_isNeg = 1'h0;
m_rg_signed = 1'h0;
m_rg_state = 2'h2;
m_rg_x = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
m_rg_xy = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
m_rg_y = 64'hAAAAAAAAAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkIntMul_64
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_pixout #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output reg busy,
input pipe_stb_i,
output reg pipe_ack_o,
input [fml_depth-5-1:0] burst_addr,
input [15:0] burst_sel,
input [255:0] burst_do,
output reg [fml_depth-1:0] fml_adr,
output reg fml_stb,
input fml_ack,
output reg [7:0] fml_sel,
output reg [63:0] fml_do
);
reg [15:0] burst_sel_r;
reg [255:0] burst_do_r;
reg load;
always @(posedge sys_clk) begin
if(load) begin
fml_adr = {burst_addr, 5'd0};
burst_sel_r = burst_sel;
burst_do_r = burst_do;
end
end
reg [1:0] bcounter;
always @(posedge sys_clk) begin
case(bcounter)
2'd0: begin
fml_sel <= {
burst_sel_r[15], burst_sel_r[15],
burst_sel_r[14], burst_sel_r[14],
burst_sel_r[13], burst_sel_r[13],
burst_sel_r[12], burst_sel_r[12]
};
fml_do <= burst_do_r[255:192];
end
2'd1: begin
fml_sel <= {
burst_sel_r[11], burst_sel_r[11],
burst_sel_r[10], burst_sel_r[10],
burst_sel_r[ 9], burst_sel_r[ 9],
burst_sel_r[ 8], burst_sel_r[ 8]
};
fml_do <= burst_do_r[191:128];
end
2'd2: begin
fml_sel <= {
burst_sel_r[ 7], burst_sel_r[ 7],
burst_sel_r[ 6], burst_sel_r[ 6],
burst_sel_r[ 5], burst_sel_r[ 5],
burst_sel_r[ 4], burst_sel_r[ 4]
};
fml_do <= burst_do_r[127: 64];
end
2'd3: begin
fml_sel <= {
burst_sel_r[ 3], burst_sel_r[ 3],
burst_sel_r[ 2], burst_sel_r[ 2],
burst_sel_r[ 1], burst_sel_r[ 1],
burst_sel_r[ 0], burst_sel_r[ 0]
};
fml_do <= burst_do_r[ 63: 0];
end
endcase
end
reg [1:0] state;
reg [1:0] next_state;
parameter IDLE = 2'd0;
parameter WAIT = 2'd1;
parameter XFER2 = 2'd2;
parameter XFER3 = 2'd3;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else
state <= next_state;
end
always @(*) begin
next_state = state;
busy = 1'b1;
pipe_ack_o = 1'b0;
fml_stb = 1'b0;
load = 1'b0;
bcounter = 2'bxx;
case(state)
IDLE: begin
busy = 1'b0;
pipe_ack_o = 1'b1;
bcounter = 2'd0;
if(pipe_stb_i) begin
load = 1'b1;
next_state = WAIT;
end
end
WAIT: begin
fml_stb = 1'b1;
bcounter = 2'd0;
if(fml_ack) begin
bcounter = 2'd1;
next_state = XFER2;
end
end
XFER2: begin
bcounter = 2'd2;
next_state = XFER3;
end
XFER3: begin
bcounter = 2'd3;
next_state = IDLE;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31OI_M_V
`define SKY130_FD_SC_LP__A31OI_M_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31oi with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a31oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a31oi_m (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a31oi_m (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31OI_M_V
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: asyn_128_93.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.0 Build 145 04/22/2015 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module asyn_128_93 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [92:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [92:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [92:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [92:0] q = sub_wire0[92:0];
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.wrfull (sub_wire2),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Stratix V",
dcfifo_component.lpm_numwords = 128,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 93,
dcfifo_component.lpm_widthu = 7,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "93"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "93"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "93"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 93 0 INPUT NODEFVAL "data[92..0]"
// Retrieval info: USED_PORT: q 0 0 93 0 OUTPUT NODEFVAL "q[92..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 93 0 data 0 0 93 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 93 0 @q 0 0 93 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_128_93.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_128_93.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_128_93.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_128_93.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_128_93_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_128_93_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41A_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O41A_PP_SYMBOL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o41a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input A4 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41A_PP_SYMBOL_V
|
module spw_babasu (
autostart_external_connection_export,
clk_clk,
currentstate_external_connection_export,
data_i_external_connection_export,
data_o_external_connection_export,
flags_external_connection_export,
link_disable_external_connection_export,
link_start_external_connection_export,
pll_0_locked_export,
pll_0_outclk0_clk,
rd_data_external_connection_export,
reset_reset_n,
rx_empty_external_connection_export,
spill_enable_external_connection_export,
tick_in_external_connection_export,
tick_out_external_connection_export,
time_in_external_connection_export,
time_out_external_connection_export,
tx_clk_div_external_connection_export,
tx_full_external_connection_export,
wr_data_external_connection_export);
output autostart_external_connection_export;
input clk_clk;
input [2:0] currentstate_external_connection_export;
output [8:0] data_i_external_connection_export;
input [8:0] data_o_external_connection_export;
input [10:0] flags_external_connection_export;
output link_disable_external_connection_export;
output link_start_external_connection_export;
output pll_0_locked_export;
output pll_0_outclk0_clk;
output rd_data_external_connection_export;
input reset_reset_n;
input rx_empty_external_connection_export;
output spill_enable_external_connection_export;
output tick_in_external_connection_export;
input tick_out_external_connection_export;
output [7:0] time_in_external_connection_export;
input [7:0] time_out_external_connection_export;
output [6:0] tx_clk_div_external_connection_export;
input tx_full_external_connection_export;
output wr_data_external_connection_export;
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcieCore_axi_basic_tx.v
// Version : 1.11
// //
// Description: //
// AXI to TRN TX module. Instantiates pipeline and throttle control TX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_tx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcieCore_axi_basic_tx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
input user_clk, // user clock from block
input user_rst // user reset from block
);
wire tready_thrtl;
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
pcieCore_axi_basic_tx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) tx_pipeline_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tecrc_gen( trn_tecrc_gen ),
.trn_lnk_up( trn_lnk_up ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Throttle Controller //
//---------------------------------------------//
generate
if(C_PM_PRIORITY == "FALSE") begin : thrtl_ctl_enabled
pcieCore_axi_basic_tx_thrtl_ctl #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.TCQ( TCQ )
) tx_thrl_ctl_inst (
// Outgoing AXI TX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Incoming TRN RX
//-----------
.trn_tbuf_av( trn_tbuf_av ),
.trn_tdst_rdy( trn_tdst_rdy ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Seriesq/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
end
else begin : thrtl_ctl_disabled
assign tready_thrtl = 1'b0;
assign cfg_turnoff_ok = user_turnoff_ok;
assign trn_tcfg_gnt = user_tcfg_gnt;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2O_TB_V
`define SKY130_FD_SC_MS__A2BB2O_TB_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a2bb2o.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1_N = 1'b1;
#200 A2_N = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1_N = 1'b0;
#360 A2_N = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2_N = 1'b1;
#640 A1_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2_N = 1'bx;
#800 A1_N = 1'bx;
end
sky130_fd_sc_ms__a2bb2o dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2O_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EBUFN_8_V
`define SKY130_FD_SC_HS__EBUFN_8_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__ebufn_8 (
A ,
TE_B,
Z ,
VPWR,
VGND
);
input A ;
input TE_B;
output Z ;
input VPWR;
input VGND;
sky130_fd_sc_hs__ebufn base (
.A(A),
.TE_B(TE_B),
.Z(Z),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__ebufn_8 (
A ,
TE_B,
Z
);
input A ;
input TE_B;
output Z ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__ebufn base (
.A(A),
.TE_B(TE_B),
.Z(Z)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__EBUFN_8_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_PP_V
/**
* lpflow_inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_l_pp_pg/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__lpflow_inputiso1p (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, A, SLEEP );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , or0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_PP_V |
`timescale 1 ns / 1 ps
module axis_histogram #
(
parameter integer AXIS_TDATA_WIDTH = 16,
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 14
)
(
// System signals
input wire aclk,
input wire aresetn,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// BRAM port
output wire bram_porta_clk,
output wire bram_porta_rst,
output wire [BRAM_ADDR_WIDTH-1:0] bram_porta_addr,
output wire [BRAM_DATA_WIDTH-1:0] bram_porta_wrdata,
input wire [BRAM_DATA_WIDTH-1:0] bram_porta_rddata,
output wire bram_porta_we
);
reg [BRAM_ADDR_WIDTH-1:0] int_addr_reg, int_addr_next;
reg [1:0] int_case_reg, int_case_next;
reg int_tready_reg, int_tready_next;
reg int_wren_reg, int_wren_next;
reg int_zero_reg, int_zero_next;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_addr_reg <= {(BRAM_ADDR_WIDTH){1'b0}};
int_case_reg <= 2'd0;
int_tready_reg <= 1'b0;
int_wren_reg <= 1'b1;
int_zero_reg <= 1'b1;
end
else
begin
int_addr_reg <= int_addr_next;
int_case_reg <= int_case_next;
int_tready_reg <= int_tready_next;
int_wren_reg <= int_wren_next;
int_zero_reg <= int_zero_next;
end
end
always @*
begin
int_addr_next = int_addr_reg;
int_case_next = int_case_reg;
int_tready_next = int_tready_reg;
int_wren_next = int_wren_reg;
int_zero_next = int_zero_reg;
case(int_case_reg)
0:
begin
// write zeros
int_addr_next = int_addr_reg + 1'b1;
if(&int_addr_reg)
begin
int_tready_next = 1'b1;
int_wren_next = 1'b0;
int_zero_next = 1'b0;
int_case_next = 2'd1;
end
end
1:
begin
if(s_axis_tvalid)
begin
int_addr_next = s_axis_tdata[BRAM_ADDR_WIDTH-1:0];
int_tready_next = 1'b0;
int_case_next = 2'd2;
end
end
2:
begin
int_wren_next = 1'b1;
int_case_next = 2'd3;
end
3:
begin
int_tready_next = 1'b1;
int_wren_next = 1'b0;
int_case_next = 2'd1;
end
endcase
end
assign s_axis_tready = int_tready_reg;
assign bram_porta_clk = aclk;
assign bram_porta_rst = ~aresetn;
assign bram_porta_addr = int_wren_reg ? int_addr_reg : s_axis_tdata[BRAM_ADDR_WIDTH-1:0];
assign bram_porta_wrdata = int_zero_reg ? {(BRAM_DATA_WIDTH){1'b0}} : (bram_porta_rddata + 1'b1);
assign bram_porta_we = int_zero_reg ? 1'b1 : (int_wren_reg & ~&bram_porta_rddata);
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:49:40 05/27/2013
// Design Name:
// Module Name: initial_dram
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// ä»Flash读表å°DRAMä¸ï¼è¯»å¯åå¨å¼å°FPGAå¯åå¨ã
// ä½ä¸ºftl-topçä¸ä¸ªæ¨¡åï¼å°ä½ä¸io_scheduleç¸å½ï¼å¯ç±»æ¯io-scheduleç¼åã
// 交äºæ¨¡åï¼dram,controller_command_fifo
//////////////////////////////////////////////////////////////////////////////////
module initial_dram(
reset,
clk,
trigger_initial_dram,
//input
all_Cmd_Available_flag, //
//output
controller_command_fifo_in, // din
controller_command_fifo_in_en // wr_en
);
`include "ftl_define.v"
input reset;
input clk;
input trigger_initial_dram;
input all_Cmd_Available_flag;
output [COMMAND_WIDTH-1:0] controller_command_fifo_in;
output [7:0] controller_command_fifo_in_en;
reg [COMMAND_WIDTH-1:0] controller_command_fifo_in;
reg [7:0] controller_command_fifo_in_en;
reg [2:0]state;
reg [CHANNEL_ADDR_WIDTH-1:0]channel_index;
reg [7:0] enable;
reg [23:0] page_addr;
reg [DRAM_ADDR_WIDTH-1:0] dram_addr;
parameter PREPARE_FOR_READ =3'b000;
parameter SEND_READ_COMMAND =3'b001;
parameter CHANGE_PAGE_ADDR =3'b010;
parameter READ_REGISTER =3'b011;
parameter DONE =3'b100;
always@(posedge clk or negedge reset )
begin
if(!reset)
begin
state <= PREPARE_FOR_READ;
page_addr <= BADBLOCK_FLASH_ADDR1;
dram_addr <= BAD_BLOCK_INFO_BASE;
channel_index <= 3'b0;
end
else
begin
case(state)
PREPARE_FOR_READ:
begin
if(trigger_initial_dram)
begin
case(channel_index)
3'b000:enable<=8'b00000001;
3'b001:enable<=8'b00000010;
3'b010:enable<=8'b00000100;
3'b011:enable<=8'b00001000;
3'b100:enable<=8'b00010000;
3'b101:enable<=8'b00100000;
3'b110:enable<=8'b01000000;
3'b111:enable<=8'b10000000;
endcase
state <= SEND_READ_COMMAND;
end
else
state <= PREPARE_FOR_READ;
end
SEND_READ_COMMAND:
begin
if(all_Cmd_Available_flag==1'b1)
begin
controller_command_fifo_in <= {{READ, 1'b0,2'b10,27'b0},{5'b0,channel_index[2:0],page_addr[23:0]},{12'b0,dram_addr[28:12],channel_index[2:0]}, {5'b0,page_addr[23:0],channel_index[2:0]}}; //32+(7+25)+(14+18)+32
controller_command_fifo_in_en<=enable;
channel_index <=channel_index + 1'b1;
state <=CHANGE_PAGE_ADDR;
end
else
state <= SEND_READ_COMMAND;
end
CHANGE_PAGE_ADDR:
begin
controller_command_fifo_in_en<=8'b00000000;
if(channel_index ==3'b000)
begin
if(page_addr == (BADBLOCK_FLASH_ADDR2))
begin
controller_command_fifo_in <= {READ,1'b0,2'b01,27'b0,10'b0,REGISTER_BASE_FLASH,64'hffff_ffff_ffff_ffff};
state <= READ_REGISTER;
end
else
begin
page_addr <= page_addr+4'b1_000;
dram_addr <= dram_addr+13'b1_0000_0000_0000;
state <= PREPARE_FOR_READ;
end
end
else
state <= PREPARE_FOR_READ;
end
READ_REGISTER:
begin
if(all_Cmd_Available_flag==1'b1)
begin
controller_command_fifo_in <= {READ,1'b0,2'b01,27'b0,10'b0,REGISTER_BASE_FLASH,64'hffff_ffff_ffff_ffff};
controller_command_fifo_in_en <=8'b00000001;
state <=DONE;
end
else
state <= READ_REGISTER;
end
DONE:
begin
controller_command_fifo_in_en<=8'b00000000;
state <=DONE;
end
default:
state<= PREPARE_FOR_READ;
endcase
end
end
endmodule
|
/*
* pll_adv_example.v: Example program working in simulation as well as it should on real hardware.
* To be tested on Digilent Basys 3.
* author: Till Mahlburg
* year: 2019
* organization: Universität Leipzig
* license: ISC
*
*/
`timescale 1 ns / 1 ps
module pll_adv_example (
input clk,
input RST,
output [7:0] led);
reg [6:0] DADDR;
reg [15:0] DI;
wire [15:0] DO;
reg DEN;
reg DWE;
wire DRDY;
wire CLKFB;
/* More information about the instantiiation can be found in Xilinx UG953 509ff. */
PLLE2_ADV #(
.CLKFBOUT_MULT(8),
.CLKFBOUT_PHASE(90.0),
.CLKIN1_PERIOD(10.0),
.CLKIN2_PERIOD(10.0),
.CLKOUT0_DIVIDE(128),
.CLKOUT1_DIVIDE(2),
.CLKOUT2_DIVIDE(32),
.CLKOUT3_DIVIDE(16),
.CLKOUT4_DIVIDE(128),
.CLKOUT5_DIVIDE(128),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.9),
.CLKOUT5_DUTY_CYCLE(0.1),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.DIVCLK_DIVIDE(1))
pll (
.CLKOUT0(led[0]),
.CLKOUT1(led[1]),
.CLKOUT2(led[2]),
.CLKOUT3(led[3]),
.CLKOUT4(led[5]),
.CLKOUT5(led[6]),
.CLKFBOUT(CLKFB),
.LOCKED(led[7]),
.CLKIN1(clk),
.CLKIN2(clk),
.CLKINSEL(1'b1),
.DADDR(DADDR),
.DI(DI),
.DO(DO),
.DWE(DWE),
.DEN(DEN),
.DRDY(DRDY),
.DCLK(led[0]),
.PWRDWN(0),
.RST(RST),
.CLKFBIN(CLKFB));
integer step = 0;
/* CLKOUT1 will be dynamically reconfigured */
always @(posedge clk) begin
/* After some time to achieve LOCK & DRDY status, we can write the first value into ClkReg1
* for CLKOUT1 */
if (led[7] && DRDY && step == 0) begin
/* Address of ClkReg1 for CLKOUT1 */
DADDR <= 7'h0A;
/* PHASE MUX = 3
* RESERVED = 0
* HIGH TIME = 16
* LOW TIME = 32 */
/* This translates to a CLKOUT1_DIVDE of 48, a CLKOUT1_DUTY_CYCLE of 0.666
* and a phase offset of 3x45° relative to the VCO */
DI = 16'b011_0_010000_100000;
DEN <= 1;
DWE <= 1;
step <= 1;
/* Next, we will disable DEN and DWE, as soon as DRDY and LOCK are achieved again */
end else if (led[7] && step == 1) begin
DEN <= 0;
DWE <= 0;
step <= 2;
/* Now we will write into ClkReg2 for CLKOUT1 */
end else if (led[7] && DRDY && step == 2) begin
DEN <= 1;
DWE <= 1;
/* Address of ClkReg2 of CLKOUT1 */
DADDR = 7'h0B;
/* RESERVED = 000000
* MX = 2b'00
* EDGE = 0
* NO COUNT = 0
* DELAY TIME = 3 */
/* This will add an additional phase delay as high as 3 VCO clock cycles */
DI <= 16'b000000_00_0_0_000011;
step <= 3;
end else if (led[7] && step == 3) begin
/* Disable Read/Write again */
DEN <= 0;
DWE <= 0;
step <= 4;
end
end
endmodule
|
`default_nettype none
module l1_inst_cache_64entry_4way_line64b_bus_8b_disable_cache(
/********************************
System
********************************/
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Remove
input wire iREMOVE,
/********************************
Search
********************************/
//Search Request
input wire iRD_REQ,
output wire oRD_BUSY,
input wire [31:0] iRD_ADDR, //Tag:22bit | Index:4bit(4Way*16Entry) | LineSize:6bit(64B)
//Search Output Result
output wire oRD_VALID,
output wire oRD_HIT,
input wire iRD_BUSY,
output wire [63:0] oRD_DATA,
output wire [23:0] oRD_MMU_FLAGS,
/********************************
Write Request
********************************/
input wire iWR_REQ,
output wire oWR_BUSY,
input wire [31:0] iWR_ADDR, //Tag:22bit | Index:4bit(4Way*16Entry) | LineSize:6bit(64B)
input wire [511:0] iWR_DATA,
input wire [255:0] iWR_MMU_FLAGS
);
assign oRD_BUSY = 1'b0;
reg b_req_valid;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_req_valid <= 1'b0;
end
else if(iRESET_SYNC)begin
b_req_valid <= 1'b0;
end
else if(iREMOVE)begin
b_req_valid <= 1'b0;
end
else begin
b_req_valid <= iRD_REQ;
end
end
assign oRD_VALID = b_req_valid;
assign oRD_HIT = 1'b0;
assign oRD_DATA = 64'h0;
assign oRD_MMU_FLAGS = 23'h0;
assign oWR_BUSY = 1'b0;
endmodule
`default_nettype wire |
/*
* Z80 instruction decoder
* Author: Guy Hutchison
*/
module op_decode;
task decode0;
input [7:0] opcode;
inout [7:0] state;
begin
case (opcode)
8'h00 : $display ("%t: OPCODE : NOP ", $time);
8'h01 :
begin
$display ("%t: OPCODE : LD BC,word", $time);
state = {4'd1, 4'd2};
end
8'h02 : $display ("%t: OPCODE : LD (BC),A", $time);
8'h03 : $display ("%t: OPCODE : INC BC", $time);
8'h04 : $display ("%t: OPCODE : INC B", $time);
8'h05 : $display ("%t: OPCODE : DEC B", $time);
8'h06 :
begin
$display ("%t: OPCODE : LD B,byte", $time);
state = {4'd1, 4'd1};
end
8'h07 : $display ("%t: OPCODE : RLCA ", $time);
8'h08 : $display ("%t: OPCODE : EX AF,AF'", $time);
8'h09 : $display ("%t: OPCODE : ADD HL,BC", $time);
8'h0a : $display ("%t: OPCODE : LD A,(BC)", $time);
8'h0b : $display ("%t: OPCODE : DEC BC", $time);
8'h0c : $display ("%t: OPCODE : INC C", $time);
8'h0d : $display ("%t: OPCODE : DEC C", $time);
8'h0e :
begin
$display ("%t: OPCODE : LD C,byte", $time);
state = {4'd1, 4'd1};
end
8'h0f : $display ("%t: OPCODE : RRCA ", $time);
8'h10 :
begin
$display ("%t: OPCODE : DJNZ index", $time);
state = {4'd1, 4'd1};
end
8'h11 :
begin
$display ("%t: OPCODE : LD DE,word", $time);
state = {4'd1, 4'd2};
end
8'h12 : $display ("%t: OPCODE : LD (DE),A", $time);
8'h13 : $display ("%t: OPCODE : INC DE", $time);
8'h14 : $display ("%t: OPCODE : INC D", $time);
8'h15 : $display ("%t: OPCODE : DEC D", $time);
8'h16 :
begin
$display ("%t: OPCODE : LD D,byte", $time);
state = {4'd1, 4'd1};
end
8'h17 : $display ("%t: OPCODE : RLA ", $time);
8'h18 :
begin
$display ("%t: OPCODE : JR index", $time);
state = {4'd1, 4'd1};
end
8'h19 : $display ("%t: OPCODE : ADD HL,DE", $time);
8'h1a : $display ("%t: OPCODE : LD A,(DE)", $time);
8'h1b : $display ("%t: OPCODE : DEC DE", $time);
8'h1c : $display ("%t: OPCODE : INC E", $time);
8'h1d : $display ("%t: OPCODE : DEC E", $time);
8'h1e :
begin
$display ("%t: OPCODE : LD E,byte", $time);
state = {4'd1, 4'd1};
end
8'h1f : $display ("%t: OPCODE : RRA ", $time);
8'h20 :
begin
$display ("%t: OPCODE : JR NZ,index", $time);
state = {4'd1, 4'd1};
end
8'h21 :
begin
$display ("%t: OPCODE : LD HL,word", $time);
state = {4'd1, 4'd2};
end
8'h22 :
begin
$display ("%t: OPCODE : LD (word),HL", $time);
state = {4'd1, 4'd2};
end
8'h23 : $display ("%t: OPCODE : INC HL", $time);
8'h24 : $display ("%t: OPCODE : INC H", $time);
8'h25 : $display ("%t: OPCODE : DEC H", $time);
8'h26 :
begin
$display ("%t: OPCODE : LD H,byte", $time);
state = {4'd1, 4'd1};
end
8'h27 : $display ("%t: OPCODE : DAA ", $time);
8'h28 :
begin
$display ("%t: OPCODE : JR Z,index", $time);
state = {4'd1, 4'd1};
end
8'h29 : $display ("%t: OPCODE : ADD HL,HL", $time);
8'h2a :
begin
$display ("%t: OPCODE : LD HL,(word)", $time);
state = {4'd1, 4'd2};
end
8'h2b : $display ("%t: OPCODE : DEC HL", $time);
8'h2c : $display ("%t: OPCODE : INC L", $time);
8'h2d : $display ("%t: OPCODE : DEC L", $time);
8'h2e :
begin
$display ("%t: OPCODE : LD L,byte", $time);
state = {4'd1, 4'd1};
end
8'h2f : $display ("%t: OPCODE : CPL ", $time);
8'h30 :
begin
$display ("%t: OPCODE : JR NC,index", $time);
state = {4'd1, 4'd1};
end
8'h31 :
begin
$display ("%t: OPCODE : LD SP,word", $time);
state = {4'd1, 4'd2};
end
8'h32 :
begin
$display ("%t: OPCODE : LD (word),A", $time);
state = {4'd1, 4'd2};
end
8'h33 : $display ("%t: OPCODE : INC SP", $time);
8'h34 : $display ("%t: OPCODE : INC (HL)", $time);
8'h35 : $display ("%t: OPCODE : DEC (HL)", $time);
8'h36 :
begin
$display ("%t: OPCODE : LD (HL),byte", $time);
state = {4'd1, 4'd1};
end
8'h37 : $display ("%t: OPCODE : SCF ", $time);
8'h38 :
begin
$display ("%t: OPCODE : JR C,index", $time);
state = {4'd1, 4'd1};
end
8'h39 : $display ("%t: OPCODE : ADD HL,SP", $time);
8'h3a :
begin
$display ("%t: OPCODE : LD A,(word)", $time);
state = {4'd1, 4'd2};
end
8'h3b : $display ("%t: OPCODE : DEC SP", $time);
8'h3c : $display ("%t: OPCODE : INC A", $time);
8'h3d : $display ("%t: OPCODE : DEC A", $time);
8'h3e :
begin
$display ("%t: OPCODE : LD A,byte", $time);
state = {4'd1, 4'd1};
end
8'h3f : $display ("%t: OPCODE : CCF ", $time);
8'h40 : $display ("%t: OPCODE : LD B,B", $time);
8'h41 : $display ("%t: OPCODE : LD B,C", $time);
8'h42 : $display ("%t: OPCODE : LD B,D", $time);
8'h43 : $display ("%t: OPCODE : LD B,E", $time);
8'h44 : $display ("%t: OPCODE : LD B,H", $time);
8'h45 : $display ("%t: OPCODE : LD B,L", $time);
8'h46 : $display ("%t: OPCODE : LD B,(HL)", $time);
8'h47 : $display ("%t: OPCODE : LD B,A", $time);
8'h48 : $display ("%t: OPCODE : LD C,B", $time);
8'h49 : $display ("%t: OPCODE : LD C,C", $time);
8'h4a : $display ("%t: OPCODE : LD C,D", $time);
8'h4b : $display ("%t: OPCODE : LD C,E", $time);
8'h4c : $display ("%t: OPCODE : LD C,H", $time);
8'h4d : $display ("%t: OPCODE : LD C,L", $time);
8'h4e : $display ("%t: OPCODE : LD C,(HL)", $time);
8'h4f : $display ("%t: OPCODE : LD C,A", $time);
8'h50 : $display ("%t: OPCODE : LD D,B", $time);
8'h51 : $display ("%t: OPCODE : LD D,C", $time);
8'h52 : $display ("%t: OPCODE : LD D,D", $time);
8'h53 : $display ("%t: OPCODE : LD D,E", $time);
8'h54 : $display ("%t: OPCODE : LD D,H", $time);
8'h55 : $display ("%t: OPCODE : LD D,L", $time);
8'h56 : $display ("%t: OPCODE : LD D,(HL)", $time);
8'h57 : $display ("%t: OPCODE : LD D,A", $time);
8'h58 : $display ("%t: OPCODE : LD E,B", $time);
8'h59 : $display ("%t: OPCODE : LD E,C", $time);
8'h5a : $display ("%t: OPCODE : LD E,D", $time);
8'h5b : $display ("%t: OPCODE : LD E,E", $time);
8'h5c : $display ("%t: OPCODE : LD E,H", $time);
8'h5d : $display ("%t: OPCODE : LD E,L", $time);
8'h5e : $display ("%t: OPCODE : LD E,(HL)", $time);
8'h5f : $display ("%t: OPCODE : LD E,A", $time);
8'h60 : $display ("%t: OPCODE : LD H,B", $time);
8'h61 : $display ("%t: OPCODE : LD H,C", $time);
8'h62 : $display ("%t: OPCODE : LD H,D", $time);
8'h63 : $display ("%t: OPCODE : LD H,E", $time);
8'h64 : $display ("%t: OPCODE : LD H,H", $time);
8'h65 : $display ("%t: OPCODE : LD H,L", $time);
8'h66 : $display ("%t: OPCODE : LD H,(HL)", $time);
8'h67 : $display ("%t: OPCODE : LD H,A", $time);
8'h68 : $display ("%t: OPCODE : LD L,B", $time);
8'h69 : $display ("%t: OPCODE : LD L,C", $time);
8'h6a : $display ("%t: OPCODE : LD L,D", $time);
8'h6b : $display ("%t: OPCODE : LD L,E", $time);
8'h6c : $display ("%t: OPCODE : LD L,H", $time);
8'h6d : $display ("%t: OPCODE : LD L,L", $time);
8'h6e : $display ("%t: OPCODE : LD L,(HL)", $time);
8'h6f : $display ("%t: OPCODE : LD L,A", $time);
8'h70 : $display ("%t: OPCODE : LD (HL),B", $time);
8'h71 : $display ("%t: OPCODE : LD (HL),C", $time);
8'h72 : $display ("%t: OPCODE : LD (HL),D", $time);
8'h73 : $display ("%t: OPCODE : LD (HL),E", $time);
8'h74 : $display ("%t: OPCODE : LD (HL),H", $time);
8'h75 : $display ("%t: OPCODE : LD (HL),L", $time);
8'h76 : $display ("%t: OPCODE : HLT ", $time);
8'h77 : $display ("%t: OPCODE : LD (HL),A", $time);
8'h78 : $display ("%t: OPCODE : LD A,B", $time);
8'h79 : $display ("%t: OPCODE : LD A,C", $time);
8'h7a : $display ("%t: OPCODE : LD A,D", $time);
8'h7b : $display ("%t: OPCODE : LD A,E", $time);
8'h7c : $display ("%t: OPCODE : LD A,H", $time);
8'h7d : $display ("%t: OPCODE : LD A,L", $time);
8'h7e : $display ("%t: OPCODE : LD A,(HL)", $time);
8'h7f : $display ("%t: OPCODE : LD A,A", $time);
8'h80 : $display ("%t: OPCODE : ADD A,B", $time);
8'h81 : $display ("%t: OPCODE : ADD A,C", $time);
8'h82 : $display ("%t: OPCODE : ADD A,D", $time);
8'h83 : $display ("%t: OPCODE : ADD A,E", $time);
8'h84 : $display ("%t: OPCODE : ADD A,H", $time);
8'h85 : $display ("%t: OPCODE : ADD A,L", $time);
8'h86 : $display ("%t: OPCODE : ADD A,(HL)", $time);
8'h87 : $display ("%t: OPCODE : ADD A,A", $time);
8'h88 : $display ("%t: OPCODE : ADC A,B", $time);
8'h89 : $display ("%t: OPCODE : ADC A,C", $time);
8'h8a : $display ("%t: OPCODE : ADC A,D", $time);
8'h8b : $display ("%t: OPCODE : ADC A,E", $time);
8'h8c : $display ("%t: OPCODE : ADC A,H", $time);
8'h8d : $display ("%t: OPCODE : ADC A,L", $time);
8'h8e : $display ("%t: OPCODE : ADC A,(HL)", $time);
8'h8f : $display ("%t: OPCODE : ADC A,A", $time);
8'h90 : $display ("%t: OPCODE : SUB B", $time);
8'h91 : $display ("%t: OPCODE : SUB C", $time);
8'h92 : $display ("%t: OPCODE : SUB D", $time);
8'h93 : $display ("%t: OPCODE : SUB E", $time);
8'h94 : $display ("%t: OPCODE : SUB H", $time);
8'h95 : $display ("%t: OPCODE : SUB L", $time);
8'h96 : $display ("%t: OPCODE : SUB (HL)", $time);
8'h97 : $display ("%t: OPCODE : SUB A", $time);
8'h98 : $display ("%t: OPCODE : SBC B", $time);
8'h99 : $display ("%t: OPCODE : SBC C", $time);
8'h9a : $display ("%t: OPCODE : SBC D", $time);
8'h9b : $display ("%t: OPCODE : SBC E", $time);
8'h9c : $display ("%t: OPCODE : SBC H", $time);
8'h9d : $display ("%t: OPCODE : SBC L", $time);
8'h9e : $display ("%t: OPCODE : SBC (HL)", $time);
8'h9f : $display ("%t: OPCODE : SBC A", $time);
8'ha0 : $display ("%t: OPCODE : AND B", $time);
8'ha1 : $display ("%t: OPCODE : AND C", $time);
8'ha2 : $display ("%t: OPCODE : AND D", $time);
8'ha3 : $display ("%t: OPCODE : AND E", $time);
8'ha4 : $display ("%t: OPCODE : AND H", $time);
8'ha5 : $display ("%t: OPCODE : AND L", $time);
8'ha6 : $display ("%t: OPCODE : AND (HL)", $time);
8'ha7 : $display ("%t: OPCODE : AND A", $time);
8'ha8 : $display ("%t: OPCODE : XOR B", $time);
8'ha9 : $display ("%t: OPCODE : XOR C", $time);
8'haa : $display ("%t: OPCODE : XOR D", $time);
8'hab : $display ("%t: OPCODE : XOR E", $time);
8'hac : $display ("%t: OPCODE : XOR H", $time);
8'had : $display ("%t: OPCODE : XOR L", $time);
8'hae : $display ("%t: OPCODE : XOR (HL)", $time);
8'haf : $display ("%t: OPCODE : XOR A", $time);
8'hb0 : $display ("%t: OPCODE : OR B", $time);
8'hb1 : $display ("%t: OPCODE : OR C", $time);
8'hb2 : $display ("%t: OPCODE : OR D", $time);
8'hb3 : $display ("%t: OPCODE : OR E", $time);
8'hb4 : $display ("%t: OPCODE : OR H", $time);
8'hb5 : $display ("%t: OPCODE : OR L", $time);
8'hb6 : $display ("%t: OPCODE : OR (HL)", $time);
8'hb7 : $display ("%t: OPCODE : OR A", $time);
8'hb8 : $display ("%t: OPCODE : CP B", $time);
8'hb9 : $display ("%t: OPCODE : CP C", $time);
8'hba : $display ("%t: OPCODE : CP D", $time);
8'hbb : $display ("%t: OPCODE : CP E", $time);
8'hbc : $display ("%t: OPCODE : CP H", $time);
8'hbd : $display ("%t: OPCODE : CP L", $time);
8'hbe : $display ("%t: OPCODE : CP (HL)", $time);
8'hbf : $display ("%t: OPCODE : CP A", $time);
8'hc0 : $display ("%t: OPCODE : RET NZ", $time);
8'hc1 : $display ("%t: OPCODE : POP BC", $time);
8'hc2 :
begin
$display ("%t: OPCODE : JP NZ,address", $time);
state = {4'd1, 4'd2};
end
8'hc3 :
begin
$display ("%t: OPCODE : JP address", $time);
state = {4'd1, 4'd2};
end
8'hc4 :
begin
$display ("%t: OPCODE : CALL NZ,address", $time);
state = {4'd1, 4'd2};
end
8'hc5 : $display ("%t: OPCODE : PUSH BC", $time);
8'hc6 :
begin
$display ("%t: OPCODE : ADD A,byte", $time);
state = {4'd1, 4'd1};
end
8'hc7 : $display ("%t: OPCODE : RST 0", $time);
8'hc8 : $display ("%t: OPCODE : RET Z", $time);
8'hc9 : $display ("%t: OPCODE : RET ", $time);
8'hca :
begin
$display ("%t: OPCODE : JP Z,address", $time);
state = {4'd1, 4'd2};
end
8'hcb : state = 8'hcb;
8'hcc :
begin
$display ("%t: OPCODE : CALL Z,address", $time);
state = {4'd1, 4'd2};
end
8'hcd :
begin
$display ("%t: OPCODE : CALL address", $time);
state = {4'd1, 4'd2};
end
8'hce :
begin
$display ("%t: OPCODE : ADC A,byte", $time);
state = {4'd1, 4'd1};
end
8'hcf : $display ("%t: OPCODE : RST 8", $time);
8'hd0 : $display ("%t: OPCODE : RET NC", $time);
8'hd1 : $display ("%t: OPCODE : POP DE", $time);
8'hd2 :
begin
$display ("%t: OPCODE : JP NC,address", $time);
state = {4'd1, 4'd2};
end
8'hd3 :
begin
$display ("%t: OPCODE : OUT (byte),A", $time);
state = {4'd1, 4'd1};
end
8'hd4 :
begin
$display ("%t: OPCODE : CALL NC,address", $time);
state = {4'd1, 4'd2};
end
8'hd5 : $display ("%t: OPCODE : PUSH DE", $time);
8'hd6 :
begin
$display ("%t: OPCODE : SUB byte", $time);
state = {4'd1, 4'd1};
end
8'hd7 : $display ("%t: OPCODE : RST 10H", $time);
8'hd8 : $display ("%t: OPCODE : RET C", $time);
8'hd9 : $display ("%t: OPCODE : EXX ", $time);
8'hda :
begin
$display ("%t: OPCODE : JP C,address", $time);
state = {4'd1, 4'd2};
end
8'hdb :
begin
$display ("%t: OPCODE : IN A,(byte)", $time);
state = {4'd1, 4'd1};
end
8'hd3 :
begin
$display ("%t: OPCODE : OUT (byte),A", $time);
state = {4'd1, 4'd1};
end
8'hdc :
begin
$display ("%t: OPCODE : CALL C,address", $time);
state = {4'd1, 4'd2};
end
8'hdd : state = 8'hdd;
8'hde :
begin
$display ("%t: OPCODE : SBC byte", $time);
state = {4'd1, 4'd1};
end
8'hdf : $display ("%t: OPCODE : RST 18H", $time);
8'he0 : $display ("%t: OPCODE : RET PO", $time);
8'he1 : $display ("%t: OPCODE : POP HL", $time);
8'he2 :
begin
$display ("%t: OPCODE : JP PO,address", $time);
state = {4'd1, 4'd2};
end
8'he3 : $display ("%t: OPCODE : EX (SP),HL", $time);
8'he4 :
begin
$display ("%t: OPCODE : CALL PO,address", $time);
state = {4'd1, 4'd2};
end
8'he5 : $display ("%t: OPCODE : PUSH HL", $time);
8'he6 :
begin
$display ("%t: OPCODE : AND byte", $time);
state = {4'd1, 4'd1};
end
8'he7 : $display ("%t: OPCODE : RST 20H", $time);
8'he8 : $display ("%t: OPCODE : RET PE", $time);
8'he9 : $display ("%t: OPCODE : JP (HL)", $time);
8'hea :
begin
$display ("%t: OPCODE : JP PE,address", $time);
state = {4'd1, 4'd2};
end
8'heb : $display ("%t: OPCODE : EX DE,HL", $time);
8'hec :
begin
$display ("%t: OPCODE : CALL PE,address", $time);
state = {4'd1, 4'd2};
end
8'hed : state = 8'hed;
8'hee :
begin
$display ("%t: OPCODE : XOR byte", $time);
state = {4'd1, 4'd1};
end
8'hef : $display ("%t: OPCODE : RST 28H", $time);
8'hf0 : $display ("%t: OPCODE : RET P", $time);
8'hf1 : $display ("%t: OPCODE : POP AF", $time);
8'hf2 :
begin
$display ("%t: OPCODE : JP P,address", $time);
state = {4'd1, 4'd2};
end
8'hf3 : $display ("%t: OPCODE : DI ", $time);
8'hf4 :
begin
$display ("%t: OPCODE : CALL P,address", $time);
state = {4'd1, 4'd2};
end
8'hf5 : $display ("%t: OPCODE : PUSH AF", $time);
8'hf6 :
begin
$display ("%t: OPCODE : OR byte", $time);
state = {4'd1, 4'd1};
end
8'hf7 : $display ("%t: OPCODE : RST 30H", $time);
8'hf8 : $display ("%t: OPCODE : RET M", $time);
8'hf9 : $display ("%t: OPCODE : LD SP,HL", $time);
8'hfa :
begin
$display ("%t: OPCODE : JM M,address", $time);
state = {4'd1, 4'd2};
end
8'hfb : $display ("%t: OPCODE : EI ", $time);
8'hfc :
begin
$display ("%t: OPCODE : CALL M,address", $time);
state = {4'd1, 4'd2};
end
8'hfd : state = 8'hfd;
8'hfe :
begin
$display ("%t: OPCODE : CP byte", $time);
state = {4'd1, 4'd1};
end
8'hff : $display ("%t: OPCODE : RST 38H", $time);
endcase
end
endtask
task decode1;
input [7:0] opcode;
inout [7:0] state;
begin
casex (state)
8'hcb :
begin
case (opcode)
8'h07 :
begin
$display ("%t: OPCODE : RLC A", $time);
state = { 4'd0, 4'd0 };
end
8'h00 :
begin
$display ("%t: OPCODE : RLC B", $time);
state = { 4'd0, 4'd0 };
end
8'h01 :
begin
$display ("%t: OPCODE : RLC C", $time);
state = { 4'd0, 4'd0 };
end
8'h02 :
begin
$display ("%t: OPCODE : RLC D", $time);
state = { 4'd0, 4'd0 };
end
8'h03 :
begin
$display ("%t: OPCODE : RLC E", $time);
state = { 4'd0, 4'd0 };
end
8'h04 :
begin
$display ("%t: OPCODE : RLC H", $time);
state = { 4'd0, 4'd0 };
end
8'h05 :
begin
$display ("%t: OPCODE : RLC L", $time);
state = { 4'd0, 4'd0 };
end
8'h06 :
begin
$display ("%t: OPCODE : RLC (HL)", $time);
state = { 4'd0, 4'd0 };
end
8'h17 :
begin
$display ("%t: OPCODE : RL A", $time);
state = { 4'd0, 4'd0 };
end
8'h10 :
begin
$display ("%t: OPCODE : RL B", $time);
state = { 4'd0, 4'd0 };
end
8'h11 :
begin
$display ("%t: OPCODE : RL C", $time);
state = { 4'd0, 4'd0 };
end
8'h12 :
begin
$display ("%t: OPCODE : RL D", $time);
state = { 4'd0, 4'd0 };
end
8'h13 :
begin
$display ("%t: OPCODE : RL E", $time);
state = { 4'd0, 4'd0 };
end
8'h14 :
begin
$display ("%t: OPCODE : RL H", $time);
state = { 4'd0, 4'd0 };
end
8'h15 :
begin
$display ("%t: OPCODE : RL L", $time);
state = { 4'd0, 4'd0 };
end
8'h16 :
begin
$display ("%t: OPCODE : RL (HL)", $time);
state = { 4'd0, 4'd0 };
end
8'h0f :
begin
$display ("%t: OPCODE : RRC A", $time);
state = { 4'd0, 4'd0 };
end
8'h08 :
begin
$display ("%t: OPCODE : RRC B", $time);
state = { 4'd0, 4'd0 };
end
8'h09 :
begin
$display ("%t: OPCODE : RRC C", $time);
state = { 4'd0, 4'd0 };
end
8'h0a :
begin
$display ("%t: OPCODE : RRC D", $time);
state = { 4'd0, 4'd0 };
end
8'h0b :
begin
$display ("%t: OPCODE : RRC E", $time);
state = { 4'd0, 4'd0 };
end
8'h0c :
begin
$display ("%t: OPCODE : RRC H", $time);
state = { 4'd0, 4'd0 };
end
8'h0d :
begin
$display ("%t: OPCODE : RRC L", $time);
state = { 4'd0, 4'd0 };
end
8'h0e :
begin
$display ("%t: OPCODE : RRC (HL)", $time);
state = { 4'd0, 4'd0 };
end
8'h1f :
begin
$display ("%t: OPCODE : RL A", $time);
state = { 4'd0, 4'd0 };
end
8'h18 :
begin
$display ("%t: OPCODE : RL B", $time);
state = { 4'd0, 4'd0 };
end
8'h19 :
begin
$display ("%t: OPCODE : RL C", $time);
state = { 4'd0, 4'd0 };
end
8'h1a :
begin
$display ("%t: OPCODE : RL D", $time);
state = { 4'd0, 4'd0 };
end
8'h1b :
begin
$display ("%t: OPCODE : RL E", $time);
state = { 4'd0, 4'd0 };
end
8'h1c :
begin
$display ("%t: OPCODE : RL H", $time);
state = { 4'd0, 4'd0 };
end
8'h1d :
begin
$display ("%t: OPCODE : RL L", $time);
state = { 4'd0, 4'd0 };
end
8'h1e :
begin
$display ("%t: OPCODE : RL (HL)", $time);
state = { 4'd0, 4'd0 };
end
8'h47 :
begin
$display ("%t: OPCODE : BIT 0,A", $time);
state = { 4'd0, 4'd0 };
end
8'h40 :
begin
$display ("%t: OPCODE : BIT 0,B", $time);
state = { 4'd0, 4'd0 };
end
8'h41 :
begin
$display ("%t: OPCODE : BIT 0,C", $time);
state = { 4'd0, 4'd0 };
end
8'h42 :
begin
$display ("%t: OPCODE : BIT 0,D", $time);
state = { 4'd0, 4'd0 };
end
8'h43 :
begin
$display ("%t: OPCODE : BIT 0,E", $time);
state = { 4'd0, 4'd0 };
end
8'h44 :
begin
$display ("%t: OPCODE : BIT 0,H", $time);
state = { 4'd0, 4'd0 };
end
8'h45 :
begin
$display ("%t: OPCODE : BIT 0,L", $time);
state = { 4'd0, 4'd0 };
end
8'h46 :
begin
$display ("%t: OPCODE : BIT 0,(HL)", $time);
state = { 4'd0, 4'd0 };
end
8'h4f :
begin
$display ("%t: OPCODE : BIT 1,A", $time);
state = { 4'd0, 4'd0 };
end
8'h48 :
begin
$display ("%t: OPCODE : BIT 1,B", $time);
state = { 4'd0, 4'd0 };
end
8'h49 :
begin
$display ("%t: OPCODE : BIT 1,C", $time);
state = { 4'd0, 4'd0 };
end
8'h4a :
begin
$display ("%t: OPCODE : BIT 1,D", $time);
state = { 4'd0, 4'd0 };
end
8'h4b :
begin
$display ("%t: OPCODE : BIT 1,E", $time);
state = { 4'd0, 4'd0 };
end
8'h4c :
begin
$display ("%t: OPCODE : BIT 1,H", $time);
state = { 4'd0, 4'd0 };
end
8'h4d :
begin
$display ("%t: OPCODE : BIT 1,L", $time);
state = { 4'd0, 4'd0 };
end
8'h4e :
begin
$display ("%t: OPCODE : BIT 1,(HL)", $time);
state = { 4'd0, 4'd0 };
end
8'h57 :
begin
$display ("%t: OPCODE : BIT 2,A", $time);
state = { 4'd0, 4'd0 };
end
8'h50 :
begin
$display ("%t: OPCODE : BIT 2,B", $time);
state = { 4'd0, 4'd0 };
end
8'h51 :
begin
$display ("%t: OPCODE : BIT 2,C", $time);
state = { 4'd0, 4'd0 };
end
8'h52 :
begin
$display ("%t: OPCODE : BIT 2,D", $time);
state = { 4'd0, 4'd0 };
end
8'h53 :
begin
$display ("%t: OPCODE : BIT 2,E", $time);
state = { 4'd0, 4'd0 };
end
8'h54 :
begin
$display ("%t: OPCODE : BIT 2,H", $time);
state = { 4'd0, 4'd0 };
end
8'h55 :
begin
$display ("%t: OPCODE : BIT 2,L", $time);
state = { 4'd0, 4'd0 };
end
8'h56 :
begin
$display ("%t: OPCODE : BIT 2,(HL)", $time);
state = { 4'd0, 4'd0 };
end
8'h5f :
begin
$display ("%t: OPCODE : BIT 3,A", $time);
state = { 4'd0, 4'd0 };
end
8'h58 :
begin
$display ("%t: OPCODE : BIT 3,B", $time);
state = { 4'd0, 4'd0 };
end
8'h59 :
begin
$display ("%t: OPCODE : BIT 3,C", $time);
state = { 4'd0, 4'd0 };
end
8'h5a :
begin
$display ("%t: OPCODE : BIT 3,D", $time);
state = { 4'd0, 4'd0 };
end
8'h5b :
begin
$display ("%t: OPCODE : BIT 3,E", $time);
state = { 4'd0, 4'd0 };
end
8'h5c :
begin
$display ("%t: OPCODE : BIT 3,H", $time);
state = { 4'd0, 4'd0 };
end
8'h5d :
begin
$display ("%t: OPCODE : BIT 3,L", $time);
state = { 4'd0, 4'd0 };
end
8'h5e :
begin
$display ("%t: OPCODE : BIT 3,(HL)", $time);
state = { 4'd0, 4'd0 };
end
8'h67 :
begin
$display ("%t: OPCODE : BIT 4,A", $time);
state = { 4'd0, 4'd0 };
end
8'h60 :
begin
$display ("%t: OPCODE : BIT 4,B", $time);
state = { 4'd0, 4'd0 };
end
8'h61 :
begin
$display ("%t: OPCODE : BIT 4,C", $time);
state = { 4'd0, 4'd0 };
end
8'h62 :
begin
$display ("%t: OPCODE : BIT 4,D", $time);
state = { 4'd0, 4'd0 };
end
8'h63 :
begin
$display ("%t: OPCODE : BIT 4,E", $time);
state = { 4'd0, 4'd0 };
end
8'h64 :
begin
$display ("%t: OPCODE : BIT 4,H", $time);
state = { 4'd0, 4'd0 };
end
8'h65 :
begin
$display ("%t: OPCODE : BIT 4,L", $time);
state = { 4'd0, 4'd0 };
end
8'h66 :
begin
$display ("%t: OPCODE : BIT 4,(HL)", $time);
state = { 4'd0, 4'd0 };
end
8'h6f :
begin
$display ("%t: OPCODE : BIT 5,A", $time);
state = { 4'd0, 4'd0 };
end
8'h68 :
begin
$display ("%t: OPCODE : BIT 5,B", $time);
state = { 4'd0, 4'd0 };
end
8'h69 :
begin
$display ("%t: OPCODE : BIT 5,C", $time);
state = { 4'd0, 4'd0 };
end
8'h6a :
begin
$display ("%t: OPCODE : BIT 5,D", $time);
state = { 4'd0, 4'd0 };
end
8'h6b :
begin
$display ("%t: OPCODE : BIT 5,E", $time);
state = { 4'd0, 4'd0 };
end
8'h6c :
begin
$display ("%t: OPCODE : BIT 5,H", $time);
state = { 4'd0, 4'd0 };
end
8'h6d :
begin
$display ("%t: OPCODE : BIT 5,L", $time);
state = { 4'd0, 4'd0 };
end
8'h6e :
begin
$display ("%t: OPCODE : BIT 5,(HL)", $time);
state = { 4'd0, 4'd0 };
end
8'h77 :
begin
$display ("%t: OPCODE : BIT 6,A", $time);
state = { 4'd0, 4'd0 };
end
8'h70 :
begin
$display ("%t: OPCODE : BIT 6,B", $time);
state = { 4'd0, 4'd0 };
end
8'h71 :
begin
$display ("%t: OPCODE : BIT 6,C", $time);
state = { 4'd0, 4'd0 };
end
8'h72 :
begin
$display ("%t: OPCODE : BIT 6,D", $time);
state = { 4'd0, 4'd0 };
end
8'h73 :
begin
$display ("%t: OPCODE : BIT 6,E", $time);
state = { 4'd0, 4'd0 };
end
8'h74 :
begin
$display ("%t: OPCODE : BIT 6,H", $time);
state = { 4'd0, 4'd0 };
end
8'h75 :
begin
$display ("%t: OPCODE : BIT 6,L", $time);
state = { 4'd0, 4'd0 };
end
8'h76 :
begin
$display ("%t: OPCODE : BIT 6,(HL)", $time);
state = { 4'd0, 4'd0 };
end
8'h7f :
begin
$display ("%t: OPCODE : BIT 7,A", $time);
state = { 4'd0, 4'd0 };
end
8'h78 :
begin
$display ("%t: OPCODE : BIT 7,B", $time);
state = { 4'd0, 4'd0 };
end
8'h79 :
begin
$display ("%t: OPCODE : BIT 7,C", $time);
state = { 4'd0, 4'd0 };
end
8'h7a :
begin
$display ("%t: OPCODE : BIT 7,D", $time);
state = { 4'd0, 4'd0 };
end
8'h7b :
begin
$display ("%t: OPCODE : BIT 7,E", $time);
state = { 4'd0, 4'd0 };
end
8'h7c :
begin
$display ("%t: OPCODE : BIT 7,H", $time);
state = { 4'd0, 4'd0 };
end
8'h7d :
begin
$display ("%t: OPCODE : BIT 7,L", $time);
state = { 4'd0, 4'd0 };
end
8'h7e :
begin
$display ("%t: OPCODE : BIT 7,(HL)", $time);
state = { 4'd0, 4'd0 };
end
8'h87 :
begin
$display ("%t: OPCODE : RES 0,A", $time);
state = { 4'd0, 4'd0 };
end
8'h80 :
begin
$display ("%t: OPCODE : RES 0,B", $time);
state = { 4'd0, 4'd0 };
end
8'h81 :
begin
$display ("%t: OPCODE : RES 0,C", $time);
state = { 4'd0, 4'd0 };
end
8'h82 :
begin
$display ("%t: OPCODE : RES 0,D", $time);
state = { 4'd0, 4'd0 };
end
8'h83 :
begin
$display ("%t: OPCODE : RES 0,E", $time);
state = { 4'd0, 4'd0 };
end
8'h84 :
begin
$display ("%t: OPCODE : RES 0,H", $time);
state = { 4'd0, 4'd0 };
end
8'h85 :
begin
$display ("%t: OPCODE : RES 0,L", $time);
state = { 4'd0, 4'd0 };
end
8'h86 :
begin
$display ("%t: OPCODE : RES 0,(HL)", $time);
state = { 4'd0, 4'd0 };
end
8'h8f :
begin
$display ("%t: OPCODE : RES 1,A", $time);
state = { 4'd0, 4'd0 };
end
8'h88 :
begin
$display ("%t: OPCODE : RES 1,B", $time);
state = { 4'd0, 4'd0 };
end
8'h89 :
begin
$display ("%t: OPCODE : RES 1,C", $time);
state = { 4'd0, 4'd0 };
end
8'h8a :
begin
$display ("%t: OPCODE : RES 1,D", $time);
state = { 4'd0, 4'd0 };
end
8'h8b :
begin
$display ("%t: OPCODE : RES 1,E", $time);
state = { 4'd0, 4'd0 };
end
8'h8c :
begin
$display ("%t: OPCODE : RES 1,H", $time);
state = { 4'd0, 4'd0 };
end
8'h8d :
begin
$display ("%t: OPCODE : RES 1,L", $time);
state = { 4'd0, 4'd0 };
end
8'h8e :
begin
$display ("%t: OPCODE : RES 1,(HL)", $time);
state = { 4'd0, 4'd0 };
end
8'h97 :
begin
$display ("%t: OPCODE : RES 2,A", $time);
state = { 4'd0, 4'd0 };
end
8'h90 :
begin
$display ("%t: OPCODE : RES 2,B", $time);
state = { 4'd0, 4'd0 };
end
8'h91 :
begin
$display ("%t: OPCODE : RES 2,C", $time);
state = { 4'd0, 4'd0 };
end
8'h92 :
begin
$display ("%t: OPCODE : RES 2,D", $time);
state = { 4'd0, 4'd0 };
end
8'h93 :
begin
$display ("%t: OPCODE : RES 2,E", $time);
state = { 4'd0, 4'd0 };
end
8'h94 :
begin
$display ("%t: OPCODE : RES 2,H", $time);
state = { 4'd0, 4'd0 };
end
8'h95 :
begin
$display ("%t: OPCODE : RES 2,L", $time);
state = { 4'd0, 4'd0 };
end
8'h96 :
begin
$display ("%t: OPCODE : RES 2,(HL)", $time);
state = { 4'd0, 4'd0 };
end
8'h9f :
begin
$display ("%t: OPCODE : RES 3,A", $time);
state = { 4'd0, 4'd0 };
end
8'h98 :
begin
$display ("%t: OPCODE : RES 3,B", $time);
state = { 4'd0, 4'd0 };
end
8'h99 :
begin
$display ("%t: OPCODE : RES 3,C", $time);
state = { 4'd0, 4'd0 };
end
8'h9a :
begin
$display ("%t: OPCODE : RES 3,D", $time);
state = { 4'd0, 4'd0 };
end
8'h9b :
begin
$display ("%t: OPCODE : RES 3,E", $time);
state = { 4'd0, 4'd0 };
end
8'h9c :
begin
$display ("%t: OPCODE : RES 3,H", $time);
state = { 4'd0, 4'd0 };
end
8'h9d :
begin
$display ("%t: OPCODE : RES 3,L", $time);
state = { 4'd0, 4'd0 };
end
8'h9e :
begin
$display ("%t: OPCODE : RES 3,(HL)", $time);
state = { 4'd0, 4'd0 };
end
8'ha7 :
begin
$display ("%t: OPCODE : RES 4,A", $time);
state = { 4'd0, 4'd0 };
end
8'ha0 :
begin
$display ("%t: OPCODE : RES 4,B", $time);
state = { 4'd0, 4'd0 };
end
8'ha1 :
begin
$display ("%t: OPCODE : RES 4,C", $time);
state = { 4'd0, 4'd0 };
end
8'ha2 :
begin
$display ("%t: OPCODE : RES 4,D", $time);
state = { 4'd0, 4'd0 };
end
8'ha3 :
begin
$display ("%t: OPCODE : RES 4,E", $time);
state = { 4'd0, 4'd0 };
end
8'ha4 :
begin
$display ("%t: OPCODE : RES 4,H", $time);
state = { 4'd0, 4'd0 };
end
8'ha5 :
begin
$display ("%t: OPCODE : RES 4,L", $time);
state = { 4'd0, 4'd0 };
end
8'ha6 :
begin
$display ("%t: OPCODE : RES 4,(HL)", $time);
state = { 4'd0, 4'd0 };
end
8'haf :
begin
$display ("%t: OPCODE : RES 5,A", $time);
state = { 4'd0, 4'd0 };
end
8'ha8 :
begin
$display ("%t: OPCODE : RES 5,B", $time);
state = { 4'd0, 4'd0 };
end
8'ha9 :
begin
$display ("%t: OPCODE : RES 5,C", $time);
state = { 4'd0, 4'd0 };
end
8'haa :
begin
$display ("%t: OPCODE : RES 5,D", $time);
state = { 4'd0, 4'd0 };
end
8'hab :
begin
$display ("%t: OPCODE : RES 5,E", $time);
state = { 4'd0, 4'd0 };
end
8'hac :
begin
$display ("%t: OPCODE : RES 5,H", $time);
state = { 4'd0, 4'd0 };
end
8'had :
begin
$display ("%t: OPCODE : RES 5,L", $time);
state = { 4'd0, 4'd0 };
end
8'hae :
begin
$display ("%t: OPCODE : RES 5,(HL)", $time);
state = { 4'd0, 4'd0 };
end
8'hb7 :
begin
$display ("%t: OPCODE : RES 6,A", $time);
state = { 4'd0, 4'd0 };
end
8'hb0 :
begin
$display ("%t: OPCODE : RES 6,B", $time);
state = { 4'd0, 4'd0 };
end
8'hb1 :
begin
$display ("%t: OPCODE : RES 6,C", $time);
state = { 4'd0, 4'd0 };
end
8'hb2 :
begin
$display ("%t: OPCODE : RES 6,D", $time);
state = { 4'd0, 4'd0 };
end
8'hb3 :
begin
$display ("%t: OPCODE : RES 6,E", $time);
state = { 4'd0, 4'd0 };
end
8'hb4 :
begin
$display ("%t: OPCODE : RES 6,H", $time);
state = { 4'd0, 4'd0 };
end
8'hb5 :
begin
$display ("%t: OPCODE : RES 6,L", $time);
state = { 4'd0, 4'd0 };
end
8'hb6 :
begin
$display ("%t: OPCODE : RES 6,(HL)", $time);
state = { 4'd0, 4'd0 };
end
8'hbf :
begin
$display ("%t: OPCODE : RES 7,A", $time);
state = { 4'd0, 4'd0 };
end
8'hb8 :
begin
$display ("%t: OPCODE : RES 7,B", $time);
state = { 4'd0, 4'd0 };
end
8'hb9 :
begin
$display ("%t: OPCODE : RES 7,C", $time);
state = { 4'd0, 4'd0 };
end
8'hba :
begin
$display ("%t: OPCODE : RES 7,D", $time);
state = { 4'd0, 4'd0 };
end
8'hbb :
begin
$display ("%t: OPCODE : RES 7,E", $time);
state = { 4'd0, 4'd0 };
end
8'hbc :
begin
$display ("%t: OPCODE : RES 7,H", $time);
state = { 4'd0, 4'd0 };
end
8'hbd :
begin
$display ("%t: OPCODE : RES 7,L", $time);
state = { 4'd0, 4'd0 };
end
8'hbe :
begin
$display ("%t: OPCODE : RES 7,(HL)", $time);
state = { 4'd0, 4'd0 };
end
8'hc7 :
begin
$display ("%t: OPCODE : SET 0,A", $time);
state = { 4'd0, 4'd0 };
end
8'hc0 :
begin
$display ("%t: OPCODE : SET 0,B", $time);
state = { 4'd0, 4'd0 };
end
8'hc1 :
begin
$display ("%t: OPCODE : SET 0,C", $time);
state = { 4'd0, 4'd0 };
end
8'hc2 :
begin
$display ("%t: OPCODE : SET 0,D", $time);
state = { 4'd0, 4'd0 };
end
8'hc3 :
begin
$display ("%t: OPCODE : SET 0,E", $time);
state = { 4'd0, 4'd0 };
end
8'hc4 :
begin
$display ("%t: OPCODE : SET 0,H", $time);
state = { 4'd0, 4'd0 };
end
8'hc5 :
begin
$display ("%t: OPCODE : SET 0,L", $time);
state = { 4'd0, 4'd0 };
end
8'hc6 :
begin
$display ("%t: OPCODE : SET 0,(HL)", $time);
state = { 4'd0, 4'd0 };
end
8'hcf :
begin
$display ("%t: OPCODE : SET 1,A", $time);
state = { 4'd0, 4'd0 };
end
8'hc8 :
begin
$display ("%t: OPCODE : SET 1,B", $time);
state = { 4'd0, 4'd0 };
end
8'hc9 :
begin
$display ("%t: OPCODE : SET 1,C", $time);
state = { 4'd0, 4'd0 };
end
8'hca :
begin
$display ("%t: OPCODE : SET 1,D", $time);
state = { 4'd0, 4'd0 };
end
8'hcb :
begin
$display ("%t: OPCODE : SET 1,E", $time);
state = { 4'd0, 4'd0 };
end
8'hcc :
begin
$display ("%t: OPCODE : SET 1,H", $time);
state = { 4'd0, 4'd0 };
end
8'hcd :
begin
$display ("%t: OPCODE : SET 1,L", $time);
state = { 4'd0, 4'd0 };
end
8'hce :
begin
$display ("%t: OPCODE : SET 1,(HL)", $time);
state = { 4'd0, 4'd0 };
end
8'hd7 :
begin
$display ("%t: OPCODE : SET 2,A", $time);
state = { 4'd0, 4'd0 };
end
8'hd0 :
begin
$display ("%t: OPCODE : SET 2,B", $time);
state = { 4'd0, 4'd0 };
end
8'hd1 :
begin
$display ("%t: OPCODE : SET 2,C", $time);
state = { 4'd0, 4'd0 };
end
8'hd2 :
begin
$display ("%t: OPCODE : SET 2,D", $time);
state = { 4'd0, 4'd0 };
end
8'hd3 :
begin
$display ("%t: OPCODE : SET 2,E", $time);
state = { 4'd0, 4'd0 };
end
8'hd4 :
begin
$display ("%t: OPCODE : SET 2,H", $time);
state = { 4'd0, 4'd0 };
end
8'hd5 :
begin
$display ("%t: OPCODE : SET 2,L", $time);
state = { 4'd0, 4'd0 };
end
8'hd6 :
begin
$display ("%t: OPCODE : SET 2,(HL)", $time);
state = { 4'd0, 4'd0 };
end
8'hdf :
begin
$display ("%t: OPCODE : SET 3,A", $time);
state = { 4'd0, 4'd0 };
end
8'hd8 :
begin
$display ("%t: OPCODE : SET 3,B", $time);
state = { 4'd0, 4'd0 };
end
8'hd9 :
begin
$display ("%t: OPCODE : SET 3,C", $time);
state = { 4'd0, 4'd0 };
end
8'hda :
begin
$display ("%t: OPCODE : SET 3,D", $time);
state = { 4'd0, 4'd0 };
end
8'hdb :
begin
$display ("%t: OPCODE : SET 3,E", $time);
state = { 4'd0, 4'd0 };
end
8'hdc :
begin
$display ("%t: OPCODE : SET 3,H", $time);
state = { 4'd0, 4'd0 };
end
8'hdd :
begin
$display ("%t: OPCODE : SET 3,L", $time);
state = { 4'd0, 4'd0 };
end
8'hde :
begin
$display ("%t: OPCODE : SET 3,(HL)", $time);
state = { 4'd0, 4'd0 };
end
8'he7 :
begin
$display ("%t: OPCODE : SET 4,A", $time);
state = { 4'd0, 4'd0 };
end
8'he0 :
begin
$display ("%t: OPCODE : SET 4,B", $time);
state = { 4'd0, 4'd0 };
end
8'he1 :
begin
$display ("%t: OPCODE : SET 4,C", $time);
state = { 4'd0, 4'd0 };
end
8'he2 :
begin
$display ("%t: OPCODE : SET 4,D", $time);
state = { 4'd0, 4'd0 };
end
8'he3 :
begin
$display ("%t: OPCODE : SET 4,E", $time);
state = { 4'd0, 4'd0 };
end
8'he4 :
begin
$display ("%t: OPCODE : SET 4,H", $time);
state = { 4'd0, 4'd0 };
end
8'he5 :
begin
$display ("%t: OPCODE : SET 4,L", $time);
state = { 4'd0, 4'd0 };
end
8'he6 :
begin
$display ("%t: OPCODE : SET 4,(HL)", $time);
state = { 4'd0, 4'd0 };
end
8'hef :
begin
$display ("%t: OPCODE : SET 5,A", $time);
state = { 4'd0, 4'd0 };
end
8'he8 :
begin
$display ("%t: OPCODE : SET 5,B", $time);
state = { 4'd0, 4'd0 };
end
8'he9 :
begin
$display ("%t: OPCODE : SET 5,C", $time);
state = { 4'd0, 4'd0 };
end
8'hea :
begin
$display ("%t: OPCODE : SET 5,D", $time);
state = { 4'd0, 4'd0 };
end
8'heb :
begin
$display ("%t: OPCODE : SET 5,E", $time);
state = { 4'd0, 4'd0 };
end
8'hec :
begin
$display ("%t: OPCODE : SET 5,H", $time);
state = { 4'd0, 4'd0 };
end
8'hed :
begin
$display ("%t: OPCODE : SET 5,L", $time);
state = { 4'd0, 4'd0 };
end
8'hee :
begin
$display ("%t: OPCODE : SET 5,(HL)", $time);
state = { 4'd0, 4'd0 };
end
8'hf7 :
begin
$display ("%t: OPCODE : SET 6,A", $time);
state = { 4'd0, 4'd0 };
end
8'hf0 :
begin
$display ("%t: OPCODE : SET 6,B", $time);
state = { 4'd0, 4'd0 };
end
8'hf1 :
begin
$display ("%t: OPCODE : SET 6,C", $time);
state = { 4'd0, 4'd0 };
end
8'hf2 :
begin
$display ("%t: OPCODE : SET 6,D", $time);
state = { 4'd0, 4'd0 };
end
8'hf3 :
begin
$display ("%t: OPCODE : SET 6,E", $time);
state = { 4'd0, 4'd0 };
end
8'hf4 :
begin
$display ("%t: OPCODE : SET 6,H", $time);
state = { 4'd0, 4'd0 };
end
8'hf5 :
begin
$display ("%t: OPCODE : SET 6,L", $time);
state = { 4'd0, 4'd0 };
end
8'hf6 :
begin
$display ("%t: OPCODE : SET 6,(HL)", $time);
state = { 4'd0, 4'd0 };
end
8'hff :
begin
$display ("%t: OPCODE : SET 7,A", $time);
state = { 4'd0, 4'd0 };
end
8'hf8 :
begin
$display ("%t: OPCODE : SET 7,B", $time);
state = { 4'd0, 4'd0 };
end
8'hf9 :
begin
$display ("%t: OPCODE : SET 7,C", $time);
state = { 4'd0, 4'd0 };
end
8'hfa :
begin
$display ("%t: OPCODE : SET 7,D", $time);
state = { 4'd0, 4'd0 };
end
8'hfb :
begin
$display ("%t: OPCODE : SET 7,E", $time);
state = { 4'd0, 4'd0 };
end
8'hfc :
begin
$display ("%t: OPCODE : SET 7,H", $time);
state = { 4'd0, 4'd0 };
end
8'hfd :
begin
$display ("%t: OPCODE : SET 7,L", $time);
state = { 4'd0, 4'd0 };
end
8'hfe :
begin
$display ("%t: OPCODE : SET 7,(HL)", $time);
state = { 4'd0, 4'd0 };
end
8'h27 :
begin
$display ("%t: OPCODE : SLA A", $time);
state = { 4'd0, 4'd0 };
end
8'h20 :
begin
$display ("%t: OPCODE : SLA B", $time);
state = { 4'd0, 4'd0 };
end
8'h21 :
begin
$display ("%t: OPCODE : SLA C", $time);
state = { 4'd0, 4'd0 };
end
8'h22 :
begin
$display ("%t: OPCODE : SLA D", $time);
state = { 4'd0, 4'd0 };
end
8'h23 :
begin
$display ("%t: OPCODE : SLA E", $time);
state = { 4'd0, 4'd0 };
end
8'h24 :
begin
$display ("%t: OPCODE : SLA H", $time);
state = { 4'd0, 4'd0 };
end
8'h25 :
begin
$display ("%t: OPCODE : SLA L", $time);
state = { 4'd0, 4'd0 };
end
8'h26 :
begin
$display ("%t: OPCODE : SLA (HL)", $time);
state = { 4'd0, 4'd0 };
end
8'h2f :
begin
$display ("%t: OPCODE : SRA A", $time);
state = { 4'd0, 4'd0 };
end
8'h28 :
begin
$display ("%t: OPCODE : SRA B", $time);
state = { 4'd0, 4'd0 };
end
8'h29 :
begin
$display ("%t: OPCODE : SRA C", $time);
state = { 4'd0, 4'd0 };
end
8'h2a :
begin
$display ("%t: OPCODE : SRA D", $time);
state = { 4'd0, 4'd0 };
end
8'h2b :
begin
$display ("%t: OPCODE : SRA E", $time);
state = { 4'd0, 4'd0 };
end
8'h2c :
begin
$display ("%t: OPCODE : SRA H", $time);
state = { 4'd0, 4'd0 };
end
8'h2d :
begin
$display ("%t: OPCODE : SRA L", $time);
state = { 4'd0, 4'd0 };
end
8'h2e :
begin
$display ("%t: OPCODE : SRA (HL)", $time);
state = { 4'd0, 4'd0 };
end
8'h3f :
begin
$display ("%t: OPCODE : SRL A", $time);
state = { 4'd0, 4'd0 };
end
8'h38 :
begin
$display ("%t: OPCODE : SRL B", $time);
state = { 4'd0, 4'd0 };
end
8'h39 :
begin
$display ("%t: OPCODE : SRL C", $time);
state = { 4'd0, 4'd0 };
end
8'h3a :
begin
$display ("%t: OPCODE : SRL D", $time);
state = { 4'd0, 4'd0 };
end
8'h3b :
begin
$display ("%t: OPCODE : SRL E", $time);
state = { 4'd0, 4'd0 };
end
8'h3c :
begin
$display ("%t: OPCODE : SRL H", $time);
state = { 4'd0, 4'd0 };
end
8'h3d :
begin
$display ("%t: OPCODE : SRL L", $time);
state = { 4'd0, 4'd0 };
end
8'h3e :
begin
$display ("%t: OPCODE : SRL (HL)", $time);
state = { 4'd0, 4'd0 };
end
endcase
end
8'hdd :
begin
case (opcode)
8'h7e :
begin
$display ("%t: OPCODE : LD A,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h46 :
begin
$display ("%t: OPCODE : LD B,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h4e :
begin
$display ("%t: OPCODE : LD C,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h56 :
begin
$display ("%t: OPCODE : LD D,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h5e :
begin
$display ("%t: OPCODE : LD E,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h66 :
begin
$display ("%t: OPCODE : LD H,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h6e :
begin
$display ("%t: OPCODE : LD L,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h77 :
begin
$display ("%t: OPCODE : LD (IX+index),A", $time);
state = { 4'd1, 4'd1 };
end
8'h70 :
begin
$display ("%t: OPCODE : LD (IX+index),B", $time);
state = { 4'd1, 4'd1 };
end
8'h71 :
begin
$display ("%t: OPCODE : LD (IX+index),C", $time);
state = { 4'd1, 4'd1 };
end
8'h72 :
begin
$display ("%t: OPCODE : LD (IX+index),D", $time);
state = { 4'd1, 4'd1 };
end
8'h73 :
begin
$display ("%t: OPCODE : LD (IX+index),E", $time);
state = { 4'd1, 4'd1 };
end
8'h74 :
begin
$display ("%t: OPCODE : LD (IX+index),H", $time);
state = { 4'd1, 4'd1 };
end
8'h75 :
begin
$display ("%t: OPCODE : LD (IX+index),L", $time);
state = { 4'd1, 4'd1 };
end
8'h76 :
begin
$display ("%t: OPCODE : LD (IX+index),byte", $time);
state = { 4'd1, 4'd1 };
end
8'h36 :
begin
$display ("%t: OPCODE : LD (IX+index),byte", $time);
state = { 4'd1, 4'd1 };
end
8'h21 :
begin
$display ("%t: OPCODE : LD IX,word", $time);
state = { 4'd1, 4'd2 };
end
8'h2a :
begin
$display ("%t: OPCODE : LD IX,(word)", $time);
state = { 4'd1, 4'd2 };
end
8'h22 :
begin
$display ("%t: OPCODE : LD (word),IX", $time);
state = { 4'd1, 4'd2 };
end
8'h22 :
begin
$display ("%t: OPCODE : LD (word),IY", $time);
state = { 4'd1, 4'd2 };
end
8'hf9 :
begin
$display ("%t: OPCODE : LD SP,IX", $time);
state = { 4'd0, 4'd0 };
end
8'he3 :
begin
$display ("%t: OPCODE : EX (SP),IX", $time);
state = { 4'd0, 4'd0 };
end
8'h86 :
begin
$display ("%t: OPCODE : ADD A,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h8e :
begin
$display ("%t: OPCODE : ADC A,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h96 :
begin
$display ("%t: OPCODE : SUB (IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h9e :
begin
$display ("%t: OPCODE : SBC (IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h09 :
begin
$display ("%t: OPCODE : ADD IX,BC", $time);
state = { 4'd0, 4'd0 };
end
8'h19 :
begin
$display ("%t: OPCODE : ADD IX,DE", $time);
state = { 4'd0, 4'd0 };
end
8'h29 :
begin
$display ("%t: OPCODE : ADD IX,IX", $time);
state = { 4'd0, 4'd0 };
end
8'h39 :
begin
$display ("%t: OPCODE : ADD IX,SP", $time);
state = { 4'd0, 4'd0 };
end
8'h34 :
begin
$display ("%t: OPCODE : INC (IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h35 :
begin
$display ("%t: OPCODE : DEC (IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h23 :
begin
$display ("%t: OPCODE : INC IX", $time);
state = { 4'd0, 4'd0 };
end
8'h2b :
begin
$display ("%t: OPCODE : DEC IX", $time);
state = { 4'd0, 4'd0 };
end
8'hcb :
begin
$display ("%t: OPCODE : RLC (IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : RL (IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : RRC (IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : RL (IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'ha6 :
begin
$display ("%t: OPCODE : AND (IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hae :
begin
$display ("%t: OPCODE : XOR (IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hb6 :
begin
$display ("%t: OPCODE : OR (IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hbe :
begin
$display ("%t: OPCODE : CP (IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'he9 :
begin
$display ("%t: OPCODE : JP (IX)", $time);
state = { 4'd0, 4'd0 };
end
8'he5 :
begin
$display ("%t: OPCODE : PUSH IX", $time);
state = { 4'd0, 4'd0 };
end
8'he1 :
begin
$display ("%t: OPCODE : POP IX", $time);
state = { 4'd0, 4'd0 };
end
8'hcb :
begin
$display ("%t: OPCODE : BIT 0,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : BIT 1,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : BIT 2,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : BIT 3,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : BIT 4,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : BIT 5,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : BIT 6,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : BIT 7,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : RES 0,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : RES 1,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : RES 2,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : RES 3,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : RES 4,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : RES 5,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : RES 6,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : RES 7,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : SET 0,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : SET 1,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : SET 2,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : SET 3,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : SET 4,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : SET 5,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : SET 6,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : SET 7,(IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : SLA (IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : SRA (IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : SRL (IX+index)", $time);
state = { 4'd1, 4'd1 };
end
endcase
end
8'hed :
begin
case (opcode)
8'h57 :
begin
$display ("%t: OPCODE : LD A,I", $time);
state = { 4'd0, 4'd0 };
end
8'h4b :
begin
$display ("%t: OPCODE : LD BC,(word)", $time);
state = { 4'd1, 4'd2 };
end
8'h5b :
begin
$display ("%t: OPCODE : LD DE,(word)", $time);
state = { 4'd1, 4'd2 };
end
8'h6b :
begin
$display ("%t: OPCODE : LD HL,(word)", $time);
state = { 4'd1, 4'd2 };
end
8'h7b :
begin
$display ("%t: OPCODE : LD SP,(word)", $time);
state = { 4'd1, 4'd2 };
end
8'h43 :
begin
$display ("%t: OPCODE : LD (word),BC", $time);
state = { 4'd1, 4'd2 };
end
8'h53 :
begin
$display ("%t: OPCODE : LD (word),DE", $time);
state = { 4'd1, 4'd2 };
end
8'h6b :
begin
$display ("%t: OPCODE : LD (word),HL", $time);
state = { 4'd1, 4'd2 };
end
8'h73 :
begin
$display ("%t: OPCODE : LD (word),SP", $time);
state = { 4'd1, 4'd2 };
end
8'h4a :
begin
$display ("%t: OPCODE : ADC HL,BC", $time);
state = { 4'd0, 4'd0 };
end
8'h5a :
begin
$display ("%t: OPCODE : ADC HL,DE", $time);
state = { 4'd0, 4'd0 };
end
8'h6a :
begin
$display ("%t: OPCODE : ADC HL,HL", $time);
state = { 4'd0, 4'd0 };
end
8'h7a :
begin
$display ("%t: OPCODE : ADC HL,SP", $time);
state = { 4'd0, 4'd0 };
end
8'h42 :
begin
$display ("%t: OPCODE : SBC HL,BC", $time);
state = { 4'd0, 4'd0 };
end
8'h52 :
begin
$display ("%t: OPCODE : SBC HL,DE", $time);
state = { 4'd0, 4'd0 };
end
8'h62 :
begin
$display ("%t: OPCODE : SBC HL,HL", $time);
state = { 4'd0, 4'd0 };
end
8'h72 :
begin
$display ("%t: OPCODE : SBC HL,SP", $time);
state = { 4'd0, 4'd0 };
end
8'h46 :
begin
$display ("%t: OPCODE : IM 0", $time);
state = { 4'd0, 4'd0 };
end
8'h56 :
begin
$display ("%t: OPCODE : IM 1", $time);
state = { 4'd0, 4'd0 };
end
8'h5e :
begin
$display ("%t: OPCODE : IM 2", $time);
state = { 4'd0, 4'd0 };
end
8'h47 :
begin
$display ("%t: OPCODE : LD I,A", $time);
state = { 4'd0, 4'd0 };
end
8'h44 :
begin
$display ("%t: OPCODE : NEG ", $time);
state = { 4'd0, 4'd0 };
end
8'h6f :
begin
$display ("%t: OPCODE : RLD ", $time);
state = { 4'd0, 4'd0 };
end
8'h67 :
begin
$display ("%t: OPCODE : RRD ", $time);
state = { 4'd0, 4'd0 };
end
8'ha1 :
begin
$display ("%t: OPCODE : CPI ", $time);
state = { 4'd0, 4'd0 };
end
8'hb1 :
begin
$display ("%t: OPCODE : CPIR ", $time);
state = { 4'd0, 4'd0 };
end
8'ha9 :
begin
$display ("%t: OPCODE : CPD ", $time);
state = { 4'd0, 4'd0 };
end
8'hb9 :
begin
$display ("%t: OPCODE : CPDR ", $time);
state = { 4'd0, 4'd0 };
end
8'h4d :
begin
$display ("%t: OPCODE : RETI ", $time);
state = { 4'd0, 4'd0 };
end
8'h45 :
begin
$display ("%t: OPCODE : RETN ", $time);
state = { 4'd0, 4'd0 };
end
8'h78 :
begin
$display ("%t: OPCODE : IN A,(C)", $time);
state = { 4'd0, 4'd0 };
end
8'h40 :
begin
$display ("%t: OPCODE : IN B,(C)", $time);
state = { 4'd0, 4'd0 };
end
8'h48 :
begin
$display ("%t: OPCODE : IN C,(C)", $time);
state = { 4'd0, 4'd0 };
end
8'h50 :
begin
$display ("%t: OPCODE : IN D,(C)", $time);
state = { 4'd0, 4'd0 };
end
8'h58 :
begin
$display ("%t: OPCODE : IN E,(C)", $time);
state = { 4'd0, 4'd0 };
end
8'h60 :
begin
$display ("%t: OPCODE : IN H,(C)", $time);
state = { 4'd0, 4'd0 };
end
8'h68 :
begin
$display ("%t: OPCODE : IN L,(C)", $time);
state = { 4'd0, 4'd0 };
end
8'ha2 :
begin
$display ("%t: OPCODE : INI ", $time);
state = { 4'd0, 4'd0 };
end
8'hb2 :
begin
$display ("%t: OPCODE : INIR ", $time);
state = { 4'd0, 4'd0 };
end
8'haa :
begin
$display ("%t: OPCODE : IND ", $time);
state = { 4'd0, 4'd0 };
end
8'hba :
begin
$display ("%t: OPCODE : INDR ", $time);
state = { 4'd0, 4'd0 };
end
8'h79 :
begin
$display ("%t: OPCODE : OUT (C),A", $time);
state = { 4'd0, 4'd0 };
end
8'h41 :
begin
$display ("%t: OPCODE : OUT (C),B", $time);
state = { 4'd0, 4'd0 };
end
8'h49 :
begin
$display ("%t: OPCODE : OUT (C),C", $time);
state = { 4'd0, 4'd0 };
end
8'h51 :
begin
$display ("%t: OPCODE : OUT (C),D", $time);
state = { 4'd0, 4'd0 };
end
8'h59 :
begin
$display ("%t: OPCODE : OUT (C),E", $time);
state = { 4'd0, 4'd0 };
end
8'h61 :
begin
$display ("%t: OPCODE : OUT (C),H", $time);
state = { 4'd0, 4'd0 };
end
8'h69 :
begin
$display ("%t: OPCODE : OUT (C),L", $time);
state = { 4'd0, 4'd0 };
end
8'ha3 :
begin
$display ("%t: OPCODE : OUTI ", $time);
state = { 4'd0, 4'd0 };
end
8'hb3 :
begin
$display ("%t: OPCODE : OTIR ", $time);
state = { 4'd0, 4'd0 };
end
8'hab :
begin
$display ("%t: OPCODE : OUTD ", $time);
state = { 4'd0, 4'd0 };
end
8'hbb :
begin
$display ("%t: OPCODE : OTDR ", $time);
state = { 4'd0, 4'd0 };
end
8'ha0 :
begin
$display ("%t: OPCODE : LDI ", $time);
state = { 4'd0, 4'd0 };
end
8'hb0 :
begin
$display ("%t: OPCODE : LDIR ", $time);
state = { 4'd0, 4'd0 };
end
8'ha8 :
begin
$display ("%t: OPCODE : LDD ", $time);
state = { 4'd0, 4'd0 };
end
8'hb8 :
begin
$display ("%t: OPCODE : LDDR ", $time);
state = { 4'd0, 4'd0 };
end
endcase
end
8'hfd :
begin
case (opcode)
8'h7e :
begin
$display ("%t: OPCODE : LD A,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h46 :
begin
$display ("%t: OPCODE : LD B,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h4e :
begin
$display ("%t: OPCODE : LD C,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h56 :
begin
$display ("%t: OPCODE : LD D,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h5e :
begin
$display ("%t: OPCODE : LD E,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h66 :
begin
$display ("%t: OPCODE : LD H,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h6e :
begin
$display ("%t: OPCODE : LD L,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h77 :
begin
$display ("%t: OPCODE : LD (IY+index),A", $time);
state = { 4'd1, 4'd1 };
end
8'h70 :
begin
$display ("%t: OPCODE : LD (IY+index),B", $time);
state = { 4'd1, 4'd1 };
end
8'h71 :
begin
$display ("%t: OPCODE : LD (IY+index),C", $time);
state = { 4'd1, 4'd1 };
end
8'h72 :
begin
$display ("%t: OPCODE : LD (IY+index),D", $time);
state = { 4'd1, 4'd1 };
end
8'h73 :
begin
$display ("%t: OPCODE : LD (IY+index),E", $time);
state = { 4'd1, 4'd1 };
end
8'h74 :
begin
$display ("%t: OPCODE : LD (IY+index),H", $time);
state = { 4'd1, 4'd1 };
end
8'h75 :
begin
$display ("%t: OPCODE : LD (IY+index),L", $time);
state = { 4'd1, 4'd1 };
end
8'h76 :
begin
$display ("%t: OPCODE : LD (IY+index),byte", $time);
state = { 4'd1, 4'd1 };
end
8'h36 :
begin
$display ("%t: OPCODE : LD (IY+index),byte", $time);
state = { 4'd1, 4'd1 };
end
8'h21 :
begin
$display ("%t: OPCODE : LD IY,word", $time);
state = { 4'd1, 4'd2 };
end
8'h2a :
begin
$display ("%t: OPCODE : LD IY,(word)", $time);
state = { 4'd1, 4'd2 };
end
8'hf9 :
begin
$display ("%t: OPCODE : LD SP,IY", $time);
state = { 4'd0, 4'd0 };
end
8'he3 :
begin
$display ("%t: OPCODE : EX (SP),IY", $time);
state = { 4'd0, 4'd0 };
end
8'h86 :
begin
$display ("%t: OPCODE : ADD A,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h8e :
begin
$display ("%t: OPCODE : ADC A,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h96 :
begin
$display ("%t: OPCODE : SUB (IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h9e :
begin
$display ("%t: OPCODE : SBC (IX+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h09 :
begin
$display ("%t: OPCODE : ADD IY,BC", $time);
state = { 4'd0, 4'd0 };
end
8'h19 :
begin
$display ("%t: OPCODE : ADD IY,DE", $time);
state = { 4'd0, 4'd0 };
end
8'h29 :
begin
$display ("%t: OPCODE : ADD IY,IY", $time);
state = { 4'd0, 4'd0 };
end
8'h39 :
begin
$display ("%t: OPCODE : ADD IY,SP", $time);
state = { 4'd0, 4'd0 };
end
8'h34 :
begin
$display ("%t: OPCODE : INC (IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h35 :
begin
$display ("%t: OPCODE : DEC (IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'h23 :
begin
$display ("%t: OPCODE : INC IY", $time);
state = { 4'd0, 4'd0 };
end
8'h2b :
begin
$display ("%t: OPCODE : DEC IY", $time);
state = { 4'd0, 4'd0 };
end
8'hcb :
begin
$display ("%t: OPCODE : RLC (IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : RL (IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : RRC (IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : RL (IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'ha6 :
begin
$display ("%t: OPCODE : AND (IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hae :
begin
$display ("%t: OPCODE : XOR (IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hb6 :
begin
$display ("%t: OPCODE : OR (IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hbe :
begin
$display ("%t: OPCODE : CP (IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'he9 :
begin
$display ("%t: OPCODE : JP (IY)", $time);
state = { 4'd0, 4'd0 };
end
8'he5 :
begin
$display ("%t: OPCODE : PUSH IY", $time);
state = { 4'd0, 4'd0 };
end
8'he1 :
begin
$display ("%t: OPCODE : POP IY", $time);
state = { 4'd0, 4'd0 };
end
8'hcb :
begin
$display ("%t: OPCODE : BIT 0,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : BIT 1,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : BIT 2,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : BIT 3,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : BIT 4,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : BIT 5,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : BIT 6,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : BIT 7,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : RES 0,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : RES 1,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : RES 2,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : RES 3,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : RES 4,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : RES 5,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : RES 6,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : RES 7,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : SET 0,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : SET 1,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : SET 2,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : SET 3,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : SET 4,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : SET 5,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : SET 6,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : SET 7,(IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : SLA (IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : SRA (IY+index)", $time);
state = { 4'd1, 4'd1 };
end
8'hcb :
begin
$display ("%t: OPCODE : SRL (IY+index)", $time);
state = { 4'd1, 4'd1 };
end
endcase
end // case: 8'hfd
default :
begin
$display ("%t: OPCODE : Unknown opcode %x", $time, opcode);
end
endcase
end
endtask
task decode;
input [7:0] byte;
inout [7:0] state;
begin
if (state == 0)
decode0 (byte, state);
else if (state[7:4] == 1)
begin
state[3:0] = state[3:0] - 1;
if (state[3:0] == 0)
state[7:0] = 0;
end
else
begin
decode1 (byte, state);
end
end
endtask // decode
endmodule // op_decode
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll_clock.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module pll_clock (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_clock.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_clock.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_clock.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_clock.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_clock.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_clock.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_clock_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_clock_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/**
* This is written by Zhiyang Ong ([email protected]; 6004 9194 12)
* and Andrew Mattheisen ([email protected]; 2134 5147 11)
* for EE577b Troy WideWord Processor Project
*/
// GOLD VERSION
/*
*ALU Functions Included (in order coded below):
* SLL
* SRL
* ADD
* AND
* NOT
* OR
* XOR
* SUB
* PRM
* SLLI
* SRLI
* SRAI
* SRA
* mules
* mulos
* muleu
* mulou
*
*Other Functions:
* LD (NOP)
* WMV (ADD)
* WST (NOP)
*/
/**
* Reference:
* Nestoras Tzartzanis, EE 577B Verilog Example, Jan 25, 1996
* http://www-scf.usc.edu/~ee577/tutorial/verilog/alu.v
*/
/**
* Note that all instructions are 32-bits, and that Big-Endian
* byte and bit labeling is used. Hence, a[0] is the most
* significant bit, and a[31] is the least significant bit.
*
* Use of casex and casez may affect functionality, and produce
* larger and slower designs that omit the full_case directive
*
* Reference:
* Don Mills and Clifford E. Cummings, "RTL Coding Styles That
* Yield Simulation and Synthesis Mismatches", SNUG 1999
*
* ALU is a combinational logic block without clock signals
*/
// Behavioral model for the ALU
module alu (reg_A,reg_B,ctrl_ww,alu_op,result);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
// Input signals
input [0:127] reg_A;
input [0:127] reg_B;
// Control signal bits - ww
input [0:1] ctrl_ww;
input [0:4] alu_op;
// Defining constants: parameter [name_of_constant] = value;
parameter max_128_bits = 128'hffffffffffffffffffffffffffffffff;
// Declare "reg" signals:
reg [0:127] result;
reg [0:127] p_pdt;
// Temporary reg variables for WW=8, for 8-bit multiplication
reg [0:15] p_pdt8a;
reg [0:15] p_pdt8a2;
reg [0:15] p_pdt8b;
reg [0:15] p_pdt8b2;
reg [0:15] p_pdt8c;
reg [0:15] p_pdt8c2;
reg [0:15] p_pdt8d;
reg [0:15] p_pdt8d2;
reg [0:15] p_pdt8e;
reg [0:15] p_pdt8e2;
reg [0:15] p_pdt8f;
reg [0:15] p_pdt8f2;
reg [0:15] p_pdt8g;
reg [0:15] p_pdt8g2;
reg [0:15] p_pdt8h;
reg [0:15] p_pdt8h2;
// Temporary reg variables for WW=16, for 16-bit multiplication
reg [0:31] p_pdt16a;
reg [0:31] p_pdt16a2;
reg [0:31] p_pdt16a3;
reg [0:31] p_pdt16b;
reg [0:31] p_pdt16b2;
reg [0:31] p_pdt16c;
reg [0:31] p_pdt16c2;
reg [0:31] p_pdt16d;
reg [0:31] p_pdt16d2;
integer sgn;
integer i;
integer j;
always @(reg_A or reg_B or ctrl_ww or alu_op)
begin
p_pdt=128'd0;
p_pdt8a=16'd0;
p_pdt8a2=16'd0;
p_pdt8b=16'd0;
p_pdt8b2=16'd0;
p_pdt8c=16'd0;
p_pdt8c2=16'd0;
p_pdt8d=16'd0;
p_pdt8d2=16'd0;
p_pdt8e=16'd0;
p_pdt8e2=16'd0;
p_pdt8f=16'd0;
p_pdt8f2=16'd0;
p_pdt8g=16'd0;
p_pdt8g2=16'd0;
p_pdt8h=16'd0;
p_pdt8h2=16'd0;
p_pdt16a=32'd0;
p_pdt16a2=32'd0;
p_pdt16b=32'd0;
p_pdt16b2=32'd0;
p_pdt16c=32'd0;
p_pdt16c2=32'd0;
p_pdt16d=32'd0;
p_pdt16d2=32'd0;
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
/**
* In computer science, a logical shift is a shift operator
* that shifts all the bits of its operand. Unlike an
* arithmetic shift, a logical shift does not preserve
* a number's sign bit or distinguish a number's exponent
* from its mantissa; every bit in the operand is simply
* moved a given number of bit positions, and the vacant
* bit-positions are filled in, generally with zeros
* (compare with a circular shift).
*
* SRL,SLL,Srli,sra,srai...
*/
// ================================================
// ======================================================
// SLL instruction << mv to LSB << bit 127
`aluwsll:
begin
case(ctrl_ww)
`w8: // aluwsll AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]<<reg_B[5:7];
result[8:15]<=reg_A[8:15]<<reg_B[13:15];
result[16:23]<=reg_A[16:23]<<reg_B[21:23];
result[24:31]<=reg_A[24:31]<<reg_B[29:31];
result[32:39]<=reg_A[32:39]<<reg_B[37:39];
result[40:47]<=reg_A[40:47]<<reg_B[45:47];
result[48:55]<=reg_A[48:55]<<reg_B[53:55];
result[56:63]<=reg_A[56:63]<<reg_B[61:63];
result[64:71]<=reg_A[64:71]<<reg_B[69:71];
result[72:79]<=reg_A[72:79]<<reg_B[77:79];
result[80:87]<=reg_A[80:87]<<reg_B[85:87];
result[88:95]<=reg_A[88:95]<<reg_B[93:95];
result[96:103]<=reg_A[96:103]<<reg_B[101:103];
result[104:111]<=reg_A[104:111]<<reg_B[109:111];
result[112:119]<=reg_A[112:119]<<reg_B[117:119];
result[120:127]<=reg_A[120:127]<<reg_B[125:127];
end
`w16: // aluwsll AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]<<reg_B[12:15];
result[16:31]<=reg_A[16:31]<<reg_B[28:31];
result[32:47]<=reg_A[32:47]<<reg_B[44:47];
result[48:63]<=reg_A[48:63]<<reg_B[60:63];
result[64:79]<=reg_A[64:79]<<reg_B[76:79];
result[80:95]<=reg_A[80:95]<<reg_B[92:95];
result[96:111]<=reg_A[96:111]<<reg_B[108:111];
result[112:127]<=reg_A[112:127]<<reg_B[124:127];
end
`w32: // aluwsll AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]<<reg_B[27:31];
result[32:63]<=reg_A[32:63]<<reg_B[59:63];
result[64:95]<=reg_A[64:95]<<reg_B[91:95];
result[96:127]<=reg_A[96:127]<<reg_B[123:127];
end
default: // aluwsll AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
/*
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*/
// ======================================================
// SRL instruction >> mv to MSB >> bit 0
`aluwsrl:
begin
case(ctrl_ww)
`w8: // aluwsrl AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default: // aluwsrl AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
//================================================================================
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// ================================================
// ADD instruction
`aluwadd:
begin
case(ctrl_ww)
`w8: // aluwadd AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[32:63]<=reg_A[32:63]+reg_B[32:63];
result[64:95]<=reg_A[64:95]+reg_B[64:95];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default: // aluwadd AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// AND instruction
`aluwand:
begin
case(ctrl_ww)
`w8: // aluwand AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[8:15]<=reg_A[8:15]®_B[8:15];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[56:63]<=reg_A[56:63]®_B[56:63];
result[64:71]<=reg_A[64:71]®_B[64:71];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[112:119]<=reg_A[112:119]®_B[112:119];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[16:31]<=reg_A[16:31]®_B[16:31];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[48:63]<=reg_A[48:63]®_B[48:63];
result[64:79]<=reg_A[64:79]®_B[64:79];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[96:111]<=reg_A[96:111]®_B[96:111];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[32:63]<=reg_A[32:63]®_B[32:63];
result[64:95]<=reg_A[64:95]®_B[64:95];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default: // aluwand AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
// ==============================================
// ================================================
// NOT instruction
`aluwnot:
begin
case(ctrl_ww)
`w8: // aluwnot AND `aa AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[8:15]<=~reg_A[8:15];
result[16:23]<=~reg_A[16:23];
result[24:31]<=~reg_A[24:31];
result[32:39]<=~reg_A[32:39];
result[40:47]<=~reg_A[40:47];
result[48:55]<=~reg_A[48:55];
result[56:63]<=~reg_A[56:63];
result[64:71]<=~reg_A[64:71];
result[72:79]<=~reg_A[72:79];
result[80:87]<=~reg_A[80:87];
result[88:95]<=~reg_A[88:95];
result[96:103]<=~reg_A[96:103];
result[104:111]<=~reg_A[104:111];
result[112:119]<=~reg_A[112:119];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `aa AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[16:31]<=~reg_A[16:31];
result[32:47]<=~reg_A[32:47];
result[48:63]<=~reg_A[48:63];
result[64:79]<=~reg_A[64:79];
result[80:95]<=~reg_A[80:95];
result[96:111]<=~reg_A[96:111];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `aa AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[32:63]<=~reg_A[32:63];
result[64:95]<=~reg_A[64:95];
result[96:127]<=~reg_A[96:127];
end
default: // aluwnot AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// OR instruction
`aluwor:
begin
case(ctrl_ww)
`w8: // aluwor AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[32:63]<=reg_A[32:63]|reg_B[32:63];
result[64:95]<=reg_A[64:95]|reg_B[64:95];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default: // aluwor AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
// ========================================================
// XOR instruction
`aluwxor:
begin
case(ctrl_ww)
`w8: // aluwxor AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[32:63]<=reg_A[32:63]^reg_B[32:63];
result[64:95]<=reg_A[64:95]^reg_B[64:95];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default: // aluwxor AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
// ======================================================
// SUB instruction
`aluwsub:
begin
case(ctrl_ww)
`w8: // aluwsub AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[32:63]<=reg_A[32:63]-reg_B[32:63];
result[64:95]<=reg_A[64:95]-reg_B[64:95];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default: // aluwsub AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
//================================================================================
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//================================================================================
// ==============================================================
// PRM instruction
`aluwprm:
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[112:119];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
/*
* ========================================================
*=========================================================
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*=======================================================
*=======================================================
*=========================================================
*========================================================
*=========================================================
*========================================================
*========================================================
*=======================================================
*========================================================
*=======================================================
*=======================================================
*=========================================================
*========================================================
*=========================================================
*========================================================
*========================================================
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*=======================================================
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*=======================================================
*=======================================================
*/
// ==============================================================
// SLLI instruction
`aluwslli:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:15]<={reg_A[9:15],{1'b0}};
result[16:23]<={reg_A[17:23],{1'b0}};
result[24:31]<={reg_A[25:31],{1'b0}};
result[32:39]<={reg_A[33:39],{1'b0}};
result[40:47]<={reg_A[41:47],{1'b0}};
result[48:55]<={reg_A[49:55],{1'b0}};
result[56:63]<={reg_A[57:63],{1'b0}};
result[64:71]<={reg_A[65:71],{1'b0}};
result[72:79]<={reg_A[73:79],{1'b0}};
result[80:87]<={reg_A[81:87],{1'b0}};
result[88:95]<={reg_A[89:95],{1'b0}};
result[96:103]<={reg_A[97:103],{1'b0}};
result[104:111]<={reg_A[105:111],{1'b0}};
result[112:119]<={reg_A[113:119],{1'b0}};
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:15]<={reg_A[10:15],{2{1'b0}}};
result[16:23]<={reg_A[18:23],{2{1'b0}}};
result[24:31]<={reg_A[26:31],{2{1'b0}}};
result[32:39]<={reg_A[34:39],{2{1'b0}}};
result[40:47]<={reg_A[42:47],{2{1'b0}}};
result[48:55]<={reg_A[50:55],{2{1'b0}}};
result[56:63]<={reg_A[58:63],{2{1'b0}}};
result[64:71]<={reg_A[66:71],{2{1'b0}}};
result[72:79]<={reg_A[74:79],{2{1'b0}}};
result[80:87]<={reg_A[82:87],{2{1'b0}}};
result[88:95]<={reg_A[90:95],{2{1'b0}}};
result[96:103]<={reg_A[98:103],{2{1'b0}}};
result[104:111]<={reg_A[106:111],{2{1'b0}}};
result[112:119]<={reg_A[114:119],{2{1'b0}}};
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:15]<={reg_A[11:15],{3{1'b0}}};
result[16:23]<={reg_A[19:23],{3{1'b0}}};
result[24:31]<={reg_A[27:31],{3{1'b0}}};
result[32:39]<={reg_A[35:39],{3{1'b0}}};
result[40:47]<={reg_A[43:47],{3{1'b0}}};
result[48:55]<={reg_A[51:55],{3{1'b0}}};
result[56:63]<={reg_A[59:63],{3{1'b0}}};
result[64:71]<={reg_A[67:71],{3{1'b0}}};
result[72:79]<={reg_A[75:79],{3{1'b0}}};
result[80:87]<={reg_A[83:87],{3{1'b0}}};
result[88:95]<={reg_A[91:95],{3{1'b0}}};
result[96:103]<={reg_A[99:103],{3{1'b0}}};
result[104:111]<={reg_A[107:111],{3{1'b0}}};
result[112:119]<={reg_A[115:119],{3{1'b0}}};
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:15]<={reg_A[12:15],{4{1'b0}}};
result[16:23]<={reg_A[20:23],{4{1'b0}}};
result[24:31]<={reg_A[28:31],{4{1'b0}}};
result[32:39]<={reg_A[36:39],{4{1'b0}}};
result[40:47]<={reg_A[44:47],{4{1'b0}}};
result[48:55]<={reg_A[52:55],{4{1'b0}}};
result[56:63]<={reg_A[60:63],{4{1'b0}}};
result[64:71]<={reg_A[68:71],{4{1'b0}}};
result[72:79]<={reg_A[76:79],{4{1'b0}}};
result[80:87]<={reg_A[84:87],{4{1'b0}}};
result[88:95]<={reg_A[92:95],{4{1'b0}}};
result[96:103]<={reg_A[100:103],{4{1'b0}}};
result[104:111]<={reg_A[108:111],{4{1'b0}}};
result[112:119]<={reg_A[116:119],{4{1'b0}}};
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:15]<={reg_A[13:15],{5{1'b0}}};
result[16:23]<={reg_A[21:23],{5{1'b0}}};
result[24:31]<={reg_A[29:31],{5{1'b0}}};
result[32:39]<={reg_A[37:39],{5{1'b0}}};
result[40:47]<={reg_A[45:47],{5{1'b0}}};
result[48:55]<={reg_A[53:55],{5{1'b0}}};
result[56:63]<={reg_A[61:63],{5{1'b0}}};
result[64:71]<={reg_A[69:71],{5{1'b0}}};
result[72:79]<={reg_A[77:79],{5{1'b0}}};
result[80:87]<={reg_A[85:87],{5{1'b0}}};
result[88:95]<={reg_A[93:95],{5{1'b0}}};
result[96:103]<={reg_A[101:103],{5{1'b0}}};
result[104:111]<={reg_A[109:111],{5{1'b0}}};
result[112:119]<={reg_A[117:119],{5{1'b0}}};
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:15]<={reg_A[14:15],{6{1'b0}}};
result[16:23]<={reg_A[22:23],{6{1'b0}}};
result[24:31]<={reg_A[30:31],{6{1'b0}}};
result[32:39]<={reg_A[38:39],{6{1'b0}}};
result[40:47]<={reg_A[46:47],{6{1'b0}}};
result[48:55]<={reg_A[54:55],{6{1'b0}}};
result[56:63]<={reg_A[62:63],{6{1'b0}}};
result[64:71]<={reg_A[70:71],{6{1'b0}}};
result[72:79]<={reg_A[78:79],{6{1'b0}}};
result[80:87]<={reg_A[86:87],{6{1'b0}}};
result[88:95]<={reg_A[94:95],{6{1'b0}}};
result[96:103]<={reg_A[102:103],{6{1'b0}}};
result[104:111]<={reg_A[110:111],{6{1'b0}}};
result[112:119]<={reg_A[118:119],{6{1'b0}}};
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:15]<={reg_A[15],{7{1'b0}}};
result[16:23]<={reg_A[23],{7{1'b0}}};
result[24:31]<={reg_A[31],{7{1'b0}}};
result[32:39]<={reg_A[39],{7{1'b0}}};
result[40:47]<={reg_A[47],{7{1'b0}}};
result[48:55]<={reg_A[55],{7{1'b0}}};
result[56:63]<={reg_A[63],{7{1'b0}}};
result[64:71]<={reg_A[71],{7{1'b0}}};
result[72:79]<={reg_A[79],{7{1'b0}}};
result[80:87]<={reg_A[87],{7{1'b0}}};
result[88:95]<={reg_A[95],{7{1'b0}}};
result[96:103]<={reg_A[103],{7{1'b0}}};
result[104:111]<={reg_A[111],{7{1'b0}}};
result[112:119]<={reg_A[119],{7{1'b0}}};
result[120:127]<={reg_A[127],{7{1'b0}}};
end
default:
begin
result<=128'b0;
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:31]<={reg_A[17:31],{1'b0}};
result[32:47]<={reg_A[33:47],{1'b0}};
result[48:63]<={reg_A[49:63],{1'b0}};
result[64:79]<={reg_A[65:79],{1'b0}};
result[80:95]<={reg_A[81:95],{1'b0}};
result[96:111]<={reg_A[97:111],{1'b0}};
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:31]<={reg_A[18:31],{2{1'b0}}};
result[32:47]<={reg_A[34:47],{2{1'b0}}};
result[48:63]<={reg_A[50:63],{2{1'b0}}};
result[64:79]<={reg_A[66:79],{2{1'b0}}};
result[80:95]<={reg_A[82:95],{2{1'b0}}};
result[96:111]<={reg_A[98:111],{2{1'b0}}};
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:31]<={reg_A[19:31],{3{1'b0}}};
result[32:47]<={reg_A[35:47],{3{1'b0}}};
result[48:63]<={reg_A[51:63],{3{1'b0}}};
result[64:79]<={reg_A[67:79],{3{1'b0}}};
result[80:95]<={reg_A[83:95],{3{1'b0}}};
result[96:111]<={reg_A[99:111],{3{1'b0}}};
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:31]<={reg_A[20:31],{4{1'b0}}};
result[32:47]<={reg_A[36:47],{4{1'b0}}};
result[48:63]<={reg_A[52:63],{4{1'b0}}};
result[64:79]<={reg_A[68:79],{4{1'b0}}};
result[80:95]<={reg_A[84:95],{4{1'b0}}};
result[96:111]<={reg_A[100:111],{4{1'b0}}};
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:31]<={reg_A[21:31],{5{1'b0}}};
result[32:47]<={reg_A[37:47],{5{1'b0}}};
result[48:63]<={reg_A[52:63],{5{1'b0}}};
result[64:79]<={reg_A[69:79],{5{1'b0}}};
result[80:95]<={reg_A[85:95],{5{1'b0}}};
result[96:111]<={reg_A[101:111],{5{1'b0}}};
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:31]<={reg_A[22:31],{6{1'b0}}};
result[32:47]<={reg_A[38:47],{6{1'b0}}};
result[48:63]<={reg_A[53:63],{6{1'b0}}};
result[64:79]<={reg_A[70:79],{6{1'b0}}};
result[80:95]<={reg_A[86:95],{6{1'b0}}};
result[96:111]<={reg_A[102:111],{6{1'b0}}};
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:31]<={reg_A[23:31],{7{1'b0}}};
result[32:47]<={reg_A[39:47],{7{1'b0}}};
result[48:63]<={reg_A[54:63],{7{1'b0}}};
result[64:79]<={reg_A[71:79],{7{1'b0}}};
result[80:95]<={reg_A[87:95],{7{1'b0}}};
result[96:111]<={reg_A[103:111],{7{1'b0}}};
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:31]<={reg_A[24:31],{8{1'b0}}};
result[32:47]<={reg_A[40:47],{8{1'b0}}};
result[48:63]<={reg_A[55:63],{8{1'b0}}};
result[64:79]<={reg_A[72:79],{8{1'b0}}};
result[80:95]<={reg_A[88:95],{8{1'b0}}};
result[96:111]<={reg_A[104:111],{8{1'b0}}};
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:31]<={reg_A[25:31],{9{1'b0}}};
result[32:47]<={reg_A[41:47],{9{1'b0}}};
result[48:63]<={reg_A[56:63],{9{1'b0}}};
result[64:79]<={reg_A[73:79],{9{1'b0}}};
result[80:95]<={reg_A[89:95],{9{1'b0}}};
result[96:111]<={reg_A[105:111],{9{1'b0}}};
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:31]<={reg_A[26:31],{10{1'b0}}};
result[32:47]<={reg_A[42:47],{10{1'b0}}};
result[48:63]<={reg_A[58:63],{10{1'b0}}};
result[64:79]<={reg_A[74:79],{10{1'b0}}};
result[80:95]<={reg_A[90:95],{10{1'b0}}};
result[96:111]<={reg_A[106:111],{10{1'b0}}};
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:31]<={reg_A[27:31],{11{1'b0}}};
result[32:47]<={reg_A[43:47],{11{1'b0}}};
result[48:63]<={reg_A[59:63],{11{1'b0}}};
result[64:79]<={reg_A[75:79],{11{1'b0}}};
result[80:95]<={reg_A[91:95],{11{1'b0}}};
result[96:111]<={reg_A[107:111],{11{1'b0}}};
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:31]<={reg_A[28:31],{12{1'b0}}};
result[32:47]<={reg_A[44:47],{12{1'b0}}};
result[48:63]<={reg_A[60:63],{12{1'b0}}};
result[64:79]<={reg_A[76:79],{12{1'b0}}};
result[80:95]<={reg_A[92:95],{12{1'b0}}};
result[96:111]<={reg_A[108:111],{12{1'b0}}};
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:31]<={reg_A[29:31],{13{1'b0}}};
result[32:47]<={reg_A[45:47],{13{1'b0}}};
result[48:63]<={reg_A[61:63],{13{1'b0}}};
result[64:79]<={reg_A[77:79],{13{1'b0}}};
result[80:95]<={reg_A[93:95],{13{1'b0}}};
result[96:111]<={reg_A[109:111],{13{1'b0}}};
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:31]<={reg_A[30:31],{14{1'b0}}};
result[32:47]<={reg_A[46:47],{14{1'b0}}};
result[48:63]<={reg_A[62:63],{14{1'b0}}};
result[64:79]<={reg_A[78:79],{14{1'b0}}};
result[80:95]<={reg_A[94:95],{14{1'b0}}};
result[96:111]<={reg_A[110:111],{14{1'b0}}};
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:31]<={reg_A[31],{15{1'b0}}};
result[32:47]<={reg_A[47],{15{1'b0}}};
result[48:63]<={reg_A[63],{15{1'b0}}};
result[64:79]<={reg_A[79],{15{1'b0}}};
result[80:95]<={reg_A[95],{15{1'b0}}};
result[96:111]<={reg_A[111],{15{1'b0}}};
result[112:127]<={reg_A[127],{15{1'b0}}};
end
default:
begin
result<=128'b0;
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:63]<={reg_A[33:63],{1'b0}};
result[64:95]<={reg_A[65:95],{1'b0}};
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:63]<={reg_A[34:63],{2{1'b0}}};
result[64:95]<={reg_A[66:95],{2{1'b0}}};
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:63]<={reg_A[35:63],{3{1'b0}}};
result[64:95]<={reg_A[67:95],{3{1'b0}}};
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:63]<={reg_A[36:63],{4{1'b0}}};
result[64:95]<={reg_A[68:95],{4{1'b0}}};
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:63]<={reg_A[37:63],{5{1'b0}}};
result[64:95]<={reg_A[69:95],{5{1'b0}}};
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:63]<={reg_A[38:63],{6{1'b0}}};
result[64:95]<={reg_A[70:95],{6{1'b0}}};
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:63]<={reg_A[39:63],{7{1'b0}}};
result[64:95]<={reg_A[71:95],{7{1'b0}}};
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:63]<={reg_A[40:63],{8{1'b0}}};
result[64:95]<={reg_A[72:95],{8{1'b0}}};
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9:
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:63]<={reg_A[41:63],{9{1'b0}}};
result[64:95]<={reg_A[73:95],{9{1'b0}}};
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:63]<={reg_A[42:63],{10{1'b0}}};
result[64:95]<={reg_A[74:95],{10{1'b0}}};
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}}};
result[32:63]<={reg_A[43:63],{11{1'b0}}};
result[64:95]<={reg_A[75:95],{11{1'b0}}};
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:63]<={reg_A[44:63],{12{1'b0}}};
result[64:95]<={reg_A[76:95],{12{1'b0}}};
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:63]<={reg_A[45:63],{13{1'b0}}};
result[64:95]<={reg_A[77:95],{13{1'b0}}};
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:63]<={reg_A[46:63],{14{1'b0}}};
result[64:95]<={reg_A[78:95],{14{1'b0}}};
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:63]<={reg_A[47:63],{15{1'b0}}};
result[64:95]<={reg_A[79:95],{15{1'b0}}};
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:63]<={reg_A[48:63],{16{1'b0}}};
result[64:95]<={reg_A[80:95],{16{1'b0}}};
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:63]<={reg_A[49:63],{17{1'b0}}};
result[64:95]<={reg_A[81:95],{17{1'b0}}};
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:63]<={reg_A[50:63],{18{1'b0}}};
result[64:95]<={reg_A[82:95],{18{1'b0}}};
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19:
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:63]<={reg_A[51:63],{19{1'b0}}};
result[64:95]<={reg_A[83:95],{19{1'b0}}};
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:63]<={reg_A[52:63],{20{1'b0}}};
result[64:95]<={reg_A[84:95],{20{1'b0}}};
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:63]<={reg_A[53:63],{21{1'b0}}};
result[64:95]<={reg_A[85:95],{21{1'b0}}};
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:63]<={reg_A[54:63],{22{1'b0}}};
result[64:95]<={reg_A[86:95],{22{1'b0}}};
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:63]<={reg_A[55:63],{23{1'b0}}};
result[64:95]<={reg_A[87:95],{23{1'b0}}};
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:63]<={reg_A[56:63],{24{1'b0}}};
result[64:95]<={reg_A[88:95],{24{1'b0}}};
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:63]<={reg_A[57:63],{25{1'b0}}};
result[64:95]<={reg_A[89:95],{25{1'b0}}};
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:63]<={reg_A[58:63],{26{1'b0}}};
result[64:95]<={reg_A[90:95],{26{1'b0}}};
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:63]<={reg_A[59:63],{27{1'b0}}};
result[64:95]<={reg_A[91:95],{27{1'b0}}};
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:63]<={reg_A[60:63],{28{1'b0}}};
result[64:95]<={reg_A[92:95],{28{1'b0}}};
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29:
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:63]<={reg_A[61:63],{29{1'b0}}};
result[64:95]<={reg_A[93:95],{29{1'b0}}};
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:63]<={reg_A[62:63],{30{1'b0}}};
result[64:95]<={reg_A[94:95],{30{1'b0}}};
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:63]<={reg_A[63],{31{1'b0}}};
result[64:95]<={reg_A[95],{31{1'b0}}};
result[96:127]<={reg_A[127],{31{1'b0}}};
end
default:
begin
result<=128'b0;
end
endcase
end
default:
result<=128'b0;
endcase
end
// ==============================================================
// SRLI instruction
`aluwsrli:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={{1'b0},reg_A[0:6]};
result[8:15]<={{1'b0},reg_A[8:14]};
result[16:23]<={{1'b0},reg_A[16:22]};
result[24:31]<={{1'b0},reg_A[24:30]};
result[32:39]<={{1'b0},reg_A[32:38]};
result[40:47]<={{1'b0},reg_A[40:46]};
result[48:55]<={{1'b0},reg_A[48:54]};
result[56:63]<={{1'b0},reg_A[56:62]};
result[64:71]<={{1'b0},reg_A[64:70]};
result[72:79]<={{1'b0},reg_A[72:78]};
result[80:87]<={{1'b0},reg_A[80:86]};
result[88:95]<={{1'b0},reg_A[88:94]};
result[96:103]<={{1'b0},reg_A[96:102]};
result[104:111]<={{1'b0},reg_A[104:110]};
result[112:119]<={{1'b0},reg_A[112:118]};
result[120:127]<={{1'b0},reg_A[120:126]};
end
3'd2:
begin
result[0:7]<={{2{1'b0}},reg_A[0:5]};
result[8:15]<={{2{1'b0}},reg_A[8:13]};
result[16:23]<={{2{1'b0}},reg_A[16:21]};
result[24:31]<={{2{1'b0}},reg_A[24:29]};
result[32:39]<={{2{1'b0}},reg_A[32:37]};
result[40:47]<={{2{1'b0}},reg_A[40:45]};
result[48:55]<={{2{1'b0}},reg_A[48:53]};
result[56:63]<={{2{1'b0}},reg_A[56:61]};
result[64:71]<={{2{1'b0}},reg_A[64:69]};
result[72:79]<={{2{1'b0}},reg_A[72:77]};
result[80:87]<={{2{1'b0}},reg_A[80:85]};
result[88:95]<={{2{1'b0}},reg_A[88:93]};
result[96:103]<={{2{1'b0}},reg_A[96:101]};
result[104:111]<={{2{1'b0}},reg_A[104:109]};
result[112:119]<={{2{1'b0}},reg_A[112:117]};
result[120:127]<={{2{1'b0}},reg_A[120:125]};
end
3'd3:
begin
result[0:7]<={{3{1'b0}},reg_A[0:4]};
result[8:15]<={{3{1'b0}},reg_A[8:12]};
result[16:23]<={{3{1'b0}},reg_A[16:20]};
result[24:31]<={{3{1'b0}},reg_A[24:28]};
result[32:39]<={{3{1'b0}},reg_A[32:36]};
result[40:47]<={{3{1'b0}},reg_A[40:44]};
result[48:55]<={{3{1'b0}},reg_A[48:52]};
result[56:63]<={{3{1'b0}},reg_A[56:60]};
result[64:71]<={{3{1'b0}},reg_A[64:68]};
result[72:79]<={{3{1'b0}},reg_A[72:76]};
result[80:87]<={{3{1'b0}},reg_A[80:84]};
result[88:95]<={{3{1'b0}},reg_A[88:92]};
result[96:103]<={{3{1'b0}},reg_A[96:100]};
result[104:111]<={{3{1'b0}},reg_A[104:108]};
result[112:119]<={{3{1'b0}},reg_A[112:116]};
result[120:127]<={{3{1'b0}},reg_A[120:124]};
end
3'd4:
begin
result[0:7]<={{4{1'b0}},reg_A[0:3]};
result[8:15]<={{4{1'b0}},reg_A[8:11]};
result[16:23]<={{4{1'b0}},reg_A[16:19]};
result[24:31]<={{4{1'b0}},reg_A[24:27]};
result[32:39]<={{4{1'b0}},reg_A[32:35]};
result[40:47]<={{4{1'b0}},reg_A[40:43]};
result[48:55]<={{4{1'b0}},reg_A[48:51]};
result[56:63]<={{4{1'b0}},reg_A[56:69]};
result[64:71]<={{4{1'b0}},reg_A[64:67]};
result[72:79]<={{4{1'b0}},reg_A[72:75]};
result[80:87]<={{4{1'b0}},reg_A[80:83]};
result[88:95]<={{4{1'b0}},reg_A[88:91]};
result[96:103]<={{4{1'b0}},reg_A[96:99]};
result[104:111]<={{4{1'b0}},reg_A[104:107]};
result[112:119]<={{4{1'b0}},reg_A[112:115]};
result[120:127]<={{4{1'b0}},reg_A[120:123]};
end
3'd5:
begin
result[0:7]<={{5{1'b0}},reg_A[0:2]};
result[8:15]<={{5{1'b0}},reg_A[8:10]};
result[16:23]<={{5{1'b0}},reg_A[16:18]};
result[24:31]<={{5{1'b0}},reg_A[24:26]};
result[32:39]<={{5{1'b0}},reg_A[32:34]};
result[40:47]<={{5{1'b0}},reg_A[40:42]};
result[48:55]<={{5{1'b0}},reg_A[48:50]};
result[56:63]<={{5{1'b0}},reg_A[56:68]};
result[64:71]<={{5{1'b0}},reg_A[64:66]};
result[72:79]<={{5{1'b0}},reg_A[72:74]};
result[80:87]<={{5{1'b0}},reg_A[80:82]};
result[88:95]<={{5{1'b0}},reg_A[88:90]};
result[96:103]<={{5{1'b0}},reg_A[96:98]};
result[104:111]<={{5{1'b0}},reg_A[104:106]};
result[112:119]<={{5{1'b0}},reg_A[112:114]};
result[120:127]<={{5{1'b0}},reg_A[120:122]};
end
3'd6:
begin
result[0:7]<={{6{1'b0}},reg_A[0:1]};
result[8:15]<={{6{1'b0}},reg_A[8:9]};
result[16:23]<={{6{1'b0}},reg_A[16:17]};
result[24:31]<={{6{1'b0}},reg_A[24:25]};
result[32:39]<={{6{1'b0}},reg_A[32:33]};
result[40:47]<={{6{1'b0}},reg_A[40:41]};
result[48:55]<={{6{1'b0}},reg_A[48:49]};
result[56:63]<={{6{1'b0}},reg_A[56:67]};
result[64:71]<={{6{1'b0}},reg_A[64:65]};
result[72:79]<={{6{1'b0}},reg_A[72:73]};
result[80:87]<={{6{1'b0}},reg_A[80:81]};
result[88:95]<={{6{1'b0}},reg_A[88:89]};
result[96:103]<={{6{1'b0}},reg_A[96:97]};
result[104:111]<={{6{1'b0}},reg_A[104:105]};
result[112:119]<={{6{1'b0}},reg_A[112:113]};
result[120:127]<={{6{1'b0}},reg_A[120:121]};
end
3'd7:
begin
result[0:7]<={{7{1'b0}},reg_A[0]};
result[8:15]<={{7{1'b0}},reg_A[8]};
result[16:23]<={{7{1'b0}},reg_A[16]};
result[24:31]<={{7{1'b0}},reg_A[24]};
result[32:39]<={{7{1'b0}},reg_A[32]};
result[40:47]<={{7{1'b0}},reg_A[40]};
result[48:55]<={{7{1'b0}},reg_A[48]};
result[56:63]<={{7{1'b0}},reg_A[56]};
result[64:71]<={{7{1'b0}},reg_A[64]};
result[72:79]<={{7{1'b0}},reg_A[72]};
result[80:87]<={{7{1'b0}},reg_A[80]};
result[88:95]<={{7{1'b0}},reg_A[88]};
result[96:103]<={{7{1'b0}},reg_A[96]};
result[104:111]<={{7{1'b0}},reg_A[104]};
result[112:119]<={{7{1'b0}},reg_A[112]};
result[120:127]<={{7{1'b0}},reg_A[120]};
end
default:
begin
result<=128'b0;
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={{1'b0},reg_A[0:14]};
result[16:31]<={{1'b0},reg_A[16:30]};
result[32:47]<={{1'b0},reg_A[32:46]};
result[48:63]<={{1'b0},reg_A[48:62]};
result[64:79]<={{1'b0},reg_A[64:78]};
result[80:95]<={{1'b0},reg_A[80:94]};
result[96:111]<={{1'b0},reg_A[96:110]};
result[112:127]<={{1'b0},reg_A[112:126]};
end
4'd2:
begin
result[0:15]<={{2{1'b0}},reg_A[0:13]};
result[16:31]<={{2{1'b0}},reg_A[16:29]};
result[32:47]<={{2{1'b0}},reg_A[32:45]};
result[48:63]<={{2{1'b0}},reg_A[48:61]};
result[64:79]<={{2{1'b0}},reg_A[64:77]};
result[80:95]<={{2{1'b0}},reg_A[80:93]};
result[96:111]<={{2{1'b0}},reg_A[96:109]};
result[112:127]<={{2{1'b0}},reg_A[112:125]};
end
4'd3:
begin
result[0:15]<={{3{1'b0}},reg_A[0:12]};
result[16:31]<={{3{1'b0}},reg_A[16:28]};
result[32:47]<={{3{1'b0}},reg_A[32:44]};
result[48:63]<={{3{1'b0}},reg_A[48:60]};
result[64:79]<={{3{1'b0}},reg_A[64:76]};
result[80:95]<={{3{1'b0}},reg_A[80:92]};
result[96:111]<={{3{1'b0}},reg_A[96:108]};
result[112:127]<={{3{1'b0}},reg_A[112:124]};
end
4'd4:
begin
result[0:15]<={{4{1'b0}},reg_A[0:11]};
result[16:31]<={{4{1'b0}},reg_A[16:27]};
result[32:47]<={{4{1'b0}},reg_A[32:43]};
result[48:63]<={{4{1'b0}},reg_A[48:59]};
result[64:79]<={{4{1'b0}},reg_A[64:75]};
result[80:95]<={{4{1'b0}},reg_A[80:91]};
result[96:111]<={{4{1'b0}},reg_A[96:107]};
result[112:127]<={{4{1'b0}},reg_A[112:123]};
end
4'd5:
begin
result[0:15]<={{5{1'b0}},reg_A[0:10]};
result[16:31]<={{5{1'b0}},reg_A[16:26]};
result[32:47]<={{5{1'b0}},reg_A[32:42]};
result[48:63]<={{5{1'b0}},reg_A[48:58]};
result[64:79]<={{5{1'b0}},reg_A[64:74]};
result[80:95]<={{5{1'b0}},reg_A[80:90]};
result[96:111]<={{5{1'b0}},reg_A[96:106]};
result[112:127]<={{5{1'b0}},reg_A[112:122]};
end
4'd6:
begin
result[0:15]<={{6{1'b0}},reg_A[0:9]};
result[16:31]<={{6{1'b0}},reg_A[16:25]};
result[32:47]<={{6{1'b0}},reg_A[32:41]};
result[48:63]<={{6{1'b0}},reg_A[48:57]};
result[64:79]<={{6{1'b0}},reg_A[64:73]};
result[80:95]<={{6{1'b0}},reg_A[80:89]};
result[96:111]<={{6{1'b0}},reg_A[96:105]};
result[112:127]<={{6{1'b0}},reg_A[112:121]};
end
4'd7:
begin
result[0:15]<={{7{1'b0}},reg_A[0:8]};
result[16:31]<={{7{1'b0}},reg_A[16:24]};
result[32:47]<={{7{1'b0}},reg_A[32:40]};
result[48:63]<={{7{1'b0}},reg_A[48:56]};
result[64:79]<={{7{1'b0}},reg_A[64:72]};
result[80:95]<={{7{1'b0}},reg_A[80:88]};
result[96:111]<={{7{1'b0}},reg_A[96:104]};
result[112:127]<={{7{1'b0}},reg_A[112:120]};
end
4'd8:
begin
result[0:15]<={{8{1'b0}},reg_A[0:7]};
result[16:31]<={{8{1'b0}},reg_A[16:23]};
result[32:47]<={{8{1'b0}},reg_A[32:39]};
result[48:63]<={{8{1'b0}},reg_A[48:55]};
result[64:79]<={{8{1'b0}},reg_A[64:71]};
result[80:95]<={{8{1'b0}},reg_A[80:87]};
result[96:111]<={{8{1'b0}},reg_A[96:103]};
result[112:127]<={{8{1'b0}},reg_A[112:119]};
end
4'd9:
begin
result[0:15]<={{9{1'b0}},reg_A[0:6]};
result[16:31]<={{9{1'b0}},reg_A[16:22]};
result[32:47]<={{9{1'b0}},reg_A[32:38]};
result[48:63]<={{9{1'b0}},reg_A[48:54]};
result[64:79]<={{9{1'b0}},reg_A[64:70]};
result[80:95]<={{9{1'b0}},reg_A[80:86]};
result[96:111]<={{9{1'b0}},reg_A[96:102]};
result[112:127]<={{9{1'b0}},reg_A[112:118]};
end
4'd10:
begin
result[0:15]<={{10{1'b0}},reg_A[0:5]};
result[16:31]<={{10{1'b0}},reg_A[16:21]};
result[32:47]<={{10{1'b0}},reg_A[32:37]};
result[48:63]<={{10{1'b0}},reg_A[48:53]};
result[64:79]<={{10{1'b0}},reg_A[64:69]};
result[80:95]<={{10{1'b0}},reg_A[80:85]};
result[96:111]<={{10{1'b0}},reg_A[96:101]};
result[112:127]<={{10{1'b0}},reg_A[112:117]};
end
4'd11:
begin
result[0:15]<={{11{1'b0}},reg_A[0:4]};
result[16:31]<={{11{1'b0}},reg_A[16:20]};
result[32:47]<={{11{1'b0}},reg_A[32:36]};
result[48:63]<={{11{1'b0}},reg_A[48:52]};
result[64:79]<={{11{1'b0}},reg_A[64:68]};
result[80:95]<={{11{1'b0}},reg_A[80:84]};
result[96:111]<={{11{1'b0}},reg_A[96:100]};
result[112:127]<={{11{1'b0}},reg_A[112:116]};
end
4'd12:
begin
result[0:15]<={{12{1'b0}},reg_A[0:3]};
result[16:31]<={{12{1'b0}},reg_A[16:19]};
result[32:47]<={{12{1'b0}},reg_A[32:35]};
result[48:63]<={{12{1'b0}},reg_A[48:51]};
result[64:79]<={{12{1'b0}},reg_A[64:67]};
result[80:95]<={{12{1'b0}},reg_A[80:83]};
result[96:111]<={{12{1'b0}},reg_A[96:99]};
result[112:127]<={{12{1'b0}},reg_A[112:115]};
end
4'd13:
begin
result[0:15]<={{13{1'b0}},reg_A[0:2]};
result[16:31]<={{13{1'b0}},reg_A[16:18]};
result[32:47]<={{13{1'b0}},reg_A[32:34]};
result[48:63]<={{13{1'b0}},reg_A[48:50]};
result[64:79]<={{13{1'b0}},reg_A[64:66]};
result[80:95]<={{13{1'b0}},reg_A[80:82]};
result[96:111]<={{13{1'b0}},reg_A[96:98]};
result[112:127]<={{13{1'b0}},reg_A[112:114]};
end
4'd14:
begin
result[0:15]<={{14{1'b0}},reg_A[0:1]};
result[16:31]<={{14{1'b0}},reg_A[16:17]};
result[32:47]<={{14{1'b0}},reg_A[32:33]};
result[48:63]<={{14{1'b0}},reg_A[48:49]};
result[64:79]<={{14{1'b0}},reg_A[64:65]};
result[80:95]<={{14{1'b0}},reg_A[80:81]};
result[96:111]<={{14{1'b0}},reg_A[96:97]};
result[112:127]<={{14{1'b0}},reg_A[112:113]};
end
4'd15:
begin
result[0:15]<={{15{1'b0}},reg_A[0]};
result[16:31]<={{15{1'b0}},reg_A[16]};
result[32:47]<={{15{1'b0}},reg_A[32]};
result[48:63]<={{15{1'b0}},reg_A[48]};
result[64:79]<={{15{1'b0}},reg_A[64]};
result[80:95]<={{15{1'b0}},reg_A[80]};
result[96:111]<={{15{1'b0}},reg_A[96]};
result[112:127]<={{15{1'b0}},reg_A[112]};
end
default:
begin
result<=128'b0;
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={{1'b0},reg_A[0:30]};
result[32:63]<={{1'b0},reg_A[32:62]};
result[64:95]<={{1'b0},reg_A[64:94]};
result[96:127]<={{1'b0},reg_A[96:126]};
end
5'd2:
begin
result[0:31]<={{2{1'b0}},reg_A[0:29]};
result[32:63]<={{2{1'b0}},reg_A[32:61]};
result[64:95]<={{2{1'b0}},reg_A[64:93]};
result[96:127]<={{2{1'b0}},reg_A[96:125]};
end
5'd3:
begin
result[0:31]<={{3{1'b0}},reg_A[0:28]};
result[32:63]<={{3{1'b0}},reg_A[32:60]};
result[64:95]<={{3{1'b0}},reg_A[64:92]};
result[96:127]<={{3{1'b0}},reg_A[96:124]};
end
5'd4:
begin
result[0:31]<={{4{1'b0}},reg_A[0:27]};
result[32:63]<={{4{1'b0}},reg_A[32:59]};
result[64:95]<={{4{1'b0}},reg_A[64:91]};
result[96:127]<={{4{1'b0}},reg_A[96:123]};
end
5'd5:
begin
result[0:31]<={{5{1'b0}},reg_A[0:26]};
result[32:63]<={{5{1'b0}},reg_A[32:58]};
result[64:95]<={{5{1'b0}},reg_A[64:90]};
result[96:127]<={{5{1'b0}},reg_A[96:122]};
end
5'd6:
begin
result[0:31]<={{6{1'b0}},reg_A[0:25]};
result[32:63]<={{6{1'b0}},reg_A[32:57]};
result[64:95]<={{6{1'b0}},reg_A[64:89]};
result[96:127]<={{6{1'b0}},reg_A[96:121]};
end
5'd7:
begin
result[0:31]<={{7{1'b0}},reg_A[0:24]};
result[32:63]<={{7{1'b0}},reg_A[32:56]};
result[64:95]<={{7{1'b0}},reg_A[64:88]};
result[96:127]<={{7{1'b0}},reg_A[96:120]};
end
5'd8:
begin
result[0:31]<={{8{1'b0}},reg_A[0:23]};
result[32:63]<={{8{1'b0}},reg_A[32:55]};
result[64:95]<={{8{1'b0}},reg_A[64:87]};
result[96:127]<={{8{1'b0}},reg_A[96:119]};
end
5'd9:
begin
result[0:31]<={{9{1'b0}},reg_A[0:22]};
result[32:63]<={{9{1'b0}},reg_A[32:54]};
result[64:95]<={{9{1'b0}},reg_A[64:86]};
result[96:127]<={{9{1'b0}},reg_A[96:118]};
end
5'd10:
begin
result[0:31]<={{10{1'b0}},reg_A[0:21]};
result[32:63]<={{10{1'b0}},reg_A[32:53]};
result[64:95]<={{10{1'b0}},reg_A[64:85]};
result[96:127]<={{10{1'b0}},reg_A[96:117]};
end
5'd11:
begin
result[0:31]<={{11{1'b0}},reg_A[0:20]};
result[32:63]<={{11{1'b0}},reg_A[32:52]};
result[64:95]<={{11{1'b0}},reg_A[64:84]};
result[96:127]<={{11{1'b0}},reg_A[96:116]};
end
5'd12:
begin
result[0:31]<={{12{1'b0}},reg_A[0:19]};
result[32:63]<={{12{1'b0}},reg_A[32:51]};
result[64:95]<={{12{1'b0}},reg_A[64:83]};
result[96:127]<={{12{1'b0}},reg_A[96:115]};
end
5'd13:
begin
result[0:31]<={{13{1'b0}},reg_A[0:18]};
result[32:63]<={{13{1'b0}},reg_A[32:50]};
result[64:95]<={{13{1'b0}},reg_A[64:82]};
result[96:127]<={{13{1'b0}},reg_A[96:114]};
end
5'd14:
begin
result[0:31]<={{14{1'b0}},reg_A[0:17]};
result[32:63]<={{14{1'b0}},reg_A[32:49]};
result[64:95]<={{14{1'b0}},reg_A[64:81]};
result[96:127]<={{14{1'b0}},reg_A[96:113]};
end
5'd15:
begin
result[0:31]<={{15{1'b0}},reg_A[0:16]};
result[32:63]<={{15{1'b0}},reg_A[32:48]};
result[64:95]<={{15{1'b0}},reg_A[64:80]};
result[96:127]<={{15{1'b0}},reg_A[96:112]};
end
5'd16:
begin
result[0:31]<={{16{1'b0}},reg_A[0:15]};
result[32:63]<={{16{1'b0}},reg_A[32:47]};
result[64:95]<={{16{1'b0}},reg_A[64:79]};
result[96:127]<={{16{1'b0}},reg_A[96:111]};
end
5'd17:
begin
result[0:31]<={{17{1'b0}},reg_A[0:14]};
result[32:63]<={{17{1'b0}},reg_A[32:46]};
result[64:95]<={{17{1'b0}},reg_A[64:78]};
result[96:127]<={{17{1'b0}},reg_A[96:110]};
end
5'd18:
begin
result[0:31]<={{18{1'b0}},reg_A[0:13]};
result[32:63]<={{18{1'b0}},reg_A[32:45]};
result[64:95]<={{18{1'b0}},reg_A[64:77]};
result[96:127]<={{18{1'b0}},reg_A[96:109]};
end
5'd19:
begin
result[0:31]<={{19{1'b0}},reg_A[0:12]};
result[32:63]<={{19{1'b0}},reg_A[32:44]};
result[64:95]<={{19{1'b0}},reg_A[64:76]};
result[96:127]<={{19{1'b0}},reg_A[96:108]};
end
5'd20:
begin
result[0:31]<={{20{1'b0}},reg_A[0:11]};
result[32:63]<={{20{1'b0}},reg_A[32:43]};
result[64:95]<={{20{1'b0}},reg_A[64:75]};
result[96:127]<={{20{1'b0}},reg_A[96:107]};
end
5'd21:
begin
result[0:31]<={{21{1'b0}},reg_A[0:10]};
result[32:63]<={{21{1'b0}},reg_A[32:42]};
result[64:95]<={{21{1'b0}},reg_A[64:74]};
result[96:127]<={{21{1'b0}},reg_A[96:106]};
end
5'd22:
begin
result[0:31]<={{22{1'b0}},reg_A[0:9]};
result[32:63]<={{22{1'b0}},reg_A[32:41]};
result[64:95]<={{22{1'b0}},reg_A[64:73]};
result[96:127]<={{22{1'b0}},reg_A[96:105]};
end
5'd23:
begin
result[0:31]<={{23{1'b0}},reg_A[0:8]};
result[32:63]<={{23{1'b0}},reg_A[32:40]};
result[64:95]<={{23{1'b0}},reg_A[64:72]};
result[96:127]<={{23{1'b0}},reg_A[96:104]};
end
5'd24:
begin
result[0:31]<={{24{1'b0}},reg_A[0:7]};
result[32:63]<={{24{1'b0}},reg_A[32:39]};
result[64:95]<={{24{1'b0}},reg_A[64:71]};
result[96:127]<={{24{1'b0}},reg_A[96:103]};
end
5'd25:
begin
result[0:31]<={{25{1'b0}},reg_A[0:6]};
result[32:63]<={{25{1'b0}},reg_A[32:38]};
result[64:95]<={{25{1'b0}},reg_A[64:70]};
result[96:127]<={{25{1'b0}},reg_A[96:102]};
end
5'd26:
begin
result[0:31]<={{26{1'b0}},reg_A[0:5]};
result[32:63]<={{26{1'b0}},reg_A[32:37]};
result[64:95]<={{26{1'b0}},reg_A[64:69]};
result[96:127]<={{26{1'b0}},reg_A[96:101]};
end
5'd27:
begin
result[0:31]<={{27{1'b0}},reg_A[0:4]};
result[32:63]<={{27{1'b0}},reg_A[32:36]};
result[64:95]<={{27{1'b0}},reg_A[64:68]};
result[96:127]<={{27{1'b0}},reg_A[96:100]};
end
5'd28:
begin
result[0:31]<={{28{1'b0}},reg_A[0:3]};
result[32:63]<={{28{1'b0}},reg_A[32:35]};
result[64:95]<={{28{1'b0}},reg_A[64:67]};
result[96:127]<={{28{1'b0}},reg_A[96:99]};
end
5'd29:
begin
result[0:31]<={{29{1'b0}},reg_A[0:2]};
result[32:63]<={{29{1'b0}},reg_A[32:34]};
result[64:95]<={{29{1'b0}},reg_A[64:66]};
result[96:127]<={{29{1'b0}},reg_A[96:98]};
end
5'd30:
begin
result[0:31]<={{30{1'b0}},reg_A[0:1]};
result[32:63]<={{30{1'b0}},reg_A[32:33]};
result[64:95]<={{30{1'b0}},reg_A[64:65]};
result[96:127]<={{30{1'b0}},reg_A[96:97]};
end
5'd31:
begin
result[0:31]<={{31{1'b0}},reg_A[0]};
result[32:63]<={{31{1'b0}},reg_A[32]};
result[64:95]<={{31{1'b0}},reg_A[64]};
result[96:127]<={{31{1'b0}},reg_A[96]};
end
default:
begin
result<=128'b0;
end
endcase
end
default:
begin
result<=128'b0;
end
endcase
end
// ==============================================================
// SRAI instruction
`aluwsrai:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={{reg_A[0]},reg_A[0:6]};
result[8:15]<={{reg_A[8]},reg_A[8:14]};
result[16:23]<={{reg_A[16]},reg_A[16:22]};
result[24:31]<={{reg_A[24]},reg_A[24:30]};
result[32:39]<={{reg_A[32]},reg_A[32:38]};
result[40:47]<={{reg_A[40]},reg_A[40:46]};
result[48:55]<={{reg_A[48]},reg_A[48:54]};
result[56:63]<={{reg_A[56]},reg_A[56:62]};
result[64:71]<={{reg_A[64]},reg_A[64:70]};
result[72:79]<={{reg_A[72]},reg_A[72:78]};
result[80:87]<={{reg_A[80]},reg_A[80:86]};
result[88:95]<={{reg_A[88]},reg_A[88:94]};
result[96:103]<={{reg_A[96]},reg_A[96:102]};
result[104:111]<={{reg_A[104]},reg_A[104:110]};
result[112:119]<={{reg_A[112]},reg_A[112:118]};
result[120:127]<={{reg_A[120]},reg_A[120:126]};
end
3'd2:
begin
result[0:7]<={{2{reg_A[0]}},reg_A[0:5]};
result[8:15]<={{2{reg_A[8]}},reg_A[8:13]};
result[16:23]<={{2{reg_A[16]}},reg_A[16:21]};
result[24:31]<={{2{reg_A[24]}},reg_A[24:29]};
result[32:39]<={{2{reg_A[32]}},reg_A[32:37]};
result[40:47]<={{2{reg_A[40]}},reg_A[40:45]};
result[48:55]<={{2{reg_A[48]}},reg_A[48:53]};
result[56:63]<={{2{reg_A[56]}},reg_A[56:61]};
result[64:71]<={{2{reg_A[64]}},reg_A[64:69]};
result[72:79]<={{2{reg_A[72]}},reg_A[72:77]};
result[80:87]<={{2{reg_A[80]}},reg_A[80:85]};
result[88:95]<={{2{reg_A[88]}},reg_A[88:93]};
result[96:103]<={{2{reg_A[96]}},reg_A[96:101]};
result[104:111]<={{2{reg_A[104]}},reg_A[104:109]};
result[112:119]<={{2{reg_A[112]}},reg_A[112:117]};
result[120:127]<={{2{reg_A[120]}},reg_A[120:125]};
end
3'd3:
begin
result[0:7]<={{3{reg_A[0]}},reg_A[0:4]};
result[8:15]<={{3{reg_A[8]}},reg_A[8:12]};
result[16:23]<={{3{reg_A[16]}},reg_A[16:20]};
result[24:31]<={{3{reg_A[24]}},reg_A[24:28]};
result[32:39]<={{3{reg_A[32]}},reg_A[32:36]};
result[40:47]<={{3{reg_A[40]}},reg_A[40:44]};
result[48:55]<={{3{reg_A[48]}},reg_A[48:52]};
result[56:63]<={{3{reg_A[56]}},reg_A[56:60]};
result[64:71]<={{3{reg_A[64]}},reg_A[64:68]};
result[72:79]<={{3{reg_A[72]}},reg_A[72:76]};
result[80:87]<={{3{reg_A[80]}},reg_A[80:84]};
result[88:95]<={{3{reg_A[88]}},reg_A[88:92]};
result[96:103]<={{3{reg_A[96]}},reg_A[96:100]};
result[104:111]<={{3{reg_A[104]}},reg_A[104:108]};
result[112:119]<={{3{reg_A[112]}},reg_A[112:116]};
result[120:127]<={{3{reg_A[120]}},reg_A[120:124]};
end
3'd4:
begin
result[0:7]<={{4{reg_A[0]}},reg_A[0:3]};
result[8:15]<={{4{reg_A[8]}},reg_A[8:11]};
result[16:23]<={{4{reg_A[16]}},reg_A[16:19]};
result[24:31]<={{4{reg_A[24]}},reg_A[24:27]};
result[32:39]<={{4{reg_A[32]}},reg_A[32:35]};
result[40:47]<={{4{reg_A[40]}},reg_A[40:43]};
result[48:55]<={{4{reg_A[48]}},reg_A[48:51]};
result[56:63]<={{4{reg_A[56]}},reg_A[56:69]};
result[64:71]<={{4{reg_A[64]}},reg_A[64:67]};
result[72:79]<={{4{reg_A[72]}},reg_A[72:75]};
result[80:87]<={{4{reg_A[80]}},reg_A[80:83]};
result[88:95]<={{4{reg_A[88]}},reg_A[88:91]};
result[96:103]<={{4{reg_A[96]}},reg_A[96:99]};
result[104:111]<={{4{reg_A[104]}},reg_A[104:107]};
result[112:119]<={{4{reg_A[112]}},reg_A[112:115]};
result[120:127]<={{4{reg_A[120]}},reg_A[120:123]};
end
3'd5:
begin
result[0:7]<={{5{reg_A[0]}},reg_A[0:2]};
result[8:15]<={{5{reg_A[8]}},reg_A[8:10]};
result[16:23]<={{5{reg_A[16]}},reg_A[16:18]};
result[24:31]<={{5{reg_A[24]}},reg_A[24:26]};
result[32:39]<={{5{reg_A[32]}},reg_A[32:34]};
result[40:47]<={{5{reg_A[40]}},reg_A[40:42]};
result[48:55]<={{5{reg_A[48]}},reg_A[48:50]};
result[56:63]<={{5{reg_A[56]}},reg_A[56:68]};
result[64:71]<={{5{reg_A[64]}},reg_A[64:66]};
result[72:79]<={{5{reg_A[72]}},reg_A[72:74]};
result[80:87]<={{5{reg_A[80]}},reg_A[80:82]};
result[88:95]<={{5{reg_A[88]}},reg_A[88:90]};
result[96:103]<={{5{reg_A[96]}},reg_A[96:98]};
result[104:111]<={{5{reg_A[104]}},reg_A[104:106]};
result[112:119]<={{5{reg_A[112]}},reg_A[112:114]};
result[120:127]<={{5{reg_A[120]}},reg_A[120:122]};
end
3'd6:
begin
result[0:7]<={{6{reg_A[0]}},reg_A[0:1]};
result[8:15]<={{6{reg_A[8]}},reg_A[8:9]};
result[16:23]<={{6{reg_A[16]}},reg_A[16:17]};
result[24:31]<={{6{reg_A[24]}},reg_A[24:25]};
result[32:39]<={{6{reg_A[32]}},reg_A[32:33]};
result[40:47]<={{6{reg_A[40]}},reg_A[40:41]};
result[48:55]<={{6{reg_A[48]}},reg_A[48:49]};
result[56:63]<={{6{reg_A[56]}},reg_A[56:67]};
result[64:71]<={{6{reg_A[64]}},reg_A[64:65]};
result[72:79]<={{6{reg_A[72]}},reg_A[72:73]};
result[80:87]<={{6{reg_A[80]}},reg_A[80:81]};
result[88:95]<={{6{reg_A[88]}},reg_A[88:89]};
result[96:103]<={{6{reg_A[96]}},reg_A[96:97]};
result[104:111]<={{6{reg_A[104]}},reg_A[104:105]};
result[112:119]<={{6{reg_A[112]}},reg_A[112:113]};
result[120:127]<={{6{reg_A[120]}},reg_A[120:121]};
end
3'd7:
begin
result[0:7]<={{7{reg_A[0]}},reg_A[0]};
result[8:15]<={{7{reg_A[8]}},reg_A[8]};
result[16:23]<={{7{reg_A[16]}},reg_A[16]};
result[24:31]<={{7{reg_A[24]}},reg_A[24]};
result[32:39]<={{7{reg_A[32]}},reg_A[32]};
result[40:47]<={{7{reg_A[40]}},reg_A[40]};
result[48:55]<={{7{reg_A[48]}},reg_A[48]};
result[56:63]<={{7{reg_A[56]}},reg_A[56]};
result[64:71]<={{7{reg_A[64]}},reg_A[64]};
result[72:79]<={{7{reg_A[72]}},reg_A[72]};
result[80:87]<={{7{reg_A[80]}},reg_A[80]};
result[88:95]<={{7{reg_A[88]}},reg_A[88]};
result[96:103]<={{7{reg_A[96]}},reg_A[96]};
result[104:111]<={{7{reg_A[104]}},reg_A[104]};
result[112:119]<={{7{reg_A[112]}},reg_A[112]};
result[120:127]<={{7{reg_A[120]}},reg_A[120]};
end
default:
begin
result<=128'b0;
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={{reg_A[0]},reg_A[0:14]};
result[16:31]<={{reg_A[16]},reg_A[16:30]};
result[32:47]<={{reg_A[32]},reg_A[32:46]};
result[48:63]<={{reg_A[48]},reg_A[48:62]};
result[64:79]<={{reg_A[64]},reg_A[64:78]};
result[80:95]<={{reg_A[80]},reg_A[80:94]};
result[96:111]<={{reg_A[96]},reg_A[96:110]};
result[112:127]<={{reg_A[112]},reg_A[112:126]};
end
4'd2:
begin
result[0:15]<={{2{reg_A[0]}},reg_A[0:13]};
result[16:31]<={{2{reg_A[16]}},reg_A[16:29]};
result[32:47]<={{2{reg_A[32]}},reg_A[32:45]};
result[48:63]<={{2{reg_A[48]}},reg_A[48:61]};
result[64:79]<={{2{reg_A[64]}},reg_A[64:77]};
result[80:95]<={{2{reg_A[80]}},reg_A[80:93]};
result[96:111]<={{2{reg_A[96]}},reg_A[96:109]};
result[112:127]<={{2{reg_A[112]}},reg_A[112:125]};
end
4'd3:
begin
result[0:15]<={{3{reg_A[0]}},reg_A[0:12]};
result[16:31]<={{3{reg_A[16]}},reg_A[16:28]};
result[32:47]<={{3{reg_A[32]}},reg_A[32:44]};
result[48:63]<={{3{reg_A[48]}},reg_A[48:60]};
result[64:79]<={{3{reg_A[64]}},reg_A[64:76]};
result[80:95]<={{3{reg_A[80]}},reg_A[80:92]};
result[96:111]<={{3{reg_A[96]}},reg_A[96:108]};
result[112:127]<={{3{reg_A[112]}},reg_A[112:124]};
end
4'd4:
begin
result[0:15]<={{4{reg_A[0]}},reg_A[0:11]};
result[16:31]<={{4{reg_A[8]}},reg_A[16:27]};
result[32:47]<={{4{reg_A[16]}},reg_A[32:43]};
result[48:63]<={{4{reg_A[32]}},reg_A[48:59]};
result[64:79]<={{4{reg_A[48]}},reg_A[64:75]};
result[80:95]<={{4{reg_A[64]}},reg_A[80:91]};
result[96:111]<={{4{reg_A[80]}},reg_A[96:107]};
result[112:127]<={{4{reg_A[112]}},reg_A[112:123]};
end
4'd5:
begin
result[0:15]<={{5{reg_A[0]}},reg_A[0:10]};
result[16:31]<={{5{reg_A[16]}},reg_A[16:26]};
result[32:47]<={{5{reg_A[32]}},reg_A[32:42]};
result[48:63]<={{5{reg_A[48]}},reg_A[48:58]};
result[64:79]<={{5{reg_A[64]}},reg_A[64:74]};
result[80:95]<={{5{reg_A[80]}},reg_A[80:90]};
result[96:111]<={{5{reg_A[96]}},reg_A[96:106]};
result[112:127]<={{5{reg_A[112]}},reg_A[112:122]};
end
4'd6:
begin
result[0:15]<={{6{reg_A[0]}},reg_A[0:9]};
result[16:31]<={{6{reg_A[16]}},reg_A[16:25]};
result[32:47]<={{6{reg_A[32]}},reg_A[32:41]};
result[48:63]<={{6{reg_A[48]}},reg_A[48:57]};
result[64:79]<={{6{reg_A[64]}},reg_A[64:73]};
result[80:95]<={{6{reg_A[80]}},reg_A[80:89]};
result[96:111]<={{6{reg_A[96]}},reg_A[96:105]};
result[112:127]<={{6{reg_A[112]}},reg_A[112:121]};
end
4'd7:
begin
result[0:15]<={{7{reg_A[0]}},reg_A[0:8]};
result[16:31]<={{7{reg_A[16]}},reg_A[16:24]};
result[32:47]<={{7{reg_A[32]}},reg_A[32:40]};
result[48:63]<={{7{reg_A[48]}},reg_A[48:56]};
result[64:79]<={{7{reg_A[64]}},reg_A[64:72]};
result[80:95]<={{7{reg_A[80]}},reg_A[80:88]};
result[96:111]<={{7{reg_A[96]}},reg_A[96:104]};
result[112:127]<={{7{reg_A[112]}},reg_A[112:120]};
end
4'd8:
begin
result[0:15]<={{8{reg_A[0]}},reg_A[0:7]};
result[16:31]<={{8{reg_A[16]}},reg_A[16:23]};
result[32:47]<={{8{reg_A[32]}},reg_A[32:39]};
result[48:63]<={{8{reg_A[48]}},reg_A[48:55]};
result[64:79]<={{8{reg_A[64]}},reg_A[64:71]};
result[80:95]<={{8{reg_A[80]}},reg_A[80:87]};
result[96:111]<={{8{reg_A[96]}},reg_A[96:103]};
result[112:127]<={{8{reg_A[112]}},reg_A[112:119]};
end
4'd9:
begin
result[0:15]<={{9{reg_A[0]}},reg_A[0:6]};
result[16:31]<={{9{reg_A[16]}},reg_A[16:22]};
result[32:47]<={{9{reg_A[32]}},reg_A[32:38]};
result[48:63]<={{9{reg_A[48]}},reg_A[48:54]};
result[64:79]<={{9{reg_A[64]}},reg_A[64:70]};
result[80:95]<={{9{reg_A[80]}},reg_A[80:86]};
result[96:111]<={{9{reg_A[96]}},reg_A[96:102]};
result[112:127]<={{9{reg_A[112]}},reg_A[112:118]};
end
4'd10:
begin
result[0:15]<={{10{reg_A[0]}},reg_A[0:5]};
result[16:31]<={{10{reg_A[16]}},reg_A[16:21]};
result[32:47]<={{10{reg_A[32]}},reg_A[32:37]};
result[48:63]<={{10{reg_A[48]}},reg_A[48:53]};
result[64:79]<={{10{reg_A[64]}},reg_A[64:69]};
result[80:95]<={{10{reg_A[80]}},reg_A[80:85]};
result[96:111]<={{10{reg_A[96]}},reg_A[96:101]};
result[112:127]<={{10{reg_A[112]}},reg_A[112:117]};
end
4'd11:
begin
result[0:15]<={{11{reg_A[0]}},reg_A[0:4]};
result[16:31]<={{11{reg_A[16]}},reg_A[16:20]};
result[32:47]<={{11{reg_A[32]}},reg_A[32:36]};
result[48:63]<={{11{reg_A[48]}},reg_A[48:52]};
result[64:79]<={{11{reg_A[64]}},reg_A[64:68]};
result[80:95]<={{11{reg_A[80]}},reg_A[80:84]};
result[96:111]<={{11{reg_A[96]}},reg_A[96:100]};
result[112:127]<={{11{reg_A[112]}},reg_A[112:116]};
end
4'd12:
begin
result[0:15]<={{12{reg_A[0]}},reg_A[0:3]};
result[16:31]<={{12{reg_A[16]}},reg_A[16:19]};
result[32:47]<={{12{reg_A[32]}},reg_A[32:35]};
result[48:63]<={{12{reg_A[48]}},reg_A[48:51]};
result[64:79]<={{12{reg_A[64]}},reg_A[64:67]};
result[80:95]<={{12{reg_A[80]}},reg_A[80:83]};
result[96:111]<={{12{reg_A[96]}},reg_A[96:99]};
result[112:127]<={{12{reg_A[112]}},reg_A[112:115]};
end
4'd13:
begin
result[0:15]<={{13{reg_A[0]}},reg_A[0:2]};
result[16:31]<={{13{reg_A[16]}},reg_A[16:18]};
result[32:47]<={{13{reg_A[32]}},reg_A[32:34]};
result[48:63]<={{13{reg_A[48]}},reg_A[48:50]};
result[64:79]<={{13{reg_A[64]}},reg_A[64:66]};
result[80:95]<={{13{reg_A[80]}},reg_A[80:82]};
result[96:111]<={{13{reg_A[96]}},reg_A[96:98]};
result[112:127]<={{13{reg_A[112]}},reg_A[112:114]};
end
4'd14:
begin
result[0:15]<={{14{reg_A[0]}},reg_A[0:1]};
result[16:31]<={{14{reg_A[16]}},reg_A[16:17]};
result[32:47]<={{14{reg_A[32]}},reg_A[32:33]};
result[48:63]<={{14{reg_A[48]}},reg_A[48:49]};
result[64:79]<={{14{reg_A[64]}},reg_A[64:65]};
result[80:95]<={{14{reg_A[80]}},reg_A[80:81]};
result[96:111]<={{14{reg_A[96]}},reg_A[96:97]};
result[112:127]<={{14{reg_A[112]}},reg_A[112:113]};
end
4'd15:
begin
result[0:15]<={{15{reg_A[0]}},reg_A[0]};
result[16:31]<={{15{reg_A[16]}},reg_A[16]};
result[32:47]<={{15{reg_A[32]}},reg_A[32]};
result[48:63]<={{15{reg_A[48]}},reg_A[48]};
result[64:79]<={{15{reg_A[64]}},reg_A[64]};
result[80:95]<={{15{reg_A[80]}},reg_A[80]};
result[96:111]<={{15{reg_A[96]}},reg_A[96]};
result[112:127]<={{15{reg_A[112]}},reg_A[112]};
end
default:
begin
result<=128'b0;
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={{reg_A[0]},reg_A[0:30]};
result[32:63]<={{reg_A[32]},reg_A[32:62]};
result[64:95]<={{reg_A[64]},reg_A[64:94]};
result[96:127]<={{reg_A[96]},reg_A[96:126]};
end
5'd2:
begin
result[0:31]<={{2{reg_A[0]}},reg_A[0:29]};
result[32:63]<={{2{reg_A[32]}},reg_A[32:61]};
result[64:95]<={{2{reg_A[64]}},reg_A[64:93]};
result[96:127]<={{2{reg_A[96]}},reg_A[96:125]};
end
5'd3:
begin
result[0:31]<={{3{reg_A[0]}},reg_A[0:28]};
result[32:63]<={{3{reg_A[32]}},reg_A[32:60]};
result[64:95]<={{3{reg_A[64]}},reg_A[64:92]};
result[96:127]<={{3{reg_A[96]}},reg_A[96:124]};
end
5'd4:
begin
result[0:31]<={{4{reg_A[0]}},reg_A[0:27]};
result[32:63]<={{4{reg_A[32]}},reg_A[32:59]};
result[64:95]<={{4{reg_A[64]}},reg_A[64:91]};
result[96:127]<={{4{reg_A[96]}},reg_A[96:123]};
end
5'd5:
begin
result[0:31]<={{5{reg_A[0]}},reg_A[0:26]};
result[32:63]<={{5{reg_A[32]}},reg_A[32:58]};
result[64:95]<={{5{reg_A[64]}},reg_A[64:90]};
result[96:127]<={{5{reg_A[96]}},reg_A[96:122]};
end
5'd6:
begin
result[0:31]<={{6{reg_A[0]}},reg_A[0:25]};
result[32:63]<={{6{reg_A[32]}},reg_A[32:57]};
result[64:95]<={{6{reg_A[64]}},reg_A[64:89]};
result[96:127]<={{6{reg_A[96]}},reg_A[96:121]};
end
5'd7:
begin
result[0:31]<={{7{reg_A[0]}},reg_A[0:24]};
result[32:63]<={{7{reg_A[32]}},reg_A[32:56]};
result[64:95]<={{7{reg_A[64]}},reg_A[64:88]};
result[96:127]<={{7{reg_A[96]}},reg_A[96:120]};
end
5'd8:
begin
result[0:31]<={{8{reg_A[0]}},reg_A[0:23]};
result[32:63]<={{8{reg_A[32]}},reg_A[32:55]};
result[64:95]<={{8{reg_A[64]}},reg_A[64:87]};
result[96:127]<={{8{reg_A[96]}},reg_A[96:119]};
end
5'd9:
begin
result[0:31]<={{9{reg_A[0]}},reg_A[0:22]};
result[32:63]<={{9{reg_A[32]}},reg_A[32:54]};
result[64:95]<={{9{reg_A[64]}},reg_A[64:86]};
result[96:127]<={{9{reg_A[96]}},reg_A[96:118]};
end
5'd10:
begin
result[0:31]<={{10{reg_A[0]}},reg_A[0:21]};
result[32:63]<={{10{reg_A[32]}},reg_A[32:53]};
result[64:95]<={{10{reg_A[64]}},reg_A[64:85]};
result[96:127]<={{10{reg_A[96]}},reg_A[96:117]};
end
5'd11:
begin
result[0:31]<={{11{reg_A[0]}},reg_A[0:20]};
result[32:63]<={{11{reg_A[32]}},reg_A[32:52]};
result[64:95]<={{11{reg_A[64]}},reg_A[64:84]};
result[96:127]<={{11{reg_A[96]}},reg_A[96:116]};
end
5'd12:
begin
result[0:31]<={{12{reg_A[0]}},reg_A[0:19]};
result[32:63]<={{12{reg_A[32]}},reg_A[32:51]};
result[64:95]<={{12{reg_A[64]}},reg_A[64:83]};
result[96:127]<={{12{reg_A[96]}},reg_A[96:115]};
end
5'd13:
begin
result[0:31]<={{13{reg_A[0]}},reg_A[0:18]};
result[32:63]<={{13{reg_A[32]}},reg_A[32:50]};
result[64:95]<={{13{reg_A[64]}},reg_A[64:82]};
result[96:127]<={{13{reg_A[96]}},reg_A[96:114]};
end
5'd14:
begin
result[0:31]<={{14{reg_A[0]}},reg_A[0:17]};
result[32:63]<={{14{reg_A[32]}},reg_A[32:49]};
result[64:95]<={{14{reg_A[64]}},reg_A[64:81]};
result[96:127]<={{14{reg_A[96]}},reg_A[96:113]};
end
5'd15:
begin
result[0:31]<={{15{reg_A[0]}},reg_A[0:16]};
result[32:63]<={{15{reg_A[32]}},reg_A[32:48]};
result[64:95]<={{15{reg_A[64]}},reg_A[64:80]};
result[96:127]<={{15{reg_A[96]}},reg_A[96:112]};
end
5'd16:
begin
result[0:31]<={{16{reg_A[0]}},reg_A[0:15]};
result[32:63]<={{16{reg_A[32]}},reg_A[32:47]};
result[64:95]<={{16{reg_A[64]}},reg_A[64:79]};
result[96:127]<={{16{reg_A[96]}},reg_A[96:111]};
end
5'd17:
begin
result[0:31]<={{17{reg_A[0]}},reg_A[0:14]};
result[32:63]<={{17{reg_A[32]}},reg_A[32:46]};
result[64:95]<={{17{reg_A[64]}},reg_A[64:78]};
result[96:127]<={{17{reg_A[96]}},reg_A[96:110]};
end
5'd18:
begin
result[0:31]<={{18{reg_A[0]}},reg_A[0:13]};
result[32:63]<={{18{reg_A[32]}},reg_A[32:45]};
result[64:95]<={{18{reg_A[64]}},reg_A[64:77]};
result[96:127]<={{18{reg_A[96]}},reg_A[96:109]};
end
5'd19:
begin
result[0:31]<={{19{reg_A[0]}},reg_A[0:12]};
result[32:63]<={{19{reg_A[32]}},reg_A[32:44]};
result[64:95]<={{19{reg_A[64]}},reg_A[64:76]};
result[96:127]<={{19{reg_A[96]}},reg_A[96:108]};
end
5'd20:
begin
result[0:31]<={{20{reg_A[0]}},reg_A[0:11]};
result[32:63]<={{20{reg_A[32]}},reg_A[32:43]};
result[64:95]<={{20{reg_A[64]}},reg_A[64:75]};
result[96:127]<={{20{reg_A[96]}},reg_A[96:107]};
end
5'd21:
begin
result[0:31]<={{21{reg_A[0]}},reg_A[0:10]};
result[32:63]<={{21{reg_A[32]}},reg_A[32:42]};
result[64:95]<={{21{reg_A[64]}},reg_A[64:74]};
result[96:127]<={{21{reg_A[96]}},reg_A[96:106]};
end
5'd22:
begin
result[0:31]<={{22{reg_A[0]}},reg_A[0:9]};
result[32:63]<={{22{reg_A[32]}},reg_A[32:41]};
result[64:95]<={{22{reg_A[64]}},reg_A[64:73]};
result[96:127]<={{22{reg_A[96]}},reg_A[96:105]};
end
5'd23:
begin
result[0:31]<={{23{reg_A[0]}},reg_A[0:8]};
result[32:63]<={{23{reg_A[32]}},reg_A[32:40]};
result[64:95]<={{23{reg_A[64]}},reg_A[64:72]};
result[96:127]<={{23{reg_A[96]}},reg_A[96:104]};
end
5'd24:
begin
result[0:31]<={{24{reg_A[0]}},reg_A[0:7]};
result[32:63]<={{24{reg_A[32]}},reg_A[32:39]};
result[64:95]<={{24{reg_A[64]}},reg_A[64:71]};
result[96:127]<={{24{reg_A[96]}},reg_A[96:103]};
end
5'd25:
begin
result[0:31]<={{25{reg_A[0]}},reg_A[0:6]};
result[32:63]<={{25{reg_A[32]}},reg_A[32:38]};
result[64:95]<={{25{reg_A[64]}},reg_A[64:70]};
result[96:127]<={{25{reg_A[96]}},reg_A[96:102]};
end
5'd26:
begin
result[0:31]<={{26{reg_A[0]}},reg_A[0:5]};
result[32:63]<={{26{reg_A[32]}},reg_A[32:37]};
result[64:95]<={{26{reg_A[64]}},reg_A[64:69]};
result[96:127]<={{26{reg_A[96]}},reg_A[96:101]};
end
5'd27:
begin
result[0:31]<={{27{reg_A[0]}},reg_A[0:4]};
result[32:63]<={{27{reg_A[32]}},reg_A[32:36]};
result[64:95]<={{27{reg_A[64]}},reg_A[64:68]};
result[96:127]<={{27{reg_A[96]}},reg_A[96:100]};
end
5'd28:
begin
result[0:31]<={{28{reg_A[0]}},reg_A[0:3]};
result[32:63]<={{28{reg_A[32]}},reg_A[32:35]};
result[64:95]<={{28{reg_A[64]}},reg_A[64:67]};
result[96:127]<={{28{reg_A[96]}},reg_A[96:99]};
end
5'd29:
begin
result[0:31]<={{29{reg_A[0]}},reg_A[0:2]};
result[32:63]<={{29{reg_A[32]}},reg_A[32:34]};
result[64:95]<={{29{reg_A[64]}},reg_A[64:66]};
result[96:127]<={{29{reg_A[96]}},reg_A[96:98]};
end
5'd30:
begin
result[0:31]<={{30{reg_A[0]}},reg_A[0:1]};
result[32:63]<={{30{reg_A[32]}},reg_A[32:33]};
result[64:95]<={{30{reg_A[64]}},reg_A[64:65]};
result[96:127]<={{30{reg_A[96]}},reg_A[96:97]};
end
5'd31:
begin
result[0:31]<={{31{reg_A[0]}},reg_A[0]};
result[32:63]<={{31{reg_A[32]}},reg_A[32]};
result[64:95]<={{31{reg_A[64]}},reg_A[64]};
result[96:127]<={{31{reg_A[96]}},reg_A[96]};
end
default:
begin
result<=128'b0;
end
endcase
end
default:
begin
result<=128'b0;
end
endcase
end
// ==============================================================
// SRA instruction
`aluwsra:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[5:7]) // byte 0
3'd0:
result[0:7]<=reg_A[0:7];
3'd1:
result[0:7]<={{1{reg_A[0]}},reg_A[0:6]};
3'd2:
result[0:7]<={{2{reg_A[0]}},reg_A[0:5]};
3'd3:
result[0:7]<={{3{reg_A[0]}},reg_A[0:4]};
3'd4:
result[0:7]<={{4{reg_A[0]}},reg_A[0:3]};
3'd5:
result[0:7]<={{5{reg_A[0]}},reg_A[0:2]};
3'd6:
result[0:7]<={{6{reg_A[0]}},reg_A[0:1]};
3'd7:
result[0:7]<={{7{reg_A[0]}},reg_A[0]};
default:
result[0:7]<=8'b0;
endcase
case(reg_B[13:15]) // byte 1
3'd0:
result[8:15]<=reg_A[8:15];
3'd1:
result[8:15]<={{1{reg_A[8]}},reg_A[8:14]};
3'd2:
result[8:15]<={{2{reg_A[8]}},reg_A[8:13]};
3'd3:
result[8:15]<={{3{reg_A[8]}},reg_A[8:12]};
3'd4:
result[8:15]<={{4{reg_A[8]}},reg_A[8:11]};
3'd5:
result[8:15]<={{5{reg_A[8]}},reg_A[8:10]};
3'd6:
result[8:15]<={{6{reg_A[8]}},reg_A[8:9]};
3'd7:
result[8:15]<={{7{reg_A[8]}},reg_A[8]};
default:
result[8:15]<=8'b0;
endcase
case(reg_B[21:23]) // byte 2
3'd0:
result[16:23]<=reg_A[16:23];
3'd1:
result[16:23]<={{1{reg_A[16]}},reg_A[16:22]};
3'd2:
result[16:23]<={{2{reg_A[16]}},reg_A[16:21]};
3'd3:
result[16:23]<={{3{reg_A[16]}},reg_A[16:20]};
3'd4:
result[16:23]<={{4{reg_A[16]}},reg_A[16:19]};
3'd5:
result[16:23]<={{5{reg_A[16]}},reg_A[16:18]};
3'd6:
result[16:23]<={{6{reg_A[16]}},reg_A[16:17]};
3'd7:
result[16:23]<={{7{reg_A[16]}},reg_A[16]};
default:
result[16:23]<=8'b0;
endcase
case(reg_B[29:31]) // byte 3
3'd0:
result[24:31]<=reg_A[24:31];
3'd1:
result[24:31]<={{1{reg_A[24]}},reg_A[24:30]};
3'd2:
result[24:31]<={{2{reg_A[24]}},reg_A[24:29]};
3'd3:
result[24:31]<={{3{reg_A[24]}},reg_A[24:28]};
3'd4:
result[24:31]<={{4{reg_A[24]}},reg_A[24:27]};
3'd5:
result[24:31]<={{5{reg_A[24]}},reg_A[24:26]};
3'd6:
result[24:31]<={{6{reg_A[24]}},reg_A[24:25]};
3'd7:
result[24:31]<={{7{reg_A[24]}},reg_A[24]};
default:
result[24:31]<=8'b0;
endcase
case(reg_B[37:39]) // byte 4
3'd0:
result[32:39]<=reg_A[32:39];
3'd1:
result[32:39]<={{1{reg_A[32]}},reg_A[32:38]};
3'd2:
result[32:39]<={{2{reg_A[32]}},reg_A[32:37]};
3'd3:
result[32:39]<={{3{reg_A[32]}},reg_A[32:36]};
3'd4:
result[32:39]<={{4{reg_A[32]}},reg_A[32:35]};
3'd5:
result[32:39]<={{5{reg_A[32]}},reg_A[32:34]};
3'd6:
result[32:39]<={{6{reg_A[32]}},reg_A[32:33]};
3'd7:
result[32:39]<={{7{reg_A[32]}},reg_A[32]};
default:
result[32:39]<=8'b0;
endcase
case(reg_B[45:47]) // byte 5
3'd0:
result[40:47]<=reg_A[40:47];
3'd1:
result[40:47]<={{1{reg_A[40]}},reg_A[40:46]};
3'd2:
result[40:47]<={{2{reg_A[40]}},reg_A[40:45]};
3'd3:
result[40:47]<={{3{reg_A[40]}},reg_A[40:44]};
3'd4:
result[40:47]<={{4{reg_A[40]}},reg_A[40:43]};
3'd5:
result[40:47]<={{5{reg_A[40]}},reg_A[40:42]};
3'd6:
result[40:47]<={{6{reg_A[40]}},reg_A[40:41]};
3'd7:
result[40:47]<={{7{reg_A[40]}},reg_A[40]};
default:
result[40:47]<=8'b0;
endcase
case(reg_B[53:55]) // byte 6
3'd0:
result[48:55]<=reg_A[48:55];
3'd1:
result[48:55]<={{1{reg_A[48]}},reg_A[48:54]};
3'd2:
result[48:55]<={{2{reg_A[48]}},reg_A[48:53]};
3'd3:
result[48:55]<={{3{reg_A[48]}},reg_A[48:52]};
3'd4:
result[48:55]<={{4{reg_A[48]}},reg_A[48:51]};
3'd5:
result[48:55]<={{5{reg_A[48]}},reg_A[48:50]};
3'd6:
result[48:55]<={{6{reg_A[48]}},reg_A[48:49]};
3'd7:
result[48:55]<={{7{reg_A[48]}},reg_A[48]};
default:
result[48:55]<=8'b0;
endcase
case(reg_B[61:63]) // byte 7
3'd0:
result[56:63]<=reg_A[56:63];
3'd1:
result[56:63]<={{1{reg_A[56]}},reg_A[56:62]};
3'd2:
result[56:63]<={{2{reg_A[56]}},reg_A[56:61]};
3'd3:
result[56:63]<={{3{reg_A[56]}},reg_A[56:60]};
3'd4:
result[56:63]<={{4{reg_A[56]}},reg_A[56:59]};
3'd5:
result[56:63]<={{5{reg_A[56]}},reg_A[56:58]};
3'd6:
result[56:63]<={{6{reg_A[56]}},reg_A[56:57]};
3'd7:
result[56:63]<={{7{reg_A[56]}},reg_A[56]};
default:
result[56:63]<=8'b0;
endcase
case(reg_B[69:71]) // byte 8
3'd0:
result[64:71]<=reg_A[64:71];
3'd1:
result[64:71]<={{1{reg_A[64]}},reg_A[64:70]};
3'd2:
result[64:71]<={{2{reg_A[64]}},reg_A[64:69]};
3'd3:
result[64:71]<={{3{reg_A[64]}},reg_A[64:68]};
3'd4:
result[64:71]<={{4{reg_A[64]}},reg_A[64:67]};
3'd5:
result[64:71]<={{5{reg_A[64]}},reg_A[64:66]};
3'd6:
result[64:71]<={{6{reg_A[64]}},reg_A[64:65]};
3'd7:
result[64:71]<={{7{reg_A[64]}},reg_A[64]};
default:
result[64:71]<=8'b0;
endcase
case(reg_B[77:79]) // byte 9
3'd0:
result[72:79]<=reg_A[72:79];
3'd1:
result[72:79]<={{1{reg_A[72]}},reg_A[72:78]};
3'd2:
result[72:79]<={{2{reg_A[72]}},reg_A[72:77]};
3'd3:
result[72:79]<={{3{reg_A[72]}},reg_A[72:76]};
3'd4:
result[72:79]<={{4{reg_A[72]}},reg_A[72:75]};
3'd5:
result[72:79]<={{5{reg_A[72]}},reg_A[72:74]};
3'd6:
result[72:79]<={{6{reg_A[72]}},reg_A[72:73]};
3'd7:
result[72:79]<={{7{reg_A[72]}},reg_A[72]};
default:
result[72:79]<=8'b0;
endcase
case(reg_B[85:87]) // byte 10
3'd0:
result[80:87]<=reg_A[80:87];
3'd1:
result[80:87]<={{1{reg_A[80]}},reg_A[80:86]};
3'd2:
result[80:87]<={{2{reg_A[80]}},reg_A[80:85]};
3'd3:
result[80:87]<={{3{reg_A[80]}},reg_A[80:84]};
3'd4:
result[80:87]<={{4{reg_A[80]}},reg_A[80:83]};
3'd5:
result[80:87]<={{5{reg_A[80]}},reg_A[80:82]};
3'd6:
result[80:87]<={{6{reg_A[80]}},reg_A[80:81]};
3'd7:
result[80:87]<={{7{reg_A[80]}},reg_A[80]};
default:
result[80:87]<=8'b0;
endcase
case(reg_B[93:95]) // byte 11
3'd0:
result[88:95]<=reg_A[88:95];
3'd1:
result[88:95]<={{1{reg_A[88]}},reg_A[88:94]};
3'd2:
result[88:95]<={{2{reg_A[88]}},reg_A[88:93]};
3'd3:
result[88:95]<={{3{reg_A[88]}},reg_A[88:92]};
3'd4:
result[88:95]<={{4{reg_A[88]}},reg_A[88:91]};
3'd5:
result[88:95]<={{5{reg_A[88]}},reg_A[88:90]};
3'd6:
result[88:95]<={{6{reg_A[88]}},reg_A[88:89]};
3'd7:
result[88:95]<={{7{reg_A[88]}},reg_A[88]};
default:
result[88:95]<=8'b0;
endcase
case(reg_B[101:103]) // byte 12
3'd0:
result[96:103]<=reg_A[96:103];
3'd1:
result[96:103]<={{1{reg_A[96]}},reg_A[96:102]};
3'd2:
result[96:103]<={{2{reg_A[96]}},reg_A[96:101]};
3'd3:
result[96:103]<={{3{reg_A[96]}},reg_A[96:100]};
3'd4:
result[96:103]<={{4{reg_A[96]}},reg_A[96:99]};
3'd5:
result[96:103]<={{5{reg_A[96]}},reg_A[96:98]};
3'd6:
result[96:103]<={{6{reg_A[96]}},reg_A[96:97]};
3'd7:
result[96:103]<={{7{reg_A[96]}},reg_A[96]};
default:
result[96:103]<=8'b0;
endcase
case(reg_B[109:111]) // byte 13
3'd0:
result[104:111]<=reg_A[104:111];
3'd1:
result[104:111]<={{1{reg_A[104]}},reg_A[104:110]};
3'd2:
result[104:111]<={{2{reg_A[104]}},reg_A[104:109]};
3'd3:
result[104:111]<={{3{reg_A[104]}},reg_A[104:108]};
3'd4:
result[104:111]<={{4{reg_A[104]}},reg_A[104:107]};
3'd5:
result[104:111]<={{5{reg_A[104]}},reg_A[104:106]};
3'd6:
result[104:111]<={{6{reg_A[104]}},reg_A[104:105]};
3'd7:
result[104:111]<={{7{reg_A[104]}},reg_A[104]};
default:
result[104:111]<=8'b0;
endcase
case(reg_B[117:119]) // byte 14
3'd0:
result[112:119]<=reg_A[112:119];
3'd1:
result[112:119]<={{1{reg_A[112]}},reg_A[112:118]};
3'd2:
result[112:119]<={{2{reg_A[112]}},reg_A[112:117]};
3'd3:
result[112:119]<={{3{reg_A[112]}},reg_A[112:116]};
3'd4:
result[112:119]<={{4{reg_A[112]}},reg_A[112:115]};
3'd5:
result[112:119]<={{5{reg_A[112]}},reg_A[112:114]};
3'd6:
result[112:119]<={{6{reg_A[112]}},reg_A[112:113]};
3'd7:
result[112:119]<={{7{reg_A[112]}},reg_A[112]};
default:
result[112:119]<=8'b0;
endcase
case(reg_B[125:127]) // byte 15
3'd0:
result[120:127]<=reg_A[120:127];
3'd1:
result[120:127]<={{1{reg_A[120]}},reg_A[120:126]};
3'd2:
result[120:127]<={{2{reg_A[120]}},reg_A[120:125]};
3'd3:
result[120:127]<={{3{reg_A[120]}},reg_A[120:124]};
3'd4:
result[120:127]<={{4{reg_A[120]}},reg_A[120:123]};
3'd5:
result[120:127]<={{5{reg_A[120]}},reg_A[120:122]};
3'd6:
result[120:127]<={{6{reg_A[120]}},reg_A[120:121]};
3'd7:
result[120:127]<={{7{reg_A[120]}},reg_A[120]};
default:
result[120:127]<=8'b0;
endcase
end
`w16:
begin
case(reg_B[12:15]) // word0
4'd0:
result[0:15]<=reg_A[0:15];
4'd1:
result[0:15]<={{1{reg_A[0]}},reg_A[0:14]};
4'd2:
result[0:15]<={{2{reg_A[0]}},reg_A[0:13]};
4'd3:
result[0:15]<={{3{reg_A[0]}},reg_A[0:12]};
4'd4:
result[0:15]<={{4{reg_A[0]}},reg_A[0:11]};
4'd5:
result[0:15]<={{5{reg_A[0]}},reg_A[0:10]};
4'd6:
result[0:15]<={{6{reg_A[0]}},reg_A[0:9]};
4'd7:
result[0:15]<={{7{reg_A[0]}},reg_A[0:8]};
4'd8:
result[0:15]<={{8{reg_A[0]}},reg_A[0:7]};
4'd9:
result[0:15]<={{9{reg_A[0]}},reg_A[0:6]};
4'd10:
result[0:15]<={{10{reg_A[0]}},reg_A[0:5]};
4'd11:
result[0:15]<={{11{reg_A[0]}},reg_A[0:4]};
4'd12:
result[0:15]<={{12{reg_A[0]}},reg_A[0:3]};
4'd13:
result[0:15]<={{13{reg_A[0]}},reg_A[0:2]};
4'd14:
result[0:15]<={{14{reg_A[0]}},reg_A[0:1]};
4'd15:
result[0:15]<={{15{reg_A[0]}},reg_A[0]};
default:
result[0:15]<=16'b0;
endcase
case(reg_B[28:31]) //word1
4'd0:
result[16:31]<=reg_A[16:31];
4'd1:
result[16:31]<={{1{reg_A[16]}},reg_A[16:30]};
4'd2:
result[16:31]<={{2{reg_A[16]}},reg_A[16:29]};
4'd3:
result[16:31]<={{3{reg_A[16]}},reg_A[16:28]};
4'd4:
result[16:31]<={{4{reg_A[16]}},reg_A[16:27]};
4'd5:
result[16:31]<={{5{reg_A[16]}},reg_A[16:26]};
4'd6:
result[16:31]<={{6{reg_A[16]}},reg_A[16:25]};
4'd7:
result[16:31]<={{7{reg_A[16]}},reg_A[16:24]};
4'd8:
result[16:31]<={{8{reg_A[16]}},reg_A[16:23]};
4'd9:
result[16:31]<={{9{reg_A[16]}},reg_A[16:22]};
4'd10:
result[16:31]<={{10{reg_A[16]}},reg_A[16:21]};
4'd11:
result[16:31]<={{11{reg_A[16]}},reg_A[16:20]};
4'd12:
result[16:31]<={{12{reg_A[16]}},reg_A[16:19]};
4'd13:
result[16:31]<={{13{reg_A[16]}},reg_A[16:18]};
4'd14:
result[16:31]<={{14{reg_A[16]}},reg_A[16:17]};
4'd15:
result[16:31]<={{15{reg_A[16]}},reg_A[16]};
default:
result[16:31]<=16'b0;
endcase
case(reg_B[44:47]) // word2
4'd0:
result[32:47]<=reg_A[32:47];
4'd1:
result[32:47]<={{1{reg_A[32]}},reg_A[32:46]};
4'd2:
result[32:47]<={{2{reg_A[32]}},reg_A[32:45]};
4'd3:
result[32:47]<={{3{reg_A[32]}},reg_A[32:44]};
4'd4:
result[32:47]<={{4{reg_A[32]}},reg_A[32:43]};
4'd5:
result[32:47]<={{5{reg_A[32]}},reg_A[32:42]};
4'd6:
result[32:47]<={{6{reg_A[32]}},reg_A[32:41]};
4'd7:
result[32:47]<={{7{reg_A[32]}},reg_A[32:40]};
4'd8:
result[32:47]<={{8{reg_A[32]}},reg_A[32:39]};
4'd9:
result[32:47]<={{9{reg_A[32]}},reg_A[32:38]};
4'd10:
result[32:47]<={{10{reg_A[32]}},reg_A[32:37]};
4'd11:
result[32:47]<={{11{reg_A[32]}},reg_A[32:36]};
4'd12:
result[32:47]<={{12{reg_A[32]}},reg_A[32:35]};
4'd13:
result[32:47]<={{13{reg_A[32]}},reg_A[32:34]};
4'd14:
result[32:47]<={{14{reg_A[32]}},reg_A[32:33]};
4'd15:
result[32:47]<={{15{reg_A[32]}},reg_A[32]};
endcase
case(reg_B[60:63]) // word3
4'd0:
result[48:63]<=reg_A[48:63];
4'd1:
result[48:63]<={{1{reg_A[48]}},reg_A[48:62]};
4'd2:
result[48:63]<={{2{reg_A[48]}},reg_A[48:61]};
4'd3:
result[48:63]<={{3{reg_A[48]}},reg_A[48:60]};
4'd4:
result[48:63]<={{4{reg_A[48]}},reg_A[48:59]};
4'd5:
result[48:63]<={{5{reg_A[48]}},reg_A[48:58]};
4'd6:
result[48:63]<={{6{reg_A[48]}},reg_A[48:57]};
4'd7:
result[48:63]<={{7{reg_A[48]}},reg_A[48:56]};
4'd8:
result[48:63]<={{8{reg_A[48]}},reg_A[48:55]};
4'd9:
result[48:63]<={{9{reg_A[48]}},reg_A[48:54]};
4'd10:
result[48:63]<={{10{reg_A[48]}},reg_A[48:53]};
4'd11:
result[48:63]<={{11{reg_A[48]}},reg_A[48:52]};
4'd12:
result[48:63]<={{12{reg_A[48]}},reg_A[48:51]};
4'd13:
result[48:63]<={{13{reg_A[48]}},reg_A[48:50]};
4'd14:
result[48:63]<={{14{reg_A[48]}},reg_A[48:49]};
4'd15:
result[48:63]<={{15{reg_A[48]}},reg_A[48]};
default:
result[48:63]<=16'b0;
endcase
case(reg_B[76:79]) // word4
4'd0:
result[64:79]<=reg_A[64:79];
4'd1:
result[64:79]<={{1{reg_A[64]}},reg_A[64:78]};
4'd2:
result[64:79]<={{2{reg_A[64]}},reg_A[64:77]};
4'd3:
result[64:79]<={{3{reg_A[64]}},reg_A[64:76]};
4'd4:
result[64:79]<={{4{reg_A[64]}},reg_A[64:75]};
4'd5:
result[64:79]<={{5{reg_A[64]}},reg_A[64:74]};
4'd6:
result[64:79]<={{6{reg_A[64]}},reg_A[64:73]};
4'd7:
result[64:79]<={{7{reg_A[64]}},reg_A[64:72]};
4'd8:
result[64:79]<={{8{reg_A[64]}},reg_A[64:71]};
4'd9:
result[64:79]<={{9{reg_A[64]}},reg_A[64:70]};
4'd10:
result[64:79]<={{10{reg_A[64]}},reg_A[64:69]};
4'd11:
result[64:79]<={{11{reg_A[64]}},reg_A[64:68]};
4'd12:
result[64:79]<={{12{reg_A[64]}},reg_A[64:67]};
4'd13:
result[64:79]<={{13{reg_A[64]}},reg_A[64:66]};
4'd14:
result[64:79]<={{14{reg_A[64]}},reg_A[64:65]};
4'd15:
result[64:79]<={{15{reg_A[64]}},reg_A[64]};
default:
result[64:79]<=16'b0;
endcase
case(reg_B[92:95]) // word5
4'd0:
result[80:95]<=reg_A[80:95];
4'd1:
result[80:95]<={{1{reg_A[80]}},reg_A[80:94]};
4'd2:
result[80:95]<={{2{reg_A[80]}},reg_A[80:93]};
4'd3:
result[80:95]<={{3{reg_A[80]}},reg_A[80:92]};
4'd4:
result[80:95]<={{4{reg_A[80]}},reg_A[80:91]};
4'd5:
result[80:95]<={{5{reg_A[80]}},reg_A[80:90]};
4'd6:
result[80:95]<={{6{reg_A[80]}},reg_A[80:89]};
4'd7:
result[80:95]<={{7{reg_A[80]}},reg_A[80:88]};
4'd8:
result[80:95]<={{8{reg_A[80]}},reg_A[80:87]};
4'd9:
result[80:95]<={{9{reg_A[80]}},reg_A[80:86]};
4'd10:
result[80:95]<={{10{reg_A[80]}},reg_A[80:85]};
4'd11:
result[80:95]<={{11{reg_A[80]}},reg_A[80:84]};
4'd12:
result[80:95]<={{12{reg_A[80]}},reg_A[80:83]};
4'd13:
result[80:95]<={{13{reg_A[80]}},reg_A[80:82]};
4'd14:
result[80:95]<={{14{reg_A[80]}},reg_A[80:81]};
4'd15:
result[80:95]<={{15{reg_A[80]}},reg_A[80]};
default:
result[80:95]<=16'b0;
endcase
case(reg_B[92:111]) // word6
4'd0:
result[96:111]<=reg_A[96:111];
4'd1:
result[96:111]<={{1{reg_A[96]}},reg_A[96:110]};
4'd2:
result[96:111]<={{2{reg_A[96]}},reg_A[96:109]};
4'd3:
result[96:111]<={{3{reg_A[96]}},reg_A[96:108]};
4'd4:
result[96:111]<={{4{reg_A[96]}},reg_A[96:107]};
4'd5:
result[96:111]<={{5{reg_A[96]}},reg_A[96:106]};
4'd6:
result[96:111]<={{6{reg_A[96]}},reg_A[96:105]};
4'd7:
result[96:111]<={{7{reg_A[96]}},reg_A[96:104]};
4'd8:
result[96:111]<={{8{reg_A[96]}},reg_A[96:103]};
4'd9:
result[96:111]<={{9{reg_A[96]}},reg_A[96:102]};
4'd10:
result[96:111]<={{10{reg_A[96]}},reg_A[96:101]};
4'd11:
result[96:111]<={{11{reg_A[96]}},reg_A[96:100]};
4'd12:
result[96:111]<={{12{reg_A[96]}},reg_A[96:99]};
4'd13:
result[96:111]<={{13{reg_A[96]}},reg_A[96:98]};
4'd14:
result[96:111]<={{14{reg_A[96]}},reg_A[96:97]};
4'd15:
result[96:111]<={{15{reg_A[96]}},reg_A[96]};
default:
result[96:111]<=16'b0;
endcase
case(reg_B[92:127]) // word7
4'd0:
result[112:127]<=reg_A[112:127];
4'd1:
result[112:127]<={{1{reg_A[112]}},reg_A[112:126]};
4'd2:
result[112:127]<={{2{reg_A[112]}},reg_A[112:125]};
4'd3:
result[112:127]<={{3{reg_A[112]}},reg_A[112:124]};
4'd4:
result[112:127]<={{4{reg_A[112]}},reg_A[112:123]};
4'd5:
result[112:127]<={{5{reg_A[112]}},reg_A[112:122]};
4'd6:
result[112:127]<={{6{reg_A[112]}},reg_A[112:121]};
4'd7:
result[112:127]<={{7{reg_A[112]}},reg_A[112:120]};
4'd8:
result[112:127]<={{8{reg_A[112]}},reg_A[112:119]};
4'd9:
result[112:127]<={{9{reg_A[112]}},reg_A[112:118]};
4'd10:
result[112:127]<={{10{reg_A[112]}},reg_A[112:117]};
4'd11:
result[112:127]<={{11{reg_A[112]}},reg_A[112:116]};
4'd12:
result[112:127]<={{12{reg_A[112]}},reg_A[112:115]};
4'd13:
result[112:127]<={{13{reg_A[112]}},reg_A[112:114]};
4'd14:
result[112:127]<={{14{reg_A[112]}},reg_A[112:113]};
4'd15:
result[112:127]<={{15{reg_A[112]}},reg_A[112]};
default:
result[112:127]<=16'b0;
endcase
end
`w32:
begin
case(reg_B[27:31])
5'd0:
result[0:31]<=reg_A[0:31];
5'd1:
result[0:31]<={{1{reg_A[0]}},reg_A[0:30]};
5'd2:
result[0:31]<={{2{reg_A[0]}},reg_A[0:29]};
5'd3:
result[0:31]<={{3{reg_A[0]}},reg_A[0:28]};
5'd4:
result[0:31]<={{4{reg_A[0]}},reg_A[0:27]};
5'd5:
result[0:31]<={{5{reg_A[0]}},reg_A[0:26]};
5'd6:
result[0:31]<={{6{reg_A[0]}},reg_A[0:25]};
5'd7:
result[0:31]<={{7{reg_A[0]}},reg_A[0:24]};
5'd8:
result[0:31]<={{8{reg_A[0]}},reg_A[0:23]};
5'd9:
result[0:31]<={{9{reg_A[0]}},reg_A[0:22]};
5'd10:
result[0:31]<={{10{reg_A[0]}},reg_A[0:21]};
5'd11:
result[0:31]<={{11{reg_A[0]}},reg_A[0:20]};
5'd12:
result[0:31]<={{12{reg_A[0]}},reg_A[0:19]};
5'd13:
result[0:31]<={{13{reg_A[0]}},reg_A[0:18]};
5'd14:
result[0:31]<={{14{reg_A[0]}},reg_A[0:17]};
5'd15:
result[0:31]<={{15{reg_A[0]}},reg_A[0:16]};
5'd16:
result[0:31]<={{16{reg_A[0]}},reg_A[0:15]};
5'd17:
result[0:31]<={{17{reg_A[0]}},reg_A[0:14]};
5'd18:
result[0:31]<={{18{reg_A[0]}},reg_A[0:13]};
5'd19:
result[0:31]<={{19{reg_A[0]}},reg_A[0:12]};
5'd20:
result[0:31]<={{20{reg_A[0]}},reg_A[0:11]};
5'd21:
result[0:31]<={{21{reg_A[0]}},reg_A[0:10]};
5'd22:
result[0:31]<={{22{reg_A[0]}},reg_A[0:9]};
5'd23:
result[0:31]<={{23{reg_A[0]}},reg_A[0:8]};
5'd24:
result[0:31]<={{24{reg_A[0]}},reg_A[0:7]};
5'd25:
result[0:31]<={{25{reg_A[0]}},reg_A[0:6]};
5'd26:
result[0:31]<={{26{reg_A[0]}},reg_A[0:5]};
5'd27:
result[0:31]<={{27{reg_A[0]}},reg_A[0:4]};
5'd28:
result[0:31]<={{28{reg_A[0]}},reg_A[0:3]};
5'd29:
result[0:31]<={{29{reg_A[0]}},reg_A[0:2]};
5'd30:
result[0:31]<={{30{reg_A[0]}},reg_A[0:1]};
5'd31:
result[0:31]<={{31{reg_A[0]}},reg_A[0]};
default:
result[0:31]<=32'b0;
endcase
case(reg_B[59:63])
5'd0:
result[32:63]<=reg_A[32:63];
5'd1:
result[32:63]<={{1{reg_A[32]}},reg_A[32:62]};
5'd2:
result[32:63]<={{2{reg_A[32]}},reg_A[32:61]};
5'd3:
result[32:63]<={{3{reg_A[32]}},reg_A[32:60]};
5'd4:
result[32:63]<={{4{reg_A[32]}},reg_A[32:59]};
5'd5:
result[32:63]<={{5{reg_A[32]}},reg_A[32:58]};
5'd6:
result[32:63]<={{6{reg_A[32]}},reg_A[32:57]};
5'd7:
result[32:63]<={{7{reg_A[32]}},reg_A[32:56]};
5'd8:
result[32:63]<={{8{reg_A[32]}},reg_A[32:55]};
5'd9:
result[32:63]<={{9{reg_A[32]}},reg_A[32:54]};
5'd10:
result[32:63]<={{10{reg_A[32]}},reg_A[32:53]};
5'd11:
result[32:63]<={{11{reg_A[32]}},reg_A[32:52]};
5'd12:
result[32:63]<={{12{reg_A[32]}},reg_A[32:51]};
5'd13:
result[32:63]<={{13{reg_A[32]}},reg_A[32:50]};
5'd14:
result[32:63]<={{14{reg_A[32]}},reg_A[32:49]};
5'd15:
result[32:63]<={{15{reg_A[32]}},reg_A[32:48]};
5'd16:
result[32:63]<={{16{reg_A[32]}},reg_A[32:47]};
5'd17:
result[32:63]<={{17{reg_A[32]}},reg_A[32:46]};
5'd18:
result[32:63]<={{18{reg_A[32]}},reg_A[32:45]};
5'd19:
result[32:63]<={{19{reg_A[32]}},reg_A[32:44]};
5'd20:
result[32:63]<={{20{reg_A[32]}},reg_A[32:43]};
5'd21:
result[32:63]<={{21{reg_A[32]}},reg_A[32:42]};
5'd22:
result[32:63]<={{22{reg_A[32]}},reg_A[32:41]};
5'd23:
result[32:63]<={{23{reg_A[32]}},reg_A[32:40]};
5'd24:
result[32:63]<={{24{reg_A[32]}},reg_A[32:39]};
5'd25:
result[32:63]<={{25{reg_A[32]}},reg_A[32:38]};
5'd26:
result[32:63]<={{26{reg_A[32]}},reg_A[32:37]};
5'd27:
result[32:63]<={{27{reg_A[32]}},reg_A[32:36]};
5'd28:
result[32:63]<={{28{reg_A[32]}},reg_A[32:35]};
5'd29:
result[32:63]<={{29{reg_A[32]}},reg_A[32:34]};
5'd30:
result[32:63]<={{30{reg_A[32]}},reg_A[32:33]};
5'd31:
result[32:63]<={{31{reg_A[32]}},reg_A[32]};
default:
result[32:63]<=32'b0;
endcase
case(reg_B[91:95])
5'd0:
result[64:95]<=reg_A[64:95];
5'd1:
result[64:95]<={{1{reg_A[64]}},reg_A[64:94]};
5'd2:
result[64:95]<={{2{reg_A[64]}},reg_A[64:93]};
5'd3:
result[64:95]<={{3{reg_A[64]}},reg_A[64:92]};
5'd4:
result[64:95]<={{4{reg_A[64]}},reg_A[64:91]};
5'd5:
result[64:95]<={{5{reg_A[64]}},reg_A[64:90]};
5'd6:
result[64:95]<={{6{reg_A[64]}},reg_A[64:89]};
5'd7:
result[64:95]<={{7{reg_A[64]}},reg_A[64:88]};
5'd8:
result[64:95]<={{8{reg_A[64]}},reg_A[64:87]};
5'd9:
result[64:95]<={{9{reg_A[64]}},reg_A[64:86]};
5'd10:
result[64:95]<={{10{reg_A[64]}},reg_A[64:85]};
5'd11:
result[64:95]<={{11{reg_A[64]}},reg_A[64:84]};
5'd12:
result[64:95]<={{12{reg_A[64]}},reg_A[64:83]};
5'd13:
result[64:95]<={{13{reg_A[64]}},reg_A[64:82]};
5'd14:
result[64:95]<={{14{reg_A[64]}},reg_A[64:81]};
5'd15:
result[64:95]<={{15{reg_A[64]}},reg_A[64:80]};
5'd16:
result[64:95]<={{16{reg_A[64]}},reg_A[64:79]};
5'd17:
result[64:95]<={{17{reg_A[64]}},reg_A[64:78]};
5'd18:
result[64:95]<={{18{reg_A[64]}},reg_A[64:77]};
5'd19:
result[64:95]<={{19{reg_A[64]}},reg_A[64:76]};
5'd20:
result[64:95]<={{20{reg_A[64]}},reg_A[64:75]};
5'd21:
result[64:95]<={{21{reg_A[64]}},reg_A[64:74]};
5'd22:
result[64:95]<={{22{reg_A[64]}},reg_A[64:73]};
5'd23:
result[64:95]<={{23{reg_A[64]}},reg_A[64:72]};
5'd24:
result[64:95]<={{24{reg_A[64]}},reg_A[64:71]};
5'd25:
result[64:95]<={{25{reg_A[64]}},reg_A[64:70]};
5'd26:
result[64:95]<={{26{reg_A[64]}},reg_A[64:69]};
5'd27:
result[64:95]<={{27{reg_A[64]}},reg_A[64:68]};
5'd28:
result[64:95]<={{28{reg_A[64]}},reg_A[64:67]};
5'd29:
result[64:95]<={{29{reg_A[64]}},reg_A[64:66]};
5'd30:
result[64:95]<={{30{reg_A[64]}},reg_A[64:65]};
5'd31:
result[64:95]<={{31{reg_A[64]}},reg_A[64]};
default:
result[64:95]<=32'b0;
endcase
case(reg_B[123:127])
5'd0:
result[96:127]<=reg_A[96:127];
5'd1:
result[96:127]<={{1{reg_A[96]}},reg_A[96:126]};
5'd2:
result[96:127]<={{2{reg_A[96]}},reg_A[96:125]};
5'd3:
result[96:127]<={{3{reg_A[96]}},reg_A[96:124]};
5'd4:
result[96:127]<={{4{reg_A[96]}},reg_A[96:123]};
5'd5:
result[96:127]<={{5{reg_A[96]}},reg_A[96:122]};
5'd6:
result[96:127]<={{6{reg_A[96]}},reg_A[96:121]};
5'd7:
result[96:127]<={{7{reg_A[96]}},reg_A[96:120]};
5'd8:
result[96:127]<={{8{reg_A[96]}},reg_A[96:119]};
5'd9:
result[96:127]<={{9{reg_A[96]}},reg_A[96:118]};
5'd10:
result[96:127]<={{10{reg_A[96]}},reg_A[96:117]};
5'd11:
result[96:127]<={{11{reg_A[96]}},reg_A[96:116]};
5'd12:
result[96:127]<={{12{reg_A[96]}},reg_A[96:115]};
5'd13:
result[96:127]<={{13{reg_A[96]}},reg_A[96:114]};
5'd14:
result[96:127]<={{14{reg_A[96]}},reg_A[96:113]};
5'd15:
result[96:127]<={{15{reg_A[96]}},reg_A[96:112]};
5'd16:
result[96:127]<={{16{reg_A[96]}},reg_A[96:111]};
5'd17:
result[96:127]<={{17{reg_A[96]}},reg_A[96:110]};
5'd18:
result[96:127]<={{18{reg_A[96]}},reg_A[96:109]};
5'd19:
result[96:127]<={{19{reg_A[96]}},reg_A[96:108]};
5'd20:
result[96:127]<={{20{reg_A[96]}},reg_A[96:107]};
5'd21:
result[96:127]<={{21{reg_A[96]}},reg_A[96:106]};
5'd22:
result[96:127]<={{22{reg_A[96]}},reg_A[96:105]};
5'd23:
result[96:127]<={{23{reg_A[96]}},reg_A[96:104]};
5'd24:
result[96:127]<={{24{reg_A[96]}},reg_A[96:103]};
5'd25:
result[96:127]<={{25{reg_A[96]}},reg_A[96:102]};
5'd26:
result[96:127]<={{26{reg_A[96]}},reg_A[96:101]};
5'd27:
result[96:127]<={{27{reg_A[96]}},reg_A[96:100]};
5'd28:
result[96:127]<={{28{reg_A[96]}},reg_A[96:99]};
5'd29:
result[96:127]<={{29{reg_A[96]}},reg_A[96:98]};
5'd30:
result[96:127]<={{30{reg_A[96]}},reg_A[96:97]};
5'd31:
result[96:127]<={{31{reg_A[96]}},reg_A[96]};
default:
result[96:127]<=32'b0;
endcase
end
default
result<=128'b0;
endcase
end
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// !!TROY PART 2 START!!
// ======================================================
// Signed Multiplication - even subfields
`aluwmules:
begin
case(ctrl_ww)
(`w8+2'b1): // aluwmules AND `w8
begin
// Process the 1st byte
// Process operand B
p_pdt8a2[8:15]=reg_B[0:7];
p_pdt8a2[0:7]=8'd0;
// Process operand A
if(reg_A[0]==1'd1)
begin
p_pdt8a[8:15]=1+~reg_A[0:7];
if(reg_B[0]==1'd1)
begin
p_pdt8a2[8:15]=1+~reg_B[0:7];
end
else
begin
p_pdt8a2[8:15]=reg_B[0:7];
end
end
else
begin
p_pdt8a[8:15]=reg_A[0:7];
end
p_pdt8a[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8a2[15]==1'd1)
begin
p_pdt[0:15]=p_pdt[0:15] - p_pdt8a[0:15];
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8a2[sgn]==1'b1) && (p_pdt8a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]-(p_pdt8a<<(7-(sgn%8)));
end
else if((p_pdt8a2[sgn]==1'b0) && (p_pdt8a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]+(p_pdt8a<<(7-(sgn%8)));
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
end
if(p_pdt8a[8]==1'd1)
begin
result[0:15]<=1+~p_pdt[0:15];
end
else
begin
result[0:15]<=p_pdt[0:15];
end
// Process the 2nd byte
// Process operand B
p_pdt8b2[8:15]=reg_B[16:23];
p_pdt8b2[0:7]=8'd0;
// Process operand A
if(reg_A[16]==1'd1)
begin
p_pdt8b[8:15]=1+~reg_A[16:23];
if(reg_B[16]==1'd1)
begin
p_pdt8b2[8:15]=1+~reg_B[16:23];
end
else
begin
p_pdt8b2[8:15]=reg_B[16:23];
end
end
else
begin
p_pdt8b[8:15]=reg_A[16:23];
end
p_pdt8b[0:7]=8'd0;
$display("p_pdt8b[0:15]",p_pdt8b[0:15]);
$display("p_pdt8b2[0:15]",p_pdt8b2[0:15]);
// Determine the 1st recoded bit and compute the result
if(p_pdt8b2[15]==1'd1)
begin
p_pdt[16:31]=p_pdt[16:31] - p_pdt8b[0:15];
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
end
$display("p_pdt[16:31]",p_pdt[16:31]);
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8b2[sgn]==1'b1) && (p_pdt8b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]-(p_pdt8b<<(7-(sgn%8)));
$display("MINUSp_pdt[16:31]",p_pdt[16:31]);
end
else if((p_pdt8b2[sgn]==1'b0) && (p_pdt8b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]+(p_pdt8b<<(7-(sgn%8)));
$display("ADDp_pdt[16:31]",p_pdt[16:31]);
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
$display("ZEROp_pdt[16:31]",p_pdt[16:31]);
end
end
if(p_pdt8b[8]==1'd1)
begin
result[16:31]<=1+~p_pdt[16:31];
$display("INVp_pdt[16:31]",p_pdt[16:31]);
end
else
begin
result[16:31]<=p_pdt[16:31];
$display("RESp_pdt[16:31]",p_pdt[16:31]);
end
// Process the 3rd byte
// Process operand B
p_pdt8c2[8:15]=reg_B[32:39];
p_pdt8c2[0:7]=8'd0;
// Process operand A
if(reg_A[32]==1'd1)
begin
p_pdt8c[8:15]=1+~reg_A[32:39];
if(reg_B[32]==1'd1)
begin
p_pdt8c2[8:15]=1+~reg_B[32:39];
end
else
begin
p_pdt8c2[8:15]=reg_B[32:39];
end
end
else
begin
p_pdt8c[8:15]=reg_A[32:39];
end
p_pdt8c[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8c2[15]==1'd1)
begin
p_pdt[32:47]=p_pdt[32:47] - p_pdt8c[0:15];
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8c2[sgn]==1'b1) && (p_pdt8c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]-(p_pdt8c<<(7-(sgn%8)));
end
else if((p_pdt8c2[sgn]==1'b0) && (p_pdt8c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]+(p_pdt8c<<(7-(sgn%8)));
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
end
if(p_pdt8c[8]==1'd1)
begin
result[32:47]<=1+~p_pdt[32:47];
end
else
begin
result[32:47]<=p_pdt[32:47];
end
// Process the 4th byte
// Process operand B
p_pdt8d2[8:15]=reg_B[48:55];
p_pdt8d2[0:7]=8'd0;
// Process operand A
if(reg_A[48]==1'd1)
begin
p_pdt8d[8:15]=1+~reg_A[48:55];
if(reg_B[48]==1'd1)
begin
p_pdt8d2[8:15]=1+~reg_B[48:55];
end
else
begin
p_pdt8d2[8:15]=reg_B[48:55];
end
end
else
begin
p_pdt8d[8:15]=reg_A[48:55];
end
p_pdt8d[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8d2[15]==1'd1)
begin
p_pdt[48:63]=p_pdt[48:63] - p_pdt8d[0:15];
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8d2[sgn]==1'b1) && (p_pdt8d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]-(p_pdt8d<<(7-(sgn%8)));
end
else if((p_pdt8d2[sgn]==1'b0) && (p_pdt8d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]+(p_pdt8d<<(7-(sgn%8)));
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
end
if(p_pdt8d[8]==1'd1)
begin
result[48:63]<=1+~p_pdt[48:63];
end
else
begin
result[48:63]<=p_pdt[48:63];
end
// Process the 5th byte
// Process operand B
p_pdt8e2[8:15]=reg_B[64:71];
p_pdt8e2[0:7]=8'd0;
// Process operand A
if(reg_A[64]==1'd1)
begin
p_pdt8e[8:15]=1+~reg_A[64:71];
if(reg_B[64]==1'd1)
begin
p_pdt8e2[8:15]=1+~reg_B[64:71];
end
else
begin
p_pdt8e2[8:15]=reg_B[64:71];
end
end
else
begin
p_pdt8e[8:15]=reg_A[64:71];
end
p_pdt8e[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8e2[15]==1'd1)
begin
p_pdt[64:79]=p_pdt[64:79] - p_pdt8e[0:15];
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8e2[sgn]==1'b1) && (p_pdt8e2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]-(p_pdt8e<<(7-(sgn%8)));
end
else if((p_pdt8e2[sgn]==1'b0) && (p_pdt8e2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]+(p_pdt8e<<(7-(sgn%8)));
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
end
if(p_pdt8e[8]==1'd1)
begin
result[64:79]<=1+~p_pdt[64:79];
end
else
begin
result[64:79]<=p_pdt[64:79];
end
// Process the 6th byte
// Process operand B
p_pdt8f2[8:15]=reg_B[80:87];
p_pdt8f2[0:7]=8'd0;
// Process operand A
if(reg_A[80]==1'd1)
begin
p_pdt8f[8:15]=1+~reg_A[80:87];
if(reg_B[80]==1'd1)
begin
p_pdt8f2[8:15]=1+~reg_B[80:87];
end
else
begin
p_pdt8f2[8:15]=reg_B[80:87];
end
end
else
begin
p_pdt8f[8:15]=reg_A[80:87];
end
p_pdt8f[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8f2[15]==1'd1)
begin
p_pdt[80:95]=p_pdt[80:95] - p_pdt8f[0:15];
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8f2[sgn]==1'b1) && (p_pdt8f2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]-(p_pdt8f<<(7-(sgn%8)));
end
else if((p_pdt8f2[sgn]==1'b0) && (p_pdt8f2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]+(p_pdt8f<<(7-(sgn%8)));
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
end
if(p_pdt8f[8]==1'd1)
begin
result[80:95]<=1+~p_pdt[80:95];
end
else
begin
result[80:95]<=p_pdt[80:95];
end
// Process the 7th byte
// Process operand B
p_pdt8g2[8:15]=reg_B[96:103];
p_pdt8g2[0:7]=8'd0;
// Process operand A
if(reg_A[96]==1'd1)
begin
p_pdt8g[8:15]=1+~reg_A[96:103];
if(reg_B[96]==1'd1)
begin
p_pdt8g2[8:15]=1+~reg_B[96:103];
end
else
begin
p_pdt8g2[8:15]=reg_B[96:103];
end
end
else
begin
p_pdt8g[8:15]=reg_A[96:103];
end
p_pdt8g[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8g2[15]==1'd1)
begin
p_pdt[96:111]=p_pdt[96:111] - p_pdt8g[0:15];
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8g2[sgn]==1'b1) && (p_pdt8g2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]-(p_pdt8g<<(7-(sgn%8)));
end
else if((p_pdt8g2[sgn]==1'b0) && (p_pdt8g2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]+(p_pdt8g<<(7-(sgn%8)));
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
end
if(p_pdt8g[8]==1'd1)
begin
result[96:111]<=1+~p_pdt[96:111];
end
else
begin
result[96:111]<=p_pdt[96:111];
end
// Process the 8th byte
// Process operand B
p_pdt8h2[8:15]=reg_B[112:119];
p_pdt8h2[0:7]=8'd0;
// Process operand A
if(reg_A[112]==1'd1)
begin
p_pdt8h[8:15]=1+~reg_A[112:119];
if(reg_B[112]==1'd1)
begin
p_pdt8h2[8:15]=1+~reg_B[112:119];
end
else
begin
p_pdt8h2[8:15]=reg_B[112:119];
end
end
else
begin
p_pdt8h[8:15]=reg_A[112:119];
end
p_pdt8h[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8h2[15]==1'd1)
begin
p_pdt[112:127]=p_pdt[112:127] - p_pdt8h[0:15];
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8h2[sgn]==1'b1) && (p_pdt8h2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]-(p_pdt8h<<(7-(sgn%8)));
end
else if((p_pdt8h2[sgn]==1'b0) && (p_pdt8h2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]+(p_pdt8h<<(7-(sgn%8)));
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
end
if(p_pdt8h[8]==1'd1)
begin
result[112:127]<=1+~p_pdt[112:127];
end
else
begin
result[112:127]<=p_pdt[112:127];
end
// =======================================================
// =======================================================
// =======================================================
end
(`w16+2'b1): // aluwmules AND `w16
begin
// Process the first pair of bytes
// Process operand B
p_pdt16a2[16:31]=reg_B[0:15];
p_pdt16a2[0:15]=16'd0;
// Process operand A
if(reg_A[0]==1'd1)
begin
p_pdt16a[16:31]=1+~reg_A[0:15];
if(reg_B[0]==1'd1)
begin
p_pdt16a2[16:31]=1+~reg_B[0:15];
end
else
begin
p_pdt16a2[16:31]=reg_B[0:15];
end
end
else
begin
p_pdt16a[16:31]=reg_A[0:15];
end
p_pdt16a[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16a2[31]==1'd1)
begin
p_pdt[0:31]=p_pdt[0:31] - p_pdt16a[0:31];
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16a2[sgn]==1'b1) && (p_pdt16a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]-(p_pdt16a<<(15-(sgn%16)));
end
else if((p_pdt16a2[sgn]==1'b0) && (p_pdt16a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]+(p_pdt16a<<(15-(sgn%16)));
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
end
if(p_pdt16a[16]==1'd1)
begin
result[0:31]<=1+~p_pdt[0:31];
end
else
begin
result[0:31]<=p_pdt[0:31];
end
// Process the second pair of bytes
// Process operand B
p_pdt16b2[16:31]=reg_B[32:47];
p_pdt16b2[0:15]=16'd0;
// Process operand A
if(reg_A[32]==1'd1)
begin
p_pdt16b[16:31]=1+~reg_A[32:47];
if(reg_B[32]==1'd1)
begin
p_pdt16b2[16:31]=1+~reg_B[32:47];
end
else
begin
p_pdt16b2[16:31]=reg_B[32:47];
end
end
else
begin
p_pdt16b[16:31]=reg_A[0:15];
end
p_pdt16b[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16b2[31]==1'd1)
begin
p_pdt[32:63]=p_pdt[32:63] - p_pdt16b[0:31];
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16b2[sgn]==1'b1) && (p_pdt16b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]-(p_pdt16b<<(15-(sgn%16)));
end
else if((p_pdt16b2[sgn]==1'b0) && (p_pdt16b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]+(p_pdt16b<<(15-(sgn%16)));
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
end
if(p_pdt16b[16]==1'd1)
begin
result[32:63]<=1+~p_pdt[32:63];
end
else
begin
result[32:63]<=p_pdt[32:63];
end
// Process the third pair of bytes
// Process operand B
p_pdt16c2[16:31]=reg_B[64:79];
p_pdt16c2[0:15]=16'd0;
// Process operand A
if(reg_A[64]==1'd1)
begin
p_pdt16c[16:31]=1+~reg_A[64:79];
if(reg_B[64]==1'd1)
begin
p_pdt16c2[16:31]=1+~reg_B[64:79];
end
else
begin
p_pdt16c2[16:31]=reg_B[64:79];
end
end
else
begin
p_pdt16c[16:31]=reg_A[64:79];
end
p_pdt16c[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16c2[31]==1'd1)
begin
p_pdt[64:95]=p_pdt[64:95] - p_pdt16c[0:31];
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16c2[sgn]==1'b1) && (p_pdt16c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]-(p_pdt16c<<(15-(sgn%16)));
end
else if((p_pdt16c2[sgn]==1'b0) && (p_pdt16c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]+(p_pdt16c<<(15-(sgn%16)));
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
end
if(p_pdt16c[16]==1'd1)
begin
result[64:95]<=1+~p_pdt[64:95];
end
else
begin
result[64:95]<=p_pdt[64:95];
end
// Process the fourth pair of bytes
// Process operand B
p_pdt16d2[16:31]=reg_B[96:111];
p_pdt16d2[0:15]=16'd0;
// Process operand A
if(reg_A[96]==1'd1)
begin
p_pdt16d[16:31]=1+~reg_A[96:111];
if(reg_B[96]==1'd1)
begin
p_pdt16d2[16:31]=1+~reg_B[96:111];
end
else
begin
p_pdt16d2[16:31]=reg_B[96:111];
end
end
else
begin
p_pdt16d[16:31]=reg_A[96:111];
end
p_pdt16d[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16d2[31]==1'd1)
begin
p_pdt[96:127]=p_pdt[96:127] - p_pdt16d[0:31];
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16d2[sgn]==1'b1) && (p_pdt16d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]-(p_pdt16d<<(15-(sgn%16)));
end
else if((p_pdt16d2[sgn]==1'b0) && (p_pdt16d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]+(p_pdt16d<<(15-(sgn%16)));
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
end
if(p_pdt16d[16]==1'd1)
begin
result[96:127]<=1+~p_pdt[96:127];
end
else
begin
result[96:127]<=p_pdt[96:127];
end
end
default: // aluwmules AND Default
begin
result<=128'd0;
end
endcase
end
// ======================================================
// Signed Multiplication - odd subfields
`aluwmulos:
begin
case(ctrl_ww)
(`w8+2'b1): // aluwmulos AND `w8
begin
// Process the 1st byte
// Process operand B
p_pdt8a2[8:15]=reg_B[8:15];
p_pdt8a2[0:7]=8'd0;
// Process operand A
if(reg_A[8]==1'd1)
begin
p_pdt8a[8:15]=1+~reg_A[8:15];
if(reg_B[8]==1'd1)
begin
p_pdt8a2[8:15]=1+~reg_B[8:15];
end
else
begin
p_pdt8a2[8:15]=reg_B[8:15];
end
end
else
begin
p_pdt8a[8:15]=reg_A[8:15];
end
p_pdt8a[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8a2[15]==1'd1)
begin
p_pdt[0:15]=p_pdt[0:15] - p_pdt8a[0:15];
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8a2[sgn]==1'b1) && (p_pdt8a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]-(p_pdt8a<<(7-(sgn%8)));
end
else if((p_pdt8a2[sgn]==1'b0) && (p_pdt8a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]+(p_pdt8a<<(7-(sgn%8)));
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
end
if(p_pdt8a[8]==1'd1)
begin
result[0:15]<=1+~p_pdt[0:15];
end
else
begin
result[0:15]<=p_pdt[0:15];
end
// Process the 2nd byte
// Process operand B
p_pdt8b2[8:15]=reg_B[24:31];
p_pdt8b2[0:7]=8'd0;
// Process operand A
if(reg_A[24]==1'd1)
begin
p_pdt8b[8:15]=1+~reg_A[24:31];
if(reg_B[24]==1'd1)
begin
p_pdt8b2[8:15]=1+~reg_B[24:31];
end
else
begin
p_pdt8b2[8:15]=reg_B[24:31];
end
end
else
begin
p_pdt8b[8:15]=reg_A[24:31];
end
p_pdt8b[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8b2[15]==1'd1)
begin
p_pdt[16:31]=p_pdt[16:31] - p_pdt8b[0:15];
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8b2[sgn]==1'b1) && (p_pdt8b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]-(p_pdt8b<<(7-(sgn%8)));
end
else if((p_pdt8b2[sgn]==1'b0) && (p_pdt8b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]+(p_pdt8b<<(7-(sgn%8)));
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
end
end
if(p_pdt8b[8]==1'd1)
begin
result[16:31]<=1+~p_pdt[16:31];
end
else
begin
result[16:31]<=p_pdt[16:31];
end
// Process the 3rd byte
// Process operand B
p_pdt8c2[8:15]=reg_B[40:47];
p_pdt8c2[0:7]=8'd0;
// Process operand A
if(reg_A[40]==1'd1)
begin
p_pdt8c[8:15]=1+~reg_A[40:47];
if(reg_B[40]==1'd1)
begin
p_pdt8c2[8:15]=1+~reg_B[40:47];
end
else
begin
p_pdt8c2[8:15]=reg_B[40:47];
end
end
else
begin
p_pdt8c[8:15]=reg_A[40:47];
end
p_pdt8c[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8c2[15]==1'd1)
begin
p_pdt[32:47]=p_pdt[32:47] - p_pdt8c[0:15];
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8c2[sgn]==1'b1) && (p_pdt8c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]-(p_pdt8c<<(7-(sgn%8)));
end
else if((p_pdt8c2[sgn]==1'b0) && (p_pdt8c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]+(p_pdt8c<<(7-(sgn%8)));
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
end
if(p_pdt8c[8]==1'd1)
begin
result[32:47]<=1+~p_pdt[32:47];
end
else
begin
result[32:47]<=p_pdt[32:47];
end
// Process the 4th byte
// Process operand B
p_pdt8d2[8:15]=reg_B[56:63];
p_pdt8d2[0:7]=8'd0;
// Process operand A
if(reg_A[56]==1'd1)
begin
p_pdt8d[8:15]=1+~reg_A[56:63];
if(reg_B[56]==1'd1)
begin
p_pdt8d2[8:15]=1+~reg_B[56:63];
end
else
begin
p_pdt8d2[8:15]=reg_B[56:63];
end
end
else
begin
p_pdt8d[8:15]=reg_A[56:63];
end
p_pdt8d[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8d2[15]==1'd1)
begin
p_pdt[48:63]=p_pdt[48:63] - p_pdt8d[0:15];
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8d2[sgn]==1'b1) && (p_pdt8d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]-(p_pdt8d<<(7-(sgn%8)));
end
else if((p_pdt8d2[sgn]==1'b0) && (p_pdt8d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]+(p_pdt8d<<(7-(sgn%8)));
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
end
if(p_pdt8d[8]==1'd1)
begin
result[48:63]<=1+~p_pdt[48:63];
end
else
begin
result[48:63]<=p_pdt[48:63];
end
// Process the 5th byte
// Process operand B
p_pdt8e2[8:15]=reg_B[72:79];
p_pdt8e2[0:7]=8'd0;
// Process operand A
if(reg_A[72]==1'd1)
begin
p_pdt8e[8:15]=1+~reg_A[72:79];
if(reg_B[72]==1'd1)
begin
p_pdt8e2[8:15]=1+~reg_B[72:79];
end
else
begin
p_pdt8e2[8:15]=reg_B[72:79];
end
end
else
begin
p_pdt8e[8:15]=reg_A[72:79];
end
p_pdt8e[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8e2[15]==1'd1)
begin
p_pdt[64:79]=p_pdt[64:79] - p_pdt8e[0:15];
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8e2[sgn]==1'b1) && (p_pdt8e2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]-(p_pdt8e<<(7-(sgn%8)));
end
else if((p_pdt8e2[sgn]==1'b0) && (p_pdt8e2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]+(p_pdt8e<<(7-(sgn%8)));
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
end
if(p_pdt8e[8]==1'd1)
begin
result[64:79]<=1+~p_pdt[64:79];
end
else
begin
result[64:79]<=p_pdt[64:79];
end
// Process the 6th byte
// Process operand B
p_pdt8f2[8:15]=reg_B[88:95];
p_pdt8f2[0:7]=8'd0;
// Process operand A
if(reg_A[88]==1'd1)
begin
p_pdt8f[8:15]=1+~reg_A[88:95];
if(reg_B[88]==1'd1)
begin
p_pdt8f2[8:15]=1+~reg_B[88:95];
end
else
begin
p_pdt8f2[8:15]=reg_B[88:95];
end
end
else
begin
p_pdt8f[8:15]=reg_A[88:95];
end
p_pdt8f[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8f2[15]==1'd1)
begin
p_pdt[80:95]=p_pdt[80:95] - p_pdt8f[0:15];
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8f2[sgn]==1'b1) && (p_pdt8f2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]-(p_pdt8f<<(7-(sgn%8)));
end
else if((p_pdt8f2[sgn]==1'b0) && (p_pdt8f2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]+(p_pdt8f<<(7-(sgn%8)));
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
end
if(p_pdt8f[8]==1'd1)
begin
result[80:95]<=1+~p_pdt[80:95];
end
else
begin
result[80:95]<=p_pdt[80:95];
end
// Process the 7th byte
// Process operand B
p_pdt8g2[8:15]=reg_B[104:111];
p_pdt8g2[0:7]=8'd0;
// Process operand A
if(reg_A[104]==1'd1)
begin
p_pdt8g[8:15]=1+~reg_A[104:111];
if(reg_B[104]==1'd1)
begin
p_pdt8g2[8:15]=1+~reg_B[104:111];
end
else
begin
p_pdt8g2[8:15]=reg_B[104:111];
end
end
else
begin
p_pdt8g[8:15]=reg_A[104:111];
end
p_pdt8g[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8g2[15]==1'd1)
begin
p_pdt[96:111]=p_pdt[96:111] - p_pdt8g[0:15];
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8g2[sgn]==1'b1) && (p_pdt8g2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]-(p_pdt8g<<(7-(sgn%8)));
end
else if((p_pdt8g2[sgn]==1'b0) && (p_pdt8g2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]+(p_pdt8g<<(7-(sgn%8)));
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
end
if(p_pdt8g[8]==1'd1)
begin
result[96:111]<=1+~p_pdt[96:111];
end
else
begin
result[96:111]<=p_pdt[96:111];
end
// Process the 8th byte
// Process operand B
p_pdt8h2[8:15]=reg_B[120:127];
p_pdt8h2[0:7]=8'd0;
// Process operand A
if(reg_A[120]==1'd1)
begin
p_pdt8h[8:15]=1+~reg_A[120:127];
if(reg_B[120]==1'd1)
begin
p_pdt8h2[8:15]=1+~reg_B[120:127];
end
else
begin
p_pdt8h2[8:15]=reg_B[120:127];
end
end
else
begin
p_pdt8h[8:15]=reg_A[120:127];
end
p_pdt8h[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8h2[15]==1'd1)
begin
p_pdt[112:127]=p_pdt[112:127] - p_pdt8h[0:15];
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8h2[sgn]==1'b1) && (p_pdt8h2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]-(p_pdt8h<<(7-(sgn%8)));
end
else if((p_pdt8h2[sgn]==1'b0) && (p_pdt8h2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]+(p_pdt8h<<(7-(sgn%8)));
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
end
if(p_pdt8h[8]==1'd1)
begin
result[112:127]<=1+~p_pdt[112:127];
end
else
begin
result[112:127]<=p_pdt[112:127];
end
// ---------------------------------------
end
(`w16+2'b1): // aluwmulos AND `w16
begin
// Process the first pair of bytes
// Process operand B
p_pdt16a2[16:31]=reg_B[16:31];
p_pdt16a2[0:15]=16'd0;
// Process operand A
if(reg_A[16]==1'd1)
begin
p_pdt16a[16:31]=1+~reg_A[16:31];
if(reg_B[16]==1'd1)
begin
p_pdt16a2[16:31]=1+~reg_B[16:31];
end
else
begin
p_pdt16a2[16:31]=reg_B[16:31];
end
end
else
begin
p_pdt16a[16:31]=reg_A[16:31];
end
p_pdt16a[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16a2[31]==1'd1)
begin
p_pdt[0:31]=p_pdt[0:31] - p_pdt16a[0:31];
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16a2[sgn]==1'b1) && (p_pdt16a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]-(p_pdt16a<<(15-(sgn%16)));
end
else if((p_pdt16a2[sgn]==1'b0) && (p_pdt16a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]+(p_pdt16a<<(15-(sgn%16)));
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
end
if(p_pdt16a[16]==1'd1)
begin
result[0:31]<=1+~p_pdt[0:31];
end
else
begin
result[0:31]<=p_pdt[0:31];
end
// Process the second pair of bytes
// Process operand B
p_pdt16b2[16:31]=reg_B[48:63];
p_pdt16b2[0:15]=16'd0;
// Process operand A
if(reg_A[48]==1'd1)
begin
p_pdt16b[16:31]=1+~reg_A[48:63];
if(reg_B[48]==1'd1)
begin
p_pdt16b2[16:31]=1+~reg_B[48:63];
end
else
begin
p_pdt16b2[16:31]=reg_B[48:63];
end
end
else
begin
p_pdt16b[16:31]=reg_A[48:63];
end
p_pdt16b[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16b2[31]==1'd1)
begin
p_pdt[32:63]=p_pdt[32:63] - p_pdt16b[0:31];
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16b2[sgn]==1'b1) && (p_pdt16b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]-(p_pdt16b<<(15-(sgn%16)));
end
else if((p_pdt16b2[sgn]==1'b0) && (p_pdt16b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]+(p_pdt16b<<(15-(sgn%16)));
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
end
if(p_pdt16b[16]==1'd1)
begin
result[32:63]<=1+~p_pdt[32:63];
end
else
begin
result[32:63]<=p_pdt[32:63];
end
// Process the third pair of bytes
// Process operand B
p_pdt16c2[16:31]=reg_B[80:95];
p_pdt16c2[0:15]=16'd0;
// Process operand A
if(reg_A[80]==1'd1)
begin
p_pdt16c[16:31]=1+~reg_A[80:95];
if(reg_B[80]==1'd1)
begin
p_pdt16c2[16:31]=1+~reg_B[80:95];
end
else
begin
p_pdt16c2[16:31]=reg_B[80:95];
end
end
else
begin
p_pdt16c[16:31]=reg_A[80:95];
end
p_pdt16c[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16c2[31]==1'd1)
begin
p_pdt[64:95]=p_pdt[64:95] - p_pdt16c[0:31];
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16c2[sgn]==1'b1) && (p_pdt16c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]-(p_pdt16c<<(15-(sgn%16)));
end
else if((p_pdt16c2[sgn]==1'b0) && (p_pdt16c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]+(p_pdt16c<<(15-(sgn%16)));
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
end
if(p_pdt16c[16]==1'd1)
begin
result[64:95]<=1+~p_pdt[64:95];
end
else
begin
result[64:95]<=p_pdt[64:95];
end
// Process the fourth pair of bytes
// Process operand B
p_pdt16d2[16:31]=reg_B[112:127];
p_pdt16d2[0:15]=16'd0;
// Process operand A
if(reg_A[112]==1'd1)
begin
p_pdt16d[16:31]=1+~reg_A[112:127];
if(reg_B[112]==1'd1)
begin
p_pdt16d2[16:31]=1+~reg_B[112:127];
end
else
begin
p_pdt16d2[16:31]=reg_B[112:127];
end
end
else
begin
p_pdt16d[16:31]=reg_A[112:127];
end
p_pdt16d[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16d2[31]==1'd1)
begin
p_pdt[96:127]=p_pdt[96:127] - p_pdt16d[0:31];
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16d2[sgn]==1'b1) && (p_pdt16d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]-(p_pdt16d<<(15-(sgn%16)));
end
else if((p_pdt16d2[sgn]==1'b0) && (p_pdt16d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]+(p_pdt16d<<(15-(sgn%16)));
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
end
if(p_pdt16d[16]==1'd1)
begin
result[96:127]<=1+~p_pdt[96:127];
end
else
begin
result[96:127]<=p_pdt[96:127];
end
end
default: // aluwmules AND Default
begin
result<=128'd0;
end
endcase
end
// ===========================================
// Unsigned Multiplication - even subfields
`aluwmuleu:
begin
case(ctrl_ww)
(`w8+2'b1):
begin
// 1st even byte
// extend operand B
p_pdt8a2={{8{1'b0}},reg_B[0+(16*0):7+(16*0)]};
// extend operand A
p_pdt8a={{8{1'b0}},reg_A[0+(16*0):7+(16*0)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*0):15+(16*0)]=p_pdt[0+(16*0):15+(16*0)]
+ (p_pdt8a[i]?(p_pdt8a2<<(8'd15-i)):16'b0);
// 2nd even byte
// extend operand B
p_pdt8b2={{8{1'b0}},reg_B[0+(16*1):7+(16*1)]};
// extend operand A
p_pdt8b={{8{1'b0}},reg_A[0+(16*1):7+(16*1)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*1):15+(16*1)]=p_pdt[0+(16*1):15+(16*1)]
+ (p_pdt8b[i]?(p_pdt8b2<<(8'd15-i)):16'b0);
// 3rd even byte
// extend operand B
p_pdt8c2={{8{1'b0}},reg_B[0+(16*2):7+(16*2)]};
// extend operand A
p_pdt8c={{8{1'b0}},reg_A[0+(16*2):7+(16*2)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*2):15+(16*2)]=p_pdt[0+(16*2):15+(16*2)]
+ (p_pdt8c[i]?(p_pdt8c2<<(8'd15-i)):16'b0);
// 4th even byte
// extend operand B
p_pdt8d2={{8{1'b0}},reg_B[0+(16*3):7+(16*3)]};
// extend operand A
p_pdt8d={{8{1'b0}},reg_A[0+(16*3):7+(16*3)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*3):15+(16*3)]=p_pdt[0+(16*3):15+(16*3)]
+ (p_pdt8d[i]?(p_pdt8d2<<(8'd15-i)):16'b0);
// 5th even byte
// extend operand B
p_pdt8e2={{8{1'b0}},reg_B[0+(16*4):7+(16*4)]};
// extend operand A
p_pdt8e={{8{1'b0}},reg_A[0+(16*4):7+(16*4)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*4):15+(16*4)]=p_pdt[0+(16*4):15+(16*4)]
+ (p_pdt8e[i]?(p_pdt8e2<<(8'd15-i)):16'b0);
// 6th even byte
// extend operand B
p_pdt8f2={{8{1'b0}},reg_B[0+(16*5):7+(16*5)]};
// extend operand A
p_pdt8f={{8{1'b0}},reg_A[0+(16*5):7+(16*5)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*5):15+(16*5)]=p_pdt[0+(16*5):15+(16*5)]
+ (p_pdt8f[i]?(p_pdt8f2<<(8'd15-i)):16'b0);
// 7th even byte
// extend operand B
p_pdt8g2={{8{1'b0}},reg_B[0+(16*6):7+(16*6)]};
// extend operand A
p_pdt8g={{8{1'b0}},reg_A[0+(16*6):7+(16*6)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*6):15+(16*6)]=p_pdt[0+(16*6):15+(16*6)]
+ (p_pdt8g[i]?(p_pdt8g2<<(8'd15-i)):16'b0);
// 8th even byte
// extend operand B
p_pdt8h2={{8{1'b0}},reg_B[0+(16*7):7+(16*7)]};
// extend operand A
p_pdt8h={{8{1'b0}},reg_A[0+(16*7):7+(16*7)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*7):15+(16*7)]=p_pdt[0+(16*7):15+(16*7)]
+ (p_pdt8h[i]?(p_pdt8h2<<(8'd15-i)):16'b0);
result<=p_pdt;
end // case (`w8+2'b1)
(`w16+2'b1):
begin
// 1st word
// extend operand B
p_pdt16a2={{16{1'b0}},reg_B[0+(32*0):15+(32*0)]};
// extend operand A
p_pdt16a={{16{1'b0}},reg_A[0+(32*0):15+(32*0)]};
// i loops through each bit to compute sum due to partial products
for (i=31; i>15; i=i-1)
p_pdt[0+(32*0):31+(32*0)]=p_pdt[0+(32*0):31+(32*0)]
+ (p_pdt16a[i]?(p_pdt16a2<<(8'd31-i)):32'b0);
// 2nd word
// extend operand B
p_pdt16b2={{16{1'b0}},reg_B[0+(32*1):15+(32*1)]};
// extend operand A
p_pdt16b={{16{1'b0}},reg_A[0+(32*1):15+(32*1)]};
// i loops through each bit to compute sum due to partial products
for (i=31; i>15; i=i-1)
p_pdt[0+(32*1):31+(32*1)]=p_pdt[0+(32*1):31+(32*1)]
+ (p_pdt16b[i]?(p_pdt16b2<<(8'd31-i)):32'b0);
// 3rd word
// extend operand B
p_pdt16c2={{16{1'b0}},reg_B[0+(32*2):15+(32*2)]};
// extend operand A
p_pdt16c={{16{1'b0}},reg_A[0+(32*2):15+(32*2)]};
// i loops through each bit to compute sum due to partial products
for (i=31; i>15; i=i-1)
p_pdt[0+(32*2):31+(32*2)]=p_pdt[0+(32*2):31+(32*2)]
+ (p_pdt16c[i]?(p_pdt16c2<<(8'd31-i)):32'b0);
// 4th word
// extend operand B
p_pdt16d2={{16{1'b0}},reg_B[0+(32*3):15+(32*3)]};
// extend operand A
p_pdt16d={{16{1'b0}},reg_A[0+(32*3):15+(32*3)]};
// i loops through each bit to compute sum due to partial products
for (i=31; i>15; i=i-1)
p_pdt[0+(32*3):31+(32*3)]=p_pdt[0+(32*3):31+(32*3)]
+ (p_pdt16d[i]?(p_pdt16d2<<(8'd31-i)):32'b0);
result<=p_pdt;
end // case (`w16+2'b1)
default:
begin
result<=128'd0;
end
endcase // case(ctrl_ww)
end
// ===================================
// Unsigned Multiplication - odd subfields
`aluwmulou:
begin
case(ctrl_ww)
(`w8+2'd1): // aluwmulou AND `w8
begin
p_pdt8a[8:15]=reg_A[8:15];
p_pdt8a[0:7]=8'd0;
p_pdt8a2[0:15]={{8{1'b0}},reg_B[8:15]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[0:15]=p_pdt[0:15]+((p_pdt8a[sgn]==1'd1)?(p_pdt8a2<<(8'd15-sgn)):16'b0);
end
p_pdt8b[8:15]=reg_A[24:31];
p_pdt8b[0:7]=8'd0;
p_pdt8b2[0:15]={{8{1'b0}},reg_B[24:31]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[16:31]=p_pdt[16:31]+((p_pdt8b[sgn]==1'd1)?(p_pdt8b2<<(8'd15-sgn)):16'b0);
end
p_pdt8c[8:15]=reg_A[40:47];
p_pdt8c[0:7]=8'd0;
p_pdt8c2[0:15]={{8{1'b0}},reg_B[40:47]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[32:47]=p_pdt[32:47]+((p_pdt8c[sgn]==1'd1)?(p_pdt8c2<<(8'd15-sgn)):16'b0);
end
p_pdt8d[8:15]=reg_A[56:63];
p_pdt8d[0:7]=8'd0;
p_pdt8d2[0:15]={{8{1'b0}},reg_B[56:63]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[48:63]=p_pdt[48:63]+((p_pdt8d[sgn]==1'd1)?(p_pdt8d2<<(8'd15-sgn)):16'b0);
end
p_pdt8e[8:15]=reg_A[72:79];
p_pdt8e[0:7]=8'd0;
p_pdt8e2[0:15]={{8{1'b0}},reg_B[72:79]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[64:79]=p_pdt[64:79]+((p_pdt8e[sgn]==1'd1)?(p_pdt8e2<<(8'd15-sgn)):16'b0);
end
p_pdt8f[8:15]=reg_A[88:95];
p_pdt8f[0:7]=8'd0;
p_pdt8f2[0:15]={{8{1'b0}},reg_B[88:95]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[80:95]=p_pdt[80:95]+((p_pdt8f[sgn]==1'd1)?(p_pdt8f2<<(8'd15-sgn)):16'b0);
end
p_pdt8g[8:15]=reg_A[104:111];
p_pdt8g[0:7]=8'd0;
p_pdt8g2[0:15]={{8{1'b0}},reg_B[104:111]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[96:111]=p_pdt[96:111]+((p_pdt8g[sgn]==1'd1)?(p_pdt8g2<<(8'd15-sgn)):16'b0);
end
p_pdt8h[8:15]=reg_A[120:127];
p_pdt8h[0:7]=8'd0;
p_pdt8h2[0:15]={{8{1'b0}},reg_B[120:127]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[112:127]=p_pdt[112:127]+((p_pdt8h[sgn]==1'd1)?(p_pdt8h2<<(8'd15-sgn)):16'b0);
end
result<=p_pdt;
end
(`w16+2'b01): // aluwmulou AND `w16
begin
p_pdt16a[0:31]={{16{1'b0}},reg_B[16:31]};
p_pdt16a2[0:31]={{16{1'b0}},reg_A[16:31]};
p_pdt16b[0:31]={{16{1'b0}},reg_B[48:63]};
p_pdt16b2[0:31]={{16{1'b0}},reg_A[48:63]};
p_pdt16c[0:31]={{16{1'b0}},reg_B[80:95]};
p_pdt16c2[0:31]={{16{1'b0}},reg_A[80:95]};
p_pdt16d[0:31]={{16{1'b0}},reg_B[112:127]};
p_pdt16d2[0:31]={{16{1'b0}},reg_A[112:127]};
for(sgn=31; sgn>=16; sgn=sgn-1)
begin
p_pdt[0:31]=p_pdt[0:31]+((p_pdt16a[sgn]==1'd1)?(p_pdt16a2<<(16'd31-sgn)):32'd0);
p_pdt[32:63]=p_pdt[32:63]+((p_pdt16b[sgn]==1'd1)?(p_pdt16b2<<(16'd31-sgn)):32'd0);
p_pdt[64:95]=p_pdt[64:95]+((p_pdt16c[sgn]==1'd1)?(p_pdt16c2<<(16'd31-sgn)):32'd0);
p_pdt[96:127]=p_pdt[96:127]+((p_pdt16d[sgn]==1'd1)?(p_pdt16d2<<(16'd31-sgn)):32'd0);
end
result<=p_pdt;
end
default: // aluwmulou AND Default
begin
result<=128'd0;
end
endcase
end
// !!TROY PART 2 END!!
// ==================================================================
default:
begin
// Default arithmetic/logic operation
result<=128'd0;
end
endcase
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sat May 27 20:55:57 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_rgb888_to_g8_0_0/system_rgb888_to_g8_0_0_stub.v
// Design : system_rgb888_to_g8_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "rgb888_to_g8,Vivado 2016.4" *)
module system_rgb888_to_g8_0_0(clk, rgb888, g8)
/* synthesis syn_black_box black_box_pad_pin="clk,rgb888[23:0],g8[7:0]" */;
input clk;
input [23:0]rgb888;
output [7:0]g8;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O211A_1_V
`define SKY130_FD_SC_HD__O211A_1_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o211a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o211a_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o211a_1 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O211A_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SEDFXBP_TB_V
`define SKY130_FD_SC_HS__SEDFXBP_TB_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sedfxbp.v"
module top();
// Inputs are registered
reg D;
reg DE;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DE = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DE = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 DE = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 DE = 1'b0;
#300 SCD = 1'b0;
#320 SCE = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SCE = 1'b1;
#440 SCD = 1'b1;
#460 DE = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SCE = 1'bx;
#560 SCD = 1'bx;
#580 DE = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__sedfxbp dut (.D(D), .DE(DE), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SEDFXBP_TB_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
iic_scl,
iic_sda);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [14:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
inout iic_scl;
inout iic_sda;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
// instantiations
ad_iobuf #(
.DATA_WIDTH(15)
) i_gpio_bd (
.dio_t(gpio_t[14:0]),
.dio_i(gpio_o[14:0]),
.dio_o(gpio_i[14:0]),
.dio_p(gpio_bd));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.ps_intr_12 (1'b0),
.ps_intr_13 (1'b0),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************
|
module PIO8(
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_gpio_writedata,
output [31:0] avs_gpio_readdata,
input [2:0] avs_gpio_address,
input [3:0] avs_gpio_byteenable,
input avs_gpio_write,
input avs_gpio_read,
output avs_gpio_waitrequest,
inout coe_P0,
inout coe_P1,
inout coe_P2,
inout coe_P3,
inout coe_P4,
inout coe_P5,
inout coe_P6,
inout coe_P7
);
reg [7:0] io_data;
reg [7:0] io_out_en;
reg [31:0] read_data;
assign avs_gpio_readdata = read_data;
assign avs_gpio_waitrequest = 1'b0;
assign coe_P0 = (io_out_en[0]) ? io_data[0] : 1'bz;
assign coe_P1 = (io_out_en[1]) ? io_data[1] : 1'bz;
assign coe_P2 = (io_out_en[2]) ? io_data[2] : 1'bz;
assign coe_P3 = (io_out_en[3]) ? io_data[3] : 1'bz;
assign coe_P4 = (io_out_en[4]) ? io_data[4] : 1'bz;
assign coe_P5 = (io_out_en[5]) ? io_data[5] : 1'bz;
assign coe_P6 = (io_out_en[6]) ? io_data[6] : 1'bz;
assign coe_P7 = (io_out_en[7]) ? io_data[7] : 1'bz;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
read_data <= 0;
end
else begin
case(avs_gpio_address)
// 0: read_data <= 8;
// 1: read_data <= 32'hEA680001;
2: read_data <= {24'b0000, coe_P7, coe_P6, coe_P5, coe_P4, coe_P3, coe_P2, coe_P1, coe_P0};
4: read_data <= {24'b0000, io_out_en};
default: read_data <= 0;
endcase
end
end
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
io_data <= 0;
io_out_en <= 0;
end
else begin
if(avs_gpio_write) begin
case(avs_gpio_address)
2: begin
if(avs_gpio_byteenable[0]) io_data[7:0] <= avs_gpio_writedata[7:0];
end
4: begin
if(avs_gpio_byteenable[0]) io_out_en[7:0] <= avs_gpio_writedata[7:0];
end
default: begin end
endcase
end
end
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller Reset Module ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_rst.v,v 1.1 2001/08/03 06:54:50 rudi Exp $
//
// $Date: 2001/08/03 06:54:50 $
// $Revision: 1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_rst.v,v $
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:19 rudi
// Initial Checkin
//
//
//
//
`include "ac97_defines.v"
module ac97_rst(clk, rst, rst_force, ps_ce, ac97_rst_);
input clk, rst;
input rst_force;
output ps_ce;
output ac97_rst_;
reg ac97_rst_;
reg [2:0] cnt;
wire ce;
wire to;
reg [5:0] ps_cnt;
wire ps_ce;
always @(posedge clk or negedge rst)
if(!rst) ac97_rst_ <= #1 0;
else
if(rst_force) ac97_rst_ <= #1 0;
else
if(to) ac97_rst_ <= #1 1;
assign to = (cnt == `AC97_RST_DEL);
always @(posedge clk or negedge rst)
if(!rst) cnt <= #1 0;
else
if(rst_force) cnt <= #1 0;
else
if(ce) cnt <= #1 cnt + 1;
assign ce = ps_ce & (cnt != `AC97_RST_DEL);
always @(posedge clk or negedge rst)
if(!rst) ps_cnt <= #1 0;
else
if(ps_ce | rst_force) ps_cnt <= #1 0;
else ps_cnt <= #1 ps_cnt + 1;
assign ps_ce = (ps_cnt == `AC97_250_PS);
endmodule
|
module ptr(
input wire clk,
input wire reset,
/* IO bus */
input wire iobus_iob_poweron,
input wire iobus_iob_reset,
input wire iobus_datao_clear,
input wire iobus_datao_set,
input wire iobus_cono_clear,
input wire iobus_cono_set,
input wire iobus_iob_fm_datai,
input wire iobus_iob_fm_status,
input wire iobus_rdi_pulse, // unused on 6
input wire [3:9] iobus_ios,
input wire [0:35] iobus_iob_in,
output wire [1:7] iobus_pi_req,
output wire [0:35] iobus_iob_out,
output wire iobus_dr_split,
output wire iobus_rdi_data, // unused on 6
/* Console panel */
input wire key_start,
input wire key_stop,
input wire key_tape_feed,
output wire [35:0] ptr_ind,
output wire [6:0] status_ind, // also includes motor on
/* Avalon slave */
input wire s_write,
input wire [31:0] s_writedata,
output wire fe_data_rq
);
assign iobus_dr_split = 0;
assign iobus_rdi_data = 0;
assign ptr_ind = ptr;
assign status_ind = { motor_on, ptr_b, ptr_busy, ptr_flag, ptr_pia };
wire ptr_sel = iobus_ios == 7'b001_000_1;
wire [8:1] stb_hole = ptr_b ? { 2'b0, hole[6:1] } : hole[8:1];
wire ptr_data_clr;
wire ptr_data_set;
wire ptr_ic_clr;
wire ptr_ic_set;
wire iob_reset;
wire ptr_datai = ptr_sel & iobus_iob_fm_datai;
wire ptr_status = ptr_sel & iobus_iob_fm_status;
wire ptr_start_clr, ptr_stop_clr;
wire ptr_busy_set;
pa ptr_pa0(clk, reset, ptr_sel & iobus_datao_clear, ptr_data_clr);
pa ptr_pa1(clk, reset, ptr_sel & iobus_datao_set, ptr_data_set);
pa ptr_pa2(clk, reset, ptr_sel & iobus_cono_clear | iob_reset, ptr_ic_clr);
pa ptr_pa3(clk, reset, ptr_sel & iobus_cono_set, ptr_ic_set);
pa ptr_pa4(clk, reset, iobus_iob_reset, iob_reset);
pg ptr_pg0(clk, reset, motor_on, ptr_start_clr);
pg ptr_pg1(clk, reset, ~motor_on, ptr_stop_clr);
pa ptr_pa5(clk, reset, ~ptr_datai, ptr_busy_set); // CDG actually
wire ptr_clr;
pa ptr_pa6(clk, reset, ptr_busy, ptr_clr);
reg [36:31] ptr_sr; // actually 36,30,24,18,12,6
reg [35:0] ptr;
reg motor_on = 0;
wire ptr_lead;
wire ptr_mid; // mid hole, this is where the strobe happens.
// normally 400μs after leading edge of feed hole
wire ptr_strobe = ptr_mid & (~ptr_b | hole[8]);
wire ptr_trail;
assign iobus_iob_out =
ptr_datai ? ptr :
ptr_status ? { 27'b0, motor_on, 2'b0, ptr_b, ptr_busy, ptr_flag, ptr_pia } :
36'b0;
wire [1:7] ptr_req = { ptr_flag, 7'b0 } >> ptr_pia;
assign iobus_pi_req = ptr_req;
reg [33:35] ptr_pia;
reg ptr_busy;
reg ptr_flag;
reg ptr_b;
`ifdef simulation
initial begin
ptr_busy <= 0;
ptr_flag <= 0;
ptr_b <= 0;
end
`endif
always @(posedge clk) begin
if(ptr_ic_clr) begin
ptr_pia <= 0;
ptr_busy <= 0;
ptr_flag <= 0;
ptr_b <= 0;
end
if(ptr_ic_set) begin
ptr_pia <= iobus_iob_in[33:35];
if(iobus_iob_in[32])
ptr_flag <= 1;
if(iobus_iob_in[31])
ptr_busy <= 1;
if(iobus_iob_in[30])
ptr_b <= 1;
end
if(ptr_busy_set)
ptr_busy <= 1;
if(ptr_start_clr)
ptr_busy <= 0;
if(ptr_start_clr | ptr_stop_clr)
ptr_flag <= 1;
if(ptr_datai)
ptr_flag <= 0;
if(ptr_trail & ptr_busy & (~ptr_b | ptr_sr[36])) begin
ptr_busy <= 0;
ptr_flag <= 1;
end
if(ptr_clr) begin
ptr <= 0;
ptr_sr <= 0;
end
if(ptr_strobe) begin
ptr_sr <= { ptr_sr[35:31], 1'b1 };
ptr <= { ptr[29:0], 6'b0 } | stb_hole;
end
if(key_start)
motor_on <= 1;
if(key_stop | reset)
motor_on <= 0;
end
// front end interface
assign fe_data_rq = fe_req;
wire moving = motor_on & (key_tape_feed | ptr_busy);
reg fe_req; // requesting data from FE
reg fe_rs; // FE responded with data
reg [8:1] hole; // FE data
reg mid_sync; // set when mid hole
reg trail_sync; // set when trailing edge of feed hole would happen
wire start_signal = ~moving | ptr_trail;
wire start_pulse;
dly50ns fe_dly3(clk, reset, start_signal, start_pulse);
wire fe_mid_pulse, fe_trail_pulse;
`ifdef simulation
dly200ns fe_dly0(clk, reset, start_signal, ptr_lead);
dly800ns fe_dly1(clk, reset, start_signal, fe_mid_pulse);
dly1us fe_dly2(clk, reset, start_signal, fe_trail_pulse);
`else
dly1us fe_dly0(clk, reset, start_signal, ptr_lead);
dly2_1ms fe_dly1(clk, reset, start_signal, fe_mid_pulse);
dly2_5ms fe_dly2(clk, reset, start_signal, fe_trail_pulse);
`endif
pa fe_pa0(clk, reset, fe_rs & mid_sync & ptr_busy, ptr_mid);
pa fe_pa1(clk, reset, fe_rs & trail_sync, ptr_trail);
always @(posedge clk) begin
if(~moving | start_pulse) begin
fe_req <= 0;
fe_rs <= 0;
hole <= 0;
mid_sync <= 0;
trail_sync <= 0;
end
// start FE request
if(ptr_lead)
fe_req <= 1;
// got response from FE
if(s_write & fe_req) begin
hole <= s_writedata[7:0];
fe_req <= 0;
fe_rs <= 1;
end
if(fe_mid_pulse)
mid_sync <= 1;
if(fe_trail_pulse)
trail_sync <= 1;
// all done
if(ptr_trail)
fe_rs <= 0;
end
endmodule
|
//This module maps physical 512KB blocks of every memory chip to different memory ranges in Amiga
module minimig_bankmapper
(
input chip0, // chip ram select: 1st 512 KB block
input chip1, // chip ram select: 2nd 512 KB block
input chip2, // chip ram select: 3rd 512 KB block
input chip3, // chip ram select: 4th 512 KB block
input slow0, // slow ram select: 1st 512 KB block
input slow1, // slow ram select: 2nd 512 KB block
input slow2, // slow ram select: 3rd 512 KB block
input kick, // Kickstart ROM address range select
input kick1mb, // 1MB Kickstart 'upper' half
input cart, // Action Reply memory range select
input aron, // Action Reply enable
input ecs, // ECS chipset enable
input [3:0] memory_config,// memory configuration
output reg [7:0] bank // bank select
);
always @(*)
begin
case ({aron,memory_config})
5'b0_0000 : bank = { kick, kick1mb, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, chip3 | chip2 | chip1 | chip0 }; // 0.5M CHIP
5'b0_0001 : bank = { kick, kick1mb, 1'b0, 1'b0, 1'b0, 1'b0, chip3 | chip1, chip2 | chip0 }; // 1.0M CHIP
5'b0_0010 : bank = { kick, kick1mb, 1'b0, 1'b0, 1'b0, chip2, chip1, chip0 }; // 1.5M CHIP
5'b0_0011 : bank = { kick, kick1mb, 1'b0, 1'b0, chip3, chip2, chip1, chip0 }; // 2.0M CHIP
5'b0_0100 : bank = { kick, kick1mb, 1'b0, slow0, 1'b0, 1'b0, 1'b0, chip0 | (chip1 & !ecs) | chip2 | (chip3 & !ecs) }; // 0.5M CHIP + 0.5MB SLOW
5'b0_0101 : bank = { kick, kick1mb, 1'b0, slow0, 1'b0, 1'b0, chip3 | chip1, chip2 | chip0 }; // 1.0M CHIP + 0.5MB SLOW
5'b0_0110 : bank = { kick, kick1mb, 1'b0, slow0, 1'b0, chip2, chip1, chip0 }; // 1.5M CHIP + 0.5MB SLOW
5'b0_0111 : bank = { kick, kick1mb, 1'b0, slow0, chip3, chip2, chip1, chip0 }; // 2.0M CHIP + 0.5MB SLOW
5'b0_1000 : bank = { kick, kick1mb, slow1, slow0, 1'b0, 1'b0, 1'b0, chip3 | chip2 | chip1 | chip0 }; // 0.5M CHIP + 1.0MB SLOW
5'b0_1001 : bank = { kick, kick1mb, slow1, slow0, 1'b0, 1'b0, chip3 | chip1, chip2 | chip0 }; // 1.0M CHIP + 1.0MB SLOW
5'b0_1010 : bank = { kick, kick1mb, slow1, slow0, 1'b0, chip2, chip1, chip0 }; // 1.5M CHIP + 1.0MB SLOW
5'b0_1011 : bank = { kick, kick1mb, slow1, slow0, chip3, chip2, chip1, chip0 }; // 2.0M CHIP + 1.0MB SLOW
5'b0_1100 : bank = { kick, kick1mb, slow1, slow0, 1'b0, 1'b0, 1'b0, chip3 | chip2 | chip1 | chip0 }; // 0.5M CHIP + 1.5MB SLOW
5'b0_1101 : bank = { kick, kick1mb, slow1, slow0, 1'b0, 1'b0, chip3 | chip1, chip2 | chip0 }; // 1.0M CHIP + 1.5MB SLOW
5'b0_1110 : bank = { kick, kick1mb, slow1, slow0, 1'b0, chip2, chip1, chip0 }; // 1.5M CHIP + 1.5MB SLOW
5'b0_1111 : bank = { kick, kick1mb, slow1, slow0, chip3, chip2, chip1, chip0 }; // 2.0M CHIP + 1.5MB SLOW
5'b1_0000 : bank = { kick, kick1mb, cart, 1'b0, 1'b0, 1'b0, 1'b0, chip0 | chip1 | chip2 | chip3 }; // 0.5M CHIP
5'b1_0001 : bank = { kick, kick1mb, cart, 1'b0, 1'b0, 1'b0, chip1 | chip3, chip0 | chip2 }; // 1.0M CHIP
5'b1_0010 : bank = { kick, kick1mb, cart, 1'b0, 1'b0, chip2, chip1, chip0 }; // 1.5M CHIP
5'b1_0011 : bank = { kick, kick1mb, cart, 1'b0, chip3, chip2, chip1, chip0 }; // 2.0M CHIP
5'b1_0100 : bank = { kick, kick1mb, cart, slow0, 1'b0, 1'b0, 1'b0, chip0 | (chip1 & !ecs) | chip2 | (chip3 & !ecs) }; // 0.5M CHIP + 0.5MB SLOW
5'b1_0101 : bank = { kick, kick1mb, cart, slow0, 1'b0, 1'b0, chip1 | chip3, chip0 | chip2 }; // 1.0M CHIP + 0.5MB SLOW
5'b1_0110 : bank = { kick, kick1mb, cart, slow0, 1'b0, chip2, chip1, chip0 }; // 1.5M CHIP + 0.5MB SLOW
5'b1_0111 : bank = { kick, kick1mb, cart, slow0, chip3, chip2, chip1, chip0 }; // 2.0M CHIP + 0.5MB SLOW
5'b1_1000 : bank = { kick, kick1mb, cart, slow0, 1'b0, 1'b0, 1'b0, chip0 | chip1 | chip2 | chip3 }; // 0.5M CHIP + 1.0MB SLOW
5'b1_1001 : bank = { kick, kick1mb, cart, slow0, 1'b0, 1'b0, chip1 | chip3, chip0 | chip2 }; // 1.0M CHIP + 1.0MB SLOW
5'b1_1010 : bank = { kick, kick1mb, cart, slow0, 1'b0, chip2, chip1, chip0 }; // 1.5M CHIP + 1.0MB SLOW
5'b1_1011 : bank = { kick, kick1mb, cart, slow0, chip3, chip2, chip1, chip0 }; // 2.0M CHIP + 1.0MB SLOW
5'b1_1100 : bank = { kick, kick1mb, cart, slow0, 1'b0, 1'b0, 1'b0, chip0 | chip1 | chip2 | chip3 }; // 0.5M CHIP + 1.5MB SLOW
5'b1_1101 : bank = { kick, kick1mb, cart, slow0, 1'b0, 1'b0, chip1 | chip3, chip0 | chip2 }; // 1.0M CHIP + 1.5MB SLOW
5'b1_1110 : bank = { kick, kick1mb, cart, slow0, 1'b0, chip2, chip1, chip0 }; // 1.5M CHIP + 1.5MB SLOW
5'b1_1111 : bank = { kick, kick1mb, cart, slow0, chip3, chip2, chip1, chip0 }; // 2.0M CHIP + 1.5MB SLOW
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLCLKP_4_V
`define SKY130_FD_SC_HD__DLCLKP_4_V
/**
* dlclkp: Clock gate.
*
* Verilog wrapper for dlclkp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlclkp_4 (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlclkp_4 (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLCLKP_4_V
|
module anteconmutador (
input clk,
input [7:0] count,
input calculate,
output reg [3:0] centenas,
output reg [3:0] decenas,
output reg [3:0] unidades,
output reg C,
output reg De,
output reg U
);
reg [7:0] digitT;
reg i;
initial
begin
digitT = 0;
C = 0;
De = 0;
U = 0;
centenas = 0;
decenas = 0;
unidades = 0;
i = 1;
end
always@(posedge clk)
begin
if(calculate)
begin
if(i)
begin
digitT = count;
i = 0;
end
if(digitT>7'b1100011)
begin
digitT = digitT - 7'b1100100;
centenas = centenas + 1;
end
else
begin
if(digitT>7'b0001001)
begin
digitT = digitT - 7'b0001010;
decenas = decenas + 1;
end
else
begin
unidades = {digitT[3:0]};
if(centenas >= 1)
begin
C = 1;
end
if(decenas >= 1)
begin
De = 1;
end
if(unidades >= 1)
begin
U = 1;
end
end
end
end
else
begin
if(!calculate)
begin
digitT = 0;
C = 0;
De = 0;
U = 0;
i = 1;
centenas = 0;
decenas = 0;
unidades = 0;
end
end
end
endmodule
|
/* $Id: fasm_dpsram.v,v 1.3 2008/06/05 20:51:56 sybreon Exp $
**
** FASM MEMORY LIBRARY
** Copyright (C) 2004-2009 Shawn Tan <[email protected]>
** All rights reserved.
**
** FASM is free software: you can redistribute it and/or modify it
** under the terms of the GNU Lesser General Public License as
** published by the Free Software Foundation, either version 3 of the
** License, or (at your option) any later version.
**
** FASM is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
** Public License for more details.
**
** You should have received a copy of the GNU Lesser General Public
** License along with FASM. If not, see <http:**www.gnu.org/licenses/>.
*/
/*
* DUAL PORT SYNCHRONOUS RAM - WRITE-BEFORE-READ
* Synthesis proven on:
* - Xilinx ISE
* - Altera Quartus (>=8.0)
*/
module fasm_dpsram_wbr (/*AUTOARG*/
// Outputs
dat_o, xdat_o,
// Inputs
dat_i, adr_i, wre_i, stb_i, rst_i, clk_i, xdat_i, xadr_i, xwre_i,
xstb_i, xrst_i, xclk_i
);
parameter AW = 8; ///< address space (2^AW) words
parameter DW = 32; ///< data word width bits
// wishbone port a
output [DW-1:0] dat_o; // DO
input [DW-1:0] dat_i; // DI
input [AW-1:0] adr_i; // A
input wre_i; // WE
input stb_i; // CS
input rst_i,
clk_i;
// wishbone port x
output [DW-1:0] xdat_o; // DO
input [DW-1:0] xdat_i; // DI
input [AW-1:0] xadr_i; // A
input xwre_i; // WE
input xstb_i; // CS
input xrst_i,
xclk_i;
// address latch
reg [AW-1:0] rA, rX;
// memory block
reg [DW-1:0] bram [(1<<AW)-1:0];
always @(posedge xclk_i)
if (xstb_i)
begin
rX <= xadr_i;
if (xwre_i) // strobe and write-enable
bram[xadr_i] <= xdat_i;
end
always @(posedge clk_i)
if (stb_i)
begin
rA <= adr_i;
if (wre_i) // strobe and write-enable
bram[adr_i] <= dat_i;
end
assign xdat_o = bram[rX]; // write-thru
assign dat_o = bram[rA]; // write-thru
// ### SIMULATION ONLY ###
// synopsys translate_off
integer i;
initial begin
for (i=0; i<(1<<AW); i=i+1) begin
bram[i] <= $random;
end
end
// synopsys translate_on
endmodule // fasm_dpsram_wbr
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module LIST (
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [7 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [7 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *)
input wire clkb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *)
input wire [7 : 0] addrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *)
output wire [7 : 0] doutb;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(1),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INIT_FILE("LIST.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_READ_WIDTH_A(8),
.C_WRITE_DEPTH_A(256),
.C_READ_DEPTH_A(256),
.C_ADDRA_WIDTH(8),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(8),
.C_READ_WIDTH_B(8),
.C_WRITE_DEPTH_B(256),
.C_READ_DEPTH_B(256),
.C_ADDRB_WIDTH(8),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("0"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.68455 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(),
.clkb(clkb),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(addrb),
.dinb(8'B0),
.doutb(doutb),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(8'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 9
(* X_CORE_INFO = "axi_crossbar_v2_1_9_axi_crossbar,Vivado 2016.1" *)
(* CHECK_LICENSE_TYPE = "design_1_xbar_1,axi_crossbar_v2_1_9_axi_crossbar,{}" *)
(* CORE_GENERATION_INFO = "design_1_xbar_1,axi_crossbar_v2_1_9_axi_crossbar,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=zynq,C_NUM_SLAVE_SLOTS=2,C_NUM_MASTER_SLOTS=1,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_PROTOCOL=0,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x0000000000000000,C_M_AXI_ADDR_WIDTH=0x0000001e,C_S_AXI_BASE_ID=0x0000000100000000,C_S_AXI_THREAD_ID_WIDTH=0x00000000000000\
00,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x00000002,C_M_AXI_READ_CONNECTIVITY=0x00000001,C_R_REGISTER=0,C_S_AXI_SINGLE_THREAD=0x0000000000000000,C_S_AXI_WRITE_ACCEPTANCE=0x0000000200000002,C_S_AXI_READ_ACCEPTANCE=0x0000000200000002,C_M_AXI_WRITE_ISSUING=0x00000008,C_M_AXI_READ_ISSUING=0x00000008,C_S_AXI_ARB_PRIORITY=0x0000000000000000,C_M_AXI_SECURE=0x00000000,C_CONNECTIVITY_M\
ODE=1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xbar_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [31:0] [63:32]" *)
input wire [63 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLEN [7:0] [15:8]" *)
input wire [15 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE [2:0] [5:3]" *)
input wire [5 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWBURST [1:0] [3:2]" *)
input wire [3 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE [3:0] [7:4]" *)
input wire [7 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3]" *)
input wire [5 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWQOS [3:0] [7:4]" *)
input wire [7 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [63:0] [127:64]" *)
input wire [127 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [7:0] [15:8]" *)
input wire [15 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WLAST [0:0] [1:1]" *)
input wire [1 : 0] s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2]" *)
output wire [3 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1]" *)
input wire [1 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [31:0] [63:32]" *)
input wire [63 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLEN [7:0] [15:8]" *)
input wire [15 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE [2:0] [5:3]" *)
input wire [5 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARBURST [1:0] [3:2]" *)
input wire [3 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE [3:0] [7:4]" *)
input wire [7 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3]" *)
input wire [5 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARQOS [3:0] [7:4]" *)
input wire [7 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [63:0] [127:64]" *)
output wire [127 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2]" *)
output wire [3 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RLAST [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1]" *)
input wire [1 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWID" *)
output wire [0 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID" *)
output wire [0 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY" *)
input wire [0 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST" *)
output wire [0 : 0] m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID" *)
output wire [0 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY" *)
input wire [0 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BID" *)
input wire [0 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID" *)
input wire [0 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY" *)
output wire [0 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARID" *)
output wire [0 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID" *)
output wire [0 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY" *)
input wire [0 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RID" *)
input wire [0 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST" *)
input wire [0 : 0] m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID" *)
input wire [0 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY" *)
output wire [0 : 0] m_axi_rready;
axi_crossbar_v2_1_9_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(2),
.C_NUM_MASTER_SLOTS(1),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_PROTOCOL(0),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(64'H0000000000000000),
.C_M_AXI_ADDR_WIDTH(32'H0000001e),
.C_S_AXI_BASE_ID(64'H0000000100000000),
.C_S_AXI_THREAD_ID_WIDTH(64'H0000000000000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(32'H00000002),
.C_M_AXI_READ_CONNECTIVITY(32'H00000001),
.C_R_REGISTER(0),
.C_S_AXI_SINGLE_THREAD(64'H0000000000000000),
.C_S_AXI_WRITE_ACCEPTANCE(64'H0000000200000002),
.C_S_AXI_READ_ACCEPTANCE(64'H0000000200000002),
.C_M_AXI_WRITE_ISSUING(32'H00000008),
.C_M_AXI_READ_ISSUING(32'H00000008),
.C_S_AXI_ARB_PRIORITY(64'H0000000000000000),
.C_M_AXI_SECURE(32'H00000000),
.C_CONNECTIVITY_MODE(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(2'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(2'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(2'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(2'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_iface_address_to_bankaddress #(
parameter integer ADDRESS_W = 32, // > 0
parameter integer NUM_BANKS = 2, // > 1
parameter integer BANK_SEL_BIT = ADDRESS_W-$clog2(NUM_BANKS)
)
(
input logic [ADDRESS_W-1:0] address,
output logic [NUM_BANKS-1:0] bank_sel_1hot, // one-hot
output logic [$clog2(NUM_BANKS)-1:0] bank_sel_fe, // full encoded
output logic [ADDRESS_W-$clog2(NUM_BANKS)-1:0] bank_address
);
integer i;
// To support NUM_BANKS=1 we need a wider address
logic [ADDRESS_W:0] wider_address;
assign wider_address = {1'b0,address};
always@*
begin
for (i=0; i<NUM_BANKS; i=i+1)
bank_sel_1hot[i] = (wider_address[BANK_SEL_BIT+$clog2(NUM_BANKS)-1 : BANK_SEL_BIT] == i);
end
always@*
begin
bank_sel_fe = (wider_address>>BANK_SEL_BIT) & ~(64'b1<<$clog2(NUM_BANKS));
end
assign bank_address = ((address>>(BANK_SEL_BIT+$clog2(NUM_BANKS)))<<(BANK_SEL_BIT)) |
address[BANK_SEL_BIT-1:0];
endmodule
|
`timescale 1ns / 1ps
//------------------------------------------------
module UPCOUNTER_POSEDGE # (parameter SIZE=16)
(
input wire Clock, Reset,
input wire [SIZE-1:0] Initial,
input wire Enable,
output reg [SIZE-1:0] Q
);
always @(posedge Clock )
begin
if (Reset)
Q = Initial;
else
begin
if (Enable)
Q = Q + 1;
end
end
endmodule
//----------------------------------------------------
module mux (in0,in1,in2,in3, sel, out);
input wire [7:0] in0,in1,in2,in3;
input wire [1:0] sel;
output reg [7:0] out;
always @ (*)
begin
case (sel)
0: out<=in0;
1: out<=in1;
2: out<=in2;
3: out<=in3;
default: out<=0;
endcase
end
endmodule
//----------------------------------------------------
module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=8 )
(
input wire Clock,
input wire Reset,
input wire Enable,
input wire [SIZE-1:0] D,
output reg [SIZE-1:0] Q
);
always @ (posedge Clock)
begin
if ( Reset )
Q <= 0;
else
begin
if (Enable)
Q <= D;
end
end//always
endmodule
//----------------------------------------------------------------------
module FULL_ADDER (
input wire wA,wB,wCi,
output wire wR ,
output wire wCo
);
assign {wCo,wR} = wA + wB + wCi;
endmodule
//----------------------------------------------------------------------
module arrayMUL
(
input wire [3:0] A,
input wire [3:0] B,
output reg [7:0] out
);
reg rC1, rC2, rC3; //registros para los llevos
reg [2:0] rT1, rT2; //registros temporales
always @ (*) begin
//R0
out[0] =A[0] & B[0];
//R1
{rC1, out[1]} = (A[0] & B[1]) + (A[1] & B[0]);
//R2
{rC1, rT1[0]} = (A[2] & B[0]) + (A[1] & B[1]) + rC1;
{rC2, out[2]} = (A[0] & B[2]) + rT1[0];
//R3
{rC1, rT1[1]} = (A[3] & B[0]) + (A[2] & B[1]) + rC1;
{rC2, rT2[0]} = (A[1] & B[2]) + rT1[1] + rC2;
{rC3, out[3]} = (A[0] & B[3]) + rT2[0];
//R4
{rC1, rT1[2]} = (A[3] & B[1]) + rC1;
{rC2, rT2[1]} = (A[2] & B[2]) + rT1[2] + rC2;
{rC3, out[4]} = (A[1] & B[3]) + rT2[1] + rC3;
//R5
{rC2, rT2[2]} = (A[3] & B[2]) + rC2 + rC1;
{rC3, out[5]} = (A[2] & B[3]) + rT2[2] + rC3;
//R6 y R7.
{out[7], out[6]} = (A[3] & B[3]) + rC2 + rC3;
end
endmodule
//----------------------------------------------------------------------
module muxMUL (ia,ib,o);
input wire [3:0] ib,ia;
output [7:0] o;
wire [7:0] iaR,iaRA;
assign iaR=ia<<1; // A desplazado0 una posicion a la izquierda
assign iaRA=iaR+ia; // A desplazado una posicion a la izquierda mas A
mux mux0 (.in0(8'b0),.in1({4'b0,ia}),.in2(iaR),.in3(iaRA),.sel({ib[1],ib[0]}),.out(o0));
mux mux1 (.in0(8'b0),.in1({4'b0,ia}),.in2(iaR),.in3(iaRA),.sel({ib[3],ib[2]}),.out(o1));
wire [7:0] o0,o1;
wire [7:0] o1R ;
assign o1R=o1<<2; // Salida desplazada 2 posiciones a la izquierda
assign o = o0+o1R;
endmodule
//----------------------------------------------------------------------
module arrayMUL_GEN # (parameter SIZE = 4)(
input wire [SIZE-1:0] A,B,
output wire [(2*SIZE)-1:0] R
);
wire[(SIZE-1):0] wCarry[(SIZE-1):0], wResult[(SIZE-1):0];
genvar CurrentRow, CurrentCol;
generate
for ( CurrentCol = 0; CurrentCol < (SIZE); CurrentCol = CurrentCol + 1)
begin : MUL_COL
for ( CurrentRow =0; CurrentRow < SIZE; CurrentRow = CurrentRow + 1)
begin : MUL_ROW
FULL_ADDER # (SIZE) add
(
.wA((CurrentCol==0)?((CurrentRow<3)?(A[CurrentRow+1] & B[0])
:(1'b0)):((CurrentRow==3)?(wCarry[CurrentCol-1][CurrentRow])
:(wResult[CurrentCol-1][CurrentRow+1]))),
.wB(A[CurrentRow] & B[CurrentCol+1]),
.wCi((CurrentRow==0)?(1'b0):(wCarry[CurrentCol][CurrentRow-1])),
.wCo( wCarry[ CurrentCol ][ CurrentRow ]),
.wR ( wResult[ CurrentCol ][ CurrentRow ])
);
end
end
endgenerate
assign R = {wCarry[2][3],wResult[2][3],wResult[2][2],wResult[2][1],
wResult[2][0],wResult[1][0],wResult[0][0], A[0]&B[0]};
endmodule
//----------------------------------------------------------------------
|
/*
* Copyright (c) 2013-2014 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
`include "defines.v"
module stage1_fetch(
/* cpu global */
input clk_i,
input rst_i,
/* inter-stage */
input stall_i,
input take_branch_i,
input [29:0] branch_pc_i,
output [31:0] ir_o,
output [29:0] nextpc_o,
/* memory interface */
output reg re_o,
output [29:0] rmemaddr_o,
input [31:0] rmemdata_i
);
reg [29:0] pc;
initial begin
pc = 0;
end
assign nextpc_o = take_branch_i ? branch_pc_i : pc + 30'b1;
assign rmemaddr_o = nextpc_o;
assign ir_o = rmemdata_i;
always @(posedge clk_i)
begin
re_o = 0;
if (rst_i) begin
pc <= 30'b111111111111111111111111111111;
re_o = 1;
end else if (!stall_i) begin
pc <= nextpc_o;
re_o = 1;
end
end
endmodule // stage1_fetch
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2B_BEHAVIORAL_V
`define SKY130_FD_SC_LS__NOR2B_BEHAVIORAL_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nor2b (
Y ,
A ,
B_N
);
// Module ports
output Y ;
input A ;
input B_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire and0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y, not0_out, B_N );
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2B_BEHAVIORAL_V |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:system_ila:1.0
// IP Revision: 3
(* X_CORE_INFO = "bd_350b,Vivado 2017.2" *)
(* CHECK_LICENSE_TYPE = "zynq_design_1_system_ila_0,bd_350b,{}" *)
(* CORE_GENERATION_INFO = "zynq_design_1_system_ila_0,bd_350b,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=system_ila,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_TIME_TAG=0,C_TIME_TAG_WIDTH=32,C_SLOT=0,C_SLOT_15_TYPE=0,C_SLOT_14_TYPE=0,C_SLOT_13_TYPE=0,C_SLOT_12_TYPE=0,C_SLOT_11_TYPE=0,C_SLOT_10_TYPE=0,C_SLOT_9_TYPE=0,C_SLOT_8_TYPE=0,C_SLOT_7_TYPE=0,C_SLOT_6_TYPE=0,C_SLOT_5_TYPE=0,C_SLOT_4_TYPE=0,C_SLOT_3_TYPE=0,C_SLOT_2_TYPE=0,C_SLOT_1_TYPE=0,C_SLOT_0_TYP\
E=0,C_SLOT_0_MAX_RD_BURSTS=2,C_SLOT_0_MAX_WR_BURSTS=2,C_SLOT_1_MAX_RD_BURSTS=2,C_SLOT_1_MAX_WR_BURSTS=2,C_SLOT_2_MAX_RD_BURSTS=2,C_SLOT_2_MAX_WR_BURSTS=2,C_SLOT_3_MAX_RD_BURSTS=2,C_SLOT_3_MAX_WR_BURSTS=2,C_SLOT_4_MAX_RD_BURSTS=2,C_SLOT_4_MAX_WR_BURSTS=2,C_SLOT_5_MAX_RD_BURSTS=2,C_SLOT_5_MAX_WR_BURSTS=2,C_SLOT_6_MAX_RD_BURSTS=2,C_SLOT_6_MAX_WR_BURSTS=2,C_SLOT_7_MAX_RD_BURSTS=2,C_SLOT_7_MAX_WR_BURSTS=2,C_SLOT_8_MAX_RD_BURSTS=2,C_SLOT_8_MAX_WR_BURSTS=2,C_SLOT_9_MAX_RD_BURSTS=2,C_SLOT_9_MAX_WR_BURST\
S=2,C_SLOT_10_MAX_RD_BURSTS=2,C_SLOT_10_MAX_WR_BURSTS=2,C_SLOT_11_MAX_RD_BURSTS=2,C_SLOT_11_MAX_WR_BURSTS=2,C_SLOT_12_MAX_RD_BURSTS=2,C_SLOT_12_MAX_WR_BURSTS=2,C_SLOT_13_MAX_RD_BURSTS=2,C_SLOT_13_MAX_WR_BURSTS=2,C_SLOT_14_MAX_RD_BURSTS=2,C_SLOT_14_MAX_WR_BURSTS=2,C_SLOT_15_MAX_RD_BURSTS=2,C_SLOT_15_MAX_WR_BURSTS=2,C_SLOT_0_TXN_CNTR_EN=1,C_SLOT_1_TXN_CNTR_EN=1,C_SLOT_2_TXN_CNTR_EN=1,C_SLOT_3_TXN_CNTR_EN=1,C_SLOT_4_TXN_CNTR_EN=1,C_SLOT_5_TXN_CNTR_EN=1,C_SLOT_6_TXN_CNTR_EN=1,C_SLOT_7_TXN_CNTR_EN=1,\
C_SLOT_8_TXN_CNTR_EN=1,C_SLOT_9_TXN_CNTR_EN=1,C_SLOT_10_TXN_CNTR_EN=1,C_SLOT_11_TXN_CNTR_EN=1,C_SLOT_12_TXN_CNTR_EN=1,C_SLOT_13_TXN_CNTR_EN=1,C_SLOT_14_TXN_CNTR_EN=1,C_SLOT_15_TXN_CNTR_EN=1,C_SLOT_0_APC_STS_EN=0,C_SLOT_1_APC_STS_EN=0,C_SLOT_2_APC_STS_EN=0,C_SLOT_3_APC_STS_EN=0,C_SLOT_4_APC_STS_EN=0,C_SLOT_5_APC_STS_EN=0,C_SLOT_6_APC_STS_EN=0,C_SLOT_7_APC_STS_EN=0,C_SLOT_8_APC_STS_EN=0,C_SLOT_9_APC_STS_EN=0,C_SLOT_10_APC_STS_EN=0,C_SLOT_11_APC_STS_EN=0,C_SLOT_12_APC_STS_EN=0,C_SLOT_13_APC_STS_EN=\
0,C_SLOT_14_APC_STS_EN=0,C_SLOT_15_APC_STS_EN=0,C_SLOT_0_APC_EN=0,C_SLOT_1_APC_EN=0,C_SLOT_2_APC_EN=0,C_SLOT_3_APC_EN=0,C_SLOT_4_APC_EN=0,C_SLOT_5_APC_EN=0,C_SLOT_6_APC_EN=0,C_SLOT_7_APC_EN=0,C_SLOT_8_APC_EN=0,C_SLOT_9_APC_EN=0,C_SLOT_10_APC_EN=0,C_SLOT_11_APC_EN=0,C_SLOT_12_APC_EN=0,C_SLOT_13_APC_EN=0,C_SLOT_14_APC_EN=0,C_SLOT_15_APC_EN=0,C_BRAM_CNT=6.5,C_SLOT_0_AXI_AW_SEL_DATA=1,C_SLOT_0_AXI_W_SEL_DATA=1,C_SLOT_0_AXI_B_SEL_DATA=1,C_SLOT_0_AXI_AR_SEL_DATA=1,C_SLOT_0_AXI_R_SEL_DATA=1,C_SLOT_1_AX\
I_AW_SEL_DATA=1,C_SLOT_1_AXI_W_SEL_DATA=1,C_SLOT_1_AXI_B_SEL_DATA=1,C_SLOT_1_AXI_AR_SEL_DATA=1,C_SLOT_1_AXI_R_SEL_DATA=1,C_SLOT_2_AXI_AW_SEL_DATA=1,C_SLOT_2_AXI_W_SEL_DATA=1,C_SLOT_2_AXI_B_SEL_DATA=1,C_SLOT_2_AXI_AR_SEL_DATA=1,C_SLOT_2_AXI_R_SEL_DATA=1,C_SLOT_3_AXI_AW_SEL_DATA=1,C_SLOT_3_AXI_W_SEL_DATA=1,C_SLOT_3_AXI_B_SEL_DATA=1,C_SLOT_3_AXI_AR_SEL_DATA=1,C_SLOT_3_AXI_R_SEL_DATA=1,C_SLOT_4_AXI_AW_SEL_DATA=1,C_SLOT_4_AXI_W_SEL_DATA=1,C_SLOT_4_AXI_B_SEL_DATA=1,C_SLOT_4_AXI_AR_SEL_DATA=1,C_SLOT_4_\
AXI_R_SEL_DATA=1,C_SLOT_5_AXI_AW_SEL_DATA=1,C_SLOT_5_AXI_W_SEL_DATA=1,C_SLOT_5_AXI_B_SEL_DATA=1,C_SLOT_5_AXI_AR_SEL_DATA=1,C_SLOT_5_AXI_R_SEL_DATA=1,C_SLOT_6_AXI_AW_SEL_DATA=1,C_SLOT_6_AXI_W_SEL_DATA=1,C_SLOT_6_AXI_B_SEL_DATA=1,C_SLOT_6_AXI_AR_SEL_DATA=1,C_SLOT_6_AXI_R_SEL_DATA=1,C_SLOT_7_AXI_AW_SEL_DATA=1,C_SLOT_7_AXI_W_SEL_DATA=1,C_SLOT_7_AXI_B_SEL_DATA=1,C_SLOT_7_AXI_AR_SEL_DATA=1,C_SLOT_7_AXI_R_SEL_DATA=1,C_SLOT_8_AXI_AW_SEL_DATA=1,C_SLOT_8_AXI_W_SEL_DATA=1,C_SLOT_8_AXI_B_SEL_DATA=1,C_SLOT_8\
_AXI_AR_SEL_DATA=1,C_SLOT_8_AXI_R_SEL_DATA=1,C_SLOT_9_AXI_AW_SEL_DATA=1,C_SLOT_9_AXI_W_SEL_DATA=1,C_SLOT_9_AXI_B_SEL_DATA=1,C_SLOT_9_AXI_AR_SEL_DATA=1,C_SLOT_9_AXI_R_SEL_DATA=1,C_SLOT_10_AXI_AW_SEL_DATA=1,C_SLOT_10_AXI_W_SEL_DATA=1,C_SLOT_10_AXI_B_SEL_DATA=1,C_SLOT_10_AXI_AR_SEL_DATA=1,C_SLOT_10_AXI_R_SEL_DATA=1,C_SLOT_11_AXI_AW_SEL_DATA=1,C_SLOT_11_AXI_W_SEL_DATA=1,C_SLOT_11_AXI_B_SEL_DATA=1,C_SLOT_11_AXI_AR_SEL_DATA=1,C_SLOT_11_AXI_R_SEL_DATA=1,C_SLOT_12_AXI_AW_SEL_DATA=1,C_SLOT_12_AXI_W_SEL_D\
ATA=1,C_SLOT_12_AXI_B_SEL_DATA=1,C_SLOT_12_AXI_AR_SEL_DATA=1,C_SLOT_12_AXI_R_SEL_DATA=1,C_SLOT_13_AXI_AW_SEL_DATA=1,C_SLOT_13_AXI_W_SEL_DATA=1,C_SLOT_13_AXI_B_SEL_DATA=1,C_SLOT_13_AXI_AR_SEL_DATA=1,C_SLOT_13_AXI_R_SEL_DATA=1,C_SLOT_14_AXI_AW_SEL_DATA=1,C_SLOT_14_AXI_W_SEL_DATA=1,C_SLOT_14_AXI_B_SEL_DATA=1,C_SLOT_14_AXI_AR_SEL_DATA=1,C_SLOT_14_AXI_R_SEL_DATA=1,C_SLOT_15_AXI_AW_SEL_DATA=1,C_SLOT_15_AXI_W_SEL_DATA=1,C_SLOT_15_AXI_B_SEL_DATA=1,C_SLOT_15_AXI_AR_SEL_DATA=1,C_SLOT_15_AXI_R_SEL_DATA=1,C\
_SLOT_0_AXI_AW_SEL_TRIG=1,C_SLOT_0_AXI_W_SEL_TRIG=1,C_SLOT_0_AXI_B_SEL_TRIG=1,C_SLOT_0_AXI_AR_SEL_TRIG=1,C_SLOT_0_AXI_R_SEL_TRIG=1,C_SLOT_1_AXI_AW_SEL_TRIG=1,C_SLOT_1_AXI_W_SEL_TRIG=1,C_SLOT_1_AXI_B_SEL_TRIG=1,C_SLOT_1_AXI_AR_SEL_TRIG=1,C_SLOT_1_AXI_R_SEL_TRIG=1,C_SLOT_2_AXI_AW_SEL_TRIG=1,C_SLOT_2_AXI_W_SEL_TRIG=1,C_SLOT_2_AXI_B_SEL_TRIG=1,C_SLOT_2_AXI_AR_SEL_TRIG=1,C_SLOT_2_AXI_R_SEL_TRIG=1,C_SLOT_3_AXI_AW_SEL_TRIG=1,C_SLOT_3_AXI_W_SEL_TRIG=1,C_SLOT_3_AXI_B_SEL_TRIG=1,C_SLOT_3_AXI_AR_SEL_TRIG=1\
,C_SLOT_3_AXI_R_SEL_TRIG=1,C_SLOT_4_AXI_AW_SEL_TRIG=1,C_SLOT_4_AXI_W_SEL_TRIG=1,C_SLOT_4_AXI_B_SEL_TRIG=1,C_SLOT_4_AXI_AR_SEL_TRIG=1,C_SLOT_4_AXI_R_SEL_TRIG=1,C_SLOT_5_AXI_AW_SEL_TRIG=1,C_SLOT_5_AXI_W_SEL_TRIG=1,C_SLOT_5_AXI_B_SEL_TRIG=1,C_SLOT_5_AXI_AR_SEL_TRIG=1,C_SLOT_5_AXI_R_SEL_TRIG=1,C_SLOT_6_AXI_AW_SEL_TRIG=1,C_SLOT_6_AXI_W_SEL_TRIG=1,C_SLOT_6_AXI_B_SEL_TRIG=1,C_SLOT_6_AXI_AR_SEL_TRIG=1,C_SLOT_6_AXI_R_SEL_TRIG=1,C_SLOT_7_AXI_AW_SEL_TRIG=1,C_SLOT_7_AXI_W_SEL_TRIG=1,C_SLOT_7_AXI_B_SEL_TRIG=\
1,C_SLOT_7_AXI_AR_SEL_TRIG=1,C_SLOT_7_AXI_R_SEL_TRIG=1,C_SLOT_8_AXI_AW_SEL_TRIG=1,C_SLOT_8_AXI_W_SEL_TRIG=1,C_SLOT_8_AXI_B_SEL_TRIG=1,C_SLOT_8_AXI_AR_SEL_TRIG=1,C_SLOT_8_AXI_R_SEL_TRIG=1,C_SLOT_9_AXI_AW_SEL_TRIG=1,C_SLOT_9_AXI_W_SEL_TRIG=1,C_SLOT_9_AXI_B_SEL_TRIG=1,C_SLOT_9_AXI_AR_SEL_TRIG=1,C_SLOT_9_AXI_R_SEL_TRIG=1,C_SLOT_10_AXI_AW_SEL_TRIG=1,C_SLOT_10_AXI_W_SEL_TRIG=1,C_SLOT_10_AXI_B_SEL_TRIG=1,C_SLOT_10_AXI_AR_SEL_TRIG=1,C_SLOT_10_AXI_R_SEL_TRIG=1,C_SLOT_11_AXI_AW_SEL_TRIG=1,C_SLOT_11_AXI_W_\
SEL_TRIG=1,C_SLOT_11_AXI_B_SEL_TRIG=1,C_SLOT_11_AXI_AR_SEL_TRIG=1,C_SLOT_11_AXI_R_SEL_TRIG=1,C_SLOT_12_AXI_AW_SEL_TRIG=1,C_SLOT_12_AXI_W_SEL_TRIG=1,C_SLOT_12_AXI_B_SEL_TRIG=1,C_SLOT_12_AXI_AR_SEL_TRIG=1,C_SLOT_12_AXI_R_SEL_TRIG=1,C_SLOT_13_AXI_AW_SEL_TRIG=1,C_SLOT_13_AXI_W_SEL_TRIG=1,C_SLOT_13_AXI_B_SEL_TRIG=1,C_SLOT_13_AXI_AR_SEL_TRIG=1,C_SLOT_13_AXI_R_SEL_TRIG=1,C_SLOT_14_AXI_AW_SEL_TRIG=1,C_SLOT_14_AXI_W_SEL_TRIG=1,C_SLOT_14_AXI_B_SEL_TRIG=1,C_SLOT_14_AXI_AR_SEL_TRIG=1,C_SLOT_14_AXI_R_SEL_TRI\
G=1,C_SLOT_15_AXI_AW_SEL_TRIG=1,C_SLOT_15_AXI_W_SEL_TRIG=1,C_SLOT_15_AXI_B_SEL_TRIG=1,C_SLOT_15_AXI_AR_SEL_TRIG=1,C_SLOT_15_AXI_R_SEL_TRIG=1,C_SLOT_0_AXI_AW_SEL=1,C_SLOT_0_AXI_W_SEL=1,C_SLOT_0_AXI_B_SEL=1,C_SLOT_0_AXI_AR_SEL=1,C_SLOT_0_AXI_R_SEL=1,C_SLOT_1_AXI_AW_SEL=1,C_SLOT_1_AXI_W_SEL=1,C_SLOT_1_AXI_B_SEL=1,C_SLOT_1_AXI_AR_SEL=1,C_SLOT_1_AXI_R_SEL=1,C_SLOT_2_AXI_AW_SEL=1,C_SLOT_2_AXI_W_SEL=1,C_SLOT_2_AXI_B_SEL=1,C_SLOT_2_AXI_AR_SEL=1,C_SLOT_2_AXI_R_SEL=1,C_SLOT_3_AXI_AW_SEL=1,C_SLOT_3_AXI_W_S\
EL=1,C_SLOT_3_AXI_B_SEL=1,C_SLOT_3_AXI_AR_SEL=1,C_SLOT_3_AXI_R_SEL=1,C_SLOT_4_AXI_AW_SEL=1,C_SLOT_4_AXI_W_SEL=1,C_SLOT_4_AXI_B_SEL=1,C_SLOT_4_AXI_AR_SEL=1,C_SLOT_4_AXI_R_SEL=1,C_SLOT_5_AXI_AW_SEL=1,C_SLOT_5_AXI_W_SEL=1,C_SLOT_5_AXI_B_SEL=1,C_SLOT_5_AXI_AR_SEL=1,C_SLOT_5_AXI_R_SEL=1,C_SLOT_6_AXI_AW_SEL=1,C_SLOT_6_AXI_W_SEL=1,C_SLOT_6_AXI_B_SEL=1,C_SLOT_6_AXI_AR_SEL=1,C_SLOT_6_AXI_R_SEL=1,C_SLOT_7_AXI_AW_SEL=1,C_SLOT_7_AXI_W_SEL=1,C_SLOT_7_AXI_B_SEL=1,C_SLOT_7_AXI_AR_SEL=1,C_SLOT_7_AXI_R_SEL=1,C_S\
LOT_8_AXI_AW_SEL=1,C_SLOT_8_AXI_W_SEL=1,C_SLOT_8_AXI_B_SEL=1,C_SLOT_8_AXI_AR_SEL=1,C_SLOT_8_AXI_R_SEL=1,C_SLOT_9_AXI_AW_SEL=1,C_SLOT_9_AXI_W_SEL=1,C_SLOT_9_AXI_B_SEL=1,C_SLOT_9_AXI_AR_SEL=1,C_SLOT_9_AXI_R_SEL=1,C_SLOT_10_AXI_AW_SEL=1,C_SLOT_10_AXI_W_SEL=1,C_SLOT_10_AXI_B_SEL=1,C_SLOT_10_AXI_AR_SEL=1,C_SLOT_10_AXI_R_SEL=1,C_SLOT_11_AXI_AW_SEL=1,C_SLOT_11_AXI_W_SEL=1,C_SLOT_11_AXI_B_SEL=1,C_SLOT_11_AXI_AR_SEL=1,C_SLOT_11_AXI_R_SEL=1,C_SLOT_12_AXI_AW_SEL=1,C_SLOT_12_AXI_W_SEL=1,C_SLOT_12_AXI_B_SEL=\
1,C_SLOT_12_AXI_AR_SEL=1,C_SLOT_12_AXI_R_SEL=1,C_SLOT_13_AXI_AW_SEL=1,C_SLOT_13_AXI_W_SEL=1,C_SLOT_13_AXI_B_SEL=1,C_SLOT_13_AXI_AR_SEL=1,C_SLOT_13_AXI_R_SEL=1,C_SLOT_14_AXI_AW_SEL=1,C_SLOT_14_AXI_W_SEL=1,C_SLOT_14_AXI_B_SEL=1,C_SLOT_14_AXI_AR_SEL=1,C_SLOT_14_AXI_R_SEL=1,C_SLOT_15_AXI_AW_SEL=1,C_SLOT_15_AXI_W_SEL=1,C_SLOT_15_AXI_B_SEL=1,C_SLOT_15_AXI_AR_SEL=1,C_SLOT_15_AXI_R_SEL=1,C_SLOT_0_AXI_DATA_SEL=1,C_SLOT_1_AXI_DATA_SEL=1,C_SLOT_2_AXI_DATA_SEL=1,C_SLOT_3_AXI_DATA_SEL=1,C_SLOT_4_AXI_DATA_SEL\
=1,C_SLOT_5_AXI_DATA_SEL=1,C_SLOT_6_AXI_DATA_SEL=1,C_SLOT_7_AXI_DATA_SEL=1,C_SLOT_8_AXI_DATA_SEL=1,C_SLOT_9_AXI_DATA_SEL=1,C_SLOT_10_AXI_DATA_SEL=1,C_SLOT_11_AXI_DATA_SEL=1,C_SLOT_12_AXI_DATA_SEL=1,C_SLOT_13_AXI_DATA_SEL=1,C_SLOT_14_AXI_DATA_SEL=1,C_SLOT_15_AXI_DATA_SEL=1,C_SLOT_0_AXI_TRIG_SEL=1,C_SLOT_1_AXI_TRIG_SEL=1,C_SLOT_2_AXI_TRIG_SEL=1,C_SLOT_3_AXI_TRIG_SEL=1,C_SLOT_4_AXI_TRIG_SEL=1,C_SLOT_5_AXI_TRIG_SEL=1,C_SLOT_6_AXI_TRIG_SEL=1,C_SLOT_7_AXI_TRIG_SEL=1,C_SLOT_8_AXI_TRIG_SEL=1,C_SLOT_9_AX\
I_TRIG_SEL=1,C_SLOT_10_AXI_TRIG_SEL=1,C_SLOT_11_AXI_TRIG_SEL=1,C_SLOT_12_AXI_TRIG_SEL=1,C_SLOT_13_AXI_TRIG_SEL=1,C_SLOT_14_AXI_TRIG_SEL=1,C_SLOT_15_AXI_TRIG_SEL=1,C_PROBE1023_TYPE=0,C_PROBE1022_TYPE=0,C_PROBE1021_TYPE=0,C_PROBE1020_TYPE=0,C_PROBE1019_TYPE=0,C_PROBE1018_TYPE=0,C_PROBE1017_TYPE=0,C_PROBE1016_TYPE=0,C_PROBE1015_TYPE=0,C_PROBE1014_TYPE=0,C_PROBE1013_TYPE=0,C_PROBE1012_TYPE=0,C_PROBE1011_TYPE=0,C_PROBE1010_TYPE=0,C_PROBE1009_TYPE=0,C_PROBE1008_TYPE=0,C_PROBE1007_TYPE=0,C_PROBE1006_TY\
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DTH=1,C_PROBE656_WIDTH=1,C_PROBE655_WIDTH=1,C_PROBE654_WIDTH=1,C_PROBE653_WIDTH=1,C_PROBE652_WIDTH=1,C_PROBE651_WIDTH=1,C_PROBE650_WIDTH=1,C_PROBE649_WIDTH=1,C_PROBE648_WIDTH=1,C_PROBE647_WIDTH=1,C_PROBE646_WIDTH=1,C_PROBE645_WIDTH=1,C_PROBE644_WIDTH=1,C_PROBE643_WIDTH=1,C_PROBE642_WIDTH=1,C_PROBE641_WIDTH=1,C_PROBE640_WIDTH=1,C_PROBE639_WIDTH=1,C_PROBE638_WIDTH=1,C_PROBE637_WIDTH=1,C_PROBE636_WIDTH=1,C_PROBE635_WIDTH=1,C_PROBE634_WIDTH=1,C_PROBE633_WIDTH=1,C_PROBE632_WIDTH=1,C_PROBE631_WIDTH=1,\
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E604_WIDTH=1,C_PROBE603_WIDTH=1,C_PROBE602_WIDTH=1,C_PROBE601_WIDTH=1,C_PROBE600_WIDTH=1,C_PROBE599_WIDTH=1,C_PROBE598_WIDTH=1,C_PROBE597_WIDTH=1,C_PROBE596_WIDTH=1,C_PROBE595_WIDTH=1,C_PROBE594_WIDTH=1,C_PROBE593_WIDTH=1,C_PROBE592_WIDTH=1,C_PROBE591_WIDTH=1,C_PROBE590_WIDTH=1,C_PROBE589_WIDTH=1,C_PROBE588_WIDTH=1,C_PROBE587_WIDTH=1,C_PROBE586_WIDTH=1,C_PROBE585_WIDTH=1,C_PROBE584_WIDTH=1,C_PROBE583_WIDTH=1,C_PROBE582_WIDTH=1,C_PROBE581_WIDTH=1,C_PROBE580_WIDTH=1,C_PROBE579_WIDTH=1,C_PROBE578_W\
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BE525_WIDTH=1,C_PROBE524_WIDTH=1,C_PROBE523_WIDTH=1,C_PROBE522_WIDTH=1,C_PROBE521_WIDTH=1,C_PROBE520_WIDTH=1,C_PROBE519_WIDTH=1,C_PROBE518_WIDTH=1,C_PROBE517_WIDTH=1,C_PROBE516_WIDTH=1,C_PROBE515_WIDTH=1,C_PROBE514_WIDTH=1,C_PROBE513_WIDTH=1,C_PROBE512_WIDTH=1,C_PROBE511_WIDTH=1,C_PROBE510_WIDTH=1,C_PROBE509_WIDTH=1,C_PROBE508_WIDTH=1,C_PROBE507_WIDTH=1,C_PROBE506_WIDTH=1,C_PROBE505_WIDTH=1,C_PROBE504_WIDTH=1,C_PROBE503_WIDTH=1,C_PROBE502_WIDTH=1,C_PROBE501_WIDTH=1,C_PROBE500_WIDTH=1,C_PROBE499_\
WIDTH=1,C_PROBE498_WIDTH=1,C_PROBE497_WIDTH=1,C_PROBE496_WIDTH=1,C_PROBE495_WIDTH=1,C_PROBE494_WIDTH=1,C_PROBE493_WIDTH=1,C_PROBE492_WIDTH=1,C_PROBE491_WIDTH=1,C_PROBE490_WIDTH=1,C_PROBE489_WIDTH=1,C_PROBE488_WIDTH=1,C_PROBE487_WIDTH=1,C_PROBE486_WIDTH=1,C_PROBE485_WIDTH=1,C_PROBE484_WIDTH=1,C_PROBE483_WIDTH=1,C_PROBE482_WIDTH=1,C_PROBE481_WIDTH=1,C_PROBE480_WIDTH=1,C_PROBE479_WIDTH=1,C_PROBE478_WIDTH=1,C_PROBE477_WIDTH=1,C_PROBE476_WIDTH=1,C_PROBE475_WIDTH=1,C_PROBE474_WIDTH=1,C_PROBE473_WIDTH=\
1,C_PROBE472_WIDTH=1,C_PROBE471_WIDTH=1,C_PROBE470_WIDTH=1,C_PROBE469_WIDTH=1,C_PROBE468_WIDTH=1,C_PROBE467_WIDTH=1,C_PROBE466_WIDTH=1,C_PROBE465_WIDTH=1,C_PROBE464_WIDTH=1,C_PROBE463_WIDTH=1,C_PROBE462_WIDTH=1,C_PROBE461_WIDTH=1,C_PROBE460_WIDTH=1,C_PROBE459_WIDTH=1,C_PROBE458_WIDTH=1,C_PROBE457_WIDTH=1,C_PROBE456_WIDTH=1,C_PROBE455_WIDTH=1,C_PROBE454_WIDTH=1,C_PROBE453_WIDTH=1,C_PROBE452_WIDTH=1,C_PROBE451_WIDTH=1,C_PROBE450_WIDTH=1,C_PROBE449_WIDTH=1,C_PROBE448_WIDTH=1,C_PROBE447_WIDTH=1,C_PR\
OBE446_WIDTH=1,C_PROBE445_WIDTH=1,C_PROBE444_WIDTH=1,C_PROBE443_WIDTH=1,C_PROBE442_WIDTH=1,C_PROBE441_WIDTH=1,C_PROBE440_WIDTH=1,C_PROBE439_WIDTH=1,C_PROBE438_WIDTH=1,C_PROBE437_WIDTH=1,C_PROBE436_WIDTH=1,C_PROBE435_WIDTH=1,C_PROBE434_WIDTH=1,C_PROBE433_WIDTH=1,C_PROBE432_WIDTH=1,C_PROBE431_WIDTH=1,C_PROBE430_WIDTH=1,C_PROBE429_WIDTH=1,C_PROBE428_WIDTH=1,C_PROBE427_WIDTH=1,C_PROBE426_WIDTH=1,C_PROBE425_WIDTH=1,C_PROBE424_WIDTH=1,C_PROBE423_WIDTH=1,C_PROBE422_WIDTH=1,C_PROBE421_WIDTH=1,C_PROBE420\
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=1,C_PROBE393_WIDTH=1,C_PROBE392_WIDTH=1,C_PROBE391_WIDTH=1,C_PROBE390_WIDTH=1,C_PROBE389_WIDTH=1,C_PROBE388_WIDTH=1,C_PROBE387_WIDTH=1,C_PROBE386_WIDTH=1,C_PROBE385_WIDTH=1,C_PROBE384_WIDTH=1,C_PROBE383_WIDTH=1,C_PROBE382_WIDTH=1,C_PROBE381_WIDTH=1,C_PROBE380_WIDTH=1,C_PROBE379_WIDTH=1,C_PROBE378_WIDTH=1,C_PROBE377_WIDTH=1,C_PROBE376_WIDTH=1,C_PROBE375_WIDTH=1,C_PROBE374_WIDTH=1,C_PROBE373_WIDTH=1,C_PROBE372_WIDTH=1,C_PROBE371_WIDTH=1,C_PROBE370_WIDTH=1,C_PROBE369_WIDTH=1,C_PROBE368_WIDTH=1,C_P\
ROBE367_WIDTH=1,C_PROBE366_WIDTH=1,C_PROBE365_WIDTH=1,C_PROBE364_WIDTH=1,C_PROBE363_WIDTH=1,C_PROBE362_WIDTH=1,C_PROBE361_WIDTH=1,C_PROBE360_WIDTH=1,C_PROBE359_WIDTH=1,C_PROBE358_WIDTH=1,C_PROBE357_WIDTH=1,C_PROBE356_WIDTH=1,C_PROBE355_WIDTH=1,C_PROBE354_WIDTH=1,C_PROBE353_WIDTH=1,C_PROBE352_WIDTH=1,C_PROBE351_WIDTH=1,C_PROBE350_WIDTH=1,C_PROBE349_WIDTH=1,C_PROBE348_WIDTH=1,C_PROBE347_WIDTH=1,C_PROBE346_WIDTH=1,C_PROBE345_WIDTH=1,C_PROBE344_WIDTH=1,C_PROBE343_WIDTH=1,C_PROBE342_WIDTH=1,C_PROBE34\
1_WIDTH=1,C_PROBE340_WIDTH=1,C_PROBE339_WIDTH=1,C_PROBE338_WIDTH=1,C_PROBE337_WIDTH=1,C_PROBE336_WIDTH=1,C_PROBE335_WIDTH=1,C_PROBE334_WIDTH=1,C_PROBE333_WIDTH=1,C_PROBE332_WIDTH=1,C_PROBE331_WIDTH=1,C_PROBE330_WIDTH=1,C_PROBE329_WIDTH=1,C_PROBE328_WIDTH=1,C_PROBE327_WIDTH=1,C_PROBE326_WIDTH=1,C_PROBE325_WIDTH=1,C_PROBE324_WIDTH=1,C_PROBE323_WIDTH=1,C_PROBE322_WIDTH=1,C_PROBE321_WIDTH=1,C_PROBE320_WIDTH=1,C_PROBE319_WIDTH=1,C_PROBE318_WIDTH=1,C_PROBE317_WIDTH=1,C_PROBE316_WIDTH=1,C_PROBE315_WIDT\
H=1,C_PROBE314_WIDTH=1,C_PROBE313_WIDTH=1,C_PROBE312_WIDTH=1,C_PROBE311_WIDTH=1,C_PROBE310_WIDTH=1,C_PROBE309_WIDTH=1,C_PROBE308_WIDTH=1,C_PROBE307_WIDTH=1,C_PROBE306_WIDTH=1,C_PROBE305_WIDTH=1,C_PROBE304_WIDTH=1,C_PROBE303_WIDTH=1,C_PROBE302_WIDTH=1,C_PROBE301_WIDTH=1,C_PROBE300_WIDTH=1,C_PROBE299_WIDTH=1,C_PROBE298_WIDTH=1,C_PROBE297_WIDTH=1,C_PROBE296_WIDTH=1,C_PROBE295_WIDTH=1,C_PROBE294_WIDTH=1,C_PROBE293_WIDTH=1,C_PROBE292_WIDTH=1,C_PROBE291_WIDTH=1,C_PROBE290_WIDTH=1,C_PROBE289_WIDTH=1,C_\
PROBE288_WIDTH=1,C_PROBE287_WIDTH=1,C_PROBE286_WIDTH=1,C_PROBE285_WIDTH=1,C_PROBE284_WIDTH=1,C_PROBE283_WIDTH=1,C_PROBE282_WIDTH=1,C_PROBE281_WIDTH=1,C_PROBE280_WIDTH=1,C_PROBE279_WIDTH=1,C_PROBE278_WIDTH=1,C_PROBE277_WIDTH=1,C_PROBE276_WIDTH=1,C_PROBE275_WIDTH=1,C_PROBE274_WIDTH=1,C_PROBE273_WIDTH=1,C_PROBE272_WIDTH=1,C_PROBE271_WIDTH=1,C_PROBE270_WIDTH=1,C_PROBE269_WIDTH=1,C_PROBE268_WIDTH=1,C_PROBE267_WIDTH=1,C_PROBE266_WIDTH=1,C_PROBE265_WIDTH=1,C_PROBE264_WIDTH=1,C_PROBE263_WIDTH=1,C_PROBE2\
62_WIDTH=1,C_PROBE261_WIDTH=1,C_PROBE260_WIDTH=1,C_PROBE259_WIDTH=1,C_PROBE258_WIDTH=1,C_PROBE257_WIDTH=1,C_PROBE256_WIDTH=1,C_PROBE255_WIDTH=1,C_PROBE254_WIDTH=1,C_PROBE253_WIDTH=1,C_PROBE252_WIDTH=1,C_PROBE251_WIDTH=1,C_PROBE250_WIDTH=1,C_PROBE249_WIDTH=1,C_PROBE248_WIDTH=1,C_PROBE247_WIDTH=1,C_PROBE246_WIDTH=1,C_PROBE245_WIDTH=1,C_PROBE244_WIDTH=1,C_PROBE243_WIDTH=1,C_PROBE242_WIDTH=1,C_PROBE241_WIDTH=1,C_PROBE240_WIDTH=1,C_PROBE239_WIDTH=1,C_PROBE238_WIDTH=1,C_PROBE237_WIDTH=1,C_PROBE236_WID\
TH=1,C_PROBE235_WIDTH=1,C_PROBE234_WIDTH=1,C_PROBE233_WIDTH=1,C_PROBE232_WIDTH=1,C_PROBE231_WIDTH=1,C_PROBE230_WIDTH=1,C_PROBE229_WIDTH=1,C_PROBE228_WIDTH=1,C_PROBE227_WIDTH=1,C_PROBE226_WIDTH=1,C_PROBE225_WIDTH=1,C_PROBE224_WIDTH=1,C_PROBE223_WIDTH=1,C_PROBE222_WIDTH=1,C_PROBE221_WIDTH=1,C_PROBE220_WIDTH=1,C_PROBE219_WIDTH=1,C_PROBE218_WIDTH=1,C_PROBE217_WIDTH=1,C_PROBE216_WIDTH=1,C_PROBE215_WIDTH=1,C_PROBE214_WIDTH=1,C_PROBE213_WIDTH=1,C_PROBE212_WIDTH=1,C_PROBE211_WIDTH=1,C_PROBE210_WIDTH=1,C\
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183_WIDTH=1,C_PROBE182_WIDTH=1,C_PROBE181_WIDTH=1,C_PROBE180_WIDTH=1,C_PROBE179_WIDTH=1,C_PROBE178_WIDTH=1,C_PROBE177_WIDTH=1,C_PROBE176_WIDTH=1,C_PROBE175_WIDTH=1,C_PROBE174_WIDTH=1,C_PROBE173_WIDTH=1,C_PROBE172_WIDTH=1,C_PROBE171_WIDTH=1,C_PROBE170_WIDTH=1,C_PROBE169_WIDTH=1,C_PROBE168_WIDTH=1,C_PROBE167_WIDTH=1,C_PROBE166_WIDTH=1,C_PROBE165_WIDTH=1,C_PROBE164_WIDTH=1,C_PROBE163_WIDTH=1,C_PROBE162_WIDTH=1,C_PROBE161_WIDTH=1,C_PROBE160_WIDTH=1,C_PROBE159_WIDTH=1,C_PROBE158_WIDTH=1,C_PROBE157_WI\
DTH=1,C_PROBE156_WIDTH=1,C_PROBE155_WIDTH=1,C_PROBE154_WIDTH=1,C_PROBE153_WIDTH=1,C_PROBE152_WIDTH=1,C_PROBE151_WIDTH=1,C_PROBE150_WIDTH=1,C_PROBE149_WIDTH=1,C_PROBE148_WIDTH=1,C_PROBE147_WIDTH=1,C_PROBE146_WIDTH=1,C_PROBE145_WIDTH=1,C_PROBE144_WIDTH=1,C_PROBE143_WIDTH=1,C_PROBE142_WIDTH=1,C_PROBE141_WIDTH=1,C_PROBE140_WIDTH=1,C_PROBE139_WIDTH=1,C_PROBE138_WIDTH=1,C_PROBE137_WIDTH=1,C_PROBE136_WIDTH=1,C_PROBE135_WIDTH=1,C_PROBE134_WIDTH=1,C_PROBE133_WIDTH=1,C_PROBE132_WIDTH=1,C_PROBE131_WIDTH=1,\
C_PROBE130_WIDTH=1,C_PROBE129_WIDTH=1,C_PROBE128_WIDTH=1,C_PROBE127_WIDTH=1,C_PROBE126_WIDTH=1,C_PROBE125_WIDTH=1,C_PROBE124_WIDTH=1,C_PROBE123_WIDTH=1,C_PROBE122_WIDTH=1,C_PROBE121_WIDTH=1,C_PROBE120_WIDTH=1,C_PROBE119_WIDTH=1,C_PROBE118_WIDTH=1,C_PROBE117_WIDTH=1,C_PROBE116_WIDTH=1,C_PROBE115_WIDTH=1,C_PROBE114_WIDTH=1,C_PROBE113_WIDTH=1,C_PROBE112_WIDTH=1,C_PROBE111_WIDTH=1,C_PROBE110_WIDTH=1,C_PROBE109_WIDTH=1,C_PROBE108_WIDTH=1,C_PROBE107_WIDTH=1,C_PROBE106_WIDTH=1,C_PROBE105_WIDTH=1,C_PROB\
E104_WIDTH=1,C_PROBE103_WIDTH=1,C_PROBE102_WIDTH=1,C_PROBE101_WIDTH=1,C_PROBE100_WIDTH=1,C_PROBE99_WIDTH=1,C_PROBE98_WIDTH=1,C_PROBE97_WIDTH=1,C_PROBE96_WIDTH=1,C_PROBE95_WIDTH=1,C_PROBE94_WIDTH=1,C_PROBE93_WIDTH=1,C_PROBE92_WIDTH=1,C_PROBE91_WIDTH=1,C_PROBE90_WIDTH=1,C_PROBE89_WIDTH=1,C_PROBE88_WIDTH=1,C_PROBE87_WIDTH=1,C_PROBE86_WIDTH=1,C_PROBE85_WIDTH=1,C_PROBE84_WIDTH=1,C_PROBE83_WIDTH=1,C_PROBE82_WIDTH=1,C_PROBE81_WIDTH=1,C_PROBE80_WIDTH=1,C_PROBE79_WIDTH=1,C_PROBE78_WIDTH=1,C_PROBE77_WIDTH\
=1,C_PROBE76_WIDTH=1,C_PROBE75_WIDTH=1,C_PROBE74_WIDTH=1,C_PROBE73_WIDTH=1,C_PROBE72_WIDTH=1,C_PROBE71_WIDTH=1,C_PROBE69_WIDTH=1,C_PROBE68_WIDTH=1,C_PROBE67_WIDTH=1,C_PROBE66_WIDTH=1,C_PROBE65_WIDTH=1,C_PROBE64_WIDTH=1,C_PROBE63_WIDTH=1,C_PROBE62_WIDTH=1,C_PROBE61_WIDTH=1,C_PROBE60_WIDTH=1,C_PROBE59_WIDTH=1,C_PROBE58_WIDTH=1,C_PROBE57_WIDTH=1,C_PROBE56_WIDTH=1,C_PROBE55_WIDTH=1,C_PROBE54_WIDTH=1,C_PROBE53_WIDTH=1,C_PROBE52_WIDTH=1,C_PROBE51_WIDTH=1,C_PROBE50_WIDTH=1,C_PROBE49_WIDTH=1,C_PROBE48_W\
IDTH=1,C_PROBE47_WIDTH=1,C_PROBE46_WIDTH=1,C_PROBE45_WIDTH=1,C_PROBE44_WIDTH=1,C_PROBE43_WIDTH=1,C_PROBE42_WIDTH=1,C_PROBE41_WIDTH=1,C_PROBE40_WIDTH=1,C_PROBE39_WIDTH=1,C_PROBE38_WIDTH=1,C_PROBE37_WIDTH=1,C_PROBE36_WIDTH=1,C_PROBE35_WIDTH=1,C_PROBE34_WIDTH=1,C_PROBE33_WIDTH=1,C_PROBE32_WIDTH=1,C_PROBE31_WIDTH=1,C_PROBE30_WIDTH=1,C_PROBE29_WIDTH=1,C_PROBE28_WIDTH=1,C_PROBE27_WIDTH=1,C_PROBE26_WIDTH=1,C_PROBE25_WIDTH=1,C_PROBE24_WIDTH=1,C_PROBE23_WIDTH=1,C_PROBE22_WIDTH=1,C_PROBE21_WIDTH=1,C_PROBE\
20_WIDTH=1,C_PROBE19_WIDTH=1,C_PROBE18_WIDTH=1,C_PROBE17_WIDTH=1,C_PROBE16_WIDTH=1,C_PROBE15_WIDTH=1,C_PROBE14_WIDTH=1,C_PROBE13_WIDTH=1,C_PROBE12_WIDTH=1,C_PROBE11_WIDTH=1,C_PROBE10_WIDTH=1,C_PROBE9_WIDTH=1,C_PROBE8_WIDTH=1,C_PROBE7_WIDTH=1,C_PROBE6_WIDTH=1,C_PROBE5_WIDTH=1,C_PROBE4_WIDTH=1,C_PROBE3_WIDTH=1,C_PROBE2_WIDTH=1,C_PROBE1_WIDTH=1,C_PROBE0_WIDTH=1,C_DATA_DEPTH=1024,C_NUM_OF_PROBES=1,C_XLNX_HW_PROBE_INFO=DEFAULT,Component_Name=zynq_design_1_system_ila_0,C_PROBE70_WIDTH=1,C_TRIGOUT_EN=t\
rue,C_EN_STRG_QUAL=0,C_INPUT_PIPE_STAGES=0,C_DDR_CLK_GEN=FALSE,C_EN_DDR_ILA=FALSE,C_ADV_TRIGGER=FALSE,C_PROBE1023_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1009_MU_CNT=1,C_PROBE1008_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1005_MU_CNT=1\
,C_PROBE1004_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE980_MU_\
CNT=1,C_PROBE979_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE955_MU_\
CNT=1,C_PROBE954_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE930_MU_\
CNT=1,C_PROBE929_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE905_MU_\
CNT=1,C_PROBE904_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE880_MU_\
CNT=1,C_PROBE879_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE855_MU_\
CNT=1,C_PROBE854_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE830_MU_\
CNT=1,C_PROBE829_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE805_MU_\
CNT=1,C_PROBE804_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE780_MU_\
CNT=1,C_PROBE779_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE755_MU_\
CNT=1,C_PROBE754_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE730_MU_\
CNT=1,C_PROBE729_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE705_MU_\
CNT=1,C_PROBE704_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE680_MU_\
CNT=1,C_PROBE679_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE655_MU_\
CNT=1,C_PROBE654_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE630_MU_\
CNT=1,C_PROBE629_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE605_MU_\
CNT=1,C_PROBE604_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE580_MU_\
CNT=1,C_PROBE579_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE555_MU_\
CNT=1,C_PROBE554_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE530_MU_\
CNT=1,C_PROBE529_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE505_MU_\
CNT=1,C_PROBE504_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE480_MU_\
CNT=1,C_PROBE479_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE455_MU_\
CNT=1,C_PROBE454_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE430_MU_\
CNT=1,C_PROBE429_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE405_MU_\
CNT=1,C_PROBE404_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE380_MU_\
CNT=1,C_PROBE379_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE355_MU_\
CNT=1,C_PROBE354_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE330_MU_\
CNT=1,C_PROBE329_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE305_MU_\
CNT=1,C_PROBE304_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE280_MU_\
CNT=1,C_PROBE279_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE255_MU_\
CNT=1,C_PROBE254_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE230_MU_\
CNT=1,C_PROBE229_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE205_MU_\
CNT=1,C_PROBE204_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE180_MU_\
CNT=1,C_PROBE179_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE155_MU_\
CNT=1,C_PROBE154_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE130_MU_\
CNT=1,C_PROBE129_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE105_MU_\
CNT=1,C_PROBE104_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE79_MU_C\
NT=1,C_PROBE78_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE53_MU_CNT=1,C\
_PROBE52_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE30_MU_CNT=1,C_PROBE29_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE\
26_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PROBE3_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE0_MU_CNT=1,C_TR\
IGIN_EN=true,EN_BRAM_DRC=TRUE,ALL_PROBE_SAME_MU=TRUE,ALL_PROBE_SAME_MU_CNT=1,C_NUM_MONITOR_SLOTS=3,C_SLOT_0_AXI_ARUSER_WIDTH=1,C_SLOT_0_AXI_RUSER_WIDTH=1,C_SLOT_0_AXI_AWUSER_WIDTH=1,C_SLOT_0_AXI_WUSER_WIDTH=1,C_SLOT_0_AXI_BUSER_WIDTH=1,C_SLOT_0_AXI_ID_WIDTH=AUTO,C_SLOT_0_AXI_DATA_WIDTH=AUTO,C_SLOT_0_AXI_ADDR_WIDTH=AUTO,C_SLOT_0_AXI_PROTOCOL=AXI4,C_SLOT_0_AXIS_TDATA_WIDTH=AUTO,C_SLOT_0_AXIS_TID_WIDTH=AUTO,C_SLOT_0_AXIS_TUSER_WIDTH=AUTO,C_SLOT_0_AXIS_TDEST_WIDTH=AUTO,C_SLOT_1_AXI_ARUSER_WIDTH=1,C_\
SLOT_1_AXI_RUSER_WIDTH=1,C_SLOT_1_AXI_AWUSER_WIDTH=1,C_SLOT_1_AXI_WUSER_WIDTH=1,C_SLOT_1_AXI_BUSER_WIDTH=1,C_SLOT_1_AXI_ID_WIDTH=AUTO,C_SLOT_1_AXI_DATA_WIDTH=AUTO,C_SLOT_1_AXI_ADDR_WIDTH=AUTO,C_SLOT_1_AXI_PROTOCOL=AXI4,C_SLOT_1_AXIS_TDATA_WIDTH=AUTO,C_SLOT_1_AXIS_TID_WIDTH=AUTO,C_SLOT_1_AXIS_TUSER_WIDTH=AUTO,C_SLOT_1_AXIS_TDEST_WIDTH=AUTO,C_SLOT_0_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_1_INTF_TYPE=xilinx.com_interface_gpio_rtl_1.0,C_SLOT_2_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.\
0,C_SLOT_3_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_4_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_5_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_6_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_7_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_8_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_9_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_10_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_11_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_12_\
INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_13_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_14_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_15_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_MON_TYPE=INTERFACE,C_SLOT_2_AXI_ARUSER_WIDTH=1,C_SLOT_2_AXI_RUSER_WIDTH=1,C_SLOT_2_AXI_AWUSER_WIDTH=1,C_SLOT_2_AXI_WUSER_WIDTH=1,C_SLOT_2_AXI_BUSER_WIDTH=1,C_SLOT_2_AXI_ID_WIDTH=AUTO,C_SLOT_2_AXI_DATA_WIDTH=AUTO,C_SLOT_2_AXI_ADDR_WIDTH=AUTO,C_SLOT_2_AXI_PROTOCOL=AXI4,C_SLOT_2_AXIS_TDATA_\
WIDTH=AUTO,C_SLOT_2_AXIS_TID_WIDTH=AUTO,C_SLOT_2_AXIS_TUSER_WIDTH=AUTO,C_SLOT_2_AXIS_TDEST_WIDTH=AUTO,C_SLOT_3_AXI_ARUSER_WIDTH=1,C_SLOT_3_AXI_RUSER_WIDTH=1,C_SLOT_3_AXI_AWUSER_WIDTH=1,C_SLOT_3_AXI_WUSER_WIDTH=1,C_SLOT_3_AXI_BUSER_WIDTH=1,C_SLOT_3_AXI_ID_WIDTH=AUTO,C_SLOT_3_AXI_DATA_WIDTH=AUTO,C_SLOT_3_AXI_ADDR_WIDTH=AUTO,C_SLOT_3_AXI_PROTOCOL=AXI4,C_SLOT_3_AXIS_TDATA_WIDTH=AUTO,C_SLOT_3_AXIS_TID_WIDTH=AUTO,C_SLOT_3_AXIS_TUSER_WIDTH=AUTO,C_SLOT_3_AXIS_TDEST_WIDTH=AUTO,C_SLOT_4_AXI_ARUSER_WIDTH=1\
,C_SLOT_4_AXI_RUSER_WIDTH=1,C_SLOT_4_AXI_AWUSER_WIDTH=1,C_SLOT_4_AXI_WUSER_WIDTH=1,C_SLOT_4_AXI_BUSER_WIDTH=1,C_SLOT_4_AXI_ID_WIDTH=AUTO,C_SLOT_4_AXI_DATA_WIDTH=AUTO,C_SLOT_4_AXI_ADDR_WIDTH=AUTO,C_SLOT_4_AXI_PROTOCOL=AXI4,C_SLOT_4_AXIS_TDATA_WIDTH=AUTO,C_SLOT_4_AXIS_TID_WIDTH=AUTO,C_SLOT_4_AXIS_TUSER_WIDTH=AUTO,C_SLOT_4_AXIS_TDEST_WIDTH=AUTO,C_SLOT_5_AXI_ARUSER_WIDTH=1,C_SLOT_5_AXI_RUSER_WIDTH=1,C_SLOT_5_AXI_AWUSER_WIDTH=1,C_SLOT_5_AXI_WUSER_WIDTH=1,C_SLOT_5_AXI_BUSER_WIDTH=1,C_SLOT_5_AXI_ID_WID\
TH=AUTO,C_SLOT_5_AXI_DATA_WIDTH=AUTO,C_SLOT_5_AXI_ADDR_WIDTH=AUTO,C_SLOT_5_AXI_PROTOCOL=AXI4,C_SLOT_5_AXIS_TDATA_WIDTH=AUTO,C_SLOT_5_AXIS_TID_WIDTH=AUTO,C_SLOT_5_AXIS_TUSER_WIDTH=AUTO,C_SLOT_5_AXIS_TDEST_WIDTH=AUTO,C_SLOT_6_AXI_ARUSER_WIDTH=1,C_SLOT_6_AXI_RUSER_WIDTH=1,C_SLOT_6_AXI_AWUSER_WIDTH=1,C_SLOT_6_AXI_WUSER_WIDTH=1,C_SLOT_6_AXI_BUSER_WIDTH=1,C_SLOT_6_AXI_ID_WIDTH=AUTO,C_SLOT_6_AXI_DATA_WIDTH=AUTO,C_SLOT_6_AXI_ADDR_WIDTH=AUTO,C_SLOT_6_AXI_PROTOCOL=AXI4,C_SLOT_6_AXIS_TDATA_WIDTH=AUTO,C_SLO\
T_6_AXIS_TID_WIDTH=AUTO,C_SLOT_6_AXIS_TUSER_WIDTH=AUTO,C_SLOT_6_AXIS_TDEST_WIDTH=AUTO,C_SLOT_7_AXI_ARUSER_WIDTH=1,C_SLOT_7_AXI_RUSER_WIDTH=1,C_SLOT_7_AXI_AWUSER_WIDTH=1,C_SLOT_7_AXI_WUSER_WIDTH=1,C_SLOT_7_AXI_BUSER_WIDTH=1,C_SLOT_7_AXI_ID_WIDTH=AUTO,C_SLOT_7_AXI_DATA_WIDTH=AUTO,C_SLOT_7_AXI_ADDR_WIDTH=AUTO,C_SLOT_7_AXI_PROTOCOL=AXI4,C_SLOT_7_AXIS_TDATA_WIDTH=AUTO,C_SLOT_7_AXIS_TID_WIDTH=AUTO,C_SLOT_7_AXIS_TUSER_WIDTH=AUTO,C_SLOT_7_AXIS_TDEST_WIDTH=AUTO,C_SLOT_8_AXI_ARUSER_WIDTH=1,C_SLOT_8_AXI_RU\
SER_WIDTH=1,C_SLOT_8_AXI_AWUSER_WIDTH=1,C_SLOT_8_AXI_WUSER_WIDTH=1,C_SLOT_8_AXI_BUSER_WIDTH=1,C_SLOT_8_AXI_ID_WIDTH=AUTO,C_SLOT_8_AXI_DATA_WIDTH=AUTO,C_SLOT_8_AXI_ADDR_WIDTH=AUTO,C_SLOT_8_AXI_PROTOCOL=AXI4,C_SLOT_8_AXIS_TDATA_WIDTH=AUTO,C_SLOT_8_AXIS_TID_WIDTH=AUTO,C_SLOT_8_AXIS_TUSER_WIDTH=AUTO,C_SLOT_8_AXIS_TDEST_WIDTH=AUTO,C_SLOT_9_AXI_ARUSER_WIDTH=1,C_SLOT_9_AXI_RUSER_WIDTH=1,C_SLOT_9_AXI_AWUSER_WIDTH=1,C_SLOT_9_AXI_WUSER_WIDTH=1,C_SLOT_9_AXI_BUSER_WIDTH=1,C_SLOT_9_AXI_ID_WIDTH=AUTO,C_SLOT_9\
_AXI_DATA_WIDTH=AUTO,C_SLOT_9_AXI_ADDR_WIDTH=AUTO,C_SLOT_9_AXI_PROTOCOL=AXI4,C_SLOT_9_AXIS_TDATA_WIDTH=AUTO,C_SLOT_9_AXIS_TID_WIDTH=AUTO,C_SLOT_9_AXIS_TUSER_WIDTH=AUTO,C_SLOT_9_AXIS_TDEST_WIDTH=AUTO,C_SLOT_10_AXI_ARUSER_WIDTH=1,C_SLOT_10_AXI_RUSER_WIDTH=1,C_SLOT_10_AXI_AWUSER_WIDTH=1,C_SLOT_10_AXI_WUSER_WIDTH=1,C_SLOT_10_AXI_BUSER_WIDTH=1,C_SLOT_10_AXI_ID_WIDTH=AUTO,C_SLOT_10_AXI_DATA_WIDTH=AUTO,C_SLOT_10_AXI_ADDR_WIDTH=AUTO,C_SLOT_10_AXI_PROTOCOL=AXI4,C_SLOT_10_AXIS_TDATA_WIDTH=AUTO,C_SLOT_10_A\
XIS_TID_WIDTH=AUTO,C_SLOT_10_AXIS_TUSER_WIDTH=AUTO,C_SLOT_10_AXIS_TDEST_WIDTH=AUTO,C_SLOT_11_AXI_ARUSER_WIDTH=1,C_SLOT_11_AXI_RUSER_WIDTH=1,C_SLOT_11_AXI_AWUSER_WIDTH=1,C_SLOT_11_AXI_WUSER_WIDTH=1,C_SLOT_11_AXI_BUSER_WIDTH=1,C_SLOT_11_AXI_ID_WIDTH=AUTO,C_SLOT_11_AXI_DATA_WIDTH=AUTO,C_SLOT_11_AXI_ADDR_WIDTH=AUTO,C_SLOT_11_AXI_PROTOCOL=AXI4,C_SLOT_11_AXIS_TDATA_WIDTH=AUTO,C_SLOT_11_AXIS_TID_WIDTH=AUTO,C_SLOT_11_AXIS_TUSER_WIDTH=AUTO,C_SLOT_11_AXIS_TDEST_WIDTH=AUTO,C_SLOT_12_AXI_ARUSER_WIDTH=1,C_SL\
OT_12_AXI_RUSER_WIDTH=1,C_SLOT_12_AXI_AWUSER_WIDTH=1,C_SLOT_12_AXI_WUSER_WIDTH=1,C_SLOT_12_AXI_BUSER_WIDTH=1,C_SLOT_12_AXI_ID_WIDTH=AUTO,C_SLOT_12_AXI_DATA_WIDTH=AUTO,C_SLOT_12_AXI_ADDR_WIDTH=AUTO,C_SLOT_12_AXI_PROTOCOL=AXI4,C_SLOT_12_AXIS_TDATA_WIDTH=AUTO,C_SLOT_12_AXIS_TID_WIDTH=AUTO,C_SLOT_12_AXIS_TUSER_WIDTH=AUTO,C_SLOT_12_AXIS_TDEST_WIDTH=AUTO,C_SLOT_13_AXI_ARUSER_WIDTH=1,C_SLOT_13_AXI_RUSER_WIDTH=1,C_SLOT_13_AXI_AWUSER_WIDTH=1,C_SLOT_13_AXI_WUSER_WIDTH=1,C_SLOT_13_AXI_BUSER_WIDTH=1,C_SLOT_\
13_AXI_ID_WIDTH=AUTO,C_SLOT_13_AXI_DATA_WIDTH=AUTO,C_SLOT_13_AXI_ADDR_WIDTH=AUTO,C_SLOT_13_AXI_PROTOCOL=AXI4,C_SLOT_13_AXIS_TDATA_WIDTH=AUTO,C_SLOT_13_AXIS_TID_WIDTH=AUTO,C_SLOT_13_AXIS_TUSER_WIDTH=AUTO,C_SLOT_13_AXIS_TDEST_WIDTH=AUTO,C_SLOT_14_AXI_ARUSER_WIDTH=1,C_SLOT_14_AXI_RUSER_WIDTH=1,C_SLOT_14_AXI_AWUSER_WIDTH=1,C_SLOT_14_AXI_WUSER_WIDTH=1,C_SLOT_14_AXI_BUSER_WIDTH=1,C_SLOT_14_AXI_ID_WIDTH=AUTO,C_SLOT_14_AXI_DATA_WIDTH=AUTO,C_SLOT_14_AXI_ADDR_WIDTH=AUTO,C_SLOT_14_AXI_PROTOCOL=AXI4,C_SLOT_\
14_AXIS_TDATA_WIDTH=AUTO,C_SLOT_14_AXIS_TID_WIDTH=AUTO,C_SLOT_14_AXIS_TUSER_WIDTH=AUTO,C_SLOT_14_AXIS_TDEST_WIDTH=AUTO,C_SLOT_15_AXI_ARUSER_WIDTH=1,C_SLOT_15_AXI_RUSER_WIDTH=1,C_SLOT_15_AXI_AWUSER_WIDTH=1,C_SLOT_15_AXI_WUSER_WIDTH=1,C_SLOT_15_AXI_BUSER_WIDTH=1,C_SLOT_15_AXI_ID_WIDTH=AUTO,C_SLOT_15_AXI_DATA_WIDTH=AUTO,C_SLOT_15_AXI_ADDR_WIDTH=AUTO,C_SLOT_15_AXI_PROTOCOL=AXI4,C_SLOT_15_AXIS_TDATA_WIDTH=AUTO,C_SLOT_15_AXIS_TID_WIDTH=AUTO,C_SLOT_15_AXIS_TUSER_WIDTH=AUTO,C_SLOT_15_AXIS_TDEST_WIDTH=AU\
TO,C_PROBE_WIDTH_PROPAGATION=AUTO}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zynq_design_1_system_ila_0 (
clk,
SLOT_0_AXI_awaddr,
SLOT_0_AXI_awvalid,
SLOT_0_AXI_awready,
SLOT_0_AXI_wdata,
SLOT_0_AXI_wstrb,
SLOT_0_AXI_wvalid,
SLOT_0_AXI_wready,
SLOT_0_AXI_bresp,
SLOT_0_AXI_bvalid,
SLOT_0_AXI_bready,
SLOT_0_AXI_araddr,
SLOT_0_AXI_arvalid,
SLOT_0_AXI_arready,
SLOT_0_AXI_rdata,
SLOT_0_AXI_rresp,
SLOT_0_AXI_rvalid,
SLOT_0_AXI_rready,
SLOT_1_GPIO_tri_o,
SLOT_2_AXI_awid,
SLOT_2_AXI_awaddr,
SLOT_2_AXI_awlen,
SLOT_2_AXI_awsize,
SLOT_2_AXI_awburst,
SLOT_2_AXI_awlock,
SLOT_2_AXI_awcache,
SLOT_2_AXI_awprot,
SLOT_2_AXI_awqos,
SLOT_2_AXI_awvalid,
SLOT_2_AXI_awready,
SLOT_2_AXI_wdata,
SLOT_2_AXI_wstrb,
SLOT_2_AXI_wlast,
SLOT_2_AXI_wvalid,
SLOT_2_AXI_wready,
SLOT_2_AXI_bid,
SLOT_2_AXI_bresp,
SLOT_2_AXI_bvalid,
SLOT_2_AXI_bready,
SLOT_2_AXI_arid,
SLOT_2_AXI_araddr,
SLOT_2_AXI_arlen,
SLOT_2_AXI_arsize,
SLOT_2_AXI_arburst,
SLOT_2_AXI_arlock,
SLOT_2_AXI_arcache,
SLOT_2_AXI_arprot,
SLOT_2_AXI_arqos,
SLOT_2_AXI_arvalid,
SLOT_2_AXI_arready,
SLOT_2_AXI_rid,
SLOT_2_AXI_rdata,
SLOT_2_AXI_rresp,
SLOT_2_AXI_rlast,
SLOT_2_AXI_rvalid,
SLOT_2_AXI_rready,
resetn,
TRIG_IN_trig,
TRIG_IN_ack,
TRIG_OUT_trig,
TRIG_OUT_ack
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.clk CLK" *)
input wire clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWADDR" *)
input wire [8 : 0] SLOT_0_AXI_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWVALID" *)
input wire SLOT_0_AXI_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWREADY" *)
input wire SLOT_0_AXI_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WDATA" *)
input wire [31 : 0] SLOT_0_AXI_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WSTRB" *)
input wire [3 : 0] SLOT_0_AXI_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WVALID" *)
input wire SLOT_0_AXI_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WREADY" *)
input wire SLOT_0_AXI_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BRESP" *)
input wire [1 : 0] SLOT_0_AXI_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BVALID" *)
input wire SLOT_0_AXI_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BREADY" *)
input wire SLOT_0_AXI_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARADDR" *)
input wire [8 : 0] SLOT_0_AXI_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARVALID" *)
input wire SLOT_0_AXI_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARREADY" *)
input wire SLOT_0_AXI_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RDATA" *)
input wire [31 : 0] SLOT_0_AXI_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RRESP" *)
input wire [1 : 0] SLOT_0_AXI_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RVALID" *)
input wire SLOT_0_AXI_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RREADY" *)
input wire SLOT_0_AXI_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 SLOT_1_GPIO TRI_O" *)
input wire [7 : 0] SLOT_1_GPIO_tri_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI AWID" *)
input wire [11 : 0] SLOT_2_AXI_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI AWADDR" *)
input wire [15 : 0] SLOT_2_AXI_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI AWLEN" *)
input wire [7 : 0] SLOT_2_AXI_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI AWSIZE" *)
input wire [2 : 0] SLOT_2_AXI_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI AWBURST" *)
input wire [1 : 0] SLOT_2_AXI_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI AWLOCK" *)
input wire [0 : 0] SLOT_2_AXI_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI AWCACHE" *)
input wire [3 : 0] SLOT_2_AXI_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI AWPROT" *)
input wire [2 : 0] SLOT_2_AXI_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI AWQOS" *)
input wire [3 : 0] SLOT_2_AXI_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI AWVALID" *)
input wire SLOT_2_AXI_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI AWREADY" *)
input wire SLOT_2_AXI_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI WDATA" *)
input wire [31 : 0] SLOT_2_AXI_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI WSTRB" *)
input wire [3 : 0] SLOT_2_AXI_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI WLAST" *)
input wire SLOT_2_AXI_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI WVALID" *)
input wire SLOT_2_AXI_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI WREADY" *)
input wire SLOT_2_AXI_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI BID" *)
input wire [11 : 0] SLOT_2_AXI_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI BRESP" *)
input wire [1 : 0] SLOT_2_AXI_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI BVALID" *)
input wire SLOT_2_AXI_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI BREADY" *)
input wire SLOT_2_AXI_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI ARID" *)
input wire [11 : 0] SLOT_2_AXI_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI ARADDR" *)
input wire [15 : 0] SLOT_2_AXI_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI ARLEN" *)
input wire [7 : 0] SLOT_2_AXI_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI ARSIZE" *)
input wire [2 : 0] SLOT_2_AXI_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI ARBURST" *)
input wire [1 : 0] SLOT_2_AXI_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI ARLOCK" *)
input wire [0 : 0] SLOT_2_AXI_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI ARCACHE" *)
input wire [3 : 0] SLOT_2_AXI_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI ARPROT" *)
input wire [2 : 0] SLOT_2_AXI_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI ARQOS" *)
input wire [3 : 0] SLOT_2_AXI_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI ARVALID" *)
input wire SLOT_2_AXI_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI ARREADY" *)
input wire SLOT_2_AXI_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI RID" *)
input wire [11 : 0] SLOT_2_AXI_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI RDATA" *)
input wire [31 : 0] SLOT_2_AXI_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI RRESP" *)
input wire [1 : 0] SLOT_2_AXI_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI RLAST" *)
input wire SLOT_2_AXI_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI RVALID" *)
input wire SLOT_2_AXI_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_2_AXI RREADY" *)
input wire SLOT_2_AXI_rready;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.resetn RST" *)
input wire resetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:trigger:1.0 TRIG_IN TRIG" *)
input wire [0 : 0] TRIG_IN_trig;
(* X_INTERFACE_INFO = "xilinx.com:interface:trigger:1.0 TRIG_IN ACK" *)
output wire [0 : 0] TRIG_IN_ack;
(* X_INTERFACE_INFO = "xilinx.com:interface:trigger:1.0 TRIG_OUT TRIG" *)
output wire [0 : 0] TRIG_OUT_trig;
(* X_INTERFACE_INFO = "xilinx.com:interface:trigger:1.0 TRIG_OUT ACK" *)
input wire [0 : 0] TRIG_OUT_ack;
bd_350b inst (
.clk(clk),
.SLOT_0_AXI_awaddr(SLOT_0_AXI_awaddr),
.SLOT_0_AXI_awvalid(SLOT_0_AXI_awvalid),
.SLOT_0_AXI_awready(SLOT_0_AXI_awready),
.SLOT_0_AXI_wdata(SLOT_0_AXI_wdata),
.SLOT_0_AXI_wstrb(SLOT_0_AXI_wstrb),
.SLOT_0_AXI_wvalid(SLOT_0_AXI_wvalid),
.SLOT_0_AXI_wready(SLOT_0_AXI_wready),
.SLOT_0_AXI_bresp(SLOT_0_AXI_bresp),
.SLOT_0_AXI_bvalid(SLOT_0_AXI_bvalid),
.SLOT_0_AXI_bready(SLOT_0_AXI_bready),
.SLOT_0_AXI_araddr(SLOT_0_AXI_araddr),
.SLOT_0_AXI_arvalid(SLOT_0_AXI_arvalid),
.SLOT_0_AXI_arready(SLOT_0_AXI_arready),
.SLOT_0_AXI_rdata(SLOT_0_AXI_rdata),
.SLOT_0_AXI_rresp(SLOT_0_AXI_rresp),
.SLOT_0_AXI_rvalid(SLOT_0_AXI_rvalid),
.SLOT_0_AXI_rready(SLOT_0_AXI_rready),
.SLOT_1_GPIO_tri_o(SLOT_1_GPIO_tri_o),
.SLOT_2_AXI_awid(SLOT_2_AXI_awid),
.SLOT_2_AXI_awaddr(SLOT_2_AXI_awaddr),
.SLOT_2_AXI_awlen(SLOT_2_AXI_awlen),
.SLOT_2_AXI_awsize(SLOT_2_AXI_awsize),
.SLOT_2_AXI_awburst(SLOT_2_AXI_awburst),
.SLOT_2_AXI_awlock(SLOT_2_AXI_awlock),
.SLOT_2_AXI_awcache(SLOT_2_AXI_awcache),
.SLOT_2_AXI_awprot(SLOT_2_AXI_awprot),
.SLOT_2_AXI_awqos(SLOT_2_AXI_awqos),
.SLOT_2_AXI_awvalid(SLOT_2_AXI_awvalid),
.SLOT_2_AXI_awready(SLOT_2_AXI_awready),
.SLOT_2_AXI_wdata(SLOT_2_AXI_wdata),
.SLOT_2_AXI_wstrb(SLOT_2_AXI_wstrb),
.SLOT_2_AXI_wlast(SLOT_2_AXI_wlast),
.SLOT_2_AXI_wvalid(SLOT_2_AXI_wvalid),
.SLOT_2_AXI_wready(SLOT_2_AXI_wready),
.SLOT_2_AXI_bid(SLOT_2_AXI_bid),
.SLOT_2_AXI_bresp(SLOT_2_AXI_bresp),
.SLOT_2_AXI_bvalid(SLOT_2_AXI_bvalid),
.SLOT_2_AXI_bready(SLOT_2_AXI_bready),
.SLOT_2_AXI_arid(SLOT_2_AXI_arid),
.SLOT_2_AXI_araddr(SLOT_2_AXI_araddr),
.SLOT_2_AXI_arlen(SLOT_2_AXI_arlen),
.SLOT_2_AXI_arsize(SLOT_2_AXI_arsize),
.SLOT_2_AXI_arburst(SLOT_2_AXI_arburst),
.SLOT_2_AXI_arlock(SLOT_2_AXI_arlock),
.SLOT_2_AXI_arcache(SLOT_2_AXI_arcache),
.SLOT_2_AXI_arprot(SLOT_2_AXI_arprot),
.SLOT_2_AXI_arqos(SLOT_2_AXI_arqos),
.SLOT_2_AXI_arvalid(SLOT_2_AXI_arvalid),
.SLOT_2_AXI_arready(SLOT_2_AXI_arready),
.SLOT_2_AXI_rid(SLOT_2_AXI_rid),
.SLOT_2_AXI_rdata(SLOT_2_AXI_rdata),
.SLOT_2_AXI_rresp(SLOT_2_AXI_rresp),
.SLOT_2_AXI_rlast(SLOT_2_AXI_rlast),
.SLOT_2_AXI_rvalid(SLOT_2_AXI_rvalid),
.SLOT_2_AXI_rready(SLOT_2_AXI_rready),
.resetn(resetn),
.TRIG_IN_trig(TRIG_IN_trig),
.TRIG_IN_ack(TRIG_IN_ack),
.TRIG_OUT_trig(TRIG_OUT_trig),
.TRIG_OUT_ack(TRIG_OUT_ack)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRTP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DFRTP_PP_SYMBOL_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRTP_PP_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 1.7
// \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
// / / Filename : gtpa1_dual_wrapper_tile.v
// /___/ /\ Timestamp :
// \ \ / \
// \___\/\___\
//
//
// Module GTPA1_DUAL_WRAPPER_TILE (a GTPA1_DUAL Tile Wrapper)
// Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
//
//
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
`timescale 1ns / 1ps
//***************************** Entity Declaration ****************************
module GTPA1_DUAL_WRAPPER_TILE #(
// Simulation attributes
parameter TILE_SIM_GTPRESET_SPEEDUP = 0, // Set to 1 to speed up sim reset
parameter TILE_CLK25_DIVIDER_0 = 4,
parameter TILE_CLK25_DIVIDER_1 = 4,
parameter TILE_PLL_DIVSEL_FB_0 = 5,
parameter TILE_PLL_DIVSEL_FB_1 = 5,
parameter TILE_PLL_DIVSEL_REF_0 = 2,
parameter TILE_PLL_DIVSEL_REF_1 = 2,
//
parameter TILE_PLL_SOURCE_0 = "PLL0",
parameter TILE_PLL_SOURCE_1 = "PLL1"
)
(
//---------------------- Loopback and Powerdown Ports ----------------------
input [1:0] RXPOWERDOWN0_IN,
input [1:0] RXPOWERDOWN1_IN,
input [1:0] TXPOWERDOWN0_IN,
input [1:0] TXPOWERDOWN1_IN,
//------------------------------- PLL Ports --------------------------------
input CLK00_IN,
input CLK01_IN,
input GTPRESET0_IN,
input GTPRESET1_IN,
output PLLLKDET0_OUT,
output PLLLKDET1_OUT,
output RESETDONE0_OUT,
output RESETDONE1_OUT,
//--------------------- Receive Ports - 8b10b Decoder ----------------------
output [1:0] RXCHARISK0_OUT,
output [1:0] RXCHARISK1_OUT,
output [1:0] RXDISPERR0_OUT,
output [1:0] RXDISPERR1_OUT,
output [1:0] RXNOTINTABLE0_OUT,
output [1:0] RXNOTINTABLE1_OUT,
//-------------------- Receive Ports - Clock Correction --------------------
output [2:0] RXCLKCORCNT0_OUT,
output [2:0] RXCLKCORCNT1_OUT,
//------------- Receive Ports - Comma Detection and Alignment --------------
input RXENMCOMMAALIGN0_IN,
input RXENMCOMMAALIGN1_IN,
input RXENPCOMMAALIGN0_IN,
input RXENPCOMMAALIGN1_IN,
//----------------- Receive Ports - RX Data Path interface -----------------
output [15:0] RXDATA0_OUT,
output [15:0] RXDATA1_OUT,
input RXRESET0_IN,
input RXRESET1_IN,
input RXUSRCLK0_IN,
input RXUSRCLK1_IN,
input RXUSRCLK20_IN,
input RXUSRCLK21_IN,
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
input GATERXELECIDLE0_IN,
input GATERXELECIDLE1_IN,
input IGNORESIGDET0_IN,
input IGNORESIGDET1_IN,
output RXELECIDLE0_OUT,
output RXELECIDLE1_OUT,
input RXN0_IN,
input RXN1_IN,
input RXP0_IN,
input RXP1_IN,
//--------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
output [2:0] RXSTATUS0_OUT,
output [2:0] RXSTATUS1_OUT,
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
output PHYSTATUS0_OUT,
output PHYSTATUS1_OUT,
output RXVALID0_OUT,
output RXVALID1_OUT,
//------------------ Receive Ports - RX Polarity Control -------------------
input RXPOLARITY0_IN,
input RXPOLARITY1_IN,
//-------------------------- TX/RX Datapath Ports --------------------------
output [1:0] GTPCLKOUT0_OUT,
output [1:0] GTPCLKOUT1_OUT,
//----------------- Transmit Ports - 8b10b Encoder Control -----------------
input [1:0] TXCHARDISPMODE0_IN,
input [1:0] TXCHARDISPMODE1_IN,
input [1:0] TXCHARISK0_IN,
input [1:0] TXCHARISK1_IN,
//---------------- Transmit Ports - TX Data Path interface -----------------
input [15:0] TXDATA0_IN,
input [15:0] TXDATA1_IN,
input TXUSRCLK0_IN,
input TXUSRCLK1_IN,
input TXUSRCLK20_IN,
input TXUSRCLK21_IN,
//------------- Transmit Ports - TX Driver and OOB signalling --------------
output TXN0_OUT,
output TXN1_OUT,
output TXP0_OUT,
output TXP1_OUT,
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
input TXDETECTRX0_IN,
input TXDETECTRX1_IN,
input TXELECIDLE0_IN,
input TXELECIDLE1_IN,
input [1:0] rx_equalizer_ctrl,
input [3:0] tx_diff_ctrl,
input [2:0] tx_pre_emphasis
);
//***************************** Wire Declarations *****************************
// ground and vcc signals
wire tied_to_ground_i;
wire [63:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
wire [63:0] tied_to_vcc_vec_i;
//RX Datapath signals
wire [31:0] rxdata0_i;
wire [1:0] rxchariscomma0_float_i;
wire [1:0] rxcharisk0_float_i;
wire [1:0] rxdisperr0_float_i;
wire [1:0] rxnotintable0_float_i;
wire [1:0] rxrundisp0_float_i;
//TX Datapath signals
wire [31:0] txdata0_i;
wire [1:0] txkerr0_float_i;
wire [1:0] txrundisp0_float_i;
//RX Datapath signals
wire [31:0] rxdata1_i;
wire [1:0] rxchariscomma1_float_i;
wire [1:0] rxcharisk1_float_i;
wire [1:0] rxdisperr1_float_i;
wire [1:0] rxnotintable1_float_i;
wire [1:0] rxrundisp1_float_i;
//TX Datapath signals
wire [31:0] txdata1_i;
wire [1:0] txkerr1_float_i;
wire [1:0] txrundisp1_float_i;
//
//********************************* Main Body of Code**************************
//------------------------- Static signal Assigments ---------------------
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 64'h0000000000000000;
assign tied_to_vcc_i = 1'b1;
assign tied_to_vcc_vec_i = 64'hffffffffffffffff;
//------------------- GTP Datapath byte mapping -----------------
assign RXDATA0_OUT = rxdata0_i[15:0];
// The GTP transmits little endian data (TXDATA[7:0] transmitted first)
assign txdata0_i = {tied_to_ground_vec_i[15:0],TXDATA0_IN};
assign RXDATA1_OUT = rxdata1_i[15:0];
// The GTP transmits little endian data (TXDATA[7:0] transmitted first)
assign txdata1_i = {tied_to_ground_vec_i[15:0],TXDATA1_IN};
//------------------------ GTPA1_DUAL Instantiations -------------------------
GTPA1_DUAL #
(
//_______________________ Simulation-Only Attributes __________________
.SIM_TX_ELEC_IDLE_LEVEL ("Z"),
.SIM_RECEIVER_DETECT_PASS ("TRUE"),
.SIM_VERSION ("2.0"),
.SIM_REFCLK0_SOURCE (3'b000),
.SIM_REFCLK1_SOURCE (3'b000),
.SIM_GTPRESET_SPEEDUP (TILE_SIM_GTPRESET_SPEEDUP),
.CLK25_DIVIDER_0 (TILE_CLK25_DIVIDER_0),
.CLK25_DIVIDER_1 (TILE_CLK25_DIVIDER_1),
.PLL_DIVSEL_FB_0 (TILE_PLL_DIVSEL_FB_0),
.PLL_DIVSEL_FB_1 (TILE_PLL_DIVSEL_FB_1),
.PLL_DIVSEL_REF_0 (TILE_PLL_DIVSEL_REF_0),
.PLL_DIVSEL_REF_1 (TILE_PLL_DIVSEL_REF_1),
//PLL Attributes
.CLKINDC_B_0 ("TRUE"),
.CLKRCV_TRST_0 ("TRUE"),
.OOB_CLK_DIVIDER_0 (4),
.PLL_COM_CFG_0 (24'h21680a),
.PLL_CP_CFG_0 (8'h21),
.PLL_RXDIVSEL_OUT_0 (1),
.PLL_SATA_0 ("FALSE"),
.PLL_SOURCE_0 (TILE_PLL_SOURCE_0),
.PLL_TXDIVSEL_OUT_0 (1),
.PLLLKDET_CFG_0 (3'b111),
//
.CLKINDC_B_1 ("TRUE"),
.CLKRCV_TRST_1 ("TRUE"),
.OOB_CLK_DIVIDER_1 (4),
.PLL_COM_CFG_1 (24'h21680a),
.PLL_CP_CFG_1 (8'h21),
.PLL_RXDIVSEL_OUT_1 (1),
.PLL_SATA_1 ("FALSE"),
.PLL_SOURCE_1 (TILE_PLL_SOURCE_1),
.PLL_TXDIVSEL_OUT_1 (1),
.PLLLKDET_CFG_1 (3'b111),
.PMA_COM_CFG_EAST (36'h000008000),
.PMA_COM_CFG_WEST (36'h00000a000),
.TST_ATTR_0 (32'h00000000),
.TST_ATTR_1 (32'h00000000),
//TX Interface Attributes
.CLK_OUT_GTP_SEL_0 ("REFCLKPLL0"),
.TX_TDCC_CFG_0 (2'b11),
.CLK_OUT_GTP_SEL_1 ("REFCLKPLL1"),
.TX_TDCC_CFG_1 (2'b11),
//TX Buffer and Phase Alignment Attributes
.PMA_TX_CFG_0 (20'h00082),
.TX_BUFFER_USE_0 ("TRUE"),
.TX_XCLK_SEL_0 ("TXOUT"),
.TXRX_INVERT_0 (3'b011),
.PMA_TX_CFG_1 (20'h00082),
.TX_BUFFER_USE_1 ("TRUE"),
.TX_XCLK_SEL_1 ("TXOUT"),
.TXRX_INVERT_1 (3'b011),
//TX Driver and OOB signalling Attributes
.CM_TRIM_0 (2'b00),
.TX_IDLE_DELAY_0 (3'b010),
.CM_TRIM_1 (2'b00),
.TX_IDLE_DELAY_1 (3'b010),
//TX PIPE/SATA Attributes
.COM_BURST_VAL_0 (4'b1111),
.COM_BURST_VAL_1 (4'b1111),
//RX Driver,OOB signalling,Coupling and Eq,CDR Attributes
.AC_CAP_DIS_0 ("FALSE"),
.OOBDETECT_THRESHOLD_0 (3'b111),
.PMA_CDR_SCAN_0 (27'h6404040),
.PMA_RX_CFG_0 (25'h05CE044),
.PMA_RXSYNC_CFG_0 (7'h00),
.RCV_TERM_GND_0 ("TRUE"),
.RCV_TERM_VTTRX_0 ("FALSE"),
.RXEQ_CFG_0 (8'b01111011),
.TERMINATION_CTRL_0 (5'b10100),
.TERMINATION_OVRD_0 ("FALSE"),
.TX_DETECT_RX_CFG_0 (14'h1832),
.AC_CAP_DIS_1 ("FALSE"),
.OOBDETECT_THRESHOLD_1 (3'b111),
.PMA_CDR_SCAN_1 (27'h6404040),
.PMA_RX_CFG_1 (25'h05CE044),
.PMA_RXSYNC_CFG_1 (7'h00),
.RCV_TERM_GND_1 ("TRUE"),
.RCV_TERM_VTTRX_1 ("FALSE"),
.RXEQ_CFG_1 (8'b01111011),
.TERMINATION_CTRL_1 (5'b10100),
.TERMINATION_OVRD_1 ("FALSE"),
.TX_DETECT_RX_CFG_1 (14'h1832),
//PRBS Detection Attributes
.RXPRBSERR_LOOPBACK_0 (1'b0),
.RXPRBSERR_LOOPBACK_1 (1'b0),
//Comma Detection and Alignment Attributes
.ALIGN_COMMA_WORD_0 (1),
.COMMA_10B_ENABLE_0 (10'b1111111111),
.DEC_MCOMMA_DETECT_0 ("TRUE"),
.DEC_PCOMMA_DETECT_0 ("TRUE"),
.DEC_VALID_COMMA_ONLY_0 ("TRUE"),
.MCOMMA_10B_VALUE_0 (10'b1010000011),
.MCOMMA_DETECT_0 ("TRUE"),
.PCOMMA_10B_VALUE_0 (10'b0101111100),
.PCOMMA_DETECT_0 ("TRUE"),
.RX_SLIDE_MODE_0 ("PCS"),
.ALIGN_COMMA_WORD_1 (1),
.COMMA_10B_ENABLE_1 (10'b1111111111),
.DEC_MCOMMA_DETECT_1 ("TRUE"),
.DEC_PCOMMA_DETECT_1 ("TRUE"),
.DEC_VALID_COMMA_ONLY_1 ("TRUE"),
.MCOMMA_10B_VALUE_1 (10'b1010000011),
.MCOMMA_DETECT_1 ("TRUE"),
.PCOMMA_10B_VALUE_1 (10'b0101111100),
.PCOMMA_DETECT_1 ("TRUE"),
.RX_SLIDE_MODE_1 ("PCS"),
//RX Loss-of-sync State Machine Attributes
.RX_LOS_INVALID_INCR_0 (8),
.RX_LOS_THRESHOLD_0 (128),
.RX_LOSS_OF_SYNC_FSM_0 ("FALSE"),
.RX_LOS_INVALID_INCR_1 (8),
.RX_LOS_THRESHOLD_1 (128),
.RX_LOSS_OF_SYNC_FSM_1 ("FALSE"),
//RX Elastic Buffer and Phase alignment Attributes
.RX_BUFFER_USE_0 ("TRUE"),
.RX_EN_IDLE_RESET_BUF_0 ("TRUE"),
.RX_IDLE_HI_CNT_0 (4'b1000),
.RX_IDLE_LO_CNT_0 (4'b0000),
.RX_XCLK_SEL_0 ("RXREC"),
.RX_BUFFER_USE_1 ("TRUE"),
.RX_EN_IDLE_RESET_BUF_1 ("TRUE"),
.RX_IDLE_HI_CNT_1 (4'b1000),
.RX_IDLE_LO_CNT_1 (4'b0000),
.RX_XCLK_SEL_1 ("RXREC"),
//Clock Correction Attributes
.CLK_COR_ADJ_LEN_0 (1),
.CLK_COR_DET_LEN_0 (1),
.CLK_COR_INSERT_IDLE_FLAG_0 ("FALSE"),
.CLK_COR_KEEP_IDLE_0 ("FALSE"),
.CLK_COR_MAX_LAT_0 (20),
.CLK_COR_MIN_LAT_0 (18),
.CLK_COR_PRECEDENCE_0 ("TRUE"),
.CLK_COR_REPEAT_WAIT_0 (0),
.CLK_COR_SEQ_1_1_0 (10'b0100011100),
.CLK_COR_SEQ_1_2_0 (10'b0000000000),
.CLK_COR_SEQ_1_3_0 (10'b0000000000),
.CLK_COR_SEQ_1_4_0 (10'b0000000000),
.CLK_COR_SEQ_1_ENABLE_0 (4'b0001),
.CLK_COR_SEQ_2_1_0 (10'b0000000000),
.CLK_COR_SEQ_2_2_0 (10'b0000000000),
.CLK_COR_SEQ_2_3_0 (10'b0000000000),
.CLK_COR_SEQ_2_4_0 (10'b0000000000),
.CLK_COR_SEQ_2_ENABLE_0 (4'b0000),
.CLK_COR_SEQ_2_USE_0 ("FALSE"),
.CLK_CORRECT_USE_0 ("TRUE"),
.RX_DECODE_SEQ_MATCH_0 ("TRUE"),
.CLK_COR_ADJ_LEN_1 (1),
.CLK_COR_DET_LEN_1 (1),
.CLK_COR_INSERT_IDLE_FLAG_1 ("FALSE"),
.CLK_COR_KEEP_IDLE_1 ("FALSE"),
.CLK_COR_MAX_LAT_1 (20),
.CLK_COR_MIN_LAT_1 (18),
.CLK_COR_PRECEDENCE_1 ("TRUE"),
.CLK_COR_REPEAT_WAIT_1 (0),
.CLK_COR_SEQ_1_1_1 (10'b0100011100),
.CLK_COR_SEQ_1_2_1 (10'b0000000000),
.CLK_COR_SEQ_1_3_1 (10'b0000000000),
.CLK_COR_SEQ_1_4_1 (10'b0000000000),
.CLK_COR_SEQ_1_ENABLE_1 (4'b0001),
.CLK_COR_SEQ_2_1_1 (10'b0000000000),
.CLK_COR_SEQ_2_2_1 (10'b0000000000),
.CLK_COR_SEQ_2_3_1 (10'b0000000000),
.CLK_COR_SEQ_2_4_1 (10'b0000000000),
.CLK_COR_SEQ_2_ENABLE_1 (4'b0000),
.CLK_COR_SEQ_2_USE_1 ("FALSE"),
.CLK_CORRECT_USE_1 ("TRUE"),
.RX_DECODE_SEQ_MATCH_1 ("TRUE"),
//Channel Bonding Attributes
.CHAN_BOND_1_MAX_SKEW_0 (1),
.CHAN_BOND_2_MAX_SKEW_0 (1),
.CHAN_BOND_KEEP_ALIGN_0 ("FALSE"),
.CHAN_BOND_SEQ_1_1_0 (10'b0001001010),
.CHAN_BOND_SEQ_1_2_0 (10'b0001001010),
.CHAN_BOND_SEQ_1_3_0 (10'b0001001010),
.CHAN_BOND_SEQ_1_4_0 (10'b0110111100),
.CHAN_BOND_SEQ_1_ENABLE_0 (4'b0000),
.CHAN_BOND_SEQ_2_1_0 (10'b0100111100),
.CHAN_BOND_SEQ_2_2_0 (10'b0100111100),
.CHAN_BOND_SEQ_2_3_0 (10'b0110111100),
.CHAN_BOND_SEQ_2_4_0 (10'b0100011100),
.CHAN_BOND_SEQ_2_ENABLE_0 (4'b0000),
.CHAN_BOND_SEQ_2_USE_0 ("FALSE"),
.CHAN_BOND_SEQ_LEN_0 (1),
.RX_EN_MODE_RESET_BUF_0 ("TRUE"),
.CHAN_BOND_1_MAX_SKEW_1 (1),
.CHAN_BOND_2_MAX_SKEW_1 (1),
.CHAN_BOND_KEEP_ALIGN_1 ("FALSE"),
.CHAN_BOND_SEQ_1_1_1 (10'b0001001010),
.CHAN_BOND_SEQ_1_2_1 (10'b0001001010),
.CHAN_BOND_SEQ_1_3_1 (10'b0001001010),
.CHAN_BOND_SEQ_1_4_1 (10'b0110111100),
.CHAN_BOND_SEQ_1_ENABLE_1 (4'b0000),
.CHAN_BOND_SEQ_2_1_1 (10'b0100111100),
.CHAN_BOND_SEQ_2_2_1 (10'b0100111100),
.CHAN_BOND_SEQ_2_3_1 (10'b0110111100),
.CHAN_BOND_SEQ_2_4_1 (10'b0100011100),
.CHAN_BOND_SEQ_2_ENABLE_1 (4'b0000),
.CHAN_BOND_SEQ_2_USE_1 ("FALSE"),
.CHAN_BOND_SEQ_LEN_1 (1),
.RX_EN_MODE_RESET_BUF_1 ("TRUE"),
//RX PCI Express Attributes
.CB2_INH_CC_PERIOD_0 (8),
.CDR_PH_ADJ_TIME_0 (5'b01010),
.PCI_EXPRESS_MODE_0 ("TRUE"),
.RX_EN_IDLE_HOLD_CDR_0 ("TRUE"),
.RX_EN_IDLE_RESET_FR_0 ("TRUE"),
.RX_EN_IDLE_RESET_PH_0 ("TRUE"),
.RX_STATUS_FMT_0 ("PCIE"),
.TRANS_TIME_FROM_P2_0 (12'h03c),
.TRANS_TIME_NON_P2_0 (8'h19),
.TRANS_TIME_TO_P2_0 (10'h064),
.CB2_INH_CC_PERIOD_1 (8),
.CDR_PH_ADJ_TIME_1 (5'b01010),
.PCI_EXPRESS_MODE_1 ("TRUE"),
.RX_EN_IDLE_HOLD_CDR_1 ("TRUE"),
.RX_EN_IDLE_RESET_FR_1 ("TRUE"),
.RX_EN_IDLE_RESET_PH_1 ("TRUE"),
.RX_STATUS_FMT_1 ("PCIE"),
.TRANS_TIME_FROM_P2_1 (12'h03c),
.TRANS_TIME_NON_P2_1 (8'h19),
.TRANS_TIME_TO_P2_1 (10'h064),
//RX SATA Attributes
.SATA_BURST_VAL_0 (3'b100),
.SATA_IDLE_VAL_0 (3'b100),
.SATA_MAX_BURST_0 (7),
.SATA_MAX_INIT_0 (22),
.SATA_MAX_WAKE_0 (7),
.SATA_MIN_BURST_0 (4),
.SATA_MIN_INIT_0 (12),
.SATA_MIN_WAKE_0 (4),
.SATA_BURST_VAL_1 (3'b100),
.SATA_IDLE_VAL_1 (3'b100),
.SATA_MAX_BURST_1 (7),
.SATA_MAX_INIT_1 (22),
.SATA_MAX_WAKE_1 (7),
.SATA_MIN_BURST_1 (4),
.SATA_MIN_INIT_1 (12),
.SATA_MIN_WAKE_1 (4)
)
gtpa1_dual_i
(
//---------------------- Loopback and Powerdown Ports ----------------------
.LOOPBACK0 (tied_to_ground_vec_i[2:0]),
.LOOPBACK1 (tied_to_ground_vec_i[2:0]),
.RXPOWERDOWN0 (RXPOWERDOWN0_IN),
.RXPOWERDOWN1 (RXPOWERDOWN1_IN),
.TXPOWERDOWN0 (TXPOWERDOWN0_IN),
.TXPOWERDOWN1 (TXPOWERDOWN1_IN),
//------------------------------- PLL Ports --------------------------------
.CLK00 (CLK00_IN),
.CLK01 (CLK01_IN),
.CLK10 (tied_to_ground_i),
.CLK11 (tied_to_ground_i),
.CLKINEAST0 (tied_to_ground_i),
.CLKINEAST1 (tied_to_ground_i),
.CLKINWEST0 (tied_to_ground_i),
.CLKINWEST1 (tied_to_ground_i),
.GCLK00 (tied_to_ground_i),
.GCLK01 (tied_to_ground_i),
.GCLK10 (tied_to_ground_i),
.GCLK11 (tied_to_ground_i),
.GTPRESET0 (GTPRESET0_IN),
.GTPRESET1 (GTPRESET1_IN),
.GTPTEST0 (8'b00010000),
.GTPTEST1 (8'b00010000),
.INTDATAWIDTH0 (tied_to_vcc_i),
.INTDATAWIDTH1 (tied_to_vcc_i),
.PLLCLK00 (tied_to_ground_i),
.PLLCLK01 (tied_to_ground_i),
.PLLCLK10 (tied_to_ground_i),
.PLLCLK11 (tied_to_ground_i),
.PLLLKDET0 (PLLLKDET0_OUT),
.PLLLKDET1 (PLLLKDET1_OUT),
.PLLLKDETEN0 (tied_to_vcc_i),
.PLLLKDETEN1 (tied_to_vcc_i),
.PLLPOWERDOWN0 (tied_to_ground_i),
.PLLPOWERDOWN1 (tied_to_ground_i),
.REFCLKOUT0 (),
.REFCLKOUT1 (),
.REFCLKPLL0 (),
.REFCLKPLL1 (),
.REFCLKPWRDNB0 (tied_to_vcc_i),
.REFCLKPWRDNB1 (tied_to_vcc_i),
.REFSELDYPLL0 (tied_to_ground_vec_i[2:0]),
.REFSELDYPLL1 (tied_to_ground_vec_i[2:0]),
.RESETDONE0 (RESETDONE0_OUT),
.RESETDONE1 (RESETDONE1_OUT),
.TSTCLK0 (tied_to_ground_i),
.TSTCLK1 (tied_to_ground_i),
.TSTIN0 (tied_to_ground_vec_i[11:0]),
.TSTIN1 (tied_to_ground_vec_i[11:0]),
.TSTOUT0 (),
.TSTOUT1 (),
//--------------------- Receive Ports - 8b10b Decoder ----------------------
.RXCHARISCOMMA0 (),
.RXCHARISCOMMA1 (),
.RXCHARISK0 ({rxcharisk0_float_i,RXCHARISK0_OUT}),
.RXCHARISK1 ({rxcharisk1_float_i,RXCHARISK1_OUT}),
.RXDEC8B10BUSE0 (tied_to_vcc_i),
.RXDEC8B10BUSE1 (tied_to_vcc_i),
.RXDISPERR0 ({rxdisperr0_float_i,RXDISPERR0_OUT}),
.RXDISPERR1 ({rxdisperr1_float_i,RXDISPERR1_OUT}),
.RXNOTINTABLE0 ({rxnotintable0_float_i,RXNOTINTABLE0_OUT}),
.RXNOTINTABLE1 ({rxnotintable1_float_i,RXNOTINTABLE1_OUT}),
.RXRUNDISP0 (),
.RXRUNDISP1 (),
.USRCODEERR0 (tied_to_ground_i),
.USRCODEERR1 (tied_to_ground_i),
//-------------------- Receive Ports - Channel Bonding ---------------------
.RXCHANBONDSEQ0 (),
.RXCHANBONDSEQ1 (),
.RXCHANISALIGNED0 (),
.RXCHANISALIGNED1 (),
.RXCHANREALIGN0 (),
.RXCHANREALIGN1 (),
.RXCHBONDI (tied_to_ground_vec_i[2:0]),
.RXCHBONDMASTER0 (tied_to_ground_i),
.RXCHBONDMASTER1 (tied_to_ground_i),
.RXCHBONDO (),
.RXCHBONDSLAVE0 (tied_to_ground_i),
.RXCHBONDSLAVE1 (tied_to_ground_i),
.RXENCHANSYNC0 (tied_to_ground_i),
.RXENCHANSYNC1 (tied_to_ground_i),
//-------------------- Receive Ports - Clock Correction --------------------
.RXCLKCORCNT0 (RXCLKCORCNT0_OUT),
.RXCLKCORCNT1 (RXCLKCORCNT1_OUT),
//------------- Receive Ports - Comma Detection and Alignment --------------
.RXBYTEISALIGNED0 (),
.RXBYTEISALIGNED1 (),
.RXBYTEREALIGN0 (),
.RXBYTEREALIGN1 (),
.RXCOMMADET0 (),
.RXCOMMADET1 (),
.RXCOMMADETUSE0 (tied_to_vcc_i),
.RXCOMMADETUSE1 (tied_to_vcc_i),
.RXENMCOMMAALIGN0 (RXENMCOMMAALIGN0_IN),
.RXENMCOMMAALIGN1 (RXENMCOMMAALIGN1_IN),
.RXENPCOMMAALIGN0 (RXENPCOMMAALIGN0_IN),
.RXENPCOMMAALIGN1 (RXENPCOMMAALIGN1_IN),
.RXSLIDE0 (tied_to_ground_i),
.RXSLIDE1 (tied_to_ground_i),
//--------------------- Receive Ports - PRBS Detection ---------------------
.PRBSCNTRESET0 (tied_to_ground_i),
.PRBSCNTRESET1 (tied_to_ground_i),
.RXENPRBSTST0 (tied_to_ground_vec_i[2:0]),
.RXENPRBSTST1 (tied_to_ground_vec_i[2:0]),
.RXPRBSERR0 (),
.RXPRBSERR1 (),
//----------------- Receive Ports - RX Data Path interface -----------------
.RXDATA0 (rxdata0_i),
.RXDATA1 (rxdata1_i),
.RXDATAWIDTH0 (2'b01),
.RXDATAWIDTH1 (2'b01),
.RXRECCLK0 (),
.RXRECCLK1 (),
.RXRESET0 (RXRESET0_IN),
.RXRESET1 (RXRESET1_IN),
.RXUSRCLK0 (RXUSRCLK0_IN),
.RXUSRCLK1 (RXUSRCLK1_IN),
.RXUSRCLK20 (RXUSRCLK20_IN),
.RXUSRCLK21 (RXUSRCLK21_IN),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.GATERXELECIDLE0 (GATERXELECIDLE0_IN),
.GATERXELECIDLE1 (GATERXELECIDLE1_IN),
.IGNORESIGDET0 (IGNORESIGDET0_IN),
.IGNORESIGDET1 (IGNORESIGDET1_IN),
.RCALINEAST (tied_to_ground_vec_i[4:0]),
.RCALINWEST (tied_to_ground_vec_i[4:0]),
.RCALOUTEAST (),
.RCALOUTWEST (),
.RXCDRRESET0 (tied_to_ground_i),
.RXCDRRESET1 (tied_to_ground_i),
.RXELECIDLE0 (RXELECIDLE0_OUT),
.RXELECIDLE1 (RXELECIDLE1_OUT),
.RXEQMIX0 (2'b11),
.RXEQMIX1 (rx_equalizer_ctrl),
.RXN0 (RXN0_IN),
.RXN1 (RXN1_IN),
.RXP0 (RXP0_IN),
.RXP1 (RXP1_IN),
//--------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
.RXBUFRESET0 (tied_to_ground_i),
.RXBUFRESET1 (tied_to_ground_i),
.RXBUFSTATUS0 (),
.RXBUFSTATUS1 (),
.RXENPMAPHASEALIGN0 (tied_to_ground_i),
.RXENPMAPHASEALIGN1 (tied_to_ground_i),
.RXPMASETPHASE0 (tied_to_ground_i),
.RXPMASETPHASE1 (tied_to_ground_i),
.RXSTATUS0 (RXSTATUS0_OUT),
.RXSTATUS1 (RXSTATUS1_OUT),
//------------- Receive Ports - RX Loss-of-sync State Machine --------------
.RXLOSSOFSYNC0 (),
.RXLOSSOFSYNC1 (),
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
.PHYSTATUS0 (PHYSTATUS0_OUT),
.PHYSTATUS1 (PHYSTATUS1_OUT),
.RXVALID0 (RXVALID0_OUT),
.RXVALID1 (RXVALID1_OUT),
//------------------ Receive Ports - RX Polarity Control -------------------
.RXPOLARITY0 (RXPOLARITY0_IN),
.RXPOLARITY1 (RXPOLARITY1_IN),
//----------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
.DADDR (tied_to_ground_vec_i[7:0]),
.DCLK (tied_to_ground_i),
.DEN (tied_to_ground_i),
.DI (tied_to_ground_vec_i[15:0]),
.DRDY (),
.DRPDO (),
.DWE (tied_to_ground_i),
//-------------------------- TX/RX Datapath Ports --------------------------
.GTPCLKFBEAST (),
.GTPCLKFBSEL0EAST (2'b10),
.GTPCLKFBSEL0WEST (2'b00),
.GTPCLKFBSEL1EAST (2'b11),
.GTPCLKFBSEL1WEST (2'b01),
.GTPCLKFBWEST (),
.GTPCLKOUT0 (GTPCLKOUT0_OUT),
.GTPCLKOUT1 (GTPCLKOUT1_OUT),
//----------------- Transmit Ports - 8b10b Encoder Control -----------------
.TXBYPASS8B10B0 (tied_to_ground_vec_i[3:0]),
.TXBYPASS8B10B1 (tied_to_ground_vec_i[3:0]),
.TXCHARDISPMODE0 ({tied_to_ground_vec_i[1:0],TXCHARDISPMODE0_IN}),
.TXCHARDISPMODE1 ({tied_to_ground_vec_i[1:0],TXCHARDISPMODE1_IN}),
.TXCHARDISPVAL0 (tied_to_ground_vec_i[3:0]),
.TXCHARDISPVAL1 (tied_to_ground_vec_i[3:0]),
.TXCHARISK0 ({tied_to_ground_vec_i[1:0],TXCHARISK0_IN}),
.TXCHARISK1 ({tied_to_ground_vec_i[1:0],TXCHARISK1_IN}),
.TXENC8B10BUSE0 (tied_to_vcc_i),
.TXENC8B10BUSE1 (tied_to_vcc_i),
.TXKERR0 (),
.TXKERR1 (),
.TXRUNDISP0 (),
.TXRUNDISP1 (),
//------------- Transmit Ports - TX Buffer and Phase Alignment -------------
.TXBUFSTATUS0 (),
.TXBUFSTATUS1 (),
.TXENPMAPHASEALIGN0 (tied_to_ground_i),
.TXENPMAPHASEALIGN1 (tied_to_ground_i),
.TXPMASETPHASE0 (tied_to_ground_i),
.TXPMASETPHASE1 (tied_to_ground_i),
//---------------- Transmit Ports - TX Data Path interface -----------------
.TXDATA0 (txdata0_i),
.TXDATA1 (txdata1_i),
.TXDATAWIDTH0 (2'b01),
.TXDATAWIDTH1 (2'b01),
.TXOUTCLK0 (),
.TXOUTCLK1 (),
.TXRESET0 (tied_to_ground_i),
.TXRESET1 (tied_to_ground_i),
.TXUSRCLK0 (TXUSRCLK0_IN),
.TXUSRCLK1 (TXUSRCLK1_IN),
.TXUSRCLK20 (TXUSRCLK20_IN),
.TXUSRCLK21 (TXUSRCLK21_IN),
//------------- Transmit Ports - TX Driver and OOB signalling --------------
.TXBUFDIFFCTRL0 (3'b101),
.TXBUFDIFFCTRL1 (3'b101),
.TXDIFFCTRL0 (4'b1001),
.TXDIFFCTRL1 (tx_diff_ctrl),
.TXINHIBIT0 (tied_to_ground_i),
.TXINHIBIT1 (tied_to_ground_i),
.TXN0 (TXN0_OUT),
.TXN1 (TXN1_OUT),
.TXP0 (TXP0_OUT),
.TXP1 (TXP1_OUT),
.TXPREEMPHASIS0 (3'b000),
.TXPREEMPHASIS1 (tx_pre_emphasis),
//------------------- Transmit Ports - TX PRBS Generator -------------------
.TXENPRBSTST0 (tied_to_ground_vec_i[2:0]),
.TXENPRBSTST1 (tied_to_ground_vec_i[2:0]),
.TXPRBSFORCEERR0 (tied_to_ground_i),
.TXPRBSFORCEERR1 (tied_to_ground_i),
//------------------ Transmit Ports - TX Polarity Control ------------------
.TXPOLARITY0 (tied_to_ground_i),
//.TXPOLARITY1 (tied_to_vcc_i),
.TXPOLARITY1 (tied_to_ground_i),
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
.TXDETECTRX0 (TXDETECTRX0_IN),
.TXDETECTRX1 (TXDETECTRX1_IN),
.TXELECIDLE0 (TXELECIDLE0_IN),
.TXELECIDLE1 (TXELECIDLE1_IN),
.TXPDOWNASYNCH0 (tied_to_ground_i),
.TXPDOWNASYNCH1 (tied_to_ground_i),
//------------------- Transmit Ports - TX Ports for SATA -------------------
.TXCOMSTART0 (tied_to_ground_i),
.TXCOMSTART1 (tied_to_ground_i),
.TXCOMTYPE0 (tied_to_ground_i),
.TXCOMTYPE1 (tied_to_ground_i)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4_TB_V
`define SKY130_FD_SC_LS__NAND4_TB_V
/**
* nand4: 4-input NAND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand4.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_ls__nand4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4_TB_V
|
//--------------------------------------------------------------------------------
// Auto-generated by Migen (a5bc262) & LiteX (7bf6db5f) on 2021-11-09 21:49:46
//--------------------------------------------------------------------------------
module top (
output wire spiflash4x_cs_n,
output wire spiflash4x_clk,
inout wire [3:0] spiflash4x_dq,
output reg user_led0
);
(* keep = "true" *) wire sys_clk;
wire sys_rst;
wire por_clk;
reg por_rst = 1'd0;
wire soc_clkout;
reg [11:0] soc_por_counter = 12'd4095;
reg soc_soc_rst = 1'd0;
wire soc_cpu_rst;
reg [1:0] soc_reset_storage = 2'd0;
reg soc_reset_re = 1'd0;
reg [31:0] soc_scratch_storage = 32'd305419896;
reg soc_scratch_re = 1'd0;
wire [31:0] soc_bus_errors_status;
wire soc_bus_errors_we;
reg soc_bus_errors_re = 1'd0;
wire soc_bus_error;
reg [31:0] soc_bus_errors = 32'd0;
wire soc_reset;
wire [31:0] soc_interrupt;
wire [29:0] soc_ibus_adr;
wire [31:0] soc_ibus_dat_w;
wire [31:0] soc_ibus_dat_r;
wire [3:0] soc_ibus_sel;
wire soc_ibus_cyc;
wire soc_ibus_stb;
wire soc_ibus_ack;
wire soc_ibus_we;
wire [2:0] soc_ibus_cti;
wire [1:0] soc_ibus_bte;
wire soc_ibus_err;
wire [29:0] soc_dbus_adr;
wire [31:0] soc_dbus_dat_w;
wire [31:0] soc_dbus_dat_r;
wire [3:0] soc_dbus_sel;
wire soc_dbus_cyc;
wire soc_dbus_stb;
wire soc_dbus_ack;
wire soc_dbus_we;
wire [2:0] soc_dbus_cti;
wire [1:0] soc_dbus_bte;
wire soc_dbus_err;
wire soc_vexriscv_cfu_bus_cmd_valid;
wire soc_vexriscv_cfu_bus_cmd_ready;
wire [9:0] soc_vexriscv_cfu_bus_cmd_payload_function_id;
wire [31:0] soc_vexriscv_cfu_bus_cmd_payload_inputs_0;
wire [31:0] soc_vexriscv_cfu_bus_cmd_payload_inputs_1;
wire soc_vexriscv_cfu_bus_rsp_valid;
wire soc_vexriscv_cfu_bus_rsp_ready;
wire [31:0] soc_vexriscv_cfu_bus_rsp_payload_outputs_0;
reg [31:0] soc_vexriscv = 32'd538968064;
wire [29:0] soc_bus_adr;
wire [31:0] soc_bus_dat_w;
reg [31:0] soc_bus_dat_r = 32'd0;
wire [3:0] soc_bus_sel;
wire soc_bus_cyc;
wire soc_bus_stb;
reg soc_bus_ack = 1'd0;
wire soc_bus_we;
wire [2:0] soc_bus_cti;
wire [1:0] soc_bus_bte;
reg soc_bus_err = 1'd0;
wire [31:0] soc_datain0;
wire [31:0] soc_dataout0;
reg soc_cs0 = 1'd0;
reg soc_wren0 = 1'd0;
wire [31:0] soc_datain1;
wire [31:0] soc_dataout1;
reg soc_cs1 = 1'd0;
reg soc_wren1 = 1'd0;
wire [31:0] soc_datain2;
wire [31:0] soc_dataout2;
reg soc_cs2 = 1'd0;
reg soc_wren2 = 1'd0;
wire [31:0] soc_datain3;
wire [31:0] soc_dataout3;
reg soc_cs3 = 1'd0;
reg soc_wren3 = 1'd0;
wire [31:0] soc_datain4;
wire [31:0] soc_dataout4;
reg soc_cs4 = 1'd0;
reg soc_wren4 = 1'd0;
reg soc_litespiddrphycore_source_valid = 1'd0;
wire soc_litespiddrphycore_source_ready;
reg soc_litespiddrphycore_source_first = 1'd0;
reg soc_litespiddrphycore_source_last = 1'd0;
wire [31:0] soc_litespiddrphycore_source_payload_data;
wire soc_litespiddrphycore_sink_valid;
reg soc_litespiddrphycore_sink_ready = 1'd0;
wire soc_litespiddrphycore_sink_first;
wire soc_litespiddrphycore_sink_last;
wire [31:0] soc_litespiddrphycore_sink_payload_data;
wire [5:0] soc_litespiddrphycore_sink_payload_len;
wire [3:0] soc_litespiddrphycore_sink_payload_width;
wire [7:0] soc_litespiddrphycore_sink_payload_mask;
wire soc_litespiddrphycore_cs;
reg soc_litespiddrphycore_en = 1'd0;
wire soc_litespiddrphycore_wait;
wire soc_litespiddrphycore_done;
reg [3:0] soc_litespiddrphycore_count = 4'd11;
wire soc_litespiddrphycore_cs_enable;
reg [3:0] soc_litespiddrphycore0 = 4'd0;
reg [3:0] soc_litespiddrphycore1 = 4'd0;
wire [3:0] soc_litespiddrphycore2;
wire [3:0] soc_litespiddrphycore3;
reg [3:0] soc_litespiddrphycore4 = 4'd0;
wire [3:0] soc_litespiddrphycore5;
reg [7:0] soc_litespiddrphycore_sr_cnt = 8'd0;
reg soc_litespiddrphycore_sr_out_load = 1'd0;
reg soc_litespiddrphycore_sr_out_shift = 1'd0;
reg [31:0] soc_litespiddrphycore_sr_out = 32'd0;
reg soc_litespiddrphycore_sr_in_shift = 1'd0;
reg [31:0] soc_litespiddrphycore_sr_in = 32'd0;
reg soc_litespiddrphycore6 = 1'd0;
reg [1:0] soc_litespiddrphycore7 = 2'd0;
reg [3:0] soc_litespiddrphycore8 = 4'd0;
reg [7:0] soc_litespiddrphycore9 = 8'd0;
wire soc_crossbar_source_valid;
wire soc_crossbar_source_ready;
wire soc_crossbar_source_first;
wire soc_crossbar_source_last;
wire [31:0] soc_crossbar_source_payload_data;
wire [5:0] soc_crossbar_source_payload_len;
wire [3:0] soc_crossbar_source_payload_width;
wire [7:0] soc_crossbar_source_payload_mask;
wire soc_crossbar_sink_valid;
wire soc_crossbar_sink_ready;
wire soc_crossbar_sink_first;
wire soc_crossbar_sink_last;
wire [31:0] soc_crossbar_sink_payload_data;
reg soc_crossbar_cs = 1'd0;
reg soc_litespimmap_source_valid = 1'd0;
wire soc_litespimmap_source_ready;
reg soc_litespimmap_source_first = 1'd0;
reg soc_litespimmap_source_last = 1'd0;
reg [31:0] soc_litespimmap_source_payload_data = 32'd0;
reg [5:0] soc_litespimmap_source_payload_len = 6'd0;
reg [3:0] soc_litespimmap_source_payload_width = 4'd0;
reg [7:0] soc_litespimmap_source_payload_mask = 8'd0;
wire soc_litespimmap_sink_valid;
reg soc_litespimmap_sink_ready = 1'd0;
wire soc_litespimmap_sink_first;
wire soc_litespimmap_sink_last;
wire [31:0] soc_litespimmap_sink_payload_data;
wire [29:0] soc_litespimmap_bus_adr;
wire [31:0] soc_litespimmap_bus_dat_w;
reg [31:0] soc_litespimmap_bus_dat_r = 32'd0;
wire [3:0] soc_litespimmap_bus_sel;
wire soc_litespimmap_bus_cyc;
wire soc_litespimmap_bus_stb;
reg soc_litespimmap_bus_ack = 1'd0;
wire soc_litespimmap_bus_we;
wire [2:0] soc_litespimmap_bus_cti;
wire [1:0] soc_litespimmap_bus_bte;
reg soc_litespimmap_bus_err = 1'd0;
reg soc_litespimmap_cs = 1'd0;
reg soc_litespimmap_burst_cs = 1'd0;
reg [29:0] soc_litespimmap_burst_adr = 30'd0;
reg soc_litespimmap_wait = 1'd0;
wire soc_litespimmap_done;
reg [8:0] soc_litespimmap_count = 9'd256;
reg [7:0] soc_litespimmap_storage = 8'd8;
reg soc_litespimmap_re = 1'd0;
wire [7:0] soc_litespimmap_spi_dummy_bits;
reg [31:0] soc_litespimmap_dummy = 32'd57005;
reg [1:0] soc_litespimmap = 2'd0;
wire soc_port_mmap_user_port_source_valid;
wire soc_port_mmap_user_port_source_ready;
wire soc_port_mmap_user_port_source_first;
wire soc_port_mmap_user_port_source_last;
wire [31:0] soc_port_mmap_user_port_source_payload_data;
wire soc_port_mmap_user_port_sink_valid;
wire soc_port_mmap_user_port_sink_ready;
wire soc_port_mmap_user_port_sink_first;
wire soc_port_mmap_user_port_sink_last;
wire [31:0] soc_port_mmap_user_port_sink_payload_data;
wire [5:0] soc_port_mmap_user_port_sink_payload_len;
wire [3:0] soc_port_mmap_user_port_sink_payload_width;
wire [7:0] soc_port_mmap_user_port_sink_payload_mask;
wire soc_port_mmap_internal_port_source_valid;
wire soc_port_mmap_internal_port_source_ready;
wire soc_port_mmap_internal_port_source_first;
wire soc_port_mmap_internal_port_source_last;
wire [31:0] soc_port_mmap_internal_port_source_payload_data;
wire soc_port_mmap_internal_port_sink_valid;
wire soc_port_mmap_internal_port_sink_ready;
wire soc_port_mmap_internal_port_sink_first;
wire soc_port_mmap_internal_port_sink_last;
wire [31:0] soc_port_mmap_internal_port_sink_payload_data;
wire [5:0] soc_port_mmap_internal_port_sink_payload_len;
wire [3:0] soc_port_mmap_internal_port_sink_payload_width;
wire [7:0] soc_port_mmap_internal_port_sink_payload_mask;
wire soc_port_mmap_request;
wire soc_master_sink_sink_valid;
wire soc_master_sink_sink_ready;
wire soc_master_sink_sink_first;
wire soc_master_sink_sink_last;
wire [31:0] soc_master_sink_sink_payload_data;
wire soc_master_source_source_valid;
wire soc_master_source_source_ready;
wire soc_master_source_source_first;
wire soc_master_source_source_last;
wire [31:0] soc_master_source_source_payload_data;
wire [5:0] soc_master_source_source_payload_len;
wire [3:0] soc_master_source_source_payload_width;
wire [7:0] soc_master_source_source_payload_mask;
wire soc_master_cs;
reg soc_master_cs_storage = 1'd0;
reg soc_master_cs_re = 1'd0;
wire [7:0] soc_master_len;
wire [3:0] soc_master_width;
wire [7:0] soc_master_mask;
reg [23:0] soc_master_phyconfig_storage = 24'd0;
reg soc_master_phyconfig_re = 1'd0;
reg soc_master_rxtx_re = 1'd0;
wire [31:0] soc_master_rxtx_r;
reg soc_master_rxtx_we = 1'd0;
wire [31:0] soc_master_rxtx_w;
wire soc_master_tx_ready;
wire soc_master_rx_ready;
reg [1:0] soc_master_status_status = 2'd0;
wire soc_master_status_we;
reg soc_master_status_re = 1'd0;
wire soc_master_tx_fifo_sink_valid;
wire soc_master_tx_fifo_sink_ready;
reg soc_master_tx_fifo_sink_first = 1'd0;
wire soc_master_tx_fifo_sink_last;
wire [31:0] soc_master_tx_fifo_sink_payload_data;
wire [5:0] soc_master_tx_fifo_sink_payload_len;
wire [3:0] soc_master_tx_fifo_sink_payload_width;
wire [7:0] soc_master_tx_fifo_sink_payload_mask;
reg soc_master_tx_fifo_source_valid = 1'd0;
wire soc_master_tx_fifo_source_ready;
reg soc_master_tx_fifo_source_first = 1'd0;
reg soc_master_tx_fifo_source_last = 1'd0;
reg [31:0] soc_master_tx_fifo_source_payload_data = 32'd0;
reg [5:0] soc_master_tx_fifo_source_payload_len = 6'd0;
reg [3:0] soc_master_tx_fifo_source_payload_width = 4'd0;
reg [7:0] soc_master_tx_fifo_source_payload_mask = 8'd0;
wire soc_master_rx_fifo_sink_valid;
wire soc_master_rx_fifo_sink_ready;
wire soc_master_rx_fifo_sink_first;
wire soc_master_rx_fifo_sink_last;
wire [31:0] soc_master_rx_fifo_sink_payload_data;
reg soc_master_rx_fifo_source_valid = 1'd0;
wire soc_master_rx_fifo_source_ready;
reg soc_master_rx_fifo_source_first = 1'd0;
reg soc_master_rx_fifo_source_last = 1'd0;
reg [31:0] soc_master_rx_fifo_source_payload_data = 32'd0;
wire soc_port_master_user_port_source_valid;
wire soc_port_master_user_port_source_ready;
wire soc_port_master_user_port_source_first;
wire soc_port_master_user_port_source_last;
wire [31:0] soc_port_master_user_port_source_payload_data;
wire soc_port_master_user_port_sink_valid;
wire soc_port_master_user_port_sink_ready;
wire soc_port_master_user_port_sink_first;
wire soc_port_master_user_port_sink_last;
wire [31:0] soc_port_master_user_port_sink_payload_data;
wire [5:0] soc_port_master_user_port_sink_payload_len;
wire [3:0] soc_port_master_user_port_sink_payload_width;
wire [7:0] soc_port_master_user_port_sink_payload_mask;
wire soc_port_master_internal_port_source_valid;
wire soc_port_master_internal_port_source_ready;
wire soc_port_master_internal_port_source_first;
wire soc_port_master_internal_port_source_last;
wire [31:0] soc_port_master_internal_port_source_payload_data;
wire soc_port_master_internal_port_sink_valid;
wire soc_port_master_internal_port_sink_ready;
wire soc_port_master_internal_port_sink_first;
wire soc_port_master_internal_port_sink_last;
wire [31:0] soc_port_master_internal_port_sink_payload_data;
wire [5:0] soc_port_master_internal_port_sink_payload_len;
wire [3:0] soc_port_master_internal_port_sink_payload_width;
wire [7:0] soc_port_master_internal_port_sink_payload_mask;
wire soc_port_master_request;
reg soc_storage = 1'd0;
reg soc_re = 1'd0;
reg soc_chaser = 1'd0;
reg soc_mode = 1'd0;
wire soc_wait;
wire soc_done;
reg [24:0] soc_count = 25'd32142857;
reg [31:0] soc_load_storage = 32'd0;
reg soc_load_re = 1'd0;
reg [31:0] soc_reload_storage = 32'd0;
reg soc_reload_re = 1'd0;
reg soc_en_storage = 1'd0;
reg soc_en_re = 1'd0;
reg soc_update_value_storage = 1'd0;
reg soc_update_value_re = 1'd0;
reg [31:0] soc_value_status = 32'd0;
wire soc_value_we;
reg soc_value_re = 1'd0;
wire soc_irq;
wire soc_zero_status;
reg soc_zero_pending = 1'd0;
wire soc_zero_trigger;
reg soc_zero_clear = 1'd0;
reg soc_zero_trigger_d = 1'd0;
wire soc_zero0;
wire soc_status_status;
wire soc_status_we;
reg soc_status_re = 1'd0;
wire soc_zero1;
wire soc_pending_status;
wire soc_pending_we;
reg soc_pending_re = 1'd0;
reg soc_pending_r = 1'd0;
wire soc_zero2;
reg soc_enable_storage = 1'd0;
reg soc_enable_re = 1'd0;
reg [31:0] soc_value = 32'd0;
reg soc_uptime_latch_storage = 1'd0;
reg soc_uptime_latch_re = 1'd0;
reg [63:0] soc_uptime_cycles_status = 64'd0;
wire soc_uptime_cycles_we;
reg soc_uptime_cycles_re = 1'd0;
reg [63:0] soc_uptime_cycles = 64'd0;
reg [1:0] vns_litespiphy_state = 2'd0;
reg [1:0] vns_litespiphy_next_state = 2'd0;
reg soc_litespiddrphycore_en_litespiphy_next_value0 = 1'd0;
reg soc_litespiddrphycore_en_litespiphy_next_value_ce0 = 1'd0;
reg [7:0] soc_litespiddrphycore_sr_cnt_litespiphy_next_value1 = 8'd0;
reg soc_litespiddrphycore_sr_cnt_litespiphy_next_value_ce1 = 1'd0;
wire [1:0] vns_litespi_request;
reg vns_litespi_grant = 1'd0;
reg vns_litespi_tx_mux_source_valid = 1'd0;
wire vns_litespi_tx_mux_source_ready;
reg vns_litespi_tx_mux_source_first = 1'd0;
reg vns_litespi_tx_mux_source_last = 1'd0;
reg [31:0] vns_litespi_tx_mux_source_payload_data = 32'd0;
reg [5:0] vns_litespi_tx_mux_source_payload_len = 6'd0;
reg [3:0] vns_litespi_tx_mux_source_payload_width = 4'd0;
reg [7:0] vns_litespi_tx_mux_source_payload_mask = 8'd0;
wire vns_litespi_tx_mux_endpoint0_sink_valid;
reg vns_litespi_tx_mux_endpoint0_sink_ready = 1'd0;
wire vns_litespi_tx_mux_endpoint0_sink_first;
wire vns_litespi_tx_mux_endpoint0_sink_last;
wire [31:0] vns_litespi_tx_mux_endpoint0_sink_payload_data;
wire [5:0] vns_litespi_tx_mux_endpoint0_sink_payload_len;
wire [3:0] vns_litespi_tx_mux_endpoint0_sink_payload_width;
wire [7:0] vns_litespi_tx_mux_endpoint0_sink_payload_mask;
wire vns_litespi_tx_mux_endpoint1_sink_valid;
reg vns_litespi_tx_mux_endpoint1_sink_ready = 1'd0;
wire vns_litespi_tx_mux_endpoint1_sink_first;
wire vns_litespi_tx_mux_endpoint1_sink_last;
wire [31:0] vns_litespi_tx_mux_endpoint1_sink_payload_data;
wire [5:0] vns_litespi_tx_mux_endpoint1_sink_payload_len;
wire [3:0] vns_litespi_tx_mux_endpoint1_sink_payload_width;
wire [7:0] vns_litespi_tx_mux_endpoint1_sink_payload_mask;
wire vns_litespi_tx_mux_sel;
wire vns_litespi_rx_demux_sink_valid;
reg vns_litespi_rx_demux_sink_ready = 1'd0;
wire vns_litespi_rx_demux_sink_first;
wire vns_litespi_rx_demux_sink_last;
wire [31:0] vns_litespi_rx_demux_sink_payload_data;
reg vns_litespi_rx_demux_endpoint0_source_valid = 1'd0;
wire vns_litespi_rx_demux_endpoint0_source_ready;
reg vns_litespi_rx_demux_endpoint0_source_first = 1'd0;
reg vns_litespi_rx_demux_endpoint0_source_last = 1'd0;
reg [31:0] vns_litespi_rx_demux_endpoint0_source_payload_data = 32'd0;
reg vns_litespi_rx_demux_endpoint1_source_valid = 1'd0;
wire vns_litespi_rx_demux_endpoint1_source_ready;
reg vns_litespi_rx_demux_endpoint1_source_first = 1'd0;
reg vns_litespi_rx_demux_endpoint1_source_last = 1'd0;
reg [31:0] vns_litespi_rx_demux_endpoint1_source_payload_data = 32'd0;
wire vns_litespi_rx_demux_sel;
reg [3:0] vns_litespi_state = 4'd0;
reg [3:0] vns_litespi_next_state = 4'd0;
reg soc_litespimmap_burst_cs_litespi_next_value0 = 1'd0;
reg soc_litespimmap_burst_cs_litespi_next_value_ce0 = 1'd0;
reg [29:0] soc_litespimmap_burst_adr_litespi_next_value1 = 30'd0;
reg soc_litespimmap_burst_adr_litespi_next_value_ce1 = 1'd0;
reg [13:0] vns_hpssoc_adr = 14'd0;
reg vns_hpssoc_we = 1'd0;
reg [31:0] vns_hpssoc_dat_w = 32'd0;
wire [31:0] vns_hpssoc_dat_r;
wire [29:0] vns_hpssoc_wishbone_adr;
wire [31:0] vns_hpssoc_wishbone_dat_w;
reg [31:0] vns_hpssoc_wishbone_dat_r = 32'd0;
wire [3:0] vns_hpssoc_wishbone_sel;
wire vns_hpssoc_wishbone_cyc;
wire vns_hpssoc_wishbone_stb;
reg vns_hpssoc_wishbone_ack = 1'd0;
wire vns_hpssoc_wishbone_we;
wire [2:0] vns_hpssoc_wishbone_cti;
wire [1:0] vns_hpssoc_wishbone_bte;
reg vns_hpssoc_wishbone_err = 1'd0;
wire [29:0] vns_shared_adr;
wire [31:0] vns_shared_dat_w;
reg [31:0] vns_shared_dat_r = 32'd0;
wire [3:0] vns_shared_sel;
wire vns_shared_cyc;
wire vns_shared_stb;
reg vns_shared_ack = 1'd0;
wire vns_shared_we;
wire [2:0] vns_shared_cti;
wire [1:0] vns_shared_bte;
wire vns_shared_err;
wire [1:0] vns_request;
reg vns_grant = 1'd0;
reg [2:0] vns_slave_sel = 3'd0;
reg [2:0] vns_slave_sel_r = 3'd0;
reg vns_error = 1'd0;
wire vns_wait;
wire vns_done;
reg [19:0] vns_count = 20'd1000000;
wire [13:0] vns_interface0_bank_bus_adr;
wire vns_interface0_bank_bus_we;
wire [31:0] vns_interface0_bank_bus_dat_w;
reg [31:0] vns_interface0_bank_bus_dat_r = 32'd0;
reg vns_csrbank0_reset0_re = 1'd0;
wire [1:0] vns_csrbank0_reset0_r;
reg vns_csrbank0_reset0_we = 1'd0;
wire [1:0] vns_csrbank0_reset0_w;
reg vns_csrbank0_scratch0_re = 1'd0;
wire [31:0] vns_csrbank0_scratch0_r;
reg vns_csrbank0_scratch0_we = 1'd0;
wire [31:0] vns_csrbank0_scratch0_w;
reg vns_csrbank0_bus_errors_re = 1'd0;
wire [31:0] vns_csrbank0_bus_errors_r;
reg vns_csrbank0_bus_errors_we = 1'd0;
wire [31:0] vns_csrbank0_bus_errors_w;
wire vns_csrbank0_sel;
wire [13:0] vns_interface1_bank_bus_adr;
wire vns_interface1_bank_bus_we;
wire [31:0] vns_interface1_bank_bus_dat_w;
reg [31:0] vns_interface1_bank_bus_dat_r = 32'd0;
reg vns_csrbank1_out0_re = 1'd0;
wire vns_csrbank1_out0_r;
reg vns_csrbank1_out0_we = 1'd0;
wire vns_csrbank1_out0_w;
wire vns_csrbank1_sel;
wire [13:0] vns_interface2_bank_bus_adr;
wire vns_interface2_bank_bus_we;
wire [31:0] vns_interface2_bank_bus_dat_w;
reg [31:0] vns_interface2_bank_bus_dat_r = 32'd0;
reg vns_csrbank2_mmap_dummy_bits0_re = 1'd0;
wire [7:0] vns_csrbank2_mmap_dummy_bits0_r;
reg vns_csrbank2_mmap_dummy_bits0_we = 1'd0;
wire [7:0] vns_csrbank2_mmap_dummy_bits0_w;
reg vns_csrbank2_master_cs0_re = 1'd0;
wire vns_csrbank2_master_cs0_r;
reg vns_csrbank2_master_cs0_we = 1'd0;
wire vns_csrbank2_master_cs0_w;
reg vns_csrbank2_master_phyconfig0_re = 1'd0;
wire [23:0] vns_csrbank2_master_phyconfig0_r;
reg vns_csrbank2_master_phyconfig0_we = 1'd0;
wire [23:0] vns_csrbank2_master_phyconfig0_w;
reg vns_csrbank2_master_status_re = 1'd0;
wire [1:0] vns_csrbank2_master_status_r;
reg vns_csrbank2_master_status_we = 1'd0;
wire [1:0] vns_csrbank2_master_status_w;
wire vns_csrbank2_sel;
wire [13:0] vns_interface3_bank_bus_adr;
wire vns_interface3_bank_bus_we;
wire [31:0] vns_interface3_bank_bus_dat_w;
reg [31:0] vns_interface3_bank_bus_dat_r = 32'd0;
reg vns_csrbank3_load0_re = 1'd0;
wire [31:0] vns_csrbank3_load0_r;
reg vns_csrbank3_load0_we = 1'd0;
wire [31:0] vns_csrbank3_load0_w;
reg vns_csrbank3_reload0_re = 1'd0;
wire [31:0] vns_csrbank3_reload0_r;
reg vns_csrbank3_reload0_we = 1'd0;
wire [31:0] vns_csrbank3_reload0_w;
reg vns_csrbank3_en0_re = 1'd0;
wire vns_csrbank3_en0_r;
reg vns_csrbank3_en0_we = 1'd0;
wire vns_csrbank3_en0_w;
reg vns_csrbank3_update_value0_re = 1'd0;
wire vns_csrbank3_update_value0_r;
reg vns_csrbank3_update_value0_we = 1'd0;
wire vns_csrbank3_update_value0_w;
reg vns_csrbank3_value_re = 1'd0;
wire [31:0] vns_csrbank3_value_r;
reg vns_csrbank3_value_we = 1'd0;
wire [31:0] vns_csrbank3_value_w;
reg vns_csrbank3_ev_status_re = 1'd0;
wire vns_csrbank3_ev_status_r;
reg vns_csrbank3_ev_status_we = 1'd0;
wire vns_csrbank3_ev_status_w;
reg vns_csrbank3_ev_pending_re = 1'd0;
wire vns_csrbank3_ev_pending_r;
reg vns_csrbank3_ev_pending_we = 1'd0;
wire vns_csrbank3_ev_pending_w;
reg vns_csrbank3_ev_enable0_re = 1'd0;
wire vns_csrbank3_ev_enable0_r;
reg vns_csrbank3_ev_enable0_we = 1'd0;
wire vns_csrbank3_ev_enable0_w;
reg vns_csrbank3_uptime_latch0_re = 1'd0;
wire vns_csrbank3_uptime_latch0_r;
reg vns_csrbank3_uptime_latch0_we = 1'd0;
wire vns_csrbank3_uptime_latch0_w;
reg vns_csrbank3_uptime_cycles1_re = 1'd0;
wire [31:0] vns_csrbank3_uptime_cycles1_r;
reg vns_csrbank3_uptime_cycles1_we = 1'd0;
wire [31:0] vns_csrbank3_uptime_cycles1_w;
reg vns_csrbank3_uptime_cycles0_re = 1'd0;
wire [31:0] vns_csrbank3_uptime_cycles0_r;
reg vns_csrbank3_uptime_cycles0_we = 1'd0;
wire [31:0] vns_csrbank3_uptime_cycles0_w;
wire vns_csrbank3_sel;
wire [13:0] vns_csr_interconnect_adr;
wire vns_csr_interconnect_we;
wire [31:0] vns_csr_interconnect_dat_w;
wire [31:0] vns_csr_interconnect_dat_r;
reg vns_state = 1'd0;
reg vns_next_state = 1'd0;
reg [29:0] vns_array_muxed0 = 30'd0;
reg [31:0] vns_array_muxed1 = 32'd0;
reg [3:0] vns_array_muxed2 = 4'd0;
reg vns_array_muxed3 = 1'd0;
reg vns_array_muxed4 = 1'd0;
reg vns_array_muxed5 = 1'd0;
reg [2:0] vns_array_muxed6 = 3'd0;
reg [1:0] vns_array_muxed7 = 2'd0;
wire vns_rst1;
wire vns_latticenxddrtristateimpl0__o;
(* syn_useioff = 1 *) wire vns_latticenxddrtristateimpl0_oe;
wire vns_latticenxddrtristateimpl0__i;
wire vns_latticenxddrtristateimpl1__o;
(* syn_useioff = 1 *) wire vns_latticenxddrtristateimpl1_oe;
wire vns_latticenxddrtristateimpl1__i;
wire vns_latticenxddrtristateimpl2__o;
(* syn_useioff = 1 *) wire vns_latticenxddrtristateimpl2_oe;
wire vns_latticenxddrtristateimpl2__i;
wire vns_latticenxddrtristateimpl3__o;
(* syn_useioff = 1 *) wire vns_latticenxddrtristateimpl3_oe;
wire vns_latticenxddrtristateimpl3__i;
assign soc_reset = (soc_soc_rst | soc_cpu_rst);
assign soc_bus_error = vns_error;
assign soc_interrupt[0] = soc_irq;
assign por_clk = sys_clk;
assign sys_clk = soc_clkout;
assign soc_bus_errors_status = soc_bus_errors;
assign soc_datain0 = soc_bus_dat_w[31:0];
assign soc_datain1 = soc_bus_dat_w[31:0];
assign soc_datain2 = soc_bus_dat_w[31:0];
assign soc_datain3 = soc_bus_dat_w[31:0];
assign soc_datain4 = soc_bus_dat_w[31:0];
always @(*) begin
soc_wren4 <= 1'd0;
soc_wren0 <= 1'd0;
soc_cs3 <= 1'd0;
soc_bus_dat_r <= 32'd0;
soc_wren3 <= 1'd0;
soc_cs2 <= 1'd0;
soc_wren2 <= 1'd0;
soc_cs1 <= 1'd0;
soc_wren1 <= 1'd0;
soc_cs0 <= 1'd0;
soc_cs4 <= 1'd0;
if ((soc_bus_adr[16:14] == 1'd0)) begin
soc_cs0 <= 1'd1;
soc_wren0 <= ((soc_bus_we & soc_bus_stb) & soc_bus_cyc);
soc_bus_dat_r[31:0] <= soc_dataout0;
end
if ((soc_bus_adr[16:14] == 1'd1)) begin
soc_cs1 <= 1'd1;
soc_wren1 <= ((soc_bus_we & soc_bus_stb) & soc_bus_cyc);
soc_bus_dat_r[31:0] <= soc_dataout1;
end
if ((soc_bus_adr[16:14] == 2'd2)) begin
soc_cs2 <= 1'd1;
soc_wren2 <= ((soc_bus_we & soc_bus_stb) & soc_bus_cyc);
soc_bus_dat_r[31:0] <= soc_dataout2;
end
if ((soc_bus_adr[16:14] == 2'd3)) begin
soc_cs3 <= 1'd1;
soc_wren3 <= ((soc_bus_we & soc_bus_stb) & soc_bus_cyc);
soc_bus_dat_r[31:0] <= soc_dataout3;
end
if ((soc_bus_adr[16:14] == 3'd4)) begin
soc_cs4 <= 1'd1;
soc_wren4 <= ((soc_bus_we & soc_bus_stb) & soc_bus_cyc);
soc_bus_dat_r[31:0] <= soc_dataout4;
end
end
assign soc_litespiddrphycore_wait = soc_litespiddrphycore_cs;
assign soc_litespiddrphycore_cs_enable = soc_litespiddrphycore_done;
assign spiflash4x_cs_n = (~soc_litespiddrphycore_cs_enable);
assign soc_litespiddrphycore5 = soc_litespiddrphycore_sink_payload_mask;
always @(*) begin
soc_litespiddrphycore1 <= 4'd0;
case (soc_litespiddrphycore_sink_payload_width)
1'd1: begin
soc_litespiddrphycore1 <= soc_litespiddrphycore_sr_out[31];
end
2'd2: begin
soc_litespiddrphycore1 <= soc_litespiddrphycore_sr_out[31:30];
end
3'd4: begin
soc_litespiddrphycore1 <= soc_litespiddrphycore_sr_out[31:28];
end
4'd8: begin
soc_litespiddrphycore1 <= soc_litespiddrphycore_sr_out[31:24];
end
endcase
end
assign soc_litespiddrphycore_source_payload_data = soc_litespiddrphycore_sr_in;
assign soc_litespiddrphycore_done = (soc_litespiddrphycore_count == 1'd0);
always @(*) begin
soc_litespiddrphycore_source_last <= 1'd0;
soc_litespiddrphycore_sr_out_shift <= 1'd0;
soc_litespiddrphycore_sink_ready <= 1'd0;
vns_litespiphy_next_state <= 2'd0;
soc_litespiddrphycore_en_litespiphy_next_value0 <= 1'd0;
soc_litespiddrphycore_en_litespiphy_next_value_ce0 <= 1'd0;
soc_litespiddrphycore_sr_out_load <= 1'd0;
soc_litespiddrphycore_sr_in_shift <= 1'd0;
soc_litespiddrphycore_sr_cnt_litespiphy_next_value1 <= 8'd0;
soc_litespiddrphycore_source_valid <= 1'd0;
soc_litespiddrphycore_sr_cnt_litespiphy_next_value_ce1 <= 1'd0;
vns_litespiphy_next_state <= vns_litespiphy_state;
case (vns_litespiphy_state)
1'd1: begin
soc_litespiddrphycore_en_litespiphy_next_value0 <= 1'd1;
soc_litespiddrphycore_en_litespiphy_next_value_ce0 <= 1'd1;
soc_litespiddrphycore_sr_in_shift <= 1'd1;
soc_litespiddrphycore_sr_out_shift <= 1'd1;
soc_litespiddrphycore_sr_cnt_litespiphy_next_value1 <= (soc_litespiddrphycore_sr_cnt - soc_litespiddrphycore_sink_payload_width);
soc_litespiddrphycore_sr_cnt_litespiphy_next_value_ce1 <= 1'd1;
if ((soc_litespiddrphycore_sr_cnt == 1'd0)) begin
soc_litespiddrphycore_sr_cnt_litespiphy_next_value1 <= (3'd4 * soc_litespiddrphycore_sink_payload_width);
soc_litespiddrphycore_sr_cnt_litespiphy_next_value_ce1 <= 1'd1;
vns_litespiphy_next_state <= 2'd2;
end
end
2'd2: begin
soc_litespiddrphycore_en_litespiphy_next_value0 <= 1'd0;
soc_litespiddrphycore_en_litespiphy_next_value_ce0 <= 1'd1;
soc_litespiddrphycore_sr_in_shift <= 1'd1;
soc_litespiddrphycore_sr_cnt_litespiphy_next_value1 <= (soc_litespiddrphycore_sr_cnt - soc_litespiddrphycore_sink_payload_width);
soc_litespiddrphycore_sr_cnt_litespiphy_next_value_ce1 <= 1'd1;
if ((soc_litespiddrphycore_sr_cnt == 1'd0)) begin
soc_litespiddrphycore_sink_ready <= 1'd1;
vns_litespiphy_next_state <= 2'd3;
end
end
2'd3: begin
soc_litespiddrphycore_source_valid <= 1'd1;
soc_litespiddrphycore_source_last <= 1'd1;
if (soc_litespiddrphycore_source_ready) begin
vns_litespiphy_next_state <= 1'd0;
end
end
default: begin
soc_litespiddrphycore_en_litespiphy_next_value0 <= 1'd0;
soc_litespiddrphycore_en_litespiphy_next_value_ce0 <= 1'd1;
if ((soc_litespiddrphycore_cs_enable & soc_litespiddrphycore_sink_valid)) begin
soc_litespiddrphycore_sr_cnt_litespiphy_next_value1 <= (soc_litespiddrphycore_sink_payload_len - soc_litespiddrphycore_sink_payload_width);
soc_litespiddrphycore_sr_cnt_litespiphy_next_value_ce1 <= 1'd1;
soc_litespiddrphycore_sr_out_load <= 1'd1;
vns_litespiphy_next_state <= 1'd1;
end
end
endcase
end
assign soc_litespiddrphycore_cs = soc_crossbar_cs;
assign soc_litespimmap_sink_valid = soc_port_mmap_user_port_source_valid;
assign soc_port_mmap_user_port_source_ready = soc_litespimmap_sink_ready;
assign soc_litespimmap_sink_first = soc_port_mmap_user_port_source_first;
assign soc_litespimmap_sink_last = soc_port_mmap_user_port_source_last;
assign soc_litespimmap_sink_payload_data = soc_port_mmap_user_port_source_payload_data;
assign soc_port_mmap_user_port_sink_valid = soc_litespimmap_source_valid;
assign soc_litespimmap_source_ready = soc_port_mmap_user_port_sink_ready;
assign soc_port_mmap_user_port_sink_first = soc_litespimmap_source_first;
assign soc_port_mmap_user_port_sink_last = soc_litespimmap_source_last;
assign soc_port_mmap_user_port_sink_payload_data = soc_litespimmap_source_payload_data;
assign soc_port_mmap_user_port_sink_payload_len = soc_litespimmap_source_payload_len;
assign soc_port_mmap_user_port_sink_payload_width = soc_litespimmap_source_payload_width;
assign soc_port_mmap_user_port_sink_payload_mask = soc_litespimmap_source_payload_mask;
assign soc_master_sink_sink_valid = soc_port_master_user_port_source_valid;
assign soc_port_master_user_port_source_ready = soc_master_sink_sink_ready;
assign soc_master_sink_sink_first = soc_port_master_user_port_source_first;
assign soc_master_sink_sink_last = soc_port_master_user_port_source_last;
assign soc_master_sink_sink_payload_data = soc_port_master_user_port_source_payload_data;
assign soc_port_master_user_port_sink_valid = soc_master_source_source_valid;
assign soc_master_source_source_ready = soc_port_master_user_port_sink_ready;
assign soc_port_master_user_port_sink_first = soc_master_source_source_first;
assign soc_port_master_user_port_sink_last = soc_master_source_source_last;
assign soc_port_master_user_port_sink_payload_data = soc_master_source_source_payload_data;
assign soc_port_master_user_port_sink_payload_len = soc_master_source_source_payload_len;
assign soc_port_master_user_port_sink_payload_width = soc_master_source_source_payload_width;
assign soc_port_master_user_port_sink_payload_mask = soc_master_source_source_payload_mask;
assign soc_litespiddrphycore_sink_valid = soc_crossbar_source_valid;
assign soc_crossbar_source_ready = soc_litespiddrphycore_sink_ready;
assign soc_litespiddrphycore_sink_first = soc_crossbar_source_first;
assign soc_litespiddrphycore_sink_last = soc_crossbar_source_last;
assign soc_litespiddrphycore_sink_payload_data = soc_crossbar_source_payload_data;
assign soc_litespiddrphycore_sink_payload_len = soc_crossbar_source_payload_len;
assign soc_litespiddrphycore_sink_payload_width = soc_crossbar_source_payload_width;
assign soc_litespiddrphycore_sink_payload_mask = soc_crossbar_source_payload_mask;
assign soc_crossbar_sink_valid = soc_litespiddrphycore_source_valid;
assign soc_litespiddrphycore_source_ready = soc_crossbar_sink_ready;
assign soc_crossbar_sink_first = soc_litespiddrphycore_source_first;
assign soc_crossbar_sink_last = soc_litespiddrphycore_source_last;
assign soc_crossbar_sink_payload_data = soc_litespiddrphycore_source_payload_data;
assign soc_port_mmap_internal_port_sink_valid = soc_port_mmap_user_port_sink_valid;
assign soc_port_mmap_user_port_sink_ready = soc_port_mmap_internal_port_sink_ready;
assign soc_port_mmap_internal_port_sink_first = soc_port_mmap_user_port_sink_first;
assign soc_port_mmap_internal_port_sink_last = soc_port_mmap_user_port_sink_last;
assign soc_port_mmap_internal_port_sink_payload_data = soc_port_mmap_user_port_sink_payload_data;
assign soc_port_mmap_internal_port_sink_payload_len = soc_port_mmap_user_port_sink_payload_len;
assign soc_port_mmap_internal_port_sink_payload_width = soc_port_mmap_user_port_sink_payload_width;
assign soc_port_mmap_internal_port_sink_payload_mask = soc_port_mmap_user_port_sink_payload_mask;
assign soc_port_mmap_user_port_source_valid = soc_port_mmap_internal_port_source_valid;
assign soc_port_mmap_internal_port_source_ready = soc_port_mmap_user_port_source_ready;
assign soc_port_mmap_user_port_source_first = soc_port_mmap_internal_port_source_first;
assign soc_port_mmap_user_port_source_last = soc_port_mmap_internal_port_source_last;
assign soc_port_mmap_user_port_source_payload_data = soc_port_mmap_internal_port_source_payload_data;
assign soc_port_mmap_request = soc_litespimmap_cs;
assign soc_port_master_internal_port_sink_valid = soc_port_master_user_port_sink_valid;
assign soc_port_master_user_port_sink_ready = soc_port_master_internal_port_sink_ready;
assign soc_port_master_internal_port_sink_first = soc_port_master_user_port_sink_first;
assign soc_port_master_internal_port_sink_last = soc_port_master_user_port_sink_last;
assign soc_port_master_internal_port_sink_payload_data = soc_port_master_user_port_sink_payload_data;
assign soc_port_master_internal_port_sink_payload_len = soc_port_master_user_port_sink_payload_len;
assign soc_port_master_internal_port_sink_payload_width = soc_port_master_user_port_sink_payload_width;
assign soc_port_master_internal_port_sink_payload_mask = soc_port_master_user_port_sink_payload_mask;
assign soc_port_master_user_port_source_valid = soc_port_master_internal_port_source_valid;
assign soc_port_master_internal_port_source_ready = soc_port_master_user_port_source_ready;
assign soc_port_master_user_port_source_first = soc_port_master_internal_port_source_first;
assign soc_port_master_user_port_source_last = soc_port_master_internal_port_source_last;
assign soc_port_master_user_port_source_payload_data = soc_port_master_internal_port_source_payload_data;
assign soc_port_master_request = soc_master_cs;
assign vns_litespi_tx_mux_endpoint0_sink_valid = soc_port_mmap_internal_port_sink_valid;
assign soc_port_mmap_internal_port_sink_ready = vns_litespi_tx_mux_endpoint0_sink_ready;
assign vns_litespi_tx_mux_endpoint0_sink_first = soc_port_mmap_internal_port_sink_first;
assign vns_litespi_tx_mux_endpoint0_sink_last = soc_port_mmap_internal_port_sink_last;
assign vns_litespi_tx_mux_endpoint0_sink_payload_data = soc_port_mmap_internal_port_sink_payload_data;
assign vns_litespi_tx_mux_endpoint0_sink_payload_len = soc_port_mmap_internal_port_sink_payload_len;
assign vns_litespi_tx_mux_endpoint0_sink_payload_width = soc_port_mmap_internal_port_sink_payload_width;
assign vns_litespi_tx_mux_endpoint0_sink_payload_mask = soc_port_mmap_internal_port_sink_payload_mask;
assign soc_port_mmap_internal_port_source_valid = vns_litespi_rx_demux_endpoint0_source_valid;
assign vns_litespi_rx_demux_endpoint0_source_ready = soc_port_mmap_internal_port_source_ready;
assign soc_port_mmap_internal_port_source_first = vns_litespi_rx_demux_endpoint0_source_first;
assign soc_port_mmap_internal_port_source_last = vns_litespi_rx_demux_endpoint0_source_last;
assign soc_port_mmap_internal_port_source_payload_data = vns_litespi_rx_demux_endpoint0_source_payload_data;
assign vns_litespi_tx_mux_endpoint1_sink_valid = soc_port_master_internal_port_sink_valid;
assign soc_port_master_internal_port_sink_ready = vns_litespi_tx_mux_endpoint1_sink_ready;
assign vns_litespi_tx_mux_endpoint1_sink_first = soc_port_master_internal_port_sink_first;
assign vns_litespi_tx_mux_endpoint1_sink_last = soc_port_master_internal_port_sink_last;
assign vns_litespi_tx_mux_endpoint1_sink_payload_data = soc_port_master_internal_port_sink_payload_data;
assign vns_litespi_tx_mux_endpoint1_sink_payload_len = soc_port_master_internal_port_sink_payload_len;
assign vns_litespi_tx_mux_endpoint1_sink_payload_width = soc_port_master_internal_port_sink_payload_width;
assign vns_litespi_tx_mux_endpoint1_sink_payload_mask = soc_port_master_internal_port_sink_payload_mask;
assign soc_port_master_internal_port_source_valid = vns_litespi_rx_demux_endpoint1_source_valid;
assign vns_litespi_rx_demux_endpoint1_source_ready = soc_port_master_internal_port_source_ready;
assign soc_port_master_internal_port_source_first = vns_litespi_rx_demux_endpoint1_source_first;
assign soc_port_master_internal_port_source_last = vns_litespi_rx_demux_endpoint1_source_last;
assign soc_port_master_internal_port_source_payload_data = vns_litespi_rx_demux_endpoint1_source_payload_data;
assign vns_litespi_request = {soc_port_master_request, soc_port_mmap_request};
assign soc_crossbar_source_valid = vns_litespi_tx_mux_source_valid;
assign vns_litespi_tx_mux_source_ready = soc_crossbar_source_ready;
assign soc_crossbar_source_first = vns_litespi_tx_mux_source_first;
assign soc_crossbar_source_last = vns_litespi_tx_mux_source_last;
assign soc_crossbar_source_payload_data = vns_litespi_tx_mux_source_payload_data;
assign soc_crossbar_source_payload_len = vns_litespi_tx_mux_source_payload_len;
assign soc_crossbar_source_payload_width = vns_litespi_tx_mux_source_payload_width;
assign soc_crossbar_source_payload_mask = vns_litespi_tx_mux_source_payload_mask;
assign vns_litespi_tx_mux_sel = vns_litespi_grant;
assign vns_litespi_rx_demux_sink_valid = soc_crossbar_sink_valid;
assign soc_crossbar_sink_ready = vns_litespi_rx_demux_sink_ready;
assign vns_litespi_rx_demux_sink_first = soc_crossbar_sink_first;
assign vns_litespi_rx_demux_sink_last = soc_crossbar_sink_last;
assign vns_litespi_rx_demux_sink_payload_data = soc_crossbar_sink_payload_data;
assign vns_litespi_rx_demux_sel = vns_litespi_grant;
always @(*) begin
soc_crossbar_cs <= 1'd0;
case (vns_litespi_grant)
1'd0: begin
soc_crossbar_cs <= soc_litespimmap_cs;
end
1'd1: begin
soc_crossbar_cs <= soc_master_cs;
end
endcase
end
always @(*) begin
vns_litespi_tx_mux_source_valid <= 1'd0;
vns_litespi_tx_mux_endpoint1_sink_ready <= 1'd0;
vns_litespi_tx_mux_source_first <= 1'd0;
vns_litespi_tx_mux_source_last <= 1'd0;
vns_litespi_tx_mux_source_payload_data <= 32'd0;
vns_litespi_tx_mux_source_payload_len <= 6'd0;
vns_litespi_tx_mux_source_payload_width <= 4'd0;
vns_litespi_tx_mux_source_payload_mask <= 8'd0;
vns_litespi_tx_mux_endpoint0_sink_ready <= 1'd0;
case (vns_litespi_tx_mux_sel)
1'd0: begin
vns_litespi_tx_mux_source_valid <= vns_litespi_tx_mux_endpoint0_sink_valid;
vns_litespi_tx_mux_endpoint0_sink_ready <= vns_litespi_tx_mux_source_ready;
vns_litespi_tx_mux_source_first <= vns_litespi_tx_mux_endpoint0_sink_first;
vns_litespi_tx_mux_source_last <= vns_litespi_tx_mux_endpoint0_sink_last;
vns_litespi_tx_mux_source_payload_data <= vns_litespi_tx_mux_endpoint0_sink_payload_data;
vns_litespi_tx_mux_source_payload_len <= vns_litespi_tx_mux_endpoint0_sink_payload_len;
vns_litespi_tx_mux_source_payload_width <= vns_litespi_tx_mux_endpoint0_sink_payload_width;
vns_litespi_tx_mux_source_payload_mask <= vns_litespi_tx_mux_endpoint0_sink_payload_mask;
end
1'd1: begin
vns_litespi_tx_mux_source_valid <= vns_litespi_tx_mux_endpoint1_sink_valid;
vns_litespi_tx_mux_endpoint1_sink_ready <= vns_litespi_tx_mux_source_ready;
vns_litespi_tx_mux_source_first <= vns_litespi_tx_mux_endpoint1_sink_first;
vns_litespi_tx_mux_source_last <= vns_litespi_tx_mux_endpoint1_sink_last;
vns_litespi_tx_mux_source_payload_data <= vns_litespi_tx_mux_endpoint1_sink_payload_data;
vns_litespi_tx_mux_source_payload_len <= vns_litespi_tx_mux_endpoint1_sink_payload_len;
vns_litespi_tx_mux_source_payload_width <= vns_litespi_tx_mux_endpoint1_sink_payload_width;
vns_litespi_tx_mux_source_payload_mask <= vns_litespi_tx_mux_endpoint1_sink_payload_mask;
end
endcase
end
always @(*) begin
vns_litespi_rx_demux_endpoint0_source_first <= 1'd0;
vns_litespi_rx_demux_endpoint0_source_last <= 1'd0;
vns_litespi_rx_demux_endpoint0_source_payload_data <= 32'd0;
vns_litespi_rx_demux_endpoint1_source_valid <= 1'd0;
vns_litespi_rx_demux_endpoint1_source_first <= 1'd0;
vns_litespi_rx_demux_endpoint1_source_last <= 1'd0;
vns_litespi_rx_demux_endpoint1_source_payload_data <= 32'd0;
vns_litespi_rx_demux_sink_ready <= 1'd0;
vns_litespi_rx_demux_endpoint0_source_valid <= 1'd0;
case (vns_litespi_rx_demux_sel)
1'd0: begin
vns_litespi_rx_demux_endpoint0_source_valid <= vns_litespi_rx_demux_sink_valid;
vns_litespi_rx_demux_sink_ready <= vns_litespi_rx_demux_endpoint0_source_ready;
vns_litespi_rx_demux_endpoint0_source_first <= vns_litespi_rx_demux_sink_first;
vns_litespi_rx_demux_endpoint0_source_last <= vns_litespi_rx_demux_sink_last;
vns_litespi_rx_demux_endpoint0_source_payload_data <= vns_litespi_rx_demux_sink_payload_data;
end
1'd1: begin
vns_litespi_rx_demux_endpoint1_source_valid <= vns_litespi_rx_demux_sink_valid;
vns_litespi_rx_demux_sink_ready <= vns_litespi_rx_demux_endpoint1_source_ready;
vns_litespi_rx_demux_endpoint1_source_first <= vns_litespi_rx_demux_sink_first;
vns_litespi_rx_demux_endpoint1_source_last <= vns_litespi_rx_demux_sink_last;
vns_litespi_rx_demux_endpoint1_source_payload_data <= vns_litespi_rx_demux_sink_payload_data;
end
endcase
end
assign soc_litespimmap_spi_dummy_bits = soc_litespimmap_storage;
assign soc_litespimmap_done = (soc_litespimmap_count == 1'd0);
always @(*) begin
soc_litespimmap_cs <= 1'd0;
soc_litespimmap_wait <= 1'd0;
soc_litespimmap_source_valid <= 1'd0;
soc_litespimmap_source_last <= 1'd0;
soc_litespimmap_source_payload_data <= 32'd0;
vns_litespi_next_state <= 4'd0;
soc_litespimmap_source_payload_len <= 6'd0;
soc_litespimmap_burst_cs_litespi_next_value0 <= 1'd0;
soc_litespimmap_burst_cs_litespi_next_value_ce0 <= 1'd0;
soc_litespimmap_source_payload_width <= 4'd0;
soc_litespimmap_source_payload_mask <= 8'd0;
soc_litespimmap_sink_ready <= 1'd0;
soc_litespimmap_burst_adr_litespi_next_value1 <= 30'd0;
soc_litespimmap_burst_adr_litespi_next_value_ce1 <= 1'd0;
soc_litespimmap_bus_dat_r <= 32'd0;
soc_litespimmap_bus_ack <= 1'd0;
vns_litespi_next_state <= vns_litespi_state;
case (vns_litespi_state)
1'd1: begin
soc_litespimmap_cs <= 1'd1;
soc_litespimmap_source_valid <= 1'd1;
soc_litespimmap_source_payload_data <= 7'd107;
soc_litespimmap_source_payload_len <= 4'd8;
soc_litespimmap_source_payload_width <= 1'd1;
soc_litespimmap_source_payload_mask <= 1'd1;
soc_litespimmap_burst_adr_litespi_next_value1 <= soc_litespimmap_bus_adr;
soc_litespimmap_burst_adr_litespi_next_value_ce1 <= 1'd1;
if (soc_litespimmap_source_ready) begin
vns_litespi_next_state <= 2'd2;
end
end
2'd2: begin
soc_litespimmap_cs <= 1'd1;
soc_litespimmap_sink_ready <= 1'd1;
if (soc_litespimmap_sink_valid) begin
vns_litespi_next_state <= 2'd3;
end
end
2'd3: begin
soc_litespimmap_cs <= 1'd1;
soc_litespimmap_source_valid <= 1'd1;
soc_litespimmap_source_payload_width <= 1'd1;
soc_litespimmap_source_payload_mask <= 1'd1;
soc_litespimmap_source_payload_data <= {soc_litespimmap_bus_adr, soc_litespimmap};
soc_litespimmap_source_payload_len <= 5'd24;
soc_litespimmap_burst_cs_litespi_next_value0 <= 1'd1;
soc_litespimmap_burst_cs_litespi_next_value_ce0 <= 1'd1;
soc_litespimmap_burst_adr_litespi_next_value1 <= soc_litespimmap_bus_adr;
soc_litespimmap_burst_adr_litespi_next_value_ce1 <= 1'd1;
if (soc_litespimmap_source_ready) begin
vns_litespi_next_state <= 3'd4;
end
end
3'd4: begin
soc_litespimmap_cs <= 1'd1;
soc_litespimmap_sink_ready <= 1'd1;
if (soc_litespimmap_sink_valid) begin
if ((soc_litespimmap_spi_dummy_bits == 1'd0)) begin
vns_litespi_next_state <= 3'd7;
end else begin
vns_litespi_next_state <= 3'd5;
end
end
end
3'd5: begin
soc_litespimmap_cs <= 1'd1;
soc_litespimmap_source_valid <= 1'd1;
soc_litespimmap_source_payload_width <= 1'd1;
soc_litespimmap_source_payload_mask <= 1'd1;
soc_litespimmap_source_payload_data <= soc_litespimmap_dummy;
soc_litespimmap_source_payload_len <= soc_litespimmap_spi_dummy_bits;
soc_litespimmap_burst_cs_litespi_next_value0 <= 1'd1;
soc_litespimmap_burst_cs_litespi_next_value_ce0 <= 1'd1;
soc_litespimmap_burst_adr_litespi_next_value1 <= soc_litespimmap_bus_adr;
soc_litespimmap_burst_adr_litespi_next_value_ce1 <= 1'd1;
if (soc_litespimmap_source_ready) begin
vns_litespi_next_state <= 3'd6;
end
end
3'd6: begin
soc_litespimmap_cs <= 1'd1;
soc_litespimmap_sink_ready <= 1'd1;
if (soc_litespimmap_sink_valid) begin
vns_litespi_next_state <= 3'd7;
end
end
3'd7: begin
soc_litespimmap_cs <= 1'd1;
soc_litespimmap_source_valid <= 1'd1;
soc_litespimmap_source_last <= 1'd1;
soc_litespimmap_source_payload_width <= 3'd4;
soc_litespimmap_source_payload_len <= 6'd32;
soc_litespimmap_source_payload_mask <= 1'd0;
if (soc_litespimmap_source_ready) begin
vns_litespi_next_state <= 4'd8;
end
end
4'd8: begin
soc_litespimmap_cs <= 1'd1;
soc_litespimmap_sink_ready <= 1'd1;
soc_litespimmap_bus_dat_r <= {soc_litespimmap_sink_payload_data[7:0], soc_litespimmap_sink_payload_data[15:8], soc_litespimmap_sink_payload_data[23:16], soc_litespimmap_sink_payload_data[31:24]};
if (soc_litespimmap_sink_valid) begin
soc_litespimmap_bus_ack <= 1'd1;
soc_litespimmap_burst_adr_litespi_next_value1 <= (soc_litespimmap_burst_adr + 1'd1);
soc_litespimmap_burst_adr_litespi_next_value_ce1 <= 1'd1;
vns_litespi_next_state <= 1'd0;
end
end
default: begin
soc_litespimmap_wait <= 1'd1;
soc_litespimmap_burst_cs_litespi_next_value0 <= (soc_litespimmap_burst_cs & (~soc_litespimmap_done));
soc_litespimmap_burst_cs_litespi_next_value_ce0 <= 1'd1;
soc_litespimmap_cs <= soc_litespimmap_burst_cs;
if (((soc_litespimmap_bus_cyc & soc_litespimmap_bus_stb) & (~soc_litespimmap_bus_we))) begin
if ((soc_litespimmap_burst_cs & (soc_litespimmap_bus_adr == soc_litespimmap_burst_adr))) begin
vns_litespi_next_state <= 3'd7;
end else begin
soc_litespimmap_cs <= 1'd0;
vns_litespi_next_state <= 1'd1;
end
end
end
endcase
end
assign soc_master_rx_fifo_sink_valid = soc_master_sink_sink_valid;
assign soc_master_sink_sink_ready = soc_master_rx_fifo_sink_ready;
assign soc_master_rx_fifo_sink_first = soc_master_sink_sink_first;
assign soc_master_rx_fifo_sink_last = soc_master_sink_sink_last;
assign soc_master_rx_fifo_sink_payload_data = soc_master_sink_sink_payload_data;
assign soc_master_source_source_valid = soc_master_tx_fifo_source_valid;
assign soc_master_tx_fifo_source_ready = soc_master_source_source_ready;
assign soc_master_source_source_first = soc_master_tx_fifo_source_first;
assign soc_master_source_source_last = soc_master_tx_fifo_source_last;
assign soc_master_source_source_payload_data = soc_master_tx_fifo_source_payload_data;
assign soc_master_source_source_payload_len = soc_master_tx_fifo_source_payload_len;
assign soc_master_source_source_payload_width = soc_master_tx_fifo_source_payload_width;
assign soc_master_source_source_payload_mask = soc_master_tx_fifo_source_payload_mask;
assign soc_master_cs = soc_master_cs_storage;
assign soc_master_tx_fifo_sink_valid = soc_master_rxtx_re;
assign soc_master_tx_ready = soc_master_tx_fifo_sink_ready;
assign soc_master_tx_fifo_sink_payload_data = soc_master_rxtx_r;
assign soc_master_tx_fifo_sink_payload_len = soc_master_len;
assign soc_master_tx_fifo_sink_payload_width = soc_master_width;
assign soc_master_tx_fifo_sink_payload_mask = soc_master_mask;
assign soc_master_tx_fifo_sink_last = 1'd1;
assign soc_master_rx_fifo_source_ready = soc_master_rxtx_we;
assign soc_master_rx_ready = soc_master_rx_fifo_source_valid;
assign soc_master_rxtx_w = soc_master_rx_fifo_source_payload_data;
assign soc_master_tx_fifo_sink_ready = ((~soc_master_tx_fifo_source_valid) | soc_master_tx_fifo_source_ready);
assign soc_master_rx_fifo_sink_ready = ((~soc_master_rx_fifo_source_valid) | soc_master_rx_fifo_source_ready);
assign soc_wait = (~soc_done);
always @(*) begin
user_led0 <= 1'd0;
if ((soc_mode == 1'd1)) begin
{user_led0} <= soc_storage;
end else begin
{user_led0} <= soc_chaser;
end
end
assign soc_done = (soc_count == 1'd0);
assign soc_zero_trigger = (soc_value == 1'd0);
assign soc_zero0 = soc_zero_status;
assign soc_zero1 = soc_zero_pending;
always @(*) begin
soc_zero_clear <= 1'd0;
if ((soc_pending_re & soc_pending_r)) begin
soc_zero_clear <= 1'd1;
end
end
assign soc_irq = (soc_pending_status & soc_enable_storage);
assign soc_zero_status = soc_zero_trigger;
always @(*) begin
vns_hpssoc_adr <= 14'd0;
vns_hpssoc_we <= 1'd0;
vns_hpssoc_wishbone_ack <= 1'd0;
vns_next_state <= 1'd0;
vns_hpssoc_dat_w <= 32'd0;
vns_hpssoc_wishbone_dat_r <= 32'd0;
vns_next_state <= vns_state;
case (vns_state)
1'd1: begin
vns_hpssoc_wishbone_ack <= 1'd1;
vns_hpssoc_wishbone_dat_r <= vns_hpssoc_dat_r;
vns_next_state <= 1'd0;
end
default: begin
vns_hpssoc_dat_w <= vns_hpssoc_wishbone_dat_w;
if ((vns_hpssoc_wishbone_cyc & vns_hpssoc_wishbone_stb)) begin
vns_hpssoc_adr <= vns_hpssoc_wishbone_adr;
vns_hpssoc_we <= (vns_hpssoc_wishbone_we & (vns_hpssoc_wishbone_sel != 1'd0));
vns_next_state <= 1'd1;
end
end
endcase
end
assign vns_shared_adr = vns_array_muxed0;
assign vns_shared_dat_w = vns_array_muxed1;
assign vns_shared_sel = vns_array_muxed2;
assign vns_shared_cyc = vns_array_muxed3;
assign vns_shared_stb = vns_array_muxed4;
assign vns_shared_we = vns_array_muxed5;
assign vns_shared_cti = vns_array_muxed6;
assign vns_shared_bte = vns_array_muxed7;
assign soc_ibus_dat_r = vns_shared_dat_r;
assign soc_dbus_dat_r = vns_shared_dat_r;
assign soc_ibus_ack = (vns_shared_ack & (vns_grant == 1'd0));
assign soc_dbus_ack = (vns_shared_ack & (vns_grant == 1'd1));
assign soc_ibus_err = (vns_shared_err & (vns_grant == 1'd0));
assign soc_dbus_err = (vns_shared_err & (vns_grant == 1'd1));
assign vns_request = {soc_dbus_cyc, soc_ibus_cyc};
always @(*) begin
vns_slave_sel <= 3'd0;
vns_slave_sel[0] <= (vns_shared_adr[29:17] == 12'd2048);
vns_slave_sel[1] <= (vns_shared_adr[29:22] == 6'd32);
vns_slave_sel[2] <= (vns_shared_adr[29:14] == 16'd61440);
end
assign soc_bus_adr = vns_shared_adr;
assign soc_bus_dat_w = vns_shared_dat_w;
assign soc_bus_sel = vns_shared_sel;
assign soc_bus_stb = vns_shared_stb;
assign soc_bus_we = vns_shared_we;
assign soc_bus_cti = vns_shared_cti;
assign soc_bus_bte = vns_shared_bte;
assign soc_litespimmap_bus_adr = vns_shared_adr;
assign soc_litespimmap_bus_dat_w = vns_shared_dat_w;
assign soc_litespimmap_bus_sel = vns_shared_sel;
assign soc_litespimmap_bus_stb = vns_shared_stb;
assign soc_litespimmap_bus_we = vns_shared_we;
assign soc_litespimmap_bus_cti = vns_shared_cti;
assign soc_litespimmap_bus_bte = vns_shared_bte;
assign vns_hpssoc_wishbone_adr = vns_shared_adr;
assign vns_hpssoc_wishbone_dat_w = vns_shared_dat_w;
assign vns_hpssoc_wishbone_sel = vns_shared_sel;
assign vns_hpssoc_wishbone_stb = vns_shared_stb;
assign vns_hpssoc_wishbone_we = vns_shared_we;
assign vns_hpssoc_wishbone_cti = vns_shared_cti;
assign vns_hpssoc_wishbone_bte = vns_shared_bte;
assign soc_bus_cyc = (vns_shared_cyc & vns_slave_sel[0]);
assign soc_litespimmap_bus_cyc = (vns_shared_cyc & vns_slave_sel[1]);
assign vns_hpssoc_wishbone_cyc = (vns_shared_cyc & vns_slave_sel[2]);
assign vns_shared_err = ((soc_bus_err | soc_litespimmap_bus_err) | vns_hpssoc_wishbone_err);
assign vns_wait = ((vns_shared_stb & vns_shared_cyc) & (~vns_shared_ack));
always @(*) begin
vns_shared_dat_r <= 32'd0;
vns_error <= 1'd0;
vns_shared_ack <= 1'd0;
vns_shared_ack <= ((soc_bus_ack | soc_litespimmap_bus_ack) | vns_hpssoc_wishbone_ack);
vns_shared_dat_r <= ((({32{vns_slave_sel_r[0]}} & soc_bus_dat_r) | ({32{vns_slave_sel_r[1]}} & soc_litespimmap_bus_dat_r)) | ({32{vns_slave_sel_r[2]}} & vns_hpssoc_wishbone_dat_r));
if (vns_done) begin
vns_shared_dat_r <= 32'd4294967295;
vns_shared_ack <= 1'd1;
vns_error <= 1'd1;
end
end
assign vns_done = (vns_count == 1'd0);
assign vns_csrbank0_sel = (vns_interface0_bank_bus_adr[13:9] == 2'd3);
assign vns_csrbank0_reset0_r = vns_interface0_bank_bus_dat_w[1:0];
always @(*) begin
vns_csrbank0_reset0_we <= 1'd0;
vns_csrbank0_reset0_re <= 1'd0;
if ((vns_csrbank0_sel & (vns_interface0_bank_bus_adr[8:0] == 1'd0))) begin
vns_csrbank0_reset0_re <= vns_interface0_bank_bus_we;
vns_csrbank0_reset0_we <= (~vns_interface0_bank_bus_we);
end
end
assign vns_csrbank0_scratch0_r = vns_interface0_bank_bus_dat_w[31:0];
always @(*) begin
vns_csrbank0_scratch0_re <= 1'd0;
vns_csrbank0_scratch0_we <= 1'd0;
if ((vns_csrbank0_sel & (vns_interface0_bank_bus_adr[8:0] == 1'd1))) begin
vns_csrbank0_scratch0_re <= vns_interface0_bank_bus_we;
vns_csrbank0_scratch0_we <= (~vns_interface0_bank_bus_we);
end
end
assign vns_csrbank0_bus_errors_r = vns_interface0_bank_bus_dat_w[31:0];
always @(*) begin
vns_csrbank0_bus_errors_we <= 1'd0;
vns_csrbank0_bus_errors_re <= 1'd0;
if ((vns_csrbank0_sel & (vns_interface0_bank_bus_adr[8:0] == 2'd2))) begin
vns_csrbank0_bus_errors_re <= vns_interface0_bank_bus_we;
vns_csrbank0_bus_errors_we <= (~vns_interface0_bank_bus_we);
end
end
always @(*) begin
soc_soc_rst <= 1'd0;
if (soc_reset_re) begin
soc_soc_rst <= soc_reset_storage[0];
end
end
assign soc_cpu_rst = soc_reset_storage[1];
assign vns_csrbank0_reset0_w = soc_reset_storage[1:0];
assign vns_csrbank0_scratch0_w = soc_scratch_storage[31:0];
assign vns_csrbank0_bus_errors_w = soc_bus_errors_status[31:0];
assign soc_bus_errors_we = vns_csrbank0_bus_errors_we;
assign vns_csrbank1_sel = (vns_interface1_bank_bus_adr[13:9] == 2'd2);
assign vns_csrbank1_out0_r = vns_interface1_bank_bus_dat_w[0];
always @(*) begin
vns_csrbank1_out0_re <= 1'd0;
vns_csrbank1_out0_we <= 1'd0;
if ((vns_csrbank1_sel & (vns_interface1_bank_bus_adr[8:0] == 1'd0))) begin
vns_csrbank1_out0_re <= vns_interface1_bank_bus_we;
vns_csrbank1_out0_we <= (~vns_interface1_bank_bus_we);
end
end
assign vns_csrbank1_out0_w = soc_storage;
assign vns_csrbank2_sel = (vns_interface2_bank_bus_adr[13:9] == 1'd0);
assign vns_csrbank2_mmap_dummy_bits0_r = vns_interface2_bank_bus_dat_w[7:0];
always @(*) begin
vns_csrbank2_mmap_dummy_bits0_we <= 1'd0;
vns_csrbank2_mmap_dummy_bits0_re <= 1'd0;
if ((vns_csrbank2_sel & (vns_interface2_bank_bus_adr[8:0] == 1'd0))) begin
vns_csrbank2_mmap_dummy_bits0_re <= vns_interface2_bank_bus_we;
vns_csrbank2_mmap_dummy_bits0_we <= (~vns_interface2_bank_bus_we);
end
end
assign vns_csrbank2_master_cs0_r = vns_interface2_bank_bus_dat_w[0];
always @(*) begin
vns_csrbank2_master_cs0_we <= 1'd0;
vns_csrbank2_master_cs0_re <= 1'd0;
if ((vns_csrbank2_sel & (vns_interface2_bank_bus_adr[8:0] == 1'd1))) begin
vns_csrbank2_master_cs0_re <= vns_interface2_bank_bus_we;
vns_csrbank2_master_cs0_we <= (~vns_interface2_bank_bus_we);
end
end
assign vns_csrbank2_master_phyconfig0_r = vns_interface2_bank_bus_dat_w[23:0];
always @(*) begin
vns_csrbank2_master_phyconfig0_re <= 1'd0;
vns_csrbank2_master_phyconfig0_we <= 1'd0;
if ((vns_csrbank2_sel & (vns_interface2_bank_bus_adr[8:0] == 2'd2))) begin
vns_csrbank2_master_phyconfig0_re <= vns_interface2_bank_bus_we;
vns_csrbank2_master_phyconfig0_we <= (~vns_interface2_bank_bus_we);
end
end
assign soc_master_rxtx_r = vns_interface2_bank_bus_dat_w[31:0];
always @(*) begin
soc_master_rxtx_we <= 1'd0;
soc_master_rxtx_re <= 1'd0;
if ((vns_csrbank2_sel & (vns_interface2_bank_bus_adr[8:0] == 2'd3))) begin
soc_master_rxtx_re <= vns_interface2_bank_bus_we;
soc_master_rxtx_we <= (~vns_interface2_bank_bus_we);
end
end
assign vns_csrbank2_master_status_r = vns_interface2_bank_bus_dat_w[1:0];
always @(*) begin
vns_csrbank2_master_status_we <= 1'd0;
vns_csrbank2_master_status_re <= 1'd0;
if ((vns_csrbank2_sel & (vns_interface2_bank_bus_adr[8:0] == 3'd4))) begin
vns_csrbank2_master_status_re <= vns_interface2_bank_bus_we;
vns_csrbank2_master_status_we <= (~vns_interface2_bank_bus_we);
end
end
assign vns_csrbank2_mmap_dummy_bits0_w = soc_litespimmap_storage[7:0];
assign vns_csrbank2_master_cs0_w = soc_master_cs_storage;
assign soc_master_len = soc_master_phyconfig_storage[7:0];
assign soc_master_width = soc_master_phyconfig_storage[11:8];
assign soc_master_mask = soc_master_phyconfig_storage[23:16];
assign vns_csrbank2_master_phyconfig0_w = soc_master_phyconfig_storage[23:0];
always @(*) begin
soc_master_status_status <= 2'd0;
soc_master_status_status[0] <= soc_master_tx_ready;
soc_master_status_status[1] <= soc_master_rx_ready;
end
assign vns_csrbank2_master_status_w = soc_master_status_status[1:0];
assign soc_master_status_we = vns_csrbank2_master_status_we;
assign vns_csrbank3_sel = (vns_interface3_bank_bus_adr[13:9] == 3'd4);
assign vns_csrbank3_load0_r = vns_interface3_bank_bus_dat_w[31:0];
always @(*) begin
vns_csrbank3_load0_re <= 1'd0;
vns_csrbank3_load0_we <= 1'd0;
if ((vns_csrbank3_sel & (vns_interface3_bank_bus_adr[8:0] == 1'd0))) begin
vns_csrbank3_load0_re <= vns_interface3_bank_bus_we;
vns_csrbank3_load0_we <= (~vns_interface3_bank_bus_we);
end
end
assign vns_csrbank3_reload0_r = vns_interface3_bank_bus_dat_w[31:0];
always @(*) begin
vns_csrbank3_reload0_we <= 1'd0;
vns_csrbank3_reload0_re <= 1'd0;
if ((vns_csrbank3_sel & (vns_interface3_bank_bus_adr[8:0] == 1'd1))) begin
vns_csrbank3_reload0_re <= vns_interface3_bank_bus_we;
vns_csrbank3_reload0_we <= (~vns_interface3_bank_bus_we);
end
end
assign vns_csrbank3_en0_r = vns_interface3_bank_bus_dat_w[0];
always @(*) begin
vns_csrbank3_en0_we <= 1'd0;
vns_csrbank3_en0_re <= 1'd0;
if ((vns_csrbank3_sel & (vns_interface3_bank_bus_adr[8:0] == 2'd2))) begin
vns_csrbank3_en0_re <= vns_interface3_bank_bus_we;
vns_csrbank3_en0_we <= (~vns_interface3_bank_bus_we);
end
end
assign vns_csrbank3_update_value0_r = vns_interface3_bank_bus_dat_w[0];
always @(*) begin
vns_csrbank3_update_value0_re <= 1'd0;
vns_csrbank3_update_value0_we <= 1'd0;
if ((vns_csrbank3_sel & (vns_interface3_bank_bus_adr[8:0] == 2'd3))) begin
vns_csrbank3_update_value0_re <= vns_interface3_bank_bus_we;
vns_csrbank3_update_value0_we <= (~vns_interface3_bank_bus_we);
end
end
assign vns_csrbank3_value_r = vns_interface3_bank_bus_dat_w[31:0];
always @(*) begin
vns_csrbank3_value_we <= 1'd0;
vns_csrbank3_value_re <= 1'd0;
if ((vns_csrbank3_sel & (vns_interface3_bank_bus_adr[8:0] == 3'd4))) begin
vns_csrbank3_value_re <= vns_interface3_bank_bus_we;
vns_csrbank3_value_we <= (~vns_interface3_bank_bus_we);
end
end
assign vns_csrbank3_ev_status_r = vns_interface3_bank_bus_dat_w[0];
always @(*) begin
vns_csrbank3_ev_status_we <= 1'd0;
vns_csrbank3_ev_status_re <= 1'd0;
if ((vns_csrbank3_sel & (vns_interface3_bank_bus_adr[8:0] == 3'd5))) begin
vns_csrbank3_ev_status_re <= vns_interface3_bank_bus_we;
vns_csrbank3_ev_status_we <= (~vns_interface3_bank_bus_we);
end
end
assign vns_csrbank3_ev_pending_r = vns_interface3_bank_bus_dat_w[0];
always @(*) begin
vns_csrbank3_ev_pending_re <= 1'd0;
vns_csrbank3_ev_pending_we <= 1'd0;
if ((vns_csrbank3_sel & (vns_interface3_bank_bus_adr[8:0] == 3'd6))) begin
vns_csrbank3_ev_pending_re <= vns_interface3_bank_bus_we;
vns_csrbank3_ev_pending_we <= (~vns_interface3_bank_bus_we);
end
end
assign vns_csrbank3_ev_enable0_r = vns_interface3_bank_bus_dat_w[0];
always @(*) begin
vns_csrbank3_ev_enable0_we <= 1'd0;
vns_csrbank3_ev_enable0_re <= 1'd0;
if ((vns_csrbank3_sel & (vns_interface3_bank_bus_adr[8:0] == 3'd7))) begin
vns_csrbank3_ev_enable0_re <= vns_interface3_bank_bus_we;
vns_csrbank3_ev_enable0_we <= (~vns_interface3_bank_bus_we);
end
end
assign vns_csrbank3_uptime_latch0_r = vns_interface3_bank_bus_dat_w[0];
always @(*) begin
vns_csrbank3_uptime_latch0_we <= 1'd0;
vns_csrbank3_uptime_latch0_re <= 1'd0;
if ((vns_csrbank3_sel & (vns_interface3_bank_bus_adr[8:0] == 4'd8))) begin
vns_csrbank3_uptime_latch0_re <= vns_interface3_bank_bus_we;
vns_csrbank3_uptime_latch0_we <= (~vns_interface3_bank_bus_we);
end
end
assign vns_csrbank3_uptime_cycles1_r = vns_interface3_bank_bus_dat_w[31:0];
always @(*) begin
vns_csrbank3_uptime_cycles1_re <= 1'd0;
vns_csrbank3_uptime_cycles1_we <= 1'd0;
if ((vns_csrbank3_sel & (vns_interface3_bank_bus_adr[8:0] == 4'd9))) begin
vns_csrbank3_uptime_cycles1_re <= vns_interface3_bank_bus_we;
vns_csrbank3_uptime_cycles1_we <= (~vns_interface3_bank_bus_we);
end
end
assign vns_csrbank3_uptime_cycles0_r = vns_interface3_bank_bus_dat_w[31:0];
always @(*) begin
vns_csrbank3_uptime_cycles0_we <= 1'd0;
vns_csrbank3_uptime_cycles0_re <= 1'd0;
if ((vns_csrbank3_sel & (vns_interface3_bank_bus_adr[8:0] == 4'd10))) begin
vns_csrbank3_uptime_cycles0_re <= vns_interface3_bank_bus_we;
vns_csrbank3_uptime_cycles0_we <= (~vns_interface3_bank_bus_we);
end
end
assign vns_csrbank3_load0_w = soc_load_storage[31:0];
assign vns_csrbank3_reload0_w = soc_reload_storage[31:0];
assign vns_csrbank3_en0_w = soc_en_storage;
assign vns_csrbank3_update_value0_w = soc_update_value_storage;
assign vns_csrbank3_value_w = soc_value_status[31:0];
assign soc_value_we = vns_csrbank3_value_we;
assign soc_status_status = soc_zero0;
assign vns_csrbank3_ev_status_w = soc_status_status;
assign soc_status_we = vns_csrbank3_ev_status_we;
assign soc_pending_status = soc_zero1;
assign vns_csrbank3_ev_pending_w = soc_pending_status;
assign soc_pending_we = vns_csrbank3_ev_pending_we;
assign soc_zero2 = soc_enable_storage;
assign vns_csrbank3_ev_enable0_w = soc_enable_storage;
assign vns_csrbank3_uptime_latch0_w = soc_uptime_latch_storage;
assign vns_csrbank3_uptime_cycles1_w = soc_uptime_cycles_status[63:32];
assign vns_csrbank3_uptime_cycles0_w = soc_uptime_cycles_status[31:0];
assign soc_uptime_cycles_we = vns_csrbank3_uptime_cycles0_we;
assign vns_csr_interconnect_adr = vns_hpssoc_adr;
assign vns_csr_interconnect_we = vns_hpssoc_we;
assign vns_csr_interconnect_dat_w = vns_hpssoc_dat_w;
assign vns_hpssoc_dat_r = vns_csr_interconnect_dat_r;
assign vns_interface0_bank_bus_adr = vns_csr_interconnect_adr;
assign vns_interface1_bank_bus_adr = vns_csr_interconnect_adr;
assign vns_interface2_bank_bus_adr = vns_csr_interconnect_adr;
assign vns_interface3_bank_bus_adr = vns_csr_interconnect_adr;
assign vns_interface0_bank_bus_we = vns_csr_interconnect_we;
assign vns_interface1_bank_bus_we = vns_csr_interconnect_we;
assign vns_interface2_bank_bus_we = vns_csr_interconnect_we;
assign vns_interface3_bank_bus_we = vns_csr_interconnect_we;
assign vns_interface0_bank_bus_dat_w = vns_csr_interconnect_dat_w;
assign vns_interface1_bank_bus_dat_w = vns_csr_interconnect_dat_w;
assign vns_interface2_bank_bus_dat_w = vns_csr_interconnect_dat_w;
assign vns_interface3_bank_bus_dat_w = vns_csr_interconnect_dat_w;
assign vns_csr_interconnect_dat_r = (((vns_interface0_bank_bus_dat_r | vns_interface1_bank_bus_dat_r) | vns_interface2_bank_bus_dat_r) | vns_interface3_bank_bus_dat_r);
always @(*) begin
vns_array_muxed0 <= 30'd0;
case (vns_grant)
1'd0: begin
vns_array_muxed0 <= soc_ibus_adr;
end
default: begin
vns_array_muxed0 <= soc_dbus_adr;
end
endcase
end
always @(*) begin
vns_array_muxed1 <= 32'd0;
case (vns_grant)
1'd0: begin
vns_array_muxed1 <= soc_ibus_dat_w;
end
default: begin
vns_array_muxed1 <= soc_dbus_dat_w;
end
endcase
end
always @(*) begin
vns_array_muxed2 <= 4'd0;
case (vns_grant)
1'd0: begin
vns_array_muxed2 <= soc_ibus_sel;
end
default: begin
vns_array_muxed2 <= soc_dbus_sel;
end
endcase
end
always @(*) begin
vns_array_muxed3 <= 1'd0;
case (vns_grant)
1'd0: begin
vns_array_muxed3 <= soc_ibus_cyc;
end
default: begin
vns_array_muxed3 <= soc_dbus_cyc;
end
endcase
end
always @(*) begin
vns_array_muxed4 <= 1'd0;
case (vns_grant)
1'd0: begin
vns_array_muxed4 <= soc_ibus_stb;
end
default: begin
vns_array_muxed4 <= soc_dbus_stb;
end
endcase
end
always @(*) begin
vns_array_muxed5 <= 1'd0;
case (vns_grant)
1'd0: begin
vns_array_muxed5 <= soc_ibus_we;
end
default: begin
vns_array_muxed5 <= soc_dbus_we;
end
endcase
end
always @(*) begin
vns_array_muxed6 <= 3'd0;
case (vns_grant)
1'd0: begin
vns_array_muxed6 <= soc_ibus_cti;
end
default: begin
vns_array_muxed6 <= soc_dbus_cti;
end
endcase
end
always @(*) begin
vns_array_muxed7 <= 2'd0;
case (vns_grant)
1'd0: begin
vns_array_muxed7 <= soc_ibus_bte;
end
default: begin
vns_array_muxed7 <= soc_dbus_bte;
end
endcase
end
always @(posedge por_clk) begin
if ((soc_por_counter != 1'd0)) begin
soc_por_counter <= (soc_por_counter - 1'd1);
end
if (por_rst) begin
soc_por_counter <= 12'd4095;
end
end
always @(posedge sys_clk) begin
if ((soc_bus_errors != 32'd4294967295)) begin
if (soc_bus_error) begin
soc_bus_errors <= (soc_bus_errors + 1'd1);
end
end
soc_bus_ack <= ((soc_bus_stb & soc_bus_cyc) & (~soc_bus_ack));
if (soc_litespiddrphycore_sr_out_load) begin
soc_litespiddrphycore_sr_out <= (soc_litespiddrphycore_sink_payload_data <<< (6'd32 - soc_litespiddrphycore_sink_payload_len));
end
if (soc_litespiddrphycore_sr_out_shift) begin
soc_litespiddrphycore4 <= soc_litespiddrphycore5;
soc_litespiddrphycore0 <= soc_litespiddrphycore1;
case (soc_litespiddrphycore_sink_payload_width)
1'd1: begin
soc_litespiddrphycore_sr_out <= {soc_litespiddrphycore_sr_out, soc_litespiddrphycore6};
end
2'd2: begin
soc_litespiddrphycore_sr_out <= {soc_litespiddrphycore_sr_out, soc_litespiddrphycore7};
end
3'd4: begin
soc_litespiddrphycore_sr_out <= {soc_litespiddrphycore_sr_out, soc_litespiddrphycore8};
end
4'd8: begin
soc_litespiddrphycore_sr_out <= {soc_litespiddrphycore_sr_out, soc_litespiddrphycore9};
end
endcase
end
if (soc_litespiddrphycore_sr_in_shift) begin
case (soc_litespiddrphycore_sink_payload_width)
1'd1: begin
soc_litespiddrphycore_sr_in <= {soc_litespiddrphycore_sr_in, soc_litespiddrphycore2[1]};
end
2'd2: begin
soc_litespiddrphycore_sr_in <= {soc_litespiddrphycore_sr_in, soc_litespiddrphycore2[1:0]};
end
3'd4: begin
soc_litespiddrphycore_sr_in <= {soc_litespiddrphycore_sr_in, soc_litespiddrphycore2[3:0]};
end
4'd8: begin
soc_litespiddrphycore_sr_in <= {soc_litespiddrphycore_sr_in, soc_litespiddrphycore2[3:0]};
end
endcase
end
if (soc_litespiddrphycore_wait) begin
if ((~soc_litespiddrphycore_done)) begin
soc_litespiddrphycore_count <= (soc_litespiddrphycore_count - 1'd1);
end
end else begin
soc_litespiddrphycore_count <= 4'd11;
end
vns_litespiphy_state <= vns_litespiphy_next_state;
if (soc_litespiddrphycore_en_litespiphy_next_value_ce0) begin
soc_litespiddrphycore_en <= soc_litespiddrphycore_en_litespiphy_next_value0;
end
if (soc_litespiddrphycore_sr_cnt_litespiphy_next_value_ce1) begin
soc_litespiddrphycore_sr_cnt <= soc_litespiddrphycore_sr_cnt_litespiphy_next_value1;
end
case (vns_litespi_grant)
1'd0: begin
if ((~vns_litespi_request[0])) begin
if (vns_litespi_request[1]) begin
vns_litespi_grant <= 1'd1;
end
end
end
1'd1: begin
if ((~vns_litespi_request[1])) begin
if (vns_litespi_request[0]) begin
vns_litespi_grant <= 1'd0;
end
end
end
endcase
if (soc_litespimmap_wait) begin
if ((~soc_litespimmap_done)) begin
soc_litespimmap_count <= (soc_litespimmap_count - 1'd1);
end
end else begin
soc_litespimmap_count <= 9'd256;
end
vns_litespi_state <= vns_litespi_next_state;
if (soc_litespimmap_burst_cs_litespi_next_value_ce0) begin
soc_litespimmap_burst_cs <= soc_litespimmap_burst_cs_litespi_next_value0;
end
if (soc_litespimmap_burst_adr_litespi_next_value_ce1) begin
soc_litespimmap_burst_adr <= soc_litespimmap_burst_adr_litespi_next_value1;
end
if (((~soc_master_tx_fifo_source_valid) | soc_master_tx_fifo_source_ready)) begin
soc_master_tx_fifo_source_valid <= soc_master_tx_fifo_sink_valid;
soc_master_tx_fifo_source_first <= soc_master_tx_fifo_sink_first;
soc_master_tx_fifo_source_last <= soc_master_tx_fifo_sink_last;
soc_master_tx_fifo_source_payload_data <= soc_master_tx_fifo_sink_payload_data;
soc_master_tx_fifo_source_payload_len <= soc_master_tx_fifo_sink_payload_len;
soc_master_tx_fifo_source_payload_width <= soc_master_tx_fifo_sink_payload_width;
soc_master_tx_fifo_source_payload_mask <= soc_master_tx_fifo_sink_payload_mask;
end
if (((~soc_master_rx_fifo_source_valid) | soc_master_rx_fifo_source_ready)) begin
soc_master_rx_fifo_source_valid <= soc_master_rx_fifo_sink_valid;
soc_master_rx_fifo_source_first <= soc_master_rx_fifo_sink_first;
soc_master_rx_fifo_source_last <= soc_master_rx_fifo_sink_last;
soc_master_rx_fifo_source_payload_data <= soc_master_rx_fifo_sink_payload_data;
end
if (soc_done) begin
soc_chaser <= {soc_chaser, (~soc_chaser)};
end
if (soc_re) begin
soc_mode <= 1'd1;
end
if (soc_wait) begin
if ((~soc_done)) begin
soc_count <= (soc_count - 1'd1);
end
end else begin
soc_count <= 25'd32142857;
end
if (soc_en_storage) begin
if ((soc_value == 1'd0)) begin
soc_value <= soc_reload_storage;
end else begin
soc_value <= (soc_value - 1'd1);
end
end else begin
soc_value <= soc_load_storage;
end
if (soc_update_value_re) begin
soc_value_status <= soc_value;
end
soc_uptime_cycles <= (soc_uptime_cycles + 1'd1);
if (soc_uptime_latch_re) begin
soc_uptime_cycles_status <= soc_uptime_cycles;
end
if (soc_zero_clear) begin
soc_zero_pending <= 1'd0;
end
soc_zero_trigger_d <= soc_zero_trigger;
if ((soc_zero_trigger & (~soc_zero_trigger_d))) begin
soc_zero_pending <= 1'd1;
end
vns_state <= vns_next_state;
case (vns_grant)
1'd0: begin
if ((~vns_request[0])) begin
if (vns_request[1]) begin
vns_grant <= 1'd1;
end
end
end
1'd1: begin
if ((~vns_request[1])) begin
if (vns_request[0]) begin
vns_grant <= 1'd0;
end
end
end
endcase
vns_slave_sel_r <= vns_slave_sel;
if (vns_wait) begin
if ((~vns_done)) begin
vns_count <= (vns_count - 1'd1);
end
end else begin
vns_count <= 20'd1000000;
end
vns_interface0_bank_bus_dat_r <= 1'd0;
if (vns_csrbank0_sel) begin
case (vns_interface0_bank_bus_adr[8:0])
1'd0: begin
vns_interface0_bank_bus_dat_r <= vns_csrbank0_reset0_w;
end
1'd1: begin
vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch0_w;
end
2'd2: begin
vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors_w;
end
endcase
end
if (vns_csrbank0_reset0_re) begin
soc_reset_storage[1:0] <= vns_csrbank0_reset0_r;
end
soc_reset_re <= vns_csrbank0_reset0_re;
if (vns_csrbank0_scratch0_re) begin
soc_scratch_storage[31:0] <= vns_csrbank0_scratch0_r;
end
soc_scratch_re <= vns_csrbank0_scratch0_re;
soc_bus_errors_re <= vns_csrbank0_bus_errors_re;
vns_interface1_bank_bus_dat_r <= 1'd0;
if (vns_csrbank1_sel) begin
case (vns_interface1_bank_bus_adr[8:0])
1'd0: begin
vns_interface1_bank_bus_dat_r <= vns_csrbank1_out0_w;
end
endcase
end
if (vns_csrbank1_out0_re) begin
soc_storage <= vns_csrbank1_out0_r;
end
soc_re <= vns_csrbank1_out0_re;
vns_interface2_bank_bus_dat_r <= 1'd0;
if (vns_csrbank2_sel) begin
case (vns_interface2_bank_bus_adr[8:0])
1'd0: begin
vns_interface2_bank_bus_dat_r <= vns_csrbank2_mmap_dummy_bits0_w;
end
1'd1: begin
vns_interface2_bank_bus_dat_r <= vns_csrbank2_master_cs0_w;
end
2'd2: begin
vns_interface2_bank_bus_dat_r <= vns_csrbank2_master_phyconfig0_w;
end
2'd3: begin
vns_interface2_bank_bus_dat_r <= soc_master_rxtx_w;
end
3'd4: begin
vns_interface2_bank_bus_dat_r <= vns_csrbank2_master_status_w;
end
endcase
end
if (vns_csrbank2_mmap_dummy_bits0_re) begin
soc_litespimmap_storage[7:0] <= vns_csrbank2_mmap_dummy_bits0_r;
end
soc_litespimmap_re <= vns_csrbank2_mmap_dummy_bits0_re;
if (vns_csrbank2_master_cs0_re) begin
soc_master_cs_storage <= vns_csrbank2_master_cs0_r;
end
soc_master_cs_re <= vns_csrbank2_master_cs0_re;
if (vns_csrbank2_master_phyconfig0_re) begin
soc_master_phyconfig_storage[23:0] <= vns_csrbank2_master_phyconfig0_r;
end
soc_master_phyconfig_re <= vns_csrbank2_master_phyconfig0_re;
soc_master_status_re <= vns_csrbank2_master_status_re;
vns_interface3_bank_bus_dat_r <= 1'd0;
if (vns_csrbank3_sel) begin
case (vns_interface3_bank_bus_adr[8:0])
1'd0: begin
vns_interface3_bank_bus_dat_r <= vns_csrbank3_load0_w;
end
1'd1: begin
vns_interface3_bank_bus_dat_r <= vns_csrbank3_reload0_w;
end
2'd2: begin
vns_interface3_bank_bus_dat_r <= vns_csrbank3_en0_w;
end
2'd3: begin
vns_interface3_bank_bus_dat_r <= vns_csrbank3_update_value0_w;
end
3'd4: begin
vns_interface3_bank_bus_dat_r <= vns_csrbank3_value_w;
end
3'd5: begin
vns_interface3_bank_bus_dat_r <= vns_csrbank3_ev_status_w;
end
3'd6: begin
vns_interface3_bank_bus_dat_r <= vns_csrbank3_ev_pending_w;
end
3'd7: begin
vns_interface3_bank_bus_dat_r <= vns_csrbank3_ev_enable0_w;
end
4'd8: begin
vns_interface3_bank_bus_dat_r <= vns_csrbank3_uptime_latch0_w;
end
4'd9: begin
vns_interface3_bank_bus_dat_r <= vns_csrbank3_uptime_cycles1_w;
end
4'd10: begin
vns_interface3_bank_bus_dat_r <= vns_csrbank3_uptime_cycles0_w;
end
endcase
end
if (vns_csrbank3_load0_re) begin
soc_load_storage[31:0] <= vns_csrbank3_load0_r;
end
soc_load_re <= vns_csrbank3_load0_re;
if (vns_csrbank3_reload0_re) begin
soc_reload_storage[31:0] <= vns_csrbank3_reload0_r;
end
soc_reload_re <= vns_csrbank3_reload0_re;
if (vns_csrbank3_en0_re) begin
soc_en_storage <= vns_csrbank3_en0_r;
end
soc_en_re <= vns_csrbank3_en0_re;
if (vns_csrbank3_update_value0_re) begin
soc_update_value_storage <= vns_csrbank3_update_value0_r;
end
soc_update_value_re <= vns_csrbank3_update_value0_re;
soc_value_re <= vns_csrbank3_value_re;
soc_status_re <= vns_csrbank3_ev_status_re;
if (vns_csrbank3_ev_pending_re) begin
soc_pending_r <= vns_csrbank3_ev_pending_r;
end
soc_pending_re <= vns_csrbank3_ev_pending_re;
if (vns_csrbank3_ev_enable0_re) begin
soc_enable_storage <= vns_csrbank3_ev_enable0_r;
end
soc_enable_re <= vns_csrbank3_ev_enable0_re;
if (vns_csrbank3_uptime_latch0_re) begin
soc_uptime_latch_storage <= vns_csrbank3_uptime_latch0_r;
end
soc_uptime_latch_re <= vns_csrbank3_uptime_latch0_re;
soc_uptime_cycles_re <= vns_csrbank3_uptime_cycles0_re;
if (sys_rst) begin
soc_reset_storage <= 2'd0;
soc_reset_re <= 1'd0;
soc_scratch_storage <= 32'd305419896;
soc_scratch_re <= 1'd0;
soc_bus_errors_re <= 1'd0;
soc_bus_errors <= 32'd0;
soc_bus_ack <= 1'd0;
soc_litespiddrphycore_en <= 1'd0;
soc_litespiddrphycore_count <= 4'd11;
soc_litespiddrphycore0 <= 4'd0;
soc_litespiddrphycore4 <= 4'd0;
soc_litespimmap_burst_cs <= 1'd0;
soc_litespimmap_count <= 9'd256;
soc_litespimmap_storage <= 8'd8;
soc_litespimmap_re <= 1'd0;
soc_master_cs_storage <= 1'd0;
soc_master_cs_re <= 1'd0;
soc_master_phyconfig_storage <= 24'd0;
soc_master_phyconfig_re <= 1'd0;
soc_master_status_re <= 1'd0;
soc_master_tx_fifo_source_valid <= 1'd0;
soc_master_tx_fifo_source_payload_data <= 32'd0;
soc_master_tx_fifo_source_payload_len <= 6'd0;
soc_master_tx_fifo_source_payload_width <= 4'd0;
soc_master_tx_fifo_source_payload_mask <= 8'd0;
soc_master_rx_fifo_source_valid <= 1'd0;
soc_master_rx_fifo_source_payload_data <= 32'd0;
soc_storage <= 1'd0;
soc_re <= 1'd0;
soc_chaser <= 1'd0;
soc_mode <= 1'd0;
soc_count <= 25'd32142857;
soc_load_storage <= 32'd0;
soc_load_re <= 1'd0;
soc_reload_storage <= 32'd0;
soc_reload_re <= 1'd0;
soc_en_storage <= 1'd0;
soc_en_re <= 1'd0;
soc_update_value_storage <= 1'd0;
soc_update_value_re <= 1'd0;
soc_value_status <= 32'd0;
soc_value_re <= 1'd0;
soc_zero_pending <= 1'd0;
soc_zero_trigger_d <= 1'd0;
soc_status_re <= 1'd0;
soc_pending_re <= 1'd0;
soc_pending_r <= 1'd0;
soc_enable_storage <= 1'd0;
soc_enable_re <= 1'd0;
soc_value <= 32'd0;
soc_uptime_latch_storage <= 1'd0;
soc_uptime_latch_re <= 1'd0;
soc_uptime_cycles_status <= 64'd0;
soc_uptime_cycles_re <= 1'd0;
vns_litespiphy_state <= 2'd0;
vns_litespi_grant <= 1'd0;
vns_litespi_state <= 4'd0;
vns_grant <= 1'd0;
vns_slave_sel_r <= 3'd0;
vns_count <= 20'd1000000;
vns_state <= 1'd0;
end
end
Cfu Cfu(
.clk(sys_clk),
.cmd_payload_function_id(soc_vexriscv_cfu_bus_cmd_payload_function_id),
.cmd_payload_inputs_0(soc_vexriscv_cfu_bus_cmd_payload_inputs_0),
.cmd_payload_inputs_1(soc_vexriscv_cfu_bus_cmd_payload_inputs_1),
.cmd_valid(soc_vexriscv_cfu_bus_cmd_valid),
.reset(sys_rst),
.rsp_ready(soc_vexriscv_cfu_bus_rsp_ready),
.cmd_ready(soc_vexriscv_cfu_bus_cmd_ready),
.rsp_payload_outputs_0(soc_vexriscv_cfu_bus_rsp_payload_outputs_0),
.rsp_valid(soc_vexriscv_cfu_bus_rsp_valid)
);
SP512K #(
.ECC_BYTE_SEL("BYTE_EN")
) SP512K (
.AD(soc_bus_adr[13:0]),
.BYTEEN_N((~soc_bus_sel[3:0])),
.CE(1'd1),
.CEOUT(1'd0),
.CLK(sys_clk),
.CS(soc_cs0),
.DI(soc_datain0),
.RSTOUT(1'd0),
.WE(soc_wren0),
.DO(soc_dataout0)
);
SP512K #(
.ECC_BYTE_SEL("BYTE_EN")
) SP512K_1 (
.AD(soc_bus_adr[13:0]),
.BYTEEN_N((~soc_bus_sel[3:0])),
.CE(1'd1),
.CEOUT(1'd0),
.CLK(sys_clk),
.CS(soc_cs1),
.DI(soc_datain1),
.RSTOUT(1'd0),
.WE(soc_wren1),
.DO(soc_dataout1)
);
SP512K #(
.ECC_BYTE_SEL("BYTE_EN")
) SP512K_2 (
.AD(soc_bus_adr[13:0]),
.BYTEEN_N((~soc_bus_sel[3:0])),
.CE(1'd1),
.CEOUT(1'd0),
.CLK(sys_clk),
.CS(soc_cs2),
.DI(soc_datain2),
.RSTOUT(1'd0),
.WE(soc_wren2),
.DO(soc_dataout2)
);
SP512K #(
.ECC_BYTE_SEL("BYTE_EN")
) SP512K_3 (
.AD(soc_bus_adr[13:0]),
.BYTEEN_N((~soc_bus_sel[3:0])),
.CE(1'd1),
.CEOUT(1'd0),
.CLK(sys_clk),
.CS(soc_cs3),
.DI(soc_datain3),
.RSTOUT(1'd0),
.WE(soc_wren3),
.DO(soc_dataout3)
);
SP512K #(
.ECC_BYTE_SEL("BYTE_EN")
) SP512K_4 (
.AD(soc_bus_adr[13:0]),
.BYTEEN_N((~soc_bus_sel[3:0])),
.CE(1'd1),
.CEOUT(1'd0),
.CLK(sys_clk),
.CS(soc_cs4),
.DI(soc_datain4),
.RSTOUT(1'd0),
.WE(soc_wren4),
.DO(soc_dataout4)
);
OSCA #(
.HF_CLK_DIV("6"),
.HF_OSC_EN("ENABLED")
) OSCA (
.HFOUTEN(1'd1),
.HFCLKOUT(soc_clkout)
);
VexRiscv VexRiscv(
.CfuPlugin_bus_cmd_ready(soc_vexriscv_cfu_bus_cmd_ready),
.CfuPlugin_bus_rsp_payload_outputs_0(soc_vexriscv_cfu_bus_rsp_payload_outputs_0),
.CfuPlugin_bus_rsp_valid(soc_vexriscv_cfu_bus_rsp_valid),
.clk(sys_clk),
.dBusWishbone_ACK(soc_dbus_ack),
.dBusWishbone_DAT_MISO(soc_dbus_dat_r),
.dBusWishbone_ERR(soc_dbus_err),
// .externalInterruptArray(soc_interrupt),
.externalResetVector(soc_vexriscv),
.iBusWishbone_ACK(soc_ibus_ack),
.iBusWishbone_DAT_MISO(soc_ibus_dat_r),
.iBusWishbone_ERR(soc_ibus_err),
.reset((sys_rst | soc_reset)),
.softwareInterrupt(1'd0),
.timerInterrupt(1'd0),
.CfuPlugin_bus_cmd_payload_function_id(soc_vexriscv_cfu_bus_cmd_payload_function_id),
.CfuPlugin_bus_cmd_payload_inputs_0(soc_vexriscv_cfu_bus_cmd_payload_inputs_0),
.CfuPlugin_bus_cmd_payload_inputs_1(soc_vexriscv_cfu_bus_cmd_payload_inputs_1),
.CfuPlugin_bus_cmd_valid(soc_vexriscv_cfu_bus_cmd_valid),
.CfuPlugin_bus_rsp_ready(soc_vexriscv_cfu_bus_rsp_ready),
.dBusWishbone_ADR(soc_dbus_adr),
.dBusWishbone_BTE(soc_dbus_bte),
.dBusWishbone_CTI(soc_dbus_cti),
.dBusWishbone_CYC(soc_dbus_cyc),
.dBusWishbone_DAT_MOSI(soc_dbus_dat_w),
.dBusWishbone_SEL(soc_dbus_sel),
.dBusWishbone_STB(soc_dbus_stb),
.dBusWishbone_WE(soc_dbus_we),
.iBusWishbone_ADR(soc_ibus_adr),
.iBusWishbone_BTE(soc_ibus_bte),
.iBusWishbone_CTI(soc_ibus_cti),
.iBusWishbone_CYC(soc_ibus_cyc),
.iBusWishbone_DAT_MOSI(soc_ibus_dat_w),
.iBusWishbone_SEL(soc_ibus_sel),
.iBusWishbone_STB(soc_ibus_stb),
.iBusWishbone_WE(soc_ibus_we)
);
FD1P3BX FD1P3BX(
.CK(sys_clk),
.D(1'd0),
.PD((soc_por_counter != 1'd0)),
.SP(1'd1),
.Q(vns_rst1)
);
FD1P3BX FD1P3BX_1(
.CK(sys_clk),
.D(vns_rst1),
.PD((soc_por_counter != 1'd0)),
.SP(1'd1),
.Q(sys_rst)
);
ODDRX1 ODDRX1(
.D0(soc_litespiddrphycore_en),
.D1(1'd0),
.SCLK(sys_clk),
.Q(spiflash4x_clk)
);
assign spiflash4x_dq[0] = vns_latticenxddrtristateimpl0_oe ? vns_latticenxddrtristateimpl0__o : 1'bz;
assign vns_latticenxddrtristateimpl0__i = spiflash4x_dq[0];
assign spiflash4x_dq[1] = vns_latticenxddrtristateimpl1_oe ? vns_latticenxddrtristateimpl1__o : 1'bz;
assign vns_latticenxddrtristateimpl1__i = spiflash4x_dq[1];
assign spiflash4x_dq[2] = vns_latticenxddrtristateimpl2_oe ? vns_latticenxddrtristateimpl2__o : 1'bz;
assign vns_latticenxddrtristateimpl2__i = spiflash4x_dq[2];
assign spiflash4x_dq[3] = vns_latticenxddrtristateimpl3_oe ? vns_latticenxddrtristateimpl3__o : 1'bz;
assign vns_latticenxddrtristateimpl3__i = spiflash4x_dq[3];
ODDRX1 ODDRX1_1(
.D0(soc_litespiddrphycore0[0]),
.D1(soc_litespiddrphycore1[0]),
.SCLK(sys_clk),
.Q(vns_latticenxddrtristateimpl0__o)
);
FD1P3BX FD1P3BX_2(
.CK(sys_clk),
.D((soc_litespiddrphycore4[0] | soc_litespiddrphycore5[0])),
.PD(1'd0),
.SP(1'd1),
.Q(vns_latticenxddrtristateimpl0_oe)
);
IDDRX1 IDDRX1(
.D(vns_latticenxddrtristateimpl0__i),
.SCLK(sys_clk),
.Q0(soc_litespiddrphycore2[0]),
.Q1(soc_litespiddrphycore3[0])
);
ODDRX1 ODDRX1_2(
.D0(soc_litespiddrphycore0[1]),
.D1(soc_litespiddrphycore1[1]),
.SCLK(sys_clk),
.Q(vns_latticenxddrtristateimpl1__o)
);
FD1P3BX FD1P3BX_3(
.CK(sys_clk),
.D((soc_litespiddrphycore4[1] | soc_litespiddrphycore5[1])),
.PD(1'd0),
.SP(1'd1),
.Q(vns_latticenxddrtristateimpl1_oe)
);
IDDRX1 IDDRX1_1(
.D(vns_latticenxddrtristateimpl1__i),
.SCLK(sys_clk),
.Q0(soc_litespiddrphycore2[1]),
.Q1(soc_litespiddrphycore3[1])
);
ODDRX1 ODDRX1_3(
.D0(soc_litespiddrphycore0[2]),
.D1(soc_litespiddrphycore1[2]),
.SCLK(sys_clk),
.Q(vns_latticenxddrtristateimpl2__o)
);
FD1P3BX FD1P3BX_4(
.CK(sys_clk),
.D((soc_litespiddrphycore4[2] | soc_litespiddrphycore5[2])),
.PD(1'd0),
.SP(1'd1),
.Q(vns_latticenxddrtristateimpl2_oe)
);
IDDRX1 IDDRX1_2(
.D(vns_latticenxddrtristateimpl2__i),
.SCLK(sys_clk),
.Q0(soc_litespiddrphycore2[2]),
.Q1(soc_litespiddrphycore3[2])
);
ODDRX1 ODDRX1_4(
.D0(soc_litespiddrphycore0[3]),
.D1(soc_litespiddrphycore1[3]),
.SCLK(sys_clk),
.Q(vns_latticenxddrtristateimpl3__o)
);
FD1P3BX FD1P3BX_5(
.CK(sys_clk),
.D((soc_litespiddrphycore4[3] | soc_litespiddrphycore5[3])),
.PD(1'd0),
.SP(1'd1),
.Q(vns_latticenxddrtristateimpl3_oe)
);
IDDRX1 IDDRX1_3(
.D(vns_latticenxddrtristateimpl3__i),
.SCLK(sys_clk),
.Q0(soc_litespiddrphycore2[3]),
.Q1(soc_litespiddrphycore3[3])
);
endmodule
|
//==================================================================================================
// Filename : Testbench_FPUv1_Interface.v
// Created On : 2016-10-31 01:04:16
// Last Modified : 2016-10-31 01:04:28
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
module Testbench_FPU_Mark1();
parameter PERIOD = 10;
`ifdef SINGLE
parameter W = 32;
parameter EW = 8;
parameter SW = 23;
parameter SWR = 26;
parameter EWR = 5;//
`endif
`ifdef DOUBLE
parameter W = 64;
parameter EW = 11;
parameter SW = 52;
parameter SWR = 55;
parameter EWR = 6;
`endif
reg clk;
//INPUT signals
reg rst;
reg begin_operation;
reg ack_operation;
reg [2:0] operation;
//Oper_Start_in signals
reg [W-1:0] Data_1;
reg [W-1:0] Data_2;
reg [1:0] region_flag;
//reg add_subt;
//Round signals signals
reg [1:0] r_mode;
//OUTPUT SIGNALS
wire overflow_flag;
wire underflow_flag;
wire operation_ready;
wire NaN_flag;
wire [W-1:0] op_result;
// LOS CODIGOS PARA LAS OPERACIONES
localparam [2:0] FPADD = 3'b000,
FPSUB = 3'b001,
FPCOS = 3'b010,
FPSEN = 3'b011,
FPMULT = 3'b100;
// LAS REGIONES DEL ANGULO
localparam [1:0] IoIV1 = 2'b00,
II = 2'b01,
III = 2'b10,
IoIV2 = 2'b11;
localparam [1:0] ROUNDING_MODE_TRUNCT = 2'b00,
ROUNDING_MODE_NEG_INF = 2'b01,
ROUNDING_MODE_POS_INF = 2'b10;
`ifdef SINGLE
FPU_Interface_W32_EW8_SW23_SWR26_EWR5 FPU_Interface (
.clk (clk),
.rst (rst),
.begin_operation (begin_operation),
.ack_operation (ack_operation),
.operation (operation),
.region_flag (region_flag),
.Data_1 (Data_1),
.Data_2 (Data_2),
.r_mode (r_mode),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.NaN_flag (NaN_flag),
.operation_ready (operation_ready),
.op_result (op_result)
);
`endif
`ifdef DOUBLE
FPU_Interface_W64_EW11_SW52_SWR55_EWR6 FPU_Interface (
.clk (clk),
.rst (rst),
.begin_operation (begin_operation),
.ack_operation (ack_operation),
.operation (operation),
.region_flag (region_flag),
.Data_1 (Data_1),
.Data_2 (Data_2),
.r_mode (r_mode),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.NaN_flag (NaN_flag),
.operation_ready (operation_ready),
.op_result (op_result)
);
`endif
reg [W-1:0] Array_IN_1 [0:((2**PERIOD)-1)];
reg [W-1:0] Array_IN_2 [0:((2**PERIOD)-1)];
integer contador;
integer FileSaveData;
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
begin_operation = 0;
ack_operation = 0;
Data_1 = 0;
Data_2 = 0;
`ifdef SINGLE
$display("------------------------SUMA--------------------------");
$display("------------------------ --------------------------");
$display("------------------------SUMA--------------------------");
operation = FPADD;
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("ADD/SINGLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
$readmemh("ADD/SINGLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("ADD/SINGLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("ADD/SINGLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
$readmemh("ADD/SINGLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("ADD/SINGLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("ADD/SINGLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
$readmemh("ADD/SINGLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("ADD/SINGLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
$display("------------------------RSTA--------------------------");
$display("------------------------ --------------------------");
$display("------------------------RSTA--------------------------");
operation = FPSUB;
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("SUB/SINGLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
$readmemh("SUB/SINGLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("SUB/SINGLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("SUB/SINGLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
$readmemh("SUB/SINGLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("SUB/SINGLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("SUB/SINGLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
$readmemh("SUB/SINGLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("SUB/SINGLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
$display("------------------------MULT--------------------------");
$display("------------------------ --------------------------");
$display("------------------------MULT--------------------------");
operation = FPMULT;
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("MULT/SINGLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
$readmemh("MULT/SINGLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("MULT/SINGLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("MULT/SINGLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
$readmemh("MULT/SINGLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("MULT/SINGLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("MULT/SINGLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
$readmemh("MULT/SINGLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("MULT/SINGLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
$display("---------------------REGION I or IV--------------------------");
$display("------------------------ --------------------------");
$display("---------------------REGION I or IV-------------------");
region_flag = IoIV1;
$display("------------------------SENO--------------------------");
$display("------------------------ --------------------------");
$display("------------------------SENO--------------------------");
operation = FPSEN;
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("SIN/SINGLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
$readmemh("SIN/SINGLE/input_angles_hex.txt", Array_IN_1);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("SIN/SINGLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
$readmemh("SIN/SINGLE/input_angles_hex.txt", Array_IN_1);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("SIN/SINGLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
$readmemh("SIN/SINGLE/input_angles_hex.txt", Array_IN_1);
run_Arch2(FileSaveData,2**PERIOD);
$display("------------------------COS--------------------------");
$display("------------------------ --------------------------");
$display("------------------------COS--------------------------");
operation = FPCOS;
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("COS/SINGLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
$readmemh("COS/SINGLE/input_angles_hex.txt", Array_IN_1);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("COS/SINGLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
$readmemh("COS/SINGLE/input_angles_hex.txt", Array_IN_1);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("COS/SINGLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
$readmemh("COS/SINGLE/input_angles_hex.txt", Array_IN_1);
run_Arch2(FileSaveData,2**PERIOD);
`endif
`ifdef DOUBLE
$display("------------------------SUMA--------------------------");
$display("------------------------ --------------------------");
$display("------------------------SUMA--------------------------");
operation = FPADD;
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("ADD/DOUBLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
$readmemh("ADD/DOUBLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("ADD/DOUBLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("ADD/DOUBLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
$readmemh("ADD/DOUBLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("ADD/DOUBLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("ADD/DOUBLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
$readmemh("ADD/DOUBLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("ADD/DOUBLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
$display("------------------------RSTA--------------------------");
$display("------------------------ --------------------------");
$display("------------------------RSTA--------------------------");
operation = FPSUB;
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("SUB/DOUBLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
$readmemh("SUB/DOUBLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("SUB/DOUBLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("SUB/DOUBLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
$readmemh("SUB/DOUBLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("SUB/DOUBLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("SUB/DOUBLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
$readmemh("SUB/DOUBLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("SUB/DOUBLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
$display("------------------------MULT--------------------------");
$display("------------------------ --------------------------");
$display("------------------------MULT--------------------------");
operation = FPMULT;
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("MULT/DOUBLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
$readmemh("MULT/DOUBLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("MULT/DOUBLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("MULT/DOUBLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
$readmemh("MULT/DOUBLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("MULT/DOUBLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("MULT/DOUBLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
$readmemh("MULT/DOUBLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("MULT/DOUBLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
$display("---------------------REGION I or IV--------------------------");
$display("------------------------ --------------------------");
$display("---------------------REGION I or IV-------------------");
region_flag = IoIV1;
$display("------------------------SENO--------------------------");
$display("------------------------ --------------------------");
$display("------------------------SENO--------------------------");
operation = FPSEN;
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("SIN/DOUBLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
$readmemh("SIN/DOUBLE/input_angles_hex.txt", Array_IN_1);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("SIN/DOUBLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
$readmemh("SIN/DOUBLE/input_angles_hex.txt", Array_IN_1);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("SIN/DOUBLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
$readmemh("SIN/DOUBLE/input_angles_hex.txt", Array_IN_1);
run_Arch2(FileSaveData,2**PERIOD);
$display("------------------------COS--------------------------");
$display("------------------------ --------------------------");
$display("------------------------COS--------------------------");
operation = FPCOS;
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("COS/DOUBLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
$readmemh("COS/DOUBLE/input_angles_hex.txt", Array_IN_1);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("COS/DOUBLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
$readmemh("COS/DOUBLE/input_angles_hex.txt", Array_IN_1);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("COS/DOUBLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
$readmemh("COS/DOUBLE/input_angles_hex.txt", Array_IN_1);
run_Arch2(FileSaveData,2**PERIOD);
`endif
#100 rst = 0;
$finish;
//Add stimulus here
end
//******************************* Se ejecuta el CLK ************************
initial forever #5 clk = ~clk;
task run_Arch2;
input integer FDataO;
input integer Vector_size;
begin
rst = 0;
#15 rst = 1;
#15 rst = 0;
begin_operation = 0;
ack_operation = 0;
contador = 0;
repeat(Vector_size) @(negedge clk) begin
//input the new values inside the operator
Data_1 = Array_IN_1[contador];
Data_2 = Array_IN_2[contador];
#(PERIOD/4) begin_operation = 1;
//Wait for the operation operation_ready
@(posedge operation_ready) begin
#(PERIOD+2);
ack_operation = 1;
#4;
$fwrite(FDataO,"%h\n",op_result);
end
@(negedge clk) begin
ack_operation = 0;
end
contador = contador + 1;
end
$fclose(FDataO);
end
endtask
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 9
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module dma_loopback_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_9_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(12'H000),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
module wr_memory ( wr_data, wr_clk, wr_en, wr_addr,
remapping_memory,
full,
reset );
/* Parameters */
parameter WR_DATA_WIDTH = 1;
parameter WR_ADDR_WIDTH = 3;
parameter MEM_DEPTH = 8;
/* Ports */
input wire [WR_DATA_WIDTH - 1 : 0] wr_data;
input wire [WR_ADDR_WIDTH - 1 : 0] wr_addr;
input wire wr_clk, wr_en;
input wire full;
output reg [MEM_DEPTH - 1 : 0] remapping_memory;
input wire reset;
/* Variables */
reg [WR_DATA_WIDTH - 1 : 0] memory [MEM_DEPTH - 1 : 0];
integer i;
/* Behavioral */
always @(posedge wr_clk or posedge reset) begin
if(reset)
for(i = 0; i < MEM_DEPTH; i = i + 1)
memory[i] <= 0;
else
if(wr_en)
memory[wr_addr] <= wr_data;
end
always @(posedge full or posedge reset) begin
if(reset)
remapping_memory <= 0;
else
for(i = 0; i < MEM_DEPTH; i = i + 1)
remapping_memory[i] <= memory[i];
end
endmodule |
/**************************************
* Module: simul_axi_fifo
* Date:2014-03-23
* Author: Andrey Filippov
*
* Description:
***************************************/
`timescale 1ns/1ps
module simul_axi_fifo
#(
parameter integer WIDTH= 64, // total number of output bits
parameter integer LATENCY=0, // minimal delay between inout and output ( 0 - next cycle)
parameter integer DEPTH=8, // maximal number of commands in FIFO
// parameter OUT_DELAY = 3.5,
parameter integer FIFO_DEPTH=LATENCY+DEPTH+1
// parameter integer DATA_2DEPTH=(1<<DATA_DEPTH)-1
)(
input clk,
input reset,
input [WIDTH-1:0] data_in,
input load,
output input_ready,
output [WIDTH-1:0] data_out,
output valid,
input ready);
reg [WIDTH-1:0] fifo [0:FIFO_DEPTH-1];
integer in_address;
integer out_address;
integer in_count;
integer out_count;
reg [LATENCY:0] latency_delay_r;
wire [LATENCY+1:0] latency_delay={latency_delay_r,load};
wire out_inc=latency_delay[LATENCY];
assign data_out= fifo[out_address];
assign valid= out_count!=0;
assign input_ready= in_count<DEPTH;
// assign out_inc={
always @ (posedge clk or posedge reset) begin
if (reset) latency_delay_r <= 0;
else latency_delay_r <= latency_delay[LATENCY:0];
if (reset) in_address <= 0;
else if (load) in_address <= (in_address==(FIFO_DEPTH-1))?0:in_address+1;
if (reset) out_address <= 0;
else if (valid && ready) out_address <= (out_address==(FIFO_DEPTH-1))?0:out_address+1;
if (reset) in_count <= 0;
else if (!(valid && ready) && load) in_count <= in_count+1;
else if (valid && ready && !load) in_count <= in_count-1;
if (reset) out_count <= 0;
else if (!(valid && ready) && out_inc) out_count <= out_count+1;
else if (valid && ready && !out_inc) out_count <= out_count-1;
end
always @ (posedge clk) begin
if (load) fifo[in_address] <= data_in;
end
endmodule |
//
// This data structure takes in a multi-word data and serializes
// it to a single word output.
//
// The input channel handshake is a ready-and-valid interface
// and the output channel handshake is a valid-then-yumi
// interface. This makes both channels "helpful" style
// handshakes.
//
// There are two options for this module:
// 1) zero bubbles, no dependence, 2 element buffer for last data word
// 2) one bubble, no dependence, 1 element buffer for last data word
// By default option 1 is used, option 2 can be enabled by setting
// use_minimal_buffering_p = 1
//
`include "bsg_defines.v"
module bsg_parallel_in_serial_out
#(parameter `BSG_INV_PARAM(width_p)
,parameter `BSG_INV_PARAM(els_p)
,parameter hi_to_lo_p = 0 // sending from high bits to low bits
,parameter use_minimal_buffering_p = 0 // using single element buffer
)
(input clk_i
,input reset_i
// Data Input Channel (Ready and Valid)
,input valid_i
,input [els_p-1:0][width_p-1:0] data_i
,output ready_and_o
// Data Output Channel (Valid then Yumi)
,output valid_o
,output [width_p-1:0] data_o
,input yumi_i
);
// Reverse the input data array if send from HI to LO
logic [els_p-1:0][width_p-1:0] data_li;
if (hi_to_lo_p == 0)
begin: lo2hi
assign data_li = data_i;
end
else
begin: hi2lo
bsg_array_reverse
#(.width_p(width_p)
,.els_p(els_p)
) bar
(.i(data_i)
,.o(data_li)
);
end
/**
* Buffering the LAST input data word
*
* By default a two-element fifo is used to eleminate bubbling.
* One-element fifo is optional for minimal resource utilization.
*/
logic fifo0_ready_lo, fifo_v_li;
logic fifo_v_lo, fifo0_yumi_li;
logic [els_p-1:0][width_p-1:0] fifo_data_lo;
if (use_minimal_buffering_p == 0)
begin: two_fifo
bsg_two_fifo
#(.width_p(width_p)
) fifo0
(.clk_i (clk_i)
,.reset_i(reset_i)
,.ready_o(fifo0_ready_lo)
,.data_i (data_li[els_p-1])
,.v_i (fifo_v_li)
,.v_o (fifo_v_lo)
,.data_o (fifo_data_lo[els_p-1])
,.yumi_i (fifo0_yumi_li)
);
end
else
begin: one_fifo
bsg_one_fifo
#(.width_p(width_p)
) fifo0
(.clk_i (clk_i)
,.reset_i(reset_i)
,.ready_o(fifo0_ready_lo)
,.data_i (data_li[els_p-1])
,.v_i (fifo_v_li)
,.v_o (fifo_v_lo)
,.data_o (fifo_data_lo[els_p-1])
,.yumi_i (fifo0_yumi_li)
);
end
if (els_p == 1)
begin: bypass
// When conversion ratio is 1, only one data word exists
// Connect fifo0 signals directly to input/output ports
assign fifo_v_li = valid_i;
assign ready_and_o = fifo0_ready_lo;
assign valid_o = fifo_v_lo;
assign data_o = fifo_data_lo;
assign fifo0_yumi_li = yumi_i;
end
else
begin: piso
/**
* Buffering the rest of the data words
*
* Single element buffering is sufficient for bubble-free transmission.
*
* Output data of fifo1 is guaranteed to be valid if output data of fifo0 is
* valid and shift_ctr_r != (els_p-1).
* Therefore v_o signal of fifo1 is unused to minimize hardware utilization.
*/
logic fifo1_ready_lo, fifo1_yumi_li;
bsg_one_fifo
#(.width_p((els_p-1)*width_p)
) fifo1
(.clk_i (clk_i)
,.reset_i(reset_i)
,.ready_o(fifo1_ready_lo)
,.data_i (data_li[els_p-2:0])
,.v_i (fifo_v_li)
,.v_o ()
,.data_o (fifo_data_lo[els_p-2:0])
,.yumi_i (fifo1_yumi_li)
);
/**
* Enqueue data into fifo iff both fifos are ready
*/
assign ready_and_o = fifo0_ready_lo & fifo1_ready_lo;
assign fifo_v_li = valid_i & ready_and_o;
/**
* Data fifo yumi signals
*
* Dequeue from fifo1 when second-last data word has been sent out, freeing
* space for the following data words to avoid bubbling.
* Dequeue from fifo0 when last data word has been sent out, indicating
* done of transmission.
*/
localparam clog2els_lp = $clog2(els_p);
logic [clog2els_lp-1:0] shift_ctr_r;
assign fifo0_yumi_li = (shift_ctr_r == clog2els_lp ' (els_p-1)) && yumi_i;
assign fifo1_yumi_li = (shift_ctr_r == clog2els_lp ' (els_p-2)) && yumi_i;
/**
* Shift Counter Logic
*
* The shift_ctr_r register stores the word we are transmitting. Whenever
* we reset or done transmitting data, we clear the shift_ctr_r register.
* When data fifo has valid data output, we will increment the register if
* the outside world is going to accept our data (ie. yumi_i).
*
* Possible optimization
*
* Can instead use bsg_counter_clear_up_one_hot and one-hot mux down below
* for faster hardware by getting rid of a comparator and decoder on the paths.
* The downside is that there are more registers for counter (N vs lgN).
* Can do some PPA analysis for the tradeoff.
*/
bsg_counter_clear_up
#(.max_val_p (els_p-1)
,.init_val_p('0)
) shift_ctr
(.clk_i (clk_i)
,.reset_i (reset_i)
,.clear_i (fifo0_yumi_li)
,.up_i (~fifo0_yumi_li & yumi_i)
,.count_o (shift_ctr_r)
);
/**
* Valid Output Signal
*
* The valid_o signal means the output data is valid. For this
* module, the output is valid iff data fifo has valid output data.
*/
assign valid_o = fifo_v_lo;
/**
* Data Output Signal
*
* Assign data_o to the word that we have shifted to.
*/
bsg_mux
#(.width_p(width_p)
,.els_p (els_p)
) data_o_mux
(.data_i (fifo_data_lo)
,.sel_i (shift_ctr_r)
,.data_o (data_o)
);
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_parallel_in_serial_out)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPMET1_BEHAVIORAL_V
`define SKY130_FD_SC_HS__TAPMET1_BEHAVIORAL_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__tapmet1 (
VPWR,
VGND
);
// Module ports
input VPWR;
input VGND;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPMET1_BEHAVIORAL_V |
//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
//Date : Tue Feb 02 21:37:26 2016
//Host : running 64-bit Service Pack 1 (build 7601)
//Command : generate_target zc702.bd
//Design : zc702
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module m00_couplers_imp_1IKQD79
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arprot,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awprot,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [12:0]M_AXI_araddr;
input M_AXI_arready;
output M_AXI_arvalid;
output [12:0]M_AXI_awaddr;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [2:0]S_AXI_arprot;
output S_AXI_arready;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [2:0]S_AXI_awprot;
output S_AXI_awready;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire M_ACLK_1;
wire [0:0]M_ARESETN_1;
wire [31:0]m00_couplers_to_m00_regslice_ARADDR;
wire [2:0]m00_couplers_to_m00_regslice_ARPROT;
wire m00_couplers_to_m00_regslice_ARREADY;
wire m00_couplers_to_m00_regslice_ARVALID;
wire [31:0]m00_couplers_to_m00_regslice_AWADDR;
wire [2:0]m00_couplers_to_m00_regslice_AWPROT;
wire m00_couplers_to_m00_regslice_AWREADY;
wire m00_couplers_to_m00_regslice_AWVALID;
wire m00_couplers_to_m00_regslice_BREADY;
wire [1:0]m00_couplers_to_m00_regslice_BRESP;
wire m00_couplers_to_m00_regslice_BVALID;
wire [31:0]m00_couplers_to_m00_regslice_RDATA;
wire m00_couplers_to_m00_regslice_RREADY;
wire [1:0]m00_couplers_to_m00_regslice_RRESP;
wire m00_couplers_to_m00_regslice_RVALID;
wire [31:0]m00_couplers_to_m00_regslice_WDATA;
wire m00_couplers_to_m00_regslice_WREADY;
wire [3:0]m00_couplers_to_m00_regslice_WSTRB;
wire m00_couplers_to_m00_regslice_WVALID;
wire [12:0]m00_regslice_to_m00_couplers_ARADDR;
wire m00_regslice_to_m00_couplers_ARREADY;
wire m00_regslice_to_m00_couplers_ARVALID;
wire [12:0]m00_regslice_to_m00_couplers_AWADDR;
wire m00_regslice_to_m00_couplers_AWREADY;
wire m00_regslice_to_m00_couplers_AWVALID;
wire m00_regslice_to_m00_couplers_BREADY;
wire [1:0]m00_regslice_to_m00_couplers_BRESP;
wire m00_regslice_to_m00_couplers_BVALID;
wire [31:0]m00_regslice_to_m00_couplers_RDATA;
wire m00_regslice_to_m00_couplers_RREADY;
wire [1:0]m00_regslice_to_m00_couplers_RRESP;
wire m00_regslice_to_m00_couplers_RVALID;
wire [31:0]m00_regslice_to_m00_couplers_WDATA;
wire m00_regslice_to_m00_couplers_WREADY;
wire [3:0]m00_regslice_to_m00_couplers_WSTRB;
wire m00_regslice_to_m00_couplers_WVALID;
assign M_ACLK_1 = M_ACLK;
assign M_ARESETN_1 = M_ARESETN[0];
assign M_AXI_araddr[12:0] = m00_regslice_to_m00_couplers_ARADDR;
assign M_AXI_arvalid = m00_regslice_to_m00_couplers_ARVALID;
assign M_AXI_awaddr[12:0] = m00_regslice_to_m00_couplers_AWADDR;
assign M_AXI_awvalid = m00_regslice_to_m00_couplers_AWVALID;
assign M_AXI_bready = m00_regslice_to_m00_couplers_BREADY;
assign M_AXI_rready = m00_regslice_to_m00_couplers_RREADY;
assign M_AXI_wdata[31:0] = m00_regslice_to_m00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = m00_regslice_to_m00_couplers_WSTRB;
assign M_AXI_wvalid = m00_regslice_to_m00_couplers_WVALID;
assign S_AXI_arready = m00_couplers_to_m00_regslice_ARREADY;
assign S_AXI_awready = m00_couplers_to_m00_regslice_AWREADY;
assign S_AXI_bresp[1:0] = m00_couplers_to_m00_regslice_BRESP;
assign S_AXI_bvalid = m00_couplers_to_m00_regslice_BVALID;
assign S_AXI_rdata[31:0] = m00_couplers_to_m00_regslice_RDATA;
assign S_AXI_rresp[1:0] = m00_couplers_to_m00_regslice_RRESP;
assign S_AXI_rvalid = m00_couplers_to_m00_regslice_RVALID;
assign S_AXI_wready = m00_couplers_to_m00_regslice_WREADY;
assign m00_couplers_to_m00_regslice_ARADDR = S_AXI_araddr[31:0];
assign m00_couplers_to_m00_regslice_ARPROT = S_AXI_arprot[2:0];
assign m00_couplers_to_m00_regslice_ARVALID = S_AXI_arvalid;
assign m00_couplers_to_m00_regslice_AWADDR = S_AXI_awaddr[31:0];
assign m00_couplers_to_m00_regslice_AWPROT = S_AXI_awprot[2:0];
assign m00_couplers_to_m00_regslice_AWVALID = S_AXI_awvalid;
assign m00_couplers_to_m00_regslice_BREADY = S_AXI_bready;
assign m00_couplers_to_m00_regslice_RREADY = S_AXI_rready;
assign m00_couplers_to_m00_regslice_WDATA = S_AXI_wdata[31:0];
assign m00_couplers_to_m00_regslice_WSTRB = S_AXI_wstrb[3:0];
assign m00_couplers_to_m00_regslice_WVALID = S_AXI_wvalid;
assign m00_regslice_to_m00_couplers_ARREADY = M_AXI_arready;
assign m00_regslice_to_m00_couplers_AWREADY = M_AXI_awready;
assign m00_regslice_to_m00_couplers_BRESP = M_AXI_bresp[1:0];
assign m00_regslice_to_m00_couplers_BVALID = M_AXI_bvalid;
assign m00_regslice_to_m00_couplers_RDATA = M_AXI_rdata[31:0];
assign m00_regslice_to_m00_couplers_RRESP = M_AXI_rresp[1:0];
assign m00_regslice_to_m00_couplers_RVALID = M_AXI_rvalid;
assign m00_regslice_to_m00_couplers_WREADY = M_AXI_wready;
zc702_m00_regslice_0 m00_regslice
(.aclk(M_ACLK_1),
.aresetn(M_ARESETN_1),
.m_axi_araddr(m00_regslice_to_m00_couplers_ARADDR),
.m_axi_arready(m00_regslice_to_m00_couplers_ARREADY),
.m_axi_arvalid(m00_regslice_to_m00_couplers_ARVALID),
.m_axi_awaddr(m00_regslice_to_m00_couplers_AWADDR),
.m_axi_awready(m00_regslice_to_m00_couplers_AWREADY),
.m_axi_awvalid(m00_regslice_to_m00_couplers_AWVALID),
.m_axi_bready(m00_regslice_to_m00_couplers_BREADY),
.m_axi_bresp(m00_regslice_to_m00_couplers_BRESP),
.m_axi_bvalid(m00_regslice_to_m00_couplers_BVALID),
.m_axi_rdata(m00_regslice_to_m00_couplers_RDATA),
.m_axi_rready(m00_regslice_to_m00_couplers_RREADY),
.m_axi_rresp(m00_regslice_to_m00_couplers_RRESP),
.m_axi_rvalid(m00_regslice_to_m00_couplers_RVALID),
.m_axi_wdata(m00_regslice_to_m00_couplers_WDATA),
.m_axi_wready(m00_regslice_to_m00_couplers_WREADY),
.m_axi_wstrb(m00_regslice_to_m00_couplers_WSTRB),
.m_axi_wvalid(m00_regslice_to_m00_couplers_WVALID),
.s_axi_araddr(m00_couplers_to_m00_regslice_ARADDR[12:0]),
.s_axi_arprot(m00_couplers_to_m00_regslice_ARPROT),
.s_axi_arready(m00_couplers_to_m00_regslice_ARREADY),
.s_axi_arvalid(m00_couplers_to_m00_regslice_ARVALID),
.s_axi_awaddr(m00_couplers_to_m00_regslice_AWADDR[12:0]),
.s_axi_awprot(m00_couplers_to_m00_regslice_AWPROT),
.s_axi_awready(m00_couplers_to_m00_regslice_AWREADY),
.s_axi_awvalid(m00_couplers_to_m00_regslice_AWVALID),
.s_axi_bready(m00_couplers_to_m00_regslice_BREADY),
.s_axi_bresp(m00_couplers_to_m00_regslice_BRESP),
.s_axi_bvalid(m00_couplers_to_m00_regslice_BVALID),
.s_axi_rdata(m00_couplers_to_m00_regslice_RDATA),
.s_axi_rready(m00_couplers_to_m00_regslice_RREADY),
.s_axi_rresp(m00_couplers_to_m00_regslice_RRESP),
.s_axi_rvalid(m00_couplers_to_m00_regslice_RVALID),
.s_axi_wdata(m00_couplers_to_m00_regslice_WDATA),
.s_axi_wready(m00_couplers_to_m00_regslice_WREADY),
.s_axi_wstrb(m00_couplers_to_m00_regslice_WSTRB),
.s_axi_wvalid(m00_couplers_to_m00_regslice_WVALID));
endmodule
module m00_couplers_imp_F6WOYG
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arid,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arqos,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awid,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rid,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wid,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arregion,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awregion,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [0:0]M_AXI_arid;
output [3:0]M_AXI_arlen;
output [1:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
output [3:0]M_AXI_arqos;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [0:0]M_AXI_awid;
output [3:0]M_AXI_awlen;
output [1:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
output [3:0]M_AXI_awqos;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
input [2:0]M_AXI_bid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [63:0]M_AXI_rdata;
input [2:0]M_AXI_rid;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [63:0]M_AXI_wdata;
output [0:0]M_AXI_wid;
output M_AXI_wlast;
input M_AXI_wready;
output [7:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [0:0]S_AXI_arid;
input [7:0]S_AXI_arlen;
input [0:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [3:0]S_AXI_arregion;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [0:0]S_AXI_awid;
input [7:0]S_AXI_awlen;
input [0:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [3:0]S_AXI_awregion;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [0:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [63:0]S_AXI_rdata;
output [0:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [63:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [7:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire M_ACLK_1;
wire [0:0]M_ARESETN_1;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_m00_regslice_ARADDR;
wire [1:0]auto_pc_to_m00_regslice_ARBURST;
wire [3:0]auto_pc_to_m00_regslice_ARCACHE;
wire [0:0]auto_pc_to_m00_regslice_ARID;
wire [3:0]auto_pc_to_m00_regslice_ARLEN;
wire [1:0]auto_pc_to_m00_regslice_ARLOCK;
wire [2:0]auto_pc_to_m00_regslice_ARPROT;
wire [3:0]auto_pc_to_m00_regslice_ARQOS;
wire auto_pc_to_m00_regslice_ARREADY;
wire [2:0]auto_pc_to_m00_regslice_ARSIZE;
wire auto_pc_to_m00_regslice_ARVALID;
wire [31:0]auto_pc_to_m00_regslice_AWADDR;
wire [1:0]auto_pc_to_m00_regslice_AWBURST;
wire [3:0]auto_pc_to_m00_regslice_AWCACHE;
wire [0:0]auto_pc_to_m00_regslice_AWID;
wire [3:0]auto_pc_to_m00_regslice_AWLEN;
wire [1:0]auto_pc_to_m00_regslice_AWLOCK;
wire [2:0]auto_pc_to_m00_regslice_AWPROT;
wire [3:0]auto_pc_to_m00_regslice_AWQOS;
wire auto_pc_to_m00_regslice_AWREADY;
wire [2:0]auto_pc_to_m00_regslice_AWSIZE;
wire auto_pc_to_m00_regslice_AWVALID;
wire [0:0]auto_pc_to_m00_regslice_BID;
wire auto_pc_to_m00_regslice_BREADY;
wire [1:0]auto_pc_to_m00_regslice_BRESP;
wire auto_pc_to_m00_regslice_BVALID;
wire [63:0]auto_pc_to_m00_regslice_RDATA;
wire [0:0]auto_pc_to_m00_regslice_RID;
wire auto_pc_to_m00_regslice_RLAST;
wire auto_pc_to_m00_regslice_RREADY;
wire [1:0]auto_pc_to_m00_regslice_RRESP;
wire auto_pc_to_m00_regslice_RVALID;
wire [63:0]auto_pc_to_m00_regslice_WDATA;
wire [0:0]auto_pc_to_m00_regslice_WID;
wire auto_pc_to_m00_regslice_WLAST;
wire auto_pc_to_m00_regslice_WREADY;
wire [7:0]auto_pc_to_m00_regslice_WSTRB;
wire auto_pc_to_m00_regslice_WVALID;
wire [31:0]m00_couplers_to_m00_data_fifo_ARADDR;
wire [1:0]m00_couplers_to_m00_data_fifo_ARBURST;
wire [3:0]m00_couplers_to_m00_data_fifo_ARCACHE;
wire [0:0]m00_couplers_to_m00_data_fifo_ARID;
wire [7:0]m00_couplers_to_m00_data_fifo_ARLEN;
wire [0:0]m00_couplers_to_m00_data_fifo_ARLOCK;
wire [2:0]m00_couplers_to_m00_data_fifo_ARPROT;
wire [3:0]m00_couplers_to_m00_data_fifo_ARQOS;
wire m00_couplers_to_m00_data_fifo_ARREADY;
wire [3:0]m00_couplers_to_m00_data_fifo_ARREGION;
wire [2:0]m00_couplers_to_m00_data_fifo_ARSIZE;
wire m00_couplers_to_m00_data_fifo_ARVALID;
wire [31:0]m00_couplers_to_m00_data_fifo_AWADDR;
wire [1:0]m00_couplers_to_m00_data_fifo_AWBURST;
wire [3:0]m00_couplers_to_m00_data_fifo_AWCACHE;
wire [0:0]m00_couplers_to_m00_data_fifo_AWID;
wire [7:0]m00_couplers_to_m00_data_fifo_AWLEN;
wire [0:0]m00_couplers_to_m00_data_fifo_AWLOCK;
wire [2:0]m00_couplers_to_m00_data_fifo_AWPROT;
wire [3:0]m00_couplers_to_m00_data_fifo_AWQOS;
wire m00_couplers_to_m00_data_fifo_AWREADY;
wire [3:0]m00_couplers_to_m00_data_fifo_AWREGION;
wire [2:0]m00_couplers_to_m00_data_fifo_AWSIZE;
wire m00_couplers_to_m00_data_fifo_AWVALID;
wire [0:0]m00_couplers_to_m00_data_fifo_BID;
wire m00_couplers_to_m00_data_fifo_BREADY;
wire [1:0]m00_couplers_to_m00_data_fifo_BRESP;
wire m00_couplers_to_m00_data_fifo_BVALID;
wire [63:0]m00_couplers_to_m00_data_fifo_RDATA;
wire [0:0]m00_couplers_to_m00_data_fifo_RID;
wire m00_couplers_to_m00_data_fifo_RLAST;
wire m00_couplers_to_m00_data_fifo_RREADY;
wire [1:0]m00_couplers_to_m00_data_fifo_RRESP;
wire m00_couplers_to_m00_data_fifo_RVALID;
wire [63:0]m00_couplers_to_m00_data_fifo_WDATA;
wire m00_couplers_to_m00_data_fifo_WLAST;
wire m00_couplers_to_m00_data_fifo_WREADY;
wire [7:0]m00_couplers_to_m00_data_fifo_WSTRB;
wire m00_couplers_to_m00_data_fifo_WVALID;
wire [31:0]m00_data_fifo_to_auto_pc_ARADDR;
wire [1:0]m00_data_fifo_to_auto_pc_ARBURST;
wire [3:0]m00_data_fifo_to_auto_pc_ARCACHE;
wire [0:0]m00_data_fifo_to_auto_pc_ARID;
wire [7:0]m00_data_fifo_to_auto_pc_ARLEN;
wire [0:0]m00_data_fifo_to_auto_pc_ARLOCK;
wire [2:0]m00_data_fifo_to_auto_pc_ARPROT;
wire [3:0]m00_data_fifo_to_auto_pc_ARQOS;
wire m00_data_fifo_to_auto_pc_ARREADY;
wire [3:0]m00_data_fifo_to_auto_pc_ARREGION;
wire [2:0]m00_data_fifo_to_auto_pc_ARSIZE;
wire m00_data_fifo_to_auto_pc_ARVALID;
wire [31:0]m00_data_fifo_to_auto_pc_AWADDR;
wire [1:0]m00_data_fifo_to_auto_pc_AWBURST;
wire [3:0]m00_data_fifo_to_auto_pc_AWCACHE;
wire [0:0]m00_data_fifo_to_auto_pc_AWID;
wire [7:0]m00_data_fifo_to_auto_pc_AWLEN;
wire [0:0]m00_data_fifo_to_auto_pc_AWLOCK;
wire [2:0]m00_data_fifo_to_auto_pc_AWPROT;
wire [3:0]m00_data_fifo_to_auto_pc_AWQOS;
wire m00_data_fifo_to_auto_pc_AWREADY;
wire [3:0]m00_data_fifo_to_auto_pc_AWREGION;
wire [2:0]m00_data_fifo_to_auto_pc_AWSIZE;
wire m00_data_fifo_to_auto_pc_AWVALID;
wire [0:0]m00_data_fifo_to_auto_pc_BID;
wire m00_data_fifo_to_auto_pc_BREADY;
wire [1:0]m00_data_fifo_to_auto_pc_BRESP;
wire m00_data_fifo_to_auto_pc_BVALID;
wire [63:0]m00_data_fifo_to_auto_pc_RDATA;
wire [0:0]m00_data_fifo_to_auto_pc_RID;
wire m00_data_fifo_to_auto_pc_RLAST;
wire m00_data_fifo_to_auto_pc_RREADY;
wire [1:0]m00_data_fifo_to_auto_pc_RRESP;
wire m00_data_fifo_to_auto_pc_RVALID;
wire [63:0]m00_data_fifo_to_auto_pc_WDATA;
wire m00_data_fifo_to_auto_pc_WLAST;
wire m00_data_fifo_to_auto_pc_WREADY;
wire [7:0]m00_data_fifo_to_auto_pc_WSTRB;
wire m00_data_fifo_to_auto_pc_WVALID;
wire [31:0]m00_regslice_to_m00_couplers_ARADDR;
wire [1:0]m00_regslice_to_m00_couplers_ARBURST;
wire [3:0]m00_regslice_to_m00_couplers_ARCACHE;
wire [0:0]m00_regslice_to_m00_couplers_ARID;
wire [3:0]m00_regslice_to_m00_couplers_ARLEN;
wire [1:0]m00_regslice_to_m00_couplers_ARLOCK;
wire [2:0]m00_regslice_to_m00_couplers_ARPROT;
wire [3:0]m00_regslice_to_m00_couplers_ARQOS;
wire m00_regslice_to_m00_couplers_ARREADY;
wire [2:0]m00_regslice_to_m00_couplers_ARSIZE;
wire m00_regslice_to_m00_couplers_ARVALID;
wire [31:0]m00_regslice_to_m00_couplers_AWADDR;
wire [1:0]m00_regslice_to_m00_couplers_AWBURST;
wire [3:0]m00_regslice_to_m00_couplers_AWCACHE;
wire [0:0]m00_regslice_to_m00_couplers_AWID;
wire [3:0]m00_regslice_to_m00_couplers_AWLEN;
wire [1:0]m00_regslice_to_m00_couplers_AWLOCK;
wire [2:0]m00_regslice_to_m00_couplers_AWPROT;
wire [3:0]m00_regslice_to_m00_couplers_AWQOS;
wire m00_regslice_to_m00_couplers_AWREADY;
wire [2:0]m00_regslice_to_m00_couplers_AWSIZE;
wire m00_regslice_to_m00_couplers_AWVALID;
wire [2:0]m00_regslice_to_m00_couplers_BID;
wire m00_regslice_to_m00_couplers_BREADY;
wire [1:0]m00_regslice_to_m00_couplers_BRESP;
wire m00_regslice_to_m00_couplers_BVALID;
wire [63:0]m00_regslice_to_m00_couplers_RDATA;
wire [2:0]m00_regslice_to_m00_couplers_RID;
wire m00_regslice_to_m00_couplers_RLAST;
wire m00_regslice_to_m00_couplers_RREADY;
wire [1:0]m00_regslice_to_m00_couplers_RRESP;
wire m00_regslice_to_m00_couplers_RVALID;
wire [63:0]m00_regslice_to_m00_couplers_WDATA;
wire [0:0]m00_regslice_to_m00_couplers_WID;
wire m00_regslice_to_m00_couplers_WLAST;
wire m00_regslice_to_m00_couplers_WREADY;
wire [7:0]m00_regslice_to_m00_couplers_WSTRB;
wire m00_regslice_to_m00_couplers_WVALID;
assign M_ACLK_1 = M_ACLK;
assign M_ARESETN_1 = M_ARESETN[0];
assign M_AXI_araddr[31:0] = m00_regslice_to_m00_couplers_ARADDR;
assign M_AXI_arburst[1:0] = m00_regslice_to_m00_couplers_ARBURST;
assign M_AXI_arcache[3:0] = m00_regslice_to_m00_couplers_ARCACHE;
assign M_AXI_arid[0] = m00_regslice_to_m00_couplers_ARID;
assign M_AXI_arlen[3:0] = m00_regslice_to_m00_couplers_ARLEN;
assign M_AXI_arlock[1:0] = m00_regslice_to_m00_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = m00_regslice_to_m00_couplers_ARPROT;
assign M_AXI_arqos[3:0] = m00_regslice_to_m00_couplers_ARQOS;
assign M_AXI_arsize[2:0] = m00_regslice_to_m00_couplers_ARSIZE;
assign M_AXI_arvalid = m00_regslice_to_m00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = m00_regslice_to_m00_couplers_AWADDR;
assign M_AXI_awburst[1:0] = m00_regslice_to_m00_couplers_AWBURST;
assign M_AXI_awcache[3:0] = m00_regslice_to_m00_couplers_AWCACHE;
assign M_AXI_awid[0] = m00_regslice_to_m00_couplers_AWID;
assign M_AXI_awlen[3:0] = m00_regslice_to_m00_couplers_AWLEN;
assign M_AXI_awlock[1:0] = m00_regslice_to_m00_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = m00_regslice_to_m00_couplers_AWPROT;
assign M_AXI_awqos[3:0] = m00_regslice_to_m00_couplers_AWQOS;
assign M_AXI_awsize[2:0] = m00_regslice_to_m00_couplers_AWSIZE;
assign M_AXI_awvalid = m00_regslice_to_m00_couplers_AWVALID;
assign M_AXI_bready = m00_regslice_to_m00_couplers_BREADY;
assign M_AXI_rready = m00_regslice_to_m00_couplers_RREADY;
assign M_AXI_wdata[63:0] = m00_regslice_to_m00_couplers_WDATA;
assign M_AXI_wid[0] = m00_regslice_to_m00_couplers_WID;
assign M_AXI_wlast = m00_regslice_to_m00_couplers_WLAST;
assign M_AXI_wstrb[7:0] = m00_regslice_to_m00_couplers_WSTRB;
assign M_AXI_wvalid = m00_regslice_to_m00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = m00_couplers_to_m00_data_fifo_ARREADY;
assign S_AXI_awready = m00_couplers_to_m00_data_fifo_AWREADY;
assign S_AXI_bid[0] = m00_couplers_to_m00_data_fifo_BID;
assign S_AXI_bresp[1:0] = m00_couplers_to_m00_data_fifo_BRESP;
assign S_AXI_bvalid = m00_couplers_to_m00_data_fifo_BVALID;
assign S_AXI_rdata[63:0] = m00_couplers_to_m00_data_fifo_RDATA;
assign S_AXI_rid[0] = m00_couplers_to_m00_data_fifo_RID;
assign S_AXI_rlast = m00_couplers_to_m00_data_fifo_RLAST;
assign S_AXI_rresp[1:0] = m00_couplers_to_m00_data_fifo_RRESP;
assign S_AXI_rvalid = m00_couplers_to_m00_data_fifo_RVALID;
assign S_AXI_wready = m00_couplers_to_m00_data_fifo_WREADY;
assign m00_couplers_to_m00_data_fifo_ARADDR = S_AXI_araddr[31:0];
assign m00_couplers_to_m00_data_fifo_ARBURST = S_AXI_arburst[1:0];
assign m00_couplers_to_m00_data_fifo_ARCACHE = S_AXI_arcache[3:0];
assign m00_couplers_to_m00_data_fifo_ARID = S_AXI_arid[0];
assign m00_couplers_to_m00_data_fifo_ARLEN = S_AXI_arlen[7:0];
assign m00_couplers_to_m00_data_fifo_ARLOCK = S_AXI_arlock[0];
assign m00_couplers_to_m00_data_fifo_ARPROT = S_AXI_arprot[2:0];
assign m00_couplers_to_m00_data_fifo_ARQOS = S_AXI_arqos[3:0];
assign m00_couplers_to_m00_data_fifo_ARREGION = S_AXI_arregion[3:0];
assign m00_couplers_to_m00_data_fifo_ARSIZE = S_AXI_arsize[2:0];
assign m00_couplers_to_m00_data_fifo_ARVALID = S_AXI_arvalid;
assign m00_couplers_to_m00_data_fifo_AWADDR = S_AXI_awaddr[31:0];
assign m00_couplers_to_m00_data_fifo_AWBURST = S_AXI_awburst[1:0];
assign m00_couplers_to_m00_data_fifo_AWCACHE = S_AXI_awcache[3:0];
assign m00_couplers_to_m00_data_fifo_AWID = S_AXI_awid[0];
assign m00_couplers_to_m00_data_fifo_AWLEN = S_AXI_awlen[7:0];
assign m00_couplers_to_m00_data_fifo_AWLOCK = S_AXI_awlock[0];
assign m00_couplers_to_m00_data_fifo_AWPROT = S_AXI_awprot[2:0];
assign m00_couplers_to_m00_data_fifo_AWQOS = S_AXI_awqos[3:0];
assign m00_couplers_to_m00_data_fifo_AWREGION = S_AXI_awregion[3:0];
assign m00_couplers_to_m00_data_fifo_AWSIZE = S_AXI_awsize[2:0];
assign m00_couplers_to_m00_data_fifo_AWVALID = S_AXI_awvalid;
assign m00_couplers_to_m00_data_fifo_BREADY = S_AXI_bready;
assign m00_couplers_to_m00_data_fifo_RREADY = S_AXI_rready;
assign m00_couplers_to_m00_data_fifo_WDATA = S_AXI_wdata[63:0];
assign m00_couplers_to_m00_data_fifo_WLAST = S_AXI_wlast;
assign m00_couplers_to_m00_data_fifo_WSTRB = S_AXI_wstrb[7:0];
assign m00_couplers_to_m00_data_fifo_WVALID = S_AXI_wvalid;
assign m00_regslice_to_m00_couplers_ARREADY = M_AXI_arready;
assign m00_regslice_to_m00_couplers_AWREADY = M_AXI_awready;
assign m00_regslice_to_m00_couplers_BID = M_AXI_bid[2:0];
assign m00_regslice_to_m00_couplers_BRESP = M_AXI_bresp[1:0];
assign m00_regslice_to_m00_couplers_BVALID = M_AXI_bvalid;
assign m00_regslice_to_m00_couplers_RDATA = M_AXI_rdata[63:0];
assign m00_regslice_to_m00_couplers_RID = M_AXI_rid[2:0];
assign m00_regslice_to_m00_couplers_RLAST = M_AXI_rlast;
assign m00_regslice_to_m00_couplers_RRESP = M_AXI_rresp[1:0];
assign m00_regslice_to_m00_couplers_RVALID = M_AXI_rvalid;
assign m00_regslice_to_m00_couplers_WREADY = M_AXI_wready;
zc702_auto_pc_1 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_m00_regslice_ARADDR),
.m_axi_arburst(auto_pc_to_m00_regslice_ARBURST),
.m_axi_arcache(auto_pc_to_m00_regslice_ARCACHE),
.m_axi_arid(auto_pc_to_m00_regslice_ARID),
.m_axi_arlen(auto_pc_to_m00_regslice_ARLEN),
.m_axi_arlock(auto_pc_to_m00_regslice_ARLOCK),
.m_axi_arprot(auto_pc_to_m00_regslice_ARPROT),
.m_axi_arqos(auto_pc_to_m00_regslice_ARQOS),
.m_axi_arready(auto_pc_to_m00_regslice_ARREADY),
.m_axi_arsize(auto_pc_to_m00_regslice_ARSIZE),
.m_axi_arvalid(auto_pc_to_m00_regslice_ARVALID),
.m_axi_awaddr(auto_pc_to_m00_regslice_AWADDR),
.m_axi_awburst(auto_pc_to_m00_regslice_AWBURST),
.m_axi_awcache(auto_pc_to_m00_regslice_AWCACHE),
.m_axi_awid(auto_pc_to_m00_regslice_AWID),
.m_axi_awlen(auto_pc_to_m00_regslice_AWLEN),
.m_axi_awlock(auto_pc_to_m00_regslice_AWLOCK),
.m_axi_awprot(auto_pc_to_m00_regslice_AWPROT),
.m_axi_awqos(auto_pc_to_m00_regslice_AWQOS),
.m_axi_awready(auto_pc_to_m00_regslice_AWREADY),
.m_axi_awsize(auto_pc_to_m00_regslice_AWSIZE),
.m_axi_awvalid(auto_pc_to_m00_regslice_AWVALID),
.m_axi_bid(auto_pc_to_m00_regslice_BID),
.m_axi_bready(auto_pc_to_m00_regslice_BREADY),
.m_axi_bresp(auto_pc_to_m00_regslice_BRESP),
.m_axi_bvalid(auto_pc_to_m00_regslice_BVALID),
.m_axi_rdata(auto_pc_to_m00_regslice_RDATA),
.m_axi_rid(auto_pc_to_m00_regslice_RID),
.m_axi_rlast(auto_pc_to_m00_regslice_RLAST),
.m_axi_rready(auto_pc_to_m00_regslice_RREADY),
.m_axi_rresp(auto_pc_to_m00_regslice_RRESP),
.m_axi_rvalid(auto_pc_to_m00_regslice_RVALID),
.m_axi_wdata(auto_pc_to_m00_regslice_WDATA),
.m_axi_wid(auto_pc_to_m00_regslice_WID),
.m_axi_wlast(auto_pc_to_m00_regslice_WLAST),
.m_axi_wready(auto_pc_to_m00_regslice_WREADY),
.m_axi_wstrb(auto_pc_to_m00_regslice_WSTRB),
.m_axi_wvalid(auto_pc_to_m00_regslice_WVALID),
.s_axi_araddr(m00_data_fifo_to_auto_pc_ARADDR),
.s_axi_arburst(m00_data_fifo_to_auto_pc_ARBURST),
.s_axi_arcache(m00_data_fifo_to_auto_pc_ARCACHE),
.s_axi_arid(m00_data_fifo_to_auto_pc_ARID),
.s_axi_arlen(m00_data_fifo_to_auto_pc_ARLEN),
.s_axi_arlock(m00_data_fifo_to_auto_pc_ARLOCK),
.s_axi_arprot(m00_data_fifo_to_auto_pc_ARPROT),
.s_axi_arqos(m00_data_fifo_to_auto_pc_ARQOS),
.s_axi_arready(m00_data_fifo_to_auto_pc_ARREADY),
.s_axi_arregion(m00_data_fifo_to_auto_pc_ARREGION),
.s_axi_arsize(m00_data_fifo_to_auto_pc_ARSIZE),
.s_axi_arvalid(m00_data_fifo_to_auto_pc_ARVALID),
.s_axi_awaddr(m00_data_fifo_to_auto_pc_AWADDR),
.s_axi_awburst(m00_data_fifo_to_auto_pc_AWBURST),
.s_axi_awcache(m00_data_fifo_to_auto_pc_AWCACHE),
.s_axi_awid(m00_data_fifo_to_auto_pc_AWID),
.s_axi_awlen(m00_data_fifo_to_auto_pc_AWLEN),
.s_axi_awlock(m00_data_fifo_to_auto_pc_AWLOCK),
.s_axi_awprot(m00_data_fifo_to_auto_pc_AWPROT),
.s_axi_awqos(m00_data_fifo_to_auto_pc_AWQOS),
.s_axi_awready(m00_data_fifo_to_auto_pc_AWREADY),
.s_axi_awregion(m00_data_fifo_to_auto_pc_AWREGION),
.s_axi_awsize(m00_data_fifo_to_auto_pc_AWSIZE),
.s_axi_awvalid(m00_data_fifo_to_auto_pc_AWVALID),
.s_axi_bid(m00_data_fifo_to_auto_pc_BID),
.s_axi_bready(m00_data_fifo_to_auto_pc_BREADY),
.s_axi_bresp(m00_data_fifo_to_auto_pc_BRESP),
.s_axi_bvalid(m00_data_fifo_to_auto_pc_BVALID),
.s_axi_rdata(m00_data_fifo_to_auto_pc_RDATA),
.s_axi_rid(m00_data_fifo_to_auto_pc_RID),
.s_axi_rlast(m00_data_fifo_to_auto_pc_RLAST),
.s_axi_rready(m00_data_fifo_to_auto_pc_RREADY),
.s_axi_rresp(m00_data_fifo_to_auto_pc_RRESP),
.s_axi_rvalid(m00_data_fifo_to_auto_pc_RVALID),
.s_axi_wdata(m00_data_fifo_to_auto_pc_WDATA),
.s_axi_wlast(m00_data_fifo_to_auto_pc_WLAST),
.s_axi_wready(m00_data_fifo_to_auto_pc_WREADY),
.s_axi_wstrb(m00_data_fifo_to_auto_pc_WSTRB),
.s_axi_wvalid(m00_data_fifo_to_auto_pc_WVALID));
zc702_m00_data_fifo_0 m00_data_fifo
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(m00_data_fifo_to_auto_pc_ARADDR),
.m_axi_arburst(m00_data_fifo_to_auto_pc_ARBURST),
.m_axi_arcache(m00_data_fifo_to_auto_pc_ARCACHE),
.m_axi_arid(m00_data_fifo_to_auto_pc_ARID),
.m_axi_arlen(m00_data_fifo_to_auto_pc_ARLEN),
.m_axi_arlock(m00_data_fifo_to_auto_pc_ARLOCK),
.m_axi_arprot(m00_data_fifo_to_auto_pc_ARPROT),
.m_axi_arqos(m00_data_fifo_to_auto_pc_ARQOS),
.m_axi_arready(m00_data_fifo_to_auto_pc_ARREADY),
.m_axi_arregion(m00_data_fifo_to_auto_pc_ARREGION),
.m_axi_arsize(m00_data_fifo_to_auto_pc_ARSIZE),
.m_axi_arvalid(m00_data_fifo_to_auto_pc_ARVALID),
.m_axi_awaddr(m00_data_fifo_to_auto_pc_AWADDR),
.m_axi_awburst(m00_data_fifo_to_auto_pc_AWBURST),
.m_axi_awcache(m00_data_fifo_to_auto_pc_AWCACHE),
.m_axi_awid(m00_data_fifo_to_auto_pc_AWID),
.m_axi_awlen(m00_data_fifo_to_auto_pc_AWLEN),
.m_axi_awlock(m00_data_fifo_to_auto_pc_AWLOCK),
.m_axi_awprot(m00_data_fifo_to_auto_pc_AWPROT),
.m_axi_awqos(m00_data_fifo_to_auto_pc_AWQOS),
.m_axi_awready(m00_data_fifo_to_auto_pc_AWREADY),
.m_axi_awregion(m00_data_fifo_to_auto_pc_AWREGION),
.m_axi_awsize(m00_data_fifo_to_auto_pc_AWSIZE),
.m_axi_awvalid(m00_data_fifo_to_auto_pc_AWVALID),
.m_axi_bid(m00_data_fifo_to_auto_pc_BID),
.m_axi_bready(m00_data_fifo_to_auto_pc_BREADY),
.m_axi_bresp(m00_data_fifo_to_auto_pc_BRESP),
.m_axi_bvalid(m00_data_fifo_to_auto_pc_BVALID),
.m_axi_rdata(m00_data_fifo_to_auto_pc_RDATA),
.m_axi_rid(m00_data_fifo_to_auto_pc_RID),
.m_axi_rlast(m00_data_fifo_to_auto_pc_RLAST),
.m_axi_rready(m00_data_fifo_to_auto_pc_RREADY),
.m_axi_rresp(m00_data_fifo_to_auto_pc_RRESP),
.m_axi_rvalid(m00_data_fifo_to_auto_pc_RVALID),
.m_axi_wdata(m00_data_fifo_to_auto_pc_WDATA),
.m_axi_wlast(m00_data_fifo_to_auto_pc_WLAST),
.m_axi_wready(m00_data_fifo_to_auto_pc_WREADY),
.m_axi_wstrb(m00_data_fifo_to_auto_pc_WSTRB),
.m_axi_wvalid(m00_data_fifo_to_auto_pc_WVALID),
.s_axi_araddr(m00_couplers_to_m00_data_fifo_ARADDR),
.s_axi_arburst(m00_couplers_to_m00_data_fifo_ARBURST),
.s_axi_arcache(m00_couplers_to_m00_data_fifo_ARCACHE),
.s_axi_arid(m00_couplers_to_m00_data_fifo_ARID),
.s_axi_arlen(m00_couplers_to_m00_data_fifo_ARLEN),
.s_axi_arlock(m00_couplers_to_m00_data_fifo_ARLOCK),
.s_axi_arprot(m00_couplers_to_m00_data_fifo_ARPROT),
.s_axi_arqos(m00_couplers_to_m00_data_fifo_ARQOS),
.s_axi_arready(m00_couplers_to_m00_data_fifo_ARREADY),
.s_axi_arregion(m00_couplers_to_m00_data_fifo_ARREGION),
.s_axi_arsize(m00_couplers_to_m00_data_fifo_ARSIZE),
.s_axi_arvalid(m00_couplers_to_m00_data_fifo_ARVALID),
.s_axi_awaddr(m00_couplers_to_m00_data_fifo_AWADDR),
.s_axi_awburst(m00_couplers_to_m00_data_fifo_AWBURST),
.s_axi_awcache(m00_couplers_to_m00_data_fifo_AWCACHE),
.s_axi_awid(m00_couplers_to_m00_data_fifo_AWID),
.s_axi_awlen(m00_couplers_to_m00_data_fifo_AWLEN),
.s_axi_awlock(m00_couplers_to_m00_data_fifo_AWLOCK),
.s_axi_awprot(m00_couplers_to_m00_data_fifo_AWPROT),
.s_axi_awqos(m00_couplers_to_m00_data_fifo_AWQOS),
.s_axi_awready(m00_couplers_to_m00_data_fifo_AWREADY),
.s_axi_awregion(m00_couplers_to_m00_data_fifo_AWREGION),
.s_axi_awsize(m00_couplers_to_m00_data_fifo_AWSIZE),
.s_axi_awvalid(m00_couplers_to_m00_data_fifo_AWVALID),
.s_axi_bid(m00_couplers_to_m00_data_fifo_BID),
.s_axi_bready(m00_couplers_to_m00_data_fifo_BREADY),
.s_axi_bresp(m00_couplers_to_m00_data_fifo_BRESP),
.s_axi_bvalid(m00_couplers_to_m00_data_fifo_BVALID),
.s_axi_rdata(m00_couplers_to_m00_data_fifo_RDATA),
.s_axi_rid(m00_couplers_to_m00_data_fifo_RID),
.s_axi_rlast(m00_couplers_to_m00_data_fifo_RLAST),
.s_axi_rready(m00_couplers_to_m00_data_fifo_RREADY),
.s_axi_rresp(m00_couplers_to_m00_data_fifo_RRESP),
.s_axi_rvalid(m00_couplers_to_m00_data_fifo_RVALID),
.s_axi_wdata(m00_couplers_to_m00_data_fifo_WDATA),
.s_axi_wlast(m00_couplers_to_m00_data_fifo_WLAST),
.s_axi_wready(m00_couplers_to_m00_data_fifo_WREADY),
.s_axi_wstrb(m00_couplers_to_m00_data_fifo_WSTRB),
.s_axi_wvalid(m00_couplers_to_m00_data_fifo_WVALID));
zc702_m00_regslice_1 m00_regslice
(.aclk(M_ACLK_1),
.aresetn(M_ARESETN_1),
.m_axi_araddr(m00_regslice_to_m00_couplers_ARADDR),
.m_axi_arburst(m00_regslice_to_m00_couplers_ARBURST),
.m_axi_arcache(m00_regslice_to_m00_couplers_ARCACHE),
.m_axi_arid(m00_regslice_to_m00_couplers_ARID),
.m_axi_arlen(m00_regslice_to_m00_couplers_ARLEN),
.m_axi_arlock(m00_regslice_to_m00_couplers_ARLOCK),
.m_axi_arprot(m00_regslice_to_m00_couplers_ARPROT),
.m_axi_arqos(m00_regslice_to_m00_couplers_ARQOS),
.m_axi_arready(m00_regslice_to_m00_couplers_ARREADY),
.m_axi_arsize(m00_regslice_to_m00_couplers_ARSIZE),
.m_axi_arvalid(m00_regslice_to_m00_couplers_ARVALID),
.m_axi_awaddr(m00_regslice_to_m00_couplers_AWADDR),
.m_axi_awburst(m00_regslice_to_m00_couplers_AWBURST),
.m_axi_awcache(m00_regslice_to_m00_couplers_AWCACHE),
.m_axi_awid(m00_regslice_to_m00_couplers_AWID),
.m_axi_awlen(m00_regslice_to_m00_couplers_AWLEN),
.m_axi_awlock(m00_regslice_to_m00_couplers_AWLOCK),
.m_axi_awprot(m00_regslice_to_m00_couplers_AWPROT),
.m_axi_awqos(m00_regslice_to_m00_couplers_AWQOS),
.m_axi_awready(m00_regslice_to_m00_couplers_AWREADY),
.m_axi_awsize(m00_regslice_to_m00_couplers_AWSIZE),
.m_axi_awvalid(m00_regslice_to_m00_couplers_AWVALID),
.m_axi_bid(m00_regslice_to_m00_couplers_BID[0]),
.m_axi_bready(m00_regslice_to_m00_couplers_BREADY),
.m_axi_bresp(m00_regslice_to_m00_couplers_BRESP),
.m_axi_bvalid(m00_regslice_to_m00_couplers_BVALID),
.m_axi_rdata(m00_regslice_to_m00_couplers_RDATA),
.m_axi_rid(m00_regslice_to_m00_couplers_RID[0]),
.m_axi_rlast(m00_regslice_to_m00_couplers_RLAST),
.m_axi_rready(m00_regslice_to_m00_couplers_RREADY),
.m_axi_rresp(m00_regslice_to_m00_couplers_RRESP),
.m_axi_rvalid(m00_regslice_to_m00_couplers_RVALID),
.m_axi_wdata(m00_regslice_to_m00_couplers_WDATA),
.m_axi_wid(m00_regslice_to_m00_couplers_WID),
.m_axi_wlast(m00_regslice_to_m00_couplers_WLAST),
.m_axi_wready(m00_regslice_to_m00_couplers_WREADY),
.m_axi_wstrb(m00_regslice_to_m00_couplers_WSTRB),
.m_axi_wvalid(m00_regslice_to_m00_couplers_WVALID),
.s_axi_araddr(auto_pc_to_m00_regslice_ARADDR),
.s_axi_arburst(auto_pc_to_m00_regslice_ARBURST),
.s_axi_arcache(auto_pc_to_m00_regslice_ARCACHE),
.s_axi_arid(auto_pc_to_m00_regslice_ARID),
.s_axi_arlen(auto_pc_to_m00_regslice_ARLEN),
.s_axi_arlock(auto_pc_to_m00_regslice_ARLOCK),
.s_axi_arprot(auto_pc_to_m00_regslice_ARPROT),
.s_axi_arqos(auto_pc_to_m00_regslice_ARQOS),
.s_axi_arready(auto_pc_to_m00_regslice_ARREADY),
.s_axi_arsize(auto_pc_to_m00_regslice_ARSIZE),
.s_axi_arvalid(auto_pc_to_m00_regslice_ARVALID),
.s_axi_awaddr(auto_pc_to_m00_regslice_AWADDR),
.s_axi_awburst(auto_pc_to_m00_regslice_AWBURST),
.s_axi_awcache(auto_pc_to_m00_regslice_AWCACHE),
.s_axi_awid(auto_pc_to_m00_regslice_AWID),
.s_axi_awlen(auto_pc_to_m00_regslice_AWLEN),
.s_axi_awlock(auto_pc_to_m00_regslice_AWLOCK),
.s_axi_awprot(auto_pc_to_m00_regslice_AWPROT),
.s_axi_awqos(auto_pc_to_m00_regslice_AWQOS),
.s_axi_awready(auto_pc_to_m00_regslice_AWREADY),
.s_axi_awsize(auto_pc_to_m00_regslice_AWSIZE),
.s_axi_awvalid(auto_pc_to_m00_regslice_AWVALID),
.s_axi_bid(auto_pc_to_m00_regslice_BID),
.s_axi_bready(auto_pc_to_m00_regslice_BREADY),
.s_axi_bresp(auto_pc_to_m00_regslice_BRESP),
.s_axi_bvalid(auto_pc_to_m00_regslice_BVALID),
.s_axi_rdata(auto_pc_to_m00_regslice_RDATA),
.s_axi_rid(auto_pc_to_m00_regslice_RID),
.s_axi_rlast(auto_pc_to_m00_regslice_RLAST),
.s_axi_rready(auto_pc_to_m00_regslice_RREADY),
.s_axi_rresp(auto_pc_to_m00_regslice_RRESP),
.s_axi_rvalid(auto_pc_to_m00_regslice_RVALID),
.s_axi_wdata(auto_pc_to_m00_regslice_WDATA),
.s_axi_wid(auto_pc_to_m00_regslice_WID),
.s_axi_wlast(auto_pc_to_m00_regslice_WLAST),
.s_axi_wready(auto_pc_to_m00_regslice_WREADY),
.s_axi_wstrb(auto_pc_to_m00_regslice_WSTRB),
.s_axi_wvalid(auto_pc_to_m00_regslice_WVALID));
endmodule
module m01_couplers_imp_YRHFB1
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arprot,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awprot,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [12:0]M_AXI_araddr;
input M_AXI_arready;
output M_AXI_arvalid;
output [12:0]M_AXI_awaddr;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [2:0]S_AXI_arprot;
output S_AXI_arready;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [2:0]S_AXI_awprot;
output S_AXI_awready;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire M_ACLK_1;
wire [0:0]M_ARESETN_1;
wire [31:0]m01_couplers_to_m01_regslice_ARADDR;
wire [2:0]m01_couplers_to_m01_regslice_ARPROT;
wire m01_couplers_to_m01_regslice_ARREADY;
wire m01_couplers_to_m01_regslice_ARVALID;
wire [31:0]m01_couplers_to_m01_regslice_AWADDR;
wire [2:0]m01_couplers_to_m01_regslice_AWPROT;
wire m01_couplers_to_m01_regslice_AWREADY;
wire m01_couplers_to_m01_regslice_AWVALID;
wire m01_couplers_to_m01_regslice_BREADY;
wire [1:0]m01_couplers_to_m01_regslice_BRESP;
wire m01_couplers_to_m01_regslice_BVALID;
wire [31:0]m01_couplers_to_m01_regslice_RDATA;
wire m01_couplers_to_m01_regslice_RREADY;
wire [1:0]m01_couplers_to_m01_regslice_RRESP;
wire m01_couplers_to_m01_regslice_RVALID;
wire [31:0]m01_couplers_to_m01_regslice_WDATA;
wire m01_couplers_to_m01_regslice_WREADY;
wire [3:0]m01_couplers_to_m01_regslice_WSTRB;
wire m01_couplers_to_m01_regslice_WVALID;
wire [12:0]m01_regslice_to_m01_couplers_ARADDR;
wire m01_regslice_to_m01_couplers_ARREADY;
wire m01_regslice_to_m01_couplers_ARVALID;
wire [12:0]m01_regslice_to_m01_couplers_AWADDR;
wire m01_regslice_to_m01_couplers_AWREADY;
wire m01_regslice_to_m01_couplers_AWVALID;
wire m01_regslice_to_m01_couplers_BREADY;
wire [1:0]m01_regslice_to_m01_couplers_BRESP;
wire m01_regslice_to_m01_couplers_BVALID;
wire [31:0]m01_regslice_to_m01_couplers_RDATA;
wire m01_regslice_to_m01_couplers_RREADY;
wire [1:0]m01_regslice_to_m01_couplers_RRESP;
wire m01_regslice_to_m01_couplers_RVALID;
wire [31:0]m01_regslice_to_m01_couplers_WDATA;
wire m01_regslice_to_m01_couplers_WREADY;
wire [3:0]m01_regslice_to_m01_couplers_WSTRB;
wire m01_regslice_to_m01_couplers_WVALID;
assign M_ACLK_1 = M_ACLK;
assign M_ARESETN_1 = M_ARESETN[0];
assign M_AXI_araddr[12:0] = m01_regslice_to_m01_couplers_ARADDR;
assign M_AXI_arvalid = m01_regslice_to_m01_couplers_ARVALID;
assign M_AXI_awaddr[12:0] = m01_regslice_to_m01_couplers_AWADDR;
assign M_AXI_awvalid = m01_regslice_to_m01_couplers_AWVALID;
assign M_AXI_bready = m01_regslice_to_m01_couplers_BREADY;
assign M_AXI_rready = m01_regslice_to_m01_couplers_RREADY;
assign M_AXI_wdata[31:0] = m01_regslice_to_m01_couplers_WDATA;
assign M_AXI_wstrb[3:0] = m01_regslice_to_m01_couplers_WSTRB;
assign M_AXI_wvalid = m01_regslice_to_m01_couplers_WVALID;
assign S_AXI_arready = m01_couplers_to_m01_regslice_ARREADY;
assign S_AXI_awready = m01_couplers_to_m01_regslice_AWREADY;
assign S_AXI_bresp[1:0] = m01_couplers_to_m01_regslice_BRESP;
assign S_AXI_bvalid = m01_couplers_to_m01_regslice_BVALID;
assign S_AXI_rdata[31:0] = m01_couplers_to_m01_regslice_RDATA;
assign S_AXI_rresp[1:0] = m01_couplers_to_m01_regslice_RRESP;
assign S_AXI_rvalid = m01_couplers_to_m01_regslice_RVALID;
assign S_AXI_wready = m01_couplers_to_m01_regslice_WREADY;
assign m01_couplers_to_m01_regslice_ARADDR = S_AXI_araddr[31:0];
assign m01_couplers_to_m01_regslice_ARPROT = S_AXI_arprot[2:0];
assign m01_couplers_to_m01_regslice_ARVALID = S_AXI_arvalid;
assign m01_couplers_to_m01_regslice_AWADDR = S_AXI_awaddr[31:0];
assign m01_couplers_to_m01_regslice_AWPROT = S_AXI_awprot[2:0];
assign m01_couplers_to_m01_regslice_AWVALID = S_AXI_awvalid;
assign m01_couplers_to_m01_regslice_BREADY = S_AXI_bready;
assign m01_couplers_to_m01_regslice_RREADY = S_AXI_rready;
assign m01_couplers_to_m01_regslice_WDATA = S_AXI_wdata[31:0];
assign m01_couplers_to_m01_regslice_WSTRB = S_AXI_wstrb[3:0];
assign m01_couplers_to_m01_regslice_WVALID = S_AXI_wvalid;
assign m01_regslice_to_m01_couplers_ARREADY = M_AXI_arready;
assign m01_regslice_to_m01_couplers_AWREADY = M_AXI_awready;
assign m01_regslice_to_m01_couplers_BRESP = M_AXI_bresp[1:0];
assign m01_regslice_to_m01_couplers_BVALID = M_AXI_bvalid;
assign m01_regslice_to_m01_couplers_RDATA = M_AXI_rdata[31:0];
assign m01_regslice_to_m01_couplers_RRESP = M_AXI_rresp[1:0];
assign m01_regslice_to_m01_couplers_RVALID = M_AXI_rvalid;
assign m01_regslice_to_m01_couplers_WREADY = M_AXI_wready;
zc702_m01_regslice_0 m01_regslice
(.aclk(M_ACLK_1),
.aresetn(M_ARESETN_1),
.m_axi_araddr(m01_regslice_to_m01_couplers_ARADDR),
.m_axi_arready(m01_regslice_to_m01_couplers_ARREADY),
.m_axi_arvalid(m01_regslice_to_m01_couplers_ARVALID),
.m_axi_awaddr(m01_regslice_to_m01_couplers_AWADDR),
.m_axi_awready(m01_regslice_to_m01_couplers_AWREADY),
.m_axi_awvalid(m01_regslice_to_m01_couplers_AWVALID),
.m_axi_bready(m01_regslice_to_m01_couplers_BREADY),
.m_axi_bresp(m01_regslice_to_m01_couplers_BRESP),
.m_axi_bvalid(m01_regslice_to_m01_couplers_BVALID),
.m_axi_rdata(m01_regslice_to_m01_couplers_RDATA),
.m_axi_rready(m01_regslice_to_m01_couplers_RREADY),
.m_axi_rresp(m01_regslice_to_m01_couplers_RRESP),
.m_axi_rvalid(m01_regslice_to_m01_couplers_RVALID),
.m_axi_wdata(m01_regslice_to_m01_couplers_WDATA),
.m_axi_wready(m01_regslice_to_m01_couplers_WREADY),
.m_axi_wstrb(m01_regslice_to_m01_couplers_WSTRB),
.m_axi_wvalid(m01_regslice_to_m01_couplers_WVALID),
.s_axi_araddr(m01_couplers_to_m01_regslice_ARADDR[12:0]),
.s_axi_arprot(m01_couplers_to_m01_regslice_ARPROT),
.s_axi_arready(m01_couplers_to_m01_regslice_ARREADY),
.s_axi_arvalid(m01_couplers_to_m01_regslice_ARVALID),
.s_axi_awaddr(m01_couplers_to_m01_regslice_AWADDR[12:0]),
.s_axi_awprot(m01_couplers_to_m01_regslice_AWPROT),
.s_axi_awready(m01_couplers_to_m01_regslice_AWREADY),
.s_axi_awvalid(m01_couplers_to_m01_regslice_AWVALID),
.s_axi_bready(m01_couplers_to_m01_regslice_BREADY),
.s_axi_bresp(m01_couplers_to_m01_regslice_BRESP),
.s_axi_bvalid(m01_couplers_to_m01_regslice_BVALID),
.s_axi_rdata(m01_couplers_to_m01_regslice_RDATA),
.s_axi_rready(m01_couplers_to_m01_regslice_RREADY),
.s_axi_rresp(m01_couplers_to_m01_regslice_RRESP),
.s_axi_rvalid(m01_couplers_to_m01_regslice_RVALID),
.s_axi_wdata(m01_couplers_to_m01_regslice_WDATA),
.s_axi_wready(m01_couplers_to_m01_regslice_WREADY),
.s_axi_wstrb(m01_couplers_to_m01_regslice_WSTRB),
.s_axi_wvalid(m01_couplers_to_m01_regslice_WVALID));
endmodule
module s00_couplers_imp_14Q0TRY
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wid,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_araddr;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [11:0]S_AXI_arid;
input [3:0]S_AXI_arlen;
input [1:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [11:0]S_AXI_awid;
input [3:0]S_AXI_awlen;
input [1:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [11:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output [11:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input [11:0]S_AXI_wid;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire M_ACLK_1;
wire [0:0]M_ARESETN_1;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_s00_data_fifo_ARADDR;
wire [2:0]auto_pc_to_s00_data_fifo_ARPROT;
wire auto_pc_to_s00_data_fifo_ARREADY;
wire auto_pc_to_s00_data_fifo_ARVALID;
wire [31:0]auto_pc_to_s00_data_fifo_AWADDR;
wire [2:0]auto_pc_to_s00_data_fifo_AWPROT;
wire auto_pc_to_s00_data_fifo_AWREADY;
wire auto_pc_to_s00_data_fifo_AWVALID;
wire auto_pc_to_s00_data_fifo_BREADY;
wire [1:0]auto_pc_to_s00_data_fifo_BRESP;
wire auto_pc_to_s00_data_fifo_BVALID;
wire [31:0]auto_pc_to_s00_data_fifo_RDATA;
wire auto_pc_to_s00_data_fifo_RREADY;
wire [1:0]auto_pc_to_s00_data_fifo_RRESP;
wire auto_pc_to_s00_data_fifo_RVALID;
wire [31:0]auto_pc_to_s00_data_fifo_WDATA;
wire auto_pc_to_s00_data_fifo_WREADY;
wire [3:0]auto_pc_to_s00_data_fifo_WSTRB;
wire auto_pc_to_s00_data_fifo_WVALID;
wire [31:0]s00_couplers_to_s00_regslice_ARADDR;
wire [1:0]s00_couplers_to_s00_regslice_ARBURST;
wire [3:0]s00_couplers_to_s00_regslice_ARCACHE;
wire [11:0]s00_couplers_to_s00_regslice_ARID;
wire [3:0]s00_couplers_to_s00_regslice_ARLEN;
wire [1:0]s00_couplers_to_s00_regslice_ARLOCK;
wire [2:0]s00_couplers_to_s00_regslice_ARPROT;
wire [3:0]s00_couplers_to_s00_regslice_ARQOS;
wire s00_couplers_to_s00_regslice_ARREADY;
wire [2:0]s00_couplers_to_s00_regslice_ARSIZE;
wire s00_couplers_to_s00_regslice_ARVALID;
wire [31:0]s00_couplers_to_s00_regslice_AWADDR;
wire [1:0]s00_couplers_to_s00_regslice_AWBURST;
wire [3:0]s00_couplers_to_s00_regslice_AWCACHE;
wire [11:0]s00_couplers_to_s00_regslice_AWID;
wire [3:0]s00_couplers_to_s00_regslice_AWLEN;
wire [1:0]s00_couplers_to_s00_regslice_AWLOCK;
wire [2:0]s00_couplers_to_s00_regslice_AWPROT;
wire [3:0]s00_couplers_to_s00_regslice_AWQOS;
wire s00_couplers_to_s00_regslice_AWREADY;
wire [2:0]s00_couplers_to_s00_regslice_AWSIZE;
wire s00_couplers_to_s00_regslice_AWVALID;
wire [11:0]s00_couplers_to_s00_regslice_BID;
wire s00_couplers_to_s00_regslice_BREADY;
wire [1:0]s00_couplers_to_s00_regslice_BRESP;
wire s00_couplers_to_s00_regslice_BVALID;
wire [31:0]s00_couplers_to_s00_regslice_RDATA;
wire [11:0]s00_couplers_to_s00_regslice_RID;
wire s00_couplers_to_s00_regslice_RLAST;
wire s00_couplers_to_s00_regslice_RREADY;
wire [1:0]s00_couplers_to_s00_regslice_RRESP;
wire s00_couplers_to_s00_regslice_RVALID;
wire [31:0]s00_couplers_to_s00_regslice_WDATA;
wire [11:0]s00_couplers_to_s00_regslice_WID;
wire s00_couplers_to_s00_regslice_WLAST;
wire s00_couplers_to_s00_regslice_WREADY;
wire [3:0]s00_couplers_to_s00_regslice_WSTRB;
wire s00_couplers_to_s00_regslice_WVALID;
wire [31:0]s00_data_fifo_to_s00_couplers_ARADDR;
wire [2:0]s00_data_fifo_to_s00_couplers_ARPROT;
wire s00_data_fifo_to_s00_couplers_ARREADY;
wire s00_data_fifo_to_s00_couplers_ARVALID;
wire [31:0]s00_data_fifo_to_s00_couplers_AWADDR;
wire [2:0]s00_data_fifo_to_s00_couplers_AWPROT;
wire s00_data_fifo_to_s00_couplers_AWREADY;
wire s00_data_fifo_to_s00_couplers_AWVALID;
wire s00_data_fifo_to_s00_couplers_BREADY;
wire [1:0]s00_data_fifo_to_s00_couplers_BRESP;
wire s00_data_fifo_to_s00_couplers_BVALID;
wire [31:0]s00_data_fifo_to_s00_couplers_RDATA;
wire s00_data_fifo_to_s00_couplers_RREADY;
wire [1:0]s00_data_fifo_to_s00_couplers_RRESP;
wire s00_data_fifo_to_s00_couplers_RVALID;
wire [31:0]s00_data_fifo_to_s00_couplers_WDATA;
wire s00_data_fifo_to_s00_couplers_WREADY;
wire [3:0]s00_data_fifo_to_s00_couplers_WSTRB;
wire s00_data_fifo_to_s00_couplers_WVALID;
wire [31:0]s00_regslice_to_auto_pc_ARADDR;
wire [1:0]s00_regslice_to_auto_pc_ARBURST;
wire [3:0]s00_regslice_to_auto_pc_ARCACHE;
wire [11:0]s00_regslice_to_auto_pc_ARID;
wire [3:0]s00_regslice_to_auto_pc_ARLEN;
wire [1:0]s00_regslice_to_auto_pc_ARLOCK;
wire [2:0]s00_regslice_to_auto_pc_ARPROT;
wire [3:0]s00_regslice_to_auto_pc_ARQOS;
wire s00_regslice_to_auto_pc_ARREADY;
wire [2:0]s00_regslice_to_auto_pc_ARSIZE;
wire s00_regslice_to_auto_pc_ARVALID;
wire [31:0]s00_regslice_to_auto_pc_AWADDR;
wire [1:0]s00_regslice_to_auto_pc_AWBURST;
wire [3:0]s00_regslice_to_auto_pc_AWCACHE;
wire [11:0]s00_regslice_to_auto_pc_AWID;
wire [3:0]s00_regslice_to_auto_pc_AWLEN;
wire [1:0]s00_regslice_to_auto_pc_AWLOCK;
wire [2:0]s00_regslice_to_auto_pc_AWPROT;
wire [3:0]s00_regslice_to_auto_pc_AWQOS;
wire s00_regslice_to_auto_pc_AWREADY;
wire [2:0]s00_regslice_to_auto_pc_AWSIZE;
wire s00_regslice_to_auto_pc_AWVALID;
wire [11:0]s00_regslice_to_auto_pc_BID;
wire s00_regslice_to_auto_pc_BREADY;
wire [1:0]s00_regslice_to_auto_pc_BRESP;
wire s00_regslice_to_auto_pc_BVALID;
wire [31:0]s00_regslice_to_auto_pc_RDATA;
wire [11:0]s00_regslice_to_auto_pc_RID;
wire s00_regslice_to_auto_pc_RLAST;
wire s00_regslice_to_auto_pc_RREADY;
wire [1:0]s00_regslice_to_auto_pc_RRESP;
wire s00_regslice_to_auto_pc_RVALID;
wire [31:0]s00_regslice_to_auto_pc_WDATA;
wire [11:0]s00_regslice_to_auto_pc_WID;
wire s00_regslice_to_auto_pc_WLAST;
wire s00_regslice_to_auto_pc_WREADY;
wire [3:0]s00_regslice_to_auto_pc_WSTRB;
wire s00_regslice_to_auto_pc_WVALID;
assign M_ACLK_1 = M_ACLK;
assign M_ARESETN_1 = M_ARESETN[0];
assign M_AXI_araddr[31:0] = s00_data_fifo_to_s00_couplers_ARADDR;
assign M_AXI_arprot[2:0] = s00_data_fifo_to_s00_couplers_ARPROT;
assign M_AXI_arvalid = s00_data_fifo_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = s00_data_fifo_to_s00_couplers_AWADDR;
assign M_AXI_awprot[2:0] = s00_data_fifo_to_s00_couplers_AWPROT;
assign M_AXI_awvalid = s00_data_fifo_to_s00_couplers_AWVALID;
assign M_AXI_bready = s00_data_fifo_to_s00_couplers_BREADY;
assign M_AXI_rready = s00_data_fifo_to_s00_couplers_RREADY;
assign M_AXI_wdata[31:0] = s00_data_fifo_to_s00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = s00_data_fifo_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = s00_data_fifo_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = s00_couplers_to_s00_regslice_ARREADY;
assign S_AXI_awready = s00_couplers_to_s00_regslice_AWREADY;
assign S_AXI_bid[11:0] = s00_couplers_to_s00_regslice_BID;
assign S_AXI_bresp[1:0] = s00_couplers_to_s00_regslice_BRESP;
assign S_AXI_bvalid = s00_couplers_to_s00_regslice_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_s00_regslice_RDATA;
assign S_AXI_rid[11:0] = s00_couplers_to_s00_regslice_RID;
assign S_AXI_rlast = s00_couplers_to_s00_regslice_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_s00_regslice_RRESP;
assign S_AXI_rvalid = s00_couplers_to_s00_regslice_RVALID;
assign S_AXI_wready = s00_couplers_to_s00_regslice_WREADY;
assign s00_couplers_to_s00_regslice_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_s00_regslice_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_s00_regslice_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_s00_regslice_ARID = S_AXI_arid[11:0];
assign s00_couplers_to_s00_regslice_ARLEN = S_AXI_arlen[3:0];
assign s00_couplers_to_s00_regslice_ARLOCK = S_AXI_arlock[1:0];
assign s00_couplers_to_s00_regslice_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_s00_regslice_ARQOS = S_AXI_arqos[3:0];
assign s00_couplers_to_s00_regslice_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_s00_regslice_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_s00_regslice_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_s00_regslice_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_s00_regslice_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_s00_regslice_AWID = S_AXI_awid[11:0];
assign s00_couplers_to_s00_regslice_AWLEN = S_AXI_awlen[3:0];
assign s00_couplers_to_s00_regslice_AWLOCK = S_AXI_awlock[1:0];
assign s00_couplers_to_s00_regslice_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_s00_regslice_AWQOS = S_AXI_awqos[3:0];
assign s00_couplers_to_s00_regslice_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_s00_regslice_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_s00_regslice_BREADY = S_AXI_bready;
assign s00_couplers_to_s00_regslice_RREADY = S_AXI_rready;
assign s00_couplers_to_s00_regslice_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_s00_regslice_WID = S_AXI_wid[11:0];
assign s00_couplers_to_s00_regslice_WLAST = S_AXI_wlast;
assign s00_couplers_to_s00_regslice_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_s00_regslice_WVALID = S_AXI_wvalid;
assign s00_data_fifo_to_s00_couplers_ARREADY = M_AXI_arready;
assign s00_data_fifo_to_s00_couplers_AWREADY = M_AXI_awready;
assign s00_data_fifo_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign s00_data_fifo_to_s00_couplers_BVALID = M_AXI_bvalid;
assign s00_data_fifo_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
assign s00_data_fifo_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign s00_data_fifo_to_s00_couplers_RVALID = M_AXI_rvalid;
assign s00_data_fifo_to_s00_couplers_WREADY = M_AXI_wready;
zc702_auto_pc_0 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_s00_data_fifo_ARADDR),
.m_axi_arprot(auto_pc_to_s00_data_fifo_ARPROT),
.m_axi_arready(auto_pc_to_s00_data_fifo_ARREADY),
.m_axi_arvalid(auto_pc_to_s00_data_fifo_ARVALID),
.m_axi_awaddr(auto_pc_to_s00_data_fifo_AWADDR),
.m_axi_awprot(auto_pc_to_s00_data_fifo_AWPROT),
.m_axi_awready(auto_pc_to_s00_data_fifo_AWREADY),
.m_axi_awvalid(auto_pc_to_s00_data_fifo_AWVALID),
.m_axi_bready(auto_pc_to_s00_data_fifo_BREADY),
.m_axi_bresp(auto_pc_to_s00_data_fifo_BRESP),
.m_axi_bvalid(auto_pc_to_s00_data_fifo_BVALID),
.m_axi_rdata(auto_pc_to_s00_data_fifo_RDATA),
.m_axi_rready(auto_pc_to_s00_data_fifo_RREADY),
.m_axi_rresp(auto_pc_to_s00_data_fifo_RRESP),
.m_axi_rvalid(auto_pc_to_s00_data_fifo_RVALID),
.m_axi_wdata(auto_pc_to_s00_data_fifo_WDATA),
.m_axi_wready(auto_pc_to_s00_data_fifo_WREADY),
.m_axi_wstrb(auto_pc_to_s00_data_fifo_WSTRB),
.m_axi_wvalid(auto_pc_to_s00_data_fifo_WVALID),
.s_axi_araddr(s00_regslice_to_auto_pc_ARADDR),
.s_axi_arburst(s00_regslice_to_auto_pc_ARBURST),
.s_axi_arcache(s00_regslice_to_auto_pc_ARCACHE),
.s_axi_arid(s00_regslice_to_auto_pc_ARID),
.s_axi_arlen(s00_regslice_to_auto_pc_ARLEN),
.s_axi_arlock(s00_regslice_to_auto_pc_ARLOCK),
.s_axi_arprot(s00_regslice_to_auto_pc_ARPROT),
.s_axi_arqos(s00_regslice_to_auto_pc_ARQOS),
.s_axi_arready(s00_regslice_to_auto_pc_ARREADY),
.s_axi_arsize(s00_regslice_to_auto_pc_ARSIZE),
.s_axi_arvalid(s00_regslice_to_auto_pc_ARVALID),
.s_axi_awaddr(s00_regslice_to_auto_pc_AWADDR),
.s_axi_awburst(s00_regslice_to_auto_pc_AWBURST),
.s_axi_awcache(s00_regslice_to_auto_pc_AWCACHE),
.s_axi_awid(s00_regslice_to_auto_pc_AWID),
.s_axi_awlen(s00_regslice_to_auto_pc_AWLEN),
.s_axi_awlock(s00_regslice_to_auto_pc_AWLOCK),
.s_axi_awprot(s00_regslice_to_auto_pc_AWPROT),
.s_axi_awqos(s00_regslice_to_auto_pc_AWQOS),
.s_axi_awready(s00_regslice_to_auto_pc_AWREADY),
.s_axi_awsize(s00_regslice_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_regslice_to_auto_pc_AWVALID),
.s_axi_bid(s00_regslice_to_auto_pc_BID),
.s_axi_bready(s00_regslice_to_auto_pc_BREADY),
.s_axi_bresp(s00_regslice_to_auto_pc_BRESP),
.s_axi_bvalid(s00_regslice_to_auto_pc_BVALID),
.s_axi_rdata(s00_regslice_to_auto_pc_RDATA),
.s_axi_rid(s00_regslice_to_auto_pc_RID),
.s_axi_rlast(s00_regslice_to_auto_pc_RLAST),
.s_axi_rready(s00_regslice_to_auto_pc_RREADY),
.s_axi_rresp(s00_regslice_to_auto_pc_RRESP),
.s_axi_rvalid(s00_regslice_to_auto_pc_RVALID),
.s_axi_wdata(s00_regslice_to_auto_pc_WDATA),
.s_axi_wid(s00_regslice_to_auto_pc_WID),
.s_axi_wlast(s00_regslice_to_auto_pc_WLAST),
.s_axi_wready(s00_regslice_to_auto_pc_WREADY),
.s_axi_wstrb(s00_regslice_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_regslice_to_auto_pc_WVALID));
zc702_s00_data_fifo_0 s00_data_fifo
(.aclk(M_ACLK_1),
.aresetn(M_ARESETN_1),
.m_axi_araddr(s00_data_fifo_to_s00_couplers_ARADDR),
.m_axi_arprot(s00_data_fifo_to_s00_couplers_ARPROT),
.m_axi_arready(s00_data_fifo_to_s00_couplers_ARREADY),
.m_axi_arvalid(s00_data_fifo_to_s00_couplers_ARVALID),
.m_axi_awaddr(s00_data_fifo_to_s00_couplers_AWADDR),
.m_axi_awprot(s00_data_fifo_to_s00_couplers_AWPROT),
.m_axi_awready(s00_data_fifo_to_s00_couplers_AWREADY),
.m_axi_awvalid(s00_data_fifo_to_s00_couplers_AWVALID),
.m_axi_bready(s00_data_fifo_to_s00_couplers_BREADY),
.m_axi_bresp(s00_data_fifo_to_s00_couplers_BRESP),
.m_axi_bvalid(s00_data_fifo_to_s00_couplers_BVALID),
.m_axi_rdata(s00_data_fifo_to_s00_couplers_RDATA),
.m_axi_rready(s00_data_fifo_to_s00_couplers_RREADY),
.m_axi_rresp(s00_data_fifo_to_s00_couplers_RRESP),
.m_axi_rvalid(s00_data_fifo_to_s00_couplers_RVALID),
.m_axi_wdata(s00_data_fifo_to_s00_couplers_WDATA),
.m_axi_wready(s00_data_fifo_to_s00_couplers_WREADY),
.m_axi_wstrb(s00_data_fifo_to_s00_couplers_WSTRB),
.m_axi_wvalid(s00_data_fifo_to_s00_couplers_WVALID),
.s_axi_araddr(auto_pc_to_s00_data_fifo_ARADDR),
.s_axi_arprot(auto_pc_to_s00_data_fifo_ARPROT),
.s_axi_arready(auto_pc_to_s00_data_fifo_ARREADY),
.s_axi_arvalid(auto_pc_to_s00_data_fifo_ARVALID),
.s_axi_awaddr(auto_pc_to_s00_data_fifo_AWADDR),
.s_axi_awprot(auto_pc_to_s00_data_fifo_AWPROT),
.s_axi_awready(auto_pc_to_s00_data_fifo_AWREADY),
.s_axi_awvalid(auto_pc_to_s00_data_fifo_AWVALID),
.s_axi_bready(auto_pc_to_s00_data_fifo_BREADY),
.s_axi_bresp(auto_pc_to_s00_data_fifo_BRESP),
.s_axi_bvalid(auto_pc_to_s00_data_fifo_BVALID),
.s_axi_rdata(auto_pc_to_s00_data_fifo_RDATA),
.s_axi_rready(auto_pc_to_s00_data_fifo_RREADY),
.s_axi_rresp(auto_pc_to_s00_data_fifo_RRESP),
.s_axi_rvalid(auto_pc_to_s00_data_fifo_RVALID),
.s_axi_wdata(auto_pc_to_s00_data_fifo_WDATA),
.s_axi_wready(auto_pc_to_s00_data_fifo_WREADY),
.s_axi_wstrb(auto_pc_to_s00_data_fifo_WSTRB),
.s_axi_wvalid(auto_pc_to_s00_data_fifo_WVALID));
zc702_s00_regslice_0 s00_regslice
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(s00_regslice_to_auto_pc_ARADDR),
.m_axi_arburst(s00_regslice_to_auto_pc_ARBURST),
.m_axi_arcache(s00_regslice_to_auto_pc_ARCACHE),
.m_axi_arid(s00_regslice_to_auto_pc_ARID),
.m_axi_arlen(s00_regslice_to_auto_pc_ARLEN),
.m_axi_arlock(s00_regslice_to_auto_pc_ARLOCK),
.m_axi_arprot(s00_regslice_to_auto_pc_ARPROT),
.m_axi_arqos(s00_regslice_to_auto_pc_ARQOS),
.m_axi_arready(s00_regslice_to_auto_pc_ARREADY),
.m_axi_arsize(s00_regslice_to_auto_pc_ARSIZE),
.m_axi_arvalid(s00_regslice_to_auto_pc_ARVALID),
.m_axi_awaddr(s00_regslice_to_auto_pc_AWADDR),
.m_axi_awburst(s00_regslice_to_auto_pc_AWBURST),
.m_axi_awcache(s00_regslice_to_auto_pc_AWCACHE),
.m_axi_awid(s00_regslice_to_auto_pc_AWID),
.m_axi_awlen(s00_regslice_to_auto_pc_AWLEN),
.m_axi_awlock(s00_regslice_to_auto_pc_AWLOCK),
.m_axi_awprot(s00_regslice_to_auto_pc_AWPROT),
.m_axi_awqos(s00_regslice_to_auto_pc_AWQOS),
.m_axi_awready(s00_regslice_to_auto_pc_AWREADY),
.m_axi_awsize(s00_regslice_to_auto_pc_AWSIZE),
.m_axi_awvalid(s00_regslice_to_auto_pc_AWVALID),
.m_axi_bid(s00_regslice_to_auto_pc_BID),
.m_axi_bready(s00_regslice_to_auto_pc_BREADY),
.m_axi_bresp(s00_regslice_to_auto_pc_BRESP),
.m_axi_bvalid(s00_regslice_to_auto_pc_BVALID),
.m_axi_rdata(s00_regslice_to_auto_pc_RDATA),
.m_axi_rid(s00_regslice_to_auto_pc_RID),
.m_axi_rlast(s00_regslice_to_auto_pc_RLAST),
.m_axi_rready(s00_regslice_to_auto_pc_RREADY),
.m_axi_rresp(s00_regslice_to_auto_pc_RRESP),
.m_axi_rvalid(s00_regslice_to_auto_pc_RVALID),
.m_axi_wdata(s00_regslice_to_auto_pc_WDATA),
.m_axi_wid(s00_regslice_to_auto_pc_WID),
.m_axi_wlast(s00_regslice_to_auto_pc_WLAST),
.m_axi_wready(s00_regslice_to_auto_pc_WREADY),
.m_axi_wstrb(s00_regslice_to_auto_pc_WSTRB),
.m_axi_wvalid(s00_regslice_to_auto_pc_WVALID),
.s_axi_araddr(s00_couplers_to_s00_regslice_ARADDR),
.s_axi_arburst(s00_couplers_to_s00_regslice_ARBURST),
.s_axi_arcache(s00_couplers_to_s00_regslice_ARCACHE),
.s_axi_arid(s00_couplers_to_s00_regslice_ARID),
.s_axi_arlen(s00_couplers_to_s00_regslice_ARLEN),
.s_axi_arlock(s00_couplers_to_s00_regslice_ARLOCK),
.s_axi_arprot(s00_couplers_to_s00_regslice_ARPROT),
.s_axi_arqos(s00_couplers_to_s00_regslice_ARQOS),
.s_axi_arready(s00_couplers_to_s00_regslice_ARREADY),
.s_axi_arsize(s00_couplers_to_s00_regslice_ARSIZE),
.s_axi_arvalid(s00_couplers_to_s00_regslice_ARVALID),
.s_axi_awaddr(s00_couplers_to_s00_regslice_AWADDR),
.s_axi_awburst(s00_couplers_to_s00_regslice_AWBURST),
.s_axi_awcache(s00_couplers_to_s00_regslice_AWCACHE),
.s_axi_awid(s00_couplers_to_s00_regslice_AWID),
.s_axi_awlen(s00_couplers_to_s00_regslice_AWLEN),
.s_axi_awlock(s00_couplers_to_s00_regslice_AWLOCK),
.s_axi_awprot(s00_couplers_to_s00_regslice_AWPROT),
.s_axi_awqos(s00_couplers_to_s00_regslice_AWQOS),
.s_axi_awready(s00_couplers_to_s00_regslice_AWREADY),
.s_axi_awsize(s00_couplers_to_s00_regslice_AWSIZE),
.s_axi_awvalid(s00_couplers_to_s00_regslice_AWVALID),
.s_axi_bid(s00_couplers_to_s00_regslice_BID),
.s_axi_bready(s00_couplers_to_s00_regslice_BREADY),
.s_axi_bresp(s00_couplers_to_s00_regslice_BRESP),
.s_axi_bvalid(s00_couplers_to_s00_regslice_BVALID),
.s_axi_rdata(s00_couplers_to_s00_regslice_RDATA),
.s_axi_rid(s00_couplers_to_s00_regslice_RID),
.s_axi_rlast(s00_couplers_to_s00_regslice_RLAST),
.s_axi_rready(s00_couplers_to_s00_regslice_RREADY),
.s_axi_rresp(s00_couplers_to_s00_regslice_RRESP),
.s_axi_rvalid(s00_couplers_to_s00_regslice_RVALID),
.s_axi_wdata(s00_couplers_to_s00_regslice_WDATA),
.s_axi_wid(s00_couplers_to_s00_regslice_WID),
.s_axi_wlast(s00_couplers_to_s00_regslice_WLAST),
.s_axi_wready(s00_couplers_to_s00_regslice_WREADY),
.s_axi_wstrb(s00_couplers_to_s00_regslice_WSTRB),
.s_axi_wvalid(s00_couplers_to_s00_regslice_WVALID));
endmodule
module s00_couplers_imp_QU0DDF
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arqos,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arregion,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awregion,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [7:0]M_AXI_arlen;
output [0:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
output [3:0]M_AXI_arqos;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [7:0]M_AXI_awlen;
output [0:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
output [3:0]M_AXI_awqos;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [63:0]M_AXI_rdata;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [63:0]M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output [7:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [7:0]S_AXI_arlen;
input [1:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [3:0]S_AXI_arregion;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [7:0]S_AXI_awlen;
input [1:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [3:0]S_AXI_awregion;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire M_ACLK_1;
wire [0:0]M_ARESETN_1;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_us_df_to_s00_couplers_ARADDR;
wire [1:0]auto_us_df_to_s00_couplers_ARBURST;
wire [3:0]auto_us_df_to_s00_couplers_ARCACHE;
wire [7:0]auto_us_df_to_s00_couplers_ARLEN;
wire [0:0]auto_us_df_to_s00_couplers_ARLOCK;
wire [2:0]auto_us_df_to_s00_couplers_ARPROT;
wire [3:0]auto_us_df_to_s00_couplers_ARQOS;
wire auto_us_df_to_s00_couplers_ARREADY;
wire [2:0]auto_us_df_to_s00_couplers_ARSIZE;
wire auto_us_df_to_s00_couplers_ARVALID;
wire [31:0]auto_us_df_to_s00_couplers_AWADDR;
wire [1:0]auto_us_df_to_s00_couplers_AWBURST;
wire [3:0]auto_us_df_to_s00_couplers_AWCACHE;
wire [7:0]auto_us_df_to_s00_couplers_AWLEN;
wire [0:0]auto_us_df_to_s00_couplers_AWLOCK;
wire [2:0]auto_us_df_to_s00_couplers_AWPROT;
wire [3:0]auto_us_df_to_s00_couplers_AWQOS;
wire auto_us_df_to_s00_couplers_AWREADY;
wire [2:0]auto_us_df_to_s00_couplers_AWSIZE;
wire auto_us_df_to_s00_couplers_AWVALID;
wire auto_us_df_to_s00_couplers_BREADY;
wire [1:0]auto_us_df_to_s00_couplers_BRESP;
wire auto_us_df_to_s00_couplers_BVALID;
wire [63:0]auto_us_df_to_s00_couplers_RDATA;
wire auto_us_df_to_s00_couplers_RLAST;
wire auto_us_df_to_s00_couplers_RREADY;
wire [1:0]auto_us_df_to_s00_couplers_RRESP;
wire auto_us_df_to_s00_couplers_RVALID;
wire [63:0]auto_us_df_to_s00_couplers_WDATA;
wire auto_us_df_to_s00_couplers_WLAST;
wire auto_us_df_to_s00_couplers_WREADY;
wire [7:0]auto_us_df_to_s00_couplers_WSTRB;
wire auto_us_df_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_s00_regslice_ARADDR;
wire [1:0]s00_couplers_to_s00_regslice_ARBURST;
wire [3:0]s00_couplers_to_s00_regslice_ARCACHE;
wire [7:0]s00_couplers_to_s00_regslice_ARLEN;
wire [1:0]s00_couplers_to_s00_regslice_ARLOCK;
wire [2:0]s00_couplers_to_s00_regslice_ARPROT;
wire [3:0]s00_couplers_to_s00_regslice_ARQOS;
wire s00_couplers_to_s00_regslice_ARREADY;
wire [3:0]s00_couplers_to_s00_regslice_ARREGION;
wire [2:0]s00_couplers_to_s00_regslice_ARSIZE;
wire s00_couplers_to_s00_regslice_ARVALID;
wire [31:0]s00_couplers_to_s00_regslice_AWADDR;
wire [1:0]s00_couplers_to_s00_regslice_AWBURST;
wire [3:0]s00_couplers_to_s00_regslice_AWCACHE;
wire [7:0]s00_couplers_to_s00_regslice_AWLEN;
wire [1:0]s00_couplers_to_s00_regslice_AWLOCK;
wire [2:0]s00_couplers_to_s00_regslice_AWPROT;
wire [3:0]s00_couplers_to_s00_regslice_AWQOS;
wire s00_couplers_to_s00_regslice_AWREADY;
wire [3:0]s00_couplers_to_s00_regslice_AWREGION;
wire [2:0]s00_couplers_to_s00_regslice_AWSIZE;
wire s00_couplers_to_s00_regslice_AWVALID;
wire s00_couplers_to_s00_regslice_BREADY;
wire [1:0]s00_couplers_to_s00_regslice_BRESP;
wire s00_couplers_to_s00_regslice_BVALID;
wire [31:0]s00_couplers_to_s00_regslice_RDATA;
wire s00_couplers_to_s00_regslice_RLAST;
wire s00_couplers_to_s00_regslice_RREADY;
wire [1:0]s00_couplers_to_s00_regslice_RRESP;
wire s00_couplers_to_s00_regslice_RVALID;
wire [31:0]s00_couplers_to_s00_regslice_WDATA;
wire s00_couplers_to_s00_regslice_WLAST;
wire s00_couplers_to_s00_regslice_WREADY;
wire [3:0]s00_couplers_to_s00_regslice_WSTRB;
wire s00_couplers_to_s00_regslice_WVALID;
wire [31:0]s00_regslice_to_auto_us_df_ARADDR;
wire [1:0]s00_regslice_to_auto_us_df_ARBURST;
wire [3:0]s00_regslice_to_auto_us_df_ARCACHE;
wire [7:0]s00_regslice_to_auto_us_df_ARLEN;
wire [0:0]s00_regslice_to_auto_us_df_ARLOCK;
wire [2:0]s00_regslice_to_auto_us_df_ARPROT;
wire [3:0]s00_regslice_to_auto_us_df_ARQOS;
wire s00_regslice_to_auto_us_df_ARREADY;
wire [3:0]s00_regslice_to_auto_us_df_ARREGION;
wire [2:0]s00_regslice_to_auto_us_df_ARSIZE;
wire s00_regslice_to_auto_us_df_ARVALID;
wire [31:0]s00_regslice_to_auto_us_df_AWADDR;
wire [1:0]s00_regslice_to_auto_us_df_AWBURST;
wire [3:0]s00_regslice_to_auto_us_df_AWCACHE;
wire [7:0]s00_regslice_to_auto_us_df_AWLEN;
wire [0:0]s00_regslice_to_auto_us_df_AWLOCK;
wire [2:0]s00_regslice_to_auto_us_df_AWPROT;
wire [3:0]s00_regslice_to_auto_us_df_AWQOS;
wire s00_regslice_to_auto_us_df_AWREADY;
wire [3:0]s00_regslice_to_auto_us_df_AWREGION;
wire [2:0]s00_regslice_to_auto_us_df_AWSIZE;
wire s00_regslice_to_auto_us_df_AWVALID;
wire s00_regslice_to_auto_us_df_BREADY;
wire [1:0]s00_regslice_to_auto_us_df_BRESP;
wire s00_regslice_to_auto_us_df_BVALID;
wire [31:0]s00_regslice_to_auto_us_df_RDATA;
wire s00_regslice_to_auto_us_df_RLAST;
wire s00_regslice_to_auto_us_df_RREADY;
wire [1:0]s00_regslice_to_auto_us_df_RRESP;
wire s00_regslice_to_auto_us_df_RVALID;
wire [31:0]s00_regslice_to_auto_us_df_WDATA;
wire s00_regslice_to_auto_us_df_WLAST;
wire s00_regslice_to_auto_us_df_WREADY;
wire [3:0]s00_regslice_to_auto_us_df_WSTRB;
wire s00_regslice_to_auto_us_df_WVALID;
assign M_ACLK_1 = M_ACLK;
assign M_ARESETN_1 = M_ARESETN[0];
assign M_AXI_araddr[31:0] = auto_us_df_to_s00_couplers_ARADDR;
assign M_AXI_arburst[1:0] = auto_us_df_to_s00_couplers_ARBURST;
assign M_AXI_arcache[3:0] = auto_us_df_to_s00_couplers_ARCACHE;
assign M_AXI_arlen[7:0] = auto_us_df_to_s00_couplers_ARLEN;
assign M_AXI_arlock[0] = auto_us_df_to_s00_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = auto_us_df_to_s00_couplers_ARPROT;
assign M_AXI_arqos[3:0] = auto_us_df_to_s00_couplers_ARQOS;
assign M_AXI_arsize[2:0] = auto_us_df_to_s00_couplers_ARSIZE;
assign M_AXI_arvalid = auto_us_df_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_us_df_to_s00_couplers_AWADDR;
assign M_AXI_awburst[1:0] = auto_us_df_to_s00_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_us_df_to_s00_couplers_AWCACHE;
assign M_AXI_awlen[7:0] = auto_us_df_to_s00_couplers_AWLEN;
assign M_AXI_awlock[0] = auto_us_df_to_s00_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_us_df_to_s00_couplers_AWPROT;
assign M_AXI_awqos[3:0] = auto_us_df_to_s00_couplers_AWQOS;
assign M_AXI_awsize[2:0] = auto_us_df_to_s00_couplers_AWSIZE;
assign M_AXI_awvalid = auto_us_df_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_us_df_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_us_df_to_s00_couplers_RREADY;
assign M_AXI_wdata[63:0] = auto_us_df_to_s00_couplers_WDATA;
assign M_AXI_wlast = auto_us_df_to_s00_couplers_WLAST;
assign M_AXI_wstrb[7:0] = auto_us_df_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_us_df_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = s00_couplers_to_s00_regslice_ARREADY;
assign S_AXI_awready = s00_couplers_to_s00_regslice_AWREADY;
assign S_AXI_bresp[1:0] = s00_couplers_to_s00_regslice_BRESP;
assign S_AXI_bvalid = s00_couplers_to_s00_regslice_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_s00_regslice_RDATA;
assign S_AXI_rlast = s00_couplers_to_s00_regslice_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_s00_regslice_RRESP;
assign S_AXI_rvalid = s00_couplers_to_s00_regslice_RVALID;
assign S_AXI_wready = s00_couplers_to_s00_regslice_WREADY;
assign auto_us_df_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_us_df_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_us_df_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_us_df_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_us_df_to_s00_couplers_RDATA = M_AXI_rdata[63:0];
assign auto_us_df_to_s00_couplers_RLAST = M_AXI_rlast;
assign auto_us_df_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_us_df_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_us_df_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_s00_regslice_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_s00_regslice_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_s00_regslice_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_s00_regslice_ARLEN = S_AXI_arlen[7:0];
assign s00_couplers_to_s00_regslice_ARLOCK = S_AXI_arlock[1:0];
assign s00_couplers_to_s00_regslice_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_s00_regslice_ARQOS = S_AXI_arqos[3:0];
assign s00_couplers_to_s00_regslice_ARREGION = S_AXI_arregion[3:0];
assign s00_couplers_to_s00_regslice_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_s00_regslice_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_s00_regslice_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_s00_regslice_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_s00_regslice_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_s00_regslice_AWLEN = S_AXI_awlen[7:0];
assign s00_couplers_to_s00_regslice_AWLOCK = S_AXI_awlock[1:0];
assign s00_couplers_to_s00_regslice_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_s00_regslice_AWQOS = S_AXI_awqos[3:0];
assign s00_couplers_to_s00_regslice_AWREGION = S_AXI_awregion[3:0];
assign s00_couplers_to_s00_regslice_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_s00_regslice_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_s00_regslice_BREADY = S_AXI_bready;
assign s00_couplers_to_s00_regslice_RREADY = S_AXI_rready;
assign s00_couplers_to_s00_regslice_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_s00_regslice_WLAST = S_AXI_wlast;
assign s00_couplers_to_s00_regslice_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_s00_regslice_WVALID = S_AXI_wvalid;
zc702_auto_us_df_0 auto_us_df
(.m_axi_araddr(auto_us_df_to_s00_couplers_ARADDR),
.m_axi_arburst(auto_us_df_to_s00_couplers_ARBURST),
.m_axi_arcache(auto_us_df_to_s00_couplers_ARCACHE),
.m_axi_arlen(auto_us_df_to_s00_couplers_ARLEN),
.m_axi_arlock(auto_us_df_to_s00_couplers_ARLOCK),
.m_axi_arprot(auto_us_df_to_s00_couplers_ARPROT),
.m_axi_arqos(auto_us_df_to_s00_couplers_ARQOS),
.m_axi_arready(auto_us_df_to_s00_couplers_ARREADY),
.m_axi_arsize(auto_us_df_to_s00_couplers_ARSIZE),
.m_axi_arvalid(auto_us_df_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_us_df_to_s00_couplers_AWADDR),
.m_axi_awburst(auto_us_df_to_s00_couplers_AWBURST),
.m_axi_awcache(auto_us_df_to_s00_couplers_AWCACHE),
.m_axi_awlen(auto_us_df_to_s00_couplers_AWLEN),
.m_axi_awlock(auto_us_df_to_s00_couplers_AWLOCK),
.m_axi_awprot(auto_us_df_to_s00_couplers_AWPROT),
.m_axi_awqos(auto_us_df_to_s00_couplers_AWQOS),
.m_axi_awready(auto_us_df_to_s00_couplers_AWREADY),
.m_axi_awsize(auto_us_df_to_s00_couplers_AWSIZE),
.m_axi_awvalid(auto_us_df_to_s00_couplers_AWVALID),
.m_axi_bready(auto_us_df_to_s00_couplers_BREADY),
.m_axi_bresp(auto_us_df_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_us_df_to_s00_couplers_BVALID),
.m_axi_rdata(auto_us_df_to_s00_couplers_RDATA),
.m_axi_rlast(auto_us_df_to_s00_couplers_RLAST),
.m_axi_rready(auto_us_df_to_s00_couplers_RREADY),
.m_axi_rresp(auto_us_df_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_us_df_to_s00_couplers_RVALID),
.m_axi_wdata(auto_us_df_to_s00_couplers_WDATA),
.m_axi_wlast(auto_us_df_to_s00_couplers_WLAST),
.m_axi_wready(auto_us_df_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_us_df_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_us_df_to_s00_couplers_WVALID),
.s_axi_aclk(S_ACLK_1),
.s_axi_araddr(s00_regslice_to_auto_us_df_ARADDR),
.s_axi_arburst(s00_regslice_to_auto_us_df_ARBURST),
.s_axi_arcache(s00_regslice_to_auto_us_df_ARCACHE),
.s_axi_aresetn(S_ARESETN_1),
.s_axi_arlen(s00_regslice_to_auto_us_df_ARLEN),
.s_axi_arlock(s00_regslice_to_auto_us_df_ARLOCK),
.s_axi_arprot(s00_regslice_to_auto_us_df_ARPROT),
.s_axi_arqos(s00_regslice_to_auto_us_df_ARQOS),
.s_axi_arready(s00_regslice_to_auto_us_df_ARREADY),
.s_axi_arregion(s00_regslice_to_auto_us_df_ARREGION),
.s_axi_arsize(s00_regslice_to_auto_us_df_ARSIZE),
.s_axi_arvalid(s00_regslice_to_auto_us_df_ARVALID),
.s_axi_awaddr(s00_regslice_to_auto_us_df_AWADDR),
.s_axi_awburst(s00_regslice_to_auto_us_df_AWBURST),
.s_axi_awcache(s00_regslice_to_auto_us_df_AWCACHE),
.s_axi_awlen(s00_regslice_to_auto_us_df_AWLEN),
.s_axi_awlock(s00_regslice_to_auto_us_df_AWLOCK),
.s_axi_awprot(s00_regslice_to_auto_us_df_AWPROT),
.s_axi_awqos(s00_regslice_to_auto_us_df_AWQOS),
.s_axi_awready(s00_regslice_to_auto_us_df_AWREADY),
.s_axi_awregion(s00_regslice_to_auto_us_df_AWREGION),
.s_axi_awsize(s00_regslice_to_auto_us_df_AWSIZE),
.s_axi_awvalid(s00_regslice_to_auto_us_df_AWVALID),
.s_axi_bready(s00_regslice_to_auto_us_df_BREADY),
.s_axi_bresp(s00_regslice_to_auto_us_df_BRESP),
.s_axi_bvalid(s00_regslice_to_auto_us_df_BVALID),
.s_axi_rdata(s00_regslice_to_auto_us_df_RDATA),
.s_axi_rlast(s00_regslice_to_auto_us_df_RLAST),
.s_axi_rready(s00_regslice_to_auto_us_df_RREADY),
.s_axi_rresp(s00_regslice_to_auto_us_df_RRESP),
.s_axi_rvalid(s00_regslice_to_auto_us_df_RVALID),
.s_axi_wdata(s00_regslice_to_auto_us_df_WDATA),
.s_axi_wlast(s00_regslice_to_auto_us_df_WLAST),
.s_axi_wready(s00_regslice_to_auto_us_df_WREADY),
.s_axi_wstrb(s00_regslice_to_auto_us_df_WSTRB),
.s_axi_wvalid(s00_regslice_to_auto_us_df_WVALID));
zc702_s00_regslice_1 s00_regslice
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(s00_regslice_to_auto_us_df_ARADDR),
.m_axi_arburst(s00_regslice_to_auto_us_df_ARBURST),
.m_axi_arcache(s00_regslice_to_auto_us_df_ARCACHE),
.m_axi_arlen(s00_regslice_to_auto_us_df_ARLEN),
.m_axi_arlock(s00_regslice_to_auto_us_df_ARLOCK),
.m_axi_arprot(s00_regslice_to_auto_us_df_ARPROT),
.m_axi_arqos(s00_regslice_to_auto_us_df_ARQOS),
.m_axi_arready(s00_regslice_to_auto_us_df_ARREADY),
.m_axi_arregion(s00_regslice_to_auto_us_df_ARREGION),
.m_axi_arsize(s00_regslice_to_auto_us_df_ARSIZE),
.m_axi_arvalid(s00_regslice_to_auto_us_df_ARVALID),
.m_axi_awaddr(s00_regslice_to_auto_us_df_AWADDR),
.m_axi_awburst(s00_regslice_to_auto_us_df_AWBURST),
.m_axi_awcache(s00_regslice_to_auto_us_df_AWCACHE),
.m_axi_awlen(s00_regslice_to_auto_us_df_AWLEN),
.m_axi_awlock(s00_regslice_to_auto_us_df_AWLOCK),
.m_axi_awprot(s00_regslice_to_auto_us_df_AWPROT),
.m_axi_awqos(s00_regslice_to_auto_us_df_AWQOS),
.m_axi_awready(s00_regslice_to_auto_us_df_AWREADY),
.m_axi_awregion(s00_regslice_to_auto_us_df_AWREGION),
.m_axi_awsize(s00_regslice_to_auto_us_df_AWSIZE),
.m_axi_awvalid(s00_regslice_to_auto_us_df_AWVALID),
.m_axi_bready(s00_regslice_to_auto_us_df_BREADY),
.m_axi_bresp(s00_regslice_to_auto_us_df_BRESP),
.m_axi_bvalid(s00_regslice_to_auto_us_df_BVALID),
.m_axi_rdata(s00_regslice_to_auto_us_df_RDATA),
.m_axi_rlast(s00_regslice_to_auto_us_df_RLAST),
.m_axi_rready(s00_regslice_to_auto_us_df_RREADY),
.m_axi_rresp(s00_regslice_to_auto_us_df_RRESP),
.m_axi_rvalid(s00_regslice_to_auto_us_df_RVALID),
.m_axi_wdata(s00_regslice_to_auto_us_df_WDATA),
.m_axi_wlast(s00_regslice_to_auto_us_df_WLAST),
.m_axi_wready(s00_regslice_to_auto_us_df_WREADY),
.m_axi_wstrb(s00_regslice_to_auto_us_df_WSTRB),
.m_axi_wvalid(s00_regslice_to_auto_us_df_WVALID),
.s_axi_araddr(s00_couplers_to_s00_regslice_ARADDR),
.s_axi_arburst(s00_couplers_to_s00_regslice_ARBURST),
.s_axi_arcache(s00_couplers_to_s00_regslice_ARCACHE),
.s_axi_arlen(s00_couplers_to_s00_regslice_ARLEN),
.s_axi_arlock(s00_couplers_to_s00_regslice_ARLOCK[0]),
.s_axi_arprot(s00_couplers_to_s00_regslice_ARPROT),
.s_axi_arqos(s00_couplers_to_s00_regslice_ARQOS),
.s_axi_arready(s00_couplers_to_s00_regslice_ARREADY),
.s_axi_arregion(s00_couplers_to_s00_regslice_ARREGION),
.s_axi_arsize(s00_couplers_to_s00_regslice_ARSIZE),
.s_axi_arvalid(s00_couplers_to_s00_regslice_ARVALID),
.s_axi_awaddr(s00_couplers_to_s00_regslice_AWADDR),
.s_axi_awburst(s00_couplers_to_s00_regslice_AWBURST),
.s_axi_awcache(s00_couplers_to_s00_regslice_AWCACHE),
.s_axi_awlen(s00_couplers_to_s00_regslice_AWLEN),
.s_axi_awlock(s00_couplers_to_s00_regslice_AWLOCK[0]),
.s_axi_awprot(s00_couplers_to_s00_regslice_AWPROT),
.s_axi_awqos(s00_couplers_to_s00_regslice_AWQOS),
.s_axi_awready(s00_couplers_to_s00_regslice_AWREADY),
.s_axi_awregion(s00_couplers_to_s00_regslice_AWREGION),
.s_axi_awsize(s00_couplers_to_s00_regslice_AWSIZE),
.s_axi_awvalid(s00_couplers_to_s00_regslice_AWVALID),
.s_axi_bready(s00_couplers_to_s00_regslice_BREADY),
.s_axi_bresp(s00_couplers_to_s00_regslice_BRESP),
.s_axi_bvalid(s00_couplers_to_s00_regslice_BVALID),
.s_axi_rdata(s00_couplers_to_s00_regslice_RDATA),
.s_axi_rlast(s00_couplers_to_s00_regslice_RLAST),
.s_axi_rready(s00_couplers_to_s00_regslice_RREADY),
.s_axi_rresp(s00_couplers_to_s00_regslice_RRESP),
.s_axi_rvalid(s00_couplers_to_s00_regslice_RVALID),
.s_axi_wdata(s00_couplers_to_s00_regslice_WDATA),
.s_axi_wlast(s00_couplers_to_s00_regslice_WLAST),
.s_axi_wready(s00_couplers_to_s00_regslice_WREADY),
.s_axi_wstrb(s00_couplers_to_s00_regslice_WSTRB),
.s_axi_wvalid(s00_couplers_to_s00_regslice_WVALID));
endmodule
module s01_couplers_imp_1OALJYZ
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arqos,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arregion,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awregion,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [7:0]M_AXI_arlen;
output [0:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
output [3:0]M_AXI_arqos;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [7:0]M_AXI_awlen;
output [0:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
output [3:0]M_AXI_awqos;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [63:0]M_AXI_rdata;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [63:0]M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output [7:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [7:0]S_AXI_arlen;
input [1:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [3:0]S_AXI_arregion;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [7:0]S_AXI_awlen;
input [1:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [3:0]S_AXI_awregion;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire M_ACLK_1;
wire [0:0]M_ARESETN_1;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_us_df_to_s01_couplers_ARADDR;
wire [1:0]auto_us_df_to_s01_couplers_ARBURST;
wire [3:0]auto_us_df_to_s01_couplers_ARCACHE;
wire [7:0]auto_us_df_to_s01_couplers_ARLEN;
wire [0:0]auto_us_df_to_s01_couplers_ARLOCK;
wire [2:0]auto_us_df_to_s01_couplers_ARPROT;
wire [3:0]auto_us_df_to_s01_couplers_ARQOS;
wire auto_us_df_to_s01_couplers_ARREADY;
wire [2:0]auto_us_df_to_s01_couplers_ARSIZE;
wire auto_us_df_to_s01_couplers_ARVALID;
wire [31:0]auto_us_df_to_s01_couplers_AWADDR;
wire [1:0]auto_us_df_to_s01_couplers_AWBURST;
wire [3:0]auto_us_df_to_s01_couplers_AWCACHE;
wire [7:0]auto_us_df_to_s01_couplers_AWLEN;
wire [0:0]auto_us_df_to_s01_couplers_AWLOCK;
wire [2:0]auto_us_df_to_s01_couplers_AWPROT;
wire [3:0]auto_us_df_to_s01_couplers_AWQOS;
wire auto_us_df_to_s01_couplers_AWREADY;
wire [2:0]auto_us_df_to_s01_couplers_AWSIZE;
wire auto_us_df_to_s01_couplers_AWVALID;
wire auto_us_df_to_s01_couplers_BREADY;
wire [1:0]auto_us_df_to_s01_couplers_BRESP;
wire auto_us_df_to_s01_couplers_BVALID;
wire [63:0]auto_us_df_to_s01_couplers_RDATA;
wire auto_us_df_to_s01_couplers_RLAST;
wire auto_us_df_to_s01_couplers_RREADY;
wire [1:0]auto_us_df_to_s01_couplers_RRESP;
wire auto_us_df_to_s01_couplers_RVALID;
wire [63:0]auto_us_df_to_s01_couplers_WDATA;
wire auto_us_df_to_s01_couplers_WLAST;
wire auto_us_df_to_s01_couplers_WREADY;
wire [7:0]auto_us_df_to_s01_couplers_WSTRB;
wire auto_us_df_to_s01_couplers_WVALID;
wire [31:0]s01_couplers_to_s01_regslice_ARADDR;
wire [1:0]s01_couplers_to_s01_regslice_ARBURST;
wire [3:0]s01_couplers_to_s01_regslice_ARCACHE;
wire [7:0]s01_couplers_to_s01_regslice_ARLEN;
wire [1:0]s01_couplers_to_s01_regslice_ARLOCK;
wire [2:0]s01_couplers_to_s01_regslice_ARPROT;
wire [3:0]s01_couplers_to_s01_regslice_ARQOS;
wire s01_couplers_to_s01_regslice_ARREADY;
wire [3:0]s01_couplers_to_s01_regslice_ARREGION;
wire [2:0]s01_couplers_to_s01_regslice_ARSIZE;
wire s01_couplers_to_s01_regslice_ARVALID;
wire [31:0]s01_couplers_to_s01_regslice_AWADDR;
wire [1:0]s01_couplers_to_s01_regslice_AWBURST;
wire [3:0]s01_couplers_to_s01_regslice_AWCACHE;
wire [7:0]s01_couplers_to_s01_regslice_AWLEN;
wire [1:0]s01_couplers_to_s01_regslice_AWLOCK;
wire [2:0]s01_couplers_to_s01_regslice_AWPROT;
wire [3:0]s01_couplers_to_s01_regslice_AWQOS;
wire s01_couplers_to_s01_regslice_AWREADY;
wire [3:0]s01_couplers_to_s01_regslice_AWREGION;
wire [2:0]s01_couplers_to_s01_regslice_AWSIZE;
wire s01_couplers_to_s01_regslice_AWVALID;
wire s01_couplers_to_s01_regslice_BREADY;
wire [1:0]s01_couplers_to_s01_regslice_BRESP;
wire s01_couplers_to_s01_regslice_BVALID;
wire [31:0]s01_couplers_to_s01_regslice_RDATA;
wire s01_couplers_to_s01_regslice_RLAST;
wire s01_couplers_to_s01_regslice_RREADY;
wire [1:0]s01_couplers_to_s01_regslice_RRESP;
wire s01_couplers_to_s01_regslice_RVALID;
wire [31:0]s01_couplers_to_s01_regslice_WDATA;
wire s01_couplers_to_s01_regslice_WLAST;
wire s01_couplers_to_s01_regslice_WREADY;
wire [3:0]s01_couplers_to_s01_regslice_WSTRB;
wire s01_couplers_to_s01_regslice_WVALID;
wire [31:0]s01_regslice_to_auto_us_df_ARADDR;
wire [1:0]s01_regslice_to_auto_us_df_ARBURST;
wire [3:0]s01_regslice_to_auto_us_df_ARCACHE;
wire [7:0]s01_regslice_to_auto_us_df_ARLEN;
wire [0:0]s01_regslice_to_auto_us_df_ARLOCK;
wire [2:0]s01_regslice_to_auto_us_df_ARPROT;
wire [3:0]s01_regslice_to_auto_us_df_ARQOS;
wire s01_regslice_to_auto_us_df_ARREADY;
wire [3:0]s01_regslice_to_auto_us_df_ARREGION;
wire [2:0]s01_regslice_to_auto_us_df_ARSIZE;
wire s01_regslice_to_auto_us_df_ARVALID;
wire [31:0]s01_regslice_to_auto_us_df_AWADDR;
wire [1:0]s01_regslice_to_auto_us_df_AWBURST;
wire [3:0]s01_regslice_to_auto_us_df_AWCACHE;
wire [7:0]s01_regslice_to_auto_us_df_AWLEN;
wire [0:0]s01_regslice_to_auto_us_df_AWLOCK;
wire [2:0]s01_regslice_to_auto_us_df_AWPROT;
wire [3:0]s01_regslice_to_auto_us_df_AWQOS;
wire s01_regslice_to_auto_us_df_AWREADY;
wire [3:0]s01_regslice_to_auto_us_df_AWREGION;
wire [2:0]s01_regslice_to_auto_us_df_AWSIZE;
wire s01_regslice_to_auto_us_df_AWVALID;
wire s01_regslice_to_auto_us_df_BREADY;
wire [1:0]s01_regslice_to_auto_us_df_BRESP;
wire s01_regslice_to_auto_us_df_BVALID;
wire [31:0]s01_regslice_to_auto_us_df_RDATA;
wire s01_regslice_to_auto_us_df_RLAST;
wire s01_regslice_to_auto_us_df_RREADY;
wire [1:0]s01_regslice_to_auto_us_df_RRESP;
wire s01_regslice_to_auto_us_df_RVALID;
wire [31:0]s01_regslice_to_auto_us_df_WDATA;
wire s01_regslice_to_auto_us_df_WLAST;
wire s01_regslice_to_auto_us_df_WREADY;
wire [3:0]s01_regslice_to_auto_us_df_WSTRB;
wire s01_regslice_to_auto_us_df_WVALID;
assign M_ACLK_1 = M_ACLK;
assign M_ARESETN_1 = M_ARESETN[0];
assign M_AXI_araddr[31:0] = auto_us_df_to_s01_couplers_ARADDR;
assign M_AXI_arburst[1:0] = auto_us_df_to_s01_couplers_ARBURST;
assign M_AXI_arcache[3:0] = auto_us_df_to_s01_couplers_ARCACHE;
assign M_AXI_arlen[7:0] = auto_us_df_to_s01_couplers_ARLEN;
assign M_AXI_arlock[0] = auto_us_df_to_s01_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = auto_us_df_to_s01_couplers_ARPROT;
assign M_AXI_arqos[3:0] = auto_us_df_to_s01_couplers_ARQOS;
assign M_AXI_arsize[2:0] = auto_us_df_to_s01_couplers_ARSIZE;
assign M_AXI_arvalid = auto_us_df_to_s01_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_us_df_to_s01_couplers_AWADDR;
assign M_AXI_awburst[1:0] = auto_us_df_to_s01_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_us_df_to_s01_couplers_AWCACHE;
assign M_AXI_awlen[7:0] = auto_us_df_to_s01_couplers_AWLEN;
assign M_AXI_awlock[0] = auto_us_df_to_s01_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_us_df_to_s01_couplers_AWPROT;
assign M_AXI_awqos[3:0] = auto_us_df_to_s01_couplers_AWQOS;
assign M_AXI_awsize[2:0] = auto_us_df_to_s01_couplers_AWSIZE;
assign M_AXI_awvalid = auto_us_df_to_s01_couplers_AWVALID;
assign M_AXI_bready = auto_us_df_to_s01_couplers_BREADY;
assign M_AXI_rready = auto_us_df_to_s01_couplers_RREADY;
assign M_AXI_wdata[63:0] = auto_us_df_to_s01_couplers_WDATA;
assign M_AXI_wlast = auto_us_df_to_s01_couplers_WLAST;
assign M_AXI_wstrb[7:0] = auto_us_df_to_s01_couplers_WSTRB;
assign M_AXI_wvalid = auto_us_df_to_s01_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = s01_couplers_to_s01_regslice_ARREADY;
assign S_AXI_awready = s01_couplers_to_s01_regslice_AWREADY;
assign S_AXI_bresp[1:0] = s01_couplers_to_s01_regslice_BRESP;
assign S_AXI_bvalid = s01_couplers_to_s01_regslice_BVALID;
assign S_AXI_rdata[31:0] = s01_couplers_to_s01_regslice_RDATA;
assign S_AXI_rlast = s01_couplers_to_s01_regslice_RLAST;
assign S_AXI_rresp[1:0] = s01_couplers_to_s01_regslice_RRESP;
assign S_AXI_rvalid = s01_couplers_to_s01_regslice_RVALID;
assign S_AXI_wready = s01_couplers_to_s01_regslice_WREADY;
assign auto_us_df_to_s01_couplers_ARREADY = M_AXI_arready;
assign auto_us_df_to_s01_couplers_AWREADY = M_AXI_awready;
assign auto_us_df_to_s01_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_us_df_to_s01_couplers_BVALID = M_AXI_bvalid;
assign auto_us_df_to_s01_couplers_RDATA = M_AXI_rdata[63:0];
assign auto_us_df_to_s01_couplers_RLAST = M_AXI_rlast;
assign auto_us_df_to_s01_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_us_df_to_s01_couplers_RVALID = M_AXI_rvalid;
assign auto_us_df_to_s01_couplers_WREADY = M_AXI_wready;
assign s01_couplers_to_s01_regslice_ARADDR = S_AXI_araddr[31:0];
assign s01_couplers_to_s01_regslice_ARBURST = S_AXI_arburst[1:0];
assign s01_couplers_to_s01_regslice_ARCACHE = S_AXI_arcache[3:0];
assign s01_couplers_to_s01_regslice_ARLEN = S_AXI_arlen[7:0];
assign s01_couplers_to_s01_regslice_ARLOCK = S_AXI_arlock[1:0];
assign s01_couplers_to_s01_regslice_ARPROT = S_AXI_arprot[2:0];
assign s01_couplers_to_s01_regslice_ARQOS = S_AXI_arqos[3:0];
assign s01_couplers_to_s01_regslice_ARREGION = S_AXI_arregion[3:0];
assign s01_couplers_to_s01_regslice_ARSIZE = S_AXI_arsize[2:0];
assign s01_couplers_to_s01_regslice_ARVALID = S_AXI_arvalid;
assign s01_couplers_to_s01_regslice_AWADDR = S_AXI_awaddr[31:0];
assign s01_couplers_to_s01_regslice_AWBURST = S_AXI_awburst[1:0];
assign s01_couplers_to_s01_regslice_AWCACHE = S_AXI_awcache[3:0];
assign s01_couplers_to_s01_regslice_AWLEN = S_AXI_awlen[7:0];
assign s01_couplers_to_s01_regslice_AWLOCK = S_AXI_awlock[1:0];
assign s01_couplers_to_s01_regslice_AWPROT = S_AXI_awprot[2:0];
assign s01_couplers_to_s01_regslice_AWQOS = S_AXI_awqos[3:0];
assign s01_couplers_to_s01_regslice_AWREGION = S_AXI_awregion[3:0];
assign s01_couplers_to_s01_regslice_AWSIZE = S_AXI_awsize[2:0];
assign s01_couplers_to_s01_regslice_AWVALID = S_AXI_awvalid;
assign s01_couplers_to_s01_regslice_BREADY = S_AXI_bready;
assign s01_couplers_to_s01_regslice_RREADY = S_AXI_rready;
assign s01_couplers_to_s01_regslice_WDATA = S_AXI_wdata[31:0];
assign s01_couplers_to_s01_regslice_WLAST = S_AXI_wlast;
assign s01_couplers_to_s01_regslice_WSTRB = S_AXI_wstrb[3:0];
assign s01_couplers_to_s01_regslice_WVALID = S_AXI_wvalid;
zc702_auto_us_df_1 auto_us_df
(.m_axi_araddr(auto_us_df_to_s01_couplers_ARADDR),
.m_axi_arburst(auto_us_df_to_s01_couplers_ARBURST),
.m_axi_arcache(auto_us_df_to_s01_couplers_ARCACHE),
.m_axi_arlen(auto_us_df_to_s01_couplers_ARLEN),
.m_axi_arlock(auto_us_df_to_s01_couplers_ARLOCK),
.m_axi_arprot(auto_us_df_to_s01_couplers_ARPROT),
.m_axi_arqos(auto_us_df_to_s01_couplers_ARQOS),
.m_axi_arready(auto_us_df_to_s01_couplers_ARREADY),
.m_axi_arsize(auto_us_df_to_s01_couplers_ARSIZE),
.m_axi_arvalid(auto_us_df_to_s01_couplers_ARVALID),
.m_axi_awaddr(auto_us_df_to_s01_couplers_AWADDR),
.m_axi_awburst(auto_us_df_to_s01_couplers_AWBURST),
.m_axi_awcache(auto_us_df_to_s01_couplers_AWCACHE),
.m_axi_awlen(auto_us_df_to_s01_couplers_AWLEN),
.m_axi_awlock(auto_us_df_to_s01_couplers_AWLOCK),
.m_axi_awprot(auto_us_df_to_s01_couplers_AWPROT),
.m_axi_awqos(auto_us_df_to_s01_couplers_AWQOS),
.m_axi_awready(auto_us_df_to_s01_couplers_AWREADY),
.m_axi_awsize(auto_us_df_to_s01_couplers_AWSIZE),
.m_axi_awvalid(auto_us_df_to_s01_couplers_AWVALID),
.m_axi_bready(auto_us_df_to_s01_couplers_BREADY),
.m_axi_bresp(auto_us_df_to_s01_couplers_BRESP),
.m_axi_bvalid(auto_us_df_to_s01_couplers_BVALID),
.m_axi_rdata(auto_us_df_to_s01_couplers_RDATA),
.m_axi_rlast(auto_us_df_to_s01_couplers_RLAST),
.m_axi_rready(auto_us_df_to_s01_couplers_RREADY),
.m_axi_rresp(auto_us_df_to_s01_couplers_RRESP),
.m_axi_rvalid(auto_us_df_to_s01_couplers_RVALID),
.m_axi_wdata(auto_us_df_to_s01_couplers_WDATA),
.m_axi_wlast(auto_us_df_to_s01_couplers_WLAST),
.m_axi_wready(auto_us_df_to_s01_couplers_WREADY),
.m_axi_wstrb(auto_us_df_to_s01_couplers_WSTRB),
.m_axi_wvalid(auto_us_df_to_s01_couplers_WVALID),
.s_axi_aclk(S_ACLK_1),
.s_axi_araddr(s01_regslice_to_auto_us_df_ARADDR),
.s_axi_arburst(s01_regslice_to_auto_us_df_ARBURST),
.s_axi_arcache(s01_regslice_to_auto_us_df_ARCACHE),
.s_axi_aresetn(S_ARESETN_1),
.s_axi_arlen(s01_regslice_to_auto_us_df_ARLEN),
.s_axi_arlock(s01_regslice_to_auto_us_df_ARLOCK),
.s_axi_arprot(s01_regslice_to_auto_us_df_ARPROT),
.s_axi_arqos(s01_regslice_to_auto_us_df_ARQOS),
.s_axi_arready(s01_regslice_to_auto_us_df_ARREADY),
.s_axi_arregion(s01_regslice_to_auto_us_df_ARREGION),
.s_axi_arsize(s01_regslice_to_auto_us_df_ARSIZE),
.s_axi_arvalid(s01_regslice_to_auto_us_df_ARVALID),
.s_axi_awaddr(s01_regslice_to_auto_us_df_AWADDR),
.s_axi_awburst(s01_regslice_to_auto_us_df_AWBURST),
.s_axi_awcache(s01_regslice_to_auto_us_df_AWCACHE),
.s_axi_awlen(s01_regslice_to_auto_us_df_AWLEN),
.s_axi_awlock(s01_regslice_to_auto_us_df_AWLOCK),
.s_axi_awprot(s01_regslice_to_auto_us_df_AWPROT),
.s_axi_awqos(s01_regslice_to_auto_us_df_AWQOS),
.s_axi_awready(s01_regslice_to_auto_us_df_AWREADY),
.s_axi_awregion(s01_regslice_to_auto_us_df_AWREGION),
.s_axi_awsize(s01_regslice_to_auto_us_df_AWSIZE),
.s_axi_awvalid(s01_regslice_to_auto_us_df_AWVALID),
.s_axi_bready(s01_regslice_to_auto_us_df_BREADY),
.s_axi_bresp(s01_regslice_to_auto_us_df_BRESP),
.s_axi_bvalid(s01_regslice_to_auto_us_df_BVALID),
.s_axi_rdata(s01_regslice_to_auto_us_df_RDATA),
.s_axi_rlast(s01_regslice_to_auto_us_df_RLAST),
.s_axi_rready(s01_regslice_to_auto_us_df_RREADY),
.s_axi_rresp(s01_regslice_to_auto_us_df_RRESP),
.s_axi_rvalid(s01_regslice_to_auto_us_df_RVALID),
.s_axi_wdata(s01_regslice_to_auto_us_df_WDATA),
.s_axi_wlast(s01_regslice_to_auto_us_df_WLAST),
.s_axi_wready(s01_regslice_to_auto_us_df_WREADY),
.s_axi_wstrb(s01_regslice_to_auto_us_df_WSTRB),
.s_axi_wvalid(s01_regslice_to_auto_us_df_WVALID));
zc702_s01_regslice_0 s01_regslice
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(s01_regslice_to_auto_us_df_ARADDR),
.m_axi_arburst(s01_regslice_to_auto_us_df_ARBURST),
.m_axi_arcache(s01_regslice_to_auto_us_df_ARCACHE),
.m_axi_arlen(s01_regslice_to_auto_us_df_ARLEN),
.m_axi_arlock(s01_regslice_to_auto_us_df_ARLOCK),
.m_axi_arprot(s01_regslice_to_auto_us_df_ARPROT),
.m_axi_arqos(s01_regslice_to_auto_us_df_ARQOS),
.m_axi_arready(s01_regslice_to_auto_us_df_ARREADY),
.m_axi_arregion(s01_regslice_to_auto_us_df_ARREGION),
.m_axi_arsize(s01_regslice_to_auto_us_df_ARSIZE),
.m_axi_arvalid(s01_regslice_to_auto_us_df_ARVALID),
.m_axi_awaddr(s01_regslice_to_auto_us_df_AWADDR),
.m_axi_awburst(s01_regslice_to_auto_us_df_AWBURST),
.m_axi_awcache(s01_regslice_to_auto_us_df_AWCACHE),
.m_axi_awlen(s01_regslice_to_auto_us_df_AWLEN),
.m_axi_awlock(s01_regslice_to_auto_us_df_AWLOCK),
.m_axi_awprot(s01_regslice_to_auto_us_df_AWPROT),
.m_axi_awqos(s01_regslice_to_auto_us_df_AWQOS),
.m_axi_awready(s01_regslice_to_auto_us_df_AWREADY),
.m_axi_awregion(s01_regslice_to_auto_us_df_AWREGION),
.m_axi_awsize(s01_regslice_to_auto_us_df_AWSIZE),
.m_axi_awvalid(s01_regslice_to_auto_us_df_AWVALID),
.m_axi_bready(s01_regslice_to_auto_us_df_BREADY),
.m_axi_bresp(s01_regslice_to_auto_us_df_BRESP),
.m_axi_bvalid(s01_regslice_to_auto_us_df_BVALID),
.m_axi_rdata(s01_regslice_to_auto_us_df_RDATA),
.m_axi_rlast(s01_regslice_to_auto_us_df_RLAST),
.m_axi_rready(s01_regslice_to_auto_us_df_RREADY),
.m_axi_rresp(s01_regslice_to_auto_us_df_RRESP),
.m_axi_rvalid(s01_regslice_to_auto_us_df_RVALID),
.m_axi_wdata(s01_regslice_to_auto_us_df_WDATA),
.m_axi_wlast(s01_regslice_to_auto_us_df_WLAST),
.m_axi_wready(s01_regslice_to_auto_us_df_WREADY),
.m_axi_wstrb(s01_regslice_to_auto_us_df_WSTRB),
.m_axi_wvalid(s01_regslice_to_auto_us_df_WVALID),
.s_axi_araddr(s01_couplers_to_s01_regslice_ARADDR),
.s_axi_arburst(s01_couplers_to_s01_regslice_ARBURST),
.s_axi_arcache(s01_couplers_to_s01_regslice_ARCACHE),
.s_axi_arlen(s01_couplers_to_s01_regslice_ARLEN),
.s_axi_arlock(s01_couplers_to_s01_regslice_ARLOCK[0]),
.s_axi_arprot(s01_couplers_to_s01_regslice_ARPROT),
.s_axi_arqos(s01_couplers_to_s01_regslice_ARQOS),
.s_axi_arready(s01_couplers_to_s01_regslice_ARREADY),
.s_axi_arregion(s01_couplers_to_s01_regslice_ARREGION),
.s_axi_arsize(s01_couplers_to_s01_regslice_ARSIZE),
.s_axi_arvalid(s01_couplers_to_s01_regslice_ARVALID),
.s_axi_awaddr(s01_couplers_to_s01_regslice_AWADDR),
.s_axi_awburst(s01_couplers_to_s01_regslice_AWBURST),
.s_axi_awcache(s01_couplers_to_s01_regslice_AWCACHE),
.s_axi_awlen(s01_couplers_to_s01_regslice_AWLEN),
.s_axi_awlock(s01_couplers_to_s01_regslice_AWLOCK[0]),
.s_axi_awprot(s01_couplers_to_s01_regslice_AWPROT),
.s_axi_awqos(s01_couplers_to_s01_regslice_AWQOS),
.s_axi_awready(s01_couplers_to_s01_regslice_AWREADY),
.s_axi_awregion(s01_couplers_to_s01_regslice_AWREGION),
.s_axi_awsize(s01_couplers_to_s01_regslice_AWSIZE),
.s_axi_awvalid(s01_couplers_to_s01_regslice_AWVALID),
.s_axi_bready(s01_couplers_to_s01_regslice_BREADY),
.s_axi_bresp(s01_couplers_to_s01_regslice_BRESP),
.s_axi_bvalid(s01_couplers_to_s01_regslice_BVALID),
.s_axi_rdata(s01_couplers_to_s01_regslice_RDATA),
.s_axi_rlast(s01_couplers_to_s01_regslice_RLAST),
.s_axi_rready(s01_couplers_to_s01_regslice_RREADY),
.s_axi_rresp(s01_couplers_to_s01_regslice_RRESP),
.s_axi_rvalid(s01_couplers_to_s01_regslice_RVALID),
.s_axi_wdata(s01_couplers_to_s01_regslice_WDATA),
.s_axi_wlast(s01_couplers_to_s01_regslice_WLAST),
.s_axi_wready(s01_couplers_to_s01_regslice_WREADY),
.s_axi_wstrb(s01_couplers_to_s01_regslice_WSTRB),
.s_axi_wvalid(s01_couplers_to_s01_regslice_WVALID));
endmodule
(* CORE_GENERATION_INFO = "zc702,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=zc702,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=35,numReposBlks=27,numNonXlnxBlks=0,numHierBlks=8,maxHierDepth=0,synth_mode=Global}" *) (* HW_HANDOFF = "zc702.hwdef" *)
module zc702
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire [3:0]acp_axcache_0xF_dout;
wire [12:0]axi_ic_ps7_M_AXI_GP0_M00_AXI_ARADDR;
wire axi_ic_ps7_M_AXI_GP0_M00_AXI_ARREADY;
wire axi_ic_ps7_M_AXI_GP0_M00_AXI_ARVALID;
wire [12:0]axi_ic_ps7_M_AXI_GP0_M00_AXI_AWADDR;
wire axi_ic_ps7_M_AXI_GP0_M00_AXI_AWREADY;
wire axi_ic_ps7_M_AXI_GP0_M00_AXI_AWVALID;
wire axi_ic_ps7_M_AXI_GP0_M00_AXI_BREADY;
wire [1:0]axi_ic_ps7_M_AXI_GP0_M00_AXI_BRESP;
wire axi_ic_ps7_M_AXI_GP0_M00_AXI_BVALID;
wire [31:0]axi_ic_ps7_M_AXI_GP0_M00_AXI_RDATA;
wire axi_ic_ps7_M_AXI_GP0_M00_AXI_RREADY;
wire [1:0]axi_ic_ps7_M_AXI_GP0_M00_AXI_RRESP;
wire axi_ic_ps7_M_AXI_GP0_M00_AXI_RVALID;
wire [31:0]axi_ic_ps7_M_AXI_GP0_M00_AXI_WDATA;
wire axi_ic_ps7_M_AXI_GP0_M00_AXI_WREADY;
wire [3:0]axi_ic_ps7_M_AXI_GP0_M00_AXI_WSTRB;
wire axi_ic_ps7_M_AXI_GP0_M00_AXI_WVALID;
wire [12:0]axi_ic_ps7_M_AXI_GP0_M01_AXI_ARADDR;
wire axi_ic_ps7_M_AXI_GP0_M01_AXI_ARREADY;
wire axi_ic_ps7_M_AXI_GP0_M01_AXI_ARVALID;
wire [12:0]axi_ic_ps7_M_AXI_GP0_M01_AXI_AWADDR;
wire axi_ic_ps7_M_AXI_GP0_M01_AXI_AWREADY;
wire axi_ic_ps7_M_AXI_GP0_M01_AXI_AWVALID;
wire axi_ic_ps7_M_AXI_GP0_M01_AXI_BREADY;
wire [1:0]axi_ic_ps7_M_AXI_GP0_M01_AXI_BRESP;
wire axi_ic_ps7_M_AXI_GP0_M01_AXI_BVALID;
wire [31:0]axi_ic_ps7_M_AXI_GP0_M01_AXI_RDATA;
wire axi_ic_ps7_M_AXI_GP0_M01_AXI_RREADY;
wire [1:0]axi_ic_ps7_M_AXI_GP0_M01_AXI_RRESP;
wire axi_ic_ps7_M_AXI_GP0_M01_AXI_RVALID;
wire [31:0]axi_ic_ps7_M_AXI_GP0_M01_AXI_WDATA;
wire axi_ic_ps7_M_AXI_GP0_M01_AXI_WREADY;
wire [3:0]axi_ic_ps7_M_AXI_GP0_M01_AXI_WSTRB;
wire axi_ic_ps7_M_AXI_GP0_M01_AXI_WVALID;
wire [31:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_ARADDR;
wire [1:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_ARBURST;
wire [3:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_ARCACHE;
wire [0:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_ARID;
wire [3:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_ARLEN;
wire [1:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_ARLOCK;
wire [2:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_ARPROT;
wire [3:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_ARQOS;
wire axi_ic_ps7_S_AXI_ACP_M00_AXI_ARREADY;
wire [2:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_ARSIZE;
wire axi_ic_ps7_S_AXI_ACP_M00_AXI_ARVALID;
wire [31:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_AWADDR;
wire [1:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_AWBURST;
wire [3:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_AWCACHE;
wire [0:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_AWID;
wire [3:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_AWLEN;
wire [1:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_AWLOCK;
wire [2:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_AWPROT;
wire [3:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_AWQOS;
wire axi_ic_ps7_S_AXI_ACP_M00_AXI_AWREADY;
wire [2:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_AWSIZE;
wire axi_ic_ps7_S_AXI_ACP_M00_AXI_AWVALID;
wire [2:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_BID;
wire axi_ic_ps7_S_AXI_ACP_M00_AXI_BREADY;
wire [1:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_BRESP;
wire axi_ic_ps7_S_AXI_ACP_M00_AXI_BVALID;
wire [63:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_RDATA;
wire [2:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_RID;
wire axi_ic_ps7_S_AXI_ACP_M00_AXI_RLAST;
wire axi_ic_ps7_S_AXI_ACP_M00_AXI_RREADY;
wire [1:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_RRESP;
wire axi_ic_ps7_S_AXI_ACP_M00_AXI_RVALID;
wire [63:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_WDATA;
wire [0:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_WID;
wire axi_ic_ps7_S_AXI_ACP_M00_AXI_WLAST;
wire axi_ic_ps7_S_AXI_ACP_M00_AXI_WREADY;
wire [7:0]axi_ic_ps7_S_AXI_ACP_M00_AXI_WSTRB;
wire axi_ic_ps7_S_AXI_ACP_M00_AXI_WVALID;
wire clkid0;
wire clkid1;
wire clkid2;
wire clkid3;
wire [31:0]get_0_ap_return;
wire get_0_if_AP_CTRL_done;
wire get_0_if_AP_CTRL_idle;
wire get_0_if_AP_CTRL_ready;
wire get_0_if_AP_CTRL_start;
wire [31:0]get_0_if_ap_iscalar_0_dout;
wire [31:0]get_0_if_ap_iscalar_1_dout;
wire get_0_if_aresetn;
wire [31:0]get_0_m_axi_gmem_ARADDR;
wire [1:0]get_0_m_axi_gmem_ARBURST;
wire [7:0]get_0_m_axi_gmem_ARLEN;
wire [1:0]get_0_m_axi_gmem_ARLOCK;
wire [2:0]get_0_m_axi_gmem_ARPROT;
wire [3:0]get_0_m_axi_gmem_ARQOS;
wire get_0_m_axi_gmem_ARREADY;
wire [3:0]get_0_m_axi_gmem_ARREGION;
wire [2:0]get_0_m_axi_gmem_ARSIZE;
wire get_0_m_axi_gmem_ARVALID;
wire [31:0]get_0_m_axi_gmem_AWADDR;
wire [1:0]get_0_m_axi_gmem_AWBURST;
wire [7:0]get_0_m_axi_gmem_AWLEN;
wire [1:0]get_0_m_axi_gmem_AWLOCK;
wire [2:0]get_0_m_axi_gmem_AWPROT;
wire [3:0]get_0_m_axi_gmem_AWQOS;
wire get_0_m_axi_gmem_AWREADY;
wire [3:0]get_0_m_axi_gmem_AWREGION;
wire [2:0]get_0_m_axi_gmem_AWSIZE;
wire get_0_m_axi_gmem_AWVALID;
wire get_0_m_axi_gmem_BREADY;
wire [1:0]get_0_m_axi_gmem_BRESP;
wire get_0_m_axi_gmem_BVALID;
wire [31:0]get_0_m_axi_gmem_RDATA;
wire get_0_m_axi_gmem_RLAST;
wire get_0_m_axi_gmem_RREADY;
wire [1:0]get_0_m_axi_gmem_RRESP;
wire get_0_m_axi_gmem_RVALID;
wire [31:0]get_0_m_axi_gmem_WDATA;
wire get_0_m_axi_gmem_WLAST;
wire get_0_m_axi_gmem_WREADY;
wire [3:0]get_0_m_axi_gmem_WSTRB;
wire get_0_m_axi_gmem_WVALID;
wire [31:0]get_0_val_r1;
wire get_0_val_r_ap_vld;
wire [31:0]get_0_val_r_data_out;
wire get_0_val_r_vld_out;
wire [0:0]proc_sys_reset_2_interconnect_aresetn;
wire [0:0]proc_sys_reset_2_peripheral_aresetn;
wire [31:0]ps7_M_AXI_GP0_ARADDR;
wire [1:0]ps7_M_AXI_GP0_ARBURST;
wire [3:0]ps7_M_AXI_GP0_ARCACHE;
wire [11:0]ps7_M_AXI_GP0_ARID;
wire [3:0]ps7_M_AXI_GP0_ARLEN;
wire [1:0]ps7_M_AXI_GP0_ARLOCK;
wire [2:0]ps7_M_AXI_GP0_ARPROT;
wire [3:0]ps7_M_AXI_GP0_ARQOS;
wire ps7_M_AXI_GP0_ARREADY;
wire [2:0]ps7_M_AXI_GP0_ARSIZE;
wire ps7_M_AXI_GP0_ARVALID;
wire [31:0]ps7_M_AXI_GP0_AWADDR;
wire [1:0]ps7_M_AXI_GP0_AWBURST;
wire [3:0]ps7_M_AXI_GP0_AWCACHE;
wire [11:0]ps7_M_AXI_GP0_AWID;
wire [3:0]ps7_M_AXI_GP0_AWLEN;
wire [1:0]ps7_M_AXI_GP0_AWLOCK;
wire [2:0]ps7_M_AXI_GP0_AWPROT;
wire [3:0]ps7_M_AXI_GP0_AWQOS;
wire ps7_M_AXI_GP0_AWREADY;
wire [2:0]ps7_M_AXI_GP0_AWSIZE;
wire ps7_M_AXI_GP0_AWVALID;
wire [11:0]ps7_M_AXI_GP0_BID;
wire ps7_M_AXI_GP0_BREADY;
wire [1:0]ps7_M_AXI_GP0_BRESP;
wire ps7_M_AXI_GP0_BVALID;
wire [31:0]ps7_M_AXI_GP0_RDATA;
wire [11:0]ps7_M_AXI_GP0_RID;
wire ps7_M_AXI_GP0_RLAST;
wire ps7_M_AXI_GP0_RREADY;
wire [1:0]ps7_M_AXI_GP0_RRESP;
wire ps7_M_AXI_GP0_RVALID;
wire [31:0]ps7_M_AXI_GP0_WDATA;
wire [11:0]ps7_M_AXI_GP0_WID;
wire ps7_M_AXI_GP0_WLAST;
wire ps7_M_AXI_GP0_WREADY;
wire [3:0]ps7_M_AXI_GP0_WSTRB;
wire ps7_M_AXI_GP0_WVALID;
wire [14:0]ps7_ddr_ADDR;
wire [2:0]ps7_ddr_BA;
wire ps7_ddr_CAS_N;
wire ps7_ddr_CKE;
wire ps7_ddr_CK_N;
wire ps7_ddr_CK_P;
wire ps7_ddr_CS_N;
wire [3:0]ps7_ddr_DM;
wire [31:0]ps7_ddr_DQ;
wire [3:0]ps7_ddr_DQS_N;
wire [3:0]ps7_ddr_DQS_P;
wire ps7_ddr_ODT;
wire ps7_ddr_RAS_N;
wire ps7_ddr_RESET_N;
wire ps7_ddr_WE_N;
wire ps7_fclk_reset0_n;
wire ps7_fixed_io_DDR_VRN;
wire ps7_fixed_io_DDR_VRP;
wire [53:0]ps7_fixed_io_MIO;
wire ps7_fixed_io_PS_CLK;
wire ps7_fixed_io_PS_PORB;
wire ps7_fixed_io_PS_SRSTB;
wire [0:0]ps7_irq_const_dout;
wire [31:0]set_0_ap_return;
wire set_0_if_AP_CTRL_done;
wire set_0_if_AP_CTRL_idle;
wire set_0_if_AP_CTRL_ready;
wire set_0_if_AP_CTRL_start;
wire [31:0]set_0_if_ap_iscalar_0_dout;
wire [31:0]set_0_if_ap_iscalar_1_dout;
wire [31:0]set_0_if_ap_iscalar_2_dout;
wire set_0_if_aresetn;
wire [31:0]set_0_m_axi_gmem_ARADDR;
wire [1:0]set_0_m_axi_gmem_ARBURST;
wire [7:0]set_0_m_axi_gmem_ARLEN;
wire [1:0]set_0_m_axi_gmem_ARLOCK;
wire [2:0]set_0_m_axi_gmem_ARPROT;
wire [3:0]set_0_m_axi_gmem_ARQOS;
wire set_0_m_axi_gmem_ARREADY;
wire [3:0]set_0_m_axi_gmem_ARREGION;
wire [2:0]set_0_m_axi_gmem_ARSIZE;
wire set_0_m_axi_gmem_ARVALID;
wire [31:0]set_0_m_axi_gmem_AWADDR;
wire [1:0]set_0_m_axi_gmem_AWBURST;
wire [7:0]set_0_m_axi_gmem_AWLEN;
wire [1:0]set_0_m_axi_gmem_AWLOCK;
wire [2:0]set_0_m_axi_gmem_AWPROT;
wire [3:0]set_0_m_axi_gmem_AWQOS;
wire set_0_m_axi_gmem_AWREADY;
wire [3:0]set_0_m_axi_gmem_AWREGION;
wire [2:0]set_0_m_axi_gmem_AWSIZE;
wire set_0_m_axi_gmem_AWVALID;
wire set_0_m_axi_gmem_BREADY;
wire [1:0]set_0_m_axi_gmem_BRESP;
wire set_0_m_axi_gmem_BVALID;
wire [31:0]set_0_m_axi_gmem_RDATA;
wire set_0_m_axi_gmem_RLAST;
wire set_0_m_axi_gmem_RREADY;
wire [1:0]set_0_m_axi_gmem_RRESP;
wire set_0_m_axi_gmem_RVALID;
wire [31:0]set_0_m_axi_gmem_WDATA;
wire set_0_m_axi_gmem_WLAST;
wire set_0_m_axi_gmem_WREADY;
wire [3:0]set_0_m_axi_gmem_WSTRB;
wire set_0_m_axi_gmem_WVALID;
wire [0:0]xlconcat_1_dout;
zc702_acp_axcache_0xF_0 acp_axcache_0xF
(.dout(acp_axcache_0xF_dout));
zc702_axi_ic_ps7_M_AXI_GP0_0 axi_ic_ps7_M_AXI_GP0
(.ACLK(clkid2),
.ARESETN(proc_sys_reset_2_interconnect_aresetn),
.M00_ACLK(clkid2),
.M00_ARESETN(proc_sys_reset_2_interconnect_aresetn),
.M00_AXI_araddr(axi_ic_ps7_M_AXI_GP0_M00_AXI_ARADDR),
.M00_AXI_arready(axi_ic_ps7_M_AXI_GP0_M00_AXI_ARREADY),
.M00_AXI_arvalid(axi_ic_ps7_M_AXI_GP0_M00_AXI_ARVALID),
.M00_AXI_awaddr(axi_ic_ps7_M_AXI_GP0_M00_AXI_AWADDR),
.M00_AXI_awready(axi_ic_ps7_M_AXI_GP0_M00_AXI_AWREADY),
.M00_AXI_awvalid(axi_ic_ps7_M_AXI_GP0_M00_AXI_AWVALID),
.M00_AXI_bready(axi_ic_ps7_M_AXI_GP0_M00_AXI_BREADY),
.M00_AXI_bresp(axi_ic_ps7_M_AXI_GP0_M00_AXI_BRESP),
.M00_AXI_bvalid(axi_ic_ps7_M_AXI_GP0_M00_AXI_BVALID),
.M00_AXI_rdata(axi_ic_ps7_M_AXI_GP0_M00_AXI_RDATA),
.M00_AXI_rready(axi_ic_ps7_M_AXI_GP0_M00_AXI_RREADY),
.M00_AXI_rresp(axi_ic_ps7_M_AXI_GP0_M00_AXI_RRESP),
.M00_AXI_rvalid(axi_ic_ps7_M_AXI_GP0_M00_AXI_RVALID),
.M00_AXI_wdata(axi_ic_ps7_M_AXI_GP0_M00_AXI_WDATA),
.M00_AXI_wready(axi_ic_ps7_M_AXI_GP0_M00_AXI_WREADY),
.M00_AXI_wstrb(axi_ic_ps7_M_AXI_GP0_M00_AXI_WSTRB),
.M00_AXI_wvalid(axi_ic_ps7_M_AXI_GP0_M00_AXI_WVALID),
.M01_ACLK(clkid2),
.M01_ARESETN(proc_sys_reset_2_interconnect_aresetn),
.M01_AXI_araddr(axi_ic_ps7_M_AXI_GP0_M01_AXI_ARADDR),
.M01_AXI_arready(axi_ic_ps7_M_AXI_GP0_M01_AXI_ARREADY),
.M01_AXI_arvalid(axi_ic_ps7_M_AXI_GP0_M01_AXI_ARVALID),
.M01_AXI_awaddr(axi_ic_ps7_M_AXI_GP0_M01_AXI_AWADDR),
.M01_AXI_awready(axi_ic_ps7_M_AXI_GP0_M01_AXI_AWREADY),
.M01_AXI_awvalid(axi_ic_ps7_M_AXI_GP0_M01_AXI_AWVALID),
.M01_AXI_bready(axi_ic_ps7_M_AXI_GP0_M01_AXI_BREADY),
.M01_AXI_bresp(axi_ic_ps7_M_AXI_GP0_M01_AXI_BRESP),
.M01_AXI_bvalid(axi_ic_ps7_M_AXI_GP0_M01_AXI_BVALID),
.M01_AXI_rdata(axi_ic_ps7_M_AXI_GP0_M01_AXI_RDATA),
.M01_AXI_rready(axi_ic_ps7_M_AXI_GP0_M01_AXI_RREADY),
.M01_AXI_rresp(axi_ic_ps7_M_AXI_GP0_M01_AXI_RRESP),
.M01_AXI_rvalid(axi_ic_ps7_M_AXI_GP0_M01_AXI_RVALID),
.M01_AXI_wdata(axi_ic_ps7_M_AXI_GP0_M01_AXI_WDATA),
.M01_AXI_wready(axi_ic_ps7_M_AXI_GP0_M01_AXI_WREADY),
.M01_AXI_wstrb(axi_ic_ps7_M_AXI_GP0_M01_AXI_WSTRB),
.M01_AXI_wvalid(axi_ic_ps7_M_AXI_GP0_M01_AXI_WVALID),
.S00_ACLK(clkid2),
.S00_ARESETN(proc_sys_reset_2_interconnect_aresetn),
.S00_AXI_araddr(ps7_M_AXI_GP0_ARADDR),
.S00_AXI_arburst(ps7_M_AXI_GP0_ARBURST),
.S00_AXI_arcache(ps7_M_AXI_GP0_ARCACHE),
.S00_AXI_arid(ps7_M_AXI_GP0_ARID),
.S00_AXI_arlen(ps7_M_AXI_GP0_ARLEN),
.S00_AXI_arlock(ps7_M_AXI_GP0_ARLOCK),
.S00_AXI_arprot(ps7_M_AXI_GP0_ARPROT),
.S00_AXI_arqos(ps7_M_AXI_GP0_ARQOS),
.S00_AXI_arready(ps7_M_AXI_GP0_ARREADY),
.S00_AXI_arsize(ps7_M_AXI_GP0_ARSIZE),
.S00_AXI_arvalid(ps7_M_AXI_GP0_ARVALID),
.S00_AXI_awaddr(ps7_M_AXI_GP0_AWADDR),
.S00_AXI_awburst(ps7_M_AXI_GP0_AWBURST),
.S00_AXI_awcache(ps7_M_AXI_GP0_AWCACHE),
.S00_AXI_awid(ps7_M_AXI_GP0_AWID),
.S00_AXI_awlen(ps7_M_AXI_GP0_AWLEN),
.S00_AXI_awlock(ps7_M_AXI_GP0_AWLOCK),
.S00_AXI_awprot(ps7_M_AXI_GP0_AWPROT),
.S00_AXI_awqos(ps7_M_AXI_GP0_AWQOS),
.S00_AXI_awready(ps7_M_AXI_GP0_AWREADY),
.S00_AXI_awsize(ps7_M_AXI_GP0_AWSIZE),
.S00_AXI_awvalid(ps7_M_AXI_GP0_AWVALID),
.S00_AXI_bid(ps7_M_AXI_GP0_BID),
.S00_AXI_bready(ps7_M_AXI_GP0_BREADY),
.S00_AXI_bresp(ps7_M_AXI_GP0_BRESP),
.S00_AXI_bvalid(ps7_M_AXI_GP0_BVALID),
.S00_AXI_rdata(ps7_M_AXI_GP0_RDATA),
.S00_AXI_rid(ps7_M_AXI_GP0_RID),
.S00_AXI_rlast(ps7_M_AXI_GP0_RLAST),
.S00_AXI_rready(ps7_M_AXI_GP0_RREADY),
.S00_AXI_rresp(ps7_M_AXI_GP0_RRESP),
.S00_AXI_rvalid(ps7_M_AXI_GP0_RVALID),
.S00_AXI_wdata(ps7_M_AXI_GP0_WDATA),
.S00_AXI_wid(ps7_M_AXI_GP0_WID),
.S00_AXI_wlast(ps7_M_AXI_GP0_WLAST),
.S00_AXI_wready(ps7_M_AXI_GP0_WREADY),
.S00_AXI_wstrb(ps7_M_AXI_GP0_WSTRB),
.S00_AXI_wvalid(ps7_M_AXI_GP0_WVALID));
zc702_axi_ic_ps7_S_AXI_ACP_0 axi_ic_ps7_S_AXI_ACP
(.ACLK(clkid2),
.ARESETN(proc_sys_reset_2_interconnect_aresetn),
.M00_ACLK(clkid2),
.M00_ARESETN(proc_sys_reset_2_interconnect_aresetn),
.M00_AXI_araddr(axi_ic_ps7_S_AXI_ACP_M00_AXI_ARADDR),
.M00_AXI_arburst(axi_ic_ps7_S_AXI_ACP_M00_AXI_ARBURST),
.M00_AXI_arcache(axi_ic_ps7_S_AXI_ACP_M00_AXI_ARCACHE),
.M00_AXI_arid(axi_ic_ps7_S_AXI_ACP_M00_AXI_ARID),
.M00_AXI_arlen(axi_ic_ps7_S_AXI_ACP_M00_AXI_ARLEN),
.M00_AXI_arlock(axi_ic_ps7_S_AXI_ACP_M00_AXI_ARLOCK),
.M00_AXI_arprot(axi_ic_ps7_S_AXI_ACP_M00_AXI_ARPROT),
.M00_AXI_arqos(axi_ic_ps7_S_AXI_ACP_M00_AXI_ARQOS),
.M00_AXI_arready(axi_ic_ps7_S_AXI_ACP_M00_AXI_ARREADY),
.M00_AXI_arsize(axi_ic_ps7_S_AXI_ACP_M00_AXI_ARSIZE),
.M00_AXI_arvalid(axi_ic_ps7_S_AXI_ACP_M00_AXI_ARVALID),
.M00_AXI_awaddr(axi_ic_ps7_S_AXI_ACP_M00_AXI_AWADDR),
.M00_AXI_awburst(axi_ic_ps7_S_AXI_ACP_M00_AXI_AWBURST),
.M00_AXI_awcache(axi_ic_ps7_S_AXI_ACP_M00_AXI_AWCACHE),
.M00_AXI_awid(axi_ic_ps7_S_AXI_ACP_M00_AXI_AWID),
.M00_AXI_awlen(axi_ic_ps7_S_AXI_ACP_M00_AXI_AWLEN),
.M00_AXI_awlock(axi_ic_ps7_S_AXI_ACP_M00_AXI_AWLOCK),
.M00_AXI_awprot(axi_ic_ps7_S_AXI_ACP_M00_AXI_AWPROT),
.M00_AXI_awqos(axi_ic_ps7_S_AXI_ACP_M00_AXI_AWQOS),
.M00_AXI_awready(axi_ic_ps7_S_AXI_ACP_M00_AXI_AWREADY),
.M00_AXI_awsize(axi_ic_ps7_S_AXI_ACP_M00_AXI_AWSIZE),
.M00_AXI_awvalid(axi_ic_ps7_S_AXI_ACP_M00_AXI_AWVALID),
.M00_AXI_bid(axi_ic_ps7_S_AXI_ACP_M00_AXI_BID),
.M00_AXI_bready(axi_ic_ps7_S_AXI_ACP_M00_AXI_BREADY),
.M00_AXI_bresp(axi_ic_ps7_S_AXI_ACP_M00_AXI_BRESP),
.M00_AXI_bvalid(axi_ic_ps7_S_AXI_ACP_M00_AXI_BVALID),
.M00_AXI_rdata(axi_ic_ps7_S_AXI_ACP_M00_AXI_RDATA),
.M00_AXI_rid(axi_ic_ps7_S_AXI_ACP_M00_AXI_RID),
.M00_AXI_rlast(axi_ic_ps7_S_AXI_ACP_M00_AXI_RLAST),
.M00_AXI_rready(axi_ic_ps7_S_AXI_ACP_M00_AXI_RREADY),
.M00_AXI_rresp(axi_ic_ps7_S_AXI_ACP_M00_AXI_RRESP),
.M00_AXI_rvalid(axi_ic_ps7_S_AXI_ACP_M00_AXI_RVALID),
.M00_AXI_wdata(axi_ic_ps7_S_AXI_ACP_M00_AXI_WDATA),
.M00_AXI_wid(axi_ic_ps7_S_AXI_ACP_M00_AXI_WID),
.M00_AXI_wlast(axi_ic_ps7_S_AXI_ACP_M00_AXI_WLAST),
.M00_AXI_wready(axi_ic_ps7_S_AXI_ACP_M00_AXI_WREADY),
.M00_AXI_wstrb(axi_ic_ps7_S_AXI_ACP_M00_AXI_WSTRB),
.M00_AXI_wvalid(axi_ic_ps7_S_AXI_ACP_M00_AXI_WVALID),
.S00_ACLK(clkid2),
.S00_ARESETN(proc_sys_reset_2_interconnect_aresetn),
.S00_AXI_araddr(get_0_m_axi_gmem_ARADDR),
.S00_AXI_arburst(get_0_m_axi_gmem_ARBURST),
.S00_AXI_arcache(acp_axcache_0xF_dout),
.S00_AXI_arlen(get_0_m_axi_gmem_ARLEN),
.S00_AXI_arlock(get_0_m_axi_gmem_ARLOCK),
.S00_AXI_arprot(get_0_m_axi_gmem_ARPROT),
.S00_AXI_arqos(get_0_m_axi_gmem_ARQOS),
.S00_AXI_arready(get_0_m_axi_gmem_ARREADY),
.S00_AXI_arregion(get_0_m_axi_gmem_ARREGION),
.S00_AXI_arsize(get_0_m_axi_gmem_ARSIZE),
.S00_AXI_arvalid(get_0_m_axi_gmem_ARVALID),
.S00_AXI_awaddr(get_0_m_axi_gmem_AWADDR),
.S00_AXI_awburst(get_0_m_axi_gmem_AWBURST),
.S00_AXI_awcache(acp_axcache_0xF_dout),
.S00_AXI_awlen(get_0_m_axi_gmem_AWLEN),
.S00_AXI_awlock(get_0_m_axi_gmem_AWLOCK),
.S00_AXI_awprot(get_0_m_axi_gmem_AWPROT),
.S00_AXI_awqos(get_0_m_axi_gmem_AWQOS),
.S00_AXI_awready(get_0_m_axi_gmem_AWREADY),
.S00_AXI_awregion(get_0_m_axi_gmem_AWREGION),
.S00_AXI_awsize(get_0_m_axi_gmem_AWSIZE),
.S00_AXI_awvalid(get_0_m_axi_gmem_AWVALID),
.S00_AXI_bready(get_0_m_axi_gmem_BREADY),
.S00_AXI_bresp(get_0_m_axi_gmem_BRESP),
.S00_AXI_bvalid(get_0_m_axi_gmem_BVALID),
.S00_AXI_rdata(get_0_m_axi_gmem_RDATA),
.S00_AXI_rlast(get_0_m_axi_gmem_RLAST),
.S00_AXI_rready(get_0_m_axi_gmem_RREADY),
.S00_AXI_rresp(get_0_m_axi_gmem_RRESP),
.S00_AXI_rvalid(get_0_m_axi_gmem_RVALID),
.S00_AXI_wdata(get_0_m_axi_gmem_WDATA),
.S00_AXI_wlast(get_0_m_axi_gmem_WLAST),
.S00_AXI_wready(get_0_m_axi_gmem_WREADY),
.S00_AXI_wstrb(get_0_m_axi_gmem_WSTRB),
.S00_AXI_wvalid(get_0_m_axi_gmem_WVALID),
.S01_ACLK(clkid2),
.S01_ARESETN(proc_sys_reset_2_interconnect_aresetn),
.S01_AXI_araddr(set_0_m_axi_gmem_ARADDR),
.S01_AXI_arburst(set_0_m_axi_gmem_ARBURST),
.S01_AXI_arcache(acp_axcache_0xF_dout),
.S01_AXI_arlen(set_0_m_axi_gmem_ARLEN),
.S01_AXI_arlock(set_0_m_axi_gmem_ARLOCK),
.S01_AXI_arprot(set_0_m_axi_gmem_ARPROT),
.S01_AXI_arqos(set_0_m_axi_gmem_ARQOS),
.S01_AXI_arready(set_0_m_axi_gmem_ARREADY),
.S01_AXI_arregion(set_0_m_axi_gmem_ARREGION),
.S01_AXI_arsize(set_0_m_axi_gmem_ARSIZE),
.S01_AXI_arvalid(set_0_m_axi_gmem_ARVALID),
.S01_AXI_awaddr(set_0_m_axi_gmem_AWADDR),
.S01_AXI_awburst(set_0_m_axi_gmem_AWBURST),
.S01_AXI_awcache(acp_axcache_0xF_dout),
.S01_AXI_awlen(set_0_m_axi_gmem_AWLEN),
.S01_AXI_awlock(set_0_m_axi_gmem_AWLOCK),
.S01_AXI_awprot(set_0_m_axi_gmem_AWPROT),
.S01_AXI_awqos(set_0_m_axi_gmem_AWQOS),
.S01_AXI_awready(set_0_m_axi_gmem_AWREADY),
.S01_AXI_awregion(set_0_m_axi_gmem_AWREGION),
.S01_AXI_awsize(set_0_m_axi_gmem_AWSIZE),
.S01_AXI_awvalid(set_0_m_axi_gmem_AWVALID),
.S01_AXI_bready(set_0_m_axi_gmem_BREADY),
.S01_AXI_bresp(set_0_m_axi_gmem_BRESP),
.S01_AXI_bvalid(set_0_m_axi_gmem_BVALID),
.S01_AXI_rdata(set_0_m_axi_gmem_RDATA),
.S01_AXI_rlast(set_0_m_axi_gmem_RLAST),
.S01_AXI_rready(set_0_m_axi_gmem_RREADY),
.S01_AXI_rresp(set_0_m_axi_gmem_RRESP),
.S01_AXI_rvalid(set_0_m_axi_gmem_RVALID),
.S01_AXI_wdata(set_0_m_axi_gmem_WDATA),
.S01_AXI_wlast(set_0_m_axi_gmem_WLAST),
.S01_AXI_wready(set_0_m_axi_gmem_WREADY),
.S01_AXI_wstrb(set_0_m_axi_gmem_WSTRB),
.S01_AXI_wvalid(set_0_m_axi_gmem_WVALID));
zc702_get_0_0 get_0
(.ap_clk(clkid2),
.ap_done(get_0_if_AP_CTRL_done),
.ap_idle(get_0_if_AP_CTRL_idle),
.ap_ready(get_0_if_AP_CTRL_ready),
.ap_return(get_0_ap_return),
.ap_rst_n(get_0_if_aresetn),
.ap_start(get_0_if_AP_CTRL_start),
.data(get_0_if_ap_iscalar_0_dout),
.key(get_0_if_ap_iscalar_1_dout),
.m_axi_gmem_ARADDR(get_0_m_axi_gmem_ARADDR),
.m_axi_gmem_ARBURST(get_0_m_axi_gmem_ARBURST),
.m_axi_gmem_ARLEN(get_0_m_axi_gmem_ARLEN),
.m_axi_gmem_ARLOCK(get_0_m_axi_gmem_ARLOCK),
.m_axi_gmem_ARPROT(get_0_m_axi_gmem_ARPROT),
.m_axi_gmem_ARQOS(get_0_m_axi_gmem_ARQOS),
.m_axi_gmem_ARREADY(get_0_m_axi_gmem_ARREADY),
.m_axi_gmem_ARREGION(get_0_m_axi_gmem_ARREGION),
.m_axi_gmem_ARSIZE(get_0_m_axi_gmem_ARSIZE),
.m_axi_gmem_ARVALID(get_0_m_axi_gmem_ARVALID),
.m_axi_gmem_AWADDR(get_0_m_axi_gmem_AWADDR),
.m_axi_gmem_AWBURST(get_0_m_axi_gmem_AWBURST),
.m_axi_gmem_AWLEN(get_0_m_axi_gmem_AWLEN),
.m_axi_gmem_AWLOCK(get_0_m_axi_gmem_AWLOCK),
.m_axi_gmem_AWPROT(get_0_m_axi_gmem_AWPROT),
.m_axi_gmem_AWQOS(get_0_m_axi_gmem_AWQOS),
.m_axi_gmem_AWREADY(get_0_m_axi_gmem_AWREADY),
.m_axi_gmem_AWREGION(get_0_m_axi_gmem_AWREGION),
.m_axi_gmem_AWSIZE(get_0_m_axi_gmem_AWSIZE),
.m_axi_gmem_AWVALID(get_0_m_axi_gmem_AWVALID),
.m_axi_gmem_BREADY(get_0_m_axi_gmem_BREADY),
.m_axi_gmem_BRESP(get_0_m_axi_gmem_BRESP),
.m_axi_gmem_BVALID(get_0_m_axi_gmem_BVALID),
.m_axi_gmem_RDATA(get_0_m_axi_gmem_RDATA),
.m_axi_gmem_RLAST(get_0_m_axi_gmem_RLAST),
.m_axi_gmem_RREADY(get_0_m_axi_gmem_RREADY),
.m_axi_gmem_RRESP(get_0_m_axi_gmem_RRESP),
.m_axi_gmem_RVALID(get_0_m_axi_gmem_RVALID),
.m_axi_gmem_WDATA(get_0_m_axi_gmem_WDATA),
.m_axi_gmem_WLAST(get_0_m_axi_gmem_WLAST),
.m_axi_gmem_WREADY(get_0_m_axi_gmem_WREADY),
.m_axi_gmem_WSTRB(get_0_m_axi_gmem_WSTRB),
.m_axi_gmem_WVALID(get_0_m_axi_gmem_WVALID),
.val_r(get_0_val_r1),
.val_r_ap_vld(get_0_val_r_ap_vld));
zc702_get_0_if_0 get_0_if
(.aclk(clkid2),
.ap_done(get_0_if_AP_CTRL_done),
.ap_idle(get_0_if_AP_CTRL_idle),
.ap_iscalar_0_dout(get_0_if_ap_iscalar_0_dout),
.ap_iscalar_1_dout(get_0_if_ap_iscalar_1_dout),
.ap_oscalar_0_din(get_0_ap_return),
.ap_oscalar_1_din(get_0_val_r_data_out),
.ap_oscalar_1_vld(get_0_val_r_vld_out),
.ap_ready(get_0_if_AP_CTRL_ready),
.ap_start(get_0_if_AP_CTRL_start),
.aresetn(get_0_if_aresetn),
.s_axi_aclk(clkid2),
.s_axi_araddr(axi_ic_ps7_M_AXI_GP0_M00_AXI_ARADDR),
.s_axi_aresetn(proc_sys_reset_2_peripheral_aresetn),
.s_axi_arready(axi_ic_ps7_M_AXI_GP0_M00_AXI_ARREADY),
.s_axi_arvalid(axi_ic_ps7_M_AXI_GP0_M00_AXI_ARVALID),
.s_axi_awaddr(axi_ic_ps7_M_AXI_GP0_M00_AXI_AWADDR),
.s_axi_awready(axi_ic_ps7_M_AXI_GP0_M00_AXI_AWREADY),
.s_axi_awvalid(axi_ic_ps7_M_AXI_GP0_M00_AXI_AWVALID),
.s_axi_bready(axi_ic_ps7_M_AXI_GP0_M00_AXI_BREADY),
.s_axi_bresp(axi_ic_ps7_M_AXI_GP0_M00_AXI_BRESP),
.s_axi_bvalid(axi_ic_ps7_M_AXI_GP0_M00_AXI_BVALID),
.s_axi_rdata(axi_ic_ps7_M_AXI_GP0_M00_AXI_RDATA),
.s_axi_rready(axi_ic_ps7_M_AXI_GP0_M00_AXI_RREADY),
.s_axi_rresp(axi_ic_ps7_M_AXI_GP0_M00_AXI_RRESP),
.s_axi_rvalid(axi_ic_ps7_M_AXI_GP0_M00_AXI_RVALID),
.s_axi_wdata(axi_ic_ps7_M_AXI_GP0_M00_AXI_WDATA),
.s_axi_wready(axi_ic_ps7_M_AXI_GP0_M00_AXI_WREADY),
.s_axi_wstrb(axi_ic_ps7_M_AXI_GP0_M00_AXI_WSTRB),
.s_axi_wvalid(axi_ic_ps7_M_AXI_GP0_M00_AXI_WVALID));
zc702_get_0_val_r_0 get_0_val_r
(.ap_done(get_0_if_AP_CTRL_done),
.clk(clkid2),
.data_in(get_0_val_r1),
.data_out(get_0_val_r_data_out),
.vld_in(get_0_val_r_ap_vld),
.vld_out(get_0_val_r_vld_out));
zc702_proc_sys_reset_4_3 proc_sys_reset_0
(.aux_reset_in(1'b1),
.dcm_locked(1'b1),
.ext_reset_in(ps7_fclk_reset0_n),
.mb_debug_sys_rst(1'b0),
.slowest_sync_clk(clkid0));
zc702_proc_sys_reset_1_0 proc_sys_reset_1
(.aux_reset_in(1'b1),
.dcm_locked(1'b1),
.ext_reset_in(ps7_fclk_reset0_n),
.mb_debug_sys_rst(1'b0),
.slowest_sync_clk(clkid1));
zc702_proc_sys_reset_2_1 proc_sys_reset_2
(.aux_reset_in(1'b1),
.dcm_locked(1'b1),
.ext_reset_in(ps7_fclk_reset0_n),
.interconnect_aresetn(proc_sys_reset_2_interconnect_aresetn),
.mb_debug_sys_rst(1'b0),
.peripheral_aresetn(proc_sys_reset_2_peripheral_aresetn),
.slowest_sync_clk(clkid2));
zc702_proc_sys_reset_3_2 proc_sys_reset_3
(.aux_reset_in(1'b1),
.dcm_locked(1'b1),
.ext_reset_in(ps7_fclk_reset0_n),
.mb_debug_sys_rst(1'b0),
.slowest_sync_clk(clkid3));
zc702_processing_system7_1_0 ps7
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.FCLK_CLK0(clkid0),
.FCLK_CLK1(clkid1),
.FCLK_CLK2(clkid2),
.FCLK_CLK3(clkid3),
.FCLK_RESET0_N(ps7_fclk_reset0_n),
.IRQ_F2P(xlconcat_1_dout),
.MIO(FIXED_IO_mio[53:0]),
.M_AXI_GP0_ACLK(clkid2),
.M_AXI_GP0_ARADDR(ps7_M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(ps7_M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(ps7_M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARID(ps7_M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(ps7_M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(ps7_M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(ps7_M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(ps7_M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(ps7_M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(ps7_M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(ps7_M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(ps7_M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(ps7_M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(ps7_M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(ps7_M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(ps7_M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(ps7_M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(ps7_M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(ps7_M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(ps7_M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(ps7_M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(ps7_M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(ps7_M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(ps7_M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(ps7_M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(ps7_M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(ps7_M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(ps7_M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(ps7_M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(ps7_M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(ps7_M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(ps7_M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(ps7_M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(ps7_M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(ps7_M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(ps7_M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(ps7_M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(ps7_M_AXI_GP0_WVALID),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb),
.S_AXI_ACP_ACLK(clkid2),
.S_AXI_ACP_ARADDR(axi_ic_ps7_S_AXI_ACP_M00_AXI_ARADDR),
.S_AXI_ACP_ARBURST(axi_ic_ps7_S_AXI_ACP_M00_AXI_ARBURST),
.S_AXI_ACP_ARCACHE(axi_ic_ps7_S_AXI_ACP_M00_AXI_ARCACHE),
.S_AXI_ACP_ARID({1'b0,1'b0,axi_ic_ps7_S_AXI_ACP_M00_AXI_ARID}),
.S_AXI_ACP_ARLEN(axi_ic_ps7_S_AXI_ACP_M00_AXI_ARLEN),
.S_AXI_ACP_ARLOCK(axi_ic_ps7_S_AXI_ACP_M00_AXI_ARLOCK),
.S_AXI_ACP_ARPROT(axi_ic_ps7_S_AXI_ACP_M00_AXI_ARPROT),
.S_AXI_ACP_ARQOS(axi_ic_ps7_S_AXI_ACP_M00_AXI_ARQOS),
.S_AXI_ACP_ARREADY(axi_ic_ps7_S_AXI_ACP_M00_AXI_ARREADY),
.S_AXI_ACP_ARSIZE(axi_ic_ps7_S_AXI_ACP_M00_AXI_ARSIZE),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(axi_ic_ps7_S_AXI_ACP_M00_AXI_ARVALID),
.S_AXI_ACP_AWADDR(axi_ic_ps7_S_AXI_ACP_M00_AXI_AWADDR),
.S_AXI_ACP_AWBURST(axi_ic_ps7_S_AXI_ACP_M00_AXI_AWBURST),
.S_AXI_ACP_AWCACHE(axi_ic_ps7_S_AXI_ACP_M00_AXI_AWCACHE),
.S_AXI_ACP_AWID({1'b0,1'b0,axi_ic_ps7_S_AXI_ACP_M00_AXI_AWID}),
.S_AXI_ACP_AWLEN(axi_ic_ps7_S_AXI_ACP_M00_AXI_AWLEN),
.S_AXI_ACP_AWLOCK(axi_ic_ps7_S_AXI_ACP_M00_AXI_AWLOCK),
.S_AXI_ACP_AWPROT(axi_ic_ps7_S_AXI_ACP_M00_AXI_AWPROT),
.S_AXI_ACP_AWQOS(axi_ic_ps7_S_AXI_ACP_M00_AXI_AWQOS),
.S_AXI_ACP_AWREADY(axi_ic_ps7_S_AXI_ACP_M00_AXI_AWREADY),
.S_AXI_ACP_AWSIZE(axi_ic_ps7_S_AXI_ACP_M00_AXI_AWSIZE),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(axi_ic_ps7_S_AXI_ACP_M00_AXI_AWVALID),
.S_AXI_ACP_BID(axi_ic_ps7_S_AXI_ACP_M00_AXI_BID),
.S_AXI_ACP_BREADY(axi_ic_ps7_S_AXI_ACP_M00_AXI_BREADY),
.S_AXI_ACP_BRESP(axi_ic_ps7_S_AXI_ACP_M00_AXI_BRESP),
.S_AXI_ACP_BVALID(axi_ic_ps7_S_AXI_ACP_M00_AXI_BVALID),
.S_AXI_ACP_RDATA(axi_ic_ps7_S_AXI_ACP_M00_AXI_RDATA),
.S_AXI_ACP_RID(axi_ic_ps7_S_AXI_ACP_M00_AXI_RID),
.S_AXI_ACP_RLAST(axi_ic_ps7_S_AXI_ACP_M00_AXI_RLAST),
.S_AXI_ACP_RREADY(axi_ic_ps7_S_AXI_ACP_M00_AXI_RREADY),
.S_AXI_ACP_RRESP(axi_ic_ps7_S_AXI_ACP_M00_AXI_RRESP),
.S_AXI_ACP_RVALID(axi_ic_ps7_S_AXI_ACP_M00_AXI_RVALID),
.S_AXI_ACP_WDATA(axi_ic_ps7_S_AXI_ACP_M00_AXI_WDATA),
.S_AXI_ACP_WID({1'b0,1'b0,axi_ic_ps7_S_AXI_ACP_M00_AXI_WID}),
.S_AXI_ACP_WLAST(axi_ic_ps7_S_AXI_ACP_M00_AXI_WLAST),
.S_AXI_ACP_WREADY(axi_ic_ps7_S_AXI_ACP_M00_AXI_WREADY),
.S_AXI_ACP_WSTRB(axi_ic_ps7_S_AXI_ACP_M00_AXI_WSTRB),
.S_AXI_ACP_WVALID(axi_ic_ps7_S_AXI_ACP_M00_AXI_WVALID),
.USB0_VBUS_PWRFAULT(1'b0));
zc702_ps7_irq_const_0 ps7_irq_const
(.dout(ps7_irq_const_dout));
zc702_set_0_0 set_0
(.ap_clk(clkid2),
.ap_done(set_0_if_AP_CTRL_done),
.ap_idle(set_0_if_AP_CTRL_idle),
.ap_ready(set_0_if_AP_CTRL_ready),
.ap_return(set_0_ap_return),
.ap_rst_n(set_0_if_aresetn),
.ap_start(set_0_if_AP_CTRL_start),
.data(set_0_if_ap_iscalar_0_dout),
.key(set_0_if_ap_iscalar_1_dout),
.m_axi_gmem_ARADDR(set_0_m_axi_gmem_ARADDR),
.m_axi_gmem_ARBURST(set_0_m_axi_gmem_ARBURST),
.m_axi_gmem_ARLEN(set_0_m_axi_gmem_ARLEN),
.m_axi_gmem_ARLOCK(set_0_m_axi_gmem_ARLOCK),
.m_axi_gmem_ARPROT(set_0_m_axi_gmem_ARPROT),
.m_axi_gmem_ARQOS(set_0_m_axi_gmem_ARQOS),
.m_axi_gmem_ARREADY(set_0_m_axi_gmem_ARREADY),
.m_axi_gmem_ARREGION(set_0_m_axi_gmem_ARREGION),
.m_axi_gmem_ARSIZE(set_0_m_axi_gmem_ARSIZE),
.m_axi_gmem_ARVALID(set_0_m_axi_gmem_ARVALID),
.m_axi_gmem_AWADDR(set_0_m_axi_gmem_AWADDR),
.m_axi_gmem_AWBURST(set_0_m_axi_gmem_AWBURST),
.m_axi_gmem_AWLEN(set_0_m_axi_gmem_AWLEN),
.m_axi_gmem_AWLOCK(set_0_m_axi_gmem_AWLOCK),
.m_axi_gmem_AWPROT(set_0_m_axi_gmem_AWPROT),
.m_axi_gmem_AWQOS(set_0_m_axi_gmem_AWQOS),
.m_axi_gmem_AWREADY(set_0_m_axi_gmem_AWREADY),
.m_axi_gmem_AWREGION(set_0_m_axi_gmem_AWREGION),
.m_axi_gmem_AWSIZE(set_0_m_axi_gmem_AWSIZE),
.m_axi_gmem_AWVALID(set_0_m_axi_gmem_AWVALID),
.m_axi_gmem_BREADY(set_0_m_axi_gmem_BREADY),
.m_axi_gmem_BRESP(set_0_m_axi_gmem_BRESP),
.m_axi_gmem_BVALID(set_0_m_axi_gmem_BVALID),
.m_axi_gmem_RDATA(set_0_m_axi_gmem_RDATA),
.m_axi_gmem_RLAST(set_0_m_axi_gmem_RLAST),
.m_axi_gmem_RREADY(set_0_m_axi_gmem_RREADY),
.m_axi_gmem_RRESP(set_0_m_axi_gmem_RRESP),
.m_axi_gmem_RVALID(set_0_m_axi_gmem_RVALID),
.m_axi_gmem_WDATA(set_0_m_axi_gmem_WDATA),
.m_axi_gmem_WLAST(set_0_m_axi_gmem_WLAST),
.m_axi_gmem_WREADY(set_0_m_axi_gmem_WREADY),
.m_axi_gmem_WSTRB(set_0_m_axi_gmem_WSTRB),
.m_axi_gmem_WVALID(set_0_m_axi_gmem_WVALID),
.val_r(set_0_if_ap_iscalar_2_dout));
zc702_set_0_if_0 set_0_if
(.aclk(clkid2),
.ap_done(set_0_if_AP_CTRL_done),
.ap_idle(set_0_if_AP_CTRL_idle),
.ap_iscalar_0_dout(set_0_if_ap_iscalar_0_dout),
.ap_iscalar_1_dout(set_0_if_ap_iscalar_1_dout),
.ap_iscalar_2_dout(set_0_if_ap_iscalar_2_dout),
.ap_oscalar_0_din(set_0_ap_return),
.ap_ready(set_0_if_AP_CTRL_ready),
.ap_start(set_0_if_AP_CTRL_start),
.aresetn(set_0_if_aresetn),
.s_axi_aclk(clkid2),
.s_axi_araddr(axi_ic_ps7_M_AXI_GP0_M01_AXI_ARADDR),
.s_axi_aresetn(proc_sys_reset_2_peripheral_aresetn),
.s_axi_arready(axi_ic_ps7_M_AXI_GP0_M01_AXI_ARREADY),
.s_axi_arvalid(axi_ic_ps7_M_AXI_GP0_M01_AXI_ARVALID),
.s_axi_awaddr(axi_ic_ps7_M_AXI_GP0_M01_AXI_AWADDR),
.s_axi_awready(axi_ic_ps7_M_AXI_GP0_M01_AXI_AWREADY),
.s_axi_awvalid(axi_ic_ps7_M_AXI_GP0_M01_AXI_AWVALID),
.s_axi_bready(axi_ic_ps7_M_AXI_GP0_M01_AXI_BREADY),
.s_axi_bresp(axi_ic_ps7_M_AXI_GP0_M01_AXI_BRESP),
.s_axi_bvalid(axi_ic_ps7_M_AXI_GP0_M01_AXI_BVALID),
.s_axi_rdata(axi_ic_ps7_M_AXI_GP0_M01_AXI_RDATA),
.s_axi_rready(axi_ic_ps7_M_AXI_GP0_M01_AXI_RREADY),
.s_axi_rresp(axi_ic_ps7_M_AXI_GP0_M01_AXI_RRESP),
.s_axi_rvalid(axi_ic_ps7_M_AXI_GP0_M01_AXI_RVALID),
.s_axi_wdata(axi_ic_ps7_M_AXI_GP0_M01_AXI_WDATA),
.s_axi_wready(axi_ic_ps7_M_AXI_GP0_M01_AXI_WREADY),
.s_axi_wstrb(axi_ic_ps7_M_AXI_GP0_M01_AXI_WSTRB),
.s_axi_wvalid(axi_ic_ps7_M_AXI_GP0_M01_AXI_WVALID));
zc702_xlconcat_1_0 xlconcat
(.In0(ps7_irq_const_dout),
.dout(xlconcat_1_dout));
endmodule
module zc702_axi_ic_ps7_M_AXI_GP0_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arready,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awready,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
M01_ACLK,
M01_ARESETN,
M01_AXI_araddr,
M01_AXI_arready,
M01_AXI_arvalid,
M01_AXI_awaddr,
M01_AXI_awready,
M01_AXI_awvalid,
M01_AXI_bready,
M01_AXI_bresp,
M01_AXI_bvalid,
M01_AXI_rdata,
M01_AXI_rready,
M01_AXI_rresp,
M01_AXI_rvalid,
M01_AXI_wdata,
M01_AXI_wready,
M01_AXI_wstrb,
M01_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wid,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [12:0]M00_AXI_araddr;
input M00_AXI_arready;
output M00_AXI_arvalid;
output [12:0]M00_AXI_awaddr;
input M00_AXI_awready;
output M00_AXI_awvalid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [31:0]M00_AXI_rdata;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [31:0]M00_AXI_wdata;
input M00_AXI_wready;
output [3:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input M01_ACLK;
input [0:0]M01_ARESETN;
output [12:0]M01_AXI_araddr;
input M01_AXI_arready;
output M01_AXI_arvalid;
output [12:0]M01_AXI_awaddr;
input M01_AXI_awready;
output M01_AXI_awvalid;
output M01_AXI_bready;
input [1:0]M01_AXI_bresp;
input M01_AXI_bvalid;
input [31:0]M01_AXI_rdata;
output M01_AXI_rready;
input [1:0]M01_AXI_rresp;
input M01_AXI_rvalid;
output [31:0]M01_AXI_wdata;
input M01_AXI_wready;
output [3:0]M01_AXI_wstrb;
output M01_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [11:0]S00_AXI_arid;
input [3:0]S00_AXI_arlen;
input [1:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [11:0]S00_AXI_awid;
input [3:0]S00_AXI_awlen;
input [1:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [11:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output [11:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input [11:0]S00_AXI_wid;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire axi_ic_ps7_M_AXI_GP0_ACLK_net;
wire [0:0]axi_ic_ps7_M_AXI_GP0_ARESETN_net;
wire [31:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARADDR;
wire [1:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARBURST;
wire [3:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARCACHE;
wire [11:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARID;
wire [3:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARLEN;
wire [1:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARLOCK;
wire [2:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARPROT;
wire [3:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARQOS;
wire axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARREADY;
wire [2:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARSIZE;
wire axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARVALID;
wire [31:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWADDR;
wire [1:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWBURST;
wire [3:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWCACHE;
wire [11:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWID;
wire [3:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWLEN;
wire [1:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWLOCK;
wire [2:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWPROT;
wire [3:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWQOS;
wire axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWREADY;
wire [2:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWSIZE;
wire axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWVALID;
wire [11:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_BID;
wire axi_ic_ps7_M_AXI_GP0_to_s00_couplers_BREADY;
wire [1:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_BRESP;
wire axi_ic_ps7_M_AXI_GP0_to_s00_couplers_BVALID;
wire [31:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_RDATA;
wire [11:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_RID;
wire axi_ic_ps7_M_AXI_GP0_to_s00_couplers_RLAST;
wire axi_ic_ps7_M_AXI_GP0_to_s00_couplers_RREADY;
wire [1:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_RRESP;
wire axi_ic_ps7_M_AXI_GP0_to_s00_couplers_RVALID;
wire [31:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_WDATA;
wire [11:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_WID;
wire axi_ic_ps7_M_AXI_GP0_to_s00_couplers_WLAST;
wire axi_ic_ps7_M_AXI_GP0_to_s00_couplers_WREADY;
wire [3:0]axi_ic_ps7_M_AXI_GP0_to_s00_couplers_WSTRB;
wire axi_ic_ps7_M_AXI_GP0_to_s00_couplers_WVALID;
wire [12:0]m00_couplers_to_axi_ic_ps7_M_AXI_GP0_ARADDR;
wire m00_couplers_to_axi_ic_ps7_M_AXI_GP0_ARREADY;
wire m00_couplers_to_axi_ic_ps7_M_AXI_GP0_ARVALID;
wire [12:0]m00_couplers_to_axi_ic_ps7_M_AXI_GP0_AWADDR;
wire m00_couplers_to_axi_ic_ps7_M_AXI_GP0_AWREADY;
wire m00_couplers_to_axi_ic_ps7_M_AXI_GP0_AWVALID;
wire m00_couplers_to_axi_ic_ps7_M_AXI_GP0_BREADY;
wire [1:0]m00_couplers_to_axi_ic_ps7_M_AXI_GP0_BRESP;
wire m00_couplers_to_axi_ic_ps7_M_AXI_GP0_BVALID;
wire [31:0]m00_couplers_to_axi_ic_ps7_M_AXI_GP0_RDATA;
wire m00_couplers_to_axi_ic_ps7_M_AXI_GP0_RREADY;
wire [1:0]m00_couplers_to_axi_ic_ps7_M_AXI_GP0_RRESP;
wire m00_couplers_to_axi_ic_ps7_M_AXI_GP0_RVALID;
wire [31:0]m00_couplers_to_axi_ic_ps7_M_AXI_GP0_WDATA;
wire m00_couplers_to_axi_ic_ps7_M_AXI_GP0_WREADY;
wire [3:0]m00_couplers_to_axi_ic_ps7_M_AXI_GP0_WSTRB;
wire m00_couplers_to_axi_ic_ps7_M_AXI_GP0_WVALID;
wire [12:0]m01_couplers_to_axi_ic_ps7_M_AXI_GP0_ARADDR;
wire m01_couplers_to_axi_ic_ps7_M_AXI_GP0_ARREADY;
wire m01_couplers_to_axi_ic_ps7_M_AXI_GP0_ARVALID;
wire [12:0]m01_couplers_to_axi_ic_ps7_M_AXI_GP0_AWADDR;
wire m01_couplers_to_axi_ic_ps7_M_AXI_GP0_AWREADY;
wire m01_couplers_to_axi_ic_ps7_M_AXI_GP0_AWVALID;
wire m01_couplers_to_axi_ic_ps7_M_AXI_GP0_BREADY;
wire [1:0]m01_couplers_to_axi_ic_ps7_M_AXI_GP0_BRESP;
wire m01_couplers_to_axi_ic_ps7_M_AXI_GP0_BVALID;
wire [31:0]m01_couplers_to_axi_ic_ps7_M_AXI_GP0_RDATA;
wire m01_couplers_to_axi_ic_ps7_M_AXI_GP0_RREADY;
wire [1:0]m01_couplers_to_axi_ic_ps7_M_AXI_GP0_RRESP;
wire m01_couplers_to_axi_ic_ps7_M_AXI_GP0_RVALID;
wire [31:0]m01_couplers_to_axi_ic_ps7_M_AXI_GP0_WDATA;
wire m01_couplers_to_axi_ic_ps7_M_AXI_GP0_WREADY;
wire [3:0]m01_couplers_to_axi_ic_ps7_M_AXI_GP0_WSTRB;
wire m01_couplers_to_axi_ic_ps7_M_AXI_GP0_WVALID;
wire [31:0]s00_couplers_to_xbar_ARADDR;
wire [2:0]s00_couplers_to_xbar_ARPROT;
wire [0:0]s00_couplers_to_xbar_ARREADY;
wire s00_couplers_to_xbar_ARVALID;
wire [31:0]s00_couplers_to_xbar_AWADDR;
wire [2:0]s00_couplers_to_xbar_AWPROT;
wire [0:0]s00_couplers_to_xbar_AWREADY;
wire s00_couplers_to_xbar_AWVALID;
wire s00_couplers_to_xbar_BREADY;
wire [1:0]s00_couplers_to_xbar_BRESP;
wire [0:0]s00_couplers_to_xbar_BVALID;
wire [31:0]s00_couplers_to_xbar_RDATA;
wire s00_couplers_to_xbar_RREADY;
wire [1:0]s00_couplers_to_xbar_RRESP;
wire [0:0]s00_couplers_to_xbar_RVALID;
wire [31:0]s00_couplers_to_xbar_WDATA;
wire [0:0]s00_couplers_to_xbar_WREADY;
wire [3:0]s00_couplers_to_xbar_WSTRB;
wire s00_couplers_to_xbar_WVALID;
wire [31:0]xbar_to_m00_couplers_ARADDR;
wire [2:0]xbar_to_m00_couplers_ARPROT;
wire xbar_to_m00_couplers_ARREADY;
wire [0:0]xbar_to_m00_couplers_ARVALID;
wire [31:0]xbar_to_m00_couplers_AWADDR;
wire [2:0]xbar_to_m00_couplers_AWPROT;
wire xbar_to_m00_couplers_AWREADY;
wire [0:0]xbar_to_m00_couplers_AWVALID;
wire [0:0]xbar_to_m00_couplers_BREADY;
wire [1:0]xbar_to_m00_couplers_BRESP;
wire xbar_to_m00_couplers_BVALID;
wire [31:0]xbar_to_m00_couplers_RDATA;
wire [0:0]xbar_to_m00_couplers_RREADY;
wire [1:0]xbar_to_m00_couplers_RRESP;
wire xbar_to_m00_couplers_RVALID;
wire [31:0]xbar_to_m00_couplers_WDATA;
wire xbar_to_m00_couplers_WREADY;
wire [3:0]xbar_to_m00_couplers_WSTRB;
wire [0:0]xbar_to_m00_couplers_WVALID;
wire [63:32]xbar_to_m01_couplers_ARADDR;
wire [5:3]xbar_to_m01_couplers_ARPROT;
wire xbar_to_m01_couplers_ARREADY;
wire [1:1]xbar_to_m01_couplers_ARVALID;
wire [63:32]xbar_to_m01_couplers_AWADDR;
wire [5:3]xbar_to_m01_couplers_AWPROT;
wire xbar_to_m01_couplers_AWREADY;
wire [1:1]xbar_to_m01_couplers_AWVALID;
wire [1:1]xbar_to_m01_couplers_BREADY;
wire [1:0]xbar_to_m01_couplers_BRESP;
wire xbar_to_m01_couplers_BVALID;
wire [31:0]xbar_to_m01_couplers_RDATA;
wire [1:1]xbar_to_m01_couplers_RREADY;
wire [1:0]xbar_to_m01_couplers_RRESP;
wire xbar_to_m01_couplers_RVALID;
wire [63:32]xbar_to_m01_couplers_WDATA;
wire xbar_to_m01_couplers_WREADY;
wire [7:4]xbar_to_m01_couplers_WSTRB;
wire [1:1]xbar_to_m01_couplers_WVALID;
assign M00_AXI_araddr[12:0] = m00_couplers_to_axi_ic_ps7_M_AXI_GP0_ARADDR;
assign M00_AXI_arvalid = m00_couplers_to_axi_ic_ps7_M_AXI_GP0_ARVALID;
assign M00_AXI_awaddr[12:0] = m00_couplers_to_axi_ic_ps7_M_AXI_GP0_AWADDR;
assign M00_AXI_awvalid = m00_couplers_to_axi_ic_ps7_M_AXI_GP0_AWVALID;
assign M00_AXI_bready = m00_couplers_to_axi_ic_ps7_M_AXI_GP0_BREADY;
assign M00_AXI_rready = m00_couplers_to_axi_ic_ps7_M_AXI_GP0_RREADY;
assign M00_AXI_wdata[31:0] = m00_couplers_to_axi_ic_ps7_M_AXI_GP0_WDATA;
assign M00_AXI_wstrb[3:0] = m00_couplers_to_axi_ic_ps7_M_AXI_GP0_WSTRB;
assign M00_AXI_wvalid = m00_couplers_to_axi_ic_ps7_M_AXI_GP0_WVALID;
assign M01_AXI_araddr[12:0] = m01_couplers_to_axi_ic_ps7_M_AXI_GP0_ARADDR;
assign M01_AXI_arvalid = m01_couplers_to_axi_ic_ps7_M_AXI_GP0_ARVALID;
assign M01_AXI_awaddr[12:0] = m01_couplers_to_axi_ic_ps7_M_AXI_GP0_AWADDR;
assign M01_AXI_awvalid = m01_couplers_to_axi_ic_ps7_M_AXI_GP0_AWVALID;
assign M01_AXI_bready = m01_couplers_to_axi_ic_ps7_M_AXI_GP0_BREADY;
assign M01_AXI_rready = m01_couplers_to_axi_ic_ps7_M_AXI_GP0_RREADY;
assign M01_AXI_wdata[31:0] = m01_couplers_to_axi_ic_ps7_M_AXI_GP0_WDATA;
assign M01_AXI_wstrb[3:0] = m01_couplers_to_axi_ic_ps7_M_AXI_GP0_WSTRB;
assign M01_AXI_wvalid = m01_couplers_to_axi_ic_ps7_M_AXI_GP0_WVALID;
assign S00_AXI_arready = axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARREADY;
assign S00_AXI_awready = axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWREADY;
assign S00_AXI_bid[11:0] = axi_ic_ps7_M_AXI_GP0_to_s00_couplers_BID;
assign S00_AXI_bresp[1:0] = axi_ic_ps7_M_AXI_GP0_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = axi_ic_ps7_M_AXI_GP0_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = axi_ic_ps7_M_AXI_GP0_to_s00_couplers_RDATA;
assign S00_AXI_rid[11:0] = axi_ic_ps7_M_AXI_GP0_to_s00_couplers_RID;
assign S00_AXI_rlast = axi_ic_ps7_M_AXI_GP0_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = axi_ic_ps7_M_AXI_GP0_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = axi_ic_ps7_M_AXI_GP0_to_s00_couplers_RVALID;
assign S00_AXI_wready = axi_ic_ps7_M_AXI_GP0_to_s00_couplers_WREADY;
assign axi_ic_ps7_M_AXI_GP0_ACLK_net = ACLK;
assign axi_ic_ps7_M_AXI_GP0_ARESETN_net = ARESETN[0];
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARID = S00_AXI_arid[11:0];
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWID = S00_AXI_awid[11:0];
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_BREADY = S00_AXI_bready;
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_RREADY = S00_AXI_rready;
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_WID = S00_AXI_wid[11:0];
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_WLAST = S00_AXI_wlast;
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign axi_ic_ps7_M_AXI_GP0_to_s00_couplers_WVALID = S00_AXI_wvalid;
assign m00_couplers_to_axi_ic_ps7_M_AXI_GP0_ARREADY = M00_AXI_arready;
assign m00_couplers_to_axi_ic_ps7_M_AXI_GP0_AWREADY = M00_AXI_awready;
assign m00_couplers_to_axi_ic_ps7_M_AXI_GP0_BRESP = M00_AXI_bresp[1:0];
assign m00_couplers_to_axi_ic_ps7_M_AXI_GP0_BVALID = M00_AXI_bvalid;
assign m00_couplers_to_axi_ic_ps7_M_AXI_GP0_RDATA = M00_AXI_rdata[31:0];
assign m00_couplers_to_axi_ic_ps7_M_AXI_GP0_RRESP = M00_AXI_rresp[1:0];
assign m00_couplers_to_axi_ic_ps7_M_AXI_GP0_RVALID = M00_AXI_rvalid;
assign m00_couplers_to_axi_ic_ps7_M_AXI_GP0_WREADY = M00_AXI_wready;
assign m01_couplers_to_axi_ic_ps7_M_AXI_GP0_ARREADY = M01_AXI_arready;
assign m01_couplers_to_axi_ic_ps7_M_AXI_GP0_AWREADY = M01_AXI_awready;
assign m01_couplers_to_axi_ic_ps7_M_AXI_GP0_BRESP = M01_AXI_bresp[1:0];
assign m01_couplers_to_axi_ic_ps7_M_AXI_GP0_BVALID = M01_AXI_bvalid;
assign m01_couplers_to_axi_ic_ps7_M_AXI_GP0_RDATA = M01_AXI_rdata[31:0];
assign m01_couplers_to_axi_ic_ps7_M_AXI_GP0_RRESP = M01_AXI_rresp[1:0];
assign m01_couplers_to_axi_ic_ps7_M_AXI_GP0_RVALID = M01_AXI_rvalid;
assign m01_couplers_to_axi_ic_ps7_M_AXI_GP0_WREADY = M01_AXI_wready;
m00_couplers_imp_1IKQD79 m00_couplers
(.M_ACLK(axi_ic_ps7_M_AXI_GP0_ACLK_net),
.M_ARESETN(axi_ic_ps7_M_AXI_GP0_ARESETN_net),
.M_AXI_araddr(m00_couplers_to_axi_ic_ps7_M_AXI_GP0_ARADDR),
.M_AXI_arready(m00_couplers_to_axi_ic_ps7_M_AXI_GP0_ARREADY),
.M_AXI_arvalid(m00_couplers_to_axi_ic_ps7_M_AXI_GP0_ARVALID),
.M_AXI_awaddr(m00_couplers_to_axi_ic_ps7_M_AXI_GP0_AWADDR),
.M_AXI_awready(m00_couplers_to_axi_ic_ps7_M_AXI_GP0_AWREADY),
.M_AXI_awvalid(m00_couplers_to_axi_ic_ps7_M_AXI_GP0_AWVALID),
.M_AXI_bready(m00_couplers_to_axi_ic_ps7_M_AXI_GP0_BREADY),
.M_AXI_bresp(m00_couplers_to_axi_ic_ps7_M_AXI_GP0_BRESP),
.M_AXI_bvalid(m00_couplers_to_axi_ic_ps7_M_AXI_GP0_BVALID),
.M_AXI_rdata(m00_couplers_to_axi_ic_ps7_M_AXI_GP0_RDATA),
.M_AXI_rready(m00_couplers_to_axi_ic_ps7_M_AXI_GP0_RREADY),
.M_AXI_rresp(m00_couplers_to_axi_ic_ps7_M_AXI_GP0_RRESP),
.M_AXI_rvalid(m00_couplers_to_axi_ic_ps7_M_AXI_GP0_RVALID),
.M_AXI_wdata(m00_couplers_to_axi_ic_ps7_M_AXI_GP0_WDATA),
.M_AXI_wready(m00_couplers_to_axi_ic_ps7_M_AXI_GP0_WREADY),
.M_AXI_wstrb(m00_couplers_to_axi_ic_ps7_M_AXI_GP0_WSTRB),
.M_AXI_wvalid(m00_couplers_to_axi_ic_ps7_M_AXI_GP0_WVALID),
.S_ACLK(axi_ic_ps7_M_AXI_GP0_ACLK_net),
.S_ARESETN(axi_ic_ps7_M_AXI_GP0_ARESETN_net),
.S_AXI_araddr(xbar_to_m00_couplers_ARADDR),
.S_AXI_arprot(xbar_to_m00_couplers_ARPROT),
.S_AXI_arready(xbar_to_m00_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m00_couplers_AWADDR),
.S_AXI_awprot(xbar_to_m00_couplers_AWPROT),
.S_AXI_awready(xbar_to_m00_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),
.S_AXI_bready(xbar_to_m00_couplers_BREADY),
.S_AXI_bresp(xbar_to_m00_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m00_couplers_BVALID),
.S_AXI_rdata(xbar_to_m00_couplers_RDATA),
.S_AXI_rready(xbar_to_m00_couplers_RREADY),
.S_AXI_rresp(xbar_to_m00_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m00_couplers_RVALID),
.S_AXI_wdata(xbar_to_m00_couplers_WDATA),
.S_AXI_wready(xbar_to_m00_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m00_couplers_WVALID));
m01_couplers_imp_YRHFB1 m01_couplers
(.M_ACLK(axi_ic_ps7_M_AXI_GP0_ACLK_net),
.M_ARESETN(axi_ic_ps7_M_AXI_GP0_ARESETN_net),
.M_AXI_araddr(m01_couplers_to_axi_ic_ps7_M_AXI_GP0_ARADDR),
.M_AXI_arready(m01_couplers_to_axi_ic_ps7_M_AXI_GP0_ARREADY),
.M_AXI_arvalid(m01_couplers_to_axi_ic_ps7_M_AXI_GP0_ARVALID),
.M_AXI_awaddr(m01_couplers_to_axi_ic_ps7_M_AXI_GP0_AWADDR),
.M_AXI_awready(m01_couplers_to_axi_ic_ps7_M_AXI_GP0_AWREADY),
.M_AXI_awvalid(m01_couplers_to_axi_ic_ps7_M_AXI_GP0_AWVALID),
.M_AXI_bready(m01_couplers_to_axi_ic_ps7_M_AXI_GP0_BREADY),
.M_AXI_bresp(m01_couplers_to_axi_ic_ps7_M_AXI_GP0_BRESP),
.M_AXI_bvalid(m01_couplers_to_axi_ic_ps7_M_AXI_GP0_BVALID),
.M_AXI_rdata(m01_couplers_to_axi_ic_ps7_M_AXI_GP0_RDATA),
.M_AXI_rready(m01_couplers_to_axi_ic_ps7_M_AXI_GP0_RREADY),
.M_AXI_rresp(m01_couplers_to_axi_ic_ps7_M_AXI_GP0_RRESP),
.M_AXI_rvalid(m01_couplers_to_axi_ic_ps7_M_AXI_GP0_RVALID),
.M_AXI_wdata(m01_couplers_to_axi_ic_ps7_M_AXI_GP0_WDATA),
.M_AXI_wready(m01_couplers_to_axi_ic_ps7_M_AXI_GP0_WREADY),
.M_AXI_wstrb(m01_couplers_to_axi_ic_ps7_M_AXI_GP0_WSTRB),
.M_AXI_wvalid(m01_couplers_to_axi_ic_ps7_M_AXI_GP0_WVALID),
.S_ACLK(axi_ic_ps7_M_AXI_GP0_ACLK_net),
.S_ARESETN(axi_ic_ps7_M_AXI_GP0_ARESETN_net),
.S_AXI_araddr(xbar_to_m01_couplers_ARADDR),
.S_AXI_arprot(xbar_to_m01_couplers_ARPROT),
.S_AXI_arready(xbar_to_m01_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m01_couplers_AWADDR),
.S_AXI_awprot(xbar_to_m01_couplers_AWPROT),
.S_AXI_awready(xbar_to_m01_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),
.S_AXI_bready(xbar_to_m01_couplers_BREADY),
.S_AXI_bresp(xbar_to_m01_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m01_couplers_BVALID),
.S_AXI_rdata(xbar_to_m01_couplers_RDATA),
.S_AXI_rready(xbar_to_m01_couplers_RREADY),
.S_AXI_rresp(xbar_to_m01_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m01_couplers_RVALID),
.S_AXI_wdata(xbar_to_m01_couplers_WDATA),
.S_AXI_wready(xbar_to_m01_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m01_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m01_couplers_WVALID));
s00_couplers_imp_14Q0TRY s00_couplers
(.M_ACLK(axi_ic_ps7_M_AXI_GP0_ACLK_net),
.M_ARESETN(axi_ic_ps7_M_AXI_GP0_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_xbar_ARADDR),
.M_AXI_arprot(s00_couplers_to_xbar_ARPROT),
.M_AXI_arready(s00_couplers_to_xbar_ARREADY),
.M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),
.M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),
.M_AXI_awprot(s00_couplers_to_xbar_AWPROT),
.M_AXI_awready(s00_couplers_to_xbar_AWREADY),
.M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),
.M_AXI_bready(s00_couplers_to_xbar_BREADY),
.M_AXI_bresp(s00_couplers_to_xbar_BRESP),
.M_AXI_bvalid(s00_couplers_to_xbar_BVALID),
.M_AXI_rdata(s00_couplers_to_xbar_RDATA),
.M_AXI_rready(s00_couplers_to_xbar_RREADY),
.M_AXI_rresp(s00_couplers_to_xbar_RRESP),
.M_AXI_rvalid(s00_couplers_to_xbar_RVALID),
.M_AXI_wdata(s00_couplers_to_xbar_WDATA),
.M_AXI_wready(s00_couplers_to_xbar_WREADY),
.M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),
.M_AXI_wvalid(s00_couplers_to_xbar_WVALID),
.S_ACLK(axi_ic_ps7_M_AXI_GP0_ACLK_net),
.S_ARESETN(axi_ic_ps7_M_AXI_GP0_ARESETN_net),
.S_AXI_araddr(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARADDR),
.S_AXI_arburst(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARBURST),
.S_AXI_arcache(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARCACHE),
.S_AXI_arid(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARID),
.S_AXI_arlen(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARLEN),
.S_AXI_arlock(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARLOCK),
.S_AXI_arprot(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARPROT),
.S_AXI_arqos(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARQOS),
.S_AXI_arready(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARREADY),
.S_AXI_arsize(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_ARVALID),
.S_AXI_awaddr(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWADDR),
.S_AXI_awburst(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWBURST),
.S_AXI_awcache(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWCACHE),
.S_AXI_awid(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWID),
.S_AXI_awlen(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWLEN),
.S_AXI_awlock(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWLOCK),
.S_AXI_awprot(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWPROT),
.S_AXI_awqos(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWQOS),
.S_AXI_awready(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWREADY),
.S_AXI_awsize(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_AWVALID),
.S_AXI_bid(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_BID),
.S_AXI_bready(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_BREADY),
.S_AXI_bresp(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_BRESP),
.S_AXI_bvalid(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_BVALID),
.S_AXI_rdata(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_RDATA),
.S_AXI_rid(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_RID),
.S_AXI_rlast(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_RLAST),
.S_AXI_rready(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_RREADY),
.S_AXI_rresp(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_RRESP),
.S_AXI_rvalid(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_RVALID),
.S_AXI_wdata(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_WDATA),
.S_AXI_wid(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_WID),
.S_AXI_wlast(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_WLAST),
.S_AXI_wready(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_WREADY),
.S_AXI_wstrb(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_WSTRB),
.S_AXI_wvalid(axi_ic_ps7_M_AXI_GP0_to_s00_couplers_WVALID));
zc702_xbar_0 xbar
(.aclk(axi_ic_ps7_M_AXI_GP0_ACLK_net),
.aresetn(axi_ic_ps7_M_AXI_GP0_ARESETN_net),
.m_axi_araddr({xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),
.m_axi_arprot({xbar_to_m01_couplers_ARPROT,xbar_to_m00_couplers_ARPROT}),
.m_axi_arready({xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),
.m_axi_arvalid({xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),
.m_axi_awaddr({xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),
.m_axi_awprot({xbar_to_m01_couplers_AWPROT,xbar_to_m00_couplers_AWPROT}),
.m_axi_awready({xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),
.m_axi_awvalid({xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),
.m_axi_bready({xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),
.m_axi_bresp({xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}),
.m_axi_bvalid({xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),
.m_axi_rdata({xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}),
.m_axi_rready({xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),
.m_axi_rresp({xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}),
.m_axi_rvalid({xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),
.m_axi_wdata({xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),
.m_axi_wready({xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),
.m_axi_wstrb({xbar_to_m01_couplers_WSTRB,xbar_to_m00_couplers_WSTRB}),
.m_axi_wvalid({xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),
.s_axi_araddr(s00_couplers_to_xbar_ARADDR),
.s_axi_arprot(s00_couplers_to_xbar_ARPROT),
.s_axi_arready(s00_couplers_to_xbar_ARREADY),
.s_axi_arvalid(s00_couplers_to_xbar_ARVALID),
.s_axi_awaddr(s00_couplers_to_xbar_AWADDR),
.s_axi_awprot(s00_couplers_to_xbar_AWPROT),
.s_axi_awready(s00_couplers_to_xbar_AWREADY),
.s_axi_awvalid(s00_couplers_to_xbar_AWVALID),
.s_axi_bready(s00_couplers_to_xbar_BREADY),
.s_axi_bresp(s00_couplers_to_xbar_BRESP),
.s_axi_bvalid(s00_couplers_to_xbar_BVALID),
.s_axi_rdata(s00_couplers_to_xbar_RDATA),
.s_axi_rready(s00_couplers_to_xbar_RREADY),
.s_axi_rresp(s00_couplers_to_xbar_RRESP),
.s_axi_rvalid(s00_couplers_to_xbar_RVALID),
.s_axi_wdata(s00_couplers_to_xbar_WDATA),
.s_axi_wready(s00_couplers_to_xbar_WREADY),
.s_axi_wstrb(s00_couplers_to_xbar_WSTRB),
.s_axi_wvalid(s00_couplers_to_xbar_WVALID));
endmodule
module zc702_axi_ic_ps7_S_AXI_ACP_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arburst,
M00_AXI_arcache,
M00_AXI_arid,
M00_AXI_arlen,
M00_AXI_arlock,
M00_AXI_arprot,
M00_AXI_arqos,
M00_AXI_arready,
M00_AXI_arsize,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awburst,
M00_AXI_awcache,
M00_AXI_awid,
M00_AXI_awlen,
M00_AXI_awlock,
M00_AXI_awprot,
M00_AXI_awqos,
M00_AXI_awready,
M00_AXI_awsize,
M00_AXI_awvalid,
M00_AXI_bid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rid,
M00_AXI_rlast,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wid,
M00_AXI_wlast,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arregion,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awregion,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid,
S01_ACLK,
S01_ARESETN,
S01_AXI_araddr,
S01_AXI_arburst,
S01_AXI_arcache,
S01_AXI_arlen,
S01_AXI_arlock,
S01_AXI_arprot,
S01_AXI_arqos,
S01_AXI_arready,
S01_AXI_arregion,
S01_AXI_arsize,
S01_AXI_arvalid,
S01_AXI_awaddr,
S01_AXI_awburst,
S01_AXI_awcache,
S01_AXI_awlen,
S01_AXI_awlock,
S01_AXI_awprot,
S01_AXI_awqos,
S01_AXI_awready,
S01_AXI_awregion,
S01_AXI_awsize,
S01_AXI_awvalid,
S01_AXI_bready,
S01_AXI_bresp,
S01_AXI_bvalid,
S01_AXI_rdata,
S01_AXI_rlast,
S01_AXI_rready,
S01_AXI_rresp,
S01_AXI_rvalid,
S01_AXI_wdata,
S01_AXI_wlast,
S01_AXI_wready,
S01_AXI_wstrb,
S01_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [31:0]M00_AXI_araddr;
output [1:0]M00_AXI_arburst;
output [3:0]M00_AXI_arcache;
output [0:0]M00_AXI_arid;
output [3:0]M00_AXI_arlen;
output [1:0]M00_AXI_arlock;
output [2:0]M00_AXI_arprot;
output [3:0]M00_AXI_arqos;
input M00_AXI_arready;
output [2:0]M00_AXI_arsize;
output M00_AXI_arvalid;
output [31:0]M00_AXI_awaddr;
output [1:0]M00_AXI_awburst;
output [3:0]M00_AXI_awcache;
output [0:0]M00_AXI_awid;
output [3:0]M00_AXI_awlen;
output [1:0]M00_AXI_awlock;
output [2:0]M00_AXI_awprot;
output [3:0]M00_AXI_awqos;
input M00_AXI_awready;
output [2:0]M00_AXI_awsize;
output M00_AXI_awvalid;
input [2:0]M00_AXI_bid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [63:0]M00_AXI_rdata;
input [2:0]M00_AXI_rid;
input M00_AXI_rlast;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [63:0]M00_AXI_wdata;
output [0:0]M00_AXI_wid;
output M00_AXI_wlast;
input M00_AXI_wready;
output [7:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [7:0]S00_AXI_arlen;
input [1:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [3:0]S00_AXI_arregion;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [7:0]S00_AXI_awlen;
input [1:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [3:0]S00_AXI_awregion;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
input S01_ACLK;
input [0:0]S01_ARESETN;
input [31:0]S01_AXI_araddr;
input [1:0]S01_AXI_arburst;
input [3:0]S01_AXI_arcache;
input [7:0]S01_AXI_arlen;
input [1:0]S01_AXI_arlock;
input [2:0]S01_AXI_arprot;
input [3:0]S01_AXI_arqos;
output S01_AXI_arready;
input [3:0]S01_AXI_arregion;
input [2:0]S01_AXI_arsize;
input S01_AXI_arvalid;
input [31:0]S01_AXI_awaddr;
input [1:0]S01_AXI_awburst;
input [3:0]S01_AXI_awcache;
input [7:0]S01_AXI_awlen;
input [1:0]S01_AXI_awlock;
input [2:0]S01_AXI_awprot;
input [3:0]S01_AXI_awqos;
output S01_AXI_awready;
input [3:0]S01_AXI_awregion;
input [2:0]S01_AXI_awsize;
input S01_AXI_awvalid;
input S01_AXI_bready;
output [1:0]S01_AXI_bresp;
output S01_AXI_bvalid;
output [31:0]S01_AXI_rdata;
output S01_AXI_rlast;
input S01_AXI_rready;
output [1:0]S01_AXI_rresp;
output S01_AXI_rvalid;
input [31:0]S01_AXI_wdata;
input S01_AXI_wlast;
output S01_AXI_wready;
input [3:0]S01_AXI_wstrb;
input S01_AXI_wvalid;
wire axi_ic_ps7_S_AXI_ACP_ACLK_net;
wire [0:0]axi_ic_ps7_S_AXI_ACP_ARESETN_net;
wire [31:0]axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARADDR;
wire [1:0]axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARBURST;
wire [3:0]axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARCACHE;
wire [7:0]axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARLEN;
wire [1:0]axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARLOCK;
wire [2:0]axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARPROT;
wire [3:0]axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARQOS;
wire axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARREADY;
wire [3:0]axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARREGION;
wire [2:0]axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARSIZE;
wire axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARVALID;
wire [31:0]axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWADDR;
wire [1:0]axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWBURST;
wire [3:0]axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWCACHE;
wire [7:0]axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWLEN;
wire [1:0]axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWLOCK;
wire [2:0]axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWPROT;
wire [3:0]axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWQOS;
wire axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWREADY;
wire [3:0]axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWREGION;
wire [2:0]axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWSIZE;
wire axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWVALID;
wire axi_ic_ps7_S_AXI_ACP_to_s00_couplers_BREADY;
wire [1:0]axi_ic_ps7_S_AXI_ACP_to_s00_couplers_BRESP;
wire axi_ic_ps7_S_AXI_ACP_to_s00_couplers_BVALID;
wire [31:0]axi_ic_ps7_S_AXI_ACP_to_s00_couplers_RDATA;
wire axi_ic_ps7_S_AXI_ACP_to_s00_couplers_RLAST;
wire axi_ic_ps7_S_AXI_ACP_to_s00_couplers_RREADY;
wire [1:0]axi_ic_ps7_S_AXI_ACP_to_s00_couplers_RRESP;
wire axi_ic_ps7_S_AXI_ACP_to_s00_couplers_RVALID;
wire [31:0]axi_ic_ps7_S_AXI_ACP_to_s00_couplers_WDATA;
wire axi_ic_ps7_S_AXI_ACP_to_s00_couplers_WLAST;
wire axi_ic_ps7_S_AXI_ACP_to_s00_couplers_WREADY;
wire [3:0]axi_ic_ps7_S_AXI_ACP_to_s00_couplers_WSTRB;
wire axi_ic_ps7_S_AXI_ACP_to_s00_couplers_WVALID;
wire [31:0]axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARADDR;
wire [1:0]axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARBURST;
wire [3:0]axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARCACHE;
wire [7:0]axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARLEN;
wire [1:0]axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARLOCK;
wire [2:0]axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARPROT;
wire [3:0]axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARQOS;
wire axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARREADY;
wire [3:0]axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARREGION;
wire [2:0]axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARSIZE;
wire axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARVALID;
wire [31:0]axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWADDR;
wire [1:0]axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWBURST;
wire [3:0]axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWCACHE;
wire [7:0]axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWLEN;
wire [1:0]axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWLOCK;
wire [2:0]axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWPROT;
wire [3:0]axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWQOS;
wire axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWREADY;
wire [3:0]axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWREGION;
wire [2:0]axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWSIZE;
wire axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWVALID;
wire axi_ic_ps7_S_AXI_ACP_to_s01_couplers_BREADY;
wire [1:0]axi_ic_ps7_S_AXI_ACP_to_s01_couplers_BRESP;
wire axi_ic_ps7_S_AXI_ACP_to_s01_couplers_BVALID;
wire [31:0]axi_ic_ps7_S_AXI_ACP_to_s01_couplers_RDATA;
wire axi_ic_ps7_S_AXI_ACP_to_s01_couplers_RLAST;
wire axi_ic_ps7_S_AXI_ACP_to_s01_couplers_RREADY;
wire [1:0]axi_ic_ps7_S_AXI_ACP_to_s01_couplers_RRESP;
wire axi_ic_ps7_S_AXI_ACP_to_s01_couplers_RVALID;
wire [31:0]axi_ic_ps7_S_AXI_ACP_to_s01_couplers_WDATA;
wire axi_ic_ps7_S_AXI_ACP_to_s01_couplers_WLAST;
wire axi_ic_ps7_S_AXI_ACP_to_s01_couplers_WREADY;
wire [3:0]axi_ic_ps7_S_AXI_ACP_to_s01_couplers_WSTRB;
wire axi_ic_ps7_S_AXI_ACP_to_s01_couplers_WVALID;
wire [31:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARADDR;
wire [1:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARBURST;
wire [3:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARCACHE;
wire [0:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARID;
wire [3:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARLEN;
wire [1:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARLOCK;
wire [2:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARPROT;
wire [3:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARQOS;
wire m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARREADY;
wire [2:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARSIZE;
wire m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARVALID;
wire [31:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWADDR;
wire [1:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWBURST;
wire [3:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWCACHE;
wire [0:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWID;
wire [3:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWLEN;
wire [1:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWLOCK;
wire [2:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWPROT;
wire [3:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWQOS;
wire m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWREADY;
wire [2:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWSIZE;
wire m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWVALID;
wire [2:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_BID;
wire m00_couplers_to_axi_ic_ps7_S_AXI_ACP_BREADY;
wire [1:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_BRESP;
wire m00_couplers_to_axi_ic_ps7_S_AXI_ACP_BVALID;
wire [63:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_RDATA;
wire [2:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_RID;
wire m00_couplers_to_axi_ic_ps7_S_AXI_ACP_RLAST;
wire m00_couplers_to_axi_ic_ps7_S_AXI_ACP_RREADY;
wire [1:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_RRESP;
wire m00_couplers_to_axi_ic_ps7_S_AXI_ACP_RVALID;
wire [63:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_WDATA;
wire [0:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_WID;
wire m00_couplers_to_axi_ic_ps7_S_AXI_ACP_WLAST;
wire m00_couplers_to_axi_ic_ps7_S_AXI_ACP_WREADY;
wire [7:0]m00_couplers_to_axi_ic_ps7_S_AXI_ACP_WSTRB;
wire m00_couplers_to_axi_ic_ps7_S_AXI_ACP_WVALID;
wire [31:0]s00_couplers_to_xbar_ARADDR;
wire [1:0]s00_couplers_to_xbar_ARBURST;
wire [3:0]s00_couplers_to_xbar_ARCACHE;
wire [7:0]s00_couplers_to_xbar_ARLEN;
wire [0:0]s00_couplers_to_xbar_ARLOCK;
wire [2:0]s00_couplers_to_xbar_ARPROT;
wire [3:0]s00_couplers_to_xbar_ARQOS;
wire [0:0]s00_couplers_to_xbar_ARREADY;
wire [2:0]s00_couplers_to_xbar_ARSIZE;
wire s00_couplers_to_xbar_ARVALID;
wire [31:0]s00_couplers_to_xbar_AWADDR;
wire [1:0]s00_couplers_to_xbar_AWBURST;
wire [3:0]s00_couplers_to_xbar_AWCACHE;
wire [7:0]s00_couplers_to_xbar_AWLEN;
wire [0:0]s00_couplers_to_xbar_AWLOCK;
wire [2:0]s00_couplers_to_xbar_AWPROT;
wire [3:0]s00_couplers_to_xbar_AWQOS;
wire [0:0]s00_couplers_to_xbar_AWREADY;
wire [2:0]s00_couplers_to_xbar_AWSIZE;
wire s00_couplers_to_xbar_AWVALID;
wire s00_couplers_to_xbar_BREADY;
wire [1:0]s00_couplers_to_xbar_BRESP;
wire [0:0]s00_couplers_to_xbar_BVALID;
wire [63:0]s00_couplers_to_xbar_RDATA;
wire [0:0]s00_couplers_to_xbar_RLAST;
wire s00_couplers_to_xbar_RREADY;
wire [1:0]s00_couplers_to_xbar_RRESP;
wire [0:0]s00_couplers_to_xbar_RVALID;
wire [63:0]s00_couplers_to_xbar_WDATA;
wire s00_couplers_to_xbar_WLAST;
wire [0:0]s00_couplers_to_xbar_WREADY;
wire [7:0]s00_couplers_to_xbar_WSTRB;
wire s00_couplers_to_xbar_WVALID;
wire [31:0]s01_couplers_to_xbar_ARADDR;
wire [1:0]s01_couplers_to_xbar_ARBURST;
wire [3:0]s01_couplers_to_xbar_ARCACHE;
wire [7:0]s01_couplers_to_xbar_ARLEN;
wire [0:0]s01_couplers_to_xbar_ARLOCK;
wire [2:0]s01_couplers_to_xbar_ARPROT;
wire [3:0]s01_couplers_to_xbar_ARQOS;
wire [1:1]s01_couplers_to_xbar_ARREADY;
wire [2:0]s01_couplers_to_xbar_ARSIZE;
wire s01_couplers_to_xbar_ARVALID;
wire [31:0]s01_couplers_to_xbar_AWADDR;
wire [1:0]s01_couplers_to_xbar_AWBURST;
wire [3:0]s01_couplers_to_xbar_AWCACHE;
wire [7:0]s01_couplers_to_xbar_AWLEN;
wire [0:0]s01_couplers_to_xbar_AWLOCK;
wire [2:0]s01_couplers_to_xbar_AWPROT;
wire [3:0]s01_couplers_to_xbar_AWQOS;
wire [1:1]s01_couplers_to_xbar_AWREADY;
wire [2:0]s01_couplers_to_xbar_AWSIZE;
wire s01_couplers_to_xbar_AWVALID;
wire s01_couplers_to_xbar_BREADY;
wire [3:2]s01_couplers_to_xbar_BRESP;
wire [1:1]s01_couplers_to_xbar_BVALID;
wire [127:64]s01_couplers_to_xbar_RDATA;
wire [1:1]s01_couplers_to_xbar_RLAST;
wire s01_couplers_to_xbar_RREADY;
wire [3:2]s01_couplers_to_xbar_RRESP;
wire [1:1]s01_couplers_to_xbar_RVALID;
wire [63:0]s01_couplers_to_xbar_WDATA;
wire s01_couplers_to_xbar_WLAST;
wire [1:1]s01_couplers_to_xbar_WREADY;
wire [7:0]s01_couplers_to_xbar_WSTRB;
wire s01_couplers_to_xbar_WVALID;
wire [31:0]xbar_to_m00_couplers_ARADDR;
wire [1:0]xbar_to_m00_couplers_ARBURST;
wire [3:0]xbar_to_m00_couplers_ARCACHE;
wire [0:0]xbar_to_m00_couplers_ARID;
wire [7:0]xbar_to_m00_couplers_ARLEN;
wire [0:0]xbar_to_m00_couplers_ARLOCK;
wire [2:0]xbar_to_m00_couplers_ARPROT;
wire [3:0]xbar_to_m00_couplers_ARQOS;
wire xbar_to_m00_couplers_ARREADY;
wire [3:0]xbar_to_m00_couplers_ARREGION;
wire [2:0]xbar_to_m00_couplers_ARSIZE;
wire [0:0]xbar_to_m00_couplers_ARVALID;
wire [31:0]xbar_to_m00_couplers_AWADDR;
wire [1:0]xbar_to_m00_couplers_AWBURST;
wire [3:0]xbar_to_m00_couplers_AWCACHE;
wire [0:0]xbar_to_m00_couplers_AWID;
wire [7:0]xbar_to_m00_couplers_AWLEN;
wire [0:0]xbar_to_m00_couplers_AWLOCK;
wire [2:0]xbar_to_m00_couplers_AWPROT;
wire [3:0]xbar_to_m00_couplers_AWQOS;
wire xbar_to_m00_couplers_AWREADY;
wire [3:0]xbar_to_m00_couplers_AWREGION;
wire [2:0]xbar_to_m00_couplers_AWSIZE;
wire [0:0]xbar_to_m00_couplers_AWVALID;
wire [0:0]xbar_to_m00_couplers_BID;
wire [0:0]xbar_to_m00_couplers_BREADY;
wire [1:0]xbar_to_m00_couplers_BRESP;
wire xbar_to_m00_couplers_BVALID;
wire [63:0]xbar_to_m00_couplers_RDATA;
wire [0:0]xbar_to_m00_couplers_RID;
wire xbar_to_m00_couplers_RLAST;
wire [0:0]xbar_to_m00_couplers_RREADY;
wire [1:0]xbar_to_m00_couplers_RRESP;
wire xbar_to_m00_couplers_RVALID;
wire [63:0]xbar_to_m00_couplers_WDATA;
wire [0:0]xbar_to_m00_couplers_WLAST;
wire xbar_to_m00_couplers_WREADY;
wire [7:0]xbar_to_m00_couplers_WSTRB;
wire [0:0]xbar_to_m00_couplers_WVALID;
assign M00_AXI_araddr[31:0] = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARADDR;
assign M00_AXI_arburst[1:0] = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARBURST;
assign M00_AXI_arcache[3:0] = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARCACHE;
assign M00_AXI_arid[0] = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARID;
assign M00_AXI_arlen[3:0] = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARLEN;
assign M00_AXI_arlock[1:0] = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARLOCK;
assign M00_AXI_arprot[2:0] = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARPROT;
assign M00_AXI_arqos[3:0] = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARQOS;
assign M00_AXI_arsize[2:0] = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARSIZE;
assign M00_AXI_arvalid = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARVALID;
assign M00_AXI_awaddr[31:0] = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWADDR;
assign M00_AXI_awburst[1:0] = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWBURST;
assign M00_AXI_awcache[3:0] = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWCACHE;
assign M00_AXI_awid[0] = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWID;
assign M00_AXI_awlen[3:0] = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWLEN;
assign M00_AXI_awlock[1:0] = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWLOCK;
assign M00_AXI_awprot[2:0] = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWPROT;
assign M00_AXI_awqos[3:0] = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWQOS;
assign M00_AXI_awsize[2:0] = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWSIZE;
assign M00_AXI_awvalid = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWVALID;
assign M00_AXI_bready = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_BREADY;
assign M00_AXI_rready = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_RREADY;
assign M00_AXI_wdata[63:0] = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_WDATA;
assign M00_AXI_wid[0] = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_WID;
assign M00_AXI_wlast = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_WLAST;
assign M00_AXI_wstrb[7:0] = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_WSTRB;
assign M00_AXI_wvalid = m00_couplers_to_axi_ic_ps7_S_AXI_ACP_WVALID;
assign S00_AXI_arready = axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARREADY;
assign S00_AXI_awready = axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWREADY;
assign S00_AXI_bresp[1:0] = axi_ic_ps7_S_AXI_ACP_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = axi_ic_ps7_S_AXI_ACP_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = axi_ic_ps7_S_AXI_ACP_to_s00_couplers_RDATA;
assign S00_AXI_rlast = axi_ic_ps7_S_AXI_ACP_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = axi_ic_ps7_S_AXI_ACP_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = axi_ic_ps7_S_AXI_ACP_to_s00_couplers_RVALID;
assign S00_AXI_wready = axi_ic_ps7_S_AXI_ACP_to_s00_couplers_WREADY;
assign S01_AXI_arready = axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARREADY;
assign S01_AXI_awready = axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWREADY;
assign S01_AXI_bresp[1:0] = axi_ic_ps7_S_AXI_ACP_to_s01_couplers_BRESP;
assign S01_AXI_bvalid = axi_ic_ps7_S_AXI_ACP_to_s01_couplers_BVALID;
assign S01_AXI_rdata[31:0] = axi_ic_ps7_S_AXI_ACP_to_s01_couplers_RDATA;
assign S01_AXI_rlast = axi_ic_ps7_S_AXI_ACP_to_s01_couplers_RLAST;
assign S01_AXI_rresp[1:0] = axi_ic_ps7_S_AXI_ACP_to_s01_couplers_RRESP;
assign S01_AXI_rvalid = axi_ic_ps7_S_AXI_ACP_to_s01_couplers_RVALID;
assign S01_AXI_wready = axi_ic_ps7_S_AXI_ACP_to_s01_couplers_WREADY;
assign axi_ic_ps7_S_AXI_ACP_ACLK_net = ACLK;
assign axi_ic_ps7_S_AXI_ACP_ARESETN_net = ARESETN[0];
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARLEN = S00_AXI_arlen[7:0];
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARREGION = S00_AXI_arregion[3:0];
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWLEN = S00_AXI_awlen[7:0];
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWREGION = S00_AXI_awregion[3:0];
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_BREADY = S00_AXI_bready;
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_RREADY = S00_AXI_rready;
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_WLAST = S00_AXI_wlast;
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign axi_ic_ps7_S_AXI_ACP_to_s00_couplers_WVALID = S00_AXI_wvalid;
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARADDR = S01_AXI_araddr[31:0];
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARBURST = S01_AXI_arburst[1:0];
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARCACHE = S01_AXI_arcache[3:0];
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARLEN = S01_AXI_arlen[7:0];
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARLOCK = S01_AXI_arlock[1:0];
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARPROT = S01_AXI_arprot[2:0];
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARQOS = S01_AXI_arqos[3:0];
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARREGION = S01_AXI_arregion[3:0];
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARSIZE = S01_AXI_arsize[2:0];
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARVALID = S01_AXI_arvalid;
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWADDR = S01_AXI_awaddr[31:0];
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWBURST = S01_AXI_awburst[1:0];
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWCACHE = S01_AXI_awcache[3:0];
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWLEN = S01_AXI_awlen[7:0];
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWLOCK = S01_AXI_awlock[1:0];
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWPROT = S01_AXI_awprot[2:0];
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWQOS = S01_AXI_awqos[3:0];
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWREGION = S01_AXI_awregion[3:0];
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWSIZE = S01_AXI_awsize[2:0];
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWVALID = S01_AXI_awvalid;
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_BREADY = S01_AXI_bready;
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_RREADY = S01_AXI_rready;
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_WDATA = S01_AXI_wdata[31:0];
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_WLAST = S01_AXI_wlast;
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_WSTRB = S01_AXI_wstrb[3:0];
assign axi_ic_ps7_S_AXI_ACP_to_s01_couplers_WVALID = S01_AXI_wvalid;
assign m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARREADY = M00_AXI_arready;
assign m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWREADY = M00_AXI_awready;
assign m00_couplers_to_axi_ic_ps7_S_AXI_ACP_BID = M00_AXI_bid[2:0];
assign m00_couplers_to_axi_ic_ps7_S_AXI_ACP_BRESP = M00_AXI_bresp[1:0];
assign m00_couplers_to_axi_ic_ps7_S_AXI_ACP_BVALID = M00_AXI_bvalid;
assign m00_couplers_to_axi_ic_ps7_S_AXI_ACP_RDATA = M00_AXI_rdata[63:0];
assign m00_couplers_to_axi_ic_ps7_S_AXI_ACP_RID = M00_AXI_rid[2:0];
assign m00_couplers_to_axi_ic_ps7_S_AXI_ACP_RLAST = M00_AXI_rlast;
assign m00_couplers_to_axi_ic_ps7_S_AXI_ACP_RRESP = M00_AXI_rresp[1:0];
assign m00_couplers_to_axi_ic_ps7_S_AXI_ACP_RVALID = M00_AXI_rvalid;
assign m00_couplers_to_axi_ic_ps7_S_AXI_ACP_WREADY = M00_AXI_wready;
m00_couplers_imp_F6WOYG m00_couplers
(.M_ACLK(axi_ic_ps7_S_AXI_ACP_ACLK_net),
.M_ARESETN(axi_ic_ps7_S_AXI_ACP_ARESETN_net),
.M_AXI_araddr(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARADDR),
.M_AXI_arburst(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARBURST),
.M_AXI_arcache(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARCACHE),
.M_AXI_arid(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARID),
.M_AXI_arlen(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARLEN),
.M_AXI_arlock(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARLOCK),
.M_AXI_arprot(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARPROT),
.M_AXI_arqos(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARQOS),
.M_AXI_arready(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARREADY),
.M_AXI_arsize(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARSIZE),
.M_AXI_arvalid(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_ARVALID),
.M_AXI_awaddr(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWADDR),
.M_AXI_awburst(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWBURST),
.M_AXI_awcache(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWCACHE),
.M_AXI_awid(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWID),
.M_AXI_awlen(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWLEN),
.M_AXI_awlock(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWLOCK),
.M_AXI_awprot(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWPROT),
.M_AXI_awqos(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWQOS),
.M_AXI_awready(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWREADY),
.M_AXI_awsize(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWSIZE),
.M_AXI_awvalid(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_AWVALID),
.M_AXI_bid(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_BID),
.M_AXI_bready(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_BREADY),
.M_AXI_bresp(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_BRESP),
.M_AXI_bvalid(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_BVALID),
.M_AXI_rdata(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_RDATA),
.M_AXI_rid(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_RID),
.M_AXI_rlast(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_RLAST),
.M_AXI_rready(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_RREADY),
.M_AXI_rresp(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_RRESP),
.M_AXI_rvalid(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_RVALID),
.M_AXI_wdata(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_WDATA),
.M_AXI_wid(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_WID),
.M_AXI_wlast(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_WLAST),
.M_AXI_wready(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_WREADY),
.M_AXI_wstrb(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_WSTRB),
.M_AXI_wvalid(m00_couplers_to_axi_ic_ps7_S_AXI_ACP_WVALID),
.S_ACLK(axi_ic_ps7_S_AXI_ACP_ACLK_net),
.S_ARESETN(axi_ic_ps7_S_AXI_ACP_ARESETN_net),
.S_AXI_araddr(xbar_to_m00_couplers_ARADDR),
.S_AXI_arburst(xbar_to_m00_couplers_ARBURST),
.S_AXI_arcache(xbar_to_m00_couplers_ARCACHE),
.S_AXI_arid(xbar_to_m00_couplers_ARID),
.S_AXI_arlen(xbar_to_m00_couplers_ARLEN),
.S_AXI_arlock(xbar_to_m00_couplers_ARLOCK),
.S_AXI_arprot(xbar_to_m00_couplers_ARPROT),
.S_AXI_arqos(xbar_to_m00_couplers_ARQOS),
.S_AXI_arready(xbar_to_m00_couplers_ARREADY),
.S_AXI_arregion(xbar_to_m00_couplers_ARREGION),
.S_AXI_arsize(xbar_to_m00_couplers_ARSIZE),
.S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m00_couplers_AWADDR),
.S_AXI_awburst(xbar_to_m00_couplers_AWBURST),
.S_AXI_awcache(xbar_to_m00_couplers_AWCACHE),
.S_AXI_awid(xbar_to_m00_couplers_AWID),
.S_AXI_awlen(xbar_to_m00_couplers_AWLEN),
.S_AXI_awlock(xbar_to_m00_couplers_AWLOCK),
.S_AXI_awprot(xbar_to_m00_couplers_AWPROT),
.S_AXI_awqos(xbar_to_m00_couplers_AWQOS),
.S_AXI_awready(xbar_to_m00_couplers_AWREADY),
.S_AXI_awregion(xbar_to_m00_couplers_AWREGION),
.S_AXI_awsize(xbar_to_m00_couplers_AWSIZE),
.S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),
.S_AXI_bid(xbar_to_m00_couplers_BID),
.S_AXI_bready(xbar_to_m00_couplers_BREADY),
.S_AXI_bresp(xbar_to_m00_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m00_couplers_BVALID),
.S_AXI_rdata(xbar_to_m00_couplers_RDATA),
.S_AXI_rid(xbar_to_m00_couplers_RID),
.S_AXI_rlast(xbar_to_m00_couplers_RLAST),
.S_AXI_rready(xbar_to_m00_couplers_RREADY),
.S_AXI_rresp(xbar_to_m00_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m00_couplers_RVALID),
.S_AXI_wdata(xbar_to_m00_couplers_WDATA),
.S_AXI_wlast(xbar_to_m00_couplers_WLAST),
.S_AXI_wready(xbar_to_m00_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m00_couplers_WVALID));
s00_couplers_imp_QU0DDF s00_couplers
(.M_ACLK(axi_ic_ps7_S_AXI_ACP_ACLK_net),
.M_ARESETN(axi_ic_ps7_S_AXI_ACP_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_xbar_ARADDR),
.M_AXI_arburst(s00_couplers_to_xbar_ARBURST),
.M_AXI_arcache(s00_couplers_to_xbar_ARCACHE),
.M_AXI_arlen(s00_couplers_to_xbar_ARLEN),
.M_AXI_arlock(s00_couplers_to_xbar_ARLOCK),
.M_AXI_arprot(s00_couplers_to_xbar_ARPROT),
.M_AXI_arqos(s00_couplers_to_xbar_ARQOS),
.M_AXI_arready(s00_couplers_to_xbar_ARREADY),
.M_AXI_arsize(s00_couplers_to_xbar_ARSIZE),
.M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),
.M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),
.M_AXI_awburst(s00_couplers_to_xbar_AWBURST),
.M_AXI_awcache(s00_couplers_to_xbar_AWCACHE),
.M_AXI_awlen(s00_couplers_to_xbar_AWLEN),
.M_AXI_awlock(s00_couplers_to_xbar_AWLOCK),
.M_AXI_awprot(s00_couplers_to_xbar_AWPROT),
.M_AXI_awqos(s00_couplers_to_xbar_AWQOS),
.M_AXI_awready(s00_couplers_to_xbar_AWREADY),
.M_AXI_awsize(s00_couplers_to_xbar_AWSIZE),
.M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),
.M_AXI_bready(s00_couplers_to_xbar_BREADY),
.M_AXI_bresp(s00_couplers_to_xbar_BRESP),
.M_AXI_bvalid(s00_couplers_to_xbar_BVALID),
.M_AXI_rdata(s00_couplers_to_xbar_RDATA),
.M_AXI_rlast(s00_couplers_to_xbar_RLAST),
.M_AXI_rready(s00_couplers_to_xbar_RREADY),
.M_AXI_rresp(s00_couplers_to_xbar_RRESP),
.M_AXI_rvalid(s00_couplers_to_xbar_RVALID),
.M_AXI_wdata(s00_couplers_to_xbar_WDATA),
.M_AXI_wlast(s00_couplers_to_xbar_WLAST),
.M_AXI_wready(s00_couplers_to_xbar_WREADY),
.M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),
.M_AXI_wvalid(s00_couplers_to_xbar_WVALID),
.S_ACLK(axi_ic_ps7_S_AXI_ACP_ACLK_net),
.S_ARESETN(axi_ic_ps7_S_AXI_ACP_ARESETN_net),
.S_AXI_araddr(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARADDR),
.S_AXI_arburst(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARBURST),
.S_AXI_arcache(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARCACHE),
.S_AXI_arlen(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARLEN),
.S_AXI_arlock(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARLOCK),
.S_AXI_arprot(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARPROT),
.S_AXI_arqos(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARQOS),
.S_AXI_arready(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARREADY),
.S_AXI_arregion(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARREGION),
.S_AXI_arsize(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_ARVALID),
.S_AXI_awaddr(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWADDR),
.S_AXI_awburst(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWBURST),
.S_AXI_awcache(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWCACHE),
.S_AXI_awlen(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWLEN),
.S_AXI_awlock(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWLOCK),
.S_AXI_awprot(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWPROT),
.S_AXI_awqos(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWQOS),
.S_AXI_awready(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWREADY),
.S_AXI_awregion(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWREGION),
.S_AXI_awsize(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_AWVALID),
.S_AXI_bready(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_BREADY),
.S_AXI_bresp(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_BRESP),
.S_AXI_bvalid(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_BVALID),
.S_AXI_rdata(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_RDATA),
.S_AXI_rlast(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_RLAST),
.S_AXI_rready(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_RREADY),
.S_AXI_rresp(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_RRESP),
.S_AXI_rvalid(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_RVALID),
.S_AXI_wdata(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_WDATA),
.S_AXI_wlast(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_WLAST),
.S_AXI_wready(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_WREADY),
.S_AXI_wstrb(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_WSTRB),
.S_AXI_wvalid(axi_ic_ps7_S_AXI_ACP_to_s00_couplers_WVALID));
s01_couplers_imp_1OALJYZ s01_couplers
(.M_ACLK(axi_ic_ps7_S_AXI_ACP_ACLK_net),
.M_ARESETN(axi_ic_ps7_S_AXI_ACP_ARESETN_net),
.M_AXI_araddr(s01_couplers_to_xbar_ARADDR),
.M_AXI_arburst(s01_couplers_to_xbar_ARBURST),
.M_AXI_arcache(s01_couplers_to_xbar_ARCACHE),
.M_AXI_arlen(s01_couplers_to_xbar_ARLEN),
.M_AXI_arlock(s01_couplers_to_xbar_ARLOCK),
.M_AXI_arprot(s01_couplers_to_xbar_ARPROT),
.M_AXI_arqos(s01_couplers_to_xbar_ARQOS),
.M_AXI_arready(s01_couplers_to_xbar_ARREADY),
.M_AXI_arsize(s01_couplers_to_xbar_ARSIZE),
.M_AXI_arvalid(s01_couplers_to_xbar_ARVALID),
.M_AXI_awaddr(s01_couplers_to_xbar_AWADDR),
.M_AXI_awburst(s01_couplers_to_xbar_AWBURST),
.M_AXI_awcache(s01_couplers_to_xbar_AWCACHE),
.M_AXI_awlen(s01_couplers_to_xbar_AWLEN),
.M_AXI_awlock(s01_couplers_to_xbar_AWLOCK),
.M_AXI_awprot(s01_couplers_to_xbar_AWPROT),
.M_AXI_awqos(s01_couplers_to_xbar_AWQOS),
.M_AXI_awready(s01_couplers_to_xbar_AWREADY),
.M_AXI_awsize(s01_couplers_to_xbar_AWSIZE),
.M_AXI_awvalid(s01_couplers_to_xbar_AWVALID),
.M_AXI_bready(s01_couplers_to_xbar_BREADY),
.M_AXI_bresp(s01_couplers_to_xbar_BRESP),
.M_AXI_bvalid(s01_couplers_to_xbar_BVALID),
.M_AXI_rdata(s01_couplers_to_xbar_RDATA),
.M_AXI_rlast(s01_couplers_to_xbar_RLAST),
.M_AXI_rready(s01_couplers_to_xbar_RREADY),
.M_AXI_rresp(s01_couplers_to_xbar_RRESP),
.M_AXI_rvalid(s01_couplers_to_xbar_RVALID),
.M_AXI_wdata(s01_couplers_to_xbar_WDATA),
.M_AXI_wlast(s01_couplers_to_xbar_WLAST),
.M_AXI_wready(s01_couplers_to_xbar_WREADY),
.M_AXI_wstrb(s01_couplers_to_xbar_WSTRB),
.M_AXI_wvalid(s01_couplers_to_xbar_WVALID),
.S_ACLK(axi_ic_ps7_S_AXI_ACP_ACLK_net),
.S_ARESETN(axi_ic_ps7_S_AXI_ACP_ARESETN_net),
.S_AXI_araddr(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARADDR),
.S_AXI_arburst(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARBURST),
.S_AXI_arcache(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARCACHE),
.S_AXI_arlen(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARLEN),
.S_AXI_arlock(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARLOCK),
.S_AXI_arprot(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARPROT),
.S_AXI_arqos(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARQOS),
.S_AXI_arready(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARREADY),
.S_AXI_arregion(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARREGION),
.S_AXI_arsize(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARSIZE),
.S_AXI_arvalid(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_ARVALID),
.S_AXI_awaddr(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWADDR),
.S_AXI_awburst(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWBURST),
.S_AXI_awcache(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWCACHE),
.S_AXI_awlen(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWLEN),
.S_AXI_awlock(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWLOCK),
.S_AXI_awprot(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWPROT),
.S_AXI_awqos(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWQOS),
.S_AXI_awready(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWREADY),
.S_AXI_awregion(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWREGION),
.S_AXI_awsize(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWSIZE),
.S_AXI_awvalid(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_AWVALID),
.S_AXI_bready(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_BREADY),
.S_AXI_bresp(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_BRESP),
.S_AXI_bvalid(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_BVALID),
.S_AXI_rdata(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_RDATA),
.S_AXI_rlast(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_RLAST),
.S_AXI_rready(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_RREADY),
.S_AXI_rresp(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_RRESP),
.S_AXI_rvalid(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_RVALID),
.S_AXI_wdata(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_WDATA),
.S_AXI_wlast(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_WLAST),
.S_AXI_wready(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_WREADY),
.S_AXI_wstrb(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_WSTRB),
.S_AXI_wvalid(axi_ic_ps7_S_AXI_ACP_to_s01_couplers_WVALID));
zc702_xbar_1 xbar
(.aclk(axi_ic_ps7_S_AXI_ACP_ACLK_net),
.aresetn(axi_ic_ps7_S_AXI_ACP_ARESETN_net),
.m_axi_araddr(xbar_to_m00_couplers_ARADDR),
.m_axi_arburst(xbar_to_m00_couplers_ARBURST),
.m_axi_arcache(xbar_to_m00_couplers_ARCACHE),
.m_axi_arid(xbar_to_m00_couplers_ARID),
.m_axi_arlen(xbar_to_m00_couplers_ARLEN),
.m_axi_arlock(xbar_to_m00_couplers_ARLOCK),
.m_axi_arprot(xbar_to_m00_couplers_ARPROT),
.m_axi_arqos(xbar_to_m00_couplers_ARQOS),
.m_axi_arready(xbar_to_m00_couplers_ARREADY),
.m_axi_arregion(xbar_to_m00_couplers_ARREGION),
.m_axi_arsize(xbar_to_m00_couplers_ARSIZE),
.m_axi_arvalid(xbar_to_m00_couplers_ARVALID),
.m_axi_awaddr(xbar_to_m00_couplers_AWADDR),
.m_axi_awburst(xbar_to_m00_couplers_AWBURST),
.m_axi_awcache(xbar_to_m00_couplers_AWCACHE),
.m_axi_awid(xbar_to_m00_couplers_AWID),
.m_axi_awlen(xbar_to_m00_couplers_AWLEN),
.m_axi_awlock(xbar_to_m00_couplers_AWLOCK),
.m_axi_awprot(xbar_to_m00_couplers_AWPROT),
.m_axi_awqos(xbar_to_m00_couplers_AWQOS),
.m_axi_awready(xbar_to_m00_couplers_AWREADY),
.m_axi_awregion(xbar_to_m00_couplers_AWREGION),
.m_axi_awsize(xbar_to_m00_couplers_AWSIZE),
.m_axi_awvalid(xbar_to_m00_couplers_AWVALID),
.m_axi_bid(xbar_to_m00_couplers_BID),
.m_axi_bready(xbar_to_m00_couplers_BREADY),
.m_axi_bresp(xbar_to_m00_couplers_BRESP),
.m_axi_bvalid(xbar_to_m00_couplers_BVALID),
.m_axi_rdata(xbar_to_m00_couplers_RDATA),
.m_axi_rid(xbar_to_m00_couplers_RID),
.m_axi_rlast(xbar_to_m00_couplers_RLAST),
.m_axi_rready(xbar_to_m00_couplers_RREADY),
.m_axi_rresp(xbar_to_m00_couplers_RRESP),
.m_axi_rvalid(xbar_to_m00_couplers_RVALID),
.m_axi_wdata(xbar_to_m00_couplers_WDATA),
.m_axi_wlast(xbar_to_m00_couplers_WLAST),
.m_axi_wready(xbar_to_m00_couplers_WREADY),
.m_axi_wstrb(xbar_to_m00_couplers_WSTRB),
.m_axi_wvalid(xbar_to_m00_couplers_WVALID),
.s_axi_araddr({s01_couplers_to_xbar_ARADDR,s00_couplers_to_xbar_ARADDR}),
.s_axi_arburst({s01_couplers_to_xbar_ARBURST,s00_couplers_to_xbar_ARBURST}),
.s_axi_arcache({s01_couplers_to_xbar_ARCACHE,s00_couplers_to_xbar_ARCACHE}),
.s_axi_arid({1'b0,1'b0}),
.s_axi_arlen({s01_couplers_to_xbar_ARLEN,s00_couplers_to_xbar_ARLEN}),
.s_axi_arlock({s01_couplers_to_xbar_ARLOCK,s00_couplers_to_xbar_ARLOCK}),
.s_axi_arprot({s01_couplers_to_xbar_ARPROT,s00_couplers_to_xbar_ARPROT}),
.s_axi_arqos({s01_couplers_to_xbar_ARQOS,s00_couplers_to_xbar_ARQOS}),
.s_axi_arready({s01_couplers_to_xbar_ARREADY,s00_couplers_to_xbar_ARREADY}),
.s_axi_arsize({s01_couplers_to_xbar_ARSIZE,s00_couplers_to_xbar_ARSIZE}),
.s_axi_arvalid({s01_couplers_to_xbar_ARVALID,s00_couplers_to_xbar_ARVALID}),
.s_axi_awaddr({s01_couplers_to_xbar_AWADDR,s00_couplers_to_xbar_AWADDR}),
.s_axi_awburst({s01_couplers_to_xbar_AWBURST,s00_couplers_to_xbar_AWBURST}),
.s_axi_awcache({s01_couplers_to_xbar_AWCACHE,s00_couplers_to_xbar_AWCACHE}),
.s_axi_awid({1'b0,1'b0}),
.s_axi_awlen({s01_couplers_to_xbar_AWLEN,s00_couplers_to_xbar_AWLEN}),
.s_axi_awlock({s01_couplers_to_xbar_AWLOCK,s00_couplers_to_xbar_AWLOCK}),
.s_axi_awprot({s01_couplers_to_xbar_AWPROT,s00_couplers_to_xbar_AWPROT}),
.s_axi_awqos({s01_couplers_to_xbar_AWQOS,s00_couplers_to_xbar_AWQOS}),
.s_axi_awready({s01_couplers_to_xbar_AWREADY,s00_couplers_to_xbar_AWREADY}),
.s_axi_awsize({s01_couplers_to_xbar_AWSIZE,s00_couplers_to_xbar_AWSIZE}),
.s_axi_awvalid({s01_couplers_to_xbar_AWVALID,s00_couplers_to_xbar_AWVALID}),
.s_axi_bready({s01_couplers_to_xbar_BREADY,s00_couplers_to_xbar_BREADY}),
.s_axi_bresp({s01_couplers_to_xbar_BRESP,s00_couplers_to_xbar_BRESP}),
.s_axi_bvalid({s01_couplers_to_xbar_BVALID,s00_couplers_to_xbar_BVALID}),
.s_axi_rdata({s01_couplers_to_xbar_RDATA,s00_couplers_to_xbar_RDATA}),
.s_axi_rlast({s01_couplers_to_xbar_RLAST,s00_couplers_to_xbar_RLAST}),
.s_axi_rready({s01_couplers_to_xbar_RREADY,s00_couplers_to_xbar_RREADY}),
.s_axi_rresp({s01_couplers_to_xbar_RRESP,s00_couplers_to_xbar_RRESP}),
.s_axi_rvalid({s01_couplers_to_xbar_RVALID,s00_couplers_to_xbar_RVALID}),
.s_axi_wdata({s01_couplers_to_xbar_WDATA,s00_couplers_to_xbar_WDATA}),
.s_axi_wlast({s01_couplers_to_xbar_WLAST,s00_couplers_to_xbar_WLAST}),
.s_axi_wready({s01_couplers_to_xbar_WREADY,s00_couplers_to_xbar_WREADY}),
.s_axi_wstrb({s01_couplers_to_xbar_WSTRB,s00_couplers_to_xbar_WSTRB}),
.s_axi_wvalid({s01_couplers_to_xbar_WVALID,s00_couplers_to_xbar_WVALID}));
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Tue Jun 06 02:45:50 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/system_vga_pll_0_0_sim_netlist.v
// Design : system_vga_pll_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_vga_pll_0_0,vga_pll,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "vga_pll,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_vga_pll_0_0
(clk_100,
clk_50,
clk_25,
clk_12_5,
clk_6_25);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_100 CLK" *) input clk_100;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_50 CLK" *) output clk_50;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_25 CLK" *) output clk_25;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_12_5 CLK" *) output clk_12_5;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_6_25 CLK" *) output clk_6_25;
wire clk_100;
wire clk_12_5;
wire clk_25;
wire clk_50;
wire clk_6_25;
system_vga_pll_0_0_vga_pll U0
(.clk_100(clk_100),
.clk_12_5(clk_12_5),
.clk_25(clk_25),
.clk_50(clk_50),
.clk_6_25(clk_6_25));
endmodule
(* ORIG_REF_NAME = "vga_pll" *)
module system_vga_pll_0_0_vga_pll
(clk_50,
clk_25,
clk_12_5,
clk_6_25,
clk_100);
output clk_50;
output clk_25;
output clk_12_5;
output clk_6_25;
input clk_100;
wire clk_100;
wire clk_12_5;
wire clk_12_5_s_i_1_n_0;
wire clk_25;
wire clk_25_s_i_1_n_0;
wire clk_50;
wire clk_6_25;
wire clk_6_25_s_i_1_n_0;
wire p_0_in;
LUT1 #(
.INIT(2'h1))
clk_12_5_s_i_1
(.I0(clk_12_5),
.O(clk_12_5_s_i_1_n_0));
FDRE #(
.INIT(1'b0))
clk_12_5_s_reg
(.C(clk_25),
.CE(1'b1),
.D(clk_12_5_s_i_1_n_0),
.Q(clk_12_5),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
clk_25_s_i_1
(.I0(clk_25),
.O(clk_25_s_i_1_n_0));
FDRE #(
.INIT(1'b0))
clk_25_s_reg
(.C(clk_50),
.CE(1'b1),
.D(clk_25_s_i_1_n_0),
.Q(clk_25),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
clk_50_s_i_1
(.I0(clk_50),
.O(p_0_in));
FDRE #(
.INIT(1'b0))
clk_50_s_reg
(.C(clk_100),
.CE(1'b1),
.D(p_0_in),
.Q(clk_50),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
clk_6_25_s_i_1
(.I0(clk_6_25),
.O(clk_6_25_s_i_1_n_0));
FDRE #(
.INIT(1'b0))
clk_6_25_s_reg
(.C(clk_6_25),
.CE(1'b1),
.D(clk_6_25_s_i_1_n_0),
.Q(clk_6_25),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* bsg_cache_to_test_dram.v
*
* multiple caches can attach here and connect to one test dram channel.
*
* @author tommy
*
*/
`include "bsg_defines.v"
`include "bsg_cache.vh"
module bsg_cache_to_test_dram
import bsg_cache_pkg::*;
#(parameter `BSG_INV_PARAM(num_cache_p)
, parameter `BSG_INV_PARAM(addr_width_p) // cache addr (byte)
, parameter `BSG_INV_PARAM(data_width_p) // cache data width
, parameter `BSG_INV_PARAM(block_size_in_words_p) // cache block_size (word)
, parameter `BSG_INV_PARAM(cache_bank_addr_width_p) // actual number of bits used for address (byte)
, parameter `BSG_INV_PARAM(dram_channel_addr_width_p) // dram channel addr
, parameter `BSG_INV_PARAM(dram_data_width_p) // dram channel data width
, parameter dma_data_width_p=data_width_p // cache dma data width
, parameter num_req_lp = (block_size_in_words_p*data_width_p/dram_data_width_p) // number of DRAM requests sent per cache miss.
, parameter lg_num_req_lp = `BSG_SAFE_CLOG2(num_req_lp)
, parameter dram_byte_offset_width_lp = `BSG_SAFE_CLOG2(dram_data_width_p>>3)
, parameter lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p)
, parameter dma_pkt_width_lp=`bsg_cache_dma_pkt_width(addr_width_p)
)
(
// vcache dma interface
input core_clk_i
, input core_reset_i
, input [num_cache_p-1:0][dma_pkt_width_lp-1:0] dma_pkt_i
, input [num_cache_p-1:0] dma_pkt_v_i
, output logic [num_cache_p-1:0] dma_pkt_yumi_o
, output logic [num_cache_p-1:0][dma_data_width_p-1:0] dma_data_o
, output logic [num_cache_p-1:0] dma_data_v_o
, input [num_cache_p-1:0] dma_data_ready_i
, input [num_cache_p-1:0][dma_data_width_p-1:0] dma_data_i
, input [num_cache_p-1:0] dma_data_v_i
, output logic [num_cache_p-1:0] dma_data_yumi_o
// dram
, input dram_clk_i
, input dram_reset_i
// dram request channel (valid-yumi)
, output logic dram_req_v_o
, output logic dram_write_not_read_o
, output logic [dram_channel_addr_width_p-1:0] dram_ch_addr_o // read done addr
, input dram_req_yumi_i
// dram write data channel (valid-yumi)
, output logic dram_data_v_o
, output logic [dram_data_width_p-1:0] dram_data_o
, input dram_data_yumi_i
// dram read data channel (valid-only)
, input dram_data_v_i
, input [dram_data_width_p-1:0] dram_data_i
, input [dram_channel_addr_width_p-1:0] dram_ch_addr_i // the address of incoming data
);
// dma pkt
//
`declare_bsg_cache_dma_pkt_s(addr_width_p);
bsg_cache_dma_pkt_s [num_cache_p-1:0] dma_pkt;
assign dma_pkt = dma_pkt_i;
// request round robin
//
logic rr_v_lo;
logic rr_yumi_li;
bsg_cache_dma_pkt_s rr_dma_pkt_lo;
logic [lg_num_cache_lp-1:0] rr_tag_lo;
logic [lg_num_cache_lp-1:0] rr_tag_r, rr_tag_n;
bsg_cache_dma_pkt_s dma_pkt_r, dma_pkt_n;
bsg_round_robin_n_to_1 #(
.width_p(dma_pkt_width_lp)
,.num_in_p(num_cache_p)
,.strict_p(0)
,.use_scan_p(1)
) rr0 (
.clk_i(core_clk_i)
,.reset_i(core_reset_i)
,.data_i(dma_pkt)
,.v_i(dma_pkt_v_i)
,.yumi_o(dma_pkt_yumi_o)
,.v_o(rr_v_lo)
,.data_o(rr_dma_pkt_lo)
,.tag_o(rr_tag_lo)
,.yumi_i(rr_yumi_li)
);
logic counter_clear;
logic counter_up;
logic [lg_num_req_lp-1:0] count_r; // this counts the number of DRAM requests sent.
bsg_counter_clear_up #(
.max_val_p(num_req_lp-1)
,.init_val_p(0)
) ccu0 (
.clk_i(core_clk_i)
,.reset_i(core_reset_i)
,.clear_i(counter_clear)
,.up_i(counter_up)
,.count_o(count_r)
);
logic [dram_channel_addr_width_p-1:0] dram_req_addr;
// request async fifo
//
logic req_afifo_enq;
logic req_afifo_full;
bsg_async_fifo #(
.lg_size_p(`BSG_SAFE_CLOG2(4*num_cache_p))
,.width_p(1+dram_channel_addr_width_p)
) req_afifo (
.w_clk_i(core_clk_i)
,.w_reset_i(core_reset_i)
,.w_enq_i(req_afifo_enq)
,.w_data_i({dma_pkt_n.write_not_read, dram_req_addr})
,.w_full_o(req_afifo_full)
,.r_clk_i(dram_clk_i)
,.r_reset_i(dram_reset_i)
,.r_deq_i(dram_req_yumi_i)
,.r_data_o({dram_write_not_read_o, dram_ch_addr_o})
,.r_valid_o(dram_req_v_o)
);
// RX
//
bsg_cache_to_test_dram_rx #(
.num_cache_p(num_cache_p)
,.data_width_p(data_width_p)
,.dma_data_width_p(dma_data_width_p)
,.dram_data_width_p(dram_data_width_p)
,.dram_channel_addr_width_p(dram_channel_addr_width_p)
,.block_size_in_words_p(block_size_in_words_p)
) rx0 (
.core_clk_i(core_clk_i)
,.core_reset_i(core_reset_i)
,.dma_data_o(dma_data_o)
,.dma_data_v_o(dma_data_v_o)
,.dma_data_ready_i(dma_data_ready_i)
,.dram_clk_i(dram_clk_i)
,.dram_reset_i(dram_reset_i)
,.dram_data_v_i(dram_data_v_i)
,.dram_data_i(dram_data_i)
,.dram_ch_addr_i(dram_ch_addr_i)
);
// TX
//
logic tx_v_li;
logic tx_ready_lo;
bsg_cache_to_test_dram_tx #(
.num_cache_p(num_cache_p)
,.data_width_p(data_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.dma_data_width_p(dma_data_width_p)
,.dram_data_width_p(dram_data_width_p)
) tx0 (
.core_clk_i(core_clk_i)
,.core_reset_i(core_reset_i)
,.v_i(tx_v_li)
,.tag_i(rr_tag_n)
,.ready_o(tx_ready_lo)
,.dma_data_i(dma_data_i)
,.dma_data_v_i(dma_data_v_i)
,.dma_data_yumi_o(dma_data_yumi_o)
,.dram_clk_i(dram_clk_i)
,.dram_reset_i(dram_reset_i)
,.dram_data_v_o(dram_data_v_o)
,.dram_data_o(dram_data_o)
,.dram_data_yumi_i(dram_data_yumi_i)
);
if (num_req_lp == 1) begin
assign counter_up = 1'b0;
assign counter_clear = 1'b0;
assign rr_yumi_li = rr_v_lo & ~req_afifo_full & (rr_dma_pkt_lo.write_not_read ? tx_ready_lo : 1'b1);
assign req_afifo_enq = rr_v_lo & ~req_afifo_full & (rr_dma_pkt_lo.write_not_read ? tx_ready_lo : 1'b1);
assign tx_v_li = rr_v_lo & ~req_afifo_full & rr_dma_pkt_lo.write_not_read & tx_ready_lo;
assign rr_tag_n = rr_tag_lo;
assign dma_pkt_n = rr_dma_pkt_lo;
end
else begin
always_comb begin
counter_up = 1'b0;
counter_clear = 1'b0;
rr_yumi_li = 1'b0;
req_afifo_enq = 1'b0;
tx_v_li = 1'b0;
rr_tag_n = rr_tag_r;
dma_pkt_n = dma_pkt_r;
if (count_r == 0) begin
if (rr_v_lo & ~req_afifo_full & (rr_dma_pkt_lo.write_not_read ? tx_ready_lo : 1'b1)) begin
counter_up = 1'b1;
rr_yumi_li = 1'b1;
req_afifo_enq = 1'b1;
tx_v_li = rr_dma_pkt_lo.write_not_read;
rr_tag_n = rr_tag_lo;
dma_pkt_n = rr_dma_pkt_lo;
end
end
else if (count_r == num_req_lp-1) begin
if (~req_afifo_full & (dma_pkt_r.write_not_read ? tx_ready_lo : 1'b1)) begin
counter_clear = 1'b1;
req_afifo_enq = 1'b1;
tx_v_li = dma_pkt_r.write_not_read;
end
end
else begin
if (~req_afifo_full & (dma_pkt_r.write_not_read ? tx_ready_lo : 1'b1)) begin
counter_up = 1'b1;
req_afifo_enq = 1'b1;
tx_v_li = dma_pkt_r.write_not_read;
end
end
end
end
always_ff @ (posedge core_clk_i) begin
if (core_reset_i) begin
dma_pkt_r <= '0;
rr_tag_r <= '0;
end
else begin
dma_pkt_r <= dma_pkt_n;
rr_tag_r <= rr_tag_n;
end
end
// address logic
if (num_cache_p == 1) begin
if (num_req_lp == 1) begin
assign dram_req_addr = {
{(dram_channel_addr_width_p-cache_bank_addr_width_p){1'b0}},
dma_pkt_n.addr[cache_bank_addr_width_p-1:dram_byte_offset_width_lp],
{dram_byte_offset_width_lp{1'b0}}
};
end
else begin
assign dram_req_addr = {
{(dram_channel_addr_width_p-cache_bank_addr_width_p){1'b0}},
dma_pkt_n.addr[cache_bank_addr_width_p-1:dram_byte_offset_width_lp+lg_num_req_lp],
count_r,
{dram_byte_offset_width_lp{1'b0}}
};
end
end
else begin
if (num_req_lp == 1) begin
assign dram_req_addr = {
rr_tag_n,
{(dram_channel_addr_width_p-cache_bank_addr_width_p-lg_num_cache_lp){1'b0}},
dma_pkt_n.addr[cache_bank_addr_width_p-1:dram_byte_offset_width_lp],
{dram_byte_offset_width_lp{1'b0}}
};
end
else begin
assign dram_req_addr = {
rr_tag_n,
{(dram_channel_addr_width_p-cache_bank_addr_width_p-lg_num_cache_lp){1'b0}},
dma_pkt_n.addr[cache_bank_addr_width_p-1:dram_byte_offset_width_lp+lg_num_req_lp],
count_r,
{dram_byte_offset_width_lp{1'b0}}
};
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_cache_to_test_dram)
|
//////////////////////////////////////////////////////////////////
// //
// Decompiler for Amber 25 Core //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Decompiler for debugging core - not synthesizable //
// Shows instruction in Execute Stage at last clock of //
// the instruction //
// //
// Author(s): //
// - Conor Santifort, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2011 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`include "global_defines.v"
`include "a25_config_defines.v"
module a25_decompile
(
input i_clk,
input i_core_stall,
input [31:0] i_instruction,
input i_instruction_valid,
input i_instruction_undefined,
input i_instruction_execute,
input [2:0] i_interrupt, // non-zero value means interrupt triggered
input i_interrupt_state,
input [31:0] i_instruction_address,
input [2:0] i_pc_sel,
input i_pc_wen
);
`include "a25_localparams.v"
`ifdef A25_DECOMPILE
integer i;
wire [31:0] imm32;
wire [7:0] imm8;
wire [11:0] offset12;
wire [7:0] offset8;
wire [3:0] reg_n, reg_d, reg_m, reg_s;
wire [4:0] shift_imm;
wire [3:0] opcode;
wire [3:0] condition;
wire [3:0] type;
wire opcode_compare;
wire opcode_move;
wire no_shift;
wire shift_op_imm;
wire [1:0] mtrans_type;
wire s_bit;
reg [(5*8)-1:0] xINSTRUCTION_EXECUTE;
reg [(5*8)-1:0] xINSTRUCTION_EXECUTE_R = "--- ";
wire [(8*8)-1:0] TYPE_NAME;
reg [3:0] fchars;
reg [31:0] execute_address = 'd0;
reg [2:0] interrupt_d1;
reg [31:0] execute_instruction = 'd0;
reg execute_now = 'd0;
reg execute_valid = 'd0;
reg execute_undefined = 'd0;
// ========================================================
// Delay instruction to Execute stage
// ========================================================
always @( posedge i_clk )
if ( !i_core_stall && i_instruction_valid )
begin
execute_instruction <= i_instruction;
execute_address <= i_instruction_address;
execute_undefined <= i_instruction_undefined;
execute_now <= 1'd1;
end
else
execute_now <= 1'd0;
always @ ( posedge i_clk )
if ( !i_core_stall )
execute_valid <= i_instruction_valid;
// ========================================================
// Open File
// ========================================================
integer decompile_file;
initial
#1 decompile_file = $fopen(`A25_DECOMPILE_FILE, "w");
// ========================================================
// Fields within the instruction
// ========================================================
assign opcode = execute_instruction[24:21];
assign condition = execute_instruction[31:28];
assign s_bit = execute_instruction[20];
assign reg_n = execute_instruction[19:16];
assign reg_d = execute_instruction[15:12];
assign reg_m = execute_instruction[3:0];
assign reg_s = execute_instruction[11:8];
assign shift_imm = execute_instruction[11:7];
assign offset12 = execute_instruction[11:0];
assign offset8 = {execute_instruction[11:8], execute_instruction[3:0]};
assign imm8 = execute_instruction[7:0];
assign no_shift = execute_instruction[11:4] == 8'h0;
assign mtrans_type = execute_instruction[24:23];
assign opcode_compare =
opcode == CMP ||
opcode == CMN ||
opcode == TEQ ||
opcode == TST ;
assign opcode_move =
opcode == MOV ||
opcode == MVN ;
assign shift_op_imm = type == REGOP && execute_instruction[25] == 1'd1;
assign imm32 = execute_instruction[11:8] == 4'h0 ? { 24'h0, imm8[7:0] } :
execute_instruction[11:8] == 4'h1 ? { imm8[1:0], 24'h0, imm8[7:2] } :
execute_instruction[11:8] == 4'h2 ? { imm8[3:0], 24'h0, imm8[7:4] } :
execute_instruction[11:8] == 4'h3 ? { imm8[5:0], 24'h0, imm8[7:6] } :
execute_instruction[11:8] == 4'h4 ? { imm8[7:0], 24'h0 } :
execute_instruction[11:8] == 4'h5 ? { 2'h0, imm8[7:0], 22'h0 } :
execute_instruction[11:8] == 4'h6 ? { 4'h0, imm8[7:0], 20'h0 } :
execute_instruction[11:8] == 4'h7 ? { 6'h0, imm8[7:0], 18'h0 } :
execute_instruction[11:8] == 4'h8 ? { 8'h0, imm8[7:0], 16'h0 } :
execute_instruction[11:8] == 4'h9 ? { 10'h0, imm8[7:0], 14'h0 } :
execute_instruction[11:8] == 4'ha ? { 12'h0, imm8[7:0], 12'h0 } :
execute_instruction[11:8] == 4'hb ? { 14'h0, imm8[7:0], 10'h0 } :
execute_instruction[11:8] == 4'hc ? { 16'h0, imm8[7:0], 8'h0 } :
execute_instruction[11:8] == 4'hd ? { 18'h0, imm8[7:0], 6'h0 } :
execute_instruction[11:8] == 4'he ? { 20'h0, imm8[7:0], 4'h0 } :
{ 22'h0, imm8[7:0], 2'h0 } ;
// ========================================================
// Instruction decode
// ========================================================
// the order of these matters
assign type =
{execute_instruction[27:23], execute_instruction[21:20], execute_instruction[11:4] } == { 5'b00010, 2'b00, 8'b00001001 } ? SWAP : // Before REGOP
{execute_instruction[27:22], execute_instruction[7:4] } == { 6'b000000, 4'b1001 } ? MULT : // Before REGOP
{execute_instruction[27:26] } == { 2'b00 } ? REGOP :
{execute_instruction[27:26] } == { 2'b01 } ? TRANS :
{execute_instruction[27:25] } == { 3'b100 } ? MTRANS :
{execute_instruction[27:25] } == { 3'b101 } ? BRANCH :
{execute_instruction[27:25] } == { 3'b110 } ? CODTRANS :
{execute_instruction[27:24], execute_instruction[4] } == { 4'b1110, 1'b0 } ? COREGOP :
{execute_instruction[27:24], execute_instruction[4] } == { 4'b1110, 1'b1 } ? CORTRANS :
SWI ;
//
// Convert some important signals to ASCII
// so their values can easily be displayed on a waveform viewer
//
assign TYPE_NAME = type == REGOP ? "REGOP " :
type == MULT ? "MULT " :
type == SWAP ? "SWAP " :
type == TRANS ? "TRANS " :
type == MTRANS ? "MTRANS " :
type == BRANCH ? "BRANCH " :
type == CODTRANS ? "CODTRANS" :
type == COREGOP ? "COREGOP " :
type == CORTRANS ? "CORTRANS" :
type == SWI ? "SWI " :
"UNKNOWN " ;
always @*
begin
if ( !execute_now )
begin
xINSTRUCTION_EXECUTE = xINSTRUCTION_EXECUTE_R;
end // stalled
else if ( type == REGOP && opcode == ADC ) xINSTRUCTION_EXECUTE = "adc ";
else if ( type == REGOP && opcode == ADD ) xINSTRUCTION_EXECUTE = "add ";
else if ( type == REGOP && opcode == AND ) xINSTRUCTION_EXECUTE = "and ";
else if ( type == BRANCH && execute_instruction[24] == 1'b0 ) xINSTRUCTION_EXECUTE = "b ";
else if ( type == REGOP && opcode == BIC ) xINSTRUCTION_EXECUTE = "bic ";
else if ( type == BRANCH && execute_instruction[24] == 1'b1 ) xINSTRUCTION_EXECUTE = "bl ";
else if ( type == COREGOP ) xINSTRUCTION_EXECUTE = "cdp ";
else if ( type == REGOP && opcode == CMN ) xINSTRUCTION_EXECUTE = "cmn ";
else if ( type == REGOP && opcode == CMP ) xINSTRUCTION_EXECUTE = "cmp ";
else if ( type == REGOP && opcode == EOR ) xINSTRUCTION_EXECUTE = "eor ";
else if ( type == CODTRANS && execute_instruction[20] == 1'b1 ) xINSTRUCTION_EXECUTE = "ldc ";
else if ( type == MTRANS && execute_instruction[20] == 1'b1 ) xINSTRUCTION_EXECUTE = "ldm ";
else if ( type == TRANS && {execute_instruction[22],execute_instruction[20]} == {1'b0, 1'b1} ) xINSTRUCTION_EXECUTE = "ldr ";
else if ( type == TRANS && {execute_instruction[22],execute_instruction[20]} == {1'b1, 1'b1} ) xINSTRUCTION_EXECUTE = "ldrb ";
else if ( type == CORTRANS && execute_instruction[20] == 1'b0 ) xINSTRUCTION_EXECUTE = "mcr ";
else if ( type == MULT && execute_instruction[21] == 1'b1 ) xINSTRUCTION_EXECUTE = "mla ";
else if ( type == REGOP && opcode == MOV ) xINSTRUCTION_EXECUTE = "mov ";
else if ( type == CORTRANS && execute_instruction[20] == 1'b1 ) xINSTRUCTION_EXECUTE = "mrc ";
else if ( type == MULT && execute_instruction[21] == 1'b0 ) xINSTRUCTION_EXECUTE = "mul ";
else if ( type == REGOP && opcode == MVN ) xINSTRUCTION_EXECUTE = "mvn ";
else if ( type == REGOP && opcode == ORR ) xINSTRUCTION_EXECUTE = "orr ";
else if ( type == REGOP && opcode == RSB ) xINSTRUCTION_EXECUTE = "rsb ";
else if ( type == REGOP && opcode == RSC ) xINSTRUCTION_EXECUTE = "rsc ";
else if ( type == REGOP && opcode == SBC ) xINSTRUCTION_EXECUTE = "sbc ";
else if ( type == CODTRANS && execute_instruction[20] == 1'b0 ) xINSTRUCTION_EXECUTE = "stc ";
else if ( type == MTRANS && execute_instruction[20] == 1'b0 ) xINSTRUCTION_EXECUTE = "stm ";
else if ( type == TRANS && {execute_instruction[22],execute_instruction[20]} == {1'b0, 1'b0} ) xINSTRUCTION_EXECUTE = "str ";
else if ( type == TRANS && {execute_instruction[22],execute_instruction[20]} == {1'b1, 1'b0} ) xINSTRUCTION_EXECUTE = "strb ";
else if ( type == REGOP && opcode == SUB ) xINSTRUCTION_EXECUTE = "sub ";
else if ( type == SWI ) xINSTRUCTION_EXECUTE = "swi ";
else if ( type == SWAP && execute_instruction[22] == 1'b0 ) xINSTRUCTION_EXECUTE = "swp ";
else if ( type == SWAP && execute_instruction[22] == 1'b1 ) xINSTRUCTION_EXECUTE = "swpb ";
else if ( type == REGOP && opcode == TEQ ) xINSTRUCTION_EXECUTE = "teq ";
else if ( type == REGOP && opcode == TST ) xINSTRUCTION_EXECUTE = "tst ";
else xINSTRUCTION_EXECUTE = "unkow";
end
always @ ( posedge i_clk )
xINSTRUCTION_EXECUTE_R <= xINSTRUCTION_EXECUTE;
// =================================================================================
// Memory Reads and Writes
// =================================================================================
reg [31:0] tmp_address;
always @( posedge i_clk )
begin
// Data Write
if ( get_1bit_signal(0) && !get_1bit_signal(3) )
begin
$fwrite(decompile_file, "%09d write addr ", `U_TB.clk_count);
tmp_address = get_32bit_signal(2);
fwrite_hex_drop_zeros(decompile_file, {tmp_address [31:2], 2'd0} );
$fwrite(decompile_file, ", data %08h, be %h",
get_32bit_signal(3), // u_cache.i_write_data
get_4bit_signal (0)); // u_cache.i_byte_enable
$fwrite(decompile_file, "\n");
end
// Data Read
if ( get_1bit_signal(4) && !get_1bit_signal(1) )
begin
$fwrite(decompile_file, "%09d read addr ", `U_TB.clk_count);
tmp_address = get_32bit_signal(5);
fwrite_hex_drop_zeros(decompile_file, {tmp_address[31:2], 2'd0} );
$fwrite(decompile_file, ", data %08h to ", get_32bit_signal(4));
warmreg(get_4bit_signal(1));
$fwrite(decompile_file, "\n");
end
// instruction
if ( execute_now )
begin
// Interrupts override instructions that are just starting
if ( interrupt_d1 == 3'd0 || interrupt_d1 == 3'd7 )
begin
$fwrite(decompile_file,"%09d ", `U_TB.clk_count);
// Right justify the address
if ( execute_address < 32'h10) $fwrite(decompile_file," %01x: ", {execute_address[ 3:1], 1'd0});
else if ( execute_address < 32'h100) $fwrite(decompile_file," %02x: ", {execute_address[ 7:1], 1'd0});
else if ( execute_address < 32'h1000) $fwrite(decompile_file," %03x: ", {execute_address[11:1], 1'd0});
else if ( execute_address < 32'h10000) $fwrite(decompile_file," %04x: ", {execute_address[15:1], 1'd0});
else if ( execute_address < 32'h100000) $fwrite(decompile_file," %05x: ", {execute_address[19:1], 1'd0});
else if ( execute_address < 32'h1000000) $fwrite(decompile_file," %06x: ", {execute_address[23:1], 1'd0});
else if ( execute_address < 32'h10000000) $fwrite(decompile_file," %07x: ", {execute_address[27:1], 1'd0});
else $fwrite(decompile_file,"%8x: ", {execute_address[31:1], 1'd0});
// Mark that the instruction is not being executed
// condition field in execute stage allows instruction to execute ?
if (!i_instruction_execute)
begin
$fwrite(decompile_file,"-");
if ( type == SWI )
$display ("Cycle %09d SWI not taken *************", `U_TB.clk_count);
end
else
$fwrite(decompile_file," ");
// ========================================
// print the instruction name
// ========================================
case (numchars( xINSTRUCTION_EXECUTE ))
4'd1: $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39:32] );
4'd2: $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39:24] );
4'd3: $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39:16] );
4'd4: $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39: 8] );
default: $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39: 0] );
endcase
fchars = 8 - numchars(xINSTRUCTION_EXECUTE);
// Print the Multiple transfer type
if (type == MTRANS )
begin
w_mtrans_type;
fchars = fchars - 2;
end
// Print the s bit
if ( ((type == REGOP && !opcode_compare) || type == MULT ) && s_bit == 1'b1 )
begin
$fwrite(decompile_file,"s");
fchars = fchars - 1;
end
// Print the p bit
if ( type == REGOP && opcode_compare && s_bit == 1'b1 && reg_d == 4'd15 )
begin
$fwrite(decompile_file,"p");
fchars = fchars - 1;
end
// Print the condition code
if ( condition != AL )
begin
wcond;
fchars = fchars - 2;
end
// Align spaces after instruction
case ( fchars )
4'd0: $fwrite(decompile_file,"");
4'd1: $fwrite(decompile_file," ");
4'd2: $fwrite(decompile_file," ");
4'd3: $fwrite(decompile_file," ");
4'd4: $fwrite(decompile_file," ");
4'd5: $fwrite(decompile_file," ");
4'd6: $fwrite(decompile_file," ");
4'd7: $fwrite(decompile_file," ");
4'd8: $fwrite(decompile_file," ");
default: $fwrite(decompile_file," ");
endcase
// ========================================
// print the arguments for the instruction
// ========================================
case ( type )
REGOP: regop_args;
TRANS: trans_args;
MTRANS: mtrans_args;
BRANCH: branch_args;
MULT: mult_args;
SWAP: swap_args;
CODTRANS: codtrans_args;
COREGOP: begin
// `TB_ERROR_MESSAGE
$write("Coregop not implemented in decompiler yet\n");
end
CORTRANS: cortrans_args;
SWI: $fwrite(decompile_file,"#0x%06h", execute_instruction[23:0]);
default: begin
`TB_ERROR_MESSAGE
$write("Unknown Instruction Type ERROR\n");
end
endcase
$fwrite( decompile_file,"\n" );
end
// Undefined Instruction Interrupts
if ( i_instruction_execute && execute_undefined )
begin
$fwrite( decompile_file,"%09d interrupt undefined instruction", `U_TB.clk_count );
$fwrite( decompile_file,", return addr " );
$fwrite( decompile_file,"%08x\n", pcf(get_reg_val(5'd21)-4'd4) );
end
// Software Interrupt
if ( i_instruction_execute && type == SWI )
begin
$fwrite( decompile_file,"%09d interrupt swi", `U_TB.clk_count );
$fwrite( decompile_file,", return addr " );
$fwrite( decompile_file,"%08x\n", pcf(get_reg_val(5'd21)-4'd4) );
end
end
end
always @( posedge i_clk )
if ( !i_core_stall )
begin
interrupt_d1 <= i_interrupt;
// Asynchronous Interrupts
if ( interrupt_d1 != 3'd0 && i_interrupt_state )
begin
$fwrite( decompile_file,"%09d interrupt ", `U_TB.clk_count );
case ( interrupt_d1 )
3'd1: $fwrite( decompile_file,"data abort" );
3'd2: $fwrite( decompile_file,"firq" );
3'd3: $fwrite( decompile_file,"irq" );
3'd4: $fwrite( decompile_file,"address exception" );
3'd5: $fwrite( decompile_file,"instruction abort" );
default: $fwrite( decompile_file,"unknown type" );
endcase
$fwrite( decompile_file,", return addr " );
case ( interrupt_d1 )
3'd1: $fwrite(decompile_file,"%08h\n", pcf(get_reg_val(5'd16)));
3'd2: $fwrite(decompile_file,"%08h\n", pcf(get_reg_val(5'd17)));
3'd3: $fwrite(decompile_file,"%08h\n", pcf(get_reg_val(5'd18)));
3'd4: $fwrite(decompile_file,"%08h\n", pcf(get_reg_val(5'd19)));
3'd5: $fwrite(decompile_file,"%08h\n", pcf(get_reg_val(5'd19)));
3'd7: $fwrite(decompile_file,"%08h\n", pcf(get_reg_val(5'd20)));
default: ;
endcase
end
end
// jump
// Dont print a jump message for interrupts
always @( posedge i_clk )
if (
i_pc_sel != 3'd0 &&
i_pc_wen &&
!i_core_stall &&
i_instruction_execute &&
i_interrupt == 3'd0 &&
!execute_undefined &&
type != SWI &&
execute_address != get_32bit_signal(0) // Don't print jump to same address
)
begin
$fwrite(decompile_file,"%09d jump from ", `U_TB.clk_count);
fwrite_hex_drop_zeros(decompile_file, pcf(execute_address));
$fwrite(decompile_file," to ");
fwrite_hex_drop_zeros(decompile_file, pcf(get_32bit_signal(0)) ); // u_execute.pc_nxt
$fwrite(decompile_file,", r0 %08h, ", get_reg_val ( 5'd0 ));
$fwrite(decompile_file,"r1 %08h\n", get_reg_val ( 5'd1 ));
end
// =================================================================================
// Tasks
// =================================================================================
// Write Condition field
task wcond;
begin
case( condition)
4'h0: $fwrite(decompile_file,"eq");
4'h1: $fwrite(decompile_file,"ne");
4'h2: $fwrite(decompile_file,"cs");
4'h3: $fwrite(decompile_file,"cc");
4'h4: $fwrite(decompile_file,"mi");
4'h5: $fwrite(decompile_file,"pl");
4'h6: $fwrite(decompile_file,"vs");
4'h7: $fwrite(decompile_file,"vc");
4'h8: $fwrite(decompile_file,"hi");
4'h9: $fwrite(decompile_file,"ls");
4'ha: $fwrite(decompile_file,"ge");
4'hb: $fwrite(decompile_file,"lt");
4'hc: $fwrite(decompile_file,"gt");
4'hd: $fwrite(decompile_file,"le");
4'he: $fwrite(decompile_file," "); // Always
default: $fwrite(decompile_file,"nv"); // Never
endcase
end
endtask
// ldm and stm types
task w_mtrans_type;
begin
case( mtrans_type )
4'h0: $fwrite(decompile_file,"da");
4'h1: $fwrite(decompile_file,"ia");
4'h2: $fwrite(decompile_file,"db");
4'h3: $fwrite(decompile_file,"ib");
default: $fwrite(decompile_file,"xx");
endcase
end
endtask
// e.g. mrc 15, 0, r9, cr0, cr0, {0}
task cortrans_args;
begin
// Co-Processor Number
$fwrite(decompile_file,"%1d, ", execute_instruction[11:8]);
// opcode1
$fwrite(decompile_file,"%1d, ", execute_instruction[23:21]);
// Rd [15:12]
warmreg(reg_d);
// CRn [19:16]
$fwrite(decompile_file,", cr%1d", execute_instruction[19:16]);
// CRm [3:0]
$fwrite(decompile_file,", cr%1d", execute_instruction[3:0]);
// Opcode2 [7:5]
$fwrite(decompile_file,", {%1d}", execute_instruction[7:5]);
end
endtask
// ldc 15, 0, r9, cr0, cr0, {0}
task codtrans_args;
begin
// Co-Processor Number
$fwrite(decompile_file,"%1d, ", execute_instruction[11:8]);
// CRd [15:12]
$fwrite(decompile_file,"cr%1d, ", execute_instruction[15:12]);
// Rd [19:16]
warmreg(reg_n);
end
endtask
task branch_args;
reg [31:0] shift_amount;
begin
if (execute_instruction[23]) // negative
shift_amount = {~execute_instruction[23:0] + 24'd1, 2'd0};
else
shift_amount = {execute_instruction[23:0], 2'd0};
if (execute_instruction[23]) // negative
fwrite_hex_drop_zeros ( decompile_file, get_reg_val( 5'd21 ) - shift_amount );
else
fwrite_hex_drop_zeros ( decompile_file, get_reg_val( 5'd21 ) + shift_amount );
end
endtask
task mult_args;
begin
warmreg(reg_n); // Rd is in the Rn position for MULT instructions
$fwrite(decompile_file,", ");
warmreg(reg_m);
$fwrite(decompile_file,", ");
warmreg(reg_s);
if (execute_instruction[21]) // MLA
begin
$fwrite(decompile_file,", ");
warmreg(reg_d);
end
end
endtask
task swap_args;
begin
warmreg(reg_d);
$fwrite(decompile_file,", ");
warmreg(reg_m);
$fwrite(decompile_file,", [");
warmreg(reg_n);
$fwrite(decompile_file,"]");
end
endtask
task regop_args;
begin
if (!opcode_compare)
warmreg(reg_d);
if (!opcode_move )
begin
if (!opcode_compare)
begin
$fwrite(decompile_file,", ");
if (reg_d < 4'd10 || reg_d > 4'd12)
$fwrite(decompile_file," ");
end
warmreg(reg_n);
$fwrite(decompile_file,", ");
if (reg_n < 4'd10 || reg_n > 4'd12)
$fwrite(decompile_file," ");
end
else
begin
$fwrite(decompile_file,", ");
if (reg_d < 4'd10 || reg_d > 4'd12)
$fwrite(decompile_file," ");
end
if (shift_op_imm)
begin
if (|imm32[31:15])
$fwrite(decompile_file,"#0x%08h", imm32);
else
$fwrite(decompile_file,"#%1d", imm32);
end
else // Rm
begin
warmreg(reg_m);
if (execute_instruction[4])
// Register Shifts
wshiftreg;
else
// Immediate shifts
wshift;
end
end
endtask
task trans_args;
begin
warmreg(reg_d); // Destination register
casez ({execute_instruction[25:23], execute_instruction[21], no_shift, offset12==12'd0})
6'b0100?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", #-%1d]" , offset12); end
6'b0110?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", #%1d]" , offset12); end
6'b0100?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
6'b0110?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
6'b0101?? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", #-%1d]!", offset12); end
6'b0111?? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", #%1d]!" , offset12); end
6'b0000?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], #-%1d", offset12); end
6'b0010?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], #%1d" , offset12); end
6'b0001?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], #-%1d", offset12); end
6'b0011?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], #%1d" , offset12); end
6'b0000?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
6'b0010?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
6'b0001?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
6'b0011?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
6'b11001? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", -"); warmreg(reg_m); $fwrite(decompile_file,"]"); end
6'b11101? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", "); warmreg(reg_m); $fwrite(decompile_file,"]"); end
6'b11011? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", -"); warmreg(reg_m); $fwrite(decompile_file,"]!"); end
6'b11111? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", "); warmreg(reg_m); $fwrite(decompile_file,"]!"); end
6'b10001? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], -"); warmreg(reg_m); end
6'b10101? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], "); warmreg(reg_m); end
6'b10011? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], -"); warmreg(reg_m); end
6'b10111? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], "); warmreg(reg_m); end
6'b11000? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", -"); warmreg(reg_m); wshift; $fwrite(decompile_file,"]"); end
6'b11100? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", "); warmreg(reg_m); wshift; $fwrite(decompile_file,"]"); end
6'b11010? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", -"); warmreg(reg_m); wshift; $fwrite(decompile_file,"]!");end
6'b11110? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", "); warmreg(reg_m); wshift; $fwrite(decompile_file,"]!");end
6'b10000? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], -"); warmreg(reg_m); wshift; end
6'b10100? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], "); warmreg(reg_m); wshift; end
6'b10010? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], -"); warmreg(reg_m); wshift; end
6'b10110? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], "); warmreg(reg_m); wshift; end
endcase
end
endtask
task mtrans_args;
begin
warmreg(reg_n);
if (execute_instruction[21]) $fwrite(decompile_file,"!");
$fwrite(decompile_file,", {");
for (i=0;i<16;i=i+1)
if (execute_instruction[i])
begin
warmreg(i);
if (more_to_come(execute_instruction[15:0], i))
$fwrite(decompile_file,", ");
end
$fwrite(decompile_file,"}");
// SDM: store the user mode registers, when in priviledged mode
if (execute_instruction[22:20] == 3'b100)
$fwrite(decompile_file,"^");
end
endtask
task wshift;
begin
// Check that its a valid shift operation. LSL by #0 is the null operator
if (execute_instruction[6:5] != LSL || shift_imm != 5'd0)
begin
case(execute_instruction[6:5])
2'd0: $fwrite(decompile_file,", lsl");
2'd1: $fwrite(decompile_file,", lsr");
2'd2: $fwrite(decompile_file,", asr");
2'd3: if (shift_imm == 5'd0) $fwrite(decompile_file,", rrx"); else $fwrite(decompile_file,", ror");
endcase
if (execute_instruction[6:5] != 2'd3 || shift_imm != 5'd0)
$fwrite(decompile_file," #%1d", shift_imm);
end
end
endtask
task wshiftreg;
begin
case(execute_instruction[6:5])
2'd0: $fwrite(decompile_file,", lsl ");
2'd1: $fwrite(decompile_file,", lsr ");
2'd2: $fwrite(decompile_file,", asr ");
2'd3: $fwrite(decompile_file,", ror ");
endcase
warmreg(reg_s);
end
endtask
task warmreg;
input [3:0] regnum;
begin
if (regnum < 4'd12)
$fwrite(decompile_file,"r%1d", regnum);
else
case (regnum)
4'd12 : $fwrite(decompile_file,"ip");
4'd13 : $fwrite(decompile_file,"sp");
4'd14 : $fwrite(decompile_file,"lr");
4'd15 : $fwrite(decompile_file,"pc");
endcase
end
endtask
task fwrite_hex_drop_zeros;
input [31:0] file;
input [31:0] num;
begin
if (num[31:28] != 4'd0)
$fwrite(file, "%x", num);
else if (num[27:24] != 4'd0)
$fwrite(file, "%x", num[27:0]);
else if (num[23:20] != 4'd0)
$fwrite(file, "%x", num[23:0]);
else if (num[19:16] != 4'd0)
$fwrite(file, "%x", num[19:0]);
else if (num[15:12] != 4'd0)
$fwrite(file, "%x", num[15:0]);
else if (num[11:8] != 4'd0)
$fwrite(file, "%x", num[11:0]);
else if (num[7:4] != 4'd0)
$fwrite(file, "%x", num[7:0]);
else
$fwrite(file, "%x", num[3:0]);
end
endtask
// =================================================================================
// Functions
// =================================================================================
// Get current value of register
function [31:0] get_reg_val;
input [4:0] regnum;
begin
case (regnum)
5'd0 : get_reg_val = `U_REGISTER_BANK.r0_out;
5'd1 : get_reg_val = `U_REGISTER_BANK.r1_out;
5'd2 : get_reg_val = `U_REGISTER_BANK.r2_out;
5'd3 : get_reg_val = `U_REGISTER_BANK.r3_out;
5'd4 : get_reg_val = `U_REGISTER_BANK.r4_out;
5'd5 : get_reg_val = `U_REGISTER_BANK.r5_out;
5'd6 : get_reg_val = `U_REGISTER_BANK.r6_out;
5'd7 : get_reg_val = `U_REGISTER_BANK.r7_out;
5'd8 : get_reg_val = `U_REGISTER_BANK.r8_out;
5'd9 : get_reg_val = `U_REGISTER_BANK.r9_out;
5'd10 : get_reg_val = `U_REGISTER_BANK.r10_out;
5'd11 : get_reg_val = `U_REGISTER_BANK.r11_out;
5'd12 : get_reg_val = `U_REGISTER_BANK.r12_out;
5'd13 : get_reg_val = `U_REGISTER_BANK.r13_out;
5'd14 : get_reg_val = `U_REGISTER_BANK.r14_out;
5'd15 : get_reg_val = `U_REGISTER_BANK.r15_out_rm; // the version of pc with status bits
5'd16 : get_reg_val = `U_REGISTER_BANK.r14_svc;
5'd17 : get_reg_val = `U_REGISTER_BANK.r14_firq;
5'd18 : get_reg_val = `U_REGISTER_BANK.r14_irq;
5'd19 : get_reg_val = `U_REGISTER_BANK.r14_svc;
5'd20 : get_reg_val = `U_REGISTER_BANK.r14_svc;
5'd21 : get_reg_val = `U_REGISTER_BANK.r15_out_rn; // the version of pc without status bits
endcase
end
endfunction
function [31:0] get_32bit_signal;
input [2:0] num;
begin
case (num)
3'd0: get_32bit_signal = `U_EXECUTE.pc_nxt;
3'd1: get_32bit_signal = `U_EXECUTE.o_iaddress;
3'd2: get_32bit_signal = `U_EXECUTE.o_daddress;
3'd3: get_32bit_signal = `U_EXECUTE.o_write_data;
// 3'd4: get_32bit_signal = `U_EXECUTE.read_data_filtered;
3'd4: get_32bit_signal = `U_EXECUTE.i_wb_read_data;
3'd5: get_32bit_signal = `U_WB.daddress_r;
endcase
end
endfunction
function get_1bit_signal;
input [2:0] num;
begin
case (num)
3'd0: get_1bit_signal = `U_EXECUTE.o_write_enable;
3'd1: get_1bit_signal = `U_AMBER.mem_stall;
3'd2: get_1bit_signal = `U_EXECUTE.o_daddress_valid;
3'd3: get_1bit_signal = `U_AMBER.core_stall;
3'd4: get_1bit_signal = `U_WB.mem_read_data_valid_r;
endcase
end
endfunction
function [3:0] get_4bit_signal;
input [2:0] num;
begin
case (num)
3'd0: get_4bit_signal = `U_EXECUTE.o_byte_enable;
3'd1: get_4bit_signal = `U_WB.mem_load_rd_r;
endcase
end
endfunction
function [3:0] numchars;
input [(5*8)-1:0] xINSTRUCTION_EXECUTE;
begin
if (xINSTRUCTION_EXECUTE[31:0] == " ")
numchars = 4'd1;
else if (xINSTRUCTION_EXECUTE[23:0] == " ")
numchars = 4'd2;
else if (xINSTRUCTION_EXECUTE[15:0] == " ")
numchars = 4'd3;
else if (xINSTRUCTION_EXECUTE[7:0] == " ")
numchars = 4'd4;
else
numchars = 4'd5;
end
endfunction
function more_to_come;
input [15:0] regs;
input [31:0] i;
begin
case (i)
15 : more_to_come = 1'd0;
14 : more_to_come = regs[15] ? 1'd1 : 1'd0;
13 : more_to_come = |regs[15:14] ? 1'd1 : 1'd0;
12 : more_to_come = |regs[15:13] ? 1'd1 : 1'd0;
11 : more_to_come = |regs[15:12] ? 1'd1 : 1'd0;
10 : more_to_come = |regs[15:11] ? 1'd1 : 1'd0;
9 : more_to_come = |regs[15:10] ? 1'd1 : 1'd0;
8 : more_to_come = |regs[15: 9] ? 1'd1 : 1'd0;
7 : more_to_come = |regs[15: 8] ? 1'd1 : 1'd0;
6 : more_to_come = |regs[15: 7] ? 1'd1 : 1'd0;
5 : more_to_come = |regs[15: 6] ? 1'd1 : 1'd0;
4 : more_to_come = |regs[15: 5] ? 1'd1 : 1'd0;
3 : more_to_come = |regs[15: 4] ? 1'd1 : 1'd0;
2 : more_to_come = |regs[15: 3] ? 1'd1 : 1'd0;
1 : more_to_come = |regs[15: 2] ? 1'd1 : 1'd0;
0 : more_to_come = |regs[15: 1] ? 1'd1 : 1'd0;
endcase
end
endfunction
`endif
endmodule
|
module sockit_top (
input OSC_50_B8A,
input RESET_n,
input [3:0] KEY,
input [3:0] SW,
output [3:0] LED,
output [14:0] hps_memory_mem_a,
output [2:0] hps_memory_mem_ba,
output hps_memory_mem_ck,
output hps_memory_mem_ck_n,
output hps_memory_mem_cke,
output hps_memory_mem_cs_n,
output hps_memory_mem_ras_n,
output hps_memory_mem_cas_n,
output hps_memory_mem_we_n,
output hps_memory_mem_reset_n,
inout [39:0] hps_memory_mem_dq,
inout [4:0] hps_memory_mem_dqs,
inout [4:0] hps_memory_mem_dqs_n,
output hps_memory_mem_odt,
output [4:0] hps_memory_mem_dm,
input hps_memory_oct_rzqin
);
assign LED = 4'b0000;
soc_system soc (
.clk_clk (OSC_50_B8A),
.reset_reset_n (RESET_n),
.memory_mem_a (hps_memory_mem_a),
.memory_mem_ba (hps_memory_mem_ba),
.memory_mem_ck (hps_memory_mem_ck),
.memory_mem_ck_n (hps_memory_mem_ck_n),
.memory_mem_cke (hps_memory_mem_cke),
.memory_mem_cs_n (hps_memory_mem_cs_n),
.memory_mem_ras_n (hps_memory_mem_ras_n),
.memory_mem_cas_n (hps_memory_mem_cas_n),
.memory_mem_we_n (hps_memory_mem_we_n),
.memory_mem_reset_n (hps_memory_mem_reset_n),
.memory_mem_dq (hps_memory_mem_dq),
.memory_mem_dqs (hps_memory_mem_dqs),
.memory_mem_dqs_n (hps_memory_mem_dqs_n),
.memory_mem_odt (hps_memory_mem_odt),
.memory_mem_dm (hps_memory_mem_dm),
.memory_oct_rzqin (hps_memory_oct_rzqin),
.user_input_keys (KEY),
.user_input_switches (SW)
);
endmodule
|
/* mor1kx_wrapper.v */
// only removes all un-needed signals
module mor1kx_wrapper #(
parameter AW = 24
)(
// system
input wire clk,
input wire rst,
// data bus
output wire dcpu_cs,
output wire dcpu_we,
output wire [ 4-1:0] dcpu_sel,
output wire [ AW-1:0] dcpu_adr,
output wire [ 32-1:0] dcpu_dat_w,
input wire [ 32-1:0] dcpu_dat_r,
input wire dcpu_ack,
// instruction bus
output wire icpu_cs,
output wire icpu_we,
output wire [ 4-1:0] icpu_sel,
output wire [ AW-1:0] icpu_adr,
output wire [ 32-1:0] icpu_dat_w,
input wire [ 32-1:0] icpu_dat_r,
input wire icpu_ack
);
wire [ 31:0] d_adr;
wire d_stb;
wire d_cyc;
reg d_ack;
wire [ 31:0] i_adr;
wire i_stb;
wire i_cyc;
reg i_ack;
// cut address to desired width
assign dcpu_adr = d_adr[AW-1:0];
assign icpu_adr = i_adr[AW-1:0];
assign dcpu_cs = d_stb & d_cyc & !d_ack;
assign icpu_cs = i_stb & i_cyc & !i_ack;
always @(posedge clk) begin
d_ack <= dcpu_ack & dcpu_cs;
i_ack <= icpu_ack & icpu_cs;
end
mor1kx #(
.FEATURE_DEBUGUNIT("NONE"),
.FEATURE_CMOV("NONE"),
.FEATURE_FFL1("NONE"),
.FEATURE_ATOMIC("NONE"),
.FEATURE_STORE_BUFFER("NONE"),
.FEATURE_PIC("NONE"),
.FEATURE_TIMER("NONE"),
.FEATURE_MULTIPLIER("NONE"),
.FEATURE_DIVIDER("NONE"),
.FEATURE_INSTRUCTIONCACHE("NONE"),
.OPTION_ICACHE_BLOCK_WIDTH(4),
.OPTION_ICACHE_SET_WIDTH(8),
.OPTION_ICACHE_WAYS(1),
.OPTION_ICACHE_LIMIT_WIDTH(32),
.FEATURE_IMMU("NONE"),
.FEATURE_DATACACHE("NONE"),
.OPTION_DCACHE_BLOCK_WIDTH(4),
.OPTION_DCACHE_SET_WIDTH(8),
.OPTION_DCACHE_WAYS(1),
.OPTION_DCACHE_LIMIT_WIDTH(31),
.FEATURE_DMMU("NONE"),
.IBUS_WB_TYPE("B3_REGISTERED_FEEDBACK"),
.DBUS_WB_TYPE("B3_REGISTERED_FEEDBACK"),
.OPTION_CPU0("CAPPUCCINO"),
.OPTION_RESET_PC(32'h00000004)
) mor1kx0 (
.iwbm_adr_o(i_adr),
.iwbm_stb_o(i_stb),
.iwbm_cyc_o(i_cyc),
.iwbm_sel_o(icpu_sel),
.iwbm_we_o (icpu_we),
.iwbm_cti_o(),
.iwbm_bte_o(),
.iwbm_dat_o(icpu_dat_w),
.dwbm_adr_o(d_adr),
.dwbm_stb_o(d_stb),
.dwbm_cyc_o(d_cyc),
.dwbm_sel_o(dcpu_sel),
.dwbm_we_o (dcpu_we),
.dwbm_cti_o(),
.dwbm_bte_o(),
.dwbm_dat_o(dcpu_dat_w),
.clk(clk),
.rst(rst),
.iwbm_err_i(1'b0),
.iwbm_ack_i(i_ack),
.iwbm_dat_i(icpu_dat_r),
.iwbm_rty_i(1'b0),
.dwbm_err_i(1'b0),
.dwbm_ack_i(d_ack),
.dwbm_dat_i(dcpu_dat_r),
.dwbm_rty_i(1'b0),
.avm_d_address_o (),
.avm_d_byteenable_o (),
.avm_d_read_o (),
.avm_d_readdata_i (32'h00000000),
.avm_d_burstcount_o (),
.avm_d_write_o (),
.avm_d_writedata_o (),
.avm_d_waitrequest_i (1'b0),
.avm_d_readdatavalid_i (1'b0),
.avm_i_address_o (),
.avm_i_byteenable_o (),
.avm_i_read_o (),
.avm_i_readdata_i (32'h00000000),
.avm_i_burstcount_o (),
.avm_i_waitrequest_i (1'b0),
.avm_i_readdatavalid_i (1'b0),
.irq_i(32'h00000000),
.du_addr_i(16'h0000),
.du_stb_i(1'b0),
.du_dat_i(32'h00000000),
.du_we_i(1'b0),
.du_dat_o(),
.du_ack_o(),
.du_stall_i(1'b0),
.du_stall_o()
);
endmodule
|
module ArrayUltrasound(
input sysclk,
output [15:0] E_P,
output [15:0] E_N,
output HV_SW_CLR,
output HV_SW_LE,
output HV_SW_CLK,
output HV_SW_DOUT,
output HV_EN,
output [3:0] AX,
output [2:0] AY,
output MT_CS,
output MT_Strobe,
output MT_Data,
output ADCLK,
input DCO,
input FCO,
input OUTA,
input OUTB,
input OUTC,
input OUTD,
input OUTE,
input OUTF,
input OUTG,
input OUTH,
output SPI_CLK,
inout SPI_Data,
output SPI_CS,
output STBY,
output PWDN,
output sclk,
output reg sync,
output reg sdin,
output reg HSync, //output Enable
output reg FSync, //frame
output reg TestCLK,
output reg LCLK_o, //LCD CLK
output HS,
output VS,
output reg [7:0] R_Data,
output reg [7:0] G_Data,
output reg [7:0]B_Data,
output DE,
output LCD_RST,
output LCD_PWM,
output SPENA,
output SPDA,
output SPCK,
input CC3200_SPI_CLK,
input CC3200_SPI_CS,
output CC3200_SPI_DIN,
input CC3200_SPI_DOUT,
input Envelop
);
reg RST_n;
reg [31:0] RST_Counter;
always @(posedge sysclk) begin //48MHz
if(RST_Counter <= 32'd48) begin
RST_Counter <= RST_Counter + 1'b1;
RST_n <= 1'b1;
end
else if(RST_Counter <= 32'd96000) begin
RST_Counter <= RST_Counter + 1'b1;
RST_n <= 1'b0;
end
else begin
RST_n <= 1'b1;
end
end
reg Enable;
wire [1:0] Zoom;
wire [5:0] Gain;
reg [7:0] Line_Num;
wire [7:0] Line_Num_tmp;
wire [8:0] Trans_Addr;
wire [8:0] Trans_Data;
// assign Line_Num= {Line_Num_tmp[6:1],1'b1};
ComWithCC3200(
.CC3200_SPI_CLK(CC3200_SPI_CLK),
.CC3200_SPI_CS(CC3200_SPI_CS),
.CC3200_SPI_DIN(CC3200_SPI_DIN),
.CC3200_SPI_DOUT(CC3200_SPI_DOUT),
.Envelop(Envelop),
.Line_Num(Line_Num_tmp), //Current Sample Line
.Enable(),
.Zoom(Zoom),
.Gain(Gain),
.Trans_Data(Trans_Data[8:1]),
.Trans_Addr(Trans_Addr)
);
always @(posedge Envelop) begin
Line_Num <= Line_Num_tmp;
end
reg [31:0] Idle_Counter;
always @( posedge sysclk or posedge Envelop) begin
if(Envelop) begin
Idle_Counter <= 32'd0;
Enable <= 1'b1;
end
else begin
if(Idle_Counter <= 32'd25000000) begin//0.5s
Enable <= 1'b1;
Idle_Counter <= Idle_Counter + 1'b1;
end
else begin
Enable <= 1'b0;
end
end
end
//assign Line_Num = Test_q[6:0];
wire CLK_100M;
wire CLK_20M;
PLL PLL_inst (
.inclk0 ( sysclk ),
.c0 ( CLK_100M ),
.c1 (CLK_20M)
);
assign ADCLK=sysclk;
wire AD_CLK;
reg [31:0] Pulse_Counter;
reg Pr_Gate;
reg RX_Gate;
reg End_Gate;
wire Sample_Gate; //start Sampling ,50ns width
reg [1:0] Focus_Num ;
reg [1:0] Focus_Num_Pre ;
//Focus_Num 0:20mm 16CH, 1:40mm:16CH, 2:80mm 16CH(outside) 3:80mm 16CH(inner),
always @(posedge RX_Gate or posedge Envelop) begin //255 emit ,128line,
if(Envelop) begin
Focus_Num_Pre <= 2'b0;
end
else begin
if(Focus_Num_Pre[1:0] == 2'b00) begin
Focus_Num_Pre[1:0] <= 2'b01;
end
else if(Focus_Num_Pre[1:0] == 2'b01) begin
Focus_Num_Pre[1:0] <= 2'b10;
end
else if(Focus_Num_Pre[1:0] == 2'b10) begin
Focus_Num_Pre[1:0] <= 2'b11;
end
else if(Focus_Num_Pre[1:0] == 2'b11) begin
Focus_Num_Pre[1:0] <= 2'b00;
end
else
begin
Focus_Num_Pre[1:0] <= 2'b00;
end
end
end
always @(posedge End_Gate) begin //latch the Line_num Line_Num must be prepared before Pr_Gate
Focus_Num <= Focus_Num_Pre;
end
//assign Line_Num = Line_Num_Test[7:0];
reg [31:0] Envelop_Counter;
reg [31:0] Line_Period;
always @(posedge Pr_Gate) begin
case(Focus_Num[1:0])
2'b00: //
Line_Period=32'd9000; //60us
2'b01:
Line_Period=32'd12000; //70us
2'b10:
Line_Period=32'd18000; //150us
2'b11:
Line_Period=32'd18000; //150us
endcase
end
always @(posedge CLK_100M or posedge Envelop) begin
if(Envelop) begin
Pulse_Counter <= 32'd0;
end
else begin
if(Pulse_Counter < 32'd3000) //30us
begin
Pulse_Counter <= Pulse_Counter + 1'b1;
Pr_Gate <= 1'b1;
RX_Gate <= 1'b0;
End_Gate <= 1'b0;
end
else if(Pulse_Counter < 32'd3250) //2.5us?
begin
Pulse_Counter <= Pulse_Counter + 1'b1;
Pr_Gate <= 1'b0;
RX_Gate <= 1'b1;
End_Gate <= 1'b0;
end
else if(Pulse_Counter < Line_Period) //300us
begin
Pulse_Counter <= Pulse_Counter + 1'b1;
Pr_Gate <= 1'b0;
RX_Gate <= 1'b0;
End_Gate <= 1'b0;
end
else if(Pulse_Counter < (Line_Period + 8'd80)) //1us
begin
Pulse_Counter <= Pulse_Counter + 1'b1;
Pr_Gate <= 1'b0;
RX_Gate <= 1'b0;
End_Gate <= 1'b1;
end
else begin
if(Focus_Num_Pre >2'b00)
Pulse_Counter <= 32'd0;
else
Pulse_Counter <= 32'd65536;
Pr_Gate <= 1'b0;
RX_Gate <= 1'b0;
End_Gate <= 1'b0;
end
end
end
//assign HV_SW_LE2 = HV_SW_LE; //route wrong,should combine HV_SW_LE and HV_SW_LE2;
Transmit Transmit_Inst(
.Transmit_CLK(CLK_100M), //80MHz
.Line_Num(Line_Num),//Line_Num_Test), //Line Num,256 Lines totally,0~255
.Focus_Num(Focus_Num),//Focus_Num_Test), //Focus_num ,4 totally
.Pr_Gate(Pr_Gate), //prepare for everythings
.RX_Gate(RX_Gate), // Start Transmit
.Sample_Gate(Sample_Gate), //start Sampling
.P(E_P),
.N(E_N),
.HV_SW_CLR(HV_SW_CLR),
.HV_SW_LE(HV_SW_LE),
.HV_SW_CLK(HV_SW_CLK),
.HV_SW_DOUT(HV_SW_DOUT),
.AX(AX),
.AY(AY),
.MT_CS(MT_CS),
.MT_Strobe(MT_Strobe),
.MT_Data(MT_Data)
);
wire [11:0] Data_A,Data_B,Data_C,Data_D;
wire [11:0] Data_E,Data_F,Data_G,Data_H;
LVDS_AD LVDS_AD_inst_A (
.rx_in ( {OUTA,OUTB,OUTC,OUTD,OUTE,OUTF,OUTG,OUTH} ),
.rx_inclock ( FCO ),
.rx_out ( {Data_A,Data_B,Data_C,Data_D,Data_E,Data_F,Data_G,Data_H} ),
.rx_outclock ( AD_CLK )
);
// assign TestCLK = AD_CLK;
assign HV_EN = ~Enable;//Focus_Num_Test[0];//Envelop;//
assign STBY = ~Enable;//Focus_Num_Test[1];
assign PWDN = ~Enable;//Focus_Num_Test[2];
// test for why VRef can't Boost.
assign SPI_CLK = CLK_20M;
AD9273_SPI_Config AD9273_SPI_Config_Inst(
.RST_n(RST_n),
.SPI_CLK(SPI_CLK),
.SPI_Data(SPI_Data),
.SPI_CS(SPI_CS)
);
reg [3:0] div_Sclk;
reg [7:0] Send_Counter;
reg [15:0] Send_Data;
reg [8:0] Tgc_Counter;
assign sclk = CLK_20M;
wire [6:0] Tgc_Data;
TGC_ROM TGC_ROM_inst (
.address ( Tgc_Counter[7:1] ),
.clock ( CLK_20M ),
.q ( Tgc_Data )
);
always @(posedge CLK_20M or posedge Pr_Gate) begin
if(Pr_Gate) begin
Tgc_Counter <= 9'd0;
Send_Counter <= 8'b0;
end
else begin
if(Tgc_Counter < 9'd255) begin
if( Send_Counter <8'd3) begin
sync <= 1'b1;
Send_Counter <= Send_Counter + 1'b1;
//Send_Data <= {2'b0,{1'b0,TGC_Data[6:0]}+{2'b0,TGC_Data[6:1]}+{2'b0,Gain[6:1]},6'b0};
//Send_Data <= {2'b0,1'b1,Tgc_Counter[7:1],6'b0};
Send_Data <= {2'b0,({1'b0,Tgc_Data[6:0]}+{1'b0,Gain[5:0],1'b0}),6'b0};
//Send_Data <= {2'b0,8'd255,6'b0};
end
else if(Send_Counter <8'd19) begin
Send_Counter <= Send_Counter + 1'b1;
sync <= 1'b0;
sdin <= Send_Data[8'd18-Send_Counter];
end
else begin
sync <= 1'b1;
Send_Counter <= 8'd0;
Tgc_Counter <= Tgc_Counter + 1'b1;
end
end
else begin
if( Send_Counter <8'd3) begin
sync <= 1'b1;
Send_Counter <= Send_Counter + 1'b1;
//Send_Data <= {2'b0,{1'b0,TGC_Data[6:0]}+{2'b0,TGC_Data[6:1]}+{2'b0,Gain[6:1]},6'b0};
Send_Data <= {2'b0,{1'b0,Gain[5:0],1'b0},6'b0};
//Send_Data <= {2'b0,8'h0,6'b0};
//Send_Data <= {2'b0,8'h80,6'b0};
end
else if(Send_Counter <8'd19) begin
Send_Counter <= Send_Counter + 1'b1;
sync <= 1'b0;
sdin <= Send_Data[8'd18-Send_Counter];
end
else begin
sync <= 1'b1;
//Send_Counter <= 8'd255;
end
end
end
end
reg RX_Gate_Reg;
reg Pr_Gate_Reg;
reg Sample_Gate_Reg;
reg End_Gate_Reg;
always @(posedge AD_CLK) begin
RX_Gate_Reg <= RX_Gate;
Pr_Gate_Reg <= Pr_Gate;
Sample_Gate_Reg <= Sample_Gate;
End_Gate_Reg <= End_Gate;
end
wire [15:0] DAS_Value;
wire So_Gate;
wire [7:0] Coheren_Coff;
Receive Receive_Inst(
.AD_CLK(AD_CLK),
.Data_A(Data_A),
.Data_B(Data_B),
.Data_C(Data_C),
.Data_D(Data_D),
.Data_E(Data_E),
.Data_F(Data_F),
.Data_G(Data_G),
.Data_H(Data_H),
.Line_Num(Line_Num), //Line Num,256 Lines totally,0~255
.Focus_Num(Focus_Num),//Focus_Num[7:6]), //Focus_num ,4 totally
.Pr_Gate(Pr_Gate_Reg), //prepare for everythings
.RX_Gate(RX_Gate_Reg), // Start Transmit
.Sample_Gate(Sample_Gate_Reg),
.End_Gate(End_Gate_Reg),
.So_Gate(So_Gate), //output Enable
.DAS_Value(DAS_Value),
.Coheren_Coff(Coheren_Coff),
);
wire [29:0] Match_Filter_Data;
wire MF_Output_RDY;
wire MF_Output_Valid;
//match 2-4 8-10 filter
//80taps,
matchfilter MatchFilter_Inst(
.clk(AD_CLK),
.reset_n(1'b1),
.ast_sink_data(DAS_Value[14:0]), //15bit
.ast_sink_valid(So_Gate),
.ast_source_ready(1'b1),
.ast_sink_error(2'b00),
.ast_source_data(Match_Filter_Data), //30bit
.ast_sink_ready(MF_Output_RDY),
.ast_source_valid(MF_Output_Valid),
.ast_source_error()
);
/*
wire [38:0] Coherent_Result;
reg [7:0] Coheren_Coff_REG[35:0];
//Coff delay 29clk to Data,
//matchfilter delay 64clk to input,
//so Coff should delay more 64-29=35clk
integer i;
always @(posedge AD_CLK) begin
Coheren_Coff_REG[0] <= Coheren_Coff;
for(i=0;i<8'd34;i=i+1) begin
Coheren_Coff_REG[i+1] <= Coheren_Coff_REG[i] ;
end
end
mult30_9 mult30_9_inst (
.clock ( AD_CLK ),
.dataa ( Match_Filter_Data ),
.datab ( {1'b0,Coheren_Coff_REG[29]} ),
.result ( Coherent_Result )
);
wire [29:0] ABS_Data;
ABS ABS_inst (
.data ( Coherent_Result[38:8]),//Match_Filter_Data ),//Coherent_Result[38:8]) ,need change input bit width
.result ( ABS_Data )
);
*/
wire [29:0] ABS_Data;
ABS ABS_inst (
.data ( Match_Filter_Data ),
.result ( ABS_Data )
);
//wire [28:0] LF_Data;
wire LF_Valid;
wire [30:0] LF_Data;
lf LF_Inst(
.clk(AD_CLK),
.reset_n(1'b1),
.ast_sink_data(ABS_Data[26:12]), //15bit
.ast_sink_valid(MF_Output_Valid),
.ast_source_ready(1'b1),
.ast_sink_error(2'b00),
.ast_source_data(LF_Data), //31bit
.ast_sink_ready(),
.ast_source_valid(LF_Valid),
.ast_source_error()
);
wire [12:0] Log_IN;
//assign Log_IN =(LF_Data[30])?13'd0:((LF_Data[30:14] > 18'd8091)?13'd8191:LF_Data[26:14]);
assign Log_IN =(LF_Data[30])?13'd0:((LF_Data[30:12] > 18'd8091)?13'd8191:LF_Data[24:12]);
//assign Log_IN =(LF_Data[30])?13'd0:((LF_Data[28:13] > 18'd8091)?13'd8191:LF_Data[25:13]);
wire [7:0] Log_OUT;
LOG_Table LOG_Table_inst (
.address ( Log_IN),
.clock ( AD_CLK ),
.q ( Log_OUT )
);
reg [8:0] WR_RAM_ADDR;
reg [7:0] LF_Reg;
reg [7:0] Interlace_Counter;
reg [7:0] Log1,Log2,Log3,Log4,Log5,Log6,Log7,Log8,Log9,Log10,Log11,Log12,Log13,Log14,Log15;
reg [11:0] Sum_Log;
reg [15:0] Sample_Counter;
reg Seg_Enable;
reg [7:0] Interlace;
always @(*) begin
case(Zoom)
2'b00: //40mm
Interlace <= 8'd4;
2'b01: //63mm
Interlace <= 8'd7;
2'b10: //78mm
Interlace <= 8'd9;
2'b11: //102mm
Interlace <= 8'd12;
endcase
end
wire [7:0] Base_Noise1;
wire [7:0] Base_Noise2;
//wire [7:0] Focus_Num;
wire [7:0] Line_Num_Test;
Test Test_inst (
.address ( 1'b0 ),
.clock ( AD_CLK ),
.q ( {Base_Noise1,Base_Noise2} )
);
always @(posedge AD_CLK or negedge LF_Valid ) begin
if(~LF_Valid) begin
Interlace_Counter <= 8'd0;
WR_RAM_ADDR[8:0] <= 8'd0;
Sample_Counter <= 16'd0;
end
else begin
Log15 <= Log14;
Log14 <= Log13;
Log13 <= Log12;
Log12 <= Log11;
Log11 <= Log10;
Log10 <= Log9;
Log9 <= Log8;
Log8 <= Log7;
Log7 <= Log6;
Log6 <= Log5;
Log5 <= Log4;
Log4 <= Log3;
Log3 <= Log2;
Log2 <= Log1;
Log1 <= Log_OUT;
Sum_Log <= Log1+Log2+Log3+Log4+Log5+Log6+Log7+Log8+Log9+Log10+Log11+Log12+Log13+Log14+Log15;
if(Sample_Counter <16'd16000) begin
Sample_Counter <= Sample_Counter + 1'b1;
end
if(Sample_Counter <=16'd900) begin //<15mm
if(Focus_Num[1:0] == 2'b00) begin
Seg_Enable <= 1'b1;
end
else begin
Seg_Enable <= 1'b0;
end
LF_Reg <= (Sum_Log[11:4]>Base_Noise1)? (Sum_Log[11:4]-Base_Noise1): 8'd0 ;
end
else if(Sample_Counter <=16'd1599) begin //<25mm
if(Focus_Num[1:0] == 2'b01) begin
Seg_Enable <= 1'b1;
end
else begin
Seg_Enable <= 1'b0;
end
LF_Reg <= Sum_Log[11:4];
end
else begin
if(Focus_Num[1:0] == 2'b11) begin
Seg_Enable <= 1'b1;
end
else begin
Seg_Enable <= 1'b0;
end
LF_Reg <= (Sum_Log[11:4]>Base_Noise2)? (Sum_Log[11:4]-Base_Noise2): 8'd0 ;
end
if(Interlace_Counter < Interlace) begin
Interlace_Counter <= Interlace_Counter + 1'b1;
end
else begin
if(WR_RAM_ADDR[8:0] <9'd511) begin
WR_RAM_ADDR[8:0] <= WR_RAM_ADDR[8:0] + 1'b1;
end
Interlace_Counter <= 8'd0;
end
end
end
/*
reg Toggle;
always @(posedge Envelop) begin
Toggle <= ~Toggle;
end
IMG_BUFFER IMG_BUFFER_inst (
.data ( LF_Reg ),
.rdaddress ( {Toggle,Trans_Addr} ),
.rdclock ( CC3200_SPI_CS ),
.wraddress ( {~Toggle,WR_RAM_ADDR} ),
.wrclock ( AD_CLK ),
.wren ( LF_Valid & Seg_Enable ),
.q ( Trans_Data )
);
*/
reg [1:0] Toggle;
always @(posedge Envelop) begin
Toggle <= Toggle + 1'b1;
end
wire [7:0] Trans_Data1,Trans_Data2;
IMG_TRI_BUFFER IMG_TRI_BUFFER_inst (
.data ( LF_Reg ),
.rdaddress_a ( {Toggle[1:0]-2'b01,Trans_Addr} ),
.rdaddress_b ( {Toggle[1:0]-2'b10,Trans_Addr} ),
.rdclock ( CC3200_SPI_CS ),
.wraddress ( {Toggle[1:0],WR_RAM_ADDR} ),
.wrclock ( AD_CLK ),
.wren ( LF_Valid & Seg_Enable ),
.qa ( Trans_Data1 ),
.qb ( Trans_Data2 )
);
assign Trans_Data ={1'b0,Trans_Data1} + {1'b0,Trans_Data2};
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:19:20 04/17/2017
// Design Name:
// Module Name: decryptor
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module decrypter(
input clk,
input reset,
input [7:0] encrypted_data,
input decrypter_active,
input [63:0] key,
output reg [14:0] read_addr,
output reg [7:0] decrypted_data,
output reg [14:0] write_addr,
output reg done
);
wire [63:0] message;
wire [63:0] decrypted;
wire algo_done;
reg algo_en, ack;
decrypt_dumb uut (
.message(message),
.DESkey(key),
.decrypted(decrypted),
.done(algo_done),
.clk(clk),
.reset(reset),
.enable(algo_en),
.ack(ack)
);
// parameter [7:0] KEY = 8'b10110011;
reg [7:0] pixels [7:0];
reg [7:0] dec_pixels [7:0];
reg ready_to_write;
reg [2:0] read_count;
reg [2:0] write_count;
reg [14:0] counter;
reg [14:0] last_write_count;
assign message = {pixels[7], pixels[6], pixels[5], pixels[4], pixels[3], pixels[2], pixels[1], pixels[0]};
/*always @(posedge done) begin
//copy decrypted into mem
integer i;
for (int i = 0; i < 8; i = i + 1) begin
dec_pixels[i] <= decrypted[8 * i +: 8];
end
ready_to_write <= 1;
end*/
always @(posedge clk) begin
if (reset) begin
read_count <= 0;
write_count <= 0;
counter <= 0;
last_write_count <= 0;
algo_en <= 0;
ready_to_write <= 0;
end else begin
if (decrypter_active) begin
// decryption algo
// decrypted_data <= encrypted_data ^ KEY;
pixels[read_count] <= encrypted_data;
if (read_count == 3'd7) begin
algo_en <= 1;
ack <= 0;
end else begin
algo_en <= 0;
ack <= 0;
end
// end deryption algo
if (algo_done) begin: ALGO_DONE
//copy decrypted into mem
integer i;
for (i = 0; i < 8; i = i + 1) begin
dec_pixels[i] <= decrypted[8 * i +: 8];
end
ack <= 1;
ready_to_write <= 1;
end
if (ready_to_write) begin
write_addr <= last_write_count;
write_count <= write_count + 1;
last_write_count <= last_write_count + 1;
if (write_count == 3'd7)
ready_to_write <= 0;
end
decrypted_data <= dec_pixels[3'd7 - write_count];
read_addr <= counter;
read_count <= read_count + 1;
counter <= counter + 1;
if (counter > (175 * 175) & done)
done = 1'b1;
else
done = 1'b0;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_PP_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hd__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk , CLK_N );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, intclk, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A41OI_TB_V
`define SKY130_FD_SC_MS__A41OI_TB_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a41oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg A4;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
A4 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 A4 = 1'b0;
#100 B1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 A4 = 1'b1;
#280 B1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 A4 = 1'b0;
#460 B1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B1 = 1'b1;
#660 A4 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B1 = 1'bx;
#840 A4 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ms__a41oi dut (.A1(A1), .A2(A2), .A3(A3), .A4(A4), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A41OI_TB_V
|
module center_pos(x_row , y_col ,reset , clk ,center_x,center_y,valid);
input [15:0] x_row;
input [15:0] y_col ;
input reset;
input clk ;
input [15:0] valid ;
output [15:0] center_x;
output [15:0] center_y;
reg [15:0] center_x;
reg [15:0] center_y;
reg [31:0] center_x_temp;
reg [31:0] center_y_temp;
reg [31:0]pixel_counter ;
reg [31 : 0 ] dirty ;
always @ (posedge clk)
begin
if (dirty >= 32'h00075300 )
begin
//center_x = result_x[15:0];
//center_y = result_y[15:0];
center_x = 16'h1111;
//center_y = pixel_counter[15:0];
center_y = 16'h1111;
center_x_temp = 32'h00000000;
center_y_temp = 32'h00000000;
pixel_counter = 32'h0000FFFF;
dirty = 32'h00000000;
end
else //if (valid [ 7 : 0 ] == 8'b11111111 ) // pink
begin
center_y = dirty[31:16];
center_x = 16'hAAAA;
center_x_temp = center_x_temp + x_row ;
center_y_temp = center_y_temp + y_col ;
pixel_counter = pixel_counter + 32'h00000001;
dirty = dirty + 32'h00000001;
end
end
wire [31:0] result_x;
wire [31:0] result_y;
alt_div div_x(
.denom(pixel_counter),
.numer(center_x_temp),
.quotient(result_x),
.remain());
alt_div div_y(
.denom(pixel_counter),
.numer(center_y_temp),
.quotient(result_y),
.remain());
endmodule
|
/*
########################################################################
Generic Clock Domain Crossing Block
########################################################################
*/
module fifo_cdc (/*AUTOARG*/
// Outputs
wait_out, access_out, packet_out,
// Inputs
clk_in, reset_in, access_in, packet_in, clk_out, reset_out,
wait_in
);
parameter DW = 104;
parameter DEPTH = 32;
/********************************/
/*Incoming Packet */
/********************************/
input clk_in;
input reset_in;
input access_in;
input [DW-1:0] packet_in;
output wait_out;
/********************************/
/*Outgoing Packet */
/********************************/
input clk_out;
input reset_out;
output access_out;
output [DW-1:0] packet_out;
input wait_in;
//Local wires
wire wr_en;
wire rd_en;
wire empty;
wire full;
wire valid;
reg access_out;
assign wr_en = access_in;//&~full
assign rd_en = ~empty & ~wait_in;
assign wait_out = full;
//Keep access high until "acknowledge"
always @ (posedge clk_out or posedge reset_out)
if(reset_out)
access_out <=1'b0;
else if(~wait_in)
access_out <=rd_en;
//Read response fifo (from master)
defparam fifo.DW = DW;
defparam fifo.DEPTH = DEPTH;
fifo_async fifo (.prog_full (full),//stay safe for now
.full (),
// Outputs
.dout (packet_out[DW-1:0]),
.empty (empty),
.valid (valid),
// Inputs
.wr_rst (reset_in),
.rd_rst (reset_out),
.wr_clk (clk_in),
.rd_clk (clk_out),
.wr_en (wr_en),
.din (packet_in[DW-1:0]),
.rd_en (rd_en)
);
endmodule // fifo_cdc
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4B_4_V
`define SKY130_FD_SC_LS__OR4B_4_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog wrapper for or4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__or4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or4b_4 (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or4b_4 (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4B_4_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:24:43 06/12/2013
// Design Name: TopModule
// Module Name: D:/Xilinx_ISE_Pro/maju_ASIC_FPGA/SINGLECycle/main_Unit/testbnch.v
// Project Name: main_Unit
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: TopModule
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testbnch;
// Inputs
reg clk;
reg rst;
// Outputs
wire AN0;
wire AN1;
wire AN2;
wire AN3;
wire CA;
wire CB;
wire CC;
wire CD;
wire CE;
wire CF;
wire CG;
wire CDP;
wire clktick;
// Instantiate the Unit Under Test (UUT)
TopModule uut (
.clk(clk),
.rst(rst),
.AN0(AN0),
.AN1(AN1),
.AN2(AN2),
.AN3(AN3),
.CA(CA),
.CB(CB),
.CC(CC),
.CD(CD),
.CE(CE),
.CF(CF),
.CG(CG),
.CDP(CDP),
.clktick(clktick)
);
localparam T =20;
always begin
clk = 0;
#(T/2);
clk=1;
#(T/2);
end
initial begin
// Initialize Inputs
rst = 1;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
#600;
rst = 1;
#20;
rst = 0;
// Add stimulus here
end
endmodule
|
/*
F-PA unit (FPU arithmetic)
document: 12-006370-01-4A
unit: F-PA2-1
pages: 2-29..2-48
*/
module fpa(
input clk_sys,
input strob_fp,
input strobb_fp,
// sheet 1
input [0:15] w,
input taa,
// sheet 2
output t_1,
input t_1_d,
input m_1_d,
input tab,
input clockta,
input clocktb,
input clocktc,
output t_0_1,
output t_2_7,
output t_8_15,
output t_16_23,
output t_24_31,
output t_32_39,
// sheet 3
output m_1,
input ma,
input mb,
input clockm,
input _0_m,
output c0_eq_c1,
output c0,
output t1,
output t0_eq_c0,
output t0_neq_c0,
output t0_neq_t1,
output t0_neq_t_1,
output m0,
output t0,
// sheet 4
input fab,
input faa,
output fp0_,
// sheet 5
// sheet 6
input p_16,
output m14,
output m15,
// sheet 7
// (nothing)
// sheet 8
output fp16_,
// sheet 9
output t16,
// sheet 10
// (nothing)
// sheet 11
input m_32,
input p_32,
// sheet 12
// also w[8:11]
// sheet 13
// w[12:15]
// sheet 14
input m_40,
input cp,
input t_c,
output m32,
output m38,
output m39,
output c39,
// sheet 15
input fra,
input frb,
input p_40,
output p32_,
// sheet 16
input trb,
input _0_t,
output t39,
// sheet 17
input f9,
input lkb,
// sheet 18
input z_f,
input m_f,
input v_f,
input c_f,
output [0:15] zp,
// sheet 19
input [-2:7] d,
input _0_zp,
input zpb,
input zpa
);
// --- K bus ------------------------------------------------------------
wire [0:39] k;
k K(
.lkb(lkb),
.f9(f9),
.sum(sum),
.m(m[0:39]),
.w(w),
.k(k)
);
// --- T register -------------------------------------------------------
wire [-1:39] t;
t T(
.clk_sys(clk_sys),
._0_t(_0_t),
.taa(taa),
.tab(tab),
.trb(trb),
.clockta(clockta),
.clocktb(clocktb),
.clocktc(clocktc),
.t_1_d(t_1_d),
.k(k),
.m_1(m[-1]),
.t(t)
);
assign t_1 = t[-1];
assign t0 = t[0];
assign t1 = t[1];
assign t16 = t[16];
assign t39 = t[39];
assign t0_eq_c0 = t[0] == c[0];
assign t0_neq_c0 = c[0] != t[0];
assign t0_neq_t1 = t[0] != t[1];
assign t0_neq_t_1 = t[0] != t[-1];
assign t_0_1 = |t[0:1];
assign t_2_7 = |t[2:7];
assign t_8_15 = |t[8:15];
assign t_16_23 = |t[16:23];
assign t_24_31 = |t[24:31];
assign t_32_39 = |t[32:39];
// --- M register -------------------------------------------------------
wire [-1:39] m;
m M(
.clk_sys(clk_sys),
._0_m(_0_m),
.clockm(clockm),
.ma(ma),
.mb(mb),
.m_32(m_32),
.m_40(m_40),
.m_1_d(m_1_d),
.t(t[0:39]),
.m(m)
);
assign m_1 = m[-1];
assign m0 = m[0];
assign m14 = m[14];
assign m15 = m[15];
assign m32 = m[32];
assign m38 = m[38];
assign m39 = m[39];
// --- C register -------------------------------------------------------
wire [0:39] c;
c C(
.clk_sys(clk_sys),
.t(t[0:39]),
.t_c(t_c),
.cp(cp),
.c(c)
);
assign c0_eq_c1 = c[0] == c[1];
assign c0 = c[0];
assign c39 = c[39];
// --- Mantissa ALU -----------------------------------------------------
wire [0:39] sum;
fpalu FPALU(
.t(t[0:39]),
.c(c),
.faa(faa),
.fab(fab),
.fra(fra),
.frb(frb),
.p_16(p_16),
.p_32(p_32),
.p_40(p_40),
.fp0_(fp0_), // carry out above bit 0
.fp16_(fp16_), // carry out above bit 16
.p32_(p32_), // carry out above bit 32
.sum(sum)
);
// --- ZP bus -----------------------------------------------------------
zp ZP(
._0_zp(_0_zp),
.zpa(zpa),
.zpb(zpb),
.t(t[0:39]),
.d(d[0:7]),
.z_f(z_f),
.m_f(m_f),
.v_f(v_f),
.c_f(c_f),
.zp(zp)
);
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
module top(input count, count_sw, thresh_sw,
output gtu, gts, ltu, lts, geu, ges, leu, les, zero, max,
output gtu_n, gts_n, ltu_n, lts_n, geu_n, ges_n, leu_n, les_n, zero_n, max_n
);
reg [31:0] threshold = 32'b0;
reg [31:0] threshold_down = 32'b0;
reg [31:0] counter = 32'b0;
reg [31:0] counter_down = 32'b0;
wire clk;
BUFG bufg(.I(count), .O(clk));
always @(posedge clk) begin
if (count_sw) begin
counter <= counter + 1;
counter_down <= counter_down - 1;
end
if (thresh_sw) begin
threshold <= counter - 32'd31;
threshold_down <= counter_down + 32'd31;
end else begin
threshold <= threshold + 1;
threshold_down <= threshold_down - 1;
end
end
assign zero = counter == 32'b0;
assign max = counter == 32'hFFFFFFFF;
assign gtu = counter > threshold;
assign gts = $signed(counter) > $signed(threshold);
assign ltu = counter < threshold;
assign lts = $signed(counter) < $signed(threshold);
assign geu = counter >= threshold;
assign ges = $signed(counter) >= $signed(threshold);
assign leu = counter <= threshold;
assign les = $signed(counter) <= $signed(threshold);
assign zero_n = counter_down == 32'b0;
assign max_n = counter_down == 32'hFFFFFFFF;
assign gtu_n = counter_down > threshold_down;
assign gts_n = $signed(counter_down) > $signed(threshold_down);
assign ltu_n = counter_down < threshold_down;
assign lts_n = $signed(counter_down) < $signed(threshold_down);
assign geu_n = counter_down >= threshold_down;
assign ges_n = $signed(counter_down) >= $signed(threshold_down);
assign leu_n = counter_down <= threshold_down;
assign les_n = $signed(counter_down) <= $signed(threshold_down);
endmodule
|
//--------------------------------------------------------------------------------
// sync.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Synchronizes input with clock on rising or falling edge and does some
// optional preprocessing. (Noise filter and demux.)
//
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Verilog Version + cleanups created by Ian Davis - mygizmos.org
// Revised to carefully avoid any cross-connections between indata
// bits from the I/O's until a couple flops have sampled everything.
// Also moved testcount & numberScheme selects from top level here.
//
`timescale 1ns/100ps
module sync (clock, indata, intTestMode, numberScheme, filter_mode, demux_mode, falling_edge, outdata);
input clock;
input [31:0] indata;
input intTestMode;
input numberScheme;
input filter_mode;
input demux_mode;
input falling_edge;
output [31:0] outdata;
//
// Sample config flags (for better synthesis)...
//
dly_signal sampled_intTestMode_reg (clock, intTestMode, sampled_intTestMode);
dly_signal sampled_numberScheme_reg (clock, numberScheme, sampled_numberScheme);
//
// Synchronize indata guarantees use of iob ff on spartan 3 (as filter and demux do)
//
wire [31:0] sync_indata, sync_indata180;
ddr_inbuf inbuf (clock, indata, sync_indata, sync_indata180);
//
// Internal test mode. Put aa 8-bit test pattern munged in
// different ways onto the 32-bit input...
//
reg [7:0] testcount, next_testcount;
initial testcount=0;
always @ (posedge clock) testcount = next_testcount;
always @* begin #1; next_testcount = testcount+1'b1; end
wire [7:0] testcount1 = {
testcount[0],testcount[1],testcount[2],testcount[3],
testcount[4],testcount[5],testcount[6],testcount[7]};
wire [7:0] testcount2 = {
testcount[3],testcount[2],testcount[1],testcount[0],
testcount[4],testcount[5],testcount[6],testcount[7]};
wire [7:0] testcount3 = {
testcount[3],testcount[2],testcount[1],testcount[0],
testcount[7],testcount[6],testcount[5],testcount[4]};
wire [31:0] itm_count;
(* equivalent_register_removal = "no" *)
dly_signal #(32) sampled_testcount_reg (clock, {testcount3,testcount2,testcount1,testcount}, itm_count);
//wire [31:0] itm_indata = (sampled_intTestMode) ? {testcount3,testcount2,testcount1,testcount} : sync_indata;
//wire [31:0] itm_indata180 = (sampled_intTestMode) ? {~testcount3,~testcount2,~testcount1,~testcount} : sync_indata180;
wire [31:0] itm_indata = (sampled_intTestMode) ? itm_count : sync_indata;
wire [31:0] itm_indata180 = (sampled_intTestMode) ? ~itm_count : sync_indata180;
//
// Instantiate demux. Special case for number scheme mode, since demux upper bits we have
// the final full 32-bit shouldn't be swapped. So it's preswapped here, to "undo" the final
// numberscheme on output...
//
wire [31:0] demuxL_indata;
demux demuxL (
.clock(clock),
.indata(itm_indata[15:0]),
.indata180(itm_indata180[15:0]),
.outdata(demuxL_indata));
wire [31:0] demuxH_indata;
demux demuxH (
.clock(clock),
.indata(itm_indata[31:16]),
.indata180(itm_indata180[31:16]),
.outdata(demuxH_indata));
wire [31:0] demux_indata = (sampled_numberScheme) ? {demuxH_indata[15:0],demuxH_indata[31:16]} : demuxL_indata;
//
// Instantiate noise filter...
//
wire [31:0] filtered_indata;
filter filter (
.clock(clock),
.indata(itm_indata),
.indata180(itm_indata180),
.outdata(filtered_indata));
//
// Another pipeline step for indata selector to not decrease maximum clock rate...
//
reg [1:0] select, next_select;
reg [31:0] selectdata, next_selectdata;
reg [31:0] outdata;
always @(posedge clock)
begin
select = next_select;
selectdata = next_selectdata;
end
always @*
begin
#1;
if (demux_mode) // IED - better starting point for synth tools...
next_select = 2'b10;
else if (filter_mode)
next_select = 2'b11;
else next_select = {1'b0,falling_edge};
// 4:1 mux...
case (select)
2'b00 : next_selectdata = itm_indata;
2'b01 : next_selectdata = itm_indata180;
2'b10 : next_selectdata = demux_indata;
2'b11 : next_selectdata = filtered_indata;
endcase
//
// Apply number scheme. ie: swap upper/lower 16 bits as desired...
//
outdata = (sampled_numberScheme) ? {selectdata[15:0],selectdata[31:16]} : selectdata;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:57:50 08/25/2009
// Design Name:
// Module Name: mcu_cmd
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mcu_cmd(
input clk,
input cmd_ready,
input param_ready,
input [7:0] cmd_data,
input [7:0] param_data,
output [2:0] mcu_mapper,
output mcu_rrq,
output mcu_write,
output mcu_wrq,
input mcu_rq_rdy,
output [7:0] mcu_data_out,
input [7:0] mcu_data_in,
output [7:0] spi_data_out,
input [31:0] spi_byte_cnt,
input [2:0] spi_bit_cnt,
output [23:0] addr_out,
output [23:0] saveram_mask_out,
output [23:0] rom_mask_out,
// SD "DMA" extension
output SD_DMA_EN,
input SD_DMA_STATUS,
input SD_DMA_NEXTADDR,
input [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_SRAM_WE,
output [1:0] SD_DMA_TGT,
output SD_DMA_PARTIAL,
output [10:0] SD_DMA_PARTIAL_START,
output [10:0] SD_DMA_PARTIAL_END,
output reg SD_DMA_START_MID_BLOCK,
output reg SD_DMA_END_MID_BLOCK,
// DAC
output [10:0] dac_addr_out,
input DAC_STATUS,
output reg dac_play_out = 0,
output reg dac_reset_out = 0,
output reg [2:0] dac_vol_select_out = 3'b000,
output reg dac_palmode_out = 0,
// MSU data
output [13:0] msu_addr_out,
input [7:0] MSU_STATUS,
output [5:0] msu_status_reset_out,
output [5:0] msu_status_set_out,
output msu_status_reset_we,
input [31:0] msu_addressrq,
input [15:0] msu_trackrq,
input [7:0] msu_volumerq,
output [13:0] msu_ptr_out,
output msu_reset_out,
// feature enable
output reg [7:0] featurebits_out,
output reg region_out,
// SNES sync/clk
input snes_sysclk,
// snes cmd interface
input [7:0] snescmd_data_in,
output reg [7:0] snescmd_data_out,
output reg [8:0] snescmd_addr_out,
output reg snescmd_we_out,
// cheat configuration
output reg [7:0] cheat_pgm_idx_out,
output reg [31:0] cheat_pgm_data_out,
output reg cheat_pgm_we_out,
// debug
output DBG_mcu_nextaddr
);
initial begin
region_out = 0;
SD_DMA_START_MID_BLOCK = 0;
SD_DMA_END_MID_BLOCK = 0;
end
wire [31:0] snes_sysclk_freq;
clk_test snes_clk_test (
.clk(clk),
.sysclk(snes_sysclk),
.snes_sysclk_freq(snes_sysclk_freq)
);
reg [2:0] MAPPER_BUF;
reg [23:0] ADDR_OUT_BUF;
reg [10:0] DAC_ADDR_OUT_BUF;
reg [7:0] DAC_VOL_OUT_BUF;
reg [13:0] MSU_ADDR_OUT_BUF;
reg [13:0] MSU_PTR_OUT_BUF;
reg [5:0] msu_status_set_out_buf;
reg [5:0] msu_status_reset_out_buf;
reg msu_status_reset_we_buf;
reg MSU_RESET_OUT_BUF;
reg [31:0] SNES_SYSCLK_FREQ_BUF;
reg [7:0] MCU_DATA_OUT_BUF;
reg [7:0] MCU_DATA_IN_BUF;
reg [2:0] mcu_nextaddr_buf;
wire mcu_nextaddr;
reg DAC_STATUSr;
reg SD_DMA_STATUSr;
reg [7:0] MSU_STATUSr;
always @(posedge clk) begin
DAC_STATUSr <= DAC_STATUS;
SD_DMA_STATUSr <= SD_DMA_STATUS;
MSU_STATUSr <= MSU_STATUS;
end
reg SD_DMA_PARTIALr;
assign SD_DMA_PARTIAL = SD_DMA_PARTIALr;
reg SD_DMA_ENr;
assign SD_DMA_EN = SD_DMA_ENr;
reg [1:0] SD_DMA_TGTr;
assign SD_DMA_TGT = SD_DMA_TGTr;
reg [10:0] SD_DMA_PARTIAL_STARTr;
reg [10:0] SD_DMA_PARTIAL_ENDr;
assign SD_DMA_PARTIAL_START = SD_DMA_PARTIAL_STARTr;
assign SD_DMA_PARTIAL_END = SD_DMA_PARTIAL_ENDr;
reg [23:0] SAVERAM_MASK;
reg [23:0] ROM_MASK;
assign spi_data_out = MCU_DATA_IN_BUF;
initial begin
ADDR_OUT_BUF = 0;
DAC_ADDR_OUT_BUF = 0;
MSU_ADDR_OUT_BUF = 0;
SD_DMA_ENr = 0;
MAPPER_BUF = 1;
SD_DMA_PARTIALr = 0;
end
// command interpretation
always @(posedge clk) begin
snescmd_we_out <= 1'b0;
cheat_pgm_we_out <= 1'b0;
dac_reset_out <= 1'b0;
if (cmd_ready) begin
case (cmd_data[7:4])
4'h3: // select mapper
MAPPER_BUF <= cmd_data[2:0];
4'h4: begin// SD DMA
SD_DMA_ENr <= 1;
SD_DMA_TGTr <= cmd_data[1:0];
SD_DMA_PARTIALr <= cmd_data[2];
end
4'h8: SD_DMA_TGTr <= 2'b00;
4'h9: SD_DMA_TGTr <= 2'b00; // cmd_data[1:0]; // not implemented
// 4'hE:
// select memory unit
endcase
end else if (param_ready) begin
casex (cmd_data[7:0])
8'h1x:
case (spi_byte_cnt)
32'h2:
ROM_MASK[23:16] <= param_data;
32'h3:
ROM_MASK[15:8] <= param_data;
32'h4:
ROM_MASK[7:0] <= param_data;
endcase
8'h2x:
case (spi_byte_cnt)
32'h2:
SAVERAM_MASK[23:16] <= param_data;
32'h3:
SAVERAM_MASK[15:8] <= param_data;
32'h4:
SAVERAM_MASK[7:0] <= param_data;
endcase
8'h4x:
SD_DMA_ENr <= 1'b0;
8'h6x:
case (spi_byte_cnt)
32'h2: begin
SD_DMA_START_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_STARTr[10:9] <= param_data[1:0];
end
32'h3:
SD_DMA_PARTIAL_STARTr[8:0] <= {param_data, 1'b0};
32'h4: begin
SD_DMA_END_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_ENDr[10:9] <= param_data[1:0];
end
32'h5:
SD_DMA_PARTIAL_ENDr[8:0] <= {param_data, 1'b0};
endcase
8'h9x:
MCU_DATA_OUT_BUF <= param_data;
8'hd0:
case (spi_byte_cnt)
32'h2:
snescmd_addr_out[7:0] <= param_data;
32'h3:
snescmd_addr_out[8] <= param_data[0];
endcase
8'hd1:
snescmd_addr_out <= snescmd_addr_out + 1;
8'hd2: begin
case (spi_byte_cnt)
32'h2:
snescmd_we_out <= 1'b1;
32'h3:
snescmd_addr_out <= snescmd_addr_out + 1;
endcase
snescmd_data_out <= param_data;
end
8'hd3: begin
case (spi_byte_cnt)
32'h2:
cheat_pgm_idx_out <= param_data[2:0];
32'h3:
cheat_pgm_data_out[31:24] <= param_data;
32'h4:
cheat_pgm_data_out[23:16] <= param_data;
32'h5:
cheat_pgm_data_out[15:8] <= param_data;
32'h6: begin
cheat_pgm_data_out[7:0] <= param_data;
cheat_pgm_we_out <= 1'b1;
end
endcase
end
8'he0:
case (spi_byte_cnt)
32'h2: begin
msu_status_set_out_buf <= param_data[5:0];
end
32'h3: begin
msu_status_reset_out_buf <= param_data[5:0];
msu_status_reset_we_buf <= 1'b1;
end
32'h4:
msu_status_reset_we_buf <= 1'b0;
endcase
8'he1: // pause DAC
dac_play_out <= 1'b0;
8'he2: // resume DAC
dac_play_out <= 1'b1;
8'he3: // reset DAC (set DAC playback address = 0)
dac_reset_out <= 1'b1; // reset by default value, see above
8'he4: // reset MSU read buffer pointer
case (spi_byte_cnt)
32'h2: begin
MSU_PTR_OUT_BUF[13:8] <= param_data[5:0];
MSU_PTR_OUT_BUF[7:0] <= 8'h0;
end
32'h3: begin
MSU_PTR_OUT_BUF[7:0] <= param_data;
MSU_RESET_OUT_BUF <= 1'b1;
end
32'h4:
MSU_RESET_OUT_BUF <= 1'b0;
endcase
8'hec: // set DAC properties
begin
dac_vol_select_out <= param_data[2:0];
dac_palmode_out <= param_data[7];
end
8'hed:
featurebits_out <= param_data;
8'hee:
region_out <= param_data[0];
endcase
end
end
always @(posedge clk) begin
if(param_ready && cmd_data[7:4] == 4'h0) begin
case (cmd_data[1:0])
2'b01: begin
case (spi_byte_cnt)
32'h2: begin
DAC_ADDR_OUT_BUF[10:8] <= param_data[2:0];
DAC_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
DAC_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
2'b10: begin
case (spi_byte_cnt)
32'h2: begin
MSU_ADDR_OUT_BUF[13:8] <= param_data[5:0];
MSU_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
MSU_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
default:
case (spi_byte_cnt)
32'h2: begin
ADDR_OUT_BUF[23:16] <= param_data;
ADDR_OUT_BUF[15:0] <= 16'b0;
end
32'h3:
ADDR_OUT_BUF[15:8] <= param_data;
32'h4:
ADDR_OUT_BUF[7:0] <= param_data;
endcase
endcase
end else if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4)
&& (cmd_data[3])
&& (spi_byte_cnt >= (32'h1+cmd_data[4])))
) begin
case (SD_DMA_TGTr)
2'b00: ADDR_OUT_BUF <= ADDR_OUT_BUF + 1;
2'b01: DAC_ADDR_OUT_BUF <= DAC_ADDR_OUT_BUF + 1;
2'b10: MSU_ADDR_OUT_BUF <= MSU_ADDR_OUT_BUF + 1;
endcase
end
end
// value fetch during last SPI bit
always @(posedge clk) begin
if (cmd_data[7:4] == 4'h8 && mcu_nextaddr)
MCU_DATA_IN_BUF <= mcu_data_in;
else if (cmd_ready | param_ready /* bit_cnt == 7 */) begin
if (cmd_data[7:0] == 8'hF0)
MCU_DATA_IN_BUF <= 8'hA5;
else if (cmd_data[7:0] == 8'hF1)
case (spi_byte_cnt[0])
1'b1: // buffer status (1st byte)
MCU_DATA_IN_BUF <= {SD_DMA_STATUSr, DAC_STATUSr, MSU_STATUSr[7], 5'b0};
1'b0: // control status (2nd byte)
MCU_DATA_IN_BUF <= {1'b0, MSU_STATUSr[6:0]};
endcase
else if (cmd_data[7:0] == 8'hF2)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_addressrq[31:24];
32'h2:
MCU_DATA_IN_BUF <= msu_addressrq[23:16];
32'h3:
MCU_DATA_IN_BUF <= msu_addressrq[15:8];
32'h4:
MCU_DATA_IN_BUF <= msu_addressrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF3)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_trackrq[15:8];
32'h2:
MCU_DATA_IN_BUF <= msu_trackrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF4)
MCU_DATA_IN_BUF <= msu_volumerq;
else if (cmd_data[7:0] == 8'hFE)
case (spi_byte_cnt)
32'h1:
SNES_SYSCLK_FREQ_BUF <= snes_sysclk_freq;
32'h2:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
32'h3:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
32'h4:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
32'h5:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
endcase
else if (cmd_data[7:0] == 8'hFF)
MCU_DATA_IN_BUF <= param_data;
else if (cmd_data[7:0] == 8'hD1)
MCU_DATA_IN_BUF <= snescmd_data_in;
end
end
// nextaddr pulse generation
always @(posedge clk) begin
mcu_nextaddr_buf <= {mcu_nextaddr_buf[1:0], mcu_rq_rdy};
end
parameter ST_RQ = 2'b01;
parameter ST_IDLE = 2'b10;
reg [1:0] rrq_state;
initial rrq_state = ST_IDLE;
reg mcu_rrq_r;
reg [1:0] wrq_state;
initial wrq_state = ST_IDLE;
reg mcu_wrq_r;
always @(posedge clk) begin
case(rrq_state)
ST_IDLE: begin
if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
mcu_rrq_r <= 1'b1;
rrq_state <= ST_RQ;
end else
rrq_state <= ST_IDLE;
end
ST_RQ: begin
mcu_rrq_r <= 1'b0;
rrq_state <= ST_IDLE;
end
endcase
end
always @(posedge clk) begin
case(wrq_state)
ST_IDLE: begin
if(param_ready && cmd_data[7:4] == 4'h9) begin
mcu_wrq_r <= 1'b1;
wrq_state <= ST_RQ;
end else
wrq_state <= ST_IDLE;
end
ST_RQ: begin
mcu_wrq_r <= 1'b0;
wrq_state <= ST_IDLE;
end
endcase
end
// trigger for nextaddr
assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
assign mcu_rrq = mcu_rrq_r;
assign mcu_wrq = mcu_wrq_r;
assign mcu_write = SD_DMA_STATUS
? (SD_DMA_TGTr == 2'b00
? SD_DMA_SRAM_WE
: 1'b1
)
: 1'b1;
assign addr_out = ADDR_OUT_BUF;
assign dac_addr_out = DAC_ADDR_OUT_BUF;
assign msu_addr_out = MSU_ADDR_OUT_BUF;
assign msu_status_reset_we = msu_status_reset_we_buf;
assign msu_status_reset_out = msu_status_reset_out_buf;
assign msu_status_set_out = msu_status_set_out_buf;
assign msu_reset_out = MSU_RESET_OUT_BUF;
assign msu_ptr_out = MSU_PTR_OUT_BUF;
assign mcu_data_out = SD_DMA_STATUS ? SD_DMA_SRAM_DATA : MCU_DATA_OUT_BUF;
assign mcu_mapper = MAPPER_BUF;
assign rom_mask_out = ROM_MASK;
assign saveram_mask_out = SAVERAM_MASK;
assign DBG_mcu_nextaddr = mcu_nextaddr;
endmodule
|
/*
ORSoC GFX accelerator core
Copyright 2012, ORSoC, Per Lenander, Anton Fosselius.
RASTERIZER MODULE
This file is part of orgfx.
orgfx is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
orgfx is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public License
along with orgfx. If not, see <http://www.gnu.org/licenses/>.
*/
/*
This module takes a rect write or line write request and generates pixels in the span given by dest_pixel0-1.
Triangles can be declared by dest_pixel0-2, they are handled by the triangle module
The operation is clipped to the span given by clip_pixel0-1. Pixels outside the span are discarded.
If texturing is enabled, texture coordinates u (horizontal) and v (vertical) are emitted, offset and clipped by the span given by src_pixel0-1.
When all pixels have been generated and acked, the rasterizer acks the operation and returns to wait state.
*/
module gfx_rasterizer(clk_i, rst_i,
clip_ack_i, interp_ack_i, ack_o,
rect_write_i, line_write_i, triangle_write_i, interpolate_i, texture_enable_i,
//source pixel 0 and pixel 1
src_pixel0_x_i, src_pixel0_y_i, src_pixel1_x_i, src_pixel1_y_i,
//destination point 0, 1, 2
dest_pixel0_x_i, dest_pixel0_y_i,
dest_pixel1_x_i, dest_pixel1_y_i,
dest_pixel2_x_i, dest_pixel2_y_i,
clipping_enable_i,
//clip pixel 0 and pixel 1
clip_pixel0_x_i, clip_pixel0_y_i, clip_pixel1_x_i, clip_pixel1_y_i,
target_size_x_i, target_size_y_i,
x_counter_o, y_counter_o, u_o,v_o,
clip_write_o, interp_write_o,
triangle_edge0_o, triangle_edge1_o, triangle_area_o
);
parameter point_width = 16;
parameter subpixel_width = 16;
parameter delay_width = 5;
input clk_i;
input rst_i;
input clip_ack_i;
input interp_ack_i;
output reg ack_o;
input rect_write_i;
input line_write_i;
input triangle_write_i;
input interpolate_i;
input texture_enable_i;
//src pixels
input [point_width-1:0] src_pixel0_x_i;
input [point_width-1:0] src_pixel0_y_i;
input [point_width-1:0] src_pixel1_x_i;
input [point_width-1:0] src_pixel1_y_i;
//dest pixels
input signed [point_width-1:-subpixel_width] dest_pixel0_x_i;
input signed [point_width-1:-subpixel_width] dest_pixel0_y_i;
input signed [point_width-1:-subpixel_width] dest_pixel1_x_i;
input signed [point_width-1:-subpixel_width] dest_pixel1_y_i;
input signed [point_width-1:-subpixel_width] dest_pixel2_x_i;
input signed [point_width-1:-subpixel_width] dest_pixel2_y_i;
wire signed [point_width-1:0] p0_x = $signed(dest_pixel0_x_i[point_width-1:0]);
wire signed [point_width-1:0] p0_y = $signed(dest_pixel0_y_i[point_width-1:0]);
wire signed [point_width-1:0] p1_x = $signed(dest_pixel1_x_i[point_width-1:0]);
wire signed [point_width-1:0] p1_y = $signed(dest_pixel1_y_i[point_width-1:0]);
//clip pixels
input clipping_enable_i;
input [point_width-1:0] clip_pixel0_x_i;
input [point_width-1:0] clip_pixel0_y_i;
input [point_width-1:0] clip_pixel1_x_i;
input [point_width-1:0] clip_pixel1_y_i;
input [point_width-1:0] target_size_x_i;
input [point_width-1:0] target_size_y_i;
// Generated pixel coordinates
output reg [point_width-1:0] x_counter_o;
output reg [point_width-1:0] y_counter_o;
// Generated texture coordinates
output reg [point_width-1:0] u_o;
output reg [point_width-1:0] v_o;
// Write pixel output signals
output reg clip_write_o;
output reg interp_write_o;
output [2*point_width-1:0] triangle_edge0_o;
output [2*point_width-1:0] triangle_edge1_o;
output [2*point_width-1:0] triangle_area_o;
wire ack_i = interpolate_i ? interp_ack_i : clip_ack_i;
// Variables used in rect drawing
reg [point_width-1:0] rect_p0_x;
reg [point_width-1:0] rect_p0_y;
reg [point_width-1:0] rect_p1_x;
reg [point_width-1:0] rect_p1_y;
//line drawing reg & wires
wire raster_line_busy; // busy, drawing a line.
wire x_major; // is true if x is the major axis
wire valid_out;
reg draw_line; // trigger the line drawing.
wire [point_width-1:0] major_out; // the major axis
wire [point_width-1:0] minor_out; // the minor axis
wire request_next_pixel;
// State machine
reg [2:0] state;
parameter wait_state = 3'b000,
rect_state = 3'b001,
line_state = 3'b010,
triangle_state = 3'b011,
triangle_final_state = 3'b100;
// Write/ack counter
reg [delay_width-1:0] ack_counter;
always @(posedge clk_i or posedge rst_i)
if(rst_i)
ack_counter <= 1'b0;
else if(interpolate_i & ack_i & ~triangle_write_o)
ack_counter <= ack_counter - 1'b1;
else if(interpolate_i & triangle_write_o & ~ack_i)
ack_counter <= ack_counter + 1'b1;
// Rect drawing variables
always @(posedge clk_i or posedge rst_i)
begin
if(rst_i)
begin
rect_p0_x <= 1'b0;
rect_p0_y <= 1'b0;
rect_p1_x <= 1'b0;
rect_p1_y <= 1'b0;
end
else
begin
if(clipping_enable_i)
begin
// pixel0 x
if(p0_x < $signed(clip_pixel0_x_i)) // check if pixel is left of screen
rect_p0_x <= clip_pixel0_x_i;
else if(p0_x > $signed(clip_pixel1_x_i)) // check if pixel is right of screen
rect_p0_x <= clip_pixel1_x_i;
else
rect_p0_x <= p0_x;
// pixel0 y
if(p0_y < $signed(clip_pixel0_y_i)) // check if pixel is above the screen
rect_p0_y <= clip_pixel0_y_i;
else if(p0_y > $signed(clip_pixel1_y_i)) // check if pixel is below the screen
rect_p0_y <= clip_pixel1_y_i;
else
rect_p0_y <= p0_y;
// pixel1 x
if(p1_x < $signed(clip_pixel0_x_i)) // check if pixel is left of screen
rect_p1_x <= clip_pixel0_x_i;
else if(p1_x > $signed(clip_pixel1_x_i -1)) // check if pixel is right of screen
rect_p1_x <= clip_pixel1_x_i -1'b1;
else
rect_p1_x <= dest_pixel1_x_i[point_width-1:0] - 1;
// pixel1 y
if(p1_y < $signed(clip_pixel0_y_i)) // check if pixel is above the screen
rect_p1_y <= clip_pixel0_y_i;
else if(p1_y > $signed(clip_pixel1_y_i -1)) // check if pixel is below the screen
rect_p1_y <= clip_pixel1_y_i -1'b1;
else
rect_p1_y <= p1_y - 1;
end
else
begin
rect_p0_x <= p0_x >= 0 ? p0_x : 1'b0;
rect_p0_y <= p0_y >= 0 ? p0_y : 1'b0;
rect_p1_x <= (p1_x - 1) >= 0 ? p1_x - 1 : 1'b0;
rect_p1_y <= (p1_y - 1) >= 0 ? p1_y - 1 : 1'b0;
end
end
end
// Checks if the current line in the rect being drawn is complete
wire raster_rect_line_done = (x_counter_o >= rect_p1_x) | (texture_enable_i && (u_o >= src_pixel1_x_i-1));
// Checks if the current rect is completely drawn
// TODO: ugly fix to prevent the an extra pixel being written when texturing is enabled. Ugly.
//wire raster_rect_done = ack_i & (x_counter_o >= rect_p1_x) & ((y_counter_o >= rect_p1_y) | (texture_enable_i && (v_o >= src_pixel1_y_i-1)));
wire raster_rect_done = (ack_i | texture_enable_i) &
(x_counter_o >= rect_p1_x) &
((y_counter_o >= rect_p1_y) | (texture_enable_i && (v_o >= src_pixel1_y_i-1)));
// Special check if there are no pixels to draw at all (send ack immediately)
wire empty_raster = (rect_p0_x > rect_p1_x) | (rect_p0_y > rect_p1_y);
wire triangle_finished = ~interpolate_i | (ack_counter == 1'b0);
// Manage states
always @(posedge clk_i or posedge rst_i)
if(rst_i)
state <= wait_state;
else
case (state)
wait_state:
if(triangle_write_i)
state <= triangle_state;
else if(rect_write_i & !empty_raster) // if request for drawing a rect, go to rect drawing state
state <= rect_state;
else if(line_write_i)
state <= line_state; // if request for drawing a line, go to line drawing state
rect_state:
if(raster_rect_done) // if we are done drawing a rect, go to wait state
state <= wait_state;
line_state:
if(!raster_line_busy & !draw_line) // if we are done drawing a line, go to wait state
state <= wait_state;
triangle_state:
if(triangle_ack & triangle_finished)
state <= wait_state;
else if(triangle_ack)
state <= triangle_final_state;
triangle_final_state:
if(triangle_finished)
state <= wait_state;
endcase
// If interpolation is active, only write to interp module if queue is not full.
wire interp_ready = interpolate_i ? (ack_counter <= point_width) & ~interp_write_o : ack_i;
wire triangle_ready = interpolate_i ? (ack_counter <= point_width-1) & ~interp_write_o : ack_i;
// Manage outputs (mealy machine)
always @(posedge clk_i or posedge rst_i)
begin
// Reset
if(rst_i)
begin
ack_o <= 1'b0;
x_counter_o <= 1'b0;
y_counter_o <= 1'b0;
clip_write_o <= 1'b0;
interp_write_o <= 1'b0;
u_o <= 1'b0;
v_o <= 1'b0;
//reset line regs
draw_line <= 1'b0;
end
else
begin
case (state)
// Wait for incoming instructions
wait_state:
if(rect_write_i & !empty_raster) // Start a raster rectangle operation
begin
ack_o <= 1'b0;
clip_write_o <= 1'b1;
// Generate pixel coordinates
x_counter_o <= rect_p0_x;
y_counter_o <= rect_p0_y;
// Generate texture coordinates
u_o <= (($signed(clip_pixel0_x_i) < p0_x) ? 1'b0 :
$signed(clip_pixel0_x_i) - p0_x) + src_pixel0_x_i;
v_o <= (($signed(clip_pixel0_y_i) < p0_y) ? 1'b0 :
$signed(clip_pixel0_y_i) - p0_y) + src_pixel0_y_i;
end
else if(rect_write_i & empty_raster & !ack_o) // Start a raster rectangle operation
ack_o <= 1'b1;
// Start a raster line operation
else if(line_write_i)
begin
draw_line <= 1'b1;
ack_o <= 1'b0;
end
else
ack_o <= 1'b0;
// Rasterize a rectangle between p0 and p1 (rasterize = generate the pixels)
rect_state:
begin
if(ack_i) // If our last coordinate was acknowledged by a fragment processor
begin
if(raster_rect_line_done) // iterate through width of rect
begin
x_counter_o <= rect_p0_x;
y_counter_o <= y_counter_o + 1'b1;
u_o <= ($signed(clip_pixel0_x_i) < p0_x ? 1'b0 :
$signed(clip_pixel0_x_i) - p0_x) + $signed(src_pixel0_x_i);
v_o <= v_o + 1'b1;
end
else
begin
x_counter_o <= x_counter_o + 1'b1;
u_o <= u_o + 1'b1;
end
end
if(raster_rect_done) // iterate through height of rect (are we done?)
begin
clip_write_o <= 1'b0; // Only send ack when we get ack_i (see wait state)
ack_o <= 1'b1;
end
end
// Rasterize a line between dest_pixel0 and dest_pixel1 (rasterize = generate the pixels)
line_state:
begin
draw_line <= 1'b0;
clip_write_o <= raster_line_busy & valid_out;
x_counter_o <= x_major ? major_out : minor_out;
y_counter_o <= x_major ? minor_out : major_out;
ack_o <= !raster_line_busy & !draw_line;
end
triangle_state:
if(triangle_ack)
begin
interp_write_o <= 1'b0;
clip_write_o <= 1'b0;
if(triangle_finished)
ack_o <= 1'b1;
end
else if(~interpolate_i)
begin
x_counter_o <= triangle_x_o;
y_counter_o <= triangle_y_o;
clip_write_o <= triangle_write_o ;
end
else if(interpolate_i & interp_ready)
begin
x_counter_o <= triangle_x_o;
y_counter_o <= triangle_y_o;
// edge0, edge1 and area are set by the triangle module
interp_write_o <= triangle_write_o;
end
else
begin
interp_write_o <= 1'b0;
clip_write_o <= 1'b0;
end
triangle_final_state:
if(triangle_finished)
ack_o <= 1'b1;
endcase
end
end
// Request wire for line drawing module
assign request_next_pixel = ack_i & raster_line_busy;
// Instansiation of bresenham line drawing module
bresenham_line bresenham(
.clk_i ( clk_i ), //clock
.rst_i ( rst_i ), //rest
.pixel0_x_i ( dest_pixel0_x_i ), // left pixel x
.pixel0_y_i ( dest_pixel0_y_i ), // left pixel y
.pixel1_x_i ( dest_pixel1_x_i ), // right pixel x
.pixel1_y_i ( dest_pixel1_y_i ), // right pixel y
.draw_line_i ( draw_line ), // trigger for drawing a line
.read_pixel_i ( request_next_pixel ), // request next pixel
.busy_o ( raster_line_busy ), // is true while line is drawn
.x_major_o ( x_major ), // is true if x is the major axis
.major_o ( major_out ), // the major axis pixel coordinate
.minor_o ( minor_out ), // the minor axis pixel coordinate
.valid_o ( valid_out )
);
defparam bresenham.point_width = point_width;
defparam bresenham.subpixel_width = subpixel_width;
wire triangle_ack;
wire [point_width-1:0] triangle_x_o;
wire [point_width-1:0] triangle_y_o;
wire triangle_write_o;
// Triangle module instanciated
gfx_triangle triangle(
.clk_i (clk_i),
.rst_i (rst_i),
.ack_i (triangle_ready),
.ack_o (triangle_ack),
.triangle_write_i (triangle_write_i),
.texture_enable_i (texture_enable_i),
.dest_pixel0_x_i (dest_pixel0_x_i),
.dest_pixel0_y_i (dest_pixel0_y_i),
.dest_pixel1_x_i (dest_pixel1_x_i),
.dest_pixel1_y_i (dest_pixel1_y_i),
.dest_pixel2_x_i (dest_pixel2_x_i),
.dest_pixel2_y_i (dest_pixel2_y_i),
.x_counter_o (triangle_x_o),
.y_counter_o (triangle_y_o),
.triangle_edge0_o (triangle_edge0_o),
.triangle_edge1_o (triangle_edge1_o),
.triangle_area_o (triangle_area_o),
.write_o (triangle_write_o)
);
defparam triangle.point_width = point_width;
defparam triangle.subpixel_width = subpixel_width;
endmodule
|
//
// Conformal-LEC Version 16.10-d005 ( 21-Apr-2016 ) ( 64 bit executable )
//
module top ( n0 , n1 , n2 , n3 , n4 , n5 , n6 , n7 , n8 , n9 , n10 , n11 , n12 , n13 , n14 , n15 , n16 , n17 , n18 , n19 , n20 , n21 , n22 , n23 , n24 , n25 , n26 , n27 , n28 , n29 , n30 , n31 , n32 , n33 , n34 , n35 , n36 , n37 , n38 , n39 , n40 , n41 , n42 , n43 , n44 , n45 , n46 , n47 , n48 , n49 , n50 , n51 , n52 , n53 , n54 , n55 , n56 , n57 , n58 , n59 , n60 , n61 , n62 , n63 , n64 , n65 , n66 , n67 , n68 , n69 , n70 , n71 , n72 , n73 , n74 , n75 , n76 , n77 , n78 , n79 , n80 , n81 , n82 , n83 , n84 , n85 , n86 , n87 , n88 , n89 , n90 , n91 , n92 , n93 , n94 , n95 , n96 , n97 , n98 , n99 , n100 , n101 , n102 , n103 , n104 , n105 , n106 , n107 , n108 , n109 , n110 , n111 , n112 , n113 , n114 , n115 , n116 , n117 , n118 , n119 , n120 , n121 , n122 , n123 , n124 , n125 , n126 , n127 , n128 , n129 , n130 , n131 , n132 , n133 , n134 , n135 , n136 , n137 , n138 , n139 , n140 , n141 , n142 , n143 , n144 , n145 , n146 , n147 , n148 , n149 , n150 , n151 , n152 , n153 , n154 , n155 , n156 , n157 , n158 , n159 , n160 , n161 , n162 , n163 , n164 , n165 , n166 , n167 , n168 , n169 , n170 , n171 , n172 , n173 , n174 , n175 , n176 , n177 , n178 , n179 , n180 , n181 , n182 , n183 , n184 , n185 , n186 , n187 , n188 , n189 , n190 , n191 , n192 , n193 , n194 , n195 , n196 , n197 , n198 , n199 , n200 , n201 );
input n0 , n1 , n2 , n3 , n4 , n5 , n6 , n7 , n8 , n9 , n10 , n11 , n12 , n13 , n14 , n15 , n16 , n17 , n18 , n19 , n20 , n21 , n22 , n23 , n24 , n25 , n26 , n27 , n28 , n29 , n30 , n31 , n32 , n33 , n34 , n35 , n36 , n37 , n38 , n39 , n40 , n41 , n42 , n43 , n44 , n45 , n46 , n47 , n48 , n49 , n50 , n51 , n52 , n53 , n54 , n55 , n56 , n57 , n58 , n59 , n60 , n61 , n62 , n63 , n64 , n65 , n66 , n67 , n68 , n69 , n70 , n71 , n72 , n73 , n74 , n75 , n76 , n77 , n78 , n79 , n80 , n81 , n82 , n83 , n84 , n85 , n86 , n87 , n88 , n89 , n90 , n91 , n92 , n93 , n94 , n95 , n96 , n97 , n98 , n99 , n100 , n101 , n102 , n103 , n104 , n105 , n106 , n107 , n108 , n109 , n110 , n111 , n112 , n113 , n114 , n115 , n116 , n117 , n118 , n119 , n120 , n121 , n122 , n123 , n124 , n125 , n126 , n127 , n128 , n129 , n130 , n131 , n132 , n133 , n134 , n135 , n136 , n137 , n138 , n139 , n140 , n141 , n142 , n143 , n144 , n145 , n146 , n147 , n148 , n149 , n150 , n151 , n152 , n153 , n154 , n155 , n156 , n157 , n158 , n159 , n160 , n161 , n162 , n163 , n164 , n165 , n166 , n167 , n168 , n169 , n170 , n171 , n172 , n173 , n174 , n175 , n176 , n177 , n178 , n179 , n180 , n181 , n182 , n183 , n184 , n185 , n186 , n187 , n188 , n189 , n190 , n191 ;
output n192 , n193 , n194 , n195 , n196 , n197 , n198 , n199 , n200 , n201 ;
wire n404 , n405 , n406 , n407 , n408 , n409 , n410 , n411 , n412 ,
n413 , n414 , n415 , n416 , n417 , n418 , n419 , n420 , n421 , n422 ,
n423 , n424 , n425 , n426 , n427 , n428 , n429 , n430 , n431 , n432 ,
n433 , n434 , n435 , n436 , n437 , n438 , n439 , n440 , n441 , n442 ,
n443 , n444 , n445 , n446 , n447 , n448 , n449 , n450 , n451 , n452 ,
n453 , n454 , n455 , n456 , n457 , n458 , n459 , n460 , n461 , n462 ,
n463 , n464 , n465 , n466 , n467 , n468 , n469 , n470 , n471 , n472 ,
n473 , n474 , n475 , n476 , n477 , n478 , n479 , n480 , n481 , n482 ,
n483 , n484 , n485 , n486 , n487 , n488 , n489 , n490 , n491 , n492 ,
n493 , n494 , n495 , n496 , n497 , n498 , n499 , n500 , n501 , n502 ,
n503 , n504 , n505 , n506 , n507 , n508 , n509 , n510 , n511 , n512 ,
n513 , n514 , n515 , n516 , n517 , n518 , n519 , n520 , n521 , n522 ,
n523 , n524 , n525 , n526 , n527 , n528 , n529 , n530 , n531 , n532 ,
n533 , n534 , n535 , n536 , n537 , n538 , n539 , n540 , n541 , n542 ,
n543 , n544 , n545 , n546 , n547 , n548 , n549 , n550 , n551 , n552 ,
n553 , n554 , n555 , n556 , n557 , n558 , n559 , n560 , n561 , n562 ,
n563 , n564 , n565 , n566 , n567 , n568 , n569 , n570 , n571 , n572 ,
n573 , n574 , n575 , n576 , n577 , n578 , n579 , n580 , n581 , n582 ,
n583 , n584 , n585 , n586 , n587 , n588 , n589 , n590 , n591 , n592 ,
n593 , n594 , n595 , n596 , n597 , n598 , n599 , n600 , n601 , n602 ,
n603 , n604 , n605 , n606 , n607 , n608 , n609 , n610 , n611 , n612 ,
n613 , n614 , n615 , n616 , n617 , n618 , n619 , n620 , n621 , n622 ,
n623 , n624 , n625 , n626 , n627 , n628 , n629 , n630 , n631 , n632 ,
n633 , n634 , n635 , n636 , n637 , n638 , n639 , n640 , n641 , n642 ,
n643 , n644 , n645 , n646 , n647 , n648 , n649 , n650 , n651 , n652 ,
n653 , n654 , n655 , n656 , n657 , n658 , n659 , n660 , n661 , n662 ,
n663 , n664 , n665 , n666 , n667 , n668 , n669 , n670 , n671 , n672 ,
n673 , n674 , n675 , n676 , n677 , n678 , n679 , n680 , n681 , n682 ,
n683 , n684 , n685 , n686 , n687 , n688 , n689 , n690 , n691 , n692 ,
n693 , n694 , n695 , n696 , n697 , n698 , n699 , n700 , n701 , n702 ,
n703 , n704 , n705 , n706 , n707 , n708 , n709 , n710 , n711 , n712 ,
n713 , n714 , n715 , n716 , n717 , n718 , n719 , n720 , n721 , n722 ,
n723 , n724 , n725 , n726 , n727 , n728 , n729 , n730 , n731 , n732 ,
n733 , n734 , n735 , n736 , n737 , n738 , n739 , n740 , n741 , n742 ,
n743 , n744 , n745 , n746 , n747 , n748 , n749 , n750 , n751 , n752 ,
n753 , n754 , n755 , n756 , n757 , n758 , n759 , n760 , n761 , n762 ,
n763 , n764 , n765 , n766 , n767 , n768 , n769 , n770 , n771 , n772 ,
n773 , n774 , n775 , n776 , n777 , n778 , n779 , n780 , n781 , n782 ,
n783 , n784 , n785 , n786 , n787 , n788 , n789 , n790 , n791 , n792 ,
n793 , n794 , n795 , n796 , n797 , n798 , n799 , n800 , n801 , n802 ,
n803 , n804 , n805 , n806 , n807 , n808 , n809 , n810 , n811 , n812 ,
n813 , n814 , n815 , n816 , n817 , n818 , n819 , n820 , n821 , n822 ,
n823 , n824 , n825 , n826 , n827 , n828 , n829 , n830 , n831 , n832 ,
n833 , n834 , n835 , n836 , n837 , n838 , n839 , n840 , n841 , n842 ,
n843 , n844 , n845 , n846 , n847 , n848 , n849 , n850 , n851 , n852 ,
n853 , n854 , n855 , n856 , n857 , n858 , n859 , n860 , n861 , n862 ,
n863 , n864 , n865 , n866 , n867 , n868 , n869 , n870 , n871 , n872 ,
n873 , n874 , n875 , n876 , n877 , n878 , n879 , n880 , n881 , n882 ,
n883 , n884 , n885 , n886 , n887 , n888 , n889 , n890 , n891 , n892 ,
n893 , n894 , n895 , n896 , n897 , n898 , n899 , n900 , n901 , n902 ,
n903 , n904 , n905 , n906 , n907 , n908 , n909 , n910 , n911 , n912 ,
n913 , n914 , n915 , n916 , n917 , n918 , n919 , n920 , n921 , n922 ,
n923 , n924 , n925 , n926 , n927 , n928 , n929 , n930 , n931 , n932 ,
n933 , n934 , n935 , n936 , n937 , n938 , n939 , n940 , n941 , n942 ,
n943 , n944 , n945 , n946 , n947 , n948 , n949 , n950 , n951 , n952 ,
n953 , n954 , n955 , n956 , n957 , n958 , n959 , n960 , n961 , n962 ,
n963 , n964 , n965 , n966 , n967 , n968 , n969 , n970 , n971 , n972 ,
n973 , n974 , n975 , n976 , n977 , n978 , n979 , n980 , n981 , n982 ,
n983 , n984 , n985 , n986 , n987 , n988 , n989 , n990 , n991 , n992 ,
n993 , n994 , n995 , n996 , n997 , n998 , n999 , n1000 , n1001 , n1002 ,
n1003 , n1004 , n1005 , n1006 , n1007 , n1008 , n1009 , n1010 , n1011 , n1012 ,
n1013 , n1014 , n1015 , n1016 , n1017 , n1018 , n1019 , n1020 , n1021 , n1022 ,
n1023 , n1024 , n1025 , n1026 , n1027 , n1028 , n1029 , n1030 , n1031 , n1032 ,
n1033 , n1034 , n1035 , n1036 , n1037 , n1038 , n1039 , n1040 , n1041 , n1042 ,
n1043 , n1044 , n1045 , n1046 , n1047 , n1048 , n1049 , n1050 , n1051 , n1052 ,
n1053 , n1054 , n1055 , n1056 , n1057 , n1058 , n1059 , n1060 , n1061 , n1062 ,
n1063 , n1064 , n1065 , n1066 , n1067 , n1068 , n1069 , n1070 , n1071 , n1072 ,
n1073 , n1074 , n1075 , n1076 , n1077 , n1078 , n1079 , n1080 , n1081 , n1082 ,
n1083 , n1084 , n1085 , n1086 , n1087 , n1088 , n1089 , n1090 , n1091 , n1092 ,
n1093 , n1094 , n1095 , n1096 , n1097 , n1098 , n1099 , n1100 , n1101 , n1102 ,
n1103 , n1104 , n1105 , n1106 , n1107 , n1108 , n1109 , n1110 , n1111 , n1112 ,
n1113 , n1114 , n1115 , n1116 , n1117 , n1118 , n1119 , n1120 , n1121 , n1122 ,
n1123 , n1124 , n1125 , n1126 , n1127 , n1128 , n1129 , n1130 , n1131 , n1132 ,
n1133 , n1134 , n1135 , n1136 , n1137 , n1138 , n1139 , n1140 , n1141 , n1142 ,
n1143 , n1144 , n1145 , n1146 , n1147 , n1148 , n1149 , n1150 , n1151 , n1152 ,
n1153 , n1154 , n1155 , n1156 , n1157 , n1158 , n1159 , n1160 , n1161 , n1162 ,
n1163 , n1164 , n1165 , n1166 , n1167 , n1168 , n1169 , n1170 , n1171 , n1172 ,
n1173 , n1174 , n1175 , n1176 , n1177 , n1178 , n1179 , n1180 , n1181 , n1182 ,
n1183 , n1184 , n1185 , n1186 , n1187 , n1188 , n1189 , n1190 , n1191 , n1192 ,
n1193 , n1194 , n1195 , n1196 , n1197 , n1198 , n1199 , n1200 , n1201 , n1202 ,
n1203 , n1204 , n1205 , n1206 , n1207 , n1208 , n1209 , n1210 , n1211 , n1212 ,
n1213 , n1214 , n1215 , n1216 , n1217 , n1218 , n1219 , n1220 , n1221 , n1222 ,
n1223 , n1224 , n1225 , n1226 , n1227 , n1228 , n1229 , n1230 , n1231 , n1232 ,
n1233 , n1234 , n1235 , n1236 , n1237 , n1238 , n1239 , n1240 , n1241 , n1242 ,
n1243 , n1244 , n1245 , n1246 , n1247 , n1248 , n1249 , n1250 , n1251 , n1252 ,
n1253 , n1254 , n1255 , n1256 , n1257 , n1258 , n1259 , n1260 , n1261 , n1262 ,
n1263 , n1264 , n1265 , n1266 , n1267 , n1268 , n1269 , n1270 , n1271 , n1272 ,
n1273 , n1274 , n1275 , n1276 , n1277 , n1278 , n1279 , n1280 , n1281 , n1282 ,
n1283 , n1284 , n1285 , n1286 , n1287 , n1288 , n1289 , n1290 , n1291 , n1292 ,
n1293 , n1294 , n1295 , n1296 , n1297 , n1298 , n1299 , n1300 , n1301 , n1302 ,
n1303 , n1304 , n1305 , n1306 , n1307 , n1308 , n1309 , n1310 , n1311 , n1312 ,
n1313 , n1314 , n1315 , n1316 , n1317 , n1318 , n1319 , n1320 , n1321 , n1322 ,
n1323 , n1324 , n1325 , n1326 , n1327 , n1328 , n1329 , n1330 , n1331 , n1332 ,
n1333 , n1334 , n1335 , n1336 , n1337 , n1338 , n1339 , n1340 , n1341 , n1342 ,
n1343 , n1344 , n1345 , n1346 , n1347 , n1348 , n1349 , n1350 , n1351 , n1352 ,
n1353 , n1354 , n1355 , n1356 , n1357 , n1358 , n1359 , n1360 , n1361 , n1362 ,
n1363 , n1364 , n1365 , n1366 , n1367 , n1368 , n1369 , n1370 , n1371 , n1372 ,
n1373 , n1374 , n1375 , n1376 , n1377 , n1378 , n1379 , n1380 , n1381 , n1382 ,
n1383 , n1384 , n1385 , n1386 , n1387 , n1388 , n1389 , n1390 , n1391 , n1392 ,
n1393 , n1394 , n1395 , n1396 , n1397 , n1398 , n1399 , n1400 , n1401 , n1402 ,
n1403 , n1404 , n1405 , n1406 , n1407 , n1408 , n1409 , n1410 , n1411 , n1412 ,
n1413 , n1414 , n1415 , n1416 , n1417 , n1418 , n1419 , n1420 , n1421 , n1422 ,
n1423 , n1424 , n1425 , n1426 , n1427 , n1428 , n1429 , n1430 , n1431 , n1432 ,
n1433 , n1434 , n1435 , n1436 , n1437 , n1438 , n1439 , n1440 , n1441 , n1442 ,
n1443 , n1444 , n1445 , n1446 , n1447 , n1448 , n1449 , n1450 , n1451 , n1452 ,
n1453 , n1454 , n1455 , n1456 , n1457 , n1458 , n1459 , n1460 , n1461 , n1462 ,
n1463 , n1464 , n1465 , n1466 , n1467 , n1468 , n1469 , n1470 , n1471 , n1472 ,
n1473 , n1474 , n1475 , n1476 , n1477 , n1478 , n1479 , n1480 , n1481 , n1482 ,
n1483 , n1484 , n1485 , n1486 , n1487 , n1488 , n1489 , n1490 , n1491 , n1492 ,
n1493 , n1494 , n1495 , n1496 , n1497 , n1498 , n1499 , n1500 , n1501 , n1502 ,
n1503 , n1504 , n1505 , n1506 , n1507 , n1508 , n1509 , n1510 , n1511 , n1512 ,
n1513 , n1514 , n1515 , n1516 , n1517 , n1518 , n1519 , n1520 , n1521 , n1522 ,
n1523 , n1524 , n1525 , n1526 , n1527 , n1528 , n1529 , n1530 , n1531 , n1532 ,
n1533 , n1534 , n1535 , n1536 , n1537 , n1538 , n1539 , n1540 , n1541 , n1542 ,
n1543 , n1544 , n1545 , n1546 , n1547 , n1548 , n1549 , n1550 , n1551 , n1552 ,
n1553 , n1554 , n1555 , n1556 , n1557 , n1558 , n1559 , n1560 , n1561 , n1562 ,
n1563 , n1564 , n1565 , n1566 , n1567 , n1568 , n1569 , n1570 , n1571 , n1572 ,
n1573 , n1574 , n1575 , n1576 , n1577 , n1578 , n1579 , n1580 , n1581 , n1582 ,
n1583 , n1584 , n1585 , n1586 , n1587 , n1588 , n1589 , n1590 , n1591 , n1592 ,
n1593 , n1594 , n1595 , n1596 , n1597 , n1598 , n1599 , n1600 , n1601 , n1602 ,
n1603 , n1604 , n1605 , n1606 , n1607 , n1608 , n1609 , n1610 , n1611 , n1612 ,
n1613 , n1614 , n1615 , n1616 , n1617 , n1618 , n1619 , n1620 , n1621 , n1622 ,
n1623 , n1624 , n1625 , n1626 , n1627 , n1628 , n1629 , n1630 , n1631 , n1632 ,
n1633 , n1634 , n1635 , n1636 , n1637 , n1638 , n1639 , n1640 , n1641 , n1642 ,
n1643 , n1644 , n1645 , n1646 , n1647 , n1648 , n1649 , n1650 , n1651 , n1652 ,
n1653 , n1654 , n1655 , n1656 , n1657 , n1658 , n1659 , n1660 , n1661 , n1662 ,
n1663 , n1664 , n1665 , n1666 , n1667 , n1668 , n1669 , n1670 , n1671 , n1672 ,
n1673 , n1674 , n1675 , n1676 , n1677 , n1678 , n1679 , n1680 , n1681 , n1682 ,
n1683 , n1684 , n1685 , n1686 , n1687 , n1688 , n1689 , n1690 , n1691 , n1692 ,
n1693 , n1694 , n1695 , n1696 , n1697 , n1698 , n1699 , n1700 , n1701 , n1702 ,
n1703 , n1704 , n1705 , n1706 , n1707 , n1708 , n1709 , n1710 , n1711 , n1712 ,
n1713 , n1714 , n1715 , n1716 , n1717 , n1718 , n1719 , n1720 , n1721 , n1722 ,
n1723 , n1724 , n1725 , n1726 , n1727 , n1728 , n1729 , n1730 , n1731 , n1732 ,
n1733 , n1734 , n1735 , n1736 , n1737 , n1738 , n1739 , n1740 , n1741 , n1742 ,
n1743 , n1744 , n1745 , n1746 , n1747 , n1748 , n1749 , n1750 , n1751 , n1752 ,
n1753 , n1754 , n1755 , n1756 , n1757 , n1758 , n1759 , n1760 , n1761 , n1762 ,
n1763 , n1764 , n1765 , n1766 , n1767 , n1768 , n1769 , n1770 , n1771 , n1772 ,
n1773 , n1774 , n1775 , n1776 , n1777 , n1778 , n1779 , n1780 , n1781 , n1782 ,
n1783 , n1784 , n1785 , n1786 , n1787 , n1788 , n1789 , n1790 , n1791 , n1792 ,
n1793 , n1794 , n1795 , n1796 , n1797 , n1798 , n1799 , n1800 , n1801 , n1802 ,
n1803 , n1804 , n1805 , n1806 , n1807 , n1808 , n1809 , n1810 , n1811 , n1812 ,
n1813 , n1814 , n1815 , n1816 , n1817 , n1818 , n1819 , n1820 , n1821 , n1822 ,
n1823 , n1824 , n1825 , n1826 , n1827 , n1828 , n1829 , n1830 , n1831 , n1832 ,
n1833 , n1834 , n1835 , n1836 , n1837 , n1838 , n1839 , n1840 , n1841 , n1842 ,
n1843 , n1844 , n1845 , n1846 , n1847 , n1848 , n1849 , n1850 , n1851 , n1852 ,
n1853 , n1854 , n1855 , n1856 , n1857 , n1858 , n1859 , n1860 , n1861 , n1862 ,
n1863 , n1864 , n1865 , n1866 , n1867 , n1868 , n1869 , n1870 , n1871 , n1872 ,
n1873 , n1874 , n1875 , n1876 , n1877 , n1878 , n1879 , n1880 , n1881 , n1882 ,
n1883 , n1884 , n1885 , n1886 , n1887 , n1888 , n1889 , n1890 , n1891 , n1892 ,
n1893 , n1894 , n1895 , n1896 , n1897 , n1898 , n1899 , n1900 , n1901 , n1902 ,
n1903 , n1904 , n1905 , n1906 , n1907 , n1908 , n1909 , n1910 , n1911 , n1912 ,
n1913 , n1914 , n1915 , n1916 , n1917 , n1918 , n1919 , n1920 , n1921 , n1922 ,
n1923 , n1924 , n1925 , n1926 , n1927 , n1928 , n1929 , n1930 , n1931 , n1932 ,
n1933 , n1934 , n1935 , n1936 , n1937 , n1938 , n1939 , n1940 , n1941 , n1942 ,
n1943 , n1944 , n1945 , n1946 , n1947 , n1948 , n1949 , n1950 , n1951 , n1952 ,
n1953 , n1954 , n1955 , n1956 , n1957 , n1958 , n1959 , n1960 , n1961 , n1962 ,
n1963 , n1964 , n1965 , n1966 , n1967 , n1968 , n1969 , n1970 , n1971 , n1972 ,
n1973 , n1974 , n1975 , n1976 , n1977 , n1978 , n1979 , n1980 , n1981 , n1982 ,
n1983 , n1984 , n1985 , n1986 , n1987 , n1988 , n1989 , n1990 , n1991 , n1992 ,
n1993 , n1994 , n1995 , n1996 , n1997 , n1998 , n1999 , n2000 , n2001 , n2002 ,
n2003 , n2004 , n2005 , n2006 , n2007 , n2008 , n2009 , n2010 , n2011 , n2012 ,
n2013 , n2014 , n2015 , n2016 , n2017 , n2018 , n2019 , n2020 , n2021 , n2022 ,
n2023 , n2024 , n2025 , n2026 , n2027 , n2028 , n2029 , n2030 , n2031 , n2032 ,
n2033 , n2034 , n2035 , n2036 , n2037 , n2038 , n2039 , n2040 , n2041 , n2042 ,
n2043 , n2044 , n2045 , n2046 , n2047 , n2048 , n2049 , n2050 , n2051 , n2052 ,
n2053 , n2054 , n2055 , n2056 , n2057 , n2058 , n2059 , n2060 , n2061 , n2062 ,
n2063 , n2064 , n2065 , n2066 , n2067 , n2068 , n2069 , n2070 , n2071 , n2072 ,
n2073 , n2074 , n2075 , n2076 , n2077 , n2078 , n2079 , n2080 , n2081 , n2082 ,
n2083 , n2084 , n2085 , n2086 , n2087 , n2088 , n2089 , n2090 , n2091 , n2092 ,
n2093 , n2094 , n2095 , n2096 , n2097 , n2098 , n2099 , n2100 , n2101 , n2102 ,
n2103 , n2104 , n2105 , n2106 , n2107 , n2108 , n2109 , n2110 , n2111 , n2112 ,
n2113 , n2114 , n2115 , n2116 , n2117 , n2118 , n2119 , n2120 , n2121 , n2122 ,
n2123 , n2124 , n2125 , n2126 , n2127 , n2128 , n2129 , n2130 , n2131 , n2132 ,
n2133 , n2134 , n2135 , n2136 , n2137 , n2138 , n2139 , n2140 , n2141 , n2142 ,
n2143 , n2144 , n2145 , n2146 , n2147 , n2148 , n2149 , n2150 , n2151 , n2152 ,
n2153 , n2154 , n2155 , n2156 , n2157 , n2158 , n2159 , n2160 , n2161 , n2162 ,
n2163 , n2164 , n2165 , n2166 , n2167 , n2168 , n2169 , n2170 , n2171 , n2172 ,
n2173 , n2174 , n2175 , n2176 , n2177 , n2178 , n2179 , n2180 , n2181 , n2182 ,
n2183 , n2184 , n2185 , n2186 , n2187 , n2188 , n2189 , n2190 , n2191 , n2192 ,
n2193 , n2194 , n2195 , n2196 , n2197 , n2198 , n2199 , n2200 , n2201 , n2202 ,
n2203 , n2204 , n2205 , n2206 , n2207 , n2208 , n2209 , n2210 , n2211 , n2212 ,
n2213 , n2214 , n2215 , n2216 , n2217 , n2218 , n2219 , n2220 , n2221 , n2222 ,
n2223 , n2224 , n2225 , n2226 , n2227 , n2228 , n2229 , n2230 , n2231 , n2232 ,
n2233 , n2234 , n2235 , n2236 , n2237 , n2238 , n2239 , n2240 , n2241 , n2242 ,
n2243 , n2244 , n2245 , n2246 , n2247 , n2248 , n2249 , n2250 , n2251 , n2252 ,
n2253 , n2254 , n2255 , n2256 , n2257 , n2258 , n2259 , n2260 , n2261 , n2262 ,
n2263 , n2264 , n2265 , n2266 , n2267 , n2268 , n2269 , n2270 , n2271 , n2272 ,
n2273 , n2274 , n2275 , n2276 , n2277 , n2278 , n2279 , n2280 , n2281 , n2282 ,
n2283 , n2284 , n2285 , n2286 , n2287 , n2288 , n2289 , n2290 , n2291 , n2292 ,
n2293 , n2294 , n2295 , n2296 , n2297 , n2298 , n2299 , n2300 , n2301 , n2302 ,
n2303 , n2304 , n2305 , n2306 , n2307 , n2308 , n2309 , n2310 , n2311 , n2312 ,
n2313 , n2314 , n2315 , n2316 , n2317 , n2318 , n2319 , n2320 , n2321 , n2322 ,
n2323 , n2324 , n2325 , n2326 , n2327 , n2328 , n2329 , n2330 , n2331 , n2332 ,
n2333 , n2334 , n2335 , n2336 , n2337 , n2338 , n2339 , n2340 , n2341 , n2342 ,
n2343 , n2344 , n2345 , n2346 , n2347 , n2348 , n2349 , n2350 , n2351 , n2352 ,
n2353 , n2354 , n2355 , n2356 , n2357 , n2358 , n2359 , n2360 , n2361 , n2362 ,
n2363 , n2364 , n2365 , n2366 , n2367 , n2368 , n2369 , n2370 , n2371 , n2372 ,
n2373 , n2374 , n2375 , n2376 , n2377 , n2378 , n2379 , n2380 , n2381 , n2382 ,
n2383 , n2384 , n2385 , n2386 , n2387 , n2388 , n2389 , n2390 , n2391 , n2392 ,
n2393 , n2394 , n2395 , n2396 , n2397 , n2398 , n2399 , n2400 , n2401 , n2402 ,
n2403 , n2404 , n2405 , n2406 , n2407 , n2408 , n2409 , n2410 , n2411 , n2412 ,
n2413 , n2414 , n2415 , n2416 , n2417 , n2418 , n2419 , n2420 , n2421 , n2422 ,
n2423 , n2424 , n2425 , n2426 , n2427 , n2428 , n2429 , n2430 , n2431 , n2432 ,
n2433 , n2434 , n2435 , n2436 , n2437 , n2438 , n2439 , n2440 , n2441 , n2442 ,
n2443 , n2444 , n2445 , n2446 , n2447 , n2448 , n2449 , n2450 , n2451 , n2452 ,
n2453 , n2454 , n2455 , n2456 , n2457 , n2458 , n2459 , n2460 , n2461 , n2462 ,
n2463 , n2464 , n2465 , n2466 , n2467 , n2468 , n2469 , n2470 , n2471 , n2472 ,
n2473 , n2474 , n2475 , n2476 , n2477 , n2478 , n2479 , n2480 , n2481 , n2482 ,
n2483 , n2484 , n2485 , n2486 , n2487 , n2488 , n2489 , n2490 , n2491 , n2492 ,
n2493 , n2494 , n2495 , n2496 , n2497 , n2498 , n2499 , n2500 , n2501 , n2502 ,
n2503 , n2504 , n2505 , n2506 , n2507 , n2508 , n2509 , n2510 , n2511 , n2512 ,
n2513 , n2514 , n2515 , n2516 , n2517 , n2518 , n2519 , n2520 , n2521 , n2522 ,
n2523 , n2524 , n2525 , n2526 , n2527 , n2528 , n2529 , n2530 , n2531 , n2532 ,
n2533 , n2534 , n2535 , n2536 , n2537 , n2538 , n2539 , n2540 , n2541 , n2542 ,
n2543 , n2544 , n2545 , n2546 , n2547 , n2548 , n2549 , n2550 , n2551 , n2552 ,
n2553 , n2554 , n2555 , n2556 , n2557 , n2558 , n2559 , n2560 , n2561 , n2562 ,
n2563 , n2564 , n2565 , n2566 , n2567 , n2568 , n2569 , n2570 , n2571 , n2572 ,
n2573 , n2574 , n2575 , n2576 , n2577 , n2578 , n2579 , n2580 , n2581 , n2582 ,
n2583 , n2584 , n2585 , n2586 , n2587 , n2588 , n2589 , n2590 , n2591 , n2592 ,
n2593 , n2594 , n2595 , n2596 , n2597 , n2598 , n2599 , n2600 , n2601 , n2602 ,
n2603 , n2604 , n2605 , n2606 , n2607 , n2608 , n2609 , n2610 , n2611 , n2612 ,
n2613 , n2614 , n2615 , n2616 , n2617 , n2618 , n2619 , n2620 , n2621 , n2622 ,
n2623 , n2624 , n2625 , n2626 , n2627 , n2628 , n2629 , n2630 , n2631 , n2632 ,
n2633 , n2634 , n2635 , n2636 , n2637 , n2638 , n2639 , n2640 , n2641 , n2642 ,
n2643 , n2644 , n2645 , n2646 , n2647 , n2648 , n2649 , n2650 , n2651 , n2652 ,
n2653 , n2654 , n2655 , n2656 , n2657 , n2658 , n2659 , n2660 , n2661 , n2662 ,
n2663 , n2664 , n2665 , n2666 , n2667 , n2668 , n2669 , n2670 , n2671 , n2672 ,
n2673 , n2674 , n2675 , n2676 , n2677 , n2678 , n2679 , n2680 , n2681 , n2682 ,
n2683 , n2684 , n2685 , n2686 , n2687 , n2688 , n2689 , n2690 , n2691 , n2692 ,
n2693 , n2694 , n2695 , n2696 , n2697 , n2698 , n2699 , n2700 , n2701 , n2702 ,
n2703 , n2704 , n2705 , n2706 , n2707 , n2708 , n2709 , n2710 , n2711 , n2712 ,
n2713 , n2714 , n2715 , n2716 , n2717 , n2718 , n2719 , n2720 , n2721 , n2722 ,
n2723 , n2724 , n2725 , n2726 , n2727 , n2728 , n2729 , n2730 , n2731 , n2732 ,
n2733 , n2734 , n2735 , n2736 , n2737 , n2738 , n2739 , n2740 , n2741 , n2742 ,
n2743 , n2744 , n2745 , n2746 , n2747 , n2748 , n2749 , n2750 , n2751 , n2752 ,
n2753 , n2754 , n2755 , n2756 , n2757 , n2758 , n2759 , n2760 , n2761 , n2762 ,
n2763 , n2764 , n2765 , n2766 , n2767 , n2768 , n2769 , n2770 , n2771 , n2772 ,
n2773 , n2774 , n2775 , n2776 , n2777 , n2778 , n2779 , n2780 , n2781 , n2782 ,
n2783 , n2784 , n2785 , n2786 , n2787 , n2788 , n2789 , n2790 , n2791 , n2792 ,
n2793 , n2794 , n2795 , n2796 , n2797 , n2798 , n2799 , n2800 , n2801 , n2802 ,
n2803 , n2804 , n2805 , n2806 , n2807 , n2808 , n2809 , n2810 , n2811 , n2812 ,
n2813 , n2814 , n2815 , n2816 , n2817 , n2818 , n2819 , n2820 , n2821 , n2822 ,
n2823 , n2824 , n2825 , n2826 , n2827 , n2828 , n2829 , n2830 , n2831 , n2832 ,
n2833 , n2834 , n2835 , n2836 , n2837 , n2838 , n2839 , n2840 , n2841 , n2842 ,
n2843 , n2844 , n2845 , n2846 , n2847 , n2848 , n2849 , n2850 , n2851 , n2852 ,
n2853 , n2854 , n2855 , n2856 , n2857 , n2858 , n2859 , n2860 , n2861 , n2862 ,
n2863 , n2864 , n2865 , n2866 , n2867 , n2868 , n2869 , n2870 , n2871 , n2872 ,
n2873 , n2874 , n2875 , n2876 , n2877 , n2878 , n2879 , n2880 , n2881 , n2882 ,
n2883 , n2884 , n2885 , n2886 , n2887 , n2888 , n2889 , n2890 , n2891 , n2892 ,
n2893 , n2894 , n2895 , n2896 , n2897 , n2898 , n2899 , n2900 , n2901 , n2902 ,
n2903 , n2904 , n2905 , n2906 , n2907 , n2908 , n2909 , n2910 , n2911 , n2912 ,
n2913 , n2914 , n2915 , n2916 , n2917 , n2918 , n2919 , n2920 , n2921 , n2922 ,
n2923 , n2924 , n2925 , n2926 , n2927 , n2928 , n2929 , n2930 , n2931 , n2932 ,
n2933 , n2934 , n2935 , n2936 , n2937 , n2938 , n2939 , n2940 , n2941 , n2942 ,
n2943 , n2944 , n2945 , n2946 , n2947 , n2948 , n2949 , n2950 , n2951 , n2952 ,
n2953 , n2954 , n2955 , n2956 , n2957 , n2958 , n2959 , n2960 , n2961 , n2962 ,
n2963 , n2964 , n2965 , n2966 , n2967 , n2968 , n2969 , n2970 , n2971 , n2972 ,
n2973 , n2974 , n2975 , n2976 , n2977 , n2978 , n2979 , n2980 , n2981 , n2982 ,
n2983 , n2984 , n2985 , n2986 , n2987 , n2988 , n2989 , n2990 , n2991 , n2992 ,
n2993 , n2994 , n2995 , n2996 , n2997 , n2998 , n2999 , n3000 , n3001 , n3002 ,
n3003 , n3004 , n3005 , n3006 , n3007 , n3008 , n3009 , n3010 , n3011 , n3012 ,
n3013 , n3014 , n3015 , n3016 , n3017 , n3018 , n3019 , n3020 , n3021 , n3022 ,
n3023 , n3024 , n3025 , n3026 , n3027 , n3028 , n3029 , n3030 , n3031 , n3032 ,
n3033 , n3034 , n3035 , n3036 , n3037 , n3038 , n3039 , n3040 , n3041 , n3042 ,
n3043 , n3044 , n3045 , n3046 , n3047 , n3048 , n3049 , n3050 , n3051 , n3052 ,
n3053 , n3054 , n3055 , n3056 , n3057 , n3058 , n3059 , n3060 , n3061 , n3062 ,
n3063 , n3064 , n3065 , n3066 , n3067 , n3068 , n3069 , n3070 , n3071 , n3072 ,
n3073 , n3074 , n3075 , n3076 , n3077 , n3078 , n3079 , n3080 , n3081 , n3082 ,
n3083 , n3084 , n3085 , n3086 , n3087 , n3088 , n3089 , n3090 , n3091 , n3092 ,
n3093 , n3094 , n3095 , n3096 , n3097 , n3098 , n3099 , n3100 , n3101 , n3102 ,
n3103 , n3104 , n3105 , n3106 , n3107 , n3108 , n3109 , n3110 , n3111 , n3112 ,
n3113 , n3114 , n3115 , n3116 , n3117 , n3118 , n3119 , n3120 , n3121 , n3122 ,
n3123 , n3124 , n3125 , n3126 , n3127 , n3128 , n3129 , n3130 , n3131 , n3132 ,
n3133 , n3134 , n3135 , n3136 , n3137 , n3138 , n3139 , n3140 , n3141 , n3142 ,
n3143 , n3144 , n3145 , n3146 , n3147 , n3148 , n3149 , n3150 , n3151 , n3152 ,
n3153 , n3154 , n3155 , n3156 , n3157 , n3158 , n3159 , n3160 , n3161 , n3162 ,
n3163 , n3164 , n3165 , n3166 , n3167 , n3168 , n3169 , n3170 , n3171 , n3172 ,
n3173 , n3174 , n3175 , n3176 , n3177 , n3178 , n3179 , n3180 , n3181 , n3182 ,
n3183 , n3184 , n3185 , n3186 , n3187 , n3188 , n3189 , n3190 , n3191 , n3192 ,
n3193 , n3194 , n3195 , n3196 , n3197 , n3198 , n3199 , n3200 , n3201 , n3202 ,
n3203 , n3204 , n3205 , n3206 , n3207 , n3208 , n3209 , n3210 , n3211 , n3212 ,
n3213 , n3214 , n3215 , n3216 , n3217 , n3218 , n3219 , n3220 , n3221 , n3222 ,
n3223 , n3224 ;
buf ( n195 , n1861 );
buf ( n194 , n2305 );
buf ( n196 , n2369 );
buf ( n197 , n2427 );
buf ( n199 , n2757 );
buf ( n201 , n2888 );
buf ( n200 , n2976 );
buf ( n192 , n3041 );
buf ( n193 , n3111 );
buf ( n198 , n3224 );
buf ( n406 , n136 );
buf ( n407 , n25 );
buf ( n408 , n94 );
buf ( n409 , n2 );
buf ( n410 , n132 );
buf ( n411 , n156 );
buf ( n412 , n114 );
buf ( n413 , n159 );
buf ( n414 , n67 );
buf ( n415 , n184 );
buf ( n416 , n111 );
buf ( n417 , n130 );
buf ( n418 , n181 );
buf ( n419 , n52 );
buf ( n420 , n166 );
buf ( n421 , n153 );
buf ( n422 , n131 );
buf ( n423 , n141 );
buf ( n424 , n140 );
buf ( n425 , n9 );
buf ( n426 , n71 );
buf ( n427 , n113 );
buf ( n428 , n43 );
buf ( n429 , n126 );
buf ( n430 , n137 );
buf ( n431 , n22 );
buf ( n432 , n150 );
buf ( n433 , n104 );
buf ( n434 , n73 );
buf ( n435 , n100 );
buf ( n436 , n180 );
buf ( n437 , n167 );
buf ( n438 , n135 );
buf ( n439 , n178 );
buf ( n440 , n106 );
buf ( n441 , n57 );
buf ( n442 , n69 );
buf ( n443 , n175 );
buf ( n444 , n15 );
buf ( n445 , n152 );
buf ( n446 , n24 );
buf ( n447 , n70 );
buf ( n448 , n115 );
buf ( n449 , n68 );
buf ( n450 , n50 );
buf ( n451 , n134 );
buf ( n452 , n4 );
buf ( n453 , n31 );
buf ( n454 , n146 );
buf ( n455 , n59 );
buf ( n456 , n38 );
buf ( n457 , n138 );
buf ( n458 , n0 );
buf ( n459 , n95 );
buf ( n460 , n75 );
buf ( n461 , n60 );
buf ( n462 , n168 );
buf ( n463 , n157 );
buf ( n464 , n169 );
buf ( n465 , n21 );
buf ( n466 , n89 );
buf ( n467 , n92 );
buf ( n468 , n26 );
buf ( n469 , n51 );
buf ( n470 , n34 );
buf ( n471 , n124 );
buf ( n472 , n82 );
buf ( n473 , n62 );
buf ( n474 , n40 );
buf ( n475 , n125 );
buf ( n476 , n54 );
buf ( n477 , n107 );
buf ( n478 , n116 );
buf ( n479 , n88 );
buf ( n480 , n117 );
buf ( n481 , n173 );
buf ( n482 , n127 );
buf ( n483 , n63 );
buf ( n484 , n123 );
buf ( n485 , n1 );
buf ( n486 , n84 );
buf ( n487 , n66 );
buf ( n488 , n7 );
buf ( n489 , n165 );
buf ( n490 , n45 );
buf ( n491 , n163 );
buf ( n492 , n172 );
buf ( n493 , n19 );
buf ( n494 , n171 );
buf ( n495 , n182 );
buf ( n496 , n147 );
buf ( n497 , n55 );
buf ( n498 , n154 );
buf ( n499 , n109 );
buf ( n500 , n121 );
buf ( n501 , n10 );
buf ( n502 , n191 );
buf ( n503 , n122 );
buf ( n504 , n41 );
buf ( n505 , n77 );
buf ( n506 , n98 );
buf ( n507 , n118 );
buf ( n508 , n164 );
buf ( n509 , n44 );
buf ( n510 , n78 );
buf ( n511 , n83 );
buf ( n512 , n129 );
buf ( n513 , n161 );
buf ( n514 , n103 );
buf ( n515 , n33 );
buf ( n516 , n188 );
buf ( n517 , n46 );
buf ( n518 , n30 );
buf ( n519 , n86 );
buf ( n520 , n186 );
buf ( n521 , n155 );
buf ( n522 , n56 );
buf ( n523 , n28 );
buf ( n524 , n85 );
buf ( n525 , n93 );
buf ( n526 , n58 );
buf ( n527 , n102 );
buf ( n528 , n128 );
buf ( n529 , n119 );
buf ( n530 , n53 );
buf ( n531 , n142 );
buf ( n532 , n96 );
buf ( n533 , n160 );
buf ( n534 , n174 );
buf ( n535 , n61 );
buf ( n536 , n65 );
buf ( n537 , n13 );
buf ( n538 , n8 );
buf ( n539 , n36 );
buf ( n540 , n11 );
buf ( n541 , n39 );
buf ( n542 , n177 );
buf ( n543 , n105 );
buf ( n544 , n139 );
buf ( n545 , n12 );
buf ( n546 , n99 );
buf ( n547 , n47 );
buf ( n548 , n79 );
buf ( n549 , n16 );
buf ( n550 , n87 );
buf ( n551 , n162 );
buf ( n552 , n110 );
buf ( n553 , n23 );
buf ( n554 , n187 );
buf ( n555 , n120 );
buf ( n556 , n32 );
buf ( n557 , n158 );
buf ( n558 , n176 );
buf ( n559 , n149 );
buf ( n560 , n148 );
buf ( n561 , n29 );
buf ( n562 , n97 );
buf ( n563 , n144 );
buf ( n564 , n27 );
buf ( n565 , n145 );
buf ( n566 , n108 );
buf ( n567 , n72 );
buf ( n568 , n90 );
buf ( n569 , n3 );
buf ( n570 , n133 );
buf ( n571 , n14 );
buf ( n572 , n6 );
buf ( n573 , n183 );
buf ( n574 , n81 );
buf ( n575 , n112 );
buf ( n576 , n5 );
buf ( n577 , n80 );
buf ( n578 , n17 );
buf ( n579 , n74 );
buf ( n580 , n37 );
buf ( n581 , n91 );
buf ( n582 , n151 );
buf ( n583 , n101 );
buf ( n584 , n189 );
buf ( n585 , n185 );
buf ( n586 , n42 );
buf ( n587 , n49 );
buf ( n588 , n18 );
buf ( n589 , n64 );
buf ( n590 , n48 );
buf ( n591 , n143 );
buf ( n592 , n76 );
buf ( n593 , n20 );
buf ( n594 , n190 );
buf ( n595 , n179 );
buf ( n596 , n35 );
buf ( n597 , n170 );
buf ( n598 , n406 );
buf ( n599 , n407 );
not ( n600 , n599 );
buf ( n601 , n408 );
and ( n602 , n600 , n601 );
not ( n603 , n602 );
buf ( n604 , n409 );
not ( n605 , n604 );
buf ( n606 , n410 );
not ( n607 , n606 );
buf ( n608 , n411 );
not ( n609 , n608 );
buf ( n610 , n412 );
not ( n611 , n610 );
buf ( n612 , n413 );
not ( n613 , n612 );
buf ( n614 , n414 );
not ( n615 , n614 );
buf ( n616 , n415 );
not ( n617 , n616 );
and ( n618 , n615 , n617 );
and ( n619 , n613 , n618 );
buf ( n620 , n416 );
not ( n621 , n620 );
buf ( n622 , n417 );
not ( n623 , n622 );
and ( n624 , n621 , n623 );
buf ( n625 , n418 );
not ( n626 , n625 );
buf ( n627 , n419 );
not ( n628 , n627 );
and ( n629 , n626 , n628 );
and ( n630 , n624 , n629 );
and ( n631 , n619 , n630 );
buf ( n632 , n420 );
not ( n633 , n632 );
buf ( n634 , n421 );
not ( n635 , n634 );
and ( n636 , n633 , n635 );
buf ( n637 , n422 );
not ( n638 , n637 );
buf ( n639 , n423 );
not ( n640 , n639 );
and ( n641 , n638 , n640 );
and ( n642 , n636 , n641 );
buf ( n643 , n424 );
not ( n644 , n643 );
buf ( n645 , n425 );
not ( n646 , n645 );
buf ( n647 , n426 );
not ( n648 , n647 );
buf ( n649 , n427 );
not ( n650 , n649 );
and ( n651 , n648 , n650 );
and ( n652 , n646 , n651 );
and ( n653 , n644 , n652 );
and ( n654 , n642 , n653 );
and ( n655 , n631 , n654 );
and ( n656 , n611 , n655 );
and ( n657 , n609 , n656 );
and ( n658 , n607 , n657 );
and ( n659 , n605 , n658 );
xor ( n660 , n601 , n659 );
not ( n661 , n660 );
and ( n662 , n599 , n661 );
not ( n663 , n662 );
and ( n664 , n603 , n663 );
buf ( n665 , n428 );
and ( n666 , n600 , n665 );
not ( n667 , n666 );
not ( n668 , n601 );
and ( n669 , n668 , n659 );
xor ( n670 , n665 , n669 );
not ( n671 , n670 );
and ( n672 , n599 , n671 );
not ( n673 , n672 );
and ( n674 , n667 , n673 );
and ( n675 , n664 , n674 );
not ( n676 , n675 );
not ( n677 , n674 );
buf ( n678 , n429 );
and ( n679 , n600 , n678 );
not ( n680 , n679 );
buf ( n681 , n430 );
not ( n682 , n681 );
not ( n683 , n665 );
and ( n684 , n683 , n669 );
and ( n685 , n682 , n684 );
xor ( n686 , n678 , n685 );
not ( n687 , n686 );
and ( n688 , n599 , n687 );
not ( n689 , n688 );
and ( n690 , n680 , n689 );
and ( n691 , n677 , n690 );
not ( n692 , n691 );
and ( n693 , n600 , n681 );
not ( n694 , n693 );
xor ( n695 , n681 , n684 );
not ( n696 , n695 );
and ( n697 , n599 , n696 );
not ( n698 , n697 );
and ( n699 , n694 , n698 );
not ( n700 , n699 );
not ( n701 , n690 );
and ( n702 , n700 , n701 );
not ( n703 , n702 );
and ( n704 , n699 , n690 );
not ( n705 , n704 );
and ( n706 , n703 , n705 );
not ( n707 , n706 );
and ( n708 , n676 , n692 , n707 );
not ( n709 , n708 );
buf ( n710 , n431 );
and ( n711 , n600 , n710 );
not ( n712 , n711 );
not ( n713 , n678 );
and ( n714 , n713 , n685 );
xor ( n715 , n710 , n714 );
not ( n716 , n715 );
and ( n717 , n599 , n716 );
not ( n718 , n717 );
and ( n719 , n712 , n718 );
buf ( n720 , n432 );
buf ( n721 , n433 );
and ( n722 , n600 , n721 );
not ( n723 , n722 );
buf ( n724 , n434 );
not ( n725 , n724 );
buf ( n726 , n435 );
not ( n727 , n726 );
not ( n728 , n710 );
and ( n729 , n728 , n714 );
and ( n730 , n727 , n729 );
and ( n731 , n725 , n730 );
xor ( n732 , n721 , n731 );
not ( n733 , n732 );
and ( n734 , n599 , n733 );
not ( n735 , n734 );
and ( n736 , n723 , n735 );
not ( n737 , n736 );
and ( n738 , n600 , n726 );
not ( n739 , n738 );
xor ( n740 , n726 , n729 );
not ( n741 , n740 );
and ( n742 , n599 , n741 );
not ( n743 , n742 );
and ( n744 , n739 , n743 );
not ( n745 , n744 );
and ( n746 , n600 , n724 );
not ( n747 , n746 );
xor ( n748 , n724 , n730 );
not ( n749 , n748 );
and ( n750 , n599 , n749 );
not ( n751 , n750 );
and ( n752 , n747 , n751 );
not ( n753 , n752 );
and ( n754 , n745 , n753 );
and ( n755 , n737 , n754 );
not ( n756 , n755 );
and ( n757 , n720 , n756 );
and ( n758 , n719 , n757 );
buf ( n759 , n436 );
not ( n760 , n759 );
buf ( n761 , n437 );
and ( n762 , n761 , n744 );
and ( n763 , n752 , n762 );
not ( n764 , n763 );
and ( n765 , n760 , n764 );
not ( n766 , n765 );
and ( n767 , n737 , n766 );
not ( n768 , n767 );
not ( n769 , n761 );
and ( n770 , n769 , n752 );
not ( n771 , n770 );
and ( n772 , n737 , n771 );
not ( n773 , n772 );
and ( n774 , n745 , n773 );
not ( n775 , n774 );
and ( n776 , n768 , n775 );
not ( n777 , n776 );
and ( n778 , n753 , n736 );
not ( n779 , n778 );
buf ( n780 , n438 );
not ( n781 , n780 );
and ( n782 , n769 , n745 );
not ( n783 , n782 );
not ( n784 , n762 );
and ( n785 , n783 , n784 );
not ( n786 , n785 );
and ( n787 , n752 , n786 );
not ( n788 , n787 );
and ( n789 , n781 , n788 );
not ( n790 , n789 );
and ( n791 , n737 , n790 );
not ( n792 , n791 );
and ( n793 , n779 , n792 );
and ( n794 , n709 , n758 , n777 , n793 );
not ( n795 , n794 );
and ( n796 , n598 , n795 );
not ( n797 , n796 );
buf ( n798 , n439 );
and ( n799 , n600 , n798 );
not ( n800 , n799 );
buf ( n801 , n440 );
not ( n802 , n801 );
not ( n803 , n721 );
and ( n804 , n803 , n731 );
and ( n805 , n802 , n804 );
xor ( n806 , n798 , n805 );
not ( n807 , n806 );
and ( n808 , n599 , n807 );
not ( n809 , n808 );
and ( n810 , n800 , n809 );
not ( n811 , n810 );
buf ( n812 , n441 );
buf ( n813 , n442 );
and ( n814 , n600 , n813 );
not ( n815 , n814 );
not ( n816 , n798 );
and ( n817 , n816 , n805 );
xor ( n818 , n813 , n817 );
not ( n819 , n818 );
and ( n820 , n599 , n819 );
not ( n821 , n820 );
and ( n822 , n815 , n821 );
not ( n823 , n822 );
buf ( n824 , n443 );
and ( n825 , n600 , n824 );
not ( n826 , n825 );
not ( n827 , n813 );
and ( n828 , n827 , n817 );
xor ( n829 , n824 , n828 );
not ( n830 , n829 );
and ( n831 , n599 , n830 );
not ( n832 , n831 );
and ( n833 , n826 , n832 );
and ( n834 , n823 , n833 );
and ( n835 , n812 , n834 );
not ( n836 , n835 );
buf ( n837 , n444 );
and ( n838 , n822 , n833 );
and ( n839 , n837 , n838 );
not ( n840 , n839 );
buf ( n841 , n445 );
not ( n842 , n833 );
and ( n843 , n823 , n842 );
and ( n844 , n841 , n843 );
not ( n845 , n844 );
buf ( n846 , n446 );
and ( n847 , n822 , n842 );
and ( n848 , n846 , n847 );
not ( n849 , n848 );
and ( n850 , n836 , n840 , n845 , n849 );
buf ( n851 , n447 );
and ( n852 , n851 , n834 );
not ( n853 , n852 );
buf ( n854 , n448 );
and ( n855 , n854 , n838 );
not ( n856 , n855 );
buf ( n857 , n449 );
and ( n858 , n857 , n843 );
not ( n859 , n858 );
buf ( n860 , n450 );
and ( n861 , n860 , n847 );
not ( n862 , n861 );
and ( n863 , n853 , n856 , n859 , n862 );
not ( n864 , n863 );
buf ( n865 , n451 );
and ( n866 , n865 , n838 );
not ( n867 , n866 );
buf ( n868 , n452 );
and ( n869 , n868 , n843 );
not ( n870 , n869 );
and ( n871 , n867 , n870 );
buf ( n872 , n453 );
and ( n873 , n872 , n847 );
not ( n874 , n873 );
buf ( n875 , n454 );
and ( n876 , n875 , n834 );
not ( n877 , n876 );
and ( n878 , n874 , n877 );
and ( n879 , n871 , n878 );
not ( n880 , n879 );
and ( n881 , n864 , n880 );
buf ( n882 , n455 );
and ( n883 , n882 , n834 );
not ( n884 , n883 );
buf ( n885 , n456 );
and ( n886 , n885 , n838 );
not ( n887 , n886 );
buf ( n888 , n457 );
and ( n889 , n888 , n843 );
not ( n890 , n889 );
buf ( n891 , n458 );
and ( n892 , n891 , n847 );
not ( n893 , n892 );
and ( n894 , n884 , n887 , n890 , n893 );
not ( n895 , n894 );
buf ( n896 , n459 );
and ( n897 , n896 , n834 );
not ( n898 , n897 );
buf ( n899 , n460 );
and ( n900 , n899 , n838 );
not ( n901 , n900 );
buf ( n902 , n461 );
and ( n903 , n902 , n843 );
not ( n904 , n903 );
buf ( n905 , n462 );
and ( n906 , n905 , n847 );
not ( n907 , n906 );
and ( n908 , n898 , n901 , n904 , n907 );
not ( n909 , n908 );
buf ( n910 , n463 );
and ( n911 , n910 , n834 );
not ( n912 , n911 );
buf ( n913 , n464 );
and ( n914 , n913 , n838 );
not ( n915 , n914 );
buf ( n916 , n465 );
and ( n917 , n916 , n843 );
not ( n918 , n917 );
buf ( n919 , n466 );
and ( n920 , n919 , n847 );
not ( n921 , n920 );
and ( n922 , n912 , n915 , n918 , n921 );
not ( n923 , n922 );
buf ( n924 , n467 );
and ( n925 , n924 , n834 );
not ( n926 , n925 );
buf ( n927 , n468 );
and ( n928 , n927 , n838 );
not ( n929 , n928 );
buf ( n930 , n469 );
and ( n931 , n930 , n843 );
not ( n932 , n931 );
buf ( n933 , n470 );
and ( n934 , n933 , n847 );
not ( n935 , n934 );
and ( n936 , n926 , n929 , n932 , n935 );
not ( n937 , n936 );
and ( n938 , n923 , n937 );
and ( n939 , n895 , n909 , n938 );
buf ( n940 , n471 );
and ( n941 , n940 , n834 );
not ( n942 , n941 );
buf ( n943 , n472 );
and ( n944 , n943 , n838 );
not ( n945 , n944 );
buf ( n946 , n473 );
and ( n947 , n946 , n843 );
not ( n948 , n947 );
buf ( n949 , n474 );
and ( n950 , n949 , n847 );
not ( n951 , n950 );
and ( n952 , n942 , n945 , n948 , n951 );
not ( n953 , n952 );
buf ( n954 , n475 );
and ( n955 , n954 , n834 );
not ( n956 , n955 );
buf ( n957 , n476 );
and ( n958 , n957 , n838 );
not ( n959 , n958 );
buf ( n960 , n477 );
and ( n961 , n960 , n843 );
not ( n962 , n961 );
buf ( n963 , n478 );
and ( n964 , n963 , n847 );
not ( n965 , n964 );
and ( n966 , n956 , n959 , n962 , n965 );
not ( n967 , n966 );
and ( n968 , n953 , n967 );
buf ( n969 , n479 );
and ( n970 , n969 , n834 );
not ( n971 , n970 );
buf ( n972 , n480 );
and ( n973 , n972 , n838 );
not ( n974 , n973 );
buf ( n975 , n481 );
and ( n976 , n975 , n843 );
not ( n977 , n976 );
buf ( n978 , n482 );
and ( n979 , n978 , n847 );
not ( n980 , n979 );
and ( n981 , n971 , n974 , n977 , n980 );
not ( n982 , n981 );
buf ( n983 , n483 );
and ( n984 , n983 , n834 );
not ( n985 , n984 );
buf ( n986 , n484 );
and ( n987 , n986 , n838 );
not ( n988 , n987 );
buf ( n989 , n485 );
and ( n990 , n989 , n843 );
not ( n991 , n990 );
buf ( n992 , n486 );
and ( n993 , n992 , n847 );
not ( n994 , n993 );
and ( n995 , n985 , n988 , n991 , n994 );
not ( n996 , n995 );
buf ( n997 , n487 );
and ( n998 , n997 , n834 );
not ( n999 , n998 );
buf ( n1000 , n488 );
and ( n1001 , n1000 , n838 );
not ( n1002 , n1001 );
buf ( n1003 , n489 );
and ( n1004 , n1003 , n843 );
not ( n1005 , n1004 );
buf ( n1006 , n490 );
and ( n1007 , n1006 , n847 );
not ( n1008 , n1007 );
and ( n1009 , n999 , n1002 , n1005 , n1008 );
not ( n1010 , n1009 );
and ( n1011 , n843 , n982 , n996 , n1010 );
and ( n1012 , n968 , n1011 );
and ( n1013 , n881 , n939 , n1012 );
and ( n1014 , n850 , n1013 );
not ( n1015 , n1014 );
not ( n1016 , n850 );
not ( n1017 , n1013 );
and ( n1018 , n1016 , n1017 );
not ( n1019 , n1018 );
and ( n1020 , n1015 , n1019 );
not ( n1021 , n1020 );
and ( n1022 , n811 , n1021 );
not ( n1023 , n1022 );
buf ( n1024 , n491 );
and ( n1025 , n1024 , n834 );
not ( n1026 , n1025 );
buf ( n1027 , n492 );
and ( n1028 , n1027 , n838 );
not ( n1029 , n1028 );
buf ( n1030 , n493 );
and ( n1031 , n1030 , n843 );
not ( n1032 , n1031 );
buf ( n1033 , n494 );
and ( n1034 , n1033 , n847 );
not ( n1035 , n1034 );
and ( n1036 , n1026 , n1029 , n1032 , n1035 );
and ( n1037 , n895 , n909 );
and ( n1038 , n598 , n834 );
not ( n1039 , n1038 );
buf ( n1040 , n495 );
and ( n1041 , n1040 , n838 );
not ( n1042 , n1041 );
buf ( n1043 , n496 );
and ( n1044 , n1043 , n843 );
not ( n1045 , n1044 );
buf ( n1046 , n497 );
and ( n1047 , n1046 , n847 );
not ( n1048 , n1047 );
and ( n1049 , n1039 , n1042 , n1045 , n1048 );
not ( n1050 , n1049 );
and ( n1051 , n1016 , n1050 );
and ( n1052 , n1037 , n1051 );
and ( n1053 , n923 , n937 , n953 , n967 );
and ( n1054 , n1053 , n881 );
and ( n1055 , n1011 , n1052 , n1054 );
xor ( n1056 , n1036 , n1055 );
buf ( n1057 , n498 );
and ( n1058 , n1057 , n834 );
not ( n1059 , n1058 );
buf ( n1060 , n499 );
and ( n1061 , n1060 , n838 );
not ( n1062 , n1061 );
buf ( n1063 , n500 );
and ( n1064 , n1063 , n847 );
not ( n1065 , n1064 );
and ( n1066 , n1059 , n1062 , n1065 );
not ( n1067 , n1066 );
buf ( n1068 , n501 );
and ( n1069 , n1068 , n838 );
not ( n1070 , n1069 );
buf ( n1071 , n502 );
and ( n1072 , n1071 , n834 );
not ( n1073 , n1072 );
and ( n1074 , n1070 , n1073 );
buf ( n1075 , n503 );
and ( n1076 , n1075 , n843 );
not ( n1077 , n1076 );
buf ( n1078 , n504 );
and ( n1079 , n1078 , n847 );
not ( n1080 , n1079 );
and ( n1081 , n1077 , n1080 );
and ( n1082 , n1074 , n1081 );
not ( n1083 , n1082 );
and ( n1084 , n1067 , n1083 );
and ( n1085 , n1016 , n881 );
and ( n1086 , n939 , n1012 );
and ( n1087 , n1085 , n1086 );
xor ( n1088 , n1049 , n1087 );
not ( n1089 , n1088 );
and ( n1090 , n1021 , n1089 );
and ( n1091 , n864 , n939 , n1012 );
xor ( n1092 , n879 , n1091 );
not ( n1093 , n1092 );
xor ( n1094 , n936 , n1012 );
not ( n1095 , n1094 );
and ( n1096 , n1004 , n996 , n968 );
and ( n1097 , n981 , n1096 );
not ( n1098 , n1097 );
not ( n1099 , n1096 );
and ( n1100 , n982 , n1099 );
not ( n1101 , n1100 );
and ( n1102 , n1098 , n1101 );
not ( n1103 , n1102 );
not ( n1104 , n843 );
and ( n1105 , n1104 , n1009 );
not ( n1106 , n1105 );
and ( n1107 , n1005 , n1106 );
buf ( n1108 , n505 );
and ( n1109 , n1108 , n834 );
not ( n1110 , n1109 );
buf ( n1111 , n506 );
and ( n1112 , n1111 , n838 );
not ( n1113 , n1112 );
buf ( n1114 , n507 );
and ( n1115 , n1114 , n843 );
not ( n1116 , n1115 );
buf ( n1117 , n508 );
and ( n1118 , n1117 , n847 );
not ( n1119 , n1118 );
and ( n1120 , n1110 , n1113 , n1116 , n1119 );
not ( n1121 , n1120 );
buf ( n1122 , n509 );
and ( n1123 , n1122 , n838 );
not ( n1124 , n1123 );
buf ( n1125 , n510 );
and ( n1126 , n1125 , n834 );
not ( n1127 , n1126 );
and ( n1128 , n1124 , n1127 );
buf ( n1129 , n511 );
and ( n1130 , n1129 , n843 );
not ( n1131 , n1130 );
buf ( n1132 , n512 );
and ( n1133 , n1132 , n847 );
not ( n1134 , n1133 );
and ( n1135 , n1131 , n1134 );
and ( n1136 , n1128 , n1135 );
not ( n1137 , n1136 );
and ( n1138 , n1121 , n1137 );
and ( n1139 , n1004 , n966 );
not ( n1140 , n1139 );
and ( n1141 , n1005 , n967 );
not ( n1142 , n1141 );
and ( n1143 , n1140 , n1142 );
not ( n1144 , n1143 );
and ( n1145 , n1107 , n1138 , n1144 );
and ( n1146 , n1004 , n968 );
and ( n1147 , n995 , n1146 );
not ( n1148 , n1147 );
not ( n1149 , n1146 );
and ( n1150 , n996 , n1149 );
not ( n1151 , n1150 );
and ( n1152 , n1148 , n1151 );
not ( n1153 , n1152 );
and ( n1154 , n1004 , n967 );
not ( n1155 , n1154 );
and ( n1156 , n952 , n1155 );
not ( n1157 , n1156 );
and ( n1158 , n1149 , n1157 );
and ( n1159 , n1153 , n1158 );
and ( n1160 , n1145 , n1159 );
and ( n1161 , n1095 , n1103 , n1160 );
and ( n1162 , n909 , n938 , n1012 );
and ( n1163 , n894 , n1162 );
not ( n1164 , n1163 );
not ( n1165 , n1162 );
and ( n1166 , n895 , n1165 );
not ( n1167 , n1166 );
and ( n1168 , n1164 , n1167 );
not ( n1169 , n1168 );
and ( n1170 , n863 , n1086 );
not ( n1171 , n1170 );
not ( n1172 , n1086 );
and ( n1173 , n864 , n1172 );
not ( n1174 , n1173 );
and ( n1175 , n1171 , n1174 );
not ( n1176 , n1175 );
and ( n1177 , n1169 , n1176 );
and ( n1178 , n938 , n1012 );
and ( n1179 , n908 , n1178 );
not ( n1180 , n1179 );
not ( n1181 , n1178 );
and ( n1182 , n909 , n1181 );
not ( n1183 , n1182 );
and ( n1184 , n1180 , n1183 );
not ( n1185 , n1184 );
and ( n1186 , n937 , n1012 );
and ( n1187 , n922 , n1186 );
not ( n1188 , n1187 );
not ( n1189 , n1186 );
and ( n1190 , n923 , n1189 );
not ( n1191 , n1190 );
and ( n1192 , n1188 , n1191 );
not ( n1193 , n1192 );
and ( n1194 , n1185 , n1193 );
and ( n1195 , n1177 , n1194 );
and ( n1196 , n1093 , n1161 , n1195 );
and ( n1197 , n1090 , n1196 );
and ( n1198 , n1084 , n1197 );
and ( n1199 , n1056 , n1198 );
not ( n1200 , n1199 );
not ( n1201 , n1056 );
not ( n1202 , n1198 );
and ( n1203 , n1201 , n1202 );
not ( n1204 , n1203 );
and ( n1205 , n1200 , n1204 );
not ( n1206 , n1205 );
and ( n1207 , n810 , n1206 );
not ( n1208 , n1207 );
and ( n1209 , n1023 , n1208 );
not ( n1210 , n1209 );
and ( n1211 , n702 , n1210 );
not ( n1212 , n1211 );
and ( n1213 , n699 , n691 );
buf ( n1214 , n513 );
and ( n1215 , n600 , n801 );
not ( n1216 , n1215 );
xor ( n1217 , n801 , n804 );
not ( n1218 , n1217 );
and ( n1219 , n599 , n1218 );
not ( n1220 , n1219 );
and ( n1221 , n1216 , n1220 );
not ( n1222 , n1221 );
and ( n1223 , n1222 , n810 );
not ( n1224 , n1223 );
and ( n1225 , n1221 , n811 );
not ( n1226 , n1225 );
and ( n1227 , n1224 , n1226 );
and ( n1228 , n1221 , n1227 );
not ( n1229 , n1228 );
and ( n1230 , n1214 , n1229 );
not ( n1231 , n1230 );
and ( n1232 , n600 , n610 );
not ( n1233 , n1232 );
xor ( n1234 , n610 , n655 );
not ( n1235 , n1234 );
and ( n1236 , n599 , n1235 );
not ( n1237 , n1236 );
and ( n1238 , n1233 , n1237 );
not ( n1239 , n1238 );
and ( n1240 , n1239 , n1228 );
not ( n1241 , n1240 );
and ( n1242 , n1231 , n1241 );
not ( n1243 , n1242 );
and ( n1244 , n1213 , n1243 );
not ( n1245 , n1244 );
and ( n1246 , n664 , n674 , n699 , n690 );
buf ( n1247 , n514 );
and ( n1248 , n1247 , n1229 );
not ( n1249 , n1248 );
and ( n1250 , n600 , n612 );
not ( n1251 , n1250 );
and ( n1252 , n630 , n654 );
and ( n1253 , n617 , n1252 );
and ( n1254 , n615 , n1253 );
xor ( n1255 , n612 , n1254 );
not ( n1256 , n1255 );
and ( n1257 , n599 , n1256 );
not ( n1258 , n1257 );
and ( n1259 , n1251 , n1258 );
not ( n1260 , n1259 );
and ( n1261 , n1260 , n1228 );
not ( n1262 , n1261 );
and ( n1263 , n1249 , n1262 );
buf ( n1264 , n515 );
and ( n1265 , n1264 , n1229 );
not ( n1266 , n1265 );
and ( n1267 , n600 , n620 );
not ( n1268 , n1267 );
and ( n1269 , n623 , n629 );
and ( n1270 , n1269 , n654 );
xor ( n1271 , n620 , n1270 );
not ( n1272 , n1271 );
and ( n1273 , n599 , n1272 );
not ( n1274 , n1273 );
and ( n1275 , n1268 , n1274 );
not ( n1276 , n1275 );
and ( n1277 , n1276 , n1228 );
not ( n1278 , n1277 );
and ( n1279 , n1266 , n1278 );
buf ( n1280 , n516 );
and ( n1281 , n1280 , n1229 );
not ( n1282 , n1281 );
and ( n1283 , n600 , n622 );
not ( n1284 , n1283 );
and ( n1285 , n629 , n654 );
xor ( n1286 , n622 , n1285 );
not ( n1287 , n1286 );
and ( n1288 , n599 , n1287 );
not ( n1289 , n1288 );
and ( n1290 , n1284 , n1289 );
not ( n1291 , n1290 );
and ( n1292 , n1291 , n1228 );
not ( n1293 , n1292 );
and ( n1294 , n1282 , n1293 );
buf ( n1295 , n517 );
and ( n1296 , n1295 , n1229 );
not ( n1297 , n1296 );
and ( n1298 , n600 , n627 );
not ( n1299 , n1298 );
xor ( n1300 , n627 , n654 );
not ( n1301 , n1300 );
and ( n1302 , n599 , n1301 );
not ( n1303 , n1302 );
and ( n1304 , n1299 , n1303 );
not ( n1305 , n1304 );
and ( n1306 , n1305 , n1228 );
not ( n1307 , n1306 );
and ( n1308 , n1297 , n1307 );
buf ( n1309 , n518 );
and ( n1310 , n1309 , n1229 );
not ( n1311 , n1310 );
and ( n1312 , n600 , n625 );
not ( n1313 , n1312 );
and ( n1314 , n628 , n654 );
xor ( n1315 , n625 , n1314 );
not ( n1316 , n1315 );
and ( n1317 , n599 , n1316 );
not ( n1318 , n1317 );
and ( n1319 , n1313 , n1318 );
not ( n1320 , n1319 );
and ( n1321 , n1320 , n1228 );
not ( n1322 , n1321 );
and ( n1323 , n1311 , n1322 );
and ( n1324 , n1308 , n1323 );
and ( n1325 , n1279 , n1294 , n1324 );
buf ( n1326 , n519 );
and ( n1327 , n1326 , n1229 );
not ( n1328 , n1327 );
and ( n1329 , n600 , n616 );
not ( n1330 , n1329 );
xor ( n1331 , n616 , n1252 );
not ( n1332 , n1331 );
and ( n1333 , n599 , n1332 );
not ( n1334 , n1333 );
and ( n1335 , n1330 , n1334 );
not ( n1336 , n1335 );
and ( n1337 , n1336 , n1228 );
not ( n1338 , n1337 );
and ( n1339 , n1328 , n1338 );
buf ( n1340 , n520 );
and ( n1341 , n1340 , n1229 );
not ( n1342 , n1341 );
and ( n1343 , n600 , n614 );
not ( n1344 , n1343 );
xor ( n1345 , n614 , n1253 );
not ( n1346 , n1345 );
and ( n1347 , n599 , n1346 );
not ( n1348 , n1347 );
and ( n1349 , n1344 , n1348 );
not ( n1350 , n1349 );
and ( n1351 , n1350 , n1228 );
not ( n1352 , n1351 );
and ( n1353 , n1342 , n1352 );
and ( n1354 , n1339 , n1353 );
and ( n1355 , n1263 , n1325 , n1354 );
buf ( n1356 , n521 );
and ( n1357 , n1356 , n1229 );
not ( n1358 , n1357 );
and ( n1359 , n600 , n643 );
not ( n1360 , n1359 );
xor ( n1361 , n643 , n652 );
not ( n1362 , n1361 );
and ( n1363 , n599 , n1362 );
not ( n1364 , n1363 );
and ( n1365 , n1360 , n1364 );
not ( n1366 , n1365 );
and ( n1367 , n1366 , n1228 );
not ( n1368 , n1367 );
and ( n1369 , n1358 , n1368 );
buf ( n1370 , n522 );
and ( n1371 , n1370 , n1229 );
not ( n1372 , n1371 );
and ( n1373 , n600 , n645 );
not ( n1374 , n1373 );
xor ( n1375 , n645 , n651 );
not ( n1376 , n1375 );
and ( n1377 , n599 , n1376 );
not ( n1378 , n1377 );
and ( n1379 , n1374 , n1378 );
not ( n1380 , n1379 );
and ( n1381 , n1380 , n1228 );
not ( n1382 , n1381 );
and ( n1383 , n1372 , n1382 );
and ( n1384 , n1369 , n1383 );
buf ( n1385 , n523 );
and ( n1386 , n1385 , n1229 );
not ( n1387 , n1386 );
and ( n1388 , n649 , n1228 );
not ( n1389 , n1388 );
and ( n1390 , n1387 , n1389 );
buf ( n1391 , n524 );
and ( n1392 , n1391 , n1229 );
not ( n1393 , n1392 );
and ( n1394 , n600 , n647 );
not ( n1395 , n1394 );
xor ( n1396 , n647 , n649 );
and ( n1397 , n599 , n1396 );
not ( n1398 , n1397 );
and ( n1399 , n1395 , n1398 );
not ( n1400 , n1399 );
and ( n1401 , n1400 , n1228 );
not ( n1402 , n1401 );
and ( n1403 , n1393 , n1402 );
and ( n1404 , n1390 , n1403 );
and ( n1405 , n1384 , n1404 );
buf ( n1406 , n525 );
and ( n1407 , n1406 , n1229 );
not ( n1408 , n1407 );
and ( n1409 , n600 , n632 );
not ( n1410 , n1409 );
and ( n1411 , n640 , n653 );
and ( n1412 , n638 , n1411 );
and ( n1413 , n635 , n1412 );
xor ( n1414 , n632 , n1413 );
not ( n1415 , n1414 );
and ( n1416 , n599 , n1415 );
not ( n1417 , n1416 );
and ( n1418 , n1410 , n1417 );
not ( n1419 , n1418 );
and ( n1420 , n1419 , n1228 );
not ( n1421 , n1420 );
and ( n1422 , n1408 , n1421 );
buf ( n1423 , n526 );
and ( n1424 , n1423 , n1229 );
not ( n1425 , n1424 );
and ( n1426 , n600 , n637 );
not ( n1427 , n1426 );
xor ( n1428 , n637 , n1411 );
not ( n1429 , n1428 );
and ( n1430 , n599 , n1429 );
not ( n1431 , n1430 );
and ( n1432 , n1427 , n1431 );
not ( n1433 , n1432 );
and ( n1434 , n1433 , n1228 );
not ( n1435 , n1434 );
and ( n1436 , n1425 , n1435 );
and ( n1437 , n1422 , n1436 );
buf ( n1438 , n527 );
and ( n1439 , n1438 , n1229 );
not ( n1440 , n1439 );
and ( n1441 , n600 , n634 );
not ( n1442 , n1441 );
xor ( n1443 , n634 , n1412 );
not ( n1444 , n1443 );
and ( n1445 , n599 , n1444 );
not ( n1446 , n1445 );
and ( n1447 , n1442 , n1446 );
not ( n1448 , n1447 );
and ( n1449 , n1448 , n1228 );
not ( n1450 , n1449 );
and ( n1451 , n1440 , n1450 );
buf ( n1452 , n528 );
and ( n1453 , n1452 , n1229 );
not ( n1454 , n1453 );
and ( n1455 , n600 , n639 );
not ( n1456 , n1455 );
xor ( n1457 , n639 , n653 );
not ( n1458 , n1457 );
and ( n1459 , n599 , n1458 );
not ( n1460 , n1459 );
and ( n1461 , n1456 , n1460 );
not ( n1462 , n1461 );
and ( n1463 , n1462 , n1228 );
not ( n1464 , n1463 );
and ( n1465 , n1454 , n1464 );
and ( n1466 , n1451 , n1465 );
and ( n1467 , n1437 , n1466 );
and ( n1468 , n1405 , n1467 );
and ( n1469 , n1355 , n1468 );
and ( n1470 , n1243 , n1469 );
not ( n1471 , n1470 );
not ( n1472 , n1469 );
and ( n1473 , n1242 , n1472 );
not ( n1474 , n1473 );
and ( n1475 , n1471 , n1474 );
not ( n1476 , n1475 );
and ( n1477 , n1246 , n1476 );
not ( n1478 , n1477 );
and ( n1479 , n1245 , n1478 );
not ( n1480 , n664 );
and ( n1481 , n1480 , n701 );
not ( n1482 , n1481 );
and ( n1483 , n1482 , n692 );
and ( n1484 , n1483 , n706 );
not ( n1485 , n1263 );
and ( n1486 , n1485 , n1016 );
and ( n1487 , n1242 , n1050 );
not ( n1488 , n1487 );
and ( n1489 , n1243 , n1049 );
not ( n1490 , n1489 );
and ( n1491 , n1488 , n1490 );
not ( n1492 , n1491 );
and ( n1493 , n1486 , n1492 );
not ( n1494 , n1493 );
not ( n1495 , n1486 );
and ( n1496 , n1495 , n1491 );
not ( n1497 , n1496 );
and ( n1498 , n1494 , n1497 );
not ( n1499 , n1353 );
and ( n1500 , n1499 , n880 );
not ( n1501 , n1500 );
and ( n1502 , n1263 , n1016 );
not ( n1503 , n1502 );
and ( n1504 , n1485 , n850 );
not ( n1505 , n1504 );
and ( n1506 , n1503 , n1505 );
and ( n1507 , n1501 , n1506 );
not ( n1508 , n1507 );
not ( n1509 , n1279 );
and ( n1510 , n1509 , n895 );
not ( n1511 , n1510 );
not ( n1512 , n1339 );
and ( n1513 , n1512 , n863 );
not ( n1514 , n1513 );
and ( n1515 , n1339 , n864 );
not ( n1516 , n1515 );
and ( n1517 , n1514 , n1516 );
and ( n1518 , n1511 , n1517 );
not ( n1519 , n1518 );
and ( n1520 , n1512 , n864 );
not ( n1521 , n1520 );
and ( n1522 , n1353 , n879 );
not ( n1523 , n1522 );
and ( n1524 , n1501 , n1523 );
not ( n1525 , n1524 );
and ( n1526 , n1521 , n1525 );
not ( n1527 , n1526 );
and ( n1528 , n1519 , n1527 );
and ( n1529 , n1508 , n1528 );
not ( n1530 , n1294 );
and ( n1531 , n1530 , n909 );
and ( n1532 , n1509 , n894 );
not ( n1533 , n1532 );
and ( n1534 , n1279 , n895 );
not ( n1535 , n1534 );
and ( n1536 , n1533 , n1535 );
not ( n1537 , n1536 );
and ( n1538 , n1531 , n1537 );
not ( n1539 , n1538 );
xor ( n1540 , n1294 , n908 );
not ( n1541 , n1540 );
not ( n1542 , n1323 );
and ( n1543 , n1542 , n923 );
not ( n1544 , n1543 );
and ( n1545 , n1541 , n1544 );
not ( n1546 , n1545 );
not ( n1547 , n1531 );
and ( n1548 , n1547 , n1536 );
not ( n1549 , n1548 );
and ( n1550 , n1546 , n1549 );
not ( n1551 , n1550 );
and ( n1552 , n1539 , n1551 );
not ( n1553 , n1552 );
and ( n1554 , n1540 , n1543 );
not ( n1555 , n1554 );
xor ( n1556 , n1323 , n922 );
not ( n1557 , n1308 );
and ( n1558 , n1557 , n937 );
and ( n1559 , n1556 , n1558 );
not ( n1560 , n1559 );
and ( n1561 , n1555 , n1539 , n1560 );
not ( n1562 , n1556 );
not ( n1563 , n1558 );
and ( n1564 , n1562 , n1563 );
not ( n1565 , n1564 );
not ( n1566 , n1422 );
and ( n1567 , n1566 , n982 );
and ( n1568 , n1557 , n936 );
not ( n1569 , n1568 );
and ( n1570 , n1308 , n937 );
not ( n1571 , n1570 );
and ( n1572 , n1569 , n1571 );
not ( n1573 , n1572 );
and ( n1574 , n1567 , n1573 );
and ( n1575 , n1565 , n1574 );
not ( n1576 , n1575 );
and ( n1577 , n1561 , n1576 );
not ( n1578 , n1577 );
and ( n1579 , n1553 , n1578 );
and ( n1580 , n1529 , n1579 );
not ( n1581 , n1580 );
not ( n1582 , n1506 );
and ( n1583 , n1500 , n1582 );
not ( n1584 , n1583 );
and ( n1585 , n1520 , n1524 );
not ( n1586 , n1585 );
not ( n1587 , n1517 );
and ( n1588 , n1510 , n1587 );
and ( n1589 , n1588 , n1527 );
not ( n1590 , n1589 );
and ( n1591 , n1586 , n1590 );
not ( n1592 , n1591 );
and ( n1593 , n1508 , n1592 );
not ( n1594 , n1593 );
and ( n1595 , n1584 , n1594 );
and ( n1596 , n1581 , n1595 );
not ( n1597 , n1567 );
and ( n1598 , n1597 , n1572 );
not ( n1599 , n1598 );
and ( n1600 , n1565 , n1599 );
and ( n1601 , n1550 , n1600 );
and ( n1602 , n1529 , n1601 );
not ( n1603 , n1451 );
and ( n1604 , n1603 , n996 );
and ( n1605 , n1422 , n981 );
not ( n1606 , n1605 );
and ( n1607 , n1597 , n1606 );
and ( n1608 , n1604 , n1607 );
not ( n1609 , n1608 );
not ( n1610 , n1604 );
not ( n1611 , n1607 );
and ( n1612 , n1610 , n1611 );
not ( n1613 , n1612 );
not ( n1614 , n1436 );
and ( n1615 , n1614 , n953 );
and ( n1616 , n1451 , n996 );
not ( n1617 , n1616 );
and ( n1618 , n1603 , n995 );
not ( n1619 , n1618 );
and ( n1620 , n1617 , n1619 );
not ( n1621 , n1620 );
and ( n1622 , n1615 , n1621 );
and ( n1623 , n1613 , n1622 );
not ( n1624 , n1623 );
and ( n1625 , n1609 , n1624 );
not ( n1626 , n1615 );
and ( n1627 , n1626 , n1620 );
not ( n1628 , n1627 );
and ( n1629 , n1613 , n1628 );
not ( n1630 , n1465 );
and ( n1631 , n1630 , n967 );
and ( n1632 , n1614 , n952 );
not ( n1633 , n1632 );
and ( n1634 , n1436 , n953 );
not ( n1635 , n1634 );
and ( n1636 , n1633 , n1635 );
not ( n1637 , n1636 );
and ( n1638 , n1631 , n1637 );
not ( n1639 , n1638 );
not ( n1640 , n1631 );
and ( n1641 , n1640 , n1636 );
not ( n1642 , n1641 );
and ( n1643 , n1465 , n967 );
not ( n1644 , n1643 );
and ( n1645 , n1630 , n966 );
not ( n1646 , n1645 );
and ( n1647 , n1644 , n1646 );
not ( n1648 , n1647 );
not ( n1649 , n1369 );
and ( n1650 , n1649 , n1107 );
not ( n1651 , n1650 );
and ( n1652 , n1005 , n1651 );
not ( n1653 , n1652 );
and ( n1654 , n1648 , n1653 );
and ( n1655 , n1642 , n1654 );
not ( n1656 , n1655 );
and ( n1657 , n1639 , n1656 );
not ( n1658 , n1657 );
and ( n1659 , n1629 , n1658 );
not ( n1660 , n1659 );
and ( n1661 , n1625 , n1660 );
and ( n1662 , n1647 , n1652 );
not ( n1663 , n1662 );
and ( n1664 , n1642 , n1663 );
and ( n1665 , n1629 , n1664 );
not ( n1666 , n1383 );
and ( n1667 , n1666 , n1137 );
xor ( n1668 , n1369 , n1107 );
not ( n1669 , n1668 );
and ( n1670 , n1667 , n1669 );
not ( n1671 , n1670 );
not ( n1672 , n1667 );
and ( n1673 , n1672 , n1668 );
not ( n1674 , n1673 );
not ( n1675 , n1403 );
and ( n1676 , n1675 , n1121 );
xor ( n1677 , n1383 , n1136 );
and ( n1678 , n1676 , n1677 );
and ( n1679 , n1674 , n1678 );
not ( n1680 , n1679 );
xor ( n1681 , n1403 , n1120 );
not ( n1682 , n1390 );
and ( n1683 , n1682 , n1083 );
and ( n1684 , n1681 , n1683 );
not ( n1685 , n1676 );
not ( n1686 , n1677 );
and ( n1687 , n1685 , n1686 );
not ( n1688 , n1687 );
and ( n1689 , n1684 , n1688 );
and ( n1690 , n1674 , n1689 );
not ( n1691 , n1690 );
and ( n1692 , n1671 , n1680 , n1691 );
not ( n1693 , n1692 );
and ( n1694 , n1665 , n1693 );
not ( n1695 , n1694 );
and ( n1696 , n1661 , n1695 );
not ( n1697 , n1696 );
and ( n1698 , n1602 , n1697 );
not ( n1699 , n1698 );
and ( n1700 , n1596 , n1699 );
and ( n1701 , n1498 , n1700 );
not ( n1702 , n1701 );
not ( n1703 , n1498 );
not ( n1704 , n1700 );
and ( n1705 , n1703 , n1704 );
not ( n1706 , n1705 );
and ( n1707 , n1702 , n1706 );
not ( n1708 , n1707 );
and ( n1709 , n1484 , n1708 );
not ( n1710 , n1709 );
and ( n1711 , n1479 , n1710 );
and ( n1712 , n691 , n705 );
not ( n1713 , n1712 );
and ( n1714 , n1482 , n1713 );
not ( n1715 , n1714 );
xor ( n1716 , n1502 , n1491 );
and ( n1717 , n1353 , n880 );
and ( n1718 , n1717 , n1506 );
not ( n1719 , n1718 );
not ( n1720 , n1717 );
and ( n1721 , n1720 , n1582 );
not ( n1722 , n1721 );
and ( n1723 , n1515 , n1525 );
not ( n1724 , n1723 );
and ( n1725 , n1516 , n1524 );
not ( n1726 , n1725 );
and ( n1727 , n1534 , n1517 );
and ( n1728 , n1726 , n1727 );
not ( n1729 , n1728 );
and ( n1730 , n1724 , n1729 );
not ( n1731 , n1730 );
and ( n1732 , n1722 , n1731 );
not ( n1733 , n1732 );
and ( n1734 , n1719 , n1733 );
and ( n1735 , n1535 , n1587 );
not ( n1736 , n1735 );
and ( n1737 , n1726 , n1736 );
and ( n1738 , n1722 , n1737 );
and ( n1739 , n1294 , n909 );
and ( n1740 , n1739 , n1536 );
not ( n1741 , n1740 );
not ( n1742 , n1739 );
and ( n1743 , n1742 , n1537 );
not ( n1744 , n1743 );
and ( n1745 , n1323 , n923 );
and ( n1746 , n1541 , n1745 );
and ( n1747 , n1744 , n1746 );
not ( n1748 , n1747 );
and ( n1749 , n1741 , n1748 );
not ( n1750 , n1745 );
and ( n1751 , n1540 , n1750 );
not ( n1752 , n1751 );
and ( n1753 , n1744 , n1752 );
and ( n1754 , n1562 , n1570 );
not ( n1755 , n1754 );
and ( n1756 , n1556 , n1571 );
not ( n1757 , n1756 );
and ( n1758 , n1422 , n982 );
and ( n1759 , n1758 , n1572 );
and ( n1760 , n1757 , n1759 );
not ( n1761 , n1760 );
and ( n1762 , n1755 , n1761 );
not ( n1763 , n1762 );
and ( n1764 , n1753 , n1763 );
not ( n1765 , n1764 );
and ( n1766 , n1749 , n1765 );
not ( n1767 , n1766 );
and ( n1768 , n1738 , n1767 );
not ( n1769 , n1768 );
and ( n1770 , n1734 , n1769 );
not ( n1771 , n1758 );
and ( n1772 , n1771 , n1573 );
not ( n1773 , n1772 );
and ( n1774 , n1744 , n1752 , n1757 , n1773 );
and ( n1775 , n1738 , n1774 );
and ( n1776 , n1616 , n1611 );
not ( n1777 , n1776 );
and ( n1778 , n1617 , n1607 );
not ( n1779 , n1778 );
and ( n1780 , n1634 , n1620 );
and ( n1781 , n1779 , n1780 );
not ( n1782 , n1781 );
and ( n1783 , n1777 , n1782 );
and ( n1784 , n1635 , n1621 );
not ( n1785 , n1784 );
and ( n1786 , n1779 , n1785 );
and ( n1787 , n1643 , n1636 );
not ( n1788 , n1787 );
and ( n1789 , n1644 , n1637 );
not ( n1790 , n1789 );
and ( n1791 , n1369 , n1106 );
not ( n1792 , n1791 );
and ( n1793 , n1005 , n1792 );
not ( n1794 , n1793 );
and ( n1795 , n1647 , n1794 );
and ( n1796 , n1790 , n1795 );
not ( n1797 , n1796 );
and ( n1798 , n1788 , n1797 );
not ( n1799 , n1798 );
and ( n1800 , n1786 , n1799 );
not ( n1801 , n1800 );
and ( n1802 , n1783 , n1801 );
and ( n1803 , n1648 , n1793 );
not ( n1804 , n1803 );
and ( n1805 , n1790 , n1804 );
and ( n1806 , n1805 , n1786 );
and ( n1807 , n1383 , n1137 );
not ( n1808 , n1807 );
and ( n1809 , n1808 , n1669 );
not ( n1810 , n1809 );
and ( n1811 , n1390 , n1082 );
not ( n1812 , n1811 );
not ( n1813 , n1681 );
and ( n1814 , n1083 , n1813 );
not ( n1815 , n1814 );
and ( n1816 , n1812 , n1815 );
not ( n1817 , n1816 );
and ( n1818 , n1082 , n1681 );
not ( n1819 , n1818 );
and ( n1820 , n1403 , n1121 );
not ( n1821 , n1820 );
and ( n1822 , n1821 , n1677 );
not ( n1823 , n1822 );
and ( n1824 , n1819 , n1823 );
and ( n1825 , n1817 , n1824 );
and ( n1826 , n1810 , n1825 );
not ( n1827 , n1826 );
and ( n1828 , n1807 , n1668 );
not ( n1829 , n1828 );
and ( n1830 , n1820 , n1686 );
and ( n1831 , n1830 , n1810 );
not ( n1832 , n1831 );
and ( n1833 , n1829 , n1832 );
and ( n1834 , n1827 , n1833 );
not ( n1835 , n1834 );
and ( n1836 , n1806 , n1835 );
not ( n1837 , n1836 );
and ( n1838 , n1802 , n1837 );
not ( n1839 , n1838 );
and ( n1840 , n1775 , n1839 );
not ( n1841 , n1840 );
and ( n1842 , n1770 , n1841 );
and ( n1843 , n1716 , n1842 );
not ( n1844 , n1843 );
not ( n1845 , n1716 );
not ( n1846 , n1842 );
and ( n1847 , n1845 , n1846 );
not ( n1848 , n1847 );
and ( n1849 , n1844 , n1848 );
not ( n1850 , n1849 );
and ( n1851 , n1715 , n1850 );
not ( n1852 , n1851 );
and ( n1853 , n1711 , n1852 );
and ( n1854 , n1212 , n1853 );
not ( n1855 , n1854 );
and ( n1856 , n794 , n1855 );
not ( n1857 , n1856 );
and ( n1858 , n797 , n1857 );
not ( n1859 , n1858 );
buf ( n1860 , n1859 );
buf ( n1861 , n1860 );
buf ( n1862 , n529 );
and ( n1863 , n709 , n758 , n776 , n793 );
not ( n1864 , n1863 );
and ( n1865 , n1862 , n1864 );
not ( n1866 , n1865 );
buf ( n1867 , n530 );
and ( n1868 , n1867 , n1229 );
and ( n1869 , n1868 , n1213 );
not ( n1870 , n1869 );
not ( n1871 , n1868 );
buf ( n1872 , n531 );
and ( n1873 , n1872 , n1229 );
not ( n1874 , n1873 );
buf ( n1875 , n532 );
and ( n1876 , n1875 , n1229 );
not ( n1877 , n1876 );
and ( n1878 , n1874 , n1877 );
buf ( n1879 , n533 );
and ( n1880 , n1879 , n1229 );
not ( n1881 , n1880 );
buf ( n1882 , n534 );
and ( n1883 , n1882 , n1229 );
not ( n1884 , n1883 );
and ( n1885 , n1881 , n1884 );
buf ( n1886 , n535 );
and ( n1887 , n1886 , n1229 );
not ( n1888 , n1887 );
buf ( n1889 , n536 );
and ( n1890 , n1889 , n1229 );
not ( n1891 , n1890 );
and ( n1892 , n1888 , n1891 );
and ( n1893 , n1885 , n1892 );
buf ( n1894 , n537 );
and ( n1895 , n1894 , n1229 );
not ( n1896 , n1895 );
buf ( n1897 , n538 );
and ( n1898 , n1897 , n1229 );
not ( n1899 , n1898 );
and ( n1900 , n1896 , n1899 );
buf ( n1901 , n539 );
and ( n1902 , n1901 , n1229 );
not ( n1903 , n1902 );
buf ( n1904 , n540 );
and ( n1905 , n1904 , n1229 );
not ( n1906 , n1905 );
and ( n1907 , n1903 , n1906 );
and ( n1908 , n1900 , n1907 );
buf ( n1909 , n541 );
and ( n1910 , n1909 , n1229 );
not ( n1911 , n1910 );
and ( n1912 , n600 , n606 );
not ( n1913 , n1912 );
xor ( n1914 , n606 , n657 );
not ( n1915 , n1914 );
and ( n1916 , n599 , n1915 );
not ( n1917 , n1916 );
and ( n1918 , n1913 , n1917 );
not ( n1919 , n1918 );
and ( n1920 , n1919 , n1228 );
not ( n1921 , n1920 );
and ( n1922 , n1911 , n1921 );
buf ( n1923 , n542 );
and ( n1924 , n1923 , n1229 );
not ( n1925 , n1924 );
and ( n1926 , n600 , n608 );
not ( n1927 , n1926 );
xor ( n1928 , n608 , n656 );
not ( n1929 , n1928 );
and ( n1930 , n599 , n1929 );
not ( n1931 , n1930 );
and ( n1932 , n1927 , n1931 );
not ( n1933 , n1932 );
and ( n1934 , n1933 , n1228 );
not ( n1935 , n1934 );
and ( n1936 , n1925 , n1935 );
and ( n1937 , n1922 , n1936 );
buf ( n1938 , n543 );
and ( n1939 , n1938 , n1229 );
not ( n1940 , n1939 );
and ( n1941 , n600 , n604 );
not ( n1942 , n1941 );
xor ( n1943 , n604 , n658 );
not ( n1944 , n1943 );
and ( n1945 , n599 , n1944 );
not ( n1946 , n1945 );
and ( n1947 , n1942 , n1946 );
not ( n1948 , n1947 );
and ( n1949 , n1948 , n1228 );
not ( n1950 , n1949 );
and ( n1951 , n1940 , n1950 );
buf ( n1952 , n544 );
and ( n1953 , n1952 , n1229 );
not ( n1954 , n1953 );
and ( n1955 , n1480 , n1228 );
not ( n1956 , n1955 );
and ( n1957 , n1954 , n1956 );
and ( n1958 , n1951 , n1957 );
and ( n1959 , n1937 , n1958 );
and ( n1960 , n1908 , n1959 );
and ( n1961 , n1878 , n1893 , n1960 );
and ( n1962 , n1263 , n1242 );
and ( n1963 , n1437 , n1384 , n1466 , n1962 );
and ( n1964 , n1325 , n1404 , n1354 , n1963 );
and ( n1965 , n1961 , n1964 );
not ( n1966 , n1965 );
and ( n1967 , n1871 , n1966 );
not ( n1968 , n1967 );
and ( n1969 , n1868 , n1965 );
not ( n1970 , n1969 );
and ( n1971 , n1968 , n1970 );
not ( n1972 , n1971 );
and ( n1973 , n1246 , n1972 );
not ( n1974 , n1973 );
and ( n1975 , n1870 , n1974 );
and ( n1976 , n769 , n810 );
not ( n1977 , n1976 );
and ( n1978 , n1229 , n1977 );
not ( n1979 , n1978 );
and ( n1980 , n702 , n1979 );
buf ( n1981 , n545 );
and ( n1982 , n1981 , n834 );
not ( n1983 , n1982 );
and ( n1984 , n1862 , n838 );
not ( n1985 , n1984 );
buf ( n1986 , n546 );
and ( n1987 , n1986 , n847 );
not ( n1988 , n1987 );
and ( n1989 , n1983 , n1985 , n1988 );
not ( n1990 , n1989 );
buf ( n1991 , n547 );
and ( n1992 , n1991 , n834 );
not ( n1993 , n1992 );
buf ( n1994 , n548 );
and ( n1995 , n1994 , n838 );
not ( n1996 , n1995 );
buf ( n1997 , n549 );
and ( n1998 , n1997 , n847 );
not ( n1999 , n1998 );
and ( n2000 , n1993 , n1996 , n1999 );
buf ( n2001 , n550 );
and ( n2002 , n2001 , n838 );
not ( n2003 , n2002 );
buf ( n2004 , n551 );
and ( n2005 , n2004 , n843 );
not ( n2006 , n2005 );
and ( n2007 , n2003 , n2006 );
buf ( n2008 , n552 );
and ( n2009 , n2008 , n847 );
not ( n2010 , n2009 );
buf ( n2011 , n553 );
and ( n2012 , n2011 , n834 );
not ( n2013 , n2012 );
and ( n2014 , n2010 , n2013 );
and ( n2015 , n2007 , n2014 );
not ( n2016 , n2015 );
buf ( n2017 , n554 );
and ( n2018 , n2017 , n834 );
not ( n2019 , n2018 );
buf ( n2020 , n555 );
and ( n2021 , n2020 , n847 );
not ( n2022 , n2021 );
and ( n2023 , n2019 , n2022 );
buf ( n2024 , n556 );
and ( n2025 , n2024 , n838 );
not ( n2026 , n2025 );
buf ( n2027 , n557 );
and ( n2028 , n2027 , n843 );
not ( n2029 , n2028 );
and ( n2030 , n2026 , n2029 );
and ( n2031 , n2023 , n2030 );
not ( n2032 , n2031 );
buf ( n2033 , n558 );
and ( n2034 , n2033 , n838 );
not ( n2035 , n2034 );
buf ( n2036 , n559 );
and ( n2037 , n2036 , n843 );
not ( n2038 , n2037 );
and ( n2039 , n2035 , n2038 );
buf ( n2040 , n560 );
and ( n2041 , n2040 , n847 );
not ( n2042 , n2041 );
buf ( n2043 , n561 );
and ( n2044 , n2043 , n834 );
not ( n2045 , n2044 );
and ( n2046 , n2042 , n2045 );
and ( n2047 , n2039 , n2046 );
not ( n2048 , n2047 );
and ( n2049 , n2032 , n2048 );
buf ( n2050 , n562 );
and ( n2051 , n2050 , n838 );
not ( n2052 , n2051 );
buf ( n2053 , n563 );
and ( n2054 , n2053 , n843 );
not ( n2055 , n2054 );
and ( n2056 , n2052 , n2055 );
buf ( n2057 , n564 );
and ( n2058 , n2057 , n834 );
not ( n2059 , n2058 );
buf ( n2060 , n565 );
and ( n2061 , n2060 , n847 );
not ( n2062 , n2061 );
and ( n2063 , n2059 , n2062 );
and ( n2064 , n2056 , n2063 );
not ( n2065 , n2064 );
buf ( n2066 , n566 );
and ( n2067 , n2066 , n838 );
not ( n2068 , n2067 );
buf ( n2069 , n567 );
and ( n2070 , n2069 , n843 );
not ( n2071 , n2070 );
and ( n2072 , n2068 , n2071 );
buf ( n2073 , n568 );
and ( n2074 , n2073 , n834 );
not ( n2075 , n2074 );
buf ( n2076 , n569 );
and ( n2077 , n2076 , n847 );
not ( n2078 , n2077 );
and ( n2079 , n2075 , n2078 );
and ( n2080 , n2072 , n2079 );
not ( n2081 , n2080 );
and ( n2082 , n2065 , n2081 );
and ( n2083 , n2049 , n2082 );
and ( n2084 , n2016 , n2083 );
buf ( n2085 , n570 );
and ( n2086 , n2085 , n834 );
not ( n2087 , n2086 );
buf ( n2088 , n571 );
and ( n2089 , n2088 , n838 );
not ( n2090 , n2089 );
buf ( n2091 , n572 );
and ( n2092 , n2091 , n843 );
not ( n2093 , n2092 );
buf ( n2094 , n573 );
and ( n2095 , n2094 , n847 );
not ( n2096 , n2095 );
and ( n2097 , n2087 , n2090 , n2093 , n2096 );
not ( n2098 , n2097 );
buf ( n2099 , n574 );
and ( n2100 , n2099 , n838 );
not ( n2101 , n2100 );
buf ( n2102 , n575 );
and ( n2103 , n2102 , n847 );
not ( n2104 , n2103 );
and ( n2105 , n2101 , n2104 );
buf ( n2106 , n576 );
and ( n2107 , n2106 , n843 );
not ( n2108 , n2107 );
buf ( n2109 , n577 );
and ( n2110 , n2109 , n834 );
not ( n2111 , n2110 );
and ( n2112 , n2108 , n2111 );
and ( n2113 , n2105 , n2112 );
not ( n2114 , n2113 );
buf ( n2115 , n578 );
and ( n2116 , n2115 , n838 );
not ( n2117 , n2116 );
buf ( n2118 , n579 );
and ( n2119 , n2118 , n847 );
not ( n2120 , n2119 );
and ( n2121 , n2117 , n2120 );
buf ( n2122 , n580 );
and ( n2123 , n2122 , n843 );
not ( n2124 , n2123 );
buf ( n2125 , n581 );
and ( n2126 , n2125 , n834 );
not ( n2127 , n2126 );
and ( n2128 , n2124 , n2127 );
and ( n2129 , n2121 , n2128 );
not ( n2130 , n2129 );
buf ( n2131 , n582 );
and ( n2132 , n2131 , n838 );
not ( n2133 , n2132 );
buf ( n2134 , n583 );
and ( n2135 , n2134 , n843 );
not ( n2136 , n2135 );
and ( n2137 , n2133 , n2136 );
buf ( n2138 , n584 );
and ( n2139 , n2138 , n834 );
not ( n2140 , n2139 );
buf ( n2141 , n585 );
and ( n2142 , n2141 , n847 );
not ( n2143 , n2142 );
and ( n2144 , n2140 , n2143 );
and ( n2145 , n2137 , n2144 );
not ( n2146 , n2145 );
and ( n2147 , n2098 , n2114 , n2130 , n2146 );
buf ( n2148 , n586 );
and ( n2149 , n2148 , n834 );
not ( n2150 , n2149 );
buf ( n2151 , n587 );
and ( n2152 , n2151 , n838 );
not ( n2153 , n2152 );
buf ( n2154 , n588 );
and ( n2155 , n2154 , n843 );
not ( n2156 , n2155 );
buf ( n2157 , n589 );
and ( n2158 , n2157 , n847 );
not ( n2159 , n2158 );
and ( n2160 , n2150 , n2153 , n2156 , n2159 );
not ( n2161 , n2160 );
not ( n2162 , n1036 );
and ( n2163 , n2161 , n2162 );
buf ( n2164 , n590 );
and ( n2165 , n2164 , n838 );
not ( n2166 , n2165 );
buf ( n2167 , n591 );
and ( n2168 , n2167 , n843 );
not ( n2169 , n2168 );
and ( n2170 , n2166 , n2169 );
buf ( n2171 , n592 );
and ( n2172 , n2171 , n834 );
not ( n2173 , n2172 );
buf ( n2174 , n593 );
and ( n2175 , n2174 , n847 );
not ( n2176 , n2175 );
and ( n2177 , n2173 , n2176 );
and ( n2178 , n2170 , n2177 );
not ( n2179 , n2178 );
buf ( n2180 , n594 );
and ( n2181 , n2180 , n838 );
not ( n2182 , n2181 );
buf ( n2183 , n595 );
and ( n2184 , n2183 , n843 );
not ( n2185 , n2184 );
and ( n2186 , n2182 , n2185 );
buf ( n2187 , n596 );
and ( n2188 , n2187 , n834 );
not ( n2189 , n2188 );
buf ( n2190 , n597 );
and ( n2191 , n2190 , n847 );
not ( n2192 , n2191 );
and ( n2193 , n2189 , n2192 );
and ( n2194 , n2186 , n2193 );
not ( n2195 , n2194 );
and ( n2196 , n2179 , n2195 );
and ( n2197 , n2163 , n2196 );
and ( n2198 , n2147 , n2197 );
and ( n2199 , n2084 , n2198 );
and ( n2200 , n1055 , n2199 );
not ( n2201 , n2200 );
and ( n2202 , n2000 , n2201 );
not ( n2203 , n2202 );
and ( n2204 , n2083 , n2198 );
and ( n2205 , n1055 , n2204 );
xor ( n2206 , n2015 , n2205 );
not ( n2207 , n2206 );
not ( n2208 , n2205 );
and ( n2209 , n2032 , n2082 );
and ( n2210 , n2209 , n2198 );
and ( n2211 , n1055 , n2210 );
not ( n2212 , n2211 );
and ( n2213 , n2047 , n2212 );
not ( n2214 , n2213 );
and ( n2215 , n2208 , n2214 );
and ( n2216 , n2082 , n2198 );
and ( n2217 , n1055 , n2216 );
not ( n2218 , n2217 );
and ( n2219 , n2065 , n2198 );
and ( n2220 , n1055 , n2219 );
not ( n2221 , n2220 );
and ( n2222 , n2080 , n2221 );
not ( n2223 , n2222 );
and ( n2224 , n2218 , n2223 );
and ( n2225 , n2031 , n2218 );
not ( n2226 , n2225 );
and ( n2227 , n2212 , n2226 );
and ( n2228 , n2224 , n2227 );
and ( n2229 , n2215 , n2228 );
and ( n2230 , n1055 , n2198 );
not ( n2231 , n2230 );
and ( n2232 , n2064 , n2231 );
not ( n2233 , n2232 );
and ( n2234 , n2221 , n2233 );
and ( n2235 , n2098 , n2146 );
and ( n2236 , n2163 , n2235 );
and ( n2237 , n2130 , n2195 );
and ( n2238 , n2114 , n2237 );
and ( n2239 , n2236 , n2238 );
and ( n2240 , n1055 , n2239 );
not ( n2241 , n2240 );
and ( n2242 , n2178 , n2241 );
not ( n2243 , n2242 );
and ( n2244 , n2231 , n2243 );
and ( n2245 , n2237 , n2236 );
and ( n2246 , n1055 , n2245 );
not ( n2247 , n2246 );
and ( n2248 , n2113 , n2247 );
not ( n2249 , n2248 );
and ( n2250 , n2241 , n2249 );
and ( n2251 , n2244 , n2250 );
and ( n2252 , n2234 , n2251 );
and ( n2253 , n1161 , n1194 );
and ( n2254 , n1177 , n2252 , n2253 );
and ( n2255 , n2146 , n2163 );
and ( n2256 , n2255 , n1055 );
not ( n2257 , n2256 );
and ( n2258 , n2163 , n1055 );
not ( n2259 , n2258 );
and ( n2260 , n2145 , n2259 );
not ( n2261 , n2260 );
and ( n2262 , n2257 , n2261 );
xor ( n2263 , n2097 , n2256 );
not ( n2264 , n2263 );
and ( n2265 , n2162 , n1055 );
not ( n2266 , n2265 );
and ( n2267 , n2160 , n2266 );
not ( n2268 , n2267 );
and ( n2269 , n2259 , n2268 );
and ( n2270 , n2264 , n2269 );
and ( n2271 , n2130 , n2236 );
and ( n2272 , n1055 , n2271 );
not ( n2273 , n2272 );
and ( n2274 , n2236 , n1055 );
not ( n2275 , n2274 );
and ( n2276 , n2129 , n2275 );
not ( n2277 , n2276 );
and ( n2278 , n2273 , n2277 );
and ( n2279 , n2194 , n2272 );
not ( n2280 , n2279 );
and ( n2281 , n2195 , n2273 );
not ( n2282 , n2281 );
and ( n2283 , n2280 , n2282 );
not ( n2284 , n2283 );
and ( n2285 , n2278 , n2284 );
and ( n2286 , n1093 , n1201 );
and ( n2287 , n1090 , n2286 );
and ( n2288 , n2262 , n2270 , n2285 , n2287 );
and ( n2289 , n1084 , n2288 );
and ( n2290 , n2229 , n2254 , n2289 );
and ( n2291 , n2207 , n2290 );
and ( n2292 , n2203 , n2291 );
and ( n2293 , n1990 , n2292 );
not ( n2294 , n2293 );
and ( n2295 , n1067 , n2294 );
and ( n2296 , n1980 , n2295 );
not ( n2297 , n2296 );
and ( n2298 , n1975 , n2297 );
not ( n2299 , n2298 );
and ( n2300 , n1863 , n2299 );
not ( n2301 , n2300 );
and ( n2302 , n1866 , n2301 );
not ( n2303 , n2302 );
buf ( n2304 , n2303 );
buf ( n2305 , n2304 );
and ( n2306 , n997 , n795 );
not ( n2307 , n2306 );
not ( n2308 , n1830 );
not ( n2309 , n1825 );
and ( n2310 , n2308 , n2309 );
and ( n2311 , n1829 , n1810 );
xor ( n2312 , n2310 , n2311 );
not ( n2313 , n2312 );
and ( n2314 , n1715 , n2313 );
not ( n2315 , n2314 );
and ( n2316 , n1649 , n1213 );
not ( n2317 , n2316 );
and ( n2318 , n1383 , n1404 );
not ( n2319 , n2318 );
and ( n2320 , n1369 , n2319 );
not ( n2321 , n2320 );
and ( n2322 , n1649 , n2318 );
not ( n2323 , n2322 );
and ( n2324 , n2321 , n2323 );
not ( n2325 , n2324 );
and ( n2326 , n1246 , n2325 );
not ( n2327 , n2326 );
and ( n2328 , n2317 , n2327 );
and ( n2329 , n1671 , n1674 );
not ( n2330 , n1678 );
not ( n2331 , n1689 );
and ( n2332 , n2330 , n2331 );
and ( n2333 , n2329 , n2332 );
not ( n2334 , n2333 );
not ( n2335 , n2329 );
not ( n2336 , n2332 );
and ( n2337 , n2335 , n2336 );
not ( n2338 , n2337 );
and ( n2339 , n2334 , n2338 );
not ( n2340 , n2339 );
and ( n2341 , n1484 , n2340 );
not ( n2342 , n2341 );
and ( n2343 , n2328 , n2342 );
and ( n2344 , n2315 , n2343 );
and ( n2345 , n811 , n1137 );
not ( n2346 , n2345 );
and ( n2347 , n1145 , n1084 );
not ( n2348 , n2347 );
and ( n2349 , n1121 , n1084 );
and ( n2350 , n1137 , n2349 );
and ( n2351 , n1107 , n2350 );
not ( n2352 , n2351 );
and ( n2353 , n1143 , n2352 );
not ( n2354 , n2353 );
and ( n2355 , n2348 , n2354 );
and ( n2356 , n810 , n2355 );
not ( n2357 , n2356 );
and ( n2358 , n2346 , n2357 );
not ( n2359 , n2358 );
and ( n2360 , n702 , n2359 );
not ( n2361 , n2360 );
and ( n2362 , n2344 , n2361 );
not ( n2363 , n2362 );
and ( n2364 , n794 , n2363 );
not ( n2365 , n2364 );
and ( n2366 , n2307 , n2365 );
not ( n2367 , n2366 );
buf ( n2368 , n2367 );
buf ( n2369 , n2368 );
and ( n2370 , n1122 , n1864 );
not ( n2371 , n2370 );
and ( n2372 , n1811 , n1819 );
not ( n2373 , n2372 );
and ( n2374 , n1815 , n2373 );
and ( n2375 , n2308 , n1823 );
and ( n2376 , n2374 , n2375 );
not ( n2377 , n2376 );
not ( n2378 , n2374 );
not ( n2379 , n2375 );
and ( n2380 , n2378 , n2379 );
not ( n2381 , n2380 );
and ( n2382 , n2377 , n2381 );
not ( n2383 , n2382 );
and ( n2384 , n1715 , n2383 );
not ( n2385 , n2384 );
and ( n2386 , n1213 , n1666 );
not ( n2387 , n2386 );
not ( n2388 , n1404 );
and ( n2389 , n1383 , n2388 );
not ( n2390 , n2389 );
and ( n2391 , n1666 , n1404 );
not ( n2392 , n2391 );
and ( n2393 , n2390 , n2392 );
not ( n2394 , n2393 );
and ( n2395 , n1246 , n2394 );
not ( n2396 , n2395 );
and ( n2397 , n2387 , n2396 );
not ( n2398 , n1684 );
and ( n2399 , n2330 , n1688 );
and ( n2400 , n2398 , n2399 );
not ( n2401 , n2400 );
not ( n2402 , n2399 );
and ( n2403 , n1684 , n2402 );
not ( n2404 , n2403 );
and ( n2405 , n2401 , n2404 );
not ( n2406 , n2405 );
and ( n2407 , n1484 , n2406 );
not ( n2408 , n2407 );
and ( n2409 , n2397 , n2408 );
and ( n2410 , n2385 , n2409 );
and ( n2411 , n811 , n1121 );
not ( n2412 , n2411 );
xor ( n2413 , n1107 , n2350 );
and ( n2414 , n810 , n2413 );
not ( n2415 , n2414 );
and ( n2416 , n2412 , n2415 );
not ( n2417 , n2416 );
and ( n2418 , n702 , n2417 );
not ( n2419 , n2418 );
and ( n2420 , n2410 , n2419 );
not ( n2421 , n2420 );
and ( n2422 , n1863 , n2421 );
not ( n2423 , n2422 );
and ( n2424 , n2371 , n2423 );
not ( n2425 , n2424 );
buf ( n2426 , n2425 );
buf ( n2427 , n2426 );
and ( n2428 , n720 , n675 );
and ( n2429 , n2428 , n702 , n756 );
not ( n2430 , n793 );
and ( n2431 , n719 , n777 , n2430 );
and ( n2432 , n2429 , n2431 );
and ( n2433 , n811 , n2284 );
not ( n2434 , n2433 );
not ( n2435 , n2244 );
and ( n2436 , n1161 , n1177 , n1194 );
and ( n2437 , n1084 , n2436 );
and ( n2438 , n2288 , n2437 );
and ( n2439 , n2250 , n2438 );
not ( n2440 , n2439 );
and ( n2441 , n2435 , n2440 );
not ( n2442 , n2441 );
and ( n2443 , n2244 , n2439 );
not ( n2444 , n2443 );
and ( n2445 , n2442 , n2444 );
and ( n2446 , n810 , n2445 );
not ( n2447 , n2446 );
and ( n2448 , n2434 , n2447 );
not ( n2449 , n2448 );
and ( n2450 , n2432 , n2449 );
not ( n2451 , n2450 );
not ( n2452 , n1483 );
and ( n2453 , n2452 , n706 );
and ( n2454 , n757 , n2431 );
and ( n2455 , n2453 , n2454 );
and ( n2456 , n1899 , n2195 );
and ( n2457 , n1902 , n2113 );
not ( n2458 , n2457 );
and ( n2459 , n1903 , n2114 );
not ( n2460 , n2459 );
and ( n2461 , n2458 , n2460 );
xor ( n2462 , n2456 , n2461 );
and ( n2463 , n1896 , n2130 );
and ( n2464 , n1898 , n2195 );
not ( n2465 , n2464 );
and ( n2466 , n1899 , n2194 );
not ( n2467 , n2466 );
and ( n2468 , n2465 , n2467 );
not ( n2469 , n2468 );
and ( n2470 , n2463 , n2469 );
not ( n2471 , n2470 );
not ( n2472 , n2463 );
and ( n2473 , n2472 , n2468 );
not ( n2474 , n2473 );
and ( n2475 , n1957 , n2098 );
and ( n2476 , n1895 , n2129 );
not ( n2477 , n2476 );
and ( n2478 , n2477 , n2472 );
and ( n2479 , n2475 , n2478 );
and ( n2480 , n2474 , n2479 );
not ( n2481 , n2480 );
and ( n2482 , n2471 , n2481 );
not ( n2483 , n2475 );
not ( n2484 , n2478 );
and ( n2485 , n2483 , n2484 );
not ( n2486 , n2485 );
and ( n2487 , n2474 , n2486 );
not ( n2488 , n1957 );
and ( n2489 , n2488 , n2097 );
not ( n2490 , n2489 );
and ( n2491 , n2483 , n2490 );
and ( n2492 , n1951 , n2146 );
and ( n2493 , n2491 , n2492 );
not ( n2494 , n2493 );
not ( n2495 , n2491 );
not ( n2496 , n2492 );
and ( n2497 , n2495 , n2496 );
not ( n2498 , n2497 );
and ( n2499 , n1922 , n2161 );
not ( n2500 , n1951 );
and ( n2501 , n2500 , n2145 );
not ( n2502 , n2501 );
and ( n2503 , n2502 , n2496 );
and ( n2504 , n2499 , n2503 );
and ( n2505 , n2498 , n2504 );
not ( n2506 , n2505 );
and ( n2507 , n2494 , n2506 );
not ( n2508 , n2499 );
not ( n2509 , n2503 );
and ( n2510 , n2508 , n2509 );
not ( n2511 , n2510 );
and ( n2512 , n2498 , n2511 );
and ( n2513 , n1936 , n2162 );
not ( n2514 , n1922 );
and ( n2515 , n2514 , n2161 );
not ( n2516 , n2515 );
and ( n2517 , n1922 , n2160 );
not ( n2518 , n2517 );
and ( n2519 , n2516 , n2518 );
not ( n2520 , n2519 );
and ( n2521 , n2513 , n2520 );
not ( n2522 , n2521 );
not ( n2523 , n2513 );
and ( n2524 , n2523 , n2519 );
not ( n2525 , n2524 );
not ( n2526 , n1936 );
and ( n2527 , n2526 , n1036 );
not ( n2528 , n2527 );
and ( n2529 , n2528 , n2523 );
and ( n2530 , n1487 , n2529 );
and ( n2531 , n2525 , n2530 );
not ( n2532 , n2531 );
and ( n2533 , n2522 , n2532 );
not ( n2534 , n2533 );
and ( n2535 , n2512 , n2534 );
not ( n2536 , n2535 );
and ( n2537 , n2507 , n2536 );
not ( n2538 , n2537 );
and ( n2539 , n2487 , n2538 );
not ( n2540 , n2539 );
and ( n2541 , n2482 , n2540 );
not ( n2542 , n2529 );
and ( n2543 , n1488 , n2542 );
not ( n2544 , n2543 );
and ( n2545 , n2525 , n2544 );
and ( n2546 , n2545 , n2512 );
and ( n2547 , n2487 , n2546 );
and ( n2548 , n1503 , n1492 );
not ( n2549 , n2548 );
and ( n2550 , n1722 , n2549 );
and ( n2551 , n1737 , n2550 );
not ( n2552 , n1786 );
and ( n2553 , n1783 , n2552 );
not ( n2554 , n2553 );
and ( n2555 , n1777 , n1788 , n1782 , n1797 );
not ( n2556 , n2555 );
and ( n2557 , n1774 , n2551 , n2554 , n2556 );
not ( n2558 , n2557 );
and ( n2559 , n2551 , n1764 );
not ( n2560 , n2559 );
and ( n2561 , n2308 , n1829 );
and ( n2562 , n2309 , n2561 );
not ( n2563 , n2562 );
and ( n2564 , n1757 , n1773 );
and ( n2565 , n1753 , n1805 , n2564 , n1810 );
and ( n2566 , n2551 , n2554 , n2563 , n2565 );
not ( n2567 , n2566 );
and ( n2568 , n1502 , n1491 );
not ( n2569 , n2568 );
and ( n2570 , n1718 , n2549 );
not ( n2571 , n2570 );
and ( n2572 , n2569 , n2571 );
and ( n2573 , n2550 , n1731 );
not ( n2574 , n2573 );
and ( n2575 , n2572 , n2574 );
not ( n2576 , n1749 );
and ( n2577 , n2551 , n2576 );
not ( n2578 , n2577 );
and ( n2579 , n2575 , n2578 );
and ( n2580 , n2558 , n2560 , n2567 , n2579 );
not ( n2581 , n2580 );
and ( n2582 , n2547 , n2581 );
not ( n2583 , n2582 );
and ( n2584 , n2541 , n2583 );
not ( n2585 , n2584 );
and ( n2586 , n2462 , n2585 );
not ( n2587 , n2586 );
not ( n2588 , n2462 );
and ( n2589 , n2588 , n2584 );
not ( n2590 , n2589 );
and ( n2591 , n2587 , n2590 );
and ( n2592 , n2455 , n2591 );
not ( n2593 , n2592 );
not ( n2594 , n720 );
and ( n2595 , n2594 , n2106 );
not ( n2596 , n2595 );
and ( n2597 , n2428 , n704 , n756 );
and ( n2598 , n2597 , n2431 );
and ( n2599 , n1900 , n1959 );
and ( n2600 , n2599 , n1964 );
not ( n2601 , n2600 );
and ( n2602 , n1903 , n2601 );
not ( n2603 , n2602 );
and ( n2604 , n1902 , n2600 );
not ( n2605 , n2604 );
and ( n2606 , n2603 , n2605 );
not ( n2607 , n2606 );
and ( n2608 , n2598 , n2607 );
not ( n2609 , n2608 );
and ( n2610 , n2596 , n2609 );
and ( n2611 , n1480 , n674 );
and ( n2612 , n720 , n2611 );
and ( n2613 , n719 , n2612 , n704 , n756 );
not ( n2614 , n2613 );
and ( n2615 , n1213 , n2454 );
not ( n2616 , n2615 );
and ( n2617 , n2614 , n2616 );
not ( n2618 , n2617 );
and ( n2619 , n1902 , n2618 );
not ( n2620 , n2619 );
and ( n2621 , n1003 , n960 );
and ( n2622 , n946 , n2621 );
and ( n2623 , n989 , n2622 );
and ( n2624 , n975 , n2623 );
and ( n2625 , n930 , n2624 );
and ( n2626 , n916 , n2625 );
and ( n2627 , n902 , n2626 );
and ( n2628 , n888 , n2627 );
and ( n2629 , n857 , n2628 );
and ( n2630 , n868 , n2629 );
and ( n2631 , n841 , n2630 );
and ( n2632 , n1043 , n2631 );
and ( n2633 , n1030 , n2632 );
and ( n2634 , n2154 , n2633 );
and ( n2635 , n2134 , n2634 );
and ( n2636 , n2091 , n2635 );
and ( n2637 , n2122 , n2636 );
and ( n2638 , n2183 , n2637 );
xor ( n2639 , n2106 , n2638 );
not ( n2640 , n2455 );
and ( n2641 , n1484 , n2454 );
not ( n2642 , n2641 );
not ( n2643 , n2432 );
and ( n2644 , n720 , n2643 );
and ( n2645 , n2640 , n2642 , n2644 );
not ( n2646 , n2598 );
and ( n2647 , n2646 , n2617 );
and ( n2648 , n2645 , n2647 );
and ( n2649 , n2639 , n2648 );
not ( n2650 , n2649 );
and ( n2651 , n2610 , n2620 , n2650 );
not ( n2652 , n2461 );
and ( n2653 , n2464 , n2652 );
not ( n2654 , n2653 );
and ( n2655 , n2465 , n2461 );
not ( n2656 , n2655 );
and ( n2657 , n2654 , n2656 );
and ( n2658 , n1895 , n2130 );
and ( n2659 , n2658 , n2468 );
not ( n2660 , n2659 );
and ( n2661 , n2488 , n2098 );
and ( n2662 , n2661 , n2484 );
not ( n2663 , n2658 );
and ( n2664 , n2663 , n2469 );
not ( n2665 , n2664 );
and ( n2666 , n2662 , n2665 );
not ( n2667 , n2666 );
and ( n2668 , n2660 , n2667 );
not ( n2669 , n2661 );
and ( n2670 , n2669 , n2478 );
not ( n2671 , n2670 );
and ( n2672 , n2665 , n2671 );
and ( n2673 , n2500 , n2146 );
not ( n2674 , n2673 );
and ( n2675 , n2491 , n2674 );
not ( n2676 , n2675 );
and ( n2677 , n2516 , n2503 );
not ( n2678 , n2677 );
and ( n2679 , n2676 , n2678 );
and ( n2680 , n2526 , n2162 );
and ( n2681 , n2680 , n2519 );
not ( n2682 , n2681 );
and ( n2683 , n1243 , n1050 );
and ( n2684 , n2683 , n2542 );
not ( n2685 , n2680 );
and ( n2686 , n2685 , n2520 );
not ( n2687 , n2686 );
and ( n2688 , n2684 , n2687 );
not ( n2689 , n2688 );
and ( n2690 , n2682 , n2689 );
not ( n2691 , n2690 );
and ( n2692 , n2679 , n2691 );
not ( n2693 , n2692 );
and ( n2694 , n2495 , n2673 );
not ( n2695 , n2694 );
and ( n2696 , n2515 , n2509 );
and ( n2697 , n2676 , n2696 );
not ( n2698 , n2697 );
and ( n2699 , n2695 , n2698 );
and ( n2700 , n2693 , n2699 );
not ( n2701 , n2700 );
and ( n2702 , n2672 , n2701 );
not ( n2703 , n2702 );
and ( n2704 , n2668 , n2703 );
not ( n2705 , n2683 );
and ( n2706 , n2705 , n2529 );
not ( n2707 , n2706 );
and ( n2708 , n2687 , n2707 );
and ( n2709 , n2679 , n2708 );
and ( n2710 , n2672 , n2709 );
and ( n2711 , n1508 , n1497 );
not ( n2712 , n2711 );
and ( n2713 , n1583 , n1497 );
not ( n2714 , n2713 );
and ( n2715 , n1494 , n2714 );
and ( n2716 , n2712 , n2715 );
not ( n2717 , n2716 );
and ( n2718 , n1528 , n1553 , n1578 );
not ( n2719 , n2718 );
and ( n2720 , n1591 , n2715 );
and ( n2721 , n2719 , n2720 );
not ( n2722 , n2721 );
and ( n2723 , n2717 , n2722 );
not ( n2724 , n2723 );
not ( n2725 , n1629 );
and ( n2726 , n2725 , n1625 );
not ( n2727 , n2726 );
and ( n2728 , n2711 , n1528 , n1601 , n2727 );
and ( n2729 , n1671 , n2330 , n2331 );
not ( n2730 , n2729 );
and ( n2731 , n1674 , n1664 , n2730 );
not ( n2732 , n2731 );
and ( n2733 , n1625 , n1657 );
and ( n2734 , n2732 , n2733 );
not ( n2735 , n2734 );
and ( n2736 , n2728 , n2735 );
not ( n2737 , n2736 );
and ( n2738 , n2724 , n2737 );
not ( n2739 , n2738 );
and ( n2740 , n2710 , n2739 );
not ( n2741 , n2740 );
and ( n2742 , n2704 , n2741 );
not ( n2743 , n2742 );
and ( n2744 , n2657 , n2743 );
not ( n2745 , n2744 );
not ( n2746 , n2657 );
and ( n2747 , n2746 , n2742 );
not ( n2748 , n2747 );
and ( n2749 , n2745 , n2748 );
and ( n2750 , n2641 , n2749 );
not ( n2751 , n2750 );
and ( n2752 , n2651 , n2751 );
and ( n2753 , n2593 , n2752 );
and ( n2754 , n2451 , n2753 );
not ( n2755 , n2754 );
buf ( n2756 , n2755 );
buf ( n2757 , n2756 );
and ( n2758 , n2050 , n1864 );
not ( n2759 , n2758 );
and ( n2760 , n811 , n2244 );
not ( n2761 , n2760 );
and ( n2762 , n2288 , n2254 );
and ( n2763 , n1084 , n2762 );
and ( n2764 , n2224 , n2763 );
not ( n2765 , n2764 );
not ( n2766 , n2224 );
not ( n2767 , n2763 );
and ( n2768 , n2766 , n2767 );
not ( n2769 , n2768 );
and ( n2770 , n2765 , n2769 );
and ( n2771 , n810 , n2770 );
not ( n2772 , n2771 );
and ( n2773 , n2761 , n2772 );
not ( n2774 , n2773 );
and ( n2775 , n702 , n2774 );
not ( n2776 , n2775 );
and ( n2777 , n1906 , n2179 );
not ( n2778 , n2777 );
and ( n2779 , n1883 , n2065 );
not ( n2780 , n2779 );
and ( n2781 , n1884 , n2064 );
not ( n2782 , n2781 );
and ( n2783 , n2780 , n2782 );
xor ( n2784 , n2778 , n2783 );
and ( n2785 , n1905 , n2179 );
not ( n2786 , n2785 );
and ( n2787 , n1906 , n2178 );
not ( n2788 , n2787 );
and ( n2789 , n2786 , n2788 );
not ( n2790 , n2789 );
and ( n2791 , n2459 , n2790 );
not ( n2792 , n2791 );
and ( n2793 , n2456 , n2461 );
and ( n2794 , n2460 , n2789 );
not ( n2795 , n2794 );
and ( n2796 , n2793 , n2795 );
not ( n2797 , n2796 );
and ( n2798 , n2792 , n2797 );
not ( n2799 , n2456 );
and ( n2800 , n2799 , n2652 );
not ( n2801 , n2800 );
and ( n2802 , n2801 , n2795 );
not ( n2803 , n2482 );
and ( n2804 , n2802 , n2803 );
not ( n2805 , n2804 );
and ( n2806 , n2798 , n2805 );
and ( n2807 , n2487 , n2802 );
and ( n2808 , n2807 , n2538 );
not ( n2809 , n2808 );
and ( n2810 , n2806 , n2809 );
and ( n2811 , n2807 , n2546 );
and ( n2812 , n2811 , n2581 );
not ( n2813 , n2812 );
and ( n2814 , n2810 , n2813 );
not ( n2815 , n2814 );
and ( n2816 , n2784 , n2815 );
not ( n2817 , n2816 );
not ( n2818 , n2784 );
and ( n2819 , n2818 , n2814 );
not ( n2820 , n2819 );
and ( n2821 , n2817 , n2820 );
and ( n2822 , n1715 , n2821 );
not ( n2823 , n2822 );
and ( n2824 , n1883 , n1213 );
not ( n2825 , n2824 );
and ( n2826 , n1960 , n1964 );
not ( n2827 , n2826 );
and ( n2828 , n1884 , n2827 );
not ( n2829 , n2828 );
and ( n2830 , n1883 , n2826 );
not ( n2831 , n2830 );
and ( n2832 , n2829 , n2831 );
not ( n2833 , n2832 );
and ( n2834 , n1246 , n2833 );
not ( n2835 , n2834 );
and ( n2836 , n2825 , n2835 );
not ( n2837 , n2783 );
and ( n2838 , n2786 , n2837 );
not ( n2839 , n2838 );
and ( n2840 , n2785 , n2783 );
not ( n2841 , n2840 );
and ( n2842 , n2839 , n2841 );
and ( n2843 , n1902 , n2114 );
and ( n2844 , n2843 , n2789 );
not ( n2845 , n2844 );
not ( n2846 , n2843 );
and ( n2847 , n2846 , n2790 );
not ( n2848 , n2847 );
and ( n2849 , n2653 , n2848 );
not ( n2850 , n2849 );
and ( n2851 , n2845 , n2850 );
and ( n2852 , n2668 , n2851 );
and ( n2853 , n2693 , n2852 , n2699 );
not ( n2854 , n2853 );
not ( n2855 , n2672 );
and ( n2856 , n2855 , n2852 );
not ( n2857 , n2856 );
and ( n2858 , n2656 , n2848 );
not ( n2859 , n2858 );
and ( n2860 , n2859 , n2851 );
not ( n2861 , n2860 );
and ( n2862 , n2857 , n2861 );
and ( n2863 , n2854 , n2862 );
not ( n2864 , n2863 );
and ( n2865 , n2858 , n2672 );
and ( n2866 , n2865 , n2709 );
and ( n2867 , n2866 , n2739 );
not ( n2868 , n2867 );
and ( n2869 , n2864 , n2868 );
not ( n2870 , n2869 );
and ( n2871 , n2842 , n2870 );
not ( n2872 , n2871 );
not ( n2873 , n2842 );
and ( n2874 , n2873 , n2869 );
not ( n2875 , n2874 );
and ( n2876 , n2872 , n2875 );
and ( n2877 , n1484 , n2876 );
not ( n2878 , n2877 );
and ( n2879 , n2836 , n2878 );
and ( n2880 , n2823 , n2879 );
and ( n2881 , n2776 , n2880 );
not ( n2882 , n2881 );
and ( n2883 , n1863 , n2882 );
not ( n2884 , n2883 );
and ( n2885 , n2759 , n2884 );
not ( n2886 , n2885 );
buf ( n2887 , n2886 );
buf ( n2888 , n2887 );
and ( n2889 , n776 , n2430 );
and ( n2890 , n758 , n2889 );
and ( n2891 , n2453 , n2890 );
and ( n2892 , n2522 , n2525 );
not ( n2893 , n2530 );
and ( n2894 , n2544 , n2581 );
not ( n2895 , n2894 );
and ( n2896 , n2893 , n2895 );
xor ( n2897 , n2892 , n2896 );
not ( n2898 , n2897 );
and ( n2899 , n2891 , n2898 );
not ( n2900 , n2899 );
and ( n2901 , n675 , n702 );
and ( n2902 , n2901 , n2890 );
and ( n2903 , n811 , n1201 );
not ( n2904 , n2903 );
not ( n2905 , n2262 );
and ( n2906 , n1201 , n1090 );
and ( n2907 , n2269 , n2906 );
and ( n2908 , n2907 , n1196 );
and ( n2909 , n1084 , n2908 );
and ( n2910 , n2905 , n2909 );
not ( n2911 , n2910 );
not ( n2912 , n2909 );
and ( n2913 , n2262 , n2912 );
not ( n2914 , n2913 );
and ( n2915 , n2911 , n2914 );
not ( n2916 , n2915 );
and ( n2917 , n810 , n2916 );
not ( n2918 , n2917 );
and ( n2919 , n2904 , n2918 );
not ( n2920 , n2919 );
and ( n2921 , n2902 , n2920 );
not ( n2922 , n2921 );
and ( n2923 , n709 , n777 );
not ( n2924 , n2923 );
and ( n2925 , n676 , n702 );
not ( n2926 , n2925 );
and ( n2927 , n719 , n2926 , n757 );
and ( n2928 , n2611 , n704 );
not ( n2929 , n2928 );
and ( n2930 , n2929 , n793 );
not ( n2931 , n2930 );
and ( n2932 , n2927 , n2931 );
and ( n2933 , n2924 , n2932 );
not ( n2934 , n2933 );
and ( n2935 , n2157 , n2934 );
not ( n2936 , n2935 );
and ( n2937 , n1936 , n1964 );
not ( n2938 , n2937 );
and ( n2939 , n1922 , n2938 );
not ( n2940 , n2939 );
and ( n2941 , n2514 , n2937 );
not ( n2942 , n2941 );
and ( n2943 , n2940 , n2942 );
not ( n2944 , n2943 );
and ( n2945 , n1246 , n2890 );
and ( n2946 , n2944 , n2945 );
not ( n2947 , n2946 );
xor ( n2948 , n2154 , n2633 );
and ( n2949 , n2948 , n2613 );
not ( n2950 , n2949 );
and ( n2951 , n1213 , n2890 );
and ( n2952 , n2514 , n2951 );
not ( n2953 , n2952 );
and ( n2954 , n2950 , n2953 );
and ( n2955 , n2936 , n2947 , n2954 );
and ( n2956 , n1484 , n2890 );
and ( n2957 , n2682 , n2687 );
not ( n2958 , n2684 );
and ( n2959 , n2707 , n2739 );
not ( n2960 , n2959 );
and ( n2961 , n2958 , n2960 );
and ( n2962 , n2957 , n2961 );
not ( n2963 , n2962 );
not ( n2964 , n2957 );
not ( n2965 , n2961 );
and ( n2966 , n2964 , n2965 );
not ( n2967 , n2966 );
and ( n2968 , n2963 , n2967 );
not ( n2969 , n2968 );
and ( n2970 , n2956 , n2969 );
not ( n2971 , n2970 );
and ( n2972 , n2955 , n2971 );
and ( n2973 , n2900 , n2922 , n2972 );
not ( n2974 , n2973 );
buf ( n2975 , n2974 );
buf ( n2976 , n2975 );
not ( n2977 , n2504 );
and ( n2978 , n2511 , n2977 );
and ( n2979 , n2545 , n2581 );
not ( n2980 , n2979 );
and ( n2981 , n2533 , n2980 );
xor ( n2982 , n2978 , n2981 );
not ( n2983 , n2982 );
and ( n2984 , n2891 , n2983 );
not ( n2985 , n2984 );
and ( n2986 , n2141 , n2934 );
not ( n2987 , n2986 );
and ( n2988 , n1937 , n1964 );
not ( n2989 , n2988 );
and ( n2990 , n1951 , n2989 );
not ( n2991 , n2990 );
and ( n2992 , n2500 , n2988 );
not ( n2993 , n2992 );
and ( n2994 , n2991 , n2993 );
not ( n2995 , n2994 );
and ( n2996 , n2995 , n2945 );
not ( n2997 , n2996 );
xor ( n2998 , n2134 , n2634 );
and ( n2999 , n2998 , n2613 );
not ( n3000 , n2999 );
and ( n3001 , n2500 , n2951 );
not ( n3002 , n3001 );
and ( n3003 , n3000 , n3002 );
and ( n3004 , n2987 , n2997 , n3003 );
not ( n3005 , n2696 );
and ( n3006 , n3005 , n2678 );
and ( n3007 , n2708 , n2739 );
not ( n3008 , n3007 );
and ( n3009 , n2690 , n3008 );
and ( n3010 , n3006 , n3009 );
not ( n3011 , n3010 );
not ( n3012 , n3006 );
not ( n3013 , n3009 );
and ( n3014 , n3012 , n3013 );
not ( n3015 , n3014 );
and ( n3016 , n3011 , n3015 );
not ( n3017 , n3016 );
and ( n3018 , n2956 , n3017 );
not ( n3019 , n3018 );
and ( n3020 , n3004 , n3019 );
and ( n3021 , n2985 , n3020 );
and ( n3022 , n811 , n2269 );
not ( n3023 , n3022 );
and ( n3024 , n2262 , n2909 );
not ( n3025 , n3024 );
and ( n3026 , n2264 , n3025 );
not ( n3027 , n3026 );
and ( n3028 , n2263 , n3024 );
not ( n3029 , n3028 );
and ( n3030 , n3027 , n3029 );
not ( n3031 , n3030 );
and ( n3032 , n810 , n3031 );
not ( n3033 , n3032 );
and ( n3034 , n3023 , n3033 );
not ( n3035 , n3034 );
and ( n3036 , n2902 , n3035 );
not ( n3037 , n3036 );
and ( n3038 , n3021 , n3037 );
not ( n3039 , n3038 );
buf ( n3040 , n3039 );
buf ( n3041 , n3040 );
and ( n3042 , n2594 , n946 );
not ( n3043 , n3042 );
and ( n3044 , n1465 , n1405 );
not ( n3045 , n3044 );
and ( n3046 , n1436 , n3045 );
not ( n3047 , n3046 );
and ( n3048 , n1614 , n3044 );
not ( n3049 , n3048 );
and ( n3050 , n3047 , n3049 );
not ( n3051 , n3050 );
and ( n3052 , n3051 , n2598 );
not ( n3053 , n3052 );
and ( n3054 , n3043 , n3053 );
and ( n3055 , n1614 , n2618 );
not ( n3056 , n3055 );
and ( n3057 , n3054 , n3056 );
xor ( n3058 , n946 , n2621 );
and ( n3059 , n3058 , n2648 );
not ( n3060 , n3059 );
and ( n3061 , n1639 , n1642 );
not ( n3062 , n1654 );
and ( n3063 , n1663 , n1693 );
not ( n3064 , n3063 );
and ( n3065 , n3062 , n3064 );
and ( n3066 , n3061 , n3065 );
not ( n3067 , n3066 );
not ( n3068 , n3061 );
not ( n3069 , n3065 );
and ( n3070 , n3068 , n3069 );
not ( n3071 , n3070 );
and ( n3072 , n3067 , n3071 );
not ( n3073 , n3072 );
and ( n3074 , n2641 , n3073 );
not ( n3075 , n3074 );
and ( n3076 , n1790 , n1788 );
not ( n3077 , n1795 );
and ( n3078 , n1804 , n1835 );
not ( n3079 , n3078 );
and ( n3080 , n3077 , n3079 );
and ( n3081 , n3076 , n3080 );
not ( n3082 , n3081 );
not ( n3083 , n3076 );
not ( n3084 , n3080 );
and ( n3085 , n3083 , n3084 );
not ( n3086 , n3085 );
and ( n3087 , n3082 , n3086 );
not ( n3088 , n3087 );
and ( n3089 , n2455 , n3088 );
not ( n3090 , n3089 );
and ( n3091 , n3057 , n3060 , n3075 , n3090 );
and ( n3092 , n811 , n1144 );
not ( n3093 , n3092 );
and ( n3094 , n1158 , n2347 );
and ( n3095 , n1152 , n3094 );
not ( n3096 , n3095 );
not ( n3097 , n3094 );
and ( n3098 , n1153 , n3097 );
not ( n3099 , n3098 );
and ( n3100 , n3096 , n3099 );
not ( n3101 , n3100 );
and ( n3102 , n810 , n3101 );
not ( n3103 , n3102 );
and ( n3104 , n3093 , n3103 );
not ( n3105 , n3104 );
and ( n3106 , n2432 , n3105 );
not ( n3107 , n3106 );
and ( n3108 , n3091 , n3107 );
not ( n3109 , n3108 );
buf ( n3110 , n3109 );
buf ( n3111 , n3110 );
and ( n3112 , n2017 , n795 );
not ( n3113 , n3112 );
and ( n3114 , n811 , n2224 );
not ( n3115 , n3114 );
not ( n3116 , n2290 );
not ( n3117 , n2215 );
and ( n3118 , n1084 , n2228 , n2762 );
not ( n3119 , n3118 );
and ( n3120 , n3117 , n3119 );
not ( n3121 , n3120 );
and ( n3122 , n3116 , n3121 );
and ( n3123 , n810 , n3122 );
not ( n3124 , n3123 );
and ( n3125 , n3115 , n3124 );
not ( n3126 , n3125 );
and ( n3127 , n702 , n3126 );
not ( n3128 , n3127 );
and ( n3129 , n1887 , n1213 );
not ( n3130 , n3129 );
and ( n3131 , n1885 , n1937 , n1908 , n1958 );
and ( n3132 , n3131 , n1964 );
not ( n3133 , n3132 );
and ( n3134 , n1888 , n3133 );
not ( n3135 , n3134 );
and ( n3136 , n1887 , n3132 );
not ( n3137 , n3136 );
and ( n3138 , n3135 , n3137 );
not ( n3139 , n3138 );
and ( n3140 , n1246 , n3139 );
not ( n3141 , n3140 );
and ( n3142 , n3130 , n3141 );
and ( n3143 , n1880 , n2081 );
and ( n3144 , n1887 , n2032 );
not ( n3145 , n3144 );
and ( n3146 , n1888 , n2031 );
not ( n3147 , n3146 );
and ( n3148 , n3145 , n3147 );
and ( n3149 , n3143 , n3148 );
not ( n3150 , n3149 );
not ( n3151 , n3143 );
not ( n3152 , n3148 );
and ( n3153 , n3151 , n3152 );
not ( n3154 , n3153 );
and ( n3155 , n3150 , n3154 );
xor ( n3156 , n1880 , n2080 );
not ( n3157 , n3156 );
and ( n3158 , n2779 , n3157 );
not ( n3159 , n3158 );
and ( n3160 , n2780 , n3156 );
not ( n3161 , n3160 );
and ( n3162 , n3161 , n2840 );
not ( n3163 , n3162 );
and ( n3164 , n3159 , n3163 );
and ( n3165 , n3161 , n2839 );
and ( n3166 , n3165 , n2863 );
not ( n3167 , n3166 );
and ( n3168 , n3164 , n3167 );
and ( n3169 , n3165 , n2866 );
and ( n3170 , n3169 , n2739 );
not ( n3171 , n3170 );
and ( n3172 , n3168 , n3171 );
not ( n3173 , n3172 );
and ( n3174 , n3155 , n3173 );
not ( n3175 , n3174 );
not ( n3176 , n3155 );
and ( n3177 , n3176 , n3172 );
not ( n3178 , n3177 );
and ( n3179 , n3175 , n3178 );
and ( n3180 , n1484 , n3179 );
not ( n3181 , n3180 );
and ( n3182 , n3142 , n3181 );
and ( n3183 , n1881 , n2081 );
not ( n3184 , n3183 );
xor ( n3185 , n3184 , n3148 );
and ( n3186 , n2778 , n2783 );
not ( n3187 , n3186 );
and ( n3188 , n1884 , n2065 );
not ( n3189 , n3188 );
and ( n3190 , n3189 , n3157 );
not ( n3191 , n3190 );
and ( n3192 , n3187 , n3191 );
and ( n3193 , n3192 , n2811 );
and ( n3194 , n3193 , n2581 );
not ( n3195 , n3194 );
and ( n3196 , n3188 , n3156 );
not ( n3197 , n3196 );
and ( n3198 , n2777 , n2837 );
and ( n3199 , n3198 , n3191 );
not ( n3200 , n3199 );
and ( n3201 , n3197 , n3200 );
not ( n3202 , n2810 );
and ( n3203 , n3192 , n3202 );
not ( n3204 , n3203 );
and ( n3205 , n3201 , n3204 );
and ( n3206 , n3195 , n3205 );
not ( n3207 , n3206 );
and ( n3208 , n3185 , n3207 );
not ( n3209 , n3208 );
not ( n3210 , n3185 );
and ( n3211 , n3210 , n3206 );
not ( n3212 , n3211 );
and ( n3213 , n3209 , n3212 );
and ( n3214 , n1715 , n3213 );
not ( n3215 , n3214 );
and ( n3216 , n3182 , n3215 );
and ( n3217 , n3128 , n3216 );
not ( n3218 , n3217 );
and ( n3219 , n794 , n3218 );
not ( n3220 , n3219 );
and ( n3221 , n3113 , n3220 );
not ( n3222 , n3221 );
buf ( n3223 , n3222 );
buf ( n3224 , n3223 );
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_txcounters.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_txcounters.v,v $
// Revision 1.6 2005/02/21 11:25:27 igorm
// Delayed CRC fixed.
//
// Revision 1.5 2002/04/22 14:54:14 mohor
// FCS should not be included in NibbleMinFl.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.4 2001/06/27 21:27:45 mohor
// Few typos fixed.
//
// Revision 1.2 2001/06/19 10:38:07 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:57 mohor
// TxEthMAC initial release.
//
//
//
`include "timescale.v"
module eth_txcounters (StatePreamble, StateIPG, StateData, StatePAD, StateFCS, StateJam,
StateBackOff, StateDefer, StateIdle, StartDefer, StartIPG, StartFCS,
StartJam, StartBackoff, TxStartFrm, MTxClk, Reset, MinFL, MaxFL, HugEn,
ExDfrEn, PacketFinished_q, DlyCrcEn, StateSFD, ByteCnt, NibCnt,
ExcessiveDefer, NibCntEq7, NibCntEq15, MaxFrame, NibbleMinFl, DlyCrcCnt
);
parameter Tp = 1;
input MTxClk; // Tx clock
input Reset; // Reset
input StatePreamble; // Preamble state
input StateIPG; // IPG state
input [1:0] StateData; // Data state
input StatePAD; // PAD state
input StateFCS; // FCS state
input StateJam; // Jam state
input StateBackOff; // Backoff state
input StateDefer; // Defer state
input StateIdle; // Idle state
input StateSFD; // SFD state
input StartDefer; // Defer state will be activated in next clock
input StartIPG; // IPG state will be activated in next clock
input StartFCS; // FCS state will be activated in next clock
input StartJam; // Jam state will be activated in next clock
input StartBackoff; // Backoff state will be activated in next clock
input TxStartFrm; // Tx start frame
input [15:0] MinFL; // Minimum frame length (in bytes)
input [15:0] MaxFL; // Miximum frame length (in bytes)
input HugEn; // Pakets bigger then MaxFL enabled
input ExDfrEn; // Excessive deferral enabled
input PacketFinished_q;
input DlyCrcEn; // Delayed CRC enabled
output [15:0] ByteCnt; // Byte counter
output [15:0] NibCnt; // Nibble counter
output ExcessiveDefer; // Excessive Deferral occuring
output NibCntEq7; // Nibble counter is equal to 7
output NibCntEq15; // Nibble counter is equal to 15
output MaxFrame; // Maximum frame occured
output NibbleMinFl; // Nibble counter is greater than the minimum frame length
output [2:0] DlyCrcCnt; // Delayed CRC Count
wire ExcessiveDeferCnt;
wire ResetNibCnt;
wire IncrementNibCnt;
wire ResetByteCnt;
wire IncrementByteCnt;
wire ByteCntMax;
reg [15:0] NibCnt;
reg [15:0] ByteCnt;
reg [2:0] DlyCrcCnt;
assign IncrementNibCnt = StateIPG | StatePreamble | (|StateData) | StatePAD
| StateFCS | StateJam | StateBackOff | StateDefer & ~ExcessiveDefer & TxStartFrm;
assign ResetNibCnt = StateDefer & ExcessiveDefer & ~TxStartFrm | StatePreamble & NibCntEq15
| StateJam & NibCntEq7 | StateIdle | StartDefer | StartIPG | StartFCS | StartJam;
// Nibble Counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
NibCnt <= #Tp 16'h0;
else
begin
if(ResetNibCnt)
NibCnt <= #Tp 16'h0;
else
if(IncrementNibCnt)
NibCnt <= #Tp NibCnt + 1'b1;
end
end
assign NibCntEq7 = &NibCnt[2:0];
assign NibCntEq15 = &NibCnt[3:0];
assign NibbleMinFl = NibCnt >= (((MinFL-3'h4)<<1) -1); // FCS should not be included in NibbleMinFl
assign ExcessiveDeferCnt = NibCnt[13:0] == 16'h17b7;
assign ExcessiveDefer = NibCnt[13:0] == 16'h17b7 & ~ExDfrEn; // 6071 nibbles
assign IncrementByteCnt = StateData[1] & ~ByteCntMax
| StateBackOff & (&NibCnt[6:0])
| (StatePAD | StateFCS) & NibCnt[0] & ~ByteCntMax;
assign ResetByteCnt = StartBackoff | StateIdle & TxStartFrm | PacketFinished_q;
// Transmit Byte Counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ByteCnt[15:0] <= #Tp 16'h0;
else
begin
if(ResetByteCnt)
ByteCnt[15:0] <= #Tp 16'h0;
else
if(IncrementByteCnt)
ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1;
end
end
assign MaxFrame = ByteCnt[15:0] == MaxFL[15:0] & ~HugEn;
assign ByteCntMax = &ByteCnt[15:0];
// Delayed CRC counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
DlyCrcCnt <= #Tp 3'h0;
else
begin
if(StateData[1] & DlyCrcCnt == 3'h4 | StartJam | PacketFinished_q)
DlyCrcCnt <= #Tp 3'h0;
else
if(DlyCrcEn & (StateSFD | StateData[1] & (|DlyCrcCnt[2:0])))
DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
end
end
endmodule
|
`timescale 1ns / 1ps
`include "Defintions.v"
`define LOOP1 8'd8
`define LOOP2 8'd5
module ROM
(
input wire[15:0] iAddress,
output reg [27:0] oInstruction
);
`define LABEL_LOOP 8'd2
`define LABEL_LOOP1 8'd9
`define LABEL_LOOP2 8'd16
`define LABEL_LOOP3 8'd23
`define LABEL_LOOP4 8'd30
`define LABEL_LOOP5 8'd37
`define LABEL_LOOP6 8'd44
`define LABEL_LOOP7 8'd51
`define LABEL_LOOP8 8'd58
`define LABEL_LOOP9 8'd65
`define LABEL_LOOP10 8'd72
`define LABEL_CONTINUE 8'd5
`define LABEL_CONTINUE1 8'd8
`define LABEL_CONTINUE2 8'd12
`define LABEL_CONTINUE3 8'd15
`define LABEL_CONTINUE4 8'd19
`define LABEL_CONTINUE5 8'd22
`define LABEL_CONTINUE6 8'd26
`define LABEL_CONTINUE7 8'd29
`define LABEL_CONTINUE8 8'd33
`define LABEL_CONTINUE9 8'd36
`define LABEL_CONTINUE10 8'd40
`define LABEL_CONTINUE11 8'd43
`define LABEL_CONTINUE12 8'd47
`define LABEL_CONTINUE13 8'd50
`define LABEL_CONTINUE14 8'd54
`define LABEL_CONTINUE15 8'd57
`define LABEL_CONTINUE16 8'd61
`define LABEL_CONTINUE17 8'd64
`define LABEL_CONTINUE18 8'd68
`define LABEL_CONTINUE19 8'd71
`define LABEL_CONTINUE20 8'd75
`define LABEL_CONTINUE21 8'd78
always @ ( iAddress )
begin
case (iAddress)
0: oInstruction = { `NOP ,24'd4000 };
1: oInstruction = { `STO , `R1,16'd72 };//carga H
//LABEL_LOOP:
2: oInstruction = { `LCD , 8'd0, `R1 , 8'd0 };
3: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE ,16'd0 };
4: oInstruction = { `JMP , `LABEL_LOOP ,16'd0 };
//LABEL_CONTINUE
5: oInstruction = { `SLH , 8'd0, `R1 , 8'd0 };
6: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE1 ,16'd0 };
7: oInstruction = { `JMP , `LABEL_CONTINUE ,16'd0 };
//`LABEL_CONTINUE1
8: oInstruction = { `STO , `R1,16'd101 };//carga E
//LABEL_LOOP1:
9: oInstruction = { `LCD , 8'd0, `R1 , 8'd0 };
10: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE2 ,16'd0 };
11: oInstruction = { `JMP , `LABEL_LOOP1 ,16'd0 };
//`LABEL_CONTINUE2
12: oInstruction = { `SLH , 8'd0, `R1 , 8'd0 };
13: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE3 ,16'd0 };
14:oInstruction = { `JMP , `LABEL_CONTINUE2 ,16'd0 };
//`LABEL_CONTINUE3
15: oInstruction = { `STO , `R1,16'd108 };//carga L
//LABEL_LOOP2:
16: oInstruction = { `LCD , 8'd0, `R1 , 8'd0 };
17: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE4 ,16'd0 };
18: oInstruction = { `JMP , `LABEL_LOOP2 ,16'd0 };
//`LABEL_CONTINUE4
19: oInstruction = { `SLH , 8'd0, `R1 , 8'd0 };
20: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE5 ,16'd0 };
21: oInstruction = { `JMP , `LABEL_CONTINUE4 ,16'd0 };
//`LABEL_CONTINUE5
22: oInstruction = { `STO , `R1,16'd108 };//carga L
//LABEL_LOOP3:
23: oInstruction = { `LCD , 8'd0, `R1 , 8'd0 };
24: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE6 ,16'd0 };
25: oInstruction = { `JMP , `LABEL_LOOP3 ,16'd0 };
//`LABEL_CONTINUE6
26: oInstruction = { `SLH , 8'd0, `R1 , 8'd0 };
27: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE7 ,16'd0 };
28: oInstruction = { `JMP , `LABEL_CONTINUE6 ,16'd0 };
//`LABEL_CONTINUE7
29: oInstruction = { `STO , `R1,16'd111 };//carga O
//LABEL_LOOP4:
30: oInstruction = { `LCD , 8'd0, `R1 , 8'd0 };
31: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE8 ,16'd0 };
32: oInstruction = { `JMP , `LABEL_LOOP4 ,16'd0 };
//`LABEL_CONTINUE8
33: oInstruction = { `SLH , 8'd0, `R1 , 8'd0 };
34: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE9 ,16'd0 };
35: oInstruction = { `JMP , `LABEL_CONTINUE8 ,16'd0 };
//`LABEL_CONTINUE9
36: oInstruction = { `STO , `R1,16'd32 };//carga space
//LABEL_LOOP5:
37: oInstruction = { `LCD , 8'd0, `R1 , 8'd0 };
38: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE10 ,16'd0 };
39: oInstruction = { `JMP , `LABEL_LOOP5 ,16'd0 };
//`LABEL_CONTINUE10
40: oInstruction = { `SLH , 8'd0, `R1 , 8'd0 };
41: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE11 ,16'd0 };
42: oInstruction = { `JMP , `LABEL_CONTINUE10 ,16'd0 };
//`LABEL_CONTINUE11
43: oInstruction = { `STO , `R1,16'd119 };//carga W
//LABEL_LOOP6:
44: oInstruction = { `LCD , 8'd0, `R1 , 8'd0 };
45: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE12 ,16'd0 };
46: oInstruction = { `JMP , `LABEL_LOOP6 ,16'd0 };
//`LABEL_CONTINUE12
47: oInstruction = { `SLH , 8'd0, `R1 , 8'd0 };
48: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE13 ,16'd0 };
49: oInstruction = { `JMP , `LABEL_CONTINUE12 ,16'd0 };
//`LABEL_CONTINUE13
50: oInstruction = { `STO , `R1,16'd111 };//carga O
//LABEL_LOOP7:
51: oInstruction = { `LCD , 8'd0, `R1 , 8'd0 };
52: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE14 ,16'd0 };
53: oInstruction = { `JMP , `LABEL_LOOP7 ,16'd0 };
//`LABEL_CONTINUE14
54: oInstruction = { `SLH , 8'd0, `R1 , 8'd0 };
55: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE15 ,16'd0 };
56: oInstruction = { `JMP , `LABEL_CONTINUE14 ,16'd0 };
//`LABEL_CONTINUE15
57: oInstruction = { `STO , `R1,16'd111 };//carga R
//LABEL_LOOP8:
58: oInstruction = { `LCD , 8'd0, `R1 , 8'd0 };
59: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE16 ,16'd0 };
60: oInstruction = { `JMP , `LABEL_LOOP8 ,16'd0 };
//`LABEL_CONTINUE16
61: oInstruction = { `SLH , 8'd0, `R1 , 8'd0 };
62: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE17 ,16'd0 };
63: oInstruction = { `JMP , `LABEL_CONTINUE16 ,16'd0 };
//`LABEL_CONTINUE17
64: oInstruction = { `STO , `R1,16'd108 };//carga L
//LABEL_LOOP9:
65: oInstruction = { `LCD , 8'd0, `R1 , 8'd0 };
66: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE18 ,16'd0 };
67: oInstruction = { `JMP , `LABEL_LOOP9 ,16'd0 };
//`LABEL_CONTINUE18
68: oInstruction = { `SLH , 8'd0, `R1 , 8'd0 };
69: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE19 ,16'd0 };
70: oInstruction = { `JMP , `LABEL_CONTINUE18 ,16'd0 };
//`LABEL_CONTINUE19
71: oInstruction = { `STO , `R1,16'd100 };//carga D
//LABEL_LOOP10:
72: oInstruction = { `LCD , 8'd0, `R1 , 8'd0 };
73: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE20 ,16'd0 };
74: oInstruction = { `JMP , `LABEL_LOOP10 ,16'd0 };
//`LABEL_CONTINUE20
75: oInstruction = { `SLH , 8'd0, `R1 , 8'd0 };
76: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE21 ,16'd0 };
77: oInstruction = { `JMP , `LABEL_CONTINUE20 ,16'd0 };
//`LABEL_CONTINUE21
78: oInstruction = { `STO , `R1,16'd100 };
default:
oInstruction = { `LED , 24'b10101010 }; //NOP
endcase
end
endmodule
|
// lab3_hps_0_hps_io.v
// This file was auto-generated from altera_hps_io_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 13.1.1 166 at 2014.04.26.23:17:39
`timescale 1 ps / 1 ps
module lab3_hps_0_hps_io (
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_io_qspi_inst_IO0, // .hps_io_qspi_inst_IO0
inout wire hps_io_qspi_inst_IO1, // .hps_io_qspi_inst_IO1
inout wire hps_io_qspi_inst_IO2, // .hps_io_qspi_inst_IO2
inout wire hps_io_qspi_inst_IO3, // .hps_io_qspi_inst_IO3
output wire hps_io_qspi_inst_SS0, // .hps_io_qspi_inst_SS0
output wire hps_io_qspi_inst_CLK, // .hps_io_qspi_inst_CLK
inout wire hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_io_spim0_inst_CLK, // .hps_io_spim0_inst_CLK
output wire hps_io_spim0_inst_MOSI, // .hps_io_spim0_inst_MOSI
input wire hps_io_spim0_inst_MISO, // .hps_io_spim0_inst_MISO
output wire hps_io_spim0_inst_SS0, // .hps_io_spim0_inst_SS0
output wire hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_io_i2c1_inst_SCL // .hps_io_i2c1_inst_SCL
);
lab3_hps_0_hps_io_border border (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_qspi_inst_IO0 (hps_io_qspi_inst_IO0), // .hps_io_qspi_inst_IO0
.hps_io_qspi_inst_IO1 (hps_io_qspi_inst_IO1), // .hps_io_qspi_inst_IO1
.hps_io_qspi_inst_IO2 (hps_io_qspi_inst_IO2), // .hps_io_qspi_inst_IO2
.hps_io_qspi_inst_IO3 (hps_io_qspi_inst_IO3), // .hps_io_qspi_inst_IO3
.hps_io_qspi_inst_SS0 (hps_io_qspi_inst_SS0), // .hps_io_qspi_inst_SS0
.hps_io_qspi_inst_CLK (hps_io_qspi_inst_CLK), // .hps_io_qspi_inst_CLK
.hps_io_sdio_inst_CMD (hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim0_inst_CLK (hps_io_spim0_inst_CLK), // .hps_io_spim0_inst_CLK
.hps_io_spim0_inst_MOSI (hps_io_spim0_inst_MOSI), // .hps_io_spim0_inst_MOSI
.hps_io_spim0_inst_MISO (hps_io_spim0_inst_MISO), // .hps_io_spim0_inst_MISO
.hps_io_spim0_inst_SS0 (hps_io_spim0_inst_SS0), // .hps_io_spim0_inst_SS0
.hps_io_spim1_inst_CLK (hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c1_inst_SDA (hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_i2c1_inst_SCL) // .hps_io_i2c1_inst_SCL
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR3_PP_SYMBOL_V
`define SKY130_FD_SC_LS__NOR3_PP_SYMBOL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR3_PP_SYMBOL_V
|
//date:2016/3/11
//engineer:ZhaiShaoMin
//module name:inter registers between inst fetch stage and inst decode stage
module core_if_id(//input
clk,
rst,
// stall,
if_id_we,
if_flush,
pc_plus_4,
inst_word,
//used for update Branch predictor
pc,
pred_target,
delayed_PHT,
delayed_BHR,
btb_type,
btb_v,
//output
pc_plus_4_out,
inst_word_out,
pc_out,
pred_target_out,
delayed_PHT_out,
delayed_BHR_out,
btb_type_out,
btb_v_out
);
//input
input clk;
input rst;
input [31:0] pc_plus_4;
input [31:0] inst_word;
input [31:0] pc;
input [31:0] pred_target;
input [1:0] delayed_PHT;
input [2:0] delayed_BHR;
input [1:0] btb_type;
input btb_v;
//input stall;
input if_id_we;
input if_flush;
//output
output [31:0] pc_plus_4_out;
output [31:0] inst_word_out;
output [31:0] pc_out;
output [31:0] pred_target_out;
output [1:0] delayed_PHT_out;
output [2:0] delayed_BHR_out;
output [1:0] btb_type_out;
output btb_v_out;
//reg
reg [31:0] inst_word_out;
reg [31:0] pc_plus_4_out;
reg [31:0] pc_out;
reg [31:0] pred_target_out;
reg [1:0] delayed_PHT_out;
reg [2:0] delayed_BHR_out;
reg [1:0] btb_type_out;
reg btb_v_out;
always@(posedge clk)
begin
if(rst||if_flush)
begin
pc_plus_4_out<=32'h0000;
inst_word_out<=32'h0000;
pc_out<=32'h0000;
pred_target_out<=32'h0000;
delayed_PHT_out<=2'b00;
delayed_BHR_out<=3'b000;
btb_type_out<=2'b00;
btb_v_out<=1'b0;
end
else if(if_id_we)
begin
pc_plus_4_out<=pc_plus_4;
inst_word_out<=inst_word;
pc_out<=pc;
pred_target_out<=pred_target;
delayed_PHT_out<=delayed_PHT;
delayed_BHR_out<=delayed_BHR;
btb_type_out<=btb_type;
btb_v_out<=btb_v;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FA_FUNCTIONAL_V
`define SKY130_FD_SC_LS__FA_FUNCTIONAL_V
/**
* fa: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__fa (
COUT,
SUM ,
A ,
B ,
CIN
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire nor0_out ;
wire nor1_out ;
wire or1_out_COUT;
wire or2_out_SUM ;
// Name Output Other arguments
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT, and1_out, and0_out);
buf buf0 (COUT , or1_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out);
buf buf1 (SUM , or2_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FA_FUNCTIONAL_V |
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module ddr3_s4_uniphy_example_if0_p0_addr_cmd_datapath(
clk,
reset_n,
afi_address,
afi_bank,
afi_cs_n,
afi_cke,
afi_odt,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_rst_n,
phy_ddio_address,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_ddio_reset_n,
phy_ddio_odt
);
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter NUM_AC_FR_CYCLE_SHIFTS = "";
localparam RATE_MULT = 2;
input reset_n;
input clk;
input [AFI_ADDRESS_WIDTH-1:0] afi_address;
input [AFI_BANK_WIDTH-1:0] afi_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] afi_cke;
input [AFI_ODT_WIDTH-1:0] afi_odt;
input [AFI_CONTROL_WIDTH-1:0] afi_ras_n;
input [AFI_CONTROL_WIDTH-1:0] afi_cas_n;
input [AFI_CONTROL_WIDTH-1:0] afi_we_n;
input [AFI_CONTROL_WIDTH-1:0] afi_rst_n;
output [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
output [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
output [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
output [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
output [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
wire [AFI_ADDRESS_WIDTH-1:0] afi_address_r = afi_address;
wire [AFI_BANK_WIDTH-1:0] afi_bank_r = afi_bank;
wire [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n_r = afi_cs_n;
wire [AFI_CLK_EN_WIDTH-1:0] afi_cke_r = afi_cke;
wire [AFI_ODT_WIDTH-1:0] afi_odt_r = afi_odt;
wire [AFI_CONTROL_WIDTH-1:0] afi_ras_n_r = afi_ras_n;
wire [AFI_CONTROL_WIDTH-1:0] afi_cas_n_r = afi_cas_n;
wire [AFI_CONTROL_WIDTH-1:0] afi_we_n_r = afi_we_n;
wire [AFI_CONTROL_WIDTH-1:0] afi_rst_n_r = afi_rst_n;
wire [1:0] shift_fr_cycle =
(NUM_AC_FR_CYCLE_SHIFTS == 0) ? 2'b00 : (
(NUM_AC_FR_CYCLE_SHIFTS == 1) ? 2'b01 : (
(NUM_AC_FR_CYCLE_SHIFTS == 2) ? 2'b10 : (
2'b11 )));
ddr3_s4_uniphy_example_if0_p0_fr_cycle_shifter uaddr_cmd_shift_address(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_address_r),
.dataout (phy_ddio_address)
);
defparam uaddr_cmd_shift_address.DATA_WIDTH = MEM_ADDRESS_WIDTH;
defparam uaddr_cmd_shift_address.REG_POST_RESET_HIGH = "false";
ddr3_s4_uniphy_example_if0_p0_fr_cycle_shifter uaddr_cmd_shift_bank(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_bank_r),
.dataout (phy_ddio_bank)
);
defparam uaddr_cmd_shift_bank.DATA_WIDTH = MEM_BANK_WIDTH;
defparam uaddr_cmd_shift_bank.REG_POST_RESET_HIGH = "false";
ddr3_s4_uniphy_example_if0_p0_fr_cycle_shifter uaddr_cmd_shift_cke(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_cke_r),
.dataout (phy_ddio_cke)
);
defparam uaddr_cmd_shift_cke.DATA_WIDTH = MEM_CLK_EN_WIDTH;
defparam uaddr_cmd_shift_cke.REG_POST_RESET_HIGH = "false";
ddr3_s4_uniphy_example_if0_p0_fr_cycle_shifter uaddr_cmd_shift_cs_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_cs_n_r),
.dataout (phy_ddio_cs_n)
);
defparam uaddr_cmd_shift_cs_n.DATA_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_shift_cs_n.REG_POST_RESET_HIGH = "true";
ddr3_s4_uniphy_example_if0_p0_fr_cycle_shifter uaddr_cmd_shift_odt(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_odt_r),
.dataout (phy_ddio_odt)
);
defparam uaddr_cmd_shift_odt.DATA_WIDTH = MEM_ODT_WIDTH;
defparam uaddr_cmd_shift_odt.REG_POST_RESET_HIGH = "false";
ddr3_s4_uniphy_example_if0_p0_fr_cycle_shifter uaddr_cmd_shift_ras_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_ras_n_r),
.dataout (phy_ddio_ras_n)
);
defparam uaddr_cmd_shift_ras_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_ras_n.REG_POST_RESET_HIGH = "true";
ddr3_s4_uniphy_example_if0_p0_fr_cycle_shifter uaddr_cmd_shift_cas_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_cas_n_r),
.dataout (phy_ddio_cas_n)
);
defparam uaddr_cmd_shift_cas_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_cas_n.REG_POST_RESET_HIGH = "true";
ddr3_s4_uniphy_example_if0_p0_fr_cycle_shifter uaddr_cmd_shift_we_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_we_n_r),
.dataout (phy_ddio_we_n)
);
defparam uaddr_cmd_shift_we_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_we_n.REG_POST_RESET_HIGH = "true";
ddr3_s4_uniphy_example_if0_p0_fr_cycle_shifter uaddr_cmd_shift_rst_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_rst_n_r),
.dataout (phy_ddio_reset_n)
);
defparam uaddr_cmd_shift_rst_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_rst_n.REG_POST_RESET_HIGH = "true";
endmodule
|
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram (addr_rd, addr_rw, clock, data, wren, q, q_rw);
input clock;
input [13:0] addr_rw;
input [7:0] data;
input wren;
input [13:0] addr_rd;
output [7:0] q;
output [7:0] q_rw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q = sub_wire0[7:0];
wire [7:0] q_rw = sub_wire1[7:0];
altsyncram altsyncram_component (
.clock0 (clock),
.wren_a (1'b0),
.wren_b (wren),
.address_a (addr_rd),
.address_b (addr_rw),
.data_a (16'h0),
.data_b (data),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.init_file = "ram.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16384,
altsyncram_component.numwords_b = 16384,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_WITH_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_WITH_NBE_READ",
altsyncram_component.widthad_a = 14,
altsyncram_component.widthad_b = 14,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
/**
* Import the design modules for other design submodules
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
/*
`include "acs.v"
`include "bmu.v"
`include "pmsm.v"
`include "spd.v"
*/
// Design of the Viterbi decoder
module viterbi_decoder (d, cx, clk, reset);
// Output signals for the design module
// Decoded output signal from the Viterbi decoder
output d;
// Input signals for the design module
// Received encoded signal that may have corrupted bits
input [1:0] cx;
// Input clock signal for the Viterbi decoder
input clk;
// Reset signal for the Viterbi decoder
input reset;
// Declare "reg" signals... that will be assigned values
// reg d;
// Set of branch metric outputs from the BMU
// reg [1:0] brch_met0,brch_met1,brch_met2,brch_met3;
// reg [1:0] brch_met4,brch_met5,brch_met6,brch_met7;
// Outputs from the ACS units
// Decision bit output from the ACS units
// reg d0,d1,d2,d3;
// Output from the ACS that indicates the new path metric
// reg [3:0] n_pm0,n_pm1,n_pm2,n_pm3;
// Outputs from the PMSM units
// reg [3:0] p_m0, p_m1, p_m2, p_m3;
// Declare "wire" signals...
wire d;
// Set of branch metric outputs from the BMU
wire [1:0] brch_met0,brch_met1,brch_met2,brch_met3;
wire [1:0] brch_met4,brch_met5,brch_met6,brch_met7;
// Outputs from the ACS units
// Decision bit output from the ACS units
wire d0,d1,d2,d3;
// Output from the ACS that indicates the new path metric
wire [3:0] n_pm0,n_pm1,n_pm2,n_pm3;
// Outputs from the PMSM units
wire [3:0] p_m0, p_m1, p_m2, p_m3;
// Defining constants: parameter [name_of_constant] = value;
/*******************************************************
*
* Connecting the modules of the Viterbi decoder together
* That is, link the following modules together:
* # Branch Metric calculation Unit (BMU)
* # Add-Compare-Select unit (ACS)
* # Survivor Path Decoding Unit (SPDU)
* # Survivor Path Decoder (SPD)
* # Path Metric State Memory (PMSM)
*
* Note that the SPD module includes the demux (2-to-4
* DEMUX/demultiplexer) and selector.
*
* The selector chooses the smallest path metric to
* create the control signal to select the smallest path
*
* In addition, note that the SPD module includes 15 SPDU
* units.
*
*
*
* Basic architecture of the Viterbi decoder:
*
* (1) (4) (1) (1)
* BMU->ACS->PMSM->SPD
* v ^ V ^
* | | | |
* | ----- |
* | |
* ------------|
*
*******************************************************
*/
// =====================================================
/**
* Instantiate the BMU to receive inputs for the Viterbi
* decoder, and produce outputs for the ACS units
*
* There is only one BMU for the Viterbi decoder
*/
bmu brch_met (cx[0], cx[1],
brch_met0,brch_met1,brch_met2,brch_met3,
brch_met4,brch_met5,brch_met6,brch_met7);
// =====================================================
/**
* Instantiate the 4 ACS units to receive inputs from
* the BMU and the PMSM, and produce outputs for the SPD
* and the PMSM
*
* The assignment of branch and path metrics to each
* state is based on the Trellis diagrams for different
* inputs for the input code(s), cx or cin
*
* See the BMU module for the interconnections.
*/
// Instantiate the 1st ACS unit
add_compare_select acs0 (n_pm0, d0,
p_m0, brch_met0, p_m1, brch_met2);
// Instantiate the 2nd ACS unit
add_compare_select acs1 (n_pm1, d1,
p_m2, brch_met4, p_m3, brch_met6);
// Instantiate the 3rd ACS unit
add_compare_select acs2 (n_pm2, d2,
p_m0, brch_met1, p_m1, brch_met3);
// Instantiate the 4th ACS unit
add_compare_select acs3 (n_pm3, d3,
p_m2, brch_met5, p_m3, brch_met7);
// =====================================================
/**
* Instantiate the PMSM that contains a set of 4
* registers, and circuitry to normalize the path metrics
* by subtracting the smallest path metric from all of
* the path metrics
*
* There is only one PMSM for the Viterbi decoder
*/
pmsm path_metric_sm (n_pm0, n_pm1, n_pm2, n_pm3,
p_m0, p_m1, p_m2, p_m3, clk, reset);
// =====================================================
/**
* Instantiate the SPD that uses the current path metric
* and the decision bits to determine the optimal path
* for Viterbi decoding using dynamic programming
*
* There is only one SPD for the Viterbi decoder
*/
spd survivor_path_dec (d0, d1, d2, d3, p_m0, p_m1, p_m2, p_m3,
d, clk, reset);
endmodule
|
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