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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4BB_2_V
`define SKY130_FD_SC_HDLL__NOR4BB_2_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog wrapper for nor4bb with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4bb_2 (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4bb_2 (
Y ,
A ,
B ,
C_N,
D_N
);
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4BB_2_V
|
// Hazard checking unit
module hazard_unit
(
input wire[4:0] rs_ex_mem_hz_i,
input wire[4:0] rt_ex_mem_hz_i,
input wire[4:0] rd_mem_wb_hz_i,
input wire[4:0] rd_wb_ret_hz_i,
input wire mem_to_reg_ex_mem_hz_i,
input wire reg_wr_mem_wb_hz_i,
input wire reg_wr_wb_ret_hz_i,
input wire branch_taken_ex_mem_hz_i,
input wire jump_iss_ex_hz_i,
input wire brn_pred_ex_mem_hz_i,
output wire stall_fetch_hz_o,
output wire stall_iss_hz_o,
output wire flush_ex_hz_o,
output wire flush_iss_hz_o,
output wire[1:0] fwd_p1_ex_mem_hz_o,
output wire[1:0] fwd_p2_ex_mem_hz_o
);
wire stall_fetch_hz;
wire stall_iss_hz;
wire flush_ex_hz;
wire flush_iss_hz;
wire[1:0] fwd_p1_ex_mem_hz;
wire[1:0] fwd_p2_ex_mem_hz;
assign stall_fetch_hz_o = stall_fetch_hz;
assign stall_iss_hz_o = stall_iss_hz;
assign flush_ex_hz_o = flush_ex_hz;
assign flush_iss_hz_o = flush_iss_hz;
assign fwd_p1_ex_mem_hz_o = fwd_p1_ex_mem_hz;
assign fwd_p2_ex_mem_hz_o = fwd_p2_ex_mem_hz;
// Forward the data only when we are writing to a non-zero register
// in the WB/MEM stage and the same register is being read at the
// EX stage
assign fwd_p1_ex_mem_hz = (reg_wr_mem_wb_hz_i & |rd_mem_wb_hz_i &
(rd_mem_wb_hz_i == rs_ex_mem_hz_i)) ? 2'b10
: (reg_wr_wb_ret_hz_i & |rd_wb_ret_hz_i &
(rd_wb_ret_hz_i == rs_ex_mem_hz_i)) ? 2'b01
: 2'b00;
assign fwd_p2_ex_mem_hz = (reg_wr_mem_wb_hz_i & |rd_mem_wb_hz_i &
(rd_mem_wb_hz_i == rt_ex_mem_hz_i)) ? 2'b10
: (reg_wr_wb_ret_hz_i & |rd_wb_ret_hz_i &
(rd_wb_ret_hz_i == rt_ex_mem_hz_i)) ? 2'b01
: 2'b00;
// All forwarding paths have been implemented
// There is not need to stall either Fetch or
// the Issue stage of the pipelines
assign stall_fetch_hz = 1'b0;
assign stall_iss_hz = 1'b0;
// Branches would be resolved in the EXECUTE stage
// the following signals should be based on those values
// This is required to flush the value in the EX Pipe register
// to a NO-OP.
assign flush_ex_hz = branch_taken_ex_mem_hz_i & ~brn_pred_ex_mem_hz_i;
// Jumps would be resolved in the ISSUE (DECODE) stage
// the following signals should be based on those values
assign flush_iss_hz = (branch_taken_ex_mem_hz_i & ~brn_pred_ex_mem_hz_i) | jump_iss_ex_hz_i;
endmodule
|
// file: pll_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module pll_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [2:1] COUNT;
reg COUNTER_RESET = 0;
wire [2:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "wait lock";
#(PER1*50);
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
pll_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT));
// Freq Check
endmodule
|
// --------------------------------------------------------------------
// -- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
// -- --
// -- This file contains confidential and proprietary information --
// -- of Xilinx, Inc. and is protected under U.S. and --
// -- international copyright and other intellectual property --
// -- laws. --
// -- --
// -- DISCLAIMER --
// -- This disclaimer is not a license and does not grant any --
// -- rights to the materials distributed herewith. Except as --
// -- otherwise provided in a valid license issued to you by --
// -- Xilinx, and to the maximum extent permitted by applicable --
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
// -- (2) Xilinx shall not be liable (whether in contract or tort, --
// -- including negligence, or under any other theory of --
// -- liability) for any loss or damage of any kind or nature --
// -- related to, arising under or in connection with these --
// -- materials, including for any direct, or any indirect, --
// -- special, incidental, or consequential loss or damage --
// -- (including loss of data, profits, goodwill, or any type of --
// -- loss or damage suffered as a result of any action brought --
// -- by a third party) even if such damage or loss was --
// -- reasonably foreseeable or Xilinx had been advised of the --
// -- possibility of the same. --
// -- --
// -- CRITICAL APPLICATIONS --
// -- Xilinx products are not designed or intended to be fail- --
// -- safe, or for use in any application requiring fail-safe --
// -- performance, such as life-support or safety devices or --
// -- systems, Class III medical devices, nuclear facilities, --
// -- applications related to the deployment of airbags, or any --
// -- other applications that could lead to death, personal --
// -- injury, or severe property or environmental damage --
// -- (individually and collectively, "Critical --
// -- Applications"). Customer assumes the sole risk and --
// -- liability of any use of Xilinx products in Critical --
// -- Applications, subject only to applicable laws and --
// -- regulations governing limitations on product liability. --
// -- --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
// -- PART OF THIS FILE AT ALL TIMES. --
// --------------------------------------------------------------------
//-----------------------------------------------------------------------------
// axi_tft_v2_0_v_sync.v
//-----------------------------------------------------------------------------
// Filename: axi_tft_v2_0_v_sync.v
// Version: v1.00a
// Description: This is the VSYNC signal generator. It generates
// the appropriate VSYNC signal for the target TFT display.
// The core of this module is a state machine that controls
// 4 counters and the VSYNC and V_DE signals.
//
//
// Verilog-Standard: Verilog'2001
//-----------------------------------------------------------------------------
// Structure:
// axi_tft.vhd
// -- axi_master_burst.vhd
// -- axi_lite_ipif.vhd
// -- tft_controller.v
// -- line_buffer.v
// -- v_sync.v
// -- h_sync.v
// -- slave_register.v
// -- tft_interface.v
// -- iic_init.v
//-----------------------------------------------------------------------------
// Author: PVK
// History:
// PVK 06/10/08 First Version
// ^^^^^^
//
// -- Input clock is (~HSYNC)
// -- Input Rst is vsync_rst signal generated from the h_sync.v module.
// -- V_DE and H_DE is used to generate DE signal for the TFT display.
// -- V_bp_cnt_tc and V_l_cnt_tc are the terminal count for the back
// -- porch time counter and Line time counter respectively and are
// -- used to generate get_line_start pulse.
// ~~~~~~~~
//-----------------------------------------------------------------------------
// Naming Conventions:
// active low signals: "*_n"
// clock signals: "clk", "clk_div#", "clk_#x"
// reset signals: "rst", "rst_n"
// parameters: "C_*"
// user defined types: "*_TYPE"
// state machine next state: "*_ns"
// state machine current state: "*_cs"
// combinatorial signals: "*_com"
// pipelined or register delay signals: "*_d#"
// counter signals: "*cnt*"
// clock enable signals: "*_ce"
// internal version of output port "*_i"
// device pins: "*_pin"
// ports: - Names begin with Uppercase
// component instantiations: "<MODULE>I_<#|FUNC>
//-----------------------------------------------------------------------------
///////////////////////////////////////////////////////////////////////////////
// Module Declaration
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_tft_v2_0_v_sync(
Clk, // Clock
Clk_stb, // Hsync clock strobe
Rst, // Reset
VSYNC, // Vertical Sync output
V_DE, // Vertical Data enable
V_bp_cnt_tc, // Vertical back porch terminal count pulse
V_p_cnt_tc, // Vertical pulse terminal count
V_l_cnt_tc); // Vertical line terminal count pulse
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input Clk;
input Clk_stb;
input Rst;
output VSYNC;
output V_DE;
output V_bp_cnt_tc;
output V_p_cnt_tc;
output V_l_cnt_tc;
///////////////////////////////////////////////////////////////////////////////
// Signal Declaration
///////////////////////////////////////////////////////////////////////////////
reg V_DE;
reg VSYNC;
reg [0:1] v_p_cnt; // 2-bit counter (2 HSYNCs for pulse time)
reg [0:4] v_bp_cnt; // 5-bit counter (31 HSYNCs for back porch time)
reg [0:8] v_l_cnt; // 9-bit counter (480 HSYNCs for line time)
reg [0:3] v_fp_cnt; // 4-bit counter (12 HSYNCs for front porch time)
reg v_p_cnt_clr;
reg v_bp_cnt_clr;
reg v_l_cnt_clr;
reg v_fp_cnt_clr;
reg V_p_cnt_tc;
reg V_bp_cnt_tc;
reg V_l_cnt_tc;
reg v_fp_cnt_tc;
///////////////////////////////////////////////////////////////////////////////
// VSYNC State Machine - State Declaration
///////////////////////////////////////////////////////////////////////////////
parameter [0:4] SET_COUNTERS = 5'b00001;
parameter [0:4] PULSE = 5'b00010;
parameter [0:4] BACK_PORCH = 5'b00100;
parameter [0:4] LINE = 5'b01000;
parameter [0:4] FRONT_PORCH = 5'b10000;
reg [0:4] VSYNC_cs;
reg [0:4] VSYNC_ns;
///////////////////////////////////////////////////////////////////////////////
// clock enable State Machine - Sequential Block
///////////////////////////////////////////////////////////////////////////////
reg clk_stb_d1;
reg clk_ce_neg;
reg clk_ce_pos;
// posedge and negedge of clock strobe
always @ (posedge Clk)
begin : CLOCK_STRB_GEN
clk_stb_d1 <= Clk_stb;
clk_ce_pos <= Clk_stb & ~clk_stb_d1;
clk_ce_neg <= ~Clk_stb & clk_stb_d1;
end
///////////////////////////////////////////////////////////////////////////////
// VSYNC State Machine - Sequential Block
///////////////////////////////////////////////////////////////////////////////
always @ (posedge Clk)
begin : VSYNC_REG_STATE
if (Rst)
VSYNC_cs <= SET_COUNTERS;
else if (clk_ce_pos)
VSYNC_cs <= VSYNC_ns;
end
///////////////////////////////////////////////////////////////////////////////
// VSYNC State Machine - Combinatorial Block
///////////////////////////////////////////////////////////////////////////////
always @ (VSYNC_cs or V_p_cnt_tc or V_bp_cnt_tc or V_l_cnt_tc or
v_fp_cnt_tc)
begin : VSYNC_SM_CMB
case (VSYNC_cs)
///////////////////////////////////////////////////////////////////
// SET COUNTERS STATE
// -- Clear and de-enable all counters on frame_start signal
///////////////////////////////////////////////////////////////////
SET_COUNTERS: begin
v_p_cnt_clr = 1;
v_bp_cnt_clr = 1;
v_l_cnt_clr = 1;
v_fp_cnt_clr = 1;
VSYNC = 1;
V_DE = 0;
VSYNC_ns = PULSE;
end
///////////////////////////////////////////////////////////////////
// PULSE STATE
// -- Enable pulse counter
// -- De-enable others
///////////////////////////////////////////////////////////////////
PULSE: begin
v_p_cnt_clr = 0;
v_bp_cnt_clr = 1;
v_l_cnt_clr = 1;
v_fp_cnt_clr = 1;
VSYNC = 0;
V_DE = 0;
if (V_p_cnt_tc == 0)
VSYNC_ns = PULSE;
else
VSYNC_ns = BACK_PORCH;
end
///////////////////////////////////////////////////////////////////
// BACK PORCH STATE
// -- Enable back porch counter
// -- De-enable others
///////////////////////////////////////////////////////////////////
BACK_PORCH: begin
v_p_cnt_clr = 1;
v_bp_cnt_clr = 0;
v_l_cnt_clr = 1;
v_fp_cnt_clr = 1;
VSYNC = 1;
V_DE = 0;
if (V_bp_cnt_tc == 0)
VSYNC_ns = BACK_PORCH;
else
VSYNC_ns = LINE;
end
///////////////////////////////////////////////////////////////////
// LINE STATE
// -- Enable line counter
// -- De-enable others
///////////////////////////////////////////////////////////////////
LINE: begin
v_p_cnt_clr = 1;
v_bp_cnt_clr = 1;
v_l_cnt_clr = 0;
v_fp_cnt_clr = 1;
VSYNC = 1;
V_DE = 1;
if (V_l_cnt_tc == 0)
VSYNC_ns = LINE;
else
VSYNC_ns = FRONT_PORCH;
end
///////////////////////////////////////////////////////////////////
// FRONT PORCH STATE
// -- Enable front porch counter
// -- De-enable others
// -- Wraps to PULSE state
///////////////////////////////////////////////////////////////////
FRONT_PORCH: begin
v_p_cnt_clr = 1;
v_bp_cnt_clr = 1;
v_l_cnt_clr = 1;
v_fp_cnt_clr = 0;
VSYNC = 1;
V_DE = 0;
if (v_fp_cnt_tc == 0)
VSYNC_ns = FRONT_PORCH;
else
VSYNC_ns = PULSE;
end
///////////////////////////////////////////////////////////////////
// DEFAULT STATE
///////////////////////////////////////////////////////////////////
// added coverage off to disable the coverage for default state
// as state machine will never enter in defualt state while doing
// verification.
// coverage off
default: begin
v_p_cnt_clr = 1;
v_bp_cnt_clr = 1;
v_l_cnt_clr = 1;
v_fp_cnt_clr = 0;
VSYNC = 1;
V_DE = 0;
VSYNC_ns = SET_COUNTERS;
end
// coverage on
endcase
end
///////////////////////////////////////////////////////////////////////////////
// Vertical Pulse Counter - Counts 2 clocks(~HSYNC) for pulse time
///////////////////////////////////////////////////////////////////////////////
always @(posedge Clk)
begin : VSYNC_PULSE_CNTR
if (Rst || v_p_cnt_clr )
begin
v_p_cnt <= 2'b0;
V_p_cnt_tc <= 0;
end
else if (clk_ce_neg)
begin
if (v_p_cnt == 1)
begin
v_p_cnt <= v_p_cnt + 1;
V_p_cnt_tc <= 1;
end
else
begin
v_p_cnt <= v_p_cnt + 1;
V_p_cnt_tc <= 0;
end
end
end
///////////////////////////////////////////////////////////////////////////////
// Vertical Back Porch Counter - Counts 31 clocks(~HSYNC) for pulse time
///////////////////////////////////////////////////////////////////////////////
always @(posedge Clk)
begin : VSYNC_BP_CNTR
if (Rst || v_bp_cnt_clr)
begin
v_bp_cnt <= 5'b0;
V_bp_cnt_tc <= 0;
end
else if (clk_ce_neg)
begin
if (v_bp_cnt == 30)
begin
v_bp_cnt <= v_bp_cnt + 1;
V_bp_cnt_tc <= 1;
end
else
begin
v_bp_cnt <= v_bp_cnt + 1;
V_bp_cnt_tc <= 0;
end
end
end
///////////////////////////////////////////////////////////////////////////////
// Vertical Line Counter - Counts 480 clocks(~HSYNC) for pulse time
///////////////////////////////////////////////////////////////////////////////
always @(posedge Clk)
begin : VSYNC_LINE_CNTR
if (Rst || v_l_cnt_clr)
begin
v_l_cnt <= 9'b0;
V_l_cnt_tc <= 0;
end
else if (clk_ce_neg)
begin
if (v_l_cnt == 479)
begin
v_l_cnt <= v_l_cnt + 1;
V_l_cnt_tc <= 1;
end
else
begin
v_l_cnt <= v_l_cnt + 1;
V_l_cnt_tc <= 0;
end
end
end
///////////////////////////////////////////////////////////////////////////////
// Vertical Front Porch Counter - Counts 12 clocks(~HSYNC) for pulse time
///////////////////////////////////////////////////////////////////////////////
always @(posedge Clk)
begin : VSYNC_FP_CNTR
if (Rst || v_fp_cnt_clr)
begin
v_fp_cnt <= 4'b0;
v_fp_cnt_tc <= 0;
end
else if (clk_ce_neg)
begin
if (v_fp_cnt == 11)
begin
v_fp_cnt <= v_fp_cnt + 1;
v_fp_cnt_tc <= 1;
end
else
begin
v_fp_cnt <= v_fp_cnt + 1;
v_fp_cnt_tc <= 0;
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:02:31 02/17/2016
// Design Name:
// Module Name: AR_RXD
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module AR_RXD_2(
input clk,
input wire in1, //Èìïóëüñû êàíàëà 1
input wire in0, //Èìïóëüñû êàíàëà 0
output [7:0] sr_adr,
output [22:0]sr_dat,
output wire ce_wr);
reg [31:0] tmp_buf = 32'd0;
reg [31:0] out_buf = 32'd0;
assign sr_adr = out_buf [31:24];
genvar i;
generate
for (i = 0; i <= 22 ; i = i + 1)
begin: data_loop
assign sr_dat[i] = out_buf [23 - i];
end
endgenerate
assign par_bit = out_buf [0];
reg [1:0] Nvel = 3;
parameter Fclk = 50000000 ; //50 MHz
parameter V1Mb = 1000000 ; // 1000 kb/s
parameter V100kb = 100000 ; // 100 kb/s
parameter V50kb = 50000 ; // 50 kb/s
parameter V12_5kb = 12500 ; // 12.5 kb/s
wire [10:0]AR_Nt = (Nvel [1:0] == 3)? (Fclk / (2 * V1Mb)) : //1000.000 kb/s
(Nvel [1:0] == 2)? (Fclk / (2 * V100kb)) : // 100.000 kb/s
(Nvel [1:0] == 1)? (Fclk / (2 * V50kb)) : // 50.000 kb/s
(Fclk / (2 * V12_5kb)); // 12.500 kb/s
reg [10:0] cb_tce = 0; // Ñ÷åò÷èê òàêòà
wire ce_tact = (cb_tce == AR_Nt); // Tce_tact=1/(2*VEL)
parameter WaitNextData = 0;
parameter RecData = 1;
parameter WaitPos = 2;
parameter WaitNeg = 3;
parameter Done = 4;
parameter Clear = 5;
reg [2:0] cur_state = WaitNextData;
reg clr_before_next = 0;
reg act_par_bit = 0;
reg ok_check = 0;
assign ce_wr = ok_check;
reg [5:0] rec_bit_num = 0;
parameter MaxTimeOut = 20;
reg [3:0] time_out = 0;
always @(posedge clk)
begin
if (cur_state == WaitNextData)
begin
cur_state <= (in1 | in0) ? Clear : WaitNextData;
clr_before_next <= 1;
cb_tce <= 0;
time_out <= 0;
end
else
begin
cb_tce <= (ce_tact) ? 1 : cb_tce + 1;
end
if (cur_state == WaitPos)
begin
time_out <= ce_tact ? time_out : time_out + 1;
cur_state <= (time_out > MaxTimeOut) ? Clear : (rec_bit_num == 32) ? Done : (in1 | in0) ? RecData : WaitPos;
end
else if (cur_state == RecData)
begin
tmp_buf <= in1 ? (tmp_buf << 1 | 1) : in0 ? (tmp_buf << 1) : tmp_buf;
act_par_bit <= act_par_bit ^ in1;
rec_bit_num <= rec_bit_num + 1;
time_out <= 0;
cur_state <= WaitNeg;
end
else if (cur_state == WaitNeg)
begin
cur_state <= (!in1 & !in0) ? WaitPos : WaitNeg;
end
else if (cur_state == Done)
begin
out_buf <= tmp_buf;
ok_check <= act_par_bit;
cur_state <= WaitNextData;
end
else if (cur_state == Clear)
begin
tmp_buf <= 0;
out_buf <= 0;
act_par_bit <= 0;
ok_check <= 0;
rec_bit_num <= 0;
time_out <= 0;
cur_state <= clr_before_next ? WaitPos : WaitNextData;
end
end
endmodule
|
`define DEBOUNCE_VALUE 16'hf00f
module edge_detector (
iCLK,
iRST_n,
iTrigger_in,
oFalling_edge,
oRising_edge,
oDebounce_out,
rst_cnt
);
input iCLK;
input iRST_n;
input iTrigger_in;
output oFalling_edge;
output oRising_edge;
output reg oDebounce_out;
reg [1:0] in_delay_reg;
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
begin
in_delay_reg <= 0;
end
else
begin
in_delay_reg <= {in_delay_reg[0],iTrigger_in};
end
end
assign oFalling_edge = (in_delay_reg == 2'b01) ? 1'b1 : 1'b0;
assign oRISING_edge = (in_delay_reg == 2'b10) ? 1'b1 : 1'b0;
output reg [15:0] rst_cnt;
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
begin
rst_cnt <= 0;
end
else if (rst_cnt == `DEBOUNCE_VALUE)
rst_cnt <= 0;
else if (cnt_enable)
begin
rst_cnt <= rst_cnt + 1;
end
end
reg cnt_enable;
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
begin
cnt_enable <= 1'b0;
end
else if (oFalling_edge)
begin
cnt_enable <= 1'b1;
end
else if (rst_cnt == `DEBOUNCE_VALUE)
begin
cnt_enable <= 1'b0;
end
end
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
begin
oDebounce_out <= 1'b0;
end
else if (oFalling_edge && ~cnt_enable)
begin
oDebounce_out <= 1'b1;
end
else
oDebounce_out <= 1'b0;
end
endmodule
|
/* lab4_part4.v - 50 Mhz Clock
*
* Copyright (c) 2014, Artem Tovbin <arty99 at gmail dot com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module lab4_part4 (CLOCK_50, HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0, LEDR, KEY);
input CLOCK_50;
input [3:0] KEY;
output [15:0] LEDR;
output [0:6] HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0;
wire [25:0] Q;
wire [15:0] Q2;
reg Clr, Clr2;
counter_26bit C0 (1, CLOCK_50, Clr, Q);
counter_16bit DISPLAY (1, Clr, Clr2, Q2);
always @ (negedge CLOCK_50) begin
if (Q >= 50000000) begin
Clr = 1;
end else begin
Clr = 0;
end
end
always @ (negedge Clr) begin
if (Q2 >= 9) begin
Clr2 = 1;
end else begin
Clr2 = 0;
end
end
t_flipflop T0 (1, Clr, 0, LEDR[4]);
b2d_ssd H0 (Q2[3:0], HEX0);
endmodule
module b2d_ssd (X, SSD);
input [3:0] X;
output reg [0:6] SSD;
always begin
case(X)
0:SSD=7'b0000001;
1:SSD=7'b1001111;
2:SSD=7'b0010010;
3:SSD=7'b0000110;
4:SSD=7'b1001100;
5:SSD=7'b0100100;
6:SSD=7'b0100000;
7:SSD=7'b0001111;
8:SSD=7'b0000000;
9:SSD=7'b0001100;
endcase
end
endmodule
module hex_ssd (BIN, SSD);
input [15:0] BIN;
output reg [0:6] SSD;
always begin
case(BIN)
0:SSD=7'b0000001;
1:SSD=7'b1001111;
2:SSD=7'b0010010;
3:SSD=7'b0000110;
4:SSD=7'b1001100;
5:SSD=7'b0100100;
6:SSD=7'b0100000;
7:SSD=7'b0001111;
8:SSD=7'b0000000;
9:SSD=7'b0001100;
10:SSD=7'b0001000;
11:SSD=7'b1100000;
12:SSD=7'b0110001;
13:SSD=7'b1000010;
14:SSD=7'b0110000;
15:SSD=7'b0111000;
endcase
end
endmodule
|
//-----------------------------------------------------------------
// RISC-V Top
// V0.6
// Ultra-Embedded.com
// Copyright 2014-2019
//
// [email protected]
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Generated File
//-----------------------------------------------------------------
module dcache_if_pmem
(
// Inputs
input clk_i
,input rst_i
,input [ 31:0] mem_addr_i
,input [ 31:0] mem_data_wr_i
,input mem_rd_i
,input [ 3:0] mem_wr_i
,input mem_cacheable_i
,input [ 10:0] mem_req_tag_i
,input mem_invalidate_i
,input mem_writeback_i
,input mem_flush_i
,input outport_accept_i
,input outport_ack_i
,input outport_error_i
,input [ 31:0] outport_read_data_i
// Outputs
,output [ 31:0] mem_data_rd_o
,output mem_accept_o
,output mem_ack_o
,output mem_error_o
,output [ 10:0] mem_resp_tag_o
,output [ 3:0] outport_wr_o
,output outport_rd_o
,output [ 7:0] outport_len_o
,output [ 31:0] outport_addr_o
,output [ 31:0] outport_write_data_o
);
//-------------------------------------------------------------
// Description:
// Bridges between dcache_if -> AXI4/AXI4-Lite.
// Allows 1 outstanding transaction, but can buffer upto
// REQUEST_BUFFER dcache_if requests before back-pressuring.
//-------------------------------------------------------------
//-------------------------------------------------------------
// Request FIFO
//-------------------------------------------------------------
// Accepts from both FIFOs
wire res_accept_w;
wire req_accept_w;
// Output accept
wire request_complete_w;
wire req_pop_w = request_complete_w;
wire req_valid_w;
wire [70-1:0] req_w;
// Cache requests are dropped
// NOTE: Should not actually end up here if configured correctly.
wire drop_req_w = mem_invalidate_i || mem_writeback_i || mem_flush_i;
wire request_w = drop_req_w || mem_rd_i || mem_wr_i != 4'b0;
// Push on transaction and other FIFO not full
wire req_push_w = request_w && res_accept_w;
dcache_if_pmem_fifo
#(
.WIDTH(32+32+4+1+1),
.DEPTH(2),
.ADDR_W(1)
)
u_req
(
.clk_i(clk_i),
.rst_i(rst_i),
// Input side
.data_in_i({drop_req_w, mem_rd_i, mem_wr_i, mem_data_wr_i, mem_addr_i}),
.push_i(req_push_w),
.accept_o(req_accept_w),
// Outputs
.valid_o(req_valid_w),
.data_out_o(req_w),
.pop_i(req_pop_w)
);
assign mem_accept_o = req_accept_w & res_accept_w;
//-------------------------------------------------------------
// Response Tracking FIFO
//-------------------------------------------------------------
// Push on transaction and other FIFO not full
wire res_push_w = request_w && req_accept_w;
dcache_if_pmem_fifo
#(
.WIDTH(11),
.DEPTH(2),
.ADDR_W(1)
)
u_resp
(
.clk_i(clk_i),
.rst_i(rst_i),
// Input side
.data_in_i(mem_req_tag_i),
.push_i(res_push_w),
.accept_o(res_accept_w),
// Outputs
.valid_o(), // UNUSED
.data_out_o(mem_resp_tag_o),
.pop_i(mem_ack_o)
);
//-------------------------------------------------------------
// Request
//-------------------------------------------------------------
reg request_pending_q;
wire request_in_progress_w = request_pending_q & !mem_ack_o;
wire req_is_read_w = ((req_valid_w & !request_in_progress_w) ? req_w[68] : 1'b0);
wire req_is_write_w = ((req_valid_w & !request_in_progress_w) ? ~req_w[68] : 1'b0);
wire req_is_drop_w = ((req_valid_w & !request_in_progress_w) ? req_w[69] : 1'b0);
assign outport_wr_o = req_is_write_w ? req_w[67:64] : 4'b0;
assign outport_rd_o = req_is_read_w;
assign outport_len_o = 8'd0;
assign outport_addr_o = {req_w[31:2], 2'b0};
assign outport_write_data_o = req_w[63:32];
assign request_complete_w = req_is_drop_w || ((outport_rd_o || outport_wr_o != 4'b0) && outport_accept_i);
// Outstanding Request Tracking
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
request_pending_q <= 1'b0;
else if (request_complete_w)
request_pending_q <= 1'b1;
else if (mem_ack_o)
request_pending_q <= 1'b0;
//-------------------------------------------------------------
// Response
//-------------------------------------------------------------
reg dropped_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
dropped_q <= 1'b0;
else if (req_is_drop_w)
dropped_q <= 1'b1;
else
dropped_q <= 1'b0;
assign mem_ack_o = dropped_q || outport_ack_i;
assign mem_data_rd_o = outport_read_data_i;
assign mem_error_o = outport_error_i;
endmodule
module dcache_if_pmem_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 4,
parameter ADDR_W = 2
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input [WIDTH-1:0] data_in_i
,input push_i
,input pop_i
// Outputs
,output [WIDTH-1:0] data_out_o
,output accept_o
,output valid_o
);
//-----------------------------------------------------------------
// Local Params
//-----------------------------------------------------------------
localparam COUNT_W = ADDR_W + 1;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [WIDTH-1:0] ram_q[DEPTH-1:0];
reg [ADDR_W-1:0] rd_ptr_q;
reg [ADDR_W-1:0] wr_ptr_q;
reg [COUNT_W-1:0] count_q;
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
count_q <= {(COUNT_W) {1'b0}};
rd_ptr_q <= {(ADDR_W) {1'b0}};
wr_ptr_q <= {(ADDR_W) {1'b0}};
end
else
begin
// Push
if (push_i & accept_o)
begin
ram_q[wr_ptr_q] <= data_in_i;
wr_ptr_q <= wr_ptr_q + 1;
end
// Pop
if (pop_i & valid_o)
rd_ptr_q <= rd_ptr_q + 1;
// Count up
if ((push_i & accept_o) & ~(pop_i & valid_o))
count_q <= count_q + 1;
// Count down
else if (~(push_i & accept_o) & (pop_i & valid_o))
count_q <= count_q - 1;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
/* verilator lint_off WIDTH */
assign valid_o = (count_q != 0);
assign accept_o = (count_q != DEPTH);
/* verilator lint_on WIDTH */
assign data_out_o = ram_q[rd_ptr_q];
endmodule
|
//`timescale 1ns
module tb_fir ();
initial begin
$read_lib_saif("../saif/NangateOpenCellLibrary.saif");
$set_gate_level_monitoring("on");
$set_toggle_region(UUT);
$toggle_start;
end
wire CLK_i;
wire RST_n_i;
wire [8:0] DIN_i;
wire VIN_i;
//wire [15:0] H0_i;
//wire [15:0] H1_i;
//wire [15:0] H2_i;
//wire [15:0] H3_i;
wire [80:0] coeffs_i;
wire [17:0] DOUT_i;
wire VOUT_i;
wire END_SIM_i;
clk_gen CG(.END_SIM(END_SIM_i),
.CLK(CLK_i),
.RST_n(RST_n_i));
data_maker SM(.CLK(CLK_i),
.RST_n(RST_n_i),
.VOUT(VIN_i),
.DOUT(DIN_i),
/* .H0(H0_i),
.H1(H1_i),
.H2(H2_i),
.H3(H3_i), */
.coeffs(coeffs_i),
.END_SIM(END_SIM_i));
FIR_filter UUT(.CLK(CLK_i),
.RST_n(RST_n_i),
.DIN(DIN_i),
.VIN(VIN_i),
/* .H0(H0_i),
.H1(H1_i),
.H2(H2_i),
.H3(H3_i), */
.Coeffs(coeffs_i),
.DOUT(DOUT_i),
.VOUT(VOUT_i));
data_sink DS(.CLK(CLK_i),
.RST_n(RST_n_i),
.VIN(VOUT_i),
.DIN(DOUT_i));
always @ ( END_SIM_i ) begin
if (END_SIM_i) begin
$toggle_stop;
$toggle_report("../saif/FIR_filter_back.saif", 1.0e-9, "tb_fir.UUT");
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
//
module some_module (
input [3:0] i_clks
);
logic [ 1 : 0 ] some_state;
logic [1:0] some_other_state;
logic the_clk;
assign the_clk = i_clks[3];
always @(posedge the_clk) begin
case (some_state)
2'b11:
if (some_other_state == 0)
some_state <= 2'b00;
default:
$display ("This is a display statement");
endcase
if (the_clk)
some_other_state <= 0;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
`define BROKEN
module t1(
input [3:0] i_clks,
input i_clk0,
input i_clk1
);
some_module
some_module
(
.i_clks (i_clks)
);
endmodule
module ident(
input i_ident,
output o_ident
);
assign o_ident = i_ident;
endmodule
module t2(
input [2:0] i_clks,
input i_clk0,
input i_clk1,
input i_clk2,
input i_data
);
logic [3:0] the_clks;
logic data_q;
logic ident_clk1;
always @(posedge i_clk0) begin
data_q <= i_data;
end
ident
ident
(
.i_ident (i_clk1),
.o_ident (ident_clk1)
);
t1 t1
(
.i_clks ({ident_clk1, i_clk2, ident_clk1, i_clk0}),
.i_clk0 (i_clk0),
.i_clk1 (i_clk1)
);
endmodule
module t(
/*AUTOARG*/
// Inputs
clk /*verilator clocker*/ /*verilator public_flat*/,
input clk0 /*verilator clocker*/,
input clk1 /*verilator clocker*/,
input clk2 /*verilator clocker*/,
input data_in
);
input clk;
logic [2:0] clks;
assign clks = {1'b0, clk1, clk0};
t2
t2
(
.i_clks (clks),
.i_clk0 (clk0),
.i_clk1 (clk),
.i_clk2 (clk2),
.i_data (data_in)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O211AI_SYMBOL_V
`define SKY130_FD_SC_HD__O211AI_SYMBOL_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o211ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O211AI_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND3_2_V
`define SKY130_FD_SC_LS__AND3_2_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND3_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_XRES4V2_SYMBOL_V
`define SKY130_FD_IO__TOP_XRES4V2_SYMBOL_V
/**
* top_xres4v2: XRES (Input buffer with Glitch filter).
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_xres4v2 (
//# {{data|Data Signals}}
input FILT_IN_H ,
input INP_SEL_H ,
inout PAD ,
inout PAD_A_ESD_H ,
//# {{control|Control Signals}}
inout AMUXBUS_A ,
inout AMUXBUS_B ,
input DISABLE_PULLUP_H,
input ENABLE_H ,
input ENABLE_VDDIO ,
input EN_VDDIO_SIG_H ,
output XRES_H_N ,
//# {{power|Power}}
inout PULLUP_H ,
output TIE_HI_ESD ,
inout TIE_WEAK_HI_H ,
output TIE_LO_ESD
);
// Voltage supply signals
supply1 VCCD ;
supply1 VCCHIB ;
supply1 VDDA ;
supply1 VDDIO ;
supply1 VDDIO_Q;
supply0 VSSA ;
supply0 VSSD ;
supply0 VSSIO ;
supply0 VSSIO_Q;
supply1 VSWITCH;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_XRES4V2_SYMBOL_V
|
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : rank_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level rank machine structural block. This block
// instantiates a configurable number of rank controller blocks.
`timescale 1ps/1ps
module rank_mach #
(
parameter BURST_MODE = "8",
parameter CS_WIDTH = 4,
parameter DRAM_TYPE = "DDR3",
parameter MAINT_PRESCALER_DIV = 40,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter CL = 5,
parameter nFAW = 30,
parameter nREFRESH_BANK = 8,
parameter nRRD = 4,
parameter nWTR = 4,
parameter PERIODIC_RD_TIMER_DIV = 20,
parameter RANK_BM_BV_WIDTH = 16,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter REFRESH_TIMER_DIV = 39,
parameter ZQ_TIMER_DIV = 640000
)
(/*AUTOARG*/
// Outputs
periodic_rd_rank_r, periodic_rd_r, maint_req_r, inhbt_act_faw_r,
inhbt_rd_r, wtr_inhbt_config_r, maint_rank_r, maint_zq_r,
// Inputs
wr_this_rank_r, slot_1_present, slot_0_present, sending_row,
sending_col, rst, rd_this_rank_r, rank_busy_r, periodic_rd_ack_r,
maint_wip_r, insert_maint_r1, init_calib_complete, clk, app_zq_req,
app_ref_req, app_periodic_rd_req, act_this_rank_r
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
input app_periodic_rd_req; // To rank_cntrl0 of rank_cntrl.v
input app_ref_req; // To rank_cntrl0 of rank_cntrl.v
input app_zq_req; // To rank_common0 of rank_common.v
input clk; // To rank_cntrl0 of rank_cntrl.v, ...
input init_calib_complete; // To rank_cntrl0 of rank_cntrl.v, ...
input insert_maint_r1; // To rank_cntrl0 of rank_cntrl.v, ...
input maint_wip_r; // To rank_common0 of rank_common.v
input periodic_rd_ack_r; // To rank_common0 of rank_common.v
input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r; // To rank_cntrl0 of rank_cntrl.v
input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
input rst; // To rank_cntrl0 of rank_cntrl.v, ...
input [nBANK_MACHS-1:0] sending_col; // To rank_cntrl0 of rank_cntrl.v
input [nBANK_MACHS-1:0] sending_row; // To rank_cntrl0 of rank_cntrl.v
input [7:0] slot_0_present; // To rank_common0 of rank_common.v
input [7:0] slot_1_present; // To rank_common0 of rank_common.v
input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output maint_req_r; // From rank_common0 of rank_common.v
output periodic_rd_r; // From rank_common0 of rank_common.v
output [RANK_WIDTH-1:0] periodic_rd_rank_r; // From rank_common0 of rank_common.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire maint_prescaler_tick_r; // From rank_common0 of rank_common.v
wire refresh_tick; // From rank_common0 of rank_common.v
// End of automatics
output [RANKS-1:0] inhbt_act_faw_r;
output [RANKS-1:0] inhbt_rd_r;
output [RANKS-1:0] wtr_inhbt_config_r;
output [RANK_WIDTH-1:0] maint_rank_r;
output maint_zq_r;
wire [RANKS-1:0] refresh_request;
wire [RANKS-1:0] periodic_rd_request;
wire [RANKS-1:0] clear_periodic_rd_request;
genvar ID;
generate
for (ID=0; ID<RANKS; ID=ID+1) begin:rank_cntrl
rank_cntrl#
(/*AUTOINSTPARAM*/
// Parameters
.BURST_MODE (BURST_MODE),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.CL (CL),
.nFAW (nFAW),
.nREFRESH_BANK (nREFRESH_BANK),
.nRRD (nRRD),
.nWTR (nWTR),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV))
rank_cntrl0
(.clear_periodic_rd_request (clear_periodic_rd_request[ID]),
.inhbt_act_faw_r (inhbt_act_faw_r[ID]),
.inhbt_rd_r (inhbt_rd_r[ID]),
.periodic_rd_request (periodic_rd_request[ID]),
.refresh_request (refresh_request[ID]),
.wtr_inhbt_config_r (wtr_inhbt_config_r[ID]),
/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.app_ref_req (app_ref_req),
.init_calib_complete (init_calib_complete),
.rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),
.refresh_tick (refresh_tick),
.insert_maint_r1 (insert_maint_r1),
.maint_zq_r (maint_zq_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.app_periodic_rd_req (app_periodic_rd_req),
.maint_prescaler_tick_r (maint_prescaler_tick_r),
.rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]));
end
endgenerate
rank_common#
(/*AUTOINSTPARAM*/
// Parameters
.DRAM_TYPE (DRAM_TYPE),
.MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV),
.nBANK_MACHS (nBANK_MACHS),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV),
.ZQ_TIMER_DIV (ZQ_TIMER_DIV))
rank_common0
(.clear_periodic_rd_request (clear_periodic_rd_request[RANKS-1:0]),
/*AUTOINST*/
// Outputs
.maint_prescaler_tick_r (maint_prescaler_tick_r),
.refresh_tick (refresh_tick),
.maint_zq_r (maint_zq_r),
.maint_req_r (maint_req_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.periodic_rd_r (periodic_rd_r),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.init_calib_complete (init_calib_complete),
.app_zq_req (app_zq_req),
.insert_maint_r1 (insert_maint_r1),
.refresh_request (refresh_request[RANKS-1:0]),
.maint_wip_r (maint_wip_r),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.periodic_rd_request (periodic_rd_request[RANKS-1:0]),
.periodic_rd_ack_r (periodic_rd_ack_r));
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: mcb_flow_control.v
// /___/ /\ Date Last Modified: $Date: 2009/11/03 04:41:58 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module is the main flow control between cmd_gen.v,
// write_data_path and read_data_path modules.
//Design Name: DDR/DDR2/DDR3/LPDDR
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mcb_flow_control #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6"
)
(
input clk_i,
input [9:0] rst_i,
// interface to cmd_gen, pipeline inserter
output reg cmd_rdy_o,
input cmd_valid_i,
input [2:0] cmd_i,
input [31:0] addr_i,
input [5:0] bl_i,
// interface to mcb_cmd port
input mcb_cmd_full,
output reg [2:0] cmd_o,
output reg [31:0] addr_o,
output reg [5:0] bl_o,
output cmd_en_o, // interface to write data path module
input last_word_wr_i,
input wdp_rdy_i,
output wdp_valid_o,
output wdp_validB_o,
output wdp_validC_o,
output [31:0] wr_addr_o,
output [5:0] wr_bl_o,
// interface to read data path module
input last_word_rd_i,
input rdp_rdy_i,
output rdp_valid_o,
output [31:0] rd_addr_o,
output [5:0] rd_bl_o
);
//FSM State Defination
localparam READY = 5'b00001,
READ = 5'b00010,
WRITE = 5'b00100,
CMD_WAIT = 5'b01000,
REFRESH_ST = 5'b10000;
localparam RD = 3'b001;
localparam RDP = 3'b011;
localparam WR = 3'b000;
localparam WRP = 3'b010;
localparam REFRESH = 3'b100;
localparam NOP = 3'b101; // this defination is local to this traffic gen and is not defined
reg cmd_fifo_rdy;
wire cmd_rd;
wire cmd_wr; // need equation
wire cmd_others;
reg push_cmd;
reg xfer_cmd;
reg rd_vld ;
reg wr_vld;
reg cmd_rdy;
reg [2:0] cmd_reg;
reg [31:0] addr_reg;
reg [5:0] bl_reg;
reg rdp_valid;
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg wdp_valid,wdp_validB,wdp_validC;
reg [4:0] current_state;
reg [4:0] next_state;
reg [3:0] tstpointA;
reg push_cmd_r;
reg wait_done;
reg cmd_en_r1 ;
reg wr_in_progress;
reg tst_cmd_rdy_o;
// mcb_command bus outputs
assign cmd_en_o = cmd_en_r1;
always @ (posedge clk_i) begin
cmd_rdy_o <= #TCQ cmd_rdy;
tst_cmd_rdy_o <= #TCQ cmd_rdy;
end
always @ (posedge clk_i)
begin
if (rst_i[8])
cmd_en_r1 <= #TCQ 1'b0;
else if ( xfer_cmd)
cmd_en_r1 <= #TCQ 1'b1;
else if (!mcb_cmd_full)
cmd_en_r1 <= #TCQ 1'b0;
end
always @ (posedge clk_i)
begin
if (rst_i[9])
cmd_fifo_rdy <= #TCQ 1'b1;
else if (xfer_cmd)
cmd_fifo_rdy <= #TCQ 1'b0;
else if (!mcb_cmd_full)
cmd_fifo_rdy <= #TCQ 1'b1;
end
always @ (posedge clk_i)
begin
if (rst_i[9]) begin
addr_o <= #TCQ 'b0;
cmd_o <= #TCQ 'b0;
bl_o <= #TCQ 'b0;
end
else if (xfer_cmd ) begin
addr_o <= #TCQ addr_reg;
if (FAMILY == "SPARTAN6")
cmd_o <= #TCQ cmd_reg;
else
cmd_o <= #TCQ {2'b00,cmd_reg[0]};
bl_o <= #TCQ bl_reg;
end
end
// go directly to wr_datapath and rd_datapath modules
assign wr_addr_o = addr_i;
assign rd_addr_o = addr_i;
assign rd_bl_o = bl_i ;
assign wr_bl_o = bl_i ;
assign wdp_valid_o = wdp_valid;
assign wdp_validB_o = wdp_validB;
assign wdp_validC_o = wdp_validC;
assign rdp_valid_o = rdp_valid;
// internal control siganls
always @ (posedge clk_i)
begin
if (rst_i[8])
wait_done <= #TCQ 1'b1;
else if (push_cmd_r)
wait_done <= #TCQ 1'b1;
else if (cmd_rdy_o && cmd_valid_i && FAMILY == "SPARTAN6")
wait_done <= #TCQ 1'b0;
end
//
always @ (posedge clk_i)
begin
push_cmd_r <= #TCQ push_cmd;
// push_cmd_r2 <= #TCQ push_cmd_r;
end
always @ (posedge clk_i)
if (push_cmd)
begin
cmd_reg <= #TCQ cmd_i;
addr_reg <= #TCQ addr_i;
bl_reg <= #TCQ bl_i - 1;
end
//--Command Decodes--
assign cmd_wr = ((cmd_i == WR | cmd_i == WRP) & cmd_valid_i ) ? 1'b1 : 1'b0;
assign cmd_rd = ((cmd_i == RD | cmd_i == RDP) & cmd_valid_i) ? 1'b1 : 1'b0;
assign cmd_others = ((cmd_i[2] == 1'b1)& cmd_valid_i && (FAMILY == "SPARTAN6")) ? 1'b1 : 1'b0;
reg cmd_wr_pending_r1;
reg cmd_rd_pending_r1;
always @ (posedge clk_i)
begin
if (rst_i[0])
cmd_wr_pending_r1 <= #TCQ 1'b0;
//else if (current_state == WRITE && last_word_wr_i && !cmd_fifo_rdy)
//else if ( last_word_wr_i && !cmd_fifo_rdy)
else if ( last_word_wr_i )
cmd_wr_pending_r1 <= #TCQ 1'b1;
else if (push_cmd)//xfer_cmd)
cmd_wr_pending_r1 <= #TCQ 1'b0;
end
// corner case if fixed read command with fixed bl 64
always @ (posedge clk_i)
begin
if (cmd_rd & push_cmd)
cmd_rd_pending_r1 <= #TCQ 1'b1;
else if (xfer_cmd)
cmd_rd_pending_r1 <= #TCQ 1'b0;
end
always @ (posedge clk_i)
begin
if (rst_i[0])
wr_in_progress <= #TCQ 1'b0;
else if (last_word_wr_i)
wr_in_progress <= #TCQ 1'b0;
else if (current_state == WRITE)
wr_in_progress <= #TCQ 1'b1;
end
always @ (posedge clk_i)
begin
if (rst_i[0])
current_state <= #TCQ 4'b0001;
else
current_state <= #TCQ next_state;
end
// mcb_flow_control statemachine
always @ (*)
begin
push_cmd = 1'b0;
xfer_cmd = 1'b0;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
rdp_valid = 1'b0;
cmd_rdy = 1'b0;
next_state = current_state;
case(current_state)
READY:
begin
if(rdp_rdy_i & cmd_rd & cmd_fifo_rdy) //rdp_rdy_i comes from read_data path
begin
next_state = READ;
push_cmd = 1'b1;
xfer_cmd = 1'b0;
rdp_valid = 1'b1;
end
else if (wdp_rdy_i & cmd_wr & cmd_fifo_rdy)
begin
next_state = WRITE;
push_cmd = 1'b1;
wdp_valid = 1'b1;
wdp_validB = 1'b1;
wdp_validC = 1'b1;
end
else if ( cmd_others & cmd_fifo_rdy)
begin
next_state = REFRESH_ST;
push_cmd = 1'b1;
xfer_cmd = 1'b0;
end
else
begin
next_state = READY;
push_cmd = 1'b0;
end
if (cmd_fifo_rdy)
cmd_rdy = 1'b1;
else
cmd_rdy = 1'b0;
end
REFRESH_ST : begin
if (rdp_rdy_i && cmd_rd && cmd_fifo_rdy )
begin
next_state = READ;
push_cmd = 1'b1;
rdp_valid = 1'b1;
wdp_valid = 1'b0;
xfer_cmd = 1'b1;
// tstpointA = 4'b0101;
end
else if (cmd_fifo_rdy && cmd_wr && wdp_rdy_i )
begin
next_state = WRITE;
push_cmd = 1'b1;
xfer_cmd = 1'b1;
wdp_valid = 1'b1;
wdp_validB = 1'b1;
wdp_validC = 1'b1;
// tstpointA = 4'b0110;
end
else if (cmd_fifo_rdy && cmd_others)
begin
push_cmd = 1'b1;
xfer_cmd = 1'b1;
end
else if (!cmd_fifo_rdy)
begin
next_state = CMD_WAIT;
tstpointA = 4'b1001;
end
else
next_state = READ;
if (cmd_fifo_rdy && ((rdp_rdy_i && cmd_rd) || (wdp_rdy_i && cmd_wr) || (cmd_others)))
cmd_rdy = 1'b1;
else
cmd_rdy = 1'b0;
end
READ: begin
if (rdp_rdy_i && cmd_rd && cmd_fifo_rdy )
begin
next_state = READ;
push_cmd = 1'b1;
rdp_valid = 1'b1;
wdp_valid = 1'b0;
xfer_cmd = 1'b1;
tstpointA = 4'b0101;
end
else if (cmd_fifo_rdy && cmd_wr && wdp_rdy_i )
begin
next_state = WRITE;
push_cmd = 1'b1;
xfer_cmd = 1'b1;
wdp_valid = 1'b1;
wdp_validB = 1'b1;
wdp_validC = 1'b1;
tstpointA = 4'b0110;
end
else if (!rdp_rdy_i )
begin
next_state = READ;
push_cmd = 1'b0;
xfer_cmd = 1'b0;
tstpointA = 4'b0111;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
rdp_valid = 1'b0;
end
else if (last_word_rd_i && cmd_others && cmd_fifo_rdy )
begin
next_state = REFRESH_ST;
push_cmd = 1'b1;
xfer_cmd = 1'b1;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
rdp_valid = 1'b0;
tstpointA = 4'b1000;
end
else if (!cmd_fifo_rdy || !wdp_rdy_i)
begin
next_state = CMD_WAIT;
tstpointA = 4'b1001;
end
else
next_state = READ;
if ((rdp_rdy_i && cmd_rd || cmd_wr && wdp_rdy_i || cmd_others) && cmd_fifo_rdy)
cmd_rdy = wait_done;//1'b1;
else
cmd_rdy = 1'b0;
end
WRITE: begin // for write, always wait until the last_word_wr
if (cmd_fifo_rdy && cmd_rd && rdp_rdy_i && last_word_wr_i)
begin
next_state = READ;
push_cmd = 1'b1;
xfer_cmd = 1'b1;
rdp_valid = 1'b1;
tstpointA = 4'b0000;
end
else if (!wdp_rdy_i || (wdp_rdy_i && cmd_wr && cmd_fifo_rdy && last_word_wr_i) )
begin
next_state = WRITE;
tstpointA = 4'b0001;
if (cmd_wr && last_word_wr_i) begin
wdp_valid = 1'b1;
wdp_validB = 1'b1;
wdp_validC = 1'b1;
end
else begin
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
end
if (last_word_wr_i ) begin
push_cmd = 1'b1;
xfer_cmd = 1'b1;
end
else begin
push_cmd = 1'b0;
xfer_cmd = 1'b0;
end
end
else if (last_word_wr_i && cmd_others && cmd_fifo_rdy)
begin
next_state = REFRESH_ST;
push_cmd = 1'b1;
xfer_cmd = 1'b1;
tstpointA = 4'b0010;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
rdp_valid = 1'b0;
end
else if (!cmd_fifo_rdy && last_word_wr_i || !rdp_rdy_i || (!cmd_valid_i && wait_done) )
begin
next_state = CMD_WAIT;
push_cmd = 1'b0;
xfer_cmd = 1'b0;
tstpointA = 4'b0011;
end
else begin
next_state = WRITE;
tstpointA = 4'b0100;
end
// need to include rdp_rdy_i to prevent sending read command if
// read_data_port fifo is full in MCB
if (last_word_wr_i && (cmd_others || rdp_rdy_i && cmd_rd || cmd_wr && wdp_rdy_i) && cmd_fifo_rdy)
cmd_rdy = wait_done;//1'b1;
else
cmd_rdy = 1'b0;
end
CMD_WAIT: if (!cmd_fifo_rdy || wr_in_progress)
begin
next_state = CMD_WAIT;
cmd_rdy = 1'b0;
tstpointA = 4'b1010;
end
else if (cmd_fifo_rdy && rdp_rdy_i && cmd_rd)
begin
next_state = READ;
push_cmd = 1'b1;
xfer_cmd = 1'b1;
cmd_rdy = 1'b1;
rdp_valid = 1'b1;
tstpointA = 4'b1011;
end
else if (cmd_fifo_rdy && cmd_wr && (wait_done || cmd_wr_pending_r1))
begin
next_state = WRITE;
push_cmd = 1'b1;
xfer_cmd = 1'b1;
wdp_valid = 1'b1;
wdp_validB = 1'b1;
wdp_validC = 1'b1;
cmd_rdy = 1'b1;
tstpointA = 4'b1100;
end
else if (cmd_fifo_rdy && cmd_others)
begin
next_state = REFRESH_ST;
push_cmd = 1'b1; /////////////////
xfer_cmd = 1'b1;
tstpointA = 4'b1101;
cmd_rdy = 1'b1;
end
else
begin
next_state = CMD_WAIT;
tstpointA = 4'b1110;
if ((wdp_rdy_i && rdp_rdy_i))
cmd_rdy = 1'b1;
else
cmd_rdy = 1'b0;
end
default:
begin
push_cmd = 1'b0;
xfer_cmd = 1'b0;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
next_state = READY;
// cmd_rdy = 1'b0;
end
endcase
end
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*
*
* @reminder December 1, 2007
* Remember to remove wrbyteen and ctrl_ppp from the inputs to
* the ALU and its testbench
*/
/**
* Reference:
* Nestoras Tzartzanis, EE 577B Verilog Example, Jan 25, 1996
* http://www-scf.usc.edu/~ee577/tutorial/verilog/alu.v
*/
/**
* Note that all instructions are 32-bits, and that Big-Endian
* byte and bit labeling is used. Hence, a[0] is the most
* significant bit, and a[31] is the least significant bit.
*
* Use of casex and casez may affect functionality, and produce
* larger and slower designs that omit the full_case directive
*
* Reference:
* Don Mills and Clifford E. Cummings, "RTL Coding Styles That
* Yield Simulation and Synthesis Mismatches", SNUG 1999
*
* ALU is a combinational logic block without clock signals
*
* wallace tree multiplier???
*/
`include "control.h"
// Behavioral model for the ALU
module alu (reg_A,reg_B,ctrl_ww,alu_op,result);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
/**
* Overflow fromn arithmetic operations are ignored; use
* saturating mode for arithmetic operations - cap the value
* at the maximum value.
*
* Also, an output signal to indicate that an overflow has
* occurred will not be provided
*/
// ===============================================================
// Input signals
// Input register A
input [0:127] reg_A;
// Input register B
input [0:127] reg_B;
// Control signal bits - ww
input [0:1] ctrl_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform
*/
input [0:4] alu_op;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*
* The reset signal for the ALU is ignored
*/
// Defining constants: parameter [name_of_constant] = value;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:127] result; // Output signals
// ===============================================================
always @(reg_A or reg_B or ctrl_ww or alu_op)
begin
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
/**
* In computer science, a logical shift is a shift operator
* that shifts all the bits of its operand. Unlike an
* arithmetic shift, a logical shift does not preserve
* a number's sign bit or distinguish a number's exponent
* from its mantissa; every bit in the operand is simply
* moved a given number of bit positions, and the vacant
* bit-positions are filled in, generally with zeros
* (compare with a circular shift).
*
* SRL,SLL,Srli,sra,srai...
*/
// ======================================================
// ======================================================
// SRA instruction >> mv to LSB >> bit 127
`aluwsra:
begin
case(ctrl_ww)
`w8: // sra AND `w8
begin
case(reg_B[5:7])
0:
begin
result[0:7]<=reg_A[0:7]>>0;
result[8:15]<=reg_A[8:15]>>0;
result[16:23]<=reg_A[16:23]>>0;
result[24:31]<=reg_A[24:31]>>0;
result[32:39]<=reg_A[32:39]>>0;
result[40:47]<=reg_A[40:47]>>0;
result[48:55]<=reg_A[48:55]>>0;
result[56:63]<=reg_A[56:63]>>0;
result[64:71]<=reg_A[64:71]>>0;
result[72:79]<=reg_A[72:79]>>0;
result[80:87]<=reg_A[80:87]>>0;
result[88:95]<=reg_A[88:95]>>0;
result[96:103]<=reg_A[96:103]>>0;
result[104:111]<=reg_A[104:111]>>0;
result[112:119]<=reg_A[112:119]>>0;
result[120:127]<=reg_A[120:127]>>0;
end
1:
begin
result[0:7]<=reg_A[0:7]>>1;
result[0]<=result[0];
result[8:15]<=reg_A[8:15]>>1;
result[8]<=result[8];
result[16:23]<=reg_A[16:23]>>1;
result[16]<=result[16];
result[24:31]<=reg_A[24:31]>>1;
result[24]<=result[24];
result[32:39]<=reg_A[32:39]>>1;
result[32]<=result[32];
result[40:47]<=reg_A[40:47]>>1;
result[40]<=result[40];
result[48:55]<=reg_A[48:55]>>1;
result[48]<=result[48];
result[56:63]<=reg_A[56:63]>>1;
result[56]<=result[56];
result[64:71]<=reg_A[64:71]>>1;
result[64]<=result[64];
result[72:79]<=reg_A[72:79]>>1;
result[72]<=result[72];
result[80:87]<=reg_A[80:87]>>1;
result[80]<=result[80];
result[88:95]<=reg_A[88:95]>>1;
result[88]<=result[88];
result[96:103]<=reg_A[96:103]>>1;
result[96]<=result[96];
result[104:111]<=reg_A[104:111]>>1;
result[104]<=result[104];
result[112:119]<=reg_A[112:119]>>1;
result[112]<=result[112];
result[120:127]<=reg_A[120:127]>>1;
result[120]<=result[120];
end
2:
begin
result[0:7]<=reg_A[0:7]>>2;
result[0]<=result[0];
result[1]<=result[0];
result[8:15]<=reg_A[8:15]>>2;
result[8]<=result[8];
result[9]<=result[8];
result[16:23]<=reg_A[16:23]>>2;
result[16]<=result[16];
result[17]<=result[16];
result[24:31]<=reg_A[24:31]>>2;
result[24]<=result[24];
result[25]<=result[24];
result[32:39]<=reg_A[32:39]>>2;
result[32]<=result[32];
result[33]<=result[32];
result[40:47]<=reg_A[40:47]>>2;
result[40]<=result[40];
result[41]<=result[40];
result[48:55]<=reg_A[48:55]>>2;
result[48]<=result[48];
result[49]<=result[48];
result[56:63]<=reg_A[56:63]>>2;
result[56]<=result[56];
result[57]<=result[56];
result[64:71]<=reg_A[64:71]>>2;
result[64]<=result[64];
result[65]<=result[64];
result[72:79]<=reg_A[72:79]>>2;
result[72]<=result[72];
result[73]<=result[72];
result[80:87]<=reg_A[80:87]>>2;
result[80]<=result[80];
result[81]<=result[80];
result[88:95]<=reg_A[88:95]>>2;
result[88]<=result[88];
result[89]<=result[88];
result[96:103]<=reg_A[96:103]>>2;
result[96]<=result[96];
result[97]<=result[96];
result[104:111]<=reg_A[104:111]>>2;
result[104]<=result[104];
result[105]<=result[104];
result[112:119]<=reg_A[112:119]>>2;
result[112]<=result[112];
result[113]<=result[112];
result[120:127]<=reg_A[120:127]>>2;
result[120]<=result[120];
result[121]<=result[120];
end
3:
begin
result[0:7]<=reg_A[0:7]>>3;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[8:15]<=reg_A[8:15]>>3;
result[8]<=result[8];
result[9]<=result[8];
result[10]<=result[8];
result[16:23]<=reg_A[16:23]>>3;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[24:31]<=reg_A[24:31]>>3;
result[24]<=result[24];
result[25]<=result[24];
result[26]<=result[24];
result[32:39]<=reg_A[32:39]>>3;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[40:47]<=reg_A[40:47]>>3;
result[40]<=result[40];
result[41]<=result[40];
result[42]<=result[40];
result[48:55]<=reg_A[48:55]>>3;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[56:63]<=reg_A[56:63]>>3;
result[56]<=result[56];
result[57]<=result[56];
result[58]<=result[56];
result[64:71]<=reg_A[64:71]>>3;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[72:79]<=reg_A[72:79]>>3;
result[72]<=result[72];
result[73]<=result[72];
result[74]<=result[72];
result[80:87]<=reg_A[80:87]>>3;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[88:95]<=reg_A[88:95]>>3;
result[88]<=result[88];
result[89]<=result[88];
result[90]<=result[88];
result[96:103]<=reg_A[96:103]>>3;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[104:111]<=reg_A[104:111]>>3;
result[104]<=result[104];
result[105]<=result[104];
result[106]<=result[104];
result[112:119]<=reg_A[112:119]>>3;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[120:127]<=reg_A[120:127]>>3;
result[120]<=result[120];
result[121]<=result[120];
result[122]<=result[120];
end
4:
begin
$display("entered 8 - shift 4");
result[0:7]<=reg_A[0:7]>>4;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[8:15]<=reg_A[8:15]>>4;
result[8]<=result[8];
result[9]<=result[8];
result[10]<=result[8];
result[11]<=result[8];
result[16:23]<=reg_A[16:23]>>4;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[24:31]<=reg_A[24:31]>>4;
result[24]<=result[24];
result[25]<=result[24];
result[26]<=result[24];
result[27]<=result[24];
result[32:39]<=reg_A[32:39]>>4;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[40:47]<=reg_A[40:47]>>4;
result[40]<=result[40];
result[41]<=result[40];
result[42]<=result[40];
result[43]<=result[40];
result[48:55]<=reg_A[48:55]>>4;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[56:63]<=reg_A[56:63]>>4;
result[56]<=result[56];
result[57]<=result[56];
result[58]<=result[56];
result[59]<=result[56];
result[64:71]<=reg_A[64:71]>>4;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[72:79]<=reg_A[72:79]>>4;
result[72]<=result[72];
result[73]<=result[72];
result[74]<=result[72];
result[75]<=result[72];
result[80:87]<=reg_A[80:87]>>4;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[88:95]<=reg_A[88:95]>>4;
result[88]<=result[88];
result[89]<=result[88];
result[90]<=result[88];
result[91]<=result[88];
result[96:103]<=reg_A[96:103]>>4;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[104:111]<=reg_A[104:111]>>4;
result[104]<=result[104];
result[105]<=result[104];
result[106]<=result[104];
result[107]<=result[104];
result[112:119]<=reg_A[112:119]>>4;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[120:127]<=reg_A[120:127]>>4;
result[120]<=result[120];
result[121]<=result[120];
result[122]<=result[120];
result[123]<=result[120];
end
5:
begin
result[0:7]<=reg_A[0:7]>>5;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[8:15]<=reg_A[8:15]>>5;
result[8]<=result[8];
result[9]<=result[8];
result[10]<=result[8];
result[11]<=result[8];
result[12]<=result[8];
result[16:23]<=reg_A[16:23]>>5;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[24:31]<=reg_A[24:31]>>5;
result[24]<=result[24];
result[25]<=result[24];
result[26]<=result[24];
result[27]<=result[24];
result[28]<=result[24];
result[32:39]<=reg_A[32:39]>>5;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[40:47]<=reg_A[40:47]>>5;
result[40]<=result[40];
result[41]<=result[40];
result[42]<=result[40];
result[43]<=result[40];
result[44]<=result[40];
result[48:55]<=reg_A[48:55]>>5;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[56:63]<=reg_A[56:63]>>5;
result[56]<=result[56];
result[57]<=result[56];
result[58]<=result[56];
result[59]<=result[56];
result[60]<=result[56];
result[64:71]<=reg_A[64:71]>>5;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[72:79]<=reg_A[72:79]>>5;
result[72]<=result[72];
result[73]<=result[72];
result[74]<=result[72];
result[75]<=result[72];
result[76]<=result[72];
result[80:87]<=reg_A[80:87]>>5;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[88:95]<=reg_A[88:95]>>5;
result[88]<=result[88];
result[89]<=result[88];
result[90]<=result[88];
result[91]<=result[88];
result[92]<=result[88];
result[96:103]<=reg_A[96:103]>>5;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[104:111]<=reg_A[104:111]>>5;
result[104]<=result[104];
result[105]<=result[104];
result[106]<=result[104];
result[107]<=result[104];
result[108]<=result[104];
result[112:119]<=reg_A[112:119]>>5;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[120:127]<=reg_A[120:127]>>5;
result[120]<=result[120];
result[121]<=result[120];
result[122]<=result[120];
result[123]<=result[120];
result[124]<=result[120];
end
6:
begin
result[0:7]<=reg_A[0:7]>>6;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[8:15]<=reg_A[8:15]>>6;
result[8]<=result[8];
result[9]<=result[8];
result[10]<=result[8];
result[11]<=result[8];
result[12]<=result[8];
result[13]<=result[8];
result[16:23]<=reg_A[16:23]>>6;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[24:31]<=reg_A[24:31]>>6;
result[24]<=result[24];
result[25]<=result[24];
result[26]<=result[24];
result[27]<=result[24];
result[28]<=result[24];
result[29]<=result[24];
result[32:39]<=reg_A[32:39]>>6;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[40:47]<=reg_A[40:47]>>6;
result[40]<=result[40];
result[41]<=result[40];
result[42]<=result[40];
result[43]<=result[40];
result[44]<=result[40];
result[45]<=result[40];
result[48:55]<=reg_A[48:55]>>6;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[56:63]<=reg_A[56:63]>>6;
result[56]<=result[56];
result[57]<=result[56];
result[58]<=result[56];
result[59]<=result[56];
result[60]<=result[56];
result[61]<=result[56];
result[64:71]<=reg_A[64:71]>>6;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[72:79]<=reg_A[72:79]>>6;
result[72]<=result[72];
result[73]<=result[72];
result[74]<=result[72];
result[75]<=result[72];
result[76]<=result[72];
result[77]<=result[72];
result[80:87]<=reg_A[80:87]>>6;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[88:95]<=reg_A[88:95]>>6;
result[88]<=result[88];
result[89]<=result[88];
result[90]<=result[88];
result[91]<=result[88];
result[92]<=result[88];
result[93]<=result[88];
result[96:103]<=reg_A[96:103]>>6;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[104:111]<=reg_A[104:111]>>6;
result[104]<=result[104];
result[105]<=result[104];
result[106]<=result[104];
result[107]<=result[104];
result[108]<=result[104];
result[109]<=result[104];
result[112:119]<=reg_A[112:119]>>6;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[120:127]<=reg_A[120:127]>>6;
result[120]<=result[120];
result[121]<=result[120];
result[122]<=result[120];
result[123]<=result[120];
result[124]<=result[120];
result[125]<=result[120];
end
default: // sra AND `w8 && 7
begin
result[0:7]<=reg_A[0:7]>>7;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[8:15]<=reg_A[8:15]>>7;
result[8]<=result[8];
result[9]<=result[8];
result[10]<=result[8];
result[11]<=result[8];
result[12]<=result[8];
result[13]<=result[8];
result[14]<=result[8];
result[16:23]<=reg_A[16:23]>>7;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[24:31]<=reg_A[24:31]>>7;
result[24]<=result[24];
result[25]<=result[24];
result[26]<=result[24];
result[27]<=result[24];
result[28]<=result[24];
result[29]<=result[24];
result[30]<=result[24];
result[32:39]<=reg_A[32:39]>>7;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[40:47]<=reg_A[40:47]>>7;
result[40]<=result[40];
result[41]<=result[40];
result[42]<=result[40];
result[43]<=result[40];
result[44]<=result[40];
result[45]<=result[40];
result[46]<=result[40];
result[48:55]<=reg_A[48:55]>>7;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[56:63]<=reg_A[56:63]>>7;
result[56]<=result[56];
result[57]<=result[56];
result[58]<=result[56];
result[59]<=result[56];
result[60]<=result[56];
result[61]<=result[56];
result[62]<=result[56];
result[64:71]<=reg_A[64:71]>>7;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[72:79]<=reg_A[72:79]>>7;
result[72]<=result[72];
result[73]<=result[72];
result[74]<=result[72];
result[75]<=result[72];
result[76]<=result[72];
result[77]<=result[72];
result[78]<=result[72];
result[80:87]<=reg_A[80:87]>>7;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[88:95]<=reg_A[88:95]>>7;
result[88]<=result[88];
result[89]<=result[88];
result[90]<=result[88];
result[91]<=result[88];
result[92]<=result[88];
result[93]<=result[88];
result[94]<=result[88];
result[96:103]<=reg_A[96:103]>>7;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[104:111]<=reg_A[104:111]>>7;
result[104]<=result[104];
result[105]<=result[104];
result[106]<=result[104];
result[107]<=result[104];
result[108]<=result[104];
result[109]<=result[104];
result[110]<=result[104];
result[112:119]<=reg_A[112:119]>>7;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[120:127]<=reg_A[120:127]>>7;
result[120]<=result[120];
result[121]<=result[120];
result[122]<=result[120];
result[123]<=result[120];
result[124]<=result[120];
result[125]<=result[120];
result[126]<=result[120];
end
endcase
end
`w16: // sra AND `w16
begin
case(reg_B[4:7])
0:
begin
result[0:15]<=reg_A[0:15]>>0;
result[16:31]<=reg_A[16:31]>>0;
result[32:47]<=reg_A[32:47]>>0;
result[48:63]<=reg_A[48:63]>>0;
result[64:79]<=reg_A[64:79]>>0;
result[80:95]<=reg_A[80:95]>>0;
result[96:111]<=reg_A[96:111]>>0;
result[112:127]<=reg_A[112:127]>>0;
end
1:
begin
result[0:15]<=reg_A[0:15]>>1;
result[0]<=result[0];
result[16:31]<=reg_A[16:31]>>1;
result[16]<=result[16];
result[32:47]<=reg_A[32:47]>>1;
result[32]<=result[32];
result[48:63]<=reg_A[48:63]>>1;
result[48]<=result[48];
result[64:79]<=reg_A[64:79]>>1;
result[64]<=result[64];
result[80:95]<=reg_A[80:95]>>1;
result[80]<=result[80];
result[96:111]<=reg_A[96:111]>>1;
result[96]<=result[96];
result[112:127]<=reg_A[112:127]>>1;
result[112]<=result[112];
end
2:
begin
result[0:15]<=reg_A[0:15]>>2;
result[0]<=result[0];
result[1]<=result[0];
result[16:31]<=reg_A[16:31]>>2;
result[16]<=result[16];
result[17]<=result[16];
result[32:47]<=reg_A[32:47]>>2;
result[32]<=result[32];
result[33]<=result[32];
result[48:63]<=reg_A[48:63]>>2;
result[48]<=result[48];
result[49]<=result[48];
result[64:79]<=reg_A[64:79]>>2;
result[64]<=result[64];
result[65]<=result[64];
result[80:95]<=reg_A[80:95]>>2;
result[80]<=result[80];
result[81]<=result[80];
result[96:111]<=reg_A[96:111]>>2;
result[96]<=result[96];
result[97]<=result[96];
result[112:127]<=reg_A[112:127]>>2;
result[112]<=result[112];
result[113]<=result[112];
end
3:
begin
result[0:15]<=reg_A[0:15]>>3;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[16:31]<=reg_A[16:31]>>3;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[32:47]<=reg_A[32:47]>>3;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[48:63]<=reg_A[48:63]>>3;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[64:79]<=reg_A[64:79]>>3;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[80:95]<=reg_A[80:95]>>3;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[96:111]<=reg_A[96:111]>>3;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[112:127]<=reg_A[112:127]>>3;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
end
4:
begin
$display("entered 16 - shift 4");
result[0:15]<=reg_A[0:15]>>4;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[16:31]<=reg_A[16:31]>>4;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[32:47]<=reg_A[32:47]>>4;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[48:63]<=reg_A[48:63]>>4;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[64:79]<=reg_A[64:79]>>4;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[80:95]<=reg_A[80:95]>>4;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[96:111]<=reg_A[96:111]>>4;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[112:127]<=reg_A[112:127]>>4;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
end
5:
begin
result[0:15]<=reg_A[0:15]>>5;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[16:31]<=reg_A[16:31]>>5;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[32:47]<=reg_A[32:47]>>5;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[48:63]<=reg_A[48:63]>>5;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[64:79]<=reg_A[64:79]>>5;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[80:95]<=reg_A[80:95]>>5;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[96:111]<=reg_A[96:111]>>5;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[112:127]<=reg_A[112:127]>>5;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
end
6:
begin
result[0:15]<=reg_A[0:15]>>6;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[16:31]<=reg_A[16:31]>>6;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[32:47]<=reg_A[32:47]>>6;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[48:63]<=reg_A[48:63]>>6;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[64:79]<=reg_A[64:79]>>6;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[80:95]<=reg_A[80:95]>>6;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[96:111]<=reg_A[96:111]>>6;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[112:127]<=reg_A[112:127]>>6;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
end
7:
begin
result[0:15]<=reg_A[0:15]>>7;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[16:31]<=reg_A[16:31]>>7;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[32:47]<=reg_A[32:47]>>7;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[48:63]<=reg_A[48:63]>>7;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[64:79]<=reg_A[64:79]>>7;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[80:95]<=reg_A[80:95]>>7;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[96:111]<=reg_A[96:111]>>7;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[112:127]<=reg_A[112:127]>>7;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
end
8:
begin
$display("entered 16 - shift 8");
result[0:15]<=reg_A[0:15]>>8;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[16:31]<=reg_A[16:31]>>8;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[23]<=result[16];
result[32:47]<=reg_A[32:47]>>8;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[48:63]<=reg_A[48:63]>>8;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[55]<=result[48];
result[64:79]<=reg_A[64:79]>>8;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[80:95]<=reg_A[80:95]>>8;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[87]<=result[80];
result[96:111]<=reg_A[96:111]>>8;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[112:127]<=reg_A[112:127]>>8;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[119]<=result[112];
end
9:
begin
result[0:15]<=reg_A[0:15]>>9;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[16:31]<=reg_A[16:31]>>9;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[23]<=result[16];
result[24]<=result[16];
result[32:47]<=reg_A[32:47]>>9;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[48:63]<=reg_A[48:63]>>9;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[55]<=result[48];
result[56]<=result[48];
result[64:79]<=reg_A[64:79]>>9;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[80:95]<=reg_A[80:95]>>9;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[87]<=result[80];
result[88]<=result[80];
result[96:111]<=reg_A[96:111]>>9;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[112:127]<=reg_A[112:127]>>9;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[119]<=result[112];
result[120]<=result[112];
end
10:
begin
result[0:15]<=reg_A[0:15]>>10;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[16:31]<=reg_A[16:31]>>10;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[23]<=result[16];
result[24]<=result[16];
result[25]<=result[16];
result[32:47]<=reg_A[32:47]>>10;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[48:63]<=reg_A[48:63]>>10;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[55]<=result[48];
result[56]<=result[48];
result[57]<=result[48];
result[64:79]<=reg_A[64:79]>>10;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[80:95]<=reg_A[80:95]>>10;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[87]<=result[80];
result[88]<=result[80];
result[89]<=result[80];
result[96:111]<=reg_A[96:111]>>10;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[112:127]<=reg_A[112:127]>>10;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[119]<=result[112];
result[120]<=result[112];
result[121]<=result[112];
end
11:
begin
result[0:15]<=reg_A[0:15]>>11;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[16:31]<=reg_A[16:31]>>11;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[23]<=result[16];
result[24]<=result[16];
result[25]<=result[16];
result[26]<=result[16];
result[32:47]<=reg_A[32:47]>>11;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[48:63]<=reg_A[48:63]>>11;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[55]<=result[48];
result[56]<=result[48];
result[57]<=result[48];
result[58]<=result[48];
result[64:79]<=reg_A[64:79]>>11;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[80:95]<=reg_A[80:95]>>11;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[87]<=result[80];
result[88]<=result[80];
result[89]<=result[80];
result[90]<=result[80];
result[96:111]<=reg_A[96:111]>>11;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[112:127]<=reg_A[112:127]>>11;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[119]<=result[112];
result[120]<=result[112];
result[121]<=result[112];
result[122]<=result[112];
end
12:
begin
result[0:15]<=reg_A[0:15]>>12;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[16:31]<=reg_A[16:31]>>12;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[23]<=result[16];
result[24]<=result[16];
result[25]<=result[16];
result[26]<=result[16];
result[27]<=result[16];
result[32:47]<=reg_A[32:47]>>12;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[48:63]<=reg_A[48:63]>>12;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[55]<=result[48];
result[56]<=result[48];
result[57]<=result[48];
result[58]<=result[48];
result[59]<=result[48];
result[64:79]<=reg_A[64:79]>>12;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[80:95]<=reg_A[80:95]>>12;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[87]<=result[80];
result[88]<=result[80];
result[89]<=result[80];
result[90]<=result[80];
result[91]<=result[80];
result[96:111]<=reg_A[96:111]>>12;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[112:127]<=reg_A[112:127]>>12;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[119]<=result[112];
result[120]<=result[112];
result[121]<=result[112];
result[122]<=result[112];
result[123]<=result[112];
end
13:
begin
result[0:15]<=reg_A[0:15]>>13;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[16:31]<=reg_A[16:31]>>13;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[23]<=result[16];
result[24]<=result[16];
result[25]<=result[16];
result[26]<=result[16];
result[27]<=result[16];
result[28]<=result[16];
result[32:47]<=reg_A[32:47]>>13;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[48:63]<=reg_A[48:63]>>13;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[55]<=result[48];
result[56]<=result[48];
result[57]<=result[48];
result[58]<=result[48];
result[59]<=result[48];
result[60]<=result[48];
result[64:79]<=reg_A[64:79]>>13;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[80:95]<=reg_A[80:95]>>13;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[87]<=result[80];
result[88]<=result[80];
result[89]<=result[80];
result[90]<=result[80];
result[91]<=result[80];
result[92]<=result[80];
result[96:111]<=reg_A[96:111]>>13;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[112:127]<=reg_A[112:127]>>13;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[119]<=result[112];
result[120]<=result[112];
result[121]<=result[112];
result[122]<=result[112];
result[123]<=result[112];
result[124]<=result[112];
end
14:
begin
$display("entered 16 - shift 14");
result[0:15]<=reg_A[0:15]>>14;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[16:31]<=reg_A[16:31]>>14;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[23]<=result[16];
result[24]<=result[16];
result[25]<=result[16];
result[26]<=result[16];
result[27]<=result[16];
result[28]<=result[16];
result[29]<=result[16];
result[32:47]<=reg_A[32:47]>>14;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[48:63]<=reg_A[48:63]>>14;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[55]<=result[48];
result[56]<=result[48];
result[57]<=result[48];
result[58]<=result[48];
result[59]<=result[48];
result[60]<=result[48];
result[61]<=result[48];
result[64:79]<=reg_A[64:79]>>14;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[80:95]<=reg_A[80:95]>>14;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[87]<=result[80];
result[88]<=result[80];
result[89]<=result[80];
result[90]<=result[80];
result[91]<=result[80];
result[92]<=result[80];
result[93]<=result[80];
result[96:111]<=reg_A[96:111]>>14;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[112:127]<=reg_A[112:127]>>14;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[119]<=result[112];
result[120]<=result[112];
result[121]<=result[112];
result[122]<=result[112];
result[123]<=result[112];
result[124]<=result[112];
result[125]<=result[112];
end
default: // sra AND `w16 && 15
begin
result[0:15]<=reg_A[0:15]>>15;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[16:31]<=reg_A[16:31]>>15;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[23]<=result[16];
result[24]<=result[16];
result[25]<=result[16];
result[26]<=result[16];
result[27]<=result[16];
result[28]<=result[16];
result[29]<=result[16];
result[30]<=result[16];
result[32:47]<=reg_A[32:47]>>15;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[48:63]<=reg_A[48:63]>>15;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[55]<=result[48];
result[56]<=result[48];
result[57]<=result[48];
result[58]<=result[48];
result[59]<=result[48];
result[60]<=result[48];
result[61]<=result[48];
result[62]<=result[48];
result[64:79]<=reg_A[64:79]>>15;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[80:95]<=reg_A[80:95]>>15;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[87]<=result[80];
result[88]<=result[80];
result[89]<=result[80];
result[90]<=result[80];
result[91]<=result[80];
result[92]<=result[80];
result[93]<=result[80];
result[94]<=result[80];
result[96:111]<=reg_A[96:111]>>15;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[112:127]<=reg_A[112:127]>>15;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[119]<=result[112];
result[120]<=result[112];
result[121]<=result[112];
result[122]<=result[112];
result[123]<=result[112];
result[124]<=result[112];
result[125]<=result[112];
result[126]<=result[112];
end
endcase
end
default: // sra AND `w32:
begin
case(reg_B[5:7])
0:
begin
result[0:31]<=reg_A[0:31]>>0;
result[32:63]<=reg_A[32:63]>>0;
result[64:95]<=reg_A[64:95]>>0;
result[96:127]<=reg_A[96:127]>>0;
end
1:
begin
result[0:31]<=reg_A[0:31]>>1;
result[0]<=result[0];
result[32:63]<=reg_A[32:63]>>1;
result[32]<=result[32];
result[64:95]<=reg_A[64:95]>>1;
result[64]<=result[64];
result[96:127]<=reg_A[96:127]>>1;
result[96]<=result[96];
end
2:
begin
result[0:31]<=reg_A[0:31]>>2;
result[0]<=result[0];
result[1]<=result[0];
result[32:63]<=reg_A[32:63]>>2;
result[32]<=result[32];
result[33]<=result[32];
result[64:95]<=reg_A[64:95]>>2;
result[64]<=result[64];
result[65]<=result[64];
result[96:127]<=reg_A[96:127]>>2;
result[96]<=result[96];
result[97]<=result[96];
end
3:
begin
result[0:31]<=reg_A[0:31]>>3;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[32:63]<=reg_A[32:63]>>3;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[64:95]<=reg_A[64:95]>>3;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[96:127]<=reg_A[96:127]>>3;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
end
4:
begin
result[0:31]<=reg_A[0:31]>>4;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[32:63]<=reg_A[32:63]>>4;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[64:95]<=reg_A[64:95]>>4;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[96:127]<=reg_A[96:127]>>4;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
end
5:
begin
result[0:31]<=reg_A[0:31]>>5;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[32:63]<=reg_A[32:63]>>5;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[64:95]<=reg_A[64:95]>>5;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[96:127]<=reg_A[96:127]>>5;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
end
6:
begin
result[0:31]<=reg_A[0:31]>>6;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[32:63]<=reg_A[32:63]>>6;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[64:95]<=reg_A[64:95]>>6;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[96:127]<=reg_A[96:127]>>6;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
end
7:
begin
result[0:31]<=reg_A[0:31]>>7;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[32:63]<=reg_A[32:63]>>7;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[64:95]<=reg_A[64:95]>>7;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[96:127]<=reg_A[96:127]>>7;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
end
8:
begin
$display("entered 32 - shift 8");
result[0:31]<=reg_A[0:31]>>8;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[32:63]<=reg_A[32:63]>>8;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[64:95]<=reg_A[64:95]>>8;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[96:127]<=reg_A[96:127]>>8;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
end
9:
begin
result[0:31]<=reg_A[0:31]>>9;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[32:63]<=reg_A[32:63]>>9;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[64:95]<=reg_A[64:95]>>9;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[96:127]<=reg_A[96:127]>>9;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
end
10:
begin
result[0:31]<=reg_A[0:31]>>10;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[32:63]<=reg_A[32:63]>>10;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[64:95]<=reg_A[64:95]>>10;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[96:127]<=reg_A[96:127]>>10;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
end
11:
begin
$display("entered 32 - shift 11");
result[0:31]<=reg_A[0:31]>>11;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[32:63]<=reg_A[32:63]>>11;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[64:95]<=reg_A[64:95]>>11;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[96:127]<=reg_A[96:127]>>11;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
end
12:
begin
$display("entered 32 - shift 12");
result[0:31]<=reg_A[0:31]>>12;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[32:63]<=reg_A[32:63]>>12;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[64:95]<=reg_A[64:95]>>12;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[96:127]<=reg_A[96:127]>>12;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
end
13:
begin
result[0:31]<=reg_A[0:31]>>13;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[32:63]<=reg_A[32:63]>>13;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[64:95]<=reg_A[64:95]>>13;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[96:127]<=reg_A[96:127]>>13;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
end
14:
begin
result[0:31]<=reg_A[0:31]>>14;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[32:63]<=reg_A[32:63]>>14;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[64:95]<=reg_A[64:95]>>14;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[96:127]<=reg_A[96:127]>>14;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
end
15:
begin
result[0:31]<=reg_A[0:31]>>15;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[32:63]<=reg_A[32:63]>>15;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[64:95]<=reg_A[64:95]>>15;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[96:127]<=reg_A[96:127]>>15;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
end
16:
begin
$display("entered 32 - shift 16");
result[0:31]<=reg_A[0:31]>>16;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[32:63]<=reg_A[32:63]>>16;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[64:95]<=reg_A[64:95]>>16;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[96:127]<=reg_A[96:127]>>16;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
end
17:
begin
result[0:31]<=reg_A[0:31]>>17;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[32:63]<=reg_A[32:63]>>17;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[64:95]<=reg_A[64:95]>>17;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[96:127]<=reg_A[96:127]>>17;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
end
18:
begin
result[0:31]<=reg_A[0:31]>>18;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[32:63]<=reg_A[32:63]>>18;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[64:95]<=reg_A[64:95]>>18;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[96:127]<=reg_A[96:127]>>18;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
end
19:
begin
result[0:31]<=reg_A[0:31]>>19;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[32:63]<=reg_A[32:63]>>19;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[64:95]<=reg_A[64:95]>>19;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[96:127]<=reg_A[96:127]>>19;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
end
20:
begin
result[0:31]<=reg_A[0:31]>>20;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[32:63]<=reg_A[32:63]>>20;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[64:95]<=reg_A[64:95]>>20;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[96:127]<=reg_A[96:127]>>20;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
end
21:
begin
result[0:31]<=reg_A[0:31]>>21;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[32:63]<=reg_A[32:63]>>21;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[64:95]<=reg_A[64:95]>>21;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[96:127]<=reg_A[96:127]>>21;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
end
22:
begin
result[0:31]<=reg_A[0:31]>>22;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[32:63]<=reg_A[32:63]>>22;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[64:95]<=reg_A[64:95]>>22;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[96:127]<=reg_A[96:127]>>22;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
end
23:
begin
result[0:31]<=reg_A[0:31]>>23;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[32:63]<=reg_A[32:63]>>23;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[64:95]<=reg_A[64:95]>>23;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[96:127]<=reg_A[96:127]>>23;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
end
24:
begin
result[0:31]<=reg_A[0:31]>>24;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[23]<=result[0];
result[32:63]<=reg_A[32:63]>>24;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[55]<=result[32];
result[64:95]<=reg_A[64:95]>>24;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[87]<=result[64];
result[96:127]<=reg_A[96:127]>>24;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
result[119]<=result[96];
end
25:
begin
result[0:31]<=reg_A[0:31]>>25;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[23]<=result[0];
result[24]<=result[0];
result[32:63]<=reg_A[32:63]>>25;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[55]<=result[32];
result[56]<=result[32];
result[64:95]<=reg_A[64:95]>>25;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[87]<=result[64];
result[88]<=result[64];
result[96:127]<=reg_A[96:127]>>25;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
result[119]<=result[96];
result[120]<=result[96];
end
26:
begin
result[0:31]<=reg_A[0:31]>>26;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[23]<=result[0];
result[24]<=result[0];
result[25]<=result[0];
result[32:63]<=reg_A[32:63]>>26;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[55]<=result[32];
result[56]<=result[32];
result[57]<=result[32];
result[64:95]<=reg_A[64:95]>>26;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[87]<=result[64];
result[88]<=result[64];
result[89]<=result[64];
result[96:127]<=reg_A[96:127]>>26;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
result[119]<=result[96];
result[120]<=result[96];
result[121]<=result[96];
end
27:
begin
$display("entered 32 - shift 27");
result[0:31]<=reg_A[0:31]>>27;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[23]<=result[0];
result[24]<=result[0];
result[25]<=result[0];
result[26]<=result[0];
result[32:63]<=reg_A[32:63]>>27;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[55]<=result[32];
result[56]<=result[32];
result[57]<=result[32];
result[58]<=result[32];
result[64:95]<=reg_A[64:95]>>27;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[87]<=result[64];
result[88]<=result[64];
result[89]<=result[64];
result[90]<=result[64];
result[96:127]<=reg_A[96:127]>>27;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
result[119]<=result[96];
result[120]<=result[96];
result[121]<=result[96];
result[122]<=result[96];
end
28:
begin
result[0:31]<=reg_A[0:31]>>28;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[23]<=result[0];
result[24]<=result[0];
result[25]<=result[0];
result[26]<=result[0];
result[27]<=result[0];
result[32:63]<=reg_A[32:63]>>28;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[55]<=result[32];
result[56]<=result[32];
result[57]<=result[32];
result[58]<=result[32];
result[59]<=result[32];
result[64:95]<=reg_A[64:95]>>28;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[87]<=result[64];
result[88]<=result[64];
result[89]<=result[64];
result[90]<=result[64];
result[91]<=result[64];
result[96:127]<=reg_A[96:127]>>28;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
result[119]<=result[96];
result[120]<=result[96];
result[121]<=result[96];
result[122]<=result[96];
result[123]<=result[96];
end
29:
begin
result[0:31]<=reg_A[0:31]>>29;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[23]<=result[0];
result[24]<=result[0];
result[25]<=result[0];
result[26]<=result[0];
result[27]<=result[0];
result[28]<=result[0];
result[32:63]<=reg_A[32:63]>>29;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[55]<=result[32];
result[56]<=result[32];
result[57]<=result[32];
result[58]<=result[32];
result[59]<=result[32];
result[60]<=result[32];
result[64:95]<=reg_A[64:95]>>29;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[87]<=result[64];
result[88]<=result[64];
result[89]<=result[64];
result[90]<=result[64];
result[91]<=result[64];
result[92]<=result[64];
result[96:127]<=reg_A[96:127]>>29;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
result[119]<=result[96];
result[120]<=result[96];
result[121]<=result[96];
result[122]<=result[96];
result[123]<=result[96];
result[124]<=result[96];
end
30:
begin
result[0:31]<=reg_A[0:31]>>30;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[23]<=result[0];
result[24]<=result[0];
result[25]<=result[0];
result[26]<=result[0];
result[27]<=result[0];
result[28]<=result[0];
result[29]<=result[0];
result[32:63]<=reg_A[32:63]>>30;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[55]<=result[32];
result[56]<=result[32];
result[57]<=result[32];
result[58]<=result[32];
result[59]<=result[32];
result[60]<=result[32];
result[61]<=result[32];
result[64:95]<=reg_A[64:95]>>30;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[87]<=result[64];
result[88]<=result[64];
result[89]<=result[64];
result[90]<=result[64];
result[91]<=result[64];
result[92]<=result[64];
result[93]<=result[64];
result[96:127]<=reg_A[96:127]>>30;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
result[119]<=result[96];
result[120]<=result[96];
result[121]<=result[96];
result[122]<=result[96];
result[123]<=result[96];
result[124]<=result[96];
result[125]<=result[96];
end
default: // sra AND `w32 && 31
begin
result[0:31]<=reg_A[0:31]>>31;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[23]<=result[0];
result[24]<=result[0];
result[25]<=result[0];
result[26]<=result[0];
result[27]<=result[0];
result[28]<=result[0];
result[29]<=result[0];
result[30]<=result[0];
result[32:63]<=reg_A[32:63]>>31;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[55]<=result[32];
result[56]<=result[32];
result[57]<=result[32];
result[58]<=result[32];
result[59]<=result[32];
result[60]<=result[32];
result[61]<=result[32];
result[62]<=result[32];
result[64:95]<=reg_A[64:95]>>31;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[87]<=result[64];
result[88]<=result[64];
result[89]<=result[64];
result[90]<=result[64];
result[91]<=result[64];
result[92]<=result[64];
result[93]<=result[64];
result[94]<=result[64];
result[96:127]<=reg_A[96:127]>>31;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
result[119]<=result[96];
result[120]<=result[96];
result[121]<=result[96];
result[122]<=result[96];
result[123]<=result[96];
result[124]<=result[96];
result[125]<=result[96];
result[126]<=result[96];
end
endcase
end
endcase
end
// ======================================================
// SLL instruction << mv to LSB << bit 127
`aluwsll:
begin
case(ctrl_ww)
`w8: // aluwsll AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]<<reg_B[5:7];
result[8:15]<=reg_A[8:15]<<reg_B[13:15];
result[16:23]<=reg_A[16:23]<<reg_B[21:23];
result[24:31]<=reg_A[24:31]<<reg_B[29:31];
result[32:39]<=reg_A[32:39]<<reg_B[37:39];
result[40:47]<=reg_A[40:47]<<reg_B[45:47];
result[48:55]<=reg_A[48:55]<<reg_B[53:55];
result[56:63]<=reg_A[56:63]<<reg_B[61:63];
result[64:71]<=reg_A[64:71]<<reg_B[69:71];
result[72:79]<=reg_A[72:79]<<reg_B[77:79];
result[80:87]<=reg_A[80:87]<<reg_B[85:87];
result[88:95]<=reg_A[88:95]<<reg_B[93:95];
result[96:103]<=reg_A[96:103]<<reg_B[101:103];
result[104:111]<=reg_A[104:111]<<reg_B[109:111];
result[112:119]<=reg_A[112:119]<<reg_B[117:119];
result[120:127]<=reg_A[120:127]<<reg_B[125:127];
end
`w16: // aluwsll AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]<<reg_B[12:15];
result[16:31]<=reg_A[16:31]<<reg_B[28:31];
result[32:47]<=reg_A[32:47]<<reg_B[44:47];
result[48:63]<=reg_A[48:63]<<reg_B[60:63];
result[64:79]<=reg_A[64:79]<<reg_B[76:79];
result[80:95]<=reg_A[80:95]<<reg_B[92:95];
result[96:111]<=reg_A[96:111]<<reg_B[108:111];
result[112:127]<=reg_A[112:127]<<reg_B[124:127];
end
`w32: // aluwsll AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]<<reg_B[27:31];
result[32:63]<=reg_A[32:63]<<reg_B[59:63];
result[64:95]<=reg_A[64:95]<<reg_B[91:95];
result[96:127]<=reg_A[96:127]<<reg_B[123:127];
end
default: // aluwsll AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
/*
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
*/
// ======================================================
// SRL instruction >> mv to MSB >> bit 0
`aluwsrl:
begin
case(ctrl_ppp)
`aa: // aluwsrl AND `aa
begin
case(ctrl_ww)
`w8: // aluwsrl AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default: // aluwsrl AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwsrl AND `uu
begin
case(ctrl_ww)
`w8: // aluwsrl AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
end
`w16: // aluwsrl AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
end
`w32: // aluwsrl AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
end
default:
begin
// aluwsrl AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwsrl AND `dd
begin
case(ctrl_ww)
`w8: // aluwsrl AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default:
begin
// aluwsrl AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwsrl AND `ee
begin
case(ctrl_ww)
`w8: // aluwsrl AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
end
`w16: // aluwsrl AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
end
`w32: // aluwsrl AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
end
default:
begin
// aluwsrl AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwsrl AND `oo
begin
case(ctrl_ww)
`w8: // aluwsrl AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default:
begin
// aluwsrl AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwsrl AND `mm
begin
case(ctrl_ww)
`w8: // aluwsrl AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
end
`w16: // aluwsrl AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
end
`w32: // aluwsrl AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
end
default:
begin
// aluwsrl AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwsrl AND `ll
begin
case(ctrl_ww)
`w8: // aluwsrl AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default:
begin
// aluwsrl AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwsrl AND Default
begin
result<=128'd0;
end
endcase
end
//================================================================================
//================================================================================
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//================================================================================
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//================================================================================
//================================================================================
// ================================================
// ADD instruction
`aluwadd:
begin
case(ctrl_ppp)
`aa: // aluwadd AND `aa
begin
case(ctrl_ww)
`w8: // aluwadd AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[32:63]<=reg_A[32:63]+reg_B[32:63];
result[64:95]<=reg_A[64:95]+reg_B[64:95];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default: // aluwadd AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwadd AND `uu
begin
case(ctrl_ww)
`w8: // aluwadd AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
end
`w16: // aluwadd AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
end
`w32: // aluwadd AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[32:63]<=reg_A[32:63]+reg_B[32:63];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwadd AND `dd
begin
case(ctrl_ww)
`w8: // aluwadd AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]+reg_B[64:95];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwadd AND `ee
begin
case(ctrl_ww)
`w8: // aluwadd AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
end
`w16: // aluwadd AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
end
`w32: // aluwadd AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[64:95]<=reg_A[64:95]+reg_B[64:95];
end
default:
begin
// aluwadd AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwadd AND `oo
begin
case(ctrl_ww)
`w8: // aluwadd AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]+reg_B[32:63];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwadd AND `mm
begin
case(ctrl_ww)
`w8: // aluwadd AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
end
`w16: // aluwadd AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
end
`w32: // aluwadd AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
end
default:
begin
// aluwadd AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwadd AND `ll
begin
case(ctrl_ww)
`w8: // aluwadd AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwadd AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// AND instruction
`aluwand:
begin
case(ctrl_ppp)
`aa: // aluwand AND `aa
begin
case(ctrl_ww)
`w8: // aluwand AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[8:15]<=reg_A[8:15]®_B[8:15];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[56:63]<=reg_A[56:63]®_B[56:63];
result[64:71]<=reg_A[64:71]®_B[64:71];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[112:119]<=reg_A[112:119]®_B[112:119];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[16:31]<=reg_A[16:31]®_B[16:31];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[48:63]<=reg_A[48:63]®_B[48:63];
result[64:79]<=reg_A[64:79]®_B[64:79];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[96:111]<=reg_A[96:111]®_B[96:111];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[32:63]<=reg_A[32:63]®_B[32:63];
result[64:95]<=reg_A[64:95]®_B[64:95];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default: // aluwand AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwand AND `uu
begin
case(ctrl_ww)
`w8: // aluwand AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[8:15]<=reg_A[8:15]®_B[8:15];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[56:63]<=reg_A[56:63]®_B[56:63];
end
`w16: // aluwand AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[16:31]<=reg_A[16:31]®_B[16:31];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[48:63]<=reg_A[48:63]®_B[48:63];
end
`w32: // aluwand AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[32:63]<=reg_A[32:63]®_B[32:63];
end
default:
begin
// aluwand AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwand AND `dd
begin
case(ctrl_ww)
`w8: // aluwand AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]®_B[64:71];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[112:119]<=reg_A[112:119]®_B[112:119];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]®_B[64:79];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[96:111]<=reg_A[96:111]®_B[96:111];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]®_B[64:95];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwand AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwand AND `ee
begin
case(ctrl_ww)
`w8: // aluwand AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[64:71]<=reg_A[64:71]®_B[64:71];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[112:119]<=reg_A[112:119]®_B[112:119];
end
`w16: // aluwand AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[64:79]<=reg_A[64:79]®_B[64:79];
result[96:111]<=reg_A[96:111]®_B[96:111];
end
`w32: // aluwand AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[64:95]<=reg_A[64:95]®_B[64:95];
end
default:
begin
// aluwand AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwand AND `oo
begin
case(ctrl_ww)
`w8: // aluwand AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]®_B[8:15];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[56:63]<=reg_A[56:63]®_B[56:63];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]®_B[16:31];
result[48:63]<=reg_A[48:63]®_B[48:63];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]®_B[32:63];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwand AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwand AND `mm
begin
case(ctrl_ww)
`w8: // aluwand AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
end
`w16: // aluwand AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
end
`w32: // aluwand AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
end
default:
begin
// aluwand AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwand AND `ll
begin
case(ctrl_ww)
`w8: // aluwand AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwand AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwand AND Default
begin
result<=128'd0;
end
endcase
end
// ==============================================
// ================================================
// NOT instruction
`aluwnot:
begin
case(ctrl_ppp)
`aa: // aluwnot AND `aa
begin
case(ctrl_ww)
`w8: // aluwnot AND `aa AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[8:15]<=~reg_A[8:15];
result[16:23]<=~reg_A[16:23];
result[24:31]<=~reg_A[24:31];
result[32:39]<=~reg_A[32:39];
result[40:47]<=~reg_A[40:47];
result[48:55]<=~reg_A[48:55];
result[56:63]<=~reg_A[56:63];
result[64:71]<=~reg_A[64:71];
result[72:79]<=~reg_A[72:79];
result[80:87]<=~reg_A[80:87];
result[88:95]<=~reg_A[88:95];
result[96:103]<=~reg_A[96:103];
result[104:111]<=~reg_A[104:111];
result[112:119]<=~reg_A[112:119];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `aa AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[16:31]<=~reg_A[16:31];
result[32:47]<=~reg_A[32:47];
result[48:63]<=~reg_A[48:63];
result[64:79]<=~reg_A[64:79];
result[80:95]<=~reg_A[80:95];
result[96:111]<=~reg_A[96:111];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `aa AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[32:63]<=~reg_A[32:63];
result[64:95]<=~reg_A[64:95];
result[96:127]<=~reg_A[96:127];
end
default: // aluwnot AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwnot AND `uu
begin
case(ctrl_ww)
`w8: // aluwnot AND `uu AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[8:15]<=~reg_A[8:15];
result[16:23]<=~reg_A[16:23];
result[24:31]<=~reg_A[24:31];
result[32:39]<=~reg_A[32:39];
result[40:47]<=~reg_A[40:47];
result[48:55]<=~reg_A[48:55];
result[56:63]<=~reg_A[56:63];
end
`w16: // aluwnot AND `uu AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[16:31]<=~reg_A[16:31];
result[32:47]<=~reg_A[32:47];
result[48:63]<=~reg_A[48:63];
end
`w32: // aluwnot AND `uu AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[32:63]<=~reg_A[32:63];
end
default:
begin
// aluwnot AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwnot AND `dd
begin
case(ctrl_ww)
`w8: // aluwnot AND `dd AND `w8
begin
result[64:71]<=~reg_A[64:71];
result[72:79]<=~reg_A[72:79];
result[80:87]<=~reg_A[80:87];
result[88:95]<=~reg_A[88:95];
result[96:103]<=~reg_A[96:103];
result[104:111]<=~reg_A[104:111];
result[112:119]<=~reg_A[112:119];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `dd AND `w16
begin
result[64:79]<=~reg_A[64:79];
result[80:95]<=~reg_A[80:95];
result[96:111]<=~reg_A[96:111];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `dd AND `w32
begin
result[64:95]<=~reg_A[64:95];
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwnot AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwnot AND `ee
begin
case(ctrl_ww)
`w8: // aluwnot AND `ee AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[16:23]<=~reg_A[16:23];
result[32:39]<=~reg_A[32:39];
result[48:55]<=~reg_A[48:55];
result[64:71]<=~reg_A[64:71];
result[80:87]<=~reg_A[80:87];
result[96:103]<=~reg_A[96:103];
result[112:119]<=~reg_A[112:119];
end
`w16: // aluwnot AND `ee AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[32:47]<=~reg_A[32:47];
result[64:79]<=~reg_A[64:79];
result[96:111]<=~reg_A[96:111];
end
`w32: // aluwnot AND `ee AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[64:95]<=~reg_A[64:95];
end
default:
begin
// aluwnot AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwnot AND `oo
begin
case(ctrl_ww)
`w8: // aluwnot AND `oo AND `w8
begin
result[8:15]<=~reg_A[8:15];
result[24:31]<=~reg_A[24:31];
result[40:47]<=~reg_A[40:47];
result[56:63]<=~reg_A[56:63];
result[72:79]<=~reg_A[72:79];
result[88:95]<=~reg_A[88:95];
result[104:111]<=~reg_A[104:111];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `oo AND `w16
begin
result[16:31]<=~reg_A[16:31];
result[48:63]<=~reg_A[48:63];
result[80:95]<=~reg_A[80:95];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `oo AND `w32
begin
result[32:63]<=~reg_A[32:63];
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwnot AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwnot AND `mm
begin
case(ctrl_ww)
`w8: // aluwnot AND `mm AND `w8
begin
result[0:7]<=~reg_A[0:7];
end
`w16: // aluwnot AND `mm AND `w16
begin
result[0:15]<=~reg_A[0:15];
end
`w32: // aluwnot AND `mm AND `w32
begin
result[0:31]<=~reg_A[0:31];
end
default:
begin
// aluwnot AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwnot AND `ll
begin
case(ctrl_ww)
`w8: // aluwnot AND `ll AND `w8
begin
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `ll AND `w16
begin
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `ll AND `w32
begin
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwnot AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwnot AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// OR instruction
`aluwor:
begin
case(ctrl_ppp)
`aa: // aluwor AND `aa
begin
case(ctrl_ww)
`w8: // aluwor AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[32:63]<=reg_A[32:63]|reg_B[32:63];
result[64:95]<=reg_A[64:95]|reg_B[64:95];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default: // aluwor AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwor AND `uu
begin
case(ctrl_ww)
`w8: // aluwor AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
end
`w16: // aluwor AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
end
`w32: // aluwor AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[32:63]<=reg_A[32:63]|reg_B[32:63];
end
default:
begin
// aluwor AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwor AND `dd
begin
case(ctrl_ww)
`w8: // aluwor AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]|reg_B[64:95];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwor AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwor AND `ee
begin
case(ctrl_ww)
`w8: // aluwor AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
end
`w16: // aluwor AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
end
`w32: // aluwor AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[64:95]<=reg_A[64:95]|reg_B[64:95];
end
default:
begin
// aluwor AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwor AND `oo
begin
case(ctrl_ww)
`w8: // aluwor AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]|reg_B[32:63];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwor AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwor AND `mm
begin
case(ctrl_ww)
`w8: // aluwor AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
end
`w16: // aluwor AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
end
`w32: // aluwor AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
end
default:
begin
// aluwor AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwor AND `ll
begin
case(ctrl_ww)
`w8: // aluwor AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwor AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwor AND Default
begin
result<=128'd0;
end
endcase
end
// ========================================================
// XOR instruction
`aluwxor:
begin
case(ctrl_ppp)
`aa: // aluwxor AND `aa
begin
case(ctrl_ww)
`w8: // aluwxor AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[32:63]<=reg_A[32:63]^reg_B[32:63];
result[64:95]<=reg_A[64:95]^reg_B[64:95];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default: // aluwxor AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwxor AND `uu
begin
case(ctrl_ww)
`w8: // aluwxor AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
end
`w16: // aluwxor AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
end
`w32: // aluwxor AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[32:63]<=reg_A[32:63]^reg_B[32:63];
end
default:
begin
// aluwxor AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwxor AND `dd
begin
case(ctrl_ww)
`w8: // aluwxor AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]^reg_B[64:95];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default:
begin
// aluwxor AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwxor AND `ee
begin
case(ctrl_ww)
`w8: // aluwxor AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
end
`w16: // aluwxor AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
end
`w32: // aluwxor AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[64:95]<=reg_A[64:95]^reg_B[64:95];
end
default:
begin
// aluwxor AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwxor AND `oo
begin
case(ctrl_ww)
`w8: // aluwxor AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]^reg_B[32:63];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default:
begin
// aluwxor AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwxor AND `mm
begin
case(ctrl_ww)
`w8: // aluwxor AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
end
`w16: // aluwxor AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
end
`w32: // aluwxor AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
end
default:
begin
// aluwxor AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwxor AND `ll
begin
case(ctrl_ww)
`w8: // aluwxor AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default:
begin
// aluwxor AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwxor AND Default
begin
result<=128'd0;
end
endcase
end
// ======================================================
// SUB instruction
`aluwsub:
begin
case(ctrl_ppp)
`aa: // aluwsub AND `aa
begin
case(ctrl_ww)
`w8: // aluwsub AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[32:63]<=reg_A[32:63]-reg_B[32:63];
result[64:95]<=reg_A[64:95]-reg_B[64:95];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default: // aluwsub AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwsub AND `uu
begin
case(ctrl_ww)
`w8: // aluwsub AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
end
`w16: // aluwsub AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
end
`w32: // aluwsub AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[32:63]<=reg_A[32:63]-reg_B[32:63];
end
default:
begin
// aluwsub AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwsub AND `dd
begin
case(ctrl_ww)
`w8: // aluwsub AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]-reg_B[64:95];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default:
begin
// aluwsub AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwsub AND `ee
begin
case(ctrl_ww)
`w8: // aluwsub AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
end
`w16: // aluwsub AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
end
`w32: // aluwsub AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[64:95]<=reg_A[64:95]-reg_B[64:95];
end
default:
begin
// aluwsub AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwsub AND `oo
begin
case(ctrl_ww)
`w8: // aluwsub AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]-reg_B[32:63];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default:
begin
// aluwsub AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwsub AND `mm
begin
case(ctrl_ww)
`w8: // aluwsub AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
end
`w16: // aluwsub AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
end
`w32: // aluwsub AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
end
default:
begin
// aluwsub AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwsub AND `ll
begin
case(ctrl_ww)
`w8: // aluwsub AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default:
begin
// aluwsub AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwsub AND Default
begin
result<=128'd0;
end
endcase
end
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
// ================================================
// PRM instruction
`aluwprm:
begin
case(ctrl_ppp)
`aa: // aluwprm PRM `aa
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[112:119];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
`uu: // aluwprm PRM `uu
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
//bytes8-15
result[64:127]<=64'd0;
end
`dd: // aluwprm PRM `dd
begin
//bytes0-7
result[0:63]<=64'd0;
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[0:7];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
`ee: // aluwprm PRM `ee
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
//byte1
result[8:15]<=8'd0;
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
//byte3
result[24:31]<=8'd0;
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
//byte5
result[40:47]<=8'd0;
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
//byte7
result[56:63]<=8'd0;
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
//byte9
result[72:79]<=8'd0;
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
//byte11
result[88:95]<=8'd0;
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
//byte13
result[104:111]<=8'd0;
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[112:119];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
//byte15
result[120:127]<=8'd0;
end
`oo: // aluwprm PRM `oo
begin
//byte0
result[0:7]<=8'd0;
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
//byte2
result[16:23]<=8'd0;
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
//byte4
result[32:39]<=8'd0;
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
//byte6
result[48:55]<=8'd0;
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
//byte8
result[64:71]<=8'd0;
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
//byte10
result[80:87]<=8'd0;
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
//byte12
result[96:103]<=8'd0;
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
//byte14
result[112:119]<=8'd0;
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
`mm: // aluwprm PRM `mm
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
//bytes1-14
result[8:127]<=120'd0;
end
`ll: // aluwprm PRM `ll
begin
//bytes0-14
result[0:119]<=120'd0;
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
default: // aluwprm PRM Default
begin
result<=128'd0;
end
endcase
end
/*
* ========================================================
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*/
// ================================================
// SLLI instruction
`aluwslli:
begin
case(ctrl_ppp)
`aa: // aluwslli SLLI `aa
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:15]<={reg_A[9:15],{1'b0}};
result[16:23]<={reg_A[17:23],{1'b0}};
result[24:31]<={reg_A[25:31],{1'b0}};
result[32:39]<={reg_A[33:39],{1'b0}};
result[40:47]<={reg_A[41:47],{1'b0}};
result[48:55]<={reg_A[49:55],{1'b0}};
result[56:63]<={reg_A[57:63],{1'b0}};
result[64:71]<={reg_A[65:71],{1'b0}};
result[72:79]<={reg_A[73:79],{1'b0}};
result[80:87]<={reg_A[81:87],{1'b0}};
result[88:95]<={reg_A[89:95],{1'b0}};
result[96:103]<={reg_A[97:103],{1'b0}};
result[104:111]<={reg_A[105:111],{1'b0}};
result[112:119]<={reg_A[113:119],{1'b0}};
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:15]<={reg_A[10:15],{2{1'b0}}};
result[16:23]<={reg_A[18:23],{2{1'b0}}};
result[24:31]<={reg_A[26:31],{2{1'b0}}};
result[32:39]<={reg_A[34:39],{2{1'b0}}};
result[40:47]<={reg_A[42:47],{2{1'b0}}};
result[48:55]<={reg_A[50:55],{2{1'b0}}};
result[56:63]<={reg_A[58:63],{2{1'b0}}};
result[64:71]<={reg_A[66:71],{2{1'b0}}};
result[72:79]<={reg_A[74:79],{2{1'b0}}};
result[80:87]<={reg_A[82:87],{2{1'b0}}};
result[88:95]<={reg_A[90:95],{2{1'b0}}};
result[96:103]<={reg_A[98:103],{2{1'b0}}};
result[104:111]<={reg_A[106:111],{2{1'b0}}};
result[112:119]<={reg_A[114:119],{2{1'b0}}};
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:15]<={reg_A[11:15],{3{1'b0}}};
result[16:23]<={reg_A[19:23],{3{1'b0}}};
result[24:31]<={reg_A[27:31],{3{1'b0}}};
result[32:39]<={reg_A[35:39],{3{1'b0}}};
result[40:47]<={reg_A[43:47],{3{1'b0}}};
result[48:55]<={reg_A[51:55],{3{1'b0}}};
result[56:63]<={reg_A[59:63],{3{1'b0}}};
result[64:71]<={reg_A[67:71],{3{1'b0}}};
result[72:79]<={reg_A[75:79],{3{1'b0}}};
result[80:87]<={reg_A[83:87],{3{1'b0}}};
result[88:95]<={reg_A[91:95],{3{1'b0}}};
result[96:103]<={reg_A[99:103],{3{1'b0}}};
result[104:111]<={reg_A[107:111],{3{1'b0}}};
result[112:119]<={reg_A[115:119],{3{1'b0}}};
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:15]<={reg_A[12:15],{4{1'b0}}};
result[16:23]<={reg_A[20:23],{4{1'b0}}};
result[24:31]<={reg_A[28:31],{4{1'b0}}};
result[32:39]<={reg_A[36:39],{4{1'b0}}};
result[40:47]<={reg_A[44:47],{4{1'b0}}};
result[48:55]<={reg_A[52:55],{4{1'b0}}};
result[56:63]<={reg_A[60:63],{4{1'b0}}};
result[64:71]<={reg_A[68:71],{4{1'b0}}};
result[72:79]<={reg_A[76:79],{4{1'b0}}};
result[80:87]<={reg_A[84:87],{4{1'b0}}};
result[88:95]<={reg_A[92:95],{4{1'b0}}};
result[96:103]<={reg_A[100:103],{4{1'b0}}};
result[104:111]<={reg_A[108:111],{4{1'b0}}};
result[112:119]<={reg_A[116:119],{4{1'b0}}};
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:15]<={reg_A[13:15],{5{1'b0}}};
result[16:23]<={reg_A[21:23],{5{1'b0}}};
result[24:31]<={reg_A[29:31],{5{1'b0}}};
result[32:39]<={reg_A[37:39],{5{1'b0}}};
result[40:47]<={reg_A[45:47],{5{1'b0}}};
result[48:55]<={reg_A[53:55],{5{1'b0}}};
result[56:63]<={reg_A[61:63],{5{1'b0}}};
result[64:71]<={reg_A[69:71],{5{1'b0}}};
result[72:79]<={reg_A[77:79],{5{1'b0}}};
result[80:87]<={reg_A[85:87],{5{1'b0}}};
result[88:95]<={reg_A[93:95],{5{1'b0}}};
result[96:103]<={reg_A[101:103],{5{1'b0}}};
result[104:111]<={reg_A[109:111],{5{1'b0}}};
result[112:119]<={reg_A[117:119],{5{1'b0}}};
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:15]<={reg_A[14:15],{6{1'b0}}};
result[16:23]<={reg_A[22:23],{6{1'b0}}};
result[24:31]<={reg_A[30:31],{6{1'b0}}};
result[32:39]<={reg_A[38:39],{6{1'b0}}};
result[40:47]<={reg_A[46:47],{6{1'b0}}};
result[48:55]<={reg_A[54:55],{6{1'b0}}};
result[56:63]<={reg_A[62:63],{6{1'b0}}};
result[64:71]<={reg_A[70:71],{6{1'b0}}};
result[72:79]<={reg_A[78:79],{6{1'b0}}};
result[80:87]<={reg_A[86:87],{6{1'b0}}};
result[88:95]<={reg_A[94:95],{6{1'b0}}};
result[96:103]<={reg_A[102:103],{6{1'b0}}};
result[104:111]<={reg_A[110:111],{6{1'b0}}};
result[112:119]<={reg_A[118:119],{6{1'b0}}};
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:15]<={reg_A[15],{7{1'b0}}};
result[16:23]<={reg_A[23],{7{1'b0}}};
result[24:31]<={reg_A[31],{7{1'b0}}};
result[32:39]<={reg_A[39],{7{1'b0}}};
result[40:47]<={reg_A[47],{7{1'b0}}};
result[48:55]<={reg_A[55],{7{1'b0}}};
result[56:63]<={reg_A[63],{7{1'b0}}};
result[64:71]<={reg_A[71],{7{1'b0}}};
result[72:79]<={reg_A[79],{7{1'b0}}};
result[80:87]<={reg_A[87],{7{1'b0}}};
result[88:95]<={reg_A[95],{7{1'b0}}};
result[96:103]<={reg_A[103],{7{1'b0}}};
result[104:111]<={reg_A[111],{7{1'b0}}};
result[112:119]<={reg_A[119],{7{1'b0}}};
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:31]<={reg_A[17:31],{1'b0}};
result[32:47]<={reg_A[33:47],{1'b0}};
result[48:63]<={reg_A[49:63],{1'b0}};
result[64:79]<={reg_A[65:79],{1'b0}};
result[80:95]<={reg_A[81:95],{1'b0}};
result[96:111]<={reg_A[97:111],{1'b0}};
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:31]<={reg_A[18:31],{2{1'b0}}};
result[32:47]<={reg_A[34:47],{2{1'b0}}};
result[48:63]<={reg_A[50:63],{2{1'b0}}};
result[64:79]<={reg_A[66:79],{2{1'b0}}};
result[80:95]<={reg_A[82:95],{2{1'b0}}};
result[96:111]<={reg_A[98:111],{2{1'b0}}};
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:31]<={reg_A[19:31],{3{1'b0}}};
result[32:47]<={reg_A[35:47],{3{1'b0}}};
result[48:63]<={reg_A[51:63],{3{1'b0}}};
result[64:79]<={reg_A[67:79],{3{1'b0}}};
result[80:95]<={reg_A[83:95],{3{1'b0}}};
result[96:111]<={reg_A[99:111],{3{1'b0}}};
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:31]<={reg_A[20:31],{4{1'b0}}};
result[32:47]<={reg_A[36:47],{4{1'b0}}};
result[48:63]<={reg_A[52:63],{4{1'b0}}};
result[64:79]<={reg_A[68:79],{4{1'b0}}};
result[80:95]<={reg_A[84:95],{4{1'b0}}};
result[96:111]<={reg_A[100:111],{4{1'b0}}};
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:31]<={reg_A[21:31],{5{1'b0}}};
result[32:47]<={reg_A[37:47],{5{1'b0}}};
result[48:63]<={reg_A[52:63],{5{1'b0}}};
result[64:79]<={reg_A[69:79],{5{1'b0}}};
result[80:95]<={reg_A[85:95],{5{1'b0}}};
result[96:111]<={reg_A[101:111],{5{1'b0}}};
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:31]<={reg_A[22:31],{6{1'b0}}};
result[32:47]<={reg_A[38:47],{6{1'b0}}};
result[48:63]<={reg_A[53:63],{6{1'b0}}};
result[64:79]<={reg_A[70:79],{6{1'b0}}};
result[80:95]<={reg_A[86:95],{6{1'b0}}};
result[96:111]<={reg_A[102:111],{6{1'b0}}};
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:31]<={reg_A[23:31],{7{1'b0}}};
result[32:47]<={reg_A[39:47],{7{1'b0}}};
result[48:63]<={reg_A[54:63],{7{1'b0}}};
result[64:79]<={reg_A[71:79],{7{1'b0}}};
result[80:95]<={reg_A[87:95],{7{1'b0}}};
result[96:111]<={reg_A[103:111],{7{1'b0}}};
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:31]<={reg_A[24:31],{8{1'b0}}};
result[32:47]<={reg_A[40:47],{8{1'b0}}};
result[48:63]<={reg_A[55:63],{8{1'b0}}};
result[64:79]<={reg_A[72:79],{8{1'b0}}};
result[80:95]<={reg_A[88:95],{8{1'b0}}};
result[96:111]<={reg_A[104:111],{8{1'b0}}};
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:31]<={reg_A[25:31],{9{1'b0}}};
result[32:47]<={reg_A[41:47],{9{1'b0}}};
result[48:63]<={reg_A[56:63],{9{1'b0}}};
result[64:79]<={reg_A[73:79],{9{1'b0}}};
result[80:95]<={reg_A[89:95],{9{1'b0}}};
result[96:111]<={reg_A[105:111],{9{1'b0}}};
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:31]<={reg_A[26:31],{10{1'b0}}};
result[32:47]<={reg_A[42:47],{10{1'b0}}};
result[48:63]<={reg_A[58:63],{10{1'b0}}};
result[64:79]<={reg_A[74:79],{10{1'b0}}};
result[80:95]<={reg_A[90:95],{10{1'b0}}};
result[96:111]<={reg_A[106:111],{10{1'b0}}};
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:31]<={reg_A[27:31],{11{1'b0}}};
result[32:47]<={reg_A[43:47],{11{1'b0}}};
result[48:63]<={reg_A[59:63],{11{1'b0}}};
result[64:79]<={reg_A[75:79],{11{1'b0}}};
result[80:95]<={reg_A[91:95],{11{1'b0}}};
result[96:111]<={reg_A[107:111],{11{1'b0}}};
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:31]<={reg_A[28:31],{12{1'b0}}};
result[32:47]<={reg_A[44:47],{12{1'b0}}};
result[48:63]<={reg_A[60:63],{12{1'b0}}};
result[64:79]<={reg_A[76:79],{12{1'b0}}};
result[80:95]<={reg_A[92:95],{12{1'b0}}};
result[96:111]<={reg_A[108:111],{12{1'b0}}};
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:31]<={reg_A[29:31],{13{1'b0}}};
result[32:47]<={reg_A[45:47],{13{1'b0}}};
result[48:63]<={reg_A[61:63],{13{1'b0}}};
result[64:79]<={reg_A[77:79],{13{1'b0}}};
result[80:95]<={reg_A[93:95],{13{1'b0}}};
result[96:111]<={reg_A[109:111],{13{1'b0}}};
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:31]<={reg_A[30:31],{14{1'b0}}};
result[32:47]<={reg_A[46:47],{14{1'b0}}};
result[48:63]<={reg_A[62:63],{14{1'b0}}};
result[64:79]<={reg_A[78:79],{14{1'b0}}};
result[80:95]<={reg_A[94:95],{14{1'b0}}};
result[96:111]<={reg_A[110:111],{14{1'b0}}};
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:31]<={reg_A[31],{15{1'b0}}};
result[32:47]<={reg_A[47],{15{1'b0}}};
result[48:63]<={reg_A[63],{15{1'b0}}};
result[64:79]<={reg_A[79],{15{1'b0}}};
result[80:95]<={reg_A[95],{15{1'b0}}};
result[96:111]<={reg_A[111],{15{1'b0}}};
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:63]<={reg_A[33:63],{1'b0}};
result[64:95]<={reg_A[65:95],{1'b0}};
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:63]<={reg_A[34:63],{2{1'b0}}};
result[64:95]<={reg_A[66:95],{2{1'b0}}};
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:63]<={reg_A[35:63],{3{1'b0}}};
result[64:95]<={reg_A[67:95],{3{1'b0}}};
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:63]<={reg_A[36:63],{4{1'b0}}};
result[64:95]<={reg_A[68:95],{4{1'b0}}};
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:63]<={reg_A[37:63],{5{1'b0}}};
result[64:95]<={reg_A[69:95],{5{1'b0}}};
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:63]<={reg_A[38:63],{6{1'b0}}};
result[64:95]<={reg_A[70:95],{6{1'b0}}};
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:63]<={reg_A[39:63],{7{1'b0}}};
result[64:95]<={reg_A[71:95],{7{1'b0}}};
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:63]<={reg_A[40:63],{8{1'b0}}};
result[64:95]<={reg_A[72:95],{8{1'b0}}};
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9:
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:63]<={reg_A[41:63],{9{1'b0}}};
result[64:95]<={reg_A[73:95],{9{1'b0}}};
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:63]<={reg_A[42:63],{10{1'b0}}};
result[64:95]<={reg_A[74:95],{10{1'b0}}};
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}}};
result[32:63]<={reg_A[43:63],{11{1'b0}}};
result[64:95]<={reg_A[75:95],{11{1'b0}}};
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:63]<={reg_A[44:63],{12{1'b0}}};
result[64:95]<={reg_A[76:95],{12{1'b0}}};
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:63]<={reg_A[45:63],{13{1'b0}}};
result[64:95]<={reg_A[77:95],{13{1'b0}}};
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:63]<={reg_A[46:63],{14{1'b0}}};
result[64:95]<={reg_A[78:95],{14{1'b0}}};
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:63]<={reg_A[47:63],{15{1'b0}}};
result[64:95]<={reg_A[79:95],{15{1'b0}}};
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:63]<={reg_A[48:63],{16{1'b0}}};
result[64:95]<={reg_A[80:95],{16{1'b0}}};
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:63]<={reg_A[49:63],{17{1'b0}}};
result[64:95]<={reg_A[81:95],{17{1'b0}}};
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:63]<={reg_A[50:63],{18{1'b0}}};
result[64:95]<={reg_A[82:95],{18{1'b0}}};
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19:
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:63]<={reg_A[51:63],{19{1'b0}}};
result[64:95]<={reg_A[83:95],{19{1'b0}}};
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:63]<={reg_A[52:63],{20{1'b0}}};
result[64:95]<={reg_A[84:95],{20{1'b0}}};
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:63]<={reg_A[53:63],{21{1'b0}}};
result[64:95]<={reg_A[85:95],{21{1'b0}}};
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:63]<={reg_A[54:63],{22{1'b0}}};
result[64:95]<={reg_A[86:95],{22{1'b0}}};
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:63]<={reg_A[55:63],{23{1'b0}}};
result[64:95]<={reg_A[87:95],{23{1'b0}}};
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:63]<={reg_A[56:63],{24{1'b0}}};
result[64:95]<={reg_A[88:95],{24{1'b0}}};
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:63]<={reg_A[57:63],{25{1'b0}}};
result[64:95]<={reg_A[89:95],{25{1'b0}}};
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:63]<={reg_A[58:63],{26{1'b0}}};
result[64:95]<={reg_A[90:95],{26{1'b0}}};
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:63]<={reg_A[59:63],{27{1'b0}}};
result[64:95]<={reg_A[91:95],{27{1'b0}}};
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:63]<={reg_A[60:63],{28{1'b0}}};
result[64:95]<={reg_A[92:95],{28{1'b0}}};
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29:
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:63]<={reg_A[61:63],{29{1'b0}}};
result[64:95]<={reg_A[93:95],{29{1'b0}}};
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:63]<={reg_A[62:63],{30{1'b0}}};
result[64:95]<={reg_A[94:95],{30{1'b0}}};
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:63]<={reg_A[63],{31{1'b0}}};
result[64:95]<={reg_A[95],{31{1'b0}}};
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
endcase
end
`uu: // aluwslli SLLI `uu
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:63]<=reg_A[0:63];
result[64:127]<=64'd0;
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:15]<={reg_A[9:15],{1'b0}};
result[16:23]<={reg_A[17:23],{1'b0}};
result[24:31]<={reg_A[25:31],{1'b0}};
result[32:39]<={reg_A[33:39],{1'b0}};
result[40:47]<={reg_A[41:47],{1'b0}};
result[48:55]<={reg_A[49:55],{1'b0}};
result[56:63]<={reg_A[57:63],{1'b0}};
result[64:127]<=64'd0;
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:15]<={reg_A[10:15],{2{1'b0}}};
result[16:23]<={reg_A[18:23],{2{1'b0}}};
result[24:31]<={reg_A[26:31],{2{1'b0}}};
result[32:39]<={reg_A[34:39],{2{1'b0}}};
result[40:47]<={reg_A[42:47],{2{1'b0}}};
result[48:55]<={reg_A[50:55],{2{1'b0}}};
result[56:63]<={reg_A[58:63],{2{1'b0}}};
result[64:127]<=64'd0;
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:15]<={reg_A[11:15],{3{1'b0}}};
result[16:23]<={reg_A[19:23],{3{1'b0}}};
result[24:31]<={reg_A[27:31],{3{1'b0}}};
result[32:39]<={reg_A[35:39],{3{1'b0}}};
result[40:47]<={reg_A[43:47],{3{1'b0}}};
result[48:55]<={reg_A[51:55],{3{1'b0}}};
result[56:63]<={reg_A[59:63],{3{1'b0}}};
result[64:127]<=64'd0;
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:15]<={reg_A[12:15],{4{1'b0}}};
result[16:23]<={reg_A[20:23],{4{1'b0}}};
result[24:31]<={reg_A[28:31],{4{1'b0}}};
result[32:39]<={reg_A[36:39],{4{1'b0}}};
result[40:47]<={reg_A[44:47],{4{1'b0}}};
result[48:55]<={reg_A[52:55],{4{1'b0}}};
result[56:63]<={reg_A[60:63],{4{1'b0}}};
result[64:127]<=64'd0;
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:15]<={reg_A[13:15],{5{1'b0}}};
result[16:23]<={reg_A[21:23],{5{1'b0}}};
result[24:31]<={reg_A[29:31],{5{1'b0}}};
result[32:39]<={reg_A[37:39],{5{1'b0}}};
result[40:47]<={reg_A[45:47],{5{1'b0}}};
result[48:55]<={reg_A[53:55],{5{1'b0}}};
result[56:63]<={reg_A[61:63],{5{1'b0}}};
result[64:127]<=64'd0;
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:15]<={reg_A[14:15],{6{1'b0}}};
result[16:23]<={reg_A[22:23],{6{1'b0}}};
result[24:31]<={reg_A[30:31],{6{1'b0}}};
result[32:39]<={reg_A[38:39],{6{1'b0}}};
result[40:47]<={reg_A[46:47],{6{1'b0}}};
result[48:55]<={reg_A[54:55],{6{1'b0}}};
result[56:63]<={reg_A[62:63],{6{1'b0}}};
result[64:127]<=64'd0;
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:15]<={reg_A[15],{7{1'b0}}};
result[16:23]<={reg_A[23],{7{1'b0}}};
result[24:31]<={reg_A[31],{7{1'b0}}};
result[32:39]<={reg_A[39],{7{1'b0}}};
result[40:47]<={reg_A[47],{7{1'b0}}};
result[48:55]<={reg_A[55],{7{1'b0}}};
result[56:63]<={reg_A[63],{7{1'b0}}};
result[64:127]<=64'd0;
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:63]<=reg_A[0:63];
result[64:127]<=64'd0;
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:31]<={reg_A[17:31],{1'b0}};
result[32:47]<={reg_A[33:47],{1'b0}};
result[48:63]<={reg_A[49:63],{1'b0}};
result[64:127]<=64'd0;
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:31]<={reg_A[18:31],{2{1'b0}}};
result[32:47]<={reg_A[34:47],{2{1'b0}}};
result[48:63]<={reg_A[50:63],{2{1'b0}}};
result[64:127]<=64'd0;
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:31]<={reg_A[19:31],{3{1'b0}}};
result[32:47]<={reg_A[35:47],{3{1'b0}}};
result[48:63]<={reg_A[51:63],{3{1'b0}}};
result[64:127]<=64'd0;
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:31]<={reg_A[20:31],{4{1'b0}}};
result[32:47]<={reg_A[36:47],{4{1'b0}}};
result[48:63]<={reg_A[52:63],{4{1'b0}}};
result[64:127]<=64'd0;
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:31]<={reg_A[21:31],{5{1'b0}}};
result[32:47]<={reg_A[37:47],{5{1'b0}}};
result[48:63]<={reg_A[52:63],{5{1'b0}}};
result[64:127]<=64'd0;
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:31]<={reg_A[22:31],{6{1'b0}}};
result[32:47]<={reg_A[38:47],{6{1'b0}}};
result[48:63]<={reg_A[53:63],{6{1'b0}}};
result[64:127]<=64'd0;
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:31]<={reg_A[23:31],{7{1'b0}}};
result[32:47]<={reg_A[39:47],{7{1'b0}}};
result[48:63]<={reg_A[54:63],{7{1'b0}}};
result[64:127]<=64'd0;
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:31]<={reg_A[24:31],{8{1'b0}}};
result[32:47]<={reg_A[40:47],{8{1'b0}}};
result[48:63]<={reg_A[55:63],{8{1'b0}}};
result[64:127]<=64'd0;
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:31]<={reg_A[25:31],{9{1'b0}}};
result[32:47]<={reg_A[41:47],{9{1'b0}}};
result[48:63]<={reg_A[56:63],{9{1'b0}}};
result[64:127]<=64'd0;
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:31]<={reg_A[26:31],{10{1'b0}}};
result[32:47]<={reg_A[42:47],{10{1'b0}}};
result[48:63]<={reg_A[58:63],{10{1'b0}}};
result[64:127]<=64'd0;
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:31]<={reg_A[27:31],{11{1'b0}}};
result[32:47]<={reg_A[43:47],{11{1'b0}}};
result[48:63]<={reg_A[59:63],{11{1'b0}}};
result[64:127]<=64'd0;
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:31]<={reg_A[28:31],{12{1'b0}}};
result[32:47]<={reg_A[44:47],{12{1'b0}}};
result[48:63]<={reg_A[60:63],{12{1'b0}}};
result[64:127]<=64'd0;
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:31]<={reg_A[29:31],{13{1'b0}}};
result[32:47]<={reg_A[45:47],{13{1'b0}}};
result[48:63]<={reg_A[61:63],{13{1'b0}}};
result[64:127]<=64'd0;
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:31]<={reg_A[30:31],{14{1'b0}}};
result[32:47]<={reg_A[46:47],{14{1'b0}}};
result[48:63]<={reg_A[62:63],{14{1'b0}}};
result[64:127]<=64'd0;
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:31]<={reg_A[31],{15{1'b0}}};
result[32:47]<={reg_A[47],{15{1'b0}}};
result[48:63]<={reg_A[63],{15{1'b0}}};
result[64:127]<=64'd0;
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:63]<=reg_A[0:63];
result[64:127]<=64'd0;
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:63]<={reg_A[33:63],{1'b0}};
result[64:127]<=64'd0;
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:63]<={reg_A[34:63],{2{1'b0}}};
result[64:127]<=64'd0;
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:63]<={reg_A[35:63],{3{1'b0}}};
result[64:127]<=64'd0;
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:63]<={reg_A[36:63],{4{1'b0}}};
result[64:127]<=64'd0;
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:63]<={reg_A[37:63],{5{1'b0}}};
result[64:127]<=64'd0;
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:63]<={reg_A[38:63],{6{1'b0}}};
result[64:127]<=64'd0;
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:63]<={reg_A[39:63],{7{1'b0}}};
result[64:127]<=64'd0;
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:63]<={reg_A[40:63],{8{1'b0}}};
result[64:127]<=64'd0;
end
5'd9:
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:63]<={reg_A[41:63],{9{1'b0}}};
result[64:127]<=64'd0;
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:63]<={reg_A[42:63],{10{1'b0}}};
result[64:127]<=64'd0;
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}}};
result[32:63]<={reg_A[43:63],{11{1'b0}}};
result[64:95]<={reg_A[75:95],{11{1'b0}}};
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:63]<={reg_A[44:63],{12{1'b0}}};
result[64:127]<=64'd0;
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:63]<={reg_A[45:63],{13{1'b0}}};
result[64:127]<=64'd0;
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:63]<={reg_A[46:63],{14{1'b0}}};
result[64:127]<=64'd0;
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:63]<={reg_A[47:63],{15{1'b0}}};
result[64:127]<=64'd0;
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:63]<={reg_A[48:63],{16{1'b0}}};
result[64:127]<=64'd0;
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:63]<={reg_A[49:63],{17{1'b0}}};
result[64:127]<=64'd0;
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:63]<={reg_A[50:63],{18{1'b0}}};
result[64:127]<=64'd0;
end
5'd19:
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:63]<={reg_A[51:63],{19{1'b0}}};
result[64:127]<=64'd0;
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:63]<={reg_A[52:63],{20{1'b0}}};
result[64:127]<=64'd0;
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:63]<={reg_A[53:63],{21{1'b0}}};
result[64:127]<=64'd0;
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:63]<={reg_A[54:63],{22{1'b0}}};
result[64:127]<=64'd0;
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:63]<={reg_A[55:63],{23{1'b0}}};
result[64:127]<=64'd0;
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:63]<={reg_A[56:63],{24{1'b0}}};
result[64:127]<=64'd0;
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:63]<={reg_A[57:63],{25{1'b0}}};
result[64:127]<=64'd0;
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:63]<={reg_A[58:63],{26{1'b0}}};
result[64:127]<=64'd0;
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:63]<={reg_A[59:63],{27{1'b0}}};
result[64:127]<=64'd0;
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:63]<={reg_A[60:63],{28{1'b0}}};
result[64:127]<=64'd0;
end
5'd29:
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:63]<={reg_A[61:63],{29{1'b0}}};
result[64:127]<=64'd0;
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:63]<={reg_A[62:63],{30{1'b0}}};
result[64:127]<=64'd0;
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:63]<={reg_A[63],{31{1'b0}}};
result[64:127]<=64'd0;
end
endcase
end
endcase
end
`dd: // aluwslli SLLI `dd
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:63]<=64'd0;
result[64:127]<=reg_A[64:127];
end
3'd1:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[65:71],{1'b0}};
result[72:79]<={reg_A[73:79],{1'b0}};
result[80:87]<={reg_A[81:87],{1'b0}};
result[88:95]<={reg_A[89:95],{1'b0}};
result[96:103]<={reg_A[97:103],{1'b0}};
result[104:111]<={reg_A[105:111],{1'b0}};
result[112:119]<={reg_A[113:119],{1'b0}};
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[66:71],{2{1'b0}}};
result[72:79]<={reg_A[74:79],{2{1'b0}}};
result[80:87]<={reg_A[82:87],{2{1'b0}}};
result[88:95]<={reg_A[90:95],{2{1'b0}}};
result[96:103]<={reg_A[98:103],{2{1'b0}}};
result[104:111]<={reg_A[106:111],{2{1'b0}}};
result[112:119]<={reg_A[114:119],{2{1'b0}}};
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[67:71],{3{1'b0}}};
result[72:79]<={reg_A[75:79],{3{1'b0}}};
result[80:87]<={reg_A[83:87],{3{1'b0}}};
result[88:95]<={reg_A[91:95],{3{1'b0}}};
result[96:103]<={reg_A[99:103],{3{1'b0}}};
result[104:111]<={reg_A[107:111],{3{1'b0}}};
result[112:119]<={reg_A[115:119],{3{1'b0}}};
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[68:71],{4{1'b0}}};
result[72:79]<={reg_A[76:79],{4{1'b0}}};
result[80:87]<={reg_A[84:87],{4{1'b0}}};
result[88:95]<={reg_A[92:95],{4{1'b0}}};
result[96:103]<={reg_A[100:103],{4{1'b0}}};
result[104:111]<={reg_A[108:111],{4{1'b0}}};
result[112:119]<={reg_A[116:119],{4{1'b0}}};
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[69:71],{5{1'b0}}};
result[72:79]<={reg_A[77:79],{5{1'b0}}};
result[80:87]<={reg_A[85:87],{5{1'b0}}};
result[88:95]<={reg_A[93:95],{5{1'b0}}};
result[96:103]<={reg_A[101:103],{5{1'b0}}};
result[104:111]<={reg_A[109:111],{5{1'b0}}};
result[112:119]<={reg_A[117:119],{5{1'b0}}};
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[70:71],{6{1'b0}}};
result[72:79]<={reg_A[78:79],{6{1'b0}}};
result[80:87]<={reg_A[86:87],{6{1'b0}}};
result[88:95]<={reg_A[94:95],{6{1'b0}}};
result[96:103]<={reg_A[102:103],{6{1'b0}}};
result[104:111]<={reg_A[110:111],{6{1'b0}}};
result[112:119]<={reg_A[118:119],{6{1'b0}}};
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[71],{7{1'b0}}};
result[72:79]<={reg_A[79],{7{1'b0}}};
result[80:87]<={reg_A[87],{7{1'b0}}};
result[88:95]<={reg_A[95],{7{1'b0}}};
result[96:103]<={reg_A[103],{7{1'b0}}};
result[104:111]<={reg_A[111],{7{1'b0}}};
result[112:119]<={reg_A[119],{7{1'b0}}};
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:63]<=64'd0;
result[64:127]<=reg_A[64:127];
end
4'd1:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[65:79],{1'b0}};
result[80:95]<={reg_A[81:95],{1'b0}};
result[96:111]<={reg_A[97:111],{1'b0}};
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[66:79],{2{1'b0}}};
result[80:95]<={reg_A[82:95],{2{1'b0}}};
result[96:111]<={reg_A[98:111],{2{1'b0}}};
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[67:79],{3{1'b0}}};
result[80:95]<={reg_A[83:95],{3{1'b0}}};
result[96:111]<={reg_A[99:111],{3{1'b0}}};
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[68:79],{4{1'b0}}};
result[80:95]<={reg_A[84:95],{4{1'b0}}};
result[96:111]<={reg_A[100:111],{4{1'b0}}};
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[69:79],{5{1'b0}}};
result[80:95]<={reg_A[85:95],{5{1'b0}}};
result[96:111]<={reg_A[101:111],{5{1'b0}}};
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[70:79],{6{1'b0}}};
result[80:95]<={reg_A[86:95],{6{1'b0}}};
result[96:111]<={reg_A[102:111],{6{1'b0}}};
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[71:79],{7{1'b0}}};
result[80:95]<={reg_A[87:95],{7{1'b0}}};
result[96:111]<={reg_A[103:111],{7{1'b0}}};
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[72:79],{8{1'b0}}};
result[80:95]<={reg_A[88:95],{8{1'b0}}};
result[96:111]<={reg_A[104:111],{8{1'b0}}};
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[73:79],{9{1'b0}}};
result[80:95]<={reg_A[89:95],{9{1'b0}}};
result[96:111]<={reg_A[105:111],{9{1'b0}}};
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[74:79],{10{1'b0}}};
result[80:95]<={reg_A[90:95],{10{1'b0}}};
result[96:111]<={reg_A[106:111],{10{1'b0}}};
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[75:79],{11{1'b0}}};
result[80:95]<={reg_A[91:95],{11{1'b0}}};
result[96:111]<={reg_A[107:111],{11{1'b0}}};
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[76:79],{12{1'b0}}};
result[80:95]<={reg_A[92:95],{12{1'b0}}};
result[96:111]<={reg_A[108:111],{12{1'b0}}};
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[77:79],{13{1'b0}}};
result[80:95]<={reg_A[93:95],{13{1'b0}}};
result[96:111]<={reg_A[109:111],{13{1'b0}}};
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[78:79],{14{1'b0}}};
result[80:95]<={reg_A[94:95],{14{1'b0}}};
result[96:111]<={reg_A[110:111],{14{1'b0}}};
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[79],{15{1'b0}}};
result[80:95]<={reg_A[95],{15{1'b0}}};
result[96:111]<={reg_A[111],{15{1'b0}}};
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:63]<=64'd0;
result[64:127]<=reg_A[64:127];
end
5'd1:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[65:95],{1'b0}};
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[66:95],{2{1'b0}}};
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[67:95],{3{1'b0}}};
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[68:95],{4{1'b0}}};
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[69:95],{5{1'b0}}};
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[70:95],{6{1'b0}}};
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[71:95],{7{1'b0}}};
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[72:95],{8{1'b0}}};
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[73:95],{9{1'b0}}};
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[74:95],{10{1'b0}}};
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[75:95],{11{1'b0}}};
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[76:95],{12{1'b0}}};
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[77:95],{13{1'b0}}};
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[78:95],{14{1'b0}}};
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[79:95],{15{1'b0}}};
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[80:95],{16{1'b0}}};
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[81:95],{17{1'b0}}};
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[82:95],{18{1'b0}}};
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[83:95],{19{1'b0}}};
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[84:95],{20{1'b0}}};
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[85:95],{21{1'b0}}};
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[86:95],{22{1'b0}}};
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[87:95],{23{1'b0}}};
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[88:95],{24{1'b0}}};
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[89:95],{25{1'b0}}};
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[90:95],{26{1'b0}}};
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[91:95],{27{1'b0}}};
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[92:95],{28{1'b0}}};
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[93:95],{29{1'b0}}};
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[94:95],{30{1'b0}}};
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[95],{31{1'b0}}};
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
endcase
end
`ee: // aluwslli SLLI `ee
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:7]<=reg_A[0:7];
result[8:15]<=8'b0;
result[16:23]<=reg_A[16:23];
result[24:31]<=8'b0;
result[32:39]<=reg_A[33:39];
result[40:47]<=8'b0;
result[48:55]<=reg_A[48:55];
result[56:63]<=8'b0;
result[64:71]<=reg_A[64:71];
result[72:79]<=8'b0;
result[80:87]<=reg_A[80:87];
result[88:95]<=8'b0;
result[96:103]<=reg_A[96:103];
result[104:111]<=8'b0;
result[112:119]<=reg_A[112:119];
result[120:127]<=8'b0;
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[17:23],{1'b0}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[33:39],{1'b0}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[49:55],{1'b0}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[65:71],{1'b0}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[81:87],{1'b0}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[97:103],{1'b0}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[113:119],{1'b0}};
result[120:127]<=8'b0;
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[18:23],{2{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[34:39],{2{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[50:55],{2{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[66:71],{2{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[82:87],{2{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[98:103],{2{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[114:119],{2{1'b0}}};
result[120:127]<=8'b0;
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[19:23],{3{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[35:39],{3{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[51:55],{3{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[67:71],{3{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[83:87],{3{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[99:103],{3{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[115:119],{3{1'b0}}};
result[120:127]<=8'b0;
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[20:23],{4{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[36:39],{4{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[52:55],{4{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[68:71],{4{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[84:87],{4{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[100:103],{4{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[116:119],{4{1'b0}}};
result[120:127]<=8'b0;
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[21:23],{5{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[37:39],{5{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[53:55],{5{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[69:71],{5{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[85:87],{5{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[101:103],{5{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[117:119],{5{1'b0}}};
result[120:127]<=8'b0;
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[22:23],{6{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[38:39],{6{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[54:55],{6{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[70:71],{6{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[86:87],{6{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[102:103],{6{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[118:119],{6{1'b0}}};
result[120:127]<=8'b0;
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[23],{7{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[39],{7{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[55],{7{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[71],{7{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[87],{7{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[103],{7{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[119],{7{1'b0}}};
result[120:127]<=8'b0;
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[33:47],{1'b0}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[65:79],{1'b0}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[97:111],{1'b0}};
result[112:127]<=16'b0;
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[34:47],{2{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[66:79],{2{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[98:111],{2{1'b0}}};
result[112:127]<=16'b0;
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[35:47],{3{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[67:79],{3{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[99:111],{3{1'b0}}};
result[112:127]<=16'b0;
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[36:47],{4{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[68:79],{4{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[100:111],{4{1'b0}}};
result[112:127]<=16'b0;
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[37:47],{5{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[69:79],{5{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[101:111],{5{1'b0}}};
result[112:127]<=16'b0;
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[38:47],{6{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[70:79],{6{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[102:111],{6{1'b0}}};
result[112:127]<=16'b0;
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[39:47],{7{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[71:79],{7{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[103:111],{7{1'b0}}};
result[112:127]<=16'b0;
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[40:47],{8{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[72:79],{8{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[104:111],{8{1'b0}}};
result[112:127]<=16'b0;
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[41:47],{9{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[73:79],{9{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[105:111],{9{1'b0}}};
result[112:127]<=16'b0;
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[42:47],{10{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[74:79],{10{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[106:111],{10{1'b0}}};
result[112:127]<=16'b0;
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[43:47],{11{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[75:79],{11{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[107:111],{11{1'b0}}};
result[112:127]<=16'b0;
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[44:47],{12{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[76:79],{12{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[108:111],{12{1'b0}}};
result[112:127]<=16'b0;
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[45:47],{13{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[77:79],{13{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[109:111],{13{1'b0}}};
result[112:127]<=16'b0;
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[46:47],{14{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[78:79],{14{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[110:111],{14{1'b0}}};
result[112:127]<=16'b0;
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[47],{15{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[79],{15{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[111],{15{1'b0}}};
result[112:127]<=16'b0;
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[65:95],{1'b0}};
result[96:127]<=32'b0;
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[66:95],{2{1'b0}}};
result[96:127]<=32'b0;
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[67:95],{3{1'b0}}};
result[96:127]<=32'b0;
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[68:95],{4{1'b0}}};
result[96:127]<=32'b0;
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[69:95],{5{1'b0}}};
result[96:127]<=32'b0;
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[70:95],{6{1'b0}}};
result[96:127]<=32'b0;
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[71:95],{7{1'b0}}};
result[96:127]<=32'b0;
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[72:95],{8{1'b0}}};
result[96:127]<=32'b0;
end
5'd9:
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[73:95],{9{1'b0}}};
result[96:127]<=32'b0;
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[74:95],{10{1'b0}}};
result[96:127]<=32'b0;
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[75:95],{11{1'b0}}};
result[96:127]<=32'b0;
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[76:95],{12{1'b0}}};
result[96:127]<=32'b0;
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[77:95],{13{1'b0}}};
result[96:127]<=32'b0;
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[78:95],{14{1'b0}}};
result[96:127]<=32'b0;
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[79:95],{15{1'b0}}};
result[96:127]<=32'b0;
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[80:95],{16{1'b0}}};
result[96:127]<=32'b0;
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[81:95],{17{1'b0}}};
result[96:127]<=32'b0;
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[82:95],{18{1'b0}}};
result[96:127]<=32'b0;
end
5'd19:
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[83:95],{19{1'b0}}};
result[96:127]<=32'b0;
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[84:95],{20{1'b0}}};
result[96:127]<=32'b0;
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[85:95],{21{1'b0}}};
result[96:127]<=32'b0;
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[86:95],{22{1'b0}}};
result[96:127]<=32'b0;
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[87:95],{23{1'b0}}};
result[96:127]<=32'b0;
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[88:95],{24{1'b0}}};
result[96:127]<=32'b0;
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[89:95],{25{1'b0}}};
result[96:127]<=32'b0;
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[90:95],{26{1'b0}}};
result[96:127]<=32'b0;
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[91:95],{27{1'b0}}};
result[96:127]<=32'b0;
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[92:95],{28{1'b0}}};
result[96:127]<=32'b0;
end
5'd29:
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[93:95],{29{1'b0}}};
result[96:127]<=32'b0;
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[94:95],{30{1'b0}}};
result[96:127]<=32'b0;
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[95],{31{1'b0}}};
result[96:127]<=32'b0;
end
endcase
end
endcase
end
`oo: // aluwslli SLLI `oo
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[9:15],{1'b0}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[25:31],{1'b0}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[41:47],{1'b0}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[57:63],{1'b0}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[73:79],{1'b0}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[89:95],{1'b0}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[105:111],{1'b0}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[10:15],{2{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[26:31],{2{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[42:47],{2{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[58:63],{2{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[74:79],{2{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[90:95],{2{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[106:111],{2{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[11:15],{3{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[27:31],{3{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[43:47],{3{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[59:63],{3{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[75:79],{3{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[91:95],{3{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[107:111],{3{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[12:15],{4{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[28:31],{4{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[44:47],{4{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[60:63],{4{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[76:79],{4{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[92:95],{4{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[108:111],{4{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[13:15],{5{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[29:31],{5{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[45:47],{5{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[61:63],{5{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[77:79],{5{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[93:95],{5{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[109:111],{5{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[14:15],{6{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[30:31],{6{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[46:47],{6{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[62:63],{6{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[78:79],{6{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[94:95],{6{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[110:111],{6{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[15],{7{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[31],{7{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[47],{7{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[63],{7{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[79],{7{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[95],{7{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[111],{7{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[17:31],{1'b0}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[49:63],{1'b0}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[81:95],{1'b0}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[18:31],{2{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[50:63],{2{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[82:95],{2{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[19:31],{3{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[51:63],{3{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[83:95],{3{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[20:31],{4{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[52:63],{4{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[84:95],{4{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[21:31],{5{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[52:63],{5{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[85:95],{5{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[22:31],{6{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[53:63],{6{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[86:95],{6{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[23:31],{7{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[54:63],{7{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[87:95],{7{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[24:31],{8{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[55:63],{8{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[88:95],{8{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[25:31],{9{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[56:63],{9{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[89:95],{9{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[26:31],{10{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[58:63],{10{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[90:95],{10{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[27:31],{11{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[59:63],{11{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[91:95],{11{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[28:31],{12{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[60:63],{12{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[92:95],{12{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[29:31],{13{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[61:63],{13{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[93:95],{13{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[30:31],{14{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[62:63],{14{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[94:95],{14{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[31],{15{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[63],{15{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[95],{15{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[33:63],{1'b0}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[34:63],{2{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[35:63],{3{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[36:63],{4{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[37:63],{5{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[38:63],{6{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[39:63],{7{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[40:63],{8{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[41:63],{9{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[42:63],{10{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[43:63],{11{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[44:63],{12{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[45:63],{13{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[46:63],{14{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[47:63],{15{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[48:63],{16{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[49:63],{17{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[50:63],{18{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[51:63],{19{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[52:63],{20{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[53:63],{21{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[54:63],{22{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[55:63],{23{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[56:63],{24{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[57:63],{25{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[58:63],{26{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[59:63],{27{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[60:63],{28{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[61:63],{29{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[62:63],{30{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[63],{31{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
endcase
end
`mm: // aluwslli SLLI `mm
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:7]<=reg_A[0:7];
result[8:127]<=119'b0;
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:127]<=119'b0;
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:127]<=119'b0;
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:127]<=119'b0;
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:127]<=119'b0;
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:127]<=119'b0;
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:127]<=119'b0;
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:127]<=119'b0;
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:15]<=reg_A[0:15];
result[16:127]<=112'b0;
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:127]<=112'b0;
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:127]<=112'b0;
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:127]<=112'b0;
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:127]<=112'b0;
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:127]<=112'b0;
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:127]<=112'b0;
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:127]<=112'b0;
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:127]<=112'b0;
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:127]<=112'b0;
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:127]<=112'b0;
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:127]<=112'b0;
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:127]<=112'b0;
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:127]<=112'b0;
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:127]<=112'b0;
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:127]<=112'b0;
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:31]<=reg_A[0:31];
result[32:127]<=96'b0;
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:127]<=96'b0;
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:127]<=96'b0;
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:127]<=96'b0;
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:127]<=96'b0;
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:127]<=96'b0;
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:127]<=96'b0;
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:127]<=96'b0;
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:127]<=96'b0;
end
5'd9:
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:127]<=96'b0;
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:127]<=96'b0;
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}}};
result[32:127]<=96'b0;
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:127]<=96'b0;
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:127]<=96'b0;
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:127]<=96'b0;
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:127]<=96'b0;
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:127]<=96'b0;
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:127]<=96'b0;
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:127]<=96'b0;
end
5'd19:
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:127]<=96'b0;
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:127]<=96'b0;
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:127]<=96'b0;
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:127]<=96'b0;
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:127]<=96'b0;
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:127]<=96'b0;
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:127]<=96'b0;
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:127]<=96'b0;
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:127]<=96'b0;
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:127]<=96'b0;
end
5'd29:
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:127]<=96'b0;
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:127]<=96'b0;
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:127]<=96'b0;
end
endcase
end
endcase
end
`ll: // aluwslli SLLI `ll
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:119]<=120'b0;
result[120:127]<=reg_A[120:127];
end
3'd1:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:111]<=112'b0;
result[112:127]<=reg_A[112:127];
end
4'd1:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:95]<=96'b0;
result[96:127]<=reg_A[96:127];
end
5'd1:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
endcase
end
endcase
end
default:
begin
// Default arithmetic/logic operation
result<=128'd0;
end
endcase
end
endmodule
|
module anteconmutador (
input clk,
input [7:0] d,
input DONE,
output reg [3:0] centenas,
output reg [3:0] decenas,
output reg [3:0] unidades,
output reg C,
output reg D,
output reg U
);
reg [7:0] digitT;
reg i;
initial
begin
digitT = 0;
C = 0;
D = 0;
U = 0;
centenas = 0;
decenas = 0;
unidades = 0;
i = 1;
end
always@(posedge clk)
begin
if(DONE)
begin
if(i)
begin
digitT = d;
i = 0;
end
if(digitT>7'b1100011)
begin
digitT = digitT - 7'b1100100;
centenas = centenas + 1;
end
else
begin
if(digitT>7'b0001001)
begin
digitT = digitT - 7'b0001010;
decenas = decenas + 1;
end
else
begin
unidades = {digitT[3:0]};
if(centenas >= 1)
begin
C = 1;
end
if(decenas >= 1)
begin
D = 1;
end
if(unidades >= 1)
begin
U = 1;
end
end
end
end
else
begin
if(!DONE)
begin
digitT = 0;
C = 0;
D = 0;
U = 0;
i = 1;
centenas = 0;
decenas = 0;
unidades = 0;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O211A_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__O211A_PP_BLACKBOX_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o211a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O211A_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S25_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S25_PP_BLACKBOX_V
/**
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
* gates.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkdlybuf4s25 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S25_PP_BLACKBOX_V
|
module PFF_DSP_16 (
input clk,
input store_strb,
input feedfwd_en_b,
input useDiode_b, loop2_useDiode_b,
input diodeGating_b, loop2_diodeGating_b,
input use_strobes_b,
input [9:0] start_proc_b,
input [9:0] end_proc_b,
input [4:0] kick1_delay_b,
input [4:0] kick2_delay_b,
input [1:0] opMode_b, //0 = sample-by-sample, 1 = constant DAC, 2 = Pulse mean removal //
input [1:0] oflowMode_b, // 0 = ignore, 1 = kill output, 2 = saturate output, 3 = undefined (default to 2) //
input signed [12:0] diodeIn, loop2_diodeIn,
input signed [15:0] MixerIn, loop2_MixerIn,
input signed [12:0] kick1_constDac_val_b,
input signed [12:0] kick2_constDac_val_b,
//input signed [6:0] kick1_gain_b, loop2_kick1_gain_b,
//input signed [6:0] kick2_gain_b, loop2_kick2_gain_b,
input signed [13:0] kick1_gain_b, loop2_kick1_gain_b,
input signed [13:0] kick2_gain_b, loop2_kick2_gain_b,
input DAC1clkPhase_b,
input DAC2clkPhase_b,
input oflowClr,
input signed [6:0] DAC1_IIRtapWeight, DAC2_IIRtapWeight,
//input [1:0] IIRbypass,
//input signed [12:0] amp1lim_b,
output reg oflowDetect = 1'b0,
output signed [12:0] kick1_dout,
output signed [12:0] kick2_dout,
//output signed [12:0] kick3_dout,
//output signed [12:0] kick4_dout,
output DAC1_en,
output DAC2_en
//output DAC3_en,
//output DAC4_en
);
`define COMBINE // NB: Introduces a two-cycle delay
parameter GAIN_SCALE =-4;// -4; //sets the scale factor for the gain; e.g. 128 ADC cnts maps to 2048 at DAC for GAIN_SCALE = -4 //
//parameter GAIN_OFFSET = 5; // maps ADC counts to DAC counts for the mid-range of the gain (i.e. 2^5 for 7-bit gain) // 7-bit gain //
parameter GAIN_OFFSET = 10; // 12; // maps ADC counts to DAC counts for the mid-range of the gain (i.e. 2^5 for 7-bit gain) // 14-bit gain //
//parameter GAIN_MSB = 23; // 7-bit gain // sets the MSB of the gain multipication (i.e. 16-bit x 7-bit = 23-bit + 1 bit for overflow detection = 24-bit) //
parameter GAIN_MSB = 30; // 14-bit gain // sets the MSB of the gain multipication (i.e. 16-bit x 14-bit = 30-bit + 1 bit for overflow detection = 31-bit) //
parameter DIODE_SCALE = 4; // set to compensate the scale factor when using diode normalisation (eg. if diode =1000, sqrt(diode)~32, factor = 5 - 2 bits already included in LUT, -1 bit MSB)//
// This module is the main module for forming the phase signal to drive the amplifier. Any operation on the data common to both amplifier paths should be included here, for example, it will also contain additional features such as a combiner module for use with combined beam and (rolling) averaging. It instances two DriveOuput modules, one for each amplifier, which control the amplifiers with independant timing, gain, and droop characteristics. //
//Instance LUTROM BRAM core
wire signed [17:0] lutReg;
LUTROM LUT1(
.clka(clk),
.addra(diodeIn),
.douta(lutReg)
);
//Note re RAM sizes - needs to be optimised. Why was 18bit chosesn (native BRAM size?), and cut at 100? Also, check size in FBFW - 28 apparently!
//Dual-FF synchronisers for asynchronous UART inputs
(* shreg_extract = "no" *) reg useDiode = 1'b0, useDiode_a = 1'b0;
(* shreg_extract = "no" *) reg diodeGating = 1'b0, diodeGating_a = 1'b0;
(* shreg_extract = "no" *) reg loop2_useDiode = 1'b0, loop2_useDiode_a = 1'b0;
(* shreg_extract = "no" *) reg loop2_diodeGating = 1'b0, loop2_diodeGating_a = 1'b0;
(* shreg_extract = "no" *) reg [1:0] oflowMode = 2'd0, oflowMode_a = 2'd0;
(* keep = "yes", shreg_extract = "no" *) reg signed [17:0] lutReg_b = 18'sd0, loop2_lutReg_b = 18'sd0;
(* shreg_extract = "no" *) reg signed [17:0] lutReg_c = 18'sd0, loop2_lutReg_c = 18'sd0;
//(* shreg_extract = "no" *) reg signed [12:0] amp1lim = 13'sd0, amp1lim_a = 13'sd0;
wire signed [17:0] loop2_lutReg;
`ifdef XILINX_ISIM
(* shreg_extract = "no" *) reg feedfwd_en = 1'b1, feedfwd_en_a = 1'b1;
(* shreg_extract = "no" *) reg use_strobes = 1'b1, use_strobes_a = 1'b1;
(* shreg_extract = "no" *) reg [9:0] start_proc = 10'd0, start_proc_a = 10'd0;
(* shreg_extract = "no" *) reg [9:0] end_proc = 10'd164, end_proc_a = 10'd164;
(* shreg_extract = "no" *) reg [4:0] kick1_delay = 5'd0, kick1_delay_a = 5'd0;
(* shreg_extract = "no" *) reg [4:0] kick2_delay = 5'd0, kick2_delay_a= 5'd0;
//(* shreg_extract = "no" , ASYNC_REG = "TRUE" *) reg [1:0] opMode = 2'd0, opMode_a = 2'd0;
(* ASYNC_REG = "TRUE" *) reg [1:0] opMode = 2'd0, opMode_a = 2'd0;
(* shreg_extract = "no" *) reg signed [12:0] kick1_constDac_val = 13'd0, kick1_constDac_val_a = 13'd0;
(* shreg_extract = "no" *) reg signed [12:0] kick2_constDac_val = 13'd0, kick2_constDac_val_a = 13'd0;
// (* shreg_extract = "no" *) reg signed [6:0] kick1_gain = 7'd63, kick1_gain_a = 7'd63;
// (* shreg_extract = "no" *) reg signed [6:0] kick2_gain = 7'd32, kick2_gain_a = 7'd32;
// (* shreg_extract = "no" *) reg signed [6:0] loop2_kick1_gain = 7'd63, loop2_kick1_gain_a = 7'd63;
// (* shreg_extract = "no" *) reg signed [6:0] loop2_kick2_gain = 7'd32, loop2_kick2_gain_a = 7'd32;
(* shreg_extract = "no" *) reg signed [13:0] kick1_gain = 14'd0, kick1_gain_a = 14'd0;
(* shreg_extract = "no" *) reg signed [13:0] kick2_gain = 14'd0, kick2_gain_a = 14'd0;
(* shreg_extract = "no" *) reg signed [13:0] loop2_kick1_gain = 14'd0, loop2_kick1_gain_a = 14'd0;
(* shreg_extract = "no" *) reg signed [13:0] loop2_kick2_gain = 14'd0, loop2_kick2_gain_a = 14'd0;
(* shreg_extract = "no" *) reg DAC1clkPhase = 1'b0, DAC1clkPhase_a = 1'b0;
(* shreg_extract = "no" *) reg DAC2clkPhase = 1'b0, DAC2clkPhase_a = 1'b0;
`else
(* shreg_extract = "no" *) reg feedfwd_en = 1'b0, feedfwd_en_a = 1'b0;
(* shreg_extract = "no" *) reg use_strobes = 1'b0, use_strobes_a = 1'b0;
(* shreg_extract = "no" *) reg [9:0] start_proc = 10'd0, start_proc_a = 10'd0;
(* shreg_extract = "no" *) reg [9:0] end_proc = 10'd0, end_proc_a = 10'd0;
(* shreg_extract = "no" *) reg [4:0] kick1_delay = 5'd0, kick1_delay_a = 5'd0;
(* shreg_extract = "no" *) reg [4:0] kick2_delay = 5'd0, kick2_delay_a= 5'd0;
//(* shreg_extract = "no" *) reg [1:0] opMode = 2'd0, opMode_a = 2'd0;
(* ASYNC_REG = "TRUE" *) reg [1:0] opMode = 2'd0, opMode_a = 2'd0;
(* shreg_extract = "no" *) reg signed [12:0] kick1_constDac_val = 13'd0, kick1_constDac_val_a = 13'd0;
(* shreg_extract = "no" *) reg signed [12:0] kick2_constDac_val = 13'd0, kick2_constDac_val_a = 13'd0;
// (* shreg_extract = "no" *) reg signed [6:0] kick1_gain = 7'd0, kick1_gain_a = 7'd0;
// (* shreg_extract = "no" *) reg signed [6:0] kick2_gain = 7'd0, kick2_gain_a = 7'd0;
// (* shreg_extract = "no" *) reg signed [6:0] loop2_kick1_gain = 7'd0, loop2_kick1_gain_a = 7'd0;
// (* shreg_extract = "no" *) reg signed [6:0] loop2_kick2_gain = 7'd0, loop2_kick2_gain_a = 7'd0;
(* shreg_extract = "no" *) reg signed [13:0] kick1_gain = 14'd0, kick1_gain_a = 14'd0;
(* shreg_extract = "no" *) reg signed [13:0] kick2_gain = 14'd0, kick2_gain_a = 14'd0;
(* shreg_extract = "no" *) reg signed [13:0] loop2_kick1_gain = 14'd0, loop2_kick1_gain_a = 14'd0;
(* shreg_extract = "no" *) reg signed [13:0] loop2_kick2_gain = 14'd0, loop2_kick2_gain_a = 14'd0;
(* shreg_extract = "no" *) reg DAC1clkPhase = 1'b0, DAC1clkPhase_a = 1'b0;
(* shreg_extract = "no" *) reg DAC2clkPhase = 1'b0, DAC2clkPhase_a = 1'b0;
`endif
always @(posedge clk) begin
//amp1lim_a <= amp1lim_b;
//amp1lim <= amp1lim_a;
feedfwd_en <= feedfwd_en_a;
feedfwd_en_a <= feedfwd_en_b;
use_strobes <= use_strobes_a;
use_strobes_a <= use_strobes_b;
start_proc <= start_proc_a;
start_proc_a <= start_proc_b;
end_proc <= end_proc_a;
end_proc_a <= end_proc_b;
kick1_delay <= kick1_delay_a;
kick1_delay_a <= kick1_delay_b;
kick2_delay <= kick2_delay_a;
kick2_delay_a <= kick2_delay_b;
opMode <= opMode_a;
opMode_a <= opMode_b;
kick1_constDac_val <= kick1_constDac_val_a;
kick1_constDac_val_a <= kick1_constDac_val_b;
kick2_constDac_val <= kick2_constDac_val_a;
kick2_constDac_val_a <= kick2_constDac_val_b;
kick1_gain <= kick1_gain_a;
kick1_gain_a <= kick1_gain_b;
kick2_gain <= kick2_gain_a;
kick2_gain_a <= kick2_gain_b;
loop2_kick1_gain <= loop2_kick1_gain_a;
loop2_kick1_gain_a <= loop2_kick1_gain_b;
loop2_kick2_gain <= loop2_kick2_gain_a;
loop2_kick2_gain_a <= loop2_kick2_gain_b;
DAC1clkPhase <= DAC1clkPhase_a;
DAC1clkPhase_a <= DAC1clkPhase_b;
DAC2clkPhase <= DAC2clkPhase_a;
DAC2clkPhase_a <= DAC2clkPhase_b;
useDiode <= useDiode_a;
useDiode_a <= useDiode_b;
diodeGating <= diodeGating_a;
diodeGating_a <= diodeGating_b;
loop2_useDiode <= loop2_useDiode_a;
loop2_useDiode_a <= loop2_useDiode_b;
loop2_diodeGating <= loop2_diodeGating_a;
loop2_diodeGating_a <= loop2_diodeGating_b;
oflowMode <= oflowMode_a;
oflowMode_a <= oflowMode_b;
if (diodeGating) lutReg_b <= (useDiode) ? lutReg : {17'sd0, |lutReg};
else lutReg_b <= (useDiode) ? lutReg : 18'sd1;
//lutReg_b <= (useDiode) ? lutReg : {17'sd0, (use_strobes) ? 1'b1 : |lutReg};
if (loop2_diodeGating) loop2_lutReg_b <= (loop2_useDiode) ? loop2_lutReg : {17'sd0, |loop2_lutReg};
else loop2_lutReg_b <= (loop2_useDiode) ? loop2_lutReg : 18'sd1;
lutReg_c <= lutReg_b;
loop2_lutReg_c <= loop2_lutReg_b;
end
// GATING and COMBINATION SECTION - NEW 12/12/16 (Moved from ampDrive module to do combination ahead of the gain stage //
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
parameter real CLK_FREQ = 357e6;
parameter real SUB_PULSE_LENGTH = 280e-9;
localparam [9:0] PULSE_LENGTH = (CLK_FREQ * SUB_PULSE_LENGTH * 4); //think about how to generalise this! - just use full_pulse length OR 140ns * CF?
//Form output gate
(* shreg_extract = "no" *) reg [9:0] opGate_ctr = 10'd0;
(* shreg_extract = "no" *) reg opGate = 1'b0;
`ifdef COMBINE
localparam OFFSET_DELAY = 4'd10; // Override value - includes the 2 cycle delay from the Combiner Module
wire [9:0] startProc = (~opMode[1]) ? start_proc : end_proc - PULSE_LENGTH;
`else
localparam OFFSET_DELAY = 4'd8; // Override value - includes the 2 cycle delay from the Combiner Module
wire [9:0] startProc = start_proc;
`endif
always @(posedge clk) begin
opGate_ctr <= (store_strb) ? opGate_ctr + 1'b1 : 11'd0;
if (store_strb) begin
//(* full_case, parallel_case *)
case (opGate_ctr)
startProc: opGate <= 1'b1;
end_proc: opGate <= 1'b0;
default: opGate <= opGate;
endcase
end else begin
opGate <= 1'b0;
end
end
`ifdef COMBINE
//Instance Combiner Module 1 (Diode)
//FOR NOW DO NOT DO COMBINING ON DIODE - just add compensating delays
(* keep = "yes" *) reg signed [17:0] lutReg_d = 18'sd0, lutReg_e = 18'sd0;
always @(posedge clk) begin
lutReg_d <= lutReg_c;
lutReg_e <= lutReg_d;
end
wire signed [17:0] normMult_DiodeIn = lutReg_e;
/*wire signed [15:0] DiodeComb;
reg signed [15:0] DiodeIn_a = 16'sd0, DiodeIn_b = 16'sd0;
(* shreg_extract = "no" *) reg integ_gate = 1'b0;
Combiner #(CLK_FREQ, SUB_PULSE_LENGTH) Combiner1(.clk(clk), .din(DiodeIn), .integ(integ_gate), .bypass(1'b0), .dout(DiodeComb));
always @(posedge clk) begin
DiodeIn_b <= DiodeIn_a;
DiodeIn_a <= DiodeIn;
integ_gate <= opGate;
end
wire signed [15:0] normMult_DiodeIn = (~opMode[1]) ? DiodeIn_b : DiodeComb;*/
//Instance Combiner Module 2 (Mixer)
wire signed [15:0] MixerComb;
(* keep = "yes" *) reg signed [15:0] MixerIn_a = 16'sd0, MixerIn_b = 16'sd0;
//(* shreg_extract = "no" *) reg integ_gate = 1'b0;
Combiner #(CLK_FREQ, SUB_PULSE_LENGTH) Combiner1(.clk(clk), .din(MixerIn), .integ(opGate), .bypass(1'b0), .dout(MixerComb));
always @(posedge clk) begin
MixerIn_b <= MixerIn_a;
MixerIn_a <= MixerIn;
//integ_gate <= opGate;
end
wire signed [15:0] normMult_MixerIn = (~opMode[1]) ? MixerIn_b : MixerComb;
`else
wire signed [15:0] normMult_MixerIn = MixerIn; // Possibly remove bypass option later!
wire signed [17:0] normMult_DiodeIn = lutReg_c; // Possibly remove bypass option later!
`endif
// END GATE and COMBINER
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Apply Kicker 1 Gain
wire signed [15:0] kick1_gainMult;
wire kick1_oflowDet;
normMult #(GAIN_SCALE, GAIN_OFFSET, GAIN_MSB, DIODE_SCALE) kick1Mult(clk, useDiode, oflowMode, normMult_DiodeIn, normMult_MixerIn, kick1_gain, kick1_gainMult, kick1_oflowDet);
// Apply Kicker 2 Gain
wire signed [15:0] kick2_gainMult;
wire kick2_oflowDet;
normMult #(GAIN_SCALE, GAIN_OFFSET, GAIN_MSB, DIODE_SCALE) kick2Mult(clk, useDiode, oflowMode, normMult_DiodeIn, normMult_MixerIn, kick2_gain, kick2_gainMult, kick2_oflowDet);
///////// LOOP2 ////////////////////////////////////////// - use a define include statement and compare timings with/without 2nd loop ....
parameter LOOP2_GAIN_SCALE = -4; //sets the scale factor for the gain; e.g. 128 ADC cnts maps to 2048 at DAC for GAIN_SCALE = -4 //
//parameter LOOP2_GAIN_OFFSET = 5; // maps ADC counts to DAC counts for the mid-range of the gain (i.e. 2^5 for 7-bit gain) // 7-bit gain //
//parameter LOOP2_GAIN_OFFSET = 12; // maps ADC counts to DAC counts for the mid-range of the gain (i.e. 2^5 for 7-bit gain) // 14-bit gain //
parameter LOOP2_GAIN_OFFSET = 10; // maps ADC counts to DAC counts for the mid-range of the gain (i.e. 2^5 for 7-bit gain) // 14-bit gain //
//parameter LOOP2_GAIN_MSB = 23; // 7-bit gain // sets the MSB of the gain multipication (i.e. 16-bit x 7-bit = 23-bit + 1 bit for overflow detection = 24-bit) //
parameter LOOP2_GAIN_MSB = 30; // 14-bit gain // sets the MSB of the gain multipication (i.e. 16-bit x 7-bit = 23-bit + 1 bit for overflow detection = 24-bit) //
parameter LOOP2_DIODE_SCALE = 4; // set to compensate the scale factor when using diode normalisation (eg. if diode =1000, sqrt(diode)~32, factor = 5 - 2 bits already included in LUT, -1 bit MSB)//
//Instance LUTROM BRAM core
LUTROM LUT2(
.clka(clk),
.addra(loop2_diodeIn),
.douta(loop2_lutReg)
);
// For loop 2 just comprensate for the delays!!
`ifdef COMBINE
//Instance Combiner Module 1 (Diode)
//FOR NOW DO NOT DO COMBINING ON DIODE - just add compensating delays
(* keep = "yes" *) reg signed [17:0] loop2_lutReg_d = 18'sd0, loop2_lutReg_e = 18'sd0;
always @(posedge clk) begin
loop2_lutReg_d <= loop2_lutReg_c;
loop2_lutReg_e <= loop2_lutReg_d;
end
wire signed [17:0] loop2_normMult_DiodeIn = loop2_lutReg_e;
//Instance Combiner Module 2 (Mixer)
(* keep = "yes" *) reg signed [15:0] loop2_MixerIn_a = 16'sd0, loop2_MixerIn_b = 16'sd0;
always @(posedge clk) begin
loop2_MixerIn_a <= loop2_MixerIn;
loop2_MixerIn_b <= loop2_MixerIn_a;
end
wire signed [15:0] loop2_normMult_MixerIn = loop2_MixerIn_b;
`else
wire signed [15:0] loop2_normMult_MixerIn = loop2_MixerIn; // Possibly remove bypass option later!
wire signed [17:0] loop2_normMult_DiodeIn = loop2_lutReg_c; // Possibly remove bypass option later!
`endif
// Apply Kicker 1 Gain
wire signed [15:0] loop2_kick1_gainMult;
wire loop2_kick1_oflowDet;
normMult #(LOOP2_GAIN_SCALE, LOOP2_GAIN_OFFSET, LOOP2_GAIN_MSB, LOOP2_DIODE_SCALE) loop2_kick1Mult(clk, loop2_useDiode, oflowMode, loop2_normMult_DiodeIn, loop2_normMult_MixerIn, loop2_kick1_gain, loop2_kick1_gainMult, loop2_kick1_oflowDet);
// Apply Kicker 2 Gain
wire signed [15:0] loop2_kick2_gainMult;
wire loop2_kick2_oflowDet;
normMult #(LOOP2_GAIN_SCALE, LOOP2_GAIN_OFFSET, LOOP2_GAIN_MSB, LOOP2_DIODE_SCALE) loop2_kick2Mult(clk, loop2_useDiode, oflowMode, loop2_normMult_DiodeIn, loop2_normMult_MixerIn, loop2_kick2_gain, loop2_kick2_gainMult, loop2_kick2_oflowDet);
///////////////// END LOOP2 /////////////////////////////////
/*always @(posedge clk) begin
multReg <= mult;
if (oflowDetect && oflowClr) oflowDetect <= 1'b0;
else if (!(&multReg[43:29] || &(~multReg[43:29]))) oflowDetect <= 1'b1; //check for all ones or all zeros in overflow bits
else oflowDetect <= oflowDetect;
end*/
//Combinatorial always block for ampDrive input signals
//wire signed [16:0] kick1_drive = kick1_gainMult + loop2_kick1_gainMult;
reg signed [16:0] kick1_drive = 17'sd0;//kick1_gainMult + loop2_kick1_gainMult;
reg signed [15:0] kick1_drive_b = 16'sd0;
//wire signed [16:0] kick2_drive = kick2_gainMult + loop2_kick2_gainMult;
reg signed [16:0] kick2_drive = 17'sd0;//kick2_gainMult + loop2_kick2_gainMult;
reg signed [15:0] kick2_drive_b = 16'sd0;
reg kick1_drive_oflowDet = 1'b0, kick2_drive_oflowDet = 1'b0;
always @(posedge clk) begin
kick1_drive <= kick1_gainMult + loop2_kick1_gainMult;
kick2_drive <= kick2_gainMult + loop2_kick2_gainMult;
end
/*always @(*) begin
if (^kick1_drive[16:15]) begin
kick1_drive_oflowDet = 1'b1;
(* full_case, parallel_case *)
case(oflowMode)
2'b00: kick1_drive_b = kick1_drive[15:0];
2'b01: kick1_drive_b = 16'sd0;
2'b10: kick1_drive_b = (kick1_drive[16]) ? -16'sd32768 : 16'sd32767;
//default: kick1_drive_b = 16'sd0;
endcase
end else begin
kick1_drive_b = kick1_drive[15:0];
kick1_drive_oflowDet = 1'b0;
end
end*/
always @(*) begin
if (^kick1_drive[16:15]) begin
//if (^kick1_drive[16:15] || (kick1_drive[15:3] > amp1lim) || (kick1_drive[15:13] < ~amp1lim)) begin
kick1_drive_oflowDet = 1'b1;
(* full_case, parallel_case *)
case(oflowMode)
2'b00: kick1_drive_b = kick1_drive[15:0];
2'b01: kick1_drive_b = 16'sd0;
//2'b10: kick1_drive_b = (kick1_drive[16]) ? {~amp1lim, 3'b111} : {amp1lim, 3'b111};
2'b10: kick1_drive_b = (kick1_drive[16]) ? -16'sd32768 : 16'sd32767;
//default: kick1_drive_b = 16'sd0;
endcase
end else begin
kick1_drive_b = kick1_drive[15:0];
kick1_drive_oflowDet = 1'b0;
end
end
/*always @(posedge clk) begin
//kick1_drive <= kick1_gainMult + loop2_kick1_gainMult;
if (^kick1_drive[16:15]) begin
kick1_drive_oflowDet <= 1'b1;
(* full_case, parallel_case *)
case(oflowMode)
2'b00: kick1_drive_b <= kick1_drive[15:0];
2'b01: kick1_drive_b <= 16'sd0;
2'b10: kick1_drive_b <= (kick1_drive[16]) ? -16'sd32768 : 16'sd32767;
default: kick1_drive_b <= 16'sd0;
endcase
end else begin
kick1_drive_b <= kick1_drive[15:0];
kick1_drive_oflowDet <= 1'b0;
end
end*/
always @(*) begin
if (^kick2_drive[16:15]) begin
kick2_drive_oflowDet = 1'b1;
(* full_case, parallel_case *)
case(oflowMode)
2'b00: kick2_drive_b = kick2_drive[15:0];
2'b01: kick2_drive_b = 16'sd0;
2'b10: kick2_drive_b = (kick2_drive[16]) ? -16'sd32768 : 16'sd32767;
//default: kick2_drive_b = 16'sd0;
endcase
end else begin
kick2_drive_b = kick2_drive[15:0];
kick2_drive_oflowDet = 1'b0;
end
end
/*always @(posedge clk) begin
//kick2_drive <= kick2_gainMult + loop2_kick2_gainMult;
if (^kick2_drive[16:15]) begin
kick2_drive_oflowDet <= 1'b1;
(* full_case, parallel_case *)
case(oflowMode)
2'b00: kick2_drive_b <= kick2_drive[15:0];
2'b01: kick2_drive_b <= 16'sd0;
2'b10: kick2_drive_b <= (kick2_drive[16]) ? -16'sd32768 : 16'sd32767;
default: kick2_drive_b <= 16'sd0;
endcase
end else begin
kick2_drive_b <= kick2_drive[15:0];
kick2_drive_oflowDet <= 1'b0;
end
end*/
// Instance the DriveOutput modules //
wire DAC1_IIR_oflowDet, DAC2_IIR_oflowDet;
ampDrive #(.OFFSET_DELAY(OFFSET_DELAY)) kick1Drive(clk, feedfwd_en, (store_strb && (opGate || ~use_strobes)), opMode[0], kick1_delay, kick1_constDac_val, kick1_drive_b, DAC1clkPhase, DAC1_IIRtapWeight, DAC1_IIR_oflowDet, kick1_dout, DAC1_en);
ampDrive #(.OFFSET_DELAY(OFFSET_DELAY)) kick2Drive(clk, feedfwd_en, (store_strb && (opGate || ~use_strobes)), opMode[0], kick2_delay, kick2_constDac_val, kick2_drive_b, DAC2clkPhase, DAC2_IIRtapWeight, DAC2_IIR_oflowDet, kick2_dout, DAC2_en);
reg kick1_oflowDet_a = 1'b0, kick2_oflowDet_a = 1'b0;
always @(posedge clk) begin
kick1_oflowDet_a <= kick1_oflowDet;
kick2_oflowDet_a <= kick2_oflowDet;
oflowDetect <= (kick1_oflowDet_a | kick2_oflowDet_a | loop2_kick1_oflowDet | loop2_kick2_oflowDet | kick1_drive_oflowDet | kick2_drive_oflowDet | DAC1_IIR_oflowDet | DAC2_IIR_oflowDet);
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
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// otherwise provided in a valid license issued to you by
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.92
// \ \ Application : MIG
// / / Filename : example_top.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 07:18:00 $
// \ \ / \ Date Created : Mon Jun 23 2008
// \___\/\___\
//
// Device : Virtex-6
// Design Name : DDR3 SDRAM
// Purpose :
// Top-level module. This module serves both as an example,
// and allows the user to synthesize a self-contained design,
// which they can use to test their hardware. In addition to
// the memory controller.
// instantiates:
// 1. Clock generation/distribution, reset logic
// 2. IDELAY control block
// 3. Synthesizable testbench - used to model user's backend
// logic
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module example_top #
(
parameter REFCLK_FREQ = 200,
// # = 200 for all design frequencies of
// -1 speed grade devices
// = 200 when design frequency < 480 MHz
// for -2 and -3 speed grade devices.
// = 300 when design frequency >= 480 MHz
// for -2 and -3 speed grade devices.
parameter IODELAY_GRP = "IODELAY_MIG",
// It is associated to a set of IODELAYs with
// an IDELAYCTRL that have same IODELAY CONTROLLER
// clock frequency.
parameter MMCM_ADV_BANDWIDTH = "OPTIMIZED",
// MMCM programming algorithm
parameter CLKFBOUT_MULT_F = 8,
// write PLL VCO multiplier.
parameter DIVCLK_DIVIDE = 2,
// write PLL VCO divisor.
parameter CLKOUT_DIVIDE = 4,
// VCO output divisor for fast (memory) clocks.
parameter nCK_PER_CLK = 2,
// # of memory CKs per fabric clock.
// # = 2, 1.
parameter tCK = 2500,
// memory tCK paramter.
// # = Clock Period.
parameter DEBUG_PORT = "ON",
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
parameter SIM_BYPASS_INIT_CAL = "OFF",
// # = "OFF" - Complete memory init &
// calibration sequence
// # = "SKIP" - Skip memory init &
// calibration sequence
// # = "FAST" - Skip memory init & use
// abbreviated calib sequence
parameter nCS_PER_RANK = 1,
// # of unique CS outputs per Rank for
// phy.
parameter DQS_CNT_WIDTH = 3,
// # = ceil(log2(DQS_WIDTH)).
parameter RANK_WIDTH = 1,
// # = ceil(log2(RANKS)).
parameter BANK_WIDTH = 3,
// # of memory Bank Address bits.
parameter CK_WIDTH = 2,
// # of CK/CK# outputs to memory.
parameter CKE_WIDTH = 2,
// # of CKE outputs to memory.
parameter COL_WIDTH = 10,
// # of memory Column Address bits.
parameter CS_WIDTH = 2,
// # of unique CS outputs to memory.
parameter DM_WIDTH = 8,
// # of Data Mask bits.
parameter DQ_WIDTH = 64,
// # of Data (DQ) bits.
parameter DQS_WIDTH = 8,
// # of DQS/DQS# bits.
parameter ROW_WIDTH = 15,
// # of memory Row Address bits.
parameter BURST_MODE = "8",
// Burst Length (Mode Register 0).
// # = "8", "4", "OTF".
parameter BM_CNT_WIDTH = 2,
// # = ceil(log2(nBANK_MACHS)).
parameter ADDR_CMD_MODE = "1T" ,
// # = "2T", "1T".
parameter ORDERING = "NORM",
// # = "NORM", "STRICT".
parameter WRLVL = "ON",
// # = "ON" - DDR3 SDRAM
// = "OFF" - DDR2 SDRAM.
parameter PHASE_DETECT = "ON",
// # = "ON", "OFF".
parameter RTT_NOM = "40",
// RTT_NOM (ODT) (Mode Register 1).
// # = "DISABLED" - RTT_NOM disabled,
// = "120" - RZQ/2,
// = "60" - RZQ/4,
// = "40" - RZQ/6.
parameter RTT_WR = "120",
// RTT_WR (ODT) (Mode Register 2).
// # = "OFF" - Dynamic ODT off,
// = "120" - RZQ/2,
// = "60" - RZQ/4,
parameter OUTPUT_DRV = "HIGH",
// Output Driver Impedance Control (Mode Register 1).
// # = "HIGH" - RZQ/7,
// = "LOW" - RZQ/6.
parameter REG_CTRL = "OFF",
// # = "ON" - RDIMMs,
// = "OFF" - Components, SODIMMs, UDIMMs.
parameter nDQS_COL0 = 3,
// Number of DQS groups in I/O column #1.
parameter nDQS_COL1 = 5,
// Number of DQS groups in I/O column #2.
parameter nDQS_COL2 = 0,
// Number of DQS groups in I/O column #3.
parameter nDQS_COL3 = 0,
// Number of DQS groups in I/O column #4.
parameter DQS_LOC_COL0 = 24'h020100,
// DQS groups in column #1.
parameter DQS_LOC_COL1 = 40'h0706050403,
// DQS groups in column #2.
parameter DQS_LOC_COL2 = 0,
// DQS groups in column #3.
parameter DQS_LOC_COL3 = 0,
// DQS groups in column #4.
parameter tPRDI = 1_000_000,
// memory tPRDI paramter.
parameter tREFI = 7800000,
// memory tREFI paramter.
parameter tZQI = 128_000_000,
// memory tZQI paramter.
parameter ADDR_WIDTH = 29,
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
parameter ECC = "OFF",
parameter ECC_TEST = "OFF",
parameter TCQ = 100,
// Traffic Gen related parameters
parameter EYE_TEST = "FALSE",
// set EYE_TEST = "TRUE" to probe memory
// signals. Traffic Generator will only
// write to one single location and no
// read transactions will be generated.
parameter SIMULATION = "FALSE",
parameter DATA_MODE = 2,
parameter ADDR_MODE = 3,
parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE",
parameter DATA_PATTERN = "DGEN_ALL",
// DATA_PATTERN shoule be set to "DGEN_ALL"
// unless it is targeted for S6 small device.
// "DGEN_HAMMER", "DGEN_WALKING1",
// "DGEN_WALKING0","DGEN_ADDR","
// "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter CMD_PATTERN = "CGEN_ALL",
// CMD_PATTERN shoule be set to "CGEN_ALL"
// unless it is targeted for S6 small device.
// "CGEN_PRBS","CGEN_FIXED","CGEN_BRAM",
// "CGEN_SEQUENTIAL", "CGEN_ALL"
parameter BEGIN_ADDRESS = 32'h00000000,
parameter PRBS_SADDR_MASK_POS = 32'h00000000,
parameter END_ADDRESS = 32'h00ffffff,
parameter PRBS_EADDR_MASK_POS = 32'hff000000,
parameter SEL_VICTIM_LINE = 11,
parameter RST_ACT_LOW = 1,
// =1 for active low reset,
// =0 for active high.
parameter INPUT_CLK_TYPE = "SINGLE_ENDED",
// input clock type DIFFERENTIAL or SINGLE_ENDED
parameter STARVE_LIMIT = 2,
// # = 2,3,4.
//ftl parameter
parameter DRAM_IO_WIDTH = 256,//DRAM IO¿í¶È
parameter COMMAND_WIDTH = 128, //ÃüÁî¿í¶È
parameter FLASH_IO_WIDTH = 8 //flash¿í¶È
)
(
input sys_clk, //single ended system clocks
input clk_ref, //single ended iodelayctrl clk
inout [DQ_WIDTH-1:0] ddr3_dq,
output [ROW_WIDTH-1:0] ddr3_addr,
output [BANK_WIDTH-1:0] ddr3_ba,
output ddr3_ras_n,
output ddr3_cas_n,
output ddr3_we_n,
output ddr3_reset_n,
output [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n,
output [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_odt,
output [CKE_WIDTH-1:0] ddr3_cke,
output [DM_WIDTH-1:0] ddr3_dm,
inout [DQS_WIDTH-1:0] ddr3_dqs_p,
inout [DQS_WIDTH-1:0] ddr3_dqs_n,
output [CK_WIDTH-1:0] ddr3_ck_p,
output [CK_WIDTH-1:0] ddr3_ck_n,
inout sda,
output scl,
output heartbeat,
output phy_init_done,
//PCIE interface
output [7:0] pci_exp_txp,
output [7:0] pci_exp_txn,
input [7:0] pci_exp_rxp,
input [7:0] pci_exp_rxn,
input pcie_clk_p,
input pcie_clk_n,
input pcie_rst_n,
input sys_rst, // System reset
output nand0Cle,
output nand0Ale,
output nand0Clk_We_n,
output nand0Wr_Re_n,
output nand0Wp_n,
output [7:0] nand0Ce_n,
input [7:0] nand0Rb_n,
inout [FLASH_IO_WIDTH-1:0] nand0DQX,
inout nand0DQS,
output nand1Cle,
output nand1Ale,
output nand1Clk_We_n,
output nand1Wr_Re_n,
output nand1Wp_n,
output [7:0] nand1Ce_n,
input [7:0] nand1Rb_n,
inout [FLASH_IO_WIDTH-1:0] nand1DQX,
inout nand1DQS,
output nand2Cle,
output nand2Ale,
output nand2Clk_We_n,
output nand2Wr_Re_n,
output nand2Wp_n,
output [7:0] nand2Ce_n,
input [7:0] nand2Rb_n,
inout [FLASH_IO_WIDTH-1:0] nand2DQX,
inout nand2DQS,
output nand3Cle,
output nand3Ale,
output nand3Clk_We_n,
output nand3Wr_Re_n,
output nand3Wp_n,
output [7:0] nand3Ce_n,
input [7:0] nand3Rb_n,
inout [FLASH_IO_WIDTH-1:0] nand3DQX,
inout nand3DQS,
output nand4Cle,
output nand4Ale,
output nand4Clk_We_n,
output nand4Wr_Re_n,
output nand4Wp_n,
output [7:0] nand4Ce_n,
input [7:0] nand4Rb_n,
inout [FLASH_IO_WIDTH-1:0] nand4DQX,
inout nand4DQS,
output nand5Cle,
output nand5Ale,
output nand5Clk_We_n,
output nand5Wr_Re_n,
output nand5Wp_n,
output [7:0] nand5Ce_n,
input [7:0] nand5Rb_n,
inout [FLASH_IO_WIDTH-1:0] nand5DQX,
inout nand5DQS,
output nand6Cle,
output nand6Ale,
output nand6Clk_We_n,
output nand6Wr_Re_n,
output nand6Wp_n,
output [7:0] nand6Ce_n,
input [7:0] nand6Rb_n,
inout [FLASH_IO_WIDTH-1:0] nand6DQX,
inout nand6DQS,
output nand7Cle,
output nand7Ale,
output nand7Clk_We_n,
output nand7Wr_Re_n,
output nand7Wp_n,
output [7:0] nand7Ce_n,
input [7:0] nand7Rb_n,
inout [FLASH_IO_WIDTH-1:0] nand7DQX,
inout nand7DQS
);
// Add ML605 heartbeat counter and LED assignments
reg [28:0] led_counter;
always @( posedge clk or posedge rst)
begin
if (rst)
led_counter <= 0;
else
led_counter <= led_counter + 1;
end
assign heartbeat = led_counter[27];
function integer STR_TO_INT;
input [7:0] in;
begin
if(in == "8")
STR_TO_INT = 8;
else if(in == "4")
STR_TO_INT = 4;
else
STR_TO_INT = 0;
end
endfunction
localparam SYSCLK_PERIOD = tCK * nCK_PER_CLK;
localparam DATA_WIDTH = 64;
localparam PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH;
localparam BURST_LENGTH = STR_TO_INT(BURST_MODE);
localparam APP_DATA_WIDTH = PAYLOAD_WIDTH * 4;
localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
wire clk_ref_p;
wire clk_ref_n;
wire sys_clk_p;
wire sys_clk_n;
wire mmcm_clk;
wire iodelay_ctrl_rdy;
(* KEEP = "TRUE" *) wire sda_i;
(* KEEP = "TRUE" *) wire scl_i;
wire rst;
wire clk;
wire clk_mem;
wire clk_rd_base;
wire pd_PSDONE;
wire pd_PSEN;
wire pd_PSINCDEC;
wire [(BM_CNT_WIDTH)-1:0] bank_mach_next;
wire ddr3_parity;
wire app_hi_pri;
wire [APP_MASK_WIDTH-1:0] app_wdf_mask;
wire [3:0] app_ecc_multiple_err_i;
wire [47:0] traffic_wr_data_counts;
wire [47:0] traffic_rd_data_counts;
wire [ADDR_WIDTH-1:0] app_addr;
wire [2:0] app_cmd;
wire app_en;
wire app_sz;
wire app_rdy;
wire [APP_DATA_WIDTH-1:0] app_rd_data;
wire app_rd_data_valid;
wire [APP_DATA_WIDTH-1:0] app_wdf_data;
wire app_wdf_end;
wire app_wdf_rdy;
wire app_wdf_wren;
wire fifo_pcie_clk;
//pcie2ftl data fifo
//
//wire [COMMAND_WIDTH-1:0]pcie_data_rec_fifo_in;// input [127 : 0] din
//wire pcie_data_rec_fifo_in_en; // input wr_en
wire pcie_data_rec_fifo_out_en; // input rd_en
wire [DRAM_IO_WIDTH-1:0]pcie_data_rec_fifo_out; // output [255 : 0] dout
wire pcie_data_rec_fifo_prog_full; // output full
//wire pcie_data_rec_fifo_out_full;
//wire pcie_data_rec_fifo_out_almost_full;
wire RX_data_fifo_full;
wire RX_data_fifo_almost_full;
wire RX_data_fifo_wr_en;
wire [COMMAND_WIDTH-1:0] RX_data_fifo_data;
wire RX_data_fifo_av = !pcie_data_rec_fifo_prog_full;
//pcie2ftl command fifo
//
//wire [COMMAND_WIDTH-1:0]pcie_command_rec_fifo_in; // input [127 : 0] din
//wire pcie_command_rec_fifo_in_en; // input wr_en
wire pcie_command_rec_fifo_out_en; // input rd_en
wire [COMMAND_WIDTH-1:0]pcie_command_rec_fifo_out; // output [127 : 0] dout
//wire pcie_command_rec_fifo_out_full; // output full
//wire pcie_command_rec_fifo_out_almost_full;
wire pcie_command_rec_fifo_empty_or_not; // output empty
wire CMGFTL_cmd_fifo_full;
wire CMGFTL_cmd_fifo_almost_full;
wire CMGFTL_cmd_fifo_wr_en;
wire [COMMAND_WIDTH-1:0] CMGFTL_cmd_fifo_data;
//ftl2pcie data fifo
//
wire [DRAM_IO_WIDTH-1:0]pcie_data_send_fifo_in; // input [255 : 0] din
wire pcie_data_send_fifo_in_en; // input wr_en
//wire [COMMAND_WIDTH-1:0]pcie_data_send_fifo_out; // input rd_en
//wire pcie_data_send_fifo_out_en; // output [127 : 0] dout
//wire pcie_data_send_fifo_out_empty;
//wire pcie_data_send_fifo_out_almost_empty;
wire pcie_data_send_fifo_out_prog_full;
wire TX_data_fifo_empty;
wire TX_data_fifo_almost_empty;
wire TX_data_fifo_rd_en;
wire [COMMAND_WIDTH-1:0] TX_data_fifo_data;
//ftl2pcie cmd fifo
//
wire [COMMAND_WIDTH-1:0]pcie_command_send_fifo_in; // input [127 : 0] din
wire pcie_command_send_fifo_in_en; // input wr_en
//wire [COMMAND_WIDTH-1:0]pcie_command_send_fifo_out; // input rd_en
//wire pcie_command_send_fifo_out_en; // output [127 : 0] dout
wire pcie_command_send_fifo_full_or_not; // output full
//wire pcie_command_send_fifo_out_empty;
//wire pcie_command_send_fifo_out_almost_empty;
wire FTLCMG_cmd_fifo_empty;
wire FTLCMG_cmd_fifo_almost_empty;
wire FTLCMG_cmd_fifo_rd_en;
wire [COMMAND_WIDTH-1:0] FTLCMG_cmd_fifo_data;
//***************************************************************************
assign app_hi_pri = 1'b0;
//assign app_wdf_mask = {APP_MASK_WIDTH{1'b0}};
assign manual_clear_error = 1'b0;
MUXCY scl_inst
(
.O (scl),
.CI (scl_i),
.DI (1'b0),
.S (1'b1)
);
MUXCY sda_inst
(
.O (sda),
.CI (sda_i),
.DI (1'b0),
.S (1'b1)
);
assign clk_ref_p = 1'b0;
assign clk_ref_n = 1'b0;
assign sys_clk_p = 1'b0;
assign sys_clk_n = 1'b0;
clk_wiz_v3_6 clknetwork
(// Clock in ports
.CLK_IN1 (clk_ref),
// Clock out ports
.CLK_OUT1 (sys_clk_pll),
.CLK_OUT2 (clk_ref_pll),
// Status and control signals
.LOCKED (LOCKED));
clk_gen_83M clk_generaor_83M
(// Clock in ports
.CLK_IN1(sys_clk), // IN
// Clock out ports
.CLK_OUT1(clk_83X2M), // OUT
.CLK_OUT2(clk_83M), // OUT
.CLK_OUT3(clk_83M_reverse), // OUT
//.CLKFB_IN(CLKFB),
//.CLKFB_OUT(CLKFB),
// Status and control signals
.RESET(RESET),// IN
.LOCKED(LOCKED)); // OUT
iodelay_ctrl #
(
.TCQ (TCQ),
.IODELAY_GRP (IODELAY_GRP),
.INPUT_CLK_TYPE (INPUT_CLK_TYPE),
.RST_ACT_LOW (RST_ACT_LOW)
)
u_iodelay_ctrl
(
.clk_ref_p (clk_ref_p),
.clk_ref_n (clk_ref_n),
.clk_ref (clk_ref_pll),
.sys_rst (sys_rst),
.iodelay_ctrl_rdy (iodelay_ctrl_rdy)
);
clk_ibuf #
(
.INPUT_CLK_TYPE (INPUT_CLK_TYPE)
)
u_clk_ibuf
(
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
.sys_clk (sys_clk_pll),
.mmcm_clk (mmcm_clk)
);
infrastructure #
(
.TCQ (TCQ),
.CLK_PERIOD (SYSCLK_PERIOD),
.nCK_PER_CLK (nCK_PER_CLK),
.MMCM_ADV_BANDWIDTH (MMCM_ADV_BANDWIDTH),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_F),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKOUT_DIVIDE (CLKOUT_DIVIDE),
.RST_ACT_LOW (RST_ACT_LOW)
)
u_infrastructure
(
.clk_mem (clk_mem),
.clk (clk),
.clk_rd_base (clk_rd_base),
.rstdiv0 (rst),
.mmcm_clk (mmcm_clk),
.sys_rst (sys_rst),
.iodelay_ctrl_rdy (iodelay_ctrl_rdy),
.PSDONE (pd_PSDONE),
.PSEN (pd_PSEN),
.PSINCDEC (pd_PSINCDEC)
);
memc_ui_top #
(
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_WIDTH (BANK_WIDTH),
.CK_WIDTH (CK_WIDTH),
.CKE_WIDTH (CKE_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.COL_WIDTH (COL_WIDTH),
.CS_WIDTH (CS_WIDTH),
.DM_WIDTH (DM_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.DEBUG_PORT (DEBUG_PORT),
.IODELAY_GRP (IODELAY_GRP),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.ORDERING (ORDERING),
.OUTPUT_DRV (OUTPUT_DRV),
.PHASE_DETECT (PHASE_DETECT),
.RANK_WIDTH (RANK_WIDTH),
.REFCLK_FREQ (REFCLK_FREQ),
.REG_CTRL (REG_CTRL),
.ROW_WIDTH (ROW_WIDTH),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.WRLVL (WRLVL),
.nDQS_COL0 (nDQS_COL0),
.nDQS_COL1 (nDQS_COL1),
.nDQS_COL2 (nDQS_COL2),
.nDQS_COL3 (nDQS_COL3),
.DQS_LOC_COL0 (DQS_LOC_COL0),
.DQS_LOC_COL1 (DQS_LOC_COL1),
.DQS_LOC_COL2 (DQS_LOC_COL2),
.DQS_LOC_COL3 (DQS_LOC_COL3),
.tPRDI (tPRDI),
.tREFI (tREFI),
.tZQI (tZQI),
.BURST_MODE (BURST_MODE),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.tCK (tCK),
.ADDR_WIDTH (ADDR_WIDTH),
.TCQ (TCQ),
.ECC (ECC),
.ECC_TEST (ECC_TEST),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH)
)
u_memc_ui_top
(
.clk (clk),
.clk_mem (clk_mem),
.clk_rd_base (clk_rd_base),
.rst (rst),
.ddr_addr (ddr3_addr),
.ddr_ba (ddr3_ba),
.ddr_cas_n (ddr3_cas_n),
.ddr_ck_n (ddr3_ck_n),
.ddr_ck (ddr3_ck_p),
.ddr_cke (ddr3_cke),
.ddr_cs_n (ddr3_cs_n),
.ddr_dm (ddr3_dm),
.ddr_odt (ddr3_odt),
.ddr_ras_n (ddr3_ras_n),
.ddr_reset_n (ddr3_reset_n),
.ddr_parity (ddr3_parity),
.ddr_we_n (ddr3_we_n),
.ddr_dq (ddr3_dq),
.ddr_dqs_n (ddr3_dqs_n),
.ddr_dqs (ddr3_dqs_p),
.pd_PSEN (pd_PSEN),
.pd_PSINCDEC (pd_PSINCDEC),
.pd_PSDONE (pd_PSDONE),
.phy_init_done (phy_init_done),
.bank_mach_next (bank_mach_next),
.app_ecc_multiple_err (app_ecc_multiple_err_i),
.app_rd_data (app_rd_data),
.app_rd_data_end (app_rd_data_end),
.app_rd_data_valid (app_rd_data_valid),
.app_rdy (app_rdy),
.app_wdf_rdy (app_wdf_rdy),
.app_addr (app_addr),
.app_cmd (app_cmd),
.app_en (app_en),
.app_hi_pri (app_hi_pri),
.app_sz (1'b1),
.app_wdf_data (app_wdf_data),
.app_wdf_end (app_wdf_end),
.app_wdf_mask (app_wdf_mask),
.app_wdf_wren (app_wdf_wren),
.app_correct_en (1'b1),
.dbg_wr_dqs_tap_set (dbg_wr_dqs_tap_set),
.dbg_wr_dq_tap_set (dbg_wr_dq_tap_set),
.dbg_wr_tap_set_en (dbg_wr_tap_set_en),
.dbg_wrlvl_start (dbg_wrlvl_start),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wl_dqs_inverted (dbg_wl_dqs_inverted),
.dbg_wr_calib_clk_delay (dbg_wr_calib_clk_delay),
.dbg_wl_odelay_dqs_tap_cnt (dbg_wl_odelay_dqs_tap_cnt),
.dbg_wl_odelay_dq_tap_cnt (dbg_wl_odelay_dq_tap_cnt),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_rd_bitslip_cnt (dbg_rd_bitslip_cnt),
.dbg_rd_clkdly_cnt (dbg_rd_clkdly_cnt),
.dbg_rd_active_dly (dbg_rd_active_dly),
.dbg_pd_off (dbg_pd_off),
.dbg_pd_maintain_off (dbg_pd_maintain_off),
.dbg_pd_maintain_0_only (dbg_pd_maintain_0_only),
.dbg_inc_cpt (dbg_inc_cpt),
.dbg_dec_cpt (dbg_dec_cpt),
.dbg_inc_rd_dqs (dbg_inc_rd_dqs),
.dbg_dec_rd_dqs (dbg_dec_rd_dqs),
.dbg_inc_dec_sel (dbg_inc_dec_sel),
.dbg_inc_rd_fps (dbg_inc_rd_fps),
.dbg_dec_rd_fps (dbg_dec_rd_fps),
.dbg_dqs_tap_cnt (dbg_dqs_tap_cnt),
.dbg_dq_tap_cnt (dbg_dq_tap_cnt),
.dbg_rddata (dbg_rddata)
);
/*ftl_top ftl_top_instance(
.reset(rst),
.clk(clk),
.phy_init_done(phy_init_done),
//dram
.dram_ready_i(app_rdy),
.rd_data_valid_i(app_rd_data_valid),
.data_from_dram_i(app_rd_data),
.dram_en_o(app_en),
.dram_rd_wr_o(app_cmd[0]),
.addr_to_dram_o(app_addr),
.data_to_dram_o(app_wdf_data),
.dram_data_mask_o(app_wdf_mask),
.data_to_dram_en(app_wdf_wren),
.data_to_dram_end(app_wdf_end),
.data_to_dram_ready(app_wdf_rdy)
//.initial_dram_done(initial_dram_done)
);*/
pcie_2_0_ep pcie_module(
// system interface
.sys_clk_p(pcie_clk_p),
.sys_clk_n(pcie_clk_n),
.sys_reset_n(pcie_rst_n),
//pcie tx and rx bus
.pci_exp_txp(pci_exp_txp),
.pci_exp_txn(pci_exp_txn),
.pci_exp_rxp(pci_exp_rxp),
.pci_exp_rxn(pci_exp_rxn),
//pcie-ftl-fifo interface
//fifo clk from pcie
.fifo_clk(fifo_pcie_clk),
//ftl2pcie cmd fifo
//.cmd_fifo_empty_i(pcie_command_send_fifo_out_empty),
//.cmd_fifo_almost_empty_i(pcie_command_send_fifo_out_almost_empty),
//.cmd_fifo_rd_en_o(pcie_command_send_fifo_out_en),
//.cmd_fifo_dout_i(pcie_command_send_fifo_out),
.FTLCMG_cmd_fifo_empty_i(FTLCMG_cmd_fifo_empty),
.FTLCMG_cmd_fifo_almost_empty_i(FTLCMG_cmd_fifo_almost_empty),
.FTLCMG_cmd_fifo_rd_en_o(FTLCMG_cmd_fifo_rd_en),
.FTLCMG_cmd_fifo_data_i(FTLCMG_cmd_fifo_data),
//ftl2pcie data fifo
//.data_fifo_empty_i(pcie_data_send_fifo_out_empty),
//.data_fifo_almost_empty_i(pcie_data_send_fifo_out_almost_empty),
//.data_fifo_rd_en_o(pcie_data_send_fifo_out_en),
//.data_fifo_dout_i(pcie_data_send_fifo_out),
.TX_data_fifo_empty_i(TX_data_fifo_empty),
.TX_data_fifo_almost_empty_i(TX_data_fifo_almost_empty),
.TX_data_fifo_rd_en_o(TX_data_fifo_rd_en),
.TX_data_fifo_data_i(TX_data_fifo_data),
//pcie2ftl cmd fifo
//.cmd_fifo_full_i(pcie_command_rec_fifo_out_full),
//.cmd_fifo_almost_full_i(pcie_command_rec_fifo_out_almost_full),
//.cmd_fifo_wr_en_o(pcie_command_rec_fifo_in_en),
//.cmd_fifo_din_o(pcie_command_rec_fifo_in),
.CMGFTL_cmd_fifo_full_i(CMGFTL_cmd_fifo_full),
.CMGFTL_cmd_fifo_almost_full_i(CMGFTL_cmd_fifo_almost_full),
.CMGFTL_cmd_fifo_wr_en_o(CMGFTL_cmd_fifo_wr_en),
.CMGFTL_cmd_fifo_data_o(CMGFTL_cmd_fifo_data),
//pcie2ftl data fifo
//.data_fifo_full_i(pcie_data_rec_fifo_out_full),
//.data_fifo_almost_full_i(pcie_data_rec_fifo_out_almost_full),
//.data_fifo_wr_en_o(pcie_data_rec_fifo_in_en),
//.data_fifo_din_o(pcie_data_rec_fifo_in)
.RX_data_fifo_full_i(RX_data_fifo_full),
.RX_data_fifo_almost_full_i(RX_data_fifo_almost_full),
.RX_data_fifo_wr_en_o(RX_data_fifo_wr_en),
.RX_data_fifo_data_o(RX_data_fifo_data),
.RX_data_fifo_av_i(RX_data_fifo_av)
);
pcie_data_rec_fifo pcie2ftl_data_rec_fifo ( //data_fifo write_depth 16384 read_depth 8192
.rst(rst), // input rst
.wr_clk(fifo_pcie_clk), // input wr_clk
.rd_clk(clk), // input rd_clk
.din(RX_data_fifo_data), // input [127 : 0] din
.wr_en(RX_data_fifo_wr_en), // input wr_en
.rd_en(pcie_data_rec_fifo_out_en), // input rd_en
.dout(pcie_data_rec_fifo_out), // output [255 : 0] dout
.full(RX_data_fifo_full), // output full
.almost_full(RX_data_fifo_almost_full), // output almost_full
.empty(), // output empty
.almost_empty(), // output almost_empty
.rd_data_count(), // output [12 : 0] rd_data_count
.wr_data_count(), // output [13 : 0] wr_data_count
.prog_full(pcie_data_rec_fifo_prog_full) // output prog_full
);
pcie_command_rec_fifo pcie2ftl_command_rec_fifo (//depth 64
.rst(rst), // input rst
.wr_clk(fifo_pcie_clk), // input wr_clk
.rd_clk(clk), // input rd_clk
.din(CMGFTL_cmd_fifo_data), // input [127 : 0] din
.wr_en(CMGFTL_cmd_fifo_wr_en), // input wr_en
.rd_en(pcie_command_rec_fifo_out_en), // input rd_en
.dout(pcie_command_rec_fifo_out), // output [127 : 0] dout
.full(CMGFTL_cmd_fifo_full), // output full
.almost_full(CMGFTL_cmd_fifo_almost_full), // output almost_full
.empty(pcie_command_rec_fifo_empty_or_not), // output empty
.almost_empty(), // output almost_empty
.rd_data_count(), // output [5 : 0] rd_data_count
.wr_data_count() // output [5 : 0] wr_data_count
);
pcie_data_send_fifo ftl2pcie_data_send_fifo (
.rst(rst), // input rst
.wr_clk(clk), // input wr_clk
.rd_clk(fifo_pcie_clk), // input rd_clk
.din(pcie_data_send_fifo_in), // input [255 : 0] din
.wr_en(pcie_data_send_fifo_in_en), // input wr_en
.rd_en(TX_data_fifo_rd_en), // input rd_en
.dout(TX_data_fifo_data), // output [127 : 0] dout
.full(), // output full
.almost_full(), // output almost_full
.empty(TX_data_fifo_empty), // output empty
.almost_empty(TX_data_fifo_almost_empty), // output almost_empty
.rd_data_count(), // output [13 : 0] rd_data_count
.wr_data_count(), // output [12 : 0] wr_data_count
.prog_full(pcie_data_send_fifo_out_prog_full) // output prog_full
);
pcie_command_send_fifo ftl2pcie_command_send_fifo (//depth 16
.rst(rst), // input rst
.wr_clk(clk), // input wr_clk
.rd_clk(fifo_pcie_clk), // input rd_clk
.din(pcie_command_send_fifo_in), // input [127 : 0] din
.wr_en(pcie_command_send_fifo_in_en), // input wr_en
.rd_en(FTLCMG_cmd_fifo_rd_en), // input rd_en
.dout(FTLCMG_cmd_fifo_data), // output [127 : 0] dout
.full(pcie_command_send_fifo_full_or_not), // output full
.almost_full(), // output almost_full
.empty(FTLCMG_cmd_fifo_empty), // output empty
.almost_empty(FTLCMG_cmd_fifo_almost_empty), // output almost_empty
.rd_data_count(), // output [3 : 0] rd_data_count
.wr_data_count() // output [3: 0] wr_data_count
);
ftl_top ftl_top_instance(
.reset(rst),
.clk(clk),
.clk_83X2M(clk_83X2M),
.clk_83M(clk_83M),
.clk_83M_reverse(clk_83M_reverse),
.phy_init_done(phy_init_done),
//pcie
.pcie_data_rec_fifo_out(pcie_data_rec_fifo_out),
.pcie_data_rec_fifo_out_en(pcie_data_rec_fifo_out_en),
.pcie_command_rec_fifo_out(pcie_command_rec_fifo_out),
.pcie_command_rec_fifo_empty_or_not(pcie_command_rec_fifo_empty_or_not),
.pcie_command_rec_fifo_out_en(pcie_command_rec_fifo_out_en),
.pcie_data_send_fifo_in(pcie_data_send_fifo_in),
.pcie_data_send_fifo_in_en(pcie_data_send_fifo_in_en),
.pcie_data_send_fifo_out_prog_full(pcie_data_send_fifo_out_prog_full),
.pcie_command_send_fifo_full_or_not(pcie_command_send_fifo_full_or_not),
.pcie_command_send_fifo_in(pcie_command_send_fifo_in),
.pcie_command_send_fifo_in_en(pcie_command_send_fifo_in_en),
//dram
.dram_ready(app_rdy),
.rd_data_valid(app_rd_data_valid),
.data_from_dram(app_rd_data),
.dram_en(app_en),
.dram_read_or_write(app_cmd[0]),
.addr_to_dram(app_addr),
.data_to_dram(app_wdf_data),
.dram_data_mask(app_wdf_mask),
.data_to_dram_en(app_wdf_wren),
.data_to_dram_end(app_wdf_end),
.data_to_dram_ready(app_wdf_rdy),
.initial_dram_done(initial_dram_done),
//flash_controller
.nand0Cle(nand0Cle),
.nand0Ale(nand0Ale),
.nand0Clk_We_n(nand0Clk_We_n),
.nand0Wr_Re_n(nand0Wr_Re_n),
.nand0Wp_n(nand0Wp_n),
.nand0Ce_n(nand0Ce_n),
.nand0Rb_n(nand0Rb_n),
.nand0DQX(nand0DQX),
.nand0DQS(nand0DQS),
.nand1Cle(nand1Cle),
.nand1Ale(nand1Ale),
.nand1Clk_We_n(nand1Clk_We_n),
.nand1Wr_Re_n(nand1Wr_Re_n),
.nand1Wp_n(nand1Wp_n),
.nand1Ce_n(nand1Ce_n),
.nand1Rb_n(nand1Rb_n),
.nand1DQX(nand1DQX),
.nand1DQS(nand1DQS),
.nand2Cle(nand2Cle),
.nand2Ale(nand2Ale),
.nand2Clk_We_n(nand2Clk_We_n),
.nand2Wr_Re_n(nand2Wr_Re_n),
.nand2Wp_n(nand2Wp_n),
.nand2Ce_n(nand2Ce_n),
.nand2Rb_n(nand2Rb_n),
.nand2DQX(nand2DQX),
.nand2DQS(nand2DQS),
.nand3Cle(nand3Cle),
.nand3Ale(nand3Ale),
.nand3Clk_We_n(nand3Clk_We_n),
.nand3Wr_Re_n(nand3Wr_Re_n),
.nand3Wp_n(nand3Wp_n),
.nand3Ce_n(nand3Ce_n),
.nand3Rb_n(nand3Rb_n),
.nand3DQX(nand3DQX),
.nand3DQS(nand3DQS),
.nand4Cle(nand4Cle),
.nand4Ale(nand4Ale),
.nand4Clk_We_n(nand4Clk_We_n),
.nand4Wr_Re_n(nand4Wr_Re_n),
.nand4Wp_n(nand4Wp_n),
.nand4Ce_n(nand4Ce_n),
.nand4Rb_n(nand4Rb_n),
.nand4DQX(nand4DQX),
.nand4DQS(nand4DQS),
.nand5Cle(nand5Cle),
.nand5Ale(nand5Ale),
.nand5Clk_We_n(nand5Clk_We_n),
.nand5Wr_Re_n(nand5Wr_Re_n),
.nand5Wp_n(nand5Wp_n),
.nand5Ce_n(nand5Ce_n),
.nand5Rb_n(nand5Rb_n),
.nand5DQX(nand5DQX),
.nand5DQS(nand5DQS),
.nand6Cle(nand6Cle),
.nand6Ale(nand6Ale),
.nand6Clk_We_n(nand6Clk_We_n),
.nand6Wr_Re_n(nand6Wr_Re_n),
.nand6Wp_n(nand6Wp_n),
.nand6Ce_n(nand6Ce_n),
.nand6Rb_n(nand6Rb_n),
.nand6DQX(nand6DQX),
.nand6DQS(nand6DQS),
.nand7Cle(nand7Cle),
.nand7Ale(nand7Ale),
.nand7Clk_We_n(nand7Clk_We_n),
.nand7Wr_Re_n(nand7Wr_Re_n),
.nand7Wp_n(nand7Wp_n),
.nand7Ce_n(nand7Ce_n),
.nand7Rb_n(nand7Rb_n),
.nand7DQX(nand7DQX),
.nand7DQS(nand7DQS)
);
endmodule
|
//
// Generated by Bluespec Compiler, version 2013.01.beta1 (build 30202, 2013-01-08)
//
// On Tue Jan 22 07:12:40 EST 2013
//
//
// Ports:
// Name I/O size props
// RDY_host_request_put O 1 reg
// host_response_get O 8 reg
// RDY_host_response_get O 1 reg
// client_request_get O 59 reg
// RDY_client_request_get O 1 reg
// RDY_client_response_put O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// host_request_put I 8 reg
// client_response_put I 40 reg
// EN_host_request_put I 1
// EN_client_response_put I 1
// EN_host_response_get I 1
// EN_client_request_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkSimDCP(CLK,
RST_N,
host_request_put,
EN_host_request_put,
RDY_host_request_put,
EN_host_response_get,
host_response_get,
RDY_host_response_get,
EN_client_request_get,
client_request_get,
RDY_client_request_get,
client_response_put,
EN_client_response_put,
RDY_client_response_put);
input CLK;
input RST_N;
// action method host_request_put
input [7 : 0] host_request_put;
input EN_host_request_put;
output RDY_host_request_put;
// actionvalue method host_response_get
input EN_host_response_get;
output [7 : 0] host_response_get;
output RDY_host_response_get;
// actionvalue method client_request_get
input EN_client_request_get;
output [58 : 0] client_request_get;
output RDY_client_request_get;
// action method client_response_put
input [39 : 0] client_response_put;
input EN_client_response_put;
output RDY_client_response_put;
// signals for module outputs
wire [58 : 0] client_request_get;
wire [7 : 0] host_response_get;
wire RDY_client_request_get,
RDY_client_response_put,
RDY_host_request_put,
RDY_host_response_get;
// inlined wires
wire eDoReq_1$wget,
eDoReq_1$whas,
edpFsm_abort$wget,
edpFsm_abort$whas,
edpFsm_start_reg_2$wget,
edpFsm_start_reg_2$whas,
edpFsm_start_wire$wget,
edpFsm_start_wire$whas,
edpFsm_state_fired_1$wget,
edpFsm_state_fired_1$whas,
edpFsm_state_overlap_pw$whas,
edpFsm_state_set_pw$whas;
// register doInFlight
reg doInFlight;
wire doInFlight$D_IN, doInFlight$EN;
// register eAddr
reg [31 : 0] eAddr;
reg [31 : 0] eAddr$D_IN;
wire eAddr$EN;
// register eDMH
reg [31 : 0] eDMH;
reg [31 : 0] eDMH$D_IN;
wire eDMH$EN;
// register eData
reg [31 : 0] eData;
reg [31 : 0] eData$D_IN;
wire eData$EN;
// register eDoReq
reg eDoReq;
wire eDoReq$D_IN, eDoReq$EN;
// register ePli
reg [15 : 0] ePli;
wire [15 : 0] ePli$D_IN;
wire ePli$EN;
// register edpFsm_start_reg
reg edpFsm_start_reg;
wire edpFsm_start_reg$D_IN, edpFsm_start_reg$EN;
// register edpFsm_start_reg_1
reg edpFsm_start_reg_1;
wire edpFsm_start_reg_1$D_IN, edpFsm_start_reg_1$EN;
// register edpFsm_state_can_overlap
reg edpFsm_state_can_overlap;
wire edpFsm_state_can_overlap$D_IN, edpFsm_state_can_overlap$EN;
// register edpFsm_state_fired
reg edpFsm_state_fired;
wire edpFsm_state_fired$D_IN, edpFsm_state_fired$EN;
// register edpFsm_state_mkFSMstate
reg [3 : 0] edpFsm_state_mkFSMstate;
reg [3 : 0] edpFsm_state_mkFSMstate$D_IN;
wire edpFsm_state_mkFSMstate$EN;
// register eeDat
reg [31 : 0] eeDat;
wire [31 : 0] eeDat$D_IN;
wire eeDat$EN;
// register eeDmh
reg [31 : 0] eeDmh;
wire [31 : 0] eeDmh$D_IN;
wire eeDmh$EN;
// register eePli
reg [15 : 0] eePli;
reg [15 : 0] eePli$D_IN;
wire eePli$EN;
// register isWrtResp
reg isWrtResp;
wire isWrtResp$D_IN, isWrtResp$EN;
// register lastResp
reg [44 : 0] lastResp;
wire [44 : 0] lastResp$D_IN;
wire lastResp$EN;
// register lastTag
reg [8 : 0] lastTag;
wire [8 : 0] lastTag$D_IN;
wire lastTag$EN;
// register ptr
reg [3 : 0] ptr;
wire [3 : 0] ptr$D_IN;
wire ptr$EN;
// ports of submodule cpReqF
wire [58 : 0] cpReqF$D_IN, cpReqF$D_OUT;
wire cpReqF$CLR, cpReqF$DEQ, cpReqF$EMPTY_N, cpReqF$ENQ, cpReqF$FULL_N;
// ports of submodule cpRespF
wire [39 : 0] cpRespF$D_IN, cpRespF$D_OUT;
wire cpRespF$CLR, cpRespF$DEQ, cpRespF$EMPTY_N, cpRespF$ENQ, cpRespF$FULL_N;
// ports of submodule dcpReqF
reg [78 : 0] dcpReqF$D_IN;
wire [78 : 0] dcpReqF$D_OUT;
wire dcpReqF$CLR, dcpReqF$DEQ, dcpReqF$EMPTY_N, dcpReqF$ENQ, dcpReqF$FULL_N;
// ports of submodule dcpRespF
wire [44 : 0] dcpRespF$D_IN, dcpRespF$D_OUT;
wire dcpRespF$CLR,
dcpRespF$DEQ,
dcpRespF$EMPTY_N,
dcpRespF$ENQ,
dcpRespF$FULL_N;
// ports of submodule simReqF
wire [7 : 0] simReqF$D_IN, simReqF$D_OUT;
wire simReqF$CLR, simReqF$DEQ, simReqF$EMPTY_N, simReqF$ENQ, simReqF$FULL_N;
// ports of submodule simRespF
reg [7 : 0] simRespF$D_IN;
wire [7 : 0] simRespF$D_OUT;
wire simRespF$CLR,
simRespF$DEQ,
simRespF$EMPTY_N,
simRespF$ENQ,
simRespF$FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_cp_to_dcp_response,
WILL_FIRE_RL_dcp_to_cp_request,
WILL_FIRE_RL_edpFsm_action_l220c14,
WILL_FIRE_RL_edpFsm_action_l221c14,
WILL_FIRE_RL_edpFsm_action_l222c14,
WILL_FIRE_RL_edpFsm_action_l223c14,
WILL_FIRE_RL_edpFsm_action_l224c14,
WILL_FIRE_RL_edpFsm_action_l225c14,
WILL_FIRE_RL_edpFsm_action_l227c16,
WILL_FIRE_RL_edpFsm_action_l228c16,
WILL_FIRE_RL_edpFsm_action_l229c16,
WILL_FIRE_RL_edpFsm_action_l230c16,
WILL_FIRE_RL_edpFsm_fsm_start,
WILL_FIRE_RL_edpFsm_idle_l219c3,
WILL_FIRE_RL_edpFsm_idle_l219c3_1,
WILL_FIRE_RL_rx_sim_dcp,
WILL_FIRE_RL_sim_egress,
WILL_FIRE_RL_sim_ingress;
// inputs to muxes for submodule ports
reg [44 : 0] MUX_dcpRespF$enq_1__VAL_1;
wire [44 : 0] MUX_dcpRespF$enq_1__VAL_2;
wire MUX_dcpRespF$enq_1__SEL_1,
MUX_doInFlight$write_1__SEL_1,
MUX_edpFsm_state_mkFSMstate$write_1__SEL_1;
// remaining internal signals
reg [63 : 0] v__h26988,
v__h27142,
v__h27335,
v__h3777,
v__h3791,
v__h3805,
v__h4532,
v__h5089;
reg [7 : 0] CASE_dcpRespFD_OUT_BITS_44_TO_43_0_IF_dcpResp_ETC__q4;
reg [1 : 0] CASE_lastResp_BITS_44_TO_43_0_lastResp_BITS_44_ETC__q3;
reg CASE_dcpReqFD_OUT_BITS_78_TO_77_0_dcpRespFFU_ETC__q2,
CASE_eDMH_BITS_13_TO_12_0_dcpReqFFULL_N_0b1_d_ETC__q1;
wire [31 : 0] x__h1896,
x__h1913,
x__h1958,
x__h2003,
x__h2062,
x__h2107,
x__h2151,
x__h2210,
x__h2255,
x__h2299;
wire [15 : 0] x__h1866, y__h1877;
wire [7 : 0] IF_dcpRespF_first__35_BIT_42_42_THEN_0x70_ELSE_ETC___d343;
wire IF_NOT_dcpReqF_first__33_BITS_39_TO_32_51_EQ_I_ETC___d158,
NOT_dcpReqF_first__33_BITS_78_TO_77_34_EQ_0_35_ETC___d221,
dcpReqF_first__33_BITS_39_TO_32_51_EQ_IF_lastT_ETC___d152,
dcpReqF_first__33_BITS_71_TO_64_38_EQ_IF_lastT_ETC___d143,
dcpReqF_first__33_BITS_78_TO_77_34_EQ_0_35_OR__ETC___d166,
dcpReqF_first__33_BITS_78_TO_77_34_EQ_1_37_AND_ETC___d207,
edpFsm_abort_whas__35_AND_edpFsm_abort_wget__3_ETC___d324,
edpFsm_abort_whas__35_AND_edpFsm_abort_wget__3_ETC___d332;
// action method host_request_put
assign RDY_host_request_put = simReqF$FULL_N ;
// actionvalue method host_response_get
assign host_response_get = simRespF$D_OUT ;
assign RDY_host_response_get = simRespF$EMPTY_N ;
// actionvalue method client_request_get
assign client_request_get = cpReqF$D_OUT ;
assign RDY_client_request_get = cpReqF$EMPTY_N ;
// action method client_response_put
assign RDY_client_response_put = cpRespF$FULL_N ;
// submodule cpReqF
FIFO2 #(.width(32'd59), .guarded(32'd1)) cpReqF(.RST(RST_N),
.CLK(CLK),
.D_IN(cpReqF$D_IN),
.ENQ(cpReqF$ENQ),
.DEQ(cpReqF$DEQ),
.CLR(cpReqF$CLR),
.D_OUT(cpReqF$D_OUT),
.FULL_N(cpReqF$FULL_N),
.EMPTY_N(cpReqF$EMPTY_N));
// submodule cpRespF
FIFO2 #(.width(32'd40), .guarded(32'd1)) cpRespF(.RST(RST_N),
.CLK(CLK),
.D_IN(cpRespF$D_IN),
.ENQ(cpRespF$ENQ),
.DEQ(cpRespF$DEQ),
.CLR(cpRespF$CLR),
.D_OUT(cpRespF$D_OUT),
.FULL_N(cpRespF$FULL_N),
.EMPTY_N(cpRespF$EMPTY_N));
// submodule dcpReqF
FIFO2 #(.width(32'd79), .guarded(32'd1)) dcpReqF(.RST(RST_N),
.CLK(CLK),
.D_IN(dcpReqF$D_IN),
.ENQ(dcpReqF$ENQ),
.DEQ(dcpReqF$DEQ),
.CLR(dcpReqF$CLR),
.D_OUT(dcpReqF$D_OUT),
.FULL_N(dcpReqF$FULL_N),
.EMPTY_N(dcpReqF$EMPTY_N));
// submodule dcpRespF
FIFO2 #(.width(32'd45), .guarded(32'd1)) dcpRespF(.RST(RST_N),
.CLK(CLK),
.D_IN(dcpRespF$D_IN),
.ENQ(dcpRespF$ENQ),
.DEQ(dcpRespF$DEQ),
.CLR(dcpRespF$CLR),
.D_OUT(dcpRespF$D_OUT),
.FULL_N(dcpRespF$FULL_N),
.EMPTY_N(dcpRespF$EMPTY_N));
// submodule simReqF
FIFO2 #(.width(32'd8), .guarded(32'd1)) simReqF(.RST(RST_N),
.CLK(CLK),
.D_IN(simReqF$D_IN),
.ENQ(simReqF$ENQ),
.DEQ(simReqF$DEQ),
.CLR(simReqF$CLR),
.D_OUT(simReqF$D_OUT),
.FULL_N(simReqF$FULL_N),
.EMPTY_N(simReqF$EMPTY_N));
// submodule simRespF
FIFO2 #(.width(32'd8), .guarded(32'd1)) simRespF(.RST(RST_N),
.CLK(CLK),
.D_IN(simRespF$D_IN),
.ENQ(simRespF$ENQ),
.DEQ(simRespF$DEQ),
.CLR(simRespF$CLR),
.D_OUT(simRespF$D_OUT),
.FULL_N(simRespF$FULL_N),
.EMPTY_N(simRespF$EMPTY_N));
// rule RL_sim_ingress
assign WILL_FIRE_RL_sim_ingress = simReqF$EMPTY_N && !eDoReq ;
// rule RL_rx_sim_dcp
assign WILL_FIRE_RL_rx_sim_dcp =
CASE_eDMH_BITS_13_TO_12_0_dcpReqFFULL_N_0b1_d_ETC__q1 && eDoReq ;
// rule RL_dcp_to_cp_request
assign WILL_FIRE_RL_dcp_to_cp_request =
dcpReqF$EMPTY_N &&
CASE_dcpReqFD_OUT_BITS_78_TO_77_0_dcpRespFFU_ETC__q2 ;
// rule RL_cp_to_dcp_response
assign WILL_FIRE_RL_cp_to_dcp_response =
dcpRespF$FULL_N && cpRespF$EMPTY_N &&
!WILL_FIRE_RL_dcp_to_cp_request ;
// rule RL_edpFsm_action_l221c14
assign WILL_FIRE_RL_edpFsm_action_l221c14 =
simRespF$FULL_N && edpFsm_state_mkFSMstate == 4'd1 ;
// rule RL_edpFsm_action_l222c14
assign WILL_FIRE_RL_edpFsm_action_l222c14 =
simRespF$FULL_N && edpFsm_state_mkFSMstate == 4'd2 ;
// rule RL_edpFsm_action_l223c14
assign WILL_FIRE_RL_edpFsm_action_l223c14 =
simRespF$FULL_N && edpFsm_state_mkFSMstate == 4'd3 ;
// rule RL_edpFsm_action_l224c14
assign WILL_FIRE_RL_edpFsm_action_l224c14 =
simRespF$FULL_N && edpFsm_state_mkFSMstate == 4'd4 ;
// rule RL_edpFsm_action_l225c14
assign WILL_FIRE_RL_edpFsm_action_l225c14 =
simRespF$FULL_N && edpFsm_state_mkFSMstate == 4'd5 ;
// rule RL_edpFsm_action_l227c16
assign WILL_FIRE_RL_edpFsm_action_l227c16 =
simRespF$FULL_N && !isWrtResp &&
edpFsm_state_mkFSMstate == 4'd6 ;
// rule RL_edpFsm_action_l228c16
assign WILL_FIRE_RL_edpFsm_action_l228c16 =
simRespF$FULL_N && edpFsm_state_mkFSMstate == 4'd7 ;
// rule RL_edpFsm_action_l229c16
assign WILL_FIRE_RL_edpFsm_action_l229c16 =
simRespF$FULL_N && edpFsm_state_mkFSMstate == 4'd8 ;
// rule RL_edpFsm_action_l230c16
assign WILL_FIRE_RL_edpFsm_action_l230c16 =
simRespF$FULL_N && edpFsm_state_mkFSMstate == 4'd9 ;
// rule RL_edpFsm_fsm_start
assign WILL_FIRE_RL_edpFsm_fsm_start =
(edpFsm_abort_whas__35_AND_edpFsm_abort_wget__3_ETC___d324 ||
edpFsm_state_mkFSMstate == 4'd10) &&
(!edpFsm_start_reg_1 || edpFsm_state_fired) &&
edpFsm_start_reg ;
// rule RL_edpFsm_action_l220c14
assign WILL_FIRE_RL_edpFsm_action_l220c14 =
simRespF$FULL_N &&
(edpFsm_start_wire$whas && edpFsm_state_mkFSMstate == 4'd0 ||
isWrtResp && edpFsm_start_wire$whas &&
edpFsm_state_mkFSMstate == 4'd6 ||
edpFsm_start_wire$whas && edpFsm_state_mkFSMstate == 4'd10) ;
// rule RL_edpFsm_idle_l219c3
assign WILL_FIRE_RL_edpFsm_idle_l219c3 =
isWrtResp && !edpFsm_start_wire$whas &&
edpFsm_state_mkFSMstate == 4'd6 ;
// rule RL_sim_egress
assign WILL_FIRE_RL_sim_egress =
edpFsm_abort_whas__35_AND_edpFsm_abort_wget__3_ETC___d332 &&
dcpRespF$EMPTY_N ;
// rule RL_edpFsm_idle_l219c3_1
assign WILL_FIRE_RL_edpFsm_idle_l219c3_1 =
!edpFsm_start_wire$whas && edpFsm_state_mkFSMstate == 4'd10 ;
// inputs to muxes for submodule ports
assign MUX_dcpRespF$enq_1__SEL_1 =
WILL_FIRE_RL_dcp_to_cp_request &&
dcpReqF_first__33_BITS_78_TO_77_34_EQ_0_35_OR__ETC___d166 ;
assign MUX_doInFlight$write_1__SEL_1 =
WILL_FIRE_RL_dcp_to_cp_request &&
(dcpReqF$D_OUT[78:77] == 2'd0 && dcpReqF$D_OUT[40] ||
dcpReqF$D_OUT[78:77] != 2'd0 &&
(dcpReqF$D_OUT[78:77] == 2'd1 && dcpReqF$D_OUT[76] ||
dcpReqF$D_OUT[78:77] != 2'd1 && dcpReqF$D_OUT[44])) ;
assign MUX_edpFsm_state_mkFSMstate$write_1__SEL_1 =
WILL_FIRE_RL_edpFsm_idle_l219c3_1 ||
WILL_FIRE_RL_edpFsm_idle_l219c3 ;
always@(dcpReqF$D_OUT or
CASE_lastResp_BITS_44_TO_43_0_lastResp_BITS_44_ETC__q3 or lastResp)
begin
case (dcpReqF$D_OUT[78:77])
2'd0:
MUX_dcpRespF$enq_1__VAL_1 =
{ 2'd0,
dcpReqF$D_OUT[40],
32'h40000001,
dcpReqF$D_OUT[39:32],
2'd0 };
2'd1:
MUX_dcpRespF$enq_1__VAL_1 =
{ dcpReqF$D_OUT[78:77],
32'hAAAAAAAA,
dcpReqF$D_OUT[76],
dcpReqF$D_OUT[71:64],
2'd0 };
default: MUX_dcpRespF$enq_1__VAL_1 =
{ CASE_lastResp_BITS_44_TO_43_0_lastResp_BITS_44_ETC__q3,
lastResp[42:0] };
endcase
end
assign MUX_dcpRespF$enq_1__VAL_2 =
{ 2'd2,
doInFlight,
cpRespF$D_OUT[31:0],
cpRespF$D_OUT[39:32],
2'd0 } ;
// inlined wires
assign eDoReq_1$wget = ptr == ((eDMH[13:12] == 2'b01) ? 4'd13 : 4'd9) ;
assign eDoReq_1$whas = WILL_FIRE_RL_sim_ingress ;
assign edpFsm_start_wire$wget = 1'd1 ;
assign edpFsm_start_wire$whas =
WILL_FIRE_RL_edpFsm_fsm_start ||
edpFsm_start_reg_1 && !edpFsm_state_fired ;
assign edpFsm_start_reg_2$wget = 1'd1 ;
assign edpFsm_start_reg_2$whas = edpFsm_start_wire$whas ;
assign edpFsm_abort$wget = 1'b0 ;
assign edpFsm_abort$whas = 1'b0 ;
assign edpFsm_state_fired_1$wget = 1'd1 ;
assign edpFsm_state_fired_1$whas = edpFsm_state_set_pw$whas ;
assign edpFsm_state_set_pw$whas =
WILL_FIRE_RL_edpFsm_idle_l219c3_1 ||
WILL_FIRE_RL_edpFsm_idle_l219c3 ||
WILL_FIRE_RL_edpFsm_action_l230c16 ||
WILL_FIRE_RL_edpFsm_action_l229c16 ||
WILL_FIRE_RL_edpFsm_action_l228c16 ||
WILL_FIRE_RL_edpFsm_action_l227c16 ||
WILL_FIRE_RL_edpFsm_action_l225c14 ||
WILL_FIRE_RL_edpFsm_action_l224c14 ||
WILL_FIRE_RL_edpFsm_action_l223c14 ||
WILL_FIRE_RL_edpFsm_action_l222c14 ||
WILL_FIRE_RL_edpFsm_action_l221c14 ||
WILL_FIRE_RL_edpFsm_action_l220c14 ;
assign edpFsm_state_overlap_pw$whas = 1'b0 ;
// register doInFlight
assign doInFlight$D_IN = MUX_doInFlight$write_1__SEL_1 ;
assign doInFlight$EN =
WILL_FIRE_RL_dcp_to_cp_request &&
(dcpReqF$D_OUT[78:77] == 2'd0 && dcpReqF$D_OUT[40] ||
dcpReqF$D_OUT[78:77] != 2'd0 &&
(dcpReqF$D_OUT[78:77] == 2'd1 && dcpReqF$D_OUT[76] ||
dcpReqF$D_OUT[78:77] != 2'd1 && dcpReqF$D_OUT[44])) ||
WILL_FIRE_RL_cp_to_dcp_response ;
// register eAddr
always@(ptr or x__h2151 or x__h1896 or x__h2062 or x__h2107)
begin
case (ptr)
4'd6: eAddr$D_IN = x__h1896;
4'd7: eAddr$D_IN = x__h2062;
4'd8: eAddr$D_IN = x__h2107;
default: eAddr$D_IN = x__h2151;
endcase
end
assign eAddr$EN =
WILL_FIRE_RL_sim_ingress &&
(ptr == 4'd6 || ptr == 4'd7 || ptr == 4'd8 || ptr == 4'd9) ;
// register eDMH
always@(ptr or x__h2003 or x__h1896 or x__h1913 or x__h1958)
begin
case (ptr)
4'd2: eDMH$D_IN = x__h1896;
4'd3: eDMH$D_IN = x__h1913;
4'd4: eDMH$D_IN = x__h1958;
default: eDMH$D_IN = x__h2003;
endcase
end
assign eDMH$EN =
WILL_FIRE_RL_sim_ingress &&
(ptr == 4'd2 || ptr == 4'd3 || ptr == 4'd4 || ptr == 4'd5) ;
// register eData
always@(ptr or x__h2299 or x__h1896 or x__h2210 or x__h2255)
begin
case (ptr)
4'd10: eData$D_IN = x__h1896;
4'd11: eData$D_IN = x__h2210;
4'd12: eData$D_IN = x__h2255;
default: eData$D_IN = x__h2299;
endcase
end
assign eData$EN =
WILL_FIRE_RL_sim_ingress &&
(ptr == 4'd10 || ptr == 4'd11 || ptr == 4'd12 || ptr == 4'd13) ;
// register eDoReq
assign eDoReq$D_IN = WILL_FIRE_RL_sim_ingress && eDoReq_1$wget ;
assign eDoReq$EN = 1'd1 ;
// register ePli
assign ePli$D_IN = (ptr == 4'd0) ? 16'd0 : x__h1866 ;
assign ePli$EN = WILL_FIRE_RL_sim_ingress && (ptr == 4'd0 || ptr == 4'd1) ;
// register edpFsm_start_reg
assign edpFsm_start_reg$D_IN = !WILL_FIRE_RL_edpFsm_fsm_start ;
assign edpFsm_start_reg$EN =
WILL_FIRE_RL_edpFsm_fsm_start || WILL_FIRE_RL_sim_egress ;
// register edpFsm_start_reg_1
assign edpFsm_start_reg_1$D_IN = edpFsm_start_wire$whas ;
assign edpFsm_start_reg_1$EN = 1'd1 ;
// register edpFsm_state_can_overlap
assign edpFsm_state_can_overlap$D_IN =
edpFsm_state_set_pw$whas || edpFsm_state_can_overlap ;
assign edpFsm_state_can_overlap$EN = 1'd1 ;
// register edpFsm_state_fired
assign edpFsm_state_fired$D_IN = edpFsm_state_set_pw$whas ;
assign edpFsm_state_fired$EN = 1'd1 ;
// register edpFsm_state_mkFSMstate
always@(MUX_edpFsm_state_mkFSMstate$write_1__SEL_1 or
WILL_FIRE_RL_edpFsm_action_l220c14 or
WILL_FIRE_RL_edpFsm_action_l221c14 or
WILL_FIRE_RL_edpFsm_action_l222c14 or
WILL_FIRE_RL_edpFsm_action_l223c14 or
WILL_FIRE_RL_edpFsm_action_l224c14 or
WILL_FIRE_RL_edpFsm_action_l225c14 or
WILL_FIRE_RL_edpFsm_action_l227c16 or
WILL_FIRE_RL_edpFsm_action_l228c16 or
WILL_FIRE_RL_edpFsm_action_l229c16 or
WILL_FIRE_RL_edpFsm_action_l230c16)
begin
case (1'b1) // synopsys parallel_case
MUX_edpFsm_state_mkFSMstate$write_1__SEL_1:
edpFsm_state_mkFSMstate$D_IN = 4'd0;
WILL_FIRE_RL_edpFsm_action_l220c14: edpFsm_state_mkFSMstate$D_IN = 4'd1;
WILL_FIRE_RL_edpFsm_action_l221c14: edpFsm_state_mkFSMstate$D_IN = 4'd2;
WILL_FIRE_RL_edpFsm_action_l222c14: edpFsm_state_mkFSMstate$D_IN = 4'd3;
WILL_FIRE_RL_edpFsm_action_l223c14: edpFsm_state_mkFSMstate$D_IN = 4'd4;
WILL_FIRE_RL_edpFsm_action_l224c14: edpFsm_state_mkFSMstate$D_IN = 4'd5;
WILL_FIRE_RL_edpFsm_action_l225c14: edpFsm_state_mkFSMstate$D_IN = 4'd6;
WILL_FIRE_RL_edpFsm_action_l227c16: edpFsm_state_mkFSMstate$D_IN = 4'd7;
WILL_FIRE_RL_edpFsm_action_l228c16: edpFsm_state_mkFSMstate$D_IN = 4'd8;
WILL_FIRE_RL_edpFsm_action_l229c16: edpFsm_state_mkFSMstate$D_IN = 4'd9;
WILL_FIRE_RL_edpFsm_action_l230c16:
edpFsm_state_mkFSMstate$D_IN = 4'd10;
default: edpFsm_state_mkFSMstate$D_IN =
4'b1010 /* unspecified value */ ;
endcase
end
assign edpFsm_state_mkFSMstate$EN =
WILL_FIRE_RL_edpFsm_idle_l219c3_1 ||
WILL_FIRE_RL_edpFsm_idle_l219c3 ||
WILL_FIRE_RL_edpFsm_action_l220c14 ||
WILL_FIRE_RL_edpFsm_action_l221c14 ||
WILL_FIRE_RL_edpFsm_action_l222c14 ||
WILL_FIRE_RL_edpFsm_action_l223c14 ||
WILL_FIRE_RL_edpFsm_action_l224c14 ||
WILL_FIRE_RL_edpFsm_action_l225c14 ||
WILL_FIRE_RL_edpFsm_action_l227c16 ||
WILL_FIRE_RL_edpFsm_action_l228c16 ||
WILL_FIRE_RL_edpFsm_action_l229c16 ||
WILL_FIRE_RL_edpFsm_action_l230c16 ;
// register eeDat
assign eeDat$D_IN = dcpRespF$D_OUT[41:10] ;
assign eeDat$EN = WILL_FIRE_RL_sim_egress && dcpRespF$D_OUT[44:43] != 2'd1 ;
// register eeDmh
assign eeDmh$D_IN =
{ dcpRespF$D_OUT[9:2],
CASE_dcpRespFD_OUT_BITS_44_TO_43_0_IF_dcpResp_ETC__q4,
16'h0 } ;
assign eeDmh$EN = WILL_FIRE_RL_sim_egress ;
// register eePli
always@(dcpRespF$D_OUT)
begin
case (dcpRespF$D_OUT[44:43])
2'd0: eePli$D_IN = 16'd10;
2'd1: eePli$D_IN = 16'd6;
default: eePli$D_IN = 16'd10;
endcase
end
assign eePli$EN = WILL_FIRE_RL_sim_egress ;
// register isWrtResp
assign isWrtResp$D_IN = dcpRespF$D_OUT[44:43] == 2'd1 ;
assign isWrtResp$EN = WILL_FIRE_RL_sim_egress ;
// register lastResp
assign lastResp$D_IN = MUX_dcpRespF$enq_1__VAL_2 ;
assign lastResp$EN = WILL_FIRE_RL_cp_to_dcp_response && !doInFlight ;
// register lastTag
assign lastTag$D_IN =
{ dcpReqF$D_OUT[78:77] != 2'd0,
(dcpReqF$D_OUT[78:77] == 2'd1) ?
dcpReqF$D_OUT[71:64] :
dcpReqF$D_OUT[39:32] } ;
assign lastTag$EN =
WILL_FIRE_RL_dcp_to_cp_request &&
(dcpReqF$D_OUT[78:77] == 2'd0 && !dcpReqF$D_OUT[40] ||
dcpReqF$D_OUT[78:77] != 2'd0 &&
(dcpReqF$D_OUT[78:77] == 2'd1 &&
(!dcpReqF_first__33_BITS_71_TO_64_38_EQ_IF_lastT_ETC___d143 ||
!lastTag[8]) &&
!dcpReqF$D_OUT[76] ||
dcpReqF$D_OUT[78:77] != 2'd1 &&
(!dcpReqF_first__33_BITS_39_TO_32_51_EQ_IF_lastT_ETC___d152 ||
!lastTag[8]) &&
!dcpReqF$D_OUT[44])) ;
// register ptr
assign ptr$D_IN =
(ptr == ((eDMH[13:12] == 2'b01) ? 4'd13 : 4'd9)) ?
4'd0 :
((ptr == 4'd15) ? ptr : ptr + 4'd1) ;
assign ptr$EN = WILL_FIRE_RL_sim_ingress ;
// submodule cpReqF
assign cpReqF$D_IN =
{ dcpReqF$D_OUT[78:77] != 2'd1,
(dcpReqF$D_OUT[78:77] == 2'd1) ?
{ dcpReqF$D_OUT[23:2],
dcpReqF$D_OUT[75:72],
dcpReqF$D_OUT[63:32] } :
{ 24'hAAAAAA,
dcpReqF$D_OUT[39:32],
dcpReqF$D_OUT[23:2],
dcpReqF$D_OUT[43:40] } } ;
assign cpReqF$ENQ =
WILL_FIRE_RL_dcp_to_cp_request && dcpReqF$D_OUT[78:77] != 2'd0 &&
dcpReqF_first__33_BITS_78_TO_77_34_EQ_1_37_AND_ETC___d207 ;
assign cpReqF$DEQ = EN_client_request_get ;
assign cpReqF$CLR = 1'b0 ;
// submodule cpRespF
assign cpRespF$D_IN = client_response_put ;
assign cpRespF$ENQ = EN_client_response_put ;
assign cpRespF$DEQ = WILL_FIRE_RL_cp_to_dcp_response ;
assign cpRespF$CLR = 1'b0 ;
// submodule dcpReqF
always@(eDMH or eAddr or eData)
begin
case (eDMH[13:12])
2'd0: dcpReqF$D_IN = { 38'h0AAAAAAAAA, eDMH[14], eDMH[7:0], eAddr };
2'b01:
dcpReqF$D_IN = { eDMH[13:12], eDMH[14], eDMH[11:0], eData, eAddr };
default: dcpReqF$D_IN = { 34'h2AAAAAAAA, eDMH[14], eDMH[11:0], eAddr };
endcase
end
assign dcpReqF$ENQ =
WILL_FIRE_RL_rx_sim_dcp &&
(eDMH[13:12] == 2'd0 || eDMH[13:12] == 2'b01 ||
eDMH[13:12] == 2'd2) ;
assign dcpReqF$DEQ = WILL_FIRE_RL_dcp_to_cp_request ;
assign dcpReqF$CLR = 1'b0 ;
// submodule dcpRespF
assign dcpRespF$D_IN =
MUX_dcpRespF$enq_1__SEL_1 ?
MUX_dcpRespF$enq_1__VAL_1 :
MUX_dcpRespF$enq_1__VAL_2 ;
assign dcpRespF$ENQ =
WILL_FIRE_RL_dcp_to_cp_request &&
dcpReqF_first__33_BITS_78_TO_77_34_EQ_0_35_OR__ETC___d166 ||
WILL_FIRE_RL_cp_to_dcp_response ;
assign dcpRespF$DEQ = WILL_FIRE_RL_sim_egress ;
assign dcpRespF$CLR = 1'b0 ;
// submodule simReqF
assign simReqF$D_IN = host_request_put ;
assign simReqF$ENQ = EN_host_request_put ;
assign simReqF$DEQ = WILL_FIRE_RL_sim_ingress ;
assign simReqF$CLR = 1'b0 ;
// submodule simRespF
always@(WILL_FIRE_RL_edpFsm_action_l220c14 or
eePli or
WILL_FIRE_RL_edpFsm_action_l221c14 or
WILL_FIRE_RL_edpFsm_action_l222c14 or
eeDmh or
WILL_FIRE_RL_edpFsm_action_l223c14 or
WILL_FIRE_RL_edpFsm_action_l224c14 or
WILL_FIRE_RL_edpFsm_action_l225c14 or
WILL_FIRE_RL_edpFsm_action_l227c16 or
eeDat or
WILL_FIRE_RL_edpFsm_action_l228c16 or
WILL_FIRE_RL_edpFsm_action_l229c16 or
WILL_FIRE_RL_edpFsm_action_l230c16)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_edpFsm_action_l220c14: simRespF$D_IN = eePli[15:8];
WILL_FIRE_RL_edpFsm_action_l221c14: simRespF$D_IN = eePli[7:0];
WILL_FIRE_RL_edpFsm_action_l222c14: simRespF$D_IN = eeDmh[7:0];
WILL_FIRE_RL_edpFsm_action_l223c14: simRespF$D_IN = eeDmh[15:8];
WILL_FIRE_RL_edpFsm_action_l224c14: simRespF$D_IN = eeDmh[23:16];
WILL_FIRE_RL_edpFsm_action_l225c14: simRespF$D_IN = eeDmh[31:24];
WILL_FIRE_RL_edpFsm_action_l227c16: simRespF$D_IN = eeDat[31:24];
WILL_FIRE_RL_edpFsm_action_l228c16: simRespF$D_IN = eeDat[23:16];
WILL_FIRE_RL_edpFsm_action_l229c16: simRespF$D_IN = eeDat[15:8];
WILL_FIRE_RL_edpFsm_action_l230c16: simRespF$D_IN = eeDat[7:0];
default: simRespF$D_IN = 8'b10101010 /* unspecified value */ ;
endcase
end
assign simRespF$ENQ =
WILL_FIRE_RL_edpFsm_action_l220c14 ||
WILL_FIRE_RL_edpFsm_action_l221c14 ||
WILL_FIRE_RL_edpFsm_action_l222c14 ||
WILL_FIRE_RL_edpFsm_action_l223c14 ||
WILL_FIRE_RL_edpFsm_action_l224c14 ||
WILL_FIRE_RL_edpFsm_action_l225c14 ||
WILL_FIRE_RL_edpFsm_action_l227c16 ||
WILL_FIRE_RL_edpFsm_action_l228c16 ||
WILL_FIRE_RL_edpFsm_action_l229c16 ||
WILL_FIRE_RL_edpFsm_action_l230c16 ;
assign simRespF$DEQ = EN_host_response_get ;
assign simRespF$CLR = 1'b0 ;
// remaining internal signals
assign IF_NOT_dcpReqF_first__33_BITS_39_TO_32_51_EQ_I_ETC___d158 =
(!dcpReqF_first__33_BITS_39_TO_32_51_EQ_IF_lastT_ETC___d152 ||
!lastTag[8] ||
dcpReqF$D_OUT[44]) ?
cpReqF$FULL_N :
dcpRespF$FULL_N ;
assign IF_dcpRespF_first__35_BIT_42_42_THEN_0x70_ELSE_ETC___d343 =
dcpRespF$D_OUT[42] ? 8'h70 : 8'h30 ;
assign NOT_dcpReqF_first__33_BITS_78_TO_77_34_EQ_0_35_ETC___d221 =
dcpReqF$D_OUT[78:77] != 2'd0 && dcpReqF$D_OUT[78:77] != 2'd1 &&
dcpReqF_first__33_BITS_39_TO_32_51_EQ_IF_lastT_ETC___d152 &&
lastTag[8] &&
!dcpReqF$D_OUT[44] ;
assign dcpReqF_first__33_BITS_39_TO_32_51_EQ_IF_lastT_ETC___d152 =
dcpReqF$D_OUT[39:32] == lastTag[7:0] ;
assign dcpReqF_first__33_BITS_71_TO_64_38_EQ_IF_lastT_ETC___d143 =
dcpReqF$D_OUT[71:64] == lastTag[7:0] ;
assign dcpReqF_first__33_BITS_78_TO_77_34_EQ_0_35_OR__ETC___d166 =
dcpReqF$D_OUT[78:77] == 2'd0 || dcpReqF$D_OUT[78:77] == 2'd1 ||
dcpReqF_first__33_BITS_39_TO_32_51_EQ_IF_lastT_ETC___d152 &&
lastTag[8] &&
!dcpReqF$D_OUT[44] ;
assign dcpReqF_first__33_BITS_78_TO_77_34_EQ_1_37_AND_ETC___d207 =
dcpReqF$D_OUT[78:77] == 2'd1 &&
(!dcpReqF_first__33_BITS_71_TO_64_38_EQ_IF_lastT_ETC___d143 ||
!lastTag[8] ||
dcpReqF$D_OUT[76]) ||
dcpReqF$D_OUT[78:77] != 2'd1 &&
(!dcpReqF_first__33_BITS_39_TO_32_51_EQ_IF_lastT_ETC___d152 ||
!lastTag[8] ||
dcpReqF$D_OUT[44]) ;
assign edpFsm_abort_whas__35_AND_edpFsm_abort_wget__3_ETC___d324 =
edpFsm_state_mkFSMstate == 4'd0 ||
isWrtResp && edpFsm_state_mkFSMstate == 4'd6 ;
assign edpFsm_abort_whas__35_AND_edpFsm_abort_wget__3_ETC___d332 =
(edpFsm_abort_whas__35_AND_edpFsm_abort_wget__3_ETC___d324 ||
edpFsm_state_mkFSMstate == 4'd10) &&
(!edpFsm_start_reg_1 || edpFsm_state_fired) &&
!edpFsm_start_reg ;
assign x__h1866 = ePli | y__h1877 ;
assign x__h1896 = { simReqF$D_OUT, 24'h0 } ;
assign x__h1913 = { eDMH[31:24], simReqF$D_OUT, 16'h0 } ;
assign x__h1958 = { eDMH[31:16], simReqF$D_OUT, 8'h0 } ;
assign x__h2003 = { eDMH[31:8], simReqF$D_OUT } ;
assign x__h2062 = { eAddr[31:24], simReqF$D_OUT, 16'h0 } ;
assign x__h2107 = { eAddr[31:16], simReqF$D_OUT, 8'h0 } ;
assign x__h2151 = { eAddr[31:8], simReqF$D_OUT } ;
assign x__h2210 = { eData[31:24], simReqF$D_OUT, 16'h0 } ;
assign x__h2255 = { eData[31:16], simReqF$D_OUT, 8'h0 } ;
assign x__h2299 = { eData[31:8], simReqF$D_OUT } ;
assign y__h1877 = { 8'd0, simReqF$D_OUT } ;
always@(eDMH or dcpReqF$FULL_N)
begin
case (eDMH[13:12])
2'd0, 2'b01:
CASE_eDMH_BITS_13_TO_12_0_dcpReqFFULL_N_0b1_d_ETC__q1 =
dcpReqF$FULL_N;
default: CASE_eDMH_BITS_13_TO_12_0_dcpReqFFULL_N_0b1_d_ETC__q1 =
eDMH[13:12] != 2'd2 || dcpReqF$FULL_N;
endcase
end
always@(dcpReqF$D_OUT or
IF_NOT_dcpReqF_first__33_BITS_39_TO_32_51_EQ_I_ETC___d158 or
dcpRespF$FULL_N or
dcpReqF_first__33_BITS_71_TO_64_38_EQ_IF_lastT_ETC___d143 or
lastTag or cpReqF$FULL_N)
begin
case (dcpReqF$D_OUT[78:77])
2'd0:
CASE_dcpReqFD_OUT_BITS_78_TO_77_0_dcpRespFFU_ETC__q2 =
dcpRespF$FULL_N;
2'd1:
CASE_dcpReqFD_OUT_BITS_78_TO_77_0_dcpRespFFU_ETC__q2 =
dcpRespF$FULL_N &&
(dcpReqF_first__33_BITS_71_TO_64_38_EQ_IF_lastT_ETC___d143 &&
lastTag[8] &&
!dcpReqF$D_OUT[76] ||
cpReqF$FULL_N);
default: CASE_dcpReqFD_OUT_BITS_78_TO_77_0_dcpRespFFU_ETC__q2 =
IF_NOT_dcpReqF_first__33_BITS_39_TO_32_51_EQ_I_ETC___d158;
endcase
end
always@(lastResp)
begin
case (lastResp[44:43])
2'd0, 2'd1:
CASE_lastResp_BITS_44_TO_43_0_lastResp_BITS_44_ETC__q3 =
lastResp[44:43];
default: CASE_lastResp_BITS_44_TO_43_0_lastResp_BITS_44_ETC__q3 = 2'd2;
endcase
end
always@(dcpRespF$D_OUT or
IF_dcpRespF_first__35_BIT_42_42_THEN_0x70_ELSE_ETC___d343)
begin
case (dcpRespF$D_OUT[44:43])
2'd0:
CASE_dcpRespFD_OUT_BITS_44_TO_43_0_IF_dcpResp_ETC__q4 =
IF_dcpRespF_first__35_BIT_42_42_THEN_0x70_ELSE_ETC___d343;
2'd1:
CASE_dcpRespFD_OUT_BITS_44_TO_43_0_IF_dcpResp_ETC__q4 =
dcpRespF$D_OUT[10] ? 8'h70 : 8'h30;
default: CASE_dcpRespFD_OUT_BITS_44_TO_43_0_IF_dcpResp_ETC__q4 =
IF_dcpRespF_first__35_BIT_42_42_THEN_0x70_ELSE_ETC___d343;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
doInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
eDoReq <= `BSV_ASSIGNMENT_DELAY 1'd0;
edpFsm_start_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
edpFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
edpFsm_state_can_overlap <= `BSV_ASSIGNMENT_DELAY 1'd1;
edpFsm_state_fired <= `BSV_ASSIGNMENT_DELAY 1'd0;
edpFsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY 4'd0;
lastTag <= `BSV_ASSIGNMENT_DELAY 9'd170;
ptr <= `BSV_ASSIGNMENT_DELAY 4'd0;
end
else
begin
if (doInFlight$EN)
doInFlight <= `BSV_ASSIGNMENT_DELAY doInFlight$D_IN;
if (eDoReq$EN) eDoReq <= `BSV_ASSIGNMENT_DELAY eDoReq$D_IN;
if (edpFsm_start_reg$EN)
edpFsm_start_reg <= `BSV_ASSIGNMENT_DELAY edpFsm_start_reg$D_IN;
if (edpFsm_start_reg_1$EN)
edpFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY edpFsm_start_reg_1$D_IN;
if (edpFsm_state_can_overlap$EN)
edpFsm_state_can_overlap <= `BSV_ASSIGNMENT_DELAY
edpFsm_state_can_overlap$D_IN;
if (edpFsm_state_fired$EN)
edpFsm_state_fired <= `BSV_ASSIGNMENT_DELAY edpFsm_state_fired$D_IN;
if (edpFsm_state_mkFSMstate$EN)
edpFsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY
edpFsm_state_mkFSMstate$D_IN;
if (lastTag$EN) lastTag <= `BSV_ASSIGNMENT_DELAY lastTag$D_IN;
if (ptr$EN) ptr <= `BSV_ASSIGNMENT_DELAY ptr$D_IN;
end
if (eAddr$EN) eAddr <= `BSV_ASSIGNMENT_DELAY eAddr$D_IN;
if (eDMH$EN) eDMH <= `BSV_ASSIGNMENT_DELAY eDMH$D_IN;
if (eData$EN) eData <= `BSV_ASSIGNMENT_DELAY eData$D_IN;
if (ePli$EN) ePli <= `BSV_ASSIGNMENT_DELAY ePli$D_IN;
if (eeDat$EN) eeDat <= `BSV_ASSIGNMENT_DELAY eeDat$D_IN;
if (eeDmh$EN) eeDmh <= `BSV_ASSIGNMENT_DELAY eeDmh$D_IN;
if (eePli$EN) eePli <= `BSV_ASSIGNMENT_DELAY eePli$D_IN;
if (isWrtResp$EN) isWrtResp <= `BSV_ASSIGNMENT_DELAY isWrtResp$D_IN;
if (lastResp$EN) lastResp <= `BSV_ASSIGNMENT_DELAY lastResp$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
doInFlight = 1'h0;
eAddr = 32'hAAAAAAAA;
eDMH = 32'hAAAAAAAA;
eData = 32'hAAAAAAAA;
eDoReq = 1'h0;
ePli = 16'hAAAA;
edpFsm_start_reg = 1'h0;
edpFsm_start_reg_1 = 1'h0;
edpFsm_state_can_overlap = 1'h0;
edpFsm_state_fired = 1'h0;
edpFsm_state_mkFSMstate = 4'hA;
eeDat = 32'hAAAAAAAA;
eeDmh = 32'hAAAAAAAA;
eePli = 16'hAAAA;
isWrtResp = 1'h0;
lastResp = 45'h0AAAAAAAAAAA;
lastTag = 9'h0AA;
ptr = 4'hA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rx_sim_dcp && eDMH[13:12] == 2'd0)
begin
v__h3777 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rx_sim_dcp && eDMH[13:12] == 2'd0)
$display("[%0d]: rx_sim_dcp REQUEST: NOP ", v__h3777);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rx_sim_dcp && eDMH[13:12] == 2'b01)
begin
v__h3791 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rx_sim_dcp && eDMH[13:12] == 2'b01)
$display("[%0d]: rx_sim_dcp REQUEST: WRITE Addr:0x%0x Data:0x%0x",
v__h3791,
eAddr,
eData);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rx_sim_dcp && eDMH[13:12] == 2'd2)
begin
v__h3805 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rx_sim_dcp && eDMH[13:12] == 2'd2)
$display("[%0d]: rx_sim_dcp REQUEST: READ Addr:0x%0x ",
v__h3805,
eAddr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_dcp_to_cp_request && dcpReqF$D_OUT[78:77] == 2'd1 &&
dcpReqF_first__33_BITS_71_TO_64_38_EQ_IF_lastT_ETC___d143 &&
lastTag[8] &&
!dcpReqF$D_OUT[76])
begin
v__h4532 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_dcp_to_cp_request && dcpReqF$D_OUT[78:77] == 2'd1 &&
dcpReqF_first__33_BITS_71_TO_64_38_EQ_IF_lastT_ETC___d143 &&
lastTag[8] &&
!dcpReqF$D_OUT[76])
$display("[%0d]: dcp_to_cp_request ***TAG MATCH IN DCP WRITE*** (Not Forwarding Write Request to OCCP)",
v__h4532);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_dcp_to_cp_request &&
NOT_dcpReqF_first__33_BITS_78_TO_77_34_EQ_0_35_ETC___d221)
begin
v__h5089 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_dcp_to_cp_request &&
NOT_dcpReqF_first__33_BITS_78_TO_77_34_EQ_0_35_ETC___d221)
$display("[%0d]: dcp_to_cp_request ***TAG MATCH IN DCP READ*** (Returning Previous Response)",
v__h5089);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_edpFsm_action_l221c14 &&
(WILL_FIRE_RL_edpFsm_action_l222c14 ||
WILL_FIRE_RL_edpFsm_action_l223c14 ||
WILL_FIRE_RL_edpFsm_action_l224c14 ||
WILL_FIRE_RL_edpFsm_action_l225c14 ||
WILL_FIRE_RL_edpFsm_action_l227c16 ||
WILL_FIRE_RL_edpFsm_action_l228c16 ||
WILL_FIRE_RL_edpFsm_action_l229c16 ||
WILL_FIRE_RL_edpFsm_action_l230c16))
$display("Error: \"bsv/eth/SimDCP.bsv\", line 221, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l221c14] and\n [RL_edpFsm_action_l222c14, RL_edpFsm_action_l223c14,\n RL_edpFsm_action_l224c14, RL_edpFsm_action_l225c14,\n RL_edpFsm_action_l227c16, RL_edpFsm_action_l228c16,\n RL_edpFsm_action_l229c16, RL_edpFsm_action_l230c16] ) fired in the same\n clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_edpFsm_action_l222c14 &&
(WILL_FIRE_RL_edpFsm_action_l223c14 ||
WILL_FIRE_RL_edpFsm_action_l224c14 ||
WILL_FIRE_RL_edpFsm_action_l225c14 ||
WILL_FIRE_RL_edpFsm_action_l227c16 ||
WILL_FIRE_RL_edpFsm_action_l228c16 ||
WILL_FIRE_RL_edpFsm_action_l229c16 ||
WILL_FIRE_RL_edpFsm_action_l230c16))
$display("Error: \"bsv/eth/SimDCP.bsv\", line 222, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l222c14] and\n [RL_edpFsm_action_l223c14, RL_edpFsm_action_l224c14,\n RL_edpFsm_action_l225c14, RL_edpFsm_action_l227c16,\n RL_edpFsm_action_l228c16, RL_edpFsm_action_l229c16,\n RL_edpFsm_action_l230c16] ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_edpFsm_action_l223c14 &&
(WILL_FIRE_RL_edpFsm_action_l224c14 ||
WILL_FIRE_RL_edpFsm_action_l225c14 ||
WILL_FIRE_RL_edpFsm_action_l227c16 ||
WILL_FIRE_RL_edpFsm_action_l228c16 ||
WILL_FIRE_RL_edpFsm_action_l229c16 ||
WILL_FIRE_RL_edpFsm_action_l230c16))
$display("Error: \"bsv/eth/SimDCP.bsv\", line 223, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l223c14] and\n [RL_edpFsm_action_l224c14, RL_edpFsm_action_l225c14,\n RL_edpFsm_action_l227c16, RL_edpFsm_action_l228c16,\n RL_edpFsm_action_l229c16, RL_edpFsm_action_l230c16] ) fired in the same\n clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_edpFsm_action_l224c14 &&
(WILL_FIRE_RL_edpFsm_action_l225c14 ||
WILL_FIRE_RL_edpFsm_action_l227c16 ||
WILL_FIRE_RL_edpFsm_action_l228c16 ||
WILL_FIRE_RL_edpFsm_action_l229c16 ||
WILL_FIRE_RL_edpFsm_action_l230c16))
$display("Error: \"bsv/eth/SimDCP.bsv\", line 224, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l224c14] and\n [RL_edpFsm_action_l225c14, RL_edpFsm_action_l227c16,\n RL_edpFsm_action_l228c16, RL_edpFsm_action_l229c16,\n RL_edpFsm_action_l230c16] ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_edpFsm_action_l225c14 &&
(WILL_FIRE_RL_edpFsm_action_l227c16 ||
WILL_FIRE_RL_edpFsm_action_l228c16 ||
WILL_FIRE_RL_edpFsm_action_l229c16 ||
WILL_FIRE_RL_edpFsm_action_l230c16))
$display("Error: \"bsv/eth/SimDCP.bsv\", line 225, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l225c14] and\n [RL_edpFsm_action_l227c16, RL_edpFsm_action_l228c16,\n RL_edpFsm_action_l229c16, RL_edpFsm_action_l230c16] ) fired in the same\n clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_edpFsm_action_l228c16 &&
(WILL_FIRE_RL_edpFsm_action_l229c16 ||
WILL_FIRE_RL_edpFsm_action_l230c16))
$display("Error: \"bsv/eth/SimDCP.bsv\", line 228, column 16: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l228c16] and\n [RL_edpFsm_action_l229c16, RL_edpFsm_action_l230c16] ) fired in the same\n clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_edpFsm_action_l227c16 &&
(WILL_FIRE_RL_edpFsm_action_l228c16 ||
WILL_FIRE_RL_edpFsm_action_l229c16 ||
WILL_FIRE_RL_edpFsm_action_l230c16))
$display("Error: \"bsv/eth/SimDCP.bsv\", line 227, column 16: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l227c16] and\n [RL_edpFsm_action_l228c16, RL_edpFsm_action_l229c16,\n RL_edpFsm_action_l230c16] ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_edpFsm_action_l229c16 &&
WILL_FIRE_RL_edpFsm_action_l230c16)
$display("Error: \"bsv/eth/SimDCP.bsv\", line 229, column 16: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l229c16] and\n [RL_edpFsm_action_l230c16] ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_edpFsm_action_l220c14 &&
(WILL_FIRE_RL_edpFsm_action_l221c14 ||
WILL_FIRE_RL_edpFsm_action_l222c14 ||
WILL_FIRE_RL_edpFsm_action_l223c14 ||
WILL_FIRE_RL_edpFsm_action_l224c14 ||
WILL_FIRE_RL_edpFsm_action_l225c14 ||
WILL_FIRE_RL_edpFsm_action_l227c16 ||
WILL_FIRE_RL_edpFsm_action_l228c16 ||
WILL_FIRE_RL_edpFsm_action_l229c16 ||
WILL_FIRE_RL_edpFsm_action_l230c16))
$display("Error: \"bsv/eth/SimDCP.bsv\", line 220, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l220c14] and\n [RL_edpFsm_action_l221c14, RL_edpFsm_action_l222c14,\n RL_edpFsm_action_l223c14, RL_edpFsm_action_l224c14,\n RL_edpFsm_action_l225c14, RL_edpFsm_action_l227c16,\n RL_edpFsm_action_l228c16, RL_edpFsm_action_l229c16,\n RL_edpFsm_action_l230c16] ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_sim_egress && dcpRespF$D_OUT[44:43] == 2'd0)
begin
v__h26988 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_sim_egress && dcpRespF$D_OUT[44:43] == 2'd0)
$display("[%0d]: sim_egress NOP_RESPONSE", v__h26988);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_sim_egress && dcpRespF$D_OUT[44:43] == 2'd1)
begin
v__h27142 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_sim_egress && dcpRespF$D_OUT[44:43] == 2'd1)
$display("[%0d]: sim_egress WRITE_RESPONSE", v__h27142);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_sim_egress && dcpRespF$D_OUT[44:43] != 2'd0 &&
dcpRespF$D_OUT[44:43] != 2'd1)
begin
v__h27335 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_sim_egress && dcpRespF$D_OUT[44:43] != 2'd0 &&
dcpRespF$D_OUT[44:43] != 2'd1)
$display("[%0d]: sim_egress READ_RESPONSE Data:0x%0x ",
v__h27335,
dcpRespF$D_OUT[41:10]);
end
// synopsys translate_on
endmodule // mkSimDCP
|
//
// Paul Gao 03/2019
//
// This is the receiver part of bsg_link_ddr, a complete DDR communication
// endpoint over multiple source-synchronous channels.
//
// * This module MUST be mirrored with bsg_link_ddr_upstream, which is
// instantiated on the source chip or FPGA. It is not a must to
// use upstream and downstream in pair on same chip or FPGA.
//
// The purpose of bsg_link_ddr_downstream is to receive DDR data bits from
// physical IO pins, then reassemble to ready-valid interface in core clock domain.
// Token-credit based flow control ensures efficiency and correctness.
// IDDR_PHY assumes incoming clock is center-alighed to data bits.
//
// Typical usage: ASIC <-> ASIC communication and ASIC <-> FPGA communication.
// Instantiate one bsg_link_ddr_upstream on sender side, one bsg_link_ddr_downstream on
// receiver side to establish communication.
//
// Refer to bsg_link_source_sync_downstream for more information on flow control
//
//
`include "bsg_defines.v"
module bsg_link_ddr_downstream
#(// Core data width
// MUST be multiple of (2*channel_width_p*num_channels_p)
// When use_extra_data_bit_p=1, must be multiple of ((2*channel_width_p+1)*num_channels_p)
parameter `BSG_INV_PARAM(width_p )
// Number of IO pins per physical IO channels
,parameter channel_width_p = 8
// Number of physical IO channels
,parameter num_channels_p = 1
// Receive fifo depth
// MUST MATCH paired bsg_link_ddr_upstream setting
// Default value comes from child module
// Refer to bsg_link_source_sync_downstream for more detail on this parameter
,parameter lg_fifo_depth_p = 6
// Token credit decimation
// MUST MATCH paired bsg_link_ddr_upstream setting
// Default value comes from child module
// Refer to bsg_link_source_sync_downstream for more detail on this parameter
,parameter lg_credit_to_token_decimation_p = 3
// There are (channel_width_p+1) physical wires available (1 wire for valid bit)
// With DDR clock, we can handle 2*channel_width_p+2 bits each cycle
// By default the link has 2*channel_width_p data bits and 1 valid bit, 1 bit is unused
// Set use_extra_data_bit_p=1 to utilize this extra bit
// MUST MATCH paired bsg_link_ddr_upstream setting
,parameter use_extra_data_bit_p = 0
// When channel_width_p is large, it might be hard to properly align source synchronous
// clock to all data wires. One option is to cut the channel in half and align to
// different clocks. Ecoding method below helps represent valid bit for bottom half data
// without adding an extra wire.
// +-------------+---------------+---------------------+
// | v_top | bottom | Value |
// | 0_0???_???? | 0000_0000 | no data (""comma"") |
// | 1_XXXX_XXXX | YYYY_YYYY!=0 | XXXX_XXXX_YYYY_YYYY |
// | 0_1XXX_XXXX | X000_0001 | XXXX_XXXX_0000_0000 |
// +-------------+---------------+---------------------+
// Physical bonding suggestion: Regard v bit and top bits of the channel as a group
// Regard bottom bits of the channel as another group
// Set use_encode_p=1 to enable this encoding feature
// MUST MATCH paired bsg_link_ddr_downstream setting
,parameter use_encode_p = 0
,parameter bypass_twofer_fifo_p = 0
,parameter bypass_gearbox_p = 0
,parameter use_hardened_fifo_p = 0
,localparam ddr_width_lp = channel_width_p*2 + use_extra_data_bit_p
,localparam sipo_ratio_lp = width_p/(ddr_width_lp*num_channels_p)
,localparam phy_width_lp = channel_width_p+1
)
(// All reset / control signals are synchronous to core_clk
input core_clk_i
,input core_link_reset_i
// io_reset signals must be synchronous to input clock of each IO channel
,input [num_channels_p-1:0] io_link_reset_i
// Core side
,output [width_p-1:0] core_data_o
,output core_valid_o
,input core_yumi_i
// Physical IO side
// The clock io_clk_i is being remotely sent from another chip's bsg_link_ddr_upstream
// in parallel with the source-synchronous data. The receive logic runs off of this clock,
// so the clock will not start until the upstream link has come out of reset.
,input [num_channels_p-1:0] io_clk_i
,input [num_channels_p-1:0][channel_width_p-1:0] io_data_i
,input [num_channels_p-1:0] io_valid_i
,output logic [num_channels_p-1:0] core_token_r_o
);
logic core_sipo_ready_lo, core_sipo_yumi_lo;
logic [num_channels_p-1:0][ddr_width_lp-1:0] core_sipo_data_li;
// Dequeue when all channels have valid data coming in
logic [num_channels_p-1:0] core_sipo_valid_li;
genvar i;
// Multiple channels
for (i = 0; i < num_channels_p; i++)
begin:ch
// io side signals
logic io_iddr_valid_lo, io_iddr_data_v;
logic [phy_width_lp-1:0] io_iddr_data_top;
logic [1:0][channel_width_p/2-1:0] io_iddr_data_bottom;
// core side signals
logic core_ss_valid_lo, core_ss_yumi_li, core_ss_data_nonzero;
logic [phy_width_lp-1:0] core_ss_data_top;
logic [1:0][channel_width_p/2-1:0] core_ss_data_bottom;
// connect to sipo
assign core_ss_yumi_li = core_sipo_yumi_lo;
assign core_sipo_valid_li[i] = core_ss_valid_lo;
assign core_sipo_data_li[i][ddr_width_lp-1:channel_width_p] = core_ss_data_top;
if (use_encode_p == 0)
begin
assign core_sipo_data_li[i][channel_width_p-1:0] = core_ss_data_bottom;
assign io_iddr_valid_lo = io_iddr_data_v;
end
else
begin
// core side decode
assign core_sipo_data_li[i][channel_width_p-1:channel_width_p/2] =
(core_ss_data_nonzero)?
{core_ss_data_bottom[1]}
: {core_ss_data_bottom[0][channel_width_p/2-1], core_ss_data_bottom[1][channel_width_p/2-1-1:0]};
assign core_sipo_data_li[i][channel_width_p/2-1:0] =
(core_ss_data_nonzero)?
{core_ss_data_bottom[0]}
: {'0};
// io side decode
assign io_iddr_valid_lo = io_iddr_data_v | io_iddr_data_bottom[1][channel_width_p/2-1];
end
// valid and data signals are received together
bsg_link_iddr_phy
#(.width_p(phy_width_lp)
) iddr_phy
(.clk_i (io_clk_i[i])
,.data_i ({io_valid_i[i], io_data_i[i]})
,.data_r_o({io_iddr_data_top, io_iddr_data_v, io_iddr_data_bottom})
);
bsg_link_source_sync_downstream
#(.channel_width_p(2*phy_width_lp)
,.lg_fifo_depth_p(lg_fifo_depth_p)
,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_p)
,.bypass_twofer_fifo_p(bypass_twofer_fifo_p)
,.use_hardened_fifo_p(use_hardened_fifo_p)
) downstream
(.core_clk_i (core_clk_i)
,.core_link_reset_i(core_link_reset_i)
,.io_link_reset_i (io_link_reset_i[i])
// source synchronous input channel; coming from chip edge
,.io_clk_i (io_clk_i[i])
,.io_data_i ({io_iddr_data_top, io_iddr_data_v, io_iddr_data_bottom})
,.io_valid_i (io_iddr_valid_lo)
,.core_token_r_o (core_token_r_o[i])
// going into core; uses core clock
,.core_data_o ({core_ss_data_top, core_ss_data_nonzero, core_ss_data_bottom})
,.core_valid_o (core_ss_valid_lo)
,.core_yumi_i (core_ss_yumi_li)
);
end
if (sipo_ratio_lp == 1 && bypass_gearbox_p != 0)
begin
assign core_valid_o = (& core_sipo_valid_li);
assign core_data_o = core_sipo_data_li;
assign core_sipo_yumi_lo = core_yumi_i;
end
else
begin: sipo
assign core_sipo_yumi_lo = (& core_sipo_valid_li) & core_sipo_ready_lo;
// This sipof ensures no bubble cycle on receiving packets.
bsg_serial_in_parallel_out_full
#(.width_p(ddr_width_lp*num_channels_p)
,.els_p (sipo_ratio_lp)
) in_sipof
(.clk_i (core_clk_i)
,.reset_i(core_link_reset_i)
,.v_i (& core_sipo_valid_li)
,.ready_o(core_sipo_ready_lo)
,.data_i (core_sipo_data_li)
,.data_o (core_data_o)
,.v_o (core_valid_o)
,.yumi_i (core_yumi_i)
);
end
// synopsys translate_off
initial
begin
assert (sipo_ratio_lp > 0)
else
begin
$error("BaseJump STL ERROR %m: width_p should be larger than or equal to (ddr_width_lp*num_channels_p)");
$finish;
end
assert (sipo_ratio_lp*(ddr_width_lp*num_channels_p) == width_p)
else
begin
$error("BaseJump STL ERROR %m: width_p should be multiple of (ddr_width_lp*num_channels_p)");
$finish;
end
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_link_ddr_downstream)
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_512x20.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.9 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10 2001/11/27 21:24:04 lampret
// Changed instantiation name of VS RAMs.
//
// Revision 1.9 2001/11/27 19:45:04 lampret
// Fixed VS RAM instantiation - again.
//
// Revision 1.8 2001/11/23 21:42:31 simons
// Program counter divided to PPC and NPC.
//
// Revision 1.6 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_512x20(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 9;
parameter dw = 20;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_XILINX_RAMB4
wire [3:0] unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire [11:0] unconnected;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_512x20 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_512x20_bist artisan_ssp(
`else
art_hssp_512x20 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_512x20 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_512x20_bist vs_ssp(
`else
vs_hdsp_512x20 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S8 ramb4_s8_0(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[7:0]),
.EN(ce),
.WE(we),
.DO(doq[7:0])
);
//
// Block 1
//
RAMB4_S8 ramb4_s8_1(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[15:8]),
.EN(ce),
.WE(we),
.DO(doq[15:8])
);
//
// Block 2
//
RAMB4_S8 ramb4_s8_2(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI({4'b0000, di[19:16]}),
.EN(ce),
.WE(we),
.DO({unconnected, doq[19:16]})
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
RAMB16_S36 ramb16_s36(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI({12'h000,di}),
.DIP(4'h0),
.EN(ce),
.WE(we),
.DO({unconnected,doq}),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:07:50 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_gpio_0_0_sim_netlist.v
// Design : zqynq_lab_1_design_axi_gpio_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core
(D,
gpio_io_o,
GPIO_xferAck_i,
gpio_xferAck_Reg,
ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg,
gpio_io_t,
bus2ip_rnw_i_reg,
s_axi_aclk,
SS,
bus2ip_rnw,
bus2ip_cs,
E,
\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
rst_reg);
output [7:0]D;
output [7:0]gpio_io_o;
output GPIO_xferAck_i;
output gpio_xferAck_Reg;
output ip2bus_rdack_i;
output ip2bus_wrack_i_D1_reg;
output [7:0]gpio_io_t;
input bus2ip_rnw_i_reg;
input s_axi_aclk;
input [0:0]SS;
input bus2ip_rnw;
input bus2ip_cs;
input [0:0]E;
input [7:0]\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
input [0:0]rst_reg;
wire [7:0]D;
wire [0:0]E;
wire GPIO_xferAck_i;
wire [7:0]\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
wire [0:0]SS;
wire bus2ip_cs;
wire bus2ip_rnw;
wire bus2ip_rnw_i_reg;
wire [7:0]gpio_io_o;
wire [7:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire iGPIO_xferAck;
wire ip2bus_rdack_i;
wire ip2bus_wrack_i_D1_reg;
wire [0:0]rst_reg;
wire s_axi_aclk;
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[7]),
.Q(D[7]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[6]),
.Q(D[6]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[5]),
.Q(D[5]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[4]),
.Q(D[4]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[3]),
.Q(D[3]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[5].GPIO_DBus_i_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[2]),
.Q(D[2]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[6].GPIO_DBus_i_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[1]),
.Q(D[1]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[7].GPIO_DBus_i_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[0]),
.Q(D[0]),
.R(bus2ip_rnw_i_reg));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [7]),
.Q(gpio_io_o[7]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [6]),
.Q(gpio_io_o[6]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [5]),
.Q(gpio_io_o[5]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [4]),
.Q(gpio_io_o[4]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[4]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [3]),
.Q(gpio_io_o[3]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[5]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [2]),
.Q(gpio_io_o[2]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[6]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [1]),
.Q(gpio_io_o[1]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[7]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [0]),
.Q(gpio_io_o[0]),
.R(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[0]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [7]),
.Q(gpio_io_t[7]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[1]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [6]),
.Q(gpio_io_t[6]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[2]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [5]),
.Q(gpio_io_t[5]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[3]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [4]),
.Q(gpio_io_t[4]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[4]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [3]),
.Q(gpio_io_t[3]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[5]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [2]),
.Q(gpio_io_t[2]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[6]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [1]),
.Q(gpio_io_t[1]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[7]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [0]),
.Q(gpio_io_t[0]),
.S(SS));
FDRE gpio_xferAck_Reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_xferAck_i),
.Q(gpio_xferAck_Reg),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h02))
iGPIO_xferAck_i_1
(.I0(bus2ip_cs),
.I1(gpio_xferAck_Reg),
.I2(GPIO_xferAck_i),
.O(iGPIO_xferAck));
FDRE iGPIO_xferAck_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(iGPIO_xferAck),
.Q(GPIO_xferAck_i),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h8))
ip2bus_rdack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_rdack_i));
LUT2 #(
.INIT(4'h2))
ip2bus_wrack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_wrack_i_D1_reg));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ,
E,
\Not_Dual.gpio_OE_reg[0] ,
s_axi_arready,
s_axi_wready,
D,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ,
s_axi_aclk,
rst_reg,
Q,
bus2ip_rnw_i_reg,
ip2bus_rdack_i_D1,
is_read,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ,
ip2bus_wrack_i_D1,
is_write_reg,
s_axi_wdata,
start2_reg,
s_axi_aresetn,
gpio_xferAck_Reg,
GPIO_xferAck_i);
output \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
output [0:0]E;
output [0:0]\Not_Dual.gpio_OE_reg[0] ;
output s_axi_arready;
output s_axi_wready;
output [7:0]D;
output \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ;
input s_axi_aclk;
input rst_reg;
input [2:0]Q;
input bus2ip_rnw_i_reg;
input ip2bus_rdack_i_D1;
input is_read;
input [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
input ip2bus_wrack_i_D1;
input is_write_reg;
input [15:0]s_axi_wdata;
input start2_reg;
input s_axi_aresetn;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
wire [7:0]D;
wire [0:0]E;
wire GPIO_xferAck_i;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
wire \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
wire \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ;
wire [0:0]\Not_Dual.gpio_OE_reg[0] ;
wire [2:0]Q;
wire bus2ip_rnw_i_reg;
wire gpio_xferAck_Reg;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire is_read;
wire is_write_reg;
wire rst_reg;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_arready;
wire [15:0]s_axi_wdata;
wire s_axi_wready;
wire start2_reg;
LUT5 #(
.INIT(32'h000000E0))
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(start2_reg),
.I2(s_axi_aresetn),
.I3(s_axi_arready),
.I4(s_axi_wready),
.O(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ));
FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ),
.Q(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.R(1'b0));
LUT4 #(
.INIT(16'hFFF7))
\Not_Dual.ALLOUT_ND.READ_REG_GEN[7].GPIO_DBus_i[31]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(gpio_xferAck_Reg),
.I3(GPIO_xferAck_i),
.O(\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ));
LUT6 #(
.INIT(64'hAAAAAAAAAAABAAAA))
\Not_Dual.gpio_Data_Out[0]_i_1
(.I0(rst_reg),
.I1(Q[1]),
.I2(bus2ip_rnw_i_reg),
.I3(Q[0]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(Q[2]),
.O(E));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[0]_i_2
(.I0(s_axi_wdata[7]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[15]),
.O(D[7]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[1]_i_1
(.I0(s_axi_wdata[6]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[14]),
.O(D[6]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[2]_i_1
(.I0(s_axi_wdata[5]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[13]),
.O(D[5]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[3]_i_1
(.I0(s_axi_wdata[4]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[12]),
.O(D[4]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[4]_i_1
(.I0(s_axi_wdata[3]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[11]),
.O(D[3]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[5]_i_1
(.I0(s_axi_wdata[2]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[10]),
.O(D[2]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[6]_i_1
(.I0(s_axi_wdata[1]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[9]),
.O(D[1]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[7]_i_1
(.I0(s_axi_wdata[0]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[8]),
.O(D[0]));
LUT6 #(
.INIT(64'hAAAAAAAAAAAEAAAA))
\Not_Dual.gpio_OE[0]_i_1
(.I0(rst_reg),
.I1(Q[0]),
.I2(Q[1]),
.I3(bus2ip_rnw_i_reg),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(Q[2]),
.O(\Not_Dual.gpio_OE_reg[0] ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAEAAAA))
s_axi_arready_INST_0
(.I0(ip2bus_rdack_i_D1),
.I1(is_read),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
.I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
.O(s_axi_arready));
LUT6 #(
.INIT(64'hAAAAAAAAAAAEAAAA))
s_axi_wready_INST_0
(.I0(ip2bus_wrack_i_D1),
.I1(is_write_reg),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
.I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
.O(s_axi_wready));
endmodule
(* C_ALL_INPUTS = "0" *) (* C_ALL_INPUTS_2 = "0" *) (* C_ALL_OUTPUTS = "1" *)
(* C_ALL_OUTPUTS_2 = "0" *) (* C_DOUT_DEFAULT = "0" *) (* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "zynq" *) (* C_GPIO2_WIDTH = "32" *) (* C_GPIO_WIDTH = "8" *)
(* C_INTERRUPT_PRESENT = "0" *) (* C_IS_DUAL = "0" *) (* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *) (* C_TRI_DEFAULT = "-1" *) (* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *) (* ip_group = "LOGICORE" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
ip2intc_irpt,
gpio_io_i,
gpio_io_o,
gpio_io_t,
gpio2_io_i,
gpio2_io_o,
gpio2_io_t);
(* max_fanout = "10000" *) (* sigis = "Clk" *) input s_axi_aclk;
(* max_fanout = "10000" *) (* sigis = "Rst" *) input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
(* sigis = "INTR_LEVEL_HIGH" *) output ip2intc_irpt;
input [7:0]gpio_io_i;
output [7:0]gpio_io_o;
output [7:0]gpio_io_t;
input [31:0]gpio2_io_i;
output [31:0]gpio2_io_o;
output [31:0]gpio2_io_t;
wire \<const0> ;
wire \<const1> ;
wire AXI_LITE_IPIF_I_n_17;
wire AXI_LITE_IPIF_I_n_6;
wire AXI_LITE_IPIF_I_n_7;
wire [0:7]DBus_Reg;
wire GPIO_xferAck_i;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire gpio_core_1_n_19;
wire [7:0]gpio_io_o;
wire [7:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [24:31]ip2bus_data;
wire [24:31]ip2bus_data_i_D1;
wire ip2bus_rdack_i;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire s_axi_aclk;
wire [8:0]s_axi_araddr;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rst" *) wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [7:0]\^s_axi_rdata ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
assign gpio2_io_o[31] = \<const0> ;
assign gpio2_io_o[30] = \<const0> ;
assign gpio2_io_o[29] = \<const0> ;
assign gpio2_io_o[28] = \<const0> ;
assign gpio2_io_o[27] = \<const0> ;
assign gpio2_io_o[26] = \<const0> ;
assign gpio2_io_o[25] = \<const0> ;
assign gpio2_io_o[24] = \<const0> ;
assign gpio2_io_o[23] = \<const0> ;
assign gpio2_io_o[22] = \<const0> ;
assign gpio2_io_o[21] = \<const0> ;
assign gpio2_io_o[20] = \<const0> ;
assign gpio2_io_o[19] = \<const0> ;
assign gpio2_io_o[18] = \<const0> ;
assign gpio2_io_o[17] = \<const0> ;
assign gpio2_io_o[16] = \<const0> ;
assign gpio2_io_o[15] = \<const0> ;
assign gpio2_io_o[14] = \<const0> ;
assign gpio2_io_o[13] = \<const0> ;
assign gpio2_io_o[12] = \<const0> ;
assign gpio2_io_o[11] = \<const0> ;
assign gpio2_io_o[10] = \<const0> ;
assign gpio2_io_o[9] = \<const0> ;
assign gpio2_io_o[8] = \<const0> ;
assign gpio2_io_o[7] = \<const0> ;
assign gpio2_io_o[6] = \<const0> ;
assign gpio2_io_o[5] = \<const0> ;
assign gpio2_io_o[4] = \<const0> ;
assign gpio2_io_o[3] = \<const0> ;
assign gpio2_io_o[2] = \<const0> ;
assign gpio2_io_o[1] = \<const0> ;
assign gpio2_io_o[0] = \<const0> ;
assign gpio2_io_t[31] = \<const1> ;
assign gpio2_io_t[30] = \<const1> ;
assign gpio2_io_t[29] = \<const1> ;
assign gpio2_io_t[28] = \<const1> ;
assign gpio2_io_t[27] = \<const1> ;
assign gpio2_io_t[26] = \<const1> ;
assign gpio2_io_t[25] = \<const1> ;
assign gpio2_io_t[24] = \<const1> ;
assign gpio2_io_t[23] = \<const1> ;
assign gpio2_io_t[22] = \<const1> ;
assign gpio2_io_t[21] = \<const1> ;
assign gpio2_io_t[20] = \<const1> ;
assign gpio2_io_t[19] = \<const1> ;
assign gpio2_io_t[18] = \<const1> ;
assign gpio2_io_t[17] = \<const1> ;
assign gpio2_io_t[16] = \<const1> ;
assign gpio2_io_t[15] = \<const1> ;
assign gpio2_io_t[14] = \<const1> ;
assign gpio2_io_t[13] = \<const1> ;
assign gpio2_io_t[12] = \<const1> ;
assign gpio2_io_t[11] = \<const1> ;
assign gpio2_io_t[10] = \<const1> ;
assign gpio2_io_t[9] = \<const1> ;
assign gpio2_io_t[8] = \<const1> ;
assign gpio2_io_t[7] = \<const1> ;
assign gpio2_io_t[6] = \<const1> ;
assign gpio2_io_t[5] = \<const1> ;
assign gpio2_io_t[4] = \<const1> ;
assign gpio2_io_t[3] = \<const1> ;
assign gpio2_io_t[2] = \<const1> ;
assign gpio2_io_t[1] = \<const1> ;
assign gpio2_io_t[0] = \<const1> ;
assign ip2intc_irpt = \<const0> ;
assign s_axi_awready = s_axi_wready;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7:0] = \^s_axi_rdata [7:0];
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif AXI_LITE_IPIF_I
(.D({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4],DBus_Reg[5],DBus_Reg[6],DBus_Reg[7]}),
.E(AXI_LITE_IPIF_I_n_6),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] (AXI_LITE_IPIF_I_n_17),
.\Not_Dual.gpio_OE_reg[0] (AXI_LITE_IPIF_I_n_7),
.Q({ip2bus_data_i_D1[24],ip2bus_data_i_D1[25],ip2bus_data_i_D1[26],ip2bus_data_i_D1[27],ip2bus_data_i_D1[28],ip2bus_data_i_D1[29],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}),
.bus2ip_cs(bus2ip_cs),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw(bus2ip_rnw),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr({s_axi_araddr[8],s_axi_araddr[3:2]}),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr({s_axi_awaddr[8],s_axi_awaddr[3:2]}),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(\^s_axi_rdata ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata({s_axi_wdata[31:24],s_axi_wdata[7:0]}),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core gpio_core_1
(.D({ip2bus_data[24],ip2bus_data[25],ip2bus_data[26],ip2bus_data[27],ip2bus_data[28],ip2bus_data[29],ip2bus_data[30],ip2bus_data[31]}),
.E(AXI_LITE_IPIF_I_n_6),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0] ({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4],DBus_Reg[5],DBus_Reg[6],DBus_Reg[7]}),
.SS(bus2ip_reset),
.bus2ip_cs(bus2ip_cs),
.bus2ip_rnw(bus2ip_rnw),
.bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_17),
.gpio_io_o(gpio_io_o),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i(ip2bus_rdack_i),
.ip2bus_wrack_i_D1_reg(gpio_core_1_n_19),
.rst_reg(AXI_LITE_IPIF_I_n_7),
.s_axi_aclk(s_axi_aclk));
FDRE \ip2bus_data_i_D1_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[24]),
.Q(ip2bus_data_i_D1[24]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[25]),
.Q(ip2bus_data_i_D1[25]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[26]),
.Q(ip2bus_data_i_D1[26]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[27]),
.Q(ip2bus_data_i_D1[27]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[28]),
.Q(ip2bus_data_i_D1[28]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[29]),
.Q(ip2bus_data_i_D1[29]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[30]),
.Q(ip2bus_data_i_D1[30]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[31]),
.Q(ip2bus_data_i_D1[31]),
.R(bus2ip_reset));
FDRE ip2bus_rdack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_rdack_i),
.Q(ip2bus_rdack_i_D1),
.R(bus2ip_reset));
FDRE ip2bus_wrack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_core_1_n_19),
.Q(ip2bus_wrack_i_D1),
.R(bus2ip_reset));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
(bus2ip_reset,
bus2ip_rnw,
bus2ip_cs,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
E,
\Not_Dual.gpio_OE_reg[0] ,
s_axi_wready,
D,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ,
s_axi_rdata,
s_axi_aclk,
s_axi_arvalid,
s_axi_awvalid,
s_axi_wvalid,
s_axi_araddr,
s_axi_awaddr,
s_axi_aresetn,
s_axi_rready,
s_axi_bready,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_wdata,
gpio_xferAck_Reg,
GPIO_xferAck_i,
Q);
output bus2ip_reset;
output bus2ip_rnw;
output bus2ip_cs;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output [0:0]E;
output [0:0]\Not_Dual.gpio_OE_reg[0] ;
output s_axi_wready;
output [7:0]D;
output \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ;
output [7:0]s_axi_rdata;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_awvalid;
input s_axi_wvalid;
input [2:0]s_axi_araddr;
input [2:0]s_axi_awaddr;
input s_axi_aresetn;
input s_axi_rready;
input s_axi_bready;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input [15:0]s_axi_wdata;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [7:0]Q;
wire [7:0]D;
wire [0:0]E;
wire GPIO_xferAck_i;
wire \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ;
wire [0:0]\Not_Dual.gpio_OE_reg[0] ;
wire [7:0]Q;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire gpio_xferAck_Reg;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [7:0]s_axi_rdata;
wire s_axi_rready;
wire s_axi_rvalid;
wire [15:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment I_SLAVE_ATTACHMENT
(.D(D),
.E(E),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0] (bus2ip_cs),
.\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] (\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ),
.\Not_Dual.gpio_Data_Out_reg[0] (bus2ip_rnw),
.\Not_Dual.gpio_OE_reg[0] (\Not_Dual.gpio_OE_reg[0] ),
.Q(Q),
.SR(bus2ip_reset),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
(SR,
\Not_Dual.gpio_Data_Out_reg[0] ,
\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
E,
\Not_Dual.gpio_OE_reg[0] ,
s_axi_wready,
D,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ,
s_axi_rdata,
s_axi_aclk,
s_axi_arvalid,
s_axi_awvalid,
s_axi_wvalid,
s_axi_araddr,
s_axi_awaddr,
s_axi_aresetn,
s_axi_rready,
s_axi_bready,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_wdata,
gpio_xferAck_Reg,
GPIO_xferAck_i,
Q);
output SR;
output \Not_Dual.gpio_Data_Out_reg[0] ;
output \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output [0:0]E;
output [0:0]\Not_Dual.gpio_OE_reg[0] ;
output s_axi_wready;
output [7:0]D;
output \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ;
output [7:0]s_axi_rdata;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_awvalid;
input s_axi_wvalid;
input [2:0]s_axi_araddr;
input [2:0]s_axi_awaddr;
input s_axi_aresetn;
input s_axi_rready;
input s_axi_bready;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input [15:0]s_axi_wdata;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [7:0]Q;
wire [7:0]D;
wire [0:0]E;
wire GPIO_xferAck_i;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
wire \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ;
wire \Not_Dual.gpio_Data_Out_reg[0] ;
wire [0:0]\Not_Dual.gpio_OE_reg[0] ;
wire [7:0]Q;
wire SR;
wire [0:6]bus2ip_addr;
wire \bus2ip_addr_i[2]_i_1_n_0 ;
wire \bus2ip_addr_i[3]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_2_n_0 ;
wire bus2ip_rnw_i06_out;
wire clear;
wire gpio_xferAck_Reg;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire is_read;
wire is_read_i_1_n_0;
wire is_write;
wire is_write_i_1_n_0;
wire is_write_reg_n_0;
wire [1:0]p_0_out;
wire p_1_in;
wire [3:0]plusOp;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire s_axi_bvalid_i_i_1_n_0;
wire [7:0]s_axi_rdata;
wire \s_axi_rdata_i[7]_i_1_n_0 ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_rvalid_i_i_1_n_0;
wire [15:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
wire start2;
wire start2_i_1_n_0;
wire [1:0]state;
wire state1__2;
wire \state[1]_i_3_n_0 ;
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[3]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.R(clear));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder I_DECODER
(.D(D),
.E(E),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
.\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] (\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ),
.\Not_Dual.gpio_OE_reg[0] (\Not_Dual.gpio_OE_reg[0] ),
.Q({bus2ip_addr[0],bus2ip_addr[5],bus2ip_addr[6]}),
.bus2ip_rnw_i_reg(\Not_Dual.gpio_Data_Out_reg[0] ),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.is_read(is_read),
.is_write_reg(is_write_reg_n_0),
.rst_reg(SR),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.start2_reg(start2));
LUT5 #(
.INIT(32'hCCCACCCC))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_araddr[0]),
.I1(s_axi_awaddr[0]),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_arvalid),
.O(\bus2ip_addr_i[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hCCCACCCC))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_araddr[1]),
.I1(s_axi_awaddr[1]),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_arvalid),
.O(\bus2ip_addr_i[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h000000EA))
\bus2ip_addr_i[8]_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(state[1]),
.I4(state[0]),
.O(\bus2ip_addr_i[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hCCCACCCC))
\bus2ip_addr_i[8]_i_2
(.I0(s_axi_araddr[2]),
.I1(s_axi_awaddr[2]),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_arvalid),
.O(\bus2ip_addr_i[8]_i_2_n_0 ));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[2]_i_1_n_0 ),
.Q(bus2ip_addr[6]),
.R(SR));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[3]_i_1_n_0 ),
.Q(bus2ip_addr[5]),
.R(SR));
FDRE \bus2ip_addr_i_reg[8]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[8]_i_2_n_0 ),
.Q(bus2ip_addr[0]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h10))
bus2ip_rnw_i_i_1
(.I0(state[0]),
.I1(state[1]),
.I2(s_axi_arvalid),
.O(bus2ip_rnw_i06_out));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(bus2ip_rnw_i06_out),
.Q(\Not_Dual.gpio_Data_Out_reg[0] ),
.R(SR));
LUT5 #(
.INIT(32'h3FFA000A))
is_read_i_1
(.I0(s_axi_arvalid),
.I1(state1__2),
.I2(state[0]),
.I3(state[1]),
.I4(is_read),
.O(is_read_i_1_n_0));
FDRE is_read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_read_i_1_n_0),
.Q(is_read),
.R(SR));
LUT6 #(
.INIT(64'h0040FFFF00400000))
is_write_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(state[1]),
.I4(is_write),
.I5(is_write_reg_n_0),
.O(is_write_i_1_n_0));
LUT6 #(
.INIT(64'hF88800000000FFFF))
is_write_i_2
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(s_axi_bvalid),
.I3(s_axi_bready),
.I4(state[0]),
.I5(state[1]),
.O(is_write));
FDRE is_write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_write_i_1_n_0),
.Q(is_write_reg_n_0),
.R(SR));
LUT1 #(
.INIT(2'h1))
rst_i_1
(.I0(s_axi_aresetn),
.O(p_1_in));
FDRE rst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_1_in),
.Q(SR),
.R(1'b0));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_bvalid_i_i_1
(.I0(s_axi_wready),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.O(s_axi_bvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_bvalid_i_i_1_n_0),
.Q(s_axi_bvalid),
.R(SR));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[7]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(\s_axi_rdata_i[7]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[0]),
.Q(s_axi_rdata[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[1]),
.Q(s_axi_rdata[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[2]),
.Q(s_axi_rdata[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[3]),
.Q(s_axi_rdata[3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[4]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[4]),
.Q(s_axi_rdata[4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[5]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[5]),
.Q(s_axi_rdata[5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[6]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[6]),
.Q(s_axi_rdata[6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[7]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[7]),
.Q(s_axi_rdata[7]),
.R(SR));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_rvalid_i_i_1
(.I0(s_axi_arready),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.O(s_axi_rvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_rvalid_i_i_1_n_0),
.Q(s_axi_rvalid),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h000000F8))
start2_i_1
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.I2(s_axi_arvalid),
.I3(state[1]),
.I4(state[0]),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(SR));
LUT5 #(
.INIT(32'h77FC44FC))
\state[0]_i_1
(.I0(state1__2),
.I1(state[0]),
.I2(s_axi_arvalid),
.I3(state[1]),
.I4(s_axi_wready),
.O(p_0_out[0]));
LUT5 #(
.INIT(32'h5FFC50FC))
\state[1]_i_1
(.I0(state1__2),
.I1(\state[1]_i_3_n_0 ),
.I2(state[1]),
.I3(state[0]),
.I4(s_axi_arready),
.O(p_0_out[1]));
LUT4 #(
.INIT(16'hF888))
\state[1]_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(state1__2));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h08))
\state[1]_i_3
(.I0(s_axi_wvalid),
.I1(s_axi_awvalid),
.I2(s_axi_arvalid),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out[0]),
.Q(state[0]),
.R(SR));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out[1]),
.Q(state[1]),
.R(SR));
endmodule
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_axi_gpio_0_0,axi_gpio,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_gpio,Vivado 2017.2" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
gpio_io_o);
(* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [8:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_O" *) output [7:0]gpio_io_o;
wire [7:0]gpio_io_o;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_U0_ip2intc_irpt_UNCONNECTED;
wire [31:0]NLW_U0_gpio2_io_o_UNCONNECTED;
wire [31:0]NLW_U0_gpio2_io_t_UNCONNECTED;
wire [7:0]NLW_U0_gpio_io_t_UNCONNECTED;
(* C_ALL_INPUTS = "0" *)
(* C_ALL_INPUTS_2 = "0" *)
(* C_ALL_OUTPUTS = "1" *)
(* C_ALL_OUTPUTS_2 = "0" *)
(* C_DOUT_DEFAULT = "0" *)
(* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "zynq" *)
(* C_GPIO2_WIDTH = "32" *)
(* C_GPIO_WIDTH = "8" *)
(* C_INTERRUPT_PRESENT = "0" *)
(* C_IS_DUAL = "0" *)
(* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TRI_DEFAULT = "-1" *)
(* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* ip_group = "LOGICORE" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio U0
(.gpio2_io_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[31:0]),
.gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[31:0]),
.gpio_io_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.gpio_io_o(gpio_io_o),
.gpio_io_t(NLW_U0_gpio_io_t_UNCONNECTED[7:0]),
.ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O221A_4_V
`define SKY130_FD_SC_MS__O221A_4_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o221a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o221a_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o221a_4 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O221A_4_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RIT
// Engineer: Cody Cziesler and Nick Desaulniers
//
// Create Date: 11:36:45 04/07/2011
// Design Name: instruction_decode
// Module Name: instruction_decode
// Project Name: Omicron
// Target Devices: Xilinx Spartan-3E
// Tool versions:
// Description: Instruction Decode stage of pipeline
//
// Revision:
// Revision 0.01 - File Created
// Revision 1.00 - Added reg_block, need to fix instruction bits (CRC)
// Revision 2.00 - Fixed instruction bits (CRC)
// Revision 3.00 - Changed names on outputs from if -> id (CRC)
// Revision 4.00 - Changed wb_reg_load -> wb_reg_wea, fixed names (CRC)
// Revision 5.00 - Removed sign extend of address and changed size to 7 bits (CRC)
// Revision 6.00 - Removed id_regx_addr, added id_dest_reg_addr (CRC)
// Revision 7.00 - Changed ISA for register destination
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module instruction_decode(
input clk_n,
input [6:0] if_next_addr,
input [15:0] if_curr_inst,
input wb_reg_wea,
input [15:0] wb_reg_wdata,
input [2:0] wb_reg_waddr,
output [3:0] id_opcode, // [15:12]
output [6:0] id_next_addr,
output [15:0] id_register1_data,
output [15:0] id_register2_data,
output [6:0] id_sign_ext_addr, // [6:0]
output [2:0] id_dest_reg_addr // [8:6]
);
assign id_next_addr = if_next_addr;
assign id_opcode = if_curr_inst[15:12];
assign id_dest_reg_addr = if_curr_inst[8:6];
assign id_sign_ext_addr = if_curr_inst[6:0];
reg_block i_reg_block(
.clk_n(clk_n),
.wea(wb_reg_wea),
.raddr1(if_curr_inst[11:9]),
.raddr2(if_curr_inst[5:3]),
.waddr(wb_reg_waddr[2:0]),
.wdata(wb_reg_wdata[15:0]),
.rdata1(id_register1_data[15:0]),
.rdata2(id_register2_data[15:0])
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Todd Strader.
// SPDX-License-Identifier: CC0-1.0
// Test for trace file interface aliasing
typedef struct packed {
integer val100;
integer val200;
} struct_t;
interface ifc (input logic clk,
input integer cyc);
integer value;
struct_t the_struct;
endinterface
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
ifc intf_1(.*);
ifc intf_2(.*);
always @(*) begin
intf_1.value = cyc + 1;
intf_2.value = cyc + 2;
end
sub_struct s1 (.intf_for_struct(intf_1));
sub_struct s2 (.intf_for_struct(intf_2));
sub_check c1 (.intf_for_check(intf_1));
sub_check c2 (.intf_for_check(intf_2));
sub_all a (.intf_one(intf_1),
.intf_two(intf_2));
// Intentionally longer scope name
sub_all abcdefghijklmnopqrstuvwxyz (.intf_one(intf_2),
.intf_two(intf_1));
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==20) begin
if (intf_1.value != 21) $stop;
if (intf_2.value != 22) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub_struct
(
ifc intf_for_struct
);
always @(*) begin
intf_for_struct.the_struct.val100 = intf_for_struct.value + 100;
intf_for_struct.the_struct.val200 = intf_for_struct.value + 200;
end
endmodule
module sub_check
(
ifc intf_for_check
);
`ifdef NO_INLINE_A
//verilator no_inline_module
`endif
always @(posedge intf_for_check.clk) begin
if (intf_for_check.the_struct.val100 != intf_for_check.value + 100) $stop;
if (intf_for_check.the_struct.val200 != intf_for_check.value + 200) $stop;
end
endmodule
module sub_all
(
ifc intf_one,
ifc intf_two
);
`ifdef NO_INLINE_B
//verilator no_inline_module
`endif
ifc intf_in_sub_all (
.clk(intf_one.clk),
.cyc(intf_one.cyc)
);
assign intf_in_sub_all.value = intf_one.value + 1000;
sub_check ac1 (.intf_for_check(intf_one));
sub_check ac2 (.intf_for_check(intf_two));
sub_struct as3 (.intf_for_struct(intf_in_sub_all));
sub_check ac3 (.intf_for_check(intf_in_sub_all));
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: Bmul.v
// /___/ /\ Timestamp: Mon May 1 00:08:59 2017
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/rohith/Image-Watermarking/ipcore_dir/tmp/_cg/Bmul.ngc /home/rohith/Image-Watermarking/ipcore_dir/tmp/_cg/Bmul.v
// Device : 3s500efg320-5
// Input file : /home/rohith/Image-Watermarking/ipcore_dir/tmp/_cg/Bmul.ngc
// Output file : /home/rohith/Image-Watermarking/ipcore_dir/tmp/_cg/Bmul.v
// # of Modules : 1
// Design Name : Bmul
// Xilinx : /opt/14.7/ISE_DS/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module Bmul (
p, a
)/* synthesis syn_black_box syn_noprune=1 */;
output [7 : 0] p;
input [7 : 0] a;
// synthesis translate_off
wire [7 : 1] NlwRenamedSignal_a;
assign
p[6] = NlwRenamedSignal_a[7],
p[5] = NlwRenamedSignal_a[6],
p[4] = NlwRenamedSignal_a[5],
p[3] = NlwRenamedSignal_a[4],
p[2] = NlwRenamedSignal_a[3],
p[1] = NlwRenamedSignal_a[2],
p[0] = NlwRenamedSignal_a[1],
NlwRenamedSignal_a[7] = a[7],
NlwRenamedSignal_a[6] = a[6],
NlwRenamedSignal_a[5] = a[5],
NlwRenamedSignal_a[4] = a[4],
NlwRenamedSignal_a[3] = a[3],
NlwRenamedSignal_a[2] = a[2],
NlwRenamedSignal_a[1] = a[1];
GND \blk00000001/blk00000002 (
.G(p[7])
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
`timescale 1ns / 1ps
module top_string_tb;
reg clk, new, reset;
reg [6:0] char;
wire complete, change;
wire [76:0] string;
top_string uut ( .new(new), .clk(clk), .btn1(reset), .char(char), .string(string));
initial begin // Initialize Inputs
new=0;
reset=1;
char=7'b0000000;
clk=1;
#100
reset=0;
end
initial begin
forever begin
#600
new=1;
#100
new=0;
#400
new=1;
#100
new=0;
#400
new=1;
#100
new=0;
#400
new=1;
#100
new=0;
#400
new=1;
#100
new=0;
#400
new=1;
#100
new=0;
#400
new=1;
#100
new=0;
#400
new=1;
#100
new=0;
#400
new=1;
#100
new=0;
#400
new=1;
#100
new=0;
end
end
initial begin
forever begin
#600
char=7'b1111011; //o
#500
char=7'b0001000; //borrar
#500
char=7'b0111111; //virgulilla
#500
char=7'b0000111; //p
#500
char=7'b0111111; //virgulilla
#500
char=7'b0111011; //ene
#500
char=7'b0000111; //p
#500
char=7'b0010000; //enter
#500
//char=7'b1000110; //uno
char=7'b1111011;
#500
char=7'b1000110; //uno
#500
char=0;
end
end
initial begin
forever begin
#50
clk=0;
#50
clk=1;
end
end
initial begin: TEST_CASE
$dumpfile("top_string_TB.vcd");
$dumpvars(-1, uut);
#60000 $finish;
end
endmodule
|
`timescale 1ns / 1ps
module TOP(
output N2_CAn_O,
output N2_CBn_O,
output N2_CCn_O,
output N2_CDn_O,
output N2_CEn_O,
output N2_CFn_O,
output N2_CGn_O,
output N2_CDPn_O,
output N2_AN0n_O,
output N2_AN1n_O,
output N2_AN2n_O,
output N2_AN3n_O,
output N2_HSYNC_O,
output N2_VSYNC_O,
output [2:0] N2_RED_O,
output [2:0] N2_GRN_O,
output [2:1] N2_BLU_O,
input N2_PS2DAT_IO,
input N2_PS2CLK_I,
input N2_50MHZ_I,
input N2_RST_I
);
wire [15:1] cpu_adr;
wire cpu_we;
wire cpu_cyc;
wire cpu_stb;
wire [1:0] cpu_sel;
wire cpu_vda;
wire cpu_vpa;
wire [15:0] cpu_dat_o;
wire [7:0] kia_dat_o;
wire kia_ack_o;
wire [15:0] ram_dat_o;
reg ram_ack_o;
reg led_a;
reg led_b;
reg led_c;
reg led_d;
reg led_e;
reg led_f;
reg led_g;
reg led_dp;
reg led_anode_0;
reg led_anode_1;
reg led_anode_2;
reg led_anode_3;
reg vsync;
reg hsync;
reg [2:0] red;
reg [2:0] green;
reg [2:1] blue;
////// CPU //////
wire bus_access = cpu_cyc & cpu_stb;
wire kia_addressed = (cpu_adr[15:12] == 4'h2) & bus_access & cpu_sel[0];
wire ledport_addressed = (cpu_adr[15:12] == 4'h1) & bus_access;
wire ram_addressed = (cpu_adr[15:12] == 4'h0) & bus_access;
wire [15:0] cpu_dat_i = ({16{ram_addressed}} & ram_dat_o) | {8'h00, ({8{kia_addressed}} & kia_dat_o)};
wire cpu_ack_i = ((ram_addressed | ledport_addressed ) & ram_ack_o) | (kia_addressed & kia_ack_o);
STEAMER16X4 cpu(
.clk_i(N2_50MHZ_I),
.res_i(N2_RST_I),
.adr_o(cpu_adr),
.we_o (cpu_we),
.cyc_o(cpu_cyc),
.stb_o(cpu_stb),
.sel_o(cpu_sel),
.vda_o(cpu_vda),
.vpa_o(cpu_vpa),
.dat_o(cpu_dat_o),
.ack_i(cpu_ack_i),
.dat_i(cpu_dat_i)
);
////// SYSTEM RAM //////
wire ram_even_en = ram_addressed & cpu_sel[0];
wire ram_odd_en = ram_addressed & cpu_sel[1];
RAMB16_S9 progmem_E(
.CLK(N2_50MHZ_I),
.WE(cpu_we),
.EN(ram_even_en),
.SSR(1'b0),
.ADDR(cpu_adr[11:1]),
.DI(cpu_dat_o[7:0]),
.DO(ram_dat_o[7:0]),
.DIP(1'b1)
);
RAMB16_S9 progmem_O(
.CLK(N2_50MHZ_I),
.WE(cpu_we),
.EN(ram_odd_en),
.SSR(1'b0),
.ADDR(cpu_adr[11:1]),
.DI(cpu_dat_o[15:8]),
.DO(ram_dat_o[15:8]),
.DIP(1'b1)
);
always @(posedge N2_50MHZ_I) begin
if(N2_RST_I) begin
ram_ack_o <= 0;
end else begin
ram_ack_o <= (~ram_ack_o) & (ram_addressed | ledport_addressed);
end
end
////// KIA //////
KIA_M kia(
.CLK_I(N2_50MHZ_I),
.RES_I(N2_RST_I),
.ADR_I(cpu_adr[1]),
.WE_I(cpu_we),
.CYC_I(cpu_cyc),
.STB_I(kia_addressed),
.ACK_O(kia_ack_o),
.DAT_O(kia_dat_o[7:0]),
.D_I(N2_PS2DAT_IO),
.C_I(N2_PS2CLK_I)
);
////// GPIO //////
assign N2_CAn_O = ~led_a;
assign N2_CBn_O = ~led_b;
assign N2_CCn_O = ~led_c;
assign N2_CDn_O = ~led_d;
assign N2_CEn_O = ~led_e;
assign N2_CFn_O = ~led_f;
assign N2_CGn_O = ~led_g;
assign N2_CDPn_O = ~led_dp;
assign N2_AN0n_O = ~led_anode_0;
assign N2_AN1n_O = ~led_anode_1;
assign N2_AN2n_O = ~led_anode_2;
assign N2_AN3n_O = ~led_anode_3;
assign N2_VSYNC_O = vsync;
assign N2_HSYNC_O = hsync;
assign N2_RED_O = red;
assign N2_GRN_O = green;
assign N2_BLU_O = blue;
always @(posedge N2_50MHZ_I) begin
if(N2_RST_I) begin
led_a <= 1; led_e <= 1;
led_b <= 1; led_f <= 1;
led_c <= 1; led_g <= 1;
led_d <= 1; led_dp <= 1;
led_anode_0 <= 1; led_anode_1 <= 1;
led_anode_2 <= 1; led_anode_3 <= 1;
vsync <= 1; hsync <= 1;
red <= 3'b000; green <= 3'b000;
blue <= 2'b00;
end
else begin
if(ledport_addressed & cpu_sel[0]) begin
led_a <= cpu_dat_o[0]; led_e <= cpu_dat_o[4];
led_b <= cpu_dat_o[1]; led_f <= cpu_dat_o[5];
led_c <= cpu_dat_o[2]; led_g <= cpu_dat_o[6];
led_d <= cpu_dat_o[3]; led_dp <= cpu_dat_o[7];
end
if(ledport_addressed & cpu_sel[1]) begin
led_anode_0 <= cpu_dat_o[12];
led_anode_1 <= cpu_dat_o[13];
led_anode_2 <= cpu_dat_o[14];
led_anode_3 <= cpu_dat_o[15];
end
end
end
////// RAM Images //////
defparam
progmem_E.INIT_00 = 256'h030202020202020202010101010101010100000000000000000000000000E200,
progmem_E.INIT_01 = 256'h0706060606060606060505050505050505040404040404040403030303030303,
progmem_E.INIT_02 = 256'h0B0A0A0A0A0A0A0A0A0909090909090909080808080808080807070707070707,
progmem_E.INIT_03 = 256'h0F0E0E0E0E0E0E0E0E0D0D0D0D0D0D0D0D0C0C0C0C0C0C0C0C0B0B0B0B0B0B0B,
progmem_E.INIT_04 = 256'h3A00001EE009081B0A091B0B0A1B1E00007939777F7D665B3F0F0F0F0F0F0F0F,
progmem_E.INIT_05 = 256'hE007000F06156E000054E03C6AE007B00E0614540000003A08B10E07142046E0,
progmem_E.INIT_06 = 256'h14B80000009E02128AB0E006021B9E000088E0709AE05694E08800006EE03C84,
progmem_E.INIT_07 = 256'hD600E00000000816EA0000D4E0BAE6E00C0030D40000B8E0BED01E0C0C12FF0C,
progmem_E.INIT_08 = 256'h163800001EE0D634E00000000A161E000004E0D61AE00000000916040000EAE0,
progmem_E.INIT_09 = 256'hE0EC7EE00678E02072E03A6CE06000000052001252000038E0D64EE00000000B,
progmem_E.INIT_0A = 256'h9CE0A20062B8E0A0B2E0B2008AA8E09C00000088011201001588000060E05484,
progmem_E.INIT_0B = 256'hFFFFBEFF00E0E09EF2E0C2ECE0E00000C0E00B001B0A000911000800B1C00000,
progmem_E.INIT_0C = 256'h3BBFDFFCE000BF6EFFFFFF162FFFF81DFFFDC2F8FB5E5DBEF9F7FBF1BBBFE2FF,
progmem_E.INIT_0D = 256'hBCE1FEFF241278FF972AFFFFFFFF6CFE2D2B7EFFFFC22CB216B2BFF8C003030E,
progmem_E.INIT_0E = 256'h5FC5FDFFFFFF7E2BFFCBC5C7FFFFFF5C92FFF2BFFFBFEF7EF0F87FBBBFBB5FC5,
progmem_E.INIT_0F = 256'hFFBFFB5FFD2FFF775F2D00000000200000000020BBFDC5FFE5E2EDE27EDF5FF9,
progmem_E.INIT_10 = 256'h97FFBFDFC5F7FFFFC57F8B26C4FEFFFBFFFFFFAF7FFFFFDDDFF1F7BDDF7FF2C5,
progmem_E.INIT_11 = 256'hE2FE7FE597F97E79F88BF8FFFF24F0F9FFE73FF297FF3F4949F1F1912CBDFDF9,
progmem_E.INIT_12 = 256'hFCFE5FE5FEFF7F5FF9BFFFABCBFFBF8500000000000048F2FFBFFFE2592E9716,
progmem_E.INIT_13 = 256'h5957E2FF97E6F1CCCC8CE5FCFFB6E2CB49FFD7D7FFF9FFFFFFFFF87F97F9FFFE,
progmem_E.INIT_14 = 256'h7CBFFFFFBF972FDB7BDFF97F5FFE2FFFEF6FF9FDF75BDF99F397D7E557FFFEFD,
progmem_E.INIT_15 = 256'hE2F9321244915FFF5FFFF998F9FF77F77FFBFF2FFCDFF1F2FD7B7F25F8E5975F,
progmem_E.INIT_16 = 256'hBFDFFF17FFFFF97F5F92BEFF8BBEFFC55FF2CBFFFFC57FFDFCFF452FFCE225FC,
progmem_E.INIT_17 = 256'hF8F876127D5B16CB49F75E0B4849249292CBF97FFD856619FDBF97FFFF655FCB,
progmem_E.INIT_18 = 256'hFFAFF797FFF2FFFFBFAF7C450402082021410410422110211020418108088484,
progmem_E.INIT_19 = 256'h5F5FFFDE7FBB1624482FF2E7F2FFFFFBBFFFFFFFFFDFFFE5FFFEFF92ED7F725B,
progmem_E.INIT_1A = 256'hFBFBFFF7FFEF7D7DFFFFFF8BFBEFFFF917EDFAFBFFFEED7FFF7D95F8FFFF7F7F,
progmem_E.INIT_1B = 256'hFFBFFEDF5BBFFFFFFB7FEFFFF7FFF67FBFFFE5FB7EF22BE589FFFFAFFF77927F,
progmem_E.INIT_1C = 256'hFFAF5FFF7FC27E080000209249248244BFFFF7FEDFFE7FAFFFFDFFFFFECBFF5F,
progmem_E.INIT_1D = 256'hFFF7CBBE81F81244E6FFFF5FF3FEFF3FE57FCFF95FF857FFFFC27F857EDFFFFB,
progmem_E.INIT_1E = 256'hEFFFFFEFFFFFF7EFFFDFFCF22FF8FFDBFFFFF1FFBFED8BFB5FE52FF2FEFF7FBC,
progmem_E.INIT_1F = 256'h5FBFFFFFFF5FFC2F85FFFFB51FFFFFF1FF62FFF1C28B8AFE7FFE7F6E25F7F7F2;
defparam
progmem_O.INIT_00 = 256'h030202020202020202010101010101010100000000000000000000000000021E,
progmem_O.INIT_01 = 256'h0706060606060606060505050505050505040404040404040403030303030303,
progmem_O.INIT_02 = 256'h0B0A0A0A0A0A0A0A0A0909090909090909080808080808080807070707070707,
progmem_O.INIT_03 = 256'h0F0E0E0E0E0E0E0E0E0D0D0D0D0D0D0D0D0C0C0C0C0C0C0C0C0B0B0B0B0B0B0B,
progmem_O.INIT_04 = 256'h011300011200001A00001A00001A011300715E7C6F076D4F060F0F0F0F0F0F0F,
progmem_O.INIT_05 = 256'h11001B00001A011300011201011100A100001A0113002E0100A101001A010111,
progmem_O.INIT_06 = 256'h12011300E001201B01011100201A011300011201011101011101130001120101,
progmem_O.INIT_07 = 256'h010211101310001A01130001120101110040110113000112010117000013FF00,
progmem_O.INIT_08 = 256'h1A0213000212010211101340001A0213000212010211101320001A0213000112,
progmem_O.INIT_09 = 256'h11010211020211020211020211021300E0021013021300021201021110138000,
progmem_O.INIT_0A = 256'h0212021E0202110102110217020211021300E002001600201A02130002120202,
progmem_O.INIT_0B = 256'hFFFFFFED00021202021102021102130002120000B10000001B00000011021300,
progmem_O.INIT_0C = 256'hF0C083010E772FF8E1FF052FDF7FAFE58BFFFFBFFDFFF1FC7F17FF7DFEFDFCFB,
progmem_O.INIT_0D = 256'h5F63577F5E498959FFEFFEFFFFFF2FF9FF9757EF2FC5B2CB2CCB2C031DBFBFFC,
progmem_O.INIT_0E = 256'hCB7CEFFDF8E25F7F92FFEF7FFFDF975F49E4FFFF7FC5F300073B9DF7FFF38BFC,
progmem_O.INIT_0F = 256'hDFFFF777FCBBFFE2FFDE01000000000100000000FFF7BE2FFFFFFFDF2FF9FB7E,
progmem_O.INIT_10 = 256'hE5FFCBDCFBFF0BFFEFFFE12F0C2FBF7FBFFF8BFFF8F1C5F7BF7F7DC58B77EF7F,
progmem_O.INIT_11 = 256'hFF5FE579957F5DF959FFBFFFF2BF7E7FE1E22FFEF39F2F7F24227B7D48FAF87F,
progmem_O.INIT_12 = 256'h5D5FE5FE5FE5F2F97EFFFCFFFFFFF8FC25000000000082FC2ECBC5CB7FFCF35F,
progmem_O.INIT_13 = 256'h2596FE97FF2F7FCBCCCCF9AF155FF8FF652EEBE5AF77FFF22FF2B297F97F97FF,
progmem_O.INIT_14 = 256'hBE99FCF7FD8A97F7BFBF77EFF7FEFEFFEFFE25FF7DBE127F2FFFCB752B2E5FFF,
progmem_O.INIT_15 = 256'hF27FFF238922C8FC95FCCBBF7FFFF7FCFFBFEFC5BFF27DEFFFCBFFF9B1F2CB2F,
progmem_O.INIT_16 = 256'hF7FFE2BFBDFF7BFFE1E9A578FFC4FFBFDFFEFFFFFFF7E7F1BF7BFEF2BEFB8B91,
progmem_O.INIT_17 = 256'h88BF5F1689B1EC3B6E24E2DC9324924944E07EC1D98B2E8C7FCB7FDFF7FFE6DE,
progmem_O.INIT_18 = 256'hFEC5FCE5FF4BD7DFFFCC24FF2208128208041082100884084282080880442120,
progmem_O.INIT_19 = 256'hF1FCF9FFFBE52C89919249C5FFFFFFDFFFFED6FF2FFFFAFFD717EF57FDFFB9E5,
progmem_O.INIT_1A = 256'hF997FF7FBECAFFF1F1FFFFEFFFFF176FFFFFEFFFFF2FFFFAF9EFFFBFDEFBEDF9,
progmem_O.INIT_1B = 256'hFECB2496F29217BF7FDFCBDDF2DFFFCBF7FFFEFD5FFF77FF17FFFF729CE249BF,
progmem_O.INIT_1C = 256'h0BF7F8FCC5BF2FB1000000492492242495C2FFFFDF2EFFFFF8FF7FDF2BCBFFDF,
progmem_O.INIT_1D = 256'hEFFF2FA2F8572F89623FE5F3FE5F3FE5FFCFF97FF3B8C5BCE2BBFF7FFF85018B,
progmem_O.INIT_1E = 256'hFDFFEFFFFFEFFFFFBDEFB7FEFFAFFFFFC58B7FFFFFE2BEFDEBFCFFEC5D7ADEBF,
progmem_O.INIT_1F = 256'hFFBCFCFFFFFFBC0BFE17FFBFF8FE9F5FFFF7FF7FFFFFFF5F9549CBF9B9997FE5;
endmodule
|
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact: [email protected]
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: openhmc_ram
*
*/
`default_nettype none
module openhmc_ram #(
parameter DATASIZE = 78, // Memory data word width
parameter ADDRSIZE = 9, // Number of memory address bits
parameter PIPELINED = 0
) (
//----------------------------------
//----SYSTEM INTERFACE
//----------------------------------
input wire clk,
//----------------------------------
//----Signals
//----------------------------------
input wire wen,
input wire [DATASIZE-1:0] wdata,
input wire [ADDRSIZE-1:0] waddr,
input wire ren,
input wire [ADDRSIZE-1:0] raddr,
output wire [DATASIZE-1:0] rdata
);
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
wire [DATASIZE-1:0] rdata_ram;
generate
if (PIPELINED == 0)
begin
assign rdata = rdata_ram;
end
else
begin
reg [DATASIZE-1:0] rdata_dly;
reg ren_dly;
assign rdata = rdata_dly;
always @(posedge clk)
begin
ren_dly <= ren;
if (ren_dly)
rdata_dly <= rdata_ram;
end
end
endgenerate
reg [DATASIZE-1:0] MEM [0:(2**ADDRSIZE)-1];
reg [DATASIZE-1:0] data_out;
assign rdata_ram = data_out;
always @(posedge clk)
begin
if (wen)
MEM[waddr] <= wdata;
end
always @(posedge clk)
begin
if (ren)
data_out <= MEM[raddr];
end
endmodule
`default_nettype wire
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-------------------------------------------------------------------
// Filename : mem_bipo.v
// Author : Yibo FAN
// Created : 2014-01-16
// Description : Memory Buf Block Input, Parallel line Output
// Support: IN OUT
// 4x4 block 32x1 line
// 16x2 line
// 8x4 line
// 4x4 line
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module mem_bipo_2p (
clk ,
rst_n ,
wen_i ,
wsize_i ,
w4x4_x_i ,
w4x4_y_i ,
wdata_i ,
ren_i ,
rsize_i ,
r4x4_x_i ,
r4x4_y_i ,
ridx_i ,
rdata_o
);
// ********************************************
//
// Parameter DECLARATION
//
// ********************************************
localparam I_4x4 = 2'b00,
I_8x8 = 2'b01,
I_16x16 = 2'b10,
I_32x32 = 2'b11;
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk ; //clock
input rst_n ; //reset signal
input wen_i ; //
input [1:0] wsize_i ; //
input [3:0] w4x4_x_i ; //
input [3:0] w4x4_y_i ; //
input [`PIXEL_WIDTH*16-1:0] wdata_i ; //
input ren_i ; //
input [1:0] rsize_i ; //
input [3:0] r4x4_x_i ; //
input [3:0] r4x4_y_i ; //
input [4:0] ridx_i ; //
output [`PIXEL_WIDTH*32-1:0] rdata_o ; //
// ********************************************
//
// Signals DECLARATION
//
// ********************************************
// R/W Data & Address
wire [`PIXEL_WIDTH*4-1:0] w_4x4_l0 ,
w_4x4_l1 ,
w_4x4_l2 ,
w_4x4_l3 ;
reg [1:0] b0_waddr_l, b0_raddr_l,
b1_waddr_l, b1_raddr_l,
b2_waddr_l, b2_raddr_l,
b3_waddr_l, b3_raddr_l;
wire [2:0] b0_waddr_h,
b1_waddr_h,
b2_waddr_h,
b3_waddr_h;
reg [2:0] b0_raddr_h,
b1_raddr_h,
b2_raddr_h,
b3_raddr_h;
wire [4:0] b0_waddr, b0_raddr,
b1_waddr, b1_raddr,
b2_waddr, b2_raddr,
b3_waddr, b3_raddr;
reg [`PIXEL_WIDTH*8-1:0] b0_wdata,
b1_wdata,
b2_wdata,
b3_wdata;
wire [`PIXEL_WIDTH*8-1:0] b0_rdata,
b2_rdata,
b1_rdata,
b3_rdata;
reg [`PIXEL_WIDTH*32-1:0] b_rdata;
reg [1:0] rsize_r ;
reg [3:0] r4x4_x_r;
reg [4:0] ridx_r ;
// R/W Control
wire [1:0] b0_wen,
b1_wen,
b2_wen,
b3_wen;
wire b0_ren,
b1_ren,
b2_ren,
b3_ren;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
// --------------------------------------------
// Memory Banks
//---------------------------------------------
//-------------- MEM Write ----------------//
assign b0_wen = wen_i?({~w4x4_x_i[0], w4x4_x_i[0]}) : 2'b00;
assign b1_wen = wen_i?({~w4x4_x_i[0], w4x4_x_i[0]}) : 2'b00;
assign b2_wen = wen_i?({~w4x4_x_i[0], w4x4_x_i[0]}) : 2'b00;
assign b3_wen = wen_i?({~w4x4_x_i[0], w4x4_x_i[0]}) : 2'b00;
assign w_4x4_l0 = wdata_i[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*12];
assign w_4x4_l1 = wdata_i[`PIXEL_WIDTH*12-1:`PIXEL_WIDTH*8];
assign w_4x4_l2 = wdata_i[`PIXEL_WIDTH*8 -1:`PIXEL_WIDTH*4];
assign w_4x4_l3 = wdata_i[`PIXEL_WIDTH*4 -1:`PIXEL_WIDTH*0];
always@(*) begin
case (w4x4_x_i[2:0])
3'd0: {b0_wdata, b1_wdata, b2_wdata, b3_wdata} = { w_4x4_l0, `PIXEL_WIDTH*4'b0,
w_4x4_l1, `PIXEL_WIDTH*4'b0,
w_4x4_l2, `PIXEL_WIDTH*4'b0,
w_4x4_l3, `PIXEL_WIDTH*4'b0};
3'd1: {b0_wdata, b1_wdata, b2_wdata, b3_wdata} = { `PIXEL_WIDTH*4'b0, w_4x4_l0,
`PIXEL_WIDTH*4'b0, w_4x4_l1,
`PIXEL_WIDTH*4'b0, w_4x4_l2,
`PIXEL_WIDTH*4'b0, w_4x4_l3};
3'd2: {b0_wdata, b1_wdata, b2_wdata, b3_wdata} = { w_4x4_l2, `PIXEL_WIDTH*4'b0,
w_4x4_l3, `PIXEL_WIDTH*4'b0,
w_4x4_l0, `PIXEL_WIDTH*4'b0,
w_4x4_l1, `PIXEL_WIDTH*4'b0};
3'd3: {b0_wdata, b1_wdata, b2_wdata, b3_wdata} = { `PIXEL_WIDTH*4'b0, w_4x4_l2,
`PIXEL_WIDTH*4'b0, w_4x4_l3,
`PIXEL_WIDTH*4'b0, w_4x4_l0,
`PIXEL_WIDTH*4'b0, w_4x4_l1};
3'd4: {b0_wdata, b1_wdata, b2_wdata, b3_wdata} = { w_4x4_l3, `PIXEL_WIDTH*4'b0,
w_4x4_l0, `PIXEL_WIDTH*4'b0,
w_4x4_l1, `PIXEL_WIDTH*4'b0,
w_4x4_l2, `PIXEL_WIDTH*4'b0};
3'd5: {b0_wdata, b1_wdata, b2_wdata, b3_wdata} = { `PIXEL_WIDTH*4'b0, w_4x4_l3,
`PIXEL_WIDTH*4'b0, w_4x4_l0,
`PIXEL_WIDTH*4'b0, w_4x4_l1,
`PIXEL_WIDTH*4'b0, w_4x4_l2};
3'd6: {b0_wdata, b1_wdata, b2_wdata, b3_wdata} = { w_4x4_l1, `PIXEL_WIDTH*4'b0,
w_4x4_l2, `PIXEL_WIDTH*4'b0,
w_4x4_l3, `PIXEL_WIDTH*4'b0,
w_4x4_l0, `PIXEL_WIDTH*4'b0};
3'd7: {b0_wdata, b1_wdata, b2_wdata, b3_wdata} = { `PIXEL_WIDTH*4'b0, w_4x4_l1,
`PIXEL_WIDTH*4'b0, w_4x4_l2,
`PIXEL_WIDTH*4'b0, w_4x4_l3,
`PIXEL_WIDTH*4'b0, w_4x4_l0};
endcase
end
always @(*) begin
case (w4x4_x_i[2:0])
3'd0, 3'd1: begin b0_waddr_l=2'd0; b1_waddr_l=2'd1; b2_waddr_l=2'd2; b3_waddr_l=2'd3; end
3'd2, 3'd3: begin b0_waddr_l=2'd2; b1_waddr_l=2'd3; b2_waddr_l=2'd0; b3_waddr_l=2'd1; end
3'd4, 3'd5: begin b0_waddr_l=2'd3; b1_waddr_l=2'd0; b2_waddr_l=2'd1; b3_waddr_l=2'd2; end
3'd6, 3'd7: begin b0_waddr_l=2'd1; b1_waddr_l=2'd2; b2_waddr_l=2'd3; b3_waddr_l=2'd0; end
endcase
end
assign b0_waddr_h = w4x4_y_i[2:0];
assign b1_waddr_h = w4x4_y_i[2:0];
assign b2_waddr_h = w4x4_y_i[2:0];
assign b3_waddr_h = w4x4_y_i[2:0];
assign b0_waddr = {b0_waddr_h, b0_waddr_l};
assign b1_waddr = {b1_waddr_h, b1_waddr_l};
assign b2_waddr = {b2_waddr_h, b2_waddr_l};
assign b3_waddr = {b3_waddr_h, b3_waddr_l};
//-------------- MEM Read ----------------//
assign b0_ren = ren_i;
assign b1_ren = ren_i;
assign b2_ren = ren_i;
assign b3_ren = ren_i;
// address generater
always @(*) begin
case (rsize_i)
I_4x4 ,
I_8x8 : begin
case (r4x4_x_i[2:1])
2'd0: begin b0_raddr_l=2'd0; b1_raddr_l=2'd1; b2_raddr_l=2'd2; b3_raddr_l=2'd3; end
2'd1: begin b0_raddr_l=2'd2; b1_raddr_l=2'd3; b2_raddr_l=2'd0; b3_raddr_l=2'd1; end
2'd2: begin b0_raddr_l=2'd3; b1_raddr_l=2'd0; b2_raddr_l=2'd1; b3_raddr_l=2'd2; end
2'd3: begin b0_raddr_l=2'd1; b1_raddr_l=2'd2; b2_raddr_l=2'd3; b3_raddr_l=2'd0; end
endcase
end
I_16x16 : begin b0_raddr_l = {ridx_i[1], r4x4_x_i[2]};
b1_raddr_l = {ridx_i[1], ~r4x4_x_i[2]};
b2_raddr_l = {ridx_i[1], r4x4_x_i[2]};
b3_raddr_l = {ridx_i[1], ~r4x4_x_i[2]};
end
I_32x32 : begin b0_raddr_l = ridx_i[1:0];
b1_raddr_l = ridx_i[1:0];
b2_raddr_l = ridx_i[1:0];
b3_raddr_l = ridx_i[1:0];
end
endcase
end
always @(*) begin
case (rsize_i)
I_4x4 : begin b0_raddr_h = r4x4_y_i[2:0];
b1_raddr_h = r4x4_y_i[2:0];
b2_raddr_h = r4x4_y_i[2:0];
b3_raddr_h = r4x4_y_i[2:0];
end
I_8x8 : begin b0_raddr_h = {r4x4_y_i[2:1], ridx_i[2]};
b1_raddr_h = {r4x4_y_i[2:1], ridx_i[2]};
b2_raddr_h = {r4x4_y_i[2:1], ridx_i[2]};
b3_raddr_h = {r4x4_y_i[2:1], ridx_i[2]};
end
I_16x16 : begin b0_raddr_h = {r4x4_y_i[2], ridx_i[3:2]};
b1_raddr_h = {r4x4_y_i[2], ridx_i[3:2]};
b2_raddr_h = {r4x4_y_i[2], ridx_i[3:2]};
b3_raddr_h = {r4x4_y_i[2], ridx_i[3:2]};
end
I_32x32 : begin b0_raddr_h = ridx_i[4:2];
b1_raddr_h = ridx_i[4:2];
b2_raddr_h = ridx_i[4:2];
b3_raddr_h = ridx_i[4:2];
end
endcase
end
assign b0_raddr = {b0_raddr_h, b0_raddr_l};
assign b1_raddr = {b1_raddr_h, b1_raddr_l};
assign b2_raddr = {b2_raddr_h, b2_raddr_l};
assign b3_raddr = {b3_raddr_h, b3_raddr_l};
// data alignment
always@(posedge clk or negedge rst_n) begin
if (!rst_n) begin
rsize_r <= 'b0;
r4x4_x_r <= 'b0;
ridx_r <= 'b0;
end
else begin
rsize_r <= rsize_i;
r4x4_x_r <= r4x4_x_i;
ridx_r <= ridx_i;
end
end
always @(*) begin
case (rsize_r)
I_4x4 : if (r4x4_x_r[0]) begin
case (r4x4_x_r[2:1])
2'd0: b_rdata = { b0_rdata[`PIXEL_WIDTH*4-1:0] ,b0_rdata[`PIXEL_WIDTH*8-1:`PIXEL_WIDTH*4] ,
b1_rdata[`PIXEL_WIDTH*4-1:0] ,b1_rdata[`PIXEL_WIDTH*8-1:`PIXEL_WIDTH*4] ,
b2_rdata[`PIXEL_WIDTH*4-1:0] ,b2_rdata[`PIXEL_WIDTH*8-1:`PIXEL_WIDTH*4] ,
b3_rdata[`PIXEL_WIDTH*4-1:0] ,b3_rdata[`PIXEL_WIDTH*8-1:`PIXEL_WIDTH*4] };
2'd1: b_rdata = { b2_rdata[`PIXEL_WIDTH*4-1:0] ,b2_rdata[`PIXEL_WIDTH*8-1:`PIXEL_WIDTH*4] ,
b3_rdata[`PIXEL_WIDTH*4-1:0] ,b3_rdata[`PIXEL_WIDTH*8-1:`PIXEL_WIDTH*4] ,
b0_rdata[`PIXEL_WIDTH*4-1:0] ,b0_rdata[`PIXEL_WIDTH*8-1:`PIXEL_WIDTH*4] ,
b1_rdata[`PIXEL_WIDTH*4-1:0] ,b1_rdata[`PIXEL_WIDTH*8-1:`PIXEL_WIDTH*4] };
2'd2: b_rdata = { b1_rdata[`PIXEL_WIDTH*4-1:0] ,b1_rdata[`PIXEL_WIDTH*8-1:`PIXEL_WIDTH*4] ,
b2_rdata[`PIXEL_WIDTH*4-1:0] ,b2_rdata[`PIXEL_WIDTH*8-1:`PIXEL_WIDTH*4] ,
b3_rdata[`PIXEL_WIDTH*4-1:0] ,b3_rdata[`PIXEL_WIDTH*8-1:`PIXEL_WIDTH*4] ,
b0_rdata[`PIXEL_WIDTH*4-1:0] ,b0_rdata[`PIXEL_WIDTH*8-1:`PIXEL_WIDTH*4] };
2'd3: b_rdata = { b3_rdata[`PIXEL_WIDTH*4-1:0] ,b3_rdata[`PIXEL_WIDTH*8-1:`PIXEL_WIDTH*4] ,
b0_rdata[`PIXEL_WIDTH*4-1:0] ,b0_rdata[`PIXEL_WIDTH*8-1:`PIXEL_WIDTH*4] ,
b1_rdata[`PIXEL_WIDTH*4-1:0] ,b1_rdata[`PIXEL_WIDTH*8-1:`PIXEL_WIDTH*4] ,
b2_rdata[`PIXEL_WIDTH*4-1:0] ,b2_rdata[`PIXEL_WIDTH*8-1:`PIXEL_WIDTH*4] };
endcase
end
else begin
case (r4x4_x_r[2:1])
2'd0: b_rdata = {b0_rdata, b1_rdata, b2_rdata, b3_rdata};
2'd1: b_rdata = {b2_rdata, b3_rdata, b0_rdata, b1_rdata};
2'd2: b_rdata = {b1_rdata, b2_rdata, b3_rdata, b0_rdata};
2'd3: b_rdata = {b3_rdata, b0_rdata, b1_rdata, b2_rdata};
endcase
end
I_8x8 : case (r4x4_x_r[2:1])
2'd0: b_rdata = {b0_rdata, b1_rdata, b2_rdata, b3_rdata};
2'd1: b_rdata = {b2_rdata, b3_rdata, b0_rdata, b1_rdata};
2'd2: b_rdata = {b1_rdata, b2_rdata, b3_rdata, b0_rdata};
2'd3: b_rdata = {b3_rdata, b0_rdata, b1_rdata, b2_rdata};
endcase
I_16x16 : case ({r4x4_x_r[2], ridx_r[1]})
2'd0: b_rdata = {b0_rdata, b2_rdata, b1_rdata, b3_rdata};
2'd1: b_rdata = {b2_rdata, b0_rdata, b3_rdata, b1_rdata};
2'd2: b_rdata = {b1_rdata, b3_rdata, b2_rdata, b0_rdata};
2'd3: b_rdata = {b3_rdata, b1_rdata, b0_rdata, b2_rdata};
endcase
I_32x32 : case (ridx_r[1:0])
2'd0: b_rdata = {b0_rdata, b2_rdata, b1_rdata, b3_rdata};
2'd1: b_rdata = {b1_rdata, b3_rdata, b2_rdata, b0_rdata};
2'd2: b_rdata = {b2_rdata, b0_rdata, b3_rdata, b1_rdata};
2'd3: b_rdata = {b3_rdata, b1_rdata, b0_rdata, b2_rdata};
endcase
endcase
end
assign rdata_o = b_rdata;
// MEM Modules
buf_ram_2p_64x32 buf_pre_0(
.clk ( clk ),
.a_we ( b0_wen ),
.a_addr ( b0_waddr ),
.a_data_i ( b0_wdata ),
.b_re ( b0_ren ),
.b_addr ( b0_raddr ),
.b_data_o ( b0_rdata )
);
buf_ram_2p_64x32 buf_pre_1(
.clk ( clk ),
.a_we ( b1_wen ),
.a_addr ( b1_waddr ),
.a_data_i ( b1_wdata ),
.b_re ( b1_ren ),
.b_addr ( b1_raddr ),
.b_data_o ( b1_rdata )
);
buf_ram_2p_64x32 buf_pre_2(
.clk ( clk ),
.a_we ( b2_wen ),
.a_addr ( b2_waddr ),
.a_data_i ( b2_wdata ),
.b_re ( b2_ren ),
.b_addr ( b2_raddr ),
.b_data_o ( b2_rdata )
);
buf_ram_2p_64x32 buf_pre_3(
.clk ( clk ),
.a_we ( b3_wen ),
.a_addr ( b3_waddr ),
.a_data_i ( b3_wdata ),
.b_re ( b3_ren ),
.b_addr ( b3_raddr ),
.b_data_o ( b3_rdata )
);
endmodule |
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "pciw_fifo_control.v" ////
//// ////
//// This file is part of the "PCI bridge" project ////
//// http://www.opencores.org/cores/pci/ ////
//// ////
//// Author(s): ////
//// - Miha Dolenc ([email protected]) ////
//// ////
//// All additional information is avaliable in the README ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Miha Dolenc, [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: pci_pciw_fifo_control.v,v $
// Revision 1.5 2003/08/14 13:06:03 simons
// synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.
//
// Revision 1.4 2003/08/08 16:36:33 tadejm
// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.
//
// Revision 1.3 2003/07/29 08:20:11 mihad
// Found and simulated the problem in the synchronization logic.
// Repaired the synchronization logic in the FIFOs.
//
//
/* FIFO_CONTROL module provides read/write address and status generation for
FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */
module /*pci_pciw_*/fifo_control
(
rclock_in,
wclock_in,
renable_in,
wenable_in,
reset_in,
clear_in,
almost_full_out,
full_out,
almost_empty_out,
empty_out,
waddr_out,
raddr_out,
rallow_out,
wallow_out,
three_left_out,
two_left_out,
half_full_out
);
parameter ADDR_LENGTH = 7 ;
// independent clock inputs - rclock_in = read clock, wclock_in = write clock
input rclock_in, wclock_in;
// enable inputs - read address changes on rising edge of rclock_in when reads are allowed
// write address changes on rising edge of wclock_in when writes are allowed
input renable_in, wenable_in;
// reset input
input reset_in, clear_in;
// almost full and empy status outputs
output almost_full_out, almost_empty_out;
// full and empty status outputs
output full_out, empty_out;
// read and write addresses outputs
output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out;
// read and write allow outputs
output rallow_out, wallow_out ;
// three and two locations left output indicator
output three_left_out ;
output two_left_out ;
output half_full_out;
// read address register
reg [(ADDR_LENGTH - 1):0] raddr ;
// write address register
reg [(ADDR_LENGTH - 1):0] waddr;
reg [(ADDR_LENGTH - 1):0] waddr_plus1;
assign waddr_out = waddr ;
// grey code registers
// grey code pipeline for write address
reg [(ADDR_LENGTH - 1):0] wgrey_minus1 ; // previous
reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current
reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next
reg [(ADDR_LENGTH - 1):0] wgrey_next_plus1 ; // next plus 1
// next write gray address calculation - bitwise xor between address and shifted address
wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
wire [(ADDR_LENGTH - 2):0] calc_wgrey_next_plus1 = waddr_plus1[(ADDR_LENGTH - 1):1] ^ waddr_plus1[(ADDR_LENGTH - 2):0] ;
// grey code pipeline for read address
reg [(ADDR_LENGTH - 1):0] rgrey_minus2 ; // two before current
reg [(ADDR_LENGTH - 1):0] rgrey_minus1 ; // one before current
reg [(ADDR_LENGTH - 1):0] rgrey_addr ; // current
reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next
// next read gray address calculation - bitwise xor between address and shifted address
wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
// write allow - writes are allowed when fifo is not full
assign wallow_out = wenable_in & ~full_out ;
// clear generation for FFs and registers
wire clear = clear_in ;
//rallow generation
assign rallow_out = renable_in & ~empty_out ; // reads allowed if read enable is high and FIFO is not empty
// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
// when FIFO is empty, this register provides actual read address, so first location can be read
reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
wire [ADDR_LENGTH :0] fifo_fullness;
assign fifo_fullness = (waddr > raddr) ? ({1'b0, waddr} - {1'b0, raddr}) : ({1'b1, waddr} - {1'b0, raddr});
assign half_full_out = fifo_fullness[(ADDR_LENGTH - 1)] ;
// read address mux - when read is performed, next address is driven, so next data is available immediately after read
// this is convenient for zero wait stait bursts
assign raddr_out = rallow_out ? raddr_plus_one : raddr ;
always@(posedge rclock_in or posedge clear)
begin
if (clear)
begin
// initial values seem a bit odd - they are this way to allow easier grey pipeline implementation and to allow min fifo size of 8
raddr_plus_one <= #1 5 ;
raddr <= #1 4 ;
// raddr_plus_one <= #1 6 ;
// raddr <= #1 5 ;
end
else if (rallow_out)
begin
raddr_plus_one <= #1 raddr_plus_one + 1'b1 ;
raddr <= #1 raddr_plus_one ;
end
end
/*-----------------------------------------------------------------------------------------------
Read address control consists of Read address counter and Grey Address pipeline
There are 4 Grey addresses:
- rgrey_minus2 is Grey Code of address two before current address
- rgrey_minus1 is Grey Code of address one before current address
- rgrey_addr is Grey Code of current read address
- rgrey_next is Grey Code of next read address
--------------------------------------------------------------------------------------------------*/
// grey coded address pipeline for status generation in read clock domain
always@(posedge rclock_in or posedge clear)
begin
if (clear)
begin
rgrey_minus2 <= #1 0 ;
rgrey_minus1 <= #1 1 ;
rgrey_addr <= #1 3 ;
rgrey_next <= #1 2 ;
end
else
if (rallow_out)
begin
rgrey_minus2 <= #1 rgrey_minus1 ;
rgrey_minus1 <= #1 rgrey_addr ;
rgrey_addr <= #1 rgrey_next ;
rgrey_next <= #1 {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
end
end
/*--------------------------------------------------------------------------------------------
Write address control consists of write address counter and 3 Grey Code Registers:
- wgrey_minus1 represents previous Grey coded write address
- wgrey_addr represents current Grey Coded write address
- wgrey_next represents next Grey Coded write address
- wgrey_next_plus1 represents second next Grey Coded write address
----------------------------------------------------------------------------------------------*/
// grey coded address pipeline for status generation in write clock domain
always@(posedge wclock_in or posedge clear)
begin
if (clear)
begin
wgrey_minus1 <= #1 1 ;
wgrey_addr <= #1 3 ;
wgrey_next <= #1 2 ;
wgrey_next_plus1 <= #1 6;
end
else
if (wallow_out)
begin
wgrey_minus1 <= #1 wgrey_addr ;
wgrey_addr <= #1 wgrey_next ;
wgrey_next <= #1 {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
// wgrey_next <= #1 wgrey_next_plus1 ;
wgrey_next_plus1 <= #1 {waddr_plus1[(ADDR_LENGTH - 1)], calc_wgrey_next_plus1} ;
end
end
// write address counter - nothing special except initial value
always@(posedge wclock_in or posedge clear)
begin
if (clear)
begin
// initial value 5
waddr <= #1 4 ;
waddr_plus1 <= #1 5 ;
end
else
if (wallow_out)
begin
waddr <= #1 waddr + 1'b1 ;
waddr_plus1 <= #1 waddr_plus1 + 1'b1 ;
end
end
/*------------------------------------------------------------------------------------------------------------------------------
Gray coded address of read address decremented by two is synchronized to write clock domain and compared to:
- previous grey coded write address - if they are equal, the fifo is full
- gray coded write address. If they are equal, fifo is almost full.
- grey coded next write address. If they are equal, the fifo has two free locations left.
--------------------------------------------------------------------------------------------------------------------------------*/
wire [(ADDR_LENGTH - 1):0] wclk_sync_rgrey_minus2 ;
reg [(ADDR_LENGTH - 1):0] wclk_rgrey_minus2 ;
/*pci_*/synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_rgrey_minus2
(
.data_in (rgrey_minus2),
.clk_out (wclock_in),
.sync_data_out (wclk_sync_rgrey_minus2),
.async_reset (clear)
) ;
always@(posedge wclock_in or posedge clear)
begin
if (clear)
begin
wclk_rgrey_minus2 <= #1 0 ;
end
else
begin
wclk_rgrey_minus2 <= #1 wclk_sync_rgrey_minus2 ;
end
end
assign full_out = (wgrey_minus1 == wclk_rgrey_minus2) ;
assign almost_full_out = (wgrey_addr == wclk_rgrey_minus2) ;
assign two_left_out = (wgrey_next == wclk_rgrey_minus2) ;
assign three_left_out = (wgrey_next_plus1 == wclk_rgrey_minus2) ;
/*------------------------------------------------------------------------------------------------------------------------------
Empty control:
Gray coded write address pointer is synchronized to read clock domain and compared to Gray coded read address pointer.
If they are equal, fifo is empty.
Almost empty control:
Synchronized write pointer is also compared to Gray coded next read address. If these two are
equal, fifo is almost empty.
--------------------------------------------------------------------------------------------------------------------------------*/
wire [(ADDR_LENGTH - 1):0] rclk_sync_wgrey_addr ;
reg [(ADDR_LENGTH - 1):0] rclk_wgrey_addr ;
/*pci_*/synchronizer_flop #(ADDR_LENGTH, 3) i_synchronizer_reg_wgrey_addr
(
.data_in (wgrey_addr),
.clk_out (rclock_in),
.sync_data_out (rclk_sync_wgrey_addr),
.async_reset (clear)
) ;
always@(posedge rclock_in or posedge clear)
begin
if (clear)
rclk_wgrey_addr <= #1 3 ;
else
rclk_wgrey_addr <= #1 rclk_sync_wgrey_addr ;
end
assign almost_empty_out = (rgrey_next == rclk_wgrey_addr) ;
assign empty_out = (rgrey_addr == rclk_wgrey_addr) ;
endmodule
|
//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_server_core_request_put O 1 reg
// server_core_response_get O 70 reg
// RDY_server_core_response_get O 1 reg
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// server_core_request_put I 202 reg
// EN_server_core_request_put I 1
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_server_core_response_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkFPU(CLK,
RST_N,
server_core_request_put,
EN_server_core_request_put,
RDY_server_core_request_put,
EN_server_core_response_get,
server_core_response_get,
RDY_server_core_response_get,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get);
input CLK;
input RST_N;
// action method server_core_request_put
input [201 : 0] server_core_request_put;
input EN_server_core_request_put;
output RDY_server_core_request_put;
// actionvalue method server_core_response_get
input EN_server_core_response_get;
output [69 : 0] server_core_response_get;
output RDY_server_core_response_get;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// signals for module outputs
wire [69 : 0] server_core_response_get;
wire RDY_server_core_request_put,
RDY_server_core_response_get,
RDY_server_reset_request_put,
RDY_server_reset_response_get;
// inlined wires
reg [68 : 0] resWire$wget;
wire crg_done$EN_port0__write,
crg_done$EN_port1__write,
crg_done$port1__read,
crg_done$port2__read,
crg_done_1$EN_port0__write,
crg_done_1$EN_port1__write,
crg_done_1$port1__read,
crg_done_1$port2__read,
resWire$whas;
// register crg_done
reg crg_done;
wire crg_done$D_IN, crg_done$EN;
// register crg_done_1
reg crg_done_1;
wire crg_done_1$D_IN, crg_done_1$EN;
// register rg_b
reg [115 : 0] rg_b;
wire [115 : 0] rg_b$D_IN;
wire rg_b$EN;
// register rg_busy
reg rg_busy;
wire rg_busy$D_IN, rg_busy$EN;
// register rg_busy_1
reg rg_busy_1;
wire rg_busy_1$D_IN, rg_busy_1$EN;
// register rg_d
reg [57 : 0] rg_d;
wire [57 : 0] rg_d$D_IN;
wire rg_d$EN;
// register rg_index
reg [5 : 0] rg_index;
wire [5 : 0] rg_index$D_IN;
wire rg_index$EN;
// register rg_index_1
reg [5 : 0] rg_index_1;
wire [5 : 0] rg_index_1$D_IN;
wire rg_index_1$EN;
// register rg_q
reg [57 : 0] rg_q;
wire [57 : 0] rg_q$D_IN;
wire rg_q$EN;
// register rg_r
reg [115 : 0] rg_r;
wire [115 : 0] rg_r$D_IN;
wire rg_r$EN;
// register rg_r_1
reg [115 : 0] rg_r_1;
wire [115 : 0] rg_r_1$D_IN;
wire rg_r_1$EN;
// register rg_res
reg [116 : 0] rg_res;
wire [116 : 0] rg_res$D_IN;
wire rg_res$EN;
// register rg_s
reg [115 : 0] rg_s;
wire [115 : 0] rg_s$D_IN;
wire rg_s$EN;
// ports of submodule fpu_div_fOperands_S0
wire [130 : 0] fpu_div_fOperands_S0$D_IN, fpu_div_fOperands_S0$D_OUT;
wire fpu_div_fOperands_S0$CLR,
fpu_div_fOperands_S0$DEQ,
fpu_div_fOperands_S0$EMPTY_N,
fpu_div_fOperands_S0$ENQ,
fpu_div_fOperands_S0$FULL_N;
// ports of submodule fpu_div_fResult_S5
wire [68 : 0] fpu_div_fResult_S5$D_IN, fpu_div_fResult_S5$D_OUT;
wire fpu_div_fResult_S5$CLR,
fpu_div_fResult_S5$DEQ,
fpu_div_fResult_S5$EMPTY_N,
fpu_div_fResult_S5$ENQ,
fpu_div_fResult_S5$FULL_N;
// ports of submodule fpu_div_fState_S1
wire [318 : 0] fpu_div_fState_S1$D_IN, fpu_div_fState_S1$D_OUT;
wire fpu_div_fState_S1$CLR,
fpu_div_fState_S1$DEQ,
fpu_div_fState_S1$EMPTY_N,
fpu_div_fState_S1$ENQ,
fpu_div_fState_S1$FULL_N;
// ports of submodule fpu_div_fState_S2
wire [147 : 0] fpu_div_fState_S2$D_IN, fpu_div_fState_S2$D_OUT;
wire fpu_div_fState_S2$CLR,
fpu_div_fState_S2$DEQ,
fpu_div_fState_S2$EMPTY_N,
fpu_div_fState_S2$ENQ,
fpu_div_fState_S2$FULL_N;
// ports of submodule fpu_div_fState_S3
wire [194 : 0] fpu_div_fState_S3$D_IN, fpu_div_fState_S3$D_OUT;
wire fpu_div_fState_S3$CLR,
fpu_div_fState_S3$DEQ,
fpu_div_fState_S3$EMPTY_N,
fpu_div_fState_S3$ENQ,
fpu_div_fState_S3$FULL_N;
// ports of submodule fpu_div_fState_S4
wire [138 : 0] fpu_div_fState_S4$D_IN, fpu_div_fState_S4$D_OUT;
wire fpu_div_fState_S4$CLR,
fpu_div_fState_S4$DEQ,
fpu_div_fState_S4$EMPTY_N,
fpu_div_fState_S4$ENQ,
fpu_div_fState_S4$FULL_N;
// ports of submodule fpu_madd_fOperand_S0
wire [195 : 0] fpu_madd_fOperand_S0$D_IN, fpu_madd_fOperand_S0$D_OUT;
wire fpu_madd_fOperand_S0$CLR,
fpu_madd_fOperand_S0$DEQ,
fpu_madd_fOperand_S0$EMPTY_N,
fpu_madd_fOperand_S0$ENQ,
fpu_madd_fOperand_S0$FULL_N;
// ports of submodule fpu_madd_fProd_S2
wire [105 : 0] fpu_madd_fProd_S2$D_IN, fpu_madd_fProd_S2$D_OUT;
wire fpu_madd_fProd_S2$CLR,
fpu_madd_fProd_S2$DEQ,
fpu_madd_fProd_S2$EMPTY_N,
fpu_madd_fProd_S2$ENQ,
fpu_madd_fProd_S2$FULL_N;
// ports of submodule fpu_madd_fProd_S3
wire [105 : 0] fpu_madd_fProd_S3$D_IN, fpu_madd_fProd_S3$D_OUT;
wire fpu_madd_fProd_S3$CLR,
fpu_madd_fProd_S3$DEQ,
fpu_madd_fProd_S3$EMPTY_N,
fpu_madd_fProd_S3$ENQ,
fpu_madd_fProd_S3$FULL_N;
// ports of submodule fpu_madd_fResult_S9
wire [68 : 0] fpu_madd_fResult_S9$D_IN, fpu_madd_fResult_S9$D_OUT;
wire fpu_madd_fResult_S9$CLR,
fpu_madd_fResult_S9$DEQ,
fpu_madd_fResult_S9$EMPTY_N,
fpu_madd_fResult_S9$ENQ,
fpu_madd_fResult_S9$FULL_N;
// ports of submodule fpu_madd_fState_S1
wire [257 : 0] fpu_madd_fState_S1$D_IN, fpu_madd_fState_S1$D_OUT;
wire fpu_madd_fState_S1$CLR,
fpu_madd_fState_S1$DEQ,
fpu_madd_fState_S1$EMPTY_N,
fpu_madd_fState_S1$ENQ,
fpu_madd_fState_S1$FULL_N;
// ports of submodule fpu_madd_fState_S2
wire [151 : 0] fpu_madd_fState_S2$D_IN, fpu_madd_fState_S2$D_OUT;
wire fpu_madd_fState_S2$CLR,
fpu_madd_fState_S2$DEQ,
fpu_madd_fState_S2$EMPTY_N,
fpu_madd_fState_S2$ENQ,
fpu_madd_fState_S2$FULL_N;
// ports of submodule fpu_madd_fState_S3
wire [151 : 0] fpu_madd_fState_S3$D_IN, fpu_madd_fState_S3$D_OUT;
wire fpu_madd_fState_S3$CLR,
fpu_madd_fState_S3$DEQ,
fpu_madd_fState_S3$EMPTY_N,
fpu_madd_fState_S3$ENQ,
fpu_madd_fState_S3$FULL_N;
// ports of submodule fpu_madd_fState_S4
wire [203 : 0] fpu_madd_fState_S4$D_IN, fpu_madd_fState_S4$D_OUT;
wire fpu_madd_fState_S4$CLR,
fpu_madd_fState_S4$DEQ,
fpu_madd_fState_S4$EMPTY_N,
fpu_madd_fState_S4$ENQ,
fpu_madd_fState_S4$FULL_N;
// ports of submodule fpu_madd_fState_S5
wire [215 : 0] fpu_madd_fState_S5$D_IN, fpu_madd_fState_S5$D_OUT;
wire fpu_madd_fState_S5$CLR,
fpu_madd_fState_S5$DEQ,
fpu_madd_fState_S5$EMPTY_N,
fpu_madd_fState_S5$ENQ,
fpu_madd_fState_S5$FULL_N;
// ports of submodule fpu_madd_fState_S6
wire [202 : 0] fpu_madd_fState_S6$D_IN, fpu_madd_fState_S6$D_OUT;
wire fpu_madd_fState_S6$CLR,
fpu_madd_fState_S6$DEQ,
fpu_madd_fState_S6$EMPTY_N,
fpu_madd_fState_S6$ENQ,
fpu_madd_fState_S6$FULL_N;
// ports of submodule fpu_madd_fState_S7
wire [202 : 0] fpu_madd_fState_S7$D_IN, fpu_madd_fState_S7$D_OUT;
wire fpu_madd_fState_S7$CLR,
fpu_madd_fState_S7$DEQ,
fpu_madd_fState_S7$EMPTY_N,
fpu_madd_fState_S7$ENQ,
fpu_madd_fState_S7$FULL_N;
// ports of submodule fpu_madd_fState_S8
wire [140 : 0] fpu_madd_fState_S8$D_IN, fpu_madd_fState_S8$D_OUT;
wire fpu_madd_fState_S8$CLR,
fpu_madd_fState_S8$DEQ,
fpu_madd_fState_S8$EMPTY_N,
fpu_madd_fState_S8$ENQ,
fpu_madd_fState_S8$FULL_N;
// ports of submodule fpu_sqr_fOperand_S0
wire [66 : 0] fpu_sqr_fOperand_S0$D_IN, fpu_sqr_fOperand_S0$D_OUT;
wire fpu_sqr_fOperand_S0$CLR,
fpu_sqr_fOperand_S0$DEQ,
fpu_sqr_fOperand_S0$EMPTY_N,
fpu_sqr_fOperand_S0$ENQ,
fpu_sqr_fOperand_S0$FULL_N;
// ports of submodule fpu_sqr_fResult_S5
wire [68 : 0] fpu_sqr_fResult_S5$D_IN, fpu_sqr_fResult_S5$D_OUT;
wire fpu_sqr_fResult_S5$CLR,
fpu_sqr_fResult_S5$DEQ,
fpu_sqr_fResult_S5$EMPTY_N,
fpu_sqr_fResult_S5$ENQ,
fpu_sqr_fResult_S5$FULL_N;
// ports of submodule fpu_sqr_fState_S1
wire [194 : 0] fpu_sqr_fState_S1$D_IN, fpu_sqr_fState_S1$D_OUT;
wire fpu_sqr_fState_S1$CLR,
fpu_sqr_fState_S1$DEQ,
fpu_sqr_fState_S1$EMPTY_N,
fpu_sqr_fState_S1$ENQ,
fpu_sqr_fState_S1$FULL_N;
// ports of submodule fpu_sqr_fState_S2
wire [136 : 0] fpu_sqr_fState_S2$D_IN, fpu_sqr_fState_S2$D_OUT;
wire fpu_sqr_fState_S2$CLR,
fpu_sqr_fState_S2$DEQ,
fpu_sqr_fState_S2$EMPTY_N,
fpu_sqr_fState_S2$ENQ,
fpu_sqr_fState_S2$FULL_N;
// ports of submodule fpu_sqr_fState_S3
wire [195 : 0] fpu_sqr_fState_S3$D_IN, fpu_sqr_fState_S3$D_OUT;
wire fpu_sqr_fState_S3$CLR,
fpu_sqr_fState_S3$DEQ,
fpu_sqr_fState_S3$EMPTY_N,
fpu_sqr_fState_S3$ENQ,
fpu_sqr_fState_S3$FULL_N;
// ports of submodule fpu_sqr_fState_S4
wire [138 : 0] fpu_sqr_fState_S4$D_IN, fpu_sqr_fState_S4$D_OUT;
wire fpu_sqr_fState_S4$CLR,
fpu_sqr_fState_S4$DEQ,
fpu_sqr_fState_S4$EMPTY_N,
fpu_sqr_fState_S4$ENQ,
fpu_sqr_fState_S4$FULL_N;
// ports of submodule iFifo
wire [201 : 0] iFifo$D_IN, iFifo$D_OUT;
wire iFifo$CLR, iFifo$DEQ, iFifo$EMPTY_N, iFifo$ENQ, iFifo$FULL_N;
// ports of submodule isDoubleFifo
wire isDoubleFifo$CLR,
isDoubleFifo$DEQ,
isDoubleFifo$D_IN,
isDoubleFifo$D_OUT,
isDoubleFifo$EMPTY_N,
isDoubleFifo$ENQ,
isDoubleFifo$FULL_N;
// ports of submodule isNegateFifo
wire isNegateFifo$CLR,
isNegateFifo$DEQ,
isNegateFifo$D_IN,
isNegateFifo$D_OUT,
isNegateFifo$EMPTY_N,
isNegateFifo$ENQ,
isNegateFifo$FULL_N;
// ports of submodule oFifo
wire [69 : 0] oFifo$D_IN, oFifo$D_OUT;
wire oFifo$CLR, oFifo$DEQ, oFifo$EMPTY_N, oFifo$ENQ, oFifo$FULL_N;
// ports of submodule resetReqsF
wire resetReqsF$CLR,
resetReqsF$DEQ,
resetReqsF$EMPTY_N,
resetReqsF$ENQ,
resetReqsF$FULL_N;
// ports of submodule resetRspsF
wire resetRspsF$CLR,
resetRspsF$DEQ,
resetRspsF$EMPTY_N,
resetRspsF$ENQ,
resetRspsF$FULL_N;
// ports of submodule rmdFifo
wire [2 : 0] rmdFifo$D_IN, rmdFifo$D_OUT;
wire rmdFifo$CLR, rmdFifo$DEQ, rmdFifo$EMPTY_N, rmdFifo$ENQ, rmdFifo$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_fpu_div_s1_stage,
CAN_FIRE_RL_fpu_div_s2_stage,
CAN_FIRE_RL_fpu_div_s3_stage,
CAN_FIRE_RL_fpu_div_s4_stage,
CAN_FIRE_RL_fpu_div_s5_stage,
CAN_FIRE_RL_fpu_madd_s1_stage,
CAN_FIRE_RL_fpu_madd_s2_stage,
CAN_FIRE_RL_fpu_madd_s3_stage,
CAN_FIRE_RL_fpu_madd_s4_stage,
CAN_FIRE_RL_fpu_madd_s5_stage,
CAN_FIRE_RL_fpu_madd_s6_stage,
CAN_FIRE_RL_fpu_madd_s7_stage,
CAN_FIRE_RL_fpu_madd_s8_stage,
CAN_FIRE_RL_fpu_madd_s9_stage,
CAN_FIRE_RL_fpu_sqr_s1_stage,
CAN_FIRE_RL_fpu_sqr_s2_stage,
CAN_FIRE_RL_fpu_sqr_s3_stage,
CAN_FIRE_RL_fpu_sqr_s4_stage,
CAN_FIRE_RL_fpu_sqr_s5_stage,
CAN_FIRE_RL_getResFromPipe,
CAN_FIRE_RL_getResFromPipe_1,
CAN_FIRE_RL_getResFromPipe_2,
CAN_FIRE_RL_passResult,
CAN_FIRE_RL_rl_reset,
CAN_FIRE_RL_start_op,
CAN_FIRE_RL_work,
CAN_FIRE_RL_work_1,
CAN_FIRE___me_check_22,
CAN_FIRE_server_core_request_put,
CAN_FIRE_server_core_response_get,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
WILL_FIRE_RL_fpu_div_s1_stage,
WILL_FIRE_RL_fpu_div_s2_stage,
WILL_FIRE_RL_fpu_div_s3_stage,
WILL_FIRE_RL_fpu_div_s4_stage,
WILL_FIRE_RL_fpu_div_s5_stage,
WILL_FIRE_RL_fpu_madd_s1_stage,
WILL_FIRE_RL_fpu_madd_s2_stage,
WILL_FIRE_RL_fpu_madd_s3_stage,
WILL_FIRE_RL_fpu_madd_s4_stage,
WILL_FIRE_RL_fpu_madd_s5_stage,
WILL_FIRE_RL_fpu_madd_s6_stage,
WILL_FIRE_RL_fpu_madd_s7_stage,
WILL_FIRE_RL_fpu_madd_s8_stage,
WILL_FIRE_RL_fpu_madd_s9_stage,
WILL_FIRE_RL_fpu_sqr_s1_stage,
WILL_FIRE_RL_fpu_sqr_s2_stage,
WILL_FIRE_RL_fpu_sqr_s3_stage,
WILL_FIRE_RL_fpu_sqr_s4_stage,
WILL_FIRE_RL_fpu_sqr_s5_stage,
WILL_FIRE_RL_getResFromPipe,
WILL_FIRE_RL_getResFromPipe_1,
WILL_FIRE_RL_getResFromPipe_2,
WILL_FIRE_RL_passResult,
WILL_FIRE_RL_rl_reset,
WILL_FIRE_RL_start_op,
WILL_FIRE_RL_work,
WILL_FIRE_RL_work_1,
WILL_FIRE___me_check_22,
WILL_FIRE_server_core_request_put,
WILL_FIRE_server_core_response_get,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get;
// inputs to muxes for submodule ports
wire [116 : 0] MUX_rg_res$write_1__VAL_2;
wire [115 : 0] MUX_rg_b$write_1__VAL_1,
MUX_rg_b$write_1__VAL_2,
MUX_rg_r$write_1__VAL_1,
MUX_rg_r$write_1__VAL_2,
MUX_rg_r_1$write_1__VAL_2,
MUX_rg_s$write_1__VAL_1,
MUX_rg_s$write_1__VAL_2;
wire [57 : 0] MUX_rg_d$write_1__VAL_1, MUX_rg_q$write_1__VAL_2;
wire [5 : 0] MUX_rg_index$write_1__VAL_2, MUX_rg_index_1$write_1__VAL_2;
wire MUX_crg_done$port1__write_1__SEL_1,
MUX_crg_done_1$port1__write_1__SEL_1,
MUX_crg_done_1$port1__write_1__SEL_2,
MUX_rg_index$write_1__SEL_1;
// remaining internal signals
reg [63 : 0] CASE_fpu_div_fState_S4D_OUT_BITS_68_TO_66_0_C_ETC__q173,
CASE_fpu_sqr_fState_S4D_OUT_BITS_68_TO_66_0_C_ETC__q183,
CASE_iFifoD_OUT_BITS_3_TO_0_0_460718241880001_ETC__q177,
CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176,
IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623;
reg [62 : 0] CASE_fpu_div_fState_S3D_OUT_BITS_124_TO_122_0_ETC__q175,
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0_0_0_ETC__q172,
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q171,
CASE_fpu_div_fState_S4D_OUT_BITS_68_TO_66_2_I_ETC__q169,
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130,
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131,
CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132,
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0_0_0_ETC__q182,
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q181,
CASE_fpu_sqr_fState_S4D_OUT_BITS_68_TO_66_2_I_ETC__q179;
reg [51 : 0] CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q1,
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q2,
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5,
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6,
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q3,
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q4,
CASE_guard03260_0b0_sfdin11482_BITS_56_TO_5_0b_ETC__q110,
CASE_guard03260_0b0_sfdin11482_BITS_56_TO_5_0b_ETC__q111,
CASE_guard12299_0b0_theResult___snd20235_BITS__ETC__q112,
CASE_guard12299_0b0_theResult___snd20235_BITS__ETC__q113,
CASE_guard32950_0b0_theResult___snd40862_BITS__ETC__q75,
CASE_guard32950_0b0_theResult___snd40862_BITS__ETC__q76,
CASE_guard42199_0b0_sfdin50421_BITS_56_TO_5_0b_ETC__q77,
CASE_guard42199_0b0_sfdin50421_BITS_56_TO_5_0b_ETC__q78,
CASE_guard51238_0b0_theResult___snd59174_BITS__ETC__q81,
CASE_guard51238_0b0_theResult___snd59174_BITS__ETC__q82,
CASE_guard55373_0b0_theResult___snd63285_BITS__ETC__q48,
CASE_guard55373_0b0_theResult___snd63285_BITS__ETC__q49,
CASE_guard64622_0b0_sfdin72844_BITS_56_TO_5_0b_ETC__q50,
CASE_guard64622_0b0_sfdin72844_BITS_56_TO_5_0b_ETC__q51,
CASE_guard73661_0b0_theResult___snd81597_BITS__ETC__q52,
CASE_guard73661_0b0_theResult___snd81597_BITS__ETC__q53,
CASE_guard94011_0b0_theResult___snd01923_BITS__ETC__q108,
CASE_guard94011_0b0_theResult___snd01923_BITS__ETC__q109,
_theResult___fst_sfd__h142620,
_theResult___fst_sfd__h148290,
_theResult___fst_sfd__h164058,
_theResult___fst_sfd__h173648,
_theResult___fst_sfd__h182400,
_theResult___fst_sfd__h18519,
_theResult___fst_sfd__h186930,
_theResult___fst_sfd__h19008,
_theResult___fst_sfd__h202696,
_theResult___fst_sfd__h212286,
_theResult___fst_sfd__h221038,
_theResult___fst_sfd__h225869,
_theResult___fst_sfd__h241635,
_theResult___fst_sfd__h251225,
_theResult___fst_sfd__h259977,
_theResult___fst_sfd__h42605,
_theResult___fst_sfd__h95988;
reg [22 : 0] CASE_guard69623_0b0_sfdin77716_BITS_56_TO_34_0_ETC__q162,
CASE_guard69623_0b0_sfdin77716_BITS_56_TO_34_0_ETC__q163,
CASE_guard78330_0b0_theResult___snd86329_BITS__ETC__q160,
CASE_guard78330_0b0_theResult___snd86329_BITS__ETC__q161,
CASE_guard87260_0b0_sfdin95482_BITS_56_TO_34_0_ETC__q164,
CASE_guard87260_0b0_sfdin95482_BITS_56_TO_34_0_ETC__q165,
CASE_guard96096_0b0_theResult___snd04119_BITS__ETC__q166,
CASE_guard96096_0b0_theResult___snd04119_BITS__ETC__q167,
_theResult___fst_sfd__h269596,
_theResult___fst_sfd__h278317,
_theResult___fst_sfd__h286899,
_theResult___fst_sfd__h296083,
_theResult___fst_sfd__h304719;
reg [10 : 0] CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q14,
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q15,
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31,
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32,
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q21,
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q22,
CASE_guard03260_0b0_theResult___fst_exp11488_0_ETC__q104,
CASE_guard03260_0b0_theResult___fst_exp11488_0_ETC__q105,
CASE_guard12299_0b0_theResult___fst_exp20289_0_ETC__q106,
CASE_guard12299_0b0_theResult___fst_exp20289_0_ETC__q107,
CASE_guard32950_0b0_theResult___fst_exp40911_0_ETC__q69,
CASE_guard32950_0b0_theResult___fst_exp40911_0_ETC__q70,
CASE_guard42199_0b0_theResult___fst_exp50427_0_ETC__q71,
CASE_guard42199_0b0_theResult___fst_exp50427_0_ETC__q72,
CASE_guard51238_0b0_theResult___fst_exp59228_0_ETC__q73,
CASE_guard51238_0b0_theResult___fst_exp59228_0_ETC__q74,
CASE_guard55373_0b0_theResult___fst_exp63334_0_ETC__q42,
CASE_guard55373_0b0_theResult___fst_exp63334_0_ETC__q43,
CASE_guard64622_0b0_theResult___fst_exp72850_0_ETC__q44,
CASE_guard64622_0b0_theResult___fst_exp72850_0_ETC__q45,
CASE_guard73661_0b0_theResult___fst_exp81651_0_ETC__q46,
CASE_guard73661_0b0_theResult___fst_exp81651_0_ETC__q47,
CASE_guard94011_0b0_theResult___fst_exp01972_0_ETC__q102,
CASE_guard94011_0b0_theResult___fst_exp01972_0_ETC__q103,
_theResult___fst_exp__h142619,
_theResult___fst_exp__h148289,
_theResult___fst_exp__h164057,
_theResult___fst_exp__h173647,
_theResult___fst_exp__h182399,
_theResult___fst_exp__h18518,
_theResult___fst_exp__h186929,
_theResult___fst_exp__h202695,
_theResult___fst_exp__h212285,
_theResult___fst_exp__h221037,
_theResult___fst_exp__h225868,
_theResult___fst_exp__h241634,
_theResult___fst_exp__h251224,
_theResult___fst_exp__h259976,
_theResult___fst_exp__h42604,
_theResult___fst_exp__h95987;
reg [7 : 0] CASE_guard69623_0b0_theResult___fst_exp77722_0_ETC__q154,
CASE_guard69623_0b0_theResult___fst_exp77722_0_ETC__q155,
CASE_guard78330_0b0_theResult___fst_exp86378_0_ETC__q152,
CASE_guard78330_0b0_theResult___fst_exp86378_0_ETC__q153,
CASE_guard87260_0b0_theResult___fst_exp95488_0_ETC__q156,
CASE_guard87260_0b0_theResult___fst_exp95488_0_ETC__q157,
CASE_guard96096_0b0_theResult___fst_exp04173_0_ETC__q158,
CASE_guard96096_0b0_theResult___fst_exp04173_0_ETC__q159,
_theResult___fst_exp__h269595,
_theResult___fst_exp__h278316,
_theResult___fst_exp__h286898,
_theResult___fst_exp__h296082,
_theResult___fst_exp__h304718;
reg CASE_fpu_div_fOperands_S0D_OUT_BITS_2_TO_0_0__ETC__q9,
CASE_fpu_div_fState_S3D_OUT_BITS_124_TO_122_0_ETC__q174,
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q170,
CASE_fpu_div_fState_S4D_OUT_BITS_68_TO_66_2_f_ETC__q168,
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126,
CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127,
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q180,
CASE_fpu_sqr_fState_S4D_OUT_BITS_68_TO_66_2_f_ETC__q178,
CASE_guard03260_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122,
CASE_guard03260_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116,
CASE_guard12299_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124,
CASE_guard12299_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118,
CASE_guard32950_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87,
CASE_guard32950_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q79,
CASE_guard42199_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89,
CASE_guard42199_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83,
CASE_guard51238_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91,
CASE_guard51238_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85,
CASE_guard55373_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54,
CASE_guard64622_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56,
CASE_guard69623_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145,
CASE_guard69623_0b0_resWirewget_BIT_68_0b1_re_ETC__q144,
CASE_guard73661_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58,
CASE_guard78330_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147,
CASE_guard78330_0b0_resWirewget_BIT_68_0b1_re_ETC__q146,
CASE_guard87260_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149,
CASE_guard87260_0b0_resWirewget_BIT_68_0b1_re_ETC__q148,
CASE_guard94011_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120,
CASE_guard94011_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114,
CASE_guard96096_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151,
CASE_guard96096_0b0_resWirewget_BIT_68_0b1_re_ETC__q150,
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03260_ETC__q117,
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03260_ETC__q123,
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12299_ETC__q119,
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12299_ETC__q125,
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32950_ETC__q80,
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32950_ETC__q88,
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42199_ETC__q84,
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42199_ETC__q90,
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51238_ETC__q86,
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51238_ETC__q92,
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55373_ETC__q55,
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64622_ETC__q57,
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73661_ETC__q59,
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94011_ETC__q115,
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94011_ETC__q121,
IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110,
IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320,
IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028,
IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582,
IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803,
IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348,
IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028,
IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400,
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823,
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324,
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388,
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409,
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023,
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373,
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397,
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418;
wire [194 : 0] IF_fpu_sqr_fOperand_S0_first__059_BITS_65_TO_5_ETC___d1212;
wire [139 : 0] IF_NOT_fpu_madd_fState_S4_first__547_BIT_130_5_ETC___d2595;
wire [118 : 0] IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1959;
wire [115 : 0] IF_IF_rg_index_1_87_ULE_58_91_THEN_NOT_rg_b_92_ETC___d1028,
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1002,
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1022,
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1026,
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1036,
IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22,
IF_rg_res_94_BIT_116_95_THEN_rg_res_94_BITS_11_ETC___d1025,
_theResult___fst__h43498,
_theResult___fst__h43537,
_theResult___fst__h43622,
_theResult___snd_fst__h43500,
_theResult___snd_fst__h43539,
_theResult___snd_fst__h43624,
_theResult___snd_snd__h43671,
_theResult___snd_snd__h43737,
_theResult___snd_snd_snd__h43503,
_theResult___snd_snd_snd__h43542,
_theResult___snd_snd_snd__h43627,
b___1__h77160,
b__h31634,
b__h43630,
b__h43734,
r__h43681,
r__h43685,
r__h43746,
r__h43775,
s__h43680,
s__h43745,
sum__h43628,
sum__h43732,
value__h31592,
x__h85931;
wire [113 : 0] x__h30477;
wire [105 : 0] IF_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S_ETC__q24,
_theResult___fst__h116827,
_theResult___snd__h130966,
_theResult___snd__h130980,
_theResult___snd__h130982,
_theResult___snd__h130994,
_theResult___snd__h131000,
_theResult___snd__h131018,
_theResult___snd__h131023,
fpu_madd_fProd_S3_first__009_SRL_IF_7170_MINUS_ETC___d2012,
sfdBC__h115662,
sfdin__h130943,
x__h116896;
wire [68 : 0] IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3081;
wire [63 : 0] IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1936,
IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1939,
IF_fpu_div_fOperands_S0_first__6_BITS_65_TO_55_ETC___d385,
IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1938,
IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5328,
IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5378,
IF_iFifo_first__087_BITS_167_TO_160_130_EQ_255_ETC___d3846,
IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4553,
IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4612,
IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330,
IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848,
IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4555,
IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618,
IF_isDoubleFifo_first__407_THEN_IF_isNegateFif_ETC___d6657,
NOT_fpu_div_fOperands_S0_first__6_BITS_129_TO__ETC___d382,
fpu_div_fState_S3_first__16_BIT_121_37_CONCAT__ETC___d866;
wire [62 : 0] IF_0b0_CONCAT_NOT_fpu_div_fState_S4_first__73__ETC___d910,
IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065,
IF_0b0_CONCAT_NOT_fpu_sqr_fState_S4_first__687_ETC___d1724,
IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2534,
IF_IF_fpu_div_fState_S3_first__16_BITS_120_TO__ETC___d859,
IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1931,
IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2952,
IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1932,
IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911,
IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2536,
IF_fpu_sqr_fState_S3_first__375_BIT_58_384_AND_ETC___d1678,
IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5327,
IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4552;
wire [58 : 0] IF_0_CONCAT_IF_fpu_sqr_fState_S3_first__375_BI_ETC__q19,
_theResult___snd__h94767,
_theResult___snd__h94782,
_theResult___snd__h94784,
_theResult___snd__h94797,
_theResult___snd__h94803,
_theResult___snd__h94821,
_theResult___snd__h94826,
result__h85925,
sfdin__h94744,
x__h86149;
wire [57 : 0] IF_0_CONCAT_IF_IF_fpu_div_fState_S3_first__16__ETC__q12,
IF_rg_index_ULE_57_THEN_rg_q_BITS_56_TO_0_CONC_ETC___d14,
IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_89_ETC__q10,
_theResult____h31574,
_theResult___snd__h33766,
_theResult___snd__h41401,
_theResult___snd__h41416,
_theResult___snd__h41418,
_theResult___snd__h41431,
_theResult___snd__h41437,
_theResult___snd__h41455,
_theResult___snd__h41460,
_theResult___snd_snd_snd__h33014,
result__h31668,
result__h31699,
result__h31874,
rg_q_PLUS_NEG_INV_rg_q_89_90___d491,
sfd___1__h60702,
sfd__h44951,
sfd__h44953,
sfdin__h33169,
sfdin__h41378,
x__h31813,
x__h32103,
x__h60693;
wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__ETC__q133,
IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q37,
IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q64,
IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q97,
IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget_ETC__q139,
IF_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__65_ETC__q29,
IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q100,
IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q93,
IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q33,
IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q40,
IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q60,
IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q67,
IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q135,
IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q142,
_0b0_CONCAT_NOT_iFifo_first__087_BITS_102_TO_95_ETC___d4813,
_0b0_CONCAT_NOT_iFifo_first__087_BITS_167_TO_16_ETC___d3330,
_0b0_CONCAT_NOT_iFifo_first__087_BITS_37_TO_30__ETC___d4038,
_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_TO_57_ETC___d6038,
_theResult____h164612,
_theResult____h203250,
_theResult____h242189,
_theResult____h269613,
_theResult____h287250,
_theResult___snd__h141392,
_theResult___snd__h141406,
_theResult___snd__h141408,
_theResult___snd__h141420,
_theResult___snd__h141426,
_theResult___snd__h141444,
_theResult___snd__h141449,
_theResult___snd__h163285,
_theResult___snd__h163287,
_theResult___snd__h163294,
_theResult___snd__h163300,
_theResult___snd__h163323,
_theResult___snd__h172861,
_theResult___snd__h172872,
_theResult___snd__h172874,
_theResult___snd__h172884,
_theResult___snd__h172890,
_theResult___snd__h172913,
_theResult___snd__h181597,
_theResult___snd__h181611,
_theResult___snd__h181617,
_theResult___snd__h181635,
_theResult___snd__h201923,
_theResult___snd__h201925,
_theResult___snd__h201932,
_theResult___snd__h201938,
_theResult___snd__h201961,
_theResult___snd__h211499,
_theResult___snd__h211510,
_theResult___snd__h211512,
_theResult___snd__h211522,
_theResult___snd__h211528,
_theResult___snd__h211551,
_theResult___snd__h220235,
_theResult___snd__h220249,
_theResult___snd__h220255,
_theResult___snd__h220273,
_theResult___snd__h240862,
_theResult___snd__h240864,
_theResult___snd__h240871,
_theResult___snd__h240877,
_theResult___snd__h240900,
_theResult___snd__h250438,
_theResult___snd__h250449,
_theResult___snd__h250451,
_theResult___snd__h250461,
_theResult___snd__h250467,
_theResult___snd__h250490,
_theResult___snd__h259174,
_theResult___snd__h259188,
_theResult___snd__h259194,
_theResult___snd__h259212,
_theResult___snd__h277733,
_theResult___snd__h277744,
_theResult___snd__h277746,
_theResult___snd__h277756,
_theResult___snd__h277762,
_theResult___snd__h277785,
_theResult___snd__h286329,
_theResult___snd__h286331,
_theResult___snd__h286338,
_theResult___snd__h286344,
_theResult___snd__h286367,
_theResult___snd__h295499,
_theResult___snd__h295510,
_theResult___snd__h295512,
_theResult___snd__h295522,
_theResult___snd__h295528,
_theResult___snd__h295551,
_theResult___snd__h304119,
_theResult___snd__h304133,
_theResult___snd__h304139,
_theResult___snd__h304157,
fpu_madd_fState_S5_first__601_BITS_56_TO_0_610_ETC___d2615,
guard__h132367,
result__h132372,
result__h165225,
result__h203863,
result__h242802,
result__h287863,
sfdA__h131577,
sfdBC__h131578,
sfd__h133119,
sfd__h144534,
sfd__h183174,
sfd__h222113,
sfd__h262011,
sfdin__h141369,
sfdin__h172844,
sfdin__h211482,
sfdin__h250421,
sfdin__h277716,
sfdin__h295482,
value__h31712,
x__h131940,
x__h131944,
x__h132359,
x__h132871,
x__h132880,
x__h165322,
x__h203960,
x__h242899,
x__h287960,
x__h30538;
wire [53 : 0] sfd__h142040,
sfd__h163352,
sfd__h172942,
sfd__h181670,
sfd__h201990,
sfd__h211580,
sfd__h220308,
sfd__h240929,
sfd__h250519,
sfd__h259247,
sfd__h42033,
sfd__h95416,
value__h270233,
value__h30480,
value__h53174;
wire [52 : 0] sfdA__h1086,
sfdA__h1090,
sfdB__h1087,
sfdB__h1092,
x__h114243,
x__h114255;
wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3813,
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3815,
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4519,
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4521,
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5294,
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5296,
IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5268,
IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5270,
IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5313,
IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5315,
IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3786,
IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3788,
IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3832,
IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3834,
IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4493,
IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4495,
IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4538,
IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4540,
IF_fpu_div_fOperands_S0_first__6_BITS_65_TO_55_ETC___d380,
_theResult___fst_sfd__h164061,
_theResult___fst_sfd__h173651,
_theResult___fst_sfd__h182403,
_theResult___fst_sfd__h182412,
_theResult___fst_sfd__h182418,
_theResult___fst_sfd__h202699,
_theResult___fst_sfd__h212289,
_theResult___fst_sfd__h221041,
_theResult___fst_sfd__h221050,
_theResult___fst_sfd__h221056,
_theResult___fst_sfd__h241638,
_theResult___fst_sfd__h251228,
_theResult___fst_sfd__h259980,
_theResult___fst_sfd__h259989,
_theResult___fst_sfd__h259995,
_theResult___fst_sfd__h42608,
_theResult___fst_sfd__h95991,
_theResult___fst_sfd__h96608,
_theResult___sfd__h142542,
_theResult___sfd__h163980,
_theResult___sfd__h173570,
_theResult___sfd__h182322,
_theResult___sfd__h202618,
_theResult___sfd__h212208,
_theResult___sfd__h220960,
_theResult___sfd__h241557,
_theResult___sfd__h251147,
_theResult___sfd__h259899,
_theResult___sfd__h42527,
_theResult___sfd__h95910,
_theResult___snd_fst_sfd__h144484,
_theResult___snd_fst_sfd__h164064,
_theResult___snd_fst_sfd__h182406,
_theResult___snd_fst_sfd__h183124,
_theResult___snd_fst_sfd__h202702,
_theResult___snd_fst_sfd__h221044,
_theResult___snd_fst_sfd__h222063,
_theResult___snd_fst_sfd__h241641,
_theResult___snd_fst_sfd__h259983,
_theResult___snd_fst_sfd__h30413,
out___1_sfd__h144233,
out___1_sfd__h182873,
out___1_sfd__h221812,
out_sfd__h142545,
out_sfd__h163983,
out_sfd__h173573,
out_sfd__h182325,
out_sfd__h202621,
out_sfd__h212211,
out_sfd__h220963,
out_sfd__h241560,
out_sfd__h251150,
out_sfd__h259902,
out_sfd__h42530,
out_sfd__h95913,
sfd__h17985,
sfd__h17988,
sfd__h45004,
sfd__h99402,
sfd__h99405,
sfd__h99408;
wire [24 : 0] sfd__h277814,
sfd__h286396,
sfd__h295580,
sfd__h304192,
value__h148921,
value__h187559,
value__h226498;
wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6576,
IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6578,
IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6622,
IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6624,
IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6595,
IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6597,
IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6641,
IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6643,
_theResult___fst_sfd__h278320,
_theResult___fst_sfd__h286902,
_theResult___fst_sfd__h296086,
_theResult___fst_sfd__h304722,
_theResult___fst_sfd__h304731,
_theResult___fst_sfd__h304737,
_theResult___sfd__h278239,
_theResult___sfd__h286821,
_theResult___sfd__h296005,
_theResult___sfd__h304641,
_theResult___snd_fst_sfd__h261961,
_theResult___snd_fst_sfd__h286905,
_theResult___snd_fst_sfd__h304725,
out_sfd__h278242,
out_sfd__h286824,
out_sfd__h296008,
out_sfd__h304644,
sfd__h304743;
wire [12 : 0] IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d282,
IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568,
IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563,
IF_fpu_sqr_fOperand_S0_first__059_BITS_65_TO_5_ETC___d1195,
_7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007,
value__h130883,
value__h141307,
value__h30425,
value__h30601,
x__h116929,
x__h132471,
x__h52551,
x__h52569;
wire [11 : 0] IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031,
IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2462,
IF_IF_fpu_div_fState_S3_first__16_BITS_120_TO__ETC___d573,
IF_IF_fpu_div_fState_S3_first__16_BITS_120_TO__ETC___d812,
IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5106,
IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3623,
IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4331,
IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668,
IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2903,
IF_fpu_sqr_fOperand_S0_first__059_BITS_65_TO_5_ETC__q17,
IF_fpu_sqr_fState_S3_first__375_BITS_121_TO_11_ETC___d1389,
IF_fpu_sqr_fState_S3_first__375_BITS_121_TO_11_ETC___d1632,
SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806,
SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96,
SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323,
SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36,
SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031,
SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63,
SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031,
SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138,
_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5531,
_3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809,
_3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326,
_3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034,
_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3188,
_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3908,
_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4683,
_3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034,
x__h165355,
x__h203993,
x__h242932,
x__h287993;
wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3729,
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3731,
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4436,
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4438,
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5211,
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5213,
IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5173,
IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5175,
IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5242,
IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5244,
IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3690,
IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3692,
IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3760,
IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3762,
IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4398,
IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4400,
IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4467,
IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4469,
IF_fpu_div_fOperands_S0_first__6_BITS_65_TO_55_ETC___d363,
IF_fpu_div_fState_S4_first__73_BITS_64_TO_54_7_ETC___d907,
IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d2986,
IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d3011,
IF_fpu_sqr_fState_S4_first__687_BITS_64_TO_54__ETC___d1721,
SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q99,
SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q39,
SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q66,
_theResult___exp__h142541,
_theResult___exp__h163979,
_theResult___exp__h173569,
_theResult___exp__h182321,
_theResult___exp__h202617,
_theResult___exp__h212207,
_theResult___exp__h220959,
_theResult___exp__h241556,
_theResult___exp__h251146,
_theResult___exp__h259898,
_theResult___exp__h42526,
_theResult___exp__h95909,
_theResult___fst__h30373,
_theResult___fst_exp__h130949,
_theResult___fst_exp__h130952,
_theResult___fst_exp__h130971,
_theResult___fst_exp__h130986,
_theResult___fst_exp__h131025,
_theResult___fst_exp__h131031,
_theResult___fst_exp__h131034,
_theResult___fst_exp__h141375,
_theResult___fst_exp__h141378,
_theResult___fst_exp__h141397,
_theResult___fst_exp__h141412,
_theResult___fst_exp__h141451,
_theResult___fst_exp__h141457,
_theResult___fst_exp__h141460,
_theResult___fst_exp__h163325,
_theResult___fst_exp__h163331,
_theResult___fst_exp__h163334,
_theResult___fst_exp__h164060,
_theResult___fst_exp__h172850,
_theResult___fst_exp__h172915,
_theResult___fst_exp__h172921,
_theResult___fst_exp__h172924,
_theResult___fst_exp__h173650,
_theResult___fst_exp__h181603,
_theResult___fst_exp__h181642,
_theResult___fst_exp__h181648,
_theResult___fst_exp__h181651,
_theResult___fst_exp__h182402,
_theResult___fst_exp__h182411,
_theResult___fst_exp__h182414,
_theResult___fst_exp__h201963,
_theResult___fst_exp__h201969,
_theResult___fst_exp__h201972,
_theResult___fst_exp__h202698,
_theResult___fst_exp__h211488,
_theResult___fst_exp__h211553,
_theResult___fst_exp__h211559,
_theResult___fst_exp__h211562,
_theResult___fst_exp__h212288,
_theResult___fst_exp__h220241,
_theResult___fst_exp__h220280,
_theResult___fst_exp__h220286,
_theResult___fst_exp__h220289,
_theResult___fst_exp__h221040,
_theResult___fst_exp__h221049,
_theResult___fst_exp__h221052,
_theResult___fst_exp__h240902,
_theResult___fst_exp__h240908,
_theResult___fst_exp__h240911,
_theResult___fst_exp__h241637,
_theResult___fst_exp__h250427,
_theResult___fst_exp__h250492,
_theResult___fst_exp__h250498,
_theResult___fst_exp__h250501,
_theResult___fst_exp__h251227,
_theResult___fst_exp__h259180,
_theResult___fst_exp__h259219,
_theResult___fst_exp__h259225,
_theResult___fst_exp__h259228,
_theResult___fst_exp__h259979,
_theResult___fst_exp__h259988,
_theResult___fst_exp__h259991,
_theResult___fst_exp__h41335,
_theResult___fst_exp__h41338,
_theResult___fst_exp__h41341,
_theResult___fst_exp__h41384,
_theResult___fst_exp__h41387,
_theResult___fst_exp__h41407,
_theResult___fst_exp__h41423,
_theResult___fst_exp__h41462,
_theResult___fst_exp__h41468,
_theResult___fst_exp__h41471,
_theResult___fst_exp__h42607,
_theResult___fst_exp__h94750,
_theResult___fst_exp__h94753,
_theResult___fst_exp__h94773,
_theResult___fst_exp__h94789,
_theResult___fst_exp__h94828,
_theResult___fst_exp__h94834,
_theResult___fst_exp__h94837,
_theResult___fst_exp__h95990,
_theResult___snd_fst_exp__h164063,
_theResult___snd_fst_exp__h182405,
_theResult___snd_fst_exp__h202701,
_theResult___snd_fst_exp__h221043,
_theResult___snd_fst_exp__h241640,
_theResult___snd_fst_exp__h259982,
_theResult___snd_fst_exp__h30385,
_theResult___snd_fst_exp__h30388,
_theResult___snd_fst_exp__h30412,
din_exp30866_MINUS_1023__q23,
din_exp__h130866,
din_inc___2_exp__h142626,
din_inc___2_exp__h182467,
din_inc___2_exp__h182502,
din_inc___2_exp__h182528,
din_inc___2_exp__h221105,
din_inc___2_exp__h221140,
din_inc___2_exp__h221166,
din_inc___2_exp__h260044,
din_inc___2_exp__h260079,
din_inc___2_exp__h260105,
din_inc___2_exp__h42617,
din_inc___2_exp__h96000,
fpu_div_fOperands_S0D_OUT_BITS_129_TO_119_MIN_ETC__q7,
fpu_div_fOperands_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q8,
fpu_madd_fOperand_S0D_OUT_BITS_129_TO_119_MIN_ETC__q128,
fpu_madd_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q129,
fpu_madd_fState_S4D_OUT_BITS_128_TO_118_MINUS_ETC__q26,
fpu_madd_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q27,
fpu_sqr_fOperand_S0D_OUT_BITS_65_TO_55_MINUS__ETC__q16,
fpu_sqr_fState_S3D_OUT_BITS_121_TO_111_MINUS__ETC__q18,
out_exp__h142544,
out_exp__h163982,
out_exp__h173572,
out_exp__h182324,
out_exp__h202620,
out_exp__h212210,
out_exp__h220962,
out_exp__h241559,
out_exp__h251149,
out_exp__h259901,
out_exp__h42529,
out_exp__h95912,
resWirewget_BITS_67_TO_57_MINUS_1023__q137,
theResult___fst_exp1341_MINUS_1023__q11,
value41307_BITS_10_TO_0_MINUS_1023__q28,
x__h30592,
x__h31820,
x__h96539;
wire [8 : 0] IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6332;
wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6448,
IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6450,
IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6518,
IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6520,
IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6479,
IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6481,
IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6549,
IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6551,
SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q141,
_theResult___exp__h278238,
_theResult___exp__h286820,
_theResult___exp__h296004,
_theResult___exp__h304640,
_theResult___fst_exp__h277722,
_theResult___fst_exp__h277787,
_theResult___fst_exp__h277793,
_theResult___fst_exp__h277796,
_theResult___fst_exp__h278319,
_theResult___fst_exp__h286369,
_theResult___fst_exp__h286375,
_theResult___fst_exp__h286378,
_theResult___fst_exp__h286901,
_theResult___fst_exp__h295488,
_theResult___fst_exp__h295553,
_theResult___fst_exp__h295559,
_theResult___fst_exp__h295562,
_theResult___fst_exp__h296085,
_theResult___fst_exp__h304125,
_theResult___fst_exp__h304164,
_theResult___fst_exp__h304170,
_theResult___fst_exp__h304173,
_theResult___fst_exp__h304721,
_theResult___fst_exp__h304730,
_theResult___fst_exp__h304733,
_theResult___snd_fst_exp__h286904,
_theResult___snd_fst_exp__h304724,
din_inc___2_exp__h304759,
din_inc___2_exp__h304785,
din_inc___2_exp__h304820,
din_inc___2_exp__h304846,
exp__h304742,
iFifoD_OUT_BITS_102_TO_95_MINUS_127__q95,
iFifoD_OUT_BITS_167_TO_160_MINUS_127__q35,
iFifoD_OUT_BITS_37_TO_30_MINUS_127__q62,
out_exp__h278241,
out_exp__h286823,
out_exp__h296007,
out_exp__h304643;
wire [6 : 0] IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460,
IF_fpu_sqr_fState_S1_first__216_BIT_57_226_THE_ETC___d1342,
x__h85465;
wire [5 : 0] IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767,
IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055,
IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572,
IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280,
IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278,
IF_IF_fpu_div_fState_S3_first__16_BITS_120_TO__ETC___d810,
IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901,
IF_fpu_sqr_fOperand_S0_first__059_BITS_65_TO_5_ETC___d1193,
IF_fpu_sqr_fState_S3_first__375_BIT_58_384_THE_ETC___d1630,
IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757,
IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271,
IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982,
IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982,
b__h10508,
b__h3090,
x__h60732;
wire [4 : 0] IF_IF_fpu_div_fState_S3_first__16_BITS_120_TO__ETC___d856,
IF_fpu_div_fState_S3_first__16_BITS_120_TO_110_ETC___d851,
IF_fpu_madd_fState_S3_first__995_BIT_151_996_T_ETC___d2525,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705,
_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688,
fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501,
fpu_madd_fState_S7_first__651_BITS_137_TO_133__ETC___d2942,
fpu_madd_fState_S8_first__960_BITS_75_TO_71_03_ETC___d3043,
resWire_wget__410_BITS_4_TO_0_658_OR_NOT_resWi_ETC___d6768;
wire [2 : 0] IF_fpu_sqr_fState_S3_first__375_BIT_195_376_TH_ETC___d1671,
NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2523;
wire [1 : 0] IF_sfdin11482_BIT_4_THEN_2_ELSE_0__q98,
IF_sfdin1378_BIT_5_THEN_2_ELSE_0__q13,
IF_sfdin30943_BIT_53_THEN_2_ELSE_0__q25,
IF_sfdin41369_BIT_4_THEN_2_ELSE_0__q30,
IF_sfdin4744_BIT_6_THEN_2_ELSE_0__q20,
IF_sfdin50421_BIT_4_THEN_2_ELSE_0__q65,
IF_sfdin72844_BIT_4_THEN_2_ELSE_0__q38,
IF_sfdin77716_BIT_33_THEN_2_ELSE_0__q134,
IF_sfdin95482_BIT_33_THEN_2_ELSE_0__q140,
IF_theResult___snd01923_BIT_4_THEN_2_ELSE_0__q94,
IF_theResult___snd04119_BIT_33_THEN_2_ELSE_0__q143,
IF_theResult___snd20235_BIT_4_THEN_2_ELSE_0__q101,
IF_theResult___snd40862_BIT_4_THEN_2_ELSE_0__q61,
IF_theResult___snd59174_BIT_4_THEN_2_ELSE_0__q68,
IF_theResult___snd63285_BIT_4_THEN_2_ELSE_0__q34,
IF_theResult___snd81597_BIT_4_THEN_2_ELSE_0__q41,
IF_theResult___snd86329_BIT_33_THEN_2_ELSE_0__q136,
_theResult___snd_fst__h131051,
_theResult___snd_fst__h141477,
_theResult___snd_fst__h41490,
_theResult___snd_fst__h94856,
_theResult___snd_snd__h131371,
_theResult___snd_snd_snd__h131369,
guardBC__h115666,
guard__h133123,
guard__h155373,
guard__h164622,
guard__h173661,
guard__h194011,
guard__h203260,
guard__h212299,
guard__h232950,
guard__h242199,
guard__h251238,
guard__h269623,
guard__h278330,
guard__h287260,
guard__h296096,
guard__h32997,
guard__h86435,
x__h131406,
x__h141760,
x__h41756,
x__h95138;
wire IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6025,
IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6399,
IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d3317,
IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4027,
IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4581,
IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4802,
IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d5347,
IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1922,
IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2503,
IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2506,
IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5146,
IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5374,
IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3663,
IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4371,
IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4608,
IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6375,
IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6420,
IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6734,
IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6747,
IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6760,
IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d283,
IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d285,
IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d429,
IF_fpu_div_fOperands_S0_first__6_BITS_65_TO_55_ETC___d352,
IF_fpu_div_fState_S3_first__16_BITS_120_TO_110_ETC___d527,
IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1861,
IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1927,
IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1947,
IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2516,
IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2521,
IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3060,
IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5148,
IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5376,
IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3665,
IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4373,
IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4610,
IF_isNegateFifo_first__409_THEN_IF_resWire_wge_ETC___d6424,
IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6377,
IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6422,
IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6709,
IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6720,
IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6736,
IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6749,
IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6762,
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1038,
IF_rg_index_1_87_ULE_58_91_THEN_NOT_rg_b_92_EQ_ETC___d1009,
IF_rg_index_1_87_ULE_58_91_THEN_rg_b_92_EQ_0_9_ETC___d997,
NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6728,
NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6756,
NOT_IF_fpu_madd_fOperand_S0_first__803_BIT_195_ETC___d1946,
NOT_fpu_div_fOperands_S0_first__6_BITS_129_TO__ETC___d330,
NOT_fpu_div_fOperands_S0_first__6_BITS_65_TO_5_ETC___d411,
NOT_fpu_div_fOperands_S0_first__6_BITS_65_TO_5_ETC___d418,
NOT_fpu_madd_fOperand_S0_first__803_BITS_129_T_ETC___d1923,
NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854,
NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2510,
NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584,
NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244,
NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955,
NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730,
NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927,
SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807,
SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808,
SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324,
SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325,
SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032,
SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033,
SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032,
SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d5769,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d3574,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d4282,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d5057,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6280,
_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S3_f_ETC___d2463,
_0_CONCAT_IF_IF_fpu_div_fState_S3_first__16_BIT_ETC___d813,
_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__651_B_ETC___d2904,
_0_CONCAT_IF_fpu_sqr_fState_S3_first__375_BIT_5_ETC___d1633,
_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d4759,
_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d5107,
_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3273,
_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3624,
_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d3984,
_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d4332,
_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d5984,
_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6333,
_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532,
_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533,
_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6691,
_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6716,
_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6743,
_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189,
_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190,
_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909,
_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910,
_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684,
_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685,
_7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2008,
fpu_div_fOperands_S0_first__6_BITS_129_TO_119__ETC___d293,
fpu_div_fOperands_S0_first__6_BITS_129_TO_119__ETC___d331,
fpu_div_fOperands_S0_first__6_BITS_129_TO_119__ETC___d366,
fpu_div_fOperands_S0_first__6_BITS_129_TO_119__ETC___d428,
fpu_div_fOperands_S0_first__6_BITS_65_TO_55_6__ETC___d289,
fpu_div_fOperands_S0_first__6_BIT_130_33_EQ_fp_ETC___d335,
fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1857,
fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1926,
fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855,
fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002,
fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004,
guard__h165220,
guard__h203858,
guard__h242797,
guard__h287858,
rg_index_1_87_PLUS_1_89_ULE_58___d990,
rg_index_1_87_ULE_58___d991,
rg_index_PLUS_1_ULE_57___d6,
rg_index_ULE_57___d7,
rg_s_014_ULT_rg_r_1_013_PLUS_rg_b_92_015___d1016,
sfdlsb__h116825,
sfdlsb__h31694,
value_BIT_52___h53270;
// action method server_core_request_put
assign RDY_server_core_request_put = iFifo$FULL_N ;
assign CAN_FIRE_server_core_request_put = iFifo$FULL_N ;
assign WILL_FIRE_server_core_request_put = EN_server_core_request_put ;
// actionvalue method server_core_response_get
assign server_core_response_get = oFifo$D_OUT ;
assign RDY_server_core_response_get = oFifo$EMPTY_N ;
assign CAN_FIRE_server_core_response_get = oFifo$EMPTY_N ;
assign WILL_FIRE_server_core_response_get = EN_server_core_response_get ;
// action method server_reset_request_put
assign RDY_server_reset_request_put = resetReqsF$FULL_N ;
assign CAN_FIRE_server_reset_request_put = resetReqsF$FULL_N ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get = resetRspsF$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get = resetRspsF$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// submodule fpu_div_fOperands_S0
FIFOL1 #(.width(32'd131)) fpu_div_fOperands_S0(.RST(RST_N),
.CLK(CLK),
.D_IN(fpu_div_fOperands_S0$D_IN),
.ENQ(fpu_div_fOperands_S0$ENQ),
.DEQ(fpu_div_fOperands_S0$DEQ),
.CLR(fpu_div_fOperands_S0$CLR),
.D_OUT(fpu_div_fOperands_S0$D_OUT),
.FULL_N(fpu_div_fOperands_S0$FULL_N),
.EMPTY_N(fpu_div_fOperands_S0$EMPTY_N));
// submodule fpu_div_fResult_S5
FIFOL1 #(.width(32'd69)) fpu_div_fResult_S5(.RST(RST_N),
.CLK(CLK),
.D_IN(fpu_div_fResult_S5$D_IN),
.ENQ(fpu_div_fResult_S5$ENQ),
.DEQ(fpu_div_fResult_S5$DEQ),
.CLR(fpu_div_fResult_S5$CLR),
.D_OUT(fpu_div_fResult_S5$D_OUT),
.FULL_N(fpu_div_fResult_S5$FULL_N),
.EMPTY_N(fpu_div_fResult_S5$EMPTY_N));
// submodule fpu_div_fState_S1
FIFOL1 #(.width(32'd319)) fpu_div_fState_S1(.RST(RST_N),
.CLK(CLK),
.D_IN(fpu_div_fState_S1$D_IN),
.ENQ(fpu_div_fState_S1$ENQ),
.DEQ(fpu_div_fState_S1$DEQ),
.CLR(fpu_div_fState_S1$CLR),
.D_OUT(fpu_div_fState_S1$D_OUT),
.FULL_N(fpu_div_fState_S1$FULL_N),
.EMPTY_N(fpu_div_fState_S1$EMPTY_N));
// submodule fpu_div_fState_S2
FIFOL1 #(.width(32'd148)) fpu_div_fState_S2(.RST(RST_N),
.CLK(CLK),
.D_IN(fpu_div_fState_S2$D_IN),
.ENQ(fpu_div_fState_S2$ENQ),
.DEQ(fpu_div_fState_S2$DEQ),
.CLR(fpu_div_fState_S2$CLR),
.D_OUT(fpu_div_fState_S2$D_OUT),
.FULL_N(fpu_div_fState_S2$FULL_N),
.EMPTY_N(fpu_div_fState_S2$EMPTY_N));
// submodule fpu_div_fState_S3
FIFOL1 #(.width(32'd195)) fpu_div_fState_S3(.RST(RST_N),
.CLK(CLK),
.D_IN(fpu_div_fState_S3$D_IN),
.ENQ(fpu_div_fState_S3$ENQ),
.DEQ(fpu_div_fState_S3$DEQ),
.CLR(fpu_div_fState_S3$CLR),
.D_OUT(fpu_div_fState_S3$D_OUT),
.FULL_N(fpu_div_fState_S3$FULL_N),
.EMPTY_N(fpu_div_fState_S3$EMPTY_N));
// submodule fpu_div_fState_S4
FIFOL1 #(.width(32'd139)) fpu_div_fState_S4(.RST(RST_N),
.CLK(CLK),
.D_IN(fpu_div_fState_S4$D_IN),
.ENQ(fpu_div_fState_S4$ENQ),
.DEQ(fpu_div_fState_S4$DEQ),
.CLR(fpu_div_fState_S4$CLR),
.D_OUT(fpu_div_fState_S4$D_OUT),
.FULL_N(fpu_div_fState_S4$FULL_N),
.EMPTY_N(fpu_div_fState_S4$EMPTY_N));
// submodule fpu_madd_fOperand_S0
FIFOL1 #(.width(32'd196)) fpu_madd_fOperand_S0(.RST(RST_N),
.CLK(CLK),
.D_IN(fpu_madd_fOperand_S0$D_IN),
.ENQ(fpu_madd_fOperand_S0$ENQ),
.DEQ(fpu_madd_fOperand_S0$DEQ),
.CLR(fpu_madd_fOperand_S0$CLR),
.D_OUT(fpu_madd_fOperand_S0$D_OUT),
.FULL_N(fpu_madd_fOperand_S0$FULL_N),
.EMPTY_N(fpu_madd_fOperand_S0$EMPTY_N));
// submodule fpu_madd_fProd_S2
FIFOL1 #(.width(32'd106)) fpu_madd_fProd_S2(.RST(RST_N),
.CLK(CLK),
.D_IN(fpu_madd_fProd_S2$D_IN),
.ENQ(fpu_madd_fProd_S2$ENQ),
.DEQ(fpu_madd_fProd_S2$DEQ),
.CLR(fpu_madd_fProd_S2$CLR),
.D_OUT(fpu_madd_fProd_S2$D_OUT),
.FULL_N(fpu_madd_fProd_S2$FULL_N),
.EMPTY_N(fpu_madd_fProd_S2$EMPTY_N));
// submodule fpu_madd_fProd_S3
FIFOL1 #(.width(32'd106)) fpu_madd_fProd_S3(.RST(RST_N),
.CLK(CLK),
.D_IN(fpu_madd_fProd_S3$D_IN),
.ENQ(fpu_madd_fProd_S3$ENQ),
.DEQ(fpu_madd_fProd_S3$DEQ),
.CLR(fpu_madd_fProd_S3$CLR),
.D_OUT(fpu_madd_fProd_S3$D_OUT),
.FULL_N(fpu_madd_fProd_S3$FULL_N),
.EMPTY_N(fpu_madd_fProd_S3$EMPTY_N));
// submodule fpu_madd_fResult_S9
FIFOL1 #(.width(32'd69)) fpu_madd_fResult_S9(.RST(RST_N),
.CLK(CLK),
.D_IN(fpu_madd_fResult_S9$D_IN),
.ENQ(fpu_madd_fResult_S9$ENQ),
.DEQ(fpu_madd_fResult_S9$DEQ),
.CLR(fpu_madd_fResult_S9$CLR),
.D_OUT(fpu_madd_fResult_S9$D_OUT),
.FULL_N(fpu_madd_fResult_S9$FULL_N),
.EMPTY_N(fpu_madd_fResult_S9$EMPTY_N));
// submodule fpu_madd_fState_S1
FIFOL1 #(.width(32'd258)) fpu_madd_fState_S1(.RST(RST_N),
.CLK(CLK),
.D_IN(fpu_madd_fState_S1$D_IN),
.ENQ(fpu_madd_fState_S1$ENQ),
.DEQ(fpu_madd_fState_S1$DEQ),
.CLR(fpu_madd_fState_S1$CLR),
.D_OUT(fpu_madd_fState_S1$D_OUT),
.FULL_N(fpu_madd_fState_S1$FULL_N),
.EMPTY_N(fpu_madd_fState_S1$EMPTY_N));
// submodule fpu_madd_fState_S2
FIFOL1 #(.width(32'd152)) fpu_madd_fState_S2(.RST(RST_N),
.CLK(CLK),
.D_IN(fpu_madd_fState_S2$D_IN),
.ENQ(fpu_madd_fState_S2$ENQ),
.DEQ(fpu_madd_fState_S2$DEQ),
.CLR(fpu_madd_fState_S2$CLR),
.D_OUT(fpu_madd_fState_S2$D_OUT),
.FULL_N(fpu_madd_fState_S2$FULL_N),
.EMPTY_N(fpu_madd_fState_S2$EMPTY_N));
// submodule fpu_madd_fState_S3
FIFOL1 #(.width(32'd152)) fpu_madd_fState_S3(.RST(RST_N),
.CLK(CLK),
.D_IN(fpu_madd_fState_S3$D_IN),
.ENQ(fpu_madd_fState_S3$ENQ),
.DEQ(fpu_madd_fState_S3$DEQ),
.CLR(fpu_madd_fState_S3$CLR),
.D_OUT(fpu_madd_fState_S3$D_OUT),
.FULL_N(fpu_madd_fState_S3$FULL_N),
.EMPTY_N(fpu_madd_fState_S3$EMPTY_N));
// submodule fpu_madd_fState_S4
FIFOL1 #(.width(32'd204)) fpu_madd_fState_S4(.RST(RST_N),
.CLK(CLK),
.D_IN(fpu_madd_fState_S4$D_IN),
.ENQ(fpu_madd_fState_S4$ENQ),
.DEQ(fpu_madd_fState_S4$DEQ),
.CLR(fpu_madd_fState_S4$CLR),
.D_OUT(fpu_madd_fState_S4$D_OUT),
.FULL_N(fpu_madd_fState_S4$FULL_N),
.EMPTY_N(fpu_madd_fState_S4$EMPTY_N));
// submodule fpu_madd_fState_S5
FIFOL1 #(.width(32'd216)) fpu_madd_fState_S5(.RST(RST_N),
.CLK(CLK),
.D_IN(fpu_madd_fState_S5$D_IN),
.ENQ(fpu_madd_fState_S5$ENQ),
.DEQ(fpu_madd_fState_S5$DEQ),
.CLR(fpu_madd_fState_S5$CLR),
.D_OUT(fpu_madd_fState_S5$D_OUT),
.FULL_N(fpu_madd_fState_S5$FULL_N),
.EMPTY_N(fpu_madd_fState_S5$EMPTY_N));
// submodule fpu_madd_fState_S6
FIFOL1 #(.width(32'd203)) fpu_madd_fState_S6(.RST(RST_N),
.CLK(CLK),
.D_IN(fpu_madd_fState_S6$D_IN),
.ENQ(fpu_madd_fState_S6$ENQ),
.DEQ(fpu_madd_fState_S6$DEQ),
.CLR(fpu_madd_fState_S6$CLR),
.D_OUT(fpu_madd_fState_S6$D_OUT),
.FULL_N(fpu_madd_fState_S6$FULL_N),
.EMPTY_N(fpu_madd_fState_S6$EMPTY_N));
// submodule fpu_madd_fState_S7
FIFOL1 #(.width(32'd203)) fpu_madd_fState_S7(.RST(RST_N),
.CLK(CLK),
.D_IN(fpu_madd_fState_S7$D_IN),
.ENQ(fpu_madd_fState_S7$ENQ),
.DEQ(fpu_madd_fState_S7$DEQ),
.CLR(fpu_madd_fState_S7$CLR),
.D_OUT(fpu_madd_fState_S7$D_OUT),
.FULL_N(fpu_madd_fState_S7$FULL_N),
.EMPTY_N(fpu_madd_fState_S7$EMPTY_N));
// submodule fpu_madd_fState_S8
FIFOL1 #(.width(32'd141)) fpu_madd_fState_S8(.RST(RST_N),
.CLK(CLK),
.D_IN(fpu_madd_fState_S8$D_IN),
.ENQ(fpu_madd_fState_S8$ENQ),
.DEQ(fpu_madd_fState_S8$DEQ),
.CLR(fpu_madd_fState_S8$CLR),
.D_OUT(fpu_madd_fState_S8$D_OUT),
.FULL_N(fpu_madd_fState_S8$FULL_N),
.EMPTY_N(fpu_madd_fState_S8$EMPTY_N));
// submodule fpu_sqr_fOperand_S0
FIFOL1 #(.width(32'd67)) fpu_sqr_fOperand_S0(.RST(RST_N),
.CLK(CLK),
.D_IN(fpu_sqr_fOperand_S0$D_IN),
.ENQ(fpu_sqr_fOperand_S0$ENQ),
.DEQ(fpu_sqr_fOperand_S0$DEQ),
.CLR(fpu_sqr_fOperand_S0$CLR),
.D_OUT(fpu_sqr_fOperand_S0$D_OUT),
.FULL_N(fpu_sqr_fOperand_S0$FULL_N),
.EMPTY_N(fpu_sqr_fOperand_S0$EMPTY_N));
// submodule fpu_sqr_fResult_S5
FIFOL1 #(.width(32'd69)) fpu_sqr_fResult_S5(.RST(RST_N),
.CLK(CLK),
.D_IN(fpu_sqr_fResult_S5$D_IN),
.ENQ(fpu_sqr_fResult_S5$ENQ),
.DEQ(fpu_sqr_fResult_S5$DEQ),
.CLR(fpu_sqr_fResult_S5$CLR),
.D_OUT(fpu_sqr_fResult_S5$D_OUT),
.FULL_N(fpu_sqr_fResult_S5$FULL_N),
.EMPTY_N(fpu_sqr_fResult_S5$EMPTY_N));
// submodule fpu_sqr_fState_S1
FIFOL1 #(.width(32'd195)) fpu_sqr_fState_S1(.RST(RST_N),
.CLK(CLK),
.D_IN(fpu_sqr_fState_S1$D_IN),
.ENQ(fpu_sqr_fState_S1$ENQ),
.DEQ(fpu_sqr_fState_S1$DEQ),
.CLR(fpu_sqr_fState_S1$CLR),
.D_OUT(fpu_sqr_fState_S1$D_OUT),
.FULL_N(fpu_sqr_fState_S1$FULL_N),
.EMPTY_N(fpu_sqr_fState_S1$EMPTY_N));
// submodule fpu_sqr_fState_S2
FIFOL1 #(.width(32'd137)) fpu_sqr_fState_S2(.RST(RST_N),
.CLK(CLK),
.D_IN(fpu_sqr_fState_S2$D_IN),
.ENQ(fpu_sqr_fState_S2$ENQ),
.DEQ(fpu_sqr_fState_S2$DEQ),
.CLR(fpu_sqr_fState_S2$CLR),
.D_OUT(fpu_sqr_fState_S2$D_OUT),
.FULL_N(fpu_sqr_fState_S2$FULL_N),
.EMPTY_N(fpu_sqr_fState_S2$EMPTY_N));
// submodule fpu_sqr_fState_S3
FIFOL1 #(.width(32'd196)) fpu_sqr_fState_S3(.RST(RST_N),
.CLK(CLK),
.D_IN(fpu_sqr_fState_S3$D_IN),
.ENQ(fpu_sqr_fState_S3$ENQ),
.DEQ(fpu_sqr_fState_S3$DEQ),
.CLR(fpu_sqr_fState_S3$CLR),
.D_OUT(fpu_sqr_fState_S3$D_OUT),
.FULL_N(fpu_sqr_fState_S3$FULL_N),
.EMPTY_N(fpu_sqr_fState_S3$EMPTY_N));
// submodule fpu_sqr_fState_S4
FIFOL1 #(.width(32'd139)) fpu_sqr_fState_S4(.RST(RST_N),
.CLK(CLK),
.D_IN(fpu_sqr_fState_S4$D_IN),
.ENQ(fpu_sqr_fState_S4$ENQ),
.DEQ(fpu_sqr_fState_S4$DEQ),
.CLR(fpu_sqr_fState_S4$CLR),
.D_OUT(fpu_sqr_fState_S4$D_OUT),
.FULL_N(fpu_sqr_fState_S4$FULL_N),
.EMPTY_N(fpu_sqr_fState_S4$EMPTY_N));
// submodule iFifo
FIFO2 #(.width(32'd202), .guarded(32'd1)) iFifo(.RST(RST_N),
.CLK(CLK),
.D_IN(iFifo$D_IN),
.ENQ(iFifo$ENQ),
.DEQ(iFifo$DEQ),
.CLR(iFifo$CLR),
.D_OUT(iFifo$D_OUT),
.FULL_N(iFifo$FULL_N),
.EMPTY_N(iFifo$EMPTY_N));
// submodule isDoubleFifo
FIFO2 #(.width(32'd1), .guarded(32'd1)) isDoubleFifo(.RST(RST_N),
.CLK(CLK),
.D_IN(isDoubleFifo$D_IN),
.ENQ(isDoubleFifo$ENQ),
.DEQ(isDoubleFifo$DEQ),
.CLR(isDoubleFifo$CLR),
.D_OUT(isDoubleFifo$D_OUT),
.FULL_N(isDoubleFifo$FULL_N),
.EMPTY_N(isDoubleFifo$EMPTY_N));
// submodule isNegateFifo
FIFO2 #(.width(32'd1), .guarded(32'd1)) isNegateFifo(.RST(RST_N),
.CLK(CLK),
.D_IN(isNegateFifo$D_IN),
.ENQ(isNegateFifo$ENQ),
.DEQ(isNegateFifo$DEQ),
.CLR(isNegateFifo$CLR),
.D_OUT(isNegateFifo$D_OUT),
.FULL_N(isNegateFifo$FULL_N),
.EMPTY_N(isNegateFifo$EMPTY_N));
// submodule oFifo
FIFO2 #(.width(32'd70), .guarded(32'd1)) oFifo(.RST(RST_N),
.CLK(CLK),
.D_IN(oFifo$D_IN),
.ENQ(oFifo$ENQ),
.DEQ(oFifo$DEQ),
.CLR(oFifo$CLR),
.D_OUT(oFifo$D_OUT),
.FULL_N(oFifo$FULL_N),
.EMPTY_N(oFifo$EMPTY_N));
// submodule resetReqsF
FIFO20 #(.guarded(32'd1)) resetReqsF(.RST(RST_N),
.CLK(CLK),
.ENQ(resetReqsF$ENQ),
.DEQ(resetReqsF$DEQ),
.CLR(resetReqsF$CLR),
.FULL_N(resetReqsF$FULL_N),
.EMPTY_N(resetReqsF$EMPTY_N));
// submodule resetRspsF
FIFO20 #(.guarded(32'd1)) resetRspsF(.RST(RST_N),
.CLK(CLK),
.ENQ(resetRspsF$ENQ),
.DEQ(resetRspsF$DEQ),
.CLR(resetRspsF$CLR),
.FULL_N(resetRspsF$FULL_N),
.EMPTY_N(resetRspsF$EMPTY_N));
// submodule rmdFifo
FIFO2 #(.width(32'd3), .guarded(32'd1)) rmdFifo(.RST(RST_N),
.CLK(CLK),
.D_IN(rmdFifo$D_IN),
.ENQ(rmdFifo$ENQ),
.DEQ(rmdFifo$DEQ),
.CLR(rmdFifo$CLR),
.D_OUT(rmdFifo$D_OUT),
.FULL_N(rmdFifo$FULL_N),
.EMPTY_N(rmdFifo$EMPTY_N));
// rule RL_getResFromPipe
assign CAN_FIRE_RL_getResFromPipe = fpu_madd_fResult_S9$EMPTY_N ;
assign WILL_FIRE_RL_getResFromPipe = fpu_madd_fResult_S9$EMPTY_N ;
// rule RL_getResFromPipe_1
assign CAN_FIRE_RL_getResFromPipe_1 = fpu_div_fResult_S5$EMPTY_N ;
assign WILL_FIRE_RL_getResFromPipe_1 = fpu_div_fResult_S5$EMPTY_N ;
// rule RL_getResFromPipe_2
assign CAN_FIRE_RL_getResFromPipe_2 = fpu_sqr_fResult_S5$EMPTY_N ;
assign WILL_FIRE_RL_getResFromPipe_2 = fpu_sqr_fResult_S5$EMPTY_N ;
// rule __me_check_22
assign CAN_FIRE___me_check_22 = 1'b1 ;
assign WILL_FIRE___me_check_22 = 1'b1 ;
// rule RL_passResult
assign CAN_FIRE_RL_passResult =
isDoubleFifo$EMPTY_N && isNegateFifo$EMPTY_N &&
rmdFifo$EMPTY_N &&
oFifo$FULL_N &&
resWire$whas ;
assign WILL_FIRE_RL_passResult = CAN_FIRE_RL_passResult ;
// rule RL_fpu_div_s5_stage
assign CAN_FIRE_RL_fpu_div_s5_stage =
fpu_div_fState_S4$EMPTY_N && fpu_div_fResult_S5$FULL_N ;
assign WILL_FIRE_RL_fpu_div_s5_stage = CAN_FIRE_RL_fpu_div_s5_stage ;
// rule RL_fpu_div_s4_stage
assign CAN_FIRE_RL_fpu_div_s4_stage =
fpu_div_fState_S3$EMPTY_N && fpu_div_fState_S4$FULL_N ;
assign WILL_FIRE_RL_fpu_div_s4_stage = CAN_FIRE_RL_fpu_div_s4_stage ;
// rule RL_fpu_div_s3_stage
assign CAN_FIRE_RL_fpu_div_s3_stage =
fpu_div_fState_S2$EMPTY_N && fpu_div_fState_S3$FULL_N &&
(fpu_div_fState_S2$D_OUT[147] || crg_done) ;
assign WILL_FIRE_RL_fpu_div_s3_stage = CAN_FIRE_RL_fpu_div_s3_stage ;
// rule RL_work
assign CAN_FIRE_RL_work = rg_busy ;
assign WILL_FIRE_RL_work = rg_busy ;
// rule RL_fpu_div_s2_stage
assign CAN_FIRE_RL_fpu_div_s2_stage =
fpu_div_fState_S1$EMPTY_N && fpu_div_fState_S2$FULL_N &&
(fpu_div_fState_S1$D_OUT[318] || !rg_busy) ;
assign WILL_FIRE_RL_fpu_div_s2_stage =
CAN_FIRE_RL_fpu_div_s2_stage && !rg_busy ;
// rule RL_fpu_div_s1_stage
assign CAN_FIRE_RL_fpu_div_s1_stage =
fpu_div_fOperands_S0$EMPTY_N && fpu_div_fState_S1$FULL_N ;
assign WILL_FIRE_RL_fpu_div_s1_stage = CAN_FIRE_RL_fpu_div_s1_stage ;
// rule RL_fpu_sqr_s5_stage
assign CAN_FIRE_RL_fpu_sqr_s5_stage =
fpu_sqr_fState_S4$EMPTY_N && fpu_sqr_fResult_S5$FULL_N ;
assign WILL_FIRE_RL_fpu_sqr_s5_stage = CAN_FIRE_RL_fpu_sqr_s5_stage ;
// rule RL_fpu_sqr_s4_stage
assign CAN_FIRE_RL_fpu_sqr_s4_stage =
fpu_sqr_fState_S3$EMPTY_N && fpu_sqr_fState_S4$FULL_N ;
assign WILL_FIRE_RL_fpu_sqr_s4_stage = CAN_FIRE_RL_fpu_sqr_s4_stage ;
// rule RL_fpu_sqr_s3_stage
assign CAN_FIRE_RL_fpu_sqr_s3_stage =
fpu_sqr_fState_S2$EMPTY_N && fpu_sqr_fState_S3$FULL_N &&
(fpu_sqr_fState_S2$D_OUT[136] || crg_done_1) ;
assign WILL_FIRE_RL_fpu_sqr_s3_stage = CAN_FIRE_RL_fpu_sqr_s3_stage ;
// rule RL_work_1
assign CAN_FIRE_RL_work_1 = rg_busy_1 ;
assign WILL_FIRE_RL_work_1 = rg_busy_1 ;
// rule RL_fpu_sqr_s2_stage
assign CAN_FIRE_RL_fpu_sqr_s2_stage =
fpu_sqr_fState_S1$EMPTY_N && fpu_sqr_fState_S2$FULL_N &&
(fpu_sqr_fState_S1$D_OUT[194] || !rg_busy_1) ;
assign WILL_FIRE_RL_fpu_sqr_s2_stage =
CAN_FIRE_RL_fpu_sqr_s2_stage && !rg_busy_1 ;
// rule RL_fpu_sqr_s1_stage
assign CAN_FIRE_RL_fpu_sqr_s1_stage =
fpu_sqr_fOperand_S0$EMPTY_N && fpu_sqr_fState_S1$FULL_N ;
assign WILL_FIRE_RL_fpu_sqr_s1_stage = CAN_FIRE_RL_fpu_sqr_s1_stage ;
// rule RL_fpu_madd_s9_stage
assign CAN_FIRE_RL_fpu_madd_s9_stage =
fpu_madd_fState_S8$EMPTY_N && fpu_madd_fResult_S9$FULL_N ;
assign WILL_FIRE_RL_fpu_madd_s9_stage = CAN_FIRE_RL_fpu_madd_s9_stage ;
// rule RL_fpu_madd_s8_stage
assign CAN_FIRE_RL_fpu_madd_s8_stage =
fpu_madd_fState_S7$EMPTY_N && fpu_madd_fState_S8$FULL_N ;
assign WILL_FIRE_RL_fpu_madd_s8_stage = CAN_FIRE_RL_fpu_madd_s8_stage ;
// rule RL_fpu_madd_s7_stage
assign CAN_FIRE_RL_fpu_madd_s7_stage =
fpu_madd_fState_S6$EMPTY_N && fpu_madd_fState_S7$FULL_N ;
assign WILL_FIRE_RL_fpu_madd_s7_stage = CAN_FIRE_RL_fpu_madd_s7_stage ;
// rule RL_fpu_madd_s6_stage
assign CAN_FIRE_RL_fpu_madd_s6_stage =
fpu_madd_fState_S5$EMPTY_N && fpu_madd_fState_S6$FULL_N ;
assign WILL_FIRE_RL_fpu_madd_s6_stage = CAN_FIRE_RL_fpu_madd_s6_stage ;
// rule RL_fpu_madd_s5_stage
assign CAN_FIRE_RL_fpu_madd_s5_stage =
fpu_madd_fState_S4$EMPTY_N && fpu_madd_fState_S5$FULL_N ;
assign WILL_FIRE_RL_fpu_madd_s5_stage = CAN_FIRE_RL_fpu_madd_s5_stage ;
// rule RL_fpu_madd_s4_stage
assign CAN_FIRE_RL_fpu_madd_s4_stage =
fpu_madd_fState_S3$EMPTY_N && fpu_madd_fProd_S3$EMPTY_N &&
fpu_madd_fState_S4$FULL_N ;
assign WILL_FIRE_RL_fpu_madd_s4_stage = CAN_FIRE_RL_fpu_madd_s4_stage ;
// rule RL_fpu_madd_s3_stage
assign CAN_FIRE_RL_fpu_madd_s3_stage =
fpu_madd_fState_S2$EMPTY_N && fpu_madd_fProd_S2$EMPTY_N &&
fpu_madd_fProd_S3$FULL_N &&
fpu_madd_fState_S3$FULL_N ;
assign WILL_FIRE_RL_fpu_madd_s3_stage = CAN_FIRE_RL_fpu_madd_s3_stage ;
// rule RL_fpu_madd_s2_stage
assign CAN_FIRE_RL_fpu_madd_s2_stage =
fpu_madd_fState_S1$EMPTY_N && fpu_madd_fProd_S2$FULL_N &&
fpu_madd_fState_S2$FULL_N ;
assign WILL_FIRE_RL_fpu_madd_s2_stage = CAN_FIRE_RL_fpu_madd_s2_stage ;
// rule RL_fpu_madd_s1_stage
assign CAN_FIRE_RL_fpu_madd_s1_stage =
fpu_madd_fOperand_S0$EMPTY_N && fpu_madd_fState_S1$FULL_N ;
assign WILL_FIRE_RL_fpu_madd_s1_stage = CAN_FIRE_RL_fpu_madd_s1_stage ;
// rule RL_start_op
assign CAN_FIRE_RL_start_op =
iFifo$EMPTY_N && isDoubleFifo$FULL_N && isNegateFifo$FULL_N &&
rmdFifo$FULL_N &&
IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 ;
assign WILL_FIRE_RL_start_op = CAN_FIRE_RL_start_op ;
// rule RL_rl_reset
assign CAN_FIRE_RL_rl_reset = resetReqsF$EMPTY_N && resetRspsF$FULL_N ;
assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ;
// inputs to muxes for submodule ports
assign MUX_crg_done$port1__write_1__SEL_1 = rg_busy && rg_index == 6'd28 ;
assign MUX_crg_done_1$port1__write_1__SEL_1 =
rg_busy_1 && rg_index_1 == 6'd29 ;
assign MUX_crg_done_1$port1__write_1__SEL_2 =
WILL_FIRE_RL_fpu_sqr_s2_stage && !fpu_sqr_fState_S1$D_OUT[194] ;
assign MUX_rg_index$write_1__SEL_1 =
WILL_FIRE_RL_fpu_div_s2_stage && !fpu_div_fState_S1$D_OUT[318] ;
assign MUX_rg_b$write_1__VAL_1 =
fpu_sqr_fState_S1$D_OUT[57] ?
116'h40000000000000000000000000000 :
b___1__h77160 ;
assign MUX_rg_b$write_1__VAL_2 =
rg_index_1_87_PLUS_1_89_ULE_58___d990 ?
_theResult___fst__h43498 :
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1002 ;
assign MUX_rg_d$write_1__VAL_1 = { 1'd0, fpu_div_fState_S1$D_OUT[67:11] } ;
assign MUX_rg_index$write_1__VAL_2 = rg_index + 6'd1 ;
assign MUX_rg_index_1$write_1__VAL_2 = rg_index_1 + 6'd1 ;
assign MUX_rg_q$write_1__VAL_2 =
rg_index_PLUS_1_ULE_57___d6 ?
{ IF_rg_index_ULE_57_THEN_rg_q_BITS_56_TO_0_CONC_ETC___d14[56:0],
!IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22[115] } :
IF_rg_index_ULE_57_THEN_rg_q_BITS_56_TO_0_CONC_ETC___d14 ;
assign MUX_rg_r$write_1__VAL_1 = { 2'd0, fpu_div_fState_S1$D_OUT[181:68] } ;
assign MUX_rg_r$write_1__VAL_2 =
rg_index_PLUS_1_ULE_57___d6 ?
(IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22[115] ?
{ IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22[114:0],
1'd0 } +
b__h31634 :
{ IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22[114:0],
1'd0 } -
b__h31634) :
IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22 ;
assign MUX_rg_r_1$write_1__VAL_2 =
rg_index_1_87_PLUS_1_89_ULE_58___d990 ?
_theResult___snd_snd_snd__h43503 :
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1022 ;
assign MUX_rg_res$write_1__VAL_2 =
{ rg_index_1_87_PLUS_1_89_ULE_58___d990 ?
IF_rg_index_1_87_ULE_58_91_THEN_rg_b_92_EQ_0_9_ETC___d997 ||
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1002 ==
116'd0 :
IF_rg_index_1_87_ULE_58_91_THEN_rg_b_92_EQ_0_9_ETC___d997,
rg_index_1_87_PLUS_1_89_ULE_58___d990 ?
IF_IF_rg_index_1_87_ULE_58_91_THEN_NOT_rg_b_92_ETC___d1028 :
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1026 } ;
assign MUX_rg_s$write_1__VAL_1 = { fpu_sqr_fState_S1$D_OUT[57:0], 58'd0 } ;
assign MUX_rg_s$write_1__VAL_2 =
rg_index_1_87_PLUS_1_89_ULE_58___d990 ?
_theResult___snd_fst__h43500 :
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1036 ;
// inlined wires
always@(fpu_madd_fResult_S9$EMPTY_N or
fpu_madd_fResult_S9$D_OUT or
fpu_div_fResult_S5$EMPTY_N or
fpu_div_fResult_S5$D_OUT or
fpu_sqr_fResult_S5$EMPTY_N or fpu_sqr_fResult_S5$D_OUT)
begin
case (1'b1) // synopsys parallel_case
fpu_madd_fResult_S9$EMPTY_N: resWire$wget = fpu_madd_fResult_S9$D_OUT;
fpu_div_fResult_S5$EMPTY_N: resWire$wget = fpu_div_fResult_S5$D_OUT;
fpu_sqr_fResult_S5$EMPTY_N: resWire$wget = fpu_sqr_fResult_S5$D_OUT;
default: resWire$wget = 69'h0AAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign resWire$whas =
fpu_madd_fResult_S9$EMPTY_N || fpu_div_fResult_S5$EMPTY_N ||
fpu_sqr_fResult_S5$EMPTY_N ;
assign crg_done$EN_port0__write =
WILL_FIRE_RL_fpu_div_s3_stage && !fpu_div_fState_S2$D_OUT[147] ;
assign crg_done$port1__read = !crg_done$EN_port0__write && crg_done ;
assign crg_done$EN_port1__write =
rg_busy && rg_index == 6'd28 ||
WILL_FIRE_RL_fpu_div_s2_stage && !fpu_div_fState_S1$D_OUT[318] ;
assign crg_done$port2__read =
crg_done$EN_port1__write ?
MUX_crg_done$port1__write_1__SEL_1 :
crg_done$port1__read ;
assign crg_done_1$EN_port0__write =
WILL_FIRE_RL_fpu_sqr_s3_stage && !fpu_sqr_fState_S2$D_OUT[136] ;
assign crg_done_1$port1__read = !crg_done_1$EN_port0__write && crg_done_1 ;
assign crg_done_1$EN_port1__write =
rg_busy_1 && rg_index_1 == 6'd29 ||
WILL_FIRE_RL_fpu_sqr_s2_stage && !fpu_sqr_fState_S1$D_OUT[194] ;
assign crg_done_1$port2__read =
crg_done_1$EN_port1__write ?
MUX_crg_done_1$port1__write_1__SEL_1 :
crg_done_1$port1__read ;
// register crg_done
assign crg_done$D_IN = crg_done$port2__read ;
assign crg_done$EN = 1'b1 ;
// register crg_done_1
assign crg_done_1$D_IN = crg_done_1$port2__read ;
assign crg_done_1$EN = 1'b1 ;
// register rg_b
assign rg_b$D_IN =
MUX_crg_done_1$port1__write_1__SEL_2 ?
MUX_rg_b$write_1__VAL_1 :
MUX_rg_b$write_1__VAL_2 ;
assign rg_b$EN =
WILL_FIRE_RL_fpu_sqr_s2_stage && !fpu_sqr_fState_S1$D_OUT[194] ||
rg_busy_1 ;
// register rg_busy
assign rg_busy$D_IN = !MUX_crg_done$port1__write_1__SEL_1 ;
assign rg_busy$EN =
rg_busy && rg_index == 6'd28 ||
WILL_FIRE_RL_fpu_div_s2_stage && !fpu_div_fState_S1$D_OUT[318] ;
// register rg_busy_1
assign rg_busy_1$D_IN = !MUX_crg_done_1$port1__write_1__SEL_1 ;
assign rg_busy_1$EN =
rg_busy_1 && rg_index_1 == 6'd29 ||
WILL_FIRE_RL_fpu_sqr_s2_stage && !fpu_sqr_fState_S1$D_OUT[194] ;
// register rg_d
assign rg_d$D_IN =
MUX_rg_index$write_1__SEL_1 ? MUX_rg_d$write_1__VAL_1 : rg_d ;
assign rg_d$EN =
WILL_FIRE_RL_fpu_div_s2_stage && !fpu_div_fState_S1$D_OUT[318] ||
rg_busy ;
// register rg_index
assign rg_index$D_IN =
MUX_rg_index$write_1__SEL_1 ?
6'd0 :
MUX_rg_index$write_1__VAL_2 ;
assign rg_index$EN =
WILL_FIRE_RL_fpu_div_s2_stage && !fpu_div_fState_S1$D_OUT[318] ||
rg_busy ;
// register rg_index_1
assign rg_index_1$D_IN =
MUX_crg_done_1$port1__write_1__SEL_2 ?
6'd0 :
MUX_rg_index_1$write_1__VAL_2 ;
assign rg_index_1$EN =
WILL_FIRE_RL_fpu_sqr_s2_stage && !fpu_sqr_fState_S1$D_OUT[194] ||
rg_busy_1 ;
// register rg_q
assign rg_q$D_IN =
MUX_rg_index$write_1__SEL_1 ? 58'd0 : MUX_rg_q$write_1__VAL_2 ;
assign rg_q$EN =
WILL_FIRE_RL_fpu_div_s2_stage && !fpu_div_fState_S1$D_OUT[318] ||
rg_busy ;
// register rg_r
assign rg_r$D_IN =
MUX_rg_index$write_1__SEL_1 ?
MUX_rg_r$write_1__VAL_1 :
MUX_rg_r$write_1__VAL_2 ;
assign rg_r$EN =
WILL_FIRE_RL_fpu_div_s2_stage && !fpu_div_fState_S1$D_OUT[318] ||
rg_busy ;
// register rg_r_1
assign rg_r_1$D_IN =
MUX_crg_done_1$port1__write_1__SEL_2 ?
116'd0 :
MUX_rg_r_1$write_1__VAL_2 ;
assign rg_r_1$EN =
WILL_FIRE_RL_fpu_sqr_s2_stage && !fpu_sqr_fState_S1$D_OUT[194] ||
rg_busy_1 ;
// register rg_res
assign rg_res$D_IN =
MUX_crg_done_1$port1__write_1__SEL_2 ?
117'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAA :
MUX_rg_res$write_1__VAL_2 ;
assign rg_res$EN =
WILL_FIRE_RL_fpu_sqr_s2_stage && !fpu_sqr_fState_S1$D_OUT[194] ||
rg_busy_1 ;
// register rg_s
assign rg_s$D_IN =
MUX_crg_done_1$port1__write_1__SEL_2 ?
MUX_rg_s$write_1__VAL_1 :
MUX_rg_s$write_1__VAL_2 ;
assign rg_s$EN =
WILL_FIRE_RL_fpu_sqr_s2_stage && !fpu_sqr_fState_S1$D_OUT[194] ||
rg_busy_1 ;
// submodule fpu_div_fOperands_S0
assign fpu_div_fOperands_S0$D_IN =
{ IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848,
IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330,
iFifo$D_OUT[6:4] } ;
assign fpu_div_fOperands_S0$ENQ =
WILL_FIRE_RL_start_op && iFifo$D_OUT[3:0] == 4'd3 ;
assign fpu_div_fOperands_S0$DEQ = CAN_FIRE_RL_fpu_div_s1_stage ;
assign fpu_div_fOperands_S0$CLR = 1'b0 ;
// submodule fpu_div_fResult_S5
assign fpu_div_fResult_S5$D_IN =
fpu_div_fState_S4$D_OUT[138] ?
fpu_div_fState_S4$D_OUT[137:69] :
{ (fpu_div_fState_S4$D_OUT[64:54] == 11'd2047) ?
fpu_div_fState_S4$D_OUT[65:2] :
CASE_fpu_div_fState_S4D_OUT_BITS_68_TO_66_0_C_ETC__q173,
fpu_div_fState_S4$D_OUT[73:69] |
{ 2'd0,
_theResult___fst_exp__h42607 == 11'd2047 &&
_theResult___fst_sfd__h42608 == 52'd0,
1'd0,
fpu_div_fState_S4$D_OUT[64:54] != 11'd2047 &&
fpu_div_fState_S4$D_OUT[1:0] != 2'b0 } } ;
assign fpu_div_fResult_S5$ENQ = CAN_FIRE_RL_fpu_div_s5_stage ;
assign fpu_div_fResult_S5$DEQ = fpu_div_fResult_S5$EMPTY_N ;
assign fpu_div_fResult_S5$CLR = 1'b0 ;
// submodule fpu_div_fState_S1
assign fpu_div_fState_S1$D_IN =
{ fpu_div_fOperands_S0_first__6_BITS_129_TO_119__ETC___d293,
(fpu_div_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
fpu_div_fOperands_S0$D_OUT[118:67] != 52'd0 &&
!fpu_div_fOperands_S0$D_OUT[118]) ?
{ fpu_div_fOperands_S0$D_OUT[130:119], sfd__h17985 } :
IF_fpu_div_fOperands_S0_first__6_BITS_65_TO_55_ETC___d385,
fpu_div_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
fpu_div_fOperands_S0$D_OUT[118:67] != 52'd0 &&
!fpu_div_fOperands_S0$D_OUT[118] ||
fpu_div_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
fpu_div_fOperands_S0$D_OUT[54:3] != 52'd0 &&
!fpu_div_fOperands_S0$D_OUT[54] ||
(fpu_div_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
!fpu_div_fOperands_S0$D_OUT[118]) &&
(fpu_div_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
!fpu_div_fOperands_S0$D_OUT[54]) &&
fpu_div_fOperands_S0_first__6_BITS_129_TO_119__ETC___d366,
(fpu_div_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
fpu_div_fOperands_S0$D_OUT[118:67] == 52'd0 ||
fpu_div_fOperands_S0$D_OUT[118]) &&
(fpu_div_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
!fpu_div_fOperands_S0$D_OUT[118]) &&
NOT_fpu_div_fOperands_S0_first__6_BITS_129_TO__ETC___d330 &&
fpu_div_fOperands_S0$D_OUT[65:55] == 11'd0 &&
fpu_div_fOperands_S0$D_OUT[54:3] == 52'd0 &&
(fpu_div_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
fpu_div_fOperands_S0$D_OUT[118:67] != 52'd0),
(fpu_div_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
fpu_div_fOperands_S0$D_OUT[118:67] == 52'd0 ||
fpu_div_fOperands_S0$D_OUT[118]) &&
(fpu_div_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
fpu_div_fOperands_S0$D_OUT[54:3] == 52'd0 ||
fpu_div_fOperands_S0$D_OUT[54]) &&
(fpu_div_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
!fpu_div_fOperands_S0$D_OUT[118]) &&
(fpu_div_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
!fpu_div_fOperands_S0$D_OUT[54]) &&
(fpu_div_fOperands_S0$D_OUT[65:55] != 11'd0 ||
fpu_div_fOperands_S0$D_OUT[54:3] != 52'd0) &&
(fpu_div_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
fpu_div_fOperands_S0$D_OUT[118:67] != 52'd0) &&
(fpu_div_fOperands_S0$D_OUT[129:119] != 11'd0 ||
fpu_div_fOperands_S0$D_OUT[118:67] != 52'd0) &&
(fpu_div_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
fpu_div_fOperands_S0$D_OUT[54:3] != 52'd0) &&
!IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d283,
(fpu_div_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
fpu_div_fOperands_S0$D_OUT[118:67] == 52'd0 ||
fpu_div_fOperands_S0$D_OUT[118]) &&
(fpu_div_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
fpu_div_fOperands_S0$D_OUT[54:3] == 52'd0 ||
fpu_div_fOperands_S0$D_OUT[54]) &&
(fpu_div_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
!fpu_div_fOperands_S0$D_OUT[118]) &&
(fpu_div_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
!fpu_div_fOperands_S0$D_OUT[54]) &&
NOT_fpu_div_fOperands_S0_first__6_BITS_65_TO_5_ETC___d411,
(fpu_div_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
fpu_div_fOperands_S0$D_OUT[118:67] == 52'd0 ||
fpu_div_fOperands_S0$D_OUT[118]) &&
(fpu_div_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
fpu_div_fOperands_S0$D_OUT[54:3] == 52'd0 ||
fpu_div_fOperands_S0$D_OUT[54]) &&
(fpu_div_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
!fpu_div_fOperands_S0$D_OUT[118]) &&
(fpu_div_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
!fpu_div_fOperands_S0$D_OUT[54]) &&
NOT_fpu_div_fOperands_S0_first__6_BITS_65_TO_5_ETC___d418,
fpu_div_fOperands_S0$D_OUT[2:0],
!fpu_div_fOperands_S0_first__6_BIT_130_33_EQ_fp_ETC___d335,
_theResult___snd_fst_exp__h30412,
_theResult___snd_fst_sfd__h30413,
x__h30477,
x__h30538,
x__h30592 } ;
assign fpu_div_fState_S1$ENQ = CAN_FIRE_RL_fpu_div_s1_stage ;
assign fpu_div_fState_S1$DEQ = WILL_FIRE_RL_fpu_div_s2_stage ;
assign fpu_div_fState_S1$CLR = 1'b0 ;
// submodule fpu_div_fState_S2
assign fpu_div_fState_S2$D_IN =
{ fpu_div_fState_S1$D_OUT[318:182],
fpu_div_fState_S1$D_OUT[10:0] } ;
assign fpu_div_fState_S2$ENQ = WILL_FIRE_RL_fpu_div_s2_stage ;
assign fpu_div_fState_S2$DEQ = CAN_FIRE_RL_fpu_div_s3_stage ;
assign fpu_div_fState_S2$CLR = 1'b0 ;
// submodule fpu_div_fState_S3
assign fpu_div_fState_S3$D_IN =
{ fpu_div_fState_S2$D_OUT[147:11], x__h32103 } ;
assign fpu_div_fState_S3$ENQ = CAN_FIRE_RL_fpu_div_s3_stage ;
assign fpu_div_fState_S3$DEQ = CAN_FIRE_RL_fpu_div_s4_stage ;
assign fpu_div_fState_S3$CLR = 1'b0 ;
// submodule fpu_div_fState_S4
assign fpu_div_fState_S4$D_IN =
{ (fpu_div_fState_S3$D_OUT[120:110] == 11'd2047) ?
fpu_div_fState_S3$D_OUT[57:56] != 2'b0 ||
fpu_div_fState_S3$D_OUT[194] :
fpu_div_fState_S3$D_OUT[194],
(fpu_div_fState_S3$D_OUT[120:110] == 11'd2047) ?
((fpu_div_fState_S3$D_OUT[57:56] == 2'b0) ?
fpu_div_fState_S3$D_OUT[193:130] :
{ CASE_fpu_div_fState_S3D_OUT_BITS_124_TO_122_0_ETC__q174,
CASE_fpu_div_fState_S3D_OUT_BITS_124_TO_122_0_ETC__q175 }) :
fpu_div_fState_S3$D_OUT[193:130],
IF_IF_fpu_div_fState_S3_first__16_BITS_120_TO__ETC___d856,
fpu_div_fState_S3$D_OUT[124:122],
fpu_div_fState_S3_first__16_BIT_121_37_CONCAT__ETC___d866,
x__h41756 } ;
assign fpu_div_fState_S4$ENQ = CAN_FIRE_RL_fpu_div_s4_stage ;
assign fpu_div_fState_S4$DEQ = CAN_FIRE_RL_fpu_div_s5_stage ;
assign fpu_div_fState_S4$CLR = 1'b0 ;
// submodule fpu_madd_fOperand_S0
assign fpu_madd_fOperand_S0$D_IN =
{ iFifo$D_OUT[3:0] != 4'd2,
IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623,
CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176,
CASE_iFifoD_OUT_BITS_3_TO_0_0_460718241880001_ETC__q177,
iFifo$D_OUT[6:4] } ;
assign fpu_madd_fOperand_S0$ENQ =
WILL_FIRE_RL_start_op &&
(iFifo$D_OUT[3:0] == 4'd0 || iFifo$D_OUT[3:0] == 4'd1 ||
iFifo$D_OUT[3:0] == 4'd2 ||
iFifo$D_OUT[3:0] == 4'd5 ||
iFifo$D_OUT[3:0] == 4'd6 ||
iFifo$D_OUT[3:0] == 4'd7 ||
iFifo$D_OUT[3:0] == 4'd8) ;
assign fpu_madd_fOperand_S0$DEQ = CAN_FIRE_RL_fpu_madd_s1_stage ;
assign fpu_madd_fOperand_S0$CLR = 1'b0 ;
// submodule fpu_madd_fProd_S2
assign fpu_madd_fProd_S2$D_IN =
fpu_madd_fState_S1$D_OUT[105:53] *
fpu_madd_fState_S1$D_OUT[52:0] ;
assign fpu_madd_fProd_S2$ENQ = CAN_FIRE_RL_fpu_madd_s2_stage ;
assign fpu_madd_fProd_S2$DEQ = CAN_FIRE_RL_fpu_madd_s3_stage ;
assign fpu_madd_fProd_S2$CLR = 1'b0 ;
// submodule fpu_madd_fProd_S3
assign fpu_madd_fProd_S3$D_IN = fpu_madd_fProd_S2$D_OUT ;
assign fpu_madd_fProd_S3$ENQ = CAN_FIRE_RL_fpu_madd_s3_stage ;
assign fpu_madd_fProd_S3$DEQ = CAN_FIRE_RL_fpu_madd_s4_stage ;
assign fpu_madd_fProd_S3$CLR = 1'b0 ;
// submodule fpu_madd_fResult_S9
assign fpu_madd_fResult_S9$D_IN =
fpu_madd_fState_S8$D_OUT[140] ?
fpu_madd_fState_S8$D_OUT[139:71] :
IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3081 ;
assign fpu_madd_fResult_S9$ENQ = CAN_FIRE_RL_fpu_madd_s9_stage ;
assign fpu_madd_fResult_S9$DEQ = fpu_madd_fResult_S9$EMPTY_N ;
assign fpu_madd_fResult_S9$CLR = 1'b0 ;
// submodule fpu_madd_fState_S1
assign fpu_madd_fState_S1$D_IN =
{ x__h96539 == 11'd2047 &&
_theResult___fst_sfd__h96608 != 52'd0 &&
!_theResult___fst_sfd__h96608[51] ||
fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 &&
!fpu_madd_fOperand_S0$D_OUT[118] ||
fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0 &&
!fpu_madd_fOperand_S0$D_OUT[54] ||
IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1861,
IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1939,
IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1947,
4'd0,
fpu_madd_fOperand_S0$D_OUT[2:0],
fpu_madd_fOperand_S0$D_OUT[195],
fpu_madd_fOperand_S0$D_OUT[195] &&
fpu_madd_fOperand_S0$D_OUT[194],
IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911,
NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854,
IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1959 } ;
assign fpu_madd_fState_S1$ENQ = CAN_FIRE_RL_fpu_madd_s1_stage ;
assign fpu_madd_fState_S1$DEQ = CAN_FIRE_RL_fpu_madd_s2_stage ;
assign fpu_madd_fState_S1$CLR = 1'b0 ;
// submodule fpu_madd_fState_S2
assign fpu_madd_fState_S2$D_IN = fpu_madd_fState_S1$D_OUT[257:106] ;
assign fpu_madd_fState_S2$ENQ = CAN_FIRE_RL_fpu_madd_s2_stage ;
assign fpu_madd_fState_S2$DEQ = CAN_FIRE_RL_fpu_madd_s3_stage ;
assign fpu_madd_fState_S2$CLR = 1'b0 ;
// submodule fpu_madd_fState_S3
assign fpu_madd_fState_S3$D_IN = fpu_madd_fState_S2$D_OUT ;
assign fpu_madd_fState_S3$ENQ = CAN_FIRE_RL_fpu_madd_s3_stage ;
assign fpu_madd_fState_S3$DEQ = CAN_FIRE_RL_fpu_madd_s4_stage ;
assign fpu_madd_fState_S3$CLR = 1'b0 ;
// submodule fpu_madd_fState_S4
assign fpu_madd_fState_S4$D_IN =
{ fpu_madd_fState_S3$D_OUT[151:87],
IF_fpu_madd_fState_S3_first__995_BIT_151_996_T_ETC___d2525,
fpu_madd_fState_S3$D_OUT[81:14],
!fpu_madd_fState_S3$D_OUT[151] && fpu_madd_fState_S3$D_OUT[13],
fpu_madd_fState_S3$D_OUT[151] ?
63'd0 :
IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2536,
x__h131406 } ;
assign fpu_madd_fState_S4$ENQ = CAN_FIRE_RL_fpu_madd_s4_stage ;
assign fpu_madd_fState_S4$DEQ = CAN_FIRE_RL_fpu_madd_s5_stage ;
assign fpu_madd_fState_S4$CLR = 1'b0 ;
// submodule fpu_madd_fState_S5
assign fpu_madd_fState_S5$D_IN =
{ fpu_madd_fState_S4$D_OUT[203:130],
fpu_madd_fState_S4$D_OUT[129] != fpu_madd_fState_S4$D_OUT[65],
NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ?
fpu_madd_fState_S4$D_OUT[65] :
fpu_madd_fState_S4$D_OUT[129],
IF_NOT_fpu_madd_fState_S4_first__547_BIT_130_5_ETC___d2595 } ;
assign fpu_madd_fState_S5$ENQ = CAN_FIRE_RL_fpu_madd_s5_stage ;
assign fpu_madd_fState_S5$DEQ = CAN_FIRE_RL_fpu_madd_s6_stage ;
assign fpu_madd_fState_S5$CLR = 1'b0 ;
// submodule fpu_madd_fState_S6
assign fpu_madd_fState_S6$D_IN =
{ fpu_madd_fState_S5$D_OUT[215:127],
fpu_madd_fState_S5$D_OUT[113:57],
x__h132359 } ;
assign fpu_madd_fState_S6$ENQ = CAN_FIRE_RL_fpu_madd_s6_stage ;
assign fpu_madd_fState_S6$DEQ = CAN_FIRE_RL_fpu_madd_s7_stage ;
assign fpu_madd_fState_S6$CLR = 1'b0 ;
// submodule fpu_madd_fState_S7
assign fpu_madd_fState_S7$D_IN =
{ fpu_madd_fState_S6$D_OUT[202:114], x__h132871, x__h132880 } ;
assign fpu_madd_fState_S7$ENQ = CAN_FIRE_RL_fpu_madd_s7_stage ;
assign fpu_madd_fState_S7$DEQ = CAN_FIRE_RL_fpu_madd_s8_stage ;
assign fpu_madd_fState_S7$CLR = 1'b0 ;
// submodule fpu_madd_fState_S8
assign fpu_madd_fState_S8$D_IN =
{ fpu_madd_fState_S7$D_OUT[202:138],
fpu_madd_fState_S7$D_OUT[202] ?
fpu_madd_fState_S7$D_OUT[137:133] :
fpu_madd_fState_S7_first__651_BITS_137_TO_133__ETC___d2942,
fpu_madd_fState_S7$D_OUT[132:129],
!fpu_madd_fState_S7$D_OUT[202] &&
fpu_madd_fState_S7$D_OUT[127],
fpu_madd_fState_S7$D_OUT[202] ?
63'd0 :
IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2952,
x__h141760,
fpu_madd_fState_S7$D_OUT[128] } ;
assign fpu_madd_fState_S8$ENQ = CAN_FIRE_RL_fpu_madd_s8_stage ;
assign fpu_madd_fState_S8$DEQ = CAN_FIRE_RL_fpu_madd_s9_stage ;
assign fpu_madd_fState_S8$CLR = 1'b0 ;
// submodule fpu_sqr_fOperand_S0
assign fpu_sqr_fOperand_S0$D_IN =
{ IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848,
iFifo$D_OUT[6:4] } ;
assign fpu_sqr_fOperand_S0$ENQ =
WILL_FIRE_RL_start_op && iFifo$D_OUT[3:0] == 4'd4 ;
assign fpu_sqr_fOperand_S0$DEQ = CAN_FIRE_RL_fpu_sqr_s1_stage ;
assign fpu_sqr_fOperand_S0$CLR = 1'b0 ;
// submodule fpu_sqr_fResult_S5
assign fpu_sqr_fResult_S5$D_IN =
fpu_sqr_fState_S4$D_OUT[138] ?
fpu_sqr_fState_S4$D_OUT[137:69] :
{ (fpu_sqr_fState_S4$D_OUT[64:54] == 11'd2047) ?
fpu_sqr_fState_S4$D_OUT[65:2] :
CASE_fpu_sqr_fState_S4D_OUT_BITS_68_TO_66_0_C_ETC__q183,
fpu_sqr_fState_S4$D_OUT[73:69] |
{ 2'd0,
_theResult___fst_exp__h95990 == 11'd2047 &&
_theResult___fst_sfd__h95991 == 52'd0,
1'd0,
fpu_sqr_fState_S4$D_OUT[64:54] != 11'd2047 &&
fpu_sqr_fState_S4$D_OUT[1:0] != 2'b0 } } ;
assign fpu_sqr_fResult_S5$ENQ = CAN_FIRE_RL_fpu_sqr_s5_stage ;
assign fpu_sqr_fResult_S5$DEQ = fpu_sqr_fResult_S5$EMPTY_N ;
assign fpu_sqr_fResult_S5$CLR = 1'b0 ;
// submodule fpu_sqr_fState_S1
assign fpu_sqr_fState_S1$D_IN =
(fpu_sqr_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
fpu_sqr_fOperand_S0$D_OUT[54:3] != 52'd0 &&
!fpu_sqr_fOperand_S0$D_OUT[54]) ?
{ 1'd1,
fpu_sqr_fOperand_S0$D_OUT[66:55],
sfd__h45004,
130'h20AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } :
IF_fpu_sqr_fOperand_S0_first__059_BITS_65_TO_5_ETC___d1212 ;
assign fpu_sqr_fState_S1$ENQ = CAN_FIRE_RL_fpu_sqr_s1_stage ;
assign fpu_sqr_fState_S1$DEQ = WILL_FIRE_RL_fpu_sqr_s2_stage ;
assign fpu_sqr_fState_S1$CLR = 1'b0 ;
// submodule fpu_sqr_fState_S2
assign fpu_sqr_fState_S2$D_IN = fpu_sqr_fState_S1$D_OUT[194:58] ;
assign fpu_sqr_fState_S2$ENQ = WILL_FIRE_RL_fpu_sqr_s2_stage ;
assign fpu_sqr_fState_S2$DEQ = CAN_FIRE_RL_fpu_sqr_s3_stage ;
assign fpu_sqr_fState_S2$CLR = 1'b0 ;
// submodule fpu_sqr_fState_S3
assign fpu_sqr_fState_S3$D_IN = { fpu_sqr_fState_S2$D_OUT, x__h86149 } ;
assign fpu_sqr_fState_S3$ENQ = CAN_FIRE_RL_fpu_sqr_s3_stage ;
assign fpu_sqr_fState_S3$DEQ = CAN_FIRE_RL_fpu_sqr_s4_stage ;
assign fpu_sqr_fState_S3$CLR = 1'b0 ;
// submodule fpu_sqr_fState_S4
assign fpu_sqr_fState_S4$D_IN =
{ fpu_sqr_fState_S3$D_OUT[195:131],
fpu_sqr_fState_S3$D_OUT[195] && fpu_sqr_fState_S3$D_OUT[130],
fpu_sqr_fState_S3$D_OUT[195] && fpu_sqr_fState_S3$D_OUT[129],
IF_fpu_sqr_fState_S3_first__375_BIT_195_376_TH_ETC___d1671,
fpu_sqr_fState_S3$D_OUT[125:122],
fpu_sqr_fState_S3$D_OUT[195] ?
fpu_sqr_fState_S3$D_OUT[121:59] :
IF_fpu_sqr_fState_S3_first__375_BIT_58_384_AND_ETC___d1678,
x__h95138 } ;
assign fpu_sqr_fState_S4$ENQ = CAN_FIRE_RL_fpu_sqr_s4_stage ;
assign fpu_sqr_fState_S4$DEQ = CAN_FIRE_RL_fpu_sqr_s5_stage ;
assign fpu_sqr_fState_S4$CLR = 1'b0 ;
// submodule iFifo
assign iFifo$D_IN = server_core_request_put ;
assign iFifo$ENQ = EN_server_core_request_put ;
assign iFifo$DEQ = CAN_FIRE_RL_start_op ;
assign iFifo$CLR = CAN_FIRE_RL_rl_reset ;
// submodule isDoubleFifo
assign isDoubleFifo$D_IN = !iFifo$D_OUT[201] ;
assign isDoubleFifo$ENQ = CAN_FIRE_RL_start_op ;
assign isDoubleFifo$DEQ = CAN_FIRE_RL_passResult ;
assign isDoubleFifo$CLR = CAN_FIRE_RL_rl_reset ;
// submodule isNegateFifo
assign isNegateFifo$D_IN =
iFifo$D_OUT[3:0] == 4'd7 || iFifo$D_OUT[3:0] == 4'd8 ;
assign isNegateFifo$ENQ = CAN_FIRE_RL_start_op ;
assign isNegateFifo$DEQ = CAN_FIRE_RL_passResult ;
assign isNegateFifo$CLR = CAN_FIRE_RL_rl_reset ;
// submodule oFifo
assign oFifo$D_IN =
{ !isDoubleFifo$D_OUT,
IF_isDoubleFifo_first__407_THEN_IF_isNegateFif_ETC___d6657,
isDoubleFifo$D_OUT ?
resWire$wget[4:0] :
resWire_wget__410_BITS_4_TO_0_658_OR_NOT_resWi_ETC___d6768 } ;
assign oFifo$ENQ = CAN_FIRE_RL_passResult ;
assign oFifo$DEQ = EN_server_core_response_get ;
assign oFifo$CLR = CAN_FIRE_RL_rl_reset ;
// submodule resetReqsF
assign resetReqsF$ENQ = EN_server_reset_request_put ;
assign resetReqsF$DEQ = CAN_FIRE_RL_rl_reset ;
assign resetReqsF$CLR = 1'b0 ;
// submodule resetRspsF
assign resetRspsF$ENQ = CAN_FIRE_RL_rl_reset ;
assign resetRspsF$DEQ = EN_server_reset_response_get ;
assign resetRspsF$CLR = 1'b0 ;
// submodule rmdFifo
assign rmdFifo$D_IN = iFifo$D_OUT[6:4] ;
assign rmdFifo$ENQ = CAN_FIRE_RL_start_op ;
assign rmdFifo$DEQ = CAN_FIRE_RL_passResult ;
assign rmdFifo$CLR = CAN_FIRE_RL_rl_reset ;
// remaining internal signals
assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__ETC__q133 =
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d5769 ?
_theResult___snd__h277785 :
_theResult____h269613 ;
assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q37 =
_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d3574 ?
_theResult___snd__h172913 :
_theResult____h164612 ;
assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q64 =
_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d4282 ?
_theResult___snd__h250490 :
_theResult____h242189 ;
assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q97 =
_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d5057 ?
_theResult___snd__h211551 :
_theResult____h203250 ;
assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget_ETC__q139 =
_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6280 ?
_theResult___snd__h295551 :
_theResult____h287250 ;
assign IF_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S_ETC__q24 =
_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S3_f_ETC___d2463 ?
_theResult___snd__h131023 :
_theResult___snd__h131018 ;
assign IF_0_CONCAT_IF_IF_fpu_div_fState_S3_first__16__ETC__q12 =
_0_CONCAT_IF_IF_fpu_div_fState_S3_first__16_BIT_ETC___d813 ?
_theResult___snd__h41460 :
_theResult___snd__h41455 ;
assign IF_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__65_ETC__q29 =
_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__651_B_ETC___d2904 ?
_theResult___snd__h141449 :
_theResult___snd__h141444 ;
assign IF_0_CONCAT_IF_fpu_sqr_fState_S3_first__375_BI_ETC__q19 =
_0_CONCAT_IF_fpu_sqr_fState_S3_first__375_BIT_5_ETC___d1633 ?
_theResult___snd__h94826 :
_theResult___snd__h94821 ;
assign IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q100 =
_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d5107 ?
_theResult___snd__h201961 :
_theResult___snd__h220273 ;
assign IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q93 =
_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d4759 ?
_theResult___snd__h201961 :
57'd0 ;
assign IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q33 =
_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3273 ?
_theResult___snd__h163323 :
57'd0 ;
assign IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q40 =
_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3624 ?
_theResult___snd__h163323 :
_theResult___snd__h181635 ;
assign IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q60 =
_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d3984 ?
_theResult___snd__h240900 :
57'd0 ;
assign IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q67 =
_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d4332 ?
_theResult___snd__h240900 :
_theResult___snd__h259212 ;
assign IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q135 =
_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d5984 ?
_theResult___snd__h286367 :
57'd0 ;
assign IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q142 =
_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6333 ?
_theResult___snd__h286367 :
_theResult___snd__h304157 ;
assign IF_0b0_CONCAT_NOT_fpu_div_fState_S4_first__73__ETC___d910 =
sfd__h42033[53] ?
((fpu_div_fState_S4$D_OUT[64:54] == 11'd2046) ?
63'h7FF0000000000000 :
{ din_inc___2_exp__h42617, sfd__h42033[52:1] }) :
{ IF_fpu_div_fState_S4_first__73_BITS_64_TO_54_7_ETC___d907,
sfd__h42033[51:0] } ;
assign IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065 =
sfd__h142040[53] ?
((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2046) ?
63'h7FF0000000000000 :
{ din_inc___2_exp__h142626, sfd__h142040[52:1] }) :
{ IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d2986,
sfd__h142040[51:0] } ;
assign IF_0b0_CONCAT_NOT_fpu_sqr_fState_S4_first__687_ETC___d1724 =
sfd__h95416[53] ?
((fpu_sqr_fState_S4$D_OUT[64:54] == 11'd2046) ?
63'h7FF0000000000000 :
{ din_inc___2_exp__h96000, sfd__h95416[52:1] }) :
{ IF_fpu_sqr_fState_S4_first__687_BITS_64_TO_54__ETC___d1721,
sfd__h95416[51:0] } ;
assign IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6025 =
_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ?
((_theResult___fst_exp__h277722 == 8'd255) ?
!resWire$wget[68] :
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823) :
((_theResult___fst_exp__h286378 == 8'd255) ?
!resWire$wget[68] :
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023) ;
assign IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6399 =
_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ?
((_theResult___fst_exp__h277722 == 8'd255) ?
resWire$wget[68] :
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388) :
((_theResult___fst_exp__h286378 == 8'd255) ?
resWire$wget[68] :
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397) ;
assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d3317 =
_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190 ?
(iFifo$D_OUT[6:4] == 3'd0 || iFifo$D_OUT[6:4] == 3'd1 ||
iFifo$D_OUT[6:4] == 3'd2 ||
iFifo$D_OUT[6:4] == 3'd3 ||
iFifo$D_OUT[6:4] == 3'd4) &&
iFifo$D_OUT[168] :
((_theResult___fst_exp__h163334 == 11'd2047) ?
iFifo$D_OUT[168] :
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55373_ETC__q55) ;
assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4027 =
_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 ?
(iFifo$D_OUT[6:4] == 3'd0 || iFifo$D_OUT[6:4] == 3'd1 ||
iFifo$D_OUT[6:4] == 3'd2 ||
iFifo$D_OUT[6:4] == 3'd3 ||
iFifo$D_OUT[6:4] == 3'd4) &&
iFifo$D_OUT[38] :
((_theResult___fst_exp__h240911 == 11'd2047) ?
iFifo$D_OUT[38] :
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32950_ETC__q80) ;
assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4581 =
_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 ?
iFifo$D_OUT[6:4] != 3'd0 && iFifo$D_OUT[6:4] != 3'd1 &&
iFifo$D_OUT[6:4] != 3'd2 &&
iFifo$D_OUT[6:4] != 3'd3 &&
iFifo$D_OUT[6:4] != 3'd4 ||
!iFifo$D_OUT[38] :
((_theResult___fst_exp__h240911 == 11'd2047) ?
!iFifo$D_OUT[38] :
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32950_ETC__q88) ;
assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4802 =
_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 ?
(iFifo$D_OUT[6:4] == 3'd0 || iFifo$D_OUT[6:4] == 3'd1 ||
iFifo$D_OUT[6:4] == 3'd2 ||
iFifo$D_OUT[6:4] == 3'd3 ||
iFifo$D_OUT[6:4] == 3'd4) &&
iFifo$D_OUT[103] :
((_theResult___fst_exp__h201972 == 11'd2047) ?
iFifo$D_OUT[103] :
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94011_ETC__q115) ;
assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d5347 =
_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 ?
iFifo$D_OUT[6:4] != 3'd0 && iFifo$D_OUT[6:4] != 3'd1 &&
iFifo$D_OUT[6:4] != 3'd2 &&
iFifo$D_OUT[6:4] != 3'd3 &&
iFifo$D_OUT[6:4] != 3'd4 ||
!iFifo$D_OUT[103] :
((_theResult___fst_exp__h201972 == 11'd2047) ?
!iFifo$D_OUT[103] :
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94011_ETC__q121) ;
assign IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767 =
(_theResult____h269613[56] ?
6'd0 :
(_theResult____h269613[55] ?
6'd1 :
(_theResult____h269613[54] ?
6'd2 :
(_theResult____h269613[53] ?
6'd3 :
(_theResult____h269613[52] ?
6'd4 :
(_theResult____h269613[51] ?
6'd5 :
(_theResult____h269613[50] ?
6'd6 :
(_theResult____h269613[49] ?
6'd7 :
(_theResult____h269613[48] ?
6'd8 :
(_theResult____h269613[47] ?
6'd9 :
(_theResult____h269613[46] ?
6'd10 :
(_theResult____h269613[45] ?
6'd11 :
(_theResult____h269613[44] ?
6'd12 :
(_theResult____h269613[43] ?
6'd13 :
(_theResult____h269613[42] ?
6'd14 :
(_theResult____h269613[41] ?
6'd15 :
(_theResult____h269613[40] ?
6'd16 :
(_theResult____h269613[39] ?
6'd17 :
(_theResult____h269613[38] ?
6'd18 :
(_theResult____h269613[37] ?
6'd19 :
(_theResult____h269613[36] ?
6'd20 :
(_theResult____h269613[35] ?
6'd21 :
(_theResult____h269613[34] ?
6'd22 :
(_theResult____h269613[33] ?
6'd23 :
(_theResult____h269613[32] ?
6'd24 :
(_theResult____h269613[31] ?
6'd25 :
(_theResult____h269613[30] ?
6'd26 :
(_theResult____h269613[29] ?
6'd27 :
(_theResult____h269613[28] ?
6'd28 :
(_theResult____h269613[27] ?
6'd29 :
(_theResult____h269613[26] ?
6'd30 :
(_theResult____h269613[25] ?
6'd31 :
(_theResult____h269613[24] ?
6'd32 :
(_theResult____h269613[23] ?
6'd33 :
(_theResult____h269613[22] ?
6'd34 :
(_theResult____h269613[21] ?
6'd35 :
(_theResult____h269613[20] ?
6'd36 :
(_theResult____h269613[19] ?
6'd37 :
(_theResult____h269613[18] ?
6'd38 :
(_theResult____h269613[17] ?
6'd39 :
(_theResult____h269613[16] ?
6'd40 :
(_theResult____h269613[15] ?
6'd41 :
(_theResult____h269613[14] ?
6'd42 :
(_theResult____h269613[13] ?
6'd43 :
(_theResult____h269613[12] ?
6'd44 :
(_theResult____h269613[11] ?
6'd45 :
(_theResult____h269613[10] ?
6'd46 :
(_theResult____h269613[9] ?
6'd47 :
(_theResult____h269613[8] ?
6'd48 :
(_theResult____h269613[7] ?
6'd49 :
(_theResult____h269613[6] ?
6'd50 :
(_theResult____h269613[5] ?
6'd51 :
(_theResult____h269613[4] ?
6'd52 :
(_theResult____h269613[3] ?
6'd53 :
(_theResult____h269613[2] ?
6'd54 :
(_theResult____h269613[1] ?
6'd55 :
(_theResult____h269613[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055 =
(_theResult____h203250[56] ?
6'd0 :
(_theResult____h203250[55] ?
6'd1 :
(_theResult____h203250[54] ?
6'd2 :
(_theResult____h203250[53] ?
6'd3 :
(_theResult____h203250[52] ?
6'd4 :
(_theResult____h203250[51] ?
6'd5 :
(_theResult____h203250[50] ?
6'd6 :
(_theResult____h203250[49] ?
6'd7 :
(_theResult____h203250[48] ?
6'd8 :
(_theResult____h203250[47] ?
6'd9 :
(_theResult____h203250[46] ?
6'd10 :
(_theResult____h203250[45] ?
6'd11 :
(_theResult____h203250[44] ?
6'd12 :
(_theResult____h203250[43] ?
6'd13 :
(_theResult____h203250[42] ?
6'd14 :
(_theResult____h203250[41] ?
6'd15 :
(_theResult____h203250[40] ?
6'd16 :
(_theResult____h203250[39] ?
6'd17 :
(_theResult____h203250[38] ?
6'd18 :
(_theResult____h203250[37] ?
6'd19 :
(_theResult____h203250[36] ?
6'd20 :
(_theResult____h203250[35] ?
6'd21 :
(_theResult____h203250[34] ?
6'd22 :
(_theResult____h203250[33] ?
6'd23 :
(_theResult____h203250[32] ?
6'd24 :
(_theResult____h203250[31] ?
6'd25 :
(_theResult____h203250[30] ?
6'd26 :
(_theResult____h203250[29] ?
6'd27 :
(_theResult____h203250[28] ?
6'd28 :
(_theResult____h203250[27] ?
6'd29 :
(_theResult____h203250[26] ?
6'd30 :
(_theResult____h203250[25] ?
6'd31 :
(_theResult____h203250[24] ?
6'd32 :
(_theResult____h203250[23] ?
6'd33 :
(_theResult____h203250[22] ?
6'd34 :
(_theResult____h203250[21] ?
6'd35 :
(_theResult____h203250[20] ?
6'd36 :
(_theResult____h203250[19] ?
6'd37 :
(_theResult____h203250[18] ?
6'd38 :
(_theResult____h203250[17] ?
6'd39 :
(_theResult____h203250[16] ?
6'd40 :
(_theResult____h203250[15] ?
6'd41 :
(_theResult____h203250[14] ?
6'd42 :
(_theResult____h203250[13] ?
6'd43 :
(_theResult____h203250[12] ?
6'd44 :
(_theResult____h203250[11] ?
6'd45 :
(_theResult____h203250[10] ?
6'd46 :
(_theResult____h203250[9] ?
6'd47 :
(_theResult____h203250[8] ?
6'd48 :
(_theResult____h203250[7] ?
6'd49 :
(_theResult____h203250[6] ?
6'd50 :
(_theResult____h203250[5] ?
6'd51 :
(_theResult____h203250[4] ?
6'd52 :
(_theResult____h203250[3] ?
6'd53 :
(_theResult____h203250[2] ?
6'd54 :
(_theResult____h203250[1] ?
6'd55 :
(_theResult____h203250[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572 =
(_theResult____h164612[56] ?
6'd0 :
(_theResult____h164612[55] ?
6'd1 :
(_theResult____h164612[54] ?
6'd2 :
(_theResult____h164612[53] ?
6'd3 :
(_theResult____h164612[52] ?
6'd4 :
(_theResult____h164612[51] ?
6'd5 :
(_theResult____h164612[50] ?
6'd6 :
(_theResult____h164612[49] ?
6'd7 :
(_theResult____h164612[48] ?
6'd8 :
(_theResult____h164612[47] ?
6'd9 :
(_theResult____h164612[46] ?
6'd10 :
(_theResult____h164612[45] ?
6'd11 :
(_theResult____h164612[44] ?
6'd12 :
(_theResult____h164612[43] ?
6'd13 :
(_theResult____h164612[42] ?
6'd14 :
(_theResult____h164612[41] ?
6'd15 :
(_theResult____h164612[40] ?
6'd16 :
(_theResult____h164612[39] ?
6'd17 :
(_theResult____h164612[38] ?
6'd18 :
(_theResult____h164612[37] ?
6'd19 :
(_theResult____h164612[36] ?
6'd20 :
(_theResult____h164612[35] ?
6'd21 :
(_theResult____h164612[34] ?
6'd22 :
(_theResult____h164612[33] ?
6'd23 :
(_theResult____h164612[32] ?
6'd24 :
(_theResult____h164612[31] ?
6'd25 :
(_theResult____h164612[30] ?
6'd26 :
(_theResult____h164612[29] ?
6'd27 :
(_theResult____h164612[28] ?
6'd28 :
(_theResult____h164612[27] ?
6'd29 :
(_theResult____h164612[26] ?
6'd30 :
(_theResult____h164612[25] ?
6'd31 :
(_theResult____h164612[24] ?
6'd32 :
(_theResult____h164612[23] ?
6'd33 :
(_theResult____h164612[22] ?
6'd34 :
(_theResult____h164612[21] ?
6'd35 :
(_theResult____h164612[20] ?
6'd36 :
(_theResult____h164612[19] ?
6'd37 :
(_theResult____h164612[18] ?
6'd38 :
(_theResult____h164612[17] ?
6'd39 :
(_theResult____h164612[16] ?
6'd40 :
(_theResult____h164612[15] ?
6'd41 :
(_theResult____h164612[14] ?
6'd42 :
(_theResult____h164612[13] ?
6'd43 :
(_theResult____h164612[12] ?
6'd44 :
(_theResult____h164612[11] ?
6'd45 :
(_theResult____h164612[10] ?
6'd46 :
(_theResult____h164612[9] ?
6'd47 :
(_theResult____h164612[8] ?
6'd48 :
(_theResult____h164612[7] ?
6'd49 :
(_theResult____h164612[6] ?
6'd50 :
(_theResult____h164612[5] ?
6'd51 :
(_theResult____h164612[4] ?
6'd52 :
(_theResult____h164612[3] ?
6'd53 :
(_theResult____h164612[2] ?
6'd54 :
(_theResult____h164612[1] ?
6'd55 :
(_theResult____h164612[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280 =
(_theResult____h242189[56] ?
6'd0 :
(_theResult____h242189[55] ?
6'd1 :
(_theResult____h242189[54] ?
6'd2 :
(_theResult____h242189[53] ?
6'd3 :
(_theResult____h242189[52] ?
6'd4 :
(_theResult____h242189[51] ?
6'd5 :
(_theResult____h242189[50] ?
6'd6 :
(_theResult____h242189[49] ?
6'd7 :
(_theResult____h242189[48] ?
6'd8 :
(_theResult____h242189[47] ?
6'd9 :
(_theResult____h242189[46] ?
6'd10 :
(_theResult____h242189[45] ?
6'd11 :
(_theResult____h242189[44] ?
6'd12 :
(_theResult____h242189[43] ?
6'd13 :
(_theResult____h242189[42] ?
6'd14 :
(_theResult____h242189[41] ?
6'd15 :
(_theResult____h242189[40] ?
6'd16 :
(_theResult____h242189[39] ?
6'd17 :
(_theResult____h242189[38] ?
6'd18 :
(_theResult____h242189[37] ?
6'd19 :
(_theResult____h242189[36] ?
6'd20 :
(_theResult____h242189[35] ?
6'd21 :
(_theResult____h242189[34] ?
6'd22 :
(_theResult____h242189[33] ?
6'd23 :
(_theResult____h242189[32] ?
6'd24 :
(_theResult____h242189[31] ?
6'd25 :
(_theResult____h242189[30] ?
6'd26 :
(_theResult____h242189[29] ?
6'd27 :
(_theResult____h242189[28] ?
6'd28 :
(_theResult____h242189[27] ?
6'd29 :
(_theResult____h242189[26] ?
6'd30 :
(_theResult____h242189[25] ?
6'd31 :
(_theResult____h242189[24] ?
6'd32 :
(_theResult____h242189[23] ?
6'd33 :
(_theResult____h242189[22] ?
6'd34 :
(_theResult____h242189[21] ?
6'd35 :
(_theResult____h242189[20] ?
6'd36 :
(_theResult____h242189[19] ?
6'd37 :
(_theResult____h242189[18] ?
6'd38 :
(_theResult____h242189[17] ?
6'd39 :
(_theResult____h242189[16] ?
6'd40 :
(_theResult____h242189[15] ?
6'd41 :
(_theResult____h242189[14] ?
6'd42 :
(_theResult____h242189[13] ?
6'd43 :
(_theResult____h242189[12] ?
6'd44 :
(_theResult____h242189[11] ?
6'd45 :
(_theResult____h242189[10] ?
6'd46 :
(_theResult____h242189[9] ?
6'd47 :
(_theResult____h242189[8] ?
6'd48 :
(_theResult____h242189[7] ?
6'd49 :
(_theResult____h242189[6] ?
6'd50 :
(_theResult____h242189[5] ?
6'd51 :
(_theResult____h242189[4] ?
6'd52 :
(_theResult____h242189[3] ?
6'd53 :
(_theResult____h242189[2] ?
6'd54 :
(_theResult____h242189[1] ?
6'd55 :
(_theResult____h242189[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278 =
(_theResult____h287250[56] ?
6'd0 :
(_theResult____h287250[55] ?
6'd1 :
(_theResult____h287250[54] ?
6'd2 :
(_theResult____h287250[53] ?
6'd3 :
(_theResult____h287250[52] ?
6'd4 :
(_theResult____h287250[51] ?
6'd5 :
(_theResult____h287250[50] ?
6'd6 :
(_theResult____h287250[49] ?
6'd7 :
(_theResult____h287250[48] ?
6'd8 :
(_theResult____h287250[47] ?
6'd9 :
(_theResult____h287250[46] ?
6'd10 :
(_theResult____h287250[45] ?
6'd11 :
(_theResult____h287250[44] ?
6'd12 :
(_theResult____h287250[43] ?
6'd13 :
(_theResult____h287250[42] ?
6'd14 :
(_theResult____h287250[41] ?
6'd15 :
(_theResult____h287250[40] ?
6'd16 :
(_theResult____h287250[39] ?
6'd17 :
(_theResult____h287250[38] ?
6'd18 :
(_theResult____h287250[37] ?
6'd19 :
(_theResult____h287250[36] ?
6'd20 :
(_theResult____h287250[35] ?
6'd21 :
(_theResult____h287250[34] ?
6'd22 :
(_theResult____h287250[33] ?
6'd23 :
(_theResult____h287250[32] ?
6'd24 :
(_theResult____h287250[31] ?
6'd25 :
(_theResult____h287250[30] ?
6'd26 :
(_theResult____h287250[29] ?
6'd27 :
(_theResult____h287250[28] ?
6'd28 :
(_theResult____h287250[27] ?
6'd29 :
(_theResult____h287250[26] ?
6'd30 :
(_theResult____h287250[25] ?
6'd31 :
(_theResult____h287250[24] ?
6'd32 :
(_theResult____h287250[23] ?
6'd33 :
(_theResult____h287250[22] ?
6'd34 :
(_theResult____h287250[21] ?
6'd35 :
(_theResult____h287250[20] ?
6'd36 :
(_theResult____h287250[19] ?
6'd37 :
(_theResult____h287250[18] ?
6'd38 :
(_theResult____h287250[17] ?
6'd39 :
(_theResult____h287250[16] ?
6'd40 :
(_theResult____h287250[15] ?
6'd41 :
(_theResult____h287250[14] ?
6'd42 :
(_theResult____h287250[13] ?
6'd43 :
(_theResult____h287250[12] ?
6'd44 :
(_theResult____h287250[11] ?
6'd45 :
(_theResult____h287250[10] ?
6'd46 :
(_theResult____h287250[9] ?
6'd47 :
(_theResult____h287250[8] ?
6'd48 :
(_theResult____h287250[7] ?
6'd49 :
(_theResult____h287250[6] ?
6'd50 :
(_theResult____h287250[5] ?
6'd51 :
(_theResult____h287250[4] ?
6'd52 :
(_theResult____h287250[3] ?
6'd53 :
(_theResult____h287250[2] ?
6'd54 :
(_theResult____h287250[1] ?
6'd55 :
(_theResult____h287250[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 =
(din_exp__h130866 == 11'd0) ?
12'd3074 :
{ din_exp30866_MINUS_1023__q23[10],
din_exp30866_MINUS_1023__q23 } ;
assign IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460 =
(sfdBC__h115662[105] ?
7'd0 :
(sfdBC__h115662[104] ?
7'd1 :
(sfdBC__h115662[103] ?
7'd2 :
(sfdBC__h115662[102] ?
7'd3 :
(sfdBC__h115662[101] ?
7'd4 :
(sfdBC__h115662[100] ?
7'd5 :
(sfdBC__h115662[99] ?
7'd6 :
(sfdBC__h115662[98] ?
7'd7 :
(sfdBC__h115662[97] ?
7'd8 :
(sfdBC__h115662[96] ?
7'd9 :
(sfdBC__h115662[95] ?
7'd10 :
(sfdBC__h115662[94] ?
7'd11 :
(sfdBC__h115662[93] ?
7'd12 :
(sfdBC__h115662[92] ?
7'd13 :
(sfdBC__h115662[91] ?
7'd14 :
(sfdBC__h115662[90] ?
7'd15 :
(sfdBC__h115662[89] ?
7'd16 :
(sfdBC__h115662[88] ?
7'd17 :
(sfdBC__h115662[87] ?
7'd18 :
(sfdBC__h115662[86] ?
7'd19 :
(sfdBC__h115662[85] ?
7'd20 :
(sfdBC__h115662[84] ?
7'd21 :
(sfdBC__h115662[83] ?
7'd22 :
(sfdBC__h115662[82] ?
7'd23 :
(sfdBC__h115662[81] ?
7'd24 :
(sfdBC__h115662[80] ?
7'd25 :
(sfdBC__h115662[79] ?
7'd26 :
(sfdBC__h115662[78] ?
7'd27 :
(sfdBC__h115662[77] ?
7'd28 :
(sfdBC__h115662[76] ?
7'd29 :
(sfdBC__h115662[75] ?
7'd30 :
(sfdBC__h115662[74] ?
7'd31 :
(sfdBC__h115662[73] ?
7'd32 :
(sfdBC__h115662[72] ?
7'd33 :
(sfdBC__h115662[71] ?
7'd34 :
(sfdBC__h115662[70] ?
7'd35 :
(sfdBC__h115662[69] ?
7'd36 :
(sfdBC__h115662[68] ?
7'd37 :
(sfdBC__h115662[67] ?
7'd38 :
(sfdBC__h115662[66] ?
7'd39 :
(sfdBC__h115662[65] ?
7'd40 :
(sfdBC__h115662[64] ?
7'd41 :
(sfdBC__h115662[63] ?
7'd42 :
(sfdBC__h115662[62] ?
7'd43 :
(sfdBC__h115662[61] ?
7'd44 :
(sfdBC__h115662[60] ?
7'd45 :
(sfdBC__h115662[59] ?
7'd46 :
(sfdBC__h115662[58] ?
7'd47 :
(sfdBC__h115662[57] ?
7'd48 :
(sfdBC__h115662[56] ?
7'd49 :
(sfdBC__h115662[55] ?
7'd50 :
(sfdBC__h115662[54] ?
7'd51 :
(sfdBC__h115662[53] ?
7'd52 :
(sfdBC__h115662[52] ?
7'd53 :
(sfdBC__h115662[51] ?
7'd54 :
(sfdBC__h115662[50] ?
7'd55 :
(sfdBC__h115662[49] ?
7'd56 :
(sfdBC__h115662[48] ?
7'd57 :
(sfdBC__h115662[47] ?
7'd58 :
(sfdBC__h115662[46] ?
7'd59 :
(sfdBC__h115662[45] ?
7'd60 :
(sfdBC__h115662[44] ?
7'd61 :
(sfdBC__h115662[43] ?
7'd62 :
(sfdBC__h115662[42] ?
7'd63 :
(sfdBC__h115662[41] ?
7'd64 :
(sfdBC__h115662[40] ?
7'd65 :
(sfdBC__h115662[39] ?
7'd66 :
(sfdBC__h115662[38] ?
7'd67 :
(sfdBC__h115662[37] ?
7'd68 :
(sfdBC__h115662[36] ?
7'd69 :
(sfdBC__h115662[35] ?
7'd70 :
(sfdBC__h115662[34] ?
7'd71 :
(sfdBC__h115662[33] ?
7'd72 :
(sfdBC__h115662[32] ?
7'd73 :
(sfdBC__h115662[31] ?
7'd74 :
(sfdBC__h115662[30] ?
7'd75 :
(sfdBC__h115662[29] ?
7'd76 :
(sfdBC__h115662[28] ?
7'd77 :
(sfdBC__h115662[27] ?
7'd78 :
(sfdBC__h115662[26] ?
7'd79 :
(sfdBC__h115662[25] ?
7'd80 :
(sfdBC__h115662[24] ?
7'd81 :
(sfdBC__h115662[23] ?
7'd82 :
(sfdBC__h115662[22] ?
7'd83 :
(sfdBC__h115662[21] ?
7'd84 :
(sfdBC__h115662[20] ?
7'd85 :
(sfdBC__h115662[19] ?
7'd86 :
(sfdBC__h115662[18] ?
7'd87 :
(sfdBC__h115662[17] ?
7'd88 :
(sfdBC__h115662[16] ?
7'd89 :
(sfdBC__h115662[15] ?
7'd90 :
(sfdBC__h115662[14] ?
7'd91 :
(sfdBC__h115662[13] ?
7'd92 :
(sfdBC__h115662[12] ?
7'd93 :
(sfdBC__h115662[11] ?
7'd94 :
(sfdBC__h115662[10] ?
7'd95 :
(sfdBC__h115662[9] ?
7'd96 :
(sfdBC__h115662[8] ?
7'd97 :
(sfdBC__h115662[7] ?
7'd98 :
(sfdBC__h115662[6] ?
7'd99 :
(sfdBC__h115662[5] ?
7'd100 :
(sfdBC__h115662[4] ?
7'd101 :
(sfdBC__h115662[3] ?
7'd102 :
(sfdBC__h115662[2] ?
7'd103 :
(sfdBC__h115662[1] ?
7'd104 :
(sfdBC__h115662[0] ?
7'd105 :
7'd106)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
7'd1 ;
assign IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2462 =
IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 -
12'd3074 ;
assign IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2534 =
(sfdBC__h115662[105] &&
IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 ==
12'd1023) ?
63'h7FEFFFFFFFFFFFFF :
{ _theResult___fst_exp__h130949, sfdin__h130943[105:54] } ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6448 =
(guard__h269623 == 2'b0 || resWire$wget[68]) ?
_theResult___fst_exp__h277722 :
_theResult___exp__h278238 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6450 =
(guard__h269623 == 2'b0) ?
_theResult___fst_exp__h277722 :
(resWire$wget[68] ?
_theResult___exp__h278238 :
_theResult___fst_exp__h277722) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6576 =
(guard__h269623 == 2'b0 || resWire$wget[68]) ?
sfdin__h277716[56:34] :
_theResult___sfd__h278239 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6578 =
(guard__h269623 == 2'b0) ?
sfdin__h277716[56:34] :
(resWire$wget[68] ?
_theResult___sfd__h278239 :
sfdin__h277716[56:34]) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3729 =
(guard__h164622 == 2'b0 || iFifo$D_OUT[168]) ?
_theResult___fst_exp__h172850 :
_theResult___exp__h173569 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3731 =
(guard__h164622 == 2'b0) ?
_theResult___fst_exp__h172850 :
(iFifo$D_OUT[168] ?
_theResult___exp__h173569 :
_theResult___fst_exp__h172850) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3813 =
(guard__h164622 == 2'b0 || iFifo$D_OUT[168]) ?
sfdin__h172844[56:5] :
_theResult___sfd__h173570 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3815 =
(guard__h164622 == 2'b0) ?
sfdin__h172844[56:5] :
(iFifo$D_OUT[168] ?
_theResult___sfd__h173570 :
sfdin__h172844[56:5]) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4436 =
(guard__h242199 == 2'b0 || iFifo$D_OUT[38]) ?
_theResult___fst_exp__h250427 :
_theResult___exp__h251146 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4438 =
(guard__h242199 == 2'b0) ?
_theResult___fst_exp__h250427 :
(iFifo$D_OUT[38] ?
_theResult___exp__h251146 :
_theResult___fst_exp__h250427) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4519 =
(guard__h242199 == 2'b0 || iFifo$D_OUT[38]) ?
sfdin__h250421[56:5] :
_theResult___sfd__h251147 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4521 =
(guard__h242199 == 2'b0) ?
sfdin__h250421[56:5] :
(iFifo$D_OUT[38] ?
_theResult___sfd__h251147 :
sfdin__h250421[56:5]) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5211 =
(guard__h203260 == 2'b0 || iFifo$D_OUT[103]) ?
_theResult___fst_exp__h211488 :
_theResult___exp__h212207 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5213 =
(guard__h203260 == 2'b0) ?
_theResult___fst_exp__h211488 :
(iFifo$D_OUT[103] ?
_theResult___exp__h212207 :
_theResult___fst_exp__h211488) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5294 =
(guard__h203260 == 2'b0 || iFifo$D_OUT[103]) ?
sfdin__h211482[56:5] :
_theResult___sfd__h212208 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5296 =
(guard__h203260 == 2'b0) ?
sfdin__h211482[56:5] :
(iFifo$D_OUT[103] ?
_theResult___sfd__h212208 :
sfdin__h211482[56:5]) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6518 =
(guard__h287260 == 2'b0 || resWire$wget[68]) ?
_theResult___fst_exp__h295488 :
_theResult___exp__h296004 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6520 =
(guard__h287260 == 2'b0) ?
_theResult___fst_exp__h295488 :
(resWire$wget[68] ?
_theResult___exp__h296004 :
_theResult___fst_exp__h295488) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6622 =
(guard__h287260 == 2'b0 || resWire$wget[68]) ?
sfdin__h295482[56:34] :
_theResult___sfd__h296005 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6624 =
(guard__h287260 == 2'b0) ?
sfdin__h295482[56:34] :
(resWire$wget[68] ?
_theResult___sfd__h296005 :
sfdin__h295482[56:34]) ;
assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5173 =
(guard__h194011 == 2'b0 || iFifo$D_OUT[103]) ?
_theResult___fst_exp__h201972 :
_theResult___exp__h202617 ;
assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5175 =
(guard__h194011 == 2'b0) ?
_theResult___fst_exp__h201972 :
(iFifo$D_OUT[103] ?
_theResult___exp__h202617 :
_theResult___fst_exp__h201972) ;
assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5242 =
(guard__h212299 == 2'b0 || iFifo$D_OUT[103]) ?
_theResult___fst_exp__h220289 :
_theResult___exp__h220959 ;
assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5244 =
(guard__h212299 == 2'b0) ?
_theResult___fst_exp__h220289 :
(iFifo$D_OUT[103] ?
_theResult___exp__h220959 :
_theResult___fst_exp__h220289) ;
assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5268 =
(guard__h194011 == 2'b0 || iFifo$D_OUT[103]) ?
_theResult___snd__h201923[56:5] :
_theResult___sfd__h202618 ;
assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5270 =
(guard__h194011 == 2'b0) ?
_theResult___snd__h201923[56:5] :
(iFifo$D_OUT[103] ?
_theResult___sfd__h202618 :
_theResult___snd__h201923[56:5]) ;
assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5313 =
(guard__h212299 == 2'b0 || iFifo$D_OUT[103]) ?
_theResult___snd__h220235[56:5] :
_theResult___sfd__h220960 ;
assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5315 =
(guard__h212299 == 2'b0) ?
_theResult___snd__h220235[56:5] :
(iFifo$D_OUT[103] ?
_theResult___sfd__h220960 :
_theResult___snd__h220235[56:5]) ;
assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3690 =
(guard__h155373 == 2'b0 || iFifo$D_OUT[168]) ?
_theResult___fst_exp__h163334 :
_theResult___exp__h163979 ;
assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3692 =
(guard__h155373 == 2'b0) ?
_theResult___fst_exp__h163334 :
(iFifo$D_OUT[168] ?
_theResult___exp__h163979 :
_theResult___fst_exp__h163334) ;
assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3760 =
(guard__h173661 == 2'b0 || iFifo$D_OUT[168]) ?
_theResult___fst_exp__h181651 :
_theResult___exp__h182321 ;
assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3762 =
(guard__h173661 == 2'b0) ?
_theResult___fst_exp__h181651 :
(iFifo$D_OUT[168] ?
_theResult___exp__h182321 :
_theResult___fst_exp__h181651) ;
assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3786 =
(guard__h155373 == 2'b0 || iFifo$D_OUT[168]) ?
_theResult___snd__h163285[56:5] :
_theResult___sfd__h163980 ;
assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3788 =
(guard__h155373 == 2'b0) ?
_theResult___snd__h163285[56:5] :
(iFifo$D_OUT[168] ?
_theResult___sfd__h163980 :
_theResult___snd__h163285[56:5]) ;
assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3832 =
(guard__h173661 == 2'b0 || iFifo$D_OUT[168]) ?
_theResult___snd__h181597[56:5] :
_theResult___sfd__h182322 ;
assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3834 =
(guard__h173661 == 2'b0) ?
_theResult___snd__h181597[56:5] :
(iFifo$D_OUT[168] ?
_theResult___sfd__h182322 :
_theResult___snd__h181597[56:5]) ;
assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4398 =
(guard__h232950 == 2'b0 || iFifo$D_OUT[38]) ?
_theResult___fst_exp__h240911 :
_theResult___exp__h241556 ;
assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4400 =
(guard__h232950 == 2'b0) ?
_theResult___fst_exp__h240911 :
(iFifo$D_OUT[38] ?
_theResult___exp__h241556 :
_theResult___fst_exp__h240911) ;
assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4467 =
(guard__h251238 == 2'b0 || iFifo$D_OUT[38]) ?
_theResult___fst_exp__h259228 :
_theResult___exp__h259898 ;
assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4469 =
(guard__h251238 == 2'b0) ?
_theResult___fst_exp__h259228 :
(iFifo$D_OUT[38] ?
_theResult___exp__h259898 :
_theResult___fst_exp__h259228) ;
assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4493 =
(guard__h232950 == 2'b0 || iFifo$D_OUT[38]) ?
_theResult___snd__h240862[56:5] :
_theResult___sfd__h241557 ;
assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4495 =
(guard__h232950 == 2'b0) ?
_theResult___snd__h240862[56:5] :
(iFifo$D_OUT[38] ?
_theResult___sfd__h241557 :
_theResult___snd__h240862[56:5]) ;
assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4538 =
(guard__h251238 == 2'b0 || iFifo$D_OUT[38]) ?
_theResult___snd__h259174[56:5] :
_theResult___sfd__h259899 ;
assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4540 =
(guard__h251238 == 2'b0) ?
_theResult___snd__h259174[56:5] :
(iFifo$D_OUT[38] ?
_theResult___sfd__h259899 :
_theResult___snd__h259174[56:5]) ;
assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6479 =
(guard__h278330 == 2'b0 || resWire$wget[68]) ?
_theResult___fst_exp__h286378 :
_theResult___exp__h286820 ;
assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6481 =
(guard__h278330 == 2'b0) ?
_theResult___fst_exp__h286378 :
(resWire$wget[68] ?
_theResult___exp__h286820 :
_theResult___fst_exp__h286378) ;
assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6549 =
(guard__h296096 == 2'b0 || resWire$wget[68]) ?
_theResult___fst_exp__h304173 :
_theResult___exp__h304640 ;
assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6551 =
(guard__h296096 == 2'b0) ?
_theResult___fst_exp__h304173 :
(resWire$wget[68] ?
_theResult___exp__h304640 :
_theResult___fst_exp__h304173) ;
assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6595 =
(guard__h278330 == 2'b0 || resWire$wget[68]) ?
_theResult___snd__h286329[56:34] :
_theResult___sfd__h286821 ;
assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6597 =
(guard__h278330 == 2'b0) ?
_theResult___snd__h286329[56:34] :
(resWire$wget[68] ?
_theResult___sfd__h286821 :
_theResult___snd__h286329[56:34]) ;
assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6641 =
(guard__h296096 == 2'b0 || resWire$wget[68]) ?
_theResult___snd__h304119[56:34] :
_theResult___sfd__h304641 ;
assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6643 =
(guard__h296096 == 2'b0) ?
_theResult___snd__h304119[56:34] :
(resWire$wget[68] ?
_theResult___sfd__h304641 :
_theResult___snd__h304119[56:34]) ;
assign IF_IF_fpu_div_fState_S3_first__16_BITS_120_TO__ETC___d573 =
(_theResult___fst_exp__h41341 == 11'd0) ?
12'd3074 :
{ theResult___fst_exp1341_MINUS_1023__q11[10],
theResult___fst_exp1341_MINUS_1023__q11 } ;
assign IF_IF_fpu_div_fState_S3_first__16_BITS_120_TO__ETC___d810 =
(sfdin__h33169[57] ?
6'd0 :
(sfdin__h33169[56] ?
6'd1 :
(sfdin__h33169[55] ?
6'd2 :
(sfdin__h33169[54] ?
6'd3 :
(sfdin__h33169[53] ?
6'd4 :
(sfdin__h33169[52] ?
6'd5 :
(sfdin__h33169[51] ?
6'd6 :
(sfdin__h33169[50] ?
6'd7 :
(sfdin__h33169[49] ?
6'd8 :
(sfdin__h33169[48] ?
6'd9 :
(sfdin__h33169[47] ?
6'd10 :
(sfdin__h33169[46] ?
6'd11 :
(sfdin__h33169[45] ?
6'd12 :
(sfdin__h33169[44] ?
6'd13 :
(sfdin__h33169[43] ?
6'd14 :
(sfdin__h33169[42] ?
6'd15 :
(sfdin__h33169[41] ?
6'd16 :
(sfdin__h33169[40] ?
6'd17 :
(sfdin__h33169[39] ?
6'd18 :
(sfdin__h33169[38] ?
6'd19 :
(sfdin__h33169[37] ?
6'd20 :
(sfdin__h33169[36] ?
6'd21 :
(sfdin__h33169[35] ?
6'd22 :
(sfdin__h33169[34] ?
6'd23 :
(sfdin__h33169[33] ?
6'd24 :
(sfdin__h33169[32] ?
6'd25 :
(sfdin__h33169[31] ?
6'd26 :
(sfdin__h33169[30] ?
6'd27 :
(sfdin__h33169[29] ?
6'd28 :
(sfdin__h33169[28] ?
6'd29 :
(sfdin__h33169[27] ?
6'd30 :
(sfdin__h33169[26] ?
6'd31 :
(sfdin__h33169[25] ?
6'd32 :
(sfdin__h33169[24] ?
6'd33 :
(sfdin__h33169[23] ?
6'd34 :
(sfdin__h33169[22] ?
6'd35 :
(sfdin__h33169[21] ?
6'd36 :
(sfdin__h33169[20] ?
6'd37 :
(sfdin__h33169[19] ?
6'd38 :
(sfdin__h33169[18] ?
6'd39 :
(sfdin__h33169[17] ?
6'd40 :
(sfdin__h33169[16] ?
6'd41 :
(sfdin__h33169[15] ?
6'd42 :
(sfdin__h33169[14] ?
6'd43 :
(sfdin__h33169[13] ?
6'd44 :
(sfdin__h33169[12] ?
6'd45 :
(sfdin__h33169[11] ?
6'd46 :
(sfdin__h33169[10] ?
6'd47 :
(sfdin__h33169[9] ?
6'd48 :
(sfdin__h33169[8] ?
6'd49 :
(sfdin__h33169[7] ?
6'd50 :
(sfdin__h33169[6] ?
6'd51 :
(sfdin__h33169[5] ?
6'd52 :
(sfdin__h33169[4] ?
6'd53 :
(sfdin__h33169[3] ?
6'd54 :
(sfdin__h33169[2] ?
6'd55 :
(sfdin__h33169[1] ?
6'd56 :
(sfdin__h33169[0] ?
6'd57 :
6'd58)))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_fpu_div_fState_S3_first__16_BITS_120_TO__ETC___d812 =
IF_IF_fpu_div_fState_S3_first__16_BITS_120_TO__ETC___d573 -
12'd3074 ;
assign IF_IF_fpu_div_fState_S3_first__16_BITS_120_TO__ETC___d856 =
IF_fpu_div_fState_S3_first__16_BITS_120_TO_110_ETC___d527 ?
IF_fpu_div_fState_S3_first__16_BITS_120_TO_110_ETC___d851 :
{ fpu_div_fState_S3$D_OUT[129:128],
(fpu_div_fState_S3$D_OUT[120:110] == 11'd2047) ?
fpu_div_fState_S3$D_OUT[57:56] != 2'b0 ||
fpu_div_fState_S3$D_OUT[127] :
fpu_div_fState_S3$D_OUT[127],
fpu_div_fState_S3$D_OUT[126],
(fpu_div_fState_S3$D_OUT[120:110] == 11'd2047) ?
fpu_div_fState_S3$D_OUT[57:56] != 2'b0 ||
fpu_div_fState_S3$D_OUT[125] :
fpu_div_fState_S3$D_OUT[125] } ;
assign IF_IF_fpu_div_fState_S3_first__16_BITS_120_TO__ETC___d859 =
(sfdin__h33169[57] &&
IF_IF_fpu_div_fState_S3_first__16_BITS_120_TO__ETC___d573 ==
12'd1023) ?
63'h7FEFFFFFFFFFFFFF :
{ _theResult___fst_exp__h41384, sfdin__h41378[57:6] } ;
assign IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1922 =
(x__h96539 == 11'd2047 &&
_theResult___fst_sfd__h96608 == 52'd0) ?
fpu_madd_fOperand_S0$D_OUT[195] &&
fpu_madd_fOperand_S0$D_OUT[194] :
((fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 ||
fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0) ?
NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854 :
fpu_madd_fOperand_S0$D_OUT[195] &&
fpu_madd_fOperand_S0$D_OUT[194]) ;
assign IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1931 =
(x__h96539 == 11'd2047 &&
_theResult___fst_sfd__h96608 == 52'd0) ?
IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911 :
((fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 ||
fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0) ?
63'h7FF0000000000000 :
IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911) ;
assign IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1936 =
(x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608[51]) ?
{ fpu_madd_fOperand_S0$D_OUT[195] &&
fpu_madd_fOperand_S0$D_OUT[194],
IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911 } :
((fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
fpu_madd_fOperand_S0$D_OUT[118]) ?
fpu_madd_fOperand_S0$D_OUT[130:67] :
((fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
fpu_madd_fOperand_S0$D_OUT[54]) ?
fpu_madd_fOperand_S0$D_OUT[66:3] :
{ NOT_fpu_madd_fOperand_S0_first__803_BITS_129_T_ETC___d1923,
IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1932 })) ;
assign IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1939 =
(x__h96539 == 11'd2047 &&
_theResult___fst_sfd__h96608 != 52'd0 &&
!_theResult___fst_sfd__h96608[51]) ?
{ fpu_madd_fOperand_S0$D_OUT[195] &&
fpu_madd_fOperand_S0$D_OUT[194],
x__h96539,
sfd__h99402 } :
IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1938 ;
assign IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901 =
(sfd__h133119[56] ?
6'd0 :
(sfd__h133119[55] ?
6'd1 :
(sfd__h133119[54] ?
6'd2 :
(sfd__h133119[53] ?
6'd3 :
(sfd__h133119[52] ?
6'd4 :
(sfd__h133119[51] ?
6'd5 :
(sfd__h133119[50] ?
6'd6 :
(sfd__h133119[49] ?
6'd7 :
(sfd__h133119[48] ?
6'd8 :
(sfd__h133119[47] ?
6'd9 :
(sfd__h133119[46] ?
6'd10 :
(sfd__h133119[45] ?
6'd11 :
(sfd__h133119[44] ?
6'd12 :
(sfd__h133119[43] ?
6'd13 :
(sfd__h133119[42] ?
6'd14 :
(sfd__h133119[41] ?
6'd15 :
(sfd__h133119[40] ?
6'd16 :
(sfd__h133119[39] ?
6'd17 :
(sfd__h133119[38] ?
6'd18 :
(sfd__h133119[37] ?
6'd19 :
(sfd__h133119[36] ?
6'd20 :
(sfd__h133119[35] ?
6'd21 :
(sfd__h133119[34] ?
6'd22 :
(sfd__h133119[33] ?
6'd23 :
(sfd__h133119[32] ?
6'd24 :
(sfd__h133119[31] ?
6'd25 :
(sfd__h133119[30] ?
6'd26 :
(sfd__h133119[29] ?
6'd27 :
(sfd__h133119[28] ?
6'd28 :
(sfd__h133119[27] ?
6'd29 :
(sfd__h133119[26] ?
6'd30 :
(sfd__h133119[25] ?
6'd31 :
(sfd__h133119[24] ?
6'd32 :
(sfd__h133119[23] ?
6'd33 :
(sfd__h133119[22] ?
6'd34 :
(sfd__h133119[21] ?
6'd35 :
(sfd__h133119[20] ?
6'd36 :
(sfd__h133119[19] ?
6'd37 :
(sfd__h133119[18] ?
6'd38 :
(sfd__h133119[17] ?
6'd39 :
(sfd__h133119[16] ?
6'd40 :
(sfd__h133119[15] ?
6'd41 :
(sfd__h133119[14] ?
6'd42 :
(sfd__h133119[13] ?
6'd43 :
(sfd__h133119[12] ?
6'd44 :
(sfd__h133119[11] ?
6'd45 :
(sfd__h133119[10] ?
6'd46 :
(sfd__h133119[9] ?
6'd47 :
(sfd__h133119[8] ?
6'd48 :
(sfd__h133119[7] ?
6'd49 :
(sfd__h133119[6] ?
6'd50 :
(sfd__h133119[5] ?
6'd51 :
(sfd__h133119[4] ?
6'd52 :
(sfd__h133119[3] ?
6'd53 :
(sfd__h133119[2] ?
6'd54 :
(sfd__h133119[1] ?
6'd55 :
(sfd__h133119[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2952 =
(sfd__h133119[56] &&
IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 ==
12'd1023) ?
63'h7FEFFFFFFFFFFFFF :
{ _theResult___fst_exp__h141375, sfdin__h141369[56:5] } ;
assign IF_IF_rg_index_1_87_ULE_58_91_THEN_NOT_rg_b_92_ETC___d1028 =
IF_rg_index_1_87_ULE_58_91_THEN_NOT_rg_b_92_EQ_ETC___d1009 ?
((IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1002 ==
116'd0) ?
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1022 :
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1026) :
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1026 ;
assign IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2503 =
(!fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ||
fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004) ?
fpu_madd_fState_S3$D_OUT[86] :
fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[4] ;
assign IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2506 =
(!fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ||
fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004) ?
fpu_madd_fState_S3$D_OUT[85] :
fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[3] ;
assign IF_NOT_fpu_madd_fState_S4_first__547_BIT_130_5_ETC___d2595 =
{ NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ?
IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 :
IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568,
NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ?
IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 -
IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 :
IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 -
IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563,
x__h131940,
x__h131944 } ;
assign IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5106 =
((SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] ==
11'd0) ?
12'd3074 :
{ SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q99[10],
SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q99 }) -
12'd3074 ;
assign IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5146 =
SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 ?
((_theResult___fst_exp__h211488 == 11'd2047) ?
iFifo$D_OUT[103] :
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03260_ETC__q117) :
((_theResult___fst_exp__h220289 == 11'd2047) ?
iFifo$D_OUT[103] :
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12299_ETC__q119) ;
assign IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5374 =
SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 ?
((_theResult___fst_exp__h211488 == 11'd2047) ?
!iFifo$D_OUT[103] :
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03260_ETC__q123) :
((_theResult___fst_exp__h220289 == 11'd2047) ?
!iFifo$D_OUT[103] :
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12299_ETC__q125) ;
assign IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3623 =
((SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] ==
11'd0) ?
12'd3074 :
{ SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q39[10],
SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q39 }) -
12'd3074 ;
assign IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3663 =
SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325 ?
((_theResult___fst_exp__h172850 == 11'd2047) ?
iFifo$D_OUT[168] :
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64622_ETC__q57) :
((_theResult___fst_exp__h181651 == 11'd2047) ?
iFifo$D_OUT[168] :
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73661_ETC__q59) ;
assign IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4331 =
((SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] ==
11'd0) ?
12'd3074 :
{ SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q66[10],
SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q66 }) -
12'd3074 ;
assign IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4371 =
SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 ?
((_theResult___fst_exp__h250427 == 11'd2047) ?
iFifo$D_OUT[38] :
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42199_ETC__q84) :
((_theResult___fst_exp__h259228 == 11'd2047) ?
iFifo$D_OUT[38] :
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51238_ETC__q86) ;
assign IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4608 =
SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 ?
((_theResult___fst_exp__h250427 == 11'd2047) ?
!iFifo$D_OUT[38] :
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42199_ETC__q90) :
((_theResult___fst_exp__h259228 == 11'd2047) ?
!iFifo$D_OUT[38] :
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51238_ETC__q92) ;
assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6332 =
((SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] ==
8'd0) ?
9'd386 :
{ SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q141[7],
SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q141 }) -
9'd386 ;
assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6375 =
SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ?
((_theResult___fst_exp__h295488 == 8'd255) ?
!resWire$wget[68] :
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324) :
((_theResult___fst_exp__h304173 == 8'd255) ?
!resWire$wget[68] :
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373) ;
assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6420 =
SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ?
((_theResult___fst_exp__h295488 == 8'd255) ?
resWire$wget[68] :
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409) :
((_theResult___fst_exp__h304173 == 8'd255) ?
resWire$wget[68] :
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418) ;
assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6734 =
SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[2] :
_theResult___fst_exp__h304721 == 8'd255 &&
_theResult___fst_sfd__h304722 == 23'd0 ;
assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6747 =
SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[1] :
_theResult___fst_exp__h304173 == 8'd0 &&
guard__h296096 != 2'b0 ;
assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6760 =
SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[0] :
_theResult___fst_exp__h304173 != 8'd255 &&
guard__h296096 != 2'b0 ;
assign IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d282 =
(((fpu_div_fOperands_S0$D_OUT[129:119] == 11'd0) ?
13'd7170 :
{ {2{fpu_div_fOperands_S0D_OUT_BITS_129_TO_119_MIN_ETC__q7[10]}},
fpu_div_fOperands_S0D_OUT_BITS_129_TO_119_MIN_ETC__q7 }) -
{ 7'd0, b__h3090 }) -
(((fpu_div_fOperands_S0$D_OUT[65:55] == 11'd0) ?
13'd7170 :
{ {2{fpu_div_fOperands_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q8[10]}},
fpu_div_fOperands_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q8 }) -
{ 7'd0, b__h10508 }) ;
assign IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d283 =
(IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d282 ^
13'h1000) <=
13'd5120 ;
assign IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d285 =
(IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d282 ^
13'h1000) <
13'd3020 ;
assign IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d429 =
(IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d282 ^
13'h1000) <
13'd3074 ;
assign IF_fpu_div_fOperands_S0_first__6_BITS_65_TO_55_ETC___d352 =
(fpu_div_fOperands_S0$D_OUT[65:55] == 11'd0 &&
fpu_div_fOperands_S0$D_OUT[54:3] == 52'd0 ||
fpu_div_fOperands_S0_first__6_BITS_129_TO_119__ETC___d331) ?
!fpu_div_fOperands_S0_first__6_BIT_130_33_EQ_fp_ETC___d335 :
CASE_fpu_div_fOperands_S0D_OUT_BITS_2_TO_0_0__ETC__q9 ;
assign IF_fpu_div_fOperands_S0_first__6_BITS_65_TO_55_ETC___d363 =
(fpu_div_fOperands_S0$D_OUT[65:55] == 11'd0 &&
fpu_div_fOperands_S0$D_OUT[54:3] == 52'd0 ||
fpu_div_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
fpu_div_fOperands_S0$D_OUT[118:67] == 52'd0) ?
11'd2047 :
((fpu_div_fOperands_S0$D_OUT[129:119] == 11'd0 &&
fpu_div_fOperands_S0$D_OUT[118:67] == 52'd0 ||
fpu_div_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
fpu_div_fOperands_S0$D_OUT[54:3] == 52'd0 ||
IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d283) ?
11'd0 :
_theResult___fst_exp__h18518) ;
assign IF_fpu_div_fOperands_S0_first__6_BITS_65_TO_55_ETC___d380 =
(fpu_div_fOperands_S0$D_OUT[65:55] == 11'd0 &&
fpu_div_fOperands_S0$D_OUT[54:3] == 52'd0 ||
fpu_div_fOperands_S0_first__6_BITS_129_TO_119__ETC___d331) ?
52'd0 :
(IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d283 ?
_theResult___fst_sfd__h19008 :
_theResult___fst_sfd__h18519) ;
assign IF_fpu_div_fOperands_S0_first__6_BITS_65_TO_55_ETC___d385 =
(fpu_div_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
fpu_div_fOperands_S0$D_OUT[54:3] != 52'd0 &&
!fpu_div_fOperands_S0$D_OUT[54]) ?
{ fpu_div_fOperands_S0$D_OUT[66:55], sfd__h17988 } :
((fpu_div_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
fpu_div_fOperands_S0$D_OUT[118]) ?
fpu_div_fOperands_S0$D_OUT[130:67] :
((fpu_div_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
fpu_div_fOperands_S0$D_OUT[54]) ?
fpu_div_fOperands_S0$D_OUT[66:3] :
NOT_fpu_div_fOperands_S0_first__6_BITS_129_TO__ETC___d382)) ;
assign IF_fpu_div_fState_S3_first__16_BITS_120_TO_110_ETC___d527 =
(fpu_div_fState_S3$D_OUT[120:110] == 11'd2047) ?
fpu_div_fState_S3$D_OUT[57:56] == 2'b0 &&
!fpu_div_fState_S3$D_OUT[194] :
!fpu_div_fState_S3$D_OUT[194] ;
assign IF_fpu_div_fState_S3_first__16_BITS_120_TO_110_ETC___d851 =
((fpu_div_fState_S3$D_OUT[120:110] == 11'd2047) ?
{ fpu_div_fState_S3$D_OUT[129:128],
fpu_div_fState_S3$D_OUT[57:56] != 2'b0 ||
fpu_div_fState_S3$D_OUT[127],
fpu_div_fState_S3$D_OUT[126],
fpu_div_fState_S3$D_OUT[57:56] != 2'b0 ||
fpu_div_fState_S3$D_OUT[125] } :
fpu_div_fState_S3$D_OUT[129:125]) |
{ 2'd0,
sfdin__h33169[57] &&
IF_IF_fpu_div_fState_S3_first__16_BITS_120_TO__ETC___d573 ==
12'd1023,
_theResult___fst_exp__h41387 == 11'd0 && guard__h32997 != 2'd0,
sfdin__h33169[57] &&
IF_IF_fpu_div_fState_S3_first__16_BITS_120_TO__ETC___d573 ==
12'd1023 } ;
assign IF_fpu_div_fState_S4_first__73_BITS_64_TO_54_7_ETC___d907 =
(fpu_div_fState_S4$D_OUT[64:54] == 11'd0 &&
sfd__h42033[53:52] == 2'b01) ?
11'd1 :
fpu_div_fState_S4$D_OUT[64:54] ;
assign IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1932 =
(fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1926 ||
IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1927 &&
!fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855) ?
63'h7FF8000000000000 :
IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1931 ;
assign IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1938 =
(fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 &&
!fpu_madd_fOperand_S0$D_OUT[118]) ?
{ fpu_madd_fOperand_S0$D_OUT[130:119], sfd__h99405 } :
((fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0 &&
!fpu_madd_fOperand_S0$D_OUT[54]) ?
{ fpu_madd_fOperand_S0$D_OUT[66:55], sfd__h99408 } :
IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1936) ;
assign IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1959 =
{ ((fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd0) ?
13'd7170 :
{ {2{fpu_madd_fOperand_S0D_OUT_BITS_129_TO_119_MIN_ETC__q128[10]}},
fpu_madd_fOperand_S0D_OUT_BITS_129_TO_119_MIN_ETC__q128 }) +
((fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd0) ?
13'd7170 :
{ {2{fpu_madd_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q129[10]}},
fpu_madd_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q129 }),
x__h114243,
x__h114255 } ;
assign IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1861 =
x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608[51] ||
fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
fpu_madd_fOperand_S0$D_OUT[118] ||
fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
fpu_madd_fOperand_S0$D_OUT[54] ||
x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608 == 52'd0 ||
fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1857 ;
assign IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911 =
fpu_madd_fOperand_S0$D_OUT[195] ?
fpu_madd_fOperand_S0$D_OUT[193:131] :
63'd0 ;
assign IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1927 =
x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608 == 52'd0 &&
(fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 ||
fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0) ;
assign IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1947 =
x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608 != 52'd0 &&
!_theResult___fst_sfd__h96608[51] ||
fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 &&
!fpu_madd_fOperand_S0$D_OUT[118] ||
fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0 &&
!fpu_madd_fOperand_S0$D_OUT[54] ||
NOT_IF_fpu_madd_fOperand_S0_first__803_BIT_195_ETC___d1946 ;
assign IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2516 =
fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ?
fpu_madd_fProd_S3$D_OUT != 106'd0 ||
fpu_madd_fState_S3$D_OUT[83] :
fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[1] ;
assign IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2521 =
fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ?
fpu_madd_fProd_S3$D_OUT != 106'd0 ||
fpu_madd_fState_S3$D_OUT[82] :
fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[0] ;
assign IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2536 =
fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ?
(fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ?
63'd0 :
IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2534) :
63'h7FEFFFFFFFFFFFFF ;
assign IF_fpu_madd_fState_S3_first__995_BIT_151_996_T_ETC___d2525 =
fpu_madd_fState_S3$D_OUT[151] ?
fpu_madd_fState_S3$D_OUT[86:82] :
{ IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2503,
IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2506,
NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2523 } ;
assign IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 =
(fpu_madd_fState_S4$D_OUT[128:118] == 11'd0) ?
13'd7170 :
{ {2{fpu_madd_fState_S4D_OUT_BITS_128_TO_118_MINUS_ETC__q26[10]}},
fpu_madd_fState_S4D_OUT_BITS_128_TO_118_MINUS_ETC__q26 } ;
assign IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 =
(fpu_madd_fState_S4$D_OUT[64:54] == 11'd0) ?
13'd7170 :
{ {2{fpu_madd_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q27[10]}},
fpu_madd_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q27 } ;
assign IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 =
(value__h141307[10:0] == 11'd0) ?
12'd3074 :
{ value41307_BITS_10_TO_0_MINUS_1023__q28[10],
value41307_BITS_10_TO_0_MINUS_1023__q28 } ;
assign IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2903 =
IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 -
12'd3074 ;
assign IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d2986 =
(fpu_madd_fState_S8$D_OUT[65:55] == 11'd0 &&
sfd__h142040[53:52] == 2'b01) ?
11'd1 :
fpu_madd_fState_S8$D_OUT[65:55] ;
assign IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d3011 =
(fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ?
fpu_madd_fState_S8$D_OUT[65:55] :
_theResult___fst_exp__h142619 ;
assign IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3060 =
(fpu_madd_fState_S8$D_OUT[67] &&
IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d3011 ==
11'd0 &&
((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ?
fpu_madd_fState_S8$D_OUT[54:3] :
_theResult___fst_sfd__h142620) ==
52'd0 &&
!fpu_madd_fState_S8_first__960_BITS_75_TO_71_03_ETC___d3043[0] &&
fpu_madd_fState_S8$D_OUT[0]) ?
fpu_madd_fState_S8$D_OUT[70:68] == 3'd3 :
((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ?
fpu_madd_fState_S8$D_OUT[66] :
CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127) ;
assign IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3081 =
{ IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3060,
(fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ?
fpu_madd_fState_S8$D_OUT[65:3] :
CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132,
fpu_madd_fState_S8_first__960_BITS_75_TO_71_03_ETC___d3043 } ;
assign IF_fpu_sqr_fOperand_S0_first__059_BITS_65_TO_5_ETC___d1193 =
(fpu_sqr_fOperand_S0$D_OUT[65:55] == 11'd0) ?
(fpu_sqr_fOperand_S0$D_OUT[54] ?
6'd2 :
(fpu_sqr_fOperand_S0$D_OUT[53] ?
6'd3 :
(fpu_sqr_fOperand_S0$D_OUT[52] ?
6'd4 :
(fpu_sqr_fOperand_S0$D_OUT[51] ?
6'd5 :
(fpu_sqr_fOperand_S0$D_OUT[50] ?
6'd6 :
(fpu_sqr_fOperand_S0$D_OUT[49] ?
6'd7 :
(fpu_sqr_fOperand_S0$D_OUT[48] ?
6'd8 :
(fpu_sqr_fOperand_S0$D_OUT[47] ?
6'd9 :
(fpu_sqr_fOperand_S0$D_OUT[46] ?
6'd10 :
(fpu_sqr_fOperand_S0$D_OUT[45] ?
6'd11 :
(fpu_sqr_fOperand_S0$D_OUT[44] ?
6'd12 :
(fpu_sqr_fOperand_S0$D_OUT[43] ?
6'd13 :
(fpu_sqr_fOperand_S0$D_OUT[42] ?
6'd14 :
(fpu_sqr_fOperand_S0$D_OUT[41] ?
6'd15 :
(fpu_sqr_fOperand_S0$D_OUT[40] ?
6'd16 :
(fpu_sqr_fOperand_S0$D_OUT[39] ?
6'd17 :
(fpu_sqr_fOperand_S0$D_OUT[38] ?
6'd18 :
(fpu_sqr_fOperand_S0$D_OUT[37] ?
6'd19 :
(fpu_sqr_fOperand_S0$D_OUT[36] ?
6'd20 :
(fpu_sqr_fOperand_S0$D_OUT[35] ?
6'd21 :
(fpu_sqr_fOperand_S0$D_OUT[34] ?
6'd22 :
(fpu_sqr_fOperand_S0$D_OUT[33] ?
6'd23 :
(fpu_sqr_fOperand_S0$D_OUT[32] ?
6'd24 :
(fpu_sqr_fOperand_S0$D_OUT[31] ?
6'd25 :
(fpu_sqr_fOperand_S0$D_OUT[30] ?
6'd26 :
(fpu_sqr_fOperand_S0$D_OUT[29] ?
6'd27 :
(fpu_sqr_fOperand_S0$D_OUT[28] ?
6'd28 :
(fpu_sqr_fOperand_S0$D_OUT[27] ?
6'd29 :
(fpu_sqr_fOperand_S0$D_OUT[26] ?
6'd30 :
(fpu_sqr_fOperand_S0$D_OUT[25] ?
6'd31 :
(fpu_sqr_fOperand_S0$D_OUT[24] ?
6'd32 :
(fpu_sqr_fOperand_S0$D_OUT[23] ?
6'd33 :
(fpu_sqr_fOperand_S0$D_OUT[22] ?
6'd34 :
(fpu_sqr_fOperand_S0$D_OUT[21] ?
6'd35 :
(fpu_sqr_fOperand_S0$D_OUT[20] ?
6'd36 :
(fpu_sqr_fOperand_S0$D_OUT[19] ?
6'd37 :
(fpu_sqr_fOperand_S0$D_OUT[18] ?
6'd38 :
(fpu_sqr_fOperand_S0$D_OUT[17] ?
6'd39 :
(fpu_sqr_fOperand_S0$D_OUT[16] ?
6'd40 :
(fpu_sqr_fOperand_S0$D_OUT[15] ?
6'd41 :
(fpu_sqr_fOperand_S0$D_OUT[14] ?
6'd42 :
(fpu_sqr_fOperand_S0$D_OUT[13] ?
6'd43 :
(fpu_sqr_fOperand_S0$D_OUT[12] ?
6'd44 :
(fpu_sqr_fOperand_S0$D_OUT[11] ?
6'd45 :
(fpu_sqr_fOperand_S0$D_OUT[10] ?
6'd46 :
(fpu_sqr_fOperand_S0$D_OUT[9] ?
6'd47 :
(fpu_sqr_fOperand_S0$D_OUT[8] ?
6'd48 :
(fpu_sqr_fOperand_S0$D_OUT[7] ?
6'd49 :
(fpu_sqr_fOperand_S0$D_OUT[6] ?
6'd50 :
(fpu_sqr_fOperand_S0$D_OUT[5] ?
6'd51 :
(fpu_sqr_fOperand_S0$D_OUT[4] ?
6'd52 :
(fpu_sqr_fOperand_S0$D_OUT[3] ?
6'd53 :
6'd58)))))))))))))))))))))))))))))))))))))))))))))))))))) :
6'd1 ;
assign IF_fpu_sqr_fOperand_S0_first__059_BITS_65_TO_5_ETC___d1195 =
((fpu_sqr_fOperand_S0$D_OUT[65:55] == 11'd0) ?
13'd7170 :
{ {2{fpu_sqr_fOperand_S0D_OUT_BITS_65_TO_55_MINUS__ETC__q16[10]}},
fpu_sqr_fOperand_S0D_OUT_BITS_65_TO_55_MINUS__ETC__q16 }) -
{ 7'd0,
IF_fpu_sqr_fOperand_S0_first__059_BITS_65_TO_5_ETC___d1193 } ;
assign IF_fpu_sqr_fOperand_S0_first__059_BITS_65_TO_5_ETC___d1212 =
(fpu_sqr_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
fpu_sqr_fOperand_S0$D_OUT[54] ||
fpu_sqr_fOperand_S0$D_OUT[65:55] == 11'd0 &&
fpu_sqr_fOperand_S0$D_OUT[54:3] == 52'd0 ||
fpu_sqr_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
fpu_sqr_fOperand_S0$D_OUT[54:3] == 52'd0 &&
!fpu_sqr_fOperand_S0$D_OUT[66]) ?
{ 1'd1,
fpu_sqr_fOperand_S0$D_OUT[66:3],
130'h00AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } :
(fpu_sqr_fOperand_S0$D_OUT[66] ?
195'h5FFE00000000000020AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA :
{ 70'h155555555555555540,
fpu_sqr_fOperand_S0$D_OUT[2:0],
fpu_sqr_fOperand_S0$D_OUT[66],
x__h52551[10:0],
fpu_sqr_fOperand_S0$D_OUT[54:3],
x__h60693 }) ;
assign IF_fpu_sqr_fOperand_S0_first__059_BITS_65_TO_5_ETC__q17 =
IF_fpu_sqr_fOperand_S0_first__059_BITS_65_TO_5_ETC___d1195[12:1] ;
assign IF_fpu_sqr_fState_S1_first__216_BIT_57_226_THE_ETC___d1342 =
(fpu_sqr_fState_S1$D_OUT[57] ?
7'd0 :
(fpu_sqr_fState_S1$D_OUT[56] ?
7'd1 :
(fpu_sqr_fState_S1$D_OUT[55] ?
7'd2 :
(fpu_sqr_fState_S1$D_OUT[54] ?
7'd3 :
(fpu_sqr_fState_S1$D_OUT[53] ?
7'd4 :
(fpu_sqr_fState_S1$D_OUT[52] ?
7'd5 :
(fpu_sqr_fState_S1$D_OUT[51] ?
7'd6 :
(fpu_sqr_fState_S1$D_OUT[50] ?
7'd7 :
(fpu_sqr_fState_S1$D_OUT[49] ?
7'd8 :
(fpu_sqr_fState_S1$D_OUT[48] ?
7'd9 :
(fpu_sqr_fState_S1$D_OUT[47] ?
7'd10 :
(fpu_sqr_fState_S1$D_OUT[46] ?
7'd11 :
(fpu_sqr_fState_S1$D_OUT[45] ?
7'd12 :
(fpu_sqr_fState_S1$D_OUT[44] ?
7'd13 :
(fpu_sqr_fState_S1$D_OUT[43] ?
7'd14 :
(fpu_sqr_fState_S1$D_OUT[42] ?
7'd15 :
(fpu_sqr_fState_S1$D_OUT[41] ?
7'd16 :
(fpu_sqr_fState_S1$D_OUT[40] ?
7'd17 :
(fpu_sqr_fState_S1$D_OUT[39] ?
7'd18 :
(fpu_sqr_fState_S1$D_OUT[38] ?
7'd19 :
(fpu_sqr_fState_S1$D_OUT[37] ?
7'd20 :
(fpu_sqr_fState_S1$D_OUT[36] ?
7'd21 :
(fpu_sqr_fState_S1$D_OUT[35] ?
7'd22 :
(fpu_sqr_fState_S1$D_OUT[34] ?
7'd23 :
(fpu_sqr_fState_S1$D_OUT[33] ?
7'd24 :
(fpu_sqr_fState_S1$D_OUT[32] ?
7'd25 :
(fpu_sqr_fState_S1$D_OUT[31] ?
7'd26 :
(fpu_sqr_fState_S1$D_OUT[30] ?
7'd27 :
(fpu_sqr_fState_S1$D_OUT[29] ?
7'd28 :
(fpu_sqr_fState_S1$D_OUT[28] ?
7'd29 :
(fpu_sqr_fState_S1$D_OUT[27] ?
7'd30 :
(fpu_sqr_fState_S1$D_OUT[26] ?
7'd31 :
(fpu_sqr_fState_S1$D_OUT[25] ?
7'd32 :
(fpu_sqr_fState_S1$D_OUT[24] ?
7'd33 :
(fpu_sqr_fState_S1$D_OUT[23] ?
7'd34 :
(fpu_sqr_fState_S1$D_OUT[22] ?
7'd35 :
(fpu_sqr_fState_S1$D_OUT[21] ?
7'd36 :
(fpu_sqr_fState_S1$D_OUT[20] ?
7'd37 :
(fpu_sqr_fState_S1$D_OUT[19] ?
7'd38 :
(fpu_sqr_fState_S1$D_OUT[18] ?
7'd39 :
(fpu_sqr_fState_S1$D_OUT[17] ?
7'd40 :
(fpu_sqr_fState_S1$D_OUT[16] ?
7'd41 :
(fpu_sqr_fState_S1$D_OUT[15] ?
7'd42 :
(fpu_sqr_fState_S1$D_OUT[14] ?
7'd43 :
(fpu_sqr_fState_S1$D_OUT[13] ?
7'd44 :
(fpu_sqr_fState_S1$D_OUT[12] ?
7'd45 :
(fpu_sqr_fState_S1$D_OUT[11] ?
7'd46 :
(fpu_sqr_fState_S1$D_OUT[10] ?
7'd47 :
(fpu_sqr_fState_S1$D_OUT[9] ?
7'd48 :
(fpu_sqr_fState_S1$D_OUT[8] ?
7'd49 :
(fpu_sqr_fState_S1$D_OUT[7] ?
7'd50 :
(fpu_sqr_fState_S1$D_OUT[6] ?
7'd51 :
(fpu_sqr_fState_S1$D_OUT[5] ?
7'd52 :
(fpu_sqr_fState_S1$D_OUT[4] ?
7'd53 :
(fpu_sqr_fState_S1$D_OUT[3] ?
7'd54 :
(fpu_sqr_fState_S1$D_OUT[2] ?
7'd55 :
(fpu_sqr_fState_S1$D_OUT[1] ?
7'd56 :
(fpu_sqr_fState_S1$D_OUT[0] ?
7'd57 :
7'd116)))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
7'd1 ;
assign IF_fpu_sqr_fState_S3_first__375_BITS_121_TO_11_ETC___d1389 =
(fpu_sqr_fState_S3$D_OUT[121:111] == 11'd0) ?
12'd3074 :
{ fpu_sqr_fState_S3D_OUT_BITS_121_TO_111_MINUS__ETC__q18[10],
fpu_sqr_fState_S3D_OUT_BITS_121_TO_111_MINUS__ETC__q18 } ;
assign IF_fpu_sqr_fState_S3_first__375_BITS_121_TO_11_ETC___d1632 =
IF_fpu_sqr_fState_S3_first__375_BITS_121_TO_11_ETC___d1389 -
12'd3074 ;
assign IF_fpu_sqr_fState_S3_first__375_BIT_195_376_TH_ETC___d1671 =
fpu_sqr_fState_S3$D_OUT[195] ?
fpu_sqr_fState_S3$D_OUT[128:126] :
{ fpu_sqr_fState_S3$D_OUT[58] &&
IF_fpu_sqr_fState_S3_first__375_BITS_121_TO_11_ETC___d1389 ==
12'd1023,
_theResult___fst_exp__h94753 == 11'd0 &&
guard__h86435 != 2'd0,
fpu_sqr_fState_S3$D_OUT[58] &&
IF_fpu_sqr_fState_S3_first__375_BITS_121_TO_11_ETC___d1389 ==
12'd1023 } ;
assign IF_fpu_sqr_fState_S3_first__375_BIT_58_384_AND_ETC___d1678 =
(fpu_sqr_fState_S3$D_OUT[58] &&
IF_fpu_sqr_fState_S3_first__375_BITS_121_TO_11_ETC___d1389 ==
12'd1023) ?
63'h7FEFFFFFFFFFFFFF :
{ _theResult___fst_exp__h94750, sfdin__h94744[58:7] } ;
assign IF_fpu_sqr_fState_S3_first__375_BIT_58_384_THE_ETC___d1630 =
(fpu_sqr_fState_S3$D_OUT[58] ?
6'd0 :
(fpu_sqr_fState_S3$D_OUT[57] ?
6'd1 :
(fpu_sqr_fState_S3$D_OUT[56] ?
6'd2 :
(fpu_sqr_fState_S3$D_OUT[55] ?
6'd3 :
(fpu_sqr_fState_S3$D_OUT[54] ?
6'd4 :
(fpu_sqr_fState_S3$D_OUT[53] ?
6'd5 :
(fpu_sqr_fState_S3$D_OUT[52] ?
6'd6 :
(fpu_sqr_fState_S3$D_OUT[51] ?
6'd7 :
(fpu_sqr_fState_S3$D_OUT[50] ?
6'd8 :
(fpu_sqr_fState_S3$D_OUT[49] ?
6'd9 :
(fpu_sqr_fState_S3$D_OUT[48] ?
6'd10 :
(fpu_sqr_fState_S3$D_OUT[47] ?
6'd11 :
(fpu_sqr_fState_S3$D_OUT[46] ?
6'd12 :
(fpu_sqr_fState_S3$D_OUT[45] ?
6'd13 :
(fpu_sqr_fState_S3$D_OUT[44] ?
6'd14 :
(fpu_sqr_fState_S3$D_OUT[43] ?
6'd15 :
(fpu_sqr_fState_S3$D_OUT[42] ?
6'd16 :
(fpu_sqr_fState_S3$D_OUT[41] ?
6'd17 :
(fpu_sqr_fState_S3$D_OUT[40] ?
6'd18 :
(fpu_sqr_fState_S3$D_OUT[39] ?
6'd19 :
(fpu_sqr_fState_S3$D_OUT[38] ?
6'd20 :
(fpu_sqr_fState_S3$D_OUT[37] ?
6'd21 :
(fpu_sqr_fState_S3$D_OUT[36] ?
6'd22 :
(fpu_sqr_fState_S3$D_OUT[35] ?
6'd23 :
(fpu_sqr_fState_S3$D_OUT[34] ?
6'd24 :
(fpu_sqr_fState_S3$D_OUT[33] ?
6'd25 :
(fpu_sqr_fState_S3$D_OUT[32] ?
6'd26 :
(fpu_sqr_fState_S3$D_OUT[31] ?
6'd27 :
(fpu_sqr_fState_S3$D_OUT[30] ?
6'd28 :
(fpu_sqr_fState_S3$D_OUT[29] ?
6'd29 :
(fpu_sqr_fState_S3$D_OUT[28] ?
6'd30 :
(fpu_sqr_fState_S3$D_OUT[27] ?
6'd31 :
(fpu_sqr_fState_S3$D_OUT[26] ?
6'd32 :
(fpu_sqr_fState_S3$D_OUT[25] ?
6'd33 :
(fpu_sqr_fState_S3$D_OUT[24] ?
6'd34 :
(fpu_sqr_fState_S3$D_OUT[23] ?
6'd35 :
(fpu_sqr_fState_S3$D_OUT[22] ?
6'd36 :
(fpu_sqr_fState_S3$D_OUT[21] ?
6'd37 :
(fpu_sqr_fState_S3$D_OUT[20] ?
6'd38 :
(fpu_sqr_fState_S3$D_OUT[19] ?
6'd39 :
(fpu_sqr_fState_S3$D_OUT[18] ?
6'd40 :
(fpu_sqr_fState_S3$D_OUT[17] ?
6'd41 :
(fpu_sqr_fState_S3$D_OUT[16] ?
6'd42 :
(fpu_sqr_fState_S3$D_OUT[15] ?
6'd43 :
(fpu_sqr_fState_S3$D_OUT[14] ?
6'd44 :
(fpu_sqr_fState_S3$D_OUT[13] ?
6'd45 :
(fpu_sqr_fState_S3$D_OUT[12] ?
6'd46 :
(fpu_sqr_fState_S3$D_OUT[11] ?
6'd47 :
(fpu_sqr_fState_S3$D_OUT[10] ?
6'd48 :
(fpu_sqr_fState_S3$D_OUT[9] ?
6'd49 :
(fpu_sqr_fState_S3$D_OUT[8] ?
6'd50 :
(fpu_sqr_fState_S3$D_OUT[7] ?
6'd51 :
(fpu_sqr_fState_S3$D_OUT[6] ?
6'd52 :
(fpu_sqr_fState_S3$D_OUT[5] ?
6'd53 :
(fpu_sqr_fState_S3$D_OUT[4] ?
6'd54 :
(fpu_sqr_fState_S3$D_OUT[3] ?
6'd55 :
(fpu_sqr_fState_S3$D_OUT[2] ?
6'd56 :
(fpu_sqr_fState_S3$D_OUT[1] ?
6'd57 :
(fpu_sqr_fState_S3$D_OUT[0] ?
6'd58 :
6'd59))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_fpu_sqr_fState_S4_first__687_BITS_64_TO_54__ETC___d1721 =
(fpu_sqr_fState_S4$D_OUT[64:54] == 11'd0 &&
sfd__h95416[53:52] == 2'b01) ?
11'd1 :
fpu_sqr_fState_S4$D_OUT[64:54] ;
assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 =
((iFifo$D_OUT[102:95] == 8'd0) ?
(iFifo$D_OUT[94] ?
6'd2 :
(iFifo$D_OUT[93] ?
6'd3 :
(iFifo$D_OUT[92] ?
6'd4 :
(iFifo$D_OUT[91] ?
6'd5 :
(iFifo$D_OUT[90] ?
6'd6 :
(iFifo$D_OUT[89] ?
6'd7 :
(iFifo$D_OUT[88] ?
6'd8 :
(iFifo$D_OUT[87] ?
6'd9 :
(iFifo$D_OUT[86] ?
6'd10 :
(iFifo$D_OUT[85] ?
6'd11 :
(iFifo$D_OUT[84] ?
6'd12 :
(iFifo$D_OUT[83] ?
6'd13 :
(iFifo$D_OUT[82] ?
6'd14 :
(iFifo$D_OUT[81] ?
6'd15 :
(iFifo$D_OUT[80] ?
6'd16 :
(iFifo$D_OUT[79] ?
6'd17 :
(iFifo$D_OUT[78] ?
6'd18 :
(iFifo$D_OUT[77] ?
6'd19 :
(iFifo$D_OUT[76] ?
6'd20 :
(iFifo$D_OUT[75] ?
6'd21 :
(iFifo$D_OUT[74] ?
6'd22 :
(iFifo$D_OUT[73] ?
6'd23 :
(iFifo$D_OUT[72] ?
6'd24 :
6'd57))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5148 =
(iFifo$D_OUT[102:95] == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 ?
IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4802 :
IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803) :
(SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 ?
IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5146 :
IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803) ;
assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5376 =
(iFifo$D_OUT[102:95] == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 ?
IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d5347 :
IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348) :
(SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 ?
IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5374 :
IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348) ;
assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5327 =
{ (iFifo$D_OUT[102:95] == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h221052,
(iFifo$D_OUT[102:95] == 8'd255 &&
iFifo$D_OUT[94:72] != 23'd0) ?
_theResult___snd_fst_sfd__h183124 :
_theResult___fst_sfd__h221056 } ;
assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5328 =
{ (iFifo$D_OUT[102:95] == 8'd255 &&
iFifo$D_OUT[94:72] != 23'd0 ||
(iFifo$D_OUT[102:95] == 8'd255 ||
iFifo$D_OUT[102:95] == 8'd0) &&
iFifo$D_OUT[94:72] == 23'd0) ?
iFifo$D_OUT[103] :
IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5148,
IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5327 } ;
assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5378 =
{ (iFifo$D_OUT[102:95] == 8'd255 &&
iFifo$D_OUT[94:72] != 23'd0 ||
(iFifo$D_OUT[102:95] == 8'd255 ||
iFifo$D_OUT[102:95] == 8'd0) &&
iFifo$D_OUT[94:72] == 23'd0) ?
!iFifo$D_OUT[103] :
IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5376,
IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5327 } ;
assign IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 =
((iFifo$D_OUT[167:160] == 8'd0) ?
(iFifo$D_OUT[159] ?
6'd2 :
(iFifo$D_OUT[158] ?
6'd3 :
(iFifo$D_OUT[157] ?
6'd4 :
(iFifo$D_OUT[156] ?
6'd5 :
(iFifo$D_OUT[155] ?
6'd6 :
(iFifo$D_OUT[154] ?
6'd7 :
(iFifo$D_OUT[153] ?
6'd8 :
(iFifo$D_OUT[152] ?
6'd9 :
(iFifo$D_OUT[151] ?
6'd10 :
(iFifo$D_OUT[150] ?
6'd11 :
(iFifo$D_OUT[149] ?
6'd12 :
(iFifo$D_OUT[148] ?
6'd13 :
(iFifo$D_OUT[147] ?
6'd14 :
(iFifo$D_OUT[146] ?
6'd15 :
(iFifo$D_OUT[145] ?
6'd16 :
(iFifo$D_OUT[144] ?
6'd17 :
(iFifo$D_OUT[143] ?
6'd18 :
(iFifo$D_OUT[142] ?
6'd19 :
(iFifo$D_OUT[141] ?
6'd20 :
(iFifo$D_OUT[140] ?
6'd21 :
(iFifo$D_OUT[139] ?
6'd22 :
(iFifo$D_OUT[138] ?
6'd23 :
(iFifo$D_OUT[137] ?
6'd24 :
6'd57))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3665 =
(iFifo$D_OUT[167:160] == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189 ?
IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d3317 :
IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320) :
(SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324 ?
IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3663 :
IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320) ;
assign IF_iFifo_first__087_BITS_167_TO_160_130_EQ_255_ETC___d3846 =
{ (iFifo$D_OUT[167:160] == 8'd255 &&
iFifo$D_OUT[159:137] != 23'd0 ||
(iFifo$D_OUT[167:160] == 8'd255 ||
iFifo$D_OUT[167:160] == 8'd0) &&
iFifo$D_OUT[159:137] == 23'd0) ?
iFifo$D_OUT[168] :
IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3665,
(iFifo$D_OUT[167:160] == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h182414,
(iFifo$D_OUT[167:160] == 8'd255 &&
iFifo$D_OUT[159:137] != 23'd0) ?
_theResult___snd_fst_sfd__h144484 :
_theResult___fst_sfd__h182418 } ;
assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 =
((iFifo$D_OUT[37:30] == 8'd0) ?
(iFifo$D_OUT[29] ?
6'd2 :
(iFifo$D_OUT[28] ?
6'd3 :
(iFifo$D_OUT[27] ?
6'd4 :
(iFifo$D_OUT[26] ?
6'd5 :
(iFifo$D_OUT[25] ?
6'd6 :
(iFifo$D_OUT[24] ?
6'd7 :
(iFifo$D_OUT[23] ?
6'd8 :
(iFifo$D_OUT[22] ?
6'd9 :
(iFifo$D_OUT[21] ?
6'd10 :
(iFifo$D_OUT[20] ?
6'd11 :
(iFifo$D_OUT[19] ?
6'd12 :
(iFifo$D_OUT[18] ?
6'd13 :
(iFifo$D_OUT[17] ?
6'd14 :
(iFifo$D_OUT[16] ?
6'd15 :
(iFifo$D_OUT[15] ?
6'd16 :
(iFifo$D_OUT[14] ?
6'd17 :
(iFifo$D_OUT[13] ?
6'd18 :
(iFifo$D_OUT[12] ?
6'd19 :
(iFifo$D_OUT[11] ?
6'd20 :
(iFifo$D_OUT[10] ?
6'd21 :
(iFifo$D_OUT[9] ?
6'd22 :
(iFifo$D_OUT[8] ?
6'd23 :
(iFifo$D_OUT[7] ?
6'd24 :
6'd57))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4373 =
(iFifo$D_OUT[37:30] == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 ?
IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4027 :
IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028) :
(SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 ?
IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4371 :
IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028) ;
assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4610 =
(iFifo$D_OUT[37:30] == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 ?
IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4581 :
IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582) :
(SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 ?
IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4608 :
IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582) ;
assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4552 =
{ (iFifo$D_OUT[37:30] == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h259991,
(iFifo$D_OUT[37:30] == 8'd255 && iFifo$D_OUT[29:7] != 23'd0) ?
_theResult___snd_fst_sfd__h222063 :
_theResult___fst_sfd__h259995 } ;
assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4553 =
{ (iFifo$D_OUT[37:30] == 8'd255 && iFifo$D_OUT[29:7] != 23'd0 ||
(iFifo$D_OUT[37:30] == 8'd255 ||
iFifo$D_OUT[37:30] == 8'd0) &&
iFifo$D_OUT[29:7] == 23'd0) ?
iFifo$D_OUT[38] :
IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4373,
IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4552 } ;
assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4612 =
{ (iFifo$D_OUT[37:30] == 8'd255 && iFifo$D_OUT[29:7] != 23'd0 ||
(iFifo$D_OUT[37:30] == 8'd255 ||
iFifo$D_OUT[37:30] == 8'd0) &&
iFifo$D_OUT[29:7] == 23'd0) ?
!iFifo$D_OUT[38] :
IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4610,
IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4552 } ;
assign IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330 =
iFifo$D_OUT[136] ?
IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5328 :
iFifo$D_OUT[135:72] ;
assign IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848 =
iFifo$D_OUT[201] ?
IF_iFifo_first__087_BITS_167_TO_160_130_EQ_255_ETC___d3846 :
iFifo$D_OUT[200:137] ;
assign IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4555 =
iFifo$D_OUT[71] ?
IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4553 :
iFifo$D_OUT[70:7] ;
assign IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618 =
iFifo$D_OUT[71] ?
IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4612 :
{ iFifo$D_OUT[71] || !iFifo$D_OUT[70], iFifo$D_OUT[69:7] } ;
assign IF_isDoubleFifo_first__407_THEN_IF_isNegateFif_ETC___d6657 =
isDoubleFifo$D_OUT ?
{ isNegateFifo$D_OUT ^ resWire$wget[68], resWire$wget[67:5] } :
{ 32'hAAAAAAAA,
IF_isNegateFifo_first__409_THEN_IF_resWire_wge_ETC___d6424,
exp__h304742,
sfd__h304743 } ;
assign IF_isNegateFifo_first__409_THEN_IF_resWire_wge_ETC___d6424 =
isNegateFifo$D_OUT ?
((resWire$wget[67:57] == 11'd2047 &&
resWire$wget[56:5] != 52'd0 ||
(resWire$wget[67:57] == 11'd2047 ||
resWire$wget[67:57] == 11'd0) &&
resWire$wget[56:5] == 52'd0) ?
!resWire$wget[68] :
IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6377) :
((resWire$wget[67:57] == 11'd2047 &&
resWire$wget[56:5] != 52'd0 ||
(resWire$wget[67:57] == 11'd2047 ||
resWire$wget[67:57] == 11'd0) &&
resWire$wget[56:5] == 52'd0) ?
resWire$wget[68] :
IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6422) ;
assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 =
((resWire$wget[67:57] == 11'd0) ?
(resWire$wget[56] ?
6'd2 :
(resWire$wget[55] ?
6'd3 :
(resWire$wget[54] ?
6'd4 :
(resWire$wget[53] ?
6'd5 :
(resWire$wget[52] ?
6'd6 :
(resWire$wget[51] ?
6'd7 :
(resWire$wget[50] ?
6'd8 :
(resWire$wget[49] ?
6'd9 :
(resWire$wget[48] ?
6'd10 :
(resWire$wget[47] ?
6'd11 :
(resWire$wget[46] ?
6'd12 :
(resWire$wget[45] ?
6'd13 :
(resWire$wget[44] ?
6'd14 :
(resWire$wget[43] ?
6'd15 :
(resWire$wget[42] ?
6'd16 :
(resWire$wget[41] ?
6'd17 :
(resWire$wget[40] ?
6'd18 :
(resWire$wget[39] ?
6'd19 :
(resWire$wget[38] ?
6'd20 :
(resWire$wget[37] ?
6'd21 :
(resWire$wget[36] ?
6'd22 :
(resWire$wget[35] ?
6'd23 :
(resWire$wget[34] ?
6'd24 :
(resWire$wget[33] ?
6'd25 :
(resWire$wget[32] ?
6'd26 :
(resWire$wget[31] ?
6'd27 :
(resWire$wget[30] ?
6'd28 :
(resWire$wget[29] ?
6'd29 :
(resWire$wget[28] ?
6'd30 :
(resWire$wget[27] ?
6'd31 :
(resWire$wget[26] ?
6'd32 :
(resWire$wget[25] ?
6'd33 :
(resWire$wget[24] ?
6'd34 :
(resWire$wget[23] ?
6'd35 :
(resWire$wget[22] ?
6'd36 :
(resWire$wget[21] ?
6'd37 :
(resWire$wget[20] ?
6'd38 :
(resWire$wget[19] ?
6'd39 :
(resWire$wget[18] ?
6'd40 :
(resWire$wget[17] ?
6'd41 :
(resWire$wget[16] ?
6'd42 :
(resWire$wget[15] ?
6'd43 :
(resWire$wget[14] ?
6'd44 :
(resWire$wget[13] ?
6'd45 :
(resWire$wget[12] ?
6'd46 :
(resWire$wget[11] ?
6'd47 :
(resWire$wget[10] ?
6'd48 :
(resWire$wget[9] ?
6'd49 :
(resWire$wget[8] ?
6'd50 :
(resWire$wget[7] ?
6'd51 :
(resWire$wget[6] ?
6'd52 :
(resWire$wget[5] ?
6'd53 :
6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6377 =
(resWire$wget[67:57] == 11'd0) ?
(_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ?
IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6025 :
IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028) :
(SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ?
IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6375 :
IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028) ;
assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6422 =
(resWire$wget[67:57] == 11'd0) ?
(_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ?
IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6399 :
IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400) :
(SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ?
IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6420 :
IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400) ;
assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6709 =
(resWire$wget[67:57] == 11'd0) ?
_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6691 :
SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 &&
SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[4] ;
assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6720 =
(resWire$wget[67:57] == 11'd0) ?
_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6716 :
SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 &&
SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[3] ;
assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6736 =
(resWire$wget[67:57] == 11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6728 :
!SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ||
IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6734 ;
assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6749 =
(resWire$wget[67:57] == 11'd0) ?
_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6743 :
SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 &&
IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6747 ;
assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6762 =
(resWire$wget[67:57] == 11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6756 :
!SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ||
IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6760 ;
assign IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1002 =
rg_index_1_87_ULE_58___d991 ? _theResult___fst__h43537 : rg_b ;
assign IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1022 =
rg_index_1_87_ULE_58___d991 ?
_theResult___snd_snd_snd__h43542 :
rg_r_1 ;
assign IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1026 =
rg_index_1_87_ULE_58___d991 ?
IF_rg_res_94_BIT_116_95_THEN_rg_res_94_BITS_11_ETC___d1025 :
rg_res[115:0] ;
assign IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1036 =
rg_index_1_87_ULE_58___d991 ?
_theResult___snd_fst__h43539 :
rg_s ;
assign IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1038 =
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1036 <
sum__h43732 ;
assign IF_rg_index_1_87_ULE_58_91_THEN_NOT_rg_b_92_EQ_ETC___d1009 =
rg_index_1_87_ULE_58___d991 ?
rg_b != 116'd0 && !rg_res[116] :
!rg_res[116] ;
assign IF_rg_index_1_87_ULE_58_91_THEN_rg_b_92_EQ_0_9_ETC___d997 =
rg_index_1_87_ULE_58___d991 ?
rg_b == 116'd0 || rg_res[116] :
rg_res[116] ;
assign IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22 =
rg_index_ULE_57___d7 ?
(rg_r[115] ?
{ rg_r[114:0], 1'd0 } + b__h31634 :
{ rg_r[114:0], 1'd0 } - b__h31634) :
rg_r ;
assign IF_rg_index_ULE_57_THEN_rg_q_BITS_56_TO_0_CONC_ETC___d14 =
rg_index_ULE_57___d7 ? { rg_q[56:0], !rg_r[115] } : rg_q ;
assign IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_89_ETC__q10 =
rg_r[115] ?
rg_q_PLUS_NEG_INV_rg_q_89_90___d491 - 58'd1 :
rg_q_PLUS_NEG_INV_rg_q_89_90___d491 ;
assign IF_rg_res_94_BIT_116_95_THEN_rg_res_94_BITS_11_ETC___d1025 =
rg_res[116] ?
rg_res[115:0] :
((rg_b == 116'd0) ? rg_r_1 : rg_res[115:0]) ;
assign IF_sfdin11482_BIT_4_THEN_2_ELSE_0__q98 =
sfdin__h211482[4] ? 2'd2 : 2'd0 ;
assign IF_sfdin1378_BIT_5_THEN_2_ELSE_0__q13 =
sfdin__h41378[5] ? 2'd2 : 2'd0 ;
assign IF_sfdin30943_BIT_53_THEN_2_ELSE_0__q25 =
sfdin__h130943[53] ? 2'd2 : 2'd0 ;
assign IF_sfdin41369_BIT_4_THEN_2_ELSE_0__q30 =
sfdin__h141369[4] ? 2'd2 : 2'd0 ;
assign IF_sfdin4744_BIT_6_THEN_2_ELSE_0__q20 =
sfdin__h94744[6] ? 2'd2 : 2'd0 ;
assign IF_sfdin50421_BIT_4_THEN_2_ELSE_0__q65 =
sfdin__h250421[4] ? 2'd2 : 2'd0 ;
assign IF_sfdin72844_BIT_4_THEN_2_ELSE_0__q38 =
sfdin__h172844[4] ? 2'd2 : 2'd0 ;
assign IF_sfdin77716_BIT_33_THEN_2_ELSE_0__q134 =
sfdin__h277716[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin95482_BIT_33_THEN_2_ELSE_0__q140 =
sfdin__h295482[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd01923_BIT_4_THEN_2_ELSE_0__q94 =
_theResult___snd__h201923[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd04119_BIT_33_THEN_2_ELSE_0__q143 =
_theResult___snd__h304119[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd20235_BIT_4_THEN_2_ELSE_0__q101 =
_theResult___snd__h220235[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd40862_BIT_4_THEN_2_ELSE_0__q61 =
_theResult___snd__h240862[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd59174_BIT_4_THEN_2_ELSE_0__q68 =
_theResult___snd__h259174[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd63285_BIT_4_THEN_2_ELSE_0__q34 =
_theResult___snd__h163285[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd81597_BIT_4_THEN_2_ELSE_0__q41 =
_theResult___snd__h181597[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd86329_BIT_33_THEN_2_ELSE_0__q136 =
_theResult___snd__h286329[33] ? 2'd2 : 2'd0 ;
assign NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6728 =
!_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ||
(_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[2] :
_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[2]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6756 =
!_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ||
(_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[0] :
_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[0]) ;
assign NOT_IF_fpu_madd_fOperand_S0_first__803_BIT_195_ETC___d1946 =
(x__h96539 != 11'd2047 || !_theResult___fst_sfd__h96608[51]) &&
(fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd2047 ||
!fpu_madd_fOperand_S0$D_OUT[118]) &&
(fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd2047 ||
!fpu_madd_fOperand_S0$D_OUT[54]) &&
(fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1926 ||
IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1927 &&
!fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855) ;
assign NOT_fpu_div_fOperands_S0_first__6_BITS_129_TO__ETC___d330 =
(fpu_div_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
fpu_div_fOperands_S0$D_OUT[118:67] != 52'd0 ||
fpu_div_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
fpu_div_fOperands_S0$D_OUT[54:3] != 52'd0) &&
(fpu_div_fOperands_S0$D_OUT[129:119] != 11'd0 ||
fpu_div_fOperands_S0$D_OUT[118:67] != 52'd0 ||
fpu_div_fOperands_S0$D_OUT[65:55] != 11'd0 ||
fpu_div_fOperands_S0$D_OUT[54:3] != 52'd0) ;
assign NOT_fpu_div_fOperands_S0_first__6_BITS_129_TO__ETC___d382 =
{ NOT_fpu_div_fOperands_S0_first__6_BITS_129_TO__ETC___d330 &&
IF_fpu_div_fOperands_S0_first__6_BITS_65_TO_55_ETC___d352,
IF_fpu_div_fOperands_S0_first__6_BITS_65_TO_55_ETC___d363,
fpu_div_fOperands_S0_first__6_BITS_129_TO_119__ETC___d366 ?
52'h8000000000000 :
IF_fpu_div_fOperands_S0_first__6_BITS_65_TO_55_ETC___d380 } ;
assign NOT_fpu_div_fOperands_S0_first__6_BITS_65_TO_5_ETC___d411 =
(fpu_div_fOperands_S0$D_OUT[65:55] != 11'd0 ||
fpu_div_fOperands_S0$D_OUT[54:3] != 52'd0) &&
(fpu_div_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
fpu_div_fOperands_S0$D_OUT[118:67] != 52'd0) &&
(fpu_div_fOperands_S0$D_OUT[129:119] != 11'd0 ||
fpu_div_fOperands_S0$D_OUT[118:67] != 52'd0) &&
(fpu_div_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
fpu_div_fOperands_S0$D_OUT[54:3] != 52'd0) &&
IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d283 &&
IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d285 ;
assign NOT_fpu_div_fOperands_S0_first__6_BITS_65_TO_5_ETC___d418 =
(fpu_div_fOperands_S0$D_OUT[65:55] != 11'd0 ||
fpu_div_fOperands_S0$D_OUT[54:3] != 52'd0) &&
(fpu_div_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
fpu_div_fOperands_S0$D_OUT[118:67] != 52'd0) &&
(fpu_div_fOperands_S0$D_OUT[129:119] != 11'd0 ||
fpu_div_fOperands_S0$D_OUT[118:67] != 52'd0) &&
(fpu_div_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
fpu_div_fOperands_S0$D_OUT[54:3] != 52'd0) &&
(!IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d283 ||
IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d285) ;
assign NOT_fpu_madd_fOperand_S0_first__803_BITS_129_T_ETC___d1923 =
(fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd2047 ||
fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 ||
fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd0 ||
fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0) &&
(fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd0 ||
fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 ||
fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd2047 ||
fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0) &&
(x__h96539 != 11'd2047 ||
_theResult___fst_sfd__h96608 != 52'd0 ||
(fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd2047 ||
fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0) &&
(fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd2047 ||
fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0) ||
fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855) &&
IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1922 ;
assign NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854 =
fpu_madd_fOperand_S0$D_OUT[130] !=
fpu_madd_fOperand_S0$D_OUT[66] ;
assign NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2510 =
!fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ||
(fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ?
fpu_madd_fState_S3$D_OUT[84] :
fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[2]) ;
assign NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2523 =
{ NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2510,
fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ?
IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2516 :
fpu_madd_fState_S3$D_OUT[83],
!fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ||
IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2521 } ;
assign NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 =
!fpu_madd_fState_S4$D_OUT[130] ||
(IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 ^
13'h1000) >
(IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 ^
13'h1000) ||
IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 ==
IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 &&
sfdBC__h131578 > sfdA__h131577 ;
assign NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244 =
!iFifo$D_OUT[158] && !iFifo$D_OUT[157] && !iFifo$D_OUT[156] &&
!iFifo$D_OUT[155] &&
!iFifo$D_OUT[154] &&
!iFifo$D_OUT[153] &&
!iFifo$D_OUT[152] &&
!iFifo$D_OUT[151] &&
!iFifo$D_OUT[150] &&
!iFifo$D_OUT[149] &&
!iFifo$D_OUT[148] &&
!iFifo$D_OUT[147] &&
!iFifo$D_OUT[146] &&
!iFifo$D_OUT[145] &&
!iFifo$D_OUT[144] &&
!iFifo$D_OUT[143] &&
!iFifo$D_OUT[142] &&
!iFifo$D_OUT[141] &&
!iFifo$D_OUT[140] &&
!iFifo$D_OUT[139] &&
!iFifo$D_OUT[138] &&
!iFifo$D_OUT[137] ;
assign NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955 =
!iFifo$D_OUT[28] && !iFifo$D_OUT[27] && !iFifo$D_OUT[26] &&
!iFifo$D_OUT[25] &&
!iFifo$D_OUT[24] &&
!iFifo$D_OUT[23] &&
!iFifo$D_OUT[22] &&
!iFifo$D_OUT[21] &&
!iFifo$D_OUT[20] &&
!iFifo$D_OUT[19] &&
!iFifo$D_OUT[18] &&
!iFifo$D_OUT[17] &&
!iFifo$D_OUT[16] &&
!iFifo$D_OUT[15] &&
!iFifo$D_OUT[14] &&
!iFifo$D_OUT[13] &&
!iFifo$D_OUT[12] &&
!iFifo$D_OUT[11] &&
!iFifo$D_OUT[10] &&
!iFifo$D_OUT[9] &&
!iFifo$D_OUT[8] &&
!iFifo$D_OUT[7] ;
assign NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730 =
!iFifo$D_OUT[93] && !iFifo$D_OUT[92] && !iFifo$D_OUT[91] &&
!iFifo$D_OUT[90] &&
!iFifo$D_OUT[89] &&
!iFifo$D_OUT[88] &&
!iFifo$D_OUT[87] &&
!iFifo$D_OUT[86] &&
!iFifo$D_OUT[85] &&
!iFifo$D_OUT[84] &&
!iFifo$D_OUT[83] &&
!iFifo$D_OUT[82] &&
!iFifo$D_OUT[81] &&
!iFifo$D_OUT[80] &&
!iFifo$D_OUT[79] &&
!iFifo$D_OUT[78] &&
!iFifo$D_OUT[77] &&
!iFifo$D_OUT[76] &&
!iFifo$D_OUT[75] &&
!iFifo$D_OUT[74] &&
!iFifo$D_OUT[73] &&
!iFifo$D_OUT[72] ;
assign NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927 =
!resWire$wget[56] && !resWire$wget[55] && !resWire$wget[54] &&
!resWire$wget[53] &&
!resWire$wget[52] &&
!resWire$wget[51] &&
!resWire$wget[50] &&
!resWire$wget[49] &&
!resWire$wget[48] &&
!resWire$wget[47] &&
!resWire$wget[46] &&
!resWire$wget[45] &&
!resWire$wget[44] &&
!resWire$wget[43] &&
!resWire$wget[42] &&
!resWire$wget[41] &&
!resWire$wget[40] &&
!resWire$wget[39] &&
!resWire$wget[38] &&
!resWire$wget[37] &&
!resWire$wget[36] &&
!resWire$wget[35] &&
!resWire$wget[34] &&
!resWire$wget[33] &&
!resWire$wget[32] &&
!resWire$wget[31] &&
!resWire$wget[30] &&
!resWire$wget[29] &&
!resWire$wget[28] &&
!resWire$wget[27] &&
!resWire$wget[26] &&
!resWire$wget[25] &&
!resWire$wget[24] &&
!resWire$wget[23] &&
!resWire$wget[22] &&
!resWire$wget[21] &&
!resWire$wget[20] &&
!resWire$wget[19] &&
!resWire$wget[18] &&
!resWire$wget[17] &&
!resWire$wget[16] &&
!resWire$wget[15] &&
!resWire$wget[14] &&
!resWire$wget[13] &&
!resWire$wget[12] &&
!resWire$wget[11] &&
!resWire$wget[10] &&
!resWire$wget[9] &&
!resWire$wget[8] &&
!resWire$wget[7] &&
!resWire$wget[6] &&
!resWire$wget[5] ;
assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 =
{ {4{iFifoD_OUT_BITS_102_TO_95_MINUS_127__q95[7]}},
iFifoD_OUT_BITS_102_TO_95_MINUS_127__q95 } ;
assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 =
(SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 ^
12'h800) <=
12'd3071 ;
assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 =
(SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 ^
12'h800) <
12'd1026 ;
assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96 =
SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 +
12'd1023 ;
assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q99 =
SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] -
11'd1023 ;
assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 =
{ {4{iFifoD_OUT_BITS_167_TO_160_MINUS_127__q35[7]}},
iFifoD_OUT_BITS_167_TO_160_MINUS_127__q35 } ;
assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324 =
(SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 ^
12'h800) <=
12'd3071 ;
assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325 =
(SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 ^
12'h800) <
12'd1026 ;
assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36 =
SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 +
12'd1023 ;
assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q39 =
SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] -
11'd1023 ;
assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 =
{ {4{iFifoD_OUT_BITS_37_TO_30_MINUS_127__q62[7]}},
iFifoD_OUT_BITS_37_TO_30_MINUS_127__q62 } ;
assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 =
(SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 ^
12'h800) <=
12'd3071 ;
assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 =
(SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 ^
12'h800) <
12'd1026 ;
assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63 =
SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 +
12'd1023 ;
assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q66 =
SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] -
11'd1023 ;
assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 =
{ resWirewget_BITS_67_TO_57_MINUS_1023__q137[10],
resWirewget_BITS_67_TO_57_MINUS_1023__q137 } ;
assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 =
(SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 ^
12'h800) <=
12'd2175 ;
assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 =
(SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 ^
12'h800) <
12'd1922 ;
assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138 =
SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 +
12'd127 ;
assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q141 =
SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] -
8'd127 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d5769 =
({ 3'd0,
IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676 =
{ 3'd0,
_theResult___fst_exp__h277722 == 8'd0 &&
(sfdin__h277716[56:34] == 23'd0 || guard__h269623 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h278319 == 8'd255 &&
_theResult___fst_sfd__h278320 == 23'd0,
1'd0,
_theResult___fst_exp__h277722 != 8'd255 &&
guard__h269623 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d3574 =
({ 6'd0,
IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572 } ^
12'h800) <=
12'd2048 ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d4282 =
({ 6'd0,
IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280 } ^
12'h800) <=
12'd2048 ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d5057 =
({ 6'd0,
IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055 } ^
12'h800) <=
12'd2048 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6280 =
({ 3'd0,
IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705 =
{ 3'd0,
_theResult___fst_exp__h295488 == 8'd0 &&
(sfdin__h295482[56:34] == 23'd0 || guard__h287260 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h296085 == 8'd255 &&
_theResult___fst_sfd__h296086 == 23'd0,
1'd0,
_theResult___fst_exp__h295488 != 8'd255 &&
guard__h287260 != 2'b0 } ;
assign _0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S3_f_ETC___d2463 =
({ 5'd0,
IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460 } ^
12'h800) <=
(IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2462 ^
12'h800) ;
assign _0_CONCAT_IF_IF_fpu_div_fState_S3_first__16_BIT_ETC___d813 =
({ 6'd0,
IF_IF_fpu_div_fState_S3_first__16_BITS_120_TO__ETC___d810 } ^
12'h800) <=
(IF_IF_fpu_div_fState_S3_first__16_BITS_120_TO__ETC___d812 ^
12'h800) ;
assign _0_CONCAT_IF_IF_fpu_madd_fState_S7_first__651_B_ETC___d2904 =
({ 6'd0,
IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901 } ^
12'h800) <=
(IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2903 ^
12'h800) ;
assign _0_CONCAT_IF_fpu_sqr_fState_S3_first__375_BIT_5_ETC___d1633 =
({ 6'd0,
IF_fpu_sqr_fState_S3_first__375_BIT_58_384_THE_ETC___d1630 } ^
12'h800) <=
(IF_fpu_sqr_fState_S3_first__375_BITS_121_TO_11_ETC___d1632 ^
12'h800) ;
assign _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d4759 =
({ 6'd0,
IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 } ^
12'h800) <=
12'd2944 ;
assign _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d5107 =
({ 6'd0,
IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 } ^
12'h800) <=
(IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5106 ^
12'h800) ;
assign _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3273 =
({ 6'd0,
IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 } ^
12'h800) <=
12'd2944 ;
assign _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3624 =
({ 6'd0,
IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 } ^
12'h800) <=
(IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3623 ^
12'h800) ;
assign _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d3984 =
({ 6'd0,
IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 } ^
12'h800) <=
12'd2944 ;
assign _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d4332 =
({ 6'd0,
IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 } ^
12'h800) <=
(IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4331 ^
12'h800) ;
assign _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d5984 =
({ 3'd0,
IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 } ^
9'h100) <=
9'd384 ;
assign _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6333 =
({ 3'd0,
IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 } ^
9'h100) <=
(IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6332 ^
9'h100) ;
assign _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688 =
{ 3'd0,
_theResult___fst_exp__h286378 == 8'd0 &&
guard__h278330 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h286901 == 8'd255 &&
_theResult___fst_sfd__h286902 == 23'd0,
1'd0,
_theResult___fst_exp__h286378 != 8'd255 &&
guard__h278330 != 2'b0 } ;
assign _0b0_CONCAT_NOT_iFifo_first__087_BITS_102_TO_95_ETC___d4813 =
sfd__h183174 >>
_3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809 ;
assign _0b0_CONCAT_NOT_iFifo_first__087_BITS_167_TO_16_ETC___d3330 =
sfd__h144534 >>
_3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326 ;
assign _0b0_CONCAT_NOT_iFifo_first__087_BITS_37_TO_30__ETC___d4038 =
sfd__h222113 >>
_3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034 ;
assign _0b0_CONCAT_NOT_resWire_wget__410_BITS_67_TO_57_ETC___d6038 =
sfd__h262011 >>
_3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034 ;
assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5531 =
12'd3074 -
{ 6'd0,
resWire$wget[56] ?
6'd0 :
(resWire$wget[55] ?
6'd1 :
(resWire$wget[54] ?
6'd2 :
(resWire$wget[53] ?
6'd3 :
(resWire$wget[52] ?
6'd4 :
(resWire$wget[51] ?
6'd5 :
(resWire$wget[50] ?
6'd6 :
(resWire$wget[49] ?
6'd7 :
(resWire$wget[48] ?
6'd8 :
(resWire$wget[47] ?
6'd9 :
(resWire$wget[46] ?
6'd10 :
(resWire$wget[45] ?
6'd11 :
(resWire$wget[44] ?
6'd12 :
(resWire$wget[43] ?
6'd13 :
(resWire$wget[42] ?
6'd14 :
(resWire$wget[41] ?
6'd15 :
(resWire$wget[40] ?
6'd16 :
(resWire$wget[39] ?
6'd17 :
(resWire$wget[38] ?
6'd18 :
(resWire$wget[37] ?
6'd19 :
(resWire$wget[36] ?
6'd20 :
(resWire$wget[35] ?
6'd21 :
(resWire$wget[34] ?
6'd22 :
(resWire$wget[33] ?
6'd23 :
(resWire$wget[32] ?
6'd24 :
(resWire$wget[31] ?
6'd25 :
(resWire$wget[30] ?
6'd26 :
(resWire$wget[29] ?
6'd27 :
(resWire$wget[28] ?
6'd28 :
(resWire$wget[27] ?
6'd29 :
(resWire$wget[26] ?
6'd30 :
(resWire$wget[25] ?
6'd31 :
(resWire$wget[24] ?
6'd32 :
(resWire$wget[23] ?
6'd33 :
(resWire$wget[22] ?
6'd34 :
(resWire$wget[21] ?
6'd35 :
(resWire$wget[20] ?
6'd36 :
(resWire$wget[19] ?
6'd37 :
(resWire$wget[18] ?
6'd38 :
(resWire$wget[17] ?
6'd39 :
(resWire$wget[16] ?
6'd40 :
(resWire$wget[15] ?
6'd41 :
(resWire$wget[14] ?
6'd42 :
(resWire$wget[13] ?
6'd43 :
(resWire$wget[12] ?
6'd44 :
(resWire$wget[11] ?
6'd45 :
(resWire$wget[10] ?
6'd46 :
(resWire$wget[9] ?
6'd47 :
(resWire$wget[8] ?
6'd48 :
(resWire$wget[7] ?
6'd49 :
(resWire$wget[6] ?
6'd50 :
(resWire$wget[5] ?
6'd51 :
6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 =
(_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5531 ^
12'h800) <=
12'd2175 ;
assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 =
(_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5531 ^
12'h800) <
12'd1922 ;
assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6691 =
_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 &&
(_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[4] :
_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[4]) ;
assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6716 =
_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 &&
(_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[3] :
_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[3]) ;
assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6743 =
_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 &&
(_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[1] :
_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[1]) ;
assign _3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809 =
12'd3074 -
SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 ;
assign _3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326 =
12'd3074 -
SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 ;
assign _3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034 =
12'd3074 -
SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 ;
assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3188 =
12'd3970 -
{ 7'd0,
iFifo$D_OUT[159] ?
5'd0 :
(iFifo$D_OUT[158] ?
5'd1 :
(iFifo$D_OUT[157] ?
5'd2 :
(iFifo$D_OUT[156] ?
5'd3 :
(iFifo$D_OUT[155] ?
5'd4 :
(iFifo$D_OUT[154] ?
5'd5 :
(iFifo$D_OUT[153] ?
5'd6 :
(iFifo$D_OUT[152] ?
5'd7 :
(iFifo$D_OUT[151] ?
5'd8 :
(iFifo$D_OUT[150] ?
5'd9 :
(iFifo$D_OUT[149] ?
5'd10 :
(iFifo$D_OUT[148] ?
5'd11 :
(iFifo$D_OUT[147] ?
5'd12 :
(iFifo$D_OUT[146] ?
5'd13 :
(iFifo$D_OUT[145] ?
5'd14 :
(iFifo$D_OUT[144] ?
5'd15 :
(iFifo$D_OUT[143] ?
5'd16 :
(iFifo$D_OUT[142] ?
5'd17 :
(iFifo$D_OUT[141] ?
5'd18 :
(iFifo$D_OUT[140] ?
5'd19 :
(iFifo$D_OUT[139] ?
5'd20 :
(iFifo$D_OUT[138] ?
5'd21 :
(iFifo$D_OUT[137] ?
5'd22 :
5'd23)))))))))))))))))))))) } ;
assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189 =
(_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3188 ^
12'h800) <=
12'd3071 ;
assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190 =
(_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3188 ^
12'h800) <
12'd1026 ;
assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3908 =
12'd3970 -
{ 7'd0,
iFifo$D_OUT[29] ?
5'd0 :
(iFifo$D_OUT[28] ?
5'd1 :
(iFifo$D_OUT[27] ?
5'd2 :
(iFifo$D_OUT[26] ?
5'd3 :
(iFifo$D_OUT[25] ?
5'd4 :
(iFifo$D_OUT[24] ?
5'd5 :
(iFifo$D_OUT[23] ?
5'd6 :
(iFifo$D_OUT[22] ?
5'd7 :
(iFifo$D_OUT[21] ?
5'd8 :
(iFifo$D_OUT[20] ?
5'd9 :
(iFifo$D_OUT[19] ?
5'd10 :
(iFifo$D_OUT[18] ?
5'd11 :
(iFifo$D_OUT[17] ?
5'd12 :
(iFifo$D_OUT[16] ?
5'd13 :
(iFifo$D_OUT[15] ?
5'd14 :
(iFifo$D_OUT[14] ?
5'd15 :
(iFifo$D_OUT[13] ?
5'd16 :
(iFifo$D_OUT[12] ?
5'd17 :
(iFifo$D_OUT[11] ?
5'd18 :
(iFifo$D_OUT[10] ?
5'd19 :
(iFifo$D_OUT[9] ?
5'd20 :
(iFifo$D_OUT[8] ?
5'd21 :
(iFifo$D_OUT[7] ?
5'd22 :
5'd23)))))))))))))))))))))) } ;
assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 =
(_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3908 ^
12'h800) <=
12'd3071 ;
assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 =
(_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3908 ^
12'h800) <
12'd1026 ;
assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4683 =
12'd3970 -
{ 7'd0,
iFifo$D_OUT[94] ?
5'd0 :
(iFifo$D_OUT[93] ?
5'd1 :
(iFifo$D_OUT[92] ?
5'd2 :
(iFifo$D_OUT[91] ?
5'd3 :
(iFifo$D_OUT[90] ?
5'd4 :
(iFifo$D_OUT[89] ?
5'd5 :
(iFifo$D_OUT[88] ?
5'd6 :
(iFifo$D_OUT[87] ?
5'd7 :
(iFifo$D_OUT[86] ?
5'd8 :
(iFifo$D_OUT[85] ?
5'd9 :
(iFifo$D_OUT[84] ?
5'd10 :
(iFifo$D_OUT[83] ?
5'd11 :
(iFifo$D_OUT[82] ?
5'd12 :
(iFifo$D_OUT[81] ?
5'd13 :
(iFifo$D_OUT[80] ?
5'd14 :
(iFifo$D_OUT[79] ?
5'd15 :
(iFifo$D_OUT[78] ?
5'd16 :
(iFifo$D_OUT[77] ?
5'd17 :
(iFifo$D_OUT[76] ?
5'd18 :
(iFifo$D_OUT[75] ?
5'd19 :
(iFifo$D_OUT[74] ?
5'd20 :
(iFifo$D_OUT[73] ?
5'd21 :
(iFifo$D_OUT[72] ?
5'd22 :
5'd23)))))))))))))))))))))) } ;
assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 =
(_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4683 ^
12'h800) <=
12'd3071 ;
assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 =
(_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4683 ^
12'h800) <
12'd1026 ;
assign _3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034 =
12'd3970 -
SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 ;
assign _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007 =
13'd7170 - fpu_madd_fState_S3$D_OUT[12:0] ;
assign _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2008 =
(_7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007 ^
13'h1000) <=
13'd4096 ;
assign _theResult____h164612 =
((_3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326 ^
12'h800) <
12'd2105) ?
result__h165225 :
((value__h148921 == 25'd0) ? sfd__h144534 : 57'd1) ;
assign _theResult____h203250 =
((_3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809 ^
12'h800) <
12'd2105) ?
result__h203863 :
((value__h187559 == 25'd0) ? sfd__h183174 : 57'd1) ;
assign _theResult____h242189 =
((_3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034 ^
12'h800) <
12'd2105) ?
result__h242802 :
((value__h226498 == 25'd0) ? sfd__h222113 : 57'd1) ;
assign _theResult____h269613 =
(value__h270233 == 54'd0) ? sfd__h262011 : 57'd1 ;
assign _theResult____h287250 =
((_3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034 ^
12'h800) <
12'd2105) ?
result__h287863 :
_theResult____h269613 ;
assign _theResult____h31574 =
(fpu_div_fState_S2$D_OUT[10:0] < 11'd58) ?
result__h31699 :
result__h31874 ;
assign _theResult___exp__h142541 =
sfd__h142040[53] ?
((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h142626) :
IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d2986 ;
assign _theResult___exp__h163979 =
sfd__h163352[53] ?
((_theResult___fst_exp__h163334 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h182467) :
((_theResult___fst_exp__h163334 == 11'd0 &&
sfd__h163352[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h163334) ;
assign _theResult___exp__h173569 =
sfd__h172942[53] ?
((_theResult___fst_exp__h172850 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h182502) :
((_theResult___fst_exp__h172850 == 11'd0 &&
sfd__h172942[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h172850) ;
assign _theResult___exp__h182321 =
sfd__h181670[53] ?
((_theResult___fst_exp__h181651 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h182528) :
((_theResult___fst_exp__h181651 == 11'd0 &&
sfd__h181670[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h181651) ;
assign _theResult___exp__h202617 =
sfd__h201990[53] ?
((_theResult___fst_exp__h201972 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h221105) :
((_theResult___fst_exp__h201972 == 11'd0 &&
sfd__h201990[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h201972) ;
assign _theResult___exp__h212207 =
sfd__h211580[53] ?
((_theResult___fst_exp__h211488 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h221140) :
((_theResult___fst_exp__h211488 == 11'd0 &&
sfd__h211580[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h211488) ;
assign _theResult___exp__h220959 =
sfd__h220308[53] ?
((_theResult___fst_exp__h220289 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h221166) :
((_theResult___fst_exp__h220289 == 11'd0 &&
sfd__h220308[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h220289) ;
assign _theResult___exp__h241556 =
sfd__h240929[53] ?
((_theResult___fst_exp__h240911 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h260044) :
((_theResult___fst_exp__h240911 == 11'd0 &&
sfd__h240929[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h240911) ;
assign _theResult___exp__h251146 =
sfd__h250519[53] ?
((_theResult___fst_exp__h250427 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h260079) :
((_theResult___fst_exp__h250427 == 11'd0 &&
sfd__h250519[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h250427) ;
assign _theResult___exp__h259898 =
sfd__h259247[53] ?
((_theResult___fst_exp__h259228 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h260105) :
((_theResult___fst_exp__h259228 == 11'd0 &&
sfd__h259247[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h259228) ;
assign _theResult___exp__h278238 =
sfd__h277814[24] ?
((_theResult___fst_exp__h277722 == 8'd254) ?
8'd255 :
din_inc___2_exp__h304759) :
((_theResult___fst_exp__h277722 == 8'd0 &&
sfd__h277814[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h277722) ;
assign _theResult___exp__h286820 =
sfd__h286396[24] ?
((_theResult___fst_exp__h286378 == 8'd254) ?
8'd255 :
din_inc___2_exp__h304785) :
((_theResult___fst_exp__h286378 == 8'd0 &&
sfd__h286396[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h286378) ;
assign _theResult___exp__h296004 =
sfd__h295580[24] ?
((_theResult___fst_exp__h295488 == 8'd254) ?
8'd255 :
din_inc___2_exp__h304820) :
((_theResult___fst_exp__h295488 == 8'd0 &&
sfd__h295580[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h295488) ;
assign _theResult___exp__h304640 =
sfd__h304192[24] ?
((_theResult___fst_exp__h304173 == 8'd254) ?
8'd255 :
din_inc___2_exp__h304846) :
((_theResult___fst_exp__h304173 == 8'd0 &&
sfd__h304192[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h304173) ;
assign _theResult___exp__h42526 =
sfd__h42033[53] ?
((fpu_div_fState_S4$D_OUT[64:54] == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h42617) :
IF_fpu_div_fState_S4_first__73_BITS_64_TO_54_7_ETC___d907 ;
assign _theResult___exp__h95909 =
sfd__h95416[53] ?
((fpu_sqr_fState_S4$D_OUT[64:54] == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h96000) :
IF_fpu_sqr_fState_S4_first__687_BITS_64_TO_54__ETC___d1721 ;
assign _theResult___fst__h116827 =
{ fpu_madd_fProd_S3_first__009_SRL_IF_7170_MINUS_ETC___d2012[105:1],
fpu_madd_fProd_S3_first__009_SRL_IF_7170_MINUS_ETC___d2012[0] |
sfdlsb__h116825 } ;
assign _theResult___fst__h30373 =
IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d429 ?
value__h30601[10:0] :
11'd0 ;
assign _theResult___fst__h43498 =
IF_rg_index_1_87_ULE_58_91_THEN_NOT_rg_b_92_EQ_ETC___d1009 ?
_theResult___fst__h43622 :
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1002 ;
assign _theResult___fst__h43537 =
(rg_res[116] || rg_b == 116'd0) ? rg_b : b__h43630 ;
assign _theResult___fst__h43622 =
(IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1002 ==
116'd0) ?
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1002 :
b__h43734 ;
assign _theResult___fst_exp__h130949 =
sfdBC__h115662[105] ?
_theResult___fst_exp__h130971 :
_theResult___fst_exp__h131034 ;
assign _theResult___fst_exp__h130952 =
(sfdBC__h115662[105] &&
IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 ==
12'd1023) ?
11'd2046 :
_theResult___fst_exp__h130949 ;
assign _theResult___fst_exp__h130971 =
(din_exp__h130866 == 11'd0) ? 11'd2 : din_exp__h130866 + 11'd1 ;
assign _theResult___fst_exp__h130986 =
(din_exp__h130866 == 11'd0) ? 11'd1 : din_exp__h130866 ;
assign _theResult___fst_exp__h131025 =
din_exp__h130866 -
{ 4'd0,
IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460 } ;
assign _theResult___fst_exp__h131031 =
(!sfdBC__h115662[105] && !sfdBC__h115662[104] &&
!sfdBC__h115662[103] &&
!sfdBC__h115662[102] &&
!sfdBC__h115662[101] &&
!sfdBC__h115662[100] &&
!sfdBC__h115662[99] &&
!sfdBC__h115662[98] &&
!sfdBC__h115662[97] &&
!sfdBC__h115662[96] &&
!sfdBC__h115662[95] &&
!sfdBC__h115662[94] &&
!sfdBC__h115662[93] &&
!sfdBC__h115662[92] &&
!sfdBC__h115662[91] &&
!sfdBC__h115662[90] &&
!sfdBC__h115662[89] &&
!sfdBC__h115662[88] &&
!sfdBC__h115662[87] &&
!sfdBC__h115662[86] &&
!sfdBC__h115662[85] &&
!sfdBC__h115662[84] &&
!sfdBC__h115662[83] &&
!sfdBC__h115662[82] &&
!sfdBC__h115662[81] &&
!sfdBC__h115662[80] &&
!sfdBC__h115662[79] &&
!sfdBC__h115662[78] &&
!sfdBC__h115662[77] &&
!sfdBC__h115662[76] &&
!sfdBC__h115662[75] &&
!sfdBC__h115662[74] &&
!sfdBC__h115662[73] &&
!sfdBC__h115662[72] &&
!sfdBC__h115662[71] &&
!sfdBC__h115662[70] &&
!sfdBC__h115662[69] &&
!sfdBC__h115662[68] &&
!sfdBC__h115662[67] &&
!sfdBC__h115662[66] &&
!sfdBC__h115662[65] &&
!sfdBC__h115662[64] &&
!sfdBC__h115662[63] &&
!sfdBC__h115662[62] &&
!sfdBC__h115662[61] &&
!sfdBC__h115662[60] &&
!sfdBC__h115662[59] &&
!sfdBC__h115662[58] &&
!sfdBC__h115662[57] &&
!sfdBC__h115662[56] &&
!sfdBC__h115662[55] &&
!sfdBC__h115662[54] &&
!sfdBC__h115662[53] &&
!sfdBC__h115662[52] &&
!sfdBC__h115662[51] &&
!sfdBC__h115662[50] &&
!sfdBC__h115662[49] &&
!sfdBC__h115662[48] &&
!sfdBC__h115662[47] &&
!sfdBC__h115662[46] &&
!sfdBC__h115662[45] &&
!sfdBC__h115662[44] &&
!sfdBC__h115662[43] &&
!sfdBC__h115662[42] &&
!sfdBC__h115662[41] &&
!sfdBC__h115662[40] &&
!sfdBC__h115662[39] &&
!sfdBC__h115662[38] &&
!sfdBC__h115662[37] &&
!sfdBC__h115662[36] &&
!sfdBC__h115662[35] &&
!sfdBC__h115662[34] &&
!sfdBC__h115662[33] &&
!sfdBC__h115662[32] &&
!sfdBC__h115662[31] &&
!sfdBC__h115662[30] &&
!sfdBC__h115662[29] &&
!sfdBC__h115662[28] &&
!sfdBC__h115662[27] &&
!sfdBC__h115662[26] &&
!sfdBC__h115662[25] &&
!sfdBC__h115662[24] &&
!sfdBC__h115662[23] &&
!sfdBC__h115662[22] &&
!sfdBC__h115662[21] &&
!sfdBC__h115662[20] &&
!sfdBC__h115662[19] &&
!sfdBC__h115662[18] &&
!sfdBC__h115662[17] &&
!sfdBC__h115662[16] &&
!sfdBC__h115662[15] &&
!sfdBC__h115662[14] &&
!sfdBC__h115662[13] &&
!sfdBC__h115662[12] &&
!sfdBC__h115662[11] &&
!sfdBC__h115662[10] &&
!sfdBC__h115662[9] &&
!sfdBC__h115662[8] &&
!sfdBC__h115662[7] &&
!sfdBC__h115662[6] &&
!sfdBC__h115662[5] &&
!sfdBC__h115662[4] &&
!sfdBC__h115662[3] &&
!sfdBC__h115662[2] &&
!sfdBC__h115662[1] &&
!sfdBC__h115662[0] ||
!_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S3_f_ETC___d2463) ?
11'd0 :
_theResult___fst_exp__h131025 ;
assign _theResult___fst_exp__h131034 =
(!sfdBC__h115662[105] && sfdBC__h115662[104]) ?
_theResult___fst_exp__h130986 :
_theResult___fst_exp__h131031 ;
assign _theResult___fst_exp__h141375 =
sfd__h133119[56] ?
_theResult___fst_exp__h141397 :
_theResult___fst_exp__h141460 ;
assign _theResult___fst_exp__h141378 =
(sfd__h133119[56] &&
IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 ==
12'd1023) ?
11'd2046 :
_theResult___fst_exp__h141375 ;
assign _theResult___fst_exp__h141397 =
(value__h141307[10:0] == 11'd0) ?
11'd2 :
value__h141307[10:0] + 11'd1 ;
assign _theResult___fst_exp__h141412 =
(value__h141307[10:0] == 11'd0) ? 11'd1 : value__h141307[10:0] ;
assign _theResult___fst_exp__h141451 =
value__h141307[10:0] -
{ 5'd0,
IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901 } ;
assign _theResult___fst_exp__h141457 =
(!sfd__h133119[56] && !sfd__h133119[55] && !sfd__h133119[54] &&
!sfd__h133119[53] &&
!sfd__h133119[52] &&
!sfd__h133119[51] &&
!sfd__h133119[50] &&
!sfd__h133119[49] &&
!sfd__h133119[48] &&
!sfd__h133119[47] &&
!sfd__h133119[46] &&
!sfd__h133119[45] &&
!sfd__h133119[44] &&
!sfd__h133119[43] &&
!sfd__h133119[42] &&
!sfd__h133119[41] &&
!sfd__h133119[40] &&
!sfd__h133119[39] &&
!sfd__h133119[38] &&
!sfd__h133119[37] &&
!sfd__h133119[36] &&
!sfd__h133119[35] &&
!sfd__h133119[34] &&
!sfd__h133119[33] &&
!sfd__h133119[32] &&
!sfd__h133119[31] &&
!sfd__h133119[30] &&
!sfd__h133119[29] &&
!sfd__h133119[28] &&
!sfd__h133119[27] &&
!sfd__h133119[26] &&
!sfd__h133119[25] &&
!sfd__h133119[24] &&
!sfd__h133119[23] &&
!sfd__h133119[22] &&
!sfd__h133119[21] &&
!sfd__h133119[20] &&
!sfd__h133119[19] &&
!sfd__h133119[18] &&
!sfd__h133119[17] &&
!sfd__h133119[16] &&
!sfd__h133119[15] &&
!sfd__h133119[14] &&
!sfd__h133119[13] &&
!sfd__h133119[12] &&
!sfd__h133119[11] &&
!sfd__h133119[10] &&
!sfd__h133119[9] &&
!sfd__h133119[8] &&
!sfd__h133119[7] &&
!sfd__h133119[6] &&
!sfd__h133119[5] &&
!sfd__h133119[4] &&
!sfd__h133119[3] &&
!sfd__h133119[2] &&
!sfd__h133119[1] &&
!sfd__h133119[0] ||
!_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__651_B_ETC___d2904) ?
11'd0 :
_theResult___fst_exp__h141451 ;
assign _theResult___fst_exp__h141460 =
(!sfd__h133119[56] && sfd__h133119[55]) ?
_theResult___fst_exp__h141412 :
_theResult___fst_exp__h141457 ;
assign _theResult___fst_exp__h163325 =
11'd897 -
{ 5'd0,
IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 } ;
assign _theResult___fst_exp__h163331 =
(iFifo$D_OUT[167:160] == 8'd0 && !iFifo$D_OUT[159] &&
NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244 ||
!_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3273) ?
11'd0 :
_theResult___fst_exp__h163325 ;
assign _theResult___fst_exp__h163334 =
(iFifo$D_OUT[167:160] == 8'd0) ?
_theResult___fst_exp__h163331 :
11'd897 ;
assign _theResult___fst_exp__h164060 =
(_theResult___fst_exp__h163334 == 11'd2047) ?
_theResult___fst_exp__h163334 :
_theResult___fst_exp__h164057 ;
assign _theResult___fst_exp__h172850 =
_theResult____h164612[56] ?
11'd2 :
_theResult___fst_exp__h172924 ;
assign _theResult___fst_exp__h172915 =
11'd0 -
{ 5'd0,
IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572 } ;
assign _theResult___fst_exp__h172921 =
(!_theResult____h164612[56] && !_theResult____h164612[55] &&
!_theResult____h164612[54] &&
!_theResult____h164612[53] &&
!_theResult____h164612[52] &&
!_theResult____h164612[51] &&
!_theResult____h164612[50] &&
!_theResult____h164612[49] &&
!_theResult____h164612[48] &&
!_theResult____h164612[47] &&
!_theResult____h164612[46] &&
!_theResult____h164612[45] &&
!_theResult____h164612[44] &&
!_theResult____h164612[43] &&
!_theResult____h164612[42] &&
!_theResult____h164612[41] &&
!_theResult____h164612[40] &&
!_theResult____h164612[39] &&
!_theResult____h164612[38] &&
!_theResult____h164612[37] &&
!_theResult____h164612[36] &&
!_theResult____h164612[35] &&
!_theResult____h164612[34] &&
!_theResult____h164612[33] &&
!_theResult____h164612[32] &&
!_theResult____h164612[31] &&
!_theResult____h164612[30] &&
!_theResult____h164612[29] &&
!_theResult____h164612[28] &&
!_theResult____h164612[27] &&
!_theResult____h164612[26] &&
!_theResult____h164612[25] &&
!_theResult____h164612[24] &&
!_theResult____h164612[23] &&
!_theResult____h164612[22] &&
!_theResult____h164612[21] &&
!_theResult____h164612[20] &&
!_theResult____h164612[19] &&
!_theResult____h164612[18] &&
!_theResult____h164612[17] &&
!_theResult____h164612[16] &&
!_theResult____h164612[15] &&
!_theResult____h164612[14] &&
!_theResult____h164612[13] &&
!_theResult____h164612[12] &&
!_theResult____h164612[11] &&
!_theResult____h164612[10] &&
!_theResult____h164612[9] &&
!_theResult____h164612[8] &&
!_theResult____h164612[7] &&
!_theResult____h164612[6] &&
!_theResult____h164612[5] &&
!_theResult____h164612[4] &&
!_theResult____h164612[3] &&
!_theResult____h164612[2] &&
!_theResult____h164612[1] &&
!_theResult____h164612[0] ||
!_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d3574) ?
11'd0 :
_theResult___fst_exp__h172915 ;
assign _theResult___fst_exp__h172924 =
(!_theResult____h164612[56] && _theResult____h164612[55]) ?
11'd1 :
_theResult___fst_exp__h172921 ;
assign _theResult___fst_exp__h173650 =
(_theResult___fst_exp__h172850 == 11'd2047) ?
_theResult___fst_exp__h172850 :
_theResult___fst_exp__h173647 ;
assign _theResult___fst_exp__h181603 =
(SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] ==
11'd0) ?
11'd1 :
SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] ;
assign _theResult___fst_exp__h181642 =
SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] -
{ 5'd0,
IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 } ;
assign _theResult___fst_exp__h181648 =
(iFifo$D_OUT[167:160] == 8'd0 && !iFifo$D_OUT[159] &&
NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244 ||
!_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3624) ?
11'd0 :
_theResult___fst_exp__h181642 ;
assign _theResult___fst_exp__h181651 =
(iFifo$D_OUT[167:160] == 8'd0) ?
_theResult___fst_exp__h181648 :
_theResult___fst_exp__h181603 ;
assign _theResult___fst_exp__h182402 =
(_theResult___fst_exp__h181651 == 11'd2047) ?
_theResult___fst_exp__h181651 :
_theResult___fst_exp__h182399 ;
assign _theResult___fst_exp__h182411 =
(iFifo$D_OUT[167:160] == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189 ?
_theResult___snd_fst_exp__h164063 :
_theResult___fst_exp__h148289) :
(SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324 ?
_theResult___snd_fst_exp__h182405 :
_theResult___fst_exp__h148289) ;
assign _theResult___fst_exp__h182414 =
(iFifo$D_OUT[167:160] == 8'd0 && iFifo$D_OUT[159:137] == 23'd0) ?
11'd0 :
_theResult___fst_exp__h182411 ;
assign _theResult___fst_exp__h201963 =
11'd897 -
{ 5'd0,
IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 } ;
assign _theResult___fst_exp__h201969 =
(iFifo$D_OUT[102:95] == 8'd0 && !iFifo$D_OUT[94] &&
NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730 ||
!_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d4759) ?
11'd0 :
_theResult___fst_exp__h201963 ;
assign _theResult___fst_exp__h201972 =
(iFifo$D_OUT[102:95] == 8'd0) ?
_theResult___fst_exp__h201969 :
11'd897 ;
assign _theResult___fst_exp__h202698 =
(_theResult___fst_exp__h201972 == 11'd2047) ?
_theResult___fst_exp__h201972 :
_theResult___fst_exp__h202695 ;
assign _theResult___fst_exp__h211488 =
_theResult____h203250[56] ?
11'd2 :
_theResult___fst_exp__h211562 ;
assign _theResult___fst_exp__h211553 =
11'd0 -
{ 5'd0,
IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055 } ;
assign _theResult___fst_exp__h211559 =
(!_theResult____h203250[56] && !_theResult____h203250[55] &&
!_theResult____h203250[54] &&
!_theResult____h203250[53] &&
!_theResult____h203250[52] &&
!_theResult____h203250[51] &&
!_theResult____h203250[50] &&
!_theResult____h203250[49] &&
!_theResult____h203250[48] &&
!_theResult____h203250[47] &&
!_theResult____h203250[46] &&
!_theResult____h203250[45] &&
!_theResult____h203250[44] &&
!_theResult____h203250[43] &&
!_theResult____h203250[42] &&
!_theResult____h203250[41] &&
!_theResult____h203250[40] &&
!_theResult____h203250[39] &&
!_theResult____h203250[38] &&
!_theResult____h203250[37] &&
!_theResult____h203250[36] &&
!_theResult____h203250[35] &&
!_theResult____h203250[34] &&
!_theResult____h203250[33] &&
!_theResult____h203250[32] &&
!_theResult____h203250[31] &&
!_theResult____h203250[30] &&
!_theResult____h203250[29] &&
!_theResult____h203250[28] &&
!_theResult____h203250[27] &&
!_theResult____h203250[26] &&
!_theResult____h203250[25] &&
!_theResult____h203250[24] &&
!_theResult____h203250[23] &&
!_theResult____h203250[22] &&
!_theResult____h203250[21] &&
!_theResult____h203250[20] &&
!_theResult____h203250[19] &&
!_theResult____h203250[18] &&
!_theResult____h203250[17] &&
!_theResult____h203250[16] &&
!_theResult____h203250[15] &&
!_theResult____h203250[14] &&
!_theResult____h203250[13] &&
!_theResult____h203250[12] &&
!_theResult____h203250[11] &&
!_theResult____h203250[10] &&
!_theResult____h203250[9] &&
!_theResult____h203250[8] &&
!_theResult____h203250[7] &&
!_theResult____h203250[6] &&
!_theResult____h203250[5] &&
!_theResult____h203250[4] &&
!_theResult____h203250[3] &&
!_theResult____h203250[2] &&
!_theResult____h203250[1] &&
!_theResult____h203250[0] ||
!_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d5057) ?
11'd0 :
_theResult___fst_exp__h211553 ;
assign _theResult___fst_exp__h211562 =
(!_theResult____h203250[56] && _theResult____h203250[55]) ?
11'd1 :
_theResult___fst_exp__h211559 ;
assign _theResult___fst_exp__h212288 =
(_theResult___fst_exp__h211488 == 11'd2047) ?
_theResult___fst_exp__h211488 :
_theResult___fst_exp__h212285 ;
assign _theResult___fst_exp__h220241 =
(SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] ==
11'd0) ?
11'd1 :
SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] ;
assign _theResult___fst_exp__h220280 =
SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] -
{ 5'd0,
IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 } ;
assign _theResult___fst_exp__h220286 =
(iFifo$D_OUT[102:95] == 8'd0 && !iFifo$D_OUT[94] &&
NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730 ||
!_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d5107) ?
11'd0 :
_theResult___fst_exp__h220280 ;
assign _theResult___fst_exp__h220289 =
(iFifo$D_OUT[102:95] == 8'd0) ?
_theResult___fst_exp__h220286 :
_theResult___fst_exp__h220241 ;
assign _theResult___fst_exp__h221040 =
(_theResult___fst_exp__h220289 == 11'd2047) ?
_theResult___fst_exp__h220289 :
_theResult___fst_exp__h221037 ;
assign _theResult___fst_exp__h221049 =
(iFifo$D_OUT[102:95] == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 ?
_theResult___snd_fst_exp__h202701 :
_theResult___fst_exp__h186929) :
(SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 ?
_theResult___snd_fst_exp__h221043 :
_theResult___fst_exp__h186929) ;
assign _theResult___fst_exp__h221052 =
(iFifo$D_OUT[102:95] == 8'd0 && iFifo$D_OUT[94:72] == 23'd0) ?
11'd0 :
_theResult___fst_exp__h221049 ;
assign _theResult___fst_exp__h240902 =
11'd897 -
{ 5'd0,
IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 } ;
assign _theResult___fst_exp__h240908 =
(iFifo$D_OUT[37:30] == 8'd0 && !iFifo$D_OUT[29] &&
NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955 ||
!_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d3984) ?
11'd0 :
_theResult___fst_exp__h240902 ;
assign _theResult___fst_exp__h240911 =
(iFifo$D_OUT[37:30] == 8'd0) ?
_theResult___fst_exp__h240908 :
11'd897 ;
assign _theResult___fst_exp__h241637 =
(_theResult___fst_exp__h240911 == 11'd2047) ?
_theResult___fst_exp__h240911 :
_theResult___fst_exp__h241634 ;
assign _theResult___fst_exp__h250427 =
_theResult____h242189[56] ?
11'd2 :
_theResult___fst_exp__h250501 ;
assign _theResult___fst_exp__h250492 =
11'd0 -
{ 5'd0,
IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280 } ;
assign _theResult___fst_exp__h250498 =
(!_theResult____h242189[56] && !_theResult____h242189[55] &&
!_theResult____h242189[54] &&
!_theResult____h242189[53] &&
!_theResult____h242189[52] &&
!_theResult____h242189[51] &&
!_theResult____h242189[50] &&
!_theResult____h242189[49] &&
!_theResult____h242189[48] &&
!_theResult____h242189[47] &&
!_theResult____h242189[46] &&
!_theResult____h242189[45] &&
!_theResult____h242189[44] &&
!_theResult____h242189[43] &&
!_theResult____h242189[42] &&
!_theResult____h242189[41] &&
!_theResult____h242189[40] &&
!_theResult____h242189[39] &&
!_theResult____h242189[38] &&
!_theResult____h242189[37] &&
!_theResult____h242189[36] &&
!_theResult____h242189[35] &&
!_theResult____h242189[34] &&
!_theResult____h242189[33] &&
!_theResult____h242189[32] &&
!_theResult____h242189[31] &&
!_theResult____h242189[30] &&
!_theResult____h242189[29] &&
!_theResult____h242189[28] &&
!_theResult____h242189[27] &&
!_theResult____h242189[26] &&
!_theResult____h242189[25] &&
!_theResult____h242189[24] &&
!_theResult____h242189[23] &&
!_theResult____h242189[22] &&
!_theResult____h242189[21] &&
!_theResult____h242189[20] &&
!_theResult____h242189[19] &&
!_theResult____h242189[18] &&
!_theResult____h242189[17] &&
!_theResult____h242189[16] &&
!_theResult____h242189[15] &&
!_theResult____h242189[14] &&
!_theResult____h242189[13] &&
!_theResult____h242189[12] &&
!_theResult____h242189[11] &&
!_theResult____h242189[10] &&
!_theResult____h242189[9] &&
!_theResult____h242189[8] &&
!_theResult____h242189[7] &&
!_theResult____h242189[6] &&
!_theResult____h242189[5] &&
!_theResult____h242189[4] &&
!_theResult____h242189[3] &&
!_theResult____h242189[2] &&
!_theResult____h242189[1] &&
!_theResult____h242189[0] ||
!_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d4282) ?
11'd0 :
_theResult___fst_exp__h250492 ;
assign _theResult___fst_exp__h250501 =
(!_theResult____h242189[56] && _theResult____h242189[55]) ?
11'd1 :
_theResult___fst_exp__h250498 ;
assign _theResult___fst_exp__h251227 =
(_theResult___fst_exp__h250427 == 11'd2047) ?
_theResult___fst_exp__h250427 :
_theResult___fst_exp__h251224 ;
assign _theResult___fst_exp__h259180 =
(SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] ==
11'd0) ?
11'd1 :
SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] ;
assign _theResult___fst_exp__h259219 =
SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] -
{ 5'd0,
IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 } ;
assign _theResult___fst_exp__h259225 =
(iFifo$D_OUT[37:30] == 8'd0 && !iFifo$D_OUT[29] &&
NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955 ||
!_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d4332) ?
11'd0 :
_theResult___fst_exp__h259219 ;
assign _theResult___fst_exp__h259228 =
(iFifo$D_OUT[37:30] == 8'd0) ?
_theResult___fst_exp__h259225 :
_theResult___fst_exp__h259180 ;
assign _theResult___fst_exp__h259979 =
(_theResult___fst_exp__h259228 == 11'd2047) ?
_theResult___fst_exp__h259228 :
_theResult___fst_exp__h259976 ;
assign _theResult___fst_exp__h259988 =
(iFifo$D_OUT[37:30] == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 ?
_theResult___snd_fst_exp__h241640 :
_theResult___fst_exp__h225868) :
(SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 ?
_theResult___snd_fst_exp__h259982 :
_theResult___fst_exp__h225868) ;
assign _theResult___fst_exp__h259991 =
(iFifo$D_OUT[37:30] == 8'd0 && iFifo$D_OUT[29:7] == 23'd0) ?
11'd0 :
_theResult___fst_exp__h259988 ;
assign _theResult___fst_exp__h277722 =
_theResult____h269613[56] ?
8'd2 :
_theResult___fst_exp__h277796 ;
assign _theResult___fst_exp__h277787 =
8'd0 -
{ 2'd0,
IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767 } ;
assign _theResult___fst_exp__h277793 =
(!_theResult____h269613[56] && !_theResult____h269613[55] &&
!_theResult____h269613[54] &&
!_theResult____h269613[53] &&
!_theResult____h269613[52] &&
!_theResult____h269613[51] &&
!_theResult____h269613[50] &&
!_theResult____h269613[49] &&
!_theResult____h269613[48] &&
!_theResult____h269613[47] &&
!_theResult____h269613[46] &&
!_theResult____h269613[45] &&
!_theResult____h269613[44] &&
!_theResult____h269613[43] &&
!_theResult____h269613[42] &&
!_theResult____h269613[41] &&
!_theResult____h269613[40] &&
!_theResult____h269613[39] &&
!_theResult____h269613[38] &&
!_theResult____h269613[37] &&
!_theResult____h269613[36] &&
!_theResult____h269613[35] &&
!_theResult____h269613[34] &&
!_theResult____h269613[33] &&
!_theResult____h269613[32] &&
!_theResult____h269613[31] &&
!_theResult____h269613[30] &&
!_theResult____h269613[29] &&
!_theResult____h269613[28] &&
!_theResult____h269613[27] &&
!_theResult____h269613[26] &&
!_theResult____h269613[25] &&
!_theResult____h269613[24] &&
!_theResult____h269613[23] &&
!_theResult____h269613[22] &&
!_theResult____h269613[21] &&
!_theResult____h269613[20] &&
!_theResult____h269613[19] &&
!_theResult____h269613[18] &&
!_theResult____h269613[17] &&
!_theResult____h269613[16] &&
!_theResult____h269613[15] &&
!_theResult____h269613[14] &&
!_theResult____h269613[13] &&
!_theResult____h269613[12] &&
!_theResult____h269613[11] &&
!_theResult____h269613[10] &&
!_theResult____h269613[9] &&
!_theResult____h269613[8] &&
!_theResult____h269613[7] &&
!_theResult____h269613[6] &&
!_theResult____h269613[5] &&
!_theResult____h269613[4] &&
!_theResult____h269613[3] &&
!_theResult____h269613[2] &&
!_theResult____h269613[1] &&
!_theResult____h269613[0] ||
!_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d5769) ?
8'd0 :
_theResult___fst_exp__h277787 ;
assign _theResult___fst_exp__h277796 =
(!_theResult____h269613[56] && _theResult____h269613[55]) ?
8'd1 :
_theResult___fst_exp__h277793 ;
assign _theResult___fst_exp__h278319 =
(_theResult___fst_exp__h277722 == 8'd255) ?
_theResult___fst_exp__h277722 :
_theResult___fst_exp__h278316 ;
assign _theResult___fst_exp__h286369 =
8'd129 -
{ 2'd0,
IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 } ;
assign _theResult___fst_exp__h286375 =
(resWire$wget[67:57] == 11'd0 &&
NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927 ||
!_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d5984) ?
8'd0 :
_theResult___fst_exp__h286369 ;
assign _theResult___fst_exp__h286378 =
(resWire$wget[67:57] == 11'd0) ?
_theResult___fst_exp__h286375 :
8'd129 ;
assign _theResult___fst_exp__h286901 =
(_theResult___fst_exp__h286378 == 8'd255) ?
_theResult___fst_exp__h286378 :
_theResult___fst_exp__h286898 ;
assign _theResult___fst_exp__h295488 =
_theResult____h287250[56] ?
8'd2 :
_theResult___fst_exp__h295562 ;
assign _theResult___fst_exp__h295553 =
8'd0 -
{ 2'd0,
IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278 } ;
assign _theResult___fst_exp__h295559 =
(!_theResult____h287250[56] && !_theResult____h287250[55] &&
!_theResult____h287250[54] &&
!_theResult____h287250[53] &&
!_theResult____h287250[52] &&
!_theResult____h287250[51] &&
!_theResult____h287250[50] &&
!_theResult____h287250[49] &&
!_theResult____h287250[48] &&
!_theResult____h287250[47] &&
!_theResult____h287250[46] &&
!_theResult____h287250[45] &&
!_theResult____h287250[44] &&
!_theResult____h287250[43] &&
!_theResult____h287250[42] &&
!_theResult____h287250[41] &&
!_theResult____h287250[40] &&
!_theResult____h287250[39] &&
!_theResult____h287250[38] &&
!_theResult____h287250[37] &&
!_theResult____h287250[36] &&
!_theResult____h287250[35] &&
!_theResult____h287250[34] &&
!_theResult____h287250[33] &&
!_theResult____h287250[32] &&
!_theResult____h287250[31] &&
!_theResult____h287250[30] &&
!_theResult____h287250[29] &&
!_theResult____h287250[28] &&
!_theResult____h287250[27] &&
!_theResult____h287250[26] &&
!_theResult____h287250[25] &&
!_theResult____h287250[24] &&
!_theResult____h287250[23] &&
!_theResult____h287250[22] &&
!_theResult____h287250[21] &&
!_theResult____h287250[20] &&
!_theResult____h287250[19] &&
!_theResult____h287250[18] &&
!_theResult____h287250[17] &&
!_theResult____h287250[16] &&
!_theResult____h287250[15] &&
!_theResult____h287250[14] &&
!_theResult____h287250[13] &&
!_theResult____h287250[12] &&
!_theResult____h287250[11] &&
!_theResult____h287250[10] &&
!_theResult____h287250[9] &&
!_theResult____h287250[8] &&
!_theResult____h287250[7] &&
!_theResult____h287250[6] &&
!_theResult____h287250[5] &&
!_theResult____h287250[4] &&
!_theResult____h287250[3] &&
!_theResult____h287250[2] &&
!_theResult____h287250[1] &&
!_theResult____h287250[0] ||
!_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6280) ?
8'd0 :
_theResult___fst_exp__h295553 ;
assign _theResult___fst_exp__h295562 =
(!_theResult____h287250[56] && _theResult____h287250[55]) ?
8'd1 :
_theResult___fst_exp__h295559 ;
assign _theResult___fst_exp__h296085 =
(_theResult___fst_exp__h295488 == 8'd255) ?
_theResult___fst_exp__h295488 :
_theResult___fst_exp__h296082 ;
assign _theResult___fst_exp__h304125 =
(SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] ==
8'd0) ?
8'd1 :
SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] ;
assign _theResult___fst_exp__h304164 =
SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] -
{ 2'd0,
IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 } ;
assign _theResult___fst_exp__h304170 =
(resWire$wget[67:57] == 11'd0 &&
NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927 ||
!_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6333) ?
8'd0 :
_theResult___fst_exp__h304164 ;
assign _theResult___fst_exp__h304173 =
(resWire$wget[67:57] == 11'd0) ?
_theResult___fst_exp__h304170 :
_theResult___fst_exp__h304125 ;
assign _theResult___fst_exp__h304721 =
(_theResult___fst_exp__h304173 == 8'd255) ?
_theResult___fst_exp__h304173 :
_theResult___fst_exp__h304718 ;
assign _theResult___fst_exp__h304730 =
(resWire$wget[67:57] == 11'd0) ?
(_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ?
_theResult___snd_fst_exp__h286904 :
_theResult___fst_exp__h269595) :
(SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ?
_theResult___snd_fst_exp__h304724 :
_theResult___fst_exp__h269595) ;
assign _theResult___fst_exp__h304733 =
(resWire$wget[67:57] == 11'd0 && resWire$wget[56:5] == 52'd0) ?
8'd0 :
_theResult___fst_exp__h304730 ;
assign _theResult___fst_exp__h41335 =
fpu_div_fState_S3$D_OUT[120:110] - 11'd1 ;
assign _theResult___fst_exp__h41338 =
(fpu_div_fState_S3$D_OUT[57:56] == 2'b0) ?
_theResult___fst_exp__h41335 :
11'd2046 ;
assign _theResult___fst_exp__h41341 =
(fpu_div_fState_S3$D_OUT[120:110] == 11'd2047) ?
_theResult___fst_exp__h41338 :
fpu_div_fState_S3$D_OUT[120:110] ;
assign _theResult___fst_exp__h41384 =
sfdin__h33169[57] ?
_theResult___fst_exp__h41407 :
_theResult___fst_exp__h41471 ;
assign _theResult___fst_exp__h41387 =
(sfdin__h33169[57] &&
IF_IF_fpu_div_fState_S3_first__16_BITS_120_TO__ETC___d573 ==
12'd1023) ?
11'd2046 :
_theResult___fst_exp__h41384 ;
assign _theResult___fst_exp__h41407 =
(_theResult___fst_exp__h41341 == 11'd0) ?
11'd2 :
_theResult___fst_exp__h41341 + 11'd1 ;
assign _theResult___fst_exp__h41423 =
(_theResult___fst_exp__h41341 == 11'd0) ?
11'd1 :
_theResult___fst_exp__h41341 ;
assign _theResult___fst_exp__h41462 =
_theResult___fst_exp__h41341 -
{ 5'd0,
IF_IF_fpu_div_fState_S3_first__16_BITS_120_TO__ETC___d810 } ;
assign _theResult___fst_exp__h41468 =
(!sfdin__h33169[57] && !sfdin__h33169[56] &&
!sfdin__h33169[55] &&
!sfdin__h33169[54] &&
!sfdin__h33169[53] &&
!sfdin__h33169[52] &&
!sfdin__h33169[51] &&
!sfdin__h33169[50] &&
!sfdin__h33169[49] &&
!sfdin__h33169[48] &&
!sfdin__h33169[47] &&
!sfdin__h33169[46] &&
!sfdin__h33169[45] &&
!sfdin__h33169[44] &&
!sfdin__h33169[43] &&
!sfdin__h33169[42] &&
!sfdin__h33169[41] &&
!sfdin__h33169[40] &&
!sfdin__h33169[39] &&
!sfdin__h33169[38] &&
!sfdin__h33169[37] &&
!sfdin__h33169[36] &&
!sfdin__h33169[35] &&
!sfdin__h33169[34] &&
!sfdin__h33169[33] &&
!sfdin__h33169[32] &&
!sfdin__h33169[31] &&
!sfdin__h33169[30] &&
!sfdin__h33169[29] &&
!sfdin__h33169[28] &&
!sfdin__h33169[27] &&
!sfdin__h33169[26] &&
!sfdin__h33169[25] &&
!sfdin__h33169[24] &&
!sfdin__h33169[23] &&
!sfdin__h33169[22] &&
!sfdin__h33169[21] &&
!sfdin__h33169[20] &&
!sfdin__h33169[19] &&
!sfdin__h33169[18] &&
!sfdin__h33169[17] &&
!sfdin__h33169[16] &&
!sfdin__h33169[15] &&
!sfdin__h33169[14] &&
!sfdin__h33169[13] &&
!sfdin__h33169[12] &&
!sfdin__h33169[11] &&
!sfdin__h33169[10] &&
!sfdin__h33169[9] &&
!sfdin__h33169[8] &&
!sfdin__h33169[7] &&
!sfdin__h33169[6] &&
!sfdin__h33169[5] &&
!sfdin__h33169[4] &&
!sfdin__h33169[3] &&
!sfdin__h33169[2] &&
!sfdin__h33169[1] &&
!sfdin__h33169[0] ||
!_0_CONCAT_IF_IF_fpu_div_fState_S3_first__16_BIT_ETC___d813) ?
11'd0 :
_theResult___fst_exp__h41462 ;
assign _theResult___fst_exp__h41471 =
(!sfdin__h33169[57] && sfdin__h33169[56]) ?
_theResult___fst_exp__h41423 :
_theResult___fst_exp__h41468 ;
assign _theResult___fst_exp__h42607 =
(fpu_div_fState_S4$D_OUT[64:54] == 11'd2047) ?
fpu_div_fState_S4$D_OUT[64:54] :
_theResult___fst_exp__h42604 ;
assign _theResult___fst_exp__h94750 =
fpu_sqr_fState_S3$D_OUT[58] ?
_theResult___fst_exp__h94773 :
_theResult___fst_exp__h94837 ;
assign _theResult___fst_exp__h94753 =
(fpu_sqr_fState_S3$D_OUT[58] &&
IF_fpu_sqr_fState_S3_first__375_BITS_121_TO_11_ETC___d1389 ==
12'd1023) ?
11'd2046 :
_theResult___fst_exp__h94750 ;
assign _theResult___fst_exp__h94773 =
(fpu_sqr_fState_S3$D_OUT[121:111] == 11'd0) ?
11'd2 :
fpu_sqr_fState_S3$D_OUT[121:111] + 11'd1 ;
assign _theResult___fst_exp__h94789 =
(fpu_sqr_fState_S3$D_OUT[121:111] == 11'd0) ?
11'd1 :
fpu_sqr_fState_S3$D_OUT[121:111] ;
assign _theResult___fst_exp__h94828 =
fpu_sqr_fState_S3$D_OUT[121:111] -
{ 5'd0,
IF_fpu_sqr_fState_S3_first__375_BIT_58_384_THE_ETC___d1630 } ;
assign _theResult___fst_exp__h94834 =
(!fpu_sqr_fState_S3$D_OUT[58] && !fpu_sqr_fState_S3$D_OUT[57] &&
!fpu_sqr_fState_S3$D_OUT[56] &&
!fpu_sqr_fState_S3$D_OUT[55] &&
!fpu_sqr_fState_S3$D_OUT[54] &&
!fpu_sqr_fState_S3$D_OUT[53] &&
!fpu_sqr_fState_S3$D_OUT[52] &&
!fpu_sqr_fState_S3$D_OUT[51] &&
!fpu_sqr_fState_S3$D_OUT[50] &&
!fpu_sqr_fState_S3$D_OUT[49] &&
!fpu_sqr_fState_S3$D_OUT[48] &&
!fpu_sqr_fState_S3$D_OUT[47] &&
!fpu_sqr_fState_S3$D_OUT[46] &&
!fpu_sqr_fState_S3$D_OUT[45] &&
!fpu_sqr_fState_S3$D_OUT[44] &&
!fpu_sqr_fState_S3$D_OUT[43] &&
!fpu_sqr_fState_S3$D_OUT[42] &&
!fpu_sqr_fState_S3$D_OUT[41] &&
!fpu_sqr_fState_S3$D_OUT[40] &&
!fpu_sqr_fState_S3$D_OUT[39] &&
!fpu_sqr_fState_S3$D_OUT[38] &&
!fpu_sqr_fState_S3$D_OUT[37] &&
!fpu_sqr_fState_S3$D_OUT[36] &&
!fpu_sqr_fState_S3$D_OUT[35] &&
!fpu_sqr_fState_S3$D_OUT[34] &&
!fpu_sqr_fState_S3$D_OUT[33] &&
!fpu_sqr_fState_S3$D_OUT[32] &&
!fpu_sqr_fState_S3$D_OUT[31] &&
!fpu_sqr_fState_S3$D_OUT[30] &&
!fpu_sqr_fState_S3$D_OUT[29] &&
!fpu_sqr_fState_S3$D_OUT[28] &&
!fpu_sqr_fState_S3$D_OUT[27] &&
!fpu_sqr_fState_S3$D_OUT[26] &&
!fpu_sqr_fState_S3$D_OUT[25] &&
!fpu_sqr_fState_S3$D_OUT[24] &&
!fpu_sqr_fState_S3$D_OUT[23] &&
!fpu_sqr_fState_S3$D_OUT[22] &&
!fpu_sqr_fState_S3$D_OUT[21] &&
!fpu_sqr_fState_S3$D_OUT[20] &&
!fpu_sqr_fState_S3$D_OUT[19] &&
!fpu_sqr_fState_S3$D_OUT[18] &&
!fpu_sqr_fState_S3$D_OUT[17] &&
!fpu_sqr_fState_S3$D_OUT[16] &&
!fpu_sqr_fState_S3$D_OUT[15] &&
!fpu_sqr_fState_S3$D_OUT[14] &&
!fpu_sqr_fState_S3$D_OUT[13] &&
!fpu_sqr_fState_S3$D_OUT[12] &&
!fpu_sqr_fState_S3$D_OUT[11] &&
!fpu_sqr_fState_S3$D_OUT[10] &&
!fpu_sqr_fState_S3$D_OUT[9] &&
!fpu_sqr_fState_S3$D_OUT[8] &&
!fpu_sqr_fState_S3$D_OUT[7] &&
!fpu_sqr_fState_S3$D_OUT[6] &&
!fpu_sqr_fState_S3$D_OUT[5] &&
!fpu_sqr_fState_S3$D_OUT[4] &&
!fpu_sqr_fState_S3$D_OUT[3] &&
!fpu_sqr_fState_S3$D_OUT[2] &&
!fpu_sqr_fState_S3$D_OUT[1] &&
!fpu_sqr_fState_S3$D_OUT[0] ||
!_0_CONCAT_IF_fpu_sqr_fState_S3_first__375_BIT_5_ETC___d1633) ?
11'd0 :
_theResult___fst_exp__h94828 ;
assign _theResult___fst_exp__h94837 =
(!fpu_sqr_fState_S3$D_OUT[58] && fpu_sqr_fState_S3$D_OUT[57]) ?
_theResult___fst_exp__h94789 :
_theResult___fst_exp__h94834 ;
assign _theResult___fst_exp__h95990 =
(fpu_sqr_fState_S4$D_OUT[64:54] == 11'd2047) ?
fpu_sqr_fState_S4$D_OUT[64:54] :
_theResult___fst_exp__h95987 ;
assign _theResult___fst_sfd__h164061 =
(_theResult___fst_exp__h163334 == 11'd2047) ?
_theResult___snd__h163285[56:5] :
_theResult___fst_sfd__h164058 ;
assign _theResult___fst_sfd__h173651 =
(_theResult___fst_exp__h172850 == 11'd2047) ?
sfdin__h172844[56:5] :
_theResult___fst_sfd__h173648 ;
assign _theResult___fst_sfd__h182403 =
(_theResult___fst_exp__h181651 == 11'd2047) ?
_theResult___snd__h181597[56:5] :
_theResult___fst_sfd__h182400 ;
assign _theResult___fst_sfd__h182412 =
(iFifo$D_OUT[167:160] == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189 ?
_theResult___snd_fst_sfd__h164064 :
_theResult___fst_sfd__h148290) :
(SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324 ?
_theResult___snd_fst_sfd__h182406 :
_theResult___fst_sfd__h148290) ;
assign _theResult___fst_sfd__h182418 =
((iFifo$D_OUT[167:160] == 8'd255 ||
iFifo$D_OUT[167:160] == 8'd0) &&
iFifo$D_OUT[159:137] == 23'd0) ?
52'd0 :
_theResult___fst_sfd__h182412 ;
assign _theResult___fst_sfd__h202699 =
(_theResult___fst_exp__h201972 == 11'd2047) ?
_theResult___snd__h201923[56:5] :
_theResult___fst_sfd__h202696 ;
assign _theResult___fst_sfd__h212289 =
(_theResult___fst_exp__h211488 == 11'd2047) ?
sfdin__h211482[56:5] :
_theResult___fst_sfd__h212286 ;
assign _theResult___fst_sfd__h221041 =
(_theResult___fst_exp__h220289 == 11'd2047) ?
_theResult___snd__h220235[56:5] :
_theResult___fst_sfd__h221038 ;
assign _theResult___fst_sfd__h221050 =
(iFifo$D_OUT[102:95] == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 ?
_theResult___snd_fst_sfd__h202702 :
_theResult___fst_sfd__h186930) :
(SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 ?
_theResult___snd_fst_sfd__h221044 :
_theResult___fst_sfd__h186930) ;
assign _theResult___fst_sfd__h221056 =
((iFifo$D_OUT[102:95] == 8'd255 ||
iFifo$D_OUT[102:95] == 8'd0) &&
iFifo$D_OUT[94:72] == 23'd0) ?
52'd0 :
_theResult___fst_sfd__h221050 ;
assign _theResult___fst_sfd__h241638 =
(_theResult___fst_exp__h240911 == 11'd2047) ?
_theResult___snd__h240862[56:5] :
_theResult___fst_sfd__h241635 ;
assign _theResult___fst_sfd__h251228 =
(_theResult___fst_exp__h250427 == 11'd2047) ?
sfdin__h250421[56:5] :
_theResult___fst_sfd__h251225 ;
assign _theResult___fst_sfd__h259980 =
(_theResult___fst_exp__h259228 == 11'd2047) ?
_theResult___snd__h259174[56:5] :
_theResult___fst_sfd__h259977 ;
assign _theResult___fst_sfd__h259989 =
(iFifo$D_OUT[37:30] == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 ?
_theResult___snd_fst_sfd__h241641 :
_theResult___fst_sfd__h225869) :
(SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 ?
_theResult___snd_fst_sfd__h259983 :
_theResult___fst_sfd__h225869) ;
assign _theResult___fst_sfd__h259995 =
((iFifo$D_OUT[37:30] == 8'd255 || iFifo$D_OUT[37:30] == 8'd0) &&
iFifo$D_OUT[29:7] == 23'd0) ?
52'd0 :
_theResult___fst_sfd__h259989 ;
assign _theResult___fst_sfd__h278320 =
(_theResult___fst_exp__h277722 == 8'd255) ?
sfdin__h277716[56:34] :
_theResult___fst_sfd__h278317 ;
assign _theResult___fst_sfd__h286902 =
(_theResult___fst_exp__h286378 == 8'd255) ?
_theResult___snd__h286329[56:34] :
_theResult___fst_sfd__h286899 ;
assign _theResult___fst_sfd__h296086 =
(_theResult___fst_exp__h295488 == 8'd255) ?
sfdin__h295482[56:34] :
_theResult___fst_sfd__h296083 ;
assign _theResult___fst_sfd__h304722 =
(_theResult___fst_exp__h304173 == 8'd255) ?
_theResult___snd__h304119[56:34] :
_theResult___fst_sfd__h304719 ;
assign _theResult___fst_sfd__h304731 =
(resWire$wget[67:57] == 11'd0) ?
(_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ?
_theResult___snd_fst_sfd__h286905 :
_theResult___fst_sfd__h269596) :
(SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ?
_theResult___snd_fst_sfd__h304725 :
_theResult___fst_sfd__h269596) ;
assign _theResult___fst_sfd__h304737 =
((resWire$wget[67:57] == 11'd2047 ||
resWire$wget[67:57] == 11'd0) &&
resWire$wget[56:5] == 52'd0) ?
23'd0 :
_theResult___fst_sfd__h304731 ;
assign _theResult___fst_sfd__h42608 =
(fpu_div_fState_S4$D_OUT[64:54] == 11'd2047) ?
fpu_div_fState_S4$D_OUT[53:2] :
_theResult___fst_sfd__h42605 ;
assign _theResult___fst_sfd__h95991 =
(fpu_sqr_fState_S4$D_OUT[64:54] == 11'd2047) ?
fpu_sqr_fState_S4$D_OUT[53:2] :
_theResult___fst_sfd__h95988 ;
assign _theResult___fst_sfd__h96608 =
fpu_madd_fOperand_S0$D_OUT[195] ?
fpu_madd_fOperand_S0$D_OUT[182:131] :
52'd0 ;
assign _theResult___sfd__h142542 =
sfd__h142040[53] ?
((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2046) ?
52'd0 :
sfd__h142040[52:1]) :
sfd__h142040[51:0] ;
assign _theResult___sfd__h163980 =
sfd__h163352[53] ?
((_theResult___fst_exp__h163334 == 11'd2046) ?
52'd0 :
sfd__h163352[52:1]) :
sfd__h163352[51:0] ;
assign _theResult___sfd__h173570 =
sfd__h172942[53] ?
((_theResult___fst_exp__h172850 == 11'd2046) ?
52'd0 :
sfd__h172942[52:1]) :
sfd__h172942[51:0] ;
assign _theResult___sfd__h182322 =
sfd__h181670[53] ?
((_theResult___fst_exp__h181651 == 11'd2046) ?
52'd0 :
sfd__h181670[52:1]) :
sfd__h181670[51:0] ;
assign _theResult___sfd__h202618 =
sfd__h201990[53] ?
((_theResult___fst_exp__h201972 == 11'd2046) ?
52'd0 :
sfd__h201990[52:1]) :
sfd__h201990[51:0] ;
assign _theResult___sfd__h212208 =
sfd__h211580[53] ?
((_theResult___fst_exp__h211488 == 11'd2046) ?
52'd0 :
sfd__h211580[52:1]) :
sfd__h211580[51:0] ;
assign _theResult___sfd__h220960 =
sfd__h220308[53] ?
((_theResult___fst_exp__h220289 == 11'd2046) ?
52'd0 :
sfd__h220308[52:1]) :
sfd__h220308[51:0] ;
assign _theResult___sfd__h241557 =
sfd__h240929[53] ?
((_theResult___fst_exp__h240911 == 11'd2046) ?
52'd0 :
sfd__h240929[52:1]) :
sfd__h240929[51:0] ;
assign _theResult___sfd__h251147 =
sfd__h250519[53] ?
((_theResult___fst_exp__h250427 == 11'd2046) ?
52'd0 :
sfd__h250519[52:1]) :
sfd__h250519[51:0] ;
assign _theResult___sfd__h259899 =
sfd__h259247[53] ?
((_theResult___fst_exp__h259228 == 11'd2046) ?
52'd0 :
sfd__h259247[52:1]) :
sfd__h259247[51:0] ;
assign _theResult___sfd__h278239 =
sfd__h277814[24] ?
((_theResult___fst_exp__h277722 == 8'd254) ?
23'd0 :
sfd__h277814[23:1]) :
sfd__h277814[22:0] ;
assign _theResult___sfd__h286821 =
sfd__h286396[24] ?
((_theResult___fst_exp__h286378 == 8'd254) ?
23'd0 :
sfd__h286396[23:1]) :
sfd__h286396[22:0] ;
assign _theResult___sfd__h296005 =
sfd__h295580[24] ?
((_theResult___fst_exp__h295488 == 8'd254) ?
23'd0 :
sfd__h295580[23:1]) :
sfd__h295580[22:0] ;
assign _theResult___sfd__h304641 =
sfd__h304192[24] ?
((_theResult___fst_exp__h304173 == 8'd254) ?
23'd0 :
sfd__h304192[23:1]) :
sfd__h304192[22:0] ;
assign _theResult___sfd__h42527 =
sfd__h42033[53] ?
((fpu_div_fState_S4$D_OUT[64:54] == 11'd2046) ?
52'd0 :
sfd__h42033[52:1]) :
sfd__h42033[51:0] ;
assign _theResult___sfd__h95910 =
sfd__h95416[53] ?
((fpu_sqr_fState_S4$D_OUT[64:54] == 11'd2046) ?
52'd0 :
sfd__h95416[52:1]) :
sfd__h95416[51:0] ;
assign _theResult___snd__h130966 = { sfdBC__h115662[104:0], 1'd0 } ;
assign _theResult___snd__h130980 =
(!sfdBC__h115662[105] && sfdBC__h115662[104]) ?
_theResult___snd__h130982 :
_theResult___snd__h130994 ;
assign _theResult___snd__h130982 = { sfdBC__h115662[103:0], 2'd0 } ;
assign _theResult___snd__h130994 =
(!sfdBC__h115662[105] && !sfdBC__h115662[104] &&
!sfdBC__h115662[103] &&
!sfdBC__h115662[102] &&
!sfdBC__h115662[101] &&
!sfdBC__h115662[100] &&
!sfdBC__h115662[99] &&
!sfdBC__h115662[98] &&
!sfdBC__h115662[97] &&
!sfdBC__h115662[96] &&
!sfdBC__h115662[95] &&
!sfdBC__h115662[94] &&
!sfdBC__h115662[93] &&
!sfdBC__h115662[92] &&
!sfdBC__h115662[91] &&
!sfdBC__h115662[90] &&
!sfdBC__h115662[89] &&
!sfdBC__h115662[88] &&
!sfdBC__h115662[87] &&
!sfdBC__h115662[86] &&
!sfdBC__h115662[85] &&
!sfdBC__h115662[84] &&
!sfdBC__h115662[83] &&
!sfdBC__h115662[82] &&
!sfdBC__h115662[81] &&
!sfdBC__h115662[80] &&
!sfdBC__h115662[79] &&
!sfdBC__h115662[78] &&
!sfdBC__h115662[77] &&
!sfdBC__h115662[76] &&
!sfdBC__h115662[75] &&
!sfdBC__h115662[74] &&
!sfdBC__h115662[73] &&
!sfdBC__h115662[72] &&
!sfdBC__h115662[71] &&
!sfdBC__h115662[70] &&
!sfdBC__h115662[69] &&
!sfdBC__h115662[68] &&
!sfdBC__h115662[67] &&
!sfdBC__h115662[66] &&
!sfdBC__h115662[65] &&
!sfdBC__h115662[64] &&
!sfdBC__h115662[63] &&
!sfdBC__h115662[62] &&
!sfdBC__h115662[61] &&
!sfdBC__h115662[60] &&
!sfdBC__h115662[59] &&
!sfdBC__h115662[58] &&
!sfdBC__h115662[57] &&
!sfdBC__h115662[56] &&
!sfdBC__h115662[55] &&
!sfdBC__h115662[54] &&
!sfdBC__h115662[53] &&
!sfdBC__h115662[52] &&
!sfdBC__h115662[51] &&
!sfdBC__h115662[50] &&
!sfdBC__h115662[49] &&
!sfdBC__h115662[48] &&
!sfdBC__h115662[47] &&
!sfdBC__h115662[46] &&
!sfdBC__h115662[45] &&
!sfdBC__h115662[44] &&
!sfdBC__h115662[43] &&
!sfdBC__h115662[42] &&
!sfdBC__h115662[41] &&
!sfdBC__h115662[40] &&
!sfdBC__h115662[39] &&
!sfdBC__h115662[38] &&
!sfdBC__h115662[37] &&
!sfdBC__h115662[36] &&
!sfdBC__h115662[35] &&
!sfdBC__h115662[34] &&
!sfdBC__h115662[33] &&
!sfdBC__h115662[32] &&
!sfdBC__h115662[31] &&
!sfdBC__h115662[30] &&
!sfdBC__h115662[29] &&
!sfdBC__h115662[28] &&
!sfdBC__h115662[27] &&
!sfdBC__h115662[26] &&
!sfdBC__h115662[25] &&
!sfdBC__h115662[24] &&
!sfdBC__h115662[23] &&
!sfdBC__h115662[22] &&
!sfdBC__h115662[21] &&
!sfdBC__h115662[20] &&
!sfdBC__h115662[19] &&
!sfdBC__h115662[18] &&
!sfdBC__h115662[17] &&
!sfdBC__h115662[16] &&
!sfdBC__h115662[15] &&
!sfdBC__h115662[14] &&
!sfdBC__h115662[13] &&
!sfdBC__h115662[12] &&
!sfdBC__h115662[11] &&
!sfdBC__h115662[10] &&
!sfdBC__h115662[9] &&
!sfdBC__h115662[8] &&
!sfdBC__h115662[7] &&
!sfdBC__h115662[6] &&
!sfdBC__h115662[5] &&
!sfdBC__h115662[4] &&
!sfdBC__h115662[3] &&
!sfdBC__h115662[2] &&
!sfdBC__h115662[1] &&
!sfdBC__h115662[0]) ?
sfdBC__h115662 :
_theResult___snd__h131000 ;
assign _theResult___snd__h131000 =
{ IF_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S_ETC__q24[103:0],
2'd0 } ;
assign _theResult___snd__h131018 =
sfdBC__h115662 <<
IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2462 ;
assign _theResult___snd__h131023 =
sfdBC__h115662 <<
IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460 ;
assign _theResult___snd__h141392 = { sfd__h133119[55:0], 1'd0 } ;
assign _theResult___snd__h141406 =
(!sfd__h133119[56] && sfd__h133119[55]) ?
_theResult___snd__h141408 :
_theResult___snd__h141420 ;
assign _theResult___snd__h141408 = { sfd__h133119[54:0], 2'd0 } ;
assign _theResult___snd__h141420 =
(!sfd__h133119[56] && !sfd__h133119[55] && !sfd__h133119[54] &&
!sfd__h133119[53] &&
!sfd__h133119[52] &&
!sfd__h133119[51] &&
!sfd__h133119[50] &&
!sfd__h133119[49] &&
!sfd__h133119[48] &&
!sfd__h133119[47] &&
!sfd__h133119[46] &&
!sfd__h133119[45] &&
!sfd__h133119[44] &&
!sfd__h133119[43] &&
!sfd__h133119[42] &&
!sfd__h133119[41] &&
!sfd__h133119[40] &&
!sfd__h133119[39] &&
!sfd__h133119[38] &&
!sfd__h133119[37] &&
!sfd__h133119[36] &&
!sfd__h133119[35] &&
!sfd__h133119[34] &&
!sfd__h133119[33] &&
!sfd__h133119[32] &&
!sfd__h133119[31] &&
!sfd__h133119[30] &&
!sfd__h133119[29] &&
!sfd__h133119[28] &&
!sfd__h133119[27] &&
!sfd__h133119[26] &&
!sfd__h133119[25] &&
!sfd__h133119[24] &&
!sfd__h133119[23] &&
!sfd__h133119[22] &&
!sfd__h133119[21] &&
!sfd__h133119[20] &&
!sfd__h133119[19] &&
!sfd__h133119[18] &&
!sfd__h133119[17] &&
!sfd__h133119[16] &&
!sfd__h133119[15] &&
!sfd__h133119[14] &&
!sfd__h133119[13] &&
!sfd__h133119[12] &&
!sfd__h133119[11] &&
!sfd__h133119[10] &&
!sfd__h133119[9] &&
!sfd__h133119[8] &&
!sfd__h133119[7] &&
!sfd__h133119[6] &&
!sfd__h133119[5] &&
!sfd__h133119[4] &&
!sfd__h133119[3] &&
!sfd__h133119[2] &&
!sfd__h133119[1] &&
!sfd__h133119[0]) ?
sfd__h133119 :
_theResult___snd__h141426 ;
assign _theResult___snd__h141426 =
{ IF_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__65_ETC__q29[54:0],
2'd0 } ;
assign _theResult___snd__h141444 =
sfd__h133119 <<
IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2903 ;
assign _theResult___snd__h141449 =
sfd__h133119 <<
IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901 ;
assign _theResult___snd__h163285 =
(iFifo$D_OUT[167:160] == 8'd0) ?
_theResult___snd__h163294 :
_theResult___snd__h163287 ;
assign _theResult___snd__h163287 = { iFifo$D_OUT[159:137], 34'd0 } ;
assign _theResult___snd__h163294 =
(iFifo$D_OUT[167:160] == 8'd0 && !iFifo$D_OUT[159] &&
NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244) ?
sfd__h144534 :
_theResult___snd__h163300 ;
assign _theResult___snd__h163300 =
{ IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q33[54:0],
2'd0 } ;
assign _theResult___snd__h163323 =
sfd__h144534 <<
IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 ;
assign _theResult___snd__h172861 = { _theResult____h164612[55:0], 1'd0 } ;
assign _theResult___snd__h172872 =
(!_theResult____h164612[56] && _theResult____h164612[55]) ?
_theResult___snd__h172874 :
_theResult___snd__h172884 ;
assign _theResult___snd__h172874 = { _theResult____h164612[54:0], 2'd0 } ;
assign _theResult___snd__h172884 =
(!_theResult____h164612[56] && !_theResult____h164612[55] &&
!_theResult____h164612[54] &&
!_theResult____h164612[53] &&
!_theResult____h164612[52] &&
!_theResult____h164612[51] &&
!_theResult____h164612[50] &&
!_theResult____h164612[49] &&
!_theResult____h164612[48] &&
!_theResult____h164612[47] &&
!_theResult____h164612[46] &&
!_theResult____h164612[45] &&
!_theResult____h164612[44] &&
!_theResult____h164612[43] &&
!_theResult____h164612[42] &&
!_theResult____h164612[41] &&
!_theResult____h164612[40] &&
!_theResult____h164612[39] &&
!_theResult____h164612[38] &&
!_theResult____h164612[37] &&
!_theResult____h164612[36] &&
!_theResult____h164612[35] &&
!_theResult____h164612[34] &&
!_theResult____h164612[33] &&
!_theResult____h164612[32] &&
!_theResult____h164612[31] &&
!_theResult____h164612[30] &&
!_theResult____h164612[29] &&
!_theResult____h164612[28] &&
!_theResult____h164612[27] &&
!_theResult____h164612[26] &&
!_theResult____h164612[25] &&
!_theResult____h164612[24] &&
!_theResult____h164612[23] &&
!_theResult____h164612[22] &&
!_theResult____h164612[21] &&
!_theResult____h164612[20] &&
!_theResult____h164612[19] &&
!_theResult____h164612[18] &&
!_theResult____h164612[17] &&
!_theResult____h164612[16] &&
!_theResult____h164612[15] &&
!_theResult____h164612[14] &&
!_theResult____h164612[13] &&
!_theResult____h164612[12] &&
!_theResult____h164612[11] &&
!_theResult____h164612[10] &&
!_theResult____h164612[9] &&
!_theResult____h164612[8] &&
!_theResult____h164612[7] &&
!_theResult____h164612[6] &&
!_theResult____h164612[5] &&
!_theResult____h164612[4] &&
!_theResult____h164612[3] &&
!_theResult____h164612[2] &&
!_theResult____h164612[1] &&
!_theResult____h164612[0]) ?
_theResult____h164612 :
_theResult___snd__h172890 ;
assign _theResult___snd__h172890 =
{ IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q37[54:0],
2'd0 } ;
assign _theResult___snd__h172913 =
_theResult____h164612 <<
IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572 ;
assign _theResult___snd__h181597 =
(iFifo$D_OUT[167:160] == 8'd0) ?
_theResult___snd__h181611 :
_theResult___snd__h163287 ;
assign _theResult___snd__h181611 =
(iFifo$D_OUT[167:160] == 8'd0 && !iFifo$D_OUT[159] &&
NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244) ?
sfd__h144534 :
_theResult___snd__h181617 ;
assign _theResult___snd__h181617 =
{ IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q40[54:0],
2'd0 } ;
assign _theResult___snd__h181635 =
sfd__h144534 <<
IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3623 ;
assign _theResult___snd__h201923 =
(iFifo$D_OUT[102:95] == 8'd0) ?
_theResult___snd__h201932 :
_theResult___snd__h201925 ;
assign _theResult___snd__h201925 = { iFifo$D_OUT[94:72], 34'd0 } ;
assign _theResult___snd__h201932 =
(iFifo$D_OUT[102:95] == 8'd0 && !iFifo$D_OUT[94] &&
NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730) ?
sfd__h183174 :
_theResult___snd__h201938 ;
assign _theResult___snd__h201938 =
{ IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q93[54:0],
2'd0 } ;
assign _theResult___snd__h201961 =
sfd__h183174 <<
IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 ;
assign _theResult___snd__h211499 = { _theResult____h203250[55:0], 1'd0 } ;
assign _theResult___snd__h211510 =
(!_theResult____h203250[56] && _theResult____h203250[55]) ?
_theResult___snd__h211512 :
_theResult___snd__h211522 ;
assign _theResult___snd__h211512 = { _theResult____h203250[54:0], 2'd0 } ;
assign _theResult___snd__h211522 =
(!_theResult____h203250[56] && !_theResult____h203250[55] &&
!_theResult____h203250[54] &&
!_theResult____h203250[53] &&
!_theResult____h203250[52] &&
!_theResult____h203250[51] &&
!_theResult____h203250[50] &&
!_theResult____h203250[49] &&
!_theResult____h203250[48] &&
!_theResult____h203250[47] &&
!_theResult____h203250[46] &&
!_theResult____h203250[45] &&
!_theResult____h203250[44] &&
!_theResult____h203250[43] &&
!_theResult____h203250[42] &&
!_theResult____h203250[41] &&
!_theResult____h203250[40] &&
!_theResult____h203250[39] &&
!_theResult____h203250[38] &&
!_theResult____h203250[37] &&
!_theResult____h203250[36] &&
!_theResult____h203250[35] &&
!_theResult____h203250[34] &&
!_theResult____h203250[33] &&
!_theResult____h203250[32] &&
!_theResult____h203250[31] &&
!_theResult____h203250[30] &&
!_theResult____h203250[29] &&
!_theResult____h203250[28] &&
!_theResult____h203250[27] &&
!_theResult____h203250[26] &&
!_theResult____h203250[25] &&
!_theResult____h203250[24] &&
!_theResult____h203250[23] &&
!_theResult____h203250[22] &&
!_theResult____h203250[21] &&
!_theResult____h203250[20] &&
!_theResult____h203250[19] &&
!_theResult____h203250[18] &&
!_theResult____h203250[17] &&
!_theResult____h203250[16] &&
!_theResult____h203250[15] &&
!_theResult____h203250[14] &&
!_theResult____h203250[13] &&
!_theResult____h203250[12] &&
!_theResult____h203250[11] &&
!_theResult____h203250[10] &&
!_theResult____h203250[9] &&
!_theResult____h203250[8] &&
!_theResult____h203250[7] &&
!_theResult____h203250[6] &&
!_theResult____h203250[5] &&
!_theResult____h203250[4] &&
!_theResult____h203250[3] &&
!_theResult____h203250[2] &&
!_theResult____h203250[1] &&
!_theResult____h203250[0]) ?
_theResult____h203250 :
_theResult___snd__h211528 ;
assign _theResult___snd__h211528 =
{ IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q97[54:0],
2'd0 } ;
assign _theResult___snd__h211551 =
_theResult____h203250 <<
IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055 ;
assign _theResult___snd__h220235 =
(iFifo$D_OUT[102:95] == 8'd0) ?
_theResult___snd__h220249 :
_theResult___snd__h201925 ;
assign _theResult___snd__h220249 =
(iFifo$D_OUT[102:95] == 8'd0 && !iFifo$D_OUT[94] &&
NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730) ?
sfd__h183174 :
_theResult___snd__h220255 ;
assign _theResult___snd__h220255 =
{ IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q100[54:0],
2'd0 } ;
assign _theResult___snd__h220273 =
sfd__h183174 <<
IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5106 ;
assign _theResult___snd__h240862 =
(iFifo$D_OUT[37:30] == 8'd0) ?
_theResult___snd__h240871 :
_theResult___snd__h240864 ;
assign _theResult___snd__h240864 = { iFifo$D_OUT[29:7], 34'd0 } ;
assign _theResult___snd__h240871 =
(iFifo$D_OUT[37:30] == 8'd0 && !iFifo$D_OUT[29] &&
NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955) ?
sfd__h222113 :
_theResult___snd__h240877 ;
assign _theResult___snd__h240877 =
{ IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q60[54:0],
2'd0 } ;
assign _theResult___snd__h240900 =
sfd__h222113 <<
IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 ;
assign _theResult___snd__h250438 = { _theResult____h242189[55:0], 1'd0 } ;
assign _theResult___snd__h250449 =
(!_theResult____h242189[56] && _theResult____h242189[55]) ?
_theResult___snd__h250451 :
_theResult___snd__h250461 ;
assign _theResult___snd__h250451 = { _theResult____h242189[54:0], 2'd0 } ;
assign _theResult___snd__h250461 =
(!_theResult____h242189[56] && !_theResult____h242189[55] &&
!_theResult____h242189[54] &&
!_theResult____h242189[53] &&
!_theResult____h242189[52] &&
!_theResult____h242189[51] &&
!_theResult____h242189[50] &&
!_theResult____h242189[49] &&
!_theResult____h242189[48] &&
!_theResult____h242189[47] &&
!_theResult____h242189[46] &&
!_theResult____h242189[45] &&
!_theResult____h242189[44] &&
!_theResult____h242189[43] &&
!_theResult____h242189[42] &&
!_theResult____h242189[41] &&
!_theResult____h242189[40] &&
!_theResult____h242189[39] &&
!_theResult____h242189[38] &&
!_theResult____h242189[37] &&
!_theResult____h242189[36] &&
!_theResult____h242189[35] &&
!_theResult____h242189[34] &&
!_theResult____h242189[33] &&
!_theResult____h242189[32] &&
!_theResult____h242189[31] &&
!_theResult____h242189[30] &&
!_theResult____h242189[29] &&
!_theResult____h242189[28] &&
!_theResult____h242189[27] &&
!_theResult____h242189[26] &&
!_theResult____h242189[25] &&
!_theResult____h242189[24] &&
!_theResult____h242189[23] &&
!_theResult____h242189[22] &&
!_theResult____h242189[21] &&
!_theResult____h242189[20] &&
!_theResult____h242189[19] &&
!_theResult____h242189[18] &&
!_theResult____h242189[17] &&
!_theResult____h242189[16] &&
!_theResult____h242189[15] &&
!_theResult____h242189[14] &&
!_theResult____h242189[13] &&
!_theResult____h242189[12] &&
!_theResult____h242189[11] &&
!_theResult____h242189[10] &&
!_theResult____h242189[9] &&
!_theResult____h242189[8] &&
!_theResult____h242189[7] &&
!_theResult____h242189[6] &&
!_theResult____h242189[5] &&
!_theResult____h242189[4] &&
!_theResult____h242189[3] &&
!_theResult____h242189[2] &&
!_theResult____h242189[1] &&
!_theResult____h242189[0]) ?
_theResult____h242189 :
_theResult___snd__h250467 ;
assign _theResult___snd__h250467 =
{ IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q64[54:0],
2'd0 } ;
assign _theResult___snd__h250490 =
_theResult____h242189 <<
IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280 ;
assign _theResult___snd__h259174 =
(iFifo$D_OUT[37:30] == 8'd0) ?
_theResult___snd__h259188 :
_theResult___snd__h240864 ;
assign _theResult___snd__h259188 =
(iFifo$D_OUT[37:30] == 8'd0 && !iFifo$D_OUT[29] &&
NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955) ?
sfd__h222113 :
_theResult___snd__h259194 ;
assign _theResult___snd__h259194 =
{ IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q67[54:0],
2'd0 } ;
assign _theResult___snd__h259212 =
sfd__h222113 <<
IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4331 ;
assign _theResult___snd__h277733 = { _theResult____h269613[55:0], 1'd0 } ;
assign _theResult___snd__h277744 =
(!_theResult____h269613[56] && _theResult____h269613[55]) ?
_theResult___snd__h277746 :
_theResult___snd__h277756 ;
assign _theResult___snd__h277746 = { _theResult____h269613[54:0], 2'd0 } ;
assign _theResult___snd__h277756 =
(!_theResult____h269613[56] && !_theResult____h269613[55] &&
!_theResult____h269613[54] &&
!_theResult____h269613[53] &&
!_theResult____h269613[52] &&
!_theResult____h269613[51] &&
!_theResult____h269613[50] &&
!_theResult____h269613[49] &&
!_theResult____h269613[48] &&
!_theResult____h269613[47] &&
!_theResult____h269613[46] &&
!_theResult____h269613[45] &&
!_theResult____h269613[44] &&
!_theResult____h269613[43] &&
!_theResult____h269613[42] &&
!_theResult____h269613[41] &&
!_theResult____h269613[40] &&
!_theResult____h269613[39] &&
!_theResult____h269613[38] &&
!_theResult____h269613[37] &&
!_theResult____h269613[36] &&
!_theResult____h269613[35] &&
!_theResult____h269613[34] &&
!_theResult____h269613[33] &&
!_theResult____h269613[32] &&
!_theResult____h269613[31] &&
!_theResult____h269613[30] &&
!_theResult____h269613[29] &&
!_theResult____h269613[28] &&
!_theResult____h269613[27] &&
!_theResult____h269613[26] &&
!_theResult____h269613[25] &&
!_theResult____h269613[24] &&
!_theResult____h269613[23] &&
!_theResult____h269613[22] &&
!_theResult____h269613[21] &&
!_theResult____h269613[20] &&
!_theResult____h269613[19] &&
!_theResult____h269613[18] &&
!_theResult____h269613[17] &&
!_theResult____h269613[16] &&
!_theResult____h269613[15] &&
!_theResult____h269613[14] &&
!_theResult____h269613[13] &&
!_theResult____h269613[12] &&
!_theResult____h269613[11] &&
!_theResult____h269613[10] &&
!_theResult____h269613[9] &&
!_theResult____h269613[8] &&
!_theResult____h269613[7] &&
!_theResult____h269613[6] &&
!_theResult____h269613[5] &&
!_theResult____h269613[4] &&
!_theResult____h269613[3] &&
!_theResult____h269613[2] &&
!_theResult____h269613[1] &&
!_theResult____h269613[0]) ?
_theResult____h269613 :
_theResult___snd__h277762 ;
assign _theResult___snd__h277762 =
{ IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__ETC__q133[54:0],
2'd0 } ;
assign _theResult___snd__h277785 =
_theResult____h269613 <<
IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767 ;
assign _theResult___snd__h286329 =
(resWire$wget[67:57] == 11'd0) ?
_theResult___snd__h286338 :
_theResult___snd__h286331 ;
assign _theResult___snd__h286331 = { resWire$wget[56:5], 5'd0 } ;
assign _theResult___snd__h286338 =
(resWire$wget[67:57] == 11'd0 &&
NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927) ?
sfd__h262011 :
_theResult___snd__h286344 ;
assign _theResult___snd__h286344 =
{ IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q135[54:0],
2'd0 } ;
assign _theResult___snd__h286367 =
sfd__h262011 <<
IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 ;
assign _theResult___snd__h295499 = { _theResult____h287250[55:0], 1'd0 } ;
assign _theResult___snd__h295510 =
(!_theResult____h287250[56] && _theResult____h287250[55]) ?
_theResult___snd__h295512 :
_theResult___snd__h295522 ;
assign _theResult___snd__h295512 = { _theResult____h287250[54:0], 2'd0 } ;
assign _theResult___snd__h295522 =
(!_theResult____h287250[56] && !_theResult____h287250[55] &&
!_theResult____h287250[54] &&
!_theResult____h287250[53] &&
!_theResult____h287250[52] &&
!_theResult____h287250[51] &&
!_theResult____h287250[50] &&
!_theResult____h287250[49] &&
!_theResult____h287250[48] &&
!_theResult____h287250[47] &&
!_theResult____h287250[46] &&
!_theResult____h287250[45] &&
!_theResult____h287250[44] &&
!_theResult____h287250[43] &&
!_theResult____h287250[42] &&
!_theResult____h287250[41] &&
!_theResult____h287250[40] &&
!_theResult____h287250[39] &&
!_theResult____h287250[38] &&
!_theResult____h287250[37] &&
!_theResult____h287250[36] &&
!_theResult____h287250[35] &&
!_theResult____h287250[34] &&
!_theResult____h287250[33] &&
!_theResult____h287250[32] &&
!_theResult____h287250[31] &&
!_theResult____h287250[30] &&
!_theResult____h287250[29] &&
!_theResult____h287250[28] &&
!_theResult____h287250[27] &&
!_theResult____h287250[26] &&
!_theResult____h287250[25] &&
!_theResult____h287250[24] &&
!_theResult____h287250[23] &&
!_theResult____h287250[22] &&
!_theResult____h287250[21] &&
!_theResult____h287250[20] &&
!_theResult____h287250[19] &&
!_theResult____h287250[18] &&
!_theResult____h287250[17] &&
!_theResult____h287250[16] &&
!_theResult____h287250[15] &&
!_theResult____h287250[14] &&
!_theResult____h287250[13] &&
!_theResult____h287250[12] &&
!_theResult____h287250[11] &&
!_theResult____h287250[10] &&
!_theResult____h287250[9] &&
!_theResult____h287250[8] &&
!_theResult____h287250[7] &&
!_theResult____h287250[6] &&
!_theResult____h287250[5] &&
!_theResult____h287250[4] &&
!_theResult____h287250[3] &&
!_theResult____h287250[2] &&
!_theResult____h287250[1] &&
!_theResult____h287250[0]) ?
_theResult____h287250 :
_theResult___snd__h295528 ;
assign _theResult___snd__h295528 =
{ IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget_ETC__q139[54:0],
2'd0 } ;
assign _theResult___snd__h295551 =
_theResult____h287250 <<
IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278 ;
assign _theResult___snd__h304119 =
(resWire$wget[67:57] == 11'd0) ?
_theResult___snd__h304133 :
_theResult___snd__h286331 ;
assign _theResult___snd__h304133 =
(resWire$wget[67:57] == 11'd0 &&
NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927) ?
sfd__h262011 :
_theResult___snd__h304139 ;
assign _theResult___snd__h304139 =
{ IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q142[54:0],
2'd0 } ;
assign _theResult___snd__h304157 =
sfd__h262011 <<
IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6332 ;
assign _theResult___snd__h33766 = { fpu_div_fState_S3$D_OUT[56:0], 1'd0 } ;
assign _theResult___snd__h41401 = { sfdin__h33169[56:0], 1'd0 } ;
assign _theResult___snd__h41416 =
(!sfdin__h33169[57] && sfdin__h33169[56]) ?
_theResult___snd__h41418 :
_theResult___snd__h41431 ;
assign _theResult___snd__h41418 = { sfdin__h33169[55:0], 2'd0 } ;
assign _theResult___snd__h41431 =
(!sfdin__h33169[57] && !sfdin__h33169[56] &&
!sfdin__h33169[55] &&
!sfdin__h33169[54] &&
!sfdin__h33169[53] &&
!sfdin__h33169[52] &&
!sfdin__h33169[51] &&
!sfdin__h33169[50] &&
!sfdin__h33169[49] &&
!sfdin__h33169[48] &&
!sfdin__h33169[47] &&
!sfdin__h33169[46] &&
!sfdin__h33169[45] &&
!sfdin__h33169[44] &&
!sfdin__h33169[43] &&
!sfdin__h33169[42] &&
!sfdin__h33169[41] &&
!sfdin__h33169[40] &&
!sfdin__h33169[39] &&
!sfdin__h33169[38] &&
!sfdin__h33169[37] &&
!sfdin__h33169[36] &&
!sfdin__h33169[35] &&
!sfdin__h33169[34] &&
!sfdin__h33169[33] &&
!sfdin__h33169[32] &&
!sfdin__h33169[31] &&
!sfdin__h33169[30] &&
!sfdin__h33169[29] &&
!sfdin__h33169[28] &&
!sfdin__h33169[27] &&
!sfdin__h33169[26] &&
!sfdin__h33169[25] &&
!sfdin__h33169[24] &&
!sfdin__h33169[23] &&
!sfdin__h33169[22] &&
!sfdin__h33169[21] &&
!sfdin__h33169[20] &&
!sfdin__h33169[19] &&
!sfdin__h33169[18] &&
!sfdin__h33169[17] &&
!sfdin__h33169[16] &&
!sfdin__h33169[15] &&
!sfdin__h33169[14] &&
!sfdin__h33169[13] &&
!sfdin__h33169[12] &&
!sfdin__h33169[11] &&
!sfdin__h33169[10] &&
!sfdin__h33169[9] &&
!sfdin__h33169[8] &&
!sfdin__h33169[7] &&
!sfdin__h33169[6] &&
!sfdin__h33169[5] &&
!sfdin__h33169[4] &&
!sfdin__h33169[3] &&
!sfdin__h33169[2] &&
!sfdin__h33169[1] &&
!sfdin__h33169[0]) ?
sfdin__h33169 :
_theResult___snd__h41437 ;
assign _theResult___snd__h41437 =
{ IF_0_CONCAT_IF_IF_fpu_div_fState_S3_first__16__ETC__q12[55:0],
2'd0 } ;
assign _theResult___snd__h41455 =
sfdin__h33169 <<
IF_IF_fpu_div_fState_S3_first__16_BITS_120_TO__ETC___d812 ;
assign _theResult___snd__h41460 =
sfdin__h33169 <<
IF_IF_fpu_div_fState_S3_first__16_BITS_120_TO__ETC___d810 ;
assign _theResult___snd__h94767 = { fpu_sqr_fState_S3$D_OUT[57:0], 1'd0 } ;
assign _theResult___snd__h94782 =
(!fpu_sqr_fState_S3$D_OUT[58] && fpu_sqr_fState_S3$D_OUT[57]) ?
_theResult___snd__h94784 :
_theResult___snd__h94797 ;
assign _theResult___snd__h94784 = { fpu_sqr_fState_S3$D_OUT[56:0], 2'd0 } ;
assign _theResult___snd__h94797 =
(!fpu_sqr_fState_S3$D_OUT[58] && !fpu_sqr_fState_S3$D_OUT[57] &&
!fpu_sqr_fState_S3$D_OUT[56] &&
!fpu_sqr_fState_S3$D_OUT[55] &&
!fpu_sqr_fState_S3$D_OUT[54] &&
!fpu_sqr_fState_S3$D_OUT[53] &&
!fpu_sqr_fState_S3$D_OUT[52] &&
!fpu_sqr_fState_S3$D_OUT[51] &&
!fpu_sqr_fState_S3$D_OUT[50] &&
!fpu_sqr_fState_S3$D_OUT[49] &&
!fpu_sqr_fState_S3$D_OUT[48] &&
!fpu_sqr_fState_S3$D_OUT[47] &&
!fpu_sqr_fState_S3$D_OUT[46] &&
!fpu_sqr_fState_S3$D_OUT[45] &&
!fpu_sqr_fState_S3$D_OUT[44] &&
!fpu_sqr_fState_S3$D_OUT[43] &&
!fpu_sqr_fState_S3$D_OUT[42] &&
!fpu_sqr_fState_S3$D_OUT[41] &&
!fpu_sqr_fState_S3$D_OUT[40] &&
!fpu_sqr_fState_S3$D_OUT[39] &&
!fpu_sqr_fState_S3$D_OUT[38] &&
!fpu_sqr_fState_S3$D_OUT[37] &&
!fpu_sqr_fState_S3$D_OUT[36] &&
!fpu_sqr_fState_S3$D_OUT[35] &&
!fpu_sqr_fState_S3$D_OUT[34] &&
!fpu_sqr_fState_S3$D_OUT[33] &&
!fpu_sqr_fState_S3$D_OUT[32] &&
!fpu_sqr_fState_S3$D_OUT[31] &&
!fpu_sqr_fState_S3$D_OUT[30] &&
!fpu_sqr_fState_S3$D_OUT[29] &&
!fpu_sqr_fState_S3$D_OUT[28] &&
!fpu_sqr_fState_S3$D_OUT[27] &&
!fpu_sqr_fState_S3$D_OUT[26] &&
!fpu_sqr_fState_S3$D_OUT[25] &&
!fpu_sqr_fState_S3$D_OUT[24] &&
!fpu_sqr_fState_S3$D_OUT[23] &&
!fpu_sqr_fState_S3$D_OUT[22] &&
!fpu_sqr_fState_S3$D_OUT[21] &&
!fpu_sqr_fState_S3$D_OUT[20] &&
!fpu_sqr_fState_S3$D_OUT[19] &&
!fpu_sqr_fState_S3$D_OUT[18] &&
!fpu_sqr_fState_S3$D_OUT[17] &&
!fpu_sqr_fState_S3$D_OUT[16] &&
!fpu_sqr_fState_S3$D_OUT[15] &&
!fpu_sqr_fState_S3$D_OUT[14] &&
!fpu_sqr_fState_S3$D_OUT[13] &&
!fpu_sqr_fState_S3$D_OUT[12] &&
!fpu_sqr_fState_S3$D_OUT[11] &&
!fpu_sqr_fState_S3$D_OUT[10] &&
!fpu_sqr_fState_S3$D_OUT[9] &&
!fpu_sqr_fState_S3$D_OUT[8] &&
!fpu_sqr_fState_S3$D_OUT[7] &&
!fpu_sqr_fState_S3$D_OUT[6] &&
!fpu_sqr_fState_S3$D_OUT[5] &&
!fpu_sqr_fState_S3$D_OUT[4] &&
!fpu_sqr_fState_S3$D_OUT[3] &&
!fpu_sqr_fState_S3$D_OUT[2] &&
!fpu_sqr_fState_S3$D_OUT[1] &&
!fpu_sqr_fState_S3$D_OUT[0]) ?
fpu_sqr_fState_S3$D_OUT[58:0] :
_theResult___snd__h94803 ;
assign _theResult___snd__h94803 =
{ IF_0_CONCAT_IF_fpu_sqr_fState_S3_first__375_BI_ETC__q19[56:0],
2'd0 } ;
assign _theResult___snd__h94821 =
fpu_sqr_fState_S3$D_OUT[58:0] <<
IF_fpu_sqr_fState_S3_first__375_BITS_121_TO_11_ETC___d1632 ;
assign _theResult___snd__h94826 =
fpu_sqr_fState_S3$D_OUT[58:0] <<
IF_fpu_sqr_fState_S3_first__375_BIT_58_384_THE_ETC___d1630 ;
assign _theResult___snd_fst__h131051 =
{ IF_sfdin30943_BIT_53_THEN_2_ELSE_0__q25[1],
{ sfdin__h130943[52:0], 52'd0 } != 105'd0 } ;
assign _theResult___snd_fst__h141477 =
{ IF_sfdin41369_BIT_4_THEN_2_ELSE_0__q30[1],
{ sfdin__h141369[3:0], 52'd0 } != 56'd0 } ;
assign _theResult___snd_fst__h41490 =
{ IF_sfdin1378_BIT_5_THEN_2_ELSE_0__q13[1],
{ sfdin__h41378[4:0], 52'd0 } != 57'd0 } ;
assign _theResult___snd_fst__h43500 =
IF_rg_index_1_87_ULE_58_91_THEN_NOT_rg_b_92_EQ_ETC___d1009 ?
_theResult___snd_fst__h43624 :
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1036 ;
assign _theResult___snd_fst__h43539 =
(rg_res[116] || rg_b == 116'd0 ||
rg_s_014_ULT_rg_r_1_013_PLUS_rg_b_92_015___d1016) ?
rg_s :
s__h43680 ;
assign _theResult___snd_fst__h43624 =
(IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1002 ==
116'd0 ||
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1038) ?
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1036 :
s__h43745 ;
assign _theResult___snd_fst__h94856 =
{ IF_sfdin4744_BIT_6_THEN_2_ELSE_0__q20[1],
{ sfdin__h94744[5:0], 52'd0 } != 58'd0 } ;
assign _theResult___snd_fst_exp__h164063 =
_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190 ?
11'd0 :
_theResult___fst_exp__h164060 ;
assign _theResult___snd_fst_exp__h182405 =
SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325 ?
_theResult___fst_exp__h173650 :
_theResult___fst_exp__h182402 ;
assign _theResult___snd_fst_exp__h202701 =
_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 ?
11'd0 :
_theResult___fst_exp__h202698 ;
assign _theResult___snd_fst_exp__h221043 =
SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 ?
_theResult___fst_exp__h212288 :
_theResult___fst_exp__h221040 ;
assign _theResult___snd_fst_exp__h241640 =
_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 ?
11'd0 :
_theResult___fst_exp__h241637 ;
assign _theResult___snd_fst_exp__h259982 =
SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 ?
_theResult___fst_exp__h251227 :
_theResult___fst_exp__h259979 ;
assign _theResult___snd_fst_exp__h286904 =
_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ?
_theResult___fst_exp__h278319 :
_theResult___fst_exp__h286901 ;
assign _theResult___snd_fst_exp__h30385 =
(IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d285 ||
IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d429) ?
11'd0 :
value__h30425[10:0] ;
assign _theResult___snd_fst_exp__h30388 =
IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d283 ?
_theResult___snd_fst_exp__h30385 :
11'd2046 ;
assign _theResult___snd_fst_exp__h30412 =
fpu_div_fOperands_S0_first__6_BITS_129_TO_119__ETC___d428 ?
11'd0 :
_theResult___snd_fst_exp__h30388 ;
assign _theResult___snd_fst_exp__h304724 =
SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ?
_theResult___fst_exp__h296085 :
_theResult___fst_exp__h304721 ;
assign _theResult___snd_fst_sfd__h144484 =
(iFifo$D_OUT[159:137] == 23'd0) ?
52'h4000000000000 :
out___1_sfd__h144233 ;
assign _theResult___snd_fst_sfd__h164064 =
_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190 ?
52'd0 :
_theResult___fst_sfd__h164061 ;
assign _theResult___snd_fst_sfd__h182406 =
SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325 ?
_theResult___fst_sfd__h173651 :
_theResult___fst_sfd__h182403 ;
assign _theResult___snd_fst_sfd__h183124 =
(iFifo$D_OUT[94:72] == 23'd0) ?
52'h4000000000000 :
out___1_sfd__h182873 ;
assign _theResult___snd_fst_sfd__h202702 =
_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 ?
52'd0 :
_theResult___fst_sfd__h202699 ;
assign _theResult___snd_fst_sfd__h221044 =
SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 ?
_theResult___fst_sfd__h212289 :
_theResult___fst_sfd__h221041 ;
assign _theResult___snd_fst_sfd__h222063 =
(iFifo$D_OUT[29:7] == 23'd0) ?
52'h4000000000000 :
out___1_sfd__h221812 ;
assign _theResult___snd_fst_sfd__h241641 =
_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 ?
52'd0 :
_theResult___fst_sfd__h241638 ;
assign _theResult___snd_fst_sfd__h259983 =
SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 ?
_theResult___fst_sfd__h251228 :
_theResult___fst_sfd__h259980 ;
assign _theResult___snd_fst_sfd__h261961 =
(resWire$wget[56:34] == 23'd0) ?
23'd2097152 :
resWire$wget[56:34] ;
assign _theResult___snd_fst_sfd__h286905 =
_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ?
_theResult___fst_sfd__h278320 :
_theResult___fst_sfd__h286902 ;
assign _theResult___snd_fst_sfd__h30413 =
(fpu_div_fOperands_S0_first__6_BITS_129_TO_119__ETC___d428 ||
IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d283) ?
52'd0 :
52'hFFFFFFFFFFFFF ;
assign _theResult___snd_fst_sfd__h304725 =
SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ?
_theResult___fst_sfd__h296086 :
_theResult___fst_sfd__h304722 ;
assign _theResult___snd_snd__h131371 =
(fpu_madd_fProd_S3$D_OUT == 106'd0) ? 2'd0 : 2'd1 ;
assign _theResult___snd_snd__h43671 =
rg_s_014_ULT_rg_r_1_013_PLUS_rg_b_92_015___d1016 ?
r__h43685 :
r__h43681 ;
assign _theResult___snd_snd__h43737 =
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1038 ?
r__h43775 :
r__h43746 ;
assign _theResult___snd_snd_snd__h131369 =
fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ?
_theResult___snd_snd__h131371 :
guardBC__h115666 ;
assign _theResult___snd_snd_snd__h33014 =
(fpu_div_fState_S3$D_OUT[57:56] == 2'b0) ?
_theResult___snd__h33766 :
fpu_div_fState_S3$D_OUT[57:0] ;
assign _theResult___snd_snd_snd__h43503 =
IF_rg_index_1_87_ULE_58_91_THEN_NOT_rg_b_92_EQ_ETC___d1009 ?
_theResult___snd_snd_snd__h43627 :
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1022 ;
assign _theResult___snd_snd_snd__h43542 =
(rg_res[116] || rg_b == 116'd0) ?
rg_r_1 :
_theResult___snd_snd__h43671 ;
assign _theResult___snd_snd_snd__h43627 =
(IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1002 ==
116'd0) ?
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1022 :
_theResult___snd_snd__h43737 ;
assign b___1__h77160 = 116'h40000000000000000000000000000 >> x__h85465 ;
assign b__h10508 =
(fpu_div_fOperands_S0$D_OUT[65:55] == 11'd0) ?
(fpu_div_fOperands_S0$D_OUT[54] ?
6'd1 :
(fpu_div_fOperands_S0$D_OUT[53] ?
6'd2 :
(fpu_div_fOperands_S0$D_OUT[52] ?
6'd3 :
(fpu_div_fOperands_S0$D_OUT[51] ?
6'd4 :
(fpu_div_fOperands_S0$D_OUT[50] ?
6'd5 :
(fpu_div_fOperands_S0$D_OUT[49] ?
6'd6 :
(fpu_div_fOperands_S0$D_OUT[48] ?
6'd7 :
(fpu_div_fOperands_S0$D_OUT[47] ?
6'd8 :
(fpu_div_fOperands_S0$D_OUT[46] ?
6'd9 :
(fpu_div_fOperands_S0$D_OUT[45] ?
6'd10 :
(fpu_div_fOperands_S0$D_OUT[44] ?
6'd11 :
(fpu_div_fOperands_S0$D_OUT[43] ?
6'd12 :
(fpu_div_fOperands_S0$D_OUT[42] ?
6'd13 :
(fpu_div_fOperands_S0$D_OUT[41] ?
6'd14 :
(fpu_div_fOperands_S0$D_OUT[40] ?
6'd15 :
(fpu_div_fOperands_S0$D_OUT[39] ?
6'd16 :
(fpu_div_fOperands_S0$D_OUT[38] ?
6'd17 :
(fpu_div_fOperands_S0$D_OUT[37] ?
6'd18 :
(fpu_div_fOperands_S0$D_OUT[36] ?
6'd19 :
(fpu_div_fOperands_S0$D_OUT[35] ?
6'd20 :
(fpu_div_fOperands_S0$D_OUT[34] ?
6'd21 :
(fpu_div_fOperands_S0$D_OUT[33] ?
6'd22 :
(fpu_div_fOperands_S0$D_OUT[32] ?
6'd23 :
(fpu_div_fOperands_S0$D_OUT[31] ?
6'd24 :
(fpu_div_fOperands_S0$D_OUT[30] ?
6'd25 :
(fpu_div_fOperands_S0$D_OUT[29] ?
6'd26 :
(fpu_div_fOperands_S0$D_OUT[28] ?
6'd27 :
(fpu_div_fOperands_S0$D_OUT[27] ?
6'd28 :
(fpu_div_fOperands_S0$D_OUT[26] ?
6'd29 :
(fpu_div_fOperands_S0$D_OUT[25] ?
6'd30 :
(fpu_div_fOperands_S0$D_OUT[24] ?
6'd31 :
(fpu_div_fOperands_S0$D_OUT[23] ?
6'd32 :
(fpu_div_fOperands_S0$D_OUT[22] ?
6'd33 :
(fpu_div_fOperands_S0$D_OUT[21] ?
6'd34 :
(fpu_div_fOperands_S0$D_OUT[20] ?
6'd35 :
(fpu_div_fOperands_S0$D_OUT[19] ?
6'd36 :
(fpu_div_fOperands_S0$D_OUT[18] ?
6'd37 :
(fpu_div_fOperands_S0$D_OUT[17] ?
6'd38 :
(fpu_div_fOperands_S0$D_OUT[16] ?
6'd39 :
(fpu_div_fOperands_S0$D_OUT[15] ?
6'd40 :
(fpu_div_fOperands_S0$D_OUT[14] ?
6'd41 :
(fpu_div_fOperands_S0$D_OUT[13] ?
6'd42 :
(fpu_div_fOperands_S0$D_OUT[12] ?
6'd43 :
(fpu_div_fOperands_S0$D_OUT[11] ?
6'd44 :
(fpu_div_fOperands_S0$D_OUT[10] ?
6'd45 :
(fpu_div_fOperands_S0$D_OUT[9] ?
6'd46 :
(fpu_div_fOperands_S0$D_OUT[8] ?
6'd47 :
(fpu_div_fOperands_S0$D_OUT[7] ?
6'd48 :
(fpu_div_fOperands_S0$D_OUT[6] ?
6'd49 :
(fpu_div_fOperands_S0$D_OUT[5] ?
6'd50 :
(fpu_div_fOperands_S0$D_OUT[4] ?
6'd51 :
(fpu_div_fOperands_S0$D_OUT[3] ?
6'd52 :
6'd53)))))))))))))))))))))))))))))))))))))))))))))))))))) :
6'd0 ;
assign b__h3090 =
(fpu_div_fOperands_S0$D_OUT[129:119] == 11'd0) ?
(fpu_div_fOperands_S0$D_OUT[118] ?
6'd1 :
(fpu_div_fOperands_S0$D_OUT[117] ?
6'd2 :
(fpu_div_fOperands_S0$D_OUT[116] ?
6'd3 :
(fpu_div_fOperands_S0$D_OUT[115] ?
6'd4 :
(fpu_div_fOperands_S0$D_OUT[114] ?
6'd5 :
(fpu_div_fOperands_S0$D_OUT[113] ?
6'd6 :
(fpu_div_fOperands_S0$D_OUT[112] ?
6'd7 :
(fpu_div_fOperands_S0$D_OUT[111] ?
6'd8 :
(fpu_div_fOperands_S0$D_OUT[110] ?
6'd9 :
(fpu_div_fOperands_S0$D_OUT[109] ?
6'd10 :
(fpu_div_fOperands_S0$D_OUT[108] ?
6'd11 :
(fpu_div_fOperands_S0$D_OUT[107] ?
6'd12 :
(fpu_div_fOperands_S0$D_OUT[106] ?
6'd13 :
(fpu_div_fOperands_S0$D_OUT[105] ?
6'd14 :
(fpu_div_fOperands_S0$D_OUT[104] ?
6'd15 :
(fpu_div_fOperands_S0$D_OUT[103] ?
6'd16 :
(fpu_div_fOperands_S0$D_OUT[102] ?
6'd17 :
(fpu_div_fOperands_S0$D_OUT[101] ?
6'd18 :
(fpu_div_fOperands_S0$D_OUT[100] ?
6'd19 :
(fpu_div_fOperands_S0$D_OUT[99] ?
6'd20 :
(fpu_div_fOperands_S0$D_OUT[98] ?
6'd21 :
(fpu_div_fOperands_S0$D_OUT[97] ?
6'd22 :
(fpu_div_fOperands_S0$D_OUT[96] ?
6'd23 :
(fpu_div_fOperands_S0$D_OUT[95] ?
6'd24 :
(fpu_div_fOperands_S0$D_OUT[94] ?
6'd25 :
(fpu_div_fOperands_S0$D_OUT[93] ?
6'd26 :
(fpu_div_fOperands_S0$D_OUT[92] ?
6'd27 :
(fpu_div_fOperands_S0$D_OUT[91] ?
6'd28 :
(fpu_div_fOperands_S0$D_OUT[90] ?
6'd29 :
(fpu_div_fOperands_S0$D_OUT[89] ?
6'd30 :
(fpu_div_fOperands_S0$D_OUT[88] ?
6'd31 :
(fpu_div_fOperands_S0$D_OUT[87] ?
6'd32 :
(fpu_div_fOperands_S0$D_OUT[86] ?
6'd33 :
(fpu_div_fOperands_S0$D_OUT[85] ?
6'd34 :
(fpu_div_fOperands_S0$D_OUT[84] ?
6'd35 :
(fpu_div_fOperands_S0$D_OUT[83] ?
6'd36 :
(fpu_div_fOperands_S0$D_OUT[82] ?
6'd37 :
(fpu_div_fOperands_S0$D_OUT[81] ?
6'd38 :
(fpu_div_fOperands_S0$D_OUT[80] ?
6'd39 :
(fpu_div_fOperands_S0$D_OUT[79] ?
6'd40 :
(fpu_div_fOperands_S0$D_OUT[78] ?
6'd41 :
(fpu_div_fOperands_S0$D_OUT[77] ?
6'd42 :
(fpu_div_fOperands_S0$D_OUT[76] ?
6'd43 :
(fpu_div_fOperands_S0$D_OUT[75] ?
6'd44 :
(fpu_div_fOperands_S0$D_OUT[74] ?
6'd45 :
(fpu_div_fOperands_S0$D_OUT[73] ?
6'd46 :
(fpu_div_fOperands_S0$D_OUT[72] ?
6'd47 :
(fpu_div_fOperands_S0$D_OUT[71] ?
6'd48 :
(fpu_div_fOperands_S0$D_OUT[70] ?
6'd49 :
(fpu_div_fOperands_S0$D_OUT[69] ?
6'd50 :
(fpu_div_fOperands_S0$D_OUT[68] ?
6'd51 :
(fpu_div_fOperands_S0$D_OUT[67] ?
6'd52 :
6'd53)))))))))))))))))))))))))))))))))))))))))))))))))))) :
6'd0 ;
assign b__h31634 = { rg_d, 58'd0 } ;
assign b__h43630 = { 2'd0, rg_b[115:2] } ;
assign b__h43734 =
{ 2'd0,
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1002[115:2] } ;
assign din_exp30866_MINUS_1023__q23 = din_exp__h130866 - 11'd1023 ;
assign din_exp__h130866 =
_7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2008 ?
value__h130883[10:0] :
11'd0 ;
assign din_inc___2_exp__h142626 = fpu_madd_fState_S8$D_OUT[65:55] + 11'd1 ;
assign din_inc___2_exp__h182467 = _theResult___fst_exp__h163334 + 11'd1 ;
assign din_inc___2_exp__h182502 = _theResult___fst_exp__h172850 + 11'd1 ;
assign din_inc___2_exp__h182528 = _theResult___fst_exp__h181651 + 11'd1 ;
assign din_inc___2_exp__h221105 = _theResult___fst_exp__h201972 + 11'd1 ;
assign din_inc___2_exp__h221140 = _theResult___fst_exp__h211488 + 11'd1 ;
assign din_inc___2_exp__h221166 = _theResult___fst_exp__h220289 + 11'd1 ;
assign din_inc___2_exp__h260044 = _theResult___fst_exp__h240911 + 11'd1 ;
assign din_inc___2_exp__h260079 = _theResult___fst_exp__h250427 + 11'd1 ;
assign din_inc___2_exp__h260105 = _theResult___fst_exp__h259228 + 11'd1 ;
assign din_inc___2_exp__h304759 = _theResult___fst_exp__h277722 + 8'd1 ;
assign din_inc___2_exp__h304785 = _theResult___fst_exp__h286378 + 8'd1 ;
assign din_inc___2_exp__h304820 = _theResult___fst_exp__h295488 + 8'd1 ;
assign din_inc___2_exp__h304846 = _theResult___fst_exp__h304173 + 8'd1 ;
assign din_inc___2_exp__h42617 = fpu_div_fState_S4$D_OUT[64:54] + 11'd1 ;
assign din_inc___2_exp__h96000 = fpu_sqr_fState_S4$D_OUT[64:54] + 11'd1 ;
assign exp__h304742 =
(resWire$wget[67:57] == 11'd2047) ?
8'd255 :
_theResult___fst_exp__h304733 ;
assign fpu_div_fOperands_S0D_OUT_BITS_129_TO_119_MIN_ETC__q7 =
fpu_div_fOperands_S0$D_OUT[129:119] - 11'd1023 ;
assign fpu_div_fOperands_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q8 =
fpu_div_fOperands_S0$D_OUT[65:55] - 11'd1023 ;
assign fpu_div_fOperands_S0_first__6_BITS_129_TO_119__ETC___d293 =
fpu_div_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
fpu_div_fOperands_S0$D_OUT[118:67] != 52'd0 &&
!fpu_div_fOperands_S0$D_OUT[118] ||
fpu_div_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
fpu_div_fOperands_S0$D_OUT[54:3] != 52'd0 &&
!fpu_div_fOperands_S0$D_OUT[54] ||
fpu_div_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
fpu_div_fOperands_S0$D_OUT[118] ||
fpu_div_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
fpu_div_fOperands_S0$D_OUT[54] ||
fpu_div_fOperands_S0_first__6_BITS_65_TO_55_6__ETC___d289 ;
assign fpu_div_fOperands_S0_first__6_BITS_129_TO_119__ETC___d331 =
fpu_div_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
fpu_div_fOperands_S0$D_OUT[118:67] == 52'd0 ||
fpu_div_fOperands_S0$D_OUT[129:119] == 11'd0 &&
fpu_div_fOperands_S0$D_OUT[118:67] == 52'd0 ||
fpu_div_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
fpu_div_fOperands_S0$D_OUT[54:3] == 52'd0 ;
assign fpu_div_fOperands_S0_first__6_BITS_129_TO_119__ETC___d366 =
fpu_div_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
fpu_div_fOperands_S0$D_OUT[118:67] == 52'd0 &&
fpu_div_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
fpu_div_fOperands_S0$D_OUT[54:3] == 52'd0 ||
fpu_div_fOperands_S0$D_OUT[129:119] == 11'd0 &&
fpu_div_fOperands_S0$D_OUT[118:67] == 52'd0 &&
fpu_div_fOperands_S0$D_OUT[65:55] == 11'd0 &&
fpu_div_fOperands_S0$D_OUT[54:3] == 52'd0 ;
assign fpu_div_fOperands_S0_first__6_BITS_129_TO_119__ETC___d428 =
fpu_div_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
fpu_div_fOperands_S0$D_OUT[118:67] != 52'd0 &&
!fpu_div_fOperands_S0$D_OUT[118] ||
fpu_div_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
fpu_div_fOperands_S0$D_OUT[54:3] != 52'd0 &&
!fpu_div_fOperands_S0$D_OUT[54] ||
fpu_div_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
fpu_div_fOperands_S0$D_OUT[118] ||
fpu_div_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
fpu_div_fOperands_S0$D_OUT[54] ||
fpu_div_fOperands_S0$D_OUT[65:55] == 11'd0 &&
fpu_div_fOperands_S0$D_OUT[54:3] == 52'd0 ||
fpu_div_fOperands_S0_first__6_BITS_129_TO_119__ETC___d331 ;
assign fpu_div_fOperands_S0_first__6_BITS_65_TO_55_6__ETC___d289 =
fpu_div_fOperands_S0$D_OUT[65:55] == 11'd0 &&
fpu_div_fOperands_S0$D_OUT[54:3] == 52'd0 ||
fpu_div_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
fpu_div_fOperands_S0$D_OUT[118:67] == 52'd0 ||
fpu_div_fOperands_S0$D_OUT[129:119] == 11'd0 &&
fpu_div_fOperands_S0$D_OUT[118:67] == 52'd0 ||
fpu_div_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
fpu_div_fOperands_S0$D_OUT[54:3] == 52'd0 ||
!IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d283 ||
IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d285 ;
assign fpu_div_fOperands_S0_first__6_BIT_130_33_EQ_fp_ETC___d335 =
fpu_div_fOperands_S0$D_OUT[130] ==
fpu_div_fOperands_S0$D_OUT[66] ;
assign fpu_div_fState_S3_first__16_BIT_121_37_CONCAT__ETC___d866 =
{ fpu_div_fState_S3$D_OUT[121],
IF_fpu_div_fState_S3_first__16_BITS_120_TO_110_ETC___d527 ?
IF_IF_fpu_div_fState_S3_first__16_BITS_120_TO__ETC___d859 :
((fpu_div_fState_S3$D_OUT[120:110] == 11'd2047) ?
((fpu_div_fState_S3$D_OUT[57:56] == 2'b0) ?
{ _theResult___fst_exp__h41335,
fpu_div_fState_S3$D_OUT[109:58] } :
63'h7FEFFFFFFFFFFFFF) :
fpu_div_fState_S3$D_OUT[120:58]) } ;
assign fpu_madd_fOperand_S0D_OUT_BITS_129_TO_119_MIN_ETC__q128 =
fpu_madd_fOperand_S0$D_OUT[129:119] - 11'd1023 ;
assign fpu_madd_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q129 =
fpu_madd_fOperand_S0$D_OUT[65:55] - 11'd1023 ;
assign fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1857 =
fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 ||
fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0 ||
x__h96539 == 11'd0 && _theResult___fst_sfd__h96608 == 52'd0 &&
(fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd0 &&
fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 ||
fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd0 &&
fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0) &&
fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855 ;
assign fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1926 =
fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 &&
fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd0 &&
fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0 ||
fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd0 &&
fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 &&
fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0 ;
assign fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855 =
(fpu_madd_fOperand_S0$D_OUT[195] &&
fpu_madd_fOperand_S0$D_OUT[194]) ==
NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854 ;
assign fpu_madd_fProd_S3_first__009_SRL_IF_7170_MINUS_ETC___d2012 =
fpu_madd_fProd_S3$D_OUT >>
_7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007 ;
assign fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 =
(fpu_madd_fState_S3$D_OUT[12:0] ^ 13'h1000) <= 13'd5119 ;
assign fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 =
(fpu_madd_fState_S3$D_OUT[12:0] ^ 13'h1000) < 13'd3020 ;
assign fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501 =
fpu_madd_fState_S3$D_OUT[86:82] |
{ 2'd0,
sfdBC__h115662[105] &&
IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 ==
12'd1023,
_theResult___fst_exp__h130952 == 11'd0 &&
guardBC__h115666 != 2'd0,
sfdBC__h115662[105] &&
IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 ==
12'd1023 } ;
assign fpu_madd_fState_S4D_OUT_BITS_128_TO_118_MINUS_ETC__q26 =
fpu_madd_fState_S4$D_OUT[128:118] - 11'd1023 ;
assign fpu_madd_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q27 =
fpu_madd_fState_S4$D_OUT[64:54] - 11'd1023 ;
assign fpu_madd_fState_S5_first__601_BITS_56_TO_0_610_ETC___d2615 =
fpu_madd_fState_S5$D_OUT[56:0] >>
fpu_madd_fState_S5$D_OUT[126:114] ;
assign fpu_madd_fState_S7_first__651_BITS_137_TO_133__ETC___d2942 =
fpu_madd_fState_S7$D_OUT[137:133] |
{ 2'd0,
sfd__h133119[56] &&
IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 ==
12'd1023,
_theResult___fst_exp__h141378 == 11'd0 &&
guard__h133123 != 2'd0,
sfd__h133119[56] &&
IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 ==
12'd1023 } ;
assign fpu_madd_fState_S8_first__960_BITS_75_TO_71_03_ETC___d3043 =
fpu_madd_fState_S8$D_OUT[75:71] |
{ 2'd0,
IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d3011 ==
11'd2047 &&
((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ?
fpu_madd_fState_S8$D_OUT[54:3] :
_theResult___fst_sfd__h142620) ==
52'd0,
1'd0,
fpu_madd_fState_S8$D_OUT[65:55] != 11'd2047 &&
fpu_madd_fState_S8$D_OUT[2:1] != 2'b0 } ;
assign fpu_sqr_fOperand_S0D_OUT_BITS_65_TO_55_MINUS__ETC__q16 =
fpu_sqr_fOperand_S0$D_OUT[65:55] - 11'd1023 ;
assign fpu_sqr_fState_S3D_OUT_BITS_121_TO_111_MINUS__ETC__q18 =
fpu_sqr_fState_S3$D_OUT[121:111] - 11'd1023 ;
assign guardBC__h115666 =
(sfdBC__h115662[105] &&
IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 ==
12'd1023) ?
2'd3 :
_theResult___snd_fst__h131051 ;
assign guard__h132367 = fpu_madd_fState_S5$D_OUT[56:0] << x__h132471 ;
assign guard__h133123 =
(sfd__h133119[56] &&
IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 ==
12'd1023) ?
2'd3 :
_theResult___snd_fst__h141477 ;
assign guard__h155373 =
{ IF_theResult___snd63285_BIT_4_THEN_2_ELSE_0__q34[1],
{ _theResult___snd__h163285[3:0], 52'd0 } != 56'd0 } ;
assign guard__h164622 =
{ IF_sfdin72844_BIT_4_THEN_2_ELSE_0__q38[1],
{ sfdin__h172844[3:0], 52'd0 } != 56'd0 } ;
assign guard__h165220 = x__h165322 != 57'd0 ;
assign guard__h173661 =
{ IF_theResult___snd81597_BIT_4_THEN_2_ELSE_0__q41[1],
{ _theResult___snd__h181597[3:0], 52'd0 } != 56'd0 } ;
assign guard__h194011 =
{ IF_theResult___snd01923_BIT_4_THEN_2_ELSE_0__q94[1],
{ _theResult___snd__h201923[3:0], 52'd0 } != 56'd0 } ;
assign guard__h203260 =
{ IF_sfdin11482_BIT_4_THEN_2_ELSE_0__q98[1],
{ sfdin__h211482[3:0], 52'd0 } != 56'd0 } ;
assign guard__h203858 = x__h203960 != 57'd0 ;
assign guard__h212299 =
{ IF_theResult___snd20235_BIT_4_THEN_2_ELSE_0__q101[1],
{ _theResult___snd__h220235[3:0], 52'd0 } != 56'd0 } ;
assign guard__h232950 =
{ IF_theResult___snd40862_BIT_4_THEN_2_ELSE_0__q61[1],
{ _theResult___snd__h240862[3:0], 52'd0 } != 56'd0 } ;
assign guard__h242199 =
{ IF_sfdin50421_BIT_4_THEN_2_ELSE_0__q65[1],
{ sfdin__h250421[3:0], 52'd0 } != 56'd0 } ;
assign guard__h242797 = x__h242899 != 57'd0 ;
assign guard__h251238 =
{ IF_theResult___snd59174_BIT_4_THEN_2_ELSE_0__q68[1],
{ _theResult___snd__h259174[3:0], 52'd0 } != 56'd0 } ;
assign guard__h269623 =
{ IF_sfdin77716_BIT_33_THEN_2_ELSE_0__q134[1],
{ sfdin__h277716[32:0], 23'd0 } != 56'd0 } ;
assign guard__h278330 =
{ IF_theResult___snd86329_BIT_33_THEN_2_ELSE_0__q136[1],
{ _theResult___snd__h286329[32:0], 23'd0 } != 56'd0 } ;
assign guard__h287260 =
{ IF_sfdin95482_BIT_33_THEN_2_ELSE_0__q140[1],
{ sfdin__h295482[32:0], 23'd0 } != 56'd0 } ;
assign guard__h287858 = x__h287960 != 57'd0 ;
assign guard__h296096 =
{ IF_theResult___snd04119_BIT_33_THEN_2_ELSE_0__q143[1],
{ _theResult___snd__h304119[32:0], 23'd0 } != 56'd0 } ;
assign guard__h32997 = x__h41756 ;
assign guard__h86435 = x__h95138 ;
assign iFifoD_OUT_BITS_102_TO_95_MINUS_127__q95 =
iFifo$D_OUT[102:95] - 8'd127 ;
assign iFifoD_OUT_BITS_167_TO_160_MINUS_127__q35 =
iFifo$D_OUT[167:160] - 8'd127 ;
assign iFifoD_OUT_BITS_37_TO_30_MINUS_127__q62 =
iFifo$D_OUT[37:30] - 8'd127 ;
assign out___1_sfd__h144233 = { iFifo$D_OUT[159:137], 29'd0 } ;
assign out___1_sfd__h182873 = { iFifo$D_OUT[94:72], 29'd0 } ;
assign out___1_sfd__h221812 = { iFifo$D_OUT[29:7], 29'd0 } ;
assign out_exp__h142544 =
fpu_madd_fState_S8$D_OUT[3] ?
_theResult___exp__h142541 :
fpu_madd_fState_S8$D_OUT[65:55] ;
assign out_exp__h163982 =
_theResult___snd__h163285[5] ?
_theResult___exp__h163979 :
_theResult___fst_exp__h163334 ;
assign out_exp__h173572 =
sfdin__h172844[5] ?
_theResult___exp__h173569 :
_theResult___fst_exp__h172850 ;
assign out_exp__h182324 =
_theResult___snd__h181597[5] ?
_theResult___exp__h182321 :
_theResult___fst_exp__h181651 ;
assign out_exp__h202620 =
_theResult___snd__h201923[5] ?
_theResult___exp__h202617 :
_theResult___fst_exp__h201972 ;
assign out_exp__h212210 =
sfdin__h211482[5] ?
_theResult___exp__h212207 :
_theResult___fst_exp__h211488 ;
assign out_exp__h220962 =
_theResult___snd__h220235[5] ?
_theResult___exp__h220959 :
_theResult___fst_exp__h220289 ;
assign out_exp__h241559 =
_theResult___snd__h240862[5] ?
_theResult___exp__h241556 :
_theResult___fst_exp__h240911 ;
assign out_exp__h251149 =
sfdin__h250421[5] ?
_theResult___exp__h251146 :
_theResult___fst_exp__h250427 ;
assign out_exp__h259901 =
_theResult___snd__h259174[5] ?
_theResult___exp__h259898 :
_theResult___fst_exp__h259228 ;
assign out_exp__h278241 =
sfdin__h277716[34] ?
_theResult___exp__h278238 :
_theResult___fst_exp__h277722 ;
assign out_exp__h286823 =
_theResult___snd__h286329[34] ?
_theResult___exp__h286820 :
_theResult___fst_exp__h286378 ;
assign out_exp__h296007 =
sfdin__h295482[34] ?
_theResult___exp__h296004 :
_theResult___fst_exp__h295488 ;
assign out_exp__h304643 =
_theResult___snd__h304119[34] ?
_theResult___exp__h304640 :
_theResult___fst_exp__h304173 ;
assign out_exp__h42529 =
fpu_div_fState_S4$D_OUT[2] ?
_theResult___exp__h42526 :
fpu_div_fState_S4$D_OUT[64:54] ;
assign out_exp__h95912 =
fpu_sqr_fState_S4$D_OUT[2] ?
_theResult___exp__h95909 :
fpu_sqr_fState_S4$D_OUT[64:54] ;
assign out_sfd__h142545 =
fpu_madd_fState_S8$D_OUT[3] ?
_theResult___sfd__h142542 :
fpu_madd_fState_S8$D_OUT[54:3] ;
assign out_sfd__h163983 =
_theResult___snd__h163285[5] ?
_theResult___sfd__h163980 :
_theResult___snd__h163285[56:5] ;
assign out_sfd__h173573 =
sfdin__h172844[5] ?
_theResult___sfd__h173570 :
sfdin__h172844[56:5] ;
assign out_sfd__h182325 =
_theResult___snd__h181597[5] ?
_theResult___sfd__h182322 :
_theResult___snd__h181597[56:5] ;
assign out_sfd__h202621 =
_theResult___snd__h201923[5] ?
_theResult___sfd__h202618 :
_theResult___snd__h201923[56:5] ;
assign out_sfd__h212211 =
sfdin__h211482[5] ?
_theResult___sfd__h212208 :
sfdin__h211482[56:5] ;
assign out_sfd__h220963 =
_theResult___snd__h220235[5] ?
_theResult___sfd__h220960 :
_theResult___snd__h220235[56:5] ;
assign out_sfd__h241560 =
_theResult___snd__h240862[5] ?
_theResult___sfd__h241557 :
_theResult___snd__h240862[56:5] ;
assign out_sfd__h251150 =
sfdin__h250421[5] ?
_theResult___sfd__h251147 :
sfdin__h250421[56:5] ;
assign out_sfd__h259902 =
_theResult___snd__h259174[5] ?
_theResult___sfd__h259899 :
_theResult___snd__h259174[56:5] ;
assign out_sfd__h278242 =
sfdin__h277716[34] ?
_theResult___sfd__h278239 :
sfdin__h277716[56:34] ;
assign out_sfd__h286824 =
_theResult___snd__h286329[34] ?
_theResult___sfd__h286821 :
_theResult___snd__h286329[56:34] ;
assign out_sfd__h296008 =
sfdin__h295482[34] ?
_theResult___sfd__h296005 :
sfdin__h295482[56:34] ;
assign out_sfd__h304644 =
_theResult___snd__h304119[34] ?
_theResult___sfd__h304641 :
_theResult___snd__h304119[56:34] ;
assign out_sfd__h42530 =
fpu_div_fState_S4$D_OUT[2] ?
_theResult___sfd__h42527 :
fpu_div_fState_S4$D_OUT[53:2] ;
assign out_sfd__h95913 =
fpu_sqr_fState_S4$D_OUT[2] ?
_theResult___sfd__h95910 :
fpu_sqr_fState_S4$D_OUT[53:2] ;
assign r__h43681 = r__h43685 + rg_b ;
assign r__h43685 = { 1'd0, rg_r_1[115:1] } ;
assign r__h43746 =
r__h43775 +
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1002 ;
assign r__h43775 =
{ 1'd0,
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1022[115:1] } ;
assign resWire_wget__410_BITS_4_TO_0_658_OR_NOT_resWi_ETC___d6768 =
resWire$wget[4:0] |
{ (resWire$wget[67:57] != 11'd2047 ||
resWire$wget[56:5] == 52'd0) &&
(resWire$wget[67:57] != 11'd2047 ||
resWire$wget[56:5] != 52'd0) &&
(resWire$wget[67:57] != 11'd0 ||
resWire$wget[56:5] != 52'd0) &&
IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6709,
(resWire$wget[67:57] != 11'd2047 ||
resWire$wget[56:5] == 52'd0) &&
(resWire$wget[67:57] != 11'd2047 ||
resWire$wget[56:5] != 52'd0) &&
(resWire$wget[67:57] != 11'd0 ||
resWire$wget[56:5] != 52'd0) &&
IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6720,
(resWire$wget[67:57] != 11'd2047 ||
resWire$wget[56:5] == 52'd0) &&
(resWire$wget[67:57] != 11'd2047 ||
resWire$wget[56:5] != 52'd0) &&
(resWire$wget[67:57] != 11'd0 ||
resWire$wget[56:5] != 52'd0) &&
IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6736,
(resWire$wget[67:57] != 11'd2047 ||
resWire$wget[56:5] == 52'd0) &&
(resWire$wget[67:57] != 11'd2047 ||
resWire$wget[56:5] != 52'd0) &&
(resWire$wget[67:57] != 11'd0 ||
resWire$wget[56:5] != 52'd0) &&
IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6749,
(resWire$wget[67:57] != 11'd2047 ||
resWire$wget[56:5] == 52'd0) &&
(resWire$wget[67:57] != 11'd2047 ||
resWire$wget[56:5] != 52'd0) &&
(resWire$wget[67:57] != 11'd0 ||
resWire$wget[56:5] != 52'd0) &&
IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6762 } ;
assign resWirewget_BITS_67_TO_57_MINUS_1023__q137 =
resWire$wget[67:57] - 11'd1023 ;
assign result__h132372 =
{ fpu_madd_fState_S5_first__601_BITS_56_TO_0_610_ETC___d2615[56:1],
fpu_madd_fState_S5_first__601_BITS_56_TO_0_610_ETC___d2615[0] |
guard__h132367 != 57'd0 } ;
assign result__h165225 =
{ _0b0_CONCAT_NOT_iFifo_first__087_BITS_167_TO_16_ETC___d3330[56:1],
_0b0_CONCAT_NOT_iFifo_first__087_BITS_167_TO_16_ETC___d3330[0] |
guard__h165220 } ;
assign result__h203863 =
{ _0b0_CONCAT_NOT_iFifo_first__087_BITS_102_TO_95_ETC___d4813[56:1],
_0b0_CONCAT_NOT_iFifo_first__087_BITS_102_TO_95_ETC___d4813[0] |
guard__h203858 } ;
assign result__h242802 =
{ _0b0_CONCAT_NOT_iFifo_first__087_BITS_37_TO_30__ETC___d4038[56:1],
_0b0_CONCAT_NOT_iFifo_first__087_BITS_37_TO_30__ETC___d4038[0] |
guard__h242797 } ;
assign result__h287863 =
{ _0b0_CONCAT_NOT_resWire_wget__410_BITS_67_TO_57_ETC___d6038[56:1],
_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_TO_57_ETC___d6038[0] |
guard__h287858 } ;
assign result__h31668 = { _theResult____h31574[57:1], 1'd1 } ;
assign result__h31699 =
{ 1'd0,
value__h31712[56:1],
value__h31712[0] | sfdlsb__h31694 } ;
assign result__h31874 =
(IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_89_ETC__q10[56:0] ==
57'd0) ?
58'd0 :
58'd1 ;
assign result__h85925 = { x__h85931[58:1], 1'd1 } ;
assign rg_index_1_87_PLUS_1_89_ULE_58___d990 = rg_index_1 + 6'd1 <= 6'd58 ;
assign rg_index_1_87_ULE_58___d991 = rg_index_1 <= 6'd58 ;
assign rg_index_PLUS_1_ULE_57___d6 = rg_index + 6'd1 <= 6'd57 ;
assign rg_index_ULE_57___d7 = rg_index <= 6'd57 ;
assign rg_q_PLUS_NEG_INV_rg_q_89_90___d491 = rg_q + -(~rg_q) ;
assign rg_s_014_ULT_rg_r_1_013_PLUS_rg_b_92_015___d1016 =
rg_s < sum__h43628 ;
assign s__h43680 = rg_s - sum__h43628 ;
assign s__h43745 =
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1036 -
sum__h43732 ;
assign sfdA__h1086 =
{ fpu_div_fOperands_S0$D_OUT[129:119] != 11'd0,
fpu_div_fOperands_S0$D_OUT[118:67] } ;
assign sfdA__h1090 = sfdA__h1086 << b__h3090 ;
assign sfdA__h131577 =
{ 1'b0,
fpu_madd_fState_S4$D_OUT[128:118] != 11'd0,
fpu_madd_fState_S4$D_OUT[117:66],
3'b0 } ;
assign sfdBC__h115662 =
_7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2008 ?
fpu_madd_fProd_S3$D_OUT :
_theResult___fst__h116827 ;
assign sfdBC__h131578 =
{ 1'b0,
fpu_madd_fState_S4$D_OUT[64:54] != 11'd0,
fpu_madd_fState_S4$D_OUT[53:0],
1'b0 } ;
assign sfdB__h1087 =
{ fpu_div_fOperands_S0$D_OUT[65:55] != 11'd0,
fpu_div_fOperands_S0$D_OUT[54:3] } ;
assign sfdB__h1092 = sfdB__h1087 << b__h10508 ;
assign sfd___1__h60702 = { 1'd0, sfd__h44953[57:1] } ;
assign sfd__h133119 =
fpu_madd_fState_S7$D_OUT[128] ?
fpu_madd_fState_S7$D_OUT[56:0] :
fpu_madd_fState_S7$D_OUT[113:57] ;
assign sfd__h142040 =
{ 1'b0,
fpu_madd_fState_S8$D_OUT[65:55] != 11'd0,
fpu_madd_fState_S8$D_OUT[54:3] } +
54'd1 ;
assign sfd__h144534 = { value__h148921, 32'd0 } ;
assign sfd__h163352 =
{ 1'b0,
_theResult___fst_exp__h163334 != 11'd0,
_theResult___snd__h163285[56:5] } +
54'd1 ;
assign sfd__h172942 =
{ 1'b0,
_theResult___fst_exp__h172850 != 11'd0,
sfdin__h172844[56:5] } +
54'd1 ;
assign sfd__h17985 = { 1'd1, fpu_div_fOperands_S0$D_OUT[117:67] } ;
assign sfd__h17988 = { 1'd1, fpu_div_fOperands_S0$D_OUT[53:3] } ;
assign sfd__h181670 =
{ 1'b0,
_theResult___fst_exp__h181651 != 11'd0,
_theResult___snd__h181597[56:5] } +
54'd1 ;
assign sfd__h183174 = { value__h187559, 32'd0 } ;
assign sfd__h201990 =
{ 1'b0,
_theResult___fst_exp__h201972 != 11'd0,
_theResult___snd__h201923[56:5] } +
54'd1 ;
assign sfd__h211580 =
{ 1'b0,
_theResult___fst_exp__h211488 != 11'd0,
sfdin__h211482[56:5] } +
54'd1 ;
assign sfd__h220308 =
{ 1'b0,
_theResult___fst_exp__h220289 != 11'd0,
_theResult___snd__h220235[56:5] } +
54'd1 ;
assign sfd__h222113 = { value__h226498, 32'd0 } ;
assign sfd__h240929 =
{ 1'b0,
_theResult___fst_exp__h240911 != 11'd0,
_theResult___snd__h240862[56:5] } +
54'd1 ;
assign sfd__h250519 =
{ 1'b0,
_theResult___fst_exp__h250427 != 11'd0,
sfdin__h250421[56:5] } +
54'd1 ;
assign sfd__h259247 =
{ 1'b0,
_theResult___fst_exp__h259228 != 11'd0,
_theResult___snd__h259174[56:5] } +
54'd1 ;
assign sfd__h262011 = { value__h270233, 3'd0 } ;
assign sfd__h277814 =
{ 1'b0,
_theResult___fst_exp__h277722 != 8'd0,
sfdin__h277716[56:34] } +
25'd1 ;
assign sfd__h286396 =
{ 1'b0,
_theResult___fst_exp__h286378 != 8'd0,
_theResult___snd__h286329[56:34] } +
25'd1 ;
assign sfd__h295580 =
{ 1'b0,
_theResult___fst_exp__h295488 != 8'd0,
sfdin__h295482[56:34] } +
25'd1 ;
assign sfd__h304192 =
{ 1'b0,
_theResult___fst_exp__h304173 != 8'd0,
_theResult___snd__h304119[56:34] } +
25'd1 ;
assign sfd__h304743 =
(resWire$wget[67:57] == 11'd2047 &&
resWire$wget[56:5] != 52'd0) ?
_theResult___snd_fst_sfd__h261961 :
_theResult___fst_sfd__h304737 ;
assign sfd__h42033 =
{ 1'b0,
fpu_div_fState_S4$D_OUT[64:54] != 11'd0,
fpu_div_fState_S4$D_OUT[53:2] } +
54'd1 ;
assign sfd__h44951 = { value__h53174, 4'd0 } ;
assign sfd__h44953 = sfd__h44951 << x__h60732 ;
assign sfd__h45004 = { 1'd1, fpu_sqr_fOperand_S0$D_OUT[53:3] } ;
assign sfd__h95416 =
{ 1'b0,
fpu_sqr_fState_S4$D_OUT[64:54] != 11'd0,
fpu_sqr_fState_S4$D_OUT[53:2] } +
54'd1 ;
assign sfd__h99402 = { 1'd1, _theResult___fst_sfd__h96608[50:0] } ;
assign sfd__h99405 = { 1'd1, fpu_madd_fOperand_S0$D_OUT[117:67] } ;
assign sfd__h99408 = { 1'd1, fpu_madd_fOperand_S0$D_OUT[53:3] } ;
assign sfdin__h130943 =
sfdBC__h115662[105] ?
_theResult___snd__h130966 :
_theResult___snd__h130980 ;
assign sfdin__h141369 =
sfd__h133119[56] ?
_theResult___snd__h141392 :
_theResult___snd__h141406 ;
assign sfdin__h172844 =
_theResult____h164612[56] ?
_theResult___snd__h172861 :
_theResult___snd__h172872 ;
assign sfdin__h211482 =
_theResult____h203250[56] ?
_theResult___snd__h211499 :
_theResult___snd__h211510 ;
assign sfdin__h250421 =
_theResult____h242189[56] ?
_theResult___snd__h250438 :
_theResult___snd__h250449 ;
assign sfdin__h277716 =
_theResult____h269613[56] ?
_theResult___snd__h277733 :
_theResult___snd__h277744 ;
assign sfdin__h295482 =
_theResult____h287250[56] ?
_theResult___snd__h295499 :
_theResult___snd__h295510 ;
assign sfdin__h33169 =
(fpu_div_fState_S3$D_OUT[120:110] == 11'd2047) ?
_theResult___snd_snd_snd__h33014 :
fpu_div_fState_S3$D_OUT[57:0] ;
assign sfdin__h41378 =
sfdin__h33169[57] ?
_theResult___snd__h41401 :
_theResult___snd__h41416 ;
assign sfdin__h94744 =
fpu_sqr_fState_S3$D_OUT[58] ?
_theResult___snd__h94767 :
_theResult___snd__h94782 ;
assign sfdlsb__h116825 = x__h116896 != 106'd0 ;
assign sfdlsb__h31694 = x__h31813 != 58'd0 ;
assign sum__h43628 = rg_r_1 + rg_b ;
assign sum__h43732 =
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1022 +
IF_rg_index_1_87_ULE_58_91_THEN_IF_rg_res_94_B_ETC___d1002 ;
assign theResult___fst_exp1341_MINUS_1023__q11 =
_theResult___fst_exp__h41341 - 11'd1023 ;
assign value41307_BITS_10_TO_0_MINUS_1023__q28 =
value__h141307[10:0] - 11'd1023 ;
assign value_BIT_52___h53270 = fpu_sqr_fOperand_S0$D_OUT[65:55] != 11'd0 ;
assign value__h130883 = fpu_madd_fState_S3$D_OUT[12:0] + 13'd1023 ;
assign value__h141307 = fpu_madd_fState_S7$D_OUT[126:114] + 13'd1023 ;
assign value__h148921 =
{ 1'b0, iFifo$D_OUT[167:160] != 8'd0, iFifo$D_OUT[159:137] } ;
assign value__h187559 =
{ 1'b0, iFifo$D_OUT[102:95] != 8'd0, iFifo$D_OUT[94:72] } ;
assign value__h226498 =
{ 1'b0, iFifo$D_OUT[37:30] != 8'd0, iFifo$D_OUT[29:7] } ;
assign value__h270233 =
{ 1'b0, resWire$wget[67:57] != 11'd0, resWire$wget[56:5] } ;
assign value__h30425 =
IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d282 +
13'd1023 ;
assign value__h30480 = { 1'b0, sfdA__h1090 } ;
assign value__h30601 =
13'd7170 -
IF_fpu_div_fOperands_S0_first__6_BITS_129_TO_1_ETC___d282 ;
assign value__h31592 = rg_r[115] ? rg_r + b__h31634 : rg_r ;
assign value__h31712 =
IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_89_ETC__q10[56:0] >>
fpu_div_fState_S2$D_OUT[10:0] ;
assign value__h53174 =
{ 1'b0,
value_BIT_52___h53270,
fpu_sqr_fOperand_S0$D_OUT[54:3] } ;
assign x__h114243 =
{ fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd0,
fpu_madd_fOperand_S0$D_OUT[118:67] } ;
assign x__h114255 =
{ fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd0,
fpu_madd_fOperand_S0$D_OUT[54:3] } ;
assign x__h116896 = fpu_madd_fProd_S3$D_OUT << x__h116929 ;
assign x__h116929 =
13'd106 -
_7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007 ;
assign x__h131406 =
fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ?
_theResult___snd_snd_snd__h131369 :
2'd3 ;
assign x__h131940 =
{ 1'b0,
NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ?
{ fpu_madd_fState_S4$D_OUT[64:54] != 11'd0,
fpu_madd_fState_S4$D_OUT[53:0],
1'b0 } :
{ fpu_madd_fState_S4$D_OUT[128:118] != 11'd0,
fpu_madd_fState_S4$D_OUT[117:66],
3'b0 } } ;
assign x__h131944 =
{ 1'b0,
NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ?
{ fpu_madd_fState_S4$D_OUT[128:118] != 11'd0,
fpu_madd_fState_S4$D_OUT[117:66],
3'b0 } :
{ fpu_madd_fState_S4$D_OUT[64:54] != 11'd0,
fpu_madd_fState_S4$D_OUT[53:0],
1'b0 } } ;
assign x__h132359 =
fpu_madd_fState_S5$D_OUT[215] ?
fpu_madd_fState_S5$D_OUT[56:0] :
(((fpu_madd_fState_S5$D_OUT[126:114] ^ 13'h1000) < 13'd4153) ?
result__h132372 :
((fpu_madd_fState_S5$D_OUT[56:0] == 57'd0) ?
fpu_madd_fState_S5$D_OUT[56:0] :
57'd1)) ;
assign x__h132471 = 13'd57 - fpu_madd_fState_S5$D_OUT[126:114] ;
assign x__h132871 =
fpu_madd_fState_S6$D_OUT[113:57] +
fpu_madd_fState_S6$D_OUT[56:0] ;
assign x__h132880 =
fpu_madd_fState_S6$D_OUT[113:57] -
fpu_madd_fState_S6$D_OUT[56:0] ;
assign x__h141760 = fpu_madd_fState_S7$D_OUT[202] ? 2'd0 : guard__h133123 ;
assign x__h165322 = sfd__h144534 << x__h165355 ;
assign x__h165355 =
12'd57 -
_3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326 ;
assign x__h203960 = sfd__h183174 << x__h203993 ;
assign x__h203993 =
12'd57 -
_3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809 ;
assign x__h242899 = sfd__h222113 << x__h242932 ;
assign x__h242932 =
12'd57 -
_3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034 ;
assign x__h287960 = sfd__h262011 << x__h287993 ;
assign x__h287993 =
12'd57 -
_3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034 ;
assign x__h30477 = { value__h30480, 60'd0 } ;
assign x__h30538 = { sfdB__h1092, 4'b0 } ;
assign x__h30592 =
fpu_div_fOperands_S0_first__6_BITS_129_TO_119__ETC___d293 ?
11'd0 :
_theResult___fst__h30373 ;
assign x__h31813 =
{ 1'd0,
IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_89_ETC__q10[56:0] } <<
x__h31820 ;
assign x__h31820 = 11'd58 - fpu_div_fState_S2$D_OUT[10:0] ;
assign x__h32103 =
(value__h31592[114:58] == 57'd0) ?
_theResult____h31574 :
result__h31668 ;
assign x__h41756 =
(sfdin__h33169[57] &&
IF_IF_fpu_div_fState_S3_first__16_BITS_120_TO__ETC___d573 ==
12'd1023) ?
2'd3 :
_theResult___snd_fst__h41490 ;
assign x__h52551 = x__h52569 + 13'd1024 ;
assign x__h52569 =
{ IF_fpu_sqr_fOperand_S0_first__059_BITS_65_TO_5_ETC__q17[11],
IF_fpu_sqr_fOperand_S0_first__059_BITS_65_TO_5_ETC__q17 } ;
assign x__h60693 =
IF_fpu_sqr_fOperand_S0_first__059_BITS_65_TO_5_ETC___d1195[0] ?
sfd__h44953 :
sfd___1__h60702 ;
assign x__h60732 =
IF_fpu_sqr_fOperand_S0_first__059_BITS_65_TO_5_ETC___d1193 -
6'd1 ;
assign x__h85465 =
IF_fpu_sqr_fState_S1_first__216_BIT_57_226_THE_ETC___d1342[0] ?
IF_fpu_sqr_fState_S1_first__216_BIT_57_226_THE_ETC___d1342 +
7'd1 :
IF_fpu_sqr_fState_S1_first__216_BIT_57_226_THE_ETC___d1342 ;
assign x__h85931 = rg_res[116] ? rg_res[115:0] : 116'd0 ;
assign x__h86149 = (rg_s == 116'd0) ? x__h85931[58:0] : result__h85925 ;
assign x__h95138 =
(fpu_sqr_fState_S3$D_OUT[58] &&
IF_fpu_sqr_fState_S3_first__375_BITS_121_TO_11_ETC___d1389 ==
12'd1023) ?
2'd3 :
_theResult___snd_fst__h94856 ;
assign x__h96539 =
fpu_madd_fOperand_S0$D_OUT[195] ?
fpu_madd_fOperand_S0$D_OUT[193:183] :
11'd0 ;
always@(fpu_div_fState_S4$D_OUT or
out_sfd__h42530 or _theResult___sfd__h42527)
begin
case (fpu_div_fState_S4$D_OUT[1:0])
2'b0, 2'b01:
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q1 =
fpu_div_fState_S4$D_OUT[53:2];
2'b10:
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q1 =
out_sfd__h42530;
2'b11:
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q1 =
_theResult___sfd__h42527;
endcase
end
always@(fpu_div_fState_S4$D_OUT or _theResult___sfd__h42527)
begin
case (fpu_div_fState_S4$D_OUT[1:0])
2'b0:
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q2 =
fpu_div_fState_S4$D_OUT[53:2];
2'b01, 2'b10, 2'b11:
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q2 =
_theResult___sfd__h42527;
endcase
end
always@(fpu_div_fState_S4$D_OUT or
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q1 or
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q2 or
_theResult___sfd__h42527)
begin
case (fpu_div_fState_S4$D_OUT[68:66])
3'd0:
_theResult___fst_sfd__h42605 =
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q1;
3'd1:
_theResult___fst_sfd__h42605 =
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q2;
3'd2:
_theResult___fst_sfd__h42605 =
(fpu_div_fState_S4$D_OUT[1:0] == 2'b0 ||
fpu_div_fState_S4$D_OUT[65]) ?
fpu_div_fState_S4$D_OUT[53:2] :
_theResult___sfd__h42527;
3'd3:
_theResult___fst_sfd__h42605 =
(fpu_div_fState_S4$D_OUT[1:0] == 2'b0) ?
fpu_div_fState_S4$D_OUT[53:2] :
(fpu_div_fState_S4$D_OUT[65] ?
_theResult___sfd__h42527 :
fpu_div_fState_S4$D_OUT[53:2]);
3'd4: _theResult___fst_sfd__h42605 = fpu_div_fState_S4$D_OUT[53:2];
default: _theResult___fst_sfd__h42605 = 52'd0;
endcase
end
always@(fpu_sqr_fState_S4$D_OUT or
out_sfd__h95913 or _theResult___sfd__h95910)
begin
case (fpu_sqr_fState_S4$D_OUT[1:0])
2'b0, 2'b01:
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q3 =
fpu_sqr_fState_S4$D_OUT[53:2];
2'b10:
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q3 =
out_sfd__h95913;
2'b11:
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q3 =
_theResult___sfd__h95910;
endcase
end
always@(fpu_sqr_fState_S4$D_OUT or _theResult___sfd__h95910)
begin
case (fpu_sqr_fState_S4$D_OUT[1:0])
2'b0:
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q4 =
fpu_sqr_fState_S4$D_OUT[53:2];
2'b01, 2'b10, 2'b11:
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q4 =
_theResult___sfd__h95910;
endcase
end
always@(fpu_sqr_fState_S4$D_OUT or
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q3 or
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q4 or
_theResult___sfd__h95910)
begin
case (fpu_sqr_fState_S4$D_OUT[68:66])
3'd0:
_theResult___fst_sfd__h95988 =
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q3;
3'd1:
_theResult___fst_sfd__h95988 =
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q4;
3'd2:
_theResult___fst_sfd__h95988 =
(fpu_sqr_fState_S4$D_OUT[1:0] == 2'b0 ||
fpu_sqr_fState_S4$D_OUT[65]) ?
fpu_sqr_fState_S4$D_OUT[53:2] :
_theResult___sfd__h95910;
3'd3:
_theResult___fst_sfd__h95988 =
(fpu_sqr_fState_S4$D_OUT[1:0] == 2'b0) ?
fpu_sqr_fState_S4$D_OUT[53:2] :
(fpu_sqr_fState_S4$D_OUT[65] ?
_theResult___sfd__h95910 :
fpu_sqr_fState_S4$D_OUT[53:2]);
3'd4: _theResult___fst_sfd__h95988 = fpu_sqr_fState_S4$D_OUT[53:2];
default: _theResult___fst_sfd__h95988 = 52'd0;
endcase
end
always@(fpu_madd_fState_S8$D_OUT or
out_sfd__h142545 or _theResult___sfd__h142542)
begin
case (fpu_madd_fState_S8$D_OUT[2:1])
2'b0, 2'b01:
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5 =
fpu_madd_fState_S8$D_OUT[54:3];
2'b10:
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5 =
out_sfd__h142545;
2'b11:
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5 =
_theResult___sfd__h142542;
endcase
end
always@(fpu_madd_fState_S8$D_OUT or _theResult___sfd__h142542)
begin
case (fpu_madd_fState_S8$D_OUT[2:1])
2'b0:
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6 =
fpu_madd_fState_S8$D_OUT[54:3];
2'b01, 2'b10, 2'b11:
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6 =
_theResult___sfd__h142542;
endcase
end
always@(fpu_madd_fState_S8$D_OUT or
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5 or
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6 or
_theResult___sfd__h142542)
begin
case (fpu_madd_fState_S8$D_OUT[70:68])
3'd0:
_theResult___fst_sfd__h142620 =
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5;
3'd1:
_theResult___fst_sfd__h142620 =
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6;
3'd2:
_theResult___fst_sfd__h142620 =
(fpu_madd_fState_S8$D_OUT[2:1] == 2'b0 ||
fpu_madd_fState_S8$D_OUT[66]) ?
fpu_madd_fState_S8$D_OUT[54:3] :
_theResult___sfd__h142542;
3'd3:
_theResult___fst_sfd__h142620 =
(fpu_madd_fState_S8$D_OUT[2:1] == 2'b0) ?
fpu_madd_fState_S8$D_OUT[54:3] :
(fpu_madd_fState_S8$D_OUT[66] ?
_theResult___sfd__h142542 :
fpu_madd_fState_S8$D_OUT[54:3]);
3'd4: _theResult___fst_sfd__h142620 = fpu_madd_fState_S8$D_OUT[54:3];
default: _theResult___fst_sfd__h142620 = 52'd0;
endcase
end
always@(iFifo$D_OUT)
begin
case (iFifo$D_OUT[6:4])
3'd0, 3'd1: _theResult___fst_exp__h148289 = 11'd2047;
3'd2:
_theResult___fst_exp__h148289 =
iFifo$D_OUT[168] ? 11'd2046 : 11'd2047;
3'd3:
_theResult___fst_exp__h148289 =
iFifo$D_OUT[168] ? 11'd2047 : 11'd2046;
3'd4: _theResult___fst_exp__h148289 = 11'd2046;
default: _theResult___fst_exp__h148289 = 11'd0;
endcase
end
always@(iFifo$D_OUT)
begin
case (iFifo$D_OUT[6:4])
3'd0, 3'd1: _theResult___fst_sfd__h148290 = 52'd0;
3'd2:
_theResult___fst_sfd__h148290 =
iFifo$D_OUT[168] ? 52'hFFFFFFFFFFFFF : 52'd0;
3'd3:
_theResult___fst_sfd__h148290 =
iFifo$D_OUT[168] ? 52'd0 : 52'hFFFFFFFFFFFFF;
3'd4: _theResult___fst_sfd__h148290 = 52'hFFFFFFFFFFFFF;
default: _theResult___fst_sfd__h148290 = 52'd0;
endcase
end
always@(iFifo$D_OUT)
begin
case (iFifo$D_OUT[6:4])
3'd0, 3'd1: _theResult___fst_exp__h186929 = 11'd2047;
3'd2:
_theResult___fst_exp__h186929 =
iFifo$D_OUT[103] ? 11'd2046 : 11'd2047;
3'd3:
_theResult___fst_exp__h186929 =
iFifo$D_OUT[103] ? 11'd2047 : 11'd2046;
3'd4: _theResult___fst_exp__h186929 = 11'd2046;
default: _theResult___fst_exp__h186929 = 11'd0;
endcase
end
always@(iFifo$D_OUT)
begin
case (iFifo$D_OUT[6:4])
3'd0, 3'd1: _theResult___fst_exp__h225868 = 11'd2047;
3'd2:
_theResult___fst_exp__h225868 =
iFifo$D_OUT[38] ? 11'd2046 : 11'd2047;
3'd3:
_theResult___fst_exp__h225868 =
iFifo$D_OUT[38] ? 11'd2047 : 11'd2046;
3'd4: _theResult___fst_exp__h225868 = 11'd2046;
default: _theResult___fst_exp__h225868 = 11'd0;
endcase
end
always@(iFifo$D_OUT)
begin
case (iFifo$D_OUT[6:4])
3'd0, 3'd1: _theResult___fst_sfd__h186930 = 52'd0;
3'd2:
_theResult___fst_sfd__h186930 =
iFifo$D_OUT[103] ? 52'hFFFFFFFFFFFFF : 52'd0;
3'd3:
_theResult___fst_sfd__h186930 =
iFifo$D_OUT[103] ? 52'd0 : 52'hFFFFFFFFFFFFF;
3'd4: _theResult___fst_sfd__h186930 = 52'hFFFFFFFFFFFFF;
default: _theResult___fst_sfd__h186930 = 52'd0;
endcase
end
always@(iFifo$D_OUT)
begin
case (iFifo$D_OUT[6:4])
3'd0, 3'd1: _theResult___fst_sfd__h225869 = 52'd0;
3'd2:
_theResult___fst_sfd__h225869 =
iFifo$D_OUT[38] ? 52'hFFFFFFFFFFFFF : 52'd0;
3'd3:
_theResult___fst_sfd__h225869 =
iFifo$D_OUT[38] ? 52'd0 : 52'hFFFFFFFFFFFFF;
3'd4: _theResult___fst_sfd__h225869 = 52'hFFFFFFFFFFFFF;
default: _theResult___fst_sfd__h225869 = 52'd0;
endcase
end
always@(fpu_div_fOperands_S0$D_OUT or
fpu_div_fOperands_S0_first__6_BIT_130_33_EQ_fp_ETC___d335)
begin
case (fpu_div_fOperands_S0$D_OUT[2:0])
3'd0, 3'd1: _theResult___fst_exp__h18518 = 11'd2047;
3'd2:
_theResult___fst_exp__h18518 =
fpu_div_fOperands_S0_first__6_BIT_130_33_EQ_fp_ETC___d335 ?
11'd2047 :
11'd2046;
3'd3:
_theResult___fst_exp__h18518 =
fpu_div_fOperands_S0_first__6_BIT_130_33_EQ_fp_ETC___d335 ?
11'd2046 :
11'd2047;
3'd4: _theResult___fst_exp__h18518 = 11'd2046;
default: _theResult___fst_exp__h18518 = 11'd0;
endcase
end
always@(fpu_div_fOperands_S0$D_OUT or
fpu_div_fOperands_S0_first__6_BIT_130_33_EQ_fp_ETC___d335)
begin
case (fpu_div_fOperands_S0$D_OUT[2:0])
3'd0, 3'd1: _theResult___fst_sfd__h18519 = 52'd0;
3'd2:
_theResult___fst_sfd__h18519 =
fpu_div_fOperands_S0_first__6_BIT_130_33_EQ_fp_ETC___d335 ?
52'd0 :
52'hFFFFFFFFFFFFF;
3'd3:
_theResult___fst_sfd__h18519 =
fpu_div_fOperands_S0_first__6_BIT_130_33_EQ_fp_ETC___d335 ?
52'hFFFFFFFFFFFFF :
52'd0;
3'd4: _theResult___fst_sfd__h18519 = 52'hFFFFFFFFFFFFF;
default: _theResult___fst_sfd__h18519 = 52'd0;
endcase
end
always@(fpu_div_fOperands_S0$D_OUT or
fpu_div_fOperands_S0_first__6_BIT_130_33_EQ_fp_ETC___d335)
begin
case (fpu_div_fOperands_S0$D_OUT[2:0])
3'd0: _theResult___fst_sfd__h19008 = 52'd0;
3'd1: _theResult___fst_sfd__h19008 = 52'd1;
3'd2:
_theResult___fst_sfd__h19008 =
fpu_div_fOperands_S0_first__6_BIT_130_33_EQ_fp_ETC___d335 ?
52'd1 :
52'd0;
3'd3:
_theResult___fst_sfd__h19008 =
fpu_div_fOperands_S0_first__6_BIT_130_33_EQ_fp_ETC___d335 ?
52'd0 :
52'd1;
default: _theResult___fst_sfd__h19008 = 52'd0;
endcase
end
always@(fpu_div_fOperands_S0$D_OUT or
fpu_div_fOperands_S0_first__6_BIT_130_33_EQ_fp_ETC___d335)
begin
case (fpu_div_fOperands_S0$D_OUT[2:0])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_fpu_div_fOperands_S0D_OUT_BITS_2_TO_0_0__ETC__q9 =
!fpu_div_fOperands_S0_first__6_BIT_130_33_EQ_fp_ETC___d335;
default: CASE_fpu_div_fOperands_S0D_OUT_BITS_2_TO_0_0__ETC__q9 =
fpu_div_fOperands_S0$D_OUT[2:0] == 3'd4 &&
!fpu_div_fOperands_S0_first__6_BIT_130_33_EQ_fp_ETC___d335;
endcase
end
always@(fpu_div_fState_S4$D_OUT or
out_exp__h42529 or _theResult___exp__h42526)
begin
case (fpu_div_fState_S4$D_OUT[1:0])
2'b0, 2'b01:
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q14 =
fpu_div_fState_S4$D_OUT[64:54];
2'b10:
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q14 =
out_exp__h42529;
2'b11:
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q14 =
_theResult___exp__h42526;
endcase
end
always@(fpu_div_fState_S4$D_OUT or _theResult___exp__h42526)
begin
case (fpu_div_fState_S4$D_OUT[1:0])
2'b0:
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q15 =
fpu_div_fState_S4$D_OUT[64:54];
2'b01, 2'b10, 2'b11:
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q15 =
_theResult___exp__h42526;
endcase
end
always@(fpu_div_fState_S4$D_OUT or
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q14 or
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q15 or
_theResult___exp__h42526)
begin
case (fpu_div_fState_S4$D_OUT[68:66])
3'd0:
_theResult___fst_exp__h42604 =
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q14;
3'd1:
_theResult___fst_exp__h42604 =
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q15;
3'd2:
_theResult___fst_exp__h42604 =
(fpu_div_fState_S4$D_OUT[1:0] == 2'b0 ||
fpu_div_fState_S4$D_OUT[65]) ?
fpu_div_fState_S4$D_OUT[64:54] :
_theResult___exp__h42526;
3'd3:
_theResult___fst_exp__h42604 =
(fpu_div_fState_S4$D_OUT[1:0] == 2'b0) ?
fpu_div_fState_S4$D_OUT[64:54] :
(fpu_div_fState_S4$D_OUT[65] ?
_theResult___exp__h42526 :
fpu_div_fState_S4$D_OUT[64:54]);
3'd4: _theResult___fst_exp__h42604 = fpu_div_fState_S4$D_OUT[64:54];
default: _theResult___fst_exp__h42604 = 11'd0;
endcase
end
always@(fpu_sqr_fState_S4$D_OUT or
out_exp__h95912 or _theResult___exp__h95909)
begin
case (fpu_sqr_fState_S4$D_OUT[1:0])
2'b0, 2'b01:
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q21 =
fpu_sqr_fState_S4$D_OUT[64:54];
2'b10:
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q21 =
out_exp__h95912;
2'b11:
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q21 =
_theResult___exp__h95909;
endcase
end
always@(fpu_sqr_fState_S4$D_OUT or _theResult___exp__h95909)
begin
case (fpu_sqr_fState_S4$D_OUT[1:0])
2'b0:
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q22 =
fpu_sqr_fState_S4$D_OUT[64:54];
2'b01, 2'b10, 2'b11:
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q22 =
_theResult___exp__h95909;
endcase
end
always@(fpu_sqr_fState_S4$D_OUT or
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q21 or
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q22 or
_theResult___exp__h95909)
begin
case (fpu_sqr_fState_S4$D_OUT[68:66])
3'd0:
_theResult___fst_exp__h95987 =
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q21;
3'd1:
_theResult___fst_exp__h95987 =
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q22;
3'd2:
_theResult___fst_exp__h95987 =
(fpu_sqr_fState_S4$D_OUT[1:0] == 2'b0 ||
fpu_sqr_fState_S4$D_OUT[65]) ?
fpu_sqr_fState_S4$D_OUT[64:54] :
_theResult___exp__h95909;
3'd3:
_theResult___fst_exp__h95987 =
(fpu_sqr_fState_S4$D_OUT[1:0] == 2'b0) ?
fpu_sqr_fState_S4$D_OUT[64:54] :
(fpu_sqr_fState_S4$D_OUT[65] ?
_theResult___exp__h95909 :
fpu_sqr_fState_S4$D_OUT[64:54]);
3'd4: _theResult___fst_exp__h95987 = fpu_sqr_fState_S4$D_OUT[64:54];
default: _theResult___fst_exp__h95987 = 11'd0;
endcase
end
always@(fpu_madd_fState_S8$D_OUT or
out_exp__h142544 or _theResult___exp__h142541)
begin
case (fpu_madd_fState_S8$D_OUT[2:1])
2'b0, 2'b01:
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31 =
fpu_madd_fState_S8$D_OUT[65:55];
2'b10:
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31 =
out_exp__h142544;
2'b11:
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31 =
_theResult___exp__h142541;
endcase
end
always@(fpu_madd_fState_S8$D_OUT or _theResult___exp__h142541)
begin
case (fpu_madd_fState_S8$D_OUT[2:1])
2'b0:
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32 =
fpu_madd_fState_S8$D_OUT[65:55];
2'b01, 2'b10, 2'b11:
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32 =
_theResult___exp__h142541;
endcase
end
always@(fpu_madd_fState_S8$D_OUT or
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31 or
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32 or
_theResult___exp__h142541)
begin
case (fpu_madd_fState_S8$D_OUT[70:68])
3'd0:
_theResult___fst_exp__h142619 =
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31;
3'd1:
_theResult___fst_exp__h142619 =
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32;
3'd2:
_theResult___fst_exp__h142619 =
(fpu_madd_fState_S8$D_OUT[2:1] == 2'b0 ||
fpu_madd_fState_S8$D_OUT[66]) ?
fpu_madd_fState_S8$D_OUT[65:55] :
_theResult___exp__h142541;
3'd3:
_theResult___fst_exp__h142619 =
(fpu_madd_fState_S8$D_OUT[2:1] == 2'b0) ?
fpu_madd_fState_S8$D_OUT[65:55] :
(fpu_madd_fState_S8$D_OUT[66] ?
_theResult___exp__h142541 :
fpu_madd_fState_S8$D_OUT[65:55]);
3'd4: _theResult___fst_exp__h142619 = fpu_madd_fState_S8$D_OUT[65:55];
default: _theResult___fst_exp__h142619 = 11'd0;
endcase
end
always@(guard__h155373 or
_theResult___fst_exp__h163334 or
out_exp__h163982 or _theResult___exp__h163979)
begin
case (guard__h155373)
2'b0, 2'b01:
CASE_guard55373_0b0_theResult___fst_exp63334_0_ETC__q42 =
_theResult___fst_exp__h163334;
2'b10:
CASE_guard55373_0b0_theResult___fst_exp63334_0_ETC__q42 =
out_exp__h163982;
2'b11:
CASE_guard55373_0b0_theResult___fst_exp63334_0_ETC__q42 =
_theResult___exp__h163979;
endcase
end
always@(guard__h155373 or
_theResult___fst_exp__h163334 or _theResult___exp__h163979)
begin
case (guard__h155373)
2'b0:
CASE_guard55373_0b0_theResult___fst_exp63334_0_ETC__q43 =
_theResult___fst_exp__h163334;
2'b01, 2'b10, 2'b11:
CASE_guard55373_0b0_theResult___fst_exp63334_0_ETC__q43 =
_theResult___exp__h163979;
endcase
end
always@(iFifo$D_OUT or
CASE_guard55373_0b0_theResult___fst_exp63334_0_ETC__q42 or
CASE_guard55373_0b0_theResult___fst_exp63334_0_ETC__q43 or
IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3690 or
IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3692 or
_theResult___fst_exp__h163334)
begin
case (iFifo$D_OUT[6:4])
3'd0:
_theResult___fst_exp__h164057 =
CASE_guard55373_0b0_theResult___fst_exp63334_0_ETC__q42;
3'd1:
_theResult___fst_exp__h164057 =
CASE_guard55373_0b0_theResult___fst_exp63334_0_ETC__q43;
3'd2:
_theResult___fst_exp__h164057 =
IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3690;
3'd3:
_theResult___fst_exp__h164057 =
IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3692;
3'd4: _theResult___fst_exp__h164057 = _theResult___fst_exp__h163334;
default: _theResult___fst_exp__h164057 = 11'd0;
endcase
end
always@(guard__h164622 or
_theResult___fst_exp__h172850 or
out_exp__h173572 or _theResult___exp__h173569)
begin
case (guard__h164622)
2'b0, 2'b01:
CASE_guard64622_0b0_theResult___fst_exp72850_0_ETC__q44 =
_theResult___fst_exp__h172850;
2'b10:
CASE_guard64622_0b0_theResult___fst_exp72850_0_ETC__q44 =
out_exp__h173572;
2'b11:
CASE_guard64622_0b0_theResult___fst_exp72850_0_ETC__q44 =
_theResult___exp__h173569;
endcase
end
always@(guard__h164622 or
_theResult___fst_exp__h172850 or _theResult___exp__h173569)
begin
case (guard__h164622)
2'b0:
CASE_guard64622_0b0_theResult___fst_exp72850_0_ETC__q45 =
_theResult___fst_exp__h172850;
2'b01, 2'b10, 2'b11:
CASE_guard64622_0b0_theResult___fst_exp72850_0_ETC__q45 =
_theResult___exp__h173569;
endcase
end
always@(iFifo$D_OUT or
CASE_guard64622_0b0_theResult___fst_exp72850_0_ETC__q44 or
CASE_guard64622_0b0_theResult___fst_exp72850_0_ETC__q45 or
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3729 or
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3731 or
_theResult___fst_exp__h172850)
begin
case (iFifo$D_OUT[6:4])
3'd0:
_theResult___fst_exp__h173647 =
CASE_guard64622_0b0_theResult___fst_exp72850_0_ETC__q44;
3'd1:
_theResult___fst_exp__h173647 =
CASE_guard64622_0b0_theResult___fst_exp72850_0_ETC__q45;
3'd2:
_theResult___fst_exp__h173647 =
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3729;
3'd3:
_theResult___fst_exp__h173647 =
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3731;
3'd4: _theResult___fst_exp__h173647 = _theResult___fst_exp__h172850;
default: _theResult___fst_exp__h173647 = 11'd0;
endcase
end
always@(guard__h173661 or
_theResult___fst_exp__h181651 or
out_exp__h182324 or _theResult___exp__h182321)
begin
case (guard__h173661)
2'b0, 2'b01:
CASE_guard73661_0b0_theResult___fst_exp81651_0_ETC__q46 =
_theResult___fst_exp__h181651;
2'b10:
CASE_guard73661_0b0_theResult___fst_exp81651_0_ETC__q46 =
out_exp__h182324;
2'b11:
CASE_guard73661_0b0_theResult___fst_exp81651_0_ETC__q46 =
_theResult___exp__h182321;
endcase
end
always@(guard__h173661 or
_theResult___fst_exp__h181651 or _theResult___exp__h182321)
begin
case (guard__h173661)
2'b0:
CASE_guard73661_0b0_theResult___fst_exp81651_0_ETC__q47 =
_theResult___fst_exp__h181651;
2'b01, 2'b10, 2'b11:
CASE_guard73661_0b0_theResult___fst_exp81651_0_ETC__q47 =
_theResult___exp__h182321;
endcase
end
always@(iFifo$D_OUT or
CASE_guard73661_0b0_theResult___fst_exp81651_0_ETC__q46 or
CASE_guard73661_0b0_theResult___fst_exp81651_0_ETC__q47 or
IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3760 or
IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3762 or
_theResult___fst_exp__h181651)
begin
case (iFifo$D_OUT[6:4])
3'd0:
_theResult___fst_exp__h182399 =
CASE_guard73661_0b0_theResult___fst_exp81651_0_ETC__q46;
3'd1:
_theResult___fst_exp__h182399 =
CASE_guard73661_0b0_theResult___fst_exp81651_0_ETC__q47;
3'd2:
_theResult___fst_exp__h182399 =
IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3760;
3'd3:
_theResult___fst_exp__h182399 =
IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3762;
3'd4: _theResult___fst_exp__h182399 = _theResult___fst_exp__h181651;
default: _theResult___fst_exp__h182399 = 11'd0;
endcase
end
always@(guard__h155373 or
_theResult___snd__h163285 or
out_sfd__h163983 or _theResult___sfd__h163980)
begin
case (guard__h155373)
2'b0, 2'b01:
CASE_guard55373_0b0_theResult___snd63285_BITS__ETC__q48 =
_theResult___snd__h163285[56:5];
2'b10:
CASE_guard55373_0b0_theResult___snd63285_BITS__ETC__q48 =
out_sfd__h163983;
2'b11:
CASE_guard55373_0b0_theResult___snd63285_BITS__ETC__q48 =
_theResult___sfd__h163980;
endcase
end
always@(guard__h155373 or
_theResult___snd__h163285 or _theResult___sfd__h163980)
begin
case (guard__h155373)
2'b0:
CASE_guard55373_0b0_theResult___snd63285_BITS__ETC__q49 =
_theResult___snd__h163285[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard55373_0b0_theResult___snd63285_BITS__ETC__q49 =
_theResult___sfd__h163980;
endcase
end
always@(iFifo$D_OUT or
CASE_guard55373_0b0_theResult___snd63285_BITS__ETC__q48 or
CASE_guard55373_0b0_theResult___snd63285_BITS__ETC__q49 or
IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3786 or
IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3788 or
_theResult___snd__h163285)
begin
case (iFifo$D_OUT[6:4])
3'd0:
_theResult___fst_sfd__h164058 =
CASE_guard55373_0b0_theResult___snd63285_BITS__ETC__q48;
3'd1:
_theResult___fst_sfd__h164058 =
CASE_guard55373_0b0_theResult___snd63285_BITS__ETC__q49;
3'd2:
_theResult___fst_sfd__h164058 =
IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3786;
3'd3:
_theResult___fst_sfd__h164058 =
IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3788;
3'd4: _theResult___fst_sfd__h164058 = _theResult___snd__h163285[56:5];
default: _theResult___fst_sfd__h164058 = 52'd0;
endcase
end
always@(guard__h164622 or
sfdin__h172844 or out_sfd__h173573 or _theResult___sfd__h173570)
begin
case (guard__h164622)
2'b0, 2'b01:
CASE_guard64622_0b0_sfdin72844_BITS_56_TO_5_0b_ETC__q50 =
sfdin__h172844[56:5];
2'b10:
CASE_guard64622_0b0_sfdin72844_BITS_56_TO_5_0b_ETC__q50 =
out_sfd__h173573;
2'b11:
CASE_guard64622_0b0_sfdin72844_BITS_56_TO_5_0b_ETC__q50 =
_theResult___sfd__h173570;
endcase
end
always@(guard__h164622 or sfdin__h172844 or _theResult___sfd__h173570)
begin
case (guard__h164622)
2'b0:
CASE_guard64622_0b0_sfdin72844_BITS_56_TO_5_0b_ETC__q51 =
sfdin__h172844[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard64622_0b0_sfdin72844_BITS_56_TO_5_0b_ETC__q51 =
_theResult___sfd__h173570;
endcase
end
always@(iFifo$D_OUT or
CASE_guard64622_0b0_sfdin72844_BITS_56_TO_5_0b_ETC__q50 or
CASE_guard64622_0b0_sfdin72844_BITS_56_TO_5_0b_ETC__q51 or
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3813 or
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3815 or
sfdin__h172844)
begin
case (iFifo$D_OUT[6:4])
3'd0:
_theResult___fst_sfd__h173648 =
CASE_guard64622_0b0_sfdin72844_BITS_56_TO_5_0b_ETC__q50;
3'd1:
_theResult___fst_sfd__h173648 =
CASE_guard64622_0b0_sfdin72844_BITS_56_TO_5_0b_ETC__q51;
3'd2:
_theResult___fst_sfd__h173648 =
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3813;
3'd3:
_theResult___fst_sfd__h173648 =
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3815;
3'd4: _theResult___fst_sfd__h173648 = sfdin__h172844[56:5];
default: _theResult___fst_sfd__h173648 = 52'd0;
endcase
end
always@(guard__h173661 or
_theResult___snd__h181597 or
out_sfd__h182325 or _theResult___sfd__h182322)
begin
case (guard__h173661)
2'b0, 2'b01:
CASE_guard73661_0b0_theResult___snd81597_BITS__ETC__q52 =
_theResult___snd__h181597[56:5];
2'b10:
CASE_guard73661_0b0_theResult___snd81597_BITS__ETC__q52 =
out_sfd__h182325;
2'b11:
CASE_guard73661_0b0_theResult___snd81597_BITS__ETC__q52 =
_theResult___sfd__h182322;
endcase
end
always@(guard__h173661 or
_theResult___snd__h181597 or _theResult___sfd__h182322)
begin
case (guard__h173661)
2'b0:
CASE_guard73661_0b0_theResult___snd81597_BITS__ETC__q53 =
_theResult___snd__h181597[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard73661_0b0_theResult___snd81597_BITS__ETC__q53 =
_theResult___sfd__h182322;
endcase
end
always@(iFifo$D_OUT or
CASE_guard73661_0b0_theResult___snd81597_BITS__ETC__q52 or
CASE_guard73661_0b0_theResult___snd81597_BITS__ETC__q53 or
IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3832 or
IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3834 or
_theResult___snd__h181597)
begin
case (iFifo$D_OUT[6:4])
3'd0:
_theResult___fst_sfd__h182400 =
CASE_guard73661_0b0_theResult___snd81597_BITS__ETC__q52;
3'd1:
_theResult___fst_sfd__h182400 =
CASE_guard73661_0b0_theResult___snd81597_BITS__ETC__q53;
3'd2:
_theResult___fst_sfd__h182400 =
IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3832;
3'd3:
_theResult___fst_sfd__h182400 =
IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3834;
3'd4: _theResult___fst_sfd__h182400 = _theResult___snd__h181597[56:5];
default: _theResult___fst_sfd__h182400 = 52'd0;
endcase
end
always@(guard__h155373 or iFifo$D_OUT)
begin
case (guard__h155373)
2'b0, 2'b01, 2'b10:
CASE_guard55373_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54 =
iFifo$D_OUT[168];
2'd3:
CASE_guard55373_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54 =
guard__h155373 == 2'b11 && iFifo$D_OUT[168];
endcase
end
always@(iFifo$D_OUT or
CASE_guard55373_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54 or
guard__h155373)
begin
case (iFifo$D_OUT[6:4])
3'd0:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55373_ETC__q55 =
CASE_guard55373_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54;
3'd1:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55373_ETC__q55 =
(guard__h155373 == 2'b0) ?
iFifo$D_OUT[168] :
(guard__h155373 == 2'b01 || guard__h155373 == 2'b10 ||
guard__h155373 == 2'b11) &&
iFifo$D_OUT[168];
3'd2, 3'd3:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55373_ETC__q55 =
iFifo$D_OUT[168];
default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55373_ETC__q55 =
iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[168];
endcase
end
always@(iFifo$D_OUT)
begin
case (iFifo$D_OUT[6:4])
3'd0, 3'd1, 3'd2, 3'd3:
IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320 =
iFifo$D_OUT[168];
default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320 =
iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[168];
endcase
end
always@(guard__h164622 or iFifo$D_OUT)
begin
case (guard__h164622)
2'b0, 2'b01, 2'b10:
CASE_guard64622_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56 =
iFifo$D_OUT[168];
2'd3:
CASE_guard64622_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56 =
guard__h164622 == 2'b11 && iFifo$D_OUT[168];
endcase
end
always@(iFifo$D_OUT or
CASE_guard64622_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56 or
guard__h164622)
begin
case (iFifo$D_OUT[6:4])
3'd0:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64622_ETC__q57 =
CASE_guard64622_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56;
3'd1:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64622_ETC__q57 =
(guard__h164622 == 2'b0) ?
iFifo$D_OUT[168] :
(guard__h164622 == 2'b01 || guard__h164622 == 2'b10 ||
guard__h164622 == 2'b11) &&
iFifo$D_OUT[168];
3'd2, 3'd3:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64622_ETC__q57 =
iFifo$D_OUT[168];
default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64622_ETC__q57 =
iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[168];
endcase
end
always@(guard__h173661 or iFifo$D_OUT)
begin
case (guard__h173661)
2'b0, 2'b01, 2'b10:
CASE_guard73661_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58 =
iFifo$D_OUT[168];
2'd3:
CASE_guard73661_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58 =
guard__h173661 == 2'b11 && iFifo$D_OUT[168];
endcase
end
always@(iFifo$D_OUT or
CASE_guard73661_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58 or
guard__h173661)
begin
case (iFifo$D_OUT[6:4])
3'd0:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73661_ETC__q59 =
CASE_guard73661_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58;
3'd1:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73661_ETC__q59 =
(guard__h173661 == 2'b0) ?
iFifo$D_OUT[168] :
(guard__h173661 == 2'b01 || guard__h173661 == 2'b10 ||
guard__h173661 == 2'b11) &&
iFifo$D_OUT[168];
3'd2, 3'd3:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73661_ETC__q59 =
iFifo$D_OUT[168];
default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73661_ETC__q59 =
iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[168];
endcase
end
always@(guard__h232950 or
_theResult___fst_exp__h240911 or
out_exp__h241559 or _theResult___exp__h241556)
begin
case (guard__h232950)
2'b0, 2'b01:
CASE_guard32950_0b0_theResult___fst_exp40911_0_ETC__q69 =
_theResult___fst_exp__h240911;
2'b10:
CASE_guard32950_0b0_theResult___fst_exp40911_0_ETC__q69 =
out_exp__h241559;
2'b11:
CASE_guard32950_0b0_theResult___fst_exp40911_0_ETC__q69 =
_theResult___exp__h241556;
endcase
end
always@(guard__h232950 or
_theResult___fst_exp__h240911 or _theResult___exp__h241556)
begin
case (guard__h232950)
2'b0:
CASE_guard32950_0b0_theResult___fst_exp40911_0_ETC__q70 =
_theResult___fst_exp__h240911;
2'b01, 2'b10, 2'b11:
CASE_guard32950_0b0_theResult___fst_exp40911_0_ETC__q70 =
_theResult___exp__h241556;
endcase
end
always@(iFifo$D_OUT or
CASE_guard32950_0b0_theResult___fst_exp40911_0_ETC__q69 or
CASE_guard32950_0b0_theResult___fst_exp40911_0_ETC__q70 or
IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4398 or
IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4400 or
_theResult___fst_exp__h240911)
begin
case (iFifo$D_OUT[6:4])
3'd0:
_theResult___fst_exp__h241634 =
CASE_guard32950_0b0_theResult___fst_exp40911_0_ETC__q69;
3'd1:
_theResult___fst_exp__h241634 =
CASE_guard32950_0b0_theResult___fst_exp40911_0_ETC__q70;
3'd2:
_theResult___fst_exp__h241634 =
IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4398;
3'd3:
_theResult___fst_exp__h241634 =
IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4400;
3'd4: _theResult___fst_exp__h241634 = _theResult___fst_exp__h240911;
default: _theResult___fst_exp__h241634 = 11'd0;
endcase
end
always@(guard__h242199 or
_theResult___fst_exp__h250427 or
out_exp__h251149 or _theResult___exp__h251146)
begin
case (guard__h242199)
2'b0, 2'b01:
CASE_guard42199_0b0_theResult___fst_exp50427_0_ETC__q71 =
_theResult___fst_exp__h250427;
2'b10:
CASE_guard42199_0b0_theResult___fst_exp50427_0_ETC__q71 =
out_exp__h251149;
2'b11:
CASE_guard42199_0b0_theResult___fst_exp50427_0_ETC__q71 =
_theResult___exp__h251146;
endcase
end
always@(guard__h242199 or
_theResult___fst_exp__h250427 or _theResult___exp__h251146)
begin
case (guard__h242199)
2'b0:
CASE_guard42199_0b0_theResult___fst_exp50427_0_ETC__q72 =
_theResult___fst_exp__h250427;
2'b01, 2'b10, 2'b11:
CASE_guard42199_0b0_theResult___fst_exp50427_0_ETC__q72 =
_theResult___exp__h251146;
endcase
end
always@(iFifo$D_OUT or
CASE_guard42199_0b0_theResult___fst_exp50427_0_ETC__q71 or
CASE_guard42199_0b0_theResult___fst_exp50427_0_ETC__q72 or
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4436 or
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4438 or
_theResult___fst_exp__h250427)
begin
case (iFifo$D_OUT[6:4])
3'd0:
_theResult___fst_exp__h251224 =
CASE_guard42199_0b0_theResult___fst_exp50427_0_ETC__q71;
3'd1:
_theResult___fst_exp__h251224 =
CASE_guard42199_0b0_theResult___fst_exp50427_0_ETC__q72;
3'd2:
_theResult___fst_exp__h251224 =
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4436;
3'd3:
_theResult___fst_exp__h251224 =
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4438;
3'd4: _theResult___fst_exp__h251224 = _theResult___fst_exp__h250427;
default: _theResult___fst_exp__h251224 = 11'd0;
endcase
end
always@(guard__h251238 or
_theResult___fst_exp__h259228 or
out_exp__h259901 or _theResult___exp__h259898)
begin
case (guard__h251238)
2'b0, 2'b01:
CASE_guard51238_0b0_theResult___fst_exp59228_0_ETC__q73 =
_theResult___fst_exp__h259228;
2'b10:
CASE_guard51238_0b0_theResult___fst_exp59228_0_ETC__q73 =
out_exp__h259901;
2'b11:
CASE_guard51238_0b0_theResult___fst_exp59228_0_ETC__q73 =
_theResult___exp__h259898;
endcase
end
always@(guard__h251238 or
_theResult___fst_exp__h259228 or _theResult___exp__h259898)
begin
case (guard__h251238)
2'b0:
CASE_guard51238_0b0_theResult___fst_exp59228_0_ETC__q74 =
_theResult___fst_exp__h259228;
2'b01, 2'b10, 2'b11:
CASE_guard51238_0b0_theResult___fst_exp59228_0_ETC__q74 =
_theResult___exp__h259898;
endcase
end
always@(iFifo$D_OUT or
CASE_guard51238_0b0_theResult___fst_exp59228_0_ETC__q73 or
CASE_guard51238_0b0_theResult___fst_exp59228_0_ETC__q74 or
IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4467 or
IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4469 or
_theResult___fst_exp__h259228)
begin
case (iFifo$D_OUT[6:4])
3'd0:
_theResult___fst_exp__h259976 =
CASE_guard51238_0b0_theResult___fst_exp59228_0_ETC__q73;
3'd1:
_theResult___fst_exp__h259976 =
CASE_guard51238_0b0_theResult___fst_exp59228_0_ETC__q74;
3'd2:
_theResult___fst_exp__h259976 =
IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4467;
3'd3:
_theResult___fst_exp__h259976 =
IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4469;
3'd4: _theResult___fst_exp__h259976 = _theResult___fst_exp__h259228;
default: _theResult___fst_exp__h259976 = 11'd0;
endcase
end
always@(guard__h232950 or
_theResult___snd__h240862 or
out_sfd__h241560 or _theResult___sfd__h241557)
begin
case (guard__h232950)
2'b0, 2'b01:
CASE_guard32950_0b0_theResult___snd40862_BITS__ETC__q75 =
_theResult___snd__h240862[56:5];
2'b10:
CASE_guard32950_0b0_theResult___snd40862_BITS__ETC__q75 =
out_sfd__h241560;
2'b11:
CASE_guard32950_0b0_theResult___snd40862_BITS__ETC__q75 =
_theResult___sfd__h241557;
endcase
end
always@(guard__h232950 or
_theResult___snd__h240862 or _theResult___sfd__h241557)
begin
case (guard__h232950)
2'b0:
CASE_guard32950_0b0_theResult___snd40862_BITS__ETC__q76 =
_theResult___snd__h240862[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard32950_0b0_theResult___snd40862_BITS__ETC__q76 =
_theResult___sfd__h241557;
endcase
end
always@(iFifo$D_OUT or
CASE_guard32950_0b0_theResult___snd40862_BITS__ETC__q75 or
CASE_guard32950_0b0_theResult___snd40862_BITS__ETC__q76 or
IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4493 or
IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4495 or
_theResult___snd__h240862)
begin
case (iFifo$D_OUT[6:4])
3'd0:
_theResult___fst_sfd__h241635 =
CASE_guard32950_0b0_theResult___snd40862_BITS__ETC__q75;
3'd1:
_theResult___fst_sfd__h241635 =
CASE_guard32950_0b0_theResult___snd40862_BITS__ETC__q76;
3'd2:
_theResult___fst_sfd__h241635 =
IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4493;
3'd3:
_theResult___fst_sfd__h241635 =
IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4495;
3'd4: _theResult___fst_sfd__h241635 = _theResult___snd__h240862[56:5];
default: _theResult___fst_sfd__h241635 = 52'd0;
endcase
end
always@(guard__h242199 or
sfdin__h250421 or out_sfd__h251150 or _theResult___sfd__h251147)
begin
case (guard__h242199)
2'b0, 2'b01:
CASE_guard42199_0b0_sfdin50421_BITS_56_TO_5_0b_ETC__q77 =
sfdin__h250421[56:5];
2'b10:
CASE_guard42199_0b0_sfdin50421_BITS_56_TO_5_0b_ETC__q77 =
out_sfd__h251150;
2'b11:
CASE_guard42199_0b0_sfdin50421_BITS_56_TO_5_0b_ETC__q77 =
_theResult___sfd__h251147;
endcase
end
always@(guard__h242199 or sfdin__h250421 or _theResult___sfd__h251147)
begin
case (guard__h242199)
2'b0:
CASE_guard42199_0b0_sfdin50421_BITS_56_TO_5_0b_ETC__q78 =
sfdin__h250421[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard42199_0b0_sfdin50421_BITS_56_TO_5_0b_ETC__q78 =
_theResult___sfd__h251147;
endcase
end
always@(iFifo$D_OUT or
CASE_guard42199_0b0_sfdin50421_BITS_56_TO_5_0b_ETC__q77 or
CASE_guard42199_0b0_sfdin50421_BITS_56_TO_5_0b_ETC__q78 or
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4519 or
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4521 or
sfdin__h250421)
begin
case (iFifo$D_OUT[6:4])
3'd0:
_theResult___fst_sfd__h251225 =
CASE_guard42199_0b0_sfdin50421_BITS_56_TO_5_0b_ETC__q77;
3'd1:
_theResult___fst_sfd__h251225 =
CASE_guard42199_0b0_sfdin50421_BITS_56_TO_5_0b_ETC__q78;
3'd2:
_theResult___fst_sfd__h251225 =
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4519;
3'd3:
_theResult___fst_sfd__h251225 =
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4521;
3'd4: _theResult___fst_sfd__h251225 = sfdin__h250421[56:5];
default: _theResult___fst_sfd__h251225 = 52'd0;
endcase
end
always@(guard__h232950 or iFifo$D_OUT)
begin
case (guard__h232950)
2'b0, 2'b01, 2'b10:
CASE_guard32950_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q79 =
iFifo$D_OUT[38];
2'd3:
CASE_guard32950_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q79 =
guard__h232950 == 2'b11 && iFifo$D_OUT[38];
endcase
end
always@(iFifo$D_OUT or
CASE_guard32950_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q79 or
guard__h232950)
begin
case (iFifo$D_OUT[6:4])
3'd0:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32950_ETC__q80 =
CASE_guard32950_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q79;
3'd1:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32950_ETC__q80 =
(guard__h232950 == 2'b0) ?
iFifo$D_OUT[38] :
(guard__h232950 == 2'b01 || guard__h232950 == 2'b10 ||
guard__h232950 == 2'b11) &&
iFifo$D_OUT[38];
3'd2, 3'd3:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32950_ETC__q80 =
iFifo$D_OUT[38];
default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32950_ETC__q80 =
iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[38];
endcase
end
always@(guard__h251238 or
_theResult___snd__h259174 or
out_sfd__h259902 or _theResult___sfd__h259899)
begin
case (guard__h251238)
2'b0, 2'b01:
CASE_guard51238_0b0_theResult___snd59174_BITS__ETC__q81 =
_theResult___snd__h259174[56:5];
2'b10:
CASE_guard51238_0b0_theResult___snd59174_BITS__ETC__q81 =
out_sfd__h259902;
2'b11:
CASE_guard51238_0b0_theResult___snd59174_BITS__ETC__q81 =
_theResult___sfd__h259899;
endcase
end
always@(guard__h251238 or
_theResult___snd__h259174 or _theResult___sfd__h259899)
begin
case (guard__h251238)
2'b0:
CASE_guard51238_0b0_theResult___snd59174_BITS__ETC__q82 =
_theResult___snd__h259174[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard51238_0b0_theResult___snd59174_BITS__ETC__q82 =
_theResult___sfd__h259899;
endcase
end
always@(iFifo$D_OUT or
CASE_guard51238_0b0_theResult___snd59174_BITS__ETC__q81 or
CASE_guard51238_0b0_theResult___snd59174_BITS__ETC__q82 or
IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4538 or
IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4540 or
_theResult___snd__h259174)
begin
case (iFifo$D_OUT[6:4])
3'd0:
_theResult___fst_sfd__h259977 =
CASE_guard51238_0b0_theResult___snd59174_BITS__ETC__q81;
3'd1:
_theResult___fst_sfd__h259977 =
CASE_guard51238_0b0_theResult___snd59174_BITS__ETC__q82;
3'd2:
_theResult___fst_sfd__h259977 =
IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4538;
3'd3:
_theResult___fst_sfd__h259977 =
IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4540;
3'd4: _theResult___fst_sfd__h259977 = _theResult___snd__h259174[56:5];
default: _theResult___fst_sfd__h259977 = 52'd0;
endcase
end
always@(iFifo$D_OUT)
begin
case (iFifo$D_OUT[6:4])
3'd0, 3'd1, 3'd2, 3'd3:
IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028 =
iFifo$D_OUT[38];
default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028 =
iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[38];
endcase
end
always@(guard__h242199 or iFifo$D_OUT)
begin
case (guard__h242199)
2'b0, 2'b01, 2'b10:
CASE_guard42199_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83 =
iFifo$D_OUT[38];
2'd3:
CASE_guard42199_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83 =
guard__h242199 == 2'b11 && iFifo$D_OUT[38];
endcase
end
always@(iFifo$D_OUT or
CASE_guard42199_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83 or
guard__h242199)
begin
case (iFifo$D_OUT[6:4])
3'd0:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42199_ETC__q84 =
CASE_guard42199_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83;
3'd1:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42199_ETC__q84 =
(guard__h242199 == 2'b0) ?
iFifo$D_OUT[38] :
(guard__h242199 == 2'b01 || guard__h242199 == 2'b10 ||
guard__h242199 == 2'b11) &&
iFifo$D_OUT[38];
3'd2, 3'd3:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42199_ETC__q84 =
iFifo$D_OUT[38];
default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42199_ETC__q84 =
iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[38];
endcase
end
always@(guard__h251238 or iFifo$D_OUT)
begin
case (guard__h251238)
2'b0, 2'b01, 2'b10:
CASE_guard51238_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85 =
iFifo$D_OUT[38];
2'd3:
CASE_guard51238_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85 =
guard__h251238 == 2'b11 && iFifo$D_OUT[38];
endcase
end
always@(iFifo$D_OUT or
CASE_guard51238_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85 or
guard__h251238)
begin
case (iFifo$D_OUT[6:4])
3'd0:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51238_ETC__q86 =
CASE_guard51238_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85;
3'd1:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51238_ETC__q86 =
(guard__h251238 == 2'b0) ?
iFifo$D_OUT[38] :
(guard__h251238 == 2'b01 || guard__h251238 == 2'b10 ||
guard__h251238 == 2'b11) &&
iFifo$D_OUT[38];
3'd2, 3'd3:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51238_ETC__q86 =
iFifo$D_OUT[38];
default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51238_ETC__q86 =
iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[38];
endcase
end
always@(guard__h232950 or iFifo$D_OUT)
begin
case (guard__h232950)
2'b0, 2'b01, 2'b10:
CASE_guard32950_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87 =
!iFifo$D_OUT[38];
2'd3:
CASE_guard32950_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87 =
guard__h232950 != 2'b11 || !iFifo$D_OUT[38];
endcase
end
always@(iFifo$D_OUT or
CASE_guard32950_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87 or
guard__h232950)
begin
case (iFifo$D_OUT[6:4])
3'd0:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32950_ETC__q88 =
CASE_guard32950_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87;
3'd1:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32950_ETC__q88 =
(guard__h232950 == 2'b0) ?
!iFifo$D_OUT[38] :
guard__h232950 != 2'b01 && guard__h232950 != 2'b10 &&
guard__h232950 != 2'b11 ||
!iFifo$D_OUT[38];
3'd2, 3'd3:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32950_ETC__q88 =
!iFifo$D_OUT[38];
default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32950_ETC__q88 =
iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[38];
endcase
end
always@(guard__h242199 or iFifo$D_OUT)
begin
case (guard__h242199)
2'b0, 2'b01, 2'b10:
CASE_guard42199_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89 =
!iFifo$D_OUT[38];
2'd3:
CASE_guard42199_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89 =
guard__h242199 != 2'b11 || !iFifo$D_OUT[38];
endcase
end
always@(iFifo$D_OUT or
CASE_guard42199_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89 or
guard__h242199)
begin
case (iFifo$D_OUT[6:4])
3'd0:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42199_ETC__q90 =
CASE_guard42199_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89;
3'd1:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42199_ETC__q90 =
(guard__h242199 == 2'b0) ?
!iFifo$D_OUT[38] :
guard__h242199 != 2'b01 && guard__h242199 != 2'b10 &&
guard__h242199 != 2'b11 ||
!iFifo$D_OUT[38];
3'd2, 3'd3:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42199_ETC__q90 =
!iFifo$D_OUT[38];
default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42199_ETC__q90 =
iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[38];
endcase
end
always@(guard__h251238 or iFifo$D_OUT)
begin
case (guard__h251238)
2'b0, 2'b01, 2'b10:
CASE_guard51238_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91 =
!iFifo$D_OUT[38];
2'd3:
CASE_guard51238_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91 =
guard__h251238 != 2'b11 || !iFifo$D_OUT[38];
endcase
end
always@(iFifo$D_OUT or
CASE_guard51238_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91 or
guard__h251238)
begin
case (iFifo$D_OUT[6:4])
3'd0:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51238_ETC__q92 =
CASE_guard51238_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91;
3'd1:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51238_ETC__q92 =
(guard__h251238 == 2'b0) ?
!iFifo$D_OUT[38] :
guard__h251238 != 2'b01 && guard__h251238 != 2'b10 &&
guard__h251238 != 2'b11 ||
!iFifo$D_OUT[38];
3'd2, 3'd3:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51238_ETC__q92 =
!iFifo$D_OUT[38];
default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51238_ETC__q92 =
iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[38];
endcase
end
always@(iFifo$D_OUT)
begin
case (iFifo$D_OUT[6:4])
3'd0, 3'd1, 3'd2, 3'd3:
IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582 =
!iFifo$D_OUT[38];
default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582 =
iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[38];
endcase
end
always@(guard__h194011 or
_theResult___fst_exp__h201972 or
out_exp__h202620 or _theResult___exp__h202617)
begin
case (guard__h194011)
2'b0, 2'b01:
CASE_guard94011_0b0_theResult___fst_exp01972_0_ETC__q102 =
_theResult___fst_exp__h201972;
2'b10:
CASE_guard94011_0b0_theResult___fst_exp01972_0_ETC__q102 =
out_exp__h202620;
2'b11:
CASE_guard94011_0b0_theResult___fst_exp01972_0_ETC__q102 =
_theResult___exp__h202617;
endcase
end
always@(guard__h194011 or
_theResult___fst_exp__h201972 or _theResult___exp__h202617)
begin
case (guard__h194011)
2'b0:
CASE_guard94011_0b0_theResult___fst_exp01972_0_ETC__q103 =
_theResult___fst_exp__h201972;
2'b01, 2'b10, 2'b11:
CASE_guard94011_0b0_theResult___fst_exp01972_0_ETC__q103 =
_theResult___exp__h202617;
endcase
end
always@(iFifo$D_OUT or
CASE_guard94011_0b0_theResult___fst_exp01972_0_ETC__q102 or
CASE_guard94011_0b0_theResult___fst_exp01972_0_ETC__q103 or
IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5173 or
IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5175 or
_theResult___fst_exp__h201972)
begin
case (iFifo$D_OUT[6:4])
3'd0:
_theResult___fst_exp__h202695 =
CASE_guard94011_0b0_theResult___fst_exp01972_0_ETC__q102;
3'd1:
_theResult___fst_exp__h202695 =
CASE_guard94011_0b0_theResult___fst_exp01972_0_ETC__q103;
3'd2:
_theResult___fst_exp__h202695 =
IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5173;
3'd3:
_theResult___fst_exp__h202695 =
IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5175;
3'd4: _theResult___fst_exp__h202695 = _theResult___fst_exp__h201972;
default: _theResult___fst_exp__h202695 = 11'd0;
endcase
end
always@(guard__h203260 or
_theResult___fst_exp__h211488 or
out_exp__h212210 or _theResult___exp__h212207)
begin
case (guard__h203260)
2'b0, 2'b01:
CASE_guard03260_0b0_theResult___fst_exp11488_0_ETC__q104 =
_theResult___fst_exp__h211488;
2'b10:
CASE_guard03260_0b0_theResult___fst_exp11488_0_ETC__q104 =
out_exp__h212210;
2'b11:
CASE_guard03260_0b0_theResult___fst_exp11488_0_ETC__q104 =
_theResult___exp__h212207;
endcase
end
always@(guard__h203260 or
_theResult___fst_exp__h211488 or _theResult___exp__h212207)
begin
case (guard__h203260)
2'b0:
CASE_guard03260_0b0_theResult___fst_exp11488_0_ETC__q105 =
_theResult___fst_exp__h211488;
2'b01, 2'b10, 2'b11:
CASE_guard03260_0b0_theResult___fst_exp11488_0_ETC__q105 =
_theResult___exp__h212207;
endcase
end
always@(iFifo$D_OUT or
CASE_guard03260_0b0_theResult___fst_exp11488_0_ETC__q104 or
CASE_guard03260_0b0_theResult___fst_exp11488_0_ETC__q105 or
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5211 or
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5213 or
_theResult___fst_exp__h211488)
begin
case (iFifo$D_OUT[6:4])
3'd0:
_theResult___fst_exp__h212285 =
CASE_guard03260_0b0_theResult___fst_exp11488_0_ETC__q104;
3'd1:
_theResult___fst_exp__h212285 =
CASE_guard03260_0b0_theResult___fst_exp11488_0_ETC__q105;
3'd2:
_theResult___fst_exp__h212285 =
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5211;
3'd3:
_theResult___fst_exp__h212285 =
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5213;
3'd4: _theResult___fst_exp__h212285 = _theResult___fst_exp__h211488;
default: _theResult___fst_exp__h212285 = 11'd0;
endcase
end
always@(guard__h212299 or
_theResult___fst_exp__h220289 or
out_exp__h220962 or _theResult___exp__h220959)
begin
case (guard__h212299)
2'b0, 2'b01:
CASE_guard12299_0b0_theResult___fst_exp20289_0_ETC__q106 =
_theResult___fst_exp__h220289;
2'b10:
CASE_guard12299_0b0_theResult___fst_exp20289_0_ETC__q106 =
out_exp__h220962;
2'b11:
CASE_guard12299_0b0_theResult___fst_exp20289_0_ETC__q106 =
_theResult___exp__h220959;
endcase
end
always@(guard__h212299 or
_theResult___fst_exp__h220289 or _theResult___exp__h220959)
begin
case (guard__h212299)
2'b0:
CASE_guard12299_0b0_theResult___fst_exp20289_0_ETC__q107 =
_theResult___fst_exp__h220289;
2'b01, 2'b10, 2'b11:
CASE_guard12299_0b0_theResult___fst_exp20289_0_ETC__q107 =
_theResult___exp__h220959;
endcase
end
always@(iFifo$D_OUT or
CASE_guard12299_0b0_theResult___fst_exp20289_0_ETC__q106 or
CASE_guard12299_0b0_theResult___fst_exp20289_0_ETC__q107 or
IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5242 or
IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5244 or
_theResult___fst_exp__h220289)
begin
case (iFifo$D_OUT[6:4])
3'd0:
_theResult___fst_exp__h221037 =
CASE_guard12299_0b0_theResult___fst_exp20289_0_ETC__q106;
3'd1:
_theResult___fst_exp__h221037 =
CASE_guard12299_0b0_theResult___fst_exp20289_0_ETC__q107;
3'd2:
_theResult___fst_exp__h221037 =
IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5242;
3'd3:
_theResult___fst_exp__h221037 =
IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5244;
3'd4: _theResult___fst_exp__h221037 = _theResult___fst_exp__h220289;
default: _theResult___fst_exp__h221037 = 11'd0;
endcase
end
always@(guard__h194011 or
_theResult___snd__h201923 or
out_sfd__h202621 or _theResult___sfd__h202618)
begin
case (guard__h194011)
2'b0, 2'b01:
CASE_guard94011_0b0_theResult___snd01923_BITS__ETC__q108 =
_theResult___snd__h201923[56:5];
2'b10:
CASE_guard94011_0b0_theResult___snd01923_BITS__ETC__q108 =
out_sfd__h202621;
2'b11:
CASE_guard94011_0b0_theResult___snd01923_BITS__ETC__q108 =
_theResult___sfd__h202618;
endcase
end
always@(guard__h194011 or
_theResult___snd__h201923 or _theResult___sfd__h202618)
begin
case (guard__h194011)
2'b0:
CASE_guard94011_0b0_theResult___snd01923_BITS__ETC__q109 =
_theResult___snd__h201923[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard94011_0b0_theResult___snd01923_BITS__ETC__q109 =
_theResult___sfd__h202618;
endcase
end
always@(iFifo$D_OUT or
CASE_guard94011_0b0_theResult___snd01923_BITS__ETC__q108 or
CASE_guard94011_0b0_theResult___snd01923_BITS__ETC__q109 or
IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5268 or
IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5270 or
_theResult___snd__h201923)
begin
case (iFifo$D_OUT[6:4])
3'd0:
_theResult___fst_sfd__h202696 =
CASE_guard94011_0b0_theResult___snd01923_BITS__ETC__q108;
3'd1:
_theResult___fst_sfd__h202696 =
CASE_guard94011_0b0_theResult___snd01923_BITS__ETC__q109;
3'd2:
_theResult___fst_sfd__h202696 =
IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5268;
3'd3:
_theResult___fst_sfd__h202696 =
IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5270;
3'd4: _theResult___fst_sfd__h202696 = _theResult___snd__h201923[56:5];
default: _theResult___fst_sfd__h202696 = 52'd0;
endcase
end
always@(guard__h203260 or
sfdin__h211482 or out_sfd__h212211 or _theResult___sfd__h212208)
begin
case (guard__h203260)
2'b0, 2'b01:
CASE_guard03260_0b0_sfdin11482_BITS_56_TO_5_0b_ETC__q110 =
sfdin__h211482[56:5];
2'b10:
CASE_guard03260_0b0_sfdin11482_BITS_56_TO_5_0b_ETC__q110 =
out_sfd__h212211;
2'b11:
CASE_guard03260_0b0_sfdin11482_BITS_56_TO_5_0b_ETC__q110 =
_theResult___sfd__h212208;
endcase
end
always@(guard__h203260 or sfdin__h211482 or _theResult___sfd__h212208)
begin
case (guard__h203260)
2'b0:
CASE_guard03260_0b0_sfdin11482_BITS_56_TO_5_0b_ETC__q111 =
sfdin__h211482[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard03260_0b0_sfdin11482_BITS_56_TO_5_0b_ETC__q111 =
_theResult___sfd__h212208;
endcase
end
always@(iFifo$D_OUT or
CASE_guard03260_0b0_sfdin11482_BITS_56_TO_5_0b_ETC__q110 or
CASE_guard03260_0b0_sfdin11482_BITS_56_TO_5_0b_ETC__q111 or
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5294 or
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5296 or
sfdin__h211482)
begin
case (iFifo$D_OUT[6:4])
3'd0:
_theResult___fst_sfd__h212286 =
CASE_guard03260_0b0_sfdin11482_BITS_56_TO_5_0b_ETC__q110;
3'd1:
_theResult___fst_sfd__h212286 =
CASE_guard03260_0b0_sfdin11482_BITS_56_TO_5_0b_ETC__q111;
3'd2:
_theResult___fst_sfd__h212286 =
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5294;
3'd3:
_theResult___fst_sfd__h212286 =
IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5296;
3'd4: _theResult___fst_sfd__h212286 = sfdin__h211482[56:5];
default: _theResult___fst_sfd__h212286 = 52'd0;
endcase
end
always@(guard__h212299 or
_theResult___snd__h220235 or
out_sfd__h220963 or _theResult___sfd__h220960)
begin
case (guard__h212299)
2'b0, 2'b01:
CASE_guard12299_0b0_theResult___snd20235_BITS__ETC__q112 =
_theResult___snd__h220235[56:5];
2'b10:
CASE_guard12299_0b0_theResult___snd20235_BITS__ETC__q112 =
out_sfd__h220963;
2'b11:
CASE_guard12299_0b0_theResult___snd20235_BITS__ETC__q112 =
_theResult___sfd__h220960;
endcase
end
always@(guard__h212299 or
_theResult___snd__h220235 or _theResult___sfd__h220960)
begin
case (guard__h212299)
2'b0:
CASE_guard12299_0b0_theResult___snd20235_BITS__ETC__q113 =
_theResult___snd__h220235[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard12299_0b0_theResult___snd20235_BITS__ETC__q113 =
_theResult___sfd__h220960;
endcase
end
always@(iFifo$D_OUT or
CASE_guard12299_0b0_theResult___snd20235_BITS__ETC__q112 or
CASE_guard12299_0b0_theResult___snd20235_BITS__ETC__q113 or
IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5313 or
IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5315 or
_theResult___snd__h220235)
begin
case (iFifo$D_OUT[6:4])
3'd0:
_theResult___fst_sfd__h221038 =
CASE_guard12299_0b0_theResult___snd20235_BITS__ETC__q112;
3'd1:
_theResult___fst_sfd__h221038 =
CASE_guard12299_0b0_theResult___snd20235_BITS__ETC__q113;
3'd2:
_theResult___fst_sfd__h221038 =
IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5313;
3'd3:
_theResult___fst_sfd__h221038 =
IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5315;
3'd4: _theResult___fst_sfd__h221038 = _theResult___snd__h220235[56:5];
default: _theResult___fst_sfd__h221038 = 52'd0;
endcase
end
always@(guard__h194011 or iFifo$D_OUT)
begin
case (guard__h194011)
2'b0, 2'b01, 2'b10:
CASE_guard94011_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114 =
iFifo$D_OUT[103];
2'd3:
CASE_guard94011_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114 =
guard__h194011 == 2'b11 && iFifo$D_OUT[103];
endcase
end
always@(iFifo$D_OUT or
CASE_guard94011_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114 or
guard__h194011)
begin
case (iFifo$D_OUT[6:4])
3'd0:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94011_ETC__q115 =
CASE_guard94011_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114;
3'd1:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94011_ETC__q115 =
(guard__h194011 == 2'b0) ?
iFifo$D_OUT[103] :
(guard__h194011 == 2'b01 || guard__h194011 == 2'b10 ||
guard__h194011 == 2'b11) &&
iFifo$D_OUT[103];
3'd2, 3'd3:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94011_ETC__q115 =
iFifo$D_OUT[103];
default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94011_ETC__q115 =
iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[103];
endcase
end
always@(iFifo$D_OUT)
begin
case (iFifo$D_OUT[6:4])
3'd0, 3'd1, 3'd2, 3'd3:
IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803 =
iFifo$D_OUT[103];
default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803 =
iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[103];
endcase
end
always@(guard__h203260 or iFifo$D_OUT)
begin
case (guard__h203260)
2'b0, 2'b01, 2'b10:
CASE_guard03260_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116 =
iFifo$D_OUT[103];
2'd3:
CASE_guard03260_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116 =
guard__h203260 == 2'b11 && iFifo$D_OUT[103];
endcase
end
always@(iFifo$D_OUT or
CASE_guard03260_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116 or
guard__h203260)
begin
case (iFifo$D_OUT[6:4])
3'd0:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03260_ETC__q117 =
CASE_guard03260_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116;
3'd1:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03260_ETC__q117 =
(guard__h203260 == 2'b0) ?
iFifo$D_OUT[103] :
(guard__h203260 == 2'b01 || guard__h203260 == 2'b10 ||
guard__h203260 == 2'b11) &&
iFifo$D_OUT[103];
3'd2, 3'd3:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03260_ETC__q117 =
iFifo$D_OUT[103];
default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03260_ETC__q117 =
iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[103];
endcase
end
always@(guard__h212299 or iFifo$D_OUT)
begin
case (guard__h212299)
2'b0, 2'b01, 2'b10:
CASE_guard12299_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118 =
iFifo$D_OUT[103];
2'd3:
CASE_guard12299_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118 =
guard__h212299 == 2'b11 && iFifo$D_OUT[103];
endcase
end
always@(iFifo$D_OUT or
CASE_guard12299_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118 or
guard__h212299)
begin
case (iFifo$D_OUT[6:4])
3'd0:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12299_ETC__q119 =
CASE_guard12299_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118;
3'd1:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12299_ETC__q119 =
(guard__h212299 == 2'b0) ?
iFifo$D_OUT[103] :
(guard__h212299 == 2'b01 || guard__h212299 == 2'b10 ||
guard__h212299 == 2'b11) &&
iFifo$D_OUT[103];
3'd2, 3'd3:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12299_ETC__q119 =
iFifo$D_OUT[103];
default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12299_ETC__q119 =
iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[103];
endcase
end
always@(guard__h194011 or iFifo$D_OUT)
begin
case (guard__h194011)
2'b0, 2'b01, 2'b10:
CASE_guard94011_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120 =
!iFifo$D_OUT[103];
2'd3:
CASE_guard94011_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120 =
guard__h194011 != 2'b11 || !iFifo$D_OUT[103];
endcase
end
always@(iFifo$D_OUT or
CASE_guard94011_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120 or
guard__h194011)
begin
case (iFifo$D_OUT[6:4])
3'd0:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94011_ETC__q121 =
CASE_guard94011_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120;
3'd1:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94011_ETC__q121 =
(guard__h194011 == 2'b0) ?
!iFifo$D_OUT[103] :
guard__h194011 != 2'b01 && guard__h194011 != 2'b10 &&
guard__h194011 != 2'b11 ||
!iFifo$D_OUT[103];
3'd2, 3'd3:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94011_ETC__q121 =
!iFifo$D_OUT[103];
default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94011_ETC__q121 =
iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[103];
endcase
end
always@(guard__h203260 or iFifo$D_OUT)
begin
case (guard__h203260)
2'b0, 2'b01, 2'b10:
CASE_guard03260_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122 =
!iFifo$D_OUT[103];
2'd3:
CASE_guard03260_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122 =
guard__h203260 != 2'b11 || !iFifo$D_OUT[103];
endcase
end
always@(iFifo$D_OUT or
CASE_guard03260_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122 or
guard__h203260)
begin
case (iFifo$D_OUT[6:4])
3'd0:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03260_ETC__q123 =
CASE_guard03260_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122;
3'd1:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03260_ETC__q123 =
(guard__h203260 == 2'b0) ?
!iFifo$D_OUT[103] :
guard__h203260 != 2'b01 && guard__h203260 != 2'b10 &&
guard__h203260 != 2'b11 ||
!iFifo$D_OUT[103];
3'd2, 3'd3:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03260_ETC__q123 =
!iFifo$D_OUT[103];
default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03260_ETC__q123 =
iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[103];
endcase
end
always@(guard__h212299 or iFifo$D_OUT)
begin
case (guard__h212299)
2'b0, 2'b01, 2'b10:
CASE_guard12299_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124 =
!iFifo$D_OUT[103];
2'd3:
CASE_guard12299_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124 =
guard__h212299 != 2'b11 || !iFifo$D_OUT[103];
endcase
end
always@(iFifo$D_OUT or
CASE_guard12299_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124 or
guard__h212299)
begin
case (iFifo$D_OUT[6:4])
3'd0:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12299_ETC__q125 =
CASE_guard12299_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124;
3'd1:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12299_ETC__q125 =
(guard__h212299 == 2'b0) ?
!iFifo$D_OUT[103] :
guard__h212299 != 2'b01 && guard__h212299 != 2'b10 &&
guard__h212299 != 2'b11 ||
!iFifo$D_OUT[103];
3'd2, 3'd3:
CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12299_ETC__q125 =
!iFifo$D_OUT[103];
default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12299_ETC__q125 =
iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[103];
endcase
end
always@(iFifo$D_OUT)
begin
case (iFifo$D_OUT[6:4])
3'd0, 3'd1, 3'd2, 3'd3:
IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348 =
!iFifo$D_OUT[103];
default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348 =
iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[103];
endcase
end
always@(fpu_madd_fState_S8$D_OUT)
begin
case (fpu_madd_fState_S8$D_OUT[2:1])
2'b0, 2'b01, 2'b10:
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126 =
fpu_madd_fState_S8$D_OUT[66];
2'd3:
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126 =
fpu_madd_fState_S8$D_OUT[2:1] == 2'b11 &&
fpu_madd_fState_S8$D_OUT[66];
endcase
end
always@(fpu_madd_fState_S8$D_OUT or
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126)
begin
case (fpu_madd_fState_S8$D_OUT[70:68])
3'd0:
CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127 =
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126;
3'd1:
CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127 =
(fpu_madd_fState_S8$D_OUT[2:1] == 2'b0) ?
fpu_madd_fState_S8$D_OUT[66] :
(fpu_madd_fState_S8$D_OUT[2:1] == 2'b01 ||
fpu_madd_fState_S8$D_OUT[2:1] == 2'b10 ||
fpu_madd_fState_S8$D_OUT[2:1] == 2'b11) &&
fpu_madd_fState_S8$D_OUT[66];
3'd2, 3'd3:
CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127 =
fpu_madd_fState_S8$D_OUT[66];
default: CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127 =
fpu_madd_fState_S8$D_OUT[70:68] == 3'd4 &&
fpu_madd_fState_S8$D_OUT[66];
endcase
end
always@(iFifo$D_OUT or
IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618 or
IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848 or
IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4555)
begin
case (iFifo$D_OUT[3:0])
4'd0, 4'd1:
IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623 =
IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848;
4'd5, 4'd7:
IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623 =
IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4555;
4'd6:
IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623 =
IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618;
default: IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623 =
IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618;
endcase
end
always@(iFifo$D_OUT or
fpu_madd_fOperand_S0$FULL_N or
fpu_div_fOperands_S0$FULL_N or fpu_sqr_fOperand_S0$FULL_N)
begin
case (iFifo$D_OUT[3:0])
4'd0, 4'd1, 4'd2, 4'd5, 4'd6, 4'd7:
IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 =
fpu_madd_fOperand_S0$FULL_N;
4'd3:
IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 =
fpu_div_fOperands_S0$FULL_N;
4'd4:
IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 =
fpu_sqr_fOperand_S0$FULL_N;
default: IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 =
iFifo$D_OUT[3:0] != 4'd8 || fpu_madd_fOperand_S0$FULL_N;
endcase
end
always@(fpu_madd_fState_S8$D_OUT or
IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065)
begin
case (fpu_madd_fState_S8$D_OUT[2:1])
2'b0, 2'b01:
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130 =
fpu_madd_fState_S8$D_OUT[65:3];
2'b10:
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130 =
fpu_madd_fState_S8$D_OUT[3] ?
IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065 :
fpu_madd_fState_S8$D_OUT[65:3];
2'b11:
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130 =
IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065;
endcase
end
always@(fpu_madd_fState_S8$D_OUT or
IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065)
begin
case (fpu_madd_fState_S8$D_OUT[2:1])
2'b0:
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131 =
fpu_madd_fState_S8$D_OUT[65:3];
2'b01, 2'b10, 2'b11:
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131 =
IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065;
endcase
end
always@(fpu_madd_fState_S8$D_OUT or
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130 or
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131 or
IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065)
begin
case (fpu_madd_fState_S8$D_OUT[70:68])
3'd0:
CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 =
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130;
3'd1:
CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 =
CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131;
3'd2:
CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 =
(fpu_madd_fState_S8$D_OUT[2:1] == 2'b0 ||
fpu_madd_fState_S8$D_OUT[66]) ?
fpu_madd_fState_S8$D_OUT[65:3] :
IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065;
3'd3:
CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 =
(fpu_madd_fState_S8$D_OUT[2:1] == 2'b0) ?
fpu_madd_fState_S8$D_OUT[65:3] :
(fpu_madd_fState_S8$D_OUT[66] ?
IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065 :
fpu_madd_fState_S8$D_OUT[65:3]);
3'd4:
CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 =
fpu_madd_fState_S8$D_OUT[65:3];
default: CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 =
63'd0;
endcase
end
always@(rmdFifo$D_OUT or resWire$wget)
begin
case (rmdFifo$D_OUT)
3'd0, 3'd1: _theResult___fst_exp__h269595 = 8'd255;
3'd2:
_theResult___fst_exp__h269595 = resWire$wget[68] ? 8'd254 : 8'd255;
3'd3:
_theResult___fst_exp__h269595 = resWire$wget[68] ? 8'd255 : 8'd254;
3'd4: _theResult___fst_exp__h269595 = 8'd254;
default: _theResult___fst_exp__h269595 = 8'd0;
endcase
end
always@(rmdFifo$D_OUT or resWire$wget)
begin
case (rmdFifo$D_OUT)
3'd0, 3'd1: _theResult___fst_sfd__h269596 = 23'd0;
3'd2:
_theResult___fst_sfd__h269596 =
resWire$wget[68] ? 23'd8388607 : 23'd0;
3'd3:
_theResult___fst_sfd__h269596 =
resWire$wget[68] ? 23'd0 : 23'd8388607;
3'd4: _theResult___fst_sfd__h269596 = 23'd8388607;
default: _theResult___fst_sfd__h269596 = 23'd0;
endcase
end
always@(guard__h269623 or resWire$wget)
begin
case (guard__h269623)
2'b0, 2'b01, 2'b10:
CASE_guard69623_0b0_resWirewget_BIT_68_0b1_re_ETC__q144 =
resWire$wget[68];
2'd3:
CASE_guard69623_0b0_resWirewget_BIT_68_0b1_re_ETC__q144 =
guard__h269623 == 2'b11 && resWire$wget[68];
endcase
end
always@(rmdFifo$D_OUT or
resWire$wget or
CASE_guard69623_0b0_resWirewget_BIT_68_0b1_re_ETC__q144 or
guard__h269623)
begin
case (rmdFifo$D_OUT)
3'd0:
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388 =
CASE_guard69623_0b0_resWirewget_BIT_68_0b1_re_ETC__q144;
3'd1:
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388 =
(guard__h269623 == 2'b0) ?
resWire$wget[68] :
(guard__h269623 == 2'b01 || guard__h269623 == 2'b10 ||
guard__h269623 == 2'b11) &&
resWire$wget[68];
3'd2, 3'd3:
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388 =
resWire$wget[68];
default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388 =
rmdFifo$D_OUT == 3'd4 && resWire$wget[68];
endcase
end
always@(guard__h269623 or resWire$wget)
begin
case (guard__h269623)
2'b0, 2'b01, 2'b10:
CASE_guard69623_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145 =
!resWire$wget[68];
2'd3:
CASE_guard69623_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145 =
guard__h269623 != 2'b11 || !resWire$wget[68];
endcase
end
always@(rmdFifo$D_OUT or
resWire$wget or
CASE_guard69623_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145 or
guard__h269623)
begin
case (rmdFifo$D_OUT)
3'd0:
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823 =
CASE_guard69623_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145;
3'd1:
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823 =
(guard__h269623 == 2'b0) ?
!resWire$wget[68] :
guard__h269623 != 2'b01 && guard__h269623 != 2'b10 &&
guard__h269623 != 2'b11 ||
!resWire$wget[68];
3'd2, 3'd3:
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823 =
!resWire$wget[68];
default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823 =
rmdFifo$D_OUT != 3'd4 || !resWire$wget[68];
endcase
end
always@(guard__h278330 or resWire$wget)
begin
case (guard__h278330)
2'b0, 2'b01, 2'b10:
CASE_guard78330_0b0_resWirewget_BIT_68_0b1_re_ETC__q146 =
resWire$wget[68];
2'd3:
CASE_guard78330_0b0_resWirewget_BIT_68_0b1_re_ETC__q146 =
guard__h278330 == 2'b11 && resWire$wget[68];
endcase
end
always@(rmdFifo$D_OUT or
resWire$wget or
CASE_guard78330_0b0_resWirewget_BIT_68_0b1_re_ETC__q146 or
guard__h278330)
begin
case (rmdFifo$D_OUT)
3'd0:
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397 =
CASE_guard78330_0b0_resWirewget_BIT_68_0b1_re_ETC__q146;
3'd1:
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397 =
(guard__h278330 == 2'b0) ?
resWire$wget[68] :
(guard__h278330 == 2'b01 || guard__h278330 == 2'b10 ||
guard__h278330 == 2'b11) &&
resWire$wget[68];
3'd2, 3'd3:
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397 =
resWire$wget[68];
default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397 =
rmdFifo$D_OUT == 3'd4 && resWire$wget[68];
endcase
end
always@(guard__h278330 or resWire$wget)
begin
case (guard__h278330)
2'b0, 2'b01, 2'b10:
CASE_guard78330_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147 =
!resWire$wget[68];
2'd3:
CASE_guard78330_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147 =
guard__h278330 != 2'b11 || !resWire$wget[68];
endcase
end
always@(rmdFifo$D_OUT or
resWire$wget or
CASE_guard78330_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147 or
guard__h278330)
begin
case (rmdFifo$D_OUT)
3'd0:
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023 =
CASE_guard78330_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147;
3'd1:
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023 =
(guard__h278330 == 2'b0) ?
!resWire$wget[68] :
guard__h278330 != 2'b01 && guard__h278330 != 2'b10 &&
guard__h278330 != 2'b11 ||
!resWire$wget[68];
3'd2, 3'd3:
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023 =
!resWire$wget[68];
default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023 =
rmdFifo$D_OUT != 3'd4 || !resWire$wget[68];
endcase
end
always@(guard__h287260 or resWire$wget)
begin
case (guard__h287260)
2'b0, 2'b01, 2'b10:
CASE_guard87260_0b0_resWirewget_BIT_68_0b1_re_ETC__q148 =
resWire$wget[68];
2'd3:
CASE_guard87260_0b0_resWirewget_BIT_68_0b1_re_ETC__q148 =
guard__h287260 == 2'b11 && resWire$wget[68];
endcase
end
always@(rmdFifo$D_OUT or
resWire$wget or
CASE_guard87260_0b0_resWirewget_BIT_68_0b1_re_ETC__q148 or
guard__h287260)
begin
case (rmdFifo$D_OUT)
3'd0:
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409 =
CASE_guard87260_0b0_resWirewget_BIT_68_0b1_re_ETC__q148;
3'd1:
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409 =
(guard__h287260 == 2'b0) ?
resWire$wget[68] :
(guard__h287260 == 2'b01 || guard__h287260 == 2'b10 ||
guard__h287260 == 2'b11) &&
resWire$wget[68];
3'd2, 3'd3:
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409 =
resWire$wget[68];
default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409 =
rmdFifo$D_OUT == 3'd4 && resWire$wget[68];
endcase
end
always@(guard__h287260 or resWire$wget)
begin
case (guard__h287260)
2'b0, 2'b01, 2'b10:
CASE_guard87260_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149 =
!resWire$wget[68];
2'd3:
CASE_guard87260_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149 =
guard__h287260 != 2'b11 || !resWire$wget[68];
endcase
end
always@(rmdFifo$D_OUT or
resWire$wget or
CASE_guard87260_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149 or
guard__h287260)
begin
case (rmdFifo$D_OUT)
3'd0:
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324 =
CASE_guard87260_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149;
3'd1:
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324 =
(guard__h287260 == 2'b0) ?
!resWire$wget[68] :
guard__h287260 != 2'b01 && guard__h287260 != 2'b10 &&
guard__h287260 != 2'b11 ||
!resWire$wget[68];
3'd2, 3'd3:
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324 =
!resWire$wget[68];
default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324 =
rmdFifo$D_OUT != 3'd4 || !resWire$wget[68];
endcase
end
always@(guard__h296096 or resWire$wget)
begin
case (guard__h296096)
2'b0, 2'b01, 2'b10:
CASE_guard96096_0b0_resWirewget_BIT_68_0b1_re_ETC__q150 =
resWire$wget[68];
2'd3:
CASE_guard96096_0b0_resWirewget_BIT_68_0b1_re_ETC__q150 =
guard__h296096 == 2'b11 && resWire$wget[68];
endcase
end
always@(rmdFifo$D_OUT or
resWire$wget or
CASE_guard96096_0b0_resWirewget_BIT_68_0b1_re_ETC__q150 or
guard__h296096)
begin
case (rmdFifo$D_OUT)
3'd0:
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418 =
CASE_guard96096_0b0_resWirewget_BIT_68_0b1_re_ETC__q150;
3'd1:
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418 =
(guard__h296096 == 2'b0) ?
resWire$wget[68] :
(guard__h296096 == 2'b01 || guard__h296096 == 2'b10 ||
guard__h296096 == 2'b11) &&
resWire$wget[68];
3'd2, 3'd3:
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418 =
resWire$wget[68];
default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418 =
rmdFifo$D_OUT == 3'd4 && resWire$wget[68];
endcase
end
always@(guard__h296096 or resWire$wget)
begin
case (guard__h296096)
2'b0, 2'b01, 2'b10:
CASE_guard96096_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151 =
!resWire$wget[68];
2'd3:
CASE_guard96096_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151 =
guard__h296096 != 2'b11 || !resWire$wget[68];
endcase
end
always@(rmdFifo$D_OUT or
resWire$wget or
CASE_guard96096_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151 or
guard__h296096)
begin
case (rmdFifo$D_OUT)
3'd0:
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373 =
CASE_guard96096_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151;
3'd1:
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373 =
(guard__h296096 == 2'b0) ?
!resWire$wget[68] :
guard__h296096 != 2'b01 && guard__h296096 != 2'b10 &&
guard__h296096 != 2'b11 ||
!resWire$wget[68];
3'd2, 3'd3:
IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373 =
!resWire$wget[68];
default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373 =
rmdFifo$D_OUT != 3'd4 || !resWire$wget[68];
endcase
end
always@(rmdFifo$D_OUT or resWire$wget)
begin
case (rmdFifo$D_OUT)
3'd0, 3'd1, 3'd2, 3'd3:
IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400 =
resWire$wget[68];
default: IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400 =
rmdFifo$D_OUT == 3'd4 && resWire$wget[68];
endcase
end
always@(rmdFifo$D_OUT or resWire$wget)
begin
case (rmdFifo$D_OUT)
3'd0, 3'd1, 3'd2, 3'd3:
IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028 =
!resWire$wget[68];
default: IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028 =
rmdFifo$D_OUT != 3'd4 || !resWire$wget[68];
endcase
end
always@(guard__h278330 or
_theResult___fst_exp__h286378 or
out_exp__h286823 or _theResult___exp__h286820)
begin
case (guard__h278330)
2'b0, 2'b01:
CASE_guard78330_0b0_theResult___fst_exp86378_0_ETC__q152 =
_theResult___fst_exp__h286378;
2'b10:
CASE_guard78330_0b0_theResult___fst_exp86378_0_ETC__q152 =
out_exp__h286823;
2'b11:
CASE_guard78330_0b0_theResult___fst_exp86378_0_ETC__q152 =
_theResult___exp__h286820;
endcase
end
always@(guard__h278330 or
_theResult___fst_exp__h286378 or _theResult___exp__h286820)
begin
case (guard__h278330)
2'b0:
CASE_guard78330_0b0_theResult___fst_exp86378_0_ETC__q153 =
_theResult___fst_exp__h286378;
2'b01, 2'b10, 2'b11:
CASE_guard78330_0b0_theResult___fst_exp86378_0_ETC__q153 =
_theResult___exp__h286820;
endcase
end
always@(rmdFifo$D_OUT or
CASE_guard78330_0b0_theResult___fst_exp86378_0_ETC__q152 or
CASE_guard78330_0b0_theResult___fst_exp86378_0_ETC__q153 or
IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6479 or
IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6481 or
_theResult___fst_exp__h286378)
begin
case (rmdFifo$D_OUT)
3'd0:
_theResult___fst_exp__h286898 =
CASE_guard78330_0b0_theResult___fst_exp86378_0_ETC__q152;
3'd1:
_theResult___fst_exp__h286898 =
CASE_guard78330_0b0_theResult___fst_exp86378_0_ETC__q153;
3'd2:
_theResult___fst_exp__h286898 =
IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6479;
3'd3:
_theResult___fst_exp__h286898 =
IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6481;
3'd4: _theResult___fst_exp__h286898 = _theResult___fst_exp__h286378;
default: _theResult___fst_exp__h286898 = 8'd0;
endcase
end
always@(guard__h269623 or
_theResult___fst_exp__h277722 or
out_exp__h278241 or _theResult___exp__h278238)
begin
case (guard__h269623)
2'b0, 2'b01:
CASE_guard69623_0b0_theResult___fst_exp77722_0_ETC__q154 =
_theResult___fst_exp__h277722;
2'b10:
CASE_guard69623_0b0_theResult___fst_exp77722_0_ETC__q154 =
out_exp__h278241;
2'b11:
CASE_guard69623_0b0_theResult___fst_exp77722_0_ETC__q154 =
_theResult___exp__h278238;
endcase
end
always@(guard__h269623 or
_theResult___fst_exp__h277722 or _theResult___exp__h278238)
begin
case (guard__h269623)
2'b0:
CASE_guard69623_0b0_theResult___fst_exp77722_0_ETC__q155 =
_theResult___fst_exp__h277722;
2'b01, 2'b10, 2'b11:
CASE_guard69623_0b0_theResult___fst_exp77722_0_ETC__q155 =
_theResult___exp__h278238;
endcase
end
always@(rmdFifo$D_OUT or
CASE_guard69623_0b0_theResult___fst_exp77722_0_ETC__q154 or
CASE_guard69623_0b0_theResult___fst_exp77722_0_ETC__q155 or
IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6448 or
IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6450 or
_theResult___fst_exp__h277722)
begin
case (rmdFifo$D_OUT)
3'd0:
_theResult___fst_exp__h278316 =
CASE_guard69623_0b0_theResult___fst_exp77722_0_ETC__q154;
3'd1:
_theResult___fst_exp__h278316 =
CASE_guard69623_0b0_theResult___fst_exp77722_0_ETC__q155;
3'd2:
_theResult___fst_exp__h278316 =
IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6448;
3'd3:
_theResult___fst_exp__h278316 =
IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6450;
3'd4: _theResult___fst_exp__h278316 = _theResult___fst_exp__h277722;
default: _theResult___fst_exp__h278316 = 8'd0;
endcase
end
always@(guard__h287260 or
_theResult___fst_exp__h295488 or
out_exp__h296007 or _theResult___exp__h296004)
begin
case (guard__h287260)
2'b0, 2'b01:
CASE_guard87260_0b0_theResult___fst_exp95488_0_ETC__q156 =
_theResult___fst_exp__h295488;
2'b10:
CASE_guard87260_0b0_theResult___fst_exp95488_0_ETC__q156 =
out_exp__h296007;
2'b11:
CASE_guard87260_0b0_theResult___fst_exp95488_0_ETC__q156 =
_theResult___exp__h296004;
endcase
end
always@(guard__h287260 or
_theResult___fst_exp__h295488 or _theResult___exp__h296004)
begin
case (guard__h287260)
2'b0:
CASE_guard87260_0b0_theResult___fst_exp95488_0_ETC__q157 =
_theResult___fst_exp__h295488;
2'b01, 2'b10, 2'b11:
CASE_guard87260_0b0_theResult___fst_exp95488_0_ETC__q157 =
_theResult___exp__h296004;
endcase
end
always@(rmdFifo$D_OUT or
CASE_guard87260_0b0_theResult___fst_exp95488_0_ETC__q156 or
CASE_guard87260_0b0_theResult___fst_exp95488_0_ETC__q157 or
IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6518 or
IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6520 or
_theResult___fst_exp__h295488)
begin
case (rmdFifo$D_OUT)
3'd0:
_theResult___fst_exp__h296082 =
CASE_guard87260_0b0_theResult___fst_exp95488_0_ETC__q156;
3'd1:
_theResult___fst_exp__h296082 =
CASE_guard87260_0b0_theResult___fst_exp95488_0_ETC__q157;
3'd2:
_theResult___fst_exp__h296082 =
IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6518;
3'd3:
_theResult___fst_exp__h296082 =
IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6520;
3'd4: _theResult___fst_exp__h296082 = _theResult___fst_exp__h295488;
default: _theResult___fst_exp__h296082 = 8'd0;
endcase
end
always@(guard__h296096 or
_theResult___fst_exp__h304173 or
out_exp__h304643 or _theResult___exp__h304640)
begin
case (guard__h296096)
2'b0, 2'b01:
CASE_guard96096_0b0_theResult___fst_exp04173_0_ETC__q158 =
_theResult___fst_exp__h304173;
2'b10:
CASE_guard96096_0b0_theResult___fst_exp04173_0_ETC__q158 =
out_exp__h304643;
2'b11:
CASE_guard96096_0b0_theResult___fst_exp04173_0_ETC__q158 =
_theResult___exp__h304640;
endcase
end
always@(guard__h296096 or
_theResult___fst_exp__h304173 or _theResult___exp__h304640)
begin
case (guard__h296096)
2'b0:
CASE_guard96096_0b0_theResult___fst_exp04173_0_ETC__q159 =
_theResult___fst_exp__h304173;
2'b01, 2'b10, 2'b11:
CASE_guard96096_0b0_theResult___fst_exp04173_0_ETC__q159 =
_theResult___exp__h304640;
endcase
end
always@(rmdFifo$D_OUT or
CASE_guard96096_0b0_theResult___fst_exp04173_0_ETC__q158 or
CASE_guard96096_0b0_theResult___fst_exp04173_0_ETC__q159 or
IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6549 or
IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6551 or
_theResult___fst_exp__h304173)
begin
case (rmdFifo$D_OUT)
3'd0:
_theResult___fst_exp__h304718 =
CASE_guard96096_0b0_theResult___fst_exp04173_0_ETC__q158;
3'd1:
_theResult___fst_exp__h304718 =
CASE_guard96096_0b0_theResult___fst_exp04173_0_ETC__q159;
3'd2:
_theResult___fst_exp__h304718 =
IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6549;
3'd3:
_theResult___fst_exp__h304718 =
IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6551;
3'd4: _theResult___fst_exp__h304718 = _theResult___fst_exp__h304173;
default: _theResult___fst_exp__h304718 = 8'd0;
endcase
end
always@(guard__h278330 or
_theResult___snd__h286329 or
out_sfd__h286824 or _theResult___sfd__h286821)
begin
case (guard__h278330)
2'b0, 2'b01:
CASE_guard78330_0b0_theResult___snd86329_BITS__ETC__q160 =
_theResult___snd__h286329[56:34];
2'b10:
CASE_guard78330_0b0_theResult___snd86329_BITS__ETC__q160 =
out_sfd__h286824;
2'b11:
CASE_guard78330_0b0_theResult___snd86329_BITS__ETC__q160 =
_theResult___sfd__h286821;
endcase
end
always@(guard__h278330 or
_theResult___snd__h286329 or _theResult___sfd__h286821)
begin
case (guard__h278330)
2'b0:
CASE_guard78330_0b0_theResult___snd86329_BITS__ETC__q161 =
_theResult___snd__h286329[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard78330_0b0_theResult___snd86329_BITS__ETC__q161 =
_theResult___sfd__h286821;
endcase
end
always@(rmdFifo$D_OUT or
CASE_guard78330_0b0_theResult___snd86329_BITS__ETC__q160 or
CASE_guard78330_0b0_theResult___snd86329_BITS__ETC__q161 or
IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6595 or
IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6597 or
_theResult___snd__h286329)
begin
case (rmdFifo$D_OUT)
3'd0:
_theResult___fst_sfd__h286899 =
CASE_guard78330_0b0_theResult___snd86329_BITS__ETC__q160;
3'd1:
_theResult___fst_sfd__h286899 =
CASE_guard78330_0b0_theResult___snd86329_BITS__ETC__q161;
3'd2:
_theResult___fst_sfd__h286899 =
IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6595;
3'd3:
_theResult___fst_sfd__h286899 =
IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6597;
3'd4: _theResult___fst_sfd__h286899 = _theResult___snd__h286329[56:34];
default: _theResult___fst_sfd__h286899 = 23'd0;
endcase
end
always@(guard__h269623 or
sfdin__h277716 or out_sfd__h278242 or _theResult___sfd__h278239)
begin
case (guard__h269623)
2'b0, 2'b01:
CASE_guard69623_0b0_sfdin77716_BITS_56_TO_34_0_ETC__q162 =
sfdin__h277716[56:34];
2'b10:
CASE_guard69623_0b0_sfdin77716_BITS_56_TO_34_0_ETC__q162 =
out_sfd__h278242;
2'b11:
CASE_guard69623_0b0_sfdin77716_BITS_56_TO_34_0_ETC__q162 =
_theResult___sfd__h278239;
endcase
end
always@(guard__h269623 or sfdin__h277716 or _theResult___sfd__h278239)
begin
case (guard__h269623)
2'b0:
CASE_guard69623_0b0_sfdin77716_BITS_56_TO_34_0_ETC__q163 =
sfdin__h277716[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard69623_0b0_sfdin77716_BITS_56_TO_34_0_ETC__q163 =
_theResult___sfd__h278239;
endcase
end
always@(rmdFifo$D_OUT or
CASE_guard69623_0b0_sfdin77716_BITS_56_TO_34_0_ETC__q162 or
CASE_guard69623_0b0_sfdin77716_BITS_56_TO_34_0_ETC__q163 or
IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6576 or
IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6578 or
sfdin__h277716)
begin
case (rmdFifo$D_OUT)
3'd0:
_theResult___fst_sfd__h278317 =
CASE_guard69623_0b0_sfdin77716_BITS_56_TO_34_0_ETC__q162;
3'd1:
_theResult___fst_sfd__h278317 =
CASE_guard69623_0b0_sfdin77716_BITS_56_TO_34_0_ETC__q163;
3'd2:
_theResult___fst_sfd__h278317 =
IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6576;
3'd3:
_theResult___fst_sfd__h278317 =
IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6578;
3'd4: _theResult___fst_sfd__h278317 = sfdin__h277716[56:34];
default: _theResult___fst_sfd__h278317 = 23'd0;
endcase
end
always@(guard__h287260 or
sfdin__h295482 or out_sfd__h296008 or _theResult___sfd__h296005)
begin
case (guard__h287260)
2'b0, 2'b01:
CASE_guard87260_0b0_sfdin95482_BITS_56_TO_34_0_ETC__q164 =
sfdin__h295482[56:34];
2'b10:
CASE_guard87260_0b0_sfdin95482_BITS_56_TO_34_0_ETC__q164 =
out_sfd__h296008;
2'b11:
CASE_guard87260_0b0_sfdin95482_BITS_56_TO_34_0_ETC__q164 =
_theResult___sfd__h296005;
endcase
end
always@(guard__h287260 or sfdin__h295482 or _theResult___sfd__h296005)
begin
case (guard__h287260)
2'b0:
CASE_guard87260_0b0_sfdin95482_BITS_56_TO_34_0_ETC__q165 =
sfdin__h295482[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard87260_0b0_sfdin95482_BITS_56_TO_34_0_ETC__q165 =
_theResult___sfd__h296005;
endcase
end
always@(rmdFifo$D_OUT or
CASE_guard87260_0b0_sfdin95482_BITS_56_TO_34_0_ETC__q164 or
CASE_guard87260_0b0_sfdin95482_BITS_56_TO_34_0_ETC__q165 or
IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6622 or
IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6624 or
sfdin__h295482)
begin
case (rmdFifo$D_OUT)
3'd0:
_theResult___fst_sfd__h296083 =
CASE_guard87260_0b0_sfdin95482_BITS_56_TO_34_0_ETC__q164;
3'd1:
_theResult___fst_sfd__h296083 =
CASE_guard87260_0b0_sfdin95482_BITS_56_TO_34_0_ETC__q165;
3'd2:
_theResult___fst_sfd__h296083 =
IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6622;
3'd3:
_theResult___fst_sfd__h296083 =
IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6624;
3'd4: _theResult___fst_sfd__h296083 = sfdin__h295482[56:34];
default: _theResult___fst_sfd__h296083 = 23'd0;
endcase
end
always@(guard__h296096 or
_theResult___snd__h304119 or
out_sfd__h304644 or _theResult___sfd__h304641)
begin
case (guard__h296096)
2'b0, 2'b01:
CASE_guard96096_0b0_theResult___snd04119_BITS__ETC__q166 =
_theResult___snd__h304119[56:34];
2'b10:
CASE_guard96096_0b0_theResult___snd04119_BITS__ETC__q166 =
out_sfd__h304644;
2'b11:
CASE_guard96096_0b0_theResult___snd04119_BITS__ETC__q166 =
_theResult___sfd__h304641;
endcase
end
always@(guard__h296096 or
_theResult___snd__h304119 or _theResult___sfd__h304641)
begin
case (guard__h296096)
2'b0:
CASE_guard96096_0b0_theResult___snd04119_BITS__ETC__q167 =
_theResult___snd__h304119[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard96096_0b0_theResult___snd04119_BITS__ETC__q167 =
_theResult___sfd__h304641;
endcase
end
always@(rmdFifo$D_OUT or
CASE_guard96096_0b0_theResult___snd04119_BITS__ETC__q166 or
CASE_guard96096_0b0_theResult___snd04119_BITS__ETC__q167 or
IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6641 or
IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6643 or
_theResult___snd__h304119)
begin
case (rmdFifo$D_OUT)
3'd0:
_theResult___fst_sfd__h304719 =
CASE_guard96096_0b0_theResult___snd04119_BITS__ETC__q166;
3'd1:
_theResult___fst_sfd__h304719 =
CASE_guard96096_0b0_theResult___snd04119_BITS__ETC__q167;
3'd2:
_theResult___fst_sfd__h304719 =
IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6641;
3'd3:
_theResult___fst_sfd__h304719 =
IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6643;
3'd4: _theResult___fst_sfd__h304719 = _theResult___snd__h304119[56:34];
default: _theResult___fst_sfd__h304719 = 23'd0;
endcase
end
always@(fpu_div_fState_S4$D_OUT)
begin
case (fpu_div_fState_S4$D_OUT[68:66])
3'd2, 3'd3:
CASE_fpu_div_fState_S4D_OUT_BITS_68_TO_66_2_f_ETC__q168 =
fpu_div_fState_S4$D_OUT[65];
default: CASE_fpu_div_fState_S4D_OUT_BITS_68_TO_66_2_f_ETC__q168 =
fpu_div_fState_S4$D_OUT[68:66] == 3'd4 &&
fpu_div_fState_S4$D_OUT[65];
endcase
end
always@(fpu_div_fState_S4$D_OUT or
IF_0b0_CONCAT_NOT_fpu_div_fState_S4_first__73__ETC___d910)
begin
case (fpu_div_fState_S4$D_OUT[68:66])
3'd2:
CASE_fpu_div_fState_S4D_OUT_BITS_68_TO_66_2_I_ETC__q169 =
(fpu_div_fState_S4$D_OUT[1:0] == 2'b0 ||
fpu_div_fState_S4$D_OUT[65]) ?
fpu_div_fState_S4$D_OUT[64:2] :
IF_0b0_CONCAT_NOT_fpu_div_fState_S4_first__73__ETC___d910;
3'd3:
CASE_fpu_div_fState_S4D_OUT_BITS_68_TO_66_2_I_ETC__q169 =
(fpu_div_fState_S4$D_OUT[1:0] == 2'b0) ?
fpu_div_fState_S4$D_OUT[64:2] :
(fpu_div_fState_S4$D_OUT[65] ?
IF_0b0_CONCAT_NOT_fpu_div_fState_S4_first__73__ETC___d910 :
fpu_div_fState_S4$D_OUT[64:2]);
3'd4:
CASE_fpu_div_fState_S4D_OUT_BITS_68_TO_66_2_I_ETC__q169 =
fpu_div_fState_S4$D_OUT[64:2];
default: CASE_fpu_div_fState_S4D_OUT_BITS_68_TO_66_2_I_ETC__q169 =
63'd0;
endcase
end
always@(fpu_div_fState_S4$D_OUT)
begin
case (fpu_div_fState_S4$D_OUT[1:0])
2'b0, 2'b01, 2'b10:
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q170 =
fpu_div_fState_S4$D_OUT[65];
2'd3:
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q170 =
fpu_div_fState_S4$D_OUT[1:0] == 2'b11 &&
fpu_div_fState_S4$D_OUT[65];
endcase
end
always@(fpu_div_fState_S4$D_OUT or
IF_0b0_CONCAT_NOT_fpu_div_fState_S4_first__73__ETC___d910)
begin
case (fpu_div_fState_S4$D_OUT[1:0])
2'b0, 2'b01:
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q171 =
fpu_div_fState_S4$D_OUT[64:2];
2'b10:
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q171 =
fpu_div_fState_S4$D_OUT[2] ?
IF_0b0_CONCAT_NOT_fpu_div_fState_S4_first__73__ETC___d910 :
fpu_div_fState_S4$D_OUT[64:2];
2'b11:
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q171 =
IF_0b0_CONCAT_NOT_fpu_div_fState_S4_first__73__ETC___d910;
endcase
end
always@(fpu_div_fState_S4$D_OUT or
IF_0b0_CONCAT_NOT_fpu_div_fState_S4_first__73__ETC___d910)
begin
case (fpu_div_fState_S4$D_OUT[1:0])
2'd0: CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0_0_0_ETC__q172 = 63'd0;
2'b01, 2'b10, 2'b11:
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0_0_0_ETC__q172 =
IF_0b0_CONCAT_NOT_fpu_div_fState_S4_first__73__ETC___d910;
endcase
end
always@(fpu_div_fState_S4$D_OUT or
CASE_fpu_div_fState_S4D_OUT_BITS_68_TO_66_2_f_ETC__q168 or
CASE_fpu_div_fState_S4D_OUT_BITS_68_TO_66_2_I_ETC__q169 or
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q170 or
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q171 or
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0_0_0_ETC__q172)
begin
case (fpu_div_fState_S4$D_OUT[68:66])
3'd0:
CASE_fpu_div_fState_S4D_OUT_BITS_68_TO_66_0_C_ETC__q173 =
{ CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q170,
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q171 };
3'd1:
CASE_fpu_div_fState_S4D_OUT_BITS_68_TO_66_0_C_ETC__q173 =
(fpu_div_fState_S4$D_OUT[1:0] == 2'b0) ?
fpu_div_fState_S4$D_OUT[65:2] :
{ (fpu_div_fState_S4$D_OUT[1:0] == 2'b01 ||
fpu_div_fState_S4$D_OUT[1:0] == 2'b10 ||
fpu_div_fState_S4$D_OUT[1:0] == 2'b11) &&
fpu_div_fState_S4$D_OUT[65],
CASE_fpu_div_fState_S4D_OUT_BITS_1_TO_0_0_0_0_ETC__q172 };
default: CASE_fpu_div_fState_S4D_OUT_BITS_68_TO_66_0_C_ETC__q173 =
{ CASE_fpu_div_fState_S4D_OUT_BITS_68_TO_66_2_f_ETC__q168,
CASE_fpu_div_fState_S4D_OUT_BITS_68_TO_66_2_I_ETC__q169 };
endcase
end
always@(fpu_div_fState_S3$D_OUT)
begin
case (fpu_div_fState_S3$D_OUT[124:122])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_fpu_div_fState_S3D_OUT_BITS_124_TO_122_0_ETC__q174 =
fpu_div_fState_S3$D_OUT[121];
default: CASE_fpu_div_fState_S3D_OUT_BITS_124_TO_122_0_ETC__q174 =
fpu_div_fState_S3$D_OUT[124:122] == 3'd4 &&
fpu_div_fState_S3$D_OUT[121];
endcase
end
always@(fpu_div_fState_S3$D_OUT)
begin
case (fpu_div_fState_S3$D_OUT[124:122])
3'd0, 3'd1:
CASE_fpu_div_fState_S3D_OUT_BITS_124_TO_122_0_ETC__q175 =
63'h7FF0000000000000;
3'd2:
CASE_fpu_div_fState_S3D_OUT_BITS_124_TO_122_0_ETC__q175 =
fpu_div_fState_S3$D_OUT[121] ?
63'h7FEFFFFFFFFFFFFF :
63'h7FF0000000000000;
3'd3:
CASE_fpu_div_fState_S3D_OUT_BITS_124_TO_122_0_ETC__q175 =
fpu_div_fState_S3$D_OUT[121] ?
63'h7FF0000000000000 :
63'h7FEFFFFFFFFFFFFF;
3'd4:
CASE_fpu_div_fState_S3D_OUT_BITS_124_TO_122_0_ETC__q175 =
63'h7FEFFFFFFFFFFFFF;
default: CASE_fpu_div_fState_S3D_OUT_BITS_124_TO_122_0_ETC__q175 =
63'd0;
endcase
end
always@(iFifo$D_OUT or
IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848 or
IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330 or
IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5378)
begin
case (iFifo$D_OUT[3:0])
4'd0:
CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176 =
IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330;
4'd1:
CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176 =
iFifo$D_OUT[136] ?
IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5378 :
{ iFifo$D_OUT[136] || !iFifo$D_OUT[135],
iFifo$D_OUT[134:72] };
default: CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176 =
IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848;
endcase
end
always@(iFifo$D_OUT or
IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330)
begin
case (iFifo$D_OUT[3:0])
4'd0, 4'd1:
CASE_iFifoD_OUT_BITS_3_TO_0_0_460718241880001_ETC__q177 =
64'h3FF0000000000000;
default: CASE_iFifoD_OUT_BITS_3_TO_0_0_460718241880001_ETC__q177 =
IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330;
endcase
end
always@(fpu_sqr_fState_S4$D_OUT)
begin
case (fpu_sqr_fState_S4$D_OUT[68:66])
3'd2, 3'd3:
CASE_fpu_sqr_fState_S4D_OUT_BITS_68_TO_66_2_f_ETC__q178 =
fpu_sqr_fState_S4$D_OUT[65];
default: CASE_fpu_sqr_fState_S4D_OUT_BITS_68_TO_66_2_f_ETC__q178 =
fpu_sqr_fState_S4$D_OUT[68:66] == 3'd4 &&
fpu_sqr_fState_S4$D_OUT[65];
endcase
end
always@(fpu_sqr_fState_S4$D_OUT or
IF_0b0_CONCAT_NOT_fpu_sqr_fState_S4_first__687_ETC___d1724)
begin
case (fpu_sqr_fState_S4$D_OUT[68:66])
3'd2:
CASE_fpu_sqr_fState_S4D_OUT_BITS_68_TO_66_2_I_ETC__q179 =
(fpu_sqr_fState_S4$D_OUT[1:0] == 2'b0 ||
fpu_sqr_fState_S4$D_OUT[65]) ?
fpu_sqr_fState_S4$D_OUT[64:2] :
IF_0b0_CONCAT_NOT_fpu_sqr_fState_S4_first__687_ETC___d1724;
3'd3:
CASE_fpu_sqr_fState_S4D_OUT_BITS_68_TO_66_2_I_ETC__q179 =
(fpu_sqr_fState_S4$D_OUT[1:0] == 2'b0) ?
fpu_sqr_fState_S4$D_OUT[64:2] :
(fpu_sqr_fState_S4$D_OUT[65] ?
IF_0b0_CONCAT_NOT_fpu_sqr_fState_S4_first__687_ETC___d1724 :
fpu_sqr_fState_S4$D_OUT[64:2]);
3'd4:
CASE_fpu_sqr_fState_S4D_OUT_BITS_68_TO_66_2_I_ETC__q179 =
fpu_sqr_fState_S4$D_OUT[64:2];
default: CASE_fpu_sqr_fState_S4D_OUT_BITS_68_TO_66_2_I_ETC__q179 =
63'd0;
endcase
end
always@(fpu_sqr_fState_S4$D_OUT)
begin
case (fpu_sqr_fState_S4$D_OUT[1:0])
2'b0, 2'b01, 2'b10:
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q180 =
fpu_sqr_fState_S4$D_OUT[65];
2'd3:
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q180 =
fpu_sqr_fState_S4$D_OUT[1:0] == 2'b11 &&
fpu_sqr_fState_S4$D_OUT[65];
endcase
end
always@(fpu_sqr_fState_S4$D_OUT or
IF_0b0_CONCAT_NOT_fpu_sqr_fState_S4_first__687_ETC___d1724)
begin
case (fpu_sqr_fState_S4$D_OUT[1:0])
2'b0, 2'b01:
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q181 =
fpu_sqr_fState_S4$D_OUT[64:2];
2'b10:
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q181 =
fpu_sqr_fState_S4$D_OUT[2] ?
IF_0b0_CONCAT_NOT_fpu_sqr_fState_S4_first__687_ETC___d1724 :
fpu_sqr_fState_S4$D_OUT[64:2];
2'b11:
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q181 =
IF_0b0_CONCAT_NOT_fpu_sqr_fState_S4_first__687_ETC___d1724;
endcase
end
always@(fpu_sqr_fState_S4$D_OUT or
IF_0b0_CONCAT_NOT_fpu_sqr_fState_S4_first__687_ETC___d1724)
begin
case (fpu_sqr_fState_S4$D_OUT[1:0])
2'd0: CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0_0_0_ETC__q182 = 63'd0;
2'b01, 2'b10, 2'b11:
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0_0_0_ETC__q182 =
IF_0b0_CONCAT_NOT_fpu_sqr_fState_S4_first__687_ETC___d1724;
endcase
end
always@(fpu_sqr_fState_S4$D_OUT or
CASE_fpu_sqr_fState_S4D_OUT_BITS_68_TO_66_2_f_ETC__q178 or
CASE_fpu_sqr_fState_S4D_OUT_BITS_68_TO_66_2_I_ETC__q179 or
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q180 or
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q181 or
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0_0_0_ETC__q182)
begin
case (fpu_sqr_fState_S4$D_OUT[68:66])
3'd0:
CASE_fpu_sqr_fState_S4D_OUT_BITS_68_TO_66_0_C_ETC__q183 =
{ CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q180,
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0b0_f_ETC__q181 };
3'd1:
CASE_fpu_sqr_fState_S4D_OUT_BITS_68_TO_66_0_C_ETC__q183 =
(fpu_sqr_fState_S4$D_OUT[1:0] == 2'b0) ?
fpu_sqr_fState_S4$D_OUT[65:2] :
{ (fpu_sqr_fState_S4$D_OUT[1:0] == 2'b01 ||
fpu_sqr_fState_S4$D_OUT[1:0] == 2'b10 ||
fpu_sqr_fState_S4$D_OUT[1:0] == 2'b11) &&
fpu_sqr_fState_S4$D_OUT[65],
CASE_fpu_sqr_fState_S4D_OUT_BITS_1_TO_0_0_0_0_ETC__q182 };
default: CASE_fpu_sqr_fState_S4D_OUT_BITS_68_TO_66_0_C_ETC__q183 =
{ CASE_fpu_sqr_fState_S4D_OUT_BITS_68_TO_66_2_f_ETC__q178,
CASE_fpu_sqr_fState_S4D_OUT_BITS_68_TO_66_2_I_ETC__q179 };
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
crg_done <= `BSV_ASSIGNMENT_DELAY 1'd0;
crg_done_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_busy <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_busy_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (crg_done$EN) crg_done <= `BSV_ASSIGNMENT_DELAY crg_done$D_IN;
if (crg_done_1$EN)
crg_done_1 <= `BSV_ASSIGNMENT_DELAY crg_done_1$D_IN;
if (rg_busy$EN) rg_busy <= `BSV_ASSIGNMENT_DELAY rg_busy$D_IN;
if (rg_busy_1$EN) rg_busy_1 <= `BSV_ASSIGNMENT_DELAY rg_busy_1$D_IN;
end
if (rg_b$EN) rg_b <= `BSV_ASSIGNMENT_DELAY rg_b$D_IN;
if (rg_d$EN) rg_d <= `BSV_ASSIGNMENT_DELAY rg_d$D_IN;
if (rg_index$EN) rg_index <= `BSV_ASSIGNMENT_DELAY rg_index$D_IN;
if (rg_index_1$EN) rg_index_1 <= `BSV_ASSIGNMENT_DELAY rg_index_1$D_IN;
if (rg_q$EN) rg_q <= `BSV_ASSIGNMENT_DELAY rg_q$D_IN;
if (rg_r$EN) rg_r <= `BSV_ASSIGNMENT_DELAY rg_r$D_IN;
if (rg_r_1$EN) rg_r_1 <= `BSV_ASSIGNMENT_DELAY rg_r_1$D_IN;
if (rg_res$EN) rg_res <= `BSV_ASSIGNMENT_DELAY rg_res$D_IN;
if (rg_s$EN) rg_s <= `BSV_ASSIGNMENT_DELAY rg_s$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
crg_done = 1'h0;
crg_done_1 = 1'h0;
rg_b = 116'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
rg_busy = 1'h0;
rg_busy_1 = 1'h0;
rg_d = 58'h2AAAAAAAAAAAAAA;
rg_index = 6'h2A;
rg_index_1 = 6'h2A;
rg_q = 58'h2AAAAAAAAAAAAAA;
rg_r = 116'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
rg_r_1 = 116'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
rg_res = 117'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
rg_s = 116'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (fpu_madd_fResult_S9$EMPTY_N && fpu_div_fResult_S5$EMPTY_N)
$display("Error: \"../../src_Core/CPU/FPU.bsv\", line 152, column 15: (R0001)\n Mutually exclusive rules (from the ME sets [RL_getResFromPipe] and\n [RL_getResFromPipe_1] ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if ((fpu_madd_fResult_S9$EMPTY_N || fpu_div_fResult_S5$EMPTY_N) &&
fpu_sqr_fResult_S5$EMPTY_N)
$display("Error: \"../../src_Core/CPU/FPU.bsv\", line 152, column 15: (R0001)\n Mutually exclusive rules (from the ME sets [RL_getResFromPipe,\n RL_getResFromPipe_1] and [RL_getResFromPipe_2] ) fired in the same clock\n cycle.\n");
end
// synopsys translate_on
endmodule // mkFPU
|
Require Import Algebra OwnTacts Equal.
(* Natural numbers is is the simplest inductive type. *)
(* For a type to be natural numbers is has to have the following properties (The Peano Axioms) : *)
(* 1 : forall n in N, *)
(* There should exists a successor 'Succ' to n. (n + 1) *)
(* 2 : forall n, m in N, *)
(* If n and m is different, their successors should be different. *)
(* 3 : There should exist a element, which is not the successor of anything, denoted 'ZERO'. *)
(* 4 : For a property P, if 'P n' is true for 'ZERO' and for an element 'a' in N, then it implies that *)
(* that the successor of 'a' is also true, then 'P n' is true. Which is exactly the 'Induction principle'! *)
(* And actually what we are doing when we prove theorems about natural numbers, is to construct the *)
(* 'Induction Tree' for natural numbers: *)
(* P (ZERO) forall n in N, P (n) -> P (Succ n) *)
(* ============================================== *)
(* P n *)
(* So we have a very strong relation between Natural Numbers and Induction and Induction and Recursion *)
(* is intertwined, so inductive types are ideal for recursive functions. *)
Inductive Nat : Set :=
| ZERO : Nat (* Base case *)
| Succ : Nat -> Nat. (* Inductive case *)
(* As always, we need a way of telling if elements are equal. *)
(* This is our first recursive function, when working with recursive data structures in Coq *)
(* We use a fixpoint, which is able to call itself, compared to a definition which cannot. *)
Fixpoint eq_Nat (n m : Nat) : Prop :=
match n, m with
| ZERO , ZERO => True
| Succ n', ZERO => False
| ZERO , Succ m' => False
| Succ n', Succ m' => eq_Nat n' m'
end.
Notation "A =N= B" := (eq_Nat A B) (at level 70, no associativity).
Lemma eq_Nat_ZERO_ZERO :
ZERO =N= ZERO.
Proof.
unfold eq_Nat.
exact I.
Qed.
Lemma eq_Nat_Succ_ZERO :
forall n : Nat,
not (Succ n =N= ZERO).
Proof.
intro n.
unfold not.
intro H.
unfold eq_Nat in H.
contradiction H.
Qed.
Lemma eq_Nat_ZERO_Succ :
forall m : Nat,
not (ZERO =N= Succ m).
Proof.
intro n.
unfold not.
intro H.
unfold eq_Nat in H.
contradiction H.
Qed.
Lemma eq_Nat_Succ_Succ :
forall n m : Nat,
eq_Nat n m <-> eq_Nat (Succ n) (Succ m) .
Proof.
intros n m.
unfold eq_Nat.
fold eq_Nat.
split.
intro H.
exact H.
intro H.
exact H.
Qed.
Lemma eq_Nat_is_reflexive :
Reflexive Nat eq_Nat.
Proof.
unfold Reflexive.
intro n.
induction n as [ | n' IHn']. (* Whenever we have a inductive type, we use 'induction' to reason about *)
(* the base case and inductive case of the type, assuming P n. *)
(* Base case *)
exact eq_Nat_ZERO_ZERO.
apply <- eq_Nat_Succ_Succ.
exact IHn'.
Qed.
Lemma eq_Nat_is_symmetric :
Symmetric Nat eq_Nat.
Proof.
unfold Symmetric.
intros n. (* By waiting introducing all variables, we get a stronger induction hypothesis *)
induction n as [ | n' IHn']; intros [ | m']; intro H.
exact H.
apply eq_Nat_ZERO_Succ in H.
contradiction H.
apply eq_Nat_Succ_ZERO in H.
contradiction H.
apply -> eq_Nat_Succ_Succ.
apply (IHn' m').
apply <- eq_Nat_Succ_Succ in H.
exact H.
Qed.
Lemma eq_Nat_is_transitive :
Transitive Nat eq_Nat.
Proof.
unfold Transitive.
intros n.
induction n as [ | n' IHn']; intros [ | m'] l; intros H_1 H_2.
exact H_2.
case l as [ | l'].
exact eq_Nat_ZERO_ZERO.
apply eq_Nat_ZERO_Succ in H_1.
contradiction H_1.
apply eq_Nat_Succ_ZERO in H_1.
contradiction H_1.
case l as [ | l'].
contradiction (eq_Nat_Succ_ZERO m' H_2).
apply (IHn' m' l').
apply eq_Nat_Succ_Succ in H_1.
exact H_1.
apply eq_Nat_Succ_Succ in H_2.
exact H_2.
Qed.
Theorem eq_Nat_is_a_valid_equal :
Equal Nat eq_Nat.
Proof.
unfold Equal.
split.
exact eq_Nat_is_reflexive.
split.
exact eq_Nat_is_symmetric.
exact eq_Nat_is_transitive.
Qed.
(* The addition function for natural numbers *)
Definition unit_test_addtion (candidate : Nat -> Nat -> Nat) :=
(candidate ZERO ZERO =N= ZERO) /\
(candidate (Succ ZERO) ZERO =N= Succ ZERO) /\
(candidate (Succ ZERO) (Succ ZERO) =N= Succ (Succ ZERO)).
Definition specification_of_addition (add' : Nat -> Nat -> Nat) : Prop :=
(forall m : Nat,
add' ZERO m =N= m) /\
(forall n m,
add' (Succ n) m =N= Succ (add' n m)).
Theorem specification_of_addition_is_unique :
forall add add' : Nat -> Nat -> Nat,
specification_of_addition add ->
specification_of_addition add' ->
forall n m : Nat,
add n m =N= add' n m.
Proof.
intros add add'.
unfold specification_of_addition.
intros [H_add_ZERO H_add_Succ] [H_add'_ZERO H_add'_Succ].
intro n.
induction n as [ | n' IHn ]; intro m.
apply (eq_Nat_is_transitive (add ZERO m) m (add' ZERO m)).
assert (H_add_ZERO_m := H_add_ZERO m). (* We use 'assert' to make an assertion. This time we *)
(* instantiate H_add_ZERO with the variable m. *)
exact H_add_ZERO_m.
assert (H_add'_ZERO_m := H_add'_ZERO m).
apply eq_Nat_is_symmetric in H_add'_ZERO_m.
exact H_add'_ZERO_m.
assert (H_add_Succ_n'_m := H_add_Succ n' m).
assert (H_add'_Succ_n'_m := H_add'_Succ n' m).
apply (eq_Nat_is_transitive (add (Succ n') m) (Succ (add n' m)) (add' (Succ n') m)).
exact H_add_Succ_n'_m.
apply eq_Nat_is_symmetric.
apply (eq_Nat_is_transitive (add' (Succ n') m) (Succ (add' n' m)) (Succ (add n' m))).
exact H_add'_Succ_n'_m.
apply -> eq_Nat_Succ_Succ.
apply eq_Nat_is_symmetric.
exact (IHn m).
Qed.
(* If you did not prove Booleans with eq_bool', try taking a look at it now. *)
(* TODO: Define everything self. *)
Require Import Arith.
(* Proving with the built-in nat *)
Theorem Nat_and_addition_is_a_monoid :
Monoid nat plus eq.
Proof.
unfold Monoid.
split.
unfold Neutral.
exists O.
intro n.
split.
exact (plus_0_r n).
exact (plus_0_l n).
unfold Semi_Group.
split.
exact (eq_is_a_valid_Equal nat).
unfold Associative.
exact plus_assoc.
Qed.
Theorem Nat_and_multiplication_is_a_monoid :
Monoid nat mult eq.
Proof.
unfold Monoid.
split.
unfold Neutral.
exists 1.
intro n.
split.
exact (mult_1_r n).
exact (mult_1_l n).
unfold Semi_Group.
split.
exact (eq_is_a_valid_Equal nat).
unfold Associative.
exact mult_assoc.
Qed.
Theorem Nat_and_max_is_a_monoid :
Monoid nat max eq.
Proof.
unfold Monoid.
split.
unfold Neutral.
exists 0.
intro n.
split.
exact (Max.max_0_r n).
exact (Max.max_0_l n).
unfold Semi_Group.
split.
exact (eq_is_a_valid_Equal nat).
exact Max.max_assoc.
Qed.
Proposition Nat_and_min_is_NOT_a_monoid :
not (Monoid nat min eq).
Proof.
unfold Monoid.
unfold not.
intros [H_no_neutral_element _].
unfold Neutral in H_no_neutral_element.
destruct H_no_neutral_element as [not_O H_not_neutral].
destruct (H_not_neutral (S not_O)) as [H_absurd _].
rewrite -> Min.min_r in H_absurd.
apply n_Sn in H_absurd.
contradiction.
exact (le_n_Sn not_O).
Qed.
(* Please continue with Lists *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR2B_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__OR2B_PP_BLACKBOX_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or2b (
X ,
A ,
B_N ,
VPWR,
VGND
);
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR2B_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2017/07/16 23:45:14
// Design Name:
// Module Name: top_level_sim
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top_level_sim(
);
reg clk = 0, rst = 0;
wire[31:0] base_ram_data;
wire[21:0] base_ram_addr;
wire[3:0] base_ram_be_n;
wire base_ram_ce_n;
wire base_ram_oe_n;
wire base_ram_we_n;
cpu cpu_impl(
.clk50(clk),
.rst(rst),
.sram_sramEnable_o(base_ram_ce_n),
.sram_writeEnable_o(base_ram_we_n),
.sram_readEnable_o(base_ram_oe_n),
.sram_addr_o(base_ram_addr),
.sram_data_io(base_ram_data)
);
sram SRAM(
.addr_i(base_ram_addr),
//Enable
.en_i(base_ram_ce_n),
//Write
.we_i(base_ram_we_n),
//Output
.oe_i(base_ram_oe_n),
//Data
.data_io(base_ram_data)
);
always begin
#10;
clk = ~clk;
end
always begin
#20;
rst = 1;
end
endmodule
|
/*!
* <b>Module:</b>ahci_fis_transmit
* @file ahci_fis_transmit.v
* @date 2016-01-07
* @author Andrey Filippov
*
* @brief Fetches commands, command tables, creates/sends FIS
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_fis_transmit.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ahci_fis_transmit.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*/
`timescale 1ns/1ps
module ahci_fis_transmit #(
parameter PREFETCH_ALWAYS = 0,
parameter READ_REG_LATENCY = 2, // 0 if reg_rdata is available with reg_re/reg_addr, 2 with re/regen
// parameter READ_CT_LATENCY = 1, // 0 if reg_rdata is available with reg_re/reg_addr, 2 with re/regen
parameter READ_CT_LATENCY = 2, // 0 if reg_rdata is available with reg_re/reg_addr, 2 with re/regen
parameter ADDRESS_BITS = 10 // number of memory address bits - now fixed. Low half - RO/RW/RWC,RW1 (2-cycle write), 2-nd just RW (single-cycle)
)(
input hba_rst, // @posedge mclk - when port is reset (even COMINIT)?
input mclk, // for command/status
input pcmd_st_cleared, // ~= hba_rst?
// Command pulses to execute states
input fetch_cmd, // Enter p:FetchCmd, fetch command header (from the register memory, prefetch command FIS)
// wait for either fetch_cmd_busy == 0 or pCmdToIssue ==1 after fetch_cmd
input cfis_xmit, // transmit command (wait for dma_ct_busy == 0)
input dx_xmit, // send FIS header DWORD, (just 0x46), then forward DMA data
// transmit until error, 2048DWords or pDmaXferCnt
input atapi_xmit, // trasmit ATAPI command FIS
output reg done, // for fetch_cmd - dma_start, for *_xmit - xmit_ok, xmit_err, syncesc_recv or xrdy_collision
output reg busy,
input clearCmdToIssue, // From CFIS:SUCCESS
output pCmdToIssue, // AHCI port variable
// output dmaCntrZero, // DMA counter is zero - would be a duplicate to the one in receive module and dwords_sent output
// output reg fetch_cmd_busy, // does not include prefetching CT - now just use busy/done
// Should wait for xmit_ok? Timeout? Timeout will be handled by software, so just wait for OK or some error
input xmit_ok, // FIS transmission acknowledged OK
input xmit_err, //
input syncesc_recv, // These two inputs interrupt transmit
input xrdy_collision,
output [ 2:0] dx_err, // bit 0 - syncesc_recv, 1 - R_ERR (was xmit_err), 2 - collision (valid @ xmit_err and later, reset by new command)
output [15:0] ch_prdtl, // Physical region descriptor table length (in entries, 0 is 0)
output ch_c, // Clear busy upon R_OK for this FIS
output ch_b, // Built-in self test command
output ch_r, // reset - may need to send SYNC escape before this command
output ch_p, // prefetchable - only used with non-zero PRDTL or ATAPI bit set
output ch_w, // Write: system memory -> device
output ch_a, // ATAPI: 1 means device should send PIO setup FIS for ATAPI command
output [4:0] ch_cfl, // length of the command FIS in DW, 0 means none. 0 and 1 - illegal,
// maximal is 16 (0x10)
output reg [11:0] dwords_sent, // number of DWORDs transmitted (up to 2048)
// register memory interface
output reg [ADDRESS_BITS-1:0] reg_addr,
output [ 1:0] reg_re,
input [31:0] reg_rdata,
// ahci_fis_receive interface
input [31:2] xfer_cntr, // transfer counter in words for both DMA (31 bit) and PIO (lower 15 bits), updated after decr_dwc
input xfer_cntr_zero, // transfer counter was not set
output dma_ctba_ld, // load command table address from
output dma_start, // start processing command table, reset prdbc (next cycle after dma_ctba_ld, bits prdtl valid)
output dma_dev_wr, // write to device (valid at start)
input dma_ct_busy, // dma module is busy reading command table from the system memory
// issue dma_prd_start same time as dma_start if prefetch enabled, otherwise with cfis_xmit
output reg dma_prd_start, // at or after cmd_start - enable reading PRD/data (if any) ch_prdtl should be valid, twice - OK
output reg dma_cmd_abort, // try to abort a command
// reading out command table data from DMA module
output reg [ 4:0] ct_addr, // DWORD address
output [ 1:0] ct_re, // [0] - re, [1] - regen
input [31:0] ct_data, //
// DMA (memory -> device) interface
input [31:0] dma_out, // 32-bit data from the DMA module, HBA -> device port
input dma_dav, // at least one dword is ready to be read from DMA module
output dma_re, // read dword from DMA module to the output register
input last_h2d_data,// last dword in dma_out
// Data System memory or FIS -> device
output reg [31:0] todev_data, // 32-bit data from the system memory to HBA (dma data)
output reg [ 1:0] todev_type, // 0 - data, 1 - FIS head, 2 - FIS LAST)
output todev_valid, // output register full
input todev_ready // send FIFO has room for data (>= 8? dwords)
,output [9:0] debug_01
// Add a possiblity to flush any data to FIFO if error was detected after data went there?
);
localparam CLB_OFFS32 = 'h200; // # In the second half of the register space (0x800..0xbff - 1KB)
localparam DATA_FIS = 32'h46;
reg todev_full_r;
reg dma_en_r;
wire fis_data_valid;
wire [1:0] fis_data_type;
wire [31:0] fis_data_out;
wire write_or_w;
// for fis_data_valid - longer latency
// wire fis_out_w = !dma_en_r && fis_data_valid && todev_ready;
wire dma_re_w = dma_en_r && dma_dav && todev_ready;
/// wire dma_re_w = dma_en_r && dma_dav && todev_ready && (!todev_full_r || !watch_prd_end_w);
reg [15:0] ch_prdtl_r;
reg ch_c_r;
reg ch_b_r;
reg ch_r_r;
reg ch_p_r;
reg ch_w_r;
reg ch_a_r;
reg [4:0] ch_cmd_len_r;
reg [4:0] cfis_acmd_left_r; // number of DWORDS in CFIS or ACMD area of the command table left to be fetched from ahci_dma module BRAM
// For CFIS this register is set from ch_cmd_len_r, for ACMD - from the xfer_cntr input
// (stored in the ahci_fis_receive module)
reg [4:0] cfis_acmd_left_out_r; // Same, just with latency of the data available from the ahci_dma module
// reg [31:7] ch_ctba_r;
reg [READ_REG_LATENCY:0] reg_re_r;
wire reg_re_w; // combined conditions to read register memory
/// wire reg_stb = reg_re_r[READ_REG_LATENCY];
/// wire reg_stb = reg_re_r[READ_REG_LATENCY-1];
wire pre_reg_stb = reg_re_r[READ_REG_LATENCY-1] && !reg_re_r[READ_REG_LATENCY]; // only first, to make running 1
reg [3:0] fetch_chead_r;
reg [3:0] fetch_chead_stb_r;
wire chead_done_w = fetch_chead_stb_r[2]; // done fetching command header
reg chead_bsy; // busy reading command header
reg chead_bsy_re; // busy sending read command header
reg pCmdToIssue_r;
// reg fetch_ct_r;
reg acfis_xmit_pend_r; //
reg acfis_xmit_start_r;
reg acfis_xmit_busy_r; //
// reg anc_fis_r; // This is ATAPI FIS, not Command FIS
wire acfis_xmit_start_w = (cfis_xmit || atapi_xmit || acfis_xmit_pend_r) && !dma_ct_busy && !fetch_cmd_busy_r; // dma_ct_busy no gaps with fetch_cmd_busy
wire acfis_xmit_end = ct_stb && fis_dw_last;
wire ct_re_w; // next cycle will be ct_re;
reg [READ_CT_LATENCY:0] ct_re_r;
wire ct_stb = ct_re_r[READ_CT_LATENCY];
reg fis_dw_first;
wire fis_dw_last;
reg [11:0] dx_dwords_left;
reg dx_fis_pend_r; // waiting to send first DWORD of the H2D data transfer
wire dx_dma_last_w; // sending last data word
reg dx_busy_r;
reg [ 2:0] dx_err_r;
reg xmit_ok_r;
wire any_cmd_start = fetch_cmd || cfis_xmit || dx_xmit || atapi_xmit;
// wire done_w = dx_dma_last_w || ((|dx_err_r) && dx_busy_r) || chead_done_w || acfis_xmit_end || dma_start; // done on last transmit or error
// dma_start ends 'fetch_cmd'
wire done_w = xmit_ok_r || ((|dx_err_r) && dx_busy_r) || dma_start; // done on last transmit or error
reg fetch_cmd_busy_r;
// now ahci_dma watches for the last data DWORD and generates last_h2d_data, so transmission will end if either of xfer counter or DMA data (defined by total prd size)
// if xfer_cntr wazs 0, it will never be decremented and never equal to 1, will not generate last)
// reg xfer_cntr_is_set;
// reg watch_prd_end;
// wire masked_last_h2d_data = xfer_cntr_not_set && last_h2d_data; // otherwise use xfer counter to find FIS end
// wire watch_prd_end_w = masked_last_h2d_data || watch_prd_end; // Maybe not needed - just use watch_prd_end
// reg [1:0] was_dma_re; // previous values of dma_re
// reg [2:0] was_dma_ndav; // inverted/masked previous values of dma_dav
// wire send_last_w = was_dma_ndav[2];
assign todev_valid = todev_full_r;
// assign todev_valid = todev_full_r && (!watch_prd_end_w || dma_dav || send_last_w);
assign dma_re = dma_re_w;
assign reg_re = reg_re_r[1:0];
assign ch_prdtl = ch_prdtl_r;
assign ch_c = ch_c_r;
assign ch_b = ch_b_r;
assign ch_r = ch_r_r;
assign ch_p = ch_p_r;
assign ch_w = ch_w_r;
assign ch_a = ch_a_r;
// assign ch_cfl = cfis_acmd_left_r;
assign ch_cfl = ch_cmd_len_r;
assign reg_re_w = fetch_cmd || chead_bsy_re;
assign dma_ctba_ld = fetch_chead_stb_r[2];
assign dma_start = fetch_chead_stb_r[3]; // next cycle after dma_ctba_ld
assign pCmdToIssue = pCmdToIssue_r;
// assign dmaCntrZero = dmaCntrZero_r;
assign ct_re = ct_re_r[1:0];
/// assign fis_data_valid = ct_stb; // no wait write to output register 'todev_data', ct_re_r[0] is throttled according to FIFO room availability
// What else to wait for when
assign fis_data_valid = ct_stb || (!dma_ct_busy && dx_fis_pend_r); // no wait write to output register 'todev_data', ct_re_r[0] is throttled according to FIFO room availability
/// assign ct_re_w = todev_ready && ((cfis_acmd_left_r[4:1] != 0) || (cfis_acmd_left_r[0] && !ct_re_r[0])); // Later add more sources
assign ct_re_w = todev_ready && acfis_xmit_busy_r && ((cfis_acmd_left_r[4:1] != 0) || (cfis_acmd_left_r[0] && !ct_re_r[0])); // Later add more sources
//
assign fis_dw_last = (cfis_acmd_left_out_r == 1);
assign fis_data_type = {fis_dw_last, (write_or_w && dx_fis_pend_r) | (fis_dw_first && ct_stb)};
assign fis_data_out = ({32{dx_fis_pend_r}} & DATA_FIS) | ({32{ct_stb}} & ct_data) ;
assign dx_dma_last_w = dma_en_r && dma_re_w && ((dx_dwords_left[11:0] == 1) || last_h2d_data);
assign dx_err = dx_err_r;
assign dma_dev_wr = ch_w_r;
/// assign write_or_w = (dma_en_r?(dma_dav && todev_ready ):fis_data_valid); // do not fill the buffer if FIFO is not ready for DMA,
/// assign write_or_w = (dma_en_r?(dma_dav && todev_ready && (!todev_full_r || !watch_prd_end_w)):fis_data_valid); // do not fill the buffer if FIFO is not ready for DMA,
assign write_or_w = dma_re_w || fis_data_valid;
// When watching for FIS end, do not fill/use output register in the same cycle
reg [3:0] dbg_was_ct_re_r;
reg [4:0] dbg_was_cfis_acmd_left_r;
always @ (posedge mclk) begin
// Mutliplex between DMA and FIS output to the output routed to transmit FIFO
// Count bypassing DMA dwords to generate FIS_last condition?
if (hba_rst || pcmd_st_cleared) todev_full_r <= 0;
else if (write_or_w) todev_full_r <= 1; // do not fill the buffer if FIFO is not ready
else if (todev_ready) todev_full_r <= 0;
if (write_or_w) todev_data <= dma_en_r? dma_out: fis_data_out;
if (hba_rst) todev_type <= 3; // invalid? - no, now first and last word in command FIS (impossible?)
else if (write_or_w) todev_type <= dma_en_r? {dx_dma_last_w , 1'b0} : fis_data_type;
// Read 3 DWORDs from the command header
if (hba_rst) fetch_chead_r <= 0; // running 1
else fetch_chead_r <= {fetch_chead_r[2:0], fetch_cmd};
if (hba_rst) fetch_chead_stb_r <= 0;
else fetch_chead_stb_r <= {fetch_chead_stb_r[2:0], pre_reg_stb && chead_bsy};
if (hba_rst) chead_bsy <= 0;
else if (fetch_cmd) chead_bsy <= 1;
else if (chead_done_w) chead_bsy <= 0;
if (hba_rst) chead_bsy_re <= 0;
else if (fetch_cmd) chead_bsy_re <= 1;
else if (fetch_chead_r[1]) chead_bsy_re <= 0; // read 3 dwords
if (hba_rst) reg_re_r <= 0; // [0] -> reg_re output
else reg_re_r <= {reg_re[1:0], reg_re_w};
if (fetch_cmd) reg_addr <= CLB_OFFS32; // there will be more conditions
else if (reg_re_r[0]) reg_addr <= reg_addr + 1;
// save command header data to registers
if (fetch_chead_stb_r[0]) begin
ch_prdtl_r <= reg_rdata[31:16];
ch_c_r <= reg_rdata[ 10];
ch_b_r <= reg_rdata[ 9];
ch_r_r <= reg_rdata[ 8];
ch_p_r <= reg_rdata[ 7];
ch_w_r <= reg_rdata[ 6];
// ch_a_r <= reg_rdata[ 5];
ch_cmd_len_r<= reg_rdata[ 4: 0];
end
//ch_a
if (hba_rst || atapi_xmit) ch_a_r <= 0;
else if (fetch_chead_stb_r[0]) ch_a_r <= reg_rdata[ 5];
if (hba_rst) pCmdToIssue_r <= 0;
else if (chead_done_w) pCmdToIssue_r <= 1;
else if (clearCmdToIssue) pCmdToIssue_r <= 0;
if (hba_rst || pcmd_st_cleared) fetch_cmd_busy_r <= 0;
else if (fetch_cmd) fetch_cmd_busy_r <= 1;
else if (dma_start) fetch_cmd_busy_r <= 0;
//CFIS/ATAPI common
// fetch and send command/atapi FIS
if (hba_rst || acfis_xmit_start_w || pcmd_st_cleared) acfis_xmit_pend_r <= 0;
else if (cfis_xmit || atapi_xmit) acfis_xmit_pend_r <= 1;
acfis_xmit_start_r <= !hba_rst && acfis_xmit_start_w;
if (hba_rst || pcmd_st_cleared) acfis_xmit_busy_r <= 0;
else if (acfis_xmit_start_r) acfis_xmit_busy_r <= 1;
else if (acfis_xmit_end) acfis_xmit_busy_r <= 0;
if (cfis_xmit) cfis_acmd_left_r <= ch_cmd_len_r[ 4: 0]; // Will assume that there is room for ...
else if (atapi_xmit) cfis_acmd_left_r <= (|xfer_cntr[31:4]) ? 5'h4 : {3'b0,xfer_cntr[3:2]};
else if (acfis_xmit_busy_r && ct_re_r[0]) cfis_acmd_left_r <= cfis_acmd_left_r - 1;
// Counting CFIS/ATAPI FIS dwords sent to TL
if (acfis_xmit_start_r) cfis_acmd_left_out_r <= cfis_acmd_left_r;
else if (ct_stb) cfis_acmd_left_out_r <= cfis_acmd_left_out_r - 1;
if (hba_rst || acfis_xmit_start_w) ct_re_r <= 0;
else ct_re_r <= {ct_re_r[READ_CT_LATENCY-1:0], ct_re_w};
if (cfis_xmit) ct_addr <= 0;
else if (atapi_xmit) ct_addr <= 'h10; // start of ATAPI area
// else if (cfis_acmd_left_r[0]) ct_addr <= ct_addr + 1;
else if (ct_re_r[0]) ct_addr <= ct_addr + 1;
//
// first/last dword in FIS
if (!acfis_xmit_busy_r) fis_dw_first <= 1;
else if (ct_stb) fis_dw_first <= 0;
//TODO: update xfer length, prdtl (only after R_OK) - yes, do it outside
if (dx_xmit) dx_dwords_left[11:0] <= (xfer_cntr_zero || (|xfer_cntr[31:13])) ? 12'h800 : {1'b0,xfer_cntr[12:2]};
else if (dma_re_w) dx_dwords_left[11:0] <= dx_dwords_left[11:0] - 1;
if (dx_xmit) dwords_sent <= 0;
else if (dma_re_w) dwords_sent <= dwords_sent + 1;
// send FIS header
if (hba_rst || write_or_w ||pcmd_st_cleared) dx_fis_pend_r <= 0;
else if (dx_xmit) dx_fis_pend_r <= 1;
if (hba_rst || dx_dma_last_w || (|dx_err_r) || pcmd_st_cleared) dma_en_r <= 0;
else if (dx_fis_pend_r && write_or_w) dma_en_r <= 1;
// Abort on transmit errors
if (hba_rst || any_cmd_start) dx_err_r[0] <= 0;
else if (syncesc_recv) dx_err_r[0] <= 1;
if (hba_rst || any_cmd_start) dx_err_r[1] <= 0;
else if (xmit_err) dx_err_r[1] <= 1;
if (hba_rst || any_cmd_start) dx_err_r[2] <= 0;
else if (xrdy_collision) dx_err_r[2] <= 1;
if (hba_rst || pcmd_st_cleared) dx_busy_r <= 0; // sending CFIS, AFIS or data FIS (until error or R_OK)
else if (dx_xmit || acfis_xmit_start_r) dx_busy_r <= 1;
else if (xmit_ok || (|dx_err_r)) dx_busy_r <= 0;
dma_prd_start <= (dma_start && (PREFETCH_ALWAYS || ch_p_r || !ch_w_r)) || // device read may prefetch just prd addresses
(dx_fis_pend_r && write_or_w); // enable PRD read now (if it was not already done)
if (hba_rst) done <= 0;
else done <= done_w;
if (hba_rst || pcmd_st_cleared) busy <= 0;
else if (any_cmd_start) busy <= 1;
else if (done_w) busy <= 0;
if (hba_rst) xmit_ok_r <= 0;
else xmit_ok_r <= dx_busy_r && !(|dx_err_r) && xmit_ok;
dma_cmd_abort <= done_w && (|dx_err_r);
if (cfis_xmit) dbg_was_ct_re_r <= {ct_re_r, ct_re_w};
if (cfis_xmit) dbg_was_cfis_acmd_left_r <= cfis_acmd_left_r;
end
assign debug_01 = {dx_fis_pend_r, ct_re_r, ct_re_w, cfis_acmd_left_r}; // 1,2,5
// assign debug_01 = {acfis_xmit_start_w, acfis_xmit_pend_r, dma_ct_busy, fetch_cmd_busy_r, ct_re_w, dbg_was_cfis_acmd_left_r}; // 1,2,5
// wire acfis_xmit_start_w = (cfis_xmit || atapi_xmit || acfis_xmit_pend_r) && !dma_ct_busy && !fetch_cmd_busy_r; // dma_ct_busy no gaps with fetch_cmd_busy
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:46:08 08/24/2014
// Design Name:
// Module Name: vga_core
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vga_core(
vga_clk,
rst,
addr,
v_active,
h_sync,
v_sync
); // dot_in, vga_rdn, r, g, b,
input vga_clk; // 25MHz
input rst;
output [18: 0] addr; // pixel Screen address, 640 (1024) x 480 (512)
output v_active; // read VRAM RAM (active_low)
output h_sync, v_sync; // horizontal and vertical synchronization
// input [2:0] dot_in; // r_g_b, pixel
// output reg r, g, b; // red, green, blue colors, 4-bit for each if N3
// h_count: VGA horizontal counter (0-799)
reg [9:0] h_count = 0; // VGA horizontal counter (0-799): pixels
always @ (posedge vga_clk or posedge rst) begin
if (rst) begin
h_count <= 10'h0;
end else if (h_count == 10'd799) begin
h_count <= 10'h0;
end else begin
h_count <= h_count + 10'h1;
end
end
// v_count: VGA vertical counter (0-524)
reg [9:0] v_count = 0; // VGA vertical counter (0-524): lines
always @ (posedge vga_clk or posedge rst) begin
if (rst) begin
v_count <= 10'h0;
end else if (h_count == 10'd799) begin
if (v_count == 10'd524) begin
v_count <= 10'h0;
end else begin
v_count <= v_count + 10'h1;
end
end
end
// signal timing
wire h_sync = (h_count > 10'd95); // 96 -> 799
wire v_sync = (v_count > 10'd1); // 2 -> 524
wire v_active = (h_count > 10'd142) && // 143 -> 782
(h_count < 10'd783) && // 640 pixels
(v_count > 10'd34) && // 35 -> 514
(v_count < 10'd515); // 480 lines
wire [ 9: 0] col = h_count - 10'd143; // pixel Screen addr col
wire [ 9: 0] row = v_count - 10'd35; // pixel Screen addr row
wire [18: 0] addr = {row[ 8: 0], col}; // pixel Screen addr
// vga signals
/* always @ (posedge vga_clk) begin
pixel_addr <= addr;
vga_rdn <= ~read;
hs <= h_sync; // horizontal synchronization
vs <= v_sync; // vertical synchronization
r <= vga_rdn ? 4'h0 : dot_in[2]; // 1-bit red
g <= vga_rdn ? 4'h0 : dot_in[1]; // 1-bit green
b <= vga_rdn ? 4'h0 : dot_in[0]; // 1-bit blue
end
*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKBUF_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__CLKBUF_PP_BLACKBOX_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__clkbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKBUF_PP_BLACKBOX_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2009 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file virtex6_pmem.v when simulating
// the core, virtex6_pmem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module virtex6_pmem(
clka,
ena,
wea,
addra,
dina,
douta);
input clka;
input ena;
input [1 : 0] wea;
input [11 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V3_3 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(1),
.C_BYTE_SIZE(8),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("virtex6"),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(4096),
.C_READ_DEPTH_B(4096),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(1),
.C_USE_BYTE_WEB(1),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_WEA_WIDTH(2),
.C_WEB_WIDTH(2),
.C_WRITE_DEPTH_A(4096),
.C_WRITE_DEPTH_B(4096),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("virtex6"))
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of virtex6_pmem is "black_box"
endmodule
|
`include "../include/tune.v"
// Pentevo project (c) NedoPC 2011
//
// VGA scandoubler
module video_vga_double(
input wire clk,
input wire hsync_start,
input wire scanin_start,
input wire [ 5:0] pix_in,
input wire scanout_start,
output reg [ 5:0] pix_out
);
/*
addressing of non-overlapping pages:
pg0 pg1
0xx 1xx
2xx 3xx
4xx 5xx
*/
reg [9:0] ptr_in; // count up to 720
reg [9:0] ptr_out; //
reg pages; // swapping of pages
reg wr_stb;
wire [ 7:0] data_out;
always @(posedge clk) if( hsync_start )
pages <= ~pages;
// write ptr and strobe
always @(posedge clk)
begin
if( scanin_start )
begin
ptr_in[9:8] <= 2'b00;
ptr_in[5:4] <= 2'b11;
end
else
begin
if( ptr_in[9:8]!=2'b11 ) // 768-720=48
begin
wr_stb <= ~wr_stb;
if( wr_stb )
begin
ptr_in <= ptr_in + 10'd1;
end
end
end
end
// read ptr
always @(posedge clk)
begin
if( scanout_start )
begin
ptr_out[9:8] <= 2'b00;
ptr_out[5:4] <= 2'b11;
end
else
begin
if( ptr_out[9:8]!=2'b11 )
begin
ptr_out <= ptr_out + 10'd1;
end
end
end
//read data
always @(posedge clk)
begin
if( ptr_out[9:8]!=2'b11 )
pix_out <= data_out[5:0];
else
pix_out <= 6'd0;
end
mem1536 line_buf( .clk(clk),
.wraddr({ptr_in[9:8], pages, ptr_in[7:0]}),
.wrdata({2'b00,pix_in}),
.wr_stb(wr_stb),
.rdaddr({ptr_out[9:8], (~pages), ptr_out[7:0]}),
.rddata(data_out)
);
endmodule
// 3x512b memory
module mem1536(
input wire clk,
input wire [10:0] wraddr,
input wire [ 7:0] wrdata,
input wire wr_stb,
input wire [10:0] rdaddr,
output reg [ 7:0] rddata
);
reg [7:0] mem [0:1535];
always @(posedge clk)
begin
if( wr_stb )
begin
mem[wraddr] <= wrdata;
end
rddata <= mem[rdaddr];
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
(* rom_style = "distributed" *) module CvtColor_1_sectorncg_rom (
addr0, ce0, q0, clk);
parameter DWIDTH = 2;
parameter AWIDTH = 3;
parameter MEM_SIZE = 6;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./CvtColor_1_sectorncg_rom.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module CvtColor_1_sectorncg(
reset,
clk,
address0,
ce0,
q0);
parameter DataWidth = 32'd2;
parameter AddressRange = 32'd6;
parameter AddressWidth = 32'd3;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
CvtColor_1_sectorncg_rom CvtColor_1_sectorncg_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ));
endmodule
|
/*
* Titor - Barrel Processor - Performs sign extension of halfword integers
* Copyright (C) 2012 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_Sign_Ext_Imm
`else
`define INC_Sign_Ext_Imm
`timescale 1 ns / 100 ps
// Combinational module
// takes a two's complement, WORD/2 bit number and conditionally sign extends to WORD bits
module Sign_Ext_Imm (
result,
operand,
enable
);
`include "definition/Definition.v"
output [WORD-1:0] result;
input [WORD-1:0] operand;
input enable;
Sign_Ext_Return standin(
.result(result),
.operand(operand),
.size(IMM_EXT_CONSTANT),
.signage(enable)
);
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__DFXTP_FUNCTIONAL_PP_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_ms__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFXTP_FUNCTIONAL_PP_V |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module sp_best_delta_seg_ch (
dth_0_V_read,
dth_1_V_read,
dth_2_V_read,
dth_3_V_read,
sth_V,
dvl_V,
ap_return_0,
ap_return_1,
ap_return_2,
ap_return_3
);
parameter ap_const_lv2_3 = 2'b11;
parameter ap_const_lv2_1 = 2'b1;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv7_7F = 7'b1111111;
parameter ap_const_lv32_2 = 32'b10;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv2_2 = 2'b10;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv4_0 = 4'b0000;
input [6:0] dth_0_V_read;
input [6:0] dth_1_V_read;
input [6:0] dth_2_V_read;
input [6:0] dth_3_V_read;
input [3:0] sth_V;
input [3:0] dvl_V;
output [6:0] ap_return_0;
output [0:0] ap_return_1;
output [0:0] ap_return_2;
output [1:0] ap_return_3;
wire [1:0] tmp_2757_fu_94_p1;
wire [0:0] tmp_s_fu_88_p2;
wire [0:0] tmp_401_fu_98_p2;
wire [0:0] sel_tmp_fu_110_p2;
wire [0:0] tmp_402_fu_104_p2;
wire [0:0] sel_tmp1_fu_116_p2;
wire [0:0] not_sel_tmp1_fu_122_p2;
wire [0:0] tmp_403_fu_140_p2;
wire [6:0] cmp1_V_load3_fu_132_p3;
wire [1:0] p_Result_1213_1_fu_160_p4;
wire [0:0] tmp_1139_1_fu_154_p2;
wire [0:0] tmp_1142_1_fu_170_p2;
wire [0:0] sel_tmp9_fu_198_p2;
wire [0:0] tmp_1143_1_fu_176_p2;
wire [0:0] sel_tmp10_fu_204_p2;
wire [0:0] tmp_2758_fu_182_p3;
wire [0:0] tmp_2759_fu_190_p3;
wire [0:0] tmp_1153_1_fu_234_p2;
wire [6:0] cmp1_V_load_s_fu_218_p3;
wire [6:0] cmp1_V_load_fu_146_p3;
wire [6:0] cmp1_V_load_1_fu_240_p3;
wire [0:0] tmp_2760_fu_254_p1;
wire [0:0] tmp_2761_fu_258_p3;
wire [0:0] tmp_fu_248_p2;
wire [1:0] num1_V_load_cast_fu_128_p1;
wire [1:0] num1_V_load_1_fu_210_p3;
wire [0:0] tmp_216_fu_266_p3;
wire [0:0] tmp_213_fu_226_p3;
wire [6:0] a_bth_V_fu_282_p3;
wire [0:0] p_Result_s_fu_290_p3;
wire [0:0] a_bvl_V_fu_298_p2;
wire [1:0] a_bnm_V_fu_274_p3;
assign a_bnm_V_fu_274_p3 = ((tmp_fu_248_p2[0:0] === 1'b1) ? num1_V_load_cast_fu_128_p1 : num1_V_load_1_fu_210_p3);
assign a_bth_V_fu_282_p3 = ((tmp_fu_248_p2[0:0] === 1'b1) ? cmp1_V_load_fu_146_p3 : cmp1_V_load_1_fu_240_p3);
assign a_bvl_V_fu_298_p2 = ((dvl_V != ap_const_lv4_0) ? 1'b1 : 1'b0);
assign ap_return_0 = a_bth_V_fu_282_p3;
assign ap_return_1 = p_Result_s_fu_290_p3;
assign ap_return_2 = a_bvl_V_fu_298_p2;
assign ap_return_3 = a_bnm_V_fu_274_p3;
assign cmp1_V_load3_fu_132_p3 = ((sel_tmp1_fu_116_p2[0:0] === 1'b1) ? dth_0_V_read : dth_1_V_read);
assign cmp1_V_load_1_fu_240_p3 = ((tmp_1153_1_fu_234_p2[0:0] === 1'b1) ? ap_const_lv7_7F : cmp1_V_load_s_fu_218_p3);
assign cmp1_V_load_fu_146_p3 = ((tmp_403_fu_140_p2[0:0] === 1'b1) ? ap_const_lv7_7F : cmp1_V_load3_fu_132_p3);
assign cmp1_V_load_s_fu_218_p3 = ((sel_tmp10_fu_204_p2[0:0] === 1'b1) ? dth_2_V_read : dth_3_V_read);
assign not_sel_tmp1_fu_122_p2 = (sel_tmp1_fu_116_p2 ^ 1'b1);
assign num1_V_load_1_fu_210_p3 = ((sel_tmp10_fu_204_p2[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_3);
assign num1_V_load_cast_fu_128_p1 = not_sel_tmp1_fu_122_p2;
assign p_Result_1213_1_fu_160_p4 = {{dvl_V[ap_const_lv32_3 : ap_const_lv32_2]}};
assign p_Result_s_fu_290_p3 = ((tmp_fu_248_p2[0:0] === 1'b1) ? tmp_216_fu_266_p3 : tmp_213_fu_226_p3);
assign sel_tmp10_fu_204_p2 = (sel_tmp9_fu_198_p2 | tmp_1143_1_fu_176_p2);
assign sel_tmp1_fu_116_p2 = (sel_tmp_fu_110_p2 | tmp_402_fu_104_p2);
assign sel_tmp9_fu_198_p2 = (tmp_1139_1_fu_154_p2 & tmp_1142_1_fu_170_p2);
assign sel_tmp_fu_110_p2 = (tmp_s_fu_88_p2 & tmp_401_fu_98_p2);
assign tmp_1139_1_fu_154_p2 = ((dth_2_V_read < dth_3_V_read) ? 1'b1 : 1'b0);
assign tmp_1142_1_fu_170_p2 = ((p_Result_1213_1_fu_160_p4 == ap_const_lv2_3) ? 1'b1 : 1'b0);
assign tmp_1143_1_fu_176_p2 = ((p_Result_1213_1_fu_160_p4 == ap_const_lv2_1) ? 1'b1 : 1'b0);
assign tmp_1153_1_fu_234_p2 = ((p_Result_1213_1_fu_160_p4 == ap_const_lv2_0) ? 1'b1 : 1'b0);
assign tmp_213_fu_226_p3 = ((sel_tmp10_fu_204_p2[0:0] === 1'b1) ? tmp_2758_fu_182_p3 : tmp_2759_fu_190_p3);
assign tmp_216_fu_266_p3 = ((sel_tmp1_fu_116_p2[0:0] === 1'b1) ? tmp_2760_fu_254_p1 : tmp_2761_fu_258_p3);
assign tmp_2757_fu_94_p1 = dvl_V[1:0];
assign tmp_2758_fu_182_p3 = sth_V[ap_const_lv32_2];
assign tmp_2759_fu_190_p3 = sth_V[ap_const_lv32_3];
assign tmp_2760_fu_254_p1 = sth_V[0:0];
assign tmp_2761_fu_258_p3 = sth_V[ap_const_lv32_1];
assign tmp_401_fu_98_p2 = ((tmp_2757_fu_94_p1 == ap_const_lv2_3) ? 1'b1 : 1'b0);
assign tmp_402_fu_104_p2 = ((tmp_2757_fu_94_p1 == ap_const_lv2_1) ? 1'b1 : 1'b0);
assign tmp_403_fu_140_p2 = ((tmp_2757_fu_94_p1 == ap_const_lv2_0) ? 1'b1 : 1'b0);
assign tmp_fu_248_p2 = ((cmp1_V_load_fu_146_p3 < cmp1_V_load_1_fu_240_p3) ? 1'b1 : 1'b0);
assign tmp_s_fu_88_p2 = ((dth_0_V_read < dth_1_V_read) ? 1'b1 : 1'b0);
endmodule //sp_best_delta_seg_ch
|
//UART Controller
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
07/08/2012
-Initial Commit
07/30/2012
-Attached Flow control for CTS RTS
-Removed DTR DSR for this initial version
*/
`timescale 1ns/1ps
//Status Flag Defines
`define STATUS_RX_AVAILABLE 0
`define STATUS_TX_READY 1
`define STATUS_RX_FULL 2
`define STATUS_RX_ERROR 3
`define STATUS_FC_ERROR 4
`define PRESCALER_DIV 8
module uart_controller #(
parameter DEFAULT_BAUDRATE = 115200
)(
input clk,
input rst,
input rx,
output tx,
//I need to verify flow control is correct
output reg cts,
input rts,
input control_reset,
input cts_rts_flowcontrol,
output [31:0] prescaler,
input set_clock_div,
input [31:0] clock_div,
output [31:0] default_clock_div,
input write_strobe,
input [7:0] write_data,
output write_full,
output [31:0] write_available,
output [31:0] write_size,
output write_overflow,
output [7:0] read_data,
input read_strobe,
output read_empty,
output [31:0] read_count,
output [31:0] read_size,
output read_overflow
);
//FIFO Registers
wire [31:0] tx_read_count;
reg tx_read_strobe;
wire [7:0] tx_fifo_read_data;
wire tx_underflow;
wire tx_full;
wire tx_empty;
wire [31:0] rx_write_available;
wire rx_underflow;
wire rx_full;
//UART Core
reg transmit;
reg [7:0] tx_byte;
wire received;
wire [7:0] rx_byte;
wire is_receiving;
wire is_transmitting;
wire rx_error;
reg local_read;
wire cts_rts_flowcontrol;
reg [3:0] state;
reg test;
//CONTROL Flags
//STATUS FLAGs
uart_fifo uf_tx (
.clk (clk ),
.rst (rst || control_reset ),
.size (write_size ),
.write_strobe (write_strobe ),
.write_available (write_available ),
.write_data (write_data ),
.read_strobe (tx_read_strobe ),
.read_count (tx_read_count ),
.read_data (tx_fifo_read_data ),
.overflow (write_overflow ),
.underflow (tx_underflow ),
.full (tx_full ),
.empty (tx_empty )
);
uart_fifo uf_rx (
.clk (clk ),
.rst (rst || control_reset ),
.size (read_size ),
.write_strobe (received ),
.write_available (rx_write_available ),
.write_data (rx_byte ),
.read_strobe (read_strobe ),
.read_count (read_count ),
.read_data (read_data ),
.overflow (read_overflow ),
.underflow (rx_underflow ),
.full (rx_full ),
.empty (read_empty )
);
//Low Level UART
uart #(
.DEFAULT_BAUDRATE (DEFAULT_BAUDRATE )
) u(
.clk (clk ),
.rst (rst || control_reset ),
.rx (rx ),
.tx (tx ),
.transmit (transmit ),
.tx_byte (tx_byte ),
.received (received ),
.rx_byte (rx_byte ),
.is_receiving (is_receiving ),
.is_transmitting (is_transmitting ),
.rx_error (rx_error ),
.set_clock_div (set_clock_div ),
.user_clock_div (clock_div ),
.default_clock_div (default_clock_div ),
.prescaler (prescaler )
);
parameter IDLE = 3'h0;
parameter SEND = 3'h1;
parameter READ = 3'h2;
//asynchronous logic
assign write_full = tx_full;
//synchronous logic
//main control state machine
always @ (posedge clk) begin
if (rst) begin
cts <= 0;
state <= IDLE;
local_read <= 0;
test <= 0;
tx_read_strobe <= 0;
tx_byte <= 0;
end
else begin
transmit <= 0;
tx_read_strobe <= 0;
local_read <= 0;
cts <= 0;
if (tx_read_strobe) begin
//$display ("UART_CONTROLLER: Setting tx_byte to %h", tx_fifo_read_data);
tx_byte <= tx_fifo_read_data;
transmit <= 1;
end
//transmitting
//XXX: The write strobe is here to work around the condition when the user is writing and the UART is reading
//XXX: at the same time, this can be fixed with more logic
if (!tx_empty && !is_transmitting && !transmit && !tx_read_strobe && !write_strobe) begin
if (cts_rts_flowcontrol) begin
if (~rts) begin
$display ("WB_UC (%g): RTS is low", $time);
//device is ready to receive data
tx_read_strobe <= 1;
end
end
//XXX: here is where DTR DSR can be put in
else begin
tx_read_strobe <= 1;
end
end
if (rx_full && cts_rts_flowcontrol) begin
//deassert hardware flow control
$display ("WB_UC (%g): CTS high", $time);
cts <= 1;
end
end
end
endmodule
|
(** * MoreCoq: More About Coq *)
Require Export Poly.
(** This chapter introduces several more Coq tactics that,
together, allow us to prove many more theorems about the
functional programs we are writing. *)
(* ###################################################### *)
(** * The [apply] Tactic *)
(** We often encounter situations where the goal to be proved is
exactly the same as some hypothesis in the context or some
previously proved lemma. *)
Theorem silly1 : forall (n m o p : nat),
n = m ->
[n;o] = [n;p] ->
[n;o] = [m;p].
Proof.
intros n m o p eq1 eq2.
rewrite <- eq1.
(* At this point, we could finish with
"[rewrite -> eq2. reflexivity.]" as we have
done several times above. But we can achieve the
same effect in a single step by using the
[apply] tactic instead: *)
apply eq2. Qed.
(** The [apply] tactic also works with _conditional_ hypotheses
and lemmas: if the statement being applied is an implication, then
the premises of this implication will be added to the list of
subgoals needing to be proved. *)
Theorem silly2 : forall (n m o p : nat),
n = m ->
(forall (q r : nat), q = r -> [q;o] = [r;p]) ->
[n;o] = [m;p].
Proof.
intros n m o p eq1 eq2.
apply eq2. apply eq1. Qed.
(** You may find it instructive to experiment with this proof
and see if there is a way to complete it using just [rewrite]
instead of [apply]. *)
(** Typically, when we use [apply H], the statement [H] will
begin with a [forall] binding some _universal variables_. When
Coq matches the current goal against the conclusion of [H], it
will try to find appropriate values for these variables. For
example, when we do [apply eq2] in the following proof, the
universal variable [q] in [eq2] gets instantiated with [n] and [r]
gets instantiated with [m]. *)
Theorem silly2a : forall (n m : nat),
(n,n) = (m,m) ->
(forall (q r : nat), (q,q) = (r,r) -> [q] = [r]) ->
[n] = [m].
Proof.
intros.
apply H0.
apply H.
Qed.
(** **** Exercise: 2 stars, optional (silly_ex) *)
(** Complete the following proof without using [simpl]. *)
Theorem silly_ex :
(forall n, evenb n = true -> oddb (S n) = true) ->
evenb 3 = true ->
oddb 4 = true.
Proof.
intros.
apply H.
exact H0.
Qed.
(** [] *)
(** To use the [apply] tactic, the (conclusion of the) fact
being applied must match the goal _exactly_ -- for example, [apply]
will not work if the left and right sides of the equality are
swapped. *)
Theorem silly3_firsttry : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
simpl.
(* Here we cannot use [apply] directly *)
Abort.
(** In this case we can use the [symmetry] tactic, which switches the
left and right sides of an equality in the goal. *)
Theorem silly3 : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
symmetry.
simpl. (* Actually, this [simpl] is unnecessary, since
[apply] will do a [simpl] step first. *)
apply H. Qed.
(** **** Exercise: 3 stars (apply_exercise1) *)
(** Hint: you can use [apply] with previously defined lemmas, not
just hypotheses in the context. Remember that [SearchAbout] is
your friend. *)
Theorem rev_exercise1 : forall (l l' : list nat),
l = rev l' ->
l' = rev l.
Proof.
intros l l' H.
rewrite H.
symmetry.
apply rev_involutive.
Qed.
(** [] *)
(** **** Exercise: 1 star, optional (apply_rewrite) *)
(** Briefly explain the difference between the tactics [apply] and
[rewrite]. Are there situations where both can usefully be
applied?
(* FILL IN HERE *)
*)
(** [] *)
(* ###################################################### *)
(** * The [apply ... with ...] Tactic *)
(** The following silly example uses two rewrites in a row to
get from [[a,b]] to [[e,f]]. *)
Example trans_eq_example : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros a b c d e f eq1 eq2.
rewrite -> eq1. rewrite -> eq2. reflexivity. Qed.
(** Since this is a common pattern, we might
abstract it out as a lemma recording once and for all
the fact that equality is transitive. *)
Theorem trans_eq : forall (X:Type) (n m o : X),
n = m -> m = o -> n = o.
Proof.
intros X n m o eq1 eq2. rewrite -> eq1. rewrite -> eq2.
reflexivity. Qed.
(** Now, we should be able to use [trans_eq] to
prove the above example. However, to do this we need
a slight refinement of the [apply] tactic. *)
Example trans_eq_example' : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros a b c d e f eq1 eq2.
(* If we simply tell Coq [apply trans_eq] at this point,
it can tell (by matching the goal against the
conclusion of the lemma) that it should instantiate [X]
with [[nat]], [n] with [[a,b]], and [o] with [[e,f]].
However, the matching process doesn't determine an
instantiation for [m]: we have to supply one explicitly
by adding [with (m:=[c,d])] to the invocation of
[apply]. *)
apply trans_eq with (m:=[c;d]). apply eq1. apply eq2. Qed.
(** Actually, we usually don't have to include the name [m]
in the [with] clause; Coq is often smart enough to
figure out which instantiation we're giving. We could
instead write: [apply trans_eq with [c,d]]. *)
Definition minustwo (n:nat) : nat := pred (pred n).
(** **** Exercise: 3 stars, optional (apply_with_exercise) *)
Example trans_eq_exercise : forall (n m o p : nat),
m = (minustwo o) ->
(n + p) = m ->
(n + p) = (minustwo o).
Proof.
intros.
apply trans_eq with m.
exact H0.
exact H.
Qed.
(** [] *)
(* ###################################################### *)
(** * The [inversion] tactic *)
(** Recall the definition of natural numbers:
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
It is clear from this definition that every number has one of two
forms: either it is the constructor [O] or it is built by applying
the constructor [S] to another number. But there is more here than
meets the eye: implicit in the definition (and in our informal
understanding of how datatype declarations work in other
programming languages) are two other facts:
- The constructor [S] is _injective_. That is, the only way we can
have [S n = S m] is if [n = m].
- The constructors [O] and [S] are _disjoint_. That is, [O] is not
equal to [S n] for any [n]. *)
(** Similar principles apply to all inductively defined types: all
constructors are injective, and the values built from distinct
constructors are never equal. For lists, the [cons] constructor is
injective and [nil] is different from every non-empty list. For
booleans, [true] and [false] are unequal. (Since neither [true]
nor [false] take any arguments, their injectivity is not an issue.) *)
(** Coq provides a tactic called [inversion] that allows us to exploit
these principles in proofs.
The [inversion] tactic is used like this. Suppose [H] is a
hypothesis in the context (or a previously proven lemma) of the
form
c a1 a2 ... an = d b1 b2 ... bm
for some constructors [c] and [d] and arguments [a1 ... an] and
[b1 ... bm]. Then [inversion H] instructs Coq to "invert" this
equality to extract the information it contains about these terms:
- If [c] and [d] are the same constructor, then we know, by the
injectivity of this constructor, that [a1 = b1], [a2 = b2],
etc.; [inversion H] adds these facts to the context, and tries
to use them to rewrite the goal.
- If [c] and [d] are different constructors, then the hypothesis
[H] is contradictory. That is, a false assumption has crept
into the context, and this means that any goal whatsoever is
provable! In this case, [inversion H] marks the current goal as
completed and pops it off the goal stack. *)
(** The [inversion] tactic is probably easier to understand by
seeing it in action than from general descriptions like the above.
Below you will find example theorems that demonstrate the use of
[inversion] and exercises to test your understanding. *)
Theorem eq_add_S : forall (n m : nat),
S n = S m ->
n = m.
Proof.
intros n m eq. inversion eq. reflexivity. Qed.
Theorem silly4 : forall (n m : nat),
[n] = [m] ->
n = m.
Proof.
intros n o eq. inversion eq. reflexivity. Qed.
(** As a convenience, the [inversion] tactic can also
destruct equalities between complex values, binding
multiple variables as it goes. *)
Theorem silly5 : forall (n m o : nat),
[n;m] = [o;o] ->
[n] = [m].
Proof.
intros n m o eq. inversion eq. reflexivity. Qed.
(** **** Exercise: 1 star (sillyex1) *)
Example sillyex1 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = z :: j ->
y :: l = x :: j ->
x = y.
Proof.
intros.
inversion H0.
reflexivity.
Qed.
(** [] *)
Theorem silly6 : forall (n : nat),
S n = O ->
2 + 2 = 5.
Proof.
intros n contra. inversion contra. Qed.
Theorem silly7 : forall (n m : nat),
false = true ->
[n] = [m].
Proof.
intros n m contra. inversion contra. Qed.
(** **** Exercise: 1 star (sillyex2) *)
Example sillyex2 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = [] ->
y :: l = z :: j ->
x = z.
Proof.
intros.
inversion H.
Qed.
(** [] *)
(** While the injectivity of constructors allows us to reason
[forall (n m : nat), S n = S m -> n = m], the reverse direction of
the implication is an instance of a more general fact about
constructors and functions, which we will often find useful: *)
Theorem f_equal : forall (A B : Type) (f: A -> B) (x y: A),
x = y -> f x = f y.
Proof. intros A B f x y eq. rewrite eq. reflexivity. Qed.
(** Here's another illustration of [inversion]. This is a slightly
roundabout way of stating a fact that we have already proved
above. The extra equalities force us to do a little more
equational reasoning and exercise some of the tactics we've seen
recently. *)
Theorem length_snoc' : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l. induction l as [| v' l'].
intros n eq. rewrite <- eq. reflexivity.
intros n eq. simpl. destruct n as [| n'].
inversion eq.
apply f_equal. apply IHl'. inversion eq. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (practice) *)
(** A couple more nontrivial but not-too-complicated proofs to work
together in class, or for you to work as exercises. They may
involve applying lemmas from earlier lectures or homeworks. *)
Theorem beq_nat_0_l : forall n,
beq_nat 0 n = true -> n = 0.
Proof.
intros.
destruct n.
reflexivity.
inversion H.
Qed.
Theorem beq_nat_0_r : forall n,
beq_nat n 0 = true -> n = 0.
Proof.
intros.
destruct n.
reflexivity.
inversion H.
Qed.
(** [] *)
(* ###################################################### *)
(** * Using Tactics on Hypotheses *)
(** By default, most tactics work on the goal formula and leave
the context unchanged. However, most tactics also have a variant
that performs a similar operation on a statement in the context.
For example, the tactic [simpl in H] performs simplification in
the hypothesis named [H] in the context. *)
Theorem S_inj : forall (n m : nat) (b : bool),
beq_nat (S n) (S m) = b ->
beq_nat n m = b.
Proof.
intros n m b H. simpl in H. apply H. Qed.
(** Similarly, the tactic [apply L in H] matches some
conditional statement [L] (of the form [L1 -> L2], say) against a
hypothesis [H] in the context. However, unlike ordinary
[apply] (which rewrites a goal matching [L2] into a subgoal [L1]),
[apply L in H] matches [H] against [L1] and, if successful,
replaces it with [L2].
In other words, [apply L in H] gives us a form of "forward
reasoning" -- from [L1 -> L2] and a hypothesis matching [L1], it
gives us a hypothesis matching [L2]. By contrast, [apply L] is
"backward reasoning" -- it says that if we know [L1->L2] and we
are trying to prove [L2], it suffices to prove [L1].
Here is a variant of a proof from above, using forward reasoning
throughout instead of backward reasoning. *)
Theorem silly3' : forall (n : nat),
(beq_nat n 5 = true -> beq_nat (S (S n)) 7 = true) ->
true = beq_nat n 5 ->
true = beq_nat (S (S n)) 7.
Proof.
intros n eq H.
symmetry in H. apply eq in H. symmetry in H.
apply H. Qed.
(** Forward reasoning starts from what is _given_ (premises,
previously proven theorems) and iteratively draws conclusions from
them until the goal is reached. Backward reasoning starts from
the _goal_, and iteratively reasons about what would imply the
goal, until premises or previously proven theorems are reached.
If you've seen informal proofs before (for example, in a math or
computer science class), they probably used forward reasoning. In
general, Coq tends to favor backward reasoning, but in some
situations the forward style can be easier to use or to think
about. *)
(** **** Exercise: 3 stars (plus_n_n_injective) *)
(** Practice using "in" variants in this exercise. *)
Theorem plus_n_n_injective : forall n m,
n + n = m + m ->
n = m.
Proof.
intros n. induction n as [| n'].
destruct m.
reflexivity.
simpl.
intro H.
inversion H.
intro m.
destruct m.
intro H.
inversion H.
intros.
inversion H.
rewrite <- plus_n_Sm in H1.
rewrite <- plus_n_Sm in H1.
inversion H1.
apply IHn' in H2.
rewrite H2.
reflexivity.
Qed.
(* Hint: use the plus_n_Sm lemma *)
(** [] *)
(* ###################################################### *)
(** * Varying the Induction Hypothesis *)
(** Sometimes it is important to control the exact form of the
induction hypothesis when carrying out inductive proofs in Coq.
In particular, we need to be careful about which of the
assumptions we move (using [intros]) from the goal to the context
before invoking the [induction] tactic. For example, suppose
we want to show that the [double] function is injective -- i.e.,
that it always maps different arguments to different results:
Theorem double_injective: forall n m, double n = double m -> n = m.
The way we _start_ this proof is a little bit delicate: if we
begin it with
intros n. induction n.
]]
all is well. But if we begin it with
intros n m. induction n.
we get stuck in the middle of the inductive case... *)
Fixpoint double (n:nat) : nat :=
match n with
| 0 => 0
| S m => S(S(double m))
end.
Theorem double_injective_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction n as [| n'].
simpl. intros eq. destruct m as [| m'].
reflexivity.
inversion eq.
intros eq. destruct m as [| m'].
inversion eq.
apply f_equal.
(* Here we are stuck. The induction hypothesis, [IHn'], does
not give us [n' = m'] -- there is an extra [S] in the
way -- so the goal is not provable. *)
Abort.
(** What went wrong? *)
(** The problem is that, at the point we invoke the induction
hypothesis, we have already introduced [m] into the context --
intuitively, we have told Coq, "Let's consider some particular
[n] and [m]..." and we now have to prove that, if [double n =
double m] for _this particular_ [n] and [m], then [n = m].
The next tactic, [induction n] says to Coq: We are going to show
the goal by induction on [n]. That is, we are going to prove that
the proposition
- [P n] = "if [double n = double m], then [n = m]"
holds for all [n] by showing
- [P O]
(i.e., "if [double O = double m] then [O = m]")
- [P n -> P (S n)]
(i.e., "if [double n = double m] then [n = m]" implies "if
[double (S n) = double m] then [S n = m]").
If we look closely at the second statement, it is saying something
rather strange: it says that, for a _particular_ [m], if we know
- "if [double n = double m] then [n = m]"
then we can prove
- "if [double (S n) = double m] then [S n = m]".
To see why this is strange, let's think of a particular [m] --
say, [5]. The statement is then saying that, if we know
- [Q] = "if [double n = 10] then [n = 5]"
then we can prove
- [R] = "if [double (S n) = 10] then [S n = 5]".
But knowing [Q] doesn't give us any help with proving [R]! (If we
tried to prove [R] from [Q], we would say something like "Suppose
[double (S n) = 10]..." but then we'd be stuck: knowing that
[double (S n)] is [10] tells us nothing about whether [double n]
is [10], so [Q] is useless at this point.) *)
(** To summarize: Trying to carry out this proof by induction on [n]
when [m] is already in the context doesn't work because we are
trying to prove a relation involving _every_ [n] but just a
_single_ [m]. *)
(** The good proof of [double_injective] leaves [m] in the goal
statement at the point where the [induction] tactic is invoked on
[n]: *)
Theorem double_injective : forall n m,
double n = double m ->
n = m.
Proof.
intros n. induction n as [| n'].
simpl. intros m eq. destruct m as [| m'].
reflexivity.
inversion eq.
(* Notice that both the goal and the induction
hypothesis have changed: the goal asks us to prove
something more general (i.e., to prove the
statement for _every_ [m]), but the IH is
correspondingly more flexible, allowing us to
choose any [m] we like when we apply the IH. *)
intros m eq.
(* Now we choose a particular [m] and introduce the
assumption that [double n = double m]. Since we
are doing a case analysis on [n], we need a case
analysis on [m] to keep the two "in sync." *)
destruct m as [| m'].
(* The 0 case is trivial *)
inversion eq.
apply f_equal.
(* At this point, since we are in the second
branch of the [destruct m], the [m'] mentioned
in the context at this point is actually the
predecessor of the one we started out talking
about. Since we are also in the [S] branch of
the induction, this is perfect: if we
instantiate the generic [m] in the IH with the
[m'] that we are talking about right now (this
instantiation is performed automatically by
[apply]), then [IHn'] gives us exactly what we
need to finish the proof. *)
apply IHn'. inversion eq. reflexivity. Qed.
(** What this teaches us is that we need to be careful about using
induction to try to prove something too specific: If we're proving
a property of [n] and [m] by induction on [n], we may need to
leave [m] generic. *)
(** The proof of this theorem has to be treated similarly: *)
(** **** Exercise: 2 stars (beq_nat_true) *)
Theorem beq_nat_true : forall n m,
beq_nat n m = true -> n = m.
Proof.
induction n.
intros.
destruct m.
reflexivity.
inversion H.
destruct m.
intro H.
inversion H.
intro H.
inversion H.
apply f_equal.
apply IHn.
exact H1.
Qed.
(** [] *)
(** **** Exercise: 2 stars, advanced (beq_nat_true_informal) *)
(** Give a careful informal proof of [beq_nat_true], being as explicit
as possible about quantifiers. *)
(* FILL IN HERE *)
(** [] *)
(** The strategy of doing fewer [intros] before an [induction] doesn't
always work directly; sometimes a little _rearrangement_ of
quantified variables is needed. Suppose, for example, that we
wanted to prove [double_injective] by induction on [m] instead of
[n]. *)
Theorem double_injective_take2_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction m as [| m'].
simpl. intros eq. destruct n as [| n'].
reflexivity.
inversion eq.
intros eq. destruct n as [| n'].
inversion eq.
apply f_equal.
(* Stuck again here, just like before. *)
Abort.
(** The problem is that, to do induction on [m], we must first
introduce [n]. (If we simply say [induction m] without
introducing anything first, Coq will automatically introduce
[n] for us!) *)
(** What can we do about this? One possibility is to rewrite the
statement of the lemma so that [m] is quantified before [n]. This
will work, but it's not nice: We don't want to have to mangle the
statements of lemmas to fit the needs of a particular strategy for
proving them -- we want to state them in the most clear and
natural way. *)
(** What we can do instead is to first introduce all the
quantified variables and then _re-generalize_ one or more of
them, taking them out of the context and putting them back at
the beginning of the goal. The [generalize dependent] tactic
does this. *)
Theorem double_injective_take2 : forall n m,
double n = double m ->
n = m.
Proof.
intros n m.
(* [n] and [m] are both in the context *)
generalize dependent n.
(* Now [n] is back in the goal and we can do induction on
[m] and get a sufficiently general IH. *)
induction m as [| m'].
simpl. intros n eq. destruct n as [| n'].
reflexivity.
inversion eq.
intros n eq. destruct n as [| n'].
inversion eq.
apply f_equal.
apply IHm'. inversion eq. reflexivity. Qed.
(** Let's look at an informal proof of this theorem. Note that
the proposition we prove by induction leaves [n] quantified,
corresponding to the use of generalize dependent in our formal
proof.
_Theorem_: For any nats [n] and [m], if [double n = double m], then
[n = m].
_Proof_: Let [m] be a [nat]. We prove by induction on [m] that, for
any [n], if [double n = double m] then [n = m].
- First, suppose [m = 0], and suppose [n] is a number such
that [double n = double m]. We must show that [n = 0].
Since [m = 0], by the definition of [double] we have [double n =
0]. There are two cases to consider for [n]. If [n = 0] we are
done, since this is what we wanted to show. Otherwise, if [n = S
n'] for some [n'], we derive a contradiction: by the definition of
[double] we would have [double n = S (S (double n'))], but this
contradicts the assumption that [double n = 0].
- Otherwise, suppose [m = S m'] and that [n] is again a number such
that [double n = double m]. We must show that [n = S m'], with
the induction hypothesis that for every number [s], if [double s =
double m'] then [s = m'].
By the fact that [m = S m'] and the definition of [double], we
have [double n = S (S (double m'))]. There are two cases to
consider for [n].
If [n = 0], then by definition [double n = 0], a contradiction.
Thus, we may assume that [n = S n'] for some [n'], and again by
the definition of [double] we have [S (S (double n')) = S (S
(double m'))], which implies by inversion that [double n' = double
m'].
Instantiating the induction hypothesis with [n'] thus allows us to
conclude that [n' = m'], and it follows immediately that [S n' = S
m']. Since [S n' = n] and [S m' = m], this is just what we wanted
to show. [] *)
(** **** Exercise: 3 stars (gen_dep_practice) *)
(** Prove this by induction on [l]. *)
Theorem index_after_last: forall (n : nat) (X : Type) (l : list X),
length l = n ->
index n l = None.
Proof.
intros.
generalize dependent n.
induction l.
reflexivity.
induction n.
intro H.
inversion H.
simpl.
intro H.
inversion H.
rewrite H1.
apply IHl.
apply H1.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (index_after_last_informal) *)
(** Write an informal proof corresponding to your Coq proof
of [index_after_last]:
_Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index n l = None].
_Proof_:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars, optional (gen_dep_practice_more) *)
(** Prove this by induction on [l]. *)
Theorem length_snoc''' : forall (n : nat) (X : Type)
(v : X) (l : list X),
length l = n ->
length (snoc l v) = S n.
Proof.
intros.
generalize dependent n.
generalize dependent v.
induction l.
simpl.
intros.
rewrite <- H.
reflexivity.
simpl.
intros.
apply f_equal.
rewrite <- H.
apply IHl.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (app_length_cons) *)
(** Prove this by induction on [l1], without using [app_length]. *)
Theorem app_length_cons : forall (X : Type) (l1 l2 : list X)
(x : X) (n : nat),
length (l1 ++ (x :: l2)) = n ->
S (length (l1 ++ l2)) = n.
Proof.
intros.
generalize dependent x.
generalize dependent n.
induction l1.
simpl.
intros.
exact H.
intros.
simpl.
destruct n.
inversion H.
apply f_equal.
apply IHl1 with x0.
inversion H.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 4 stars, optional (app_length_twice) *)
(** Prove this by induction on [l], without using app_length. *)
Theorem app_length_twice : forall (X:Type) (n:nat) (l:list X),
length l = n ->
length (l ++ l) = n + n.
Proof.
intros.
generalize dependent n.
induction l.
intros.
simpl.
simpl in H.
rewrite <- H.
reflexivity.
simpl.
intros.
destruct n.
inversion H.
inversion H.
simpl.
apply f_equal.
assert (length (l ++ x :: l) = S(length (l ++ l))).
symmetry.
apply app_length_cons with x.
reflexivity.
rewrite H0.
rewrite H1.
rewrite <- plus_n_Sm.
apply f_equal.
apply IHl.
exact H1.
Qed.
(** [] *)
(* ###################################################### *)
(** * Using [destruct] on Compound Expressions *)
(** We have seen many examples where the [destruct] tactic is
used to perform case analysis of the value of some variable. But
sometimes we need to reason by cases on the result of some
_expression_. We can also do this with [destruct].
Here are some examples: *)
Definition sillyfun (n : nat) : bool :=
if beq_nat n 3 then false
else if beq_nat n 5 then false
else false.
Theorem sillyfun_false : forall (n : nat),
sillyfun n = false.
Proof.
intros n. unfold sillyfun.
destruct (beq_nat n 3).
reflexivity.
destruct (beq_nat n 5).
reflexivity.
reflexivity. Qed.
(** After unfolding [sillyfun] in the above proof, we find that
we are stuck on [if (beq_nat n 3) then ... else ...]. Well,
either [n] is equal to [3] or it isn't, so we use [destruct
(beq_nat n 3)] to let us reason about the two cases.
In general, the [destruct] tactic can be used to perform case
analysis of the results of arbitrary computations. If [e] is an
expression whose type is some inductively defined type [T], then,
for each constructor [c] of [T], [destruct e] generates a subgoal
in which all occurrences of [e] (in the goal and in the context)
are replaced by [c].
*)
(** **** Exercise: 1 star (override_shadow) *)
Theorem override_shadow : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
(override (override f k1 x2) k1 x1) k2 = (override f k1 x1) k2.
Proof.
intros.
unfold override.
destruct (beq_nat k1 k2).
reflexivity.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (combine_split) *)
(** Complete the proof below *)
(**
Theorem combine_split : forall X Y (l : list (X * Y)) l1 l2,
split l = (l1, l2) ->
combine l1 l2 = l.
Proof.
**)
(** [] *)
(** Sometimes, doing a [destruct] on a compound expression (a
non-variable) will erase information we need to complete a proof. *)
(** For example, suppose
we define a function [sillyfun1] like this: *)
Definition sillyfun1 (n : nat) : bool :=
if beq_nat n 3 then true
else if beq_nat n 5 then true
else false.
(** And suppose that we want to convince Coq of the rather
obvious observation that [sillyfun1 n] yields [true] only when [n]
is odd. By analogy with the proofs we did with [sillyfun] above,
it is natural to start the proof like this: *)
Theorem sillyfun1_odd_FAILED : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3).
(* stuck... *)
Abort.
(** We get stuck at this point because the context does not
contain enough information to prove the goal! The problem is that
the substitution peformed by [destruct] is too brutal -- it threw
away every occurrence of [beq_nat n 3], but we need to keep some
memory of this expression and how it was destructed, because we
need to be able to reason that since, in this branch of the case
analysis, [beq_nat n 3 = true], it must be that [n = 3], from
which it follows that [n] is odd.
What we would really like is to substitute away all existing
occurences of [beq_nat n 3], but at the same time add an equation
to the context that records which case we are in. The [eqn:]
qualifier allows us to introduce such an equation (with whatever
name we choose). *)
Theorem sillyfun1_odd : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3) eqn:Heqe3.
(* Now we have the same state as at the point where we got stuck
above, except that the context contains an extra equality
assumption, which is exactly what we need to make progress. *)
Case "e3 = true". apply beq_nat_true in Heqe3.
rewrite -> Heqe3. reflexivity.
Case "e3 = false".
(* When we come to the second equality test in the body of the
function we are reasoning about, we can use [eqn:] again in the
same way, allow us to finish the proof. *)
destruct (beq_nat n 5) eqn:Heqe5.
SCase "e5 = true".
apply beq_nat_true in Heqe5.
rewrite -> Heqe5. reflexivity.
SCase "e5 = false". inversion eq. Qed.
(** **** Exercise: 2 stars (destruct_eqn_practice) *)
Theorem bool_fn_applied_thrice :
forall (f : bool -> bool) (b : bool),
f (f (f b)) = f b.
Proof.
intros.
destruct (f b) eqn:H.
destruct b.
rewrite H.
exact H.
destruct (f true) eqn: H'.
exact H'.
exact H.
destruct b eqn: Hb.
destruct (f false) eqn: Hf.
exact H.
exact Hf.
rewrite H.
exact H.
Qed.
(** [] *)
(** **** Exercise: 2 stars (override_same) *)
Theorem override_same : forall (X:Type) x1 k1 k2 (f : nat->X),
f k1 = x1 ->
(override f k1 x1) k2 = f k2.
Proof.
intros.
unfold override.
destruct (beq_nat k1 k2) eqn: keq.
apply beq_nat_true in keq.
rewrite <- H, keq.
reflexivity.
reflexivity.
Qed.
(** [] *)
(* ################################################################## *)
(** * Review *)
(** We've now seen a bunch of Coq's fundamental tactics. We'll
introduce a few more as we go along through the coming lectures,
and later in the course we'll introduce some more powerful
_automation_ tactics that make Coq do more of the low-level work
in many cases. But basically we've got what we need to get work
done.
Here are the ones we've seen:
- [intros]:
move hypotheses/variables from goal to context
- [reflexivity]:
finish the proof (when the goal looks like [e = e])
- [apply]:
prove goal using a hypothesis, lemma, or constructor
- [apply... in H]:
apply a hypothesis, lemma, or constructor to a hypothesis in
the context (forward reasoning)
- [apply... with...]:
explicitly specify values for variables that cannot be
determined by pattern matching
- [simpl]:
simplify computations in the goal
- [simpl in H]:
... or a hypothesis
- [rewrite]:
use an equality hypothesis (or lemma) to rewrite the goal
- [rewrite ... in H]:
... or a hypothesis
- [symmetry]:
changes a goal of the form [t=u] into [u=t]
- [symmetry in H]:
changes a hypothesis of the form [t=u] into [u=t]
- [unfold]:
replace a defined constant by its right-hand side in the goal
- [unfold... in H]:
... or a hypothesis
- [destruct... as...]:
case analysis on values of inductively defined types
- [destruct... eqn:...]:
specify the name of an equation to be added to the context,
recording the result of the case analysis
- [induction... as...]:
induction on values of inductively defined types
- [inversion]:
reason by injectivity and distinctness of constructors
- [assert (e) as H]:
introduce a "local lemma" [e] and call it [H]
- [generalize dependent x]:
move the variable [x] (and anything else that depends on it)
from the context back to an explicit hypothesis in the goal
formula
*)
(* ###################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (beq_nat_sym) *)
Theorem beq_nat_sym : forall (n m : nat),
beq_nat n m = beq_nat m n.
Proof.
Lemma sym: forall ( n m: nat ) (b:bool),
beq_nat n m = b -> beq_nat m n = b.
Proof.
intro n.
induction n.
intros m b eq.
induction m.
apply eq.
apply eq.
induction m.
intros b eq.
apply eq.
intros b eq.
apply IHn.
apply eq.
Qed.
intros.
destruct (beq_nat m n) eqn: ls.
apply sym.
exact ls.
apply sym.
exact ls.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (beq_nat_sym_informal) *)
(** Give an informal proof of this lemma that corresponds to your
formal proof above:
Theorem: For any [nat]s [n] [m], [beq_nat n m = beq_nat m n].
Proof:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars, optional (beq_nat_trans) *)
Theorem beq_nat_trans : forall n m p,
beq_nat n m = true ->
beq_nat m p = true ->
beq_nat n p = true.
Proof.
intros n m p nm_eq mp_eq.
apply beq_nat_true in nm_eq.
apply beq_nat_true in mp_eq.
rewrite <- mp_eq.
rewrite nm_eq.
symmetry.
apply beq_nat_refl.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (split_combine) *)
(** We have just proven that for all lists of pairs, [combine] is the
inverse of [split]. How would you formalize the statement that
[split] is the inverse of [combine]?
Complete the definition of [split_combine_statement] below with a
property that states that [split] is the inverse of
[combine]. Then, prove that the property holds. (Be sure to leave
your induction hypothesis general by not doing [intros] on more
things than necessary. Hint: what property do you need of [l1]
and [l2] for [split] [combine l1 l2 = (l1,l2)] to be true?) *)
(**
Definition split_combine_statement : Prop :=
(* FILL IN HERE *) Admitted.
Theorem split_combine : split_combine_statement.
Proof.
(* FILL IN HERE *) Admitted.
**)
(** [] *)
(** **** Exercise: 3 stars (override_permute) *)
(**
Theorem override_permute : forall (X:Type) x1 x2 k1 k2 k3 (f : nat->X),
beq_nat k2 k1 = false ->
(override (override f k2 x2) k1 x1) k3 = (override (override f k1 x1) k2 x2) k3.
Proof.
intros.
**)
(** [] *)
(** **** Exercise: 3 stars, advanced (filter_exercise) *)
(** This one is a bit challenging. Pay attention to the form of your IH. *)
(**
Theorem filter_exercise : forall (X : Type) (test : X -> bool)
(x : X) (l lf : list X),
filter test l = x :: lf ->
test x = true.
Proof.
(* FILL IN HERE *) Admitted.
**)
(** [] *)
(** **** Exercise: 4 stars, advanced (forall_exists_challenge) *)
(** Define two recursive [Fixpoints], [forallb] and [existsb]. The
first checks whether every element in a list satisfies a given
predicate:
forallb oddb [1;3;5;7;9] = true
forallb negb [false;false] = true
forallb evenb [0;2;4;5] = false
forallb (beq_nat 5) [] = true
The second checks whether there exists an element in the list that
satisfies a given predicate:
existsb (beq_nat 5) [0;2;3;6] = false
existsb (andb true) [true;true;false] = true
existsb oddb [1;0;0;0;0;3] = true
existsb evenb [] = false
Next, define a _nonrecursive_ version of [existsb] -- call it
[existsb'] -- using [forallb] and [negb].
Prove that [existsb'] and [existsb] have the same behavior.
*)
(* FILL IN HERE *)
(** [] *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top(input clk, stb, di, output do);
localparam integer DIN_N = 160;
localparam integer DOUT_N = 160;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
module roi(input clk, input [159:0] din, output [159:0] dout);
my_RAMB36E2
#(
.LOC("RAMB36_X2Y60"),
.DOA_REG(1'b1),
.DOB_REG(1'b0),
.INIT_A(18'b001000001000010101),
.INIT_B(18'b001111100001101011),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b1),
.IS_RSTRAMB_INVERTED(1'b1),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b1),
.RDADDRCHANGEA("FALSE"),
.RDADDRCHANGEB("FALSE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(4),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(1),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SRVAL_A(18'b110111110110100101),
.SRVAL_B(18'b000001011100001111),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST")
)
inst_0 (
.clk(clk),
.din(din[ 0 +: 24]),
.dout(dout[ 0 +: 8])
);
endmodule
// ---------------------------------------------------------------------
module my_RAMB36E2 (input clk, input [23:0] din, output [7:0] dout);
parameter LOC = "";
parameter DOA_REG = 1'b0;
parameter DOB_REG = 1'b0;
parameter INIT_A = 18'b0;
parameter INIT_B = 18'b0;
parameter IS_CLKARDCLK_INVERTED = 1'b0;
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
parameter IS_ENARDEN_INVERTED = 1'b0;
parameter IS_ENBWREN_INVERTED = 1'b0;
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
parameter RDADDRCHANGEA = "FALSE";
parameter RDADDRCHANGEB = "FALSE";
parameter READ_WIDTH_A = 0;
parameter READ_WIDTH_B = 0;
parameter WRITE_WIDTH_A = 0;
parameter WRITE_WIDTH_B = 0;
parameter RSTREG_PRIORITY_A = "RSTREG";
parameter RSTREG_PRIORITY_B = "RSTREG";
parameter SRVAL_A = 18'b0;
parameter SRVAL_B = 18'b0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
(* LOC=LOC *)
RAMB36E2 #(
.INITP_00(256'b0),
.INITP_01(256'b0),
.INITP_02(256'b0),
.INITP_03(256'b0),
.INITP_04(256'b0),
.INITP_05(256'b0),
.INITP_06(256'b0),
.INITP_07(256'b0),
.INITP_08(256'b0),
.INITP_09(256'b0),
.INITP_0A(256'b0),
.INITP_0B(256'b0),
.INITP_0C(256'b0),
.INITP_0D(256'b0),
.INITP_0E(256'b0),
.INITP_0F(256'b0),
.INIT_00(256'b0),
.INIT_01(256'b0),
.INIT_02(256'b0),
.INIT_03(256'b0),
.INIT_04(256'b0),
.INIT_05(256'b0),
.INIT_06(256'b0),
.INIT_07(256'b0),
.INIT_08(256'b0),
.INIT_09(256'b0),
.INIT_0A(256'b0),
.INIT_0B(256'b0),
.INIT_0C(256'b0),
.INIT_0D(256'b0),
.INIT_0E(256'b0),
.INIT_0F(256'b0),
.INIT_10(256'b0),
.INIT_11(256'b0),
.INIT_12(256'b0),
.INIT_13(256'b0),
.INIT_14(256'b0),
.INIT_15(256'b0),
.INIT_16(256'b0),
.INIT_17(256'b0),
.INIT_18(256'b0),
.INIT_19(256'b0),
.INIT_1A(256'b0),
.INIT_1B(256'b0),
.INIT_1C(256'b0),
.INIT_1D(256'b0),
.INIT_1E(256'b0),
.INIT_1F(256'b0),
.INIT_20(256'b0),
.INIT_21(256'b0),
.INIT_22(256'b0),
.INIT_23(256'b0),
.INIT_24(256'b0),
.INIT_25(256'b0),
.INIT_26(256'b0),
.INIT_27(256'b0),
.INIT_28(256'b0),
.INIT_29(256'b0),
.INIT_2A(256'b0),
.INIT_2B(256'b0),
.INIT_2C(256'b0),
.INIT_2D(256'b0),
.INIT_2E(256'b0),
.INIT_2F(256'b0),
.INIT_30(256'b0),
.INIT_31(256'b0),
.INIT_32(256'b0),
.INIT_33(256'b0),
.INIT_34(256'b0),
.INIT_35(256'b0),
.INIT_36(256'b0),
.INIT_37(256'b0),
.INIT_38(256'b0),
.INIT_39(256'b0),
.INIT_3A(256'b0),
.INIT_3B(256'b0),
.INIT_3C(256'b0),
.INIT_3D(256'b0),
.INIT_3E(256'b0),
.INIT_3F(256'b0),
.INIT_40(256'b0),
.INIT_41(256'b0),
.INIT_42(256'b0),
.INIT_43(256'b0),
.INIT_44(256'b0),
.INIT_45(256'b0),
.INIT_46(256'b0),
.INIT_47(256'b0),
.INIT_48(256'b0),
.INIT_49(256'b0),
.INIT_4A(256'b0),
.INIT_4B(256'b0),
.INIT_4C(256'b0),
.INIT_4D(256'b0),
.INIT_4E(256'b0),
.INIT_4F(256'b0),
.INIT_50(256'b0),
.INIT_51(256'b0),
.INIT_52(256'b0),
.INIT_53(256'b0),
.INIT_54(256'b0),
.INIT_55(256'b0),
.INIT_56(256'b0),
.INIT_57(256'b0),
.INIT_58(256'b0),
.INIT_59(256'b0),
.INIT_5A(256'b0),
.INIT_5B(256'b0),
.INIT_5C(256'b0),
.INIT_5D(256'b0),
.INIT_5E(256'b0),
.INIT_5F(256'b0),
.INIT_60(256'b0),
.INIT_61(256'b0),
.INIT_62(256'b0),
.INIT_63(256'b0),
.INIT_64(256'b0),
.INIT_65(256'b0),
.INIT_66(256'b0),
.INIT_67(256'b0),
.INIT_68(256'b0),
.INIT_69(256'b0),
.INIT_6A(256'b0),
.INIT_6B(256'b0),
.INIT_6C(256'b0),
.INIT_6D(256'b0),
.INIT_6E(256'b0),
.INIT_6F(256'b0),
.INIT_70(256'b0),
.INIT_71(256'b0),
.INIT_72(256'b0),
.INIT_73(256'b0),
.INIT_74(256'b0),
.INIT_75(256'b0),
.INIT_76(256'b0),
.INIT_77(256'b0),
.INIT_78(256'b0),
.INIT_79(256'b0),
.INIT_7A(256'b0),
.INIT_7B(256'b0),
.INIT_7C(256'b0),
.INIT_7D(256'b0),
.INIT_7E(256'b0),
.INIT_7F(256'b0),
.DOA_REG(DOA_REG),
.DOB_REG(DOB_REG),
.INIT_A(INIT_A),
.INIT_B(INIT_B),
.IS_CLKARDCLK_INVERTED(IS_CLKARDCLK_INVERTED),
.IS_CLKBWRCLK_INVERTED(IS_CLKBWRCLK_INVERTED),
.IS_ENARDEN_INVERTED(IS_ENARDEN_INVERTED),
.IS_ENBWREN_INVERTED(IS_ENBWREN_INVERTED),
.IS_RSTRAMARSTRAM_INVERTED(IS_RSTRAMARSTRAM_INVERTED),
.IS_RSTRAMB_INVERTED(IS_RSTRAMB_INVERTED),
.IS_RSTREGARSTREG_INVERTED(IS_RSTREGARSTREG_INVERTED),
.IS_RSTREGB_INVERTED(IS_RSTREGB_INVERTED),
.RDADDRCHANGEA(RDADDRCHANGEA),
.RDADDRCHANGEB(RDADDRCHANGEB),
.READ_WIDTH_A(READ_WIDTH_A),
.READ_WIDTH_B(READ_WIDTH_B),
.WRITE_WIDTH_A(WRITE_WIDTH_A),
.WRITE_WIDTH_B(WRITE_WIDTH_B),
.RSTREG_PRIORITY_A(RSTREG_PRIORITY_A),
.RSTREG_PRIORITY_B(RSTREG_PRIORITY_B),
.SRVAL_A(SRVAL_A),
.SRVAL_B(SRVAL_B),
.WRITE_MODE_A(WRITE_MODE_A),
.WRITE_MODE_B(WRITE_MODE_B)
) ram (
// Port A Address/Control Signals inputs: Port A address and control signals
.ADDRARDADDR(din[0]), // 14-bit input: A/Read port address
.ADDRENA(din[1]), // 1-bit input: Active-High A/Read port address enable
.CLKARDCLK(din[2]), // 1-bit input: A/Read port clock
.ENARDEN(din[3]), // 1-bit input: Port A enable/Read enable
.REGCEAREGCE(din[4]), // 1-bit input: Port A register enable/Register enable
.RSTRAMARSTRAM(din[5]), // 1-bit input: Port A set/reset
.RSTREGARSTREG(din[6]), // 1-bit input: Port A register set/reset
.WEA(1'b0), // 2-bit input: Port A write enable
// Port A Data inputs: Port A data
.DINADIN(din[7]), // 16-bit input: Port A data/LSB data
.DINPADINP(din[8]), // 2-bit input: Port A parity/LSB parity
// Port B Address/Control Signals inputs: Port B address and control signals
.ADDRBWRADDR(din[9]), // 14-bit input: B/Write port address
.ADDRENB(din[10]), // 1-bit input: Active-High B/Write port address enable
.CLKBWRCLK(din[11]), // 1-bit input: B/Write port clock
.ENBWREN(din[12]), // 1-bit input: Port B enable/Write enable
.REGCEB(din[13]), // 1-bit input: Port B register enable
.RSTRAMB(din[14]), // 1-bit input: Port B set/reset
.RSTREGB(din[15]), // 1-bit input: Port B register set/reset
.SLEEP(din[16]), // 1-bit input: Sleep Mode
.WEBWE(din[17]), // 4-bit input: Port B write enable/Write enable
// Port B Data inputs: Port B data
.DINBDIN(din[18]), // 16-bit input: Port B data/MSB data
.DINPBDINP(din[19]), // 2-bit input: Port B parity/MSB parity
// Port A Data outputs: Port A data
.DOUTADOUT(dout[0]), // 16-bit output: Port A data/LSB data
.DOUTPADOUTP(dout[1]), // 2-bit output: Port A parity/LSB parity
// Port B Data outputs: Port B data
.DOUTBDOUT(dout[2]), // 16-bit output: Port B data/MSB data
.DOUTPBDOUTP(dout[3])); // 2-bit output: Port B parity/MSB parity
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:31:09 02/22/2015
// Design Name:
// Module Name: PackAdder
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module PackAdder(
input idle_NormaliseSum,
input [31:0] sout_NormaliseSum,
input [27:0] sum_NormaliseSum,
input clock,
output reg [31:0] sout_PackSum
);
parameter no_idle = 1'b0,
put_idle = 1'b1;
wire s_sign;
wire [7:0] s_exponent;
assign s_sign = sout_NormaliseSum[31];
assign s_exponent = sout_NormaliseSum[30:23];
always @ (posedge clock)
begin
if (idle_NormaliseSum != put_idle) begin
sout_PackSum[22:0] <= sum_NormaliseSum[25:3];
sout_PackSum[30:23] <= s_exponent + 127;
sout_PackSum[31] <= s_sign;
if ($signed(s_exponent) == -126 && sum_NormaliseSum[22] == 0) begin
sout_PackSum[30 : 23] <= 0;
end
if ($signed(s_exponent) <= -126) begin
sout_PackSum[30 : 23] <= 0;
sout_PackSum[22:0] <= 0;
end
//if overflow occurs, return inf
if ($signed(s_exponent) > 127) begin
sout_PackSum[22 : 0] <= 0;
sout_PackSum[30 : 23] <= 255;
sout_PackSum[31] <= s_sign;
end
end
else begin
sout_PackSum <= sout_NormaliseSum;
end
end
endmodule
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: frag_block.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module frag_block (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [5:0] address_a;
input [5:0] address_b;
input clock;
input [15:0] data_a;
input [15:0] data_b;
input wren_a;
input wren_b;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "1024"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "program.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INIT_FILE STRING "program.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "64"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "64"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "6"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "6"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 6 0 INPUT NODEFVAL "address_a[5..0]"
// Retrieval info: USED_PORT: address_b 0 0 6 0 INPUT NODEFVAL "address_b[5..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL "data_a[15..0]"
// Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL "data_b[15..0]"
// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 6 0 address_a 0 0 6 0
// Retrieval info: CONNECT: @address_b 0 0 6 0 address_b 0 0 6 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
// Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL frag_block.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL frag_block.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL frag_block.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL frag_block.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL frag_block_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL frag_block_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211A_PP_SYMBOL_V
`define SKY130_FD_SC_LP__O211A_PP_SYMBOL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o211a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211A_PP_SYMBOL_V
|
`timescale 1 ns / 1 ps
module axi_cfg_register #
(
parameter integer CFG_DATA_WIDTH = 1024,
parameter integer AXI_DATA_WIDTH = 32,
parameter integer AXI_ADDR_WIDTH = 32,
parameter integer CFG_DATA_DEFAULT = 0
)
(
// System signals
input wire aclk,
input wire aresetn,
// Configuration bits
output wire [CFG_DATA_WIDTH-1:0] cfg_data,
// Slave side
input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr, // AXI4-Lite slave: Write address
input wire s_axi_awvalid, // AXI4-Lite slave: Write address valid
output wire s_axi_awready, // AXI4-Lite slave: Write address ready
input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata, // AXI4-Lite slave: Write data
input wire [AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, // AXI4-Lite slave: Write strobe
input wire s_axi_wvalid, // AXI4-Lite slave: Write data valid
output wire s_axi_wready, // AXI4-Lite slave: Write data ready
output wire [1:0] s_axi_bresp, // AXI4-Lite slave: Write response
output wire s_axi_bvalid, // AXI4-Lite slave: Write response valid
input wire s_axi_bready, // AXI4-Lite slave: Write response ready
input wire [AXI_ADDR_WIDTH-1:0] s_axi_araddr, // AXI4-Lite slave: Read address
input wire s_axi_arvalid, // AXI4-Lite slave: Read address valid
output wire s_axi_arready, // AXI4-Lite slave: Read address ready
output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata, // AXI4-Lite slave: Read data
output wire [1:0] s_axi_rresp, // AXI4-Lite slave: Read data response
output wire s_axi_rvalid, // AXI4-Lite slave: Read data valid
input wire s_axi_rready // AXI4-Lite slave: Read data ready
);
function integer clogb2 (input integer value);
for(clogb2 = 0; value > 0; clogb2 = clogb2 + 1) value = value >> 1;
endfunction
localparam integer ADDR_LSB = clogb2(AXI_DATA_WIDTH/8 - 1);
localparam integer CFG_SIZE = CFG_DATA_WIDTH/AXI_DATA_WIDTH;
localparam integer CFG_WIDTH = CFG_SIZE > 1 ? clogb2(CFG_SIZE-1) : 1;
reg int_awready_reg, int_awready_next;
reg int_wready_reg, int_wready_next;
reg int_bvalid_reg, int_bvalid_next;
reg int_arready_reg, int_arready_next;
reg int_rvalid_reg, int_rvalid_next;
reg [AXI_DATA_WIDTH-1:0] int_rdata_reg, int_rdata_next;
wire [AXI_DATA_WIDTH-1:0] int_data_mux [CFG_SIZE-1:0];
wire [CFG_DATA_WIDTH-1:0] int_data_wire;
wire [CFG_SIZE-1:0] int_ce_wire;
wire int_wvalid_wire;
genvar j, k;
assign int_wvalid_wire = s_axi_awvalid & s_axi_wvalid;
generate
for(j = 0; j < CFG_SIZE; j = j + 1)
begin : WORDS
assign int_data_mux[j] = int_data_wire[j*AXI_DATA_WIDTH+AXI_DATA_WIDTH-1:j*AXI_DATA_WIDTH];
assign int_ce_wire[j] = int_wvalid_wire & (s_axi_awaddr[ADDR_LSB+CFG_WIDTH-1:ADDR_LSB] == j);
for(k = 0; k < AXI_DATA_WIDTH; k = k + 1)
begin : BITS
FDRE #(
.INIT(1'b0)
) FDRE_inst (
.CE(int_ce_wire[j] & s_axi_wstrb[k/8]),
.C(aclk),
.R(~aresetn),
.D(s_axi_wdata[k]),
.Q(int_data_wire[j*AXI_DATA_WIDTH + k])
);
end
end
endgenerate
always @(posedge aclk)
begin
if(~aresetn)
begin
int_awready_reg <= 1'b0;
int_wready_reg <= 1'b0;
int_bvalid_reg <= 1'b0;
int_arready_reg <= 1'b0;
int_rvalid_reg <= 1'b0;
int_rdata_reg <= {(AXI_DATA_WIDTH){CFG_DATA_DEFAULT}};
end
else
begin
int_awready_reg <= int_awready_next;
int_wready_reg <= int_wready_next;
int_bvalid_reg <= int_bvalid_next;
int_arready_reg <= int_arready_next;
int_rvalid_reg <= int_rvalid_next;
int_rdata_reg <= int_rdata_next;
end
end
always @*
begin
int_awready_next = int_awready_reg;
int_wready_next = int_wready_reg;
int_bvalid_next = int_bvalid_reg;
if(int_wvalid_wire & ~int_awready_reg)
begin
int_awready_next = 1'b1;
int_wready_next = 1'b1;
end
if(int_awready_reg)
begin
int_awready_next = 1'b0;
int_wready_next = 1'b0;
int_bvalid_next = 1'b1;
end
if(s_axi_bready & int_bvalid_reg)
begin
int_bvalid_next = 1'b0;
end
end
always @*
begin
int_arready_next = int_arready_reg;
int_rvalid_next = int_rvalid_reg;
int_rdata_next = int_rdata_reg;
if(s_axi_arvalid)
begin
int_arready_next = 1'b1;
int_rvalid_next = 1'b1;
int_rdata_next = int_data_mux[s_axi_araddr[ADDR_LSB+CFG_WIDTH-1:ADDR_LSB]];
end
if(int_arready_reg)
begin
int_arready_next = 1'b0;
end
if(s_axi_rready & int_rvalid_reg)
begin
int_rvalid_next = 1'b0;
end
end
assign cfg_data = int_data_wire;
assign s_axi_bresp = 2'd0;
assign s_axi_rresp = 2'd0;
assign s_axi_awready = int_awready_reg;
assign s_axi_wready = int_wready_reg;
assign s_axi_bvalid = int_bvalid_reg;
assign s_axi_arready = int_arready_reg;
assign s_axi_rdata = int_rdata_reg;
assign s_axi_rvalid = int_rvalid_reg;
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module decodes video input streams on the DE boards. *
* *
******************************************************************************/
module Raster_Laser_Projector_video_decoder_0 (
// Inputs
clk,
reset,
TD_CLK27,
TD_DATA,
TD_HS,
TD_VS,
clk27_reset,
stream_out_ready,
// Bidirectional
// Outputs
TD_RESET,
overflow_flag,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IW = 7;
parameter OW = 15;
parameter FW = 17;
parameter PIXELS = 1280;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input TD_CLK27;
input [ 7: 0] TD_DATA;
input TD_HS;
input TD_VS;
input clk27_reset;
input stream_out_ready;
// Bidirectional
// Outputs
output TD_RESET;
output reg overflow_flag;
output [OW: 0] stream_out_data;
output stream_out_startofpacket;
output stream_out_endofpacket;
output stream_out_empty;
output stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire video_clk;
wire video_clk_reset;
wire [OW: 0] decoded_pixel;
wire decoded_startofpacket;
wire decoded_endofpacket;
wire decoded_valid;
wire [FW: 0] data_from_fifo;
wire [ 6: 0] fifo_used_words;
wire [ 6: 0] wrusedw;
wire wrfull;
wire rdempty;
// Internal Registers
reg reached_start_of_frame;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge video_clk)
begin
if (video_clk_reset)
overflow_flag <= 1'b0;
else if (decoded_valid & reached_start_of_frame & wrfull)
overflow_flag <= 1'b1;
end
// Internal Registers
always @(posedge video_clk)
begin
if (video_clk_reset)
reached_start_of_frame <= 1'b0;
else if (decoded_valid & decoded_startofpacket)
reached_start_of_frame <= 1'b1;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign TD_RESET = 1'b1;
assign stream_out_data = data_from_fifo[OW: 0];
assign stream_out_startofpacket = data_from_fifo[(FW - 1)];
assign stream_out_endofpacket = data_from_fifo[FW];
assign stream_out_empty = 1'b0;
assign stream_out_valid = ~rdempty;
// Internal Assignments
assign video_clk = TD_CLK27;
assign video_clk_reset = clk27_reset;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
// NTSC Video In Decoding
altera_up_video_itu_656_decoder ITU_R_656_Decoder (
// Inputs
.clk (video_clk),
.reset (video_clk_reset),
.TD_DATA (TD_DATA),
.ready (decoded_valid & ~wrfull),
// Bidirectionals
// Outputs
.data (decoded_pixel),
.startofpacket (decoded_startofpacket),
.endofpacket (decoded_endofpacket),
.valid (decoded_valid)
);
altera_up_video_dual_clock_fifo Video_In_Dual_Clock_FIFO (
// Inputs
.wrclk (video_clk),
.wrreq (decoded_valid & reached_start_of_frame & ~wrfull),
// .data ({1'b0, decoded_startofpacket, decoded_pixel}),
.data ({decoded_endofpacket, decoded_startofpacket, decoded_pixel}),
.rdclk (clk),
.rdreq (stream_out_valid & stream_out_ready),
// Bidirectionals
// Outputs
.wrusedw (wrusedw),
.wrfull (wrfull),
.q (data_from_fifo),
.rdusedw (fifo_used_words),
.rdempty (rdempty)
);
defparam
Video_In_Dual_Clock_FIFO.DW = (FW + 1);
endmodule
|
//-----------------------------------------------------------------------------
// Title : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper Example Design
// Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// File : v6_emac_v1_5_example_design.v
// Version : 1.5
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Description: This is the Example Design wrapper for the Virtex-6
// Embedded Tri-Mode Ethernet MAC. It is intended that this
// example design can be quickly adapted and downloaded onto an
// FPGA to provide a hardware test environment.
//
// The Example Design wrapper:
//
// * instantiates the EMAC LocalLink-level wrapper (the EMAC
// block-level wrapper with the RX and TX FIFOs and a
// LocalLink interface);
//
// * instantiates a simple example design which provides an
// address swap and loopback function at the user interface;
//
// * instantiates the fundamental clocking resources required
// by the core;
//
// Please refer to the Datasheet, Getting Started Guide, and
// the Virtex-6 Embedded Tri-Mode Ethernet MAC User Gude for
// further information.
//
// ---------------------------------------------------------------------
// |EXAMPLE DESIGN WRAPPER |
// | --------------------------------------------------------|
// | |LOCALLINK-LEVEL WRAPPER |
// | | -----------------------------------------|
// | | |BLOCK-LEVEL WRAPPER |
// | | | --------------------- |
// | -------- | ---------- | | INSTANCE-LEVEL | |
// | | | | | | | | WRAPPER | --------- |
// | | |->|->| |->|--->| Tx Tx |->| |--->|
// | | | | | | | | client PHY | | | |
// | | ADDR | | | LOCAL- | | | I/F I/F | | | |
// | | SWAP | | | LINK | | | | | PHY | |
// | | | | | FIFO | | | | | I/F | |
// | | | | | | | | | | | |
// | | | | | | | | Rx Rx | | | |
// | | | | | | | | client PHY | | | |
// | | |<-|<-| |<-|<---| I/F I/F |<-| |<---|
// | | | | | | | | | --------- |
// | -------- | ---------- | --------------------- |
// | | -----------------------------------------|
// | --------------------------------------------------------|
// ---------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
`timescale 1 ps / 1 ps
//-----------------------------------------------------------------------------
// Module declaration for the example design
//-----------------------------------------------------------------------------
module v6_emac_v1_5_example_design
(
// Client receiver interface
EMACCLIENTRXDVLD,
EMACCLIENTRXFRAMEDROP,
EMACCLIENTRXSTATS,
EMACCLIENTRXSTATSVLD,
EMACCLIENTRXSTATSBYTEVLD,
// Client transmitter interface
CLIENTEMACTXIFGDELAY,
EMACCLIENTTXSTATS,
EMACCLIENTTXSTATSVLD,
EMACCLIENTTXSTATSBYTEVLD,
// MAC control interface
CLIENTEMACPAUSEREQ,
CLIENTEMACPAUSEVAL,
// Clock signal
GTX_CLK,
// GMII interface
GMII_TXD,
GMII_TX_EN,
GMII_TX_ER,
GMII_TX_CLK,
GMII_RXD,
GMII_RX_DV,
GMII_RX_ER,
GMII_RX_CLK,
// Reference clock for IODELAYs
REFCLK,
// Asynchronous reset
RESET
);
//-----------------------------------------------------------------------------
// Port declarations
//-----------------------------------------------------------------------------
// Client receiver interface
output EMACCLIENTRXDVLD;
output EMACCLIENTRXFRAMEDROP;
output [6:0] EMACCLIENTRXSTATS;
output EMACCLIENTRXSTATSVLD;
output EMACCLIENTRXSTATSBYTEVLD;
// Client transmitter interface
input [7:0] CLIENTEMACTXIFGDELAY;
output EMACCLIENTTXSTATS;
output EMACCLIENTTXSTATSVLD;
output EMACCLIENTTXSTATSBYTEVLD;
// MAC control interface
input CLIENTEMACPAUSEREQ;
input [15:0] CLIENTEMACPAUSEVAL;
// Clock signal
input GTX_CLK;
// GMII interface
output [7:0] GMII_TXD;
output GMII_TX_EN;
output GMII_TX_ER;
output GMII_TX_CLK;
input [7:0] GMII_RXD;
input GMII_RX_DV;
input GMII_RX_ER;
input GMII_RX_CLK;
// Reference clock for IODELAYs
input REFCLK;
// Asynchronous reset
input RESET;
//-----------------------------------------------------------------------------
// Wire and register declarations
//-----------------------------------------------------------------------------
// Global asynchronous reset
wire reset_i;
// LocalLink interface clocking signal
wire ll_clk_i;
// Address swap transmitter connections
wire [7:0] tx_ll_data_i;
wire tx_ll_sof_n_i;
wire tx_ll_eof_n_i;
wire tx_ll_src_rdy_n_i;
wire tx_ll_dst_rdy_n_i;
// Address swap receiver connections
wire [7:0] rx_ll_data_i;
wire rx_ll_sof_n_i;
wire rx_ll_eof_n_i;
wire rx_ll_src_rdy_n_i;
wire rx_ll_dst_rdy_n_i;
// Synchronous reset registers in the LocalLink clock domain
(* ASYNC_REG = "TRUE" *)
reg [5:0] ll_pre_reset_i;
reg ll_reset_i;
// Reference clock for IODELAYs
wire refclk_ibufg_i;
wire refclk_bufg_i;
// GMII input clocks to wrappers
(* KEEP = "TRUE" *)
wire tx_clk;
wire rx_clk_i;
wire gmii_rx_clk_bufio;
wire gmii_rx_clk_delay;
// IDELAY controller
reg [12:0] idelayctrl_reset_r;
wire idelayctrl_reset_i;
// GTX reference clock
wire gtx_clk_i;
//-----------------------------------------------------------------------------
// Main body of code
//-----------------------------------------------------------------------------
// Reset input buffer
IBUF reset_ibuf (
.I (RESET),
.O (reset_i)
);
//------------------------------------------------------------------------
// Clock skew management: use IDELAY on GMII_RX_CLK to move
// the clock into proper alignment with the data
//------------------------------------------------------------------------
// Instantiate IDELAYCTRL for the IDELAY in Fixed Tap Delay Mode
(* SYN_NOPRUNE = "TRUE" *)
IDELAYCTRL dlyctrl (
.RDY (),
.REFCLK (refclk_bufg_i),
.RST (idelayctrl_reset_i)
);
// Assert the proper reset pulse for the IDELAYCTRL
always @(posedge refclk_bufg_i, posedge reset_i)
begin
if (reset_i == 1'b1)
begin
idelayctrl_reset_r[0] <= 1'b0;
idelayctrl_reset_r[12:1] <= 12'b111111111111;
end
else
begin
idelayctrl_reset_r[0] <= 1'b0;
idelayctrl_reset_r[12:1] <= idelayctrl_reset_r[11:0];
end
end
assign idelayctrl_reset_i = idelayctrl_reset_r[12];
// Please modify the IDELAY_VALUE to suit your design.
// The IDELAY_VALUE set here is tuned to this example design.
// For more information on IDELAYCTRL and IODELAY, please
// refer to the Virtex-6 User Guide.
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.DELAY_SRC ("I"),
.SIGNAL_PATTERN ("CLOCK"),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
gmii_rxc_delay (
.IDATAIN (GMII_RX_CLK),
.ODATAIN (1'b0),
.DATAOUT (gmii_rx_clk_delay),
.DATAIN (1'b0),
.C (1'b0),
.T (1'b0),
.CE (1'b0),
.INC (1'b0),
.RST (1'b0)
);
// Globally-buffer the GTX reference clock, used to clock
// the transmit-side functions of the EMAC wrappers
// (tx_clk can be shared between multiple EMAC instances, including
// multiple instantiations of the EMAC wrappers)
BUFG bufg_tx (
.I (gtx_clk_i),
.O (tx_clk)
);
// Use a low-skew BUFIO on the delayed RX_CLK, which will be used in the
// GMII phyical interface block to capture incoming data and control.
BUFIO bufio_rx (
.I (gmii_rx_clk_delay),
.O (gmii_rx_clk_bufio)
);
// Regionally-buffer the receive-side GMII physical interface clock
// for use with receive-side functions of the EMAC
BUFR bufr_rx (
.I (gmii_rx_clk_delay),
.O (rx_clk_i),
.CE (1'b1),
.CLR (1'b0)
);
// Clock the LocalLink interface with the globally-buffered
// GTX reference clock
assign ll_clk_i = tx_clk;
//------------------------------------------------------------------------
// Instantiate the LocalLink-level EMAC wrapper (v6_emac_v1_5_locallink.v)
//------------------------------------------------------------------------
v6_emac_v1_5_locallink v6_emac_v1_5_locallink_inst
(
// TX clock output
.TX_CLK_OUT (),
// TX Clock input from BUFG
.TX_CLK (tx_clk),
// LocalLink receiver interface
.RX_LL_CLOCK (ll_clk_i),
.RX_LL_RESET (ll_reset_i),
.RX_LL_DATA (rx_ll_data_i),
.RX_LL_SOF_N (rx_ll_sof_n_i),
.RX_LL_EOF_N (rx_ll_eof_n_i),
.RX_LL_SRC_RDY_N (rx_ll_src_rdy_n_i),
.RX_LL_DST_RDY_N (rx_ll_dst_rdy_n_i),
.RX_LL_FIFO_STATUS (),
// Client receiver signals
.EMACCLIENTRXDVLD (EMACCLIENTRXDVLD),
.EMACCLIENTRXFRAMEDROP (EMACCLIENTRXFRAMEDROP),
.EMACCLIENTRXSTATS (EMACCLIENTRXSTATS),
.EMACCLIENTRXSTATSVLD (EMACCLIENTRXSTATSVLD),
.EMACCLIENTRXSTATSBYTEVLD (EMACCLIENTRXSTATSBYTEVLD),
// LocalLink transmitter interface
.TX_LL_CLOCK (ll_clk_i),
.TX_LL_RESET (ll_reset_i),
.TX_LL_DATA (tx_ll_data_i),
.TX_LL_SOF_N (tx_ll_sof_n_i),
.TX_LL_EOF_N (tx_ll_eof_n_i),
.TX_LL_SRC_RDY_N (tx_ll_src_rdy_n_i),
.TX_LL_DST_RDY_N (tx_ll_dst_rdy_n_i),
// Client transmitter signals
.CLIENTEMACTXIFGDELAY (CLIENTEMACTXIFGDELAY),
.EMACCLIENTTXSTATS (EMACCLIENTTXSTATS),
.EMACCLIENTTXSTATSVLD (EMACCLIENTTXSTATSVLD),
.EMACCLIENTTXSTATSBYTEVLD (EMACCLIENTTXSTATSBYTEVLD),
// MAC control interface
.CLIENTEMACPAUSEREQ (CLIENTEMACPAUSEREQ),
.CLIENTEMACPAUSEVAL (CLIENTEMACPAUSEVAL),
// Receive-side PHY clock on regional buffer, to EMAC
.PHY_RX_CLK (rx_clk_i),
// Reference clock (unused)
.GTX_CLK (1'b0),
// GMII interface
.GMII_TXD (GMII_TXD),
.GMII_TX_EN (GMII_TX_EN),
.GMII_TX_ER (GMII_TX_ER),
.GMII_TX_CLK (GMII_TX_CLK),
.GMII_RXD (GMII_RXD),
.GMII_RX_DV (GMII_RX_DV),
.GMII_RX_ER (GMII_RX_ER),
.GMII_RX_CLK (gmii_rx_clk_bufio),
// Asynchronous reset
.RESET (reset_i)
);
//-------------------------------------------------------------------
// Instatiate the address swapping module
//-------------------------------------------------------------------
address_swap_module_8 client_side_asm (
.rx_ll_clock (ll_clk_i),
.rx_ll_reset (ll_reset_i),
.rx_ll_data_in (rx_ll_data_i),
.rx_ll_sof_in_n (rx_ll_sof_n_i),
.rx_ll_eof_in_n (rx_ll_eof_n_i),
.rx_ll_src_rdy_in_n (rx_ll_src_rdy_n_i),
.rx_ll_data_out (tx_ll_data_i),
.rx_ll_sof_out_n (tx_ll_sof_n_i),
.rx_ll_eof_out_n (tx_ll_eof_n_i),
.rx_ll_src_rdy_out_n (tx_ll_src_rdy_n_i),
.rx_ll_dst_rdy_in_n (tx_ll_dst_rdy_n_i)
);
assign rx_ll_dst_rdy_n_i = tx_ll_dst_rdy_n_i;
// Create synchronous reset in the transmitter clock domain
always @(posedge ll_clk_i, posedge reset_i)
begin
if (reset_i === 1'b1)
begin
ll_pre_reset_i <= 6'h3F;
ll_reset_i <= 1'b1;
end
else
begin
ll_pre_reset_i[0] <= 1'b0;
ll_pre_reset_i[5:1] <= ll_pre_reset_i[4:0];
ll_reset_i <= ll_pre_reset_i[5];
end
end
// Globally-buffer the reference clock used for
// the IODELAYCTRL primitive
IBUFG refclk_ibufg (
.I (REFCLK),
.O (refclk_ibufg_i)
);
BUFG refclk_bufg (
.I (refclk_ibufg_i),
.O (refclk_bufg_i)
);
// Prepare the GTX_CLK for a BUFG
IBUFG gtx_clk_ibufg (
.I (GTX_CLK),
.O (gtx_clk_i)
);
endmodule
|
// megafunction wizard: %altdll%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTDLL
// ============================================================
// File Name: ddr3_s4_uniphy_p0_dll_memphy.v
// Megafunction Name(s):
// ALTDLL
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 208 07/03/2011 SP 1.10 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altdll CBX_AUTO_BLACKBOX="ALL" DELAY_BUFFER_MODE="high" DELAY_CHAIN_LENGTH=8 DELAYCTRLOUT_WIDTH=6 device_family="Stratix IV" DLL_OFFSET_CTRL_A_STATIC_OFFSET="0" DLL_OFFSET_CTRL_A_USE_OFFSET="false" DLL_OFFSET_CTRL_B_STATIC_OFFSET="0" DLL_OFFSET_CTRL_B_USE_OFFSET="false" INPUT_FREQUENCY="1876" JITTER_REDUCTION="true" USE_DLL_OFFSET_CTRL_A="false" USE_DLL_OFFSET_CTRL_B="false" dll_clk dll_delayctrlout
//VERSION_BEGIN 11.0SP1 cbx_altdll 2011:07:03:21:10:32:SJ cbx_mgl 2011:07:03:21:11:41:SJ cbx_stratixiii 2011:07:03:21:10:33:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = stratixiv_dll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module ddr3_s4_uniphy_p0_dll_memphy_altdll_5s51
(
dll_clk,
dll_delayctrlout) ;
input [0:0] dll_clk;
output [5:0] dll_delayctrlout;
wire [5:0] wire_dll_wys_m_delayctrlout;
stratixiv_dll dll_wys_m
(
.clk(dll_clk),
.delayctrlout(wire_dll_wys_m_delayctrlout),
.dqsupdate(),
.offsetdelayctrlclkout(),
.offsetdelayctrlout(),
.upndnout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aload(1'b0),
.upndnin(1'b1),
.upndninclkena(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b0)
// synopsys translate_on
);
defparam
dll_wys_m.delay_buffer_mode = "high",
dll_wys_m.delay_chain_length = 8,
dll_wys_m.input_frequency = "1876 ps",
dll_wys_m.jitter_reduction = "true",
dll_wys_m.static_delay_ctrl = 8,
dll_wys_m.lpm_type = "stratixiv_dll";
assign
dll_delayctrlout = wire_dll_wys_m_delayctrlout;
endmodule //ddr3_s4_uniphy_p0_dll_memphy_altdll_5s51
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ddr3_s4_uniphy_p0_dll_memphy (
dll_clk,
dll_delayctrlout);
input [0:0] dll_clk;
output [5:0] dll_delayctrlout;
wire [5:0] sub_wire0;
wire [5:0] dll_delayctrlout = sub_wire0[5:0];
ddr3_s4_uniphy_p0_dll_memphy_altdll_5s51 ddr3_s4_uniphy_p0_dll_memphy_altdll_5s51_component (
.dll_clk (dll_clk),
.dll_delayctrlout (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: FREQUENCY_UNIT_MODE STRING "MHz"
// Retrieval info: PRIVATE: INPUT_FREQUENCY_PRIVATE_ID NUMERIC "300"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: DELAYCTRLOUT_WIDTH NUMERIC "6"
// Retrieval info: CONSTANT: DELAY_BUFFER_MODE STRING "HIGH"
// Retrieval info: CONSTANT: DELAY_CHAIN_LENGTH NUMERIC "8"
// Retrieval info: CONSTANT: DLL_OFFSET_CTRL_A_STATIC_OFFSET NUMERIC "0"
// Retrieval info: CONSTANT: DLL_OFFSET_CTRL_A_USE_OFFSET STRING "false"
// Retrieval info: CONSTANT: DLL_OFFSET_CTRL_B_STATIC_OFFSET NUMERIC "0"
// Retrieval info: CONSTANT: DLL_OFFSET_CTRL_B_USE_OFFSET STRING "false"
// Retrieval info: CONSTANT: INPUT_FREQUENCY NUMERIC "1876"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: JITTER_REDUCTION STRING "true"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altdll"
// Retrieval info: CONSTANT: USE_DLL_OFFSET_CTRL_A STRING "false"
// Retrieval info: CONSTANT: USE_DLL_OFFSET_CTRL_B STRING "false"
// Retrieval info: USED_PORT: dll_clk 0 0 1 0 INPUT NODEFVAL "dll_clk[0..0]"
// Retrieval info: CONNECT: @dll_clk 0 0 1 0 dll_clk 0 0 1 0
// Retrieval info: USED_PORT: dll_delayctrlout 0 0 6 0 OUTPUT NODEFVAL "dll_delayctrlout[5..0]"
// Retrieval info: CONNECT: dll_delayctrlout 0 0 6 0 @dll_delayctrlout 0 0 6 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_p0_dll_memphy.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_p0_dll_memphy.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_p0_dll_memphy.bsf TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_p0_dll_memphy_inst.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_p0_dll_memphy_bb.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_p0_dll_memphy.inc TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_p0_dll_memphy.cmp TRUE TRUE
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: IPfifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.0.0 Build 614 04/24/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
module IPfifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrempty,
wrusedw);
input aclr;
input [9:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [9:0] q;
output rdempty;
output [13:0] rdusedw;
output wrempty;
output [13:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "8192"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "10"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "1"
// Retrieval info: PRIVATE: output_width NUMERIC "10"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_USEDW_MSB_BIT STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8192"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "14"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 10 0 INPUT NODEFVAL "data[9..0]"
// Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL "q[9..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 14 0 OUTPUT NODEFVAL "rdusedw[13..0]"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 14 0 OUTPUT NODEFVAL "wrusedw[13..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 10 0 data 0 0 10 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 10 0 @q 0 0 10 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 14 0 @rdusedw 0 0 14 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 14 0 @wrusedw 0 0 14 0
// Retrieval info: GEN_FILE: TYPE_NORMAL IPfifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL IPfifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL IPfifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL IPfifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL IPfifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL IPfifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
module idec(aluf,readAddrA,readAddrB, writeAddress,selA,selB,clrR,
clrIr0, gate, rw, sel_addr_reg, dojump, wrAddr,
ir0q,ir1q,flags,reset);
output [3:0] aluf,readAddrA,readAddrB, writeAddress;
output [1:0] selA,selB;
output clrR, clrIr0, gate, rw, sel_addr_reg, dojump,wrAddr ;
input [15:0] ir0q,ir1q;
input [3:0] flags;
input reset;
/* instruction format
ffff dddd ssss m ccc
ffff <- Four bit alu function ir[15:12]
dddd <- four bit destination register adderss and second operand
ssss <- four bit source register address
0 - immidiate data
1 - pc
2 - addressing register for load/store
3 to 15 general registers in reg file
m <- memory indirection bit 1 uses the address from r2
ccc <- condition codes for jump
ccc <-- encoded condition ir[2:0]
unc 000 pos 001
neg 010 zero 011
parodd 100 carry 101
ncarry 110 nzero 111
*/
wire m0 = ir0q[3],
m1 = ir1q[3];
/* jump condition codes in ir[2:0] */
`define unc 3'b000
`define pos 3'b001
`define neg 3'b010
`define zero 3'b011
`define parodd 3'b100
`define carry 3'b101
`define ncarry 3'b110
`define nzero 3'b111
function jmpchk;
input [2:0] condition;
input [3:0] flags;
reg sign,carry,parity,zero;
begin
{sign,carry,parity,zero} = flags;
case (condition)
`unc: jmpchk = 1;
`pos: jmpchk = ~ sign;
`neg: jmpchk = sign;
`zero: jmpchk = zero;
`parodd: jmpchk = parity;
`carry: jmpchk = carry;
`ncarry: jmpchk = ~carry;
`nzero: jmpchk = ~zero;
endcase
end
endfunction
assign #1
// Alu function comes from ir1 always
aluf = ir1q[15:12],
// the sources for the alu come from ir0
readAddrA = ir0q[11:8],
readAddrB = ir0q[ 7:4],
// the destination for the data from the alu is comes from Ir1
writeAddress = ir1q[11:8],
// The Mux selects can be derived from read Addresses
selA = readAddrA[3:2] ? 2'b11 : readAddrA[1:0],
selB = readAddrB[3:2] ? 2'b11 : readAddrB[1:0],
// Data goes to/from memory if the m bit is set when
// ssss == 0000 in ir0 or dddd == 0000 in ir1
sel_addr_reg = (m0 & (ir0q[ 7:4] == 4'b0))
| (m1 & (ir1q[11:8] == 4'b0)) ,
// the read/write signal is low for a memory write which can only occur
// when the instruction in ir1 had a desination or memory
rw = ~(m1 & (ir1q[11:8] == 4'b0)) ,
// When the destination is the PC(1) check the condition flags
dojump = jmpchk(ir1q[2:0],flags) & (ir1q[11:8] == 3'h1),
// If the desitation is the address regster (2) gernate a write for it
wrAddr = (ir1q[11:8] == 3'h2),
// The flag registers are clocked every alu cycle except on move operartions
gate = | ir1q[15:12] ,
// reset and clear signals
clrR = reset,
// Clear the pipeline if we are jumping or if data is coming from memory
// or if writing to memory
clrIr0 = reset | dojump
| ((ir0q[ 7:4] == 4'b0) & (ir0q[ 11:8] != 4'b0))
| ~rw ;
endmodule
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axis_dwidth_converter:1.1
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module daala_zynq_axis_dwidth_converter_1_1 (
aclk,
aresetn,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tlast,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tlast
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
input s_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
output s_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
input [255 : 0] s_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
input s_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
output m_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
input m_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
output [63 : 0] m_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
output m_axis_tlast;
axis_dwidth_converter_v1_1_axis_dwidth_converter #(
.C_FAMILY("zynq"),
.C_S_AXIS_TDATA_WIDTH(256),
.C_M_AXIS_TDATA_WIDTH(64),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_S_AXIS_TUSER_WIDTH(1),
.C_M_AXIS_TUSER_WIDTH(1),
.C_AXIS_SIGNAL_SET('B00010011)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.aclken(1'H1),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tdata(s_axis_tdata),
.s_axis_tstrb(32'HFFFFFFFF),
.s_axis_tkeep(32'HFFFFFFFF),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(1'H0),
.s_axis_tdest(1'H0),
.s_axis_tuser(1'H0),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser()
);
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is a rom for auto initializing the TRDB LCM lcd screen. *
* *
******************************************************************************/
module altera_up_av_config_auto_init_lcm (
// Inputs
rom_address,
// Bidirectionals
// Outputs
rom_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter LCM_INPUT_FORMAT_UB = 8'h00;
parameter LCM_INPUT_FORMAT_LB = 8'h01;
parameter LCM_POWER = 8'h3F;
parameter LCM_DIRECTION_AND_PHASE = 8'h17;
parameter LCM_HORIZONTAL_START_POSITION = 8'h18;
parameter LCM_VERTICAL_START_POSITION = 8'h08;
parameter LCM_ENB_NEGATIVE_POSITION = 8'h00;
parameter LCM_GAIN_OF_CONTRAST = 8'h20;
parameter LCM_R_GAIN_OF_SUB_CONTRAST = 8'h20;
parameter LCM_B_GAIN_OF_SUB_CONTRAST = 8'h20;
parameter LCM_OFFSET_OF_BRIGHTNESS = 8'h10;
parameter LCM_VCOM_HIGH_LEVEL = 8'h3F;
parameter LCM_VCOM_LOW_LEVEL = 8'h3F;
parameter LCM_PCD_HIGH_LEVEL = 8'h2F;
parameter LCM_PCD_LOW_LEVEL = 8'h2F;
parameter LCM_GAMMA_CORRECTION_0 = 8'h98;
parameter LCM_GAMMA_CORRECTION_1 = 8'h9A;
parameter LCM_GAMMA_CORRECTION_2 = 8'hA9;
parameter LCM_GAMMA_CORRECTION_3 = 8'h99;
parameter LCM_GAMMA_CORRECTION_4 = 8'h08;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [ 4: 0] rom_address;
// Bidirectionals
// Outputs
output [15: 0] rom_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
reg [13: 0] data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign rom_data = {data[13: 8], 2'h0,
data[ 7: 0]};
// Internal Assignments
always @(*)
begin
case (rom_address)
0 : data <= {6'h02, LCM_INPUT_FORMAT_UB};
1 : data <= {6'h03, LCM_INPUT_FORMAT_LB};
2 : data <= {6'h04, LCM_POWER};
3 : data <= {6'h05, LCM_DIRECTION_AND_PHASE};
4 : data <= {6'h06, LCM_HORIZONTAL_START_POSITION};
5 : data <= {6'h07, LCM_VERTICAL_START_POSITION};
6 : data <= {6'h08, LCM_ENB_NEGATIVE_POSITION};
7 : data <= {6'h09, LCM_GAIN_OF_CONTRAST};
8 : data <= {6'h0A, LCM_R_GAIN_OF_SUB_CONTRAST};
9 : data <= {6'h0B, LCM_B_GAIN_OF_SUB_CONTRAST};
10 : data <= {6'h0C, LCM_OFFSET_OF_BRIGHTNESS};
11 : data <= {6'h10, LCM_VCOM_HIGH_LEVEL};
12 : data <= {6'h11, LCM_VCOM_LOW_LEVEL};
13 : data <= {6'h12, LCM_PCD_HIGH_LEVEL};
14 : data <= {6'h13, LCM_PCD_LOW_LEVEL};
15 : data <= {6'h14, LCM_GAMMA_CORRECTION_0};
16 : data <= {6'h15, LCM_GAMMA_CORRECTION_1};
17 : data <= {6'h16, LCM_GAMMA_CORRECTION_2};
18 : data <= {6'h17, LCM_GAMMA_CORRECTION_3};
19 : data <= {6'h18, LCM_GAMMA_CORRECTION_4};
default : data <= 14'h0000;
endcase
end
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
//Date : Sat Jun 27 17:24:12 2015
//Host : debian-Miska running 64-bit Debian GNU/Linux 7.8 (wheezy)
//Command : generate_target design_1.bd
//Design : design_1
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
gps_rx,
gps_tx,
gsm_rx,
gsm_tx,
ov7670_data,
ov7670_href,
ov7670_pclk,
ov7670_pwdn,
ov7670_reset,
ov7670_scl,
ov7670_sda,
ov7670_vsync,
ov7670_xclk);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
input gps_rx;
output gps_tx;
input gsm_rx;
output gsm_tx;
input [7:0]ov7670_data;
input ov7670_href;
input ov7670_pclk;
output ov7670_pwdn;
output ov7670_reset;
output ov7670_scl;
inout ov7670_sda;
input ov7670_vsync;
output ov7670_xclk;
wire GND_1;
wire Net;
wire [0:0]S00_ARESETN_1;
wire [31:0]S00_AXI_1_AWADDR;
wire [1:0]S00_AXI_1_AWBURST;
wire [3:0]S00_AXI_1_AWCACHE;
wire [7:0]S00_AXI_1_AWLEN;
wire [2:0]S00_AXI_1_AWPROT;
wire S00_AXI_1_AWREADY;
wire [2:0]S00_AXI_1_AWSIZE;
wire S00_AXI_1_AWVALID;
wire S00_AXI_1_BREADY;
wire [1:0]S00_AXI_1_BRESP;
wire S00_AXI_1_BVALID;
wire [31:0]S00_AXI_1_WDATA;
wire S00_AXI_1_WLAST;
wire S00_AXI_1_WREADY;
wire [3:0]S00_AXI_1_WSTRB;
wire S00_AXI_1_WVALID;
wire VCC_1;
wire [31:0]axi_interconnect_0_M00_AXI_AWADDR;
wire [1:0]axi_interconnect_0_M00_AXI_AWBURST;
wire [3:0]axi_interconnect_0_M00_AXI_AWCACHE;
wire [3:0]axi_interconnect_0_M00_AXI_AWLEN;
wire [1:0]axi_interconnect_0_M00_AXI_AWLOCK;
wire [2:0]axi_interconnect_0_M00_AXI_AWPROT;
wire [3:0]axi_interconnect_0_M00_AXI_AWQOS;
wire axi_interconnect_0_M00_AXI_AWREADY;
wire [2:0]axi_interconnect_0_M00_AXI_AWSIZE;
wire axi_interconnect_0_M00_AXI_AWVALID;
wire axi_interconnect_0_M00_AXI_BREADY;
wire [1:0]axi_interconnect_0_M00_AXI_BRESP;
wire axi_interconnect_0_M00_AXI_BVALID;
wire [63:0]axi_interconnect_0_M00_AXI_WDATA;
wire axi_interconnect_0_M00_AXI_WLAST;
wire axi_interconnect_0_M00_AXI_WREADY;
wire [7:0]axi_interconnect_0_M00_AXI_WSTRB;
wire axi_interconnect_0_M00_AXI_WVALID;
wire axi_uartlite_0_interrupt;
wire axi_uartlite_0_tx;
wire axi_uartlite_1_interrupt;
wire axi_uartlite_1_tx;
wire gps_rx_1;
wire gsm_rx_1;
wire [7:0]ov7670_data_1;
wire ov7670_href_1;
wire ov7670_pclk_1;
wire [23:0]ov7670_top_0_M_AXIS_TDATA;
wire ov7670_top_0_M_AXIS_TLAST;
wire ov7670_top_0_M_AXIS_TREADY;
wire ov7670_top_0_M_AXIS_TUSER;
wire ov7670_top_0_M_AXIS_TVALID;
wire ov7670_top_0_ov7670_reset;
wire ov7670_top_0_pwdn;
wire ov7670_top_0_scl;
wire ov7670_top_0_xclk;
wire ov7670_vsync_1;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FCLK_CLK0;
wire processing_system7_0_FCLK_CLK1;
wire processing_system7_0_FCLK_RESET0_N;
wire processing_system7_0_FCLK_RESET1_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
wire [31:0]processing_system7_0_M_AXI_GP0_ARADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_ARBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_ARCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_ARID;
wire [3:0]processing_system7_0_M_AXI_GP0_ARLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_ARLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_ARPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_ARQOS;
wire processing_system7_0_M_AXI_GP0_ARREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_ARSIZE;
wire processing_system7_0_M_AXI_GP0_ARVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_AWADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_AWBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_AWCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_AWID;
wire [3:0]processing_system7_0_M_AXI_GP0_AWLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_AWLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_AWPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_AWQOS;
wire processing_system7_0_M_AXI_GP0_AWREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_AWSIZE;
wire processing_system7_0_M_AXI_GP0_AWVALID;
wire [11:0]processing_system7_0_M_AXI_GP0_BID;
wire processing_system7_0_M_AXI_GP0_BREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_BRESP;
wire processing_system7_0_M_AXI_GP0_BVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_RDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_RID;
wire processing_system7_0_M_AXI_GP0_RLAST;
wire processing_system7_0_M_AXI_GP0_RREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_RRESP;
wire processing_system7_0_M_AXI_GP0_RVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_WDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_WID;
wire processing_system7_0_M_AXI_GP0_WLAST;
wire processing_system7_0_M_AXI_GP0_WREADY;
wire [3:0]processing_system7_0_M_AXI_GP0_WSTRB;
wire processing_system7_0_M_AXI_GP0_WVALID;
wire [3:0]processing_system7_0_axi_periph_M00_AXI_ARADDR;
wire processing_system7_0_axi_periph_M00_AXI_ARREADY;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_ARVALID;
wire [3:0]processing_system7_0_axi_periph_M00_AXI_AWADDR;
wire processing_system7_0_axi_periph_M00_AXI_AWREADY;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_AWVALID;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M00_AXI_BRESP;
wire processing_system7_0_axi_periph_M00_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_RDATA;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M00_AXI_RRESP;
wire processing_system7_0_axi_periph_M00_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_WDATA;
wire processing_system7_0_axi_periph_M00_AXI_WREADY;
wire [3:0]processing_system7_0_axi_periph_M00_AXI_WSTRB;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_WVALID;
wire [3:0]processing_system7_0_axi_periph_M01_AXI_ARADDR;
wire processing_system7_0_axi_periph_M01_AXI_ARREADY;
wire processing_system7_0_axi_periph_M01_AXI_ARVALID;
wire [3:0]processing_system7_0_axi_periph_M01_AXI_AWADDR;
wire processing_system7_0_axi_periph_M01_AXI_AWREADY;
wire processing_system7_0_axi_periph_M01_AXI_AWVALID;
wire processing_system7_0_axi_periph_M01_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M01_AXI_BRESP;
wire processing_system7_0_axi_periph_M01_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M01_AXI_RDATA;
wire processing_system7_0_axi_periph_M01_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M01_AXI_RRESP;
wire processing_system7_0_axi_periph_M01_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M01_AXI_WDATA;
wire processing_system7_0_axi_periph_M01_AXI_WREADY;
wire [3:0]processing_system7_0_axi_periph_M01_AXI_WSTRB;
wire processing_system7_0_axi_periph_M01_AXI_WVALID;
wire [8:0]processing_system7_0_axi_periph_M02_AXI_ARADDR;
wire processing_system7_0_axi_periph_M02_AXI_ARREADY;
wire processing_system7_0_axi_periph_M02_AXI_ARVALID;
wire [8:0]processing_system7_0_axi_periph_M02_AXI_AWADDR;
wire processing_system7_0_axi_periph_M02_AXI_AWREADY;
wire processing_system7_0_axi_periph_M02_AXI_AWVALID;
wire processing_system7_0_axi_periph_M02_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M02_AXI_BRESP;
wire processing_system7_0_axi_periph_M02_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M02_AXI_RDATA;
wire processing_system7_0_axi_periph_M02_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M02_AXI_RRESP;
wire processing_system7_0_axi_periph_M02_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M02_AXI_WDATA;
wire processing_system7_0_axi_periph_M02_AXI_WREADY;
wire processing_system7_0_axi_periph_M02_AXI_WVALID;
wire [0:0]rst_processing_system7_0_100M_interconnect_aresetn;
wire [0:0]rst_processing_system7_0_100M_peripheral_aresetn;
wire [1:0]xlconcat_0_dout;
assign gps_rx_1 = gps_rx;
assign gps_tx = axi_uartlite_0_tx;
assign gsm_rx_1 = gsm_rx;
assign gsm_tx = axi_uartlite_1_tx;
assign ov7670_data_1 = ov7670_data[7:0];
assign ov7670_href_1 = ov7670_href;
assign ov7670_pclk_1 = ov7670_pclk;
assign ov7670_pwdn = ov7670_top_0_pwdn;
assign ov7670_reset = ov7670_top_0_ov7670_reset;
assign ov7670_scl = ov7670_top_0_scl;
assign ov7670_vsync_1 = ov7670_vsync;
assign ov7670_xclk = ov7670_top_0_xclk;
GND GND
(.G(GND_1));
VCC VCC
(.P(VCC_1));
design_1_axi_interconnect_0_0 axi_interconnect_0
(.ACLK(processing_system7_0_FCLK_CLK0),
.ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M00_ACLK(processing_system7_0_FCLK_CLK1),
.M00_ARESETN(S00_ARESETN_1),
.M00_AXI_awaddr(axi_interconnect_0_M00_AXI_AWADDR),
.M00_AXI_awburst(axi_interconnect_0_M00_AXI_AWBURST),
.M00_AXI_awcache(axi_interconnect_0_M00_AXI_AWCACHE),
.M00_AXI_awlen(axi_interconnect_0_M00_AXI_AWLEN),
.M00_AXI_awlock(axi_interconnect_0_M00_AXI_AWLOCK),
.M00_AXI_awprot(axi_interconnect_0_M00_AXI_AWPROT),
.M00_AXI_awqos(axi_interconnect_0_M00_AXI_AWQOS),
.M00_AXI_awready(axi_interconnect_0_M00_AXI_AWREADY),
.M00_AXI_awsize(axi_interconnect_0_M00_AXI_AWSIZE),
.M00_AXI_awvalid(axi_interconnect_0_M00_AXI_AWVALID),
.M00_AXI_bready(axi_interconnect_0_M00_AXI_BREADY),
.M00_AXI_bresp(axi_interconnect_0_M00_AXI_BRESP),
.M00_AXI_bvalid(axi_interconnect_0_M00_AXI_BVALID),
.M00_AXI_wdata(axi_interconnect_0_M00_AXI_WDATA),
.M00_AXI_wlast(axi_interconnect_0_M00_AXI_WLAST),
.M00_AXI_wready(axi_interconnect_0_M00_AXI_WREADY),
.M00_AXI_wstrb(axi_interconnect_0_M00_AXI_WSTRB),
.M00_AXI_wvalid(axi_interconnect_0_M00_AXI_WVALID),
.S00_ACLK(processing_system7_0_FCLK_CLK1),
.S00_ARESETN(S00_ARESETN_1),
.S00_AXI_awaddr(S00_AXI_1_AWADDR),
.S00_AXI_awburst(S00_AXI_1_AWBURST),
.S00_AXI_awcache(S00_AXI_1_AWCACHE),
.S00_AXI_awlen(S00_AXI_1_AWLEN),
.S00_AXI_awprot(S00_AXI_1_AWPROT),
.S00_AXI_awready(S00_AXI_1_AWREADY),
.S00_AXI_awsize(S00_AXI_1_AWSIZE),
.S00_AXI_awvalid(S00_AXI_1_AWVALID),
.S00_AXI_bready(S00_AXI_1_BREADY),
.S00_AXI_bresp(S00_AXI_1_BRESP),
.S00_AXI_bvalid(S00_AXI_1_BVALID),
.S00_AXI_wdata(S00_AXI_1_WDATA),
.S00_AXI_wlast(S00_AXI_1_WLAST),
.S00_AXI_wready(S00_AXI_1_WREADY),
.S00_AXI_wstrb(S00_AXI_1_WSTRB),
.S00_AXI_wvalid(S00_AXI_1_WVALID));
design_1_axi_uartlite_0_0 axi_uartlite_0
(.interrupt(axi_uartlite_0_interrupt),
.rx(gps_rx_1),
.s_axi_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_araddr(processing_system7_0_axi_periph_M00_AXI_ARADDR),
.s_axi_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.s_axi_arready(processing_system7_0_axi_periph_M00_AXI_ARREADY),
.s_axi_arvalid(processing_system7_0_axi_periph_M00_AXI_ARVALID),
.s_axi_awaddr(processing_system7_0_axi_periph_M00_AXI_AWADDR),
.s_axi_awready(processing_system7_0_axi_periph_M00_AXI_AWREADY),
.s_axi_awvalid(processing_system7_0_axi_periph_M00_AXI_AWVALID),
.s_axi_bready(processing_system7_0_axi_periph_M00_AXI_BREADY),
.s_axi_bresp(processing_system7_0_axi_periph_M00_AXI_BRESP),
.s_axi_bvalid(processing_system7_0_axi_periph_M00_AXI_BVALID),
.s_axi_rdata(processing_system7_0_axi_periph_M00_AXI_RDATA),
.s_axi_rready(processing_system7_0_axi_periph_M00_AXI_RREADY),
.s_axi_rresp(processing_system7_0_axi_periph_M00_AXI_RRESP),
.s_axi_rvalid(processing_system7_0_axi_periph_M00_AXI_RVALID),
.s_axi_wdata(processing_system7_0_axi_periph_M00_AXI_WDATA),
.s_axi_wready(processing_system7_0_axi_periph_M00_AXI_WREADY),
.s_axi_wstrb(processing_system7_0_axi_periph_M00_AXI_WSTRB),
.s_axi_wvalid(processing_system7_0_axi_periph_M00_AXI_WVALID),
.tx(axi_uartlite_0_tx));
design_1_axi_uartlite_1_0 axi_uartlite_1
(.interrupt(axi_uartlite_1_interrupt),
.rx(gsm_rx_1),
.s_axi_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_araddr(processing_system7_0_axi_periph_M01_AXI_ARADDR),
.s_axi_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.s_axi_arready(processing_system7_0_axi_periph_M01_AXI_ARREADY),
.s_axi_arvalid(processing_system7_0_axi_periph_M01_AXI_ARVALID),
.s_axi_awaddr(processing_system7_0_axi_periph_M01_AXI_AWADDR),
.s_axi_awready(processing_system7_0_axi_periph_M01_AXI_AWREADY),
.s_axi_awvalid(processing_system7_0_axi_periph_M01_AXI_AWVALID),
.s_axi_bready(processing_system7_0_axi_periph_M01_AXI_BREADY),
.s_axi_bresp(processing_system7_0_axi_periph_M01_AXI_BRESP),
.s_axi_bvalid(processing_system7_0_axi_periph_M01_AXI_BVALID),
.s_axi_rdata(processing_system7_0_axi_periph_M01_AXI_RDATA),
.s_axi_rready(processing_system7_0_axi_periph_M01_AXI_RREADY),
.s_axi_rresp(processing_system7_0_axi_periph_M01_AXI_RRESP),
.s_axi_rvalid(processing_system7_0_axi_periph_M01_AXI_RVALID),
.s_axi_wdata(processing_system7_0_axi_periph_M01_AXI_WDATA),
.s_axi_wready(processing_system7_0_axi_periph_M01_AXI_WREADY),
.s_axi_wstrb(processing_system7_0_axi_periph_M01_AXI_WSTRB),
.s_axi_wvalid(processing_system7_0_axi_periph_M01_AXI_WVALID),
.tx(axi_uartlite_1_tx));
design_1_axi_vdma_0_0 axi_vdma_0
(.axi_resetn(rst_processing_system7_0_100M_peripheral_aresetn),
.m_axi_s2mm_aclk(processing_system7_0_FCLK_CLK1),
.m_axi_s2mm_awaddr(S00_AXI_1_AWADDR),
.m_axi_s2mm_awburst(S00_AXI_1_AWBURST),
.m_axi_s2mm_awcache(S00_AXI_1_AWCACHE),
.m_axi_s2mm_awlen(S00_AXI_1_AWLEN),
.m_axi_s2mm_awprot(S00_AXI_1_AWPROT),
.m_axi_s2mm_awready(S00_AXI_1_AWREADY),
.m_axi_s2mm_awsize(S00_AXI_1_AWSIZE),
.m_axi_s2mm_awvalid(S00_AXI_1_AWVALID),
.m_axi_s2mm_bready(S00_AXI_1_BREADY),
.m_axi_s2mm_bresp(S00_AXI_1_BRESP),
.m_axi_s2mm_bvalid(S00_AXI_1_BVALID),
.m_axi_s2mm_wdata(S00_AXI_1_WDATA),
.m_axi_s2mm_wlast(S00_AXI_1_WLAST),
.m_axi_s2mm_wready(S00_AXI_1_WREADY),
.m_axi_s2mm_wstrb(S00_AXI_1_WSTRB),
.m_axi_s2mm_wvalid(S00_AXI_1_WVALID),
.s2mm_frame_ptr_in({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.s_axi_lite_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_lite_araddr(processing_system7_0_axi_periph_M02_AXI_ARADDR),
.s_axi_lite_arready(processing_system7_0_axi_periph_M02_AXI_ARREADY),
.s_axi_lite_arvalid(processing_system7_0_axi_periph_M02_AXI_ARVALID),
.s_axi_lite_awaddr(processing_system7_0_axi_periph_M02_AXI_AWADDR),
.s_axi_lite_awready(processing_system7_0_axi_periph_M02_AXI_AWREADY),
.s_axi_lite_awvalid(processing_system7_0_axi_periph_M02_AXI_AWVALID),
.s_axi_lite_bready(processing_system7_0_axi_periph_M02_AXI_BREADY),
.s_axi_lite_bresp(processing_system7_0_axi_periph_M02_AXI_BRESP),
.s_axi_lite_bvalid(processing_system7_0_axi_periph_M02_AXI_BVALID),
.s_axi_lite_rdata(processing_system7_0_axi_periph_M02_AXI_RDATA),
.s_axi_lite_rready(processing_system7_0_axi_periph_M02_AXI_RREADY),
.s_axi_lite_rresp(processing_system7_0_axi_periph_M02_AXI_RRESP),
.s_axi_lite_rvalid(processing_system7_0_axi_periph_M02_AXI_RVALID),
.s_axi_lite_wdata(processing_system7_0_axi_periph_M02_AXI_WDATA),
.s_axi_lite_wready(processing_system7_0_axi_periph_M02_AXI_WREADY),
.s_axi_lite_wvalid(processing_system7_0_axi_periph_M02_AXI_WVALID),
.s_axis_s2mm_aclk(processing_system7_0_FCLK_CLK1),
.s_axis_s2mm_tdata(ov7670_top_0_M_AXIS_TDATA),
.s_axis_s2mm_tkeep({VCC_1,VCC_1,VCC_1}),
.s_axis_s2mm_tlast(ov7670_top_0_M_AXIS_TLAST),
.s_axis_s2mm_tready(ov7670_top_0_M_AXIS_TREADY),
.s_axis_s2mm_tuser(ov7670_top_0_M_AXIS_TUSER),
.s_axis_s2mm_tvalid(ov7670_top_0_M_AXIS_TVALID));
design_1_ov7670_top_0_1 ov7670_top_0
(.M_AXIS_TDATA(ov7670_top_0_M_AXIS_TDATA),
.M_AXIS_TLAST(ov7670_top_0_M_AXIS_TLAST),
.M_AXIS_TREADY(ov7670_top_0_M_AXIS_TREADY),
.M_AXIS_TUSER(ov7670_top_0_M_AXIS_TUSER),
.M_AXIS_TVALID(ov7670_top_0_M_AXIS_TVALID),
.clk(processing_system7_0_FCLK_CLK1),
.data(ov7670_data_1),
.href(ov7670_href_1),
.ov7670_reset(ov7670_top_0_ov7670_reset),
.pclk(ov7670_pclk_1),
.pwdn(ov7670_top_0_pwdn),
.scl(ov7670_top_0_scl),
.sda(ov7670_sda),
.vsync(ov7670_vsync_1),
.xclk(ov7670_top_0_xclk));
design_1_proc_sys_reset_0_0 proc_sys_reset_0
(.aux_reset_in(VCC_1),
.dcm_locked(VCC_1),
.ext_reset_in(processing_system7_0_FCLK_RESET1_N),
.interconnect_aresetn(S00_ARESETN_1),
.mb_debug_sys_rst(GND_1),
.slowest_sync_clk(processing_system7_0_FCLK_CLK1));
design_1_processing_system7_0_0 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.FCLK_CLK0(processing_system7_0_FCLK_CLK0),
.FCLK_CLK1(processing_system7_0_FCLK_CLK1),
.FCLK_RESET0_N(processing_system7_0_FCLK_RESET0_N),
.FCLK_RESET1_N(processing_system7_0_FCLK_RESET1_N),
.I2C0_SCL_I(GND_1),
.I2C0_SDA_I(GND_1),
.IRQ_F2P(xlconcat_0_dout),
.MIO(FIXED_IO_mio[53:0]),
.M_AXI_GP0_ACLK(processing_system7_0_FCLK_CLK0),
.M_AXI_GP0_ARADDR(processing_system7_0_M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(processing_system7_0_M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(processing_system7_0_M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARID(processing_system7_0_M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(processing_system7_0_M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(processing_system7_0_M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(processing_system7_0_M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(processing_system7_0_M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(processing_system7_0_M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(processing_system7_0_M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(processing_system7_0_M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(processing_system7_0_M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(processing_system7_0_M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(processing_system7_0_M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(processing_system7_0_M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(processing_system7_0_M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(processing_system7_0_M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(processing_system7_0_M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(processing_system7_0_M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(processing_system7_0_M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(processing_system7_0_M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(processing_system7_0_M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(processing_system7_0_M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(processing_system7_0_M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(processing_system7_0_M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(processing_system7_0_M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(processing_system7_0_M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(processing_system7_0_M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(processing_system7_0_M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(processing_system7_0_M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(processing_system7_0_M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(processing_system7_0_M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(processing_system7_0_M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(processing_system7_0_M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(processing_system7_0_M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(processing_system7_0_M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(processing_system7_0_M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(processing_system7_0_M_AXI_GP0_WVALID),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb),
.SDIO0_WP(GND_1),
.S_AXI_HP0_ACLK(processing_system7_0_FCLK_CLK1),
.S_AXI_HP0_ARADDR({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.S_AXI_HP0_ARBURST({GND_1,GND_1}),
.S_AXI_HP0_ARCACHE({GND_1,GND_1,GND_1,GND_1}),
.S_AXI_HP0_ARID({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.S_AXI_HP0_ARLEN({GND_1,GND_1,GND_1,GND_1}),
.S_AXI_HP0_ARLOCK({GND_1,GND_1}),
.S_AXI_HP0_ARPROT({GND_1,GND_1,GND_1}),
.S_AXI_HP0_ARQOS({GND_1,GND_1,GND_1,GND_1}),
.S_AXI_HP0_ARSIZE({GND_1,GND_1,GND_1}),
.S_AXI_HP0_ARVALID(GND_1),
.S_AXI_HP0_AWADDR(axi_interconnect_0_M00_AXI_AWADDR),
.S_AXI_HP0_AWBURST(axi_interconnect_0_M00_AXI_AWBURST),
.S_AXI_HP0_AWCACHE(axi_interconnect_0_M00_AXI_AWCACHE),
.S_AXI_HP0_AWID({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.S_AXI_HP0_AWLEN(axi_interconnect_0_M00_AXI_AWLEN),
.S_AXI_HP0_AWLOCK(axi_interconnect_0_M00_AXI_AWLOCK),
.S_AXI_HP0_AWPROT(axi_interconnect_0_M00_AXI_AWPROT),
.S_AXI_HP0_AWQOS(axi_interconnect_0_M00_AXI_AWQOS),
.S_AXI_HP0_AWREADY(axi_interconnect_0_M00_AXI_AWREADY),
.S_AXI_HP0_AWSIZE(axi_interconnect_0_M00_AXI_AWSIZE),
.S_AXI_HP0_AWVALID(axi_interconnect_0_M00_AXI_AWVALID),
.S_AXI_HP0_BREADY(axi_interconnect_0_M00_AXI_BREADY),
.S_AXI_HP0_BRESP(axi_interconnect_0_M00_AXI_BRESP),
.S_AXI_HP0_BVALID(axi_interconnect_0_M00_AXI_BVALID),
.S_AXI_HP0_RDISSUECAP1_EN(GND_1),
.S_AXI_HP0_RREADY(GND_1),
.S_AXI_HP0_WDATA(axi_interconnect_0_M00_AXI_WDATA),
.S_AXI_HP0_WID({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.S_AXI_HP0_WLAST(axi_interconnect_0_M00_AXI_WLAST),
.S_AXI_HP0_WREADY(axi_interconnect_0_M00_AXI_WREADY),
.S_AXI_HP0_WRISSUECAP1_EN(GND_1),
.S_AXI_HP0_WSTRB(axi_interconnect_0_M00_AXI_WSTRB),
.S_AXI_HP0_WVALID(axi_interconnect_0_M00_AXI_WVALID),
.USB0_VBUS_PWRFAULT(GND_1));
design_1_processing_system7_0_axi_periph_0 processing_system7_0_axi_periph
(.ACLK(processing_system7_0_FCLK_CLK0),
.ARESETN(rst_processing_system7_0_100M_interconnect_aresetn),
.M00_ACLK(processing_system7_0_FCLK_CLK0),
.M00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M00_AXI_araddr(processing_system7_0_axi_periph_M00_AXI_ARADDR),
.M00_AXI_arready(processing_system7_0_axi_periph_M00_AXI_ARREADY),
.M00_AXI_arvalid(processing_system7_0_axi_periph_M00_AXI_ARVALID),
.M00_AXI_awaddr(processing_system7_0_axi_periph_M00_AXI_AWADDR),
.M00_AXI_awready(processing_system7_0_axi_periph_M00_AXI_AWREADY),
.M00_AXI_awvalid(processing_system7_0_axi_periph_M00_AXI_AWVALID),
.M00_AXI_bready(processing_system7_0_axi_periph_M00_AXI_BREADY),
.M00_AXI_bresp(processing_system7_0_axi_periph_M00_AXI_BRESP),
.M00_AXI_bvalid(processing_system7_0_axi_periph_M00_AXI_BVALID),
.M00_AXI_rdata(processing_system7_0_axi_periph_M00_AXI_RDATA),
.M00_AXI_rready(processing_system7_0_axi_periph_M00_AXI_RREADY),
.M00_AXI_rresp(processing_system7_0_axi_periph_M00_AXI_RRESP),
.M00_AXI_rvalid(processing_system7_0_axi_periph_M00_AXI_RVALID),
.M00_AXI_wdata(processing_system7_0_axi_periph_M00_AXI_WDATA),
.M00_AXI_wready(processing_system7_0_axi_periph_M00_AXI_WREADY),
.M00_AXI_wstrb(processing_system7_0_axi_periph_M00_AXI_WSTRB),
.M00_AXI_wvalid(processing_system7_0_axi_periph_M00_AXI_WVALID),
.M01_ACLK(processing_system7_0_FCLK_CLK0),
.M01_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M01_AXI_araddr(processing_system7_0_axi_periph_M01_AXI_ARADDR),
.M01_AXI_arready(processing_system7_0_axi_periph_M01_AXI_ARREADY),
.M01_AXI_arvalid(processing_system7_0_axi_periph_M01_AXI_ARVALID),
.M01_AXI_awaddr(processing_system7_0_axi_periph_M01_AXI_AWADDR),
.M01_AXI_awready(processing_system7_0_axi_periph_M01_AXI_AWREADY),
.M01_AXI_awvalid(processing_system7_0_axi_periph_M01_AXI_AWVALID),
.M01_AXI_bready(processing_system7_0_axi_periph_M01_AXI_BREADY),
.M01_AXI_bresp(processing_system7_0_axi_periph_M01_AXI_BRESP),
.M01_AXI_bvalid(processing_system7_0_axi_periph_M01_AXI_BVALID),
.M01_AXI_rdata(processing_system7_0_axi_periph_M01_AXI_RDATA),
.M01_AXI_rready(processing_system7_0_axi_periph_M01_AXI_RREADY),
.M01_AXI_rresp(processing_system7_0_axi_periph_M01_AXI_RRESP),
.M01_AXI_rvalid(processing_system7_0_axi_periph_M01_AXI_RVALID),
.M01_AXI_wdata(processing_system7_0_axi_periph_M01_AXI_WDATA),
.M01_AXI_wready(processing_system7_0_axi_periph_M01_AXI_WREADY),
.M01_AXI_wstrb(processing_system7_0_axi_periph_M01_AXI_WSTRB),
.M01_AXI_wvalid(processing_system7_0_axi_periph_M01_AXI_WVALID),
.M02_ACLK(processing_system7_0_FCLK_CLK0),
.M02_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M02_AXI_araddr(processing_system7_0_axi_periph_M02_AXI_ARADDR),
.M02_AXI_arready(processing_system7_0_axi_periph_M02_AXI_ARREADY),
.M02_AXI_arvalid(processing_system7_0_axi_periph_M02_AXI_ARVALID),
.M02_AXI_awaddr(processing_system7_0_axi_periph_M02_AXI_AWADDR),
.M02_AXI_awready(processing_system7_0_axi_periph_M02_AXI_AWREADY),
.M02_AXI_awvalid(processing_system7_0_axi_periph_M02_AXI_AWVALID),
.M02_AXI_bready(processing_system7_0_axi_periph_M02_AXI_BREADY),
.M02_AXI_bresp(processing_system7_0_axi_periph_M02_AXI_BRESP),
.M02_AXI_bvalid(processing_system7_0_axi_periph_M02_AXI_BVALID),
.M02_AXI_rdata(processing_system7_0_axi_periph_M02_AXI_RDATA),
.M02_AXI_rready(processing_system7_0_axi_periph_M02_AXI_RREADY),
.M02_AXI_rresp(processing_system7_0_axi_periph_M02_AXI_RRESP),
.M02_AXI_rvalid(processing_system7_0_axi_periph_M02_AXI_RVALID),
.M02_AXI_wdata(processing_system7_0_axi_periph_M02_AXI_WDATA),
.M02_AXI_wready(processing_system7_0_axi_periph_M02_AXI_WREADY),
.M02_AXI_wvalid(processing_system7_0_axi_periph_M02_AXI_WVALID),
.S00_ACLK(processing_system7_0_FCLK_CLK0),
.S00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.S00_AXI_araddr(processing_system7_0_M_AXI_GP0_ARADDR),
.S00_AXI_arburst(processing_system7_0_M_AXI_GP0_ARBURST),
.S00_AXI_arcache(processing_system7_0_M_AXI_GP0_ARCACHE),
.S00_AXI_arid(processing_system7_0_M_AXI_GP0_ARID),
.S00_AXI_arlen(processing_system7_0_M_AXI_GP0_ARLEN),
.S00_AXI_arlock(processing_system7_0_M_AXI_GP0_ARLOCK),
.S00_AXI_arprot(processing_system7_0_M_AXI_GP0_ARPROT),
.S00_AXI_arqos(processing_system7_0_M_AXI_GP0_ARQOS),
.S00_AXI_arready(processing_system7_0_M_AXI_GP0_ARREADY),
.S00_AXI_arsize(processing_system7_0_M_AXI_GP0_ARSIZE),
.S00_AXI_arvalid(processing_system7_0_M_AXI_GP0_ARVALID),
.S00_AXI_awaddr(processing_system7_0_M_AXI_GP0_AWADDR),
.S00_AXI_awburst(processing_system7_0_M_AXI_GP0_AWBURST),
.S00_AXI_awcache(processing_system7_0_M_AXI_GP0_AWCACHE),
.S00_AXI_awid(processing_system7_0_M_AXI_GP0_AWID),
.S00_AXI_awlen(processing_system7_0_M_AXI_GP0_AWLEN),
.S00_AXI_awlock(processing_system7_0_M_AXI_GP0_AWLOCK),
.S00_AXI_awprot(processing_system7_0_M_AXI_GP0_AWPROT),
.S00_AXI_awqos(processing_system7_0_M_AXI_GP0_AWQOS),
.S00_AXI_awready(processing_system7_0_M_AXI_GP0_AWREADY),
.S00_AXI_awsize(processing_system7_0_M_AXI_GP0_AWSIZE),
.S00_AXI_awvalid(processing_system7_0_M_AXI_GP0_AWVALID),
.S00_AXI_bid(processing_system7_0_M_AXI_GP0_BID),
.S00_AXI_bready(processing_system7_0_M_AXI_GP0_BREADY),
.S00_AXI_bresp(processing_system7_0_M_AXI_GP0_BRESP),
.S00_AXI_bvalid(processing_system7_0_M_AXI_GP0_BVALID),
.S00_AXI_rdata(processing_system7_0_M_AXI_GP0_RDATA),
.S00_AXI_rid(processing_system7_0_M_AXI_GP0_RID),
.S00_AXI_rlast(processing_system7_0_M_AXI_GP0_RLAST),
.S00_AXI_rready(processing_system7_0_M_AXI_GP0_RREADY),
.S00_AXI_rresp(processing_system7_0_M_AXI_GP0_RRESP),
.S00_AXI_rvalid(processing_system7_0_M_AXI_GP0_RVALID),
.S00_AXI_wdata(processing_system7_0_M_AXI_GP0_WDATA),
.S00_AXI_wid(processing_system7_0_M_AXI_GP0_WID),
.S00_AXI_wlast(processing_system7_0_M_AXI_GP0_WLAST),
.S00_AXI_wready(processing_system7_0_M_AXI_GP0_WREADY),
.S00_AXI_wstrb(processing_system7_0_M_AXI_GP0_WSTRB),
.S00_AXI_wvalid(processing_system7_0_M_AXI_GP0_WVALID));
design_1_rst_processing_system7_0_100M_0 rst_processing_system7_0_100M
(.aux_reset_in(VCC_1),
.dcm_locked(VCC_1),
.ext_reset_in(processing_system7_0_FCLK_RESET0_N),
.interconnect_aresetn(rst_processing_system7_0_100M_interconnect_aresetn),
.mb_debug_sys_rst(GND_1),
.peripheral_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.slowest_sync_clk(processing_system7_0_FCLK_CLK0));
design_1_xlconcat_0_0 xlconcat_0
(.In0(axi_uartlite_1_interrupt),
.In1(axi_uartlite_0_interrupt),
.dout(xlconcat_0_dout));
endmodule
module design_1_axi_interconnect_0_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_awaddr,
M00_AXI_awburst,
M00_AXI_awcache,
M00_AXI_awlen,
M00_AXI_awlock,
M00_AXI_awprot,
M00_AXI_awqos,
M00_AXI_awready,
M00_AXI_awsize,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_wdata,
M00_AXI_wlast,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awlen,
S00_AXI_awprot,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_wdata,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [31:0]M00_AXI_awaddr;
output [1:0]M00_AXI_awburst;
output [3:0]M00_AXI_awcache;
output [3:0]M00_AXI_awlen;
output [1:0]M00_AXI_awlock;
output [2:0]M00_AXI_awprot;
output [3:0]M00_AXI_awqos;
input M00_AXI_awready;
output [2:0]M00_AXI_awsize;
output M00_AXI_awvalid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
output [63:0]M00_AXI_wdata;
output M00_AXI_wlast;
input M00_AXI_wready;
output [7:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [7:0]S00_AXI_awlen;
input [2:0]S00_AXI_awprot;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
input [31:0]S00_AXI_wdata;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire S00_ACLK_1;
wire [0:0]S00_ARESETN_1;
wire axi_interconnect_0_ACLK_net;
wire [0:0]axi_interconnect_0_ARESETN_net;
wire [31:0]axi_interconnect_0_to_s00_couplers_AWADDR;
wire [1:0]axi_interconnect_0_to_s00_couplers_AWBURST;
wire [3:0]axi_interconnect_0_to_s00_couplers_AWCACHE;
wire [7:0]axi_interconnect_0_to_s00_couplers_AWLEN;
wire [2:0]axi_interconnect_0_to_s00_couplers_AWPROT;
wire axi_interconnect_0_to_s00_couplers_AWREADY;
wire [2:0]axi_interconnect_0_to_s00_couplers_AWSIZE;
wire axi_interconnect_0_to_s00_couplers_AWVALID;
wire axi_interconnect_0_to_s00_couplers_BREADY;
wire [1:0]axi_interconnect_0_to_s00_couplers_BRESP;
wire axi_interconnect_0_to_s00_couplers_BVALID;
wire [31:0]axi_interconnect_0_to_s00_couplers_WDATA;
wire axi_interconnect_0_to_s00_couplers_WLAST;
wire axi_interconnect_0_to_s00_couplers_WREADY;
wire [3:0]axi_interconnect_0_to_s00_couplers_WSTRB;
wire axi_interconnect_0_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_axi_interconnect_0_AWADDR;
wire [1:0]s00_couplers_to_axi_interconnect_0_AWBURST;
wire [3:0]s00_couplers_to_axi_interconnect_0_AWCACHE;
wire [3:0]s00_couplers_to_axi_interconnect_0_AWLEN;
wire [1:0]s00_couplers_to_axi_interconnect_0_AWLOCK;
wire [2:0]s00_couplers_to_axi_interconnect_0_AWPROT;
wire [3:0]s00_couplers_to_axi_interconnect_0_AWQOS;
wire s00_couplers_to_axi_interconnect_0_AWREADY;
wire [2:0]s00_couplers_to_axi_interconnect_0_AWSIZE;
wire s00_couplers_to_axi_interconnect_0_AWVALID;
wire s00_couplers_to_axi_interconnect_0_BREADY;
wire [1:0]s00_couplers_to_axi_interconnect_0_BRESP;
wire s00_couplers_to_axi_interconnect_0_BVALID;
wire [63:0]s00_couplers_to_axi_interconnect_0_WDATA;
wire s00_couplers_to_axi_interconnect_0_WLAST;
wire s00_couplers_to_axi_interconnect_0_WREADY;
wire [7:0]s00_couplers_to_axi_interconnect_0_WSTRB;
wire s00_couplers_to_axi_interconnect_0_WVALID;
assign M00_AXI_awaddr[31:0] = s00_couplers_to_axi_interconnect_0_AWADDR;
assign M00_AXI_awburst[1:0] = s00_couplers_to_axi_interconnect_0_AWBURST;
assign M00_AXI_awcache[3:0] = s00_couplers_to_axi_interconnect_0_AWCACHE;
assign M00_AXI_awlen[3:0] = s00_couplers_to_axi_interconnect_0_AWLEN;
assign M00_AXI_awlock[1:0] = s00_couplers_to_axi_interconnect_0_AWLOCK;
assign M00_AXI_awprot[2:0] = s00_couplers_to_axi_interconnect_0_AWPROT;
assign M00_AXI_awqos[3:0] = s00_couplers_to_axi_interconnect_0_AWQOS;
assign M00_AXI_awsize[2:0] = s00_couplers_to_axi_interconnect_0_AWSIZE;
assign M00_AXI_awvalid = s00_couplers_to_axi_interconnect_0_AWVALID;
assign M00_AXI_bready = s00_couplers_to_axi_interconnect_0_BREADY;
assign M00_AXI_wdata[63:0] = s00_couplers_to_axi_interconnect_0_WDATA;
assign M00_AXI_wlast = s00_couplers_to_axi_interconnect_0_WLAST;
assign M00_AXI_wstrb[7:0] = s00_couplers_to_axi_interconnect_0_WSTRB;
assign M00_AXI_wvalid = s00_couplers_to_axi_interconnect_0_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN[0];
assign S00_AXI_awready = axi_interconnect_0_to_s00_couplers_AWREADY;
assign S00_AXI_bresp[1:0] = axi_interconnect_0_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = axi_interconnect_0_to_s00_couplers_BVALID;
assign S00_AXI_wready = axi_interconnect_0_to_s00_couplers_WREADY;
assign axi_interconnect_0_ACLK_net = M00_ACLK;
assign axi_interconnect_0_ARESETN_net = M00_ARESETN[0];
assign axi_interconnect_0_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign axi_interconnect_0_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign axi_interconnect_0_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign axi_interconnect_0_to_s00_couplers_AWLEN = S00_AXI_awlen[7:0];
assign axi_interconnect_0_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign axi_interconnect_0_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign axi_interconnect_0_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign axi_interconnect_0_to_s00_couplers_BREADY = S00_AXI_bready;
assign axi_interconnect_0_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign axi_interconnect_0_to_s00_couplers_WLAST = S00_AXI_wlast;
assign axi_interconnect_0_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign axi_interconnect_0_to_s00_couplers_WVALID = S00_AXI_wvalid;
assign s00_couplers_to_axi_interconnect_0_AWREADY = M00_AXI_awready;
assign s00_couplers_to_axi_interconnect_0_BRESP = M00_AXI_bresp[1:0];
assign s00_couplers_to_axi_interconnect_0_BVALID = M00_AXI_bvalid;
assign s00_couplers_to_axi_interconnect_0_WREADY = M00_AXI_wready;
s00_couplers_imp_O7FAN0 s00_couplers
(.M_ACLK(axi_interconnect_0_ACLK_net),
.M_ARESETN(axi_interconnect_0_ARESETN_net),
.M_AXI_awaddr(s00_couplers_to_axi_interconnect_0_AWADDR),
.M_AXI_awburst(s00_couplers_to_axi_interconnect_0_AWBURST),
.M_AXI_awcache(s00_couplers_to_axi_interconnect_0_AWCACHE),
.M_AXI_awlen(s00_couplers_to_axi_interconnect_0_AWLEN),
.M_AXI_awlock(s00_couplers_to_axi_interconnect_0_AWLOCK),
.M_AXI_awprot(s00_couplers_to_axi_interconnect_0_AWPROT),
.M_AXI_awqos(s00_couplers_to_axi_interconnect_0_AWQOS),
.M_AXI_awready(s00_couplers_to_axi_interconnect_0_AWREADY),
.M_AXI_awsize(s00_couplers_to_axi_interconnect_0_AWSIZE),
.M_AXI_awvalid(s00_couplers_to_axi_interconnect_0_AWVALID),
.M_AXI_bready(s00_couplers_to_axi_interconnect_0_BREADY),
.M_AXI_bresp(s00_couplers_to_axi_interconnect_0_BRESP),
.M_AXI_bvalid(s00_couplers_to_axi_interconnect_0_BVALID),
.M_AXI_wdata(s00_couplers_to_axi_interconnect_0_WDATA),
.M_AXI_wlast(s00_couplers_to_axi_interconnect_0_WLAST),
.M_AXI_wready(s00_couplers_to_axi_interconnect_0_WREADY),
.M_AXI_wstrb(s00_couplers_to_axi_interconnect_0_WSTRB),
.M_AXI_wvalid(s00_couplers_to_axi_interconnect_0_WVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_awaddr(axi_interconnect_0_to_s00_couplers_AWADDR),
.S_AXI_awburst(axi_interconnect_0_to_s00_couplers_AWBURST),
.S_AXI_awcache(axi_interconnect_0_to_s00_couplers_AWCACHE),
.S_AXI_awlen(axi_interconnect_0_to_s00_couplers_AWLEN),
.S_AXI_awprot(axi_interconnect_0_to_s00_couplers_AWPROT),
.S_AXI_awready(axi_interconnect_0_to_s00_couplers_AWREADY),
.S_AXI_awsize(axi_interconnect_0_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(axi_interconnect_0_to_s00_couplers_AWVALID),
.S_AXI_bready(axi_interconnect_0_to_s00_couplers_BREADY),
.S_AXI_bresp(axi_interconnect_0_to_s00_couplers_BRESP),
.S_AXI_bvalid(axi_interconnect_0_to_s00_couplers_BVALID),
.S_AXI_wdata(axi_interconnect_0_to_s00_couplers_WDATA),
.S_AXI_wlast(axi_interconnect_0_to_s00_couplers_WLAST),
.S_AXI_wready(axi_interconnect_0_to_s00_couplers_WREADY),
.S_AXI_wstrb(axi_interconnect_0_to_s00_couplers_WSTRB),
.S_AXI_wvalid(axi_interconnect_0_to_s00_couplers_WVALID));
endmodule
module design_1_processing_system7_0_axi_periph_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arready,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awready,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
M01_ACLK,
M01_ARESETN,
M01_AXI_araddr,
M01_AXI_arready,
M01_AXI_arvalid,
M01_AXI_awaddr,
M01_AXI_awready,
M01_AXI_awvalid,
M01_AXI_bready,
M01_AXI_bresp,
M01_AXI_bvalid,
M01_AXI_rdata,
M01_AXI_rready,
M01_AXI_rresp,
M01_AXI_rvalid,
M01_AXI_wdata,
M01_AXI_wready,
M01_AXI_wstrb,
M01_AXI_wvalid,
M02_ACLK,
M02_ARESETN,
M02_AXI_araddr,
M02_AXI_arready,
M02_AXI_arvalid,
M02_AXI_awaddr,
M02_AXI_awready,
M02_AXI_awvalid,
M02_AXI_bready,
M02_AXI_bresp,
M02_AXI_bvalid,
M02_AXI_rdata,
M02_AXI_rready,
M02_AXI_rresp,
M02_AXI_rvalid,
M02_AXI_wdata,
M02_AXI_wready,
M02_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wid,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [3:0]M00_AXI_araddr;
input [0:0]M00_AXI_arready;
output [0:0]M00_AXI_arvalid;
output [3:0]M00_AXI_awaddr;
input [0:0]M00_AXI_awready;
output [0:0]M00_AXI_awvalid;
output [0:0]M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input [0:0]M00_AXI_bvalid;
input [31:0]M00_AXI_rdata;
output [0:0]M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input [0:0]M00_AXI_rvalid;
output [31:0]M00_AXI_wdata;
input [0:0]M00_AXI_wready;
output [3:0]M00_AXI_wstrb;
output [0:0]M00_AXI_wvalid;
input M01_ACLK;
input [0:0]M01_ARESETN;
output [3:0]M01_AXI_araddr;
input M01_AXI_arready;
output M01_AXI_arvalid;
output [3:0]M01_AXI_awaddr;
input M01_AXI_awready;
output M01_AXI_awvalid;
output M01_AXI_bready;
input [1:0]M01_AXI_bresp;
input M01_AXI_bvalid;
input [31:0]M01_AXI_rdata;
output M01_AXI_rready;
input [1:0]M01_AXI_rresp;
input M01_AXI_rvalid;
output [31:0]M01_AXI_wdata;
input M01_AXI_wready;
output [3:0]M01_AXI_wstrb;
output M01_AXI_wvalid;
input M02_ACLK;
input [0:0]M02_ARESETN;
output [8:0]M02_AXI_araddr;
input M02_AXI_arready;
output M02_AXI_arvalid;
output [8:0]M02_AXI_awaddr;
input M02_AXI_awready;
output M02_AXI_awvalid;
output M02_AXI_bready;
input [1:0]M02_AXI_bresp;
input M02_AXI_bvalid;
input [31:0]M02_AXI_rdata;
output M02_AXI_rready;
input [1:0]M02_AXI_rresp;
input M02_AXI_rvalid;
output [31:0]M02_AXI_wdata;
input M02_AXI_wready;
output M02_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [11:0]S00_AXI_arid;
input [3:0]S00_AXI_arlen;
input [1:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [11:0]S00_AXI_awid;
input [3:0]S00_AXI_awlen;
input [1:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [11:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output [11:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input [11:0]S00_AXI_wid;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire M00_ACLK_1;
wire [0:0]M00_ARESETN_1;
wire M01_ACLK_1;
wire [0:0]M01_ARESETN_1;
wire M02_ACLK_1;
wire [0:0]M02_ARESETN_1;
wire S00_ACLK_1;
wire [0:0]S00_ARESETN_1;
wire [3:0]m00_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [3:0]m00_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m00_couplers_to_processing_system7_0_axi_periph_BRESP;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m00_couplers_to_processing_system7_0_axi_periph_RDATA;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m00_couplers_to_processing_system7_0_axi_periph_RRESP;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m00_couplers_to_processing_system7_0_axi_periph_WDATA;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_WREADY;
wire [3:0]m00_couplers_to_processing_system7_0_axi_periph_WSTRB;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_WVALID;
wire [3:0]m01_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire m01_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire m01_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [3:0]m01_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire m01_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire m01_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire m01_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m01_couplers_to_processing_system7_0_axi_periph_BRESP;
wire m01_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m01_couplers_to_processing_system7_0_axi_periph_RDATA;
wire m01_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m01_couplers_to_processing_system7_0_axi_periph_RRESP;
wire m01_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m01_couplers_to_processing_system7_0_axi_periph_WDATA;
wire m01_couplers_to_processing_system7_0_axi_periph_WREADY;
wire [3:0]m01_couplers_to_processing_system7_0_axi_periph_WSTRB;
wire m01_couplers_to_processing_system7_0_axi_periph_WVALID;
wire [8:0]m02_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire m02_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [8:0]m02_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire m02_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire m02_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m02_couplers_to_processing_system7_0_axi_periph_BRESP;
wire m02_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m02_couplers_to_processing_system7_0_axi_periph_RDATA;
wire m02_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m02_couplers_to_processing_system7_0_axi_periph_RRESP;
wire m02_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m02_couplers_to_processing_system7_0_axi_periph_WDATA;
wire m02_couplers_to_processing_system7_0_axi_periph_WREADY;
wire m02_couplers_to_processing_system7_0_axi_periph_WVALID;
wire processing_system7_0_axi_periph_ACLK_net;
wire [0:0]processing_system7_0_axi_periph_ARESETN_net;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_ARADDR;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_ARBURST;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_ARCACHE;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_ARID;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_ARLEN;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_ARLOCK;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_ARPROT;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_ARQOS;
wire processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_ARSIZE;
wire processing_system7_0_axi_periph_to_s00_couplers_ARVALID;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_AWADDR;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_AWBURST;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_AWCACHE;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_AWID;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_AWLEN;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_AWLOCK;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_AWPROT;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_AWQOS;
wire processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_AWSIZE;
wire processing_system7_0_axi_periph_to_s00_couplers_AWVALID;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_BID;
wire processing_system7_0_axi_periph_to_s00_couplers_BREADY;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_BRESP;
wire processing_system7_0_axi_periph_to_s00_couplers_BVALID;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_RDATA;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_RID;
wire processing_system7_0_axi_periph_to_s00_couplers_RLAST;
wire processing_system7_0_axi_periph_to_s00_couplers_RREADY;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_RRESP;
wire processing_system7_0_axi_periph_to_s00_couplers_RVALID;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_WDATA;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_WID;
wire processing_system7_0_axi_periph_to_s00_couplers_WLAST;
wire processing_system7_0_axi_periph_to_s00_couplers_WREADY;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_WSTRB;
wire processing_system7_0_axi_periph_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_xbar_ARADDR;
wire [2:0]s00_couplers_to_xbar_ARPROT;
wire [0:0]s00_couplers_to_xbar_ARREADY;
wire s00_couplers_to_xbar_ARVALID;
wire [31:0]s00_couplers_to_xbar_AWADDR;
wire [2:0]s00_couplers_to_xbar_AWPROT;
wire [0:0]s00_couplers_to_xbar_AWREADY;
wire s00_couplers_to_xbar_AWVALID;
wire s00_couplers_to_xbar_BREADY;
wire [1:0]s00_couplers_to_xbar_BRESP;
wire [0:0]s00_couplers_to_xbar_BVALID;
wire [31:0]s00_couplers_to_xbar_RDATA;
wire s00_couplers_to_xbar_RREADY;
wire [1:0]s00_couplers_to_xbar_RRESP;
wire [0:0]s00_couplers_to_xbar_RVALID;
wire [31:0]s00_couplers_to_xbar_WDATA;
wire [0:0]s00_couplers_to_xbar_WREADY;
wire [3:0]s00_couplers_to_xbar_WSTRB;
wire s00_couplers_to_xbar_WVALID;
wire [31:0]xbar_to_m00_couplers_ARADDR;
wire [0:0]xbar_to_m00_couplers_ARREADY;
wire [0:0]xbar_to_m00_couplers_ARVALID;
wire [31:0]xbar_to_m00_couplers_AWADDR;
wire [0:0]xbar_to_m00_couplers_AWREADY;
wire [0:0]xbar_to_m00_couplers_AWVALID;
wire [0:0]xbar_to_m00_couplers_BREADY;
wire [1:0]xbar_to_m00_couplers_BRESP;
wire [0:0]xbar_to_m00_couplers_BVALID;
wire [31:0]xbar_to_m00_couplers_RDATA;
wire [0:0]xbar_to_m00_couplers_RREADY;
wire [1:0]xbar_to_m00_couplers_RRESP;
wire [0:0]xbar_to_m00_couplers_RVALID;
wire [31:0]xbar_to_m00_couplers_WDATA;
wire [0:0]xbar_to_m00_couplers_WREADY;
wire [3:0]xbar_to_m00_couplers_WSTRB;
wire [0:0]xbar_to_m00_couplers_WVALID;
wire [63:32]xbar_to_m01_couplers_ARADDR;
wire xbar_to_m01_couplers_ARREADY;
wire [1:1]xbar_to_m01_couplers_ARVALID;
wire [63:32]xbar_to_m01_couplers_AWADDR;
wire xbar_to_m01_couplers_AWREADY;
wire [1:1]xbar_to_m01_couplers_AWVALID;
wire [1:1]xbar_to_m01_couplers_BREADY;
wire [1:0]xbar_to_m01_couplers_BRESP;
wire xbar_to_m01_couplers_BVALID;
wire [31:0]xbar_to_m01_couplers_RDATA;
wire [1:1]xbar_to_m01_couplers_RREADY;
wire [1:0]xbar_to_m01_couplers_RRESP;
wire xbar_to_m01_couplers_RVALID;
wire [63:32]xbar_to_m01_couplers_WDATA;
wire xbar_to_m01_couplers_WREADY;
wire [7:4]xbar_to_m01_couplers_WSTRB;
wire [1:1]xbar_to_m01_couplers_WVALID;
wire [95:64]xbar_to_m02_couplers_ARADDR;
wire xbar_to_m02_couplers_ARREADY;
wire [2:2]xbar_to_m02_couplers_ARVALID;
wire [95:64]xbar_to_m02_couplers_AWADDR;
wire xbar_to_m02_couplers_AWREADY;
wire [2:2]xbar_to_m02_couplers_AWVALID;
wire [2:2]xbar_to_m02_couplers_BREADY;
wire [1:0]xbar_to_m02_couplers_BRESP;
wire xbar_to_m02_couplers_BVALID;
wire [31:0]xbar_to_m02_couplers_RDATA;
wire [2:2]xbar_to_m02_couplers_RREADY;
wire [1:0]xbar_to_m02_couplers_RRESP;
wire xbar_to_m02_couplers_RVALID;
wire [95:64]xbar_to_m02_couplers_WDATA;
wire xbar_to_m02_couplers_WREADY;
wire [2:2]xbar_to_m02_couplers_WVALID;
assign M00_ACLK_1 = M00_ACLK;
assign M00_ARESETN_1 = M00_ARESETN[0];
assign M00_AXI_araddr[3:0] = m00_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M00_AXI_arvalid[0] = m00_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M00_AXI_awaddr[3:0] = m00_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M00_AXI_awvalid[0] = m00_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M00_AXI_bready[0] = m00_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M00_AXI_rready[0] = m00_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M00_AXI_wdata[31:0] = m00_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M00_AXI_wstrb[3:0] = m00_couplers_to_processing_system7_0_axi_periph_WSTRB;
assign M00_AXI_wvalid[0] = m00_couplers_to_processing_system7_0_axi_periph_WVALID;
assign M01_ACLK_1 = M01_ACLK;
assign M01_ARESETN_1 = M01_ARESETN[0];
assign M01_AXI_araddr[3:0] = m01_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M01_AXI_arvalid = m01_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M01_AXI_awaddr[3:0] = m01_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M01_AXI_awvalid = m01_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M01_AXI_bready = m01_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M01_AXI_rready = m01_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M01_AXI_wdata[31:0] = m01_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M01_AXI_wstrb[3:0] = m01_couplers_to_processing_system7_0_axi_periph_WSTRB;
assign M01_AXI_wvalid = m01_couplers_to_processing_system7_0_axi_periph_WVALID;
assign M02_ACLK_1 = M02_ACLK;
assign M02_ARESETN_1 = M02_ARESETN[0];
assign M02_AXI_araddr[8:0] = m02_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M02_AXI_arvalid = m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M02_AXI_awaddr[8:0] = m02_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M02_AXI_awvalid = m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M02_AXI_bready = m02_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M02_AXI_rready = m02_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M02_AXI_wdata[31:0] = m02_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M02_AXI_wvalid = m02_couplers_to_processing_system7_0_axi_periph_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN[0];
assign S00_AXI_arready = processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
assign S00_AXI_awready = processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
assign S00_AXI_bid[11:0] = processing_system7_0_axi_periph_to_s00_couplers_BID;
assign S00_AXI_bresp[1:0] = processing_system7_0_axi_periph_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = processing_system7_0_axi_periph_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = processing_system7_0_axi_periph_to_s00_couplers_RDATA;
assign S00_AXI_rid[11:0] = processing_system7_0_axi_periph_to_s00_couplers_RID;
assign S00_AXI_rlast = processing_system7_0_axi_periph_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = processing_system7_0_axi_periph_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = processing_system7_0_axi_periph_to_s00_couplers_RVALID;
assign S00_AXI_wready = processing_system7_0_axi_periph_to_s00_couplers_WREADY;
assign m00_couplers_to_processing_system7_0_axi_periph_ARREADY = M00_AXI_arready[0];
assign m00_couplers_to_processing_system7_0_axi_periph_AWREADY = M00_AXI_awready[0];
assign m00_couplers_to_processing_system7_0_axi_periph_BRESP = M00_AXI_bresp[1:0];
assign m00_couplers_to_processing_system7_0_axi_periph_BVALID = M00_AXI_bvalid[0];
assign m00_couplers_to_processing_system7_0_axi_periph_RDATA = M00_AXI_rdata[31:0];
assign m00_couplers_to_processing_system7_0_axi_periph_RRESP = M00_AXI_rresp[1:0];
assign m00_couplers_to_processing_system7_0_axi_periph_RVALID = M00_AXI_rvalid[0];
assign m00_couplers_to_processing_system7_0_axi_periph_WREADY = M00_AXI_wready[0];
assign m01_couplers_to_processing_system7_0_axi_periph_ARREADY = M01_AXI_arready;
assign m01_couplers_to_processing_system7_0_axi_periph_AWREADY = M01_AXI_awready;
assign m01_couplers_to_processing_system7_0_axi_periph_BRESP = M01_AXI_bresp[1:0];
assign m01_couplers_to_processing_system7_0_axi_periph_BVALID = M01_AXI_bvalid;
assign m01_couplers_to_processing_system7_0_axi_periph_RDATA = M01_AXI_rdata[31:0];
assign m01_couplers_to_processing_system7_0_axi_periph_RRESP = M01_AXI_rresp[1:0];
assign m01_couplers_to_processing_system7_0_axi_periph_RVALID = M01_AXI_rvalid;
assign m01_couplers_to_processing_system7_0_axi_periph_WREADY = M01_AXI_wready;
assign m02_couplers_to_processing_system7_0_axi_periph_ARREADY = M02_AXI_arready;
assign m02_couplers_to_processing_system7_0_axi_periph_AWREADY = M02_AXI_awready;
assign m02_couplers_to_processing_system7_0_axi_periph_BRESP = M02_AXI_bresp[1:0];
assign m02_couplers_to_processing_system7_0_axi_periph_BVALID = M02_AXI_bvalid;
assign m02_couplers_to_processing_system7_0_axi_periph_RDATA = M02_AXI_rdata[31:0];
assign m02_couplers_to_processing_system7_0_axi_periph_RRESP = M02_AXI_rresp[1:0];
assign m02_couplers_to_processing_system7_0_axi_periph_RVALID = M02_AXI_rvalid;
assign m02_couplers_to_processing_system7_0_axi_periph_WREADY = M02_AXI_wready;
assign processing_system7_0_axi_periph_ACLK_net = ACLK;
assign processing_system7_0_axi_periph_ARESETN_net = ARESETN[0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARID = S00_AXI_arid[11:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign processing_system7_0_axi_periph_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWID = S00_AXI_awid[11:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign processing_system7_0_axi_periph_to_s00_couplers_BREADY = S00_AXI_bready;
assign processing_system7_0_axi_periph_to_s00_couplers_RREADY = S00_AXI_rready;
assign processing_system7_0_axi_periph_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign processing_system7_0_axi_periph_to_s00_couplers_WID = S00_AXI_wid[11:0];
assign processing_system7_0_axi_periph_to_s00_couplers_WLAST = S00_AXI_wlast;
assign processing_system7_0_axi_periph_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_WVALID = S00_AXI_wvalid;
m00_couplers_imp_OBU1DD m00_couplers
(.M_ACLK(M00_ACLK_1),
.M_ARESETN(M00_ARESETN_1),
.M_AXI_araddr(m00_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m00_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m00_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m00_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m00_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m00_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m00_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m00_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m00_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m00_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m00_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m00_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m00_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m00_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m00_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wstrb(m00_couplers_to_processing_system7_0_axi_periph_WSTRB),
.M_AXI_wvalid(m00_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m00_couplers_ARADDR[3:0]),
.S_AXI_arready(xbar_to_m00_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m00_couplers_AWADDR[3:0]),
.S_AXI_awready(xbar_to_m00_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),
.S_AXI_bready(xbar_to_m00_couplers_BREADY),
.S_AXI_bresp(xbar_to_m00_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m00_couplers_BVALID),
.S_AXI_rdata(xbar_to_m00_couplers_RDATA),
.S_AXI_rready(xbar_to_m00_couplers_RREADY),
.S_AXI_rresp(xbar_to_m00_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m00_couplers_RVALID),
.S_AXI_wdata(xbar_to_m00_couplers_WDATA),
.S_AXI_wready(xbar_to_m00_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m00_couplers_WVALID));
m01_couplers_imp_1FBREZ4 m01_couplers
(.M_ACLK(M01_ACLK_1),
.M_ARESETN(M01_ARESETN_1),
.M_AXI_araddr(m01_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m01_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m01_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m01_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m01_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m01_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m01_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m01_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m01_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m01_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m01_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m01_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m01_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m01_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m01_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wstrb(m01_couplers_to_processing_system7_0_axi_periph_WSTRB),
.M_AXI_wvalid(m01_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m01_couplers_ARADDR[35:32]),
.S_AXI_arready(xbar_to_m01_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m01_couplers_AWADDR[35:32]),
.S_AXI_awready(xbar_to_m01_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),
.S_AXI_bready(xbar_to_m01_couplers_BREADY),
.S_AXI_bresp(xbar_to_m01_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m01_couplers_BVALID),
.S_AXI_rdata(xbar_to_m01_couplers_RDATA),
.S_AXI_rready(xbar_to_m01_couplers_RREADY),
.S_AXI_rresp(xbar_to_m01_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m01_couplers_RVALID),
.S_AXI_wdata(xbar_to_m01_couplers_WDATA),
.S_AXI_wready(xbar_to_m01_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m01_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m01_couplers_WVALID));
m02_couplers_imp_MVV5YQ m02_couplers
(.M_ACLK(M02_ACLK_1),
.M_ARESETN(M02_ARESETN_1),
.M_AXI_araddr(m02_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m02_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m02_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m02_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m02_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m02_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m02_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m02_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m02_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m02_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m02_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m02_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m02_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m02_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m02_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wvalid(m02_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m02_couplers_ARADDR[72:64]),
.S_AXI_arready(xbar_to_m02_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m02_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m02_couplers_AWADDR[72:64]),
.S_AXI_awready(xbar_to_m02_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m02_couplers_AWVALID),
.S_AXI_bready(xbar_to_m02_couplers_BREADY),
.S_AXI_bresp(xbar_to_m02_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m02_couplers_BVALID),
.S_AXI_rdata(xbar_to_m02_couplers_RDATA),
.S_AXI_rready(xbar_to_m02_couplers_RREADY),
.S_AXI_rresp(xbar_to_m02_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m02_couplers_RVALID),
.S_AXI_wdata(xbar_to_m02_couplers_WDATA),
.S_AXI_wready(xbar_to_m02_couplers_WREADY),
.S_AXI_wvalid(xbar_to_m02_couplers_WVALID));
s00_couplers_imp_1CFO1MB s00_couplers
(.M_ACLK(processing_system7_0_axi_periph_ACLK_net),
.M_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_xbar_ARADDR),
.M_AXI_arprot(s00_couplers_to_xbar_ARPROT),
.M_AXI_arready(s00_couplers_to_xbar_ARREADY),
.M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),
.M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),
.M_AXI_awprot(s00_couplers_to_xbar_AWPROT),
.M_AXI_awready(s00_couplers_to_xbar_AWREADY),
.M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),
.M_AXI_bready(s00_couplers_to_xbar_BREADY),
.M_AXI_bresp(s00_couplers_to_xbar_BRESP),
.M_AXI_bvalid(s00_couplers_to_xbar_BVALID),
.M_AXI_rdata(s00_couplers_to_xbar_RDATA),
.M_AXI_rready(s00_couplers_to_xbar_RREADY),
.M_AXI_rresp(s00_couplers_to_xbar_RRESP),
.M_AXI_rvalid(s00_couplers_to_xbar_RVALID),
.M_AXI_wdata(s00_couplers_to_xbar_WDATA),
.M_AXI_wready(s00_couplers_to_xbar_WREADY),
.M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),
.M_AXI_wvalid(s00_couplers_to_xbar_WVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_araddr(processing_system7_0_axi_periph_to_s00_couplers_ARADDR),
.S_AXI_arburst(processing_system7_0_axi_periph_to_s00_couplers_ARBURST),
.S_AXI_arcache(processing_system7_0_axi_periph_to_s00_couplers_ARCACHE),
.S_AXI_arid(processing_system7_0_axi_periph_to_s00_couplers_ARID),
.S_AXI_arlen(processing_system7_0_axi_periph_to_s00_couplers_ARLEN),
.S_AXI_arlock(processing_system7_0_axi_periph_to_s00_couplers_ARLOCK),
.S_AXI_arprot(processing_system7_0_axi_periph_to_s00_couplers_ARPROT),
.S_AXI_arqos(processing_system7_0_axi_periph_to_s00_couplers_ARQOS),
.S_AXI_arready(processing_system7_0_axi_periph_to_s00_couplers_ARREADY),
.S_AXI_arsize(processing_system7_0_axi_periph_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(processing_system7_0_axi_periph_to_s00_couplers_ARVALID),
.S_AXI_awaddr(processing_system7_0_axi_periph_to_s00_couplers_AWADDR),
.S_AXI_awburst(processing_system7_0_axi_periph_to_s00_couplers_AWBURST),
.S_AXI_awcache(processing_system7_0_axi_periph_to_s00_couplers_AWCACHE),
.S_AXI_awid(processing_system7_0_axi_periph_to_s00_couplers_AWID),
.S_AXI_awlen(processing_system7_0_axi_periph_to_s00_couplers_AWLEN),
.S_AXI_awlock(processing_system7_0_axi_periph_to_s00_couplers_AWLOCK),
.S_AXI_awprot(processing_system7_0_axi_periph_to_s00_couplers_AWPROT),
.S_AXI_awqos(processing_system7_0_axi_periph_to_s00_couplers_AWQOS),
.S_AXI_awready(processing_system7_0_axi_periph_to_s00_couplers_AWREADY),
.S_AXI_awsize(processing_system7_0_axi_periph_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(processing_system7_0_axi_periph_to_s00_couplers_AWVALID),
.S_AXI_bid(processing_system7_0_axi_periph_to_s00_couplers_BID),
.S_AXI_bready(processing_system7_0_axi_periph_to_s00_couplers_BREADY),
.S_AXI_bresp(processing_system7_0_axi_periph_to_s00_couplers_BRESP),
.S_AXI_bvalid(processing_system7_0_axi_periph_to_s00_couplers_BVALID),
.S_AXI_rdata(processing_system7_0_axi_periph_to_s00_couplers_RDATA),
.S_AXI_rid(processing_system7_0_axi_periph_to_s00_couplers_RID),
.S_AXI_rlast(processing_system7_0_axi_periph_to_s00_couplers_RLAST),
.S_AXI_rready(processing_system7_0_axi_periph_to_s00_couplers_RREADY),
.S_AXI_rresp(processing_system7_0_axi_periph_to_s00_couplers_RRESP),
.S_AXI_rvalid(processing_system7_0_axi_periph_to_s00_couplers_RVALID),
.S_AXI_wdata(processing_system7_0_axi_periph_to_s00_couplers_WDATA),
.S_AXI_wid(processing_system7_0_axi_periph_to_s00_couplers_WID),
.S_AXI_wlast(processing_system7_0_axi_periph_to_s00_couplers_WLAST),
.S_AXI_wready(processing_system7_0_axi_periph_to_s00_couplers_WREADY),
.S_AXI_wstrb(processing_system7_0_axi_periph_to_s00_couplers_WSTRB),
.S_AXI_wvalid(processing_system7_0_axi_periph_to_s00_couplers_WVALID));
design_1_xbar_0 xbar
(.aclk(processing_system7_0_axi_periph_ACLK_net),
.aresetn(processing_system7_0_axi_periph_ARESETN_net),
.m_axi_araddr({xbar_to_m02_couplers_ARADDR,xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),
.m_axi_arready({xbar_to_m02_couplers_ARREADY,xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),
.m_axi_arvalid({xbar_to_m02_couplers_ARVALID,xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),
.m_axi_awaddr({xbar_to_m02_couplers_AWADDR,xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),
.m_axi_awready({xbar_to_m02_couplers_AWREADY,xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),
.m_axi_awvalid({xbar_to_m02_couplers_AWVALID,xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),
.m_axi_bready({xbar_to_m02_couplers_BREADY,xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),
.m_axi_bresp({xbar_to_m02_couplers_BRESP,xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}),
.m_axi_bvalid({xbar_to_m02_couplers_BVALID,xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),
.m_axi_rdata({xbar_to_m02_couplers_RDATA,xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}),
.m_axi_rready({xbar_to_m02_couplers_RREADY,xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),
.m_axi_rresp({xbar_to_m02_couplers_RRESP,xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}),
.m_axi_rvalid({xbar_to_m02_couplers_RVALID,xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),
.m_axi_wdata({xbar_to_m02_couplers_WDATA,xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),
.m_axi_wready({xbar_to_m02_couplers_WREADY,xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),
.m_axi_wstrb({xbar_to_m01_couplers_WSTRB,xbar_to_m00_couplers_WSTRB}),
.m_axi_wvalid({xbar_to_m02_couplers_WVALID,xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),
.s_axi_araddr(s00_couplers_to_xbar_ARADDR),
.s_axi_arprot(s00_couplers_to_xbar_ARPROT),
.s_axi_arready(s00_couplers_to_xbar_ARREADY),
.s_axi_arvalid(s00_couplers_to_xbar_ARVALID),
.s_axi_awaddr(s00_couplers_to_xbar_AWADDR),
.s_axi_awprot(s00_couplers_to_xbar_AWPROT),
.s_axi_awready(s00_couplers_to_xbar_AWREADY),
.s_axi_awvalid(s00_couplers_to_xbar_AWVALID),
.s_axi_bready(s00_couplers_to_xbar_BREADY),
.s_axi_bresp(s00_couplers_to_xbar_BRESP),
.s_axi_bvalid(s00_couplers_to_xbar_BVALID),
.s_axi_rdata(s00_couplers_to_xbar_RDATA),
.s_axi_rready(s00_couplers_to_xbar_RREADY),
.s_axi_rresp(s00_couplers_to_xbar_RRESP),
.s_axi_rvalid(s00_couplers_to_xbar_RVALID),
.s_axi_wdata(s00_couplers_to_xbar_WDATA),
.s_axi_wready(s00_couplers_to_xbar_WREADY),
.s_axi_wstrb(s00_couplers_to_xbar_WSTRB),
.s_axi_wvalid(s00_couplers_to_xbar_WVALID));
endmodule
module m00_couplers_imp_OBU1DD
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [3:0]M_AXI_araddr;
input [0:0]M_AXI_arready;
output [0:0]M_AXI_arvalid;
output [3:0]M_AXI_awaddr;
input [0:0]M_AXI_awready;
output [0:0]M_AXI_awvalid;
output [0:0]M_AXI_bready;
input [1:0]M_AXI_bresp;
input [0:0]M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output [0:0]M_AXI_rready;
input [1:0]M_AXI_rresp;
input [0:0]M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input [0:0]M_AXI_wready;
output [3:0]M_AXI_wstrb;
output [0:0]M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [3:0]S_AXI_araddr;
output [0:0]S_AXI_arready;
input [0:0]S_AXI_arvalid;
input [3:0]S_AXI_awaddr;
output [0:0]S_AXI_awready;
input [0:0]S_AXI_awvalid;
input [0:0]S_AXI_bready;
output [1:0]S_AXI_bresp;
output [0:0]S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input [0:0]S_AXI_rready;
output [1:0]S_AXI_rresp;
output [0:0]S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output [0:0]S_AXI_wready;
input [3:0]S_AXI_wstrb;
input [0:0]S_AXI_wvalid;
wire [3:0]m00_couplers_to_m00_couplers_ARADDR;
wire [0:0]m00_couplers_to_m00_couplers_ARREADY;
wire [0:0]m00_couplers_to_m00_couplers_ARVALID;
wire [3:0]m00_couplers_to_m00_couplers_AWADDR;
wire [0:0]m00_couplers_to_m00_couplers_AWREADY;
wire [0:0]m00_couplers_to_m00_couplers_AWVALID;
wire [0:0]m00_couplers_to_m00_couplers_BREADY;
wire [1:0]m00_couplers_to_m00_couplers_BRESP;
wire [0:0]m00_couplers_to_m00_couplers_BVALID;
wire [31:0]m00_couplers_to_m00_couplers_RDATA;
wire [0:0]m00_couplers_to_m00_couplers_RREADY;
wire [1:0]m00_couplers_to_m00_couplers_RRESP;
wire [0:0]m00_couplers_to_m00_couplers_RVALID;
wire [31:0]m00_couplers_to_m00_couplers_WDATA;
wire [0:0]m00_couplers_to_m00_couplers_WREADY;
wire [3:0]m00_couplers_to_m00_couplers_WSTRB;
wire [0:0]m00_couplers_to_m00_couplers_WVALID;
assign M_AXI_araddr[3:0] = m00_couplers_to_m00_couplers_ARADDR;
assign M_AXI_arvalid[0] = m00_couplers_to_m00_couplers_ARVALID;
assign M_AXI_awaddr[3:0] = m00_couplers_to_m00_couplers_AWADDR;
assign M_AXI_awvalid[0] = m00_couplers_to_m00_couplers_AWVALID;
assign M_AXI_bready[0] = m00_couplers_to_m00_couplers_BREADY;
assign M_AXI_rready[0] = m00_couplers_to_m00_couplers_RREADY;
assign M_AXI_wdata[31:0] = m00_couplers_to_m00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = m00_couplers_to_m00_couplers_WSTRB;
assign M_AXI_wvalid[0] = m00_couplers_to_m00_couplers_WVALID;
assign S_AXI_arready[0] = m00_couplers_to_m00_couplers_ARREADY;
assign S_AXI_awready[0] = m00_couplers_to_m00_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m00_couplers_to_m00_couplers_BRESP;
assign S_AXI_bvalid[0] = m00_couplers_to_m00_couplers_BVALID;
assign S_AXI_rdata[31:0] = m00_couplers_to_m00_couplers_RDATA;
assign S_AXI_rresp[1:0] = m00_couplers_to_m00_couplers_RRESP;
assign S_AXI_rvalid[0] = m00_couplers_to_m00_couplers_RVALID;
assign S_AXI_wready[0] = m00_couplers_to_m00_couplers_WREADY;
assign m00_couplers_to_m00_couplers_ARADDR = S_AXI_araddr[3:0];
assign m00_couplers_to_m00_couplers_ARREADY = M_AXI_arready[0];
assign m00_couplers_to_m00_couplers_ARVALID = S_AXI_arvalid[0];
assign m00_couplers_to_m00_couplers_AWADDR = S_AXI_awaddr[3:0];
assign m00_couplers_to_m00_couplers_AWREADY = M_AXI_awready[0];
assign m00_couplers_to_m00_couplers_AWVALID = S_AXI_awvalid[0];
assign m00_couplers_to_m00_couplers_BREADY = S_AXI_bready[0];
assign m00_couplers_to_m00_couplers_BRESP = M_AXI_bresp[1:0];
assign m00_couplers_to_m00_couplers_BVALID = M_AXI_bvalid[0];
assign m00_couplers_to_m00_couplers_RDATA = M_AXI_rdata[31:0];
assign m00_couplers_to_m00_couplers_RREADY = S_AXI_rready[0];
assign m00_couplers_to_m00_couplers_RRESP = M_AXI_rresp[1:0];
assign m00_couplers_to_m00_couplers_RVALID = M_AXI_rvalid[0];
assign m00_couplers_to_m00_couplers_WDATA = S_AXI_wdata[31:0];
assign m00_couplers_to_m00_couplers_WREADY = M_AXI_wready[0];
assign m00_couplers_to_m00_couplers_WSTRB = S_AXI_wstrb[3:0];
assign m00_couplers_to_m00_couplers_WVALID = S_AXI_wvalid[0];
endmodule
module m01_couplers_imp_1FBREZ4
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [3:0]M_AXI_araddr;
input M_AXI_arready;
output M_AXI_arvalid;
output [3:0]M_AXI_awaddr;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [3:0]S_AXI_araddr;
output S_AXI_arready;
input S_AXI_arvalid;
input [3:0]S_AXI_awaddr;
output S_AXI_awready;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire [3:0]m01_couplers_to_m01_couplers_ARADDR;
wire m01_couplers_to_m01_couplers_ARREADY;
wire m01_couplers_to_m01_couplers_ARVALID;
wire [3:0]m01_couplers_to_m01_couplers_AWADDR;
wire m01_couplers_to_m01_couplers_AWREADY;
wire m01_couplers_to_m01_couplers_AWVALID;
wire m01_couplers_to_m01_couplers_BREADY;
wire [1:0]m01_couplers_to_m01_couplers_BRESP;
wire m01_couplers_to_m01_couplers_BVALID;
wire [31:0]m01_couplers_to_m01_couplers_RDATA;
wire m01_couplers_to_m01_couplers_RREADY;
wire [1:0]m01_couplers_to_m01_couplers_RRESP;
wire m01_couplers_to_m01_couplers_RVALID;
wire [31:0]m01_couplers_to_m01_couplers_WDATA;
wire m01_couplers_to_m01_couplers_WREADY;
wire [3:0]m01_couplers_to_m01_couplers_WSTRB;
wire m01_couplers_to_m01_couplers_WVALID;
assign M_AXI_araddr[3:0] = m01_couplers_to_m01_couplers_ARADDR;
assign M_AXI_arvalid = m01_couplers_to_m01_couplers_ARVALID;
assign M_AXI_awaddr[3:0] = m01_couplers_to_m01_couplers_AWADDR;
assign M_AXI_awvalid = m01_couplers_to_m01_couplers_AWVALID;
assign M_AXI_bready = m01_couplers_to_m01_couplers_BREADY;
assign M_AXI_rready = m01_couplers_to_m01_couplers_RREADY;
assign M_AXI_wdata[31:0] = m01_couplers_to_m01_couplers_WDATA;
assign M_AXI_wstrb[3:0] = m01_couplers_to_m01_couplers_WSTRB;
assign M_AXI_wvalid = m01_couplers_to_m01_couplers_WVALID;
assign S_AXI_arready = m01_couplers_to_m01_couplers_ARREADY;
assign S_AXI_awready = m01_couplers_to_m01_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m01_couplers_to_m01_couplers_BRESP;
assign S_AXI_bvalid = m01_couplers_to_m01_couplers_BVALID;
assign S_AXI_rdata[31:0] = m01_couplers_to_m01_couplers_RDATA;
assign S_AXI_rresp[1:0] = m01_couplers_to_m01_couplers_RRESP;
assign S_AXI_rvalid = m01_couplers_to_m01_couplers_RVALID;
assign S_AXI_wready = m01_couplers_to_m01_couplers_WREADY;
assign m01_couplers_to_m01_couplers_ARADDR = S_AXI_araddr[3:0];
assign m01_couplers_to_m01_couplers_ARREADY = M_AXI_arready;
assign m01_couplers_to_m01_couplers_ARVALID = S_AXI_arvalid;
assign m01_couplers_to_m01_couplers_AWADDR = S_AXI_awaddr[3:0];
assign m01_couplers_to_m01_couplers_AWREADY = M_AXI_awready;
assign m01_couplers_to_m01_couplers_AWVALID = S_AXI_awvalid;
assign m01_couplers_to_m01_couplers_BREADY = S_AXI_bready;
assign m01_couplers_to_m01_couplers_BRESP = M_AXI_bresp[1:0];
assign m01_couplers_to_m01_couplers_BVALID = M_AXI_bvalid;
assign m01_couplers_to_m01_couplers_RDATA = M_AXI_rdata[31:0];
assign m01_couplers_to_m01_couplers_RREADY = S_AXI_rready;
assign m01_couplers_to_m01_couplers_RRESP = M_AXI_rresp[1:0];
assign m01_couplers_to_m01_couplers_RVALID = M_AXI_rvalid;
assign m01_couplers_to_m01_couplers_WDATA = S_AXI_wdata[31:0];
assign m01_couplers_to_m01_couplers_WREADY = M_AXI_wready;
assign m01_couplers_to_m01_couplers_WSTRB = S_AXI_wstrb[3:0];
assign m01_couplers_to_m01_couplers_WVALID = S_AXI_wvalid;
endmodule
module m02_couplers_imp_MVV5YQ
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [8:0]M_AXI_araddr;
input M_AXI_arready;
output M_AXI_arvalid;
output [8:0]M_AXI_awaddr;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [8:0]S_AXI_araddr;
output S_AXI_arready;
input S_AXI_arvalid;
input [8:0]S_AXI_awaddr;
output S_AXI_awready;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output S_AXI_wready;
input S_AXI_wvalid;
wire [8:0]m02_couplers_to_m02_couplers_ARADDR;
wire m02_couplers_to_m02_couplers_ARREADY;
wire m02_couplers_to_m02_couplers_ARVALID;
wire [8:0]m02_couplers_to_m02_couplers_AWADDR;
wire m02_couplers_to_m02_couplers_AWREADY;
wire m02_couplers_to_m02_couplers_AWVALID;
wire m02_couplers_to_m02_couplers_BREADY;
wire [1:0]m02_couplers_to_m02_couplers_BRESP;
wire m02_couplers_to_m02_couplers_BVALID;
wire [31:0]m02_couplers_to_m02_couplers_RDATA;
wire m02_couplers_to_m02_couplers_RREADY;
wire [1:0]m02_couplers_to_m02_couplers_RRESP;
wire m02_couplers_to_m02_couplers_RVALID;
wire [31:0]m02_couplers_to_m02_couplers_WDATA;
wire m02_couplers_to_m02_couplers_WREADY;
wire m02_couplers_to_m02_couplers_WVALID;
assign M_AXI_araddr[8:0] = m02_couplers_to_m02_couplers_ARADDR;
assign M_AXI_arvalid = m02_couplers_to_m02_couplers_ARVALID;
assign M_AXI_awaddr[8:0] = m02_couplers_to_m02_couplers_AWADDR;
assign M_AXI_awvalid = m02_couplers_to_m02_couplers_AWVALID;
assign M_AXI_bready = m02_couplers_to_m02_couplers_BREADY;
assign M_AXI_rready = m02_couplers_to_m02_couplers_RREADY;
assign M_AXI_wdata[31:0] = m02_couplers_to_m02_couplers_WDATA;
assign M_AXI_wvalid = m02_couplers_to_m02_couplers_WVALID;
assign S_AXI_arready = m02_couplers_to_m02_couplers_ARREADY;
assign S_AXI_awready = m02_couplers_to_m02_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m02_couplers_to_m02_couplers_BRESP;
assign S_AXI_bvalid = m02_couplers_to_m02_couplers_BVALID;
assign S_AXI_rdata[31:0] = m02_couplers_to_m02_couplers_RDATA;
assign S_AXI_rresp[1:0] = m02_couplers_to_m02_couplers_RRESP;
assign S_AXI_rvalid = m02_couplers_to_m02_couplers_RVALID;
assign S_AXI_wready = m02_couplers_to_m02_couplers_WREADY;
assign m02_couplers_to_m02_couplers_ARADDR = S_AXI_araddr[8:0];
assign m02_couplers_to_m02_couplers_ARREADY = M_AXI_arready;
assign m02_couplers_to_m02_couplers_ARVALID = S_AXI_arvalid;
assign m02_couplers_to_m02_couplers_AWADDR = S_AXI_awaddr[8:0];
assign m02_couplers_to_m02_couplers_AWREADY = M_AXI_awready;
assign m02_couplers_to_m02_couplers_AWVALID = S_AXI_awvalid;
assign m02_couplers_to_m02_couplers_BREADY = S_AXI_bready;
assign m02_couplers_to_m02_couplers_BRESP = M_AXI_bresp[1:0];
assign m02_couplers_to_m02_couplers_BVALID = M_AXI_bvalid;
assign m02_couplers_to_m02_couplers_RDATA = M_AXI_rdata[31:0];
assign m02_couplers_to_m02_couplers_RREADY = S_AXI_rready;
assign m02_couplers_to_m02_couplers_RRESP = M_AXI_rresp[1:0];
assign m02_couplers_to_m02_couplers_RVALID = M_AXI_rvalid;
assign m02_couplers_to_m02_couplers_WDATA = S_AXI_wdata[31:0];
assign m02_couplers_to_m02_couplers_WREADY = M_AXI_wready;
assign m02_couplers_to_m02_couplers_WVALID = S_AXI_wvalid;
endmodule
module s00_couplers_imp_1CFO1MB
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wid,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_araddr;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [11:0]S_AXI_arid;
input [3:0]S_AXI_arlen;
input [1:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [11:0]S_AXI_awid;
input [3:0]S_AXI_awlen;
input [1:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [11:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output [11:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input [11:0]S_AXI_wid;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
wire [2:0]auto_pc_to_s00_couplers_ARPROT;
wire auto_pc_to_s00_couplers_ARREADY;
wire auto_pc_to_s00_couplers_ARVALID;
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
wire [2:0]auto_pc_to_s00_couplers_AWPROT;
wire auto_pc_to_s00_couplers_AWREADY;
wire auto_pc_to_s00_couplers_AWVALID;
wire auto_pc_to_s00_couplers_BREADY;
wire [1:0]auto_pc_to_s00_couplers_BRESP;
wire auto_pc_to_s00_couplers_BVALID;
wire [31:0]auto_pc_to_s00_couplers_RDATA;
wire auto_pc_to_s00_couplers_RREADY;
wire [1:0]auto_pc_to_s00_couplers_RRESP;
wire auto_pc_to_s00_couplers_RVALID;
wire [31:0]auto_pc_to_s00_couplers_WDATA;
wire auto_pc_to_s00_couplers_WREADY;
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
wire auto_pc_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
wire [11:0]s00_couplers_to_auto_pc_ARID;
wire [3:0]s00_couplers_to_auto_pc_ARLEN;
wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
wire s00_couplers_to_auto_pc_ARREADY;
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
wire s00_couplers_to_auto_pc_ARVALID;
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
wire [11:0]s00_couplers_to_auto_pc_AWID;
wire [3:0]s00_couplers_to_auto_pc_AWLEN;
wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
wire s00_couplers_to_auto_pc_AWREADY;
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
wire s00_couplers_to_auto_pc_AWVALID;
wire [11:0]s00_couplers_to_auto_pc_BID;
wire s00_couplers_to_auto_pc_BREADY;
wire [1:0]s00_couplers_to_auto_pc_BRESP;
wire s00_couplers_to_auto_pc_BVALID;
wire [31:0]s00_couplers_to_auto_pc_RDATA;
wire [11:0]s00_couplers_to_auto_pc_RID;
wire s00_couplers_to_auto_pc_RLAST;
wire s00_couplers_to_auto_pc_RREADY;
wire [1:0]s00_couplers_to_auto_pc_RRESP;
wire s00_couplers_to_auto_pc_RVALID;
wire [31:0]s00_couplers_to_auto_pc_WDATA;
wire [11:0]s00_couplers_to_auto_pc_WID;
wire s00_couplers_to_auto_pc_WLAST;
wire s00_couplers_to_auto_pc_WREADY;
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
wire s00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_s00_couplers_ARADDR;
assign M_AXI_arprot[2:0] = auto_pc_to_s00_couplers_ARPROT;
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_s00_couplers_AWADDR;
assign M_AXI_awprot[2:0] = auto_pc_to_s00_couplers_AWPROT;
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
design_1_auto_pc_0 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
.m_axi_arprot(auto_pc_to_s00_couplers_ARPROT),
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
.m_axi_awprot(auto_pc_to_s00_couplers_AWPROT),
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(s00_couplers_to_auto_pc_BID),
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
.s_axi_rid(s00_couplers_to_auto_pc_RID),
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
.s_axi_wid(s00_couplers_to_auto_pc_WID),
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
endmodule
module s00_couplers_imp_O7FAN0
(M_ACLK,
M_ARESETN,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awprot,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [3:0]M_AXI_awlen;
output [1:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
output [3:0]M_AXI_awqos;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
output [63:0]M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output [7:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [7:0]S_AXI_awlen;
input [2:0]S_AXI_awprot;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
input [31:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire GND_1;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_auto_us_AWADDR;
wire [1:0]auto_pc_to_auto_us_AWBURST;
wire [3:0]auto_pc_to_auto_us_AWCACHE;
wire [3:0]auto_pc_to_auto_us_AWLEN;
wire [1:0]auto_pc_to_auto_us_AWLOCK;
wire [2:0]auto_pc_to_auto_us_AWPROT;
wire [3:0]auto_pc_to_auto_us_AWQOS;
wire auto_pc_to_auto_us_AWREADY;
wire [2:0]auto_pc_to_auto_us_AWSIZE;
wire auto_pc_to_auto_us_AWVALID;
wire auto_pc_to_auto_us_BREADY;
wire [1:0]auto_pc_to_auto_us_BRESP;
wire auto_pc_to_auto_us_BVALID;
wire [31:0]auto_pc_to_auto_us_WDATA;
wire auto_pc_to_auto_us_WLAST;
wire auto_pc_to_auto_us_WREADY;
wire [3:0]auto_pc_to_auto_us_WSTRB;
wire auto_pc_to_auto_us_WVALID;
wire [31:0]auto_us_to_s00_couplers_AWADDR;
wire [1:0]auto_us_to_s00_couplers_AWBURST;
wire [3:0]auto_us_to_s00_couplers_AWCACHE;
wire [3:0]auto_us_to_s00_couplers_AWLEN;
wire [1:0]auto_us_to_s00_couplers_AWLOCK;
wire [2:0]auto_us_to_s00_couplers_AWPROT;
wire [3:0]auto_us_to_s00_couplers_AWQOS;
wire auto_us_to_s00_couplers_AWREADY;
wire [2:0]auto_us_to_s00_couplers_AWSIZE;
wire auto_us_to_s00_couplers_AWVALID;
wire auto_us_to_s00_couplers_BREADY;
wire [1:0]auto_us_to_s00_couplers_BRESP;
wire auto_us_to_s00_couplers_BVALID;
wire [63:0]auto_us_to_s00_couplers_WDATA;
wire auto_us_to_s00_couplers_WLAST;
wire auto_us_to_s00_couplers_WREADY;
wire [7:0]auto_us_to_s00_couplers_WSTRB;
wire auto_us_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
wire [7:0]s00_couplers_to_auto_pc_AWLEN;
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
wire s00_couplers_to_auto_pc_AWREADY;
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
wire s00_couplers_to_auto_pc_AWVALID;
wire s00_couplers_to_auto_pc_BREADY;
wire [1:0]s00_couplers_to_auto_pc_BRESP;
wire s00_couplers_to_auto_pc_BVALID;
wire [31:0]s00_couplers_to_auto_pc_WDATA;
wire s00_couplers_to_auto_pc_WLAST;
wire s00_couplers_to_auto_pc_WREADY;
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
wire s00_couplers_to_auto_pc_WVALID;
assign M_AXI_awaddr[31:0] = auto_us_to_s00_couplers_AWADDR;
assign M_AXI_awburst[1:0] = auto_us_to_s00_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_us_to_s00_couplers_AWCACHE;
assign M_AXI_awlen[3:0] = auto_us_to_s00_couplers_AWLEN;
assign M_AXI_awlock[1:0] = auto_us_to_s00_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_us_to_s00_couplers_AWPROT;
assign M_AXI_awqos[3:0] = auto_us_to_s00_couplers_AWQOS;
assign M_AXI_awsize[2:0] = auto_us_to_s00_couplers_AWSIZE;
assign M_AXI_awvalid = auto_us_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_us_to_s00_couplers_BREADY;
assign M_AXI_wdata[63:0] = auto_us_to_s00_couplers_WDATA;
assign M_AXI_wlast = auto_us_to_s00_couplers_WLAST;
assign M_AXI_wstrb[7:0] = auto_us_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_us_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
assign auto_us_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_us_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_us_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_us_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[7:0];
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
GND GND
(.G(GND_1));
design_1_auto_pc_1 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_awaddr(auto_pc_to_auto_us_AWADDR),
.m_axi_awburst(auto_pc_to_auto_us_AWBURST),
.m_axi_awcache(auto_pc_to_auto_us_AWCACHE),
.m_axi_awlen(auto_pc_to_auto_us_AWLEN),
.m_axi_awlock(auto_pc_to_auto_us_AWLOCK),
.m_axi_awprot(auto_pc_to_auto_us_AWPROT),
.m_axi_awqos(auto_pc_to_auto_us_AWQOS),
.m_axi_awready(auto_pc_to_auto_us_AWREADY),
.m_axi_awsize(auto_pc_to_auto_us_AWSIZE),
.m_axi_awvalid(auto_pc_to_auto_us_AWVALID),
.m_axi_bready(auto_pc_to_auto_us_BREADY),
.m_axi_bresp(auto_pc_to_auto_us_BRESP),
.m_axi_bvalid(auto_pc_to_auto_us_BVALID),
.m_axi_wdata(auto_pc_to_auto_us_WDATA),
.m_axi_wlast(auto_pc_to_auto_us_WLAST),
.m_axi_wready(auto_pc_to_auto_us_WREADY),
.m_axi_wstrb(auto_pc_to_auto_us_WSTRB),
.m_axi_wvalid(auto_pc_to_auto_us_WVALID),
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(GND_1),
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos({GND_1,GND_1,GND_1,GND_1}),
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
.s_axi_awregion({GND_1,GND_1,GND_1,GND_1}),
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
design_1_auto_us_0 auto_us
(.m_axi_awaddr(auto_us_to_s00_couplers_AWADDR),
.m_axi_awburst(auto_us_to_s00_couplers_AWBURST),
.m_axi_awcache(auto_us_to_s00_couplers_AWCACHE),
.m_axi_awlen(auto_us_to_s00_couplers_AWLEN),
.m_axi_awlock(auto_us_to_s00_couplers_AWLOCK),
.m_axi_awprot(auto_us_to_s00_couplers_AWPROT),
.m_axi_awqos(auto_us_to_s00_couplers_AWQOS),
.m_axi_awready(auto_us_to_s00_couplers_AWREADY),
.m_axi_awsize(auto_us_to_s00_couplers_AWSIZE),
.m_axi_awvalid(auto_us_to_s00_couplers_AWVALID),
.m_axi_bready(auto_us_to_s00_couplers_BREADY),
.m_axi_bresp(auto_us_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_us_to_s00_couplers_BVALID),
.m_axi_wdata(auto_us_to_s00_couplers_WDATA),
.m_axi_wlast(auto_us_to_s00_couplers_WLAST),
.m_axi_wready(auto_us_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_us_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_us_to_s00_couplers_WVALID),
.s_axi_aclk(S_ACLK_1),
.s_axi_aresetn(S_ARESETN_1),
.s_axi_awaddr(auto_pc_to_auto_us_AWADDR),
.s_axi_awburst(auto_pc_to_auto_us_AWBURST),
.s_axi_awcache(auto_pc_to_auto_us_AWCACHE),
.s_axi_awlen(auto_pc_to_auto_us_AWLEN),
.s_axi_awlock(auto_pc_to_auto_us_AWLOCK),
.s_axi_awprot(auto_pc_to_auto_us_AWPROT),
.s_axi_awqos(auto_pc_to_auto_us_AWQOS),
.s_axi_awready(auto_pc_to_auto_us_AWREADY),
.s_axi_awsize(auto_pc_to_auto_us_AWSIZE),
.s_axi_awvalid(auto_pc_to_auto_us_AWVALID),
.s_axi_bready(auto_pc_to_auto_us_BREADY),
.s_axi_bresp(auto_pc_to_auto_us_BRESP),
.s_axi_bvalid(auto_pc_to_auto_us_BVALID),
.s_axi_wdata(auto_pc_to_auto_us_WDATA),
.s_axi_wlast(auto_pc_to_auto_us_WLAST),
.s_axi_wready(auto_pc_to_auto_us_WREADY),
.s_axi_wstrb(auto_pc_to_auto_us_WSTRB),
.s_axi_wvalid(auto_pc_to_auto_us_WVALID));
endmodule
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// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build 2018833 Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 14:49:55 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top DemoInterconnect_axi_spi_master_0_1 -prefix
// DemoInterconnect_axi_spi_master_0_1_ DemoInterconnect_axi_spi_master_0_0_stub.v
// Design : DemoInterconnect_axi_spi_master_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_spi_master_v1_0,Vivado 2017.3" *)
module DemoInterconnect_axi_spi_master_0_1(m_spi_mosi, m_spi_miso, m_spi_ss, m_spi_sclk,
s00_axi_awaddr, s00_axi_awprot, s00_axi_awvalid, s00_axi_awready, s00_axi_wdata,
s00_axi_wstrb, s00_axi_wvalid, s00_axi_wready, s00_axi_bresp, s00_axi_bvalid,
s00_axi_bready, s00_axi_araddr, s00_axi_arprot, s00_axi_arvalid, s00_axi_arready,
s00_axi_rdata, s00_axi_rresp, s00_axi_rvalid, s00_axi_rready, s00_axi_aclk,
s00_axi_aresetn)
/* synthesis syn_black_box black_box_pad_pin="m_spi_mosi,m_spi_miso,m_spi_ss,m_spi_sclk,s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn" */;
output m_spi_mosi;
input m_spi_miso;
output m_spi_ss;
output m_spi_sclk;
input [3:0]s00_axi_awaddr;
input [2:0]s00_axi_awprot;
input s00_axi_awvalid;
output s00_axi_awready;
input [31:0]s00_axi_wdata;
input [3:0]s00_axi_wstrb;
input s00_axi_wvalid;
output s00_axi_wready;
output [1:0]s00_axi_bresp;
output s00_axi_bvalid;
input s00_axi_bready;
input [3:0]s00_axi_araddr;
input [2:0]s00_axi_arprot;
input s00_axi_arvalid;
output s00_axi_arready;
output [31:0]s00_axi_rdata;
output [1:0]s00_axi_rresp;
output s00_axi_rvalid;
input s00_axi_rready;
input s00_axi_aclk;
input s00_axi_aresetn;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVGND_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__TAPVGND_BEHAVIORAL_PP_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
* row down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__tapvgnd (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVGND_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVGND2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__TAPVGND2_FUNCTIONAL_PP_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection 2
* rows down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__tapvgnd2 (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVGND2_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4_BLACKBOX_V
`define SKY130_FD_SC_MS__NAND4_BLACKBOX_V
/**
* nand4: 4-input NAND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22AI_SYMBOL_V
`define SKY130_FD_SC_LS__O22AI_SYMBOL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o22ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22AI_SYMBOL_V
|
`timescale 1ns / 1ns
// Taken from http://students.iitk.ac.in/eclub/assets/tutorials/keyboard.pdf
module topkeyboard(PS2_CLK, PS2_DAT, LEDR);
synthkeyboard(clock
endmodule
module synthkeyboard(clock, char, keyboard_data);
input clock;
input char;
output reg [3:0] keyboard_data;
reg [3:0] counter;
reg flag;
reg [7:0] temp_data;
initial begin
keyboard_data <= 8'b0;
counter <= 4'b0001;
flag <= 1'b0;
end
always @(negedge clock) begin
case (counter)
1:;
2: temp_data[0] <= char;
3: temp_data[1] <= char;
4: temp_data[2] <= char;
5: temp_data[3] <= char;
6: temp_data[4] <= char;
7: temp_data[5] <= char;
8: temp_data[6] <= char;
9: temp_data[7] <= char;
10: flag <= 1'b1;
11: flag <= 1'b0;
endcase
if (counter <= 10) begin
counter <= counter + 1;
end
else if (counter == 11) begin
counter <= 1;
end
end
always @(posedge flag) begin
/*
* A = 1C, S = 1B, D = 23, F = 2B
*/
if (temp_data == 8'h1C) begin
keyboard_data <= 4'b1000;
end
else if (temp_data == 8'h1B) begin
keyboard_data <= 4'b0100;
end
else if (temp_data == 8'h23) begin
keyboard_data <= 4'b0010;
end
else if (temp_data == 8'h2B) begin
keyboard_data <= 4'b0001;
end
else begin
keyboard_data <= 4'b0000;
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information of Xilinx, Inc.
// and is protected under U.S. and international copyright and other
// intellectual property laws.
//
// DISCLAIMER
//
// This disclaimer is not a license and does not grant any rights to the
// materials distributed herewith. Except as otherwise provided in a valid
// license issued to you by Xilinx, and to the maximum extent permitted by
// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
// and (2) Xilinx shall not be liable (whether in contract or tort, including
// negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these
// materials, including for any direct, or any indirect, special, incidental,
// or consequential loss or damage (including loss of data, profits, goodwill,
// or any type of loss or damage suffered as a result of any action brought by
// a third party) even if such damage or loss was reasonably foreseeable or
// Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
//
// Xilinx products are not designed or intended to be fail-safe, or for use in
// any application requiring fail-safe performance, such as life-support or
// safety devices or systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any other
// applications that could lead to death, personal injury, or severe property
// or environmental damage (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and liability of any use of
// Xilinx products in Critical Applications, subject only to applicable laws
// and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
// AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Spartan-6 Integrated Block for PCI Express
// File : s6_pcie_v1_2.v
// Description: Spartan-6 solution wrapper : Endpoint for PCI Express
//
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
(* CORE_GENERATION_INFO = "s6_pcie_v1_2,s6_pcie_v1_2,{TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=14,VC0_RX_RAM_LIMIT=7FF,VC0_TOTAL_CREDITS_PH=32,VC0_TOTAL_CREDITS_PD=211,VC0_TOTAL_CREDITS_NPH=8,VC0_TOTAL_CREDITS_CH=40,VC0_TOTAL_CREDITS_CD=211,VC0_CPL_INFINITE=TRUE,BAR0=FF000000,BAR1=FFFF0000,BAR2=00000000,BAR3=00000000,BAR4=00000000,BAR5=00000000,EXPANSION_ROM=000000,USR_CFG=FALSE,USR_EXT_CFG=FALSE,DEV_CAP_MAX_PAYLOAD_SUPPORTED=2,CLASS_CODE=050000,CARDBUS_CIS_POINTER=00000000,PCIE_CAP_CAPABILITY_VERSION=1,PCIE_CAP_DEVICE_PORT_TYPE=0,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,DEV_CAP_ENDPOINT_L0S_LATENCY=7,DEV_CAP_ENDPOINT_L1_LATENCY=7,LINK_CAP_ASPM_SUPPORT=1,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,LINK_STATUS_SLOT_CLOCK_CONFIG=FALSE,ENABLE_RX_TD_ECRC_TRIM=FALSE,DISABLE_SCRAMBLING=FALSE,PM_CAP_DSI=FALSE,PM_CAP_D1SUPPORT=TRUE,PM_CAP_D2SUPPORT=TRUE,PM_CAP_PMESUPPORT=0F,PM_DATA0=00,PM_DATA_SCALE0=0,PM_DATA1=00,PM_DATA_SCALE1=0,PM_DATA2=00,PM_DATA_SCALE2=0,PM_DATA3=00,PM_DATA_SCALE3=0,PM_DATA4=00,PM_DATA_SCALE4=0,PM_DATA5=00,PM_DATA_SCALE5=0,PM_DATA6=00,PM_DATA_SCALE6=0,PM_DATA7=00,PM_DATA_SCALE7=0,PCIE_GENERIC=000010101111,GTP_SEL=0,CFG_VEN_ID=10EE,CFG_DEV_ID=4243,CFG_REV_ID=02,CFG_SUBSYS_VEN_ID=10EE,CFG_SUBSYS_ID=0007,REF_CLK_FREQ=1}" *)
module s6_pcie_v1_2
#(
parameter [0:0] TL_TX_RAM_RADDR_LATENCY = 0,
parameter [1:0] TL_TX_RAM_RDATA_LATENCY = 2,
parameter [0:0] TL_RX_RAM_RADDR_LATENCY = 0,
parameter [1:0] TL_RX_RAM_RDATA_LATENCY = 2,
parameter [0:0] TL_RX_RAM_WRITE_LATENCY = 0,
parameter [4:0] VC0_TX_LASTPACKET = 14,
parameter [11:0] VC0_RX_RAM_LIMIT = 12'h7FF,
parameter [6:0] VC0_TOTAL_CREDITS_PH = 32,
parameter [10:0] VC0_TOTAL_CREDITS_PD = 211,
parameter [6:0] VC0_TOTAL_CREDITS_NPH = 8,
parameter [6:0] VC0_TOTAL_CREDITS_CH = 40,
parameter [10:0] VC0_TOTAL_CREDITS_CD = 211,
parameter VC0_CPL_INFINITE = "TRUE",
parameter [31:0] BAR0 = 32'hFF000000,
parameter [31:0] BAR1 = 32'hFFFF0000,
parameter [31:0] BAR2 = 32'h00000000,
parameter [31:0] BAR3 = 32'h00000000,
parameter [31:0] BAR4 = 32'h00000000,
parameter [31:0] BAR5 = 32'h00000000,
parameter [21:0] EXPANSION_ROM = 22'h000000,
parameter DISABLE_BAR_FILTERING = "FALSE",
parameter DISABLE_ID_CHECK = "FALSE",
parameter TL_TFC_DISABLE = "FALSE",
parameter TL_TX_CHECKS_DISABLE = "FALSE",
parameter USR_CFG = "FALSE",
parameter USR_EXT_CFG = "FALSE",
parameter [2:0] DEV_CAP_MAX_PAYLOAD_SUPPORTED = 3'd2,
parameter [23:0] CLASS_CODE = 24'h050000,
parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000,
parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h1,
parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0,
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE",
parameter [4:0] PCIE_CAP_INT_MSG_NUM = 5'b00000,
parameter [1:0] DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 2'd0,
parameter DEV_CAP_EXT_TAG_SUPPORTED = "FALSE",
parameter [2:0] DEV_CAP_ENDPOINT_L0S_LATENCY = 3'd7,
parameter [2:0] DEV_CAP_ENDPOINT_L1_LATENCY = 3'd7,
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE",
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE",
parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE",
parameter [1:0] LINK_CAP_ASPM_SUPPORT = 2'd1,
parameter [2:0] LINK_CAP_L0S_EXIT_LATENCY = 3'd7,
parameter [2:0] LINK_CAP_L1_EXIT_LATENCY = 3'd7,
parameter [14:0] LL_ACK_TIMEOUT = 15'h0000,
parameter LL_ACK_TIMEOUT_EN = "FALSE",
parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000,
parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
parameter [2:0] MSI_CAP_MULTIMSGCAP = 3'd0,
parameter [0:0] MSI_CAP_MULTIMSG_EXTENSION = 1'd0,
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "FALSE",
parameter PLM_AUTO_CONFIG = "FALSE",
parameter FAST_TRAIN = "FALSE",
parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE",
parameter DISABLE_SCRAMBLING = "FALSE",
parameter [2:0] PM_CAP_VERSION = 3'd3,
parameter PM_CAP_PME_CLOCK = "FALSE",
parameter PM_CAP_DSI = "FALSE",
parameter [2:0] PM_CAP_AUXCURRENT = 3'd0,
parameter PM_CAP_D1SUPPORT = "TRUE",
parameter PM_CAP_D2SUPPORT = "TRUE",
parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F,
parameter [7:0] PM_DATA0 = 8'h00,
parameter [1:0] PM_DATA_SCALE0 = 2'h0,
parameter [7:0] PM_DATA1 = 8'h00,
parameter [1:0] PM_DATA_SCALE1 = 2'h0,
parameter [7:0] PM_DATA2 = 8'h00,
parameter [1:0] PM_DATA_SCALE2 = 2'h0,
parameter [7:0] PM_DATA3 = 8'h00,
parameter [1:0] PM_DATA_SCALE3 = 2'h0,
parameter [7:0] PM_DATA4 = 8'h00,
parameter [1:0] PM_DATA_SCALE4 = 2'h0,
parameter [7:0] PM_DATA5 = 8'h00,
parameter [1:0] PM_DATA_SCALE5 = 2'h0,
parameter [7:0] PM_DATA6 = 8'h00,
parameter [1:0] PM_DATA_SCALE6 = 2'h0,
parameter [7:0] PM_DATA7 = 8'h00,
parameter [1:0] PM_DATA_SCALE7 = 2'h0,
parameter [11:0] PCIE_GENERIC = 12'b000011101111,
parameter [0:0] GTP_SEL = 1'b0,
parameter [15:0] CFG_VEN_ID = 16'h10EE,
parameter [15:0] CFG_DEV_ID = 16'h4243,
parameter [7:0] CFG_REV_ID = 8'h02,
parameter [15:0] CFG_SUBSYS_VEN_ID = 16'h10EE,
parameter [15:0] CFG_SUBSYS_ID = 16'h0007,
parameter REF_CLK_FREQ = 1) (
// PCI Express Fabric Interface
output pci_exp_txp,
output pci_exp_txn,
input pci_exp_rxp,
input pci_exp_rxn,
// Transaction (TRN) Interface
output trn_lnk_up_n,
// Tx
input [31:0] trn_td,
input trn_tsof_n,
input trn_teof_n,
input trn_tsrc_rdy_n,
output trn_tdst_rdy_n,
output trn_terr_drop_n,
input trn_tsrc_dsc_n,
input trn_terrfwd_n,
output [5:0] trn_tbuf_av,
input trn_tstr_n,
output trn_tcfg_req_n,
input trn_tcfg_gnt_n,
// Rx
output [31:0] trn_rd,
output trn_rsof_n,
output trn_reof_n,
output trn_rsrc_rdy_n,
output trn_rsrc_dsc_n,
input trn_rdst_rdy_n,
output trn_rerrfwd_n,
input trn_rnp_ok_n,
output [6:0] trn_rbar_hit_n,
input [2:0] trn_fc_sel,
output [7:0] trn_fc_nph,
output [11:0] trn_fc_npd,
output [7:0] trn_fc_ph,
output [11:0] trn_fc_pd,
output [7:0] trn_fc_cplh,
output [11:0] trn_fc_cpld,
// Host (CFG) Interface
output [31:0] cfg_do,
output cfg_rd_wr_done_n,
input [9:0] cfg_dwaddr,
input cfg_rd_en_n,
input cfg_err_ur_n,
input cfg_err_cor_n,
input cfg_err_ecrc_n,
input cfg_err_cpl_timeout_n,
input cfg_err_cpl_abort_n,
input cfg_err_posted_n,
input cfg_err_locked_n,
input [47:0] cfg_err_tlp_cpl_header,
output cfg_err_cpl_rdy_n,
input cfg_interrupt_n,
output cfg_interrupt_rdy_n,
input cfg_interrupt_assert_n,
output [7:0] cfg_interrupt_do,
input [7:0] cfg_interrupt_di,
output [2:0] cfg_interrupt_mmenable,
output cfg_interrupt_msienable,
input cfg_turnoff_ok_n,
output cfg_to_turnoff_n,
input cfg_pm_wake_n,
output [2:0] cfg_pcie_link_state_n,
input cfg_trn_pending_n,
input [63:0] cfg_dsn,
output [7:0] cfg_bus_number,
output [4:0] cfg_device_number,
output [2:0] cfg_function_number,
output [15:0] cfg_status,
output [15:0] cfg_command,
output [15:0] cfg_dstatus,
output [15:0] cfg_dcommand,
output [15:0] cfg_lstatus,
output [15:0] cfg_lcommand,
// System Interface
input sys_clk,
input sys_reset_n,
output trn_clk,
output trn_reset_n,
output received_hot_reset
);
//***************************************************************************
// Wire Declarations
//***************************************************************************
// Wires for the PLL
wire mgt_clk;
wire mgt_clk_2x;
wire clock_locked;
wire gt_refclk_out;
wire pll_rst;
wire clk_125;
wire clk_250;
wire clk_62_5;
wire gt_refclk_buf;
wire gt_refclk_fb;
// These values may be brought out and driven dynamically
// from pins rather than attributes if desired. Note -
// if they are not statically driven, the values must be
// stable before sys_reset_n is released
wire [15:0] w_cfg_ven_id;
wire [15:0] w_cfg_dev_id;
wire [7:0] w_cfg_rev_id;
wire [15:0] w_cfg_subsys_ven_id;
wire [15:0] w_cfg_subsys_id;
assign w_cfg_ven_id = CFG_VEN_ID;
assign w_cfg_dev_id = CFG_DEV_ID;
assign w_cfg_rev_id = CFG_REV_ID;
assign w_cfg_subsys_ven_id = CFG_SUBSYS_VEN_ID;
assign w_cfg_subsys_id = CFG_SUBSYS_ID;
wire [4:0] cfg_ltssm_state;
wire [1:0] cfg_link_control_aspm_control;
wire cfg_link_control_rcb;
wire cfg_link_control_common_clock;
wire cfg_link_control_extended_sync;
wire cfg_command_interrupt_disable;
wire cfg_command_serr_en;
wire cfg_command_bus_master_enable;
wire cfg_command_mem_enable;
wire cfg_command_io_enable;
wire cfg_dev_status_ur_detected;
wire cfg_dev_status_fatal_err_detected;
wire cfg_dev_status_nonfatal_err_detected;
wire cfg_dev_status_corr_err_detected;
wire [2:0] cfg_dev_control_max_read_req;
wire cfg_dev_control_no_snoop_en;
wire cfg_dev_control_aux_power_en;
wire cfg_dev_control_phantom_en;
wire cfg_dev_cntrol_ext_tag_en;
wire [2:0] cfg_dev_control_max_payload;
wire cfg_dev_control_enable_ro;
wire cfg_dev_control_ur_err_reporting_en;
wire cfg_dev_control_fatal_err_reporting_en;
wire cfg_dev_control_non_fatal_reporting_en;
wire cfg_dev_control_corr_err_reporting_en;
wire mim_rx_rdata_unused;
wire [11:0] mim_tx_waddr, mim_tx_raddr, mim_rx_waddr, mim_rx_raddr;
wire [35:0] mim_tx_wdata, mim_tx_rdata;
wire [34:0] mim_rx_wdata, mim_rx_rdata;
wire mim_tx_wen, mim_tx_ren, mim_rx_wen, mim_rx_ren;
wire dbg_bad_dllp_status;
wire dbg_bad_tlp_lcrc;
wire dbg_bad_tlp_seq_num;
wire dbg_bad_tlp_status;
wire dbg_dl_protocol_status;
wire dbg_fc_protocol_err_status;
wire dbg_mlfrmd_length;
wire dbg_mlfrmd_mps;
wire dbg_mlfrmd_tcvc;
wire dbg_mlfrmd_tlp_status;
wire dbg_mlfrmd_unrec_type;
wire dbg_poistlpstatus;
wire dbg_rcvr_overflow_status;
wire dbg_reg_detected_correctable;
wire dbg_reg_detected_fatal;
wire dbg_reg_detected_non_fatal;
wire dbg_reg_detected_unsupported;
wire dbg_rply_rollover_status;
wire dbg_rply_timeout_status;
wire dbg_ur_no_bar_hit;
wire dbg_ur_pois_cfg_wr;
wire dbg_ur_status;
wire dbg_ur_unsup_msg;
wire [1:0] pipe_gt_power_down_a;
wire [1:0] pipe_gt_power_down_b;
wire pipe_gt_reset_done_a;
wire pipe_gt_reset_done_b;
wire pipe_gt_tx_elec_idle_a;
wire pipe_gt_tx_elec_idle_b;
wire pipe_phy_status_a;
wire pipe_phy_status_b;
wire [1:0] pipe_rx_charisk_a;
wire [1:0] pipe_rx_charisk_b;
wire [15:0] pipe_rx_data_a;
wire [15:0] pipe_rx_data_b;
wire pipe_rx_enter_elec_idle_a;
wire pipe_rx_enter_elec_idle_b;
wire pipe_rx_polarity_a;
wire pipe_rx_polarity_b;
wire pipe_rxreset_a;
wire pipe_rxreset_b;
wire [2:0] pipe_rx_status_a;
wire [2:0] pipe_rx_status_b;
wire [1:0] pipe_tx_char_disp_mode_a;
wire [1:0] pipe_tx_char_disp_mode_b;
wire [1:0] pipe_tx_char_disp_val_a;
wire [1:0] pipe_tx_char_disp_val_b;
wire [1:0] pipe_tx_char_is_k_a;
wire [1:0] pipe_tx_char_is_k_b;
wire [15:0] pipe_tx_data_a;
wire [15:0] pipe_tx_data_b;
wire pipe_tx_rcvr_det_a;
wire pipe_tx_rcvr_det_b;
// GT->PLM PIPE Interface rx
wire [1:0] rx_char_is_k;
wire [15:0] rx_data;
wire rx_enter_elecidle;
wire [2:0] rx_status;
wire rx_polarity;
// GT<-PLM PIPE Interface tx
wire [1:0] tx_char_disp_mode;
wire [1:0] tx_char_is_k;
wire tx_rcvr_det;
wire [15:0] tx_data;
// GT<->PLM PIPE Interface Misc
wire phystatus;
// GT<->PLM PIPE Interface MGT Logic I/O
wire gt_reset_done;
wire gt_rx_valid;
wire gt_tx_elec_idle;
wire [1:0] gt_power_down;
wire rxreset;
wire gt_plllkdet_out;
// Buffer reference clock from GTP
BUFIO2 gt_refclk_bufio2 (
.DIVCLK ( gt_refclk_buf ),
.IOCLK ( ),
.SERDESSTROBE ( ),
.I ( gt_refclk_out )
);
localparam CLKFBOUT_MULT = (REF_CLK_FREQ == 0) ? 5 :
(REF_CLK_FREQ == 1) ? 4 : 2 ;
localparam CLKIN_PERIOD = (REF_CLK_FREQ == 0) ? 10 :
(REF_CLK_FREQ == 1) ? 8 : 4 ;
PLL_BASE #(
// 5 for 100 MHz, 4 for 125Mhz, 2 for 250 MHz
.CLKFBOUT_MULT ( CLKFBOUT_MULT ),
.CLKFBOUT_PHASE ( 0 ),
// 10 for 100 MHz, 8 for 125Mhz, 4 for 250 MHz
.CLKIN_PERIOD ( CLKIN_PERIOD ),
.CLKOUT0_DIVIDE ( 2 ),
.CLKOUT0_PHASE ( 0 ),
.CLKOUT1_DIVIDE ( 4 ),
.CLKOUT1_PHASE ( 0 ),
.CLKOUT2_DIVIDE ( 8 ),
.CLKOUT2_PHASE ( 0 ),
.COMPENSATION ( "INTERNAL" )
) pll_base_i (
.CLKIN ( gt_refclk_buf ),
.CLKFBIN ( gt_refclk_fb ),
.RST ( pll_rst ),
.CLKOUT0 ( clk_250 ),
.CLKOUT1 ( clk_125 ),
.CLKOUT2 ( clk_62_5 ),
.CLKOUT3 ( ),
.CLKOUT4 ( ),
.CLKOUT5 ( ),
.CLKFBOUT ( gt_refclk_fb ),
.LOCKED ( clock_locked )
);
//******************************************************************//
// Instantiate buffers where required //
//******************************************************************//
BUFG mgt_bufg (.O(mgt_clk), .I(clk_125));
BUFG mgt2x_bufg (.O(mgt_clk_2x), .I(clk_250));
BUFG phy_bufg (.O(trn_clk), .I(clk_62_5));
//***************************************************************************
// PCI Express BRAM Instance
//***************************************************************************
pcie_bram_top_s6 #(
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
.TLM_TX_OVERHEAD ( 20 ),
.TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
// NOTE: use the RX value here since there is no separate TX value
.TL_TX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),
.VC0_RX_LIMIT ( VC0_RX_RAM_LIMIT ),
.TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY )
) pcie_bram_top (
.user_clk_i ( trn_clk ),
.reset_i ( !trn_reset_n ),
.mim_tx_waddr ( mim_tx_waddr ),
.mim_tx_wen ( mim_tx_wen ),
.mim_tx_ren ( mim_tx_ren ),
.mim_tx_rce ( 1'b1 ),
.mim_tx_wdata ( mim_tx_wdata ),
.mim_tx_raddr ( mim_tx_raddr ),
.mim_tx_rdata ( mim_tx_rdata ),
.mim_rx_waddr ( mim_rx_waddr ),
.mim_rx_wen ( mim_rx_wen ),
.mim_rx_ren ( mim_rx_ren ),
.mim_rx_rce ( 1'b1 ),
.mim_rx_wdata ( {1'b0, mim_rx_wdata} ),
.mim_rx_raddr ( mim_rx_raddr ),
.mim_rx_rdata ( {mim_rx_rdata_unused, mim_rx_rdata} )
);
//***************************************************************************
// PCI Express GTA1_DUAL Wrapper Instance
//***************************************************************************
gtpa1_dual_wrapper_top #(
.SIMULATION (FAST_TRAIN == "TRUE" ? 1 : 0)
) mgt (
.rx_char_is_k ( rx_char_is_k ),
.rx_data ( rx_data ),
.rx_enter_elecidle ( rx_enter_elecidle ),
.rx_status ( rx_status ),
.rx_polarity ( rx_polarity ),
.tx_char_disp_mode ( tx_char_disp_mode ),
.tx_char_is_k ( tx_char_is_k ),
.tx_rcvr_det ( tx_rcvr_det ),
.tx_data ( tx_data ),
.phystatus ( phystatus ),
.gt_usrclk ( mgt_clk ),
.gt_usrclk2x ( mgt_clk_2x ),
.sys_clk ( sys_clk ),
.sys_rst_n ( sys_reset_n ),
.arp_txp ( pci_exp_txp ),
.arp_txn ( pci_exp_txn ),
.arp_rxp ( pci_exp_rxp ),
.arp_rxn ( pci_exp_rxn ),
.gt_reset_done ( gt_reset_done ),
.gt_rx_valid ( gt_rx_valid ),
.gt_plllkdet_out ( gt_plllkdet_out ),
.gt_refclk_out ( gt_refclk_out ),
.gt_tx_elec_idle ( gt_tx_elec_idle ),
.gt_power_down ( gt_power_down ),
.rxreset ( rxreset )
);
// Generate the reset for the PLL
assign pll_rst = !gt_plllkdet_out || !sys_reset_n;
//***************************************************************************
// Generate the connection between PCIE_A1 block and the GTPA1_DUAL. When
// the parameter GTP_SEL is 0, connect to PIPEA, when it is a 1, connect to
// PIPEB.
//***************************************************************************
generate if (!GTP_SEL) begin : PIPE_A_SEL
// Signals from GTPA1_DUAL to PCIE_A1
assign pipe_rx_charisk_a = rx_char_is_k;
assign pipe_rx_data_a = rx_data;
assign pipe_rx_enter_elec_idle_a = rx_enter_elecidle;
assign pipe_rx_status_a = rx_status;
assign pipe_phy_status_a = phystatus;
assign pipe_gt_reset_done_a = gt_reset_done;
// Unused PCIE_A1 inputs
assign pipe_rx_charisk_b = 2'b0;
assign pipe_rx_data_b = 16'h0;
assign pipe_rx_enter_elec_idle_b = 1'b0;
assign pipe_rx_status_b = 3'b0;
assign pipe_phy_status_b = 1'b0;
assign pipe_gt_reset_done_b = 1'b0;
//Signals from PCIE_A1 to GTPA1_DUAL
assign rx_polarity = pipe_rx_polarity_a;
assign tx_char_disp_mode = pipe_tx_char_disp_mode_a;
assign tx_char_is_k = pipe_tx_char_is_k_a;
assign tx_rcvr_det = pipe_tx_rcvr_det_a;
assign tx_data = pipe_tx_data_a;
assign gt_tx_elec_idle = pipe_gt_tx_elec_idle_a;
assign gt_power_down = pipe_gt_power_down_a;
assign rxreset = pipe_rxreset_a;
end else begin : PIPE_B_SEL
// Signals from GTPA1_DUAL to PCIE_A1
assign pipe_rx_charisk_b = rx_char_is_k;
assign pipe_rx_data_b = rx_data;
assign pipe_rx_enter_elec_idle_b = rx_enter_elecidle;
assign pipe_rx_status_b = rx_status;
assign pipe_phy_status_b = phystatus;
assign pipe_gt_reset_done_b = gt_reset_done;
// Unused PCIE_A1 inputs
assign pipe_rx_charisk_a = 2'b0;
assign pipe_rx_data_a = 16'h0;
assign pipe_rx_enter_elec_idle_a = 1'b0;
assign pipe_rx_status_a = 3'b0;
assign pipe_phy_status_a = 1'b0;
assign pipe_gt_reset_done_a = 1'b0;
//Signals from PCIE_A1 to GTPA1_DUAL
assign rx_polarity = pipe_rx_polarity_b;
assign tx_char_disp_mode = pipe_tx_char_disp_mode_b;
assign tx_char_is_k = pipe_tx_char_is_k_b;
assign tx_rcvr_det = pipe_tx_rcvr_det_b;
assign tx_data = pipe_tx_data_b;
assign gt_tx_elec_idle = pipe_gt_tx_elec_idle_b;
assign gt_power_down = pipe_gt_power_down_b;
assign rxreset = pipe_rxreset_b;
end
endgenerate
//***************************************************************************
// PCI Express Hard Block Instance (PCIE_A1)
//***************************************************************************
PCIE_A1 #(
.BAR0 ( BAR0 ),
.BAR1 ( BAR1 ),
.BAR2 ( BAR2 ),
.BAR3 ( BAR3 ),
.BAR4 ( BAR4 ),
.BAR5 ( BAR5 ),
.CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),
.CLASS_CODE ( CLASS_CODE ),
.DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),
.DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),
.DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),
.DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ),
.DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),
.DISABLE_ID_CHECK ( DISABLE_ID_CHECK ),
.DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),
.ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),
.EXPANSION_ROM ( EXPANSION_ROM ),
.FAST_TRAIN ( FAST_TRAIN ),
.GTP_SEL ( GTP_SEL ),
.LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),
.LINK_CAP_L0S_EXIT_LATENCY ( LINK_CAP_L0S_EXIT_LATENCY ),
.LINK_CAP_L1_EXIT_LATENCY ( LINK_CAP_L1_EXIT_LATENCY ),
.LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),
.LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
.LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
.LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
.LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
.MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),
.MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),
.PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),
.PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),
.PCIE_CAP_INT_MSG_NUM ( PCIE_CAP_INT_MSG_NUM ),
.PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),
.PCIE_GENERIC ( PCIE_GENERIC ),
.PLM_AUTO_CONFIG ( PLM_AUTO_CONFIG ),
.PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),
.PM_CAP_DSI ( PM_CAP_DSI ),
.PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ),
.PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ),
.PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ),
.PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),
.PM_CAP_VERSION ( PM_CAP_VERSION ),
.PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),
.PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),
.PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),
.PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),
.PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),
.PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),
.PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),
.PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),
.PM_DATA0 ( PM_DATA0 ),
.PM_DATA1 ( PM_DATA1 ),
.PM_DATA2 ( PM_DATA2 ),
.PM_DATA3 ( PM_DATA3 ),
.PM_DATA4 ( PM_DATA4 ),
.PM_DATA5 ( PM_DATA5 ),
.PM_DATA6 ( PM_DATA6 ),
.PM_DATA7 ( PM_DATA7 ),
.SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),
.SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),
.SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ),
.TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),
.TL_TFC_DISABLE ( TL_TFC_DISABLE ),
.TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),
.TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.USR_CFG ( USR_CFG ),
.USR_EXT_CFG ( USR_EXT_CFG ),
.VC0_CPL_INFINITE ( VC0_CPL_INFINITE ),
.VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),
.VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),
.VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),
.VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),
.VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),
.VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET )
) PCIE_A1 (
.CFGBUSNUMBER ( cfg_bus_number ),
.CFGCOMMANDBUSMASTERENABLE ( cfg_command_bus_master_enable ),
.CFGCOMMANDINTERRUPTDISABLE ( cfg_command_interrupt_disable ),
.CFGCOMMANDIOENABLE ( cfg_command_io_enable ),
.CFGCOMMANDMEMENABLE ( cfg_command_mem_enable ),
.CFGCOMMANDSERREN ( cfg_command_serr_en ),
.CFGDEVCONTROLAUXPOWEREN ( cfg_dev_control_aux_power_en ),
.CFGDEVCONTROLCORRERRREPORTINGEN ( cfg_dev_control_corr_err_reporting_en ),
.CFGDEVCONTROLENABLERO ( cfg_dev_control_enable_ro ),
.CFGDEVCONTROLEXTTAGEN ( cfg_dev_control_ext_tag_en ),
.CFGDEVCONTROLFATALERRREPORTINGEN ( cfg_dev_control_fatal_err_reporting_en ),
.CFGDEVCONTROLMAXPAYLOAD ( cfg_dev_control_max_payload ),
.CFGDEVCONTROLMAXREADREQ ( cfg_dev_control_max_read_req ),
.CFGDEVCONTROLNONFATALREPORTINGEN ( cfg_dev_control_non_fatal_reporting_en ),
.CFGDEVCONTROLNOSNOOPEN ( cfg_dev_control_no_snoop_en ),
.CFGDEVCONTROLPHANTOMEN ( cfg_dev_control_phantom_en ),
.CFGDEVCONTROLURERRREPORTINGEN ( cfg_dev_control_ur_err_reporting_en ),
.CFGDEVICENUMBER ( cfg_device_number ),
.CFGDEVID ( w_cfg_dev_id ),
.CFGDEVSTATUSCORRERRDETECTED ( cfg_dev_status_corr_err_detected ),
.CFGDEVSTATUSFATALERRDETECTED ( cfg_dev_status_fatal_err_detected ),
.CFGDEVSTATUSNONFATALERRDETECTED ( cfg_dev_status_nonfatal_err_detected ),
.CFGDEVSTATUSURDETECTED ( cfg_dev_status_ur_detected ),
.CFGDO ( cfg_do ),
.CFGDSN ( cfg_dsn ),
.CFGDWADDR ( cfg_dwaddr ),
.CFGERRCORN ( cfg_err_cor_n ),
.CFGERRCPLABORTN ( cfg_err_cpl_abort_n ),
.CFGERRCPLRDYN ( cfg_err_cpl_rdy_n ),
.CFGERRCPLTIMEOUTN ( cfg_err_cpl_timeout_n ),
.CFGERRECRCN ( cfg_err_ecrc_n ),
.CFGERRLOCKEDN ( cfg_err_locked_n ),
.CFGERRPOSTEDN ( cfg_err_posted_n ),
.CFGERRTLPCPLHEADER ( cfg_err_tlp_cpl_header ),
.CFGERRURN ( cfg_err_ur_n ),
.CFGFUNCTIONNUMBER ( cfg_function_number ),
.CFGINTERRUPTASSERTN ( cfg_interrupt_assert_n ),
.CFGINTERRUPTDI ( cfg_interrupt_di ),
.CFGINTERRUPTDO ( cfg_interrupt_do ),
.CFGINTERRUPTMMENABLE ( cfg_interrupt_mmenable ),
.CFGINTERRUPTMSIENABLE ( cfg_interrupt_msienable ),
.CFGINTERRUPTN ( cfg_interrupt_n ),
.CFGINTERRUPTRDYN ( cfg_interrupt_rdy_n ),
.CFGLINKCONTOLRCB ( cfg_link_control_rcb ),
.CFGLINKCONTROLASPMCONTROL ( cfg_link_control_aspm_control ),
.CFGLINKCONTROLCOMMONCLOCK ( cfg_link_control_common_clock ),
.CFGLINKCONTROLEXTENDEDSYNC ( cfg_link_control_extended_sync ),
.CFGLTSSMSTATE ( cfg_ltssm_state ),
.CFGPCIELINKSTATEN ( cfg_pcie_link_state_n ),
.CFGPMWAKEN ( cfg_pm_wake_n ),
.CFGRDENN ( cfg_rd_en_n ),
.CFGRDWRDONEN ( cfg_rd_wr_done_n ),
.CFGREVID ( w_cfg_rev_id ),
.CFGSUBSYSID ( w_cfg_subsys_id ),
.CFGSUBSYSVENID ( w_cfg_subsys_ven_id ),
.CFGTOTURNOFFN ( cfg_to_turnoff_n ),
.CFGTRNPENDINGN ( cfg_trn_pending_n ),
.CFGTURNOFFOKN ( cfg_turnoff_ok_n ),
.CFGVENID ( w_cfg_ven_id ),
.CLOCKLOCKED ( clock_locked ),
.DBGBADDLLPSTATUS ( dbg_bad_dllp_status ),
.DBGBADTLPLCRC ( dbg_bad_tlp_lcrc ),
.DBGBADTLPSEQNUM ( dbg_bad_tlp_seq_num ),
.DBGBADTLPSTATUS ( dbg_bad_tlp_status ),
.DBGDLPROTOCOLSTATUS ( dbg_dl_protocol_status ),
.DBGFCPROTOCOLERRSTATUS ( dbg_fc_protocol_err_status ),
.DBGMLFRMDLENGTH ( dbg_mlfrmd_length ),
.DBGMLFRMDMPS ( dbg_mlfrmd_mps ),
.DBGMLFRMDTCVC ( dbg_mlfrmd_tcvc ),
.DBGMLFRMDTLPSTATUS ( dbg_mlfrmd_tlp_status ),
.DBGMLFRMDUNRECTYPE ( dbg_mlfrmd_unrec_type ),
.DBGPOISTLPSTATUS ( dbg_poistlpstatus ),
.DBGRCVROVERFLOWSTATUS ( dbg_rcvr_overflow_status ),
.DBGREGDETECTEDCORRECTABLE ( dbg_reg_detected_correctable ),
.DBGREGDETECTEDFATAL ( dbg_reg_detected_fatal ),
.DBGREGDETECTEDNONFATAL ( dbg_reg_detected_non_fatal ),
.DBGREGDETECTEDUNSUPPORTED ( dbg_reg_detected_unsupported ),
.DBGRPLYROLLOVERSTATUS ( dbg_rply_rollover_status ),
.DBGRPLYTIMEOUTSTATUS ( dbg_rply_timeout_status ),
.DBGURNOBARHIT ( dbg_ur_no_bar_hit ),
.DBGURPOISCFGWR ( dbg_ur_pois_cfg_wr ),
.DBGURSTATUS ( dbg_ur_status ),
.DBGURUNSUPMSG ( dbg_ur_unsup_msg ),
.MGTCLK ( mgt_clk ),
.MIMRXRADDR ( mim_rx_raddr ),
.MIMRXRDATA ( mim_rx_rdata ),
.MIMRXREN ( mim_rx_ren ),
.MIMRXWADDR ( mim_rx_waddr ),
.MIMRXWDATA ( mim_rx_wdata ),
.MIMRXWEN ( mim_rx_wen ),
.MIMTXRADDR ( mim_tx_raddr ),
.MIMTXRDATA ( mim_tx_rdata ),
.MIMTXREN ( mim_tx_ren ),
.MIMTXWADDR ( mim_tx_waddr ),
.MIMTXWDATA ( mim_tx_wdata ),
.MIMTXWEN ( mim_tx_wen ),
.PIPEGTPOWERDOWNA ( pipe_gt_power_down_a ),
.PIPEGTPOWERDOWNB ( pipe_gt_power_down_b ),
.PIPEGTRESETDONEA ( pipe_gt_reset_done_a ),
.PIPEGTRESETDONEB ( pipe_gt_reset_done_b ),
.PIPEGTTXELECIDLEA ( pipe_gt_tx_elec_idle_a ),
.PIPEGTTXELECIDLEB ( pipe_gt_tx_elec_idle_b ),
.PIPEPHYSTATUSA ( pipe_phy_status_a ),
.PIPEPHYSTATUSB ( pipe_phy_status_b ),
.PIPERXCHARISKA ( pipe_rx_charisk_a ),
.PIPERXCHARISKB ( pipe_rx_charisk_b ),
.PIPERXDATAA ( pipe_rx_data_a ),
.PIPERXDATAB ( pipe_rx_data_b ),
.PIPERXENTERELECIDLEA ( pipe_rx_enter_elec_idle_a ),
.PIPERXENTERELECIDLEB ( pipe_rx_enter_elec_idle_b ),
.PIPERXPOLARITYA ( pipe_rx_polarity_a ),
.PIPERXPOLARITYB ( pipe_rx_polarity_b ),
.PIPERXRESETA ( pipe_rxreset_a ),
.PIPERXRESETB ( pipe_rxreset_b ),
.PIPERXSTATUSA ( pipe_rx_status_a ),
.PIPERXSTATUSB ( pipe_rx_status_b ),
.PIPETXCHARDISPMODEA ( pipe_tx_char_disp_mode_a ),
.PIPETXCHARDISPMODEB ( pipe_tx_char_disp_mode_b ),
.PIPETXCHARDISPVALA ( pipe_tx_char_disp_val_a ),
.PIPETXCHARDISPVALB ( pipe_tx_char_disp_val_b ),
.PIPETXCHARISKA ( pipe_tx_char_is_k_a ),
.PIPETXCHARISKB ( pipe_tx_char_is_k_b ),
.PIPETXDATAA ( pipe_tx_data_a ),
.PIPETXDATAB ( pipe_tx_data_b ),
.PIPETXRCVRDETA ( pipe_tx_rcvr_det_a ),
.PIPETXRCVRDETB ( pipe_tx_rcvr_det_b ),
.RECEIVEDHOTRESET ( received_hot_reset ),
.SYSRESETN ( sys_reset_n ),
.TRNFCCPLD ( trn_fc_cpld ),
.TRNFCCPLH ( trn_fc_cplh ),
.TRNFCNPD ( trn_fc_npd ),
.TRNFCNPH ( trn_fc_nph ),
.TRNFCPD ( trn_fc_pd ),
.TRNFCPH ( trn_fc_ph ),
.TRNFCSEL ( trn_fc_sel ),
.TRNLNKUPN ( trn_lnk_up_n ),
.TRNRBARHITN ( trn_rbar_hit_n ),
.TRNRD ( trn_rd ),
.TRNRDSTRDYN ( trn_rdst_rdy_n ),
.TRNREOFN ( trn_reof_n ),
.TRNRERRFWDN ( trn_rerrfwd_n ),
.TRNRNPOKN ( trn_rnp_ok_n ),
.TRNRSOFN ( trn_rsof_n ),
.TRNRSRCDSCN ( trn_rsrc_dsc_n ),
.TRNRSRCRDYN ( trn_rsrc_rdy_n ),
.TRNTBUFAV ( trn_tbuf_av ),
.TRNTCFGGNTN ( trn_tcfg_gnt_n ),
.TRNTCFGREQN ( trn_tcfg_req_n ),
.TRNTD ( trn_td ),
.TRNTDSTRDYN ( trn_tdst_rdy_n ),
.TRNTEOFN ( trn_teof_n ),
.TRNTERRDROPN ( trn_terr_drop_n ),
.TRNTERRFWDN ( trn_terrfwd_n ),
.TRNTSOFN ( trn_tsof_n ),
.TRNTSRCDSCN ( trn_tsrc_dsc_n ),
.TRNTSRCRDYN ( trn_tsrc_rdy_n ),
.TRNTSTRN ( trn_tstr_n ),
.USERCLK ( trn_clk ),
.USERRSTN ( trn_reset_n )
);
//***************************************************************************
// Recreate wrapper outputs from the PCIE_A1 signals.
//***************************************************************************
assign cfg_status = {16'b0};
assign cfg_command = {5'b0,
cfg_command_interrupt_disable,
1'b0,
cfg_command_serr_en,
5'b0,
cfg_command_bus_master_enable,
cfg_command_mem_enable,
cfg_command_io_enable};
assign cfg_dstatus = {10'h0,
!cfg_trn_pending_n,
1'b0,
cfg_dev_status_ur_detected,
cfg_dev_status_fatal_err_detected,
cfg_dev_status_nonfatal_err_detected,
cfg_dev_status_corr_err_detected};
assign cfg_dcommand = {1'b0,
cfg_dev_control_max_read_req,
cfg_dev_control_no_snoop_en,
cfg_dev_control_aux_power_en,
cfg_dev_control_phantom_en,
cfg_dev_control_ext_tag_en,
cfg_dev_control_max_payload,
cfg_dev_control_enable_ro,
cfg_dev_control_ur_err_reporting_en,
cfg_dev_control_fatal_err_reporting_en,
cfg_dev_control_non_fatal_reporting_en,
cfg_dev_control_corr_err_reporting_en};
assign cfg_lstatus = 16'h0011;
assign cfg_lcommand = {8'h0,
cfg_link_control_extended_sync,
cfg_link_control_common_clock,
2'b00,
cfg_link_control_rcb,
1'b0,
cfg_link_control_aspm_control};
endmodule
|
`timescale 1ns/1ps
//-----------------------------------------------------------------------------
// Title : ALU
// Project : KPU
//-----------------------------------------------------------------------------
// File : alu.v
// Author : acorallo <[email protected]>
// Created : 17.12.2016
//-----------------------------------------------------------------------------
// Description :
// Arithmetic logic implementation for KPU
//-----------------------------------------------------------------------------
// This file is part of KPU.
// KPU is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
// KPU is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY;
// without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with KPU. If not, see <http://www.gnu.org/licenses/>.
//
// Copyright (c) 2016 2017 by Andrea Corallo.
//------------------------------------------------------------------------------
// Modification history :
// 17.12.2016 : created
//-----------------------------------------------------------------------------
`ifndef _alu
`define _alu
`include "kpu_conf.v"
`include "uart_defines.v"
module alu(input wire [3:0] alu_op_i,
input wire [`N-1:0] a_i,
input wire [`N-1:0] b_i,
output reg [`N-1:0] out_o,
output reg [3:0] flags_o);
wire [`N-1:0] add_r;
wire [`N-1:0] sub_r;
wire oflow_add;
wire oflow_sub;
wire signed [`N-1:0] a_signed;
wire signed [`N-1:0] b_signed;
assign a_signed = a_i;
assign b_signed = b_i;
assign add_r = a_i + b_i;
assign sub_r = a_i - b_i;
assign oflow_add = (a_i[`N-1] == b_i[`N-1] && add_r[`N-1] != a_i[`N-1]) ?
1 : 0;
assign oflow_sub = (a_i[`N-1] == b_i[`N-1] && sub_r[`N-1] != a_i[`N-1]) ?
1 : 0;
always @(*) begin
if (alu_op_i != 4'hE) begin
flags_o[1] = a_i > b_i;
flags_o[2] = a_i == b_i;
flags_o[3] = out_o > 0;
end
else begin
flags_o[1] = a_signed > b_signed;
flags_o[2] = a_signed == b_signed;
flags_o[3] = out_o > 0;
end
case (alu_op_i)
4'h0: flags_o[0] = oflow_add; // add
4'h1: flags_o[0] = oflow_sub; // sub
default: flags_o[0] = 1'b0;
endcase
case (alu_op_i)
4'h0: out_o = add_r; // add
4'h1: out_o = sub_r; // sub
4'h2: out_o = a_i >> b_i; // shr
4'h3: out_o = a_i << b_i; // shl
4'h4: out_o = ~a_i; // not
4'h5: out_o = a_i & b_i; // and
4'h6: out_o = a_i | b_i; // or
4'h7: out_o = a_i ^ b_i; // xor
4'h8: out_o = a_i * b_i; // mult
4'h9: out_o = a_i / b_i; // div
4'hA: out_o = a_i % b_i; // mod
4'hF: out_o = a_i; // cmp
default: out_o = `N'h0; // latch prevention
endcase
end
endmodule // alu
`endif
|
//megafunction wizard: %Altera SOPC Builder%
//GENERATION: STANDARD
//VERSION: WM1.0
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arbitrator (
// inputs:
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata,
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest,
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_byteenable,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
reset_n,
// outputs:
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address,
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable,
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect,
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read,
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa,
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reset_n,
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa,
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write,
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata,
cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave,
cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave,
cpu_0_data_master_read_data_valid_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave,
cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave,
d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer
)
;
output [ 7: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address;
output [ 3: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable;
output Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect;
output Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read;
output [ 31: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa;
output Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reset_n;
output Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa;
output Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write;
output [ 31: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata;
output cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
output cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
output cpu_0_data_master_read_data_valid_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
output cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
output d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer;
input [ 31: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata;
input Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest;
input clk;
input [ 27: 0] cpu_0_data_master_address_to_slave;
input [ 3: 0] cpu_0_data_master_byteenable;
input cpu_0_data_master_read;
input cpu_0_data_master_waitrequest;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input reset_n;
wire [ 7: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_allgrants;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_allow_new_arb_cycle;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_any_bursting_master_saved_grant;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_any_continuerequest;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_counter_enable;
reg [ 2: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter;
wire [ 2: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter_next_value;
wire [ 2: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_set_values;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_beginbursttransfer_internal;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_begins_xfer;
wire [ 3: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_firsttransfer;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_grant_vector;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_in_a_read_cycle;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_in_a_write_cycle;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_master_qreq_vector;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_non_bursting_master_requests;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read;
wire [ 31: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa;
reg Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reg_firsttransfer;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reset_n;
reg Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_slavearbiterlockenable;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_slavearbiterlockenable2;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_unreg_firsttransfer;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waits_for_read;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waits_for_write;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write;
wire [ 31: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
wire cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
wire cpu_0_data_master_read_data_valid_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
wire cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
wire cpu_0_data_master_saved_grant_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
reg d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 27: 0] shifted_address_to_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_from_cpu_0_data_master;
wire wait_for_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer;
end
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave));
//assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata;
assign cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave = ({cpu_0_data_master_address_to_slave[27 : 10] , 10'b0} == 28'h400) & (cpu_0_data_master_read | cpu_0_data_master_write);
//assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter set values, which is an e_mux
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_set_values = 1;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_non_bursting_master_requests mux, which is an e_mux
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_non_bursting_master_requests = cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_any_bursting_master_saved_grant mux, which is an e_mux
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_any_bursting_master_saved_grant = 0;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter_next_value assignment, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter_next_value = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_firsttransfer ? (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_set_values - 1) : |Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter ? (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter - 1) : 0;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_allgrants all slave grants, which is an e_mux
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_allgrants = |Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_grant_vector;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer assignment, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer = ~(Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waits_for_read | Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waits_for_write);
//end_xfer_arb_share_counter_term_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer & (~Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter arbitration counter enable, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave & Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_allgrants) | (end_xfer_arb_share_counter_term_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave & ~Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_non_bursting_master_requests);
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter <= 0;
else if (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_counter_enable)
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter <= Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter_next_value;
end
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_slavearbiterlockenable <= 0;
else if ((|Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_master_qreq_vector & end_xfer_arb_share_counter_term_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave) | (end_xfer_arb_share_counter_term_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave & ~Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_non_bursting_master_requests))
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_slavearbiterlockenable <= |Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter_next_value;
end
//cpu_0/data_master Altera_UP_SD_Card_Avalon_Interface_0/avalon_sdcard_slave arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_slavearbiterlockenable2 = |Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter_next_value;
//cpu_0/data_master Altera_UP_SD_Card_Avalon_Interface_0/avalon_sdcard_slave arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_any_continuerequest at least one master continues requesting, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave = cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave & ~((cpu_0_data_master_read & (~cpu_0_data_master_waitrequest)) | ((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write));
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata mux, which is an e_mux
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata = cpu_0_data_master_writedata;
//master is always granted when requested
assign cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave = cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
//cpu_0/data_master saved-grant Altera_UP_SD_Card_Avalon_Interface_0/avalon_sdcard_slave, which is an e_assign
assign cpu_0_data_master_saved_grant_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave = cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
//allow new arb cycle for Altera_UP_SD_Card_Avalon_Interface_0/avalon_sdcard_slave, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_allow_new_arb_cycle = 1;
//placeholder chosen master
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_grant_vector = 1;
//placeholder vector of master qualified-requests
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_master_qreq_vector = 1;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reset_n assignment, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reset_n = reset_n;
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect = cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_firsttransfer first transaction, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_firsttransfer = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_begins_xfer ? Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_unreg_firsttransfer : Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reg_firsttransfer;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_unreg_firsttransfer first transaction, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_unreg_firsttransfer = ~(Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_slavearbiterlockenable & Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_any_continuerequest);
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reg_firsttransfer <= 1'b1;
else if (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_begins_xfer)
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reg_firsttransfer <= Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_unreg_firsttransfer;
end
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_beginbursttransfer_internal = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_begins_xfer;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read assignment, which is an e_mux
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read = cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave & cpu_0_data_master_read;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write assignment, which is an e_mux
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write = cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave & cpu_0_data_master_write;
assign shifted_address_to_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address mux, which is an e_mux
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address = shifted_address_to_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_from_cpu_0_data_master >> 2;
//d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer <= 1;
else
d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer <= Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer;
end
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waits_for_read in a cycle, which is an e_mux
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waits_for_read = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_in_a_read_cycle & Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_in_a_read_cycle assignment, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_in_a_read_cycle = cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_in_a_read_cycle;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waits_for_write in a cycle, which is an e_mux
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waits_for_write = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_in_a_write_cycle & Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_in_a_write_cycle assignment, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_in_a_write_cycle = cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_in_a_write_cycle;
assign wait_for_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_counter = 0;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable byte enable port mux, which is an e_mux
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable = (cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave)? cpu_0_data_master_byteenable :
-1;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Altera_UP_SD_Card_Avalon_Interface_0/avalon_sdcard_slave enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module clocks_avalon_clocks_slave_arbitrator (
// inputs:
clk,
clocks_avalon_clocks_slave_readdata,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_dbs_address,
cpu_0_data_master_read,
cpu_0_data_master_write,
reset_n,
// outputs:
clocks_avalon_clocks_slave_address,
clocks_avalon_clocks_slave_readdata_from_sa,
cpu_0_data_master_granted_clocks_avalon_clocks_slave,
cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave,
cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave,
cpu_0_data_master_requests_clocks_avalon_clocks_slave,
d1_clocks_avalon_clocks_slave_end_xfer,
registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave
)
;
output clocks_avalon_clocks_slave_address;
output [ 7: 0] clocks_avalon_clocks_slave_readdata_from_sa;
output cpu_0_data_master_granted_clocks_avalon_clocks_slave;
output cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave;
output cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave;
output cpu_0_data_master_requests_clocks_avalon_clocks_slave;
output d1_clocks_avalon_clocks_slave_end_xfer;
output registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave;
input clk;
input [ 7: 0] clocks_avalon_clocks_slave_readdata;
input [ 27: 0] cpu_0_data_master_address_to_slave;
input [ 1: 0] cpu_0_data_master_dbs_address;
input cpu_0_data_master_read;
input cpu_0_data_master_write;
input reset_n;
wire clocks_avalon_clocks_slave_address;
wire clocks_avalon_clocks_slave_allgrants;
wire clocks_avalon_clocks_slave_allow_new_arb_cycle;
wire clocks_avalon_clocks_slave_any_bursting_master_saved_grant;
wire clocks_avalon_clocks_slave_any_continuerequest;
wire clocks_avalon_clocks_slave_arb_counter_enable;
reg [ 2: 0] clocks_avalon_clocks_slave_arb_share_counter;
wire [ 2: 0] clocks_avalon_clocks_slave_arb_share_counter_next_value;
wire [ 2: 0] clocks_avalon_clocks_slave_arb_share_set_values;
wire clocks_avalon_clocks_slave_beginbursttransfer_internal;
wire clocks_avalon_clocks_slave_begins_xfer;
wire clocks_avalon_clocks_slave_end_xfer;
wire clocks_avalon_clocks_slave_firsttransfer;
wire clocks_avalon_clocks_slave_grant_vector;
wire clocks_avalon_clocks_slave_in_a_read_cycle;
wire clocks_avalon_clocks_slave_in_a_write_cycle;
wire clocks_avalon_clocks_slave_master_qreq_vector;
wire clocks_avalon_clocks_slave_non_bursting_master_requests;
wire [ 7: 0] clocks_avalon_clocks_slave_readdata_from_sa;
reg clocks_avalon_clocks_slave_reg_firsttransfer;
reg clocks_avalon_clocks_slave_slavearbiterlockenable;
wire clocks_avalon_clocks_slave_slavearbiterlockenable2;
wire clocks_avalon_clocks_slave_unreg_firsttransfer;
wire clocks_avalon_clocks_slave_waits_for_read;
wire clocks_avalon_clocks_slave_waits_for_write;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_clocks_avalon_clocks_slave;
wire cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave;
wire cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave;
reg cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register;
wire cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register_in;
wire cpu_0_data_master_requests_clocks_avalon_clocks_slave;
wire cpu_0_data_master_saved_grant_clocks_avalon_clocks_slave;
reg d1_clocks_avalon_clocks_slave_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_clocks_avalon_clocks_slave;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire p1_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register;
wire registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave;
wire wait_for_clocks_avalon_clocks_slave_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~clocks_avalon_clocks_slave_end_xfer;
end
assign clocks_avalon_clocks_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave));
//assign clocks_avalon_clocks_slave_readdata_from_sa = clocks_avalon_clocks_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign clocks_avalon_clocks_slave_readdata_from_sa = clocks_avalon_clocks_slave_readdata;
assign cpu_0_data_master_requests_clocks_avalon_clocks_slave = (({cpu_0_data_master_address_to_slave[27 : 1] , 1'b0} == 28'h28) & (cpu_0_data_master_read | cpu_0_data_master_write)) & cpu_0_data_master_read;
//registered rdv signal_name registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave assignment, which is an e_assign
assign registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave = cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register_in;
//clocks_avalon_clocks_slave_arb_share_counter set values, which is an e_mux
assign clocks_avalon_clocks_slave_arb_share_set_values = (cpu_0_data_master_granted_clocks_avalon_clocks_slave)? 4 :
1;
//clocks_avalon_clocks_slave_non_bursting_master_requests mux, which is an e_mux
assign clocks_avalon_clocks_slave_non_bursting_master_requests = cpu_0_data_master_requests_clocks_avalon_clocks_slave;
//clocks_avalon_clocks_slave_any_bursting_master_saved_grant mux, which is an e_mux
assign clocks_avalon_clocks_slave_any_bursting_master_saved_grant = 0;
//clocks_avalon_clocks_slave_arb_share_counter_next_value assignment, which is an e_assign
assign clocks_avalon_clocks_slave_arb_share_counter_next_value = clocks_avalon_clocks_slave_firsttransfer ? (clocks_avalon_clocks_slave_arb_share_set_values - 1) : |clocks_avalon_clocks_slave_arb_share_counter ? (clocks_avalon_clocks_slave_arb_share_counter - 1) : 0;
//clocks_avalon_clocks_slave_allgrants all slave grants, which is an e_mux
assign clocks_avalon_clocks_slave_allgrants = |clocks_avalon_clocks_slave_grant_vector;
//clocks_avalon_clocks_slave_end_xfer assignment, which is an e_assign
assign clocks_avalon_clocks_slave_end_xfer = ~(clocks_avalon_clocks_slave_waits_for_read | clocks_avalon_clocks_slave_waits_for_write);
//end_xfer_arb_share_counter_term_clocks_avalon_clocks_slave arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_clocks_avalon_clocks_slave = clocks_avalon_clocks_slave_end_xfer & (~clocks_avalon_clocks_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//clocks_avalon_clocks_slave_arb_share_counter arbitration counter enable, which is an e_assign
assign clocks_avalon_clocks_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_clocks_avalon_clocks_slave & clocks_avalon_clocks_slave_allgrants) | (end_xfer_arb_share_counter_term_clocks_avalon_clocks_slave & ~clocks_avalon_clocks_slave_non_bursting_master_requests);
//clocks_avalon_clocks_slave_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
clocks_avalon_clocks_slave_arb_share_counter <= 0;
else if (clocks_avalon_clocks_slave_arb_counter_enable)
clocks_avalon_clocks_slave_arb_share_counter <= clocks_avalon_clocks_slave_arb_share_counter_next_value;
end
//clocks_avalon_clocks_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
clocks_avalon_clocks_slave_slavearbiterlockenable <= 0;
else if ((|clocks_avalon_clocks_slave_master_qreq_vector & end_xfer_arb_share_counter_term_clocks_avalon_clocks_slave) | (end_xfer_arb_share_counter_term_clocks_avalon_clocks_slave & ~clocks_avalon_clocks_slave_non_bursting_master_requests))
clocks_avalon_clocks_slave_slavearbiterlockenable <= |clocks_avalon_clocks_slave_arb_share_counter_next_value;
end
//cpu_0/data_master clocks/avalon_clocks_slave arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = clocks_avalon_clocks_slave_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//clocks_avalon_clocks_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign clocks_avalon_clocks_slave_slavearbiterlockenable2 = |clocks_avalon_clocks_slave_arb_share_counter_next_value;
//cpu_0/data_master clocks/avalon_clocks_slave arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = clocks_avalon_clocks_slave_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//clocks_avalon_clocks_slave_any_continuerequest at least one master continues requesting, which is an e_assign
assign clocks_avalon_clocks_slave_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave = cpu_0_data_master_requests_clocks_avalon_clocks_slave & ~((cpu_0_data_master_read & ((|cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register))));
//cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register_in mux for readlatency shift register, which is an e_mux
assign cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register_in = cpu_0_data_master_granted_clocks_avalon_clocks_slave & cpu_0_data_master_read & ~clocks_avalon_clocks_slave_waits_for_read & ~(|cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register);
//shift register p1 cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register in if flush, otherwise shift left, which is an e_mux
assign p1_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register = {cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register, cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register_in};
//cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register for remembering which master asked for a fixed latency read, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register <= 0;
else
cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register <= p1_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register;
end
//local readdatavalid cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave, which is an e_mux
assign cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave = cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register;
//master is always granted when requested
assign cpu_0_data_master_granted_clocks_avalon_clocks_slave = cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave;
//cpu_0/data_master saved-grant clocks/avalon_clocks_slave, which is an e_assign
assign cpu_0_data_master_saved_grant_clocks_avalon_clocks_slave = cpu_0_data_master_requests_clocks_avalon_clocks_slave;
//allow new arb cycle for clocks/avalon_clocks_slave, which is an e_assign
assign clocks_avalon_clocks_slave_allow_new_arb_cycle = 1;
//placeholder chosen master
assign clocks_avalon_clocks_slave_grant_vector = 1;
//placeholder vector of master qualified-requests
assign clocks_avalon_clocks_slave_master_qreq_vector = 1;
//clocks_avalon_clocks_slave_firsttransfer first transaction, which is an e_assign
assign clocks_avalon_clocks_slave_firsttransfer = clocks_avalon_clocks_slave_begins_xfer ? clocks_avalon_clocks_slave_unreg_firsttransfer : clocks_avalon_clocks_slave_reg_firsttransfer;
//clocks_avalon_clocks_slave_unreg_firsttransfer first transaction, which is an e_assign
assign clocks_avalon_clocks_slave_unreg_firsttransfer = ~(clocks_avalon_clocks_slave_slavearbiterlockenable & clocks_avalon_clocks_slave_any_continuerequest);
//clocks_avalon_clocks_slave_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
clocks_avalon_clocks_slave_reg_firsttransfer <= 1'b1;
else if (clocks_avalon_clocks_slave_begins_xfer)
clocks_avalon_clocks_slave_reg_firsttransfer <= clocks_avalon_clocks_slave_unreg_firsttransfer;
end
//clocks_avalon_clocks_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign clocks_avalon_clocks_slave_beginbursttransfer_internal = clocks_avalon_clocks_slave_begins_xfer;
//clocks_avalon_clocks_slave_address mux, which is an e_mux
assign clocks_avalon_clocks_slave_address = {cpu_0_data_master_address_to_slave >> 2,
cpu_0_data_master_dbs_address[1 : 0]};
//d1_clocks_avalon_clocks_slave_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_clocks_avalon_clocks_slave_end_xfer <= 1;
else
d1_clocks_avalon_clocks_slave_end_xfer <= clocks_avalon_clocks_slave_end_xfer;
end
//clocks_avalon_clocks_slave_waits_for_read in a cycle, which is an e_mux
assign clocks_avalon_clocks_slave_waits_for_read = clocks_avalon_clocks_slave_in_a_read_cycle & 0;
//clocks_avalon_clocks_slave_in_a_read_cycle assignment, which is an e_assign
assign clocks_avalon_clocks_slave_in_a_read_cycle = cpu_0_data_master_granted_clocks_avalon_clocks_slave & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = clocks_avalon_clocks_slave_in_a_read_cycle;
//clocks_avalon_clocks_slave_waits_for_write in a cycle, which is an e_mux
assign clocks_avalon_clocks_slave_waits_for_write = clocks_avalon_clocks_slave_in_a_write_cycle & 0;
//clocks_avalon_clocks_slave_in_a_write_cycle assignment, which is an e_assign
assign clocks_avalon_clocks_slave_in_a_write_cycle = cpu_0_data_master_granted_clocks_avalon_clocks_slave & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = clocks_avalon_clocks_slave_in_a_write_cycle;
assign wait_for_clocks_avalon_clocks_slave_counter = 0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//clocks/avalon_clocks_slave enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_jtag_debug_module_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_byteenable,
cpu_0_data_master_debugaccess,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
cpu_0_instruction_master_address_to_slave,
cpu_0_instruction_master_read,
cpu_0_jtag_debug_module_readdata,
cpu_0_jtag_debug_module_resetrequest,
reset_n,
// outputs:
cpu_0_data_master_granted_cpu_0_jtag_debug_module,
cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module,
cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module,
cpu_0_data_master_requests_cpu_0_jtag_debug_module,
cpu_0_instruction_master_granted_cpu_0_jtag_debug_module,
cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module,
cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module,
cpu_0_instruction_master_requests_cpu_0_jtag_debug_module,
cpu_0_jtag_debug_module_address,
cpu_0_jtag_debug_module_begintransfer,
cpu_0_jtag_debug_module_byteenable,
cpu_0_jtag_debug_module_chipselect,
cpu_0_jtag_debug_module_debugaccess,
cpu_0_jtag_debug_module_readdata_from_sa,
cpu_0_jtag_debug_module_reset_n,
cpu_0_jtag_debug_module_resetrequest_from_sa,
cpu_0_jtag_debug_module_write,
cpu_0_jtag_debug_module_writedata,
d1_cpu_0_jtag_debug_module_end_xfer
)
;
output cpu_0_data_master_granted_cpu_0_jtag_debug_module;
output cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module;
output cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module;
output cpu_0_data_master_requests_cpu_0_jtag_debug_module;
output cpu_0_instruction_master_granted_cpu_0_jtag_debug_module;
output cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module;
output cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module;
output cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
output [ 8: 0] cpu_0_jtag_debug_module_address;
output cpu_0_jtag_debug_module_begintransfer;
output [ 3: 0] cpu_0_jtag_debug_module_byteenable;
output cpu_0_jtag_debug_module_chipselect;
output cpu_0_jtag_debug_module_debugaccess;
output [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
output cpu_0_jtag_debug_module_reset_n;
output cpu_0_jtag_debug_module_resetrequest_from_sa;
output cpu_0_jtag_debug_module_write;
output [ 31: 0] cpu_0_jtag_debug_module_writedata;
output d1_cpu_0_jtag_debug_module_end_xfer;
input clk;
input [ 27: 0] cpu_0_data_master_address_to_slave;
input [ 3: 0] cpu_0_data_master_byteenable;
input cpu_0_data_master_debugaccess;
input cpu_0_data_master_read;
input cpu_0_data_master_waitrequest;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input [ 27: 0] cpu_0_instruction_master_address_to_slave;
input cpu_0_instruction_master_read;
input [ 31: 0] cpu_0_jtag_debug_module_readdata;
input cpu_0_jtag_debug_module_resetrequest;
input reset_n;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_cpu_0_jtag_debug_module;
wire cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module;
wire cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module;
wire cpu_0_data_master_requests_cpu_0_jtag_debug_module;
wire cpu_0_data_master_saved_grant_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_arbiterlock;
wire cpu_0_instruction_master_arbiterlock2;
wire cpu_0_instruction_master_continuerequest;
wire cpu_0_instruction_master_granted_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_saved_grant_cpu_0_jtag_debug_module;
wire [ 8: 0] cpu_0_jtag_debug_module_address;
wire cpu_0_jtag_debug_module_allgrants;
wire cpu_0_jtag_debug_module_allow_new_arb_cycle;
wire cpu_0_jtag_debug_module_any_bursting_master_saved_grant;
wire cpu_0_jtag_debug_module_any_continuerequest;
reg [ 1: 0] cpu_0_jtag_debug_module_arb_addend;
wire cpu_0_jtag_debug_module_arb_counter_enable;
reg [ 2: 0] cpu_0_jtag_debug_module_arb_share_counter;
wire [ 2: 0] cpu_0_jtag_debug_module_arb_share_counter_next_value;
wire [ 2: 0] cpu_0_jtag_debug_module_arb_share_set_values;
wire [ 1: 0] cpu_0_jtag_debug_module_arb_winner;
wire cpu_0_jtag_debug_module_arbitration_holdoff_internal;
wire cpu_0_jtag_debug_module_beginbursttransfer_internal;
wire cpu_0_jtag_debug_module_begins_xfer;
wire cpu_0_jtag_debug_module_begintransfer;
wire [ 3: 0] cpu_0_jtag_debug_module_byteenable;
wire cpu_0_jtag_debug_module_chipselect;
wire [ 3: 0] cpu_0_jtag_debug_module_chosen_master_double_vector;
wire [ 1: 0] cpu_0_jtag_debug_module_chosen_master_rot_left;
wire cpu_0_jtag_debug_module_debugaccess;
wire cpu_0_jtag_debug_module_end_xfer;
wire cpu_0_jtag_debug_module_firsttransfer;
wire [ 1: 0] cpu_0_jtag_debug_module_grant_vector;
wire cpu_0_jtag_debug_module_in_a_read_cycle;
wire cpu_0_jtag_debug_module_in_a_write_cycle;
wire [ 1: 0] cpu_0_jtag_debug_module_master_qreq_vector;
wire cpu_0_jtag_debug_module_non_bursting_master_requests;
wire [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
reg cpu_0_jtag_debug_module_reg_firsttransfer;
wire cpu_0_jtag_debug_module_reset_n;
wire cpu_0_jtag_debug_module_resetrequest_from_sa;
reg [ 1: 0] cpu_0_jtag_debug_module_saved_chosen_master_vector;
reg cpu_0_jtag_debug_module_slavearbiterlockenable;
wire cpu_0_jtag_debug_module_slavearbiterlockenable2;
wire cpu_0_jtag_debug_module_unreg_firsttransfer;
wire cpu_0_jtag_debug_module_waits_for_read;
wire cpu_0_jtag_debug_module_waits_for_write;
wire cpu_0_jtag_debug_module_write;
wire [ 31: 0] cpu_0_jtag_debug_module_writedata;
reg d1_cpu_0_jtag_debug_module_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module;
wire in_a_read_cycle;
wire in_a_write_cycle;
reg last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module;
reg last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module;
wire [ 27: 0] shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_data_master;
wire [ 27: 0] shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_instruction_master;
wire wait_for_cpu_0_jtag_debug_module_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~cpu_0_jtag_debug_module_end_xfer;
end
assign cpu_0_jtag_debug_module_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module | cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module));
//assign cpu_0_jtag_debug_module_readdata_from_sa = cpu_0_jtag_debug_module_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign cpu_0_jtag_debug_module_readdata_from_sa = cpu_0_jtag_debug_module_readdata;
assign cpu_0_data_master_requests_cpu_0_jtag_debug_module = ({cpu_0_data_master_address_to_slave[27 : 11] , 11'b0} == 28'h800) & (cpu_0_data_master_read | cpu_0_data_master_write);
//cpu_0_jtag_debug_module_arb_share_counter set values, which is an e_mux
assign cpu_0_jtag_debug_module_arb_share_set_values = 1;
//cpu_0_jtag_debug_module_non_bursting_master_requests mux, which is an e_mux
assign cpu_0_jtag_debug_module_non_bursting_master_requests = cpu_0_data_master_requests_cpu_0_jtag_debug_module |
cpu_0_instruction_master_requests_cpu_0_jtag_debug_module |
cpu_0_data_master_requests_cpu_0_jtag_debug_module |
cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
//cpu_0_jtag_debug_module_any_bursting_master_saved_grant mux, which is an e_mux
assign cpu_0_jtag_debug_module_any_bursting_master_saved_grant = 0;
//cpu_0_jtag_debug_module_arb_share_counter_next_value assignment, which is an e_assign
assign cpu_0_jtag_debug_module_arb_share_counter_next_value = cpu_0_jtag_debug_module_firsttransfer ? (cpu_0_jtag_debug_module_arb_share_set_values - 1) : |cpu_0_jtag_debug_module_arb_share_counter ? (cpu_0_jtag_debug_module_arb_share_counter - 1) : 0;
//cpu_0_jtag_debug_module_allgrants all slave grants, which is an e_mux
assign cpu_0_jtag_debug_module_allgrants = (|cpu_0_jtag_debug_module_grant_vector) |
(|cpu_0_jtag_debug_module_grant_vector) |
(|cpu_0_jtag_debug_module_grant_vector) |
(|cpu_0_jtag_debug_module_grant_vector);
//cpu_0_jtag_debug_module_end_xfer assignment, which is an e_assign
assign cpu_0_jtag_debug_module_end_xfer = ~(cpu_0_jtag_debug_module_waits_for_read | cpu_0_jtag_debug_module_waits_for_write);
//end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_end_xfer & (~cpu_0_jtag_debug_module_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//cpu_0_jtag_debug_module_arb_share_counter arbitration counter enable, which is an e_assign
assign cpu_0_jtag_debug_module_arb_counter_enable = (end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module & cpu_0_jtag_debug_module_allgrants) | (end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module & ~cpu_0_jtag_debug_module_non_bursting_master_requests);
//cpu_0_jtag_debug_module_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_jtag_debug_module_arb_share_counter <= 0;
else if (cpu_0_jtag_debug_module_arb_counter_enable)
cpu_0_jtag_debug_module_arb_share_counter <= cpu_0_jtag_debug_module_arb_share_counter_next_value;
end
//cpu_0_jtag_debug_module_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_jtag_debug_module_slavearbiterlockenable <= 0;
else if ((|cpu_0_jtag_debug_module_master_qreq_vector & end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module) | (end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module & ~cpu_0_jtag_debug_module_non_bursting_master_requests))
cpu_0_jtag_debug_module_slavearbiterlockenable <= |cpu_0_jtag_debug_module_arb_share_counter_next_value;
end
//cpu_0/data_master cpu_0/jtag_debug_module arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = cpu_0_jtag_debug_module_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//cpu_0_jtag_debug_module_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign cpu_0_jtag_debug_module_slavearbiterlockenable2 = |cpu_0_jtag_debug_module_arb_share_counter_next_value;
//cpu_0/data_master cpu_0/jtag_debug_module arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = cpu_0_jtag_debug_module_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//cpu_0/instruction_master cpu_0/jtag_debug_module arbiterlock, which is an e_assign
assign cpu_0_instruction_master_arbiterlock = cpu_0_jtag_debug_module_slavearbiterlockenable & cpu_0_instruction_master_continuerequest;
//cpu_0/instruction_master cpu_0/jtag_debug_module arbiterlock2, which is an e_assign
assign cpu_0_instruction_master_arbiterlock2 = cpu_0_jtag_debug_module_slavearbiterlockenable2 & cpu_0_instruction_master_continuerequest;
//cpu_0/instruction_master granted cpu_0/jtag_debug_module last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module <= 0;
else
last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module <= cpu_0_instruction_master_saved_grant_cpu_0_jtag_debug_module ? 1 : (cpu_0_jtag_debug_module_arbitration_holdoff_internal | ~cpu_0_instruction_master_requests_cpu_0_jtag_debug_module) ? 0 : last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module;
end
//cpu_0_instruction_master_continuerequest continued request, which is an e_mux
assign cpu_0_instruction_master_continuerequest = last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module & cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
//cpu_0_jtag_debug_module_any_continuerequest at least one master continues requesting, which is an e_mux
assign cpu_0_jtag_debug_module_any_continuerequest = cpu_0_instruction_master_continuerequest |
cpu_0_data_master_continuerequest;
assign cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module = cpu_0_data_master_requests_cpu_0_jtag_debug_module & ~(((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write) | cpu_0_instruction_master_arbiterlock);
//cpu_0_jtag_debug_module_writedata mux, which is an e_mux
assign cpu_0_jtag_debug_module_writedata = cpu_0_data_master_writedata;
assign cpu_0_instruction_master_requests_cpu_0_jtag_debug_module = (({cpu_0_instruction_master_address_to_slave[27 : 11] , 11'b0} == 28'h800) & (cpu_0_instruction_master_read)) & cpu_0_instruction_master_read;
//cpu_0/data_master granted cpu_0/jtag_debug_module last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module <= 0;
else
last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module <= cpu_0_data_master_saved_grant_cpu_0_jtag_debug_module ? 1 : (cpu_0_jtag_debug_module_arbitration_holdoff_internal | ~cpu_0_data_master_requests_cpu_0_jtag_debug_module) ? 0 : last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module;
end
//cpu_0_data_master_continuerequest continued request, which is an e_mux
assign cpu_0_data_master_continuerequest = last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module & cpu_0_data_master_requests_cpu_0_jtag_debug_module;
assign cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module = cpu_0_instruction_master_requests_cpu_0_jtag_debug_module & ~(cpu_0_data_master_arbiterlock);
//allow new arb cycle for cpu_0/jtag_debug_module, which is an e_assign
assign cpu_0_jtag_debug_module_allow_new_arb_cycle = ~cpu_0_data_master_arbiterlock & ~cpu_0_instruction_master_arbiterlock;
//cpu_0/instruction_master assignment into master qualified-requests vector for cpu_0/jtag_debug_module, which is an e_assign
assign cpu_0_jtag_debug_module_master_qreq_vector[0] = cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module;
//cpu_0/instruction_master grant cpu_0/jtag_debug_module, which is an e_assign
assign cpu_0_instruction_master_granted_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_grant_vector[0];
//cpu_0/instruction_master saved-grant cpu_0/jtag_debug_module, which is an e_assign
assign cpu_0_instruction_master_saved_grant_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_arb_winner[0] && cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
//cpu_0/data_master assignment into master qualified-requests vector for cpu_0/jtag_debug_module, which is an e_assign
assign cpu_0_jtag_debug_module_master_qreq_vector[1] = cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module;
//cpu_0/data_master grant cpu_0/jtag_debug_module, which is an e_assign
assign cpu_0_data_master_granted_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_grant_vector[1];
//cpu_0/data_master saved-grant cpu_0/jtag_debug_module, which is an e_assign
assign cpu_0_data_master_saved_grant_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_arb_winner[1] && cpu_0_data_master_requests_cpu_0_jtag_debug_module;
//cpu_0/jtag_debug_module chosen-master double-vector, which is an e_assign
assign cpu_0_jtag_debug_module_chosen_master_double_vector = {cpu_0_jtag_debug_module_master_qreq_vector, cpu_0_jtag_debug_module_master_qreq_vector} & ({~cpu_0_jtag_debug_module_master_qreq_vector, ~cpu_0_jtag_debug_module_master_qreq_vector} + cpu_0_jtag_debug_module_arb_addend);
//stable onehot encoding of arb winner
assign cpu_0_jtag_debug_module_arb_winner = (cpu_0_jtag_debug_module_allow_new_arb_cycle & | cpu_0_jtag_debug_module_grant_vector) ? cpu_0_jtag_debug_module_grant_vector : cpu_0_jtag_debug_module_saved_chosen_master_vector;
//saved cpu_0_jtag_debug_module_grant_vector, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_jtag_debug_module_saved_chosen_master_vector <= 0;
else if (cpu_0_jtag_debug_module_allow_new_arb_cycle)
cpu_0_jtag_debug_module_saved_chosen_master_vector <= |cpu_0_jtag_debug_module_grant_vector ? cpu_0_jtag_debug_module_grant_vector : cpu_0_jtag_debug_module_saved_chosen_master_vector;
end
//onehot encoding of chosen master
assign cpu_0_jtag_debug_module_grant_vector = {(cpu_0_jtag_debug_module_chosen_master_double_vector[1] | cpu_0_jtag_debug_module_chosen_master_double_vector[3]),
(cpu_0_jtag_debug_module_chosen_master_double_vector[0] | cpu_0_jtag_debug_module_chosen_master_double_vector[2])};
//cpu_0/jtag_debug_module chosen master rotated left, which is an e_assign
assign cpu_0_jtag_debug_module_chosen_master_rot_left = (cpu_0_jtag_debug_module_arb_winner << 1) ? (cpu_0_jtag_debug_module_arb_winner << 1) : 1;
//cpu_0/jtag_debug_module's addend for next-master-grant
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_jtag_debug_module_arb_addend <= 1;
else if (|cpu_0_jtag_debug_module_grant_vector)
cpu_0_jtag_debug_module_arb_addend <= cpu_0_jtag_debug_module_end_xfer? cpu_0_jtag_debug_module_chosen_master_rot_left : cpu_0_jtag_debug_module_grant_vector;
end
assign cpu_0_jtag_debug_module_begintransfer = cpu_0_jtag_debug_module_begins_xfer;
//cpu_0_jtag_debug_module_reset_n assignment, which is an e_assign
assign cpu_0_jtag_debug_module_reset_n = reset_n;
//assign cpu_0_jtag_debug_module_resetrequest_from_sa = cpu_0_jtag_debug_module_resetrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
assign cpu_0_jtag_debug_module_resetrequest_from_sa = cpu_0_jtag_debug_module_resetrequest;
assign cpu_0_jtag_debug_module_chipselect = cpu_0_data_master_granted_cpu_0_jtag_debug_module | cpu_0_instruction_master_granted_cpu_0_jtag_debug_module;
//cpu_0_jtag_debug_module_firsttransfer first transaction, which is an e_assign
assign cpu_0_jtag_debug_module_firsttransfer = cpu_0_jtag_debug_module_begins_xfer ? cpu_0_jtag_debug_module_unreg_firsttransfer : cpu_0_jtag_debug_module_reg_firsttransfer;
//cpu_0_jtag_debug_module_unreg_firsttransfer first transaction, which is an e_assign
assign cpu_0_jtag_debug_module_unreg_firsttransfer = ~(cpu_0_jtag_debug_module_slavearbiterlockenable & cpu_0_jtag_debug_module_any_continuerequest);
//cpu_0_jtag_debug_module_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_jtag_debug_module_reg_firsttransfer <= 1'b1;
else if (cpu_0_jtag_debug_module_begins_xfer)
cpu_0_jtag_debug_module_reg_firsttransfer <= cpu_0_jtag_debug_module_unreg_firsttransfer;
end
//cpu_0_jtag_debug_module_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign cpu_0_jtag_debug_module_beginbursttransfer_internal = cpu_0_jtag_debug_module_begins_xfer;
//cpu_0_jtag_debug_module_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
assign cpu_0_jtag_debug_module_arbitration_holdoff_internal = cpu_0_jtag_debug_module_begins_xfer & cpu_0_jtag_debug_module_firsttransfer;
//cpu_0_jtag_debug_module_write assignment, which is an e_mux
assign cpu_0_jtag_debug_module_write = cpu_0_data_master_granted_cpu_0_jtag_debug_module & cpu_0_data_master_write;
assign shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//cpu_0_jtag_debug_module_address mux, which is an e_mux
assign cpu_0_jtag_debug_module_address = (cpu_0_data_master_granted_cpu_0_jtag_debug_module)? (shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_data_master >> 2) :
(shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_instruction_master >> 2);
assign shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_instruction_master = cpu_0_instruction_master_address_to_slave;
//d1_cpu_0_jtag_debug_module_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_cpu_0_jtag_debug_module_end_xfer <= 1;
else
d1_cpu_0_jtag_debug_module_end_xfer <= cpu_0_jtag_debug_module_end_xfer;
end
//cpu_0_jtag_debug_module_waits_for_read in a cycle, which is an e_mux
assign cpu_0_jtag_debug_module_waits_for_read = cpu_0_jtag_debug_module_in_a_read_cycle & cpu_0_jtag_debug_module_begins_xfer;
//cpu_0_jtag_debug_module_in_a_read_cycle assignment, which is an e_assign
assign cpu_0_jtag_debug_module_in_a_read_cycle = (cpu_0_data_master_granted_cpu_0_jtag_debug_module & cpu_0_data_master_read) | (cpu_0_instruction_master_granted_cpu_0_jtag_debug_module & cpu_0_instruction_master_read);
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = cpu_0_jtag_debug_module_in_a_read_cycle;
//cpu_0_jtag_debug_module_waits_for_write in a cycle, which is an e_mux
assign cpu_0_jtag_debug_module_waits_for_write = cpu_0_jtag_debug_module_in_a_write_cycle & 0;
//cpu_0_jtag_debug_module_in_a_write_cycle assignment, which is an e_assign
assign cpu_0_jtag_debug_module_in_a_write_cycle = cpu_0_data_master_granted_cpu_0_jtag_debug_module & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = cpu_0_jtag_debug_module_in_a_write_cycle;
assign wait_for_cpu_0_jtag_debug_module_counter = 0;
//cpu_0_jtag_debug_module_byteenable byte enable port mux, which is an e_mux
assign cpu_0_jtag_debug_module_byteenable = (cpu_0_data_master_granted_cpu_0_jtag_debug_module)? cpu_0_data_master_byteenable :
-1;
//debugaccess mux, which is an e_mux
assign cpu_0_jtag_debug_module_debugaccess = (cpu_0_data_master_granted_cpu_0_jtag_debug_module)? cpu_0_data_master_debugaccess :
0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//cpu_0/jtag_debug_module enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_0_data_master_granted_cpu_0_jtag_debug_module + cpu_0_instruction_master_granted_cpu_0_jtag_debug_module > 1)
begin
$write("%0d ns: > 1 of grant signals are active simultaneously", $time);
$stop;
end
end
//saved_grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_0_data_master_saved_grant_cpu_0_jtag_debug_module + cpu_0_instruction_master_saved_grant_cpu_0_jtag_debug_module > 1)
begin
$write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_data_master_arbitrator (
// inputs:
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa,
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa,
clk,
clocks_avalon_clocks_slave_readdata_from_sa,
cpu_0_data_master_address,
cpu_0_data_master_byteenable_nios_system_clock_1_in,
cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave,
cpu_0_data_master_granted_clocks_avalon_clocks_slave,
cpu_0_data_master_granted_cpu_0_jtag_debug_module,
cpu_0_data_master_granted_input1_s1,
cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave,
cpu_0_data_master_granted_nios_system_clock_0_in,
cpu_0_data_master_granted_nios_system_clock_1_in,
cpu_0_data_master_granted_onchip_memory2_0_s1,
cpu_0_data_master_granted_output1_s1,
cpu_0_data_master_granted_sdram_0_s1,
cpu_0_data_master_granted_sysid_control_slave,
cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave,
cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave,
cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module,
cpu_0_data_master_qualified_request_input1_s1,
cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave,
cpu_0_data_master_qualified_request_nios_system_clock_0_in,
cpu_0_data_master_qualified_request_nios_system_clock_1_in,
cpu_0_data_master_qualified_request_onchip_memory2_0_s1,
cpu_0_data_master_qualified_request_output1_s1,
cpu_0_data_master_qualified_request_sdram_0_s1,
cpu_0_data_master_qualified_request_sysid_control_slave,
cpu_0_data_master_read,
cpu_0_data_master_read_data_valid_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave,
cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave,
cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module,
cpu_0_data_master_read_data_valid_input1_s1,
cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave,
cpu_0_data_master_read_data_valid_nios_system_clock_0_in,
cpu_0_data_master_read_data_valid_nios_system_clock_1_in,
cpu_0_data_master_read_data_valid_onchip_memory2_0_s1,
cpu_0_data_master_read_data_valid_output1_s1,
cpu_0_data_master_read_data_valid_sdram_0_s1,
cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register,
cpu_0_data_master_read_data_valid_sysid_control_slave,
cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave,
cpu_0_data_master_requests_clocks_avalon_clocks_slave,
cpu_0_data_master_requests_cpu_0_jtag_debug_module,
cpu_0_data_master_requests_input1_s1,
cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave,
cpu_0_data_master_requests_nios_system_clock_0_in,
cpu_0_data_master_requests_nios_system_clock_1_in,
cpu_0_data_master_requests_onchip_memory2_0_s1,
cpu_0_data_master_requests_output1_s1,
cpu_0_data_master_requests_sdram_0_s1,
cpu_0_data_master_requests_sysid_control_slave,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
cpu_0_jtag_debug_module_readdata_from_sa,
d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer,
d1_clocks_avalon_clocks_slave_end_xfer,
d1_cpu_0_jtag_debug_module_end_xfer,
d1_input1_s1_end_xfer,
d1_jtag_uart_0_avalon_jtag_slave_end_xfer,
d1_nios_system_clock_0_in_end_xfer,
d1_nios_system_clock_1_in_end_xfer,
d1_onchip_memory2_0_s1_end_xfer,
d1_output1_s1_end_xfer,
d1_sdram_0_s1_end_xfer,
d1_sysid_control_slave_end_xfer,
input1_s1_readdata_from_sa,
jtag_uart_0_avalon_jtag_slave_irq_from_sa,
jtag_uart_0_avalon_jtag_slave_readdata_from_sa,
jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa,
nios_system_clock_0_in_readdata_from_sa,
nios_system_clock_0_in_waitrequest_from_sa,
nios_system_clock_1_in_readdata_from_sa,
nios_system_clock_1_in_waitrequest_from_sa,
onchip_memory2_0_s1_readdata_from_sa,
output1_s1_readdata_from_sa,
registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave,
registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1,
reset_n,
sdram_0_s1_readdata_from_sa,
sdram_0_s1_waitrequest_from_sa,
sysid_control_slave_readdata_from_sa,
// outputs:
cpu_0_data_master_address_to_slave,
cpu_0_data_master_dbs_address,
cpu_0_data_master_dbs_write_8,
cpu_0_data_master_irq,
cpu_0_data_master_no_byte_enables_and_last_term,
cpu_0_data_master_readdata,
cpu_0_data_master_waitrequest
)
;
output [ 27: 0] cpu_0_data_master_address_to_slave;
output [ 1: 0] cpu_0_data_master_dbs_address;
output [ 7: 0] cpu_0_data_master_dbs_write_8;
output [ 31: 0] cpu_0_data_master_irq;
output cpu_0_data_master_no_byte_enables_and_last_term;
output [ 31: 0] cpu_0_data_master_readdata;
output cpu_0_data_master_waitrequest;
input [ 31: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa;
input Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa;
input clk;
input [ 7: 0] clocks_avalon_clocks_slave_readdata_from_sa;
input [ 27: 0] cpu_0_data_master_address;
input cpu_0_data_master_byteenable_nios_system_clock_1_in;
input cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
input cpu_0_data_master_granted_clocks_avalon_clocks_slave;
input cpu_0_data_master_granted_cpu_0_jtag_debug_module;
input cpu_0_data_master_granted_input1_s1;
input cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave;
input cpu_0_data_master_granted_nios_system_clock_0_in;
input cpu_0_data_master_granted_nios_system_clock_1_in;
input cpu_0_data_master_granted_onchip_memory2_0_s1;
input cpu_0_data_master_granted_output1_s1;
input cpu_0_data_master_granted_sdram_0_s1;
input cpu_0_data_master_granted_sysid_control_slave;
input cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
input cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave;
input cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module;
input cpu_0_data_master_qualified_request_input1_s1;
input cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave;
input cpu_0_data_master_qualified_request_nios_system_clock_0_in;
input cpu_0_data_master_qualified_request_nios_system_clock_1_in;
input cpu_0_data_master_qualified_request_onchip_memory2_0_s1;
input cpu_0_data_master_qualified_request_output1_s1;
input cpu_0_data_master_qualified_request_sdram_0_s1;
input cpu_0_data_master_qualified_request_sysid_control_slave;
input cpu_0_data_master_read;
input cpu_0_data_master_read_data_valid_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
input cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave;
input cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module;
input cpu_0_data_master_read_data_valid_input1_s1;
input cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave;
input cpu_0_data_master_read_data_valid_nios_system_clock_0_in;
input cpu_0_data_master_read_data_valid_nios_system_clock_1_in;
input cpu_0_data_master_read_data_valid_onchip_memory2_0_s1;
input cpu_0_data_master_read_data_valid_output1_s1;
input cpu_0_data_master_read_data_valid_sdram_0_s1;
input cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register;
input cpu_0_data_master_read_data_valid_sysid_control_slave;
input cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
input cpu_0_data_master_requests_clocks_avalon_clocks_slave;
input cpu_0_data_master_requests_cpu_0_jtag_debug_module;
input cpu_0_data_master_requests_input1_s1;
input cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave;
input cpu_0_data_master_requests_nios_system_clock_0_in;
input cpu_0_data_master_requests_nios_system_clock_1_in;
input cpu_0_data_master_requests_onchip_memory2_0_s1;
input cpu_0_data_master_requests_output1_s1;
input cpu_0_data_master_requests_sdram_0_s1;
input cpu_0_data_master_requests_sysid_control_slave;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
input d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer;
input d1_clocks_avalon_clocks_slave_end_xfer;
input d1_cpu_0_jtag_debug_module_end_xfer;
input d1_input1_s1_end_xfer;
input d1_jtag_uart_0_avalon_jtag_slave_end_xfer;
input d1_nios_system_clock_0_in_end_xfer;
input d1_nios_system_clock_1_in_end_xfer;
input d1_onchip_memory2_0_s1_end_xfer;
input d1_output1_s1_end_xfer;
input d1_sdram_0_s1_end_xfer;
input d1_sysid_control_slave_end_xfer;
input [ 31: 0] input1_s1_readdata_from_sa;
input jtag_uart_0_avalon_jtag_slave_irq_from_sa;
input [ 31: 0] jtag_uart_0_avalon_jtag_slave_readdata_from_sa;
input jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa;
input [ 31: 0] nios_system_clock_0_in_readdata_from_sa;
input nios_system_clock_0_in_waitrequest_from_sa;
input [ 7: 0] nios_system_clock_1_in_readdata_from_sa;
input nios_system_clock_1_in_waitrequest_from_sa;
input [ 31: 0] onchip_memory2_0_s1_readdata_from_sa;
input [ 31: 0] output1_s1_readdata_from_sa;
input registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave;
input registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1;
input reset_n;
input [ 31: 0] sdram_0_s1_readdata_from_sa;
input sdram_0_s1_waitrequest_from_sa;
input [ 31: 0] sysid_control_slave_readdata_from_sa;
wire [ 27: 0] cpu_0_data_master_address_to_slave;
reg [ 1: 0] cpu_0_data_master_dbs_address;
wire [ 1: 0] cpu_0_data_master_dbs_increment;
wire [ 7: 0] cpu_0_data_master_dbs_write_8;
wire [ 31: 0] cpu_0_data_master_irq;
reg cpu_0_data_master_no_byte_enables_and_last_term;
wire [ 31: 0] cpu_0_data_master_readdata;
wire cpu_0_data_master_run;
reg cpu_0_data_master_waitrequest;
reg [ 7: 0] dbs_8_reg_segment_0;
reg [ 7: 0] dbs_8_reg_segment_1;
reg [ 7: 0] dbs_8_reg_segment_2;
wire dbs_count_enable;
wire dbs_counter_overflow;
wire last_dbs_term_and_run;
wire [ 1: 0] next_dbs_address;
wire [ 7: 0] p1_dbs_8_reg_segment_0;
wire [ 7: 0] p1_dbs_8_reg_segment_1;
wire [ 7: 0] p1_dbs_8_reg_segment_2;
wire [ 31: 0] p1_registered_cpu_0_data_master_readdata;
wire pre_dbs_count_enable;
wire r_0;
wire r_1;
wire r_2;
reg [ 31: 0] registered_cpu_0_data_master_readdata;
//r_0 master_run cascaded wait assignment, which is an e_assign
assign r_0 = 1 & (cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave | ~cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave) & ((~cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & ((cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave | (registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave & cpu_0_data_master_dbs_address[1] & cpu_0_data_master_dbs_address[0]) | ~cpu_0_data_master_requests_clocks_avalon_clocks_slave)) & ((~cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave | ~cpu_0_data_master_read | (registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave & (cpu_0_data_master_dbs_address[1] & cpu_0_data_master_dbs_address[0]) & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave | ~cpu_0_data_master_write | (1 & (cpu_0_data_master_dbs_address[1] & cpu_0_data_master_dbs_address[0]) & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module | ~cpu_0_data_master_requests_cpu_0_jtag_debug_module) & (cpu_0_data_master_granted_cpu_0_jtag_debug_module | ~cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module) & ((~cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & ((~cpu_0_data_master_qualified_request_input1_s1 | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_input1_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave | ~cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave) & ((~cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write))));
//cascaded wait assignment, which is an e_assign
assign cpu_0_data_master_run = r_0 & r_1 & r_2;
//r_1 master_run cascaded wait assignment, which is an e_assign
assign r_1 = 1 & (cpu_0_data_master_qualified_request_nios_system_clock_0_in | ~cpu_0_data_master_requests_nios_system_clock_0_in) & ((~cpu_0_data_master_qualified_request_nios_system_clock_0_in | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~nios_system_clock_0_in_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_nios_system_clock_0_in | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~nios_system_clock_0_in_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & ((cpu_0_data_master_qualified_request_nios_system_clock_1_in | ((cpu_0_data_master_write & !cpu_0_data_master_byteenable_nios_system_clock_1_in & cpu_0_data_master_dbs_address[1] & cpu_0_data_master_dbs_address[0])) | ~cpu_0_data_master_requests_nios_system_clock_1_in)) & ((~cpu_0_data_master_qualified_request_nios_system_clock_1_in | ~cpu_0_data_master_read | (1 & ~nios_system_clock_1_in_waitrequest_from_sa & (cpu_0_data_master_dbs_address[1] & cpu_0_data_master_dbs_address[0]) & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_nios_system_clock_1_in | ~cpu_0_data_master_write | (1 & ~nios_system_clock_1_in_waitrequest_from_sa & (cpu_0_data_master_dbs_address[1] & cpu_0_data_master_dbs_address[0]) & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_onchip_memory2_0_s1 | registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1 | ~cpu_0_data_master_requests_onchip_memory2_0_s1) & (cpu_0_data_master_granted_onchip_memory2_0_s1 | ~cpu_0_data_master_qualified_request_onchip_memory2_0_s1) & ((~cpu_0_data_master_qualified_request_onchip_memory2_0_s1 | ~cpu_0_data_master_read | (registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_onchip_memory2_0_s1 | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_output1_s1 | ~cpu_0_data_master_requests_output1_s1) & ((~cpu_0_data_master_qualified_request_output1_s1 | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_output1_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_sdram_0_s1 | cpu_0_data_master_read_data_valid_sdram_0_s1 | ~cpu_0_data_master_requests_sdram_0_s1) & (cpu_0_data_master_granted_sdram_0_s1 | ~cpu_0_data_master_qualified_request_sdram_0_s1);
//r_2 master_run cascaded wait assignment, which is an e_assign
assign r_2 = ((~cpu_0_data_master_qualified_request_sdram_0_s1 | ~cpu_0_data_master_read | (cpu_0_data_master_read_data_valid_sdram_0_s1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_sdram_0_s1 | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~sdram_0_s1_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & ((~cpu_0_data_master_qualified_request_sysid_control_slave | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_sysid_control_slave | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write)));
//optimize select-logic by passing only those address bits which matter.
assign cpu_0_data_master_address_to_slave = cpu_0_data_master_address[27 : 0];
//unpredictable registered wait state incoming data, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
registered_cpu_0_data_master_readdata <= 0;
else
registered_cpu_0_data_master_readdata <= p1_registered_cpu_0_data_master_readdata;
end
//registered readdata mux, which is an e_mux
assign p1_registered_cpu_0_data_master_readdata = ({32 {~cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave}} | Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa) &
({32 {~cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave}} | jtag_uart_0_avalon_jtag_slave_readdata_from_sa) &
({32 {~cpu_0_data_master_requests_nios_system_clock_0_in}} | nios_system_clock_0_in_readdata_from_sa) &
({32 {~cpu_0_data_master_requests_nios_system_clock_1_in}} | {nios_system_clock_1_in_readdata_from_sa[7 : 0],
dbs_8_reg_segment_2,
dbs_8_reg_segment_1,
dbs_8_reg_segment_0}) &
({32 {~cpu_0_data_master_requests_sdram_0_s1}} | sdram_0_s1_readdata_from_sa);
//cpu_0/data_master readdata mux, which is an e_mux
assign cpu_0_data_master_readdata = ({32 {~cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave}} | registered_cpu_0_data_master_readdata) &
({32 {~cpu_0_data_master_requests_clocks_avalon_clocks_slave}} | {clocks_avalon_clocks_slave_readdata_from_sa[7 : 0],
dbs_8_reg_segment_2,
dbs_8_reg_segment_1,
dbs_8_reg_segment_0}) &
({32 {~cpu_0_data_master_requests_cpu_0_jtag_debug_module}} | cpu_0_jtag_debug_module_readdata_from_sa) &
({32 {~cpu_0_data_master_requests_input1_s1}} | input1_s1_readdata_from_sa) &
({32 {~cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave}} | registered_cpu_0_data_master_readdata) &
({32 {~cpu_0_data_master_requests_nios_system_clock_0_in}} | registered_cpu_0_data_master_readdata) &
({32 {~cpu_0_data_master_requests_nios_system_clock_1_in}} | registered_cpu_0_data_master_readdata) &
({32 {~cpu_0_data_master_requests_onchip_memory2_0_s1}} | onchip_memory2_0_s1_readdata_from_sa) &
({32 {~cpu_0_data_master_requests_output1_s1}} | output1_s1_readdata_from_sa) &
({32 {~cpu_0_data_master_requests_sdram_0_s1}} | registered_cpu_0_data_master_readdata) &
({32 {~cpu_0_data_master_requests_sysid_control_slave}} | sysid_control_slave_readdata_from_sa);
//actual waitrequest port, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_data_master_waitrequest <= ~0;
else
cpu_0_data_master_waitrequest <= ~((~(cpu_0_data_master_read | cpu_0_data_master_write))? 0: (cpu_0_data_master_run & cpu_0_data_master_waitrequest));
end
//input to dbs-8 stored 0, which is an e_mux
assign p1_dbs_8_reg_segment_0 = (cpu_0_data_master_requests_clocks_avalon_clocks_slave)? clocks_avalon_clocks_slave_readdata_from_sa :
nios_system_clock_1_in_readdata_from_sa;
//dbs register for dbs-8 segment 0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbs_8_reg_segment_0 <= 0;
else if (dbs_count_enable & ((cpu_0_data_master_dbs_address[1 : 0]) == 0))
dbs_8_reg_segment_0 <= p1_dbs_8_reg_segment_0;
end
//input to dbs-8 stored 1, which is an e_mux
assign p1_dbs_8_reg_segment_1 = (cpu_0_data_master_requests_clocks_avalon_clocks_slave)? clocks_avalon_clocks_slave_readdata_from_sa :
nios_system_clock_1_in_readdata_from_sa;
//dbs register for dbs-8 segment 1, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbs_8_reg_segment_1 <= 0;
else if (dbs_count_enable & ((cpu_0_data_master_dbs_address[1 : 0]) == 1))
dbs_8_reg_segment_1 <= p1_dbs_8_reg_segment_1;
end
//input to dbs-8 stored 2, which is an e_mux
assign p1_dbs_8_reg_segment_2 = (cpu_0_data_master_requests_clocks_avalon_clocks_slave)? clocks_avalon_clocks_slave_readdata_from_sa :
nios_system_clock_1_in_readdata_from_sa;
//dbs register for dbs-8 segment 2, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbs_8_reg_segment_2 <= 0;
else if (dbs_count_enable & ((cpu_0_data_master_dbs_address[1 : 0]) == 2))
dbs_8_reg_segment_2 <= p1_dbs_8_reg_segment_2;
end
//dbs count increment, which is an e_mux
assign cpu_0_data_master_dbs_increment = (cpu_0_data_master_requests_clocks_avalon_clocks_slave)? 1 :
(cpu_0_data_master_requests_nios_system_clock_1_in)? 1 :
0;
//dbs counter overflow, which is an e_assign
assign dbs_counter_overflow = cpu_0_data_master_dbs_address[1] & !(next_dbs_address[1]);
//next master address, which is an e_assign
assign next_dbs_address = cpu_0_data_master_dbs_address + cpu_0_data_master_dbs_increment;
//dbs count enable, which is an e_mux
assign dbs_count_enable = pre_dbs_count_enable &
(~(cpu_0_data_master_requests_clocks_avalon_clocks_slave & ~cpu_0_data_master_waitrequest & cpu_0_data_master_write)) &
(~(cpu_0_data_master_requests_nios_system_clock_1_in & ~cpu_0_data_master_waitrequest));
//dbs counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_data_master_dbs_address <= 0;
else if (dbs_count_enable)
cpu_0_data_master_dbs_address <= next_dbs_address;
end
//pre dbs count enable, which is an e_mux
assign pre_dbs_count_enable = cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave |
(cpu_0_data_master_granted_clocks_avalon_clocks_slave & cpu_0_data_master_write & 1 & 1) |
(((~cpu_0_data_master_no_byte_enables_and_last_term) & cpu_0_data_master_requests_nios_system_clock_1_in & cpu_0_data_master_write & !cpu_0_data_master_byteenable_nios_system_clock_1_in)) |
(cpu_0_data_master_granted_nios_system_clock_1_in & cpu_0_data_master_read & 1 & 1 & ~nios_system_clock_1_in_waitrequest_from_sa) |
(cpu_0_data_master_granted_nios_system_clock_1_in & cpu_0_data_master_write & 1 & 1 & ~nios_system_clock_1_in_waitrequest_from_sa);
//irq assign, which is an e_assign
assign cpu_0_data_master_irq = {1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
jtag_uart_0_avalon_jtag_slave_irq_from_sa};
//no_byte_enables_and_last_term, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_data_master_no_byte_enables_and_last_term <= 0;
else
cpu_0_data_master_no_byte_enables_and_last_term <= last_dbs_term_and_run;
end
//compute the last dbs term, which is an e_mux
assign last_dbs_term_and_run = (cpu_0_data_master_dbs_address == 2'b11) & cpu_0_data_master_write & !cpu_0_data_master_byteenable_nios_system_clock_1_in;
//mux write dbs 2, which is an e_mux
assign cpu_0_data_master_dbs_write_8 = ((cpu_0_data_master_dbs_address[1 : 0] == 0))? cpu_0_data_master_writedata[7 : 0] :
((cpu_0_data_master_dbs_address[1 : 0] == 1))? cpu_0_data_master_writedata[15 : 8] :
((cpu_0_data_master_dbs_address[1 : 0] == 2))? cpu_0_data_master_writedata[23 : 16] :
cpu_0_data_master_writedata[31 : 24];
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_instruction_master_arbitrator (
// inputs:
clk,
cpu_0_instruction_master_address,
cpu_0_instruction_master_granted_cpu_0_jtag_debug_module,
cpu_0_instruction_master_granted_onchip_memory2_0_s1,
cpu_0_instruction_master_granted_sdram_0_s1,
cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module,
cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1,
cpu_0_instruction_master_qualified_request_sdram_0_s1,
cpu_0_instruction_master_read,
cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module,
cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1,
cpu_0_instruction_master_read_data_valid_sdram_0_s1,
cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register,
cpu_0_instruction_master_requests_cpu_0_jtag_debug_module,
cpu_0_instruction_master_requests_onchip_memory2_0_s1,
cpu_0_instruction_master_requests_sdram_0_s1,
cpu_0_jtag_debug_module_readdata_from_sa,
d1_cpu_0_jtag_debug_module_end_xfer,
d1_onchip_memory2_0_s1_end_xfer,
d1_sdram_0_s1_end_xfer,
onchip_memory2_0_s1_readdata_from_sa,
reset_n,
sdram_0_s1_readdata_from_sa,
sdram_0_s1_waitrequest_from_sa,
// outputs:
cpu_0_instruction_master_address_to_slave,
cpu_0_instruction_master_readdata,
cpu_0_instruction_master_waitrequest
)
;
output [ 27: 0] cpu_0_instruction_master_address_to_slave;
output [ 31: 0] cpu_0_instruction_master_readdata;
output cpu_0_instruction_master_waitrequest;
input clk;
input [ 27: 0] cpu_0_instruction_master_address;
input cpu_0_instruction_master_granted_cpu_0_jtag_debug_module;
input cpu_0_instruction_master_granted_onchip_memory2_0_s1;
input cpu_0_instruction_master_granted_sdram_0_s1;
input cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module;
input cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1;
input cpu_0_instruction_master_qualified_request_sdram_0_s1;
input cpu_0_instruction_master_read;
input cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module;
input cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1;
input cpu_0_instruction_master_read_data_valid_sdram_0_s1;
input cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register;
input cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
input cpu_0_instruction_master_requests_onchip_memory2_0_s1;
input cpu_0_instruction_master_requests_sdram_0_s1;
input [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
input d1_cpu_0_jtag_debug_module_end_xfer;
input d1_onchip_memory2_0_s1_end_xfer;
input d1_sdram_0_s1_end_xfer;
input [ 31: 0] onchip_memory2_0_s1_readdata_from_sa;
input reset_n;
input [ 31: 0] sdram_0_s1_readdata_from_sa;
input sdram_0_s1_waitrequest_from_sa;
reg active_and_waiting_last_time;
reg [ 27: 0] cpu_0_instruction_master_address_last_time;
wire [ 27: 0] cpu_0_instruction_master_address_to_slave;
reg cpu_0_instruction_master_read_last_time;
wire [ 31: 0] cpu_0_instruction_master_readdata;
wire cpu_0_instruction_master_run;
wire cpu_0_instruction_master_waitrequest;
wire r_0;
wire r_1;
wire r_2;
//r_0 master_run cascaded wait assignment, which is an e_assign
assign r_0 = 1 & (cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module | ~cpu_0_instruction_master_requests_cpu_0_jtag_debug_module) & (cpu_0_instruction_master_granted_cpu_0_jtag_debug_module | ~cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module) & ((~cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module | ~cpu_0_instruction_master_read | (1 & ~d1_cpu_0_jtag_debug_module_end_xfer & cpu_0_instruction_master_read)));
//cascaded wait assignment, which is an e_assign
assign cpu_0_instruction_master_run = r_0 & r_1 & r_2;
//r_1 master_run cascaded wait assignment, which is an e_assign
assign r_1 = 1 & (cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1 | cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1 | ~cpu_0_instruction_master_requests_onchip_memory2_0_s1) & (cpu_0_instruction_master_granted_onchip_memory2_0_s1 | ~cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1) & ((~cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1 | ~cpu_0_instruction_master_read | (cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1 & cpu_0_instruction_master_read))) & 1 & (cpu_0_instruction_master_qualified_request_sdram_0_s1 | cpu_0_instruction_master_read_data_valid_sdram_0_s1 | ~cpu_0_instruction_master_requests_sdram_0_s1);
//r_2 master_run cascaded wait assignment, which is an e_assign
assign r_2 = (cpu_0_instruction_master_granted_sdram_0_s1 | ~cpu_0_instruction_master_qualified_request_sdram_0_s1) & ((~cpu_0_instruction_master_qualified_request_sdram_0_s1 | ~cpu_0_instruction_master_read | (cpu_0_instruction_master_read_data_valid_sdram_0_s1 & cpu_0_instruction_master_read)));
//optimize select-logic by passing only those address bits which matter.
assign cpu_0_instruction_master_address_to_slave = cpu_0_instruction_master_address[27 : 0];
//cpu_0/instruction_master readdata mux, which is an e_mux
assign cpu_0_instruction_master_readdata = ({32 {~cpu_0_instruction_master_requests_cpu_0_jtag_debug_module}} | cpu_0_jtag_debug_module_readdata_from_sa) &
({32 {~cpu_0_instruction_master_requests_onchip_memory2_0_s1}} | onchip_memory2_0_s1_readdata_from_sa) &
({32 {~cpu_0_instruction_master_requests_sdram_0_s1}} | sdram_0_s1_readdata_from_sa);
//actual waitrequest port, which is an e_assign
assign cpu_0_instruction_master_waitrequest = ~cpu_0_instruction_master_run;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//cpu_0_instruction_master_address check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_instruction_master_address_last_time <= 0;
else
cpu_0_instruction_master_address_last_time <= cpu_0_instruction_master_address;
end
//cpu_0/instruction_master waited last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
active_and_waiting_last_time <= 0;
else
active_and_waiting_last_time <= cpu_0_instruction_master_waitrequest & (cpu_0_instruction_master_read);
end
//cpu_0_instruction_master_address matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (cpu_0_instruction_master_address != cpu_0_instruction_master_address_last_time))
begin
$write("%0d ns: cpu_0_instruction_master_address did not heed wait!!!", $time);
$stop;
end
end
//cpu_0_instruction_master_read check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_instruction_master_read_last_time <= 0;
else
cpu_0_instruction_master_read_last_time <= cpu_0_instruction_master_read;
end
//cpu_0_instruction_master_read matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (cpu_0_instruction_master_read != cpu_0_instruction_master_read_last_time))
begin
$write("%0d ns: cpu_0_instruction_master_read did not heed wait!!!", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module input1_s1_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_read,
cpu_0_data_master_write,
input1_s1_readdata,
reset_n,
// outputs:
cpu_0_data_master_granted_input1_s1,
cpu_0_data_master_qualified_request_input1_s1,
cpu_0_data_master_read_data_valid_input1_s1,
cpu_0_data_master_requests_input1_s1,
d1_input1_s1_end_xfer,
input1_s1_address,
input1_s1_readdata_from_sa,
input1_s1_reset_n
)
;
output cpu_0_data_master_granted_input1_s1;
output cpu_0_data_master_qualified_request_input1_s1;
output cpu_0_data_master_read_data_valid_input1_s1;
output cpu_0_data_master_requests_input1_s1;
output d1_input1_s1_end_xfer;
output [ 1: 0] input1_s1_address;
output [ 31: 0] input1_s1_readdata_from_sa;
output input1_s1_reset_n;
input clk;
input [ 27: 0] cpu_0_data_master_address_to_slave;
input cpu_0_data_master_read;
input cpu_0_data_master_write;
input [ 31: 0] input1_s1_readdata;
input reset_n;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_input1_s1;
wire cpu_0_data_master_qualified_request_input1_s1;
wire cpu_0_data_master_read_data_valid_input1_s1;
wire cpu_0_data_master_requests_input1_s1;
wire cpu_0_data_master_saved_grant_input1_s1;
reg d1_input1_s1_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_input1_s1;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 1: 0] input1_s1_address;
wire input1_s1_allgrants;
wire input1_s1_allow_new_arb_cycle;
wire input1_s1_any_bursting_master_saved_grant;
wire input1_s1_any_continuerequest;
wire input1_s1_arb_counter_enable;
reg [ 2: 0] input1_s1_arb_share_counter;
wire [ 2: 0] input1_s1_arb_share_counter_next_value;
wire [ 2: 0] input1_s1_arb_share_set_values;
wire input1_s1_beginbursttransfer_internal;
wire input1_s1_begins_xfer;
wire input1_s1_end_xfer;
wire input1_s1_firsttransfer;
wire input1_s1_grant_vector;
wire input1_s1_in_a_read_cycle;
wire input1_s1_in_a_write_cycle;
wire input1_s1_master_qreq_vector;
wire input1_s1_non_bursting_master_requests;
wire [ 31: 0] input1_s1_readdata_from_sa;
reg input1_s1_reg_firsttransfer;
wire input1_s1_reset_n;
reg input1_s1_slavearbiterlockenable;
wire input1_s1_slavearbiterlockenable2;
wire input1_s1_unreg_firsttransfer;
wire input1_s1_waits_for_read;
wire input1_s1_waits_for_write;
wire [ 27: 0] shifted_address_to_input1_s1_from_cpu_0_data_master;
wire wait_for_input1_s1_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~input1_s1_end_xfer;
end
assign input1_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_input1_s1));
//assign input1_s1_readdata_from_sa = input1_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign input1_s1_readdata_from_sa = input1_s1_readdata;
assign cpu_0_data_master_requests_input1_s1 = (({cpu_0_data_master_address_to_slave[27 : 4] , 4'b0} == 28'h10) & (cpu_0_data_master_read | cpu_0_data_master_write)) & cpu_0_data_master_read;
//input1_s1_arb_share_counter set values, which is an e_mux
assign input1_s1_arb_share_set_values = 1;
//input1_s1_non_bursting_master_requests mux, which is an e_mux
assign input1_s1_non_bursting_master_requests = cpu_0_data_master_requests_input1_s1;
//input1_s1_any_bursting_master_saved_grant mux, which is an e_mux
assign input1_s1_any_bursting_master_saved_grant = 0;
//input1_s1_arb_share_counter_next_value assignment, which is an e_assign
assign input1_s1_arb_share_counter_next_value = input1_s1_firsttransfer ? (input1_s1_arb_share_set_values - 1) : |input1_s1_arb_share_counter ? (input1_s1_arb_share_counter - 1) : 0;
//input1_s1_allgrants all slave grants, which is an e_mux
assign input1_s1_allgrants = |input1_s1_grant_vector;
//input1_s1_end_xfer assignment, which is an e_assign
assign input1_s1_end_xfer = ~(input1_s1_waits_for_read | input1_s1_waits_for_write);
//end_xfer_arb_share_counter_term_input1_s1 arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_input1_s1 = input1_s1_end_xfer & (~input1_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//input1_s1_arb_share_counter arbitration counter enable, which is an e_assign
assign input1_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_input1_s1 & input1_s1_allgrants) | (end_xfer_arb_share_counter_term_input1_s1 & ~input1_s1_non_bursting_master_requests);
//input1_s1_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
input1_s1_arb_share_counter <= 0;
else if (input1_s1_arb_counter_enable)
input1_s1_arb_share_counter <= input1_s1_arb_share_counter_next_value;
end
//input1_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
input1_s1_slavearbiterlockenable <= 0;
else if ((|input1_s1_master_qreq_vector & end_xfer_arb_share_counter_term_input1_s1) | (end_xfer_arb_share_counter_term_input1_s1 & ~input1_s1_non_bursting_master_requests))
input1_s1_slavearbiterlockenable <= |input1_s1_arb_share_counter_next_value;
end
//cpu_0/data_master input1/s1 arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = input1_s1_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//input1_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign input1_s1_slavearbiterlockenable2 = |input1_s1_arb_share_counter_next_value;
//cpu_0/data_master input1/s1 arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = input1_s1_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//input1_s1_any_continuerequest at least one master continues requesting, which is an e_assign
assign input1_s1_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_input1_s1 = cpu_0_data_master_requests_input1_s1;
//master is always granted when requested
assign cpu_0_data_master_granted_input1_s1 = cpu_0_data_master_qualified_request_input1_s1;
//cpu_0/data_master saved-grant input1/s1, which is an e_assign
assign cpu_0_data_master_saved_grant_input1_s1 = cpu_0_data_master_requests_input1_s1;
//allow new arb cycle for input1/s1, which is an e_assign
assign input1_s1_allow_new_arb_cycle = 1;
//placeholder chosen master
assign input1_s1_grant_vector = 1;
//placeholder vector of master qualified-requests
assign input1_s1_master_qreq_vector = 1;
//input1_s1_reset_n assignment, which is an e_assign
assign input1_s1_reset_n = reset_n;
//input1_s1_firsttransfer first transaction, which is an e_assign
assign input1_s1_firsttransfer = input1_s1_begins_xfer ? input1_s1_unreg_firsttransfer : input1_s1_reg_firsttransfer;
//input1_s1_unreg_firsttransfer first transaction, which is an e_assign
assign input1_s1_unreg_firsttransfer = ~(input1_s1_slavearbiterlockenable & input1_s1_any_continuerequest);
//input1_s1_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
input1_s1_reg_firsttransfer <= 1'b1;
else if (input1_s1_begins_xfer)
input1_s1_reg_firsttransfer <= input1_s1_unreg_firsttransfer;
end
//input1_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign input1_s1_beginbursttransfer_internal = input1_s1_begins_xfer;
assign shifted_address_to_input1_s1_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//input1_s1_address mux, which is an e_mux
assign input1_s1_address = shifted_address_to_input1_s1_from_cpu_0_data_master >> 2;
//d1_input1_s1_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_input1_s1_end_xfer <= 1;
else
d1_input1_s1_end_xfer <= input1_s1_end_xfer;
end
//input1_s1_waits_for_read in a cycle, which is an e_mux
assign input1_s1_waits_for_read = input1_s1_in_a_read_cycle & input1_s1_begins_xfer;
//input1_s1_in_a_read_cycle assignment, which is an e_assign
assign input1_s1_in_a_read_cycle = cpu_0_data_master_granted_input1_s1 & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = input1_s1_in_a_read_cycle;
//input1_s1_waits_for_write in a cycle, which is an e_mux
assign input1_s1_waits_for_write = input1_s1_in_a_write_cycle & 0;
//input1_s1_in_a_write_cycle assignment, which is an e_assign
assign input1_s1_in_a_write_cycle = cpu_0_data_master_granted_input1_s1 & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = input1_s1_in_a_write_cycle;
assign wait_for_input1_s1_counter = 0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//input1/s1 enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jtag_uart_0_avalon_jtag_slave_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
jtag_uart_0_avalon_jtag_slave_dataavailable,
jtag_uart_0_avalon_jtag_slave_irq,
jtag_uart_0_avalon_jtag_slave_readdata,
jtag_uart_0_avalon_jtag_slave_readyfordata,
jtag_uart_0_avalon_jtag_slave_waitrequest,
reset_n,
// outputs:
cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave,
cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave,
cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave,
cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave,
d1_jtag_uart_0_avalon_jtag_slave_end_xfer,
jtag_uart_0_avalon_jtag_slave_address,
jtag_uart_0_avalon_jtag_slave_chipselect,
jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa,
jtag_uart_0_avalon_jtag_slave_irq_from_sa,
jtag_uart_0_avalon_jtag_slave_read_n,
jtag_uart_0_avalon_jtag_slave_readdata_from_sa,
jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa,
jtag_uart_0_avalon_jtag_slave_reset_n,
jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa,
jtag_uart_0_avalon_jtag_slave_write_n,
jtag_uart_0_avalon_jtag_slave_writedata
)
;
output cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave;
output cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave;
output cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave;
output cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave;
output d1_jtag_uart_0_avalon_jtag_slave_end_xfer;
output jtag_uart_0_avalon_jtag_slave_address;
output jtag_uart_0_avalon_jtag_slave_chipselect;
output jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa;
output jtag_uart_0_avalon_jtag_slave_irq_from_sa;
output jtag_uart_0_avalon_jtag_slave_read_n;
output [ 31: 0] jtag_uart_0_avalon_jtag_slave_readdata_from_sa;
output jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa;
output jtag_uart_0_avalon_jtag_slave_reset_n;
output jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa;
output jtag_uart_0_avalon_jtag_slave_write_n;
output [ 31: 0] jtag_uart_0_avalon_jtag_slave_writedata;
input clk;
input [ 27: 0] cpu_0_data_master_address_to_slave;
input cpu_0_data_master_read;
input cpu_0_data_master_waitrequest;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input jtag_uart_0_avalon_jtag_slave_dataavailable;
input jtag_uart_0_avalon_jtag_slave_irq;
input [ 31: 0] jtag_uart_0_avalon_jtag_slave_readdata;
input jtag_uart_0_avalon_jtag_slave_readyfordata;
input jtag_uart_0_avalon_jtag_slave_waitrequest;
input reset_n;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave;
wire cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave;
wire cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave;
wire cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave;
wire cpu_0_data_master_saved_grant_jtag_uart_0_avalon_jtag_slave;
reg d1_jtag_uart_0_avalon_jtag_slave_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire jtag_uart_0_avalon_jtag_slave_address;
wire jtag_uart_0_avalon_jtag_slave_allgrants;
wire jtag_uart_0_avalon_jtag_slave_allow_new_arb_cycle;
wire jtag_uart_0_avalon_jtag_slave_any_bursting_master_saved_grant;
wire jtag_uart_0_avalon_jtag_slave_any_continuerequest;
wire jtag_uart_0_avalon_jtag_slave_arb_counter_enable;
reg [ 2: 0] jtag_uart_0_avalon_jtag_slave_arb_share_counter;
wire [ 2: 0] jtag_uart_0_avalon_jtag_slave_arb_share_counter_next_value;
wire [ 2: 0] jtag_uart_0_avalon_jtag_slave_arb_share_set_values;
wire jtag_uart_0_avalon_jtag_slave_beginbursttransfer_internal;
wire jtag_uart_0_avalon_jtag_slave_begins_xfer;
wire jtag_uart_0_avalon_jtag_slave_chipselect;
wire jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa;
wire jtag_uart_0_avalon_jtag_slave_end_xfer;
wire jtag_uart_0_avalon_jtag_slave_firsttransfer;
wire jtag_uart_0_avalon_jtag_slave_grant_vector;
wire jtag_uart_0_avalon_jtag_slave_in_a_read_cycle;
wire jtag_uart_0_avalon_jtag_slave_in_a_write_cycle;
wire jtag_uart_0_avalon_jtag_slave_irq_from_sa;
wire jtag_uart_0_avalon_jtag_slave_master_qreq_vector;
wire jtag_uart_0_avalon_jtag_slave_non_bursting_master_requests;
wire jtag_uart_0_avalon_jtag_slave_read_n;
wire [ 31: 0] jtag_uart_0_avalon_jtag_slave_readdata_from_sa;
wire jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa;
reg jtag_uart_0_avalon_jtag_slave_reg_firsttransfer;
wire jtag_uart_0_avalon_jtag_slave_reset_n;
reg jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable;
wire jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable2;
wire jtag_uart_0_avalon_jtag_slave_unreg_firsttransfer;
wire jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa;
wire jtag_uart_0_avalon_jtag_slave_waits_for_read;
wire jtag_uart_0_avalon_jtag_slave_waits_for_write;
wire jtag_uart_0_avalon_jtag_slave_write_n;
wire [ 31: 0] jtag_uart_0_avalon_jtag_slave_writedata;
wire [ 27: 0] shifted_address_to_jtag_uart_0_avalon_jtag_slave_from_cpu_0_data_master;
wire wait_for_jtag_uart_0_avalon_jtag_slave_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~jtag_uart_0_avalon_jtag_slave_end_xfer;
end
assign jtag_uart_0_avalon_jtag_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave));
//assign jtag_uart_0_avalon_jtag_slave_readdata_from_sa = jtag_uart_0_avalon_jtag_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_readdata_from_sa = jtag_uart_0_avalon_jtag_slave_readdata;
assign cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave = ({cpu_0_data_master_address_to_slave[27 : 3] , 3'b0} == 28'h20) & (cpu_0_data_master_read | cpu_0_data_master_write);
//assign jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_0_avalon_jtag_slave_dataavailable so that symbol knows where to group signals which may go to master only, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_0_avalon_jtag_slave_dataavailable;
//assign jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_0_avalon_jtag_slave_readyfordata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_0_avalon_jtag_slave_readyfordata;
//assign jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_0_avalon_jtag_slave_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_0_avalon_jtag_slave_waitrequest;
//jtag_uart_0_avalon_jtag_slave_arb_share_counter set values, which is an e_mux
assign jtag_uart_0_avalon_jtag_slave_arb_share_set_values = 1;
//jtag_uart_0_avalon_jtag_slave_non_bursting_master_requests mux, which is an e_mux
assign jtag_uart_0_avalon_jtag_slave_non_bursting_master_requests = cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave;
//jtag_uart_0_avalon_jtag_slave_any_bursting_master_saved_grant mux, which is an e_mux
assign jtag_uart_0_avalon_jtag_slave_any_bursting_master_saved_grant = 0;
//jtag_uart_0_avalon_jtag_slave_arb_share_counter_next_value assignment, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_arb_share_counter_next_value = jtag_uart_0_avalon_jtag_slave_firsttransfer ? (jtag_uart_0_avalon_jtag_slave_arb_share_set_values - 1) : |jtag_uart_0_avalon_jtag_slave_arb_share_counter ? (jtag_uart_0_avalon_jtag_slave_arb_share_counter - 1) : 0;
//jtag_uart_0_avalon_jtag_slave_allgrants all slave grants, which is an e_mux
assign jtag_uart_0_avalon_jtag_slave_allgrants = |jtag_uart_0_avalon_jtag_slave_grant_vector;
//jtag_uart_0_avalon_jtag_slave_end_xfer assignment, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_end_xfer = ~(jtag_uart_0_avalon_jtag_slave_waits_for_read | jtag_uart_0_avalon_jtag_slave_waits_for_write);
//end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave = jtag_uart_0_avalon_jtag_slave_end_xfer & (~jtag_uart_0_avalon_jtag_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//jtag_uart_0_avalon_jtag_slave_arb_share_counter arbitration counter enable, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave & jtag_uart_0_avalon_jtag_slave_allgrants) | (end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave & ~jtag_uart_0_avalon_jtag_slave_non_bursting_master_requests);
//jtag_uart_0_avalon_jtag_slave_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
jtag_uart_0_avalon_jtag_slave_arb_share_counter <= 0;
else if (jtag_uart_0_avalon_jtag_slave_arb_counter_enable)
jtag_uart_0_avalon_jtag_slave_arb_share_counter <= jtag_uart_0_avalon_jtag_slave_arb_share_counter_next_value;
end
//jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable <= 0;
else if ((|jtag_uart_0_avalon_jtag_slave_master_qreq_vector & end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave) | (end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave & ~jtag_uart_0_avalon_jtag_slave_non_bursting_master_requests))
jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable <= |jtag_uart_0_avalon_jtag_slave_arb_share_counter_next_value;
end
//cpu_0/data_master jtag_uart_0/avalon_jtag_slave arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable2 = |jtag_uart_0_avalon_jtag_slave_arb_share_counter_next_value;
//cpu_0/data_master jtag_uart_0/avalon_jtag_slave arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//jtag_uart_0_avalon_jtag_slave_any_continuerequest at least one master continues requesting, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave = cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & ~((cpu_0_data_master_read & (~cpu_0_data_master_waitrequest)) | ((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write));
//jtag_uart_0_avalon_jtag_slave_writedata mux, which is an e_mux
assign jtag_uart_0_avalon_jtag_slave_writedata = cpu_0_data_master_writedata;
//master is always granted when requested
assign cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave = cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave;
//cpu_0/data_master saved-grant jtag_uart_0/avalon_jtag_slave, which is an e_assign
assign cpu_0_data_master_saved_grant_jtag_uart_0_avalon_jtag_slave = cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave;
//allow new arb cycle for jtag_uart_0/avalon_jtag_slave, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_allow_new_arb_cycle = 1;
//placeholder chosen master
assign jtag_uart_0_avalon_jtag_slave_grant_vector = 1;
//placeholder vector of master qualified-requests
assign jtag_uart_0_avalon_jtag_slave_master_qreq_vector = 1;
//jtag_uart_0_avalon_jtag_slave_reset_n assignment, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_reset_n = reset_n;
assign jtag_uart_0_avalon_jtag_slave_chipselect = cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave;
//jtag_uart_0_avalon_jtag_slave_firsttransfer first transaction, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_firsttransfer = jtag_uart_0_avalon_jtag_slave_begins_xfer ? jtag_uart_0_avalon_jtag_slave_unreg_firsttransfer : jtag_uart_0_avalon_jtag_slave_reg_firsttransfer;
//jtag_uart_0_avalon_jtag_slave_unreg_firsttransfer first transaction, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_unreg_firsttransfer = ~(jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable & jtag_uart_0_avalon_jtag_slave_any_continuerequest);
//jtag_uart_0_avalon_jtag_slave_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
jtag_uart_0_avalon_jtag_slave_reg_firsttransfer <= 1'b1;
else if (jtag_uart_0_avalon_jtag_slave_begins_xfer)
jtag_uart_0_avalon_jtag_slave_reg_firsttransfer <= jtag_uart_0_avalon_jtag_slave_unreg_firsttransfer;
end
//jtag_uart_0_avalon_jtag_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_beginbursttransfer_internal = jtag_uart_0_avalon_jtag_slave_begins_xfer;
//~jtag_uart_0_avalon_jtag_slave_read_n assignment, which is an e_mux
assign jtag_uart_0_avalon_jtag_slave_read_n = ~(cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave & cpu_0_data_master_read);
//~jtag_uart_0_avalon_jtag_slave_write_n assignment, which is an e_mux
assign jtag_uart_0_avalon_jtag_slave_write_n = ~(cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave & cpu_0_data_master_write);
assign shifted_address_to_jtag_uart_0_avalon_jtag_slave_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//jtag_uart_0_avalon_jtag_slave_address mux, which is an e_mux
assign jtag_uart_0_avalon_jtag_slave_address = shifted_address_to_jtag_uart_0_avalon_jtag_slave_from_cpu_0_data_master >> 2;
//d1_jtag_uart_0_avalon_jtag_slave_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_jtag_uart_0_avalon_jtag_slave_end_xfer <= 1;
else
d1_jtag_uart_0_avalon_jtag_slave_end_xfer <= jtag_uart_0_avalon_jtag_slave_end_xfer;
end
//jtag_uart_0_avalon_jtag_slave_waits_for_read in a cycle, which is an e_mux
assign jtag_uart_0_avalon_jtag_slave_waits_for_read = jtag_uart_0_avalon_jtag_slave_in_a_read_cycle & jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa;
//jtag_uart_0_avalon_jtag_slave_in_a_read_cycle assignment, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_in_a_read_cycle = cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = jtag_uart_0_avalon_jtag_slave_in_a_read_cycle;
//jtag_uart_0_avalon_jtag_slave_waits_for_write in a cycle, which is an e_mux
assign jtag_uart_0_avalon_jtag_slave_waits_for_write = jtag_uart_0_avalon_jtag_slave_in_a_write_cycle & jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa;
//jtag_uart_0_avalon_jtag_slave_in_a_write_cycle assignment, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_in_a_write_cycle = cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = jtag_uart_0_avalon_jtag_slave_in_a_write_cycle;
assign wait_for_jtag_uart_0_avalon_jtag_slave_counter = 0;
//assign jtag_uart_0_avalon_jtag_slave_irq_from_sa = jtag_uart_0_avalon_jtag_slave_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_irq_from_sa = jtag_uart_0_avalon_jtag_slave_irq;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//jtag_uart_0/avalon_jtag_slave enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_clock_0_in_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_byteenable,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
nios_system_clock_0_in_endofpacket,
nios_system_clock_0_in_readdata,
nios_system_clock_0_in_waitrequest,
reset_n,
// outputs:
cpu_0_data_master_granted_nios_system_clock_0_in,
cpu_0_data_master_qualified_request_nios_system_clock_0_in,
cpu_0_data_master_read_data_valid_nios_system_clock_0_in,
cpu_0_data_master_requests_nios_system_clock_0_in,
d1_nios_system_clock_0_in_end_xfer,
nios_system_clock_0_in_address,
nios_system_clock_0_in_byteenable,
nios_system_clock_0_in_endofpacket_from_sa,
nios_system_clock_0_in_nativeaddress,
nios_system_clock_0_in_read,
nios_system_clock_0_in_readdata_from_sa,
nios_system_clock_0_in_reset_n,
nios_system_clock_0_in_waitrequest_from_sa,
nios_system_clock_0_in_write,
nios_system_clock_0_in_writedata
)
;
output cpu_0_data_master_granted_nios_system_clock_0_in;
output cpu_0_data_master_qualified_request_nios_system_clock_0_in;
output cpu_0_data_master_read_data_valid_nios_system_clock_0_in;
output cpu_0_data_master_requests_nios_system_clock_0_in;
output d1_nios_system_clock_0_in_end_xfer;
output [ 2: 0] nios_system_clock_0_in_address;
output [ 3: 0] nios_system_clock_0_in_byteenable;
output nios_system_clock_0_in_endofpacket_from_sa;
output nios_system_clock_0_in_nativeaddress;
output nios_system_clock_0_in_read;
output [ 31: 0] nios_system_clock_0_in_readdata_from_sa;
output nios_system_clock_0_in_reset_n;
output nios_system_clock_0_in_waitrequest_from_sa;
output nios_system_clock_0_in_write;
output [ 31: 0] nios_system_clock_0_in_writedata;
input clk;
input [ 27: 0] cpu_0_data_master_address_to_slave;
input [ 3: 0] cpu_0_data_master_byteenable;
input cpu_0_data_master_read;
input cpu_0_data_master_waitrequest;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input nios_system_clock_0_in_endofpacket;
input [ 31: 0] nios_system_clock_0_in_readdata;
input nios_system_clock_0_in_waitrequest;
input reset_n;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_nios_system_clock_0_in;
wire cpu_0_data_master_qualified_request_nios_system_clock_0_in;
wire cpu_0_data_master_read_data_valid_nios_system_clock_0_in;
wire cpu_0_data_master_requests_nios_system_clock_0_in;
wire cpu_0_data_master_saved_grant_nios_system_clock_0_in;
reg d1_nios_system_clock_0_in_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_nios_system_clock_0_in;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 2: 0] nios_system_clock_0_in_address;
wire nios_system_clock_0_in_allgrants;
wire nios_system_clock_0_in_allow_new_arb_cycle;
wire nios_system_clock_0_in_any_bursting_master_saved_grant;
wire nios_system_clock_0_in_any_continuerequest;
wire nios_system_clock_0_in_arb_counter_enable;
reg [ 2: 0] nios_system_clock_0_in_arb_share_counter;
wire [ 2: 0] nios_system_clock_0_in_arb_share_counter_next_value;
wire [ 2: 0] nios_system_clock_0_in_arb_share_set_values;
wire nios_system_clock_0_in_beginbursttransfer_internal;
wire nios_system_clock_0_in_begins_xfer;
wire [ 3: 0] nios_system_clock_0_in_byteenable;
wire nios_system_clock_0_in_end_xfer;
wire nios_system_clock_0_in_endofpacket_from_sa;
wire nios_system_clock_0_in_firsttransfer;
wire nios_system_clock_0_in_grant_vector;
wire nios_system_clock_0_in_in_a_read_cycle;
wire nios_system_clock_0_in_in_a_write_cycle;
wire nios_system_clock_0_in_master_qreq_vector;
wire nios_system_clock_0_in_nativeaddress;
wire nios_system_clock_0_in_non_bursting_master_requests;
wire nios_system_clock_0_in_read;
wire [ 31: 0] nios_system_clock_0_in_readdata_from_sa;
reg nios_system_clock_0_in_reg_firsttransfer;
wire nios_system_clock_0_in_reset_n;
reg nios_system_clock_0_in_slavearbiterlockenable;
wire nios_system_clock_0_in_slavearbiterlockenable2;
wire nios_system_clock_0_in_unreg_firsttransfer;
wire nios_system_clock_0_in_waitrequest_from_sa;
wire nios_system_clock_0_in_waits_for_read;
wire nios_system_clock_0_in_waits_for_write;
wire nios_system_clock_0_in_write;
wire [ 31: 0] nios_system_clock_0_in_writedata;
wire wait_for_nios_system_clock_0_in_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~nios_system_clock_0_in_end_xfer;
end
assign nios_system_clock_0_in_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_nios_system_clock_0_in));
//assign nios_system_clock_0_in_readdata_from_sa = nios_system_clock_0_in_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign nios_system_clock_0_in_readdata_from_sa = nios_system_clock_0_in_readdata;
assign cpu_0_data_master_requests_nios_system_clock_0_in = ({cpu_0_data_master_address_to_slave[27 : 3] , 3'b0} == 28'h38) & (cpu_0_data_master_read | cpu_0_data_master_write);
//assign nios_system_clock_0_in_waitrequest_from_sa = nios_system_clock_0_in_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
assign nios_system_clock_0_in_waitrequest_from_sa = nios_system_clock_0_in_waitrequest;
//nios_system_clock_0_in_arb_share_counter set values, which is an e_mux
assign nios_system_clock_0_in_arb_share_set_values = 1;
//nios_system_clock_0_in_non_bursting_master_requests mux, which is an e_mux
assign nios_system_clock_0_in_non_bursting_master_requests = cpu_0_data_master_requests_nios_system_clock_0_in;
//nios_system_clock_0_in_any_bursting_master_saved_grant mux, which is an e_mux
assign nios_system_clock_0_in_any_bursting_master_saved_grant = 0;
//nios_system_clock_0_in_arb_share_counter_next_value assignment, which is an e_assign
assign nios_system_clock_0_in_arb_share_counter_next_value = nios_system_clock_0_in_firsttransfer ? (nios_system_clock_0_in_arb_share_set_values - 1) : |nios_system_clock_0_in_arb_share_counter ? (nios_system_clock_0_in_arb_share_counter - 1) : 0;
//nios_system_clock_0_in_allgrants all slave grants, which is an e_mux
assign nios_system_clock_0_in_allgrants = |nios_system_clock_0_in_grant_vector;
//nios_system_clock_0_in_end_xfer assignment, which is an e_assign
assign nios_system_clock_0_in_end_xfer = ~(nios_system_clock_0_in_waits_for_read | nios_system_clock_0_in_waits_for_write);
//end_xfer_arb_share_counter_term_nios_system_clock_0_in arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_nios_system_clock_0_in = nios_system_clock_0_in_end_xfer & (~nios_system_clock_0_in_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//nios_system_clock_0_in_arb_share_counter arbitration counter enable, which is an e_assign
assign nios_system_clock_0_in_arb_counter_enable = (end_xfer_arb_share_counter_term_nios_system_clock_0_in & nios_system_clock_0_in_allgrants) | (end_xfer_arb_share_counter_term_nios_system_clock_0_in & ~nios_system_clock_0_in_non_bursting_master_requests);
//nios_system_clock_0_in_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_0_in_arb_share_counter <= 0;
else if (nios_system_clock_0_in_arb_counter_enable)
nios_system_clock_0_in_arb_share_counter <= nios_system_clock_0_in_arb_share_counter_next_value;
end
//nios_system_clock_0_in_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_0_in_slavearbiterlockenable <= 0;
else if ((|nios_system_clock_0_in_master_qreq_vector & end_xfer_arb_share_counter_term_nios_system_clock_0_in) | (end_xfer_arb_share_counter_term_nios_system_clock_0_in & ~nios_system_clock_0_in_non_bursting_master_requests))
nios_system_clock_0_in_slavearbiterlockenable <= |nios_system_clock_0_in_arb_share_counter_next_value;
end
//cpu_0/data_master nios_system_clock_0/in arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = nios_system_clock_0_in_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//nios_system_clock_0_in_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign nios_system_clock_0_in_slavearbiterlockenable2 = |nios_system_clock_0_in_arb_share_counter_next_value;
//cpu_0/data_master nios_system_clock_0/in arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = nios_system_clock_0_in_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//nios_system_clock_0_in_any_continuerequest at least one master continues requesting, which is an e_assign
assign nios_system_clock_0_in_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_nios_system_clock_0_in = cpu_0_data_master_requests_nios_system_clock_0_in & ~((cpu_0_data_master_read & (~cpu_0_data_master_waitrequest)) | ((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write));
//nios_system_clock_0_in_writedata mux, which is an e_mux
assign nios_system_clock_0_in_writedata = cpu_0_data_master_writedata;
//assign nios_system_clock_0_in_endofpacket_from_sa = nios_system_clock_0_in_endofpacket so that symbol knows where to group signals which may go to master only, which is an e_assign
assign nios_system_clock_0_in_endofpacket_from_sa = nios_system_clock_0_in_endofpacket;
//master is always granted when requested
assign cpu_0_data_master_granted_nios_system_clock_0_in = cpu_0_data_master_qualified_request_nios_system_clock_0_in;
//cpu_0/data_master saved-grant nios_system_clock_0/in, which is an e_assign
assign cpu_0_data_master_saved_grant_nios_system_clock_0_in = cpu_0_data_master_requests_nios_system_clock_0_in;
//allow new arb cycle for nios_system_clock_0/in, which is an e_assign
assign nios_system_clock_0_in_allow_new_arb_cycle = 1;
//placeholder chosen master
assign nios_system_clock_0_in_grant_vector = 1;
//placeholder vector of master qualified-requests
assign nios_system_clock_0_in_master_qreq_vector = 1;
//nios_system_clock_0_in_reset_n assignment, which is an e_assign
assign nios_system_clock_0_in_reset_n = reset_n;
//nios_system_clock_0_in_firsttransfer first transaction, which is an e_assign
assign nios_system_clock_0_in_firsttransfer = nios_system_clock_0_in_begins_xfer ? nios_system_clock_0_in_unreg_firsttransfer : nios_system_clock_0_in_reg_firsttransfer;
//nios_system_clock_0_in_unreg_firsttransfer first transaction, which is an e_assign
assign nios_system_clock_0_in_unreg_firsttransfer = ~(nios_system_clock_0_in_slavearbiterlockenable & nios_system_clock_0_in_any_continuerequest);
//nios_system_clock_0_in_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_0_in_reg_firsttransfer <= 1'b1;
else if (nios_system_clock_0_in_begins_xfer)
nios_system_clock_0_in_reg_firsttransfer <= nios_system_clock_0_in_unreg_firsttransfer;
end
//nios_system_clock_0_in_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign nios_system_clock_0_in_beginbursttransfer_internal = nios_system_clock_0_in_begins_xfer;
//nios_system_clock_0_in_read assignment, which is an e_mux
assign nios_system_clock_0_in_read = cpu_0_data_master_granted_nios_system_clock_0_in & cpu_0_data_master_read;
//nios_system_clock_0_in_write assignment, which is an e_mux
assign nios_system_clock_0_in_write = cpu_0_data_master_granted_nios_system_clock_0_in & cpu_0_data_master_write;
//nios_system_clock_0_in_address mux, which is an e_mux
assign nios_system_clock_0_in_address = cpu_0_data_master_address_to_slave;
//slaveid nios_system_clock_0_in_nativeaddress nativeaddress mux, which is an e_mux
assign nios_system_clock_0_in_nativeaddress = cpu_0_data_master_address_to_slave >> 2;
//d1_nios_system_clock_0_in_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_nios_system_clock_0_in_end_xfer <= 1;
else
d1_nios_system_clock_0_in_end_xfer <= nios_system_clock_0_in_end_xfer;
end
//nios_system_clock_0_in_waits_for_read in a cycle, which is an e_mux
assign nios_system_clock_0_in_waits_for_read = nios_system_clock_0_in_in_a_read_cycle & nios_system_clock_0_in_waitrequest_from_sa;
//nios_system_clock_0_in_in_a_read_cycle assignment, which is an e_assign
assign nios_system_clock_0_in_in_a_read_cycle = cpu_0_data_master_granted_nios_system_clock_0_in & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = nios_system_clock_0_in_in_a_read_cycle;
//nios_system_clock_0_in_waits_for_write in a cycle, which is an e_mux
assign nios_system_clock_0_in_waits_for_write = nios_system_clock_0_in_in_a_write_cycle & nios_system_clock_0_in_waitrequest_from_sa;
//nios_system_clock_0_in_in_a_write_cycle assignment, which is an e_assign
assign nios_system_clock_0_in_in_a_write_cycle = cpu_0_data_master_granted_nios_system_clock_0_in & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = nios_system_clock_0_in_in_a_write_cycle;
assign wait_for_nios_system_clock_0_in_counter = 0;
//nios_system_clock_0_in_byteenable byte enable port mux, which is an e_mux
assign nios_system_clock_0_in_byteenable = (cpu_0_data_master_granted_nios_system_clock_0_in)? cpu_0_data_master_byteenable :
-1;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//nios_system_clock_0/in enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_clock_0_out_arbitrator (
// inputs:
clk,
d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer,
nios_system_clock_0_out_address,
nios_system_clock_0_out_byteenable,
nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave,
nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave,
nios_system_clock_0_out_read,
nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave,
nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave,
nios_system_clock_0_out_write,
nios_system_clock_0_out_writedata,
reset_n,
video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa,
// outputs:
nios_system_clock_0_out_address_to_slave,
nios_system_clock_0_out_readdata,
nios_system_clock_0_out_reset_n,
nios_system_clock_0_out_waitrequest
)
;
output [ 2: 0] nios_system_clock_0_out_address_to_slave;
output [ 31: 0] nios_system_clock_0_out_readdata;
output nios_system_clock_0_out_reset_n;
output nios_system_clock_0_out_waitrequest;
input clk;
input d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer;
input [ 2: 0] nios_system_clock_0_out_address;
input [ 3: 0] nios_system_clock_0_out_byteenable;
input nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave;
input nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave;
input nios_system_clock_0_out_read;
input nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave;
input nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave;
input nios_system_clock_0_out_write;
input [ 31: 0] nios_system_clock_0_out_writedata;
input reset_n;
input [ 31: 0] video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa;
reg active_and_waiting_last_time;
reg [ 2: 0] nios_system_clock_0_out_address_last_time;
wire [ 2: 0] nios_system_clock_0_out_address_to_slave;
reg [ 3: 0] nios_system_clock_0_out_byteenable_last_time;
reg nios_system_clock_0_out_read_last_time;
wire [ 31: 0] nios_system_clock_0_out_readdata;
wire nios_system_clock_0_out_reset_n;
wire nios_system_clock_0_out_run;
wire nios_system_clock_0_out_waitrequest;
reg nios_system_clock_0_out_write_last_time;
reg [ 31: 0] nios_system_clock_0_out_writedata_last_time;
wire r_2;
//r_2 master_run cascaded wait assignment, which is an e_assign
assign r_2 = 1 & (nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave | nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave | ~nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave) & ((~nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave | ~nios_system_clock_0_out_read | (nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave & nios_system_clock_0_out_read))) & ((~nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave | ~(nios_system_clock_0_out_read | nios_system_clock_0_out_write) | (1 & (nios_system_clock_0_out_read | nios_system_clock_0_out_write))));
//cascaded wait assignment, which is an e_assign
assign nios_system_clock_0_out_run = r_2;
//optimize select-logic by passing only those address bits which matter.
assign nios_system_clock_0_out_address_to_slave = nios_system_clock_0_out_address;
//nios_system_clock_0/out readdata mux, which is an e_mux
assign nios_system_clock_0_out_readdata = video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa;
//actual waitrequest port, which is an e_assign
assign nios_system_clock_0_out_waitrequest = ~nios_system_clock_0_out_run;
//nios_system_clock_0_out_reset_n assignment, which is an e_assign
assign nios_system_clock_0_out_reset_n = reset_n;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//nios_system_clock_0_out_address check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_0_out_address_last_time <= 0;
else
nios_system_clock_0_out_address_last_time <= nios_system_clock_0_out_address;
end
//nios_system_clock_0/out waited last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
active_and_waiting_last_time <= 0;
else
active_and_waiting_last_time <= nios_system_clock_0_out_waitrequest & (nios_system_clock_0_out_read | nios_system_clock_0_out_write);
end
//nios_system_clock_0_out_address matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (nios_system_clock_0_out_address != nios_system_clock_0_out_address_last_time))
begin
$write("%0d ns: nios_system_clock_0_out_address did not heed wait!!!", $time);
$stop;
end
end
//nios_system_clock_0_out_byteenable check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_0_out_byteenable_last_time <= 0;
else
nios_system_clock_0_out_byteenable_last_time <= nios_system_clock_0_out_byteenable;
end
//nios_system_clock_0_out_byteenable matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (nios_system_clock_0_out_byteenable != nios_system_clock_0_out_byteenable_last_time))
begin
$write("%0d ns: nios_system_clock_0_out_byteenable did not heed wait!!!", $time);
$stop;
end
end
//nios_system_clock_0_out_read check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_0_out_read_last_time <= 0;
else
nios_system_clock_0_out_read_last_time <= nios_system_clock_0_out_read;
end
//nios_system_clock_0_out_read matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (nios_system_clock_0_out_read != nios_system_clock_0_out_read_last_time))
begin
$write("%0d ns: nios_system_clock_0_out_read did not heed wait!!!", $time);
$stop;
end
end
//nios_system_clock_0_out_write check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_0_out_write_last_time <= 0;
else
nios_system_clock_0_out_write_last_time <= nios_system_clock_0_out_write;
end
//nios_system_clock_0_out_write matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (nios_system_clock_0_out_write != nios_system_clock_0_out_write_last_time))
begin
$write("%0d ns: nios_system_clock_0_out_write did not heed wait!!!", $time);
$stop;
end
end
//nios_system_clock_0_out_writedata check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_0_out_writedata_last_time <= 0;
else
nios_system_clock_0_out_writedata_last_time <= nios_system_clock_0_out_writedata;
end
//nios_system_clock_0_out_writedata matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (nios_system_clock_0_out_writedata != nios_system_clock_0_out_writedata_last_time) & nios_system_clock_0_out_write)
begin
$write("%0d ns: nios_system_clock_0_out_writedata did not heed wait!!!", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_clock_1_in_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_byteenable,
cpu_0_data_master_dbs_address,
cpu_0_data_master_dbs_write_8,
cpu_0_data_master_no_byte_enables_and_last_term,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
nios_system_clock_1_in_endofpacket,
nios_system_clock_1_in_readdata,
nios_system_clock_1_in_waitrequest,
reset_n,
// outputs:
cpu_0_data_master_byteenable_nios_system_clock_1_in,
cpu_0_data_master_granted_nios_system_clock_1_in,
cpu_0_data_master_qualified_request_nios_system_clock_1_in,
cpu_0_data_master_read_data_valid_nios_system_clock_1_in,
cpu_0_data_master_requests_nios_system_clock_1_in,
d1_nios_system_clock_1_in_end_xfer,
nios_system_clock_1_in_address,
nios_system_clock_1_in_endofpacket_from_sa,
nios_system_clock_1_in_nativeaddress,
nios_system_clock_1_in_read,
nios_system_clock_1_in_readdata_from_sa,
nios_system_clock_1_in_reset_n,
nios_system_clock_1_in_waitrequest_from_sa,
nios_system_clock_1_in_write,
nios_system_clock_1_in_writedata
)
;
output cpu_0_data_master_byteenable_nios_system_clock_1_in;
output cpu_0_data_master_granted_nios_system_clock_1_in;
output cpu_0_data_master_qualified_request_nios_system_clock_1_in;
output cpu_0_data_master_read_data_valid_nios_system_clock_1_in;
output cpu_0_data_master_requests_nios_system_clock_1_in;
output d1_nios_system_clock_1_in_end_xfer;
output [ 12: 0] nios_system_clock_1_in_address;
output nios_system_clock_1_in_endofpacket_from_sa;
output [ 12: 0] nios_system_clock_1_in_nativeaddress;
output nios_system_clock_1_in_read;
output [ 7: 0] nios_system_clock_1_in_readdata_from_sa;
output nios_system_clock_1_in_reset_n;
output nios_system_clock_1_in_waitrequest_from_sa;
output nios_system_clock_1_in_write;
output [ 7: 0] nios_system_clock_1_in_writedata;
input clk;
input [ 27: 0] cpu_0_data_master_address_to_slave;
input [ 3: 0] cpu_0_data_master_byteenable;
input [ 1: 0] cpu_0_data_master_dbs_address;
input [ 7: 0] cpu_0_data_master_dbs_write_8;
input cpu_0_data_master_no_byte_enables_and_last_term;
input cpu_0_data_master_read;
input cpu_0_data_master_waitrequest;
input cpu_0_data_master_write;
input nios_system_clock_1_in_endofpacket;
input [ 7: 0] nios_system_clock_1_in_readdata;
input nios_system_clock_1_in_waitrequest;
input reset_n;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_byteenable_nios_system_clock_1_in;
wire cpu_0_data_master_byteenable_nios_system_clock_1_in_segment_0;
wire cpu_0_data_master_byteenable_nios_system_clock_1_in_segment_1;
wire cpu_0_data_master_byteenable_nios_system_clock_1_in_segment_2;
wire cpu_0_data_master_byteenable_nios_system_clock_1_in_segment_3;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_nios_system_clock_1_in;
wire cpu_0_data_master_qualified_request_nios_system_clock_1_in;
wire cpu_0_data_master_read_data_valid_nios_system_clock_1_in;
wire cpu_0_data_master_requests_nios_system_clock_1_in;
wire cpu_0_data_master_saved_grant_nios_system_clock_1_in;
reg d1_nios_system_clock_1_in_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_nios_system_clock_1_in;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 12: 0] nios_system_clock_1_in_address;
wire nios_system_clock_1_in_allgrants;
wire nios_system_clock_1_in_allow_new_arb_cycle;
wire nios_system_clock_1_in_any_bursting_master_saved_grant;
wire nios_system_clock_1_in_any_continuerequest;
wire nios_system_clock_1_in_arb_counter_enable;
reg [ 2: 0] nios_system_clock_1_in_arb_share_counter;
wire [ 2: 0] nios_system_clock_1_in_arb_share_counter_next_value;
wire [ 2: 0] nios_system_clock_1_in_arb_share_set_values;
wire nios_system_clock_1_in_beginbursttransfer_internal;
wire nios_system_clock_1_in_begins_xfer;
wire nios_system_clock_1_in_end_xfer;
wire nios_system_clock_1_in_endofpacket_from_sa;
wire nios_system_clock_1_in_firsttransfer;
wire nios_system_clock_1_in_grant_vector;
wire nios_system_clock_1_in_in_a_read_cycle;
wire nios_system_clock_1_in_in_a_write_cycle;
wire nios_system_clock_1_in_master_qreq_vector;
wire [ 12: 0] nios_system_clock_1_in_nativeaddress;
wire nios_system_clock_1_in_non_bursting_master_requests;
wire nios_system_clock_1_in_pretend_byte_enable;
wire nios_system_clock_1_in_read;
wire [ 7: 0] nios_system_clock_1_in_readdata_from_sa;
reg nios_system_clock_1_in_reg_firsttransfer;
wire nios_system_clock_1_in_reset_n;
reg nios_system_clock_1_in_slavearbiterlockenable;
wire nios_system_clock_1_in_slavearbiterlockenable2;
wire nios_system_clock_1_in_unreg_firsttransfer;
wire nios_system_clock_1_in_waitrequest_from_sa;
wire nios_system_clock_1_in_waits_for_read;
wire nios_system_clock_1_in_waits_for_write;
wire nios_system_clock_1_in_write;
wire [ 7: 0] nios_system_clock_1_in_writedata;
wire wait_for_nios_system_clock_1_in_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~nios_system_clock_1_in_end_xfer;
end
assign nios_system_clock_1_in_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_nios_system_clock_1_in));
//assign nios_system_clock_1_in_readdata_from_sa = nios_system_clock_1_in_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign nios_system_clock_1_in_readdata_from_sa = nios_system_clock_1_in_readdata;
assign cpu_0_data_master_requests_nios_system_clock_1_in = ({cpu_0_data_master_address_to_slave[27 : 13] , 13'b0} == 28'h2000) & (cpu_0_data_master_read | cpu_0_data_master_write);
//assign nios_system_clock_1_in_waitrequest_from_sa = nios_system_clock_1_in_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
assign nios_system_clock_1_in_waitrequest_from_sa = nios_system_clock_1_in_waitrequest;
//nios_system_clock_1_in_arb_share_counter set values, which is an e_mux
assign nios_system_clock_1_in_arb_share_set_values = (cpu_0_data_master_granted_nios_system_clock_1_in)? 4 :
1;
//nios_system_clock_1_in_non_bursting_master_requests mux, which is an e_mux
assign nios_system_clock_1_in_non_bursting_master_requests = cpu_0_data_master_requests_nios_system_clock_1_in;
//nios_system_clock_1_in_any_bursting_master_saved_grant mux, which is an e_mux
assign nios_system_clock_1_in_any_bursting_master_saved_grant = 0;
//nios_system_clock_1_in_arb_share_counter_next_value assignment, which is an e_assign
assign nios_system_clock_1_in_arb_share_counter_next_value = nios_system_clock_1_in_firsttransfer ? (nios_system_clock_1_in_arb_share_set_values - 1) : |nios_system_clock_1_in_arb_share_counter ? (nios_system_clock_1_in_arb_share_counter - 1) : 0;
//nios_system_clock_1_in_allgrants all slave grants, which is an e_mux
assign nios_system_clock_1_in_allgrants = |nios_system_clock_1_in_grant_vector;
//nios_system_clock_1_in_end_xfer assignment, which is an e_assign
assign nios_system_clock_1_in_end_xfer = ~(nios_system_clock_1_in_waits_for_read | nios_system_clock_1_in_waits_for_write);
//end_xfer_arb_share_counter_term_nios_system_clock_1_in arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_nios_system_clock_1_in = nios_system_clock_1_in_end_xfer & (~nios_system_clock_1_in_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//nios_system_clock_1_in_arb_share_counter arbitration counter enable, which is an e_assign
assign nios_system_clock_1_in_arb_counter_enable = (end_xfer_arb_share_counter_term_nios_system_clock_1_in & nios_system_clock_1_in_allgrants) | (end_xfer_arb_share_counter_term_nios_system_clock_1_in & ~nios_system_clock_1_in_non_bursting_master_requests);
//nios_system_clock_1_in_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_1_in_arb_share_counter <= 0;
else if (nios_system_clock_1_in_arb_counter_enable)
nios_system_clock_1_in_arb_share_counter <= nios_system_clock_1_in_arb_share_counter_next_value;
end
//nios_system_clock_1_in_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_1_in_slavearbiterlockenable <= 0;
else if ((|nios_system_clock_1_in_master_qreq_vector & end_xfer_arb_share_counter_term_nios_system_clock_1_in) | (end_xfer_arb_share_counter_term_nios_system_clock_1_in & ~nios_system_clock_1_in_non_bursting_master_requests))
nios_system_clock_1_in_slavearbiterlockenable <= |nios_system_clock_1_in_arb_share_counter_next_value;
end
//cpu_0/data_master nios_system_clock_1/in arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = nios_system_clock_1_in_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//nios_system_clock_1_in_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign nios_system_clock_1_in_slavearbiterlockenable2 = |nios_system_clock_1_in_arb_share_counter_next_value;
//cpu_0/data_master nios_system_clock_1/in arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = nios_system_clock_1_in_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//nios_system_clock_1_in_any_continuerequest at least one master continues requesting, which is an e_assign
assign nios_system_clock_1_in_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_nios_system_clock_1_in = cpu_0_data_master_requests_nios_system_clock_1_in & ~((cpu_0_data_master_read & (~cpu_0_data_master_waitrequest)) | ((~cpu_0_data_master_waitrequest | cpu_0_data_master_no_byte_enables_and_last_term | !cpu_0_data_master_byteenable_nios_system_clock_1_in) & cpu_0_data_master_write));
//nios_system_clock_1_in_writedata mux, which is an e_mux
assign nios_system_clock_1_in_writedata = cpu_0_data_master_dbs_write_8;
//assign nios_system_clock_1_in_endofpacket_from_sa = nios_system_clock_1_in_endofpacket so that symbol knows where to group signals which may go to master only, which is an e_assign
assign nios_system_clock_1_in_endofpacket_from_sa = nios_system_clock_1_in_endofpacket;
//master is always granted when requested
assign cpu_0_data_master_granted_nios_system_clock_1_in = cpu_0_data_master_qualified_request_nios_system_clock_1_in;
//cpu_0/data_master saved-grant nios_system_clock_1/in, which is an e_assign
assign cpu_0_data_master_saved_grant_nios_system_clock_1_in = cpu_0_data_master_requests_nios_system_clock_1_in;
//allow new arb cycle for nios_system_clock_1/in, which is an e_assign
assign nios_system_clock_1_in_allow_new_arb_cycle = 1;
//placeholder chosen master
assign nios_system_clock_1_in_grant_vector = 1;
//placeholder vector of master qualified-requests
assign nios_system_clock_1_in_master_qreq_vector = 1;
//nios_system_clock_1_in_reset_n assignment, which is an e_assign
assign nios_system_clock_1_in_reset_n = reset_n;
//nios_system_clock_1_in_firsttransfer first transaction, which is an e_assign
assign nios_system_clock_1_in_firsttransfer = nios_system_clock_1_in_begins_xfer ? nios_system_clock_1_in_unreg_firsttransfer : nios_system_clock_1_in_reg_firsttransfer;
//nios_system_clock_1_in_unreg_firsttransfer first transaction, which is an e_assign
assign nios_system_clock_1_in_unreg_firsttransfer = ~(nios_system_clock_1_in_slavearbiterlockenable & nios_system_clock_1_in_any_continuerequest);
//nios_system_clock_1_in_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_1_in_reg_firsttransfer <= 1'b1;
else if (nios_system_clock_1_in_begins_xfer)
nios_system_clock_1_in_reg_firsttransfer <= nios_system_clock_1_in_unreg_firsttransfer;
end
//nios_system_clock_1_in_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign nios_system_clock_1_in_beginbursttransfer_internal = nios_system_clock_1_in_begins_xfer;
//nios_system_clock_1_in_read assignment, which is an e_mux
assign nios_system_clock_1_in_read = cpu_0_data_master_granted_nios_system_clock_1_in & cpu_0_data_master_read;
//nios_system_clock_1_in_write assignment, which is an e_mux
assign nios_system_clock_1_in_write = ((cpu_0_data_master_granted_nios_system_clock_1_in & cpu_0_data_master_write)) & nios_system_clock_1_in_pretend_byte_enable;
//nios_system_clock_1_in_address mux, which is an e_mux
assign nios_system_clock_1_in_address = {cpu_0_data_master_address_to_slave >> 2,
cpu_0_data_master_dbs_address[1 : 0]};
//slaveid nios_system_clock_1_in_nativeaddress nativeaddress mux, which is an e_mux
assign nios_system_clock_1_in_nativeaddress = cpu_0_data_master_address_to_slave >> 2;
//d1_nios_system_clock_1_in_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_nios_system_clock_1_in_end_xfer <= 1;
else
d1_nios_system_clock_1_in_end_xfer <= nios_system_clock_1_in_end_xfer;
end
//nios_system_clock_1_in_waits_for_read in a cycle, which is an e_mux
assign nios_system_clock_1_in_waits_for_read = nios_system_clock_1_in_in_a_read_cycle & nios_system_clock_1_in_waitrequest_from_sa;
//nios_system_clock_1_in_in_a_read_cycle assignment, which is an e_assign
assign nios_system_clock_1_in_in_a_read_cycle = cpu_0_data_master_granted_nios_system_clock_1_in & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = nios_system_clock_1_in_in_a_read_cycle;
//nios_system_clock_1_in_waits_for_write in a cycle, which is an e_mux
assign nios_system_clock_1_in_waits_for_write = nios_system_clock_1_in_in_a_write_cycle & nios_system_clock_1_in_waitrequest_from_sa;
//nios_system_clock_1_in_in_a_write_cycle assignment, which is an e_assign
assign nios_system_clock_1_in_in_a_write_cycle = cpu_0_data_master_granted_nios_system_clock_1_in & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = nios_system_clock_1_in_in_a_write_cycle;
assign wait_for_nios_system_clock_1_in_counter = 0;
//nios_system_clock_1_in_pretend_byte_enable byte enable port mux, which is an e_mux
assign nios_system_clock_1_in_pretend_byte_enable = (cpu_0_data_master_granted_nios_system_clock_1_in)? cpu_0_data_master_byteenable_nios_system_clock_1_in :
-1;
assign {cpu_0_data_master_byteenable_nios_system_clock_1_in_segment_3,
cpu_0_data_master_byteenable_nios_system_clock_1_in_segment_2,
cpu_0_data_master_byteenable_nios_system_clock_1_in_segment_1,
cpu_0_data_master_byteenable_nios_system_clock_1_in_segment_0} = cpu_0_data_master_byteenable;
assign cpu_0_data_master_byteenable_nios_system_clock_1_in = ((cpu_0_data_master_dbs_address[1 : 0] == 0))? cpu_0_data_master_byteenable_nios_system_clock_1_in_segment_0 :
((cpu_0_data_master_dbs_address[1 : 0] == 1))? cpu_0_data_master_byteenable_nios_system_clock_1_in_segment_1 :
((cpu_0_data_master_dbs_address[1 : 0] == 2))? cpu_0_data_master_byteenable_nios_system_clock_1_in_segment_2 :
cpu_0_data_master_byteenable_nios_system_clock_1_in_segment_3;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//nios_system_clock_1/in enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_clock_1_out_arbitrator (
// inputs:
clk,
d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer,
nios_system_clock_1_out_address,
nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave,
nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave,
nios_system_clock_1_out_read,
nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave,
nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave,
nios_system_clock_1_out_write,
nios_system_clock_1_out_writedata,
reset_n,
video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa,
video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa,
// outputs:
nios_system_clock_1_out_address_to_slave,
nios_system_clock_1_out_readdata,
nios_system_clock_1_out_reset_n,
nios_system_clock_1_out_waitrequest
)
;
output [ 12: 0] nios_system_clock_1_out_address_to_slave;
output [ 7: 0] nios_system_clock_1_out_readdata;
output nios_system_clock_1_out_reset_n;
output nios_system_clock_1_out_waitrequest;
input clk;
input d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer;
input [ 12: 0] nios_system_clock_1_out_address;
input nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
input nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
input nios_system_clock_1_out_read;
input nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
input nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
input nios_system_clock_1_out_write;
input [ 7: 0] nios_system_clock_1_out_writedata;
input reset_n;
input [ 7: 0] video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa;
input video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa;
reg active_and_waiting_last_time;
reg [ 12: 0] nios_system_clock_1_out_address_last_time;
wire [ 12: 0] nios_system_clock_1_out_address_to_slave;
reg nios_system_clock_1_out_read_last_time;
wire [ 7: 0] nios_system_clock_1_out_readdata;
wire nios_system_clock_1_out_reset_n;
wire nios_system_clock_1_out_run;
wire nios_system_clock_1_out_waitrequest;
reg nios_system_clock_1_out_write_last_time;
reg [ 7: 0] nios_system_clock_1_out_writedata_last_time;
wire r_2;
//r_2 master_run cascaded wait assignment, which is an e_assign
assign r_2 = 1 & (nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave | nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave | ~nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave) & ((~nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave | ~nios_system_clock_1_out_read | (nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave & nios_system_clock_1_out_read))) & ((~nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave | ~(nios_system_clock_1_out_read | nios_system_clock_1_out_write) | (1 & ~video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa & (nios_system_clock_1_out_read | nios_system_clock_1_out_write))));
//cascaded wait assignment, which is an e_assign
assign nios_system_clock_1_out_run = r_2;
//optimize select-logic by passing only those address bits which matter.
assign nios_system_clock_1_out_address_to_slave = nios_system_clock_1_out_address;
//nios_system_clock_1/out readdata mux, which is an e_mux
assign nios_system_clock_1_out_readdata = video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa;
//actual waitrequest port, which is an e_assign
assign nios_system_clock_1_out_waitrequest = ~nios_system_clock_1_out_run;
//nios_system_clock_1_out_reset_n assignment, which is an e_assign
assign nios_system_clock_1_out_reset_n = reset_n;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//nios_system_clock_1_out_address check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_1_out_address_last_time <= 0;
else
nios_system_clock_1_out_address_last_time <= nios_system_clock_1_out_address;
end
//nios_system_clock_1/out waited last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
active_and_waiting_last_time <= 0;
else
active_and_waiting_last_time <= nios_system_clock_1_out_waitrequest & (nios_system_clock_1_out_read | nios_system_clock_1_out_write);
end
//nios_system_clock_1_out_address matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (nios_system_clock_1_out_address != nios_system_clock_1_out_address_last_time))
begin
$write("%0d ns: nios_system_clock_1_out_address did not heed wait!!!", $time);
$stop;
end
end
//nios_system_clock_1_out_read check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_1_out_read_last_time <= 0;
else
nios_system_clock_1_out_read_last_time <= nios_system_clock_1_out_read;
end
//nios_system_clock_1_out_read matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (nios_system_clock_1_out_read != nios_system_clock_1_out_read_last_time))
begin
$write("%0d ns: nios_system_clock_1_out_read did not heed wait!!!", $time);
$stop;
end
end
//nios_system_clock_1_out_write check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_1_out_write_last_time <= 0;
else
nios_system_clock_1_out_write_last_time <= nios_system_clock_1_out_write;
end
//nios_system_clock_1_out_write matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (nios_system_clock_1_out_write != nios_system_clock_1_out_write_last_time))
begin
$write("%0d ns: nios_system_clock_1_out_write did not heed wait!!!", $time);
$stop;
end
end
//nios_system_clock_1_out_writedata check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_1_out_writedata_last_time <= 0;
else
nios_system_clock_1_out_writedata_last_time <= nios_system_clock_1_out_writedata;
end
//nios_system_clock_1_out_writedata matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (nios_system_clock_1_out_writedata != nios_system_clock_1_out_writedata_last_time) & nios_system_clock_1_out_write)
begin
$write("%0d ns: nios_system_clock_1_out_writedata did not heed wait!!!", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module onchip_memory2_0_s1_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_byteenable,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
cpu_0_instruction_master_address_to_slave,
cpu_0_instruction_master_read,
onchip_memory2_0_s1_readdata,
reset_n,
// outputs:
cpu_0_data_master_granted_onchip_memory2_0_s1,
cpu_0_data_master_qualified_request_onchip_memory2_0_s1,
cpu_0_data_master_read_data_valid_onchip_memory2_0_s1,
cpu_0_data_master_requests_onchip_memory2_0_s1,
cpu_0_instruction_master_granted_onchip_memory2_0_s1,
cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1,
cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1,
cpu_0_instruction_master_requests_onchip_memory2_0_s1,
d1_onchip_memory2_0_s1_end_xfer,
onchip_memory2_0_s1_address,
onchip_memory2_0_s1_byteenable,
onchip_memory2_0_s1_chipselect,
onchip_memory2_0_s1_clken,
onchip_memory2_0_s1_readdata_from_sa,
onchip_memory2_0_s1_reset,
onchip_memory2_0_s1_write,
onchip_memory2_0_s1_writedata,
registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1
)
;
output cpu_0_data_master_granted_onchip_memory2_0_s1;
output cpu_0_data_master_qualified_request_onchip_memory2_0_s1;
output cpu_0_data_master_read_data_valid_onchip_memory2_0_s1;
output cpu_0_data_master_requests_onchip_memory2_0_s1;
output cpu_0_instruction_master_granted_onchip_memory2_0_s1;
output cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1;
output cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1;
output cpu_0_instruction_master_requests_onchip_memory2_0_s1;
output d1_onchip_memory2_0_s1_end_xfer;
output [ 11: 0] onchip_memory2_0_s1_address;
output [ 3: 0] onchip_memory2_0_s1_byteenable;
output onchip_memory2_0_s1_chipselect;
output onchip_memory2_0_s1_clken;
output [ 31: 0] onchip_memory2_0_s1_readdata_from_sa;
output onchip_memory2_0_s1_reset;
output onchip_memory2_0_s1_write;
output [ 31: 0] onchip_memory2_0_s1_writedata;
output registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1;
input clk;
input [ 27: 0] cpu_0_data_master_address_to_slave;
input [ 3: 0] cpu_0_data_master_byteenable;
input cpu_0_data_master_read;
input cpu_0_data_master_waitrequest;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input [ 27: 0] cpu_0_instruction_master_address_to_slave;
input cpu_0_instruction_master_read;
input [ 31: 0] onchip_memory2_0_s1_readdata;
input reset_n;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_onchip_memory2_0_s1;
wire cpu_0_data_master_qualified_request_onchip_memory2_0_s1;
wire cpu_0_data_master_read_data_valid_onchip_memory2_0_s1;
reg cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register;
wire cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register_in;
wire cpu_0_data_master_requests_onchip_memory2_0_s1;
wire cpu_0_data_master_saved_grant_onchip_memory2_0_s1;
wire cpu_0_instruction_master_arbiterlock;
wire cpu_0_instruction_master_arbiterlock2;
wire cpu_0_instruction_master_continuerequest;
wire cpu_0_instruction_master_granted_onchip_memory2_0_s1;
wire cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1;
wire cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1;
reg cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register;
wire cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register_in;
wire cpu_0_instruction_master_requests_onchip_memory2_0_s1;
wire cpu_0_instruction_master_saved_grant_onchip_memory2_0_s1;
reg d1_onchip_memory2_0_s1_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_onchip_memory2_0_s1;
wire in_a_read_cycle;
wire in_a_write_cycle;
reg last_cycle_cpu_0_data_master_granted_slave_onchip_memory2_0_s1;
reg last_cycle_cpu_0_instruction_master_granted_slave_onchip_memory2_0_s1;
wire [ 11: 0] onchip_memory2_0_s1_address;
wire onchip_memory2_0_s1_allgrants;
wire onchip_memory2_0_s1_allow_new_arb_cycle;
wire onchip_memory2_0_s1_any_bursting_master_saved_grant;
wire onchip_memory2_0_s1_any_continuerequest;
reg [ 1: 0] onchip_memory2_0_s1_arb_addend;
wire onchip_memory2_0_s1_arb_counter_enable;
reg [ 2: 0] onchip_memory2_0_s1_arb_share_counter;
wire [ 2: 0] onchip_memory2_0_s1_arb_share_counter_next_value;
wire [ 2: 0] onchip_memory2_0_s1_arb_share_set_values;
wire [ 1: 0] onchip_memory2_0_s1_arb_winner;
wire onchip_memory2_0_s1_arbitration_holdoff_internal;
wire onchip_memory2_0_s1_beginbursttransfer_internal;
wire onchip_memory2_0_s1_begins_xfer;
wire [ 3: 0] onchip_memory2_0_s1_byteenable;
wire onchip_memory2_0_s1_chipselect;
wire [ 3: 0] onchip_memory2_0_s1_chosen_master_double_vector;
wire [ 1: 0] onchip_memory2_0_s1_chosen_master_rot_left;
wire onchip_memory2_0_s1_clken;
wire onchip_memory2_0_s1_end_xfer;
wire onchip_memory2_0_s1_firsttransfer;
wire [ 1: 0] onchip_memory2_0_s1_grant_vector;
wire onchip_memory2_0_s1_in_a_read_cycle;
wire onchip_memory2_0_s1_in_a_write_cycle;
wire [ 1: 0] onchip_memory2_0_s1_master_qreq_vector;
wire onchip_memory2_0_s1_non_bursting_master_requests;
wire [ 31: 0] onchip_memory2_0_s1_readdata_from_sa;
reg onchip_memory2_0_s1_reg_firsttransfer;
wire onchip_memory2_0_s1_reset;
reg [ 1: 0] onchip_memory2_0_s1_saved_chosen_master_vector;
reg onchip_memory2_0_s1_slavearbiterlockenable;
wire onchip_memory2_0_s1_slavearbiterlockenable2;
wire onchip_memory2_0_s1_unreg_firsttransfer;
wire onchip_memory2_0_s1_waits_for_read;
wire onchip_memory2_0_s1_waits_for_write;
wire onchip_memory2_0_s1_write;
wire [ 31: 0] onchip_memory2_0_s1_writedata;
wire p1_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register;
wire p1_cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register;
wire registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1;
wire [ 27: 0] shifted_address_to_onchip_memory2_0_s1_from_cpu_0_data_master;
wire [ 27: 0] shifted_address_to_onchip_memory2_0_s1_from_cpu_0_instruction_master;
wire wait_for_onchip_memory2_0_s1_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~onchip_memory2_0_s1_end_xfer;
end
assign onchip_memory2_0_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_onchip_memory2_0_s1 | cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1));
//assign onchip_memory2_0_s1_readdata_from_sa = onchip_memory2_0_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign onchip_memory2_0_s1_readdata_from_sa = onchip_memory2_0_s1_readdata;
assign cpu_0_data_master_requests_onchip_memory2_0_s1 = ({cpu_0_data_master_address_to_slave[27 : 14] , 14'b0} == 28'h10000) & (cpu_0_data_master_read | cpu_0_data_master_write);
//registered rdv signal_name registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1 assignment, which is an e_assign
assign registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1 = cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register_in;
//onchip_memory2_0_s1_arb_share_counter set values, which is an e_mux
assign onchip_memory2_0_s1_arb_share_set_values = 1;
//onchip_memory2_0_s1_non_bursting_master_requests mux, which is an e_mux
assign onchip_memory2_0_s1_non_bursting_master_requests = cpu_0_data_master_requests_onchip_memory2_0_s1 |
cpu_0_instruction_master_requests_onchip_memory2_0_s1 |
cpu_0_data_master_requests_onchip_memory2_0_s1 |
cpu_0_instruction_master_requests_onchip_memory2_0_s1;
//onchip_memory2_0_s1_any_bursting_master_saved_grant mux, which is an e_mux
assign onchip_memory2_0_s1_any_bursting_master_saved_grant = 0;
//onchip_memory2_0_s1_arb_share_counter_next_value assignment, which is an e_assign
assign onchip_memory2_0_s1_arb_share_counter_next_value = onchip_memory2_0_s1_firsttransfer ? (onchip_memory2_0_s1_arb_share_set_values - 1) : |onchip_memory2_0_s1_arb_share_counter ? (onchip_memory2_0_s1_arb_share_counter - 1) : 0;
//onchip_memory2_0_s1_allgrants all slave grants, which is an e_mux
assign onchip_memory2_0_s1_allgrants = (|onchip_memory2_0_s1_grant_vector) |
(|onchip_memory2_0_s1_grant_vector) |
(|onchip_memory2_0_s1_grant_vector) |
(|onchip_memory2_0_s1_grant_vector);
//onchip_memory2_0_s1_end_xfer assignment, which is an e_assign
assign onchip_memory2_0_s1_end_xfer = ~(onchip_memory2_0_s1_waits_for_read | onchip_memory2_0_s1_waits_for_write);
//end_xfer_arb_share_counter_term_onchip_memory2_0_s1 arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_onchip_memory2_0_s1 = onchip_memory2_0_s1_end_xfer & (~onchip_memory2_0_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//onchip_memory2_0_s1_arb_share_counter arbitration counter enable, which is an e_assign
assign onchip_memory2_0_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_onchip_memory2_0_s1 & onchip_memory2_0_s1_allgrants) | (end_xfer_arb_share_counter_term_onchip_memory2_0_s1 & ~onchip_memory2_0_s1_non_bursting_master_requests);
//onchip_memory2_0_s1_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
onchip_memory2_0_s1_arb_share_counter <= 0;
else if (onchip_memory2_0_s1_arb_counter_enable)
onchip_memory2_0_s1_arb_share_counter <= onchip_memory2_0_s1_arb_share_counter_next_value;
end
//onchip_memory2_0_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
onchip_memory2_0_s1_slavearbiterlockenable <= 0;
else if ((|onchip_memory2_0_s1_master_qreq_vector & end_xfer_arb_share_counter_term_onchip_memory2_0_s1) | (end_xfer_arb_share_counter_term_onchip_memory2_0_s1 & ~onchip_memory2_0_s1_non_bursting_master_requests))
onchip_memory2_0_s1_slavearbiterlockenable <= |onchip_memory2_0_s1_arb_share_counter_next_value;
end
//cpu_0/data_master onchip_memory2_0/s1 arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = onchip_memory2_0_s1_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//onchip_memory2_0_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign onchip_memory2_0_s1_slavearbiterlockenable2 = |onchip_memory2_0_s1_arb_share_counter_next_value;
//cpu_0/data_master onchip_memory2_0/s1 arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = onchip_memory2_0_s1_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//cpu_0/instruction_master onchip_memory2_0/s1 arbiterlock, which is an e_assign
assign cpu_0_instruction_master_arbiterlock = onchip_memory2_0_s1_slavearbiterlockenable & cpu_0_instruction_master_continuerequest;
//cpu_0/instruction_master onchip_memory2_0/s1 arbiterlock2, which is an e_assign
assign cpu_0_instruction_master_arbiterlock2 = onchip_memory2_0_s1_slavearbiterlockenable2 & cpu_0_instruction_master_continuerequest;
//cpu_0/instruction_master granted onchip_memory2_0/s1 last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_0_instruction_master_granted_slave_onchip_memory2_0_s1 <= 0;
else
last_cycle_cpu_0_instruction_master_granted_slave_onchip_memory2_0_s1 <= cpu_0_instruction_master_saved_grant_onchip_memory2_0_s1 ? 1 : (onchip_memory2_0_s1_arbitration_holdoff_internal | ~cpu_0_instruction_master_requests_onchip_memory2_0_s1) ? 0 : last_cycle_cpu_0_instruction_master_granted_slave_onchip_memory2_0_s1;
end
//cpu_0_instruction_master_continuerequest continued request, which is an e_mux
assign cpu_0_instruction_master_continuerequest = last_cycle_cpu_0_instruction_master_granted_slave_onchip_memory2_0_s1 & cpu_0_instruction_master_requests_onchip_memory2_0_s1;
//onchip_memory2_0_s1_any_continuerequest at least one master continues requesting, which is an e_mux
assign onchip_memory2_0_s1_any_continuerequest = cpu_0_instruction_master_continuerequest |
cpu_0_data_master_continuerequest;
assign cpu_0_data_master_qualified_request_onchip_memory2_0_s1 = cpu_0_data_master_requests_onchip_memory2_0_s1 & ~((cpu_0_data_master_read & ((|cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register))) | ((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write) | cpu_0_instruction_master_arbiterlock);
//cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register_in mux for readlatency shift register, which is an e_mux
assign cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register_in = cpu_0_data_master_granted_onchip_memory2_0_s1 & cpu_0_data_master_read & ~onchip_memory2_0_s1_waits_for_read & ~(|cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register);
//shift register p1 cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register in if flush, otherwise shift left, which is an e_mux
assign p1_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register = {cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register, cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register_in};
//cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register <= 0;
else
cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register <= p1_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register;
end
//local readdatavalid cpu_0_data_master_read_data_valid_onchip_memory2_0_s1, which is an e_mux
assign cpu_0_data_master_read_data_valid_onchip_memory2_0_s1 = cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register;
//onchip_memory2_0_s1_writedata mux, which is an e_mux
assign onchip_memory2_0_s1_writedata = cpu_0_data_master_writedata;
//mux onchip_memory2_0_s1_clken, which is an e_mux
assign onchip_memory2_0_s1_clken = 1'b1;
assign cpu_0_instruction_master_requests_onchip_memory2_0_s1 = (({cpu_0_instruction_master_address_to_slave[27 : 14] , 14'b0} == 28'h10000) & (cpu_0_instruction_master_read)) & cpu_0_instruction_master_read;
//cpu_0/data_master granted onchip_memory2_0/s1 last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_0_data_master_granted_slave_onchip_memory2_0_s1 <= 0;
else
last_cycle_cpu_0_data_master_granted_slave_onchip_memory2_0_s1 <= cpu_0_data_master_saved_grant_onchip_memory2_0_s1 ? 1 : (onchip_memory2_0_s1_arbitration_holdoff_internal | ~cpu_0_data_master_requests_onchip_memory2_0_s1) ? 0 : last_cycle_cpu_0_data_master_granted_slave_onchip_memory2_0_s1;
end
//cpu_0_data_master_continuerequest continued request, which is an e_mux
assign cpu_0_data_master_continuerequest = last_cycle_cpu_0_data_master_granted_slave_onchip_memory2_0_s1 & cpu_0_data_master_requests_onchip_memory2_0_s1;
assign cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1 = cpu_0_instruction_master_requests_onchip_memory2_0_s1 & ~((cpu_0_instruction_master_read & ((|cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register))) | cpu_0_data_master_arbiterlock);
//cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register_in mux for readlatency shift register, which is an e_mux
assign cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register_in = cpu_0_instruction_master_granted_onchip_memory2_0_s1 & cpu_0_instruction_master_read & ~onchip_memory2_0_s1_waits_for_read & ~(|cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register);
//shift register p1 cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register in if flush, otherwise shift left, which is an e_mux
assign p1_cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register = {cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register, cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register_in};
//cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register <= 0;
else
cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register <= p1_cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register;
end
//local readdatavalid cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1, which is an e_mux
assign cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1 = cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register;
//allow new arb cycle for onchip_memory2_0/s1, which is an e_assign
assign onchip_memory2_0_s1_allow_new_arb_cycle = ~cpu_0_data_master_arbiterlock & ~cpu_0_instruction_master_arbiterlock;
//cpu_0/instruction_master assignment into master qualified-requests vector for onchip_memory2_0/s1, which is an e_assign
assign onchip_memory2_0_s1_master_qreq_vector[0] = cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1;
//cpu_0/instruction_master grant onchip_memory2_0/s1, which is an e_assign
assign cpu_0_instruction_master_granted_onchip_memory2_0_s1 = onchip_memory2_0_s1_grant_vector[0];
//cpu_0/instruction_master saved-grant onchip_memory2_0/s1, which is an e_assign
assign cpu_0_instruction_master_saved_grant_onchip_memory2_0_s1 = onchip_memory2_0_s1_arb_winner[0] && cpu_0_instruction_master_requests_onchip_memory2_0_s1;
//cpu_0/data_master assignment into master qualified-requests vector for onchip_memory2_0/s1, which is an e_assign
assign onchip_memory2_0_s1_master_qreq_vector[1] = cpu_0_data_master_qualified_request_onchip_memory2_0_s1;
//cpu_0/data_master grant onchip_memory2_0/s1, which is an e_assign
assign cpu_0_data_master_granted_onchip_memory2_0_s1 = onchip_memory2_0_s1_grant_vector[1];
//cpu_0/data_master saved-grant onchip_memory2_0/s1, which is an e_assign
assign cpu_0_data_master_saved_grant_onchip_memory2_0_s1 = onchip_memory2_0_s1_arb_winner[1] && cpu_0_data_master_requests_onchip_memory2_0_s1;
//onchip_memory2_0/s1 chosen-master double-vector, which is an e_assign
assign onchip_memory2_0_s1_chosen_master_double_vector = {onchip_memory2_0_s1_master_qreq_vector, onchip_memory2_0_s1_master_qreq_vector} & ({~onchip_memory2_0_s1_master_qreq_vector, ~onchip_memory2_0_s1_master_qreq_vector} + onchip_memory2_0_s1_arb_addend);
//stable onehot encoding of arb winner
assign onchip_memory2_0_s1_arb_winner = (onchip_memory2_0_s1_allow_new_arb_cycle & | onchip_memory2_0_s1_grant_vector) ? onchip_memory2_0_s1_grant_vector : onchip_memory2_0_s1_saved_chosen_master_vector;
//saved onchip_memory2_0_s1_grant_vector, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
onchip_memory2_0_s1_saved_chosen_master_vector <= 0;
else if (onchip_memory2_0_s1_allow_new_arb_cycle)
onchip_memory2_0_s1_saved_chosen_master_vector <= |onchip_memory2_0_s1_grant_vector ? onchip_memory2_0_s1_grant_vector : onchip_memory2_0_s1_saved_chosen_master_vector;
end
//onehot encoding of chosen master
assign onchip_memory2_0_s1_grant_vector = {(onchip_memory2_0_s1_chosen_master_double_vector[1] | onchip_memory2_0_s1_chosen_master_double_vector[3]),
(onchip_memory2_0_s1_chosen_master_double_vector[0] | onchip_memory2_0_s1_chosen_master_double_vector[2])};
//onchip_memory2_0/s1 chosen master rotated left, which is an e_assign
assign onchip_memory2_0_s1_chosen_master_rot_left = (onchip_memory2_0_s1_arb_winner << 1) ? (onchip_memory2_0_s1_arb_winner << 1) : 1;
//onchip_memory2_0/s1's addend for next-master-grant
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
onchip_memory2_0_s1_arb_addend <= 1;
else if (|onchip_memory2_0_s1_grant_vector)
onchip_memory2_0_s1_arb_addend <= onchip_memory2_0_s1_end_xfer? onchip_memory2_0_s1_chosen_master_rot_left : onchip_memory2_0_s1_grant_vector;
end
//~onchip_memory2_0_s1_reset assignment, which is an e_assign
assign onchip_memory2_0_s1_reset = ~reset_n;
assign onchip_memory2_0_s1_chipselect = cpu_0_data_master_granted_onchip_memory2_0_s1 | cpu_0_instruction_master_granted_onchip_memory2_0_s1;
//onchip_memory2_0_s1_firsttransfer first transaction, which is an e_assign
assign onchip_memory2_0_s1_firsttransfer = onchip_memory2_0_s1_begins_xfer ? onchip_memory2_0_s1_unreg_firsttransfer : onchip_memory2_0_s1_reg_firsttransfer;
//onchip_memory2_0_s1_unreg_firsttransfer first transaction, which is an e_assign
assign onchip_memory2_0_s1_unreg_firsttransfer = ~(onchip_memory2_0_s1_slavearbiterlockenable & onchip_memory2_0_s1_any_continuerequest);
//onchip_memory2_0_s1_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
onchip_memory2_0_s1_reg_firsttransfer <= 1'b1;
else if (onchip_memory2_0_s1_begins_xfer)
onchip_memory2_0_s1_reg_firsttransfer <= onchip_memory2_0_s1_unreg_firsttransfer;
end
//onchip_memory2_0_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign onchip_memory2_0_s1_beginbursttransfer_internal = onchip_memory2_0_s1_begins_xfer;
//onchip_memory2_0_s1_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
assign onchip_memory2_0_s1_arbitration_holdoff_internal = onchip_memory2_0_s1_begins_xfer & onchip_memory2_0_s1_firsttransfer;
//onchip_memory2_0_s1_write assignment, which is an e_mux
assign onchip_memory2_0_s1_write = cpu_0_data_master_granted_onchip_memory2_0_s1 & cpu_0_data_master_write;
assign shifted_address_to_onchip_memory2_0_s1_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//onchip_memory2_0_s1_address mux, which is an e_mux
assign onchip_memory2_0_s1_address = (cpu_0_data_master_granted_onchip_memory2_0_s1)? (shifted_address_to_onchip_memory2_0_s1_from_cpu_0_data_master >> 2) :
(shifted_address_to_onchip_memory2_0_s1_from_cpu_0_instruction_master >> 2);
assign shifted_address_to_onchip_memory2_0_s1_from_cpu_0_instruction_master = cpu_0_instruction_master_address_to_slave;
//d1_onchip_memory2_0_s1_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_onchip_memory2_0_s1_end_xfer <= 1;
else
d1_onchip_memory2_0_s1_end_xfer <= onchip_memory2_0_s1_end_xfer;
end
//onchip_memory2_0_s1_waits_for_read in a cycle, which is an e_mux
assign onchip_memory2_0_s1_waits_for_read = onchip_memory2_0_s1_in_a_read_cycle & 0;
//onchip_memory2_0_s1_in_a_read_cycle assignment, which is an e_assign
assign onchip_memory2_0_s1_in_a_read_cycle = (cpu_0_data_master_granted_onchip_memory2_0_s1 & cpu_0_data_master_read) | (cpu_0_instruction_master_granted_onchip_memory2_0_s1 & cpu_0_instruction_master_read);
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = onchip_memory2_0_s1_in_a_read_cycle;
//onchip_memory2_0_s1_waits_for_write in a cycle, which is an e_mux
assign onchip_memory2_0_s1_waits_for_write = onchip_memory2_0_s1_in_a_write_cycle & 0;
//onchip_memory2_0_s1_in_a_write_cycle assignment, which is an e_assign
assign onchip_memory2_0_s1_in_a_write_cycle = cpu_0_data_master_granted_onchip_memory2_0_s1 & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = onchip_memory2_0_s1_in_a_write_cycle;
assign wait_for_onchip_memory2_0_s1_counter = 0;
//onchip_memory2_0_s1_byteenable byte enable port mux, which is an e_mux
assign onchip_memory2_0_s1_byteenable = (cpu_0_data_master_granted_onchip_memory2_0_s1)? cpu_0_data_master_byteenable :
-1;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//onchip_memory2_0/s1 enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_0_data_master_granted_onchip_memory2_0_s1 + cpu_0_instruction_master_granted_onchip_memory2_0_s1 > 1)
begin
$write("%0d ns: > 1 of grant signals are active simultaneously", $time);
$stop;
end
end
//saved_grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_0_data_master_saved_grant_onchip_memory2_0_s1 + cpu_0_instruction_master_saved_grant_onchip_memory2_0_s1 > 1)
begin
$write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module output1_s1_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
output1_s1_readdata,
reset_n,
// outputs:
cpu_0_data_master_granted_output1_s1,
cpu_0_data_master_qualified_request_output1_s1,
cpu_0_data_master_read_data_valid_output1_s1,
cpu_0_data_master_requests_output1_s1,
d1_output1_s1_end_xfer,
output1_s1_address,
output1_s1_chipselect,
output1_s1_readdata_from_sa,
output1_s1_reset_n,
output1_s1_write_n,
output1_s1_writedata
)
;
output cpu_0_data_master_granted_output1_s1;
output cpu_0_data_master_qualified_request_output1_s1;
output cpu_0_data_master_read_data_valid_output1_s1;
output cpu_0_data_master_requests_output1_s1;
output d1_output1_s1_end_xfer;
output [ 1: 0] output1_s1_address;
output output1_s1_chipselect;
output [ 31: 0] output1_s1_readdata_from_sa;
output output1_s1_reset_n;
output output1_s1_write_n;
output [ 31: 0] output1_s1_writedata;
input clk;
input [ 27: 0] cpu_0_data_master_address_to_slave;
input cpu_0_data_master_read;
input cpu_0_data_master_waitrequest;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input [ 31: 0] output1_s1_readdata;
input reset_n;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_output1_s1;
wire cpu_0_data_master_qualified_request_output1_s1;
wire cpu_0_data_master_read_data_valid_output1_s1;
wire cpu_0_data_master_requests_output1_s1;
wire cpu_0_data_master_saved_grant_output1_s1;
reg d1_output1_s1_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_output1_s1;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 1: 0] output1_s1_address;
wire output1_s1_allgrants;
wire output1_s1_allow_new_arb_cycle;
wire output1_s1_any_bursting_master_saved_grant;
wire output1_s1_any_continuerequest;
wire output1_s1_arb_counter_enable;
reg [ 2: 0] output1_s1_arb_share_counter;
wire [ 2: 0] output1_s1_arb_share_counter_next_value;
wire [ 2: 0] output1_s1_arb_share_set_values;
wire output1_s1_beginbursttransfer_internal;
wire output1_s1_begins_xfer;
wire output1_s1_chipselect;
wire output1_s1_end_xfer;
wire output1_s1_firsttransfer;
wire output1_s1_grant_vector;
wire output1_s1_in_a_read_cycle;
wire output1_s1_in_a_write_cycle;
wire output1_s1_master_qreq_vector;
wire output1_s1_non_bursting_master_requests;
wire [ 31: 0] output1_s1_readdata_from_sa;
reg output1_s1_reg_firsttransfer;
wire output1_s1_reset_n;
reg output1_s1_slavearbiterlockenable;
wire output1_s1_slavearbiterlockenable2;
wire output1_s1_unreg_firsttransfer;
wire output1_s1_waits_for_read;
wire output1_s1_waits_for_write;
wire output1_s1_write_n;
wire [ 31: 0] output1_s1_writedata;
wire [ 27: 0] shifted_address_to_output1_s1_from_cpu_0_data_master;
wire wait_for_output1_s1_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~output1_s1_end_xfer;
end
assign output1_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_output1_s1));
//assign output1_s1_readdata_from_sa = output1_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign output1_s1_readdata_from_sa = output1_s1_readdata;
assign cpu_0_data_master_requests_output1_s1 = ({cpu_0_data_master_address_to_slave[27 : 4] , 4'b0} == 28'h0) & (cpu_0_data_master_read | cpu_0_data_master_write);
//output1_s1_arb_share_counter set values, which is an e_mux
assign output1_s1_arb_share_set_values = 1;
//output1_s1_non_bursting_master_requests mux, which is an e_mux
assign output1_s1_non_bursting_master_requests = cpu_0_data_master_requests_output1_s1;
//output1_s1_any_bursting_master_saved_grant mux, which is an e_mux
assign output1_s1_any_bursting_master_saved_grant = 0;
//output1_s1_arb_share_counter_next_value assignment, which is an e_assign
assign output1_s1_arb_share_counter_next_value = output1_s1_firsttransfer ? (output1_s1_arb_share_set_values - 1) : |output1_s1_arb_share_counter ? (output1_s1_arb_share_counter - 1) : 0;
//output1_s1_allgrants all slave grants, which is an e_mux
assign output1_s1_allgrants = |output1_s1_grant_vector;
//output1_s1_end_xfer assignment, which is an e_assign
assign output1_s1_end_xfer = ~(output1_s1_waits_for_read | output1_s1_waits_for_write);
//end_xfer_arb_share_counter_term_output1_s1 arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_output1_s1 = output1_s1_end_xfer & (~output1_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//output1_s1_arb_share_counter arbitration counter enable, which is an e_assign
assign output1_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_output1_s1 & output1_s1_allgrants) | (end_xfer_arb_share_counter_term_output1_s1 & ~output1_s1_non_bursting_master_requests);
//output1_s1_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
output1_s1_arb_share_counter <= 0;
else if (output1_s1_arb_counter_enable)
output1_s1_arb_share_counter <= output1_s1_arb_share_counter_next_value;
end
//output1_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
output1_s1_slavearbiterlockenable <= 0;
else if ((|output1_s1_master_qreq_vector & end_xfer_arb_share_counter_term_output1_s1) | (end_xfer_arb_share_counter_term_output1_s1 & ~output1_s1_non_bursting_master_requests))
output1_s1_slavearbiterlockenable <= |output1_s1_arb_share_counter_next_value;
end
//cpu_0/data_master output1/s1 arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = output1_s1_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//output1_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign output1_s1_slavearbiterlockenable2 = |output1_s1_arb_share_counter_next_value;
//cpu_0/data_master output1/s1 arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = output1_s1_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//output1_s1_any_continuerequest at least one master continues requesting, which is an e_assign
assign output1_s1_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_output1_s1 = cpu_0_data_master_requests_output1_s1 & ~(((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write));
//output1_s1_writedata mux, which is an e_mux
assign output1_s1_writedata = cpu_0_data_master_writedata;
//master is always granted when requested
assign cpu_0_data_master_granted_output1_s1 = cpu_0_data_master_qualified_request_output1_s1;
//cpu_0/data_master saved-grant output1/s1, which is an e_assign
assign cpu_0_data_master_saved_grant_output1_s1 = cpu_0_data_master_requests_output1_s1;
//allow new arb cycle for output1/s1, which is an e_assign
assign output1_s1_allow_new_arb_cycle = 1;
//placeholder chosen master
assign output1_s1_grant_vector = 1;
//placeholder vector of master qualified-requests
assign output1_s1_master_qreq_vector = 1;
//output1_s1_reset_n assignment, which is an e_assign
assign output1_s1_reset_n = reset_n;
assign output1_s1_chipselect = cpu_0_data_master_granted_output1_s1;
//output1_s1_firsttransfer first transaction, which is an e_assign
assign output1_s1_firsttransfer = output1_s1_begins_xfer ? output1_s1_unreg_firsttransfer : output1_s1_reg_firsttransfer;
//output1_s1_unreg_firsttransfer first transaction, which is an e_assign
assign output1_s1_unreg_firsttransfer = ~(output1_s1_slavearbiterlockenable & output1_s1_any_continuerequest);
//output1_s1_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
output1_s1_reg_firsttransfer <= 1'b1;
else if (output1_s1_begins_xfer)
output1_s1_reg_firsttransfer <= output1_s1_unreg_firsttransfer;
end
//output1_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign output1_s1_beginbursttransfer_internal = output1_s1_begins_xfer;
//~output1_s1_write_n assignment, which is an e_mux
assign output1_s1_write_n = ~(cpu_0_data_master_granted_output1_s1 & cpu_0_data_master_write);
assign shifted_address_to_output1_s1_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//output1_s1_address mux, which is an e_mux
assign output1_s1_address = shifted_address_to_output1_s1_from_cpu_0_data_master >> 2;
//d1_output1_s1_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_output1_s1_end_xfer <= 1;
else
d1_output1_s1_end_xfer <= output1_s1_end_xfer;
end
//output1_s1_waits_for_read in a cycle, which is an e_mux
assign output1_s1_waits_for_read = output1_s1_in_a_read_cycle & output1_s1_begins_xfer;
//output1_s1_in_a_read_cycle assignment, which is an e_assign
assign output1_s1_in_a_read_cycle = cpu_0_data_master_granted_output1_s1 & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = output1_s1_in_a_read_cycle;
//output1_s1_waits_for_write in a cycle, which is an e_mux
assign output1_s1_waits_for_write = output1_s1_in_a_write_cycle & 0;
//output1_s1_in_a_write_cycle assignment, which is an e_assign
assign output1_s1_in_a_write_cycle = cpu_0_data_master_granted_output1_s1 & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = output1_s1_in_a_write_cycle;
assign wait_for_output1_s1_counter = 0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//output1/s1 enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module (
// inputs:
clear_fifo,
clk,
data_in,
read,
reset_n,
sync_reset,
write,
// outputs:
data_out,
empty,
fifo_contains_ones_n,
full
)
;
output data_out;
output empty;
output fifo_contains_ones_n;
output full;
input clear_fifo;
input clk;
input data_in;
input read;
input reset_n;
input sync_reset;
input write;
wire data_out;
wire empty;
reg fifo_contains_ones_n;
wire full;
reg full_0;
reg full_1;
reg full_2;
reg full_3;
reg full_4;
reg full_5;
reg full_6;
wire full_7;
reg [ 3: 0] how_many_ones;
wire [ 3: 0] one_count_minus_one;
wire [ 3: 0] one_count_plus_one;
wire p0_full_0;
wire p0_stage_0;
wire p1_full_1;
wire p1_stage_1;
wire p2_full_2;
wire p2_stage_2;
wire p3_full_3;
wire p3_stage_3;
wire p4_full_4;
wire p4_stage_4;
wire p5_full_5;
wire p5_stage_5;
wire p6_full_6;
wire p6_stage_6;
reg stage_0;
reg stage_1;
reg stage_2;
reg stage_3;
reg stage_4;
reg stage_5;
reg stage_6;
wire [ 3: 0] updated_one_count;
assign data_out = stage_0;
assign full = full_6;
assign empty = !full_0;
assign full_7 = 0;
//data_6, which is an e_mux
assign p6_stage_6 = ((full_7 & ~clear_fifo) == 0)? data_in :
data_in;
//data_reg_6, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_6 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_6))
if (sync_reset & full_6 & !((full_7 == 0) & read & write))
stage_6 <= 0;
else
stage_6 <= p6_stage_6;
end
//control_6, which is an e_mux
assign p6_full_6 = ((read & !write) == 0)? full_5 :
0;
//control_reg_6, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_6 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo)
full_6 <= 0;
else
full_6 <= p6_full_6;
end
//data_5, which is an e_mux
assign p5_stage_5 = ((full_6 & ~clear_fifo) == 0)? data_in :
stage_6;
//data_reg_5, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_5 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_5))
if (sync_reset & full_5 & !((full_6 == 0) & read & write))
stage_5 <= 0;
else
stage_5 <= p5_stage_5;
end
//control_5, which is an e_mux
assign p5_full_5 = ((read & !write) == 0)? full_4 :
full_6;
//control_reg_5, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_5 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo)
full_5 <= 0;
else
full_5 <= p5_full_5;
end
//data_4, which is an e_mux
assign p4_stage_4 = ((full_5 & ~clear_fifo) == 0)? data_in :
stage_5;
//data_reg_4, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_4 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_4))
if (sync_reset & full_4 & !((full_5 == 0) & read & write))
stage_4 <= 0;
else
stage_4 <= p4_stage_4;
end
//control_4, which is an e_mux
assign p4_full_4 = ((read & !write) == 0)? full_3 :
full_5;
//control_reg_4, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_4 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo)
full_4 <= 0;
else
full_4 <= p4_full_4;
end
//data_3, which is an e_mux
assign p3_stage_3 = ((full_4 & ~clear_fifo) == 0)? data_in :
stage_4;
//data_reg_3, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_3 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_3))
if (sync_reset & full_3 & !((full_4 == 0) & read & write))
stage_3 <= 0;
else
stage_3 <= p3_stage_3;
end
//control_3, which is an e_mux
assign p3_full_3 = ((read & !write) == 0)? full_2 :
full_4;
//control_reg_3, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_3 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo)
full_3 <= 0;
else
full_3 <= p3_full_3;
end
//data_2, which is an e_mux
assign p2_stage_2 = ((full_3 & ~clear_fifo) == 0)? data_in :
stage_3;
//data_reg_2, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_2 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_2))
if (sync_reset & full_2 & !((full_3 == 0) & read & write))
stage_2 <= 0;
else
stage_2 <= p2_stage_2;
end
//control_2, which is an e_mux
assign p2_full_2 = ((read & !write) == 0)? full_1 :
full_3;
//control_reg_2, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_2 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo)
full_2 <= 0;
else
full_2 <= p2_full_2;
end
//data_1, which is an e_mux
assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
stage_2;
//data_reg_1, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_1 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_1))
if (sync_reset & full_1 & !((full_2 == 0) & read & write))
stage_1 <= 0;
else
stage_1 <= p1_stage_1;
end
//control_1, which is an e_mux
assign p1_full_1 = ((read & !write) == 0)? full_0 :
full_2;
//control_reg_1, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_1 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo)
full_1 <= 0;
else
full_1 <= p1_full_1;
end
//data_0, which is an e_mux
assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
stage_1;
//data_reg_0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_0 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_0))
if (sync_reset & full_0 & !((full_1 == 0) & read & write))
stage_0 <= 0;
else
stage_0 <= p0_stage_0;
end
//control_0, which is an e_mux
assign p0_full_0 = ((read & !write) == 0)? 1 :
full_1;
//control_reg_0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_0 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo & ~write)
full_0 <= 0;
else
full_0 <= p0_full_0;
end
assign one_count_plus_one = how_many_ones + 1;
assign one_count_minus_one = how_many_ones - 1;
//updated_one_count, which is an e_mux
assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
((((clear_fifo | sync_reset) & write)))? |data_in :
((read & (|data_in) & write & (|stage_0)))? how_many_ones :
((write & (|data_in)))? one_count_plus_one :
((read & (|stage_0)))? one_count_minus_one :
how_many_ones;
//counts how many ones in the data pipeline, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
how_many_ones <= 0;
else if (clear_fifo | sync_reset | read | write)
how_many_ones <= updated_one_count;
end
//this fifo contains ones in the data pipeline, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_contains_ones_n <= 1;
else if (clear_fifo | sync_reset | read | write)
fifo_contains_ones_n <= ~(|updated_one_count);
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module (
// inputs:
clear_fifo,
clk,
data_in,
read,
reset_n,
sync_reset,
write,
// outputs:
data_out,
empty,
fifo_contains_ones_n,
full
)
;
output data_out;
output empty;
output fifo_contains_ones_n;
output full;
input clear_fifo;
input clk;
input data_in;
input read;
input reset_n;
input sync_reset;
input write;
wire data_out;
wire empty;
reg fifo_contains_ones_n;
wire full;
reg full_0;
reg full_1;
reg full_2;
reg full_3;
reg full_4;
reg full_5;
reg full_6;
wire full_7;
reg [ 3: 0] how_many_ones;
wire [ 3: 0] one_count_minus_one;
wire [ 3: 0] one_count_plus_one;
wire p0_full_0;
wire p0_stage_0;
wire p1_full_1;
wire p1_stage_1;
wire p2_full_2;
wire p2_stage_2;
wire p3_full_3;
wire p3_stage_3;
wire p4_full_4;
wire p4_stage_4;
wire p5_full_5;
wire p5_stage_5;
wire p6_full_6;
wire p6_stage_6;
reg stage_0;
reg stage_1;
reg stage_2;
reg stage_3;
reg stage_4;
reg stage_5;
reg stage_6;
wire [ 3: 0] updated_one_count;
assign data_out = stage_0;
assign full = full_6;
assign empty = !full_0;
assign full_7 = 0;
//data_6, which is an e_mux
assign p6_stage_6 = ((full_7 & ~clear_fifo) == 0)? data_in :
data_in;
//data_reg_6, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_6 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_6))
if (sync_reset & full_6 & !((full_7 == 0) & read & write))
stage_6 <= 0;
else
stage_6 <= p6_stage_6;
end
//control_6, which is an e_mux
assign p6_full_6 = ((read & !write) == 0)? full_5 :
0;
//control_reg_6, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_6 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo)
full_6 <= 0;
else
full_6 <= p6_full_6;
end
//data_5, which is an e_mux
assign p5_stage_5 = ((full_6 & ~clear_fifo) == 0)? data_in :
stage_6;
//data_reg_5, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_5 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_5))
if (sync_reset & full_5 & !((full_6 == 0) & read & write))
stage_5 <= 0;
else
stage_5 <= p5_stage_5;
end
//control_5, which is an e_mux
assign p5_full_5 = ((read & !write) == 0)? full_4 :
full_6;
//control_reg_5, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_5 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo)
full_5 <= 0;
else
full_5 <= p5_full_5;
end
//data_4, which is an e_mux
assign p4_stage_4 = ((full_5 & ~clear_fifo) == 0)? data_in :
stage_5;
//data_reg_4, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_4 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_4))
if (sync_reset & full_4 & !((full_5 == 0) & read & write))
stage_4 <= 0;
else
stage_4 <= p4_stage_4;
end
//control_4, which is an e_mux
assign p4_full_4 = ((read & !write) == 0)? full_3 :
full_5;
//control_reg_4, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_4 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo)
full_4 <= 0;
else
full_4 <= p4_full_4;
end
//data_3, which is an e_mux
assign p3_stage_3 = ((full_4 & ~clear_fifo) == 0)? data_in :
stage_4;
//data_reg_3, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_3 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_3))
if (sync_reset & full_3 & !((full_4 == 0) & read & write))
stage_3 <= 0;
else
stage_3 <= p3_stage_3;
end
//control_3, which is an e_mux
assign p3_full_3 = ((read & !write) == 0)? full_2 :
full_4;
//control_reg_3, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_3 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo)
full_3 <= 0;
else
full_3 <= p3_full_3;
end
//data_2, which is an e_mux
assign p2_stage_2 = ((full_3 & ~clear_fifo) == 0)? data_in :
stage_3;
//data_reg_2, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_2 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_2))
if (sync_reset & full_2 & !((full_3 == 0) & read & write))
stage_2 <= 0;
else
stage_2 <= p2_stage_2;
end
//control_2, which is an e_mux
assign p2_full_2 = ((read & !write) == 0)? full_1 :
full_3;
//control_reg_2, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_2 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo)
full_2 <= 0;
else
full_2 <= p2_full_2;
end
//data_1, which is an e_mux
assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
stage_2;
//data_reg_1, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_1 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_1))
if (sync_reset & full_1 & !((full_2 == 0) & read & write))
stage_1 <= 0;
else
stage_1 <= p1_stage_1;
end
//control_1, which is an e_mux
assign p1_full_1 = ((read & !write) == 0)? full_0 :
full_2;
//control_reg_1, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_1 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo)
full_1 <= 0;
else
full_1 <= p1_full_1;
end
//data_0, which is an e_mux
assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
stage_1;
//data_reg_0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_0 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_0))
if (sync_reset & full_0 & !((full_1 == 0) & read & write))
stage_0 <= 0;
else
stage_0 <= p0_stage_0;
end
//control_0, which is an e_mux
assign p0_full_0 = ((read & !write) == 0)? 1 :
full_1;
//control_reg_0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_0 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo & ~write)
full_0 <= 0;
else
full_0 <= p0_full_0;
end
assign one_count_plus_one = how_many_ones + 1;
assign one_count_minus_one = how_many_ones - 1;
//updated_one_count, which is an e_mux
assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
((((clear_fifo | sync_reset) & write)))? |data_in :
((read & (|data_in) & write & (|stage_0)))? how_many_ones :
((write & (|data_in)))? one_count_plus_one :
((read & (|stage_0)))? one_count_minus_one :
how_many_ones;
//counts how many ones in the data pipeline, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
how_many_ones <= 0;
else if (clear_fifo | sync_reset | read | write)
how_many_ones <= updated_one_count;
end
//this fifo contains ones in the data pipeline, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_contains_ones_n <= 1;
else if (clear_fifo | sync_reset | read | write)
fifo_contains_ones_n <= ~(|updated_one_count);
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sdram_0_s1_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_byteenable,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
cpu_0_instruction_master_address_to_slave,
cpu_0_instruction_master_read,
reset_n,
sdram_0_s1_readdata,
sdram_0_s1_readdatavalid,
sdram_0_s1_waitrequest,
// outputs:
cpu_0_data_master_granted_sdram_0_s1,
cpu_0_data_master_qualified_request_sdram_0_s1,
cpu_0_data_master_read_data_valid_sdram_0_s1,
cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register,
cpu_0_data_master_requests_sdram_0_s1,
cpu_0_instruction_master_granted_sdram_0_s1,
cpu_0_instruction_master_qualified_request_sdram_0_s1,
cpu_0_instruction_master_read_data_valid_sdram_0_s1,
cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register,
cpu_0_instruction_master_requests_sdram_0_s1,
d1_sdram_0_s1_end_xfer,
sdram_0_s1_address,
sdram_0_s1_byteenable_n,
sdram_0_s1_chipselect,
sdram_0_s1_read_n,
sdram_0_s1_readdata_from_sa,
sdram_0_s1_reset_n,
sdram_0_s1_waitrequest_from_sa,
sdram_0_s1_write_n,
sdram_0_s1_writedata
)
;
output cpu_0_data_master_granted_sdram_0_s1;
output cpu_0_data_master_qualified_request_sdram_0_s1;
output cpu_0_data_master_read_data_valid_sdram_0_s1;
output cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register;
output cpu_0_data_master_requests_sdram_0_s1;
output cpu_0_instruction_master_granted_sdram_0_s1;
output cpu_0_instruction_master_qualified_request_sdram_0_s1;
output cpu_0_instruction_master_read_data_valid_sdram_0_s1;
output cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register;
output cpu_0_instruction_master_requests_sdram_0_s1;
output d1_sdram_0_s1_end_xfer;
output [ 24: 0] sdram_0_s1_address;
output [ 3: 0] sdram_0_s1_byteenable_n;
output sdram_0_s1_chipselect;
output sdram_0_s1_read_n;
output [ 31: 0] sdram_0_s1_readdata_from_sa;
output sdram_0_s1_reset_n;
output sdram_0_s1_waitrequest_from_sa;
output sdram_0_s1_write_n;
output [ 31: 0] sdram_0_s1_writedata;
input clk;
input [ 27: 0] cpu_0_data_master_address_to_slave;
input [ 3: 0] cpu_0_data_master_byteenable;
input cpu_0_data_master_read;
input cpu_0_data_master_waitrequest;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input [ 27: 0] cpu_0_instruction_master_address_to_slave;
input cpu_0_instruction_master_read;
input reset_n;
input [ 31: 0] sdram_0_s1_readdata;
input sdram_0_s1_readdatavalid;
input sdram_0_s1_waitrequest;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_sdram_0_s1;
wire cpu_0_data_master_qualified_request_sdram_0_s1;
wire cpu_0_data_master_rdv_fifo_empty_sdram_0_s1;
wire cpu_0_data_master_rdv_fifo_output_from_sdram_0_s1;
wire cpu_0_data_master_read_data_valid_sdram_0_s1;
wire cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register;
wire cpu_0_data_master_requests_sdram_0_s1;
wire cpu_0_data_master_saved_grant_sdram_0_s1;
wire cpu_0_instruction_master_arbiterlock;
wire cpu_0_instruction_master_arbiterlock2;
wire cpu_0_instruction_master_continuerequest;
wire cpu_0_instruction_master_granted_sdram_0_s1;
wire cpu_0_instruction_master_qualified_request_sdram_0_s1;
wire cpu_0_instruction_master_rdv_fifo_empty_sdram_0_s1;
wire cpu_0_instruction_master_rdv_fifo_output_from_sdram_0_s1;
wire cpu_0_instruction_master_read_data_valid_sdram_0_s1;
wire cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register;
wire cpu_0_instruction_master_requests_sdram_0_s1;
wire cpu_0_instruction_master_saved_grant_sdram_0_s1;
reg d1_reasons_to_wait;
reg d1_sdram_0_s1_end_xfer;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_sdram_0_s1;
wire in_a_read_cycle;
wire in_a_write_cycle;
reg last_cycle_cpu_0_data_master_granted_slave_sdram_0_s1;
reg last_cycle_cpu_0_instruction_master_granted_slave_sdram_0_s1;
wire [ 24: 0] sdram_0_s1_address;
wire sdram_0_s1_allgrants;
wire sdram_0_s1_allow_new_arb_cycle;
wire sdram_0_s1_any_bursting_master_saved_grant;
wire sdram_0_s1_any_continuerequest;
reg [ 1: 0] sdram_0_s1_arb_addend;
wire sdram_0_s1_arb_counter_enable;
reg [ 2: 0] sdram_0_s1_arb_share_counter;
wire [ 2: 0] sdram_0_s1_arb_share_counter_next_value;
wire [ 2: 0] sdram_0_s1_arb_share_set_values;
wire [ 1: 0] sdram_0_s1_arb_winner;
wire sdram_0_s1_arbitration_holdoff_internal;
wire sdram_0_s1_beginbursttransfer_internal;
wire sdram_0_s1_begins_xfer;
wire [ 3: 0] sdram_0_s1_byteenable_n;
wire sdram_0_s1_chipselect;
wire [ 3: 0] sdram_0_s1_chosen_master_double_vector;
wire [ 1: 0] sdram_0_s1_chosen_master_rot_left;
wire sdram_0_s1_end_xfer;
wire sdram_0_s1_firsttransfer;
wire [ 1: 0] sdram_0_s1_grant_vector;
wire sdram_0_s1_in_a_read_cycle;
wire sdram_0_s1_in_a_write_cycle;
wire [ 1: 0] sdram_0_s1_master_qreq_vector;
wire sdram_0_s1_move_on_to_next_transaction;
wire sdram_0_s1_non_bursting_master_requests;
wire sdram_0_s1_read_n;
wire [ 31: 0] sdram_0_s1_readdata_from_sa;
wire sdram_0_s1_readdatavalid_from_sa;
reg sdram_0_s1_reg_firsttransfer;
wire sdram_0_s1_reset_n;
reg [ 1: 0] sdram_0_s1_saved_chosen_master_vector;
reg sdram_0_s1_slavearbiterlockenable;
wire sdram_0_s1_slavearbiterlockenable2;
wire sdram_0_s1_unreg_firsttransfer;
wire sdram_0_s1_waitrequest_from_sa;
wire sdram_0_s1_waits_for_read;
wire sdram_0_s1_waits_for_write;
wire sdram_0_s1_write_n;
wire [ 31: 0] sdram_0_s1_writedata;
wire [ 27: 0] shifted_address_to_sdram_0_s1_from_cpu_0_data_master;
wire [ 27: 0] shifted_address_to_sdram_0_s1_from_cpu_0_instruction_master;
wire wait_for_sdram_0_s1_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~sdram_0_s1_end_xfer;
end
assign sdram_0_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_sdram_0_s1 | cpu_0_instruction_master_qualified_request_sdram_0_s1));
//assign sdram_0_s1_readdata_from_sa = sdram_0_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign sdram_0_s1_readdata_from_sa = sdram_0_s1_readdata;
assign cpu_0_data_master_requests_sdram_0_s1 = ({cpu_0_data_master_address_to_slave[27] , 27'b0} == 28'h8000000) & (cpu_0_data_master_read | cpu_0_data_master_write);
//assign sdram_0_s1_waitrequest_from_sa = sdram_0_s1_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
assign sdram_0_s1_waitrequest_from_sa = sdram_0_s1_waitrequest;
//assign sdram_0_s1_readdatavalid_from_sa = sdram_0_s1_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
assign sdram_0_s1_readdatavalid_from_sa = sdram_0_s1_readdatavalid;
//sdram_0_s1_arb_share_counter set values, which is an e_mux
assign sdram_0_s1_arb_share_set_values = 1;
//sdram_0_s1_non_bursting_master_requests mux, which is an e_mux
assign sdram_0_s1_non_bursting_master_requests = cpu_0_data_master_requests_sdram_0_s1 |
cpu_0_instruction_master_requests_sdram_0_s1 |
cpu_0_data_master_requests_sdram_0_s1 |
cpu_0_instruction_master_requests_sdram_0_s1;
//sdram_0_s1_any_bursting_master_saved_grant mux, which is an e_mux
assign sdram_0_s1_any_bursting_master_saved_grant = 0;
//sdram_0_s1_arb_share_counter_next_value assignment, which is an e_assign
assign sdram_0_s1_arb_share_counter_next_value = sdram_0_s1_firsttransfer ? (sdram_0_s1_arb_share_set_values - 1) : |sdram_0_s1_arb_share_counter ? (sdram_0_s1_arb_share_counter - 1) : 0;
//sdram_0_s1_allgrants all slave grants, which is an e_mux
assign sdram_0_s1_allgrants = (|sdram_0_s1_grant_vector) |
(|sdram_0_s1_grant_vector) |
(|sdram_0_s1_grant_vector) |
(|sdram_0_s1_grant_vector);
//sdram_0_s1_end_xfer assignment, which is an e_assign
assign sdram_0_s1_end_xfer = ~(sdram_0_s1_waits_for_read | sdram_0_s1_waits_for_write);
//end_xfer_arb_share_counter_term_sdram_0_s1 arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_sdram_0_s1 = sdram_0_s1_end_xfer & (~sdram_0_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//sdram_0_s1_arb_share_counter arbitration counter enable, which is an e_assign
assign sdram_0_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_sdram_0_s1 & sdram_0_s1_allgrants) | (end_xfer_arb_share_counter_term_sdram_0_s1 & ~sdram_0_s1_non_bursting_master_requests);
//sdram_0_s1_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sdram_0_s1_arb_share_counter <= 0;
else if (sdram_0_s1_arb_counter_enable)
sdram_0_s1_arb_share_counter <= sdram_0_s1_arb_share_counter_next_value;
end
//sdram_0_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sdram_0_s1_slavearbiterlockenable <= 0;
else if ((|sdram_0_s1_master_qreq_vector & end_xfer_arb_share_counter_term_sdram_0_s1) | (end_xfer_arb_share_counter_term_sdram_0_s1 & ~sdram_0_s1_non_bursting_master_requests))
sdram_0_s1_slavearbiterlockenable <= |sdram_0_s1_arb_share_counter_next_value;
end
//cpu_0/data_master sdram_0/s1 arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = sdram_0_s1_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//sdram_0_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign sdram_0_s1_slavearbiterlockenable2 = |sdram_0_s1_arb_share_counter_next_value;
//cpu_0/data_master sdram_0/s1 arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = sdram_0_s1_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//cpu_0/instruction_master sdram_0/s1 arbiterlock, which is an e_assign
assign cpu_0_instruction_master_arbiterlock = sdram_0_s1_slavearbiterlockenable & cpu_0_instruction_master_continuerequest;
//cpu_0/instruction_master sdram_0/s1 arbiterlock2, which is an e_assign
assign cpu_0_instruction_master_arbiterlock2 = sdram_0_s1_slavearbiterlockenable2 & cpu_0_instruction_master_continuerequest;
//cpu_0/instruction_master granted sdram_0/s1 last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_0_instruction_master_granted_slave_sdram_0_s1 <= 0;
else
last_cycle_cpu_0_instruction_master_granted_slave_sdram_0_s1 <= cpu_0_instruction_master_saved_grant_sdram_0_s1 ? 1 : (sdram_0_s1_arbitration_holdoff_internal | ~cpu_0_instruction_master_requests_sdram_0_s1) ? 0 : last_cycle_cpu_0_instruction_master_granted_slave_sdram_0_s1;
end
//cpu_0_instruction_master_continuerequest continued request, which is an e_mux
assign cpu_0_instruction_master_continuerequest = last_cycle_cpu_0_instruction_master_granted_slave_sdram_0_s1 & cpu_0_instruction_master_requests_sdram_0_s1;
//sdram_0_s1_any_continuerequest at least one master continues requesting, which is an e_mux
assign sdram_0_s1_any_continuerequest = cpu_0_instruction_master_continuerequest |
cpu_0_data_master_continuerequest;
assign cpu_0_data_master_qualified_request_sdram_0_s1 = cpu_0_data_master_requests_sdram_0_s1 & ~((cpu_0_data_master_read & (~cpu_0_data_master_waitrequest | (|cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register))) | ((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write) | cpu_0_instruction_master_arbiterlock);
//unique name for sdram_0_s1_move_on_to_next_transaction, which is an e_assign
assign sdram_0_s1_move_on_to_next_transaction = sdram_0_s1_readdatavalid_from_sa;
//rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1, which is an e_fifo_with_registered_outputs
rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1
(
.clear_fifo (1'b0),
.clk (clk),
.data_in (cpu_0_data_master_granted_sdram_0_s1),
.data_out (cpu_0_data_master_rdv_fifo_output_from_sdram_0_s1),
.empty (),
.fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_sdram_0_s1),
.full (),
.read (sdram_0_s1_move_on_to_next_transaction),
.reset_n (reset_n),
.sync_reset (1'b0),
.write (in_a_read_cycle & ~sdram_0_s1_waits_for_read)
);
assign cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register = ~cpu_0_data_master_rdv_fifo_empty_sdram_0_s1;
//local readdatavalid cpu_0_data_master_read_data_valid_sdram_0_s1, which is an e_mux
assign cpu_0_data_master_read_data_valid_sdram_0_s1 = (sdram_0_s1_readdatavalid_from_sa & cpu_0_data_master_rdv_fifo_output_from_sdram_0_s1) & ~ cpu_0_data_master_rdv_fifo_empty_sdram_0_s1;
//sdram_0_s1_writedata mux, which is an e_mux
assign sdram_0_s1_writedata = cpu_0_data_master_writedata;
assign cpu_0_instruction_master_requests_sdram_0_s1 = (({cpu_0_instruction_master_address_to_slave[27] , 27'b0} == 28'h8000000) & (cpu_0_instruction_master_read)) & cpu_0_instruction_master_read;
//cpu_0/data_master granted sdram_0/s1 last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_0_data_master_granted_slave_sdram_0_s1 <= 0;
else
last_cycle_cpu_0_data_master_granted_slave_sdram_0_s1 <= cpu_0_data_master_saved_grant_sdram_0_s1 ? 1 : (sdram_0_s1_arbitration_holdoff_internal | ~cpu_0_data_master_requests_sdram_0_s1) ? 0 : last_cycle_cpu_0_data_master_granted_slave_sdram_0_s1;
end
//cpu_0_data_master_continuerequest continued request, which is an e_mux
assign cpu_0_data_master_continuerequest = last_cycle_cpu_0_data_master_granted_slave_sdram_0_s1 & cpu_0_data_master_requests_sdram_0_s1;
assign cpu_0_instruction_master_qualified_request_sdram_0_s1 = cpu_0_instruction_master_requests_sdram_0_s1 & ~((cpu_0_instruction_master_read & ((|cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register))) | cpu_0_data_master_arbiterlock);
//rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1, which is an e_fifo_with_registered_outputs
rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1
(
.clear_fifo (1'b0),
.clk (clk),
.data_in (cpu_0_instruction_master_granted_sdram_0_s1),
.data_out (cpu_0_instruction_master_rdv_fifo_output_from_sdram_0_s1),
.empty (),
.fifo_contains_ones_n (cpu_0_instruction_master_rdv_fifo_empty_sdram_0_s1),
.full (),
.read (sdram_0_s1_move_on_to_next_transaction),
.reset_n (reset_n),
.sync_reset (1'b0),
.write (in_a_read_cycle & ~sdram_0_s1_waits_for_read)
);
assign cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register = ~cpu_0_instruction_master_rdv_fifo_empty_sdram_0_s1;
//local readdatavalid cpu_0_instruction_master_read_data_valid_sdram_0_s1, which is an e_mux
assign cpu_0_instruction_master_read_data_valid_sdram_0_s1 = (sdram_0_s1_readdatavalid_from_sa & cpu_0_instruction_master_rdv_fifo_output_from_sdram_0_s1) & ~ cpu_0_instruction_master_rdv_fifo_empty_sdram_0_s1;
//allow new arb cycle for sdram_0/s1, which is an e_assign
assign sdram_0_s1_allow_new_arb_cycle = ~cpu_0_data_master_arbiterlock & ~cpu_0_instruction_master_arbiterlock;
//cpu_0/instruction_master assignment into master qualified-requests vector for sdram_0/s1, which is an e_assign
assign sdram_0_s1_master_qreq_vector[0] = cpu_0_instruction_master_qualified_request_sdram_0_s1;
//cpu_0/instruction_master grant sdram_0/s1, which is an e_assign
assign cpu_0_instruction_master_granted_sdram_0_s1 = sdram_0_s1_grant_vector[0];
//cpu_0/instruction_master saved-grant sdram_0/s1, which is an e_assign
assign cpu_0_instruction_master_saved_grant_sdram_0_s1 = sdram_0_s1_arb_winner[0] && cpu_0_instruction_master_requests_sdram_0_s1;
//cpu_0/data_master assignment into master qualified-requests vector for sdram_0/s1, which is an e_assign
assign sdram_0_s1_master_qreq_vector[1] = cpu_0_data_master_qualified_request_sdram_0_s1;
//cpu_0/data_master grant sdram_0/s1, which is an e_assign
assign cpu_0_data_master_granted_sdram_0_s1 = sdram_0_s1_grant_vector[1];
//cpu_0/data_master saved-grant sdram_0/s1, which is an e_assign
assign cpu_0_data_master_saved_grant_sdram_0_s1 = sdram_0_s1_arb_winner[1] && cpu_0_data_master_requests_sdram_0_s1;
//sdram_0/s1 chosen-master double-vector, which is an e_assign
assign sdram_0_s1_chosen_master_double_vector = {sdram_0_s1_master_qreq_vector, sdram_0_s1_master_qreq_vector} & ({~sdram_0_s1_master_qreq_vector, ~sdram_0_s1_master_qreq_vector} + sdram_0_s1_arb_addend);
//stable onehot encoding of arb winner
assign sdram_0_s1_arb_winner = (sdram_0_s1_allow_new_arb_cycle & | sdram_0_s1_grant_vector) ? sdram_0_s1_grant_vector : sdram_0_s1_saved_chosen_master_vector;
//saved sdram_0_s1_grant_vector, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sdram_0_s1_saved_chosen_master_vector <= 0;
else if (sdram_0_s1_allow_new_arb_cycle)
sdram_0_s1_saved_chosen_master_vector <= |sdram_0_s1_grant_vector ? sdram_0_s1_grant_vector : sdram_0_s1_saved_chosen_master_vector;
end
//onehot encoding of chosen master
assign sdram_0_s1_grant_vector = {(sdram_0_s1_chosen_master_double_vector[1] | sdram_0_s1_chosen_master_double_vector[3]),
(sdram_0_s1_chosen_master_double_vector[0] | sdram_0_s1_chosen_master_double_vector[2])};
//sdram_0/s1 chosen master rotated left, which is an e_assign
assign sdram_0_s1_chosen_master_rot_left = (sdram_0_s1_arb_winner << 1) ? (sdram_0_s1_arb_winner << 1) : 1;
//sdram_0/s1's addend for next-master-grant
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sdram_0_s1_arb_addend <= 1;
else if (|sdram_0_s1_grant_vector)
sdram_0_s1_arb_addend <= sdram_0_s1_end_xfer? sdram_0_s1_chosen_master_rot_left : sdram_0_s1_grant_vector;
end
//sdram_0_s1_reset_n assignment, which is an e_assign
assign sdram_0_s1_reset_n = reset_n;
assign sdram_0_s1_chipselect = cpu_0_data_master_granted_sdram_0_s1 | cpu_0_instruction_master_granted_sdram_0_s1;
//sdram_0_s1_firsttransfer first transaction, which is an e_assign
assign sdram_0_s1_firsttransfer = sdram_0_s1_begins_xfer ? sdram_0_s1_unreg_firsttransfer : sdram_0_s1_reg_firsttransfer;
//sdram_0_s1_unreg_firsttransfer first transaction, which is an e_assign
assign sdram_0_s1_unreg_firsttransfer = ~(sdram_0_s1_slavearbiterlockenable & sdram_0_s1_any_continuerequest);
//sdram_0_s1_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sdram_0_s1_reg_firsttransfer <= 1'b1;
else if (sdram_0_s1_begins_xfer)
sdram_0_s1_reg_firsttransfer <= sdram_0_s1_unreg_firsttransfer;
end
//sdram_0_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign sdram_0_s1_beginbursttransfer_internal = sdram_0_s1_begins_xfer;
//sdram_0_s1_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
assign sdram_0_s1_arbitration_holdoff_internal = sdram_0_s1_begins_xfer & sdram_0_s1_firsttransfer;
//~sdram_0_s1_read_n assignment, which is an e_mux
assign sdram_0_s1_read_n = ~((cpu_0_data_master_granted_sdram_0_s1 & cpu_0_data_master_read) | (cpu_0_instruction_master_granted_sdram_0_s1 & cpu_0_instruction_master_read));
//~sdram_0_s1_write_n assignment, which is an e_mux
assign sdram_0_s1_write_n = ~(cpu_0_data_master_granted_sdram_0_s1 & cpu_0_data_master_write);
assign shifted_address_to_sdram_0_s1_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//sdram_0_s1_address mux, which is an e_mux
assign sdram_0_s1_address = (cpu_0_data_master_granted_sdram_0_s1)? (shifted_address_to_sdram_0_s1_from_cpu_0_data_master >> 2) :
(shifted_address_to_sdram_0_s1_from_cpu_0_instruction_master >> 2);
assign shifted_address_to_sdram_0_s1_from_cpu_0_instruction_master = cpu_0_instruction_master_address_to_slave;
//d1_sdram_0_s1_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_sdram_0_s1_end_xfer <= 1;
else
d1_sdram_0_s1_end_xfer <= sdram_0_s1_end_xfer;
end
//sdram_0_s1_waits_for_read in a cycle, which is an e_mux
assign sdram_0_s1_waits_for_read = sdram_0_s1_in_a_read_cycle & sdram_0_s1_waitrequest_from_sa;
//sdram_0_s1_in_a_read_cycle assignment, which is an e_assign
assign sdram_0_s1_in_a_read_cycle = (cpu_0_data_master_granted_sdram_0_s1 & cpu_0_data_master_read) | (cpu_0_instruction_master_granted_sdram_0_s1 & cpu_0_instruction_master_read);
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = sdram_0_s1_in_a_read_cycle;
//sdram_0_s1_waits_for_write in a cycle, which is an e_mux
assign sdram_0_s1_waits_for_write = sdram_0_s1_in_a_write_cycle & sdram_0_s1_waitrequest_from_sa;
//sdram_0_s1_in_a_write_cycle assignment, which is an e_assign
assign sdram_0_s1_in_a_write_cycle = cpu_0_data_master_granted_sdram_0_s1 & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = sdram_0_s1_in_a_write_cycle;
assign wait_for_sdram_0_s1_counter = 0;
//~sdram_0_s1_byteenable_n byte enable port mux, which is an e_mux
assign sdram_0_s1_byteenable_n = ~((cpu_0_data_master_granted_sdram_0_s1)? cpu_0_data_master_byteenable :
-1);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//sdram_0/s1 enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_0_data_master_granted_sdram_0_s1 + cpu_0_instruction_master_granted_sdram_0_s1 > 1)
begin
$write("%0d ns: > 1 of grant signals are active simultaneously", $time);
$stop;
end
end
//saved_grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_0_data_master_saved_grant_sdram_0_s1 + cpu_0_instruction_master_saved_grant_sdram_0_s1 > 1)
begin
$write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sysid_control_slave_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_read,
cpu_0_data_master_write,
reset_n,
sysid_control_slave_readdata,
// outputs:
cpu_0_data_master_granted_sysid_control_slave,
cpu_0_data_master_qualified_request_sysid_control_slave,
cpu_0_data_master_read_data_valid_sysid_control_slave,
cpu_0_data_master_requests_sysid_control_slave,
d1_sysid_control_slave_end_xfer,
sysid_control_slave_address,
sysid_control_slave_readdata_from_sa,
sysid_control_slave_reset_n
)
;
output cpu_0_data_master_granted_sysid_control_slave;
output cpu_0_data_master_qualified_request_sysid_control_slave;
output cpu_0_data_master_read_data_valid_sysid_control_slave;
output cpu_0_data_master_requests_sysid_control_slave;
output d1_sysid_control_slave_end_xfer;
output sysid_control_slave_address;
output [ 31: 0] sysid_control_slave_readdata_from_sa;
output sysid_control_slave_reset_n;
input clk;
input [ 27: 0] cpu_0_data_master_address_to_slave;
input cpu_0_data_master_read;
input cpu_0_data_master_write;
input reset_n;
input [ 31: 0] sysid_control_slave_readdata;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_sysid_control_slave;
wire cpu_0_data_master_qualified_request_sysid_control_slave;
wire cpu_0_data_master_read_data_valid_sysid_control_slave;
wire cpu_0_data_master_requests_sysid_control_slave;
wire cpu_0_data_master_saved_grant_sysid_control_slave;
reg d1_reasons_to_wait;
reg d1_sysid_control_slave_end_xfer;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_sysid_control_slave;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 27: 0] shifted_address_to_sysid_control_slave_from_cpu_0_data_master;
wire sysid_control_slave_address;
wire sysid_control_slave_allgrants;
wire sysid_control_slave_allow_new_arb_cycle;
wire sysid_control_slave_any_bursting_master_saved_grant;
wire sysid_control_slave_any_continuerequest;
wire sysid_control_slave_arb_counter_enable;
reg [ 2: 0] sysid_control_slave_arb_share_counter;
wire [ 2: 0] sysid_control_slave_arb_share_counter_next_value;
wire [ 2: 0] sysid_control_slave_arb_share_set_values;
wire sysid_control_slave_beginbursttransfer_internal;
wire sysid_control_slave_begins_xfer;
wire sysid_control_slave_end_xfer;
wire sysid_control_slave_firsttransfer;
wire sysid_control_slave_grant_vector;
wire sysid_control_slave_in_a_read_cycle;
wire sysid_control_slave_in_a_write_cycle;
wire sysid_control_slave_master_qreq_vector;
wire sysid_control_slave_non_bursting_master_requests;
wire [ 31: 0] sysid_control_slave_readdata_from_sa;
reg sysid_control_slave_reg_firsttransfer;
wire sysid_control_slave_reset_n;
reg sysid_control_slave_slavearbiterlockenable;
wire sysid_control_slave_slavearbiterlockenable2;
wire sysid_control_slave_unreg_firsttransfer;
wire sysid_control_slave_waits_for_read;
wire sysid_control_slave_waits_for_write;
wire wait_for_sysid_control_slave_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~sysid_control_slave_end_xfer;
end
assign sysid_control_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_sysid_control_slave));
//assign sysid_control_slave_readdata_from_sa = sysid_control_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign sysid_control_slave_readdata_from_sa = sysid_control_slave_readdata;
assign cpu_0_data_master_requests_sysid_control_slave = (({cpu_0_data_master_address_to_slave[27 : 3] , 3'b0} == 28'h30) & (cpu_0_data_master_read | cpu_0_data_master_write)) & cpu_0_data_master_read;
//sysid_control_slave_arb_share_counter set values, which is an e_mux
assign sysid_control_slave_arb_share_set_values = 1;
//sysid_control_slave_non_bursting_master_requests mux, which is an e_mux
assign sysid_control_slave_non_bursting_master_requests = cpu_0_data_master_requests_sysid_control_slave;
//sysid_control_slave_any_bursting_master_saved_grant mux, which is an e_mux
assign sysid_control_slave_any_bursting_master_saved_grant = 0;
//sysid_control_slave_arb_share_counter_next_value assignment, which is an e_assign
assign sysid_control_slave_arb_share_counter_next_value = sysid_control_slave_firsttransfer ? (sysid_control_slave_arb_share_set_values - 1) : |sysid_control_slave_arb_share_counter ? (sysid_control_slave_arb_share_counter - 1) : 0;
//sysid_control_slave_allgrants all slave grants, which is an e_mux
assign sysid_control_slave_allgrants = |sysid_control_slave_grant_vector;
//sysid_control_slave_end_xfer assignment, which is an e_assign
assign sysid_control_slave_end_xfer = ~(sysid_control_slave_waits_for_read | sysid_control_slave_waits_for_write);
//end_xfer_arb_share_counter_term_sysid_control_slave arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_sysid_control_slave = sysid_control_slave_end_xfer & (~sysid_control_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//sysid_control_slave_arb_share_counter arbitration counter enable, which is an e_assign
assign sysid_control_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_sysid_control_slave & sysid_control_slave_allgrants) | (end_xfer_arb_share_counter_term_sysid_control_slave & ~sysid_control_slave_non_bursting_master_requests);
//sysid_control_slave_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sysid_control_slave_arb_share_counter <= 0;
else if (sysid_control_slave_arb_counter_enable)
sysid_control_slave_arb_share_counter <= sysid_control_slave_arb_share_counter_next_value;
end
//sysid_control_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sysid_control_slave_slavearbiterlockenable <= 0;
else if ((|sysid_control_slave_master_qreq_vector & end_xfer_arb_share_counter_term_sysid_control_slave) | (end_xfer_arb_share_counter_term_sysid_control_slave & ~sysid_control_slave_non_bursting_master_requests))
sysid_control_slave_slavearbiterlockenable <= |sysid_control_slave_arb_share_counter_next_value;
end
//cpu_0/data_master sysid/control_slave arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = sysid_control_slave_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//sysid_control_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign sysid_control_slave_slavearbiterlockenable2 = |sysid_control_slave_arb_share_counter_next_value;
//cpu_0/data_master sysid/control_slave arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = sysid_control_slave_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//sysid_control_slave_any_continuerequest at least one master continues requesting, which is an e_assign
assign sysid_control_slave_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_sysid_control_slave = cpu_0_data_master_requests_sysid_control_slave;
//master is always granted when requested
assign cpu_0_data_master_granted_sysid_control_slave = cpu_0_data_master_qualified_request_sysid_control_slave;
//cpu_0/data_master saved-grant sysid/control_slave, which is an e_assign
assign cpu_0_data_master_saved_grant_sysid_control_slave = cpu_0_data_master_requests_sysid_control_slave;
//allow new arb cycle for sysid/control_slave, which is an e_assign
assign sysid_control_slave_allow_new_arb_cycle = 1;
//placeholder chosen master
assign sysid_control_slave_grant_vector = 1;
//placeholder vector of master qualified-requests
assign sysid_control_slave_master_qreq_vector = 1;
//sysid_control_slave_reset_n assignment, which is an e_assign
assign sysid_control_slave_reset_n = reset_n;
//sysid_control_slave_firsttransfer first transaction, which is an e_assign
assign sysid_control_slave_firsttransfer = sysid_control_slave_begins_xfer ? sysid_control_slave_unreg_firsttransfer : sysid_control_slave_reg_firsttransfer;
//sysid_control_slave_unreg_firsttransfer first transaction, which is an e_assign
assign sysid_control_slave_unreg_firsttransfer = ~(sysid_control_slave_slavearbiterlockenable & sysid_control_slave_any_continuerequest);
//sysid_control_slave_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sysid_control_slave_reg_firsttransfer <= 1'b1;
else if (sysid_control_slave_begins_xfer)
sysid_control_slave_reg_firsttransfer <= sysid_control_slave_unreg_firsttransfer;
end
//sysid_control_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign sysid_control_slave_beginbursttransfer_internal = sysid_control_slave_begins_xfer;
assign shifted_address_to_sysid_control_slave_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//sysid_control_slave_address mux, which is an e_mux
assign sysid_control_slave_address = shifted_address_to_sysid_control_slave_from_cpu_0_data_master >> 2;
//d1_sysid_control_slave_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_sysid_control_slave_end_xfer <= 1;
else
d1_sysid_control_slave_end_xfer <= sysid_control_slave_end_xfer;
end
//sysid_control_slave_waits_for_read in a cycle, which is an e_mux
assign sysid_control_slave_waits_for_read = sysid_control_slave_in_a_read_cycle & sysid_control_slave_begins_xfer;
//sysid_control_slave_in_a_read_cycle assignment, which is an e_assign
assign sysid_control_slave_in_a_read_cycle = cpu_0_data_master_granted_sysid_control_slave & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = sysid_control_slave_in_a_read_cycle;
//sysid_control_slave_waits_for_write in a cycle, which is an e_mux
assign sysid_control_slave_waits_for_write = sysid_control_slave_in_a_write_cycle & 0;
//sysid_control_slave_in_a_write_cycle assignment, which is an e_assign
assign sysid_control_slave_in_a_write_cycle = cpu_0_data_master_granted_sysid_control_slave & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = sysid_control_slave_in_a_write_cycle;
assign wait_for_sysid_control_slave_counter = 0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//sysid/control_slave enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_character_buffer_with_dma_0_avalon_char_buffer_slave_arbitrator (
// inputs:
clk,
nios_system_clock_1_out_address_to_slave,
nios_system_clock_1_out_read,
nios_system_clock_1_out_write,
nios_system_clock_1_out_writedata,
reset_n,
video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata,
video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest,
// outputs:
d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer,
nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave,
nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave,
nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave,
nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave,
video_character_buffer_with_dma_0_avalon_char_buffer_slave_address,
video_character_buffer_with_dma_0_avalon_char_buffer_slave_byteenable,
video_character_buffer_with_dma_0_avalon_char_buffer_slave_chipselect,
video_character_buffer_with_dma_0_avalon_char_buffer_slave_read,
video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa,
video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa,
video_character_buffer_with_dma_0_avalon_char_buffer_slave_write,
video_character_buffer_with_dma_0_avalon_char_buffer_slave_writedata
)
;
output d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer;
output nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
output nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
output nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
output nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
output [ 12: 0] video_character_buffer_with_dma_0_avalon_char_buffer_slave_address;
output video_character_buffer_with_dma_0_avalon_char_buffer_slave_byteenable;
output video_character_buffer_with_dma_0_avalon_char_buffer_slave_chipselect;
output video_character_buffer_with_dma_0_avalon_char_buffer_slave_read;
output [ 7: 0] video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa;
output video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa;
output video_character_buffer_with_dma_0_avalon_char_buffer_slave_write;
output [ 7: 0] video_character_buffer_with_dma_0_avalon_char_buffer_slave_writedata;
input clk;
input [ 12: 0] nios_system_clock_1_out_address_to_slave;
input nios_system_clock_1_out_read;
input nios_system_clock_1_out_write;
input [ 7: 0] nios_system_clock_1_out_writedata;
input reset_n;
input [ 7: 0] video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata;
input video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest;
reg d1_reasons_to_wait;
reg d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire nios_system_clock_1_out_arbiterlock;
wire nios_system_clock_1_out_arbiterlock2;
wire nios_system_clock_1_out_continuerequest;
wire nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
wire nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
wire nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
reg nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register;
wire nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register_in;
wire nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
wire nios_system_clock_1_out_saved_grant_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
wire p1_nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register;
wire [ 12: 0] video_character_buffer_with_dma_0_avalon_char_buffer_slave_address;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_allgrants;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_allow_new_arb_cycle;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_any_bursting_master_saved_grant;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_any_continuerequest;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_counter_enable;
reg video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter_next_value;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_set_values;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_beginbursttransfer_internal;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_begins_xfer;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_byteenable;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_chipselect;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_firsttransfer;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_grant_vector;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_in_a_read_cycle;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_in_a_write_cycle;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_master_qreq_vector;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_non_bursting_master_requests;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_read;
wire [ 7: 0] video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa;
reg video_character_buffer_with_dma_0_avalon_char_buffer_slave_reg_firsttransfer;
reg video_character_buffer_with_dma_0_avalon_char_buffer_slave_slavearbiterlockenable;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_slavearbiterlockenable2;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_unreg_firsttransfer;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_waits_for_read;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_waits_for_write;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_write;
wire [ 7: 0] video_character_buffer_with_dma_0_avalon_char_buffer_slave_writedata;
wire wait_for_video_character_buffer_with_dma_0_avalon_char_buffer_slave_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer;
end
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_begins_xfer = ~d1_reasons_to_wait & ((nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave));
//assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa = video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa = video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata;
assign nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave = (1) & (nios_system_clock_1_out_read | nios_system_clock_1_out_write);
//assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa = video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa = video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter set values, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_set_values = 1;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_non_bursting_master_requests mux, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_non_bursting_master_requests = nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_any_bursting_master_saved_grant mux, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_any_bursting_master_saved_grant = 0;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter_next_value assignment, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter_next_value = video_character_buffer_with_dma_0_avalon_char_buffer_slave_firsttransfer ? (video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_set_values - 1) : |video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter ? (video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter - 1) : 0;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_allgrants all slave grants, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_allgrants = |video_character_buffer_with_dma_0_avalon_char_buffer_slave_grant_vector;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer assignment, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer = ~(video_character_buffer_with_dma_0_avalon_char_buffer_slave_waits_for_read | video_character_buffer_with_dma_0_avalon_char_buffer_slave_waits_for_write);
//end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_buffer_slave arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_buffer_slave = video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer & (~video_character_buffer_with_dma_0_avalon_char_buffer_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter arbitration counter enable, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_buffer_slave & video_character_buffer_with_dma_0_avalon_char_buffer_slave_allgrants) | (end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_buffer_slave & ~video_character_buffer_with_dma_0_avalon_char_buffer_slave_non_bursting_master_requests);
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter <= 0;
else if (video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_counter_enable)
video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter <= video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter_next_value;
end
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
video_character_buffer_with_dma_0_avalon_char_buffer_slave_slavearbiterlockenable <= 0;
else if ((|video_character_buffer_with_dma_0_avalon_char_buffer_slave_master_qreq_vector & end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_buffer_slave) | (end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_buffer_slave & ~video_character_buffer_with_dma_0_avalon_char_buffer_slave_non_bursting_master_requests))
video_character_buffer_with_dma_0_avalon_char_buffer_slave_slavearbiterlockenable <= |video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter_next_value;
end
//nios_system_clock_1/out video_character_buffer_with_dma_0/avalon_char_buffer_slave arbiterlock, which is an e_assign
assign nios_system_clock_1_out_arbiterlock = video_character_buffer_with_dma_0_avalon_char_buffer_slave_slavearbiterlockenable & nios_system_clock_1_out_continuerequest;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_slavearbiterlockenable2 = |video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter_next_value;
//nios_system_clock_1/out video_character_buffer_with_dma_0/avalon_char_buffer_slave arbiterlock2, which is an e_assign
assign nios_system_clock_1_out_arbiterlock2 = video_character_buffer_with_dma_0_avalon_char_buffer_slave_slavearbiterlockenable2 & nios_system_clock_1_out_continuerequest;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_any_continuerequest at least one master continues requesting, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_any_continuerequest = 1;
//nios_system_clock_1_out_continuerequest continued request, which is an e_assign
assign nios_system_clock_1_out_continuerequest = 1;
assign nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave = nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave & ~((nios_system_clock_1_out_read & ((|nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register))));
//nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register_in mux for readlatency shift register, which is an e_mux
assign nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register_in = nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave & nios_system_clock_1_out_read & ~video_character_buffer_with_dma_0_avalon_char_buffer_slave_waits_for_read & ~(|nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register);
//shift register p1 nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register in if flush, otherwise shift left, which is an e_mux
assign p1_nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register = {nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register, nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register_in};
//nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register for remembering which master asked for a fixed latency read, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register <= 0;
else
nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register <= p1_nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register;
end
//local readdatavalid nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave, which is an e_mux
assign nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave = nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_writedata mux, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_writedata = nios_system_clock_1_out_writedata;
//master is always granted when requested
assign nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave = nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
//nios_system_clock_1/out saved-grant video_character_buffer_with_dma_0/avalon_char_buffer_slave, which is an e_assign
assign nios_system_clock_1_out_saved_grant_video_character_buffer_with_dma_0_avalon_char_buffer_slave = nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
//allow new arb cycle for video_character_buffer_with_dma_0/avalon_char_buffer_slave, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_allow_new_arb_cycle = 1;
//placeholder chosen master
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_grant_vector = 1;
//placeholder vector of master qualified-requests
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_master_qreq_vector = 1;
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_chipselect = nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_firsttransfer first transaction, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_firsttransfer = video_character_buffer_with_dma_0_avalon_char_buffer_slave_begins_xfer ? video_character_buffer_with_dma_0_avalon_char_buffer_slave_unreg_firsttransfer : video_character_buffer_with_dma_0_avalon_char_buffer_slave_reg_firsttransfer;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_unreg_firsttransfer first transaction, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_unreg_firsttransfer = ~(video_character_buffer_with_dma_0_avalon_char_buffer_slave_slavearbiterlockenable & video_character_buffer_with_dma_0_avalon_char_buffer_slave_any_continuerequest);
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
video_character_buffer_with_dma_0_avalon_char_buffer_slave_reg_firsttransfer <= 1'b1;
else if (video_character_buffer_with_dma_0_avalon_char_buffer_slave_begins_xfer)
video_character_buffer_with_dma_0_avalon_char_buffer_slave_reg_firsttransfer <= video_character_buffer_with_dma_0_avalon_char_buffer_slave_unreg_firsttransfer;
end
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_beginbursttransfer_internal = video_character_buffer_with_dma_0_avalon_char_buffer_slave_begins_xfer;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_read assignment, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_read = nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave & nios_system_clock_1_out_read;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_write assignment, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_write = nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave & nios_system_clock_1_out_write;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_address mux, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_address = nios_system_clock_1_out_address_to_slave;
//d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer <= 1;
else
d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer <= video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer;
end
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_waits_for_read in a cycle, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_waits_for_read = video_character_buffer_with_dma_0_avalon_char_buffer_slave_in_a_read_cycle & video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_in_a_read_cycle assignment, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_in_a_read_cycle = nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave & nios_system_clock_1_out_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = video_character_buffer_with_dma_0_avalon_char_buffer_slave_in_a_read_cycle;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_waits_for_write in a cycle, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_waits_for_write = video_character_buffer_with_dma_0_avalon_char_buffer_slave_in_a_write_cycle & video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_in_a_write_cycle assignment, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_in_a_write_cycle = nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave & nios_system_clock_1_out_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = video_character_buffer_with_dma_0_avalon_char_buffer_slave_in_a_write_cycle;
assign wait_for_video_character_buffer_with_dma_0_avalon_char_buffer_slave_counter = 0;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_byteenable byte enable port mux, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_byteenable = (nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave)? {1 {1'b1}} :
-1;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//video_character_buffer_with_dma_0/avalon_char_buffer_slave enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_character_buffer_with_dma_0_avalon_char_control_slave_arbitrator (
// inputs:
clk,
nios_system_clock_0_out_address_to_slave,
nios_system_clock_0_out_byteenable,
nios_system_clock_0_out_read,
nios_system_clock_0_out_write,
nios_system_clock_0_out_writedata,
reset_n,
video_character_buffer_with_dma_0_avalon_char_control_slave_readdata,
// outputs:
d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer,
nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave,
nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave,
nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave,
nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave,
video_character_buffer_with_dma_0_avalon_char_control_slave_address,
video_character_buffer_with_dma_0_avalon_char_control_slave_byteenable,
video_character_buffer_with_dma_0_avalon_char_control_slave_chipselect,
video_character_buffer_with_dma_0_avalon_char_control_slave_read,
video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa,
video_character_buffer_with_dma_0_avalon_char_control_slave_reset,
video_character_buffer_with_dma_0_avalon_char_control_slave_write,
video_character_buffer_with_dma_0_avalon_char_control_slave_writedata
)
;
output d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer;
output nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave;
output nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave;
output nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave;
output nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave;
output video_character_buffer_with_dma_0_avalon_char_control_slave_address;
output [ 3: 0] video_character_buffer_with_dma_0_avalon_char_control_slave_byteenable;
output video_character_buffer_with_dma_0_avalon_char_control_slave_chipselect;
output video_character_buffer_with_dma_0_avalon_char_control_slave_read;
output [ 31: 0] video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa;
output video_character_buffer_with_dma_0_avalon_char_control_slave_reset;
output video_character_buffer_with_dma_0_avalon_char_control_slave_write;
output [ 31: 0] video_character_buffer_with_dma_0_avalon_char_control_slave_writedata;
input clk;
input [ 2: 0] nios_system_clock_0_out_address_to_slave;
input [ 3: 0] nios_system_clock_0_out_byteenable;
input nios_system_clock_0_out_read;
input nios_system_clock_0_out_write;
input [ 31: 0] nios_system_clock_0_out_writedata;
input reset_n;
input [ 31: 0] video_character_buffer_with_dma_0_avalon_char_control_slave_readdata;
reg d1_reasons_to_wait;
reg d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_control_slave;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire nios_system_clock_0_out_arbiterlock;
wire nios_system_clock_0_out_arbiterlock2;
wire nios_system_clock_0_out_continuerequest;
wire nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave;
wire nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave;
wire nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave;
reg nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register;
wire nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register_in;
wire nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave;
wire nios_system_clock_0_out_saved_grant_video_character_buffer_with_dma_0_avalon_char_control_slave;
wire p1_nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register;
wire [ 2: 0] shifted_address_to_video_character_buffer_with_dma_0_avalon_char_control_slave_from_nios_system_clock_0_out;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_address;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_allgrants;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_allow_new_arb_cycle;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_any_bursting_master_saved_grant;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_any_continuerequest;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_arb_counter_enable;
reg video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter_next_value;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_set_values;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_beginbursttransfer_internal;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_begins_xfer;
wire [ 3: 0] video_character_buffer_with_dma_0_avalon_char_control_slave_byteenable;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_chipselect;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_firsttransfer;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_grant_vector;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_in_a_read_cycle;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_in_a_write_cycle;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_master_qreq_vector;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_non_bursting_master_requests;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_read;
wire [ 31: 0] video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa;
reg video_character_buffer_with_dma_0_avalon_char_control_slave_reg_firsttransfer;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_reset;
reg video_character_buffer_with_dma_0_avalon_char_control_slave_slavearbiterlockenable;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_slavearbiterlockenable2;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_unreg_firsttransfer;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_waits_for_read;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_waits_for_write;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_write;
wire [ 31: 0] video_character_buffer_with_dma_0_avalon_char_control_slave_writedata;
wire wait_for_video_character_buffer_with_dma_0_avalon_char_control_slave_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer;
end
assign video_character_buffer_with_dma_0_avalon_char_control_slave_begins_xfer = ~d1_reasons_to_wait & ((nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave));
//assign video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa = video_character_buffer_with_dma_0_avalon_char_control_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa = video_character_buffer_with_dma_0_avalon_char_control_slave_readdata;
assign nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave = (1) & (nios_system_clock_0_out_read | nios_system_clock_0_out_write);
//video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter set values, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_set_values = 1;
//video_character_buffer_with_dma_0_avalon_char_control_slave_non_bursting_master_requests mux, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_control_slave_non_bursting_master_requests = nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave;
//video_character_buffer_with_dma_0_avalon_char_control_slave_any_bursting_master_saved_grant mux, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_control_slave_any_bursting_master_saved_grant = 0;
//video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter_next_value assignment, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter_next_value = video_character_buffer_with_dma_0_avalon_char_control_slave_firsttransfer ? (video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_set_values - 1) : |video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter ? (video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter - 1) : 0;
//video_character_buffer_with_dma_0_avalon_char_control_slave_allgrants all slave grants, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_control_slave_allgrants = |video_character_buffer_with_dma_0_avalon_char_control_slave_grant_vector;
//video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer assignment, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer = ~(video_character_buffer_with_dma_0_avalon_char_control_slave_waits_for_read | video_character_buffer_with_dma_0_avalon_char_control_slave_waits_for_write);
//end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_control_slave arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_control_slave = video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer & (~video_character_buffer_with_dma_0_avalon_char_control_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter arbitration counter enable, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_control_slave & video_character_buffer_with_dma_0_avalon_char_control_slave_allgrants) | (end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_control_slave & ~video_character_buffer_with_dma_0_avalon_char_control_slave_non_bursting_master_requests);
//video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter <= 0;
else if (video_character_buffer_with_dma_0_avalon_char_control_slave_arb_counter_enable)
video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter <= video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter_next_value;
end
//video_character_buffer_with_dma_0_avalon_char_control_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
video_character_buffer_with_dma_0_avalon_char_control_slave_slavearbiterlockenable <= 0;
else if ((|video_character_buffer_with_dma_0_avalon_char_control_slave_master_qreq_vector & end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_control_slave) | (end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_control_slave & ~video_character_buffer_with_dma_0_avalon_char_control_slave_non_bursting_master_requests))
video_character_buffer_with_dma_0_avalon_char_control_slave_slavearbiterlockenable <= |video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter_next_value;
end
//nios_system_clock_0/out video_character_buffer_with_dma_0/avalon_char_control_slave arbiterlock, which is an e_assign
assign nios_system_clock_0_out_arbiterlock = video_character_buffer_with_dma_0_avalon_char_control_slave_slavearbiterlockenable & nios_system_clock_0_out_continuerequest;
//video_character_buffer_with_dma_0_avalon_char_control_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_slavearbiterlockenable2 = |video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter_next_value;
//nios_system_clock_0/out video_character_buffer_with_dma_0/avalon_char_control_slave arbiterlock2, which is an e_assign
assign nios_system_clock_0_out_arbiterlock2 = video_character_buffer_with_dma_0_avalon_char_control_slave_slavearbiterlockenable2 & nios_system_clock_0_out_continuerequest;
//video_character_buffer_with_dma_0_avalon_char_control_slave_any_continuerequest at least one master continues requesting, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_any_continuerequest = 1;
//nios_system_clock_0_out_continuerequest continued request, which is an e_assign
assign nios_system_clock_0_out_continuerequest = 1;
assign nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave = nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave & ~((nios_system_clock_0_out_read & ((|nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register))));
//nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register_in mux for readlatency shift register, which is an e_mux
assign nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register_in = nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave & nios_system_clock_0_out_read & ~video_character_buffer_with_dma_0_avalon_char_control_slave_waits_for_read & ~(|nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register);
//shift register p1 nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register in if flush, otherwise shift left, which is an e_mux
assign p1_nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register = {nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register, nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register_in};
//nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register for remembering which master asked for a fixed latency read, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register <= 0;
else
nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register <= p1_nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register;
end
//local readdatavalid nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave, which is an e_mux
assign nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave = nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register;
//video_character_buffer_with_dma_0_avalon_char_control_slave_writedata mux, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_control_slave_writedata = nios_system_clock_0_out_writedata;
//master is always granted when requested
assign nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave = nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave;
//nios_system_clock_0/out saved-grant video_character_buffer_with_dma_0/avalon_char_control_slave, which is an e_assign
assign nios_system_clock_0_out_saved_grant_video_character_buffer_with_dma_0_avalon_char_control_slave = nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave;
//allow new arb cycle for video_character_buffer_with_dma_0/avalon_char_control_slave, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_allow_new_arb_cycle = 1;
//placeholder chosen master
assign video_character_buffer_with_dma_0_avalon_char_control_slave_grant_vector = 1;
//placeholder vector of master qualified-requests
assign video_character_buffer_with_dma_0_avalon_char_control_slave_master_qreq_vector = 1;
//~video_character_buffer_with_dma_0_avalon_char_control_slave_reset assignment, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_reset = ~reset_n;
assign video_character_buffer_with_dma_0_avalon_char_control_slave_chipselect = nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave;
//video_character_buffer_with_dma_0_avalon_char_control_slave_firsttransfer first transaction, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_firsttransfer = video_character_buffer_with_dma_0_avalon_char_control_slave_begins_xfer ? video_character_buffer_with_dma_0_avalon_char_control_slave_unreg_firsttransfer : video_character_buffer_with_dma_0_avalon_char_control_slave_reg_firsttransfer;
//video_character_buffer_with_dma_0_avalon_char_control_slave_unreg_firsttransfer first transaction, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_unreg_firsttransfer = ~(video_character_buffer_with_dma_0_avalon_char_control_slave_slavearbiterlockenable & video_character_buffer_with_dma_0_avalon_char_control_slave_any_continuerequest);
//video_character_buffer_with_dma_0_avalon_char_control_slave_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
video_character_buffer_with_dma_0_avalon_char_control_slave_reg_firsttransfer <= 1'b1;
else if (video_character_buffer_with_dma_0_avalon_char_control_slave_begins_xfer)
video_character_buffer_with_dma_0_avalon_char_control_slave_reg_firsttransfer <= video_character_buffer_with_dma_0_avalon_char_control_slave_unreg_firsttransfer;
end
//video_character_buffer_with_dma_0_avalon_char_control_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_beginbursttransfer_internal = video_character_buffer_with_dma_0_avalon_char_control_slave_begins_xfer;
//video_character_buffer_with_dma_0_avalon_char_control_slave_read assignment, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_control_slave_read = nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave & nios_system_clock_0_out_read;
//video_character_buffer_with_dma_0_avalon_char_control_slave_write assignment, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_control_slave_write = nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave & nios_system_clock_0_out_write;
assign shifted_address_to_video_character_buffer_with_dma_0_avalon_char_control_slave_from_nios_system_clock_0_out = nios_system_clock_0_out_address_to_slave;
//video_character_buffer_with_dma_0_avalon_char_control_slave_address mux, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_control_slave_address = shifted_address_to_video_character_buffer_with_dma_0_avalon_char_control_slave_from_nios_system_clock_0_out >> 2;
//d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer <= 1;
else
d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer <= video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer;
end
//video_character_buffer_with_dma_0_avalon_char_control_slave_waits_for_read in a cycle, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_control_slave_waits_for_read = video_character_buffer_with_dma_0_avalon_char_control_slave_in_a_read_cycle & 0;
//video_character_buffer_with_dma_0_avalon_char_control_slave_in_a_read_cycle assignment, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_in_a_read_cycle = nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave & nios_system_clock_0_out_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = video_character_buffer_with_dma_0_avalon_char_control_slave_in_a_read_cycle;
//video_character_buffer_with_dma_0_avalon_char_control_slave_waits_for_write in a cycle, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_control_slave_waits_for_write = video_character_buffer_with_dma_0_avalon_char_control_slave_in_a_write_cycle & 0;
//video_character_buffer_with_dma_0_avalon_char_control_slave_in_a_write_cycle assignment, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_in_a_write_cycle = nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave & nios_system_clock_0_out_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = video_character_buffer_with_dma_0_avalon_char_control_slave_in_a_write_cycle;
assign wait_for_video_character_buffer_with_dma_0_avalon_char_control_slave_counter = 0;
//video_character_buffer_with_dma_0_avalon_char_control_slave_byteenable byte enable port mux, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_control_slave_byteenable = (nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave)? nios_system_clock_0_out_byteenable :
-1;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//video_character_buffer_with_dma_0/avalon_char_control_slave enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_character_buffer_with_dma_0_avalon_char_source_arbitrator (
// inputs:
clk,
reset_n,
video_character_buffer_with_dma_0_avalon_char_source_data,
video_character_buffer_with_dma_0_avalon_char_source_endofpacket,
video_character_buffer_with_dma_0_avalon_char_source_startofpacket,
video_character_buffer_with_dma_0_avalon_char_source_valid,
video_vga_controller_0_avalon_vga_sink_ready_from_sa,
// outputs:
video_character_buffer_with_dma_0_avalon_char_source_ready
)
;
output video_character_buffer_with_dma_0_avalon_char_source_ready;
input clk;
input reset_n;
input [ 29: 0] video_character_buffer_with_dma_0_avalon_char_source_data;
input video_character_buffer_with_dma_0_avalon_char_source_endofpacket;
input video_character_buffer_with_dma_0_avalon_char_source_startofpacket;
input video_character_buffer_with_dma_0_avalon_char_source_valid;
input video_vga_controller_0_avalon_vga_sink_ready_from_sa;
wire video_character_buffer_with_dma_0_avalon_char_source_ready;
//mux video_character_buffer_with_dma_0_avalon_char_source_ready, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_source_ready = video_vga_controller_0_avalon_vga_sink_ready_from_sa;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_vga_controller_0_avalon_vga_sink_arbitrator (
// inputs:
clk,
reset_n,
video_character_buffer_with_dma_0_avalon_char_source_data,
video_character_buffer_with_dma_0_avalon_char_source_endofpacket,
video_character_buffer_with_dma_0_avalon_char_source_startofpacket,
video_character_buffer_with_dma_0_avalon_char_source_valid,
video_vga_controller_0_avalon_vga_sink_ready,
// outputs:
video_vga_controller_0_avalon_vga_sink_data,
video_vga_controller_0_avalon_vga_sink_endofpacket,
video_vga_controller_0_avalon_vga_sink_ready_from_sa,
video_vga_controller_0_avalon_vga_sink_reset,
video_vga_controller_0_avalon_vga_sink_startofpacket,
video_vga_controller_0_avalon_vga_sink_valid
)
;
output [ 29: 0] video_vga_controller_0_avalon_vga_sink_data;
output video_vga_controller_0_avalon_vga_sink_endofpacket;
output video_vga_controller_0_avalon_vga_sink_ready_from_sa;
output video_vga_controller_0_avalon_vga_sink_reset;
output video_vga_controller_0_avalon_vga_sink_startofpacket;
output video_vga_controller_0_avalon_vga_sink_valid;
input clk;
input reset_n;
input [ 29: 0] video_character_buffer_with_dma_0_avalon_char_source_data;
input video_character_buffer_with_dma_0_avalon_char_source_endofpacket;
input video_character_buffer_with_dma_0_avalon_char_source_startofpacket;
input video_character_buffer_with_dma_0_avalon_char_source_valid;
input video_vga_controller_0_avalon_vga_sink_ready;
wire [ 29: 0] video_vga_controller_0_avalon_vga_sink_data;
wire video_vga_controller_0_avalon_vga_sink_endofpacket;
wire video_vga_controller_0_avalon_vga_sink_ready_from_sa;
wire video_vga_controller_0_avalon_vga_sink_reset;
wire video_vga_controller_0_avalon_vga_sink_startofpacket;
wire video_vga_controller_0_avalon_vga_sink_valid;
//mux video_vga_controller_0_avalon_vga_sink_data, which is an e_mux
assign video_vga_controller_0_avalon_vga_sink_data = video_character_buffer_with_dma_0_avalon_char_source_data;
//mux video_vga_controller_0_avalon_vga_sink_endofpacket, which is an e_mux
assign video_vga_controller_0_avalon_vga_sink_endofpacket = video_character_buffer_with_dma_0_avalon_char_source_endofpacket;
//assign video_vga_controller_0_avalon_vga_sink_ready_from_sa = video_vga_controller_0_avalon_vga_sink_ready so that symbol knows where to group signals which may go to master only, which is an e_assign
assign video_vga_controller_0_avalon_vga_sink_ready_from_sa = video_vga_controller_0_avalon_vga_sink_ready;
//mux video_vga_controller_0_avalon_vga_sink_startofpacket, which is an e_mux
assign video_vga_controller_0_avalon_vga_sink_startofpacket = video_character_buffer_with_dma_0_avalon_char_source_startofpacket;
//mux video_vga_controller_0_avalon_vga_sink_valid, which is an e_mux
assign video_vga_controller_0_avalon_vga_sink_valid = video_character_buffer_with_dma_0_avalon_char_source_valid;
//~video_vga_controller_0_avalon_vga_sink_reset assignment, which is an e_assign
assign video_vga_controller_0_avalon_vga_sink_reset = ~reset_n;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_reset_clk_0_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
)
;
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_in_d1 <= 0;
else
data_in_d1 <= data_in;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else
data_out <= data_in_d1;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_reset_vga_clock_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
)
;
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_in_d1 <= 0;
else
data_in_d1 <= data_in;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else
data_out <= data_in_d1;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system (
// 1) global signals:
clk_0,
clocks_SDRAM_CLK_out,
clocks_sys_clk_out,
reset_n,
vga_clock,
// the_Altera_UP_SD_Card_Avalon_Interface_0
b_SD_cmd_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0,
b_SD_dat3_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0,
b_SD_dat_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0,
o_SD_clock_from_the_Altera_UP_SD_Card_Avalon_Interface_0,
// the_input1
in_port_to_the_input1,
// the_output1
out_port_from_the_output1,
// the_sdram_0
zs_addr_from_the_sdram_0,
zs_ba_from_the_sdram_0,
zs_cas_n_from_the_sdram_0,
zs_cke_from_the_sdram_0,
zs_cs_n_from_the_sdram_0,
zs_dq_to_and_from_the_sdram_0,
zs_dqm_from_the_sdram_0,
zs_ras_n_from_the_sdram_0,
zs_we_n_from_the_sdram_0,
// the_video_vga_controller_0
VGA_BLANK_from_the_video_vga_controller_0,
VGA_B_from_the_video_vga_controller_0,
VGA_CLK_from_the_video_vga_controller_0,
VGA_G_from_the_video_vga_controller_0,
VGA_HS_from_the_video_vga_controller_0,
VGA_R_from_the_video_vga_controller_0,
VGA_SYNC_from_the_video_vga_controller_0,
VGA_VS_from_the_video_vga_controller_0
)
;
output VGA_BLANK_from_the_video_vga_controller_0;
output [ 7: 0] VGA_B_from_the_video_vga_controller_0;
output VGA_CLK_from_the_video_vga_controller_0;
output [ 7: 0] VGA_G_from_the_video_vga_controller_0;
output VGA_HS_from_the_video_vga_controller_0;
output [ 7: 0] VGA_R_from_the_video_vga_controller_0;
output VGA_SYNC_from_the_video_vga_controller_0;
output VGA_VS_from_the_video_vga_controller_0;
inout b_SD_cmd_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0;
inout b_SD_dat3_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0;
inout b_SD_dat_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0;
output clocks_SDRAM_CLK_out;
output clocks_sys_clk_out;
output o_SD_clock_from_the_Altera_UP_SD_Card_Avalon_Interface_0;
output [ 7: 0] out_port_from_the_output1;
output [ 12: 0] zs_addr_from_the_sdram_0;
output [ 1: 0] zs_ba_from_the_sdram_0;
output zs_cas_n_from_the_sdram_0;
output zs_cke_from_the_sdram_0;
output zs_cs_n_from_the_sdram_0;
inout [ 31: 0] zs_dq_to_and_from_the_sdram_0;
output [ 3: 0] zs_dqm_from_the_sdram_0;
output zs_ras_n_from_the_sdram_0;
output zs_we_n_from_the_sdram_0;
input clk_0;
input [ 7: 0] in_port_to_the_input1;
input reset_n;
input vga_clock;
wire [ 7: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address;
wire [ 3: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read;
wire [ 31: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata;
wire [ 31: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reset_n;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write;
wire [ 31: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata;
wire VGA_BLANK_from_the_video_vga_controller_0;
wire [ 7: 0] VGA_B_from_the_video_vga_controller_0;
wire VGA_CLK_from_the_video_vga_controller_0;
wire [ 7: 0] VGA_G_from_the_video_vga_controller_0;
wire VGA_HS_from_the_video_vga_controller_0;
wire [ 7: 0] VGA_R_from_the_video_vga_controller_0;
wire VGA_SYNC_from_the_video_vga_controller_0;
wire VGA_VS_from_the_video_vga_controller_0;
wire b_SD_cmd_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0;
wire b_SD_dat3_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0;
wire b_SD_dat_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0;
wire clk_0_reset_n;
wire clocks_SDRAM_CLK_out;
wire clocks_avalon_clocks_slave_address;
wire [ 7: 0] clocks_avalon_clocks_slave_readdata;
wire [ 7: 0] clocks_avalon_clocks_slave_readdata_from_sa;
wire clocks_sys_clk_out;
wire [ 27: 0] cpu_0_data_master_address;
wire [ 27: 0] cpu_0_data_master_address_to_slave;
wire [ 3: 0] cpu_0_data_master_byteenable;
wire cpu_0_data_master_byteenable_nios_system_clock_1_in;
wire [ 1: 0] cpu_0_data_master_dbs_address;
wire [ 7: 0] cpu_0_data_master_dbs_write_8;
wire cpu_0_data_master_debugaccess;
wire cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
wire cpu_0_data_master_granted_clocks_avalon_clocks_slave;
wire cpu_0_data_master_granted_cpu_0_jtag_debug_module;
wire cpu_0_data_master_granted_input1_s1;
wire cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave;
wire cpu_0_data_master_granted_nios_system_clock_0_in;
wire cpu_0_data_master_granted_nios_system_clock_1_in;
wire cpu_0_data_master_granted_onchip_memory2_0_s1;
wire cpu_0_data_master_granted_output1_s1;
wire cpu_0_data_master_granted_sdram_0_s1;
wire cpu_0_data_master_granted_sysid_control_slave;
wire [ 31: 0] cpu_0_data_master_irq;
wire cpu_0_data_master_no_byte_enables_and_last_term;
wire cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
wire cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave;
wire cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module;
wire cpu_0_data_master_qualified_request_input1_s1;
wire cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave;
wire cpu_0_data_master_qualified_request_nios_system_clock_0_in;
wire cpu_0_data_master_qualified_request_nios_system_clock_1_in;
wire cpu_0_data_master_qualified_request_onchip_memory2_0_s1;
wire cpu_0_data_master_qualified_request_output1_s1;
wire cpu_0_data_master_qualified_request_sdram_0_s1;
wire cpu_0_data_master_qualified_request_sysid_control_slave;
wire cpu_0_data_master_read;
wire cpu_0_data_master_read_data_valid_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
wire cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave;
wire cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module;
wire cpu_0_data_master_read_data_valid_input1_s1;
wire cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave;
wire cpu_0_data_master_read_data_valid_nios_system_clock_0_in;
wire cpu_0_data_master_read_data_valid_nios_system_clock_1_in;
wire cpu_0_data_master_read_data_valid_onchip_memory2_0_s1;
wire cpu_0_data_master_read_data_valid_output1_s1;
wire cpu_0_data_master_read_data_valid_sdram_0_s1;
wire cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register;
wire cpu_0_data_master_read_data_valid_sysid_control_slave;
wire [ 31: 0] cpu_0_data_master_readdata;
wire cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
wire cpu_0_data_master_requests_clocks_avalon_clocks_slave;
wire cpu_0_data_master_requests_cpu_0_jtag_debug_module;
wire cpu_0_data_master_requests_input1_s1;
wire cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave;
wire cpu_0_data_master_requests_nios_system_clock_0_in;
wire cpu_0_data_master_requests_nios_system_clock_1_in;
wire cpu_0_data_master_requests_onchip_memory2_0_s1;
wire cpu_0_data_master_requests_output1_s1;
wire cpu_0_data_master_requests_sdram_0_s1;
wire cpu_0_data_master_requests_sysid_control_slave;
wire cpu_0_data_master_waitrequest;
wire cpu_0_data_master_write;
wire [ 31: 0] cpu_0_data_master_writedata;
wire [ 27: 0] cpu_0_instruction_master_address;
wire [ 27: 0] cpu_0_instruction_master_address_to_slave;
wire cpu_0_instruction_master_granted_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_granted_onchip_memory2_0_s1;
wire cpu_0_instruction_master_granted_sdram_0_s1;
wire cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1;
wire cpu_0_instruction_master_qualified_request_sdram_0_s1;
wire cpu_0_instruction_master_read;
wire cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1;
wire cpu_0_instruction_master_read_data_valid_sdram_0_s1;
wire cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register;
wire [ 31: 0] cpu_0_instruction_master_readdata;
wire cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_requests_onchip_memory2_0_s1;
wire cpu_0_instruction_master_requests_sdram_0_s1;
wire cpu_0_instruction_master_waitrequest;
wire [ 8: 0] cpu_0_jtag_debug_module_address;
wire cpu_0_jtag_debug_module_begintransfer;
wire [ 3: 0] cpu_0_jtag_debug_module_byteenable;
wire cpu_0_jtag_debug_module_chipselect;
wire cpu_0_jtag_debug_module_debugaccess;
wire [ 31: 0] cpu_0_jtag_debug_module_readdata;
wire [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
wire cpu_0_jtag_debug_module_reset_n;
wire cpu_0_jtag_debug_module_resetrequest;
wire cpu_0_jtag_debug_module_resetrequest_from_sa;
wire cpu_0_jtag_debug_module_write;
wire [ 31: 0] cpu_0_jtag_debug_module_writedata;
wire d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer;
wire d1_clocks_avalon_clocks_slave_end_xfer;
wire d1_cpu_0_jtag_debug_module_end_xfer;
wire d1_input1_s1_end_xfer;
wire d1_jtag_uart_0_avalon_jtag_slave_end_xfer;
wire d1_nios_system_clock_0_in_end_xfer;
wire d1_nios_system_clock_1_in_end_xfer;
wire d1_onchip_memory2_0_s1_end_xfer;
wire d1_output1_s1_end_xfer;
wire d1_sdram_0_s1_end_xfer;
wire d1_sysid_control_slave_end_xfer;
wire d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer;
wire d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer;
wire [ 1: 0] input1_s1_address;
wire [ 31: 0] input1_s1_readdata;
wire [ 31: 0] input1_s1_readdata_from_sa;
wire input1_s1_reset_n;
wire jtag_uart_0_avalon_jtag_slave_address;
wire jtag_uart_0_avalon_jtag_slave_chipselect;
wire jtag_uart_0_avalon_jtag_slave_dataavailable;
wire jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa;
wire jtag_uart_0_avalon_jtag_slave_irq;
wire jtag_uart_0_avalon_jtag_slave_irq_from_sa;
wire jtag_uart_0_avalon_jtag_slave_read_n;
wire [ 31: 0] jtag_uart_0_avalon_jtag_slave_readdata;
wire [ 31: 0] jtag_uart_0_avalon_jtag_slave_readdata_from_sa;
wire jtag_uart_0_avalon_jtag_slave_readyfordata;
wire jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa;
wire jtag_uart_0_avalon_jtag_slave_reset_n;
wire jtag_uart_0_avalon_jtag_slave_waitrequest;
wire jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa;
wire jtag_uart_0_avalon_jtag_slave_write_n;
wire [ 31: 0] jtag_uart_0_avalon_jtag_slave_writedata;
wire [ 2: 0] nios_system_clock_0_in_address;
wire [ 3: 0] nios_system_clock_0_in_byteenable;
wire nios_system_clock_0_in_endofpacket;
wire nios_system_clock_0_in_endofpacket_from_sa;
wire nios_system_clock_0_in_nativeaddress;
wire nios_system_clock_0_in_read;
wire [ 31: 0] nios_system_clock_0_in_readdata;
wire [ 31: 0] nios_system_clock_0_in_readdata_from_sa;
wire nios_system_clock_0_in_reset_n;
wire nios_system_clock_0_in_waitrequest;
wire nios_system_clock_0_in_waitrequest_from_sa;
wire nios_system_clock_0_in_write;
wire [ 31: 0] nios_system_clock_0_in_writedata;
wire [ 2: 0] nios_system_clock_0_out_address;
wire [ 2: 0] nios_system_clock_0_out_address_to_slave;
wire [ 3: 0] nios_system_clock_0_out_byteenable;
wire nios_system_clock_0_out_endofpacket;
wire nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave;
wire nios_system_clock_0_out_nativeaddress;
wire nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave;
wire nios_system_clock_0_out_read;
wire nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave;
wire [ 31: 0] nios_system_clock_0_out_readdata;
wire nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave;
wire nios_system_clock_0_out_reset_n;
wire nios_system_clock_0_out_waitrequest;
wire nios_system_clock_0_out_write;
wire [ 31: 0] nios_system_clock_0_out_writedata;
wire [ 12: 0] nios_system_clock_1_in_address;
wire nios_system_clock_1_in_endofpacket;
wire nios_system_clock_1_in_endofpacket_from_sa;
wire [ 12: 0] nios_system_clock_1_in_nativeaddress;
wire nios_system_clock_1_in_read;
wire [ 7: 0] nios_system_clock_1_in_readdata;
wire [ 7: 0] nios_system_clock_1_in_readdata_from_sa;
wire nios_system_clock_1_in_reset_n;
wire nios_system_clock_1_in_waitrequest;
wire nios_system_clock_1_in_waitrequest_from_sa;
wire nios_system_clock_1_in_write;
wire [ 7: 0] nios_system_clock_1_in_writedata;
wire [ 12: 0] nios_system_clock_1_out_address;
wire [ 12: 0] nios_system_clock_1_out_address_to_slave;
wire nios_system_clock_1_out_endofpacket;
wire nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
wire [ 12: 0] nios_system_clock_1_out_nativeaddress;
wire nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
wire nios_system_clock_1_out_read;
wire nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
wire [ 7: 0] nios_system_clock_1_out_readdata;
wire nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
wire nios_system_clock_1_out_reset_n;
wire nios_system_clock_1_out_waitrequest;
wire nios_system_clock_1_out_write;
wire [ 7: 0] nios_system_clock_1_out_writedata;
wire o_SD_clock_from_the_Altera_UP_SD_Card_Avalon_Interface_0;
wire [ 11: 0] onchip_memory2_0_s1_address;
wire [ 3: 0] onchip_memory2_0_s1_byteenable;
wire onchip_memory2_0_s1_chipselect;
wire onchip_memory2_0_s1_clken;
wire [ 31: 0] onchip_memory2_0_s1_readdata;
wire [ 31: 0] onchip_memory2_0_s1_readdata_from_sa;
wire onchip_memory2_0_s1_reset;
wire onchip_memory2_0_s1_write;
wire [ 31: 0] onchip_memory2_0_s1_writedata;
wire out_clk_clocks_SDRAM_CLK;
wire out_clk_clocks_sys_clk;
wire [ 7: 0] out_port_from_the_output1;
wire [ 1: 0] output1_s1_address;
wire output1_s1_chipselect;
wire [ 31: 0] output1_s1_readdata;
wire [ 31: 0] output1_s1_readdata_from_sa;
wire output1_s1_reset_n;
wire output1_s1_write_n;
wire [ 31: 0] output1_s1_writedata;
wire registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave;
wire registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1;
wire reset_n_sources;
wire [ 24: 0] sdram_0_s1_address;
wire [ 3: 0] sdram_0_s1_byteenable_n;
wire sdram_0_s1_chipselect;
wire sdram_0_s1_read_n;
wire [ 31: 0] sdram_0_s1_readdata;
wire [ 31: 0] sdram_0_s1_readdata_from_sa;
wire sdram_0_s1_readdatavalid;
wire sdram_0_s1_reset_n;
wire sdram_0_s1_waitrequest;
wire sdram_0_s1_waitrequest_from_sa;
wire sdram_0_s1_write_n;
wire [ 31: 0] sdram_0_s1_writedata;
wire sysid_control_slave_address;
wire sysid_control_slave_clock;
wire [ 31: 0] sysid_control_slave_readdata;
wire [ 31: 0] sysid_control_slave_readdata_from_sa;
wire sysid_control_slave_reset_n;
wire vga_clock_reset_n;
wire [ 12: 0] video_character_buffer_with_dma_0_avalon_char_buffer_slave_address;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_byteenable;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_chipselect;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_read;
wire [ 7: 0] video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata;
wire [ 7: 0] video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_write;
wire [ 7: 0] video_character_buffer_with_dma_0_avalon_char_buffer_slave_writedata;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_address;
wire [ 3: 0] video_character_buffer_with_dma_0_avalon_char_control_slave_byteenable;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_chipselect;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_read;
wire [ 31: 0] video_character_buffer_with_dma_0_avalon_char_control_slave_readdata;
wire [ 31: 0] video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_reset;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_write;
wire [ 31: 0] video_character_buffer_with_dma_0_avalon_char_control_slave_writedata;
wire [ 29: 0] video_character_buffer_with_dma_0_avalon_char_source_data;
wire video_character_buffer_with_dma_0_avalon_char_source_endofpacket;
wire video_character_buffer_with_dma_0_avalon_char_source_ready;
wire video_character_buffer_with_dma_0_avalon_char_source_startofpacket;
wire video_character_buffer_with_dma_0_avalon_char_source_valid;
wire [ 29: 0] video_vga_controller_0_avalon_vga_sink_data;
wire video_vga_controller_0_avalon_vga_sink_endofpacket;
wire video_vga_controller_0_avalon_vga_sink_ready;
wire video_vga_controller_0_avalon_vga_sink_ready_from_sa;
wire video_vga_controller_0_avalon_vga_sink_reset;
wire video_vga_controller_0_avalon_vga_sink_startofpacket;
wire video_vga_controller_0_avalon_vga_sink_valid;
wire [ 12: 0] zs_addr_from_the_sdram_0;
wire [ 1: 0] zs_ba_from_the_sdram_0;
wire zs_cas_n_from_the_sdram_0;
wire zs_cke_from_the_sdram_0;
wire zs_cs_n_from_the_sdram_0;
wire [ 31: 0] zs_dq_to_and_from_the_sdram_0;
wire [ 3: 0] zs_dqm_from_the_sdram_0;
wire zs_ras_n_from_the_sdram_0;
wire zs_we_n_from_the_sdram_0;
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arbitrator the_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave
(
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address),
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable),
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect),
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read),
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata),
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa),
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reset_n (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reset_n),
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest),
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa),
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write),
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata),
.clk (clk_0),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_byteenable (cpu_0_data_master_byteenable),
.cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave (cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave),
.cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave (cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave (cpu_0_data_master_read_data_valid_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave),
.cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave (cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave),
.cpu_0_data_master_waitrequest (cpu_0_data_master_waitrequest),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer (d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer),
.reset_n (clk_0_reset_n)
);
Altera_UP_SD_Card_Avalon_Interface_0 the_Altera_UP_SD_Card_Avalon_Interface_0
(
.b_SD_cmd (b_SD_cmd_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0),
.b_SD_dat (b_SD_dat_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0),
.b_SD_dat3 (b_SD_dat3_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0),
.i_avalon_address (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address),
.i_avalon_byteenable (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable),
.i_avalon_chip_select (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect),
.i_avalon_read (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read),
.i_avalon_write (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write),
.i_avalon_writedata (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata),
.i_clock (clk_0),
.i_reset_n (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reset_n),
.o_SD_clock (o_SD_clock_from_the_Altera_UP_SD_Card_Avalon_Interface_0),
.o_avalon_readdata (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata),
.o_avalon_waitrequest (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest)
);
clocks_avalon_clocks_slave_arbitrator the_clocks_avalon_clocks_slave
(
.clk (clk_0),
.clocks_avalon_clocks_slave_address (clocks_avalon_clocks_slave_address),
.clocks_avalon_clocks_slave_readdata (clocks_avalon_clocks_slave_readdata),
.clocks_avalon_clocks_slave_readdata_from_sa (clocks_avalon_clocks_slave_readdata_from_sa),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_dbs_address (cpu_0_data_master_dbs_address),
.cpu_0_data_master_granted_clocks_avalon_clocks_slave (cpu_0_data_master_granted_clocks_avalon_clocks_slave),
.cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave (cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave (cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave),
.cpu_0_data_master_requests_clocks_avalon_clocks_slave (cpu_0_data_master_requests_clocks_avalon_clocks_slave),
.cpu_0_data_master_write (cpu_0_data_master_write),
.d1_clocks_avalon_clocks_slave_end_xfer (d1_clocks_avalon_clocks_slave_end_xfer),
.registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave (registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave),
.reset_n (clk_0_reset_n)
);
//clocks_SDRAM_CLK_out out_clk assignment, which is an e_assign
assign clocks_SDRAM_CLK_out = out_clk_clocks_SDRAM_CLK;
//clocks_sys_clk_out out_clk assignment, which is an e_assign
assign clocks_sys_clk_out = out_clk_clocks_sys_clk;
clocks the_clocks
(
.CLOCK_50 (clk_0),
.SDRAM_CLK (out_clk_clocks_SDRAM_CLK),
.address (clocks_avalon_clocks_slave_address),
.readdata (clocks_avalon_clocks_slave_readdata),
.sys_clk (out_clk_clocks_sys_clk)
);
cpu_0_jtag_debug_module_arbitrator the_cpu_0_jtag_debug_module
(
.clk (clk_0),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_byteenable (cpu_0_data_master_byteenable),
.cpu_0_data_master_debugaccess (cpu_0_data_master_debugaccess),
.cpu_0_data_master_granted_cpu_0_jtag_debug_module (cpu_0_data_master_granted_cpu_0_jtag_debug_module),
.cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module (cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module (cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module),
.cpu_0_data_master_requests_cpu_0_jtag_debug_module (cpu_0_data_master_requests_cpu_0_jtag_debug_module),
.cpu_0_data_master_waitrequest (cpu_0_data_master_waitrequest),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.cpu_0_instruction_master_address_to_slave (cpu_0_instruction_master_address_to_slave),
.cpu_0_instruction_master_granted_cpu_0_jtag_debug_module (cpu_0_instruction_master_granted_cpu_0_jtag_debug_module),
.cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module (cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module),
.cpu_0_instruction_master_read (cpu_0_instruction_master_read),
.cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module (cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module),
.cpu_0_instruction_master_requests_cpu_0_jtag_debug_module (cpu_0_instruction_master_requests_cpu_0_jtag_debug_module),
.cpu_0_jtag_debug_module_address (cpu_0_jtag_debug_module_address),
.cpu_0_jtag_debug_module_begintransfer (cpu_0_jtag_debug_module_begintransfer),
.cpu_0_jtag_debug_module_byteenable (cpu_0_jtag_debug_module_byteenable),
.cpu_0_jtag_debug_module_chipselect (cpu_0_jtag_debug_module_chipselect),
.cpu_0_jtag_debug_module_debugaccess (cpu_0_jtag_debug_module_debugaccess),
.cpu_0_jtag_debug_module_readdata (cpu_0_jtag_debug_module_readdata),
.cpu_0_jtag_debug_module_readdata_from_sa (cpu_0_jtag_debug_module_readdata_from_sa),
.cpu_0_jtag_debug_module_reset_n (cpu_0_jtag_debug_module_reset_n),
.cpu_0_jtag_debug_module_resetrequest (cpu_0_jtag_debug_module_resetrequest),
.cpu_0_jtag_debug_module_resetrequest_from_sa (cpu_0_jtag_debug_module_resetrequest_from_sa),
.cpu_0_jtag_debug_module_write (cpu_0_jtag_debug_module_write),
.cpu_0_jtag_debug_module_writedata (cpu_0_jtag_debug_module_writedata),
.d1_cpu_0_jtag_debug_module_end_xfer (d1_cpu_0_jtag_debug_module_end_xfer),
.reset_n (clk_0_reset_n)
);
cpu_0_data_master_arbitrator the_cpu_0_data_master
(
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa),
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa),
.clk (clk_0),
.clocks_avalon_clocks_slave_readdata_from_sa (clocks_avalon_clocks_slave_readdata_from_sa),
.cpu_0_data_master_address (cpu_0_data_master_address),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_byteenable_nios_system_clock_1_in (cpu_0_data_master_byteenable_nios_system_clock_1_in),
.cpu_0_data_master_dbs_address (cpu_0_data_master_dbs_address),
.cpu_0_data_master_dbs_write_8 (cpu_0_data_master_dbs_write_8),
.cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave (cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave),
.cpu_0_data_master_granted_clocks_avalon_clocks_slave (cpu_0_data_master_granted_clocks_avalon_clocks_slave),
.cpu_0_data_master_granted_cpu_0_jtag_debug_module (cpu_0_data_master_granted_cpu_0_jtag_debug_module),
.cpu_0_data_master_granted_input1_s1 (cpu_0_data_master_granted_input1_s1),
.cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave (cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave),
.cpu_0_data_master_granted_nios_system_clock_0_in (cpu_0_data_master_granted_nios_system_clock_0_in),
.cpu_0_data_master_granted_nios_system_clock_1_in (cpu_0_data_master_granted_nios_system_clock_1_in),
.cpu_0_data_master_granted_onchip_memory2_0_s1 (cpu_0_data_master_granted_onchip_memory2_0_s1),
.cpu_0_data_master_granted_output1_s1 (cpu_0_data_master_granted_output1_s1),
.cpu_0_data_master_granted_sdram_0_s1 (cpu_0_data_master_granted_sdram_0_s1),
.cpu_0_data_master_granted_sysid_control_slave (cpu_0_data_master_granted_sysid_control_slave),
.cpu_0_data_master_irq (cpu_0_data_master_irq),
.cpu_0_data_master_no_byte_enables_and_last_term (cpu_0_data_master_no_byte_enables_and_last_term),
.cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave (cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave),
.cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave (cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave),
.cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module (cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module),
.cpu_0_data_master_qualified_request_input1_s1 (cpu_0_data_master_qualified_request_input1_s1),
.cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave (cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave),
.cpu_0_data_master_qualified_request_nios_system_clock_0_in (cpu_0_data_master_qualified_request_nios_system_clock_0_in),
.cpu_0_data_master_qualified_request_nios_system_clock_1_in (cpu_0_data_master_qualified_request_nios_system_clock_1_in),
.cpu_0_data_master_qualified_request_onchip_memory2_0_s1 (cpu_0_data_master_qualified_request_onchip_memory2_0_s1),
.cpu_0_data_master_qualified_request_output1_s1 (cpu_0_data_master_qualified_request_output1_s1),
.cpu_0_data_master_qualified_request_sdram_0_s1 (cpu_0_data_master_qualified_request_sdram_0_s1),
.cpu_0_data_master_qualified_request_sysid_control_slave (cpu_0_data_master_qualified_request_sysid_control_slave),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave (cpu_0_data_master_read_data_valid_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave),
.cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave (cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave),
.cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module (cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module),
.cpu_0_data_master_read_data_valid_input1_s1 (cpu_0_data_master_read_data_valid_input1_s1),
.cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave (cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave),
.cpu_0_data_master_read_data_valid_nios_system_clock_0_in (cpu_0_data_master_read_data_valid_nios_system_clock_0_in),
.cpu_0_data_master_read_data_valid_nios_system_clock_1_in (cpu_0_data_master_read_data_valid_nios_system_clock_1_in),
.cpu_0_data_master_read_data_valid_onchip_memory2_0_s1 (cpu_0_data_master_read_data_valid_onchip_memory2_0_s1),
.cpu_0_data_master_read_data_valid_output1_s1 (cpu_0_data_master_read_data_valid_output1_s1),
.cpu_0_data_master_read_data_valid_sdram_0_s1 (cpu_0_data_master_read_data_valid_sdram_0_s1),
.cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register (cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register),
.cpu_0_data_master_read_data_valid_sysid_control_slave (cpu_0_data_master_read_data_valid_sysid_control_slave),
.cpu_0_data_master_readdata (cpu_0_data_master_readdata),
.cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave (cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave),
.cpu_0_data_master_requests_clocks_avalon_clocks_slave (cpu_0_data_master_requests_clocks_avalon_clocks_slave),
.cpu_0_data_master_requests_cpu_0_jtag_debug_module (cpu_0_data_master_requests_cpu_0_jtag_debug_module),
.cpu_0_data_master_requests_input1_s1 (cpu_0_data_master_requests_input1_s1),
.cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave (cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave),
.cpu_0_data_master_requests_nios_system_clock_0_in (cpu_0_data_master_requests_nios_system_clock_0_in),
.cpu_0_data_master_requests_nios_system_clock_1_in (cpu_0_data_master_requests_nios_system_clock_1_in),
.cpu_0_data_master_requests_onchip_memory2_0_s1 (cpu_0_data_master_requests_onchip_memory2_0_s1),
.cpu_0_data_master_requests_output1_s1 (cpu_0_data_master_requests_output1_s1),
.cpu_0_data_master_requests_sdram_0_s1 (cpu_0_data_master_requests_sdram_0_s1),
.cpu_0_data_master_requests_sysid_control_slave (cpu_0_data_master_requests_sysid_control_slave),
.cpu_0_data_master_waitrequest (cpu_0_data_master_waitrequest),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.cpu_0_jtag_debug_module_readdata_from_sa (cpu_0_jtag_debug_module_readdata_from_sa),
.d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer (d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer),
.d1_clocks_avalon_clocks_slave_end_xfer (d1_clocks_avalon_clocks_slave_end_xfer),
.d1_cpu_0_jtag_debug_module_end_xfer (d1_cpu_0_jtag_debug_module_end_xfer),
.d1_input1_s1_end_xfer (d1_input1_s1_end_xfer),
.d1_jtag_uart_0_avalon_jtag_slave_end_xfer (d1_jtag_uart_0_avalon_jtag_slave_end_xfer),
.d1_nios_system_clock_0_in_end_xfer (d1_nios_system_clock_0_in_end_xfer),
.d1_nios_system_clock_1_in_end_xfer (d1_nios_system_clock_1_in_end_xfer),
.d1_onchip_memory2_0_s1_end_xfer (d1_onchip_memory2_0_s1_end_xfer),
.d1_output1_s1_end_xfer (d1_output1_s1_end_xfer),
.d1_sdram_0_s1_end_xfer (d1_sdram_0_s1_end_xfer),
.d1_sysid_control_slave_end_xfer (d1_sysid_control_slave_end_xfer),
.input1_s1_readdata_from_sa (input1_s1_readdata_from_sa),
.jtag_uart_0_avalon_jtag_slave_irq_from_sa (jtag_uart_0_avalon_jtag_slave_irq_from_sa),
.jtag_uart_0_avalon_jtag_slave_readdata_from_sa (jtag_uart_0_avalon_jtag_slave_readdata_from_sa),
.jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa (jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa),
.nios_system_clock_0_in_readdata_from_sa (nios_system_clock_0_in_readdata_from_sa),
.nios_system_clock_0_in_waitrequest_from_sa (nios_system_clock_0_in_waitrequest_from_sa),
.nios_system_clock_1_in_readdata_from_sa (nios_system_clock_1_in_readdata_from_sa),
.nios_system_clock_1_in_waitrequest_from_sa (nios_system_clock_1_in_waitrequest_from_sa),
.onchip_memory2_0_s1_readdata_from_sa (onchip_memory2_0_s1_readdata_from_sa),
.output1_s1_readdata_from_sa (output1_s1_readdata_from_sa),
.registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave (registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave),
.registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1 (registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1),
.reset_n (clk_0_reset_n),
.sdram_0_s1_readdata_from_sa (sdram_0_s1_readdata_from_sa),
.sdram_0_s1_waitrequest_from_sa (sdram_0_s1_waitrequest_from_sa),
.sysid_control_slave_readdata_from_sa (sysid_control_slave_readdata_from_sa)
);
cpu_0_instruction_master_arbitrator the_cpu_0_instruction_master
(
.clk (clk_0),
.cpu_0_instruction_master_address (cpu_0_instruction_master_address),
.cpu_0_instruction_master_address_to_slave (cpu_0_instruction_master_address_to_slave),
.cpu_0_instruction_master_granted_cpu_0_jtag_debug_module (cpu_0_instruction_master_granted_cpu_0_jtag_debug_module),
.cpu_0_instruction_master_granted_onchip_memory2_0_s1 (cpu_0_instruction_master_granted_onchip_memory2_0_s1),
.cpu_0_instruction_master_granted_sdram_0_s1 (cpu_0_instruction_master_granted_sdram_0_s1),
.cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module (cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module),
.cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1 (cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1),
.cpu_0_instruction_master_qualified_request_sdram_0_s1 (cpu_0_instruction_master_qualified_request_sdram_0_s1),
.cpu_0_instruction_master_read (cpu_0_instruction_master_read),
.cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module (cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module),
.cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1 (cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1),
.cpu_0_instruction_master_read_data_valid_sdram_0_s1 (cpu_0_instruction_master_read_data_valid_sdram_0_s1),
.cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register (cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register),
.cpu_0_instruction_master_readdata (cpu_0_instruction_master_readdata),
.cpu_0_instruction_master_requests_cpu_0_jtag_debug_module (cpu_0_instruction_master_requests_cpu_0_jtag_debug_module),
.cpu_0_instruction_master_requests_onchip_memory2_0_s1 (cpu_0_instruction_master_requests_onchip_memory2_0_s1),
.cpu_0_instruction_master_requests_sdram_0_s1 (cpu_0_instruction_master_requests_sdram_0_s1),
.cpu_0_instruction_master_waitrequest (cpu_0_instruction_master_waitrequest),
.cpu_0_jtag_debug_module_readdata_from_sa (cpu_0_jtag_debug_module_readdata_from_sa),
.d1_cpu_0_jtag_debug_module_end_xfer (d1_cpu_0_jtag_debug_module_end_xfer),
.d1_onchip_memory2_0_s1_end_xfer (d1_onchip_memory2_0_s1_end_xfer),
.d1_sdram_0_s1_end_xfer (d1_sdram_0_s1_end_xfer),
.onchip_memory2_0_s1_readdata_from_sa (onchip_memory2_0_s1_readdata_from_sa),
.reset_n (clk_0_reset_n),
.sdram_0_s1_readdata_from_sa (sdram_0_s1_readdata_from_sa),
.sdram_0_s1_waitrequest_from_sa (sdram_0_s1_waitrequest_from_sa)
);
cpu_0 the_cpu_0
(
.clk (clk_0),
.d_address (cpu_0_data_master_address),
.d_byteenable (cpu_0_data_master_byteenable),
.d_irq (cpu_0_data_master_irq),
.d_read (cpu_0_data_master_read),
.d_readdata (cpu_0_data_master_readdata),
.d_waitrequest (cpu_0_data_master_waitrequest),
.d_write (cpu_0_data_master_write),
.d_writedata (cpu_0_data_master_writedata),
.i_address (cpu_0_instruction_master_address),
.i_read (cpu_0_instruction_master_read),
.i_readdata (cpu_0_instruction_master_readdata),
.i_waitrequest (cpu_0_instruction_master_waitrequest),
.jtag_debug_module_address (cpu_0_jtag_debug_module_address),
.jtag_debug_module_begintransfer (cpu_0_jtag_debug_module_begintransfer),
.jtag_debug_module_byteenable (cpu_0_jtag_debug_module_byteenable),
.jtag_debug_module_debugaccess (cpu_0_jtag_debug_module_debugaccess),
.jtag_debug_module_debugaccess_to_roms (cpu_0_data_master_debugaccess),
.jtag_debug_module_readdata (cpu_0_jtag_debug_module_readdata),
.jtag_debug_module_resetrequest (cpu_0_jtag_debug_module_resetrequest),
.jtag_debug_module_select (cpu_0_jtag_debug_module_chipselect),
.jtag_debug_module_write (cpu_0_jtag_debug_module_write),
.jtag_debug_module_writedata (cpu_0_jtag_debug_module_writedata),
.reset_n (cpu_0_jtag_debug_module_reset_n)
);
input1_s1_arbitrator the_input1_s1
(
.clk (clk_0),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_granted_input1_s1 (cpu_0_data_master_granted_input1_s1),
.cpu_0_data_master_qualified_request_input1_s1 (cpu_0_data_master_qualified_request_input1_s1),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_input1_s1 (cpu_0_data_master_read_data_valid_input1_s1),
.cpu_0_data_master_requests_input1_s1 (cpu_0_data_master_requests_input1_s1),
.cpu_0_data_master_write (cpu_0_data_master_write),
.d1_input1_s1_end_xfer (d1_input1_s1_end_xfer),
.input1_s1_address (input1_s1_address),
.input1_s1_readdata (input1_s1_readdata),
.input1_s1_readdata_from_sa (input1_s1_readdata_from_sa),
.input1_s1_reset_n (input1_s1_reset_n),
.reset_n (clk_0_reset_n)
);
input1 the_input1
(
.address (input1_s1_address),
.clk (clk_0),
.in_port (in_port_to_the_input1),
.readdata (input1_s1_readdata),
.reset_n (input1_s1_reset_n)
);
jtag_uart_0_avalon_jtag_slave_arbitrator the_jtag_uart_0_avalon_jtag_slave
(
.clk (clk_0),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave (cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave),
.cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave (cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave (cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave),
.cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave (cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave),
.cpu_0_data_master_waitrequest (cpu_0_data_master_waitrequest),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.d1_jtag_uart_0_avalon_jtag_slave_end_xfer (d1_jtag_uart_0_avalon_jtag_slave_end_xfer),
.jtag_uart_0_avalon_jtag_slave_address (jtag_uart_0_avalon_jtag_slave_address),
.jtag_uart_0_avalon_jtag_slave_chipselect (jtag_uart_0_avalon_jtag_slave_chipselect),
.jtag_uart_0_avalon_jtag_slave_dataavailable (jtag_uart_0_avalon_jtag_slave_dataavailable),
.jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa (jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa),
.jtag_uart_0_avalon_jtag_slave_irq (jtag_uart_0_avalon_jtag_slave_irq),
.jtag_uart_0_avalon_jtag_slave_irq_from_sa (jtag_uart_0_avalon_jtag_slave_irq_from_sa),
.jtag_uart_0_avalon_jtag_slave_read_n (jtag_uart_0_avalon_jtag_slave_read_n),
.jtag_uart_0_avalon_jtag_slave_readdata (jtag_uart_0_avalon_jtag_slave_readdata),
.jtag_uart_0_avalon_jtag_slave_readdata_from_sa (jtag_uart_0_avalon_jtag_slave_readdata_from_sa),
.jtag_uart_0_avalon_jtag_slave_readyfordata (jtag_uart_0_avalon_jtag_slave_readyfordata),
.jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa (jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa),
.jtag_uart_0_avalon_jtag_slave_reset_n (jtag_uart_0_avalon_jtag_slave_reset_n),
.jtag_uart_0_avalon_jtag_slave_waitrequest (jtag_uart_0_avalon_jtag_slave_waitrequest),
.jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa (jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa),
.jtag_uart_0_avalon_jtag_slave_write_n (jtag_uart_0_avalon_jtag_slave_write_n),
.jtag_uart_0_avalon_jtag_slave_writedata (jtag_uart_0_avalon_jtag_slave_writedata),
.reset_n (clk_0_reset_n)
);
jtag_uart_0 the_jtag_uart_0
(
.av_address (jtag_uart_0_avalon_jtag_slave_address),
.av_chipselect (jtag_uart_0_avalon_jtag_slave_chipselect),
.av_irq (jtag_uart_0_avalon_jtag_slave_irq),
.av_read_n (jtag_uart_0_avalon_jtag_slave_read_n),
.av_readdata (jtag_uart_0_avalon_jtag_slave_readdata),
.av_waitrequest (jtag_uart_0_avalon_jtag_slave_waitrequest),
.av_write_n (jtag_uart_0_avalon_jtag_slave_write_n),
.av_writedata (jtag_uart_0_avalon_jtag_slave_writedata),
.clk (clk_0),
.dataavailable (jtag_uart_0_avalon_jtag_slave_dataavailable),
.readyfordata (jtag_uart_0_avalon_jtag_slave_readyfordata),
.rst_n (jtag_uart_0_avalon_jtag_slave_reset_n)
);
nios_system_clock_0_in_arbitrator the_nios_system_clock_0_in
(
.clk (clk_0),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_byteenable (cpu_0_data_master_byteenable),
.cpu_0_data_master_granted_nios_system_clock_0_in (cpu_0_data_master_granted_nios_system_clock_0_in),
.cpu_0_data_master_qualified_request_nios_system_clock_0_in (cpu_0_data_master_qualified_request_nios_system_clock_0_in),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_nios_system_clock_0_in (cpu_0_data_master_read_data_valid_nios_system_clock_0_in),
.cpu_0_data_master_requests_nios_system_clock_0_in (cpu_0_data_master_requests_nios_system_clock_0_in),
.cpu_0_data_master_waitrequest (cpu_0_data_master_waitrequest),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.d1_nios_system_clock_0_in_end_xfer (d1_nios_system_clock_0_in_end_xfer),
.nios_system_clock_0_in_address (nios_system_clock_0_in_address),
.nios_system_clock_0_in_byteenable (nios_system_clock_0_in_byteenable),
.nios_system_clock_0_in_endofpacket (nios_system_clock_0_in_endofpacket),
.nios_system_clock_0_in_endofpacket_from_sa (nios_system_clock_0_in_endofpacket_from_sa),
.nios_system_clock_0_in_nativeaddress (nios_system_clock_0_in_nativeaddress),
.nios_system_clock_0_in_read (nios_system_clock_0_in_read),
.nios_system_clock_0_in_readdata (nios_system_clock_0_in_readdata),
.nios_system_clock_0_in_readdata_from_sa (nios_system_clock_0_in_readdata_from_sa),
.nios_system_clock_0_in_reset_n (nios_system_clock_0_in_reset_n),
.nios_system_clock_0_in_waitrequest (nios_system_clock_0_in_waitrequest),
.nios_system_clock_0_in_waitrequest_from_sa (nios_system_clock_0_in_waitrequest_from_sa),
.nios_system_clock_0_in_write (nios_system_clock_0_in_write),
.nios_system_clock_0_in_writedata (nios_system_clock_0_in_writedata),
.reset_n (clk_0_reset_n)
);
nios_system_clock_0_out_arbitrator the_nios_system_clock_0_out
(
.clk (vga_clock),
.d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer (d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer),
.nios_system_clock_0_out_address (nios_system_clock_0_out_address),
.nios_system_clock_0_out_address_to_slave (nios_system_clock_0_out_address_to_slave),
.nios_system_clock_0_out_byteenable (nios_system_clock_0_out_byteenable),
.nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave (nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave),
.nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave (nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave),
.nios_system_clock_0_out_read (nios_system_clock_0_out_read),
.nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave (nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave),
.nios_system_clock_0_out_readdata (nios_system_clock_0_out_readdata),
.nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave (nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave),
.nios_system_clock_0_out_reset_n (nios_system_clock_0_out_reset_n),
.nios_system_clock_0_out_waitrequest (nios_system_clock_0_out_waitrequest),
.nios_system_clock_0_out_write (nios_system_clock_0_out_write),
.nios_system_clock_0_out_writedata (nios_system_clock_0_out_writedata),
.reset_n (vga_clock_reset_n),
.video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa (video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa)
);
nios_system_clock_0 the_nios_system_clock_0
(
.master_address (nios_system_clock_0_out_address),
.master_byteenable (nios_system_clock_0_out_byteenable),
.master_clk (vga_clock),
.master_endofpacket (nios_system_clock_0_out_endofpacket),
.master_nativeaddress (nios_system_clock_0_out_nativeaddress),
.master_read (nios_system_clock_0_out_read),
.master_readdata (nios_system_clock_0_out_readdata),
.master_reset_n (nios_system_clock_0_out_reset_n),
.master_waitrequest (nios_system_clock_0_out_waitrequest),
.master_write (nios_system_clock_0_out_write),
.master_writedata (nios_system_clock_0_out_writedata),
.slave_address (nios_system_clock_0_in_address),
.slave_byteenable (nios_system_clock_0_in_byteenable),
.slave_clk (clk_0),
.slave_endofpacket (nios_system_clock_0_in_endofpacket),
.slave_nativeaddress (nios_system_clock_0_in_nativeaddress),
.slave_read (nios_system_clock_0_in_read),
.slave_readdata (nios_system_clock_0_in_readdata),
.slave_reset_n (nios_system_clock_0_in_reset_n),
.slave_waitrequest (nios_system_clock_0_in_waitrequest),
.slave_write (nios_system_clock_0_in_write),
.slave_writedata (nios_system_clock_0_in_writedata)
);
nios_system_clock_1_in_arbitrator the_nios_system_clock_1_in
(
.clk (clk_0),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_byteenable (cpu_0_data_master_byteenable),
.cpu_0_data_master_byteenable_nios_system_clock_1_in (cpu_0_data_master_byteenable_nios_system_clock_1_in),
.cpu_0_data_master_dbs_address (cpu_0_data_master_dbs_address),
.cpu_0_data_master_dbs_write_8 (cpu_0_data_master_dbs_write_8),
.cpu_0_data_master_granted_nios_system_clock_1_in (cpu_0_data_master_granted_nios_system_clock_1_in),
.cpu_0_data_master_no_byte_enables_and_last_term (cpu_0_data_master_no_byte_enables_and_last_term),
.cpu_0_data_master_qualified_request_nios_system_clock_1_in (cpu_0_data_master_qualified_request_nios_system_clock_1_in),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_nios_system_clock_1_in (cpu_0_data_master_read_data_valid_nios_system_clock_1_in),
.cpu_0_data_master_requests_nios_system_clock_1_in (cpu_0_data_master_requests_nios_system_clock_1_in),
.cpu_0_data_master_waitrequest (cpu_0_data_master_waitrequest),
.cpu_0_data_master_write (cpu_0_data_master_write),
.d1_nios_system_clock_1_in_end_xfer (d1_nios_system_clock_1_in_end_xfer),
.nios_system_clock_1_in_address (nios_system_clock_1_in_address),
.nios_system_clock_1_in_endofpacket (nios_system_clock_1_in_endofpacket),
.nios_system_clock_1_in_endofpacket_from_sa (nios_system_clock_1_in_endofpacket_from_sa),
.nios_system_clock_1_in_nativeaddress (nios_system_clock_1_in_nativeaddress),
.nios_system_clock_1_in_read (nios_system_clock_1_in_read),
.nios_system_clock_1_in_readdata (nios_system_clock_1_in_readdata),
.nios_system_clock_1_in_readdata_from_sa (nios_system_clock_1_in_readdata_from_sa),
.nios_system_clock_1_in_reset_n (nios_system_clock_1_in_reset_n),
.nios_system_clock_1_in_waitrequest (nios_system_clock_1_in_waitrequest),
.nios_system_clock_1_in_waitrequest_from_sa (nios_system_clock_1_in_waitrequest_from_sa),
.nios_system_clock_1_in_write (nios_system_clock_1_in_write),
.nios_system_clock_1_in_writedata (nios_system_clock_1_in_writedata),
.reset_n (clk_0_reset_n)
);
nios_system_clock_1_out_arbitrator the_nios_system_clock_1_out
(
.clk (vga_clock),
.d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer (d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer),
.nios_system_clock_1_out_address (nios_system_clock_1_out_address),
.nios_system_clock_1_out_address_to_slave (nios_system_clock_1_out_address_to_slave),
.nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave (nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave),
.nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave (nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave),
.nios_system_clock_1_out_read (nios_system_clock_1_out_read),
.nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave (nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave),
.nios_system_clock_1_out_readdata (nios_system_clock_1_out_readdata),
.nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave (nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave),
.nios_system_clock_1_out_reset_n (nios_system_clock_1_out_reset_n),
.nios_system_clock_1_out_waitrequest (nios_system_clock_1_out_waitrequest),
.nios_system_clock_1_out_write (nios_system_clock_1_out_write),
.nios_system_clock_1_out_writedata (nios_system_clock_1_out_writedata),
.reset_n (vga_clock_reset_n),
.video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa (video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa),
.video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa (video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa)
);
nios_system_clock_1 the_nios_system_clock_1
(
.master_address (nios_system_clock_1_out_address),
.master_clk (vga_clock),
.master_endofpacket (nios_system_clock_1_out_endofpacket),
.master_nativeaddress (nios_system_clock_1_out_nativeaddress),
.master_read (nios_system_clock_1_out_read),
.master_readdata (nios_system_clock_1_out_readdata),
.master_reset_n (nios_system_clock_1_out_reset_n),
.master_waitrequest (nios_system_clock_1_out_waitrequest),
.master_write (nios_system_clock_1_out_write),
.master_writedata (nios_system_clock_1_out_writedata),
.slave_address (nios_system_clock_1_in_address),
.slave_clk (clk_0),
.slave_endofpacket (nios_system_clock_1_in_endofpacket),
.slave_nativeaddress (nios_system_clock_1_in_nativeaddress),
.slave_read (nios_system_clock_1_in_read),
.slave_readdata (nios_system_clock_1_in_readdata),
.slave_reset_n (nios_system_clock_1_in_reset_n),
.slave_waitrequest (nios_system_clock_1_in_waitrequest),
.slave_write (nios_system_clock_1_in_write),
.slave_writedata (nios_system_clock_1_in_writedata)
);
onchip_memory2_0_s1_arbitrator the_onchip_memory2_0_s1
(
.clk (clk_0),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_byteenable (cpu_0_data_master_byteenable),
.cpu_0_data_master_granted_onchip_memory2_0_s1 (cpu_0_data_master_granted_onchip_memory2_0_s1),
.cpu_0_data_master_qualified_request_onchip_memory2_0_s1 (cpu_0_data_master_qualified_request_onchip_memory2_0_s1),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_onchip_memory2_0_s1 (cpu_0_data_master_read_data_valid_onchip_memory2_0_s1),
.cpu_0_data_master_requests_onchip_memory2_0_s1 (cpu_0_data_master_requests_onchip_memory2_0_s1),
.cpu_0_data_master_waitrequest (cpu_0_data_master_waitrequest),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.cpu_0_instruction_master_address_to_slave (cpu_0_instruction_master_address_to_slave),
.cpu_0_instruction_master_granted_onchip_memory2_0_s1 (cpu_0_instruction_master_granted_onchip_memory2_0_s1),
.cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1 (cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1),
.cpu_0_instruction_master_read (cpu_0_instruction_master_read),
.cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1 (cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1),
.cpu_0_instruction_master_requests_onchip_memory2_0_s1 (cpu_0_instruction_master_requests_onchip_memory2_0_s1),
.d1_onchip_memory2_0_s1_end_xfer (d1_onchip_memory2_0_s1_end_xfer),
.onchip_memory2_0_s1_address (onchip_memory2_0_s1_address),
.onchip_memory2_0_s1_byteenable (onchip_memory2_0_s1_byteenable),
.onchip_memory2_0_s1_chipselect (onchip_memory2_0_s1_chipselect),
.onchip_memory2_0_s1_clken (onchip_memory2_0_s1_clken),
.onchip_memory2_0_s1_readdata (onchip_memory2_0_s1_readdata),
.onchip_memory2_0_s1_readdata_from_sa (onchip_memory2_0_s1_readdata_from_sa),
.onchip_memory2_0_s1_reset (onchip_memory2_0_s1_reset),
.onchip_memory2_0_s1_write (onchip_memory2_0_s1_write),
.onchip_memory2_0_s1_writedata (onchip_memory2_0_s1_writedata),
.registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1 (registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1),
.reset_n (clk_0_reset_n)
);
onchip_memory2_0 the_onchip_memory2_0
(
.address (onchip_memory2_0_s1_address),
.byteenable (onchip_memory2_0_s1_byteenable),
.chipselect (onchip_memory2_0_s1_chipselect),
.clk (clk_0),
.clken (onchip_memory2_0_s1_clken),
.readdata (onchip_memory2_0_s1_readdata),
.reset (onchip_memory2_0_s1_reset),
.write (onchip_memory2_0_s1_write),
.writedata (onchip_memory2_0_s1_writedata)
);
output1_s1_arbitrator the_output1_s1
(
.clk (clk_0),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_granted_output1_s1 (cpu_0_data_master_granted_output1_s1),
.cpu_0_data_master_qualified_request_output1_s1 (cpu_0_data_master_qualified_request_output1_s1),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_output1_s1 (cpu_0_data_master_read_data_valid_output1_s1),
.cpu_0_data_master_requests_output1_s1 (cpu_0_data_master_requests_output1_s1),
.cpu_0_data_master_waitrequest (cpu_0_data_master_waitrequest),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.d1_output1_s1_end_xfer (d1_output1_s1_end_xfer),
.output1_s1_address (output1_s1_address),
.output1_s1_chipselect (output1_s1_chipselect),
.output1_s1_readdata (output1_s1_readdata),
.output1_s1_readdata_from_sa (output1_s1_readdata_from_sa),
.output1_s1_reset_n (output1_s1_reset_n),
.output1_s1_write_n (output1_s1_write_n),
.output1_s1_writedata (output1_s1_writedata),
.reset_n (clk_0_reset_n)
);
output1 the_output1
(
.address (output1_s1_address),
.chipselect (output1_s1_chipselect),
.clk (clk_0),
.out_port (out_port_from_the_output1),
.readdata (output1_s1_readdata),
.reset_n (output1_s1_reset_n),
.write_n (output1_s1_write_n),
.writedata (output1_s1_writedata)
);
sdram_0_s1_arbitrator the_sdram_0_s1
(
.clk (clk_0),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_byteenable (cpu_0_data_master_byteenable),
.cpu_0_data_master_granted_sdram_0_s1 (cpu_0_data_master_granted_sdram_0_s1),
.cpu_0_data_master_qualified_request_sdram_0_s1 (cpu_0_data_master_qualified_request_sdram_0_s1),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_sdram_0_s1 (cpu_0_data_master_read_data_valid_sdram_0_s1),
.cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register (cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register),
.cpu_0_data_master_requests_sdram_0_s1 (cpu_0_data_master_requests_sdram_0_s1),
.cpu_0_data_master_waitrequest (cpu_0_data_master_waitrequest),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.cpu_0_instruction_master_address_to_slave (cpu_0_instruction_master_address_to_slave),
.cpu_0_instruction_master_granted_sdram_0_s1 (cpu_0_instruction_master_granted_sdram_0_s1),
.cpu_0_instruction_master_qualified_request_sdram_0_s1 (cpu_0_instruction_master_qualified_request_sdram_0_s1),
.cpu_0_instruction_master_read (cpu_0_instruction_master_read),
.cpu_0_instruction_master_read_data_valid_sdram_0_s1 (cpu_0_instruction_master_read_data_valid_sdram_0_s1),
.cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register (cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register),
.cpu_0_instruction_master_requests_sdram_0_s1 (cpu_0_instruction_master_requests_sdram_0_s1),
.d1_sdram_0_s1_end_xfer (d1_sdram_0_s1_end_xfer),
.reset_n (clk_0_reset_n),
.sdram_0_s1_address (sdram_0_s1_address),
.sdram_0_s1_byteenable_n (sdram_0_s1_byteenable_n),
.sdram_0_s1_chipselect (sdram_0_s1_chipselect),
.sdram_0_s1_read_n (sdram_0_s1_read_n),
.sdram_0_s1_readdata (sdram_0_s1_readdata),
.sdram_0_s1_readdata_from_sa (sdram_0_s1_readdata_from_sa),
.sdram_0_s1_readdatavalid (sdram_0_s1_readdatavalid),
.sdram_0_s1_reset_n (sdram_0_s1_reset_n),
.sdram_0_s1_waitrequest (sdram_0_s1_waitrequest),
.sdram_0_s1_waitrequest_from_sa (sdram_0_s1_waitrequest_from_sa),
.sdram_0_s1_write_n (sdram_0_s1_write_n),
.sdram_0_s1_writedata (sdram_0_s1_writedata)
);
sdram_0 the_sdram_0
(
.az_addr (sdram_0_s1_address),
.az_be_n (sdram_0_s1_byteenable_n),
.az_cs (sdram_0_s1_chipselect),
.az_data (sdram_0_s1_writedata),
.az_rd_n (sdram_0_s1_read_n),
.az_wr_n (sdram_0_s1_write_n),
.clk (clk_0),
.reset_n (sdram_0_s1_reset_n),
.za_data (sdram_0_s1_readdata),
.za_valid (sdram_0_s1_readdatavalid),
.za_waitrequest (sdram_0_s1_waitrequest),
.zs_addr (zs_addr_from_the_sdram_0),
.zs_ba (zs_ba_from_the_sdram_0),
.zs_cas_n (zs_cas_n_from_the_sdram_0),
.zs_cke (zs_cke_from_the_sdram_0),
.zs_cs_n (zs_cs_n_from_the_sdram_0),
.zs_dq (zs_dq_to_and_from_the_sdram_0),
.zs_dqm (zs_dqm_from_the_sdram_0),
.zs_ras_n (zs_ras_n_from_the_sdram_0),
.zs_we_n (zs_we_n_from_the_sdram_0)
);
sysid_control_slave_arbitrator the_sysid_control_slave
(
.clk (clk_0),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_granted_sysid_control_slave (cpu_0_data_master_granted_sysid_control_slave),
.cpu_0_data_master_qualified_request_sysid_control_slave (cpu_0_data_master_qualified_request_sysid_control_slave),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_sysid_control_slave (cpu_0_data_master_read_data_valid_sysid_control_slave),
.cpu_0_data_master_requests_sysid_control_slave (cpu_0_data_master_requests_sysid_control_slave),
.cpu_0_data_master_write (cpu_0_data_master_write),
.d1_sysid_control_slave_end_xfer (d1_sysid_control_slave_end_xfer),
.reset_n (clk_0_reset_n),
.sysid_control_slave_address (sysid_control_slave_address),
.sysid_control_slave_readdata (sysid_control_slave_readdata),
.sysid_control_slave_readdata_from_sa (sysid_control_slave_readdata_from_sa),
.sysid_control_slave_reset_n (sysid_control_slave_reset_n)
);
sysid the_sysid
(
.address (sysid_control_slave_address),
.clock (sysid_control_slave_clock),
.readdata (sysid_control_slave_readdata),
.reset_n (sysid_control_slave_reset_n)
);
video_character_buffer_with_dma_0_avalon_char_buffer_slave_arbitrator the_video_character_buffer_with_dma_0_avalon_char_buffer_slave
(
.clk (vga_clock),
.d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer (d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer),
.nios_system_clock_1_out_address_to_slave (nios_system_clock_1_out_address_to_slave),
.nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave (nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave),
.nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave (nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave),
.nios_system_clock_1_out_read (nios_system_clock_1_out_read),
.nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave (nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave),
.nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave (nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave),
.nios_system_clock_1_out_write (nios_system_clock_1_out_write),
.nios_system_clock_1_out_writedata (nios_system_clock_1_out_writedata),
.reset_n (vga_clock_reset_n),
.video_character_buffer_with_dma_0_avalon_char_buffer_slave_address (video_character_buffer_with_dma_0_avalon_char_buffer_slave_address),
.video_character_buffer_with_dma_0_avalon_char_buffer_slave_byteenable (video_character_buffer_with_dma_0_avalon_char_buffer_slave_byteenable),
.video_character_buffer_with_dma_0_avalon_char_buffer_slave_chipselect (video_character_buffer_with_dma_0_avalon_char_buffer_slave_chipselect),
.video_character_buffer_with_dma_0_avalon_char_buffer_slave_read (video_character_buffer_with_dma_0_avalon_char_buffer_slave_read),
.video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata (video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata),
.video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa (video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa),
.video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest (video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest),
.video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa (video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa),
.video_character_buffer_with_dma_0_avalon_char_buffer_slave_write (video_character_buffer_with_dma_0_avalon_char_buffer_slave_write),
.video_character_buffer_with_dma_0_avalon_char_buffer_slave_writedata (video_character_buffer_with_dma_0_avalon_char_buffer_slave_writedata)
);
video_character_buffer_with_dma_0_avalon_char_control_slave_arbitrator the_video_character_buffer_with_dma_0_avalon_char_control_slave
(
.clk (vga_clock),
.d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer (d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer),
.nios_system_clock_0_out_address_to_slave (nios_system_clock_0_out_address_to_slave),
.nios_system_clock_0_out_byteenable (nios_system_clock_0_out_byteenable),
.nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave (nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave),
.nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave (nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave),
.nios_system_clock_0_out_read (nios_system_clock_0_out_read),
.nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave (nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave),
.nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave (nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave),
.nios_system_clock_0_out_write (nios_system_clock_0_out_write),
.nios_system_clock_0_out_writedata (nios_system_clock_0_out_writedata),
.reset_n (vga_clock_reset_n),
.video_character_buffer_with_dma_0_avalon_char_control_slave_address (video_character_buffer_with_dma_0_avalon_char_control_slave_address),
.video_character_buffer_with_dma_0_avalon_char_control_slave_byteenable (video_character_buffer_with_dma_0_avalon_char_control_slave_byteenable),
.video_character_buffer_with_dma_0_avalon_char_control_slave_chipselect (video_character_buffer_with_dma_0_avalon_char_control_slave_chipselect),
.video_character_buffer_with_dma_0_avalon_char_control_slave_read (video_character_buffer_with_dma_0_avalon_char_control_slave_read),
.video_character_buffer_with_dma_0_avalon_char_control_slave_readdata (video_character_buffer_with_dma_0_avalon_char_control_slave_readdata),
.video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa (video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa),
.video_character_buffer_with_dma_0_avalon_char_control_slave_reset (video_character_buffer_with_dma_0_avalon_char_control_slave_reset),
.video_character_buffer_with_dma_0_avalon_char_control_slave_write (video_character_buffer_with_dma_0_avalon_char_control_slave_write),
.video_character_buffer_with_dma_0_avalon_char_control_slave_writedata (video_character_buffer_with_dma_0_avalon_char_control_slave_writedata)
);
video_character_buffer_with_dma_0_avalon_char_source_arbitrator the_video_character_buffer_with_dma_0_avalon_char_source
(
.clk (vga_clock),
.reset_n (vga_clock_reset_n),
.video_character_buffer_with_dma_0_avalon_char_source_data (video_character_buffer_with_dma_0_avalon_char_source_data),
.video_character_buffer_with_dma_0_avalon_char_source_endofpacket (video_character_buffer_with_dma_0_avalon_char_source_endofpacket),
.video_character_buffer_with_dma_0_avalon_char_source_ready (video_character_buffer_with_dma_0_avalon_char_source_ready),
.video_character_buffer_with_dma_0_avalon_char_source_startofpacket (video_character_buffer_with_dma_0_avalon_char_source_startofpacket),
.video_character_buffer_with_dma_0_avalon_char_source_valid (video_character_buffer_with_dma_0_avalon_char_source_valid),
.video_vga_controller_0_avalon_vga_sink_ready_from_sa (video_vga_controller_0_avalon_vga_sink_ready_from_sa)
);
video_character_buffer_with_dma_0 the_video_character_buffer_with_dma_0
(
.buf_address (video_character_buffer_with_dma_0_avalon_char_buffer_slave_address),
.buf_byteenable (video_character_buffer_with_dma_0_avalon_char_buffer_slave_byteenable),
.buf_chipselect (video_character_buffer_with_dma_0_avalon_char_buffer_slave_chipselect),
.buf_read (video_character_buffer_with_dma_0_avalon_char_buffer_slave_read),
.buf_readdata (video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata),
.buf_waitrequest (video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest),
.buf_write (video_character_buffer_with_dma_0_avalon_char_buffer_slave_write),
.buf_writedata (video_character_buffer_with_dma_0_avalon_char_buffer_slave_writedata),
.clk (vga_clock),
.ctrl_address (video_character_buffer_with_dma_0_avalon_char_control_slave_address),
.ctrl_byteenable (video_character_buffer_with_dma_0_avalon_char_control_slave_byteenable),
.ctrl_chipselect (video_character_buffer_with_dma_0_avalon_char_control_slave_chipselect),
.ctrl_read (video_character_buffer_with_dma_0_avalon_char_control_slave_read),
.ctrl_readdata (video_character_buffer_with_dma_0_avalon_char_control_slave_readdata),
.ctrl_write (video_character_buffer_with_dma_0_avalon_char_control_slave_write),
.ctrl_writedata (video_character_buffer_with_dma_0_avalon_char_control_slave_writedata),
.reset (video_character_buffer_with_dma_0_avalon_char_control_slave_reset),
.stream_data (video_character_buffer_with_dma_0_avalon_char_source_data),
.stream_endofpacket (video_character_buffer_with_dma_0_avalon_char_source_endofpacket),
.stream_ready (video_character_buffer_with_dma_0_avalon_char_source_ready),
.stream_startofpacket (video_character_buffer_with_dma_0_avalon_char_source_startofpacket),
.stream_valid (video_character_buffer_with_dma_0_avalon_char_source_valid)
);
video_vga_controller_0_avalon_vga_sink_arbitrator the_video_vga_controller_0_avalon_vga_sink
(
.clk (vga_clock),
.reset_n (vga_clock_reset_n),
.video_character_buffer_with_dma_0_avalon_char_source_data (video_character_buffer_with_dma_0_avalon_char_source_data),
.video_character_buffer_with_dma_0_avalon_char_source_endofpacket (video_character_buffer_with_dma_0_avalon_char_source_endofpacket),
.video_character_buffer_with_dma_0_avalon_char_source_startofpacket (video_character_buffer_with_dma_0_avalon_char_source_startofpacket),
.video_character_buffer_with_dma_0_avalon_char_source_valid (video_character_buffer_with_dma_0_avalon_char_source_valid),
.video_vga_controller_0_avalon_vga_sink_data (video_vga_controller_0_avalon_vga_sink_data),
.video_vga_controller_0_avalon_vga_sink_endofpacket (video_vga_controller_0_avalon_vga_sink_endofpacket),
.video_vga_controller_0_avalon_vga_sink_ready (video_vga_controller_0_avalon_vga_sink_ready),
.video_vga_controller_0_avalon_vga_sink_ready_from_sa (video_vga_controller_0_avalon_vga_sink_ready_from_sa),
.video_vga_controller_0_avalon_vga_sink_reset (video_vga_controller_0_avalon_vga_sink_reset),
.video_vga_controller_0_avalon_vga_sink_startofpacket (video_vga_controller_0_avalon_vga_sink_startofpacket),
.video_vga_controller_0_avalon_vga_sink_valid (video_vga_controller_0_avalon_vga_sink_valid)
);
video_vga_controller_0 the_video_vga_controller_0
(
.VGA_B (VGA_B_from_the_video_vga_controller_0),
.VGA_BLANK (VGA_BLANK_from_the_video_vga_controller_0),
.VGA_CLK (VGA_CLK_from_the_video_vga_controller_0),
.VGA_G (VGA_G_from_the_video_vga_controller_0),
.VGA_HS (VGA_HS_from_the_video_vga_controller_0),
.VGA_R (VGA_R_from_the_video_vga_controller_0),
.VGA_SYNC (VGA_SYNC_from_the_video_vga_controller_0),
.VGA_VS (VGA_VS_from_the_video_vga_controller_0),
.clk (vga_clock),
.data (video_vga_controller_0_avalon_vga_sink_data),
.endofpacket (video_vga_controller_0_avalon_vga_sink_endofpacket),
.ready (video_vga_controller_0_avalon_vga_sink_ready),
.reset (video_vga_controller_0_avalon_vga_sink_reset),
.startofpacket (video_vga_controller_0_avalon_vga_sink_startofpacket),
.valid (video_vga_controller_0_avalon_vga_sink_valid)
);
//reset is asserted asynchronously and deasserted synchronously
nios_system_reset_clk_0_domain_synch_module nios_system_reset_clk_0_domain_synch
(
.clk (clk_0),
.data_in (1'b1),
.data_out (clk_0_reset_n),
.reset_n (reset_n_sources)
);
//reset sources mux, which is an e_mux
assign reset_n_sources = ~(~reset_n |
0 |
cpu_0_jtag_debug_module_resetrequest_from_sa |
cpu_0_jtag_debug_module_resetrequest_from_sa |
0);
//reset is asserted asynchronously and deasserted synchronously
nios_system_reset_vga_clock_domain_synch_module nios_system_reset_vga_clock_domain_synch
(
.clk (vga_clock),
.data_in (1'b1),
.data_out (vga_clock_reset_n),
.reset_n (reset_n_sources)
);
//nios_system_clock_0_out_endofpacket of type endofpacket does not connect to anything so wire it to default (0)
assign nios_system_clock_0_out_endofpacket = 0;
//nios_system_clock_1_out_endofpacket of type endofpacket does not connect to anything so wire it to default (0)
assign nios_system_clock_1_out_endofpacket = 0;
//sysid_control_slave_clock of type clock does not connect to anything so wire it to default (0)
assign sysid_control_slave_clock = 0;
endmodule
//synthesis translate_off
// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
// AND HERE WILL BE PRESERVED </ALTERA_NOTE>
// If user logic components use Altsync_Ram with convert_hex2ver.dll,
// set USE_convert_hex2ver in the user comments section above
// `ifdef USE_convert_hex2ver
// `else
// `define NO_PLI 1
// `endif
`include "c:/altera/quartus/eda/sim_lib/altera_mf.v"
`include "c:/altera/quartus/eda/sim_lib/220model.v"
`include "c:/altera/quartus/eda/sim_lib/sgate.v"
`include "C:/altera/ip/University_Program/Audio_Video/Video/altera_up_avalon_video_vga_controller/hdl/altera_up_avalon_video_vga_timing.v"
`include "video_vga_controller_0.v"
`include "C:/altera/ip/University_Program/Audio_Video/Video/altera_up_avalon_video_character_buffer_with_dma/hdl/altera_up_video_128_character_rom.v"
`include "C:/altera/ip/University_Program/Audio_Video/Video/altera_up_avalon_video_character_buffer_with_dma/hdl/altera_up_video_fb_color_rom.v"
`include "video_character_buffer_with_dma_0.v"
`include "clocks.v"
// Altera_UP_SD_Card_Avalon_Interface_0.vhd
`include "sdram_0.v"
`include "nios_system_clock_1.v"
`include "sysid.v"
`include "cpu_0_test_bench.v"
`include "cpu_0_oci_test_bench.v"
`include "cpu_0_jtag_debug_module_tck.v"
`include "cpu_0_jtag_debug_module_sysclk.v"
`include "cpu_0_jtag_debug_module_wrapper.v"
`include "cpu_0.v"
`include "output1.v"
`include "input1.v"
`include "jtag_uart_0.v"
`include "onchip_memory2_0.v"
`include "nios_system_clock_0.v"
`timescale 1ns / 1ps
module test_bench
;
wire VGA_BLANK_from_the_video_vga_controller_0;
wire [ 7: 0] VGA_B_from_the_video_vga_controller_0;
wire VGA_CLK_from_the_video_vga_controller_0;
wire [ 7: 0] VGA_G_from_the_video_vga_controller_0;
wire VGA_HS_from_the_video_vga_controller_0;
wire [ 7: 0] VGA_R_from_the_video_vga_controller_0;
wire VGA_SYNC_from_the_video_vga_controller_0;
wire VGA_VS_from_the_video_vga_controller_0;
wire b_SD_cmd_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0;
wire b_SD_dat3_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0;
wire b_SD_dat_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0;
wire clk;
reg clk_0;
wire clocks_SDRAM_CLK_out;
wire clocks_sys_clk_out;
wire [ 7: 0] in_port_to_the_input1;
wire jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa;
wire jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa;
wire nios_system_clock_0_in_endofpacket_from_sa;
wire nios_system_clock_0_out_endofpacket;
wire nios_system_clock_0_out_nativeaddress;
wire nios_system_clock_1_in_endofpacket_from_sa;
wire nios_system_clock_1_out_endofpacket;
wire [ 12: 0] nios_system_clock_1_out_nativeaddress;
wire o_SD_clock_from_the_Altera_UP_SD_Card_Avalon_Interface_0;
wire [ 7: 0] out_port_from_the_output1;
reg reset_n;
wire sysid_control_slave_clock;
reg vga_clock;
wire [ 12: 0] zs_addr_from_the_sdram_0;
wire [ 1: 0] zs_ba_from_the_sdram_0;
wire zs_cas_n_from_the_sdram_0;
wire zs_cke_from_the_sdram_0;
wire zs_cs_n_from_the_sdram_0;
wire [ 31: 0] zs_dq_to_and_from_the_sdram_0;
wire [ 3: 0] zs_dqm_from_the_sdram_0;
wire zs_ras_n_from_the_sdram_0;
wire zs_we_n_from_the_sdram_0;
// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
// add your signals and additional architecture here
// AND HERE WILL BE PRESERVED </ALTERA_NOTE>
//Set us up the Dut
nios_system DUT
(
.VGA_BLANK_from_the_video_vga_controller_0 (VGA_BLANK_from_the_video_vga_controller_0),
.VGA_B_from_the_video_vga_controller_0 (VGA_B_from_the_video_vga_controller_0),
.VGA_CLK_from_the_video_vga_controller_0 (VGA_CLK_from_the_video_vga_controller_0),
.VGA_G_from_the_video_vga_controller_0 (VGA_G_from_the_video_vga_controller_0),
.VGA_HS_from_the_video_vga_controller_0 (VGA_HS_from_the_video_vga_controller_0),
.VGA_R_from_the_video_vga_controller_0 (VGA_R_from_the_video_vga_controller_0),
.VGA_SYNC_from_the_video_vga_controller_0 (VGA_SYNC_from_the_video_vga_controller_0),
.VGA_VS_from_the_video_vga_controller_0 (VGA_VS_from_the_video_vga_controller_0),
.b_SD_cmd_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0 (b_SD_cmd_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0),
.b_SD_dat3_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0 (b_SD_dat3_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0),
.b_SD_dat_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0 (b_SD_dat_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0),
.clk_0 (clk_0),
.clocks_SDRAM_CLK_out (clocks_SDRAM_CLK_out),
.clocks_sys_clk_out (clocks_sys_clk_out),
.in_port_to_the_input1 (in_port_to_the_input1),
.o_SD_clock_from_the_Altera_UP_SD_Card_Avalon_Interface_0 (o_SD_clock_from_the_Altera_UP_SD_Card_Avalon_Interface_0),
.out_port_from_the_output1 (out_port_from_the_output1),
.reset_n (reset_n),
.vga_clock (vga_clock),
.zs_addr_from_the_sdram_0 (zs_addr_from_the_sdram_0),
.zs_ba_from_the_sdram_0 (zs_ba_from_the_sdram_0),
.zs_cas_n_from_the_sdram_0 (zs_cas_n_from_the_sdram_0),
.zs_cke_from_the_sdram_0 (zs_cke_from_the_sdram_0),
.zs_cs_n_from_the_sdram_0 (zs_cs_n_from_the_sdram_0),
.zs_dq_to_and_from_the_sdram_0 (zs_dq_to_and_from_the_sdram_0),
.zs_dqm_from_the_sdram_0 (zs_dqm_from_the_sdram_0),
.zs_ras_n_from_the_sdram_0 (zs_ras_n_from_the_sdram_0),
.zs_we_n_from_the_sdram_0 (zs_we_n_from_the_sdram_0)
);
initial
clk_0 = 1'b0;
always
#10 clk_0 <= ~clk_0;
initial
begin
reset_n <= 0;
#200 reset_n <= 1;
end
initial
vga_clock = 1'b0;
always
#20 vga_clock <= ~vga_clock;
endmodule
//synthesis translate_on |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXTP_TB_V
`define SKY130_FD_SC_LP__SDFXTP_TB_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfxtp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 SCD = 1'b0;
#340 SCE = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SCE = 1'b1;
#540 SCD = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SCE = 1'bx;
#680 SCD = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_lp__sdfxtp dut (.D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXTP_TB_V
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_charFromReceiver (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 7: 0] in_port;
input reset_n;
wire clk_en;
wire [ 7: 0] data_in;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file instructionMemory.v when simulating
// the core, instructionMemory. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module instructionMemory(
clka,
ena,
addra,
douta
);
input clka;
input ena;
input [31 : 0] addra;
output [31 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(32),
.C_ADDRB_WIDTH(32),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(8),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(1),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("instructionMemory.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(128),
.C_READ_DEPTH_B(128),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(128),
.C_WRITE_DEPTH_B(128),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ENA(ena),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFSTP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__DFSTP_BEHAVIORAL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfstp (
Q ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_ls__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFSTP_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31OI_FUNCTIONAL_V
`define SKY130_FD_SC_LS__A31OI_FUNCTIONAL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a31oi (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31OI_FUNCTIONAL_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_clsp_clkctrl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/*
// Module Name: clctrls
///////////////////////////////////////////////////////////////////////
*/
`include "sys.h"
`include "iop.h"
`include "ctu.h"
module ctu_clsp_clkctrl (/*AUTOARG*/
// Outputs
clsp_ctrl_rd_bus_cl, ctu_sparc0_cken_cl, ctu_sparc1_cken_cl,
ctu_sparc2_cken_cl, ctu_sparc3_cken_cl, ctu_sparc4_cken_cl,
ctu_sparc5_cken_cl, ctu_sparc6_cken_cl, ctu_sparc7_cken_cl,
ctu_scdata0_cken_cl, ctu_scdata1_cken_cl, ctu_scdata2_cken_cl,
ctu_scdata3_cken_cl, ctu_sctag0_cken_cl, ctu_sctag1_cken_cl,
ctu_sctag2_cken_cl, ctu_sctag3_cken_cl, ctu_dram02_cken_cl,
ctu_dram13_cken_cl, ctu_ccx_cken_cl, ctu_fpu_cken_cl,
ctu_ddr0_cken_cl, ctu_ddr1_cken_cl, ctu_ddr2_cken_cl,
ctu_ddr3_cken_cl, ctu_iob_cken_cl, ctu_efc_cken_cl, ctu_dbg_cken_cl,
ctu_jbi_cken_cl, ctu_jbusl_cken_cl, ctu_misc_cken_cl,
ctu_jbusr_cken_cl, ctu_io_j_err_cl, clkctrl_dn_cl,
clsp_ctrl_srarm_cl,
// Inputs
cmp_clk, io_pwron_rst_l, creg_cken_vld_cl, jbus_tx_sync, start_clk_cl,
rstctrl_idle_cl, rstctrl_disclk_cl, rstctrl_enclk_cl,
sctag0_ctu_tr_cl, sctag1_ctu_tr_cl, sctag2_ctu_tr_cl,
sctag3_ctu_tr_cl, iob_ctu_tr_cl, dram02_ctu_tr_cl, dram13_ctu_tr_cl,
jbi_ctu_tr_cl, iob_ctu_l2_tr_cl, dbgtrig_dly_cnt_val_cl,
update_clkctrl_reg_cl, clkctrl_data_in_reg, rd_clkctrl_reg_cl,
stop_id_vld_cl, stop_id_decoded
);
//unit level signals
input cmp_clk;
input io_pwron_rst_l;
input creg_cken_vld_cl;
input jbus_tx_sync;
input start_clk_cl;
input rstctrl_idle_cl;
input rstctrl_disclk_cl;
input rstctrl_enclk_cl;
input sctag0_ctu_tr_cl;
input sctag1_ctu_tr_cl;
input sctag2_ctu_tr_cl;
input sctag3_ctu_tr_cl;
input iob_ctu_tr_cl;
input dram02_ctu_tr_cl;
input dram13_ctu_tr_cl;
input jbi_ctu_tr_cl;
input iob_ctu_l2_tr_cl;
input [4:0] dbgtrig_dly_cnt_val_cl;
input update_clkctrl_reg_cl;
input [63:0] clkctrl_data_in_reg;
input rd_clkctrl_reg_cl;
input stop_id_vld_cl;
input [`CCTRLSM_MAX_ST-1:0] stop_id_decoded;
output [63:0] clsp_ctrl_rd_bus_cl;
output ctu_sparc0_cken_cl;
output ctu_sparc1_cken_cl;
output ctu_sparc2_cken_cl;
output ctu_sparc3_cken_cl;
output ctu_sparc4_cken_cl;
output ctu_sparc5_cken_cl;
output ctu_sparc6_cken_cl;
output ctu_sparc7_cken_cl;
output ctu_scdata0_cken_cl;
output ctu_scdata1_cken_cl;
output ctu_scdata2_cken_cl;
output ctu_scdata3_cken_cl;
output ctu_sctag0_cken_cl;
output ctu_sctag1_cken_cl;
output ctu_sctag2_cken_cl;
output ctu_sctag3_cken_cl;
output ctu_dram02_cken_cl;
output ctu_dram13_cken_cl;
output ctu_ccx_cken_cl;
output ctu_fpu_cken_cl;
output ctu_ddr0_cken_cl;
output ctu_ddr1_cken_cl;
output ctu_ddr2_cken_cl;
output ctu_ddr3_cken_cl;
output ctu_iob_cken_cl;
output ctu_efc_cken_cl;
output ctu_dbg_cken_cl;
output ctu_jbi_cken_cl;
output ctu_jbusl_cken_cl;
output ctu_misc_cken_cl;
output ctu_jbusr_cken_cl;
output ctu_io_j_err_cl;
output clkctrl_dn_cl;
output clsp_ctrl_srarm_cl;
// wires
wire [`CCTRLSM_MAX_ST-1:0] stop_id_decoded_cl;
wire [`CCTRLSM_MAX_ST-1:0] stop_id_decoded_cl_nxt;
wire dummy_unused;
wire clsp_ctrl_misc_en_cl;
wire clsp_ctrl_iob_en_cl;
wire clsp_ctrl_jbusr_en_cl;
wire clsp_ctrl_jbusl_en_cl;
wire clsp_ctrl_jbi_en_cl;
wire [3:0] clsp_ctrl_ddr_en_cl;
wire clsp_ctrl_fpu_en_cl;
wire clsp_ctrl_ccx_en_cl;
wire clsp_ctrl_efc_en_cl;
wire clsp_ctrl_dbg_en_cl;
wire [1:0] clsp_ctrl_dram_en_cl;
wire [3:0] clsp_ctrl_sctag_en_cl;
wire [3:0] clsp_ctrl_scdata_en_cl;
wire [7:0] clsp_ctrl_sparc_en_cl;
wire clsp_ctrl_ossdis_cl;
wire clsp_ctrl_clkdis_cl;
wire clsp_ctrl_misc_en_nxt;
wire clsp_ctrl_iob_en_nxt;
wire clsp_ctrl_jbusr_en_nxt;
wire clsp_ctrl_jbusl_en_nxt;
wire clsp_ctrl_jbi_en_nxt;
wire [3:0] clsp_ctrl_ddr_en_nxt;
wire clsp_ctrl_fpu_en_nxt;
wire clsp_ctrl_ccx_en_nxt;
wire clsp_ctrl_efc_en_nxt;
wire clsp_ctrl_dbg_en_nxt;
wire [1:0] clsp_ctrl_dram_en_nxt;
wire [3:0] clsp_ctrl_sctag_en_nxt;
wire [3:0] clsp_ctrl_scdata_en_nxt;
wire [7:0] clsp_ctrl_sparc_en_nxt;
wire clsp_ctrl_ossdis_nxt;
wire clsp_ctrl_clkdis_nxt;
wire clsp_ctrl_srarm_nxt;
wire [6:0] clsp_ctrl_clkstop_dly_nxt;
wire [6:0] clsp_ctrl_clkstop_dly_cl;
wire rstctrl_disclk_cl;
wire rstctrl_disclk_cl_dly_l;
wire rstctrl_disclk_tr;
wire rstctrl_enclk_cl;
wire rstctrl_enclk_cl_dly_l;
wire rstctrl_enclk_cl_dly;
wire rstctrl_enclk_tr;
wire start_clk_cl;
wire wr_state_pending_nxt;
wire wr_state_pending;
wire clk_dcnt_dn;
wire clk_dcnt_dn_nxt;
wire [6:0] clk_dcnt_nxt;
wire [6:0] clk_dcnt;
wire [4:0] cluster_cnt_nxt;
wire [4:0] cluster_cnt;
wire clk_start_seq_nxt;
wire clk_start_seq;
wire clk_stop_seq_nxt;
wire clk_stop_seq;
wire clk_stop_nxt;
wire clk_stop;
wire cctrl_state_ld;
wire [`CCTRLSM_MAX_ST-1:0] nxt_cctrl_start_state ;
wire [`CCTRLSM_MAX_ST-1:0] cctrl_start_state ;
wire [`CCTRLSM_MAX_ST-1:0] nxt_cctrlsm;
wire [`CCTRLSM_MAX_ST-1:0] cctrlsm;
wire seq_dn;
wire clkctrl_dn_cl_nxt;
wire clkctrl_dn_cl;
wire cctrl_enable_dly;
wire cctrl_enable_nxt;
wire cctrl_enable;
wire cctrl_enable_1st_sht;
wire stop_id_vld_cl_dly_l;
wire stop_id_vld_1sht;
wire stop_id_vld_1sht_dly;
wire stop_id_vld_1sht_dly2;
wire dbg_trig_nxt;
wire dbg_trig;
wire [63:0] clsp_ctrl_rd_bus_nxt;
wire rd_clkctrl_reg_1sht;
wire rd_clkctrl_reg_cl_dly_l;
wire ctu_sparc0_cken_nxt;
wire ctu_sparc1_cken_nxt;
wire ctu_sparc2_cken_nxt;
wire ctu_sparc3_cken_nxt;
wire ctu_sparc4_cken_nxt;
wire ctu_sparc5_cken_nxt;
wire ctu_sparc6_cken_nxt;
wire ctu_sparc7_cken_nxt;
wire ctu_scdata0_cken_nxt;
wire ctu_scdata1_cken_nxt;
wire ctu_scdata2_cken_nxt;
wire ctu_scdata3_cken_nxt;
wire ctu_sctag0_cken_nxt;
wire ctu_sctag1_cken_nxt;
wire ctu_sctag2_cken_nxt;
wire ctu_sctag3_cken_nxt;
wire ctu_dram02_cken_nxt;
wire ctu_dram13_cken_nxt;
wire ctu_ccx_cken_nxt;
wire ctu_fpu_cken_nxt;
wire ctu_iob_cken_nxt;
wire ctu_efc_cken_nxt;
wire ctu_dbg_cken_nxt;
wire ctu_jbi_cken_nxt;
wire ctu_ddr2_cken_nxt;
wire ctu_jbusl_cken_nxt;
wire ctu_ddr0_cken_nxt;
wire ctu_ddr1_cken_nxt;
wire ctu_ddr3_cken_nxt;
wire ctu_misc_cken_nxt;
wire ctu_jbusr_cken_nxt;
wire ctu_jbusr_cken_cl_nxt;
wire ctu_jbusl_cken_cl_nxt;
wire ctu_misc_cken_cl_nxt;
wire ctu_dbg_cken_cl_nxt;
wire dbg_trig_stop_clk_nxt;
wire dbg_trig_stop_clk;
wire dbg_trig_1sht;
wire [4:0] dbg_trig_cnt_nxt;
wire [4:0] dbg_trig_cnt;
wire dbg_trig_dly_l;
wire clk_start_cnt_dn;
wire clk_stop_cnt_dn;
wire dbg_trig_en;
wire dbg_trig_en_nxt;
parameter CLKCNTL_CNT = 7'b1111110;
parameter CLUSTER_CNT = 5'b11110;
//-----------------------------------------------------------------------
//
// output assignment
//
//-----------------------------------------------------------------------
dff_ns u_rstctrl_disclk_dly(
.din (~rstctrl_disclk_cl),
.clk (cmp_clk),
.q(rstctrl_disclk_cl_dly_l)
);
assign rstctrl_disclk_tr = rstctrl_disclk_cl & rstctrl_disclk_cl_dly_l;
dff_ns u_rstctrl_enclk_dly(
.din (rstctrl_enclk_cl),
.clk (cmp_clk),
.q(rstctrl_enclk_cl_dly)
);
dff_ns u_rstctrl_enclk_dly_l(
.din (~rstctrl_enclk_cl_dly),
.clk (cmp_clk),
.q(rstctrl_enclk_cl_dly_l)
);
assign rstctrl_enclk_tr = rstctrl_enclk_cl_dly & rstctrl_enclk_cl_dly_l;
//-----------------------------------------------------------------------
//
// JTAG instruction write
//
//-----------------------------------------------------------------------
dff_ns u_stop_id_vld_1sht(
.din (~stop_id_vld_cl),
.clk (cmp_clk),
.q(stop_id_vld_cl_dly_l)
);
assign stop_id_vld_1sht = stop_id_vld_cl & stop_id_vld_cl_dly_l;
dff_ns u_stop_id_vld_1sht_dly(
.din (stop_id_vld_1sht),
.clk (cmp_clk),
.q(stop_id_vld_1sht_dly)
);
dff_ns u_stop_id_vld_1sht_dly2(
.din (stop_id_vld_1sht_dly),
.clk (cmp_clk),
.q(stop_id_vld_1sht_dly2)
);
// stop_id_decoded needs to be stable for 2 cycles (relax layout requirement)
assign stop_id_decoded_cl_nxt = stop_id_vld_1sht_dly ? stop_id_decoded : stop_id_decoded_cl;
dffrl_async_ns #(`CCTRLSM_MAX_ST) u_stop_id_decoded_cl(
.din ( stop_id_decoded_cl_nxt),
.clk (cmp_clk),
.rst_l(io_pwron_rst_l),
.q ( stop_id_decoded_cl)
);
// state machine could be busy when jtag write top id instruction is issued
assign wr_state_pending_nxt = (stop_id_vld_1sht & cctrl_enable ? 1'b1:
~cctrl_enable ? 1'b0:
wr_state_pending) & start_clk_cl;
dffrl_async_ns u_wr_state_pending(
.din (wr_state_pending_nxt),
.clk (cmp_clk),
.rst_l(io_pwron_rst_l),
.q (wr_state_pending)
);
//-----------------------------------------------------------------------
//
// Debug triggers
//
//-----------------------------------------------------------------------
assign dbg_trig_nxt = (
sctag0_ctu_tr_cl |
sctag1_ctu_tr_cl |
sctag2_ctu_tr_cl |
sctag3_ctu_tr_cl |
dram02_ctu_tr_cl |
dram13_ctu_tr_cl |
iob_ctu_l2_tr_cl |
iob_ctu_tr_cl |
jbi_ctu_tr_cl ) & start_clk_cl;
// Fix for ECO 6526 - Debug trigger does not get to J_ERR (bug 6274).
wire eco6526_dbg_trig_nxt = dbg_trig_nxt || (dbg_trig && !jbus_tx_sync);
dff_ns u_ctu_io_j_err_cl (
.din (eco6526_dbg_trig_nxt),
.clk (cmp_clk),
.q (dbg_trig)
);
dff_ns u_dbg_trig_dly(
.din (~dbg_trig),
.clk (cmp_clk),
.q (dbg_trig_dly_l)
);
// gated with clsp_ctrl_clkdis_cl to mask unknown when dbg enable is off
assign dbg_trig_1sht = dbg_trig & dbg_trig_dly_l & clsp_ctrl_clkdis_cl ;
// level signal
//assign ctu_io_j_err_cl = dbg_trig & clsp_ctrl_clkdis_cl;
// bug 5732
assign ctu_io_j_err_cl = dbg_trig;
//-----------------------------------------------------------------------
//
// clk delay counter
//
//-----------------------------------------------------------------------
// depend on doing clock start stop or clock start load different counter value
// cannot control clock start counts (always 128 cmp clocks)
assign clk_start_cnt_dn = (clk_dcnt == CLKCNTL_CNT);
assign clk_stop_cnt_dn = (clk_dcnt == clsp_ctrl_clkstop_dly_cl);
assign clk_dcnt_dn_nxt = clk_stop_seq? clk_stop_cnt_dn: clk_start_cnt_dn;
dffrl_ns u_clk_dcnt_dn (
.din ( clk_dcnt_dn_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q (clk_dcnt_dn));
assign clk_dcnt_nxt = clk_dcnt_dn ? 7'b0000000:
cctrl_enable_dly & (|(cluster_cnt[4:0]))? clk_dcnt + 7'b0000001 :
clk_dcnt;
dffrl_ns #(7) u_clk_dcnt (
.din ( clk_dcnt_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q (clk_dcnt));
//-----------------------------------------------------------------------
//
// dbg_trig_cnt
//
//-----------------------------------------------------------------------
// when counter matches csr register dbg trigger delay count, dbg_trig_stop_clk
// is asserted
assign dbg_trig_en_nxt = ~clsp_ctrl_clkdis_cl | dbg_trig_stop_clk_nxt ? 1'b0:
dbg_trig_1sht ? 1'b1:
dbg_trig_en;
dffrl_ns u_dbg_trig_en(
.din ( dbg_trig_en_nxt ),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q (dbg_trig_en));
dffrl_ns u_dbg_trig_stop_clk(
.din ( dbg_trig_stop_clk_nxt ),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q (dbg_trig_stop_clk));
assign dbg_trig_cnt_nxt = dbg_trig_en ? dbg_trig_cnt + 5'b00001:
dbg_trig_1sht ? 5'b00000:
dbg_trig_cnt;
dffrl_ns #(5) u_dbg_trig_cnt(
.din ( dbg_trig_cnt_nxt[4:0] ),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q (dbg_trig_cnt[4:0]));
assign dbg_trig_stop_clk_nxt = (dbg_trig_cnt [4:0] == dbgtrig_dly_cnt_val_cl)
& clsp_ctrl_clkdis_cl & dbg_trig_en;
//-----------------------------------------------------------------------
//
// cluster counter
//
//-----------------------------------------------------------------------
// This is created to keep track of how many cluster are processed
// instead of check if cctrlsm are all ones
dffrl_ns u_seq_dn (
.din ( seq_dn_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q (seq_dn));
assign cluster_cnt_nxt = cctrl_enable_1st_sht ? CLUSTER_CNT :
(|(cluster_cnt[4:0]) & clk_dcnt_dn) ? cluster_cnt - 5'b00001 :
cluster_cnt;
dffrl_ns #(5) u_cluster_cnt(
.din ( cluster_cnt_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q (cluster_cnt));
assign seq_dn_nxt = ~(|(cluster_cnt[4:1])) & clk_dcnt_dn;
//-----------------------------------------------------------------------
//
// Clock start and stop logic
//
//-----------------------------------------------------------------------
// clock could be disabled by raising debug trigger or freq change (rstsm)
// clk_stop_seq and clk_stop should be mutually exclusive
// start on 1sht signal of the rstctrl state machine
// start after any reset
assign clk_start_seq_nxt = rstctrl_enclk_tr ? 1'b1:
seq_dn ? 1'b0:
clk_start_seq;
dffrl_ns u_clk_start_seq( .din ( clk_start_seq_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q ( clk_start_seq)
);
// stop on 1sht signal of the rstctrl state machine (before reset)
// debug triggers will stop clk if clsp_ctrl_clkdis_cl is 1
//assign dbg_stop = dbg_trig_stop_clk & clsp_ctrl_clkdis_cl;
assign clk_stop_seq_nxt = ((dbg_trig_stop_clk & ~clsp_ctrl_ossdis_cl )
| rstctrl_disclk_tr) ? 1'b1:
seq_dn ? 1'b0:
clk_stop_seq;
dffrl_ns u_clk_stop_seq( .din ( clk_stop_seq_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q ( clk_stop_seq)
);
// clk_stop and clk_stop_seq cannot be 1 the same time
assign clk_stop_nxt = (dbg_trig_stop_clk & clsp_ctrl_ossdis_cl ) & ~rstctrl_disclk_cl;
dff_ns u_clk_stop( .din (clk_stop_nxt), .clk (cmp_clk), .q (clk_stop));
//-----------------------------------------------------------------------
//
// clk ctrl state machine
//
//-----------------------------------------------------------------------
// default to IDLE state ; only load new id if cctrlsm is not enabled
assign cctrl_state_ld = ( wr_state_pending | stop_id_vld_1sht_dly2) & ~cctrl_enable_dly;
assign nxt_cctrl_start_state = cctrl_state_ld ? stop_id_decoded_cl : cctrl_start_state;
// default to SPARC0
dffrl_ns #(`CCTRLSM_MAX_ST-1) u_cctrl_start_state_30_1(
.din (nxt_cctrl_start_state[`CCTRLSM_MAX_ST-1:1]),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(cctrl_start_state[`CCTRLSM_MAX_ST-1:1])
);
dffsl_ns u_cctrl_start_state_0(
.din (nxt_cctrl_start_state[0]),
.clk (cmp_clk),
.set_l(start_clk_cl),
.q(cctrl_start_state[0])
);
assign nxt_cctrlsm= cctrl_enable_1st_sht ? cctrl_start_state[`CCTRLSM_MAX_ST-1:0] :
~seq_dn & clk_dcnt_dn ? ( cctrlsm[`CCTRLSM_MAX_ST-1:0] |
{cctrlsm[`CCTRLSM_MAX_ST-2:0],cctrlsm[`CCTRLSM_MAX_ST-1]}) :
seq_dn ? { `CCTRLSM_MAX_ST {1'b0}}:
cctrlsm[`CCTRLSM_MAX_ST-1:0];
dffrl_ns #(`CCTRLSM_MAX_ST) u_cctrlsm(
.din (nxt_cctrlsm),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(cctrlsm)
);
//-----------------------------------------------------------------------
//
// clk enable logic
//
//-----------------------------------------------------------------------
// Do not want to change XX_en_cl bit during regular reset seq
// Only want to change the assertion/deassertion of cken
// XX_en_cl will be disabled upon the reception of debug trigger
// cken will automatically disabled
// cken =1 when:
// 1. during clock start seq and clsp_ctrl_X_en_cl is 1
// and its turn of arbitation
// 2. clsp_ctrl_X_en_cl is one when finish clock start/stop seq
// cken =0 when:
// 1. during clock stop seq and its turn of arbitration to turn of clock
// 2. clsp_ctrl_X_en_cl is zero when finish clock start/stop seq
// when dbg trigger is received, clsp_ctrl_X_en_cl becomes 0
assign ctu_sparc0_cken_nxt =
(clk_start_seq & clsp_ctrl_sparc_en_cl[0] & cctrlsm[`CCTRL_SPARC0_POS]) |
(clsp_ctrl_sparc_en_cl[0] & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_SPARC0_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_sparc_en_cl[0] & creg_cken_vld_cl) ? 1'b0:
ctu_sparc0_cken_cl;
assign ctu_sparc1_cken_nxt =
(clk_start_seq & clsp_ctrl_sparc_en_cl[1] & cctrlsm[`CCTRL_SPARC1_POS]) |
(clsp_ctrl_sparc_en_cl[1] & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_SPARC1_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_sparc_en_cl[1] & creg_cken_vld_cl) ? 1'b0:
ctu_sparc1_cken_cl;
assign ctu_sparc2_cken_nxt =
(clk_start_seq & clsp_ctrl_sparc_en_cl[2] & cctrlsm[`CCTRL_SPARC2_POS]) |
(clsp_ctrl_sparc_en_cl[2] & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_SPARC2_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_sparc_en_cl[2] & creg_cken_vld_cl) ? 1'b0:
ctu_sparc2_cken_cl;
assign ctu_sparc3_cken_nxt =
(clk_start_seq & clsp_ctrl_sparc_en_cl[3] & cctrlsm[`CCTRL_SPARC3_POS]) |
(clsp_ctrl_sparc_en_cl[3] & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_SPARC3_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_sparc_en_cl[3] & creg_cken_vld_cl) ? 1'b0:
ctu_sparc3_cken_cl;
assign ctu_sparc4_cken_nxt =
(clk_start_seq & clsp_ctrl_sparc_en_cl[4] & cctrlsm[`CCTRL_SPARC4_POS]) |
(clsp_ctrl_sparc_en_cl[4] & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_SPARC4_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_sparc_en_cl[4] & creg_cken_vld_cl) ? 1'b0:
ctu_sparc4_cken_cl;
assign ctu_sparc5_cken_nxt =
(clk_start_seq & clsp_ctrl_sparc_en_cl[5] & cctrlsm[`CCTRL_SPARC5_POS]) |
(clsp_ctrl_sparc_en_cl[5] & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_SPARC5_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_sparc_en_cl[5] & creg_cken_vld_cl) ? 1'b0:
ctu_sparc5_cken_cl;
assign ctu_sparc6_cken_nxt =
(clk_start_seq & clsp_ctrl_sparc_en_cl[6] & cctrlsm[`CCTRL_SPARC6_POS]) |
(clsp_ctrl_sparc_en_cl[6] & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_SPARC6_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_sparc_en_cl[6] & creg_cken_vld_cl) ? 1'b0:
ctu_sparc6_cken_cl;
assign ctu_sparc7_cken_nxt =
(clk_start_seq & clsp_ctrl_sparc_en_cl[7] & cctrlsm[`CCTRL_SPARC7_POS]) |
(clsp_ctrl_sparc_en_cl[7] & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_SPARC7_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_sparc_en_cl[7] & creg_cken_vld_cl) ? 1'b0:
ctu_sparc7_cken_cl;
assign ctu_scdata0_cken_nxt =
(clk_start_seq & clsp_ctrl_scdata_en_cl[0] & cctrlsm[`CCTRL_SCDATA0_POS]) |
(clsp_ctrl_scdata_en_cl[0] & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_SCDATA0_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_scdata_en_cl[0] & creg_cken_vld_cl) ? 1'b0:
ctu_scdata0_cken_cl;
assign ctu_scdata1_cken_nxt =
(clk_start_seq & clsp_ctrl_scdata_en_cl[1] & cctrlsm[`CCTRL_SCDATA1_POS]) |
(clsp_ctrl_scdata_en_cl[1] & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_SCDATA1_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_scdata_en_cl[1] & creg_cken_vld_cl) ? 1'b0:
ctu_scdata1_cken_cl;
assign ctu_scdata2_cken_nxt =
(clk_start_seq & clsp_ctrl_scdata_en_cl[2] & cctrlsm[`CCTRL_SCDATA2_POS]) |
(clsp_ctrl_scdata_en_cl[2] & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_SCDATA2_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_scdata_en_cl[2] & creg_cken_vld_cl) ? 1'b0:
ctu_scdata2_cken_cl;
assign ctu_scdata3_cken_nxt =
(clk_start_seq & clsp_ctrl_scdata_en_cl[3] & cctrlsm[`CCTRL_SCDATA3_POS]) |
(clsp_ctrl_scdata_en_cl[3] & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_SCDATA3_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_scdata_en_cl[3] & creg_cken_vld_cl) ? 1'b0:
ctu_scdata3_cken_cl;
assign ctu_sctag0_cken_nxt =
(clk_start_seq & clsp_ctrl_sctag_en_cl[0] & cctrlsm[`CCTRL_SCTAG0_POS]) |
(clsp_ctrl_sctag_en_cl[0] & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_SCTAG0_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_sctag_en_cl[0] & creg_cken_vld_cl) ? 1'b0:
ctu_sctag0_cken_cl;
assign ctu_sctag1_cken_nxt =
(clk_start_seq & clsp_ctrl_sctag_en_cl[1] & cctrlsm[`CCTRL_SCTAG1_POS]) |
(clsp_ctrl_sctag_en_cl[1] & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_SCTAG1_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_sctag_en_cl[1] & creg_cken_vld_cl) ? 1'b0:
ctu_sctag1_cken_cl;
assign ctu_sctag2_cken_nxt =
(clk_start_seq & clsp_ctrl_sctag_en_cl[2] & cctrlsm[`CCTRL_SCTAG2_POS]) |
(clsp_ctrl_sctag_en_cl[2] & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_SCTAG2_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_sctag_en_cl[2] & creg_cken_vld_cl) ? 1'b0:
ctu_sctag2_cken_cl;
assign ctu_sctag3_cken_nxt =
(clk_start_seq & clsp_ctrl_sctag_en_cl[3] & cctrlsm[`CCTRL_SCTAG3_POS]) |
(clsp_ctrl_sctag_en_cl[3] & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_SCTAG3_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_sctag_en_cl[3] & creg_cken_vld_cl) ? 1'b0:
ctu_sctag3_cken_cl;
assign ctu_dram02_cken_nxt =
(clk_start_seq & clsp_ctrl_dram_en_cl[0] & cctrlsm[`CCTRL_DRAM02_POS]) |
(clsp_ctrl_dram_en_cl[0] & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_DRAM02_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_dram_en_cl[0] & creg_cken_vld_cl) ? 1'b0:
ctu_dram02_cken_cl;
assign ctu_dram13_cken_nxt =
(clk_start_seq & clsp_ctrl_dram_en_cl[1] & cctrlsm[`CCTRL_DRAM13_POS]) |
(clsp_ctrl_dram_en_cl[1] & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_DRAM13_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_dram_en_cl[1] & creg_cken_vld_cl) ? 1'b0:
ctu_dram13_cken_cl;
assign ctu_ccx_cken_nxt =
(clk_start_seq & clsp_ctrl_ccx_en_cl & cctrlsm[`CCTRL_CCX_POS]) |
(clsp_ctrl_ccx_en_cl & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_CCX_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_ccx_en_cl & creg_cken_vld_cl) ? 1'b0:
ctu_ccx_cken_cl;
assign ctu_fpu_cken_nxt =
(clk_start_seq & clsp_ctrl_fpu_en_cl & cctrlsm[`CCTRL_FPU_POS]) |
(clsp_ctrl_fpu_en_cl & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_FPU_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_fpu_en_cl & creg_cken_vld_cl) ? 1'b0:
ctu_fpu_cken_cl;
assign ctu_ddr0_cken_nxt =
(clk_start_seq & clsp_ctrl_ddr_en_cl[0] & cctrlsm[`CCTRL_DDR0_POS]) |
(clsp_ctrl_ddr_en_cl[0] & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_DDR0_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_ddr_en_cl[0] & creg_cken_vld_cl) ? 1'b0:
ctu_ddr0_cken_cl;
assign ctu_ddr1_cken_nxt =
(clk_start_seq & clsp_ctrl_ddr_en_cl[1] & cctrlsm[`CCTRL_DDR1_POS]) |
(clsp_ctrl_ddr_en_cl[1] & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_DDR1_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_ddr_en_cl[1] & creg_cken_vld_cl) ? 1'b0:
ctu_ddr1_cken_cl;
assign ctu_ddr2_cken_nxt =
(clk_start_seq & clsp_ctrl_ddr_en_cl[2] & cctrlsm[`CCTRL_DDR2_POS]) |
(clsp_ctrl_ddr_en_cl[2] & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_DDR2_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_ddr_en_cl[2] & creg_cken_vld_cl) ? 1'b0:
ctu_ddr2_cken_cl;
assign ctu_ddr3_cken_nxt =
(clk_start_seq & clsp_ctrl_ddr_en_cl[3] & cctrlsm[`CCTRL_DDR3_POS]) |
(clsp_ctrl_ddr_en_cl[3] & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_DDR3_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_ddr_en_cl[3] & creg_cken_vld_cl) ? 1'b0:
ctu_ddr3_cken_cl;
assign ctu_jbi_cken_nxt =
(clk_start_seq & clsp_ctrl_jbi_en_cl & cctrlsm[`CCTRL_JBI_POS]) |
(clsp_ctrl_jbi_en_cl & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_JBI_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_jbi_en_cl & creg_cken_vld_cl) ? 1'b0:
ctu_jbi_cken_cl;
// DO not want to disable clock during regular reset sequence
// jbusr, jbusl, dbg and misc
assign ctu_jbusr_cken_nxt =
(clsp_ctrl_jbusr_en_cl & creg_cken_vld_cl) ? 1'b1:
(~clsp_ctrl_jbusr_en_cl & creg_cken_vld_cl) ? 1'b0:
ctu_jbusr_cken_cl;
assign ctu_jbusl_cken_nxt =
(clsp_ctrl_jbusl_en_cl & creg_cken_vld_cl) ? 1'b1:
(~clsp_ctrl_jbusl_en_cl & creg_cken_vld_cl) ? 1'b0:
ctu_jbusl_cken_cl;
assign ctu_iob_cken_nxt =
(clk_start_seq & clsp_ctrl_iob_en_cl & cctrlsm[`CCTRL_IOB_POS]) |
(clsp_ctrl_iob_en_cl & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_IOB_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_iob_en_cl & creg_cken_vld_cl) ? 1'b0:
ctu_iob_cken_cl;
assign ctu_efc_cken_nxt =
(clk_start_seq & clsp_ctrl_efc_en_cl & cctrlsm[`CCTRL_EFC_POS]) |
(clsp_ctrl_efc_en_cl & creg_cken_vld_cl) ? 1'b1:
(clk_stop_seq & cctrlsm[`CCTRL_EFC_POS] & rstctrl_disclk_cl) |
(~clsp_ctrl_efc_en_cl & creg_cken_vld_cl) ? 1'b0:
ctu_efc_cken_cl;
assign ctu_dbg_cken_nxt =
(clsp_ctrl_dbg_en_cl & creg_cken_vld_cl) ? 1'b1:
(~clsp_ctrl_dbg_en_cl & creg_cken_vld_cl) ? 1'b0:
ctu_dbg_cken_cl;
assign ctu_misc_cken_nxt =
(clsp_ctrl_misc_en_cl & creg_cken_vld_cl) ? 1'b1:
(~clsp_ctrl_misc_en_cl & creg_cken_vld_cl) ? 1'b0:
ctu_misc_cken_cl;
dffrl_ns u_ctu_sparc0_cken( .din (ctu_sparc0_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_sparc0_cken_cl));
dffrl_ns u_ctu_sparc1_cken( .din (ctu_sparc1_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_sparc1_cken_cl));
dffrl_ns u_ctu_sparc2_cken( .din (ctu_sparc2_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_sparc2_cken_cl));
dffrl_ns u_ctu_sparc3_cken( .din (ctu_sparc3_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_sparc3_cken_cl));
dffrl_ns u_ctu_sparc4_cken( .din (ctu_sparc4_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_sparc4_cken_cl));
dffrl_ns u_ctu_sparc5_cken( .din (ctu_sparc5_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_sparc5_cken_cl));
dffrl_ns u_ctu_sparc6_cken( .din (ctu_sparc6_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_sparc6_cken_cl));
dffrl_ns u_ctu_sparc7_cken( .din (ctu_sparc7_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_sparc7_cken_cl));
dffrl_ns u_ctu_scdata0_cken( .din (ctu_scdata0_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_scdata0_cken_cl));
dffrl_ns u_ctu_scdata1_cken( .din (ctu_scdata1_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_scdata1_cken_cl));
dffrl_ns u_ctu_scdata2_cken( .din (ctu_scdata2_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_scdata2_cken_cl));
dffrl_ns u_ctu_scdata3_cken( .din (ctu_scdata3_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_scdata3_cken_cl));
dffrl_ns u_ctu_sctag0_cken( .din (ctu_sctag0_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_sctag0_cken_cl));
dffrl_ns u_ctu_sctag1_cken( .din (ctu_sctag1_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_sctag1_cken_cl));
dffrl_ns u_ctu_sctag2_cken( .din (ctu_sctag2_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_sctag2_cken_cl));
dffrl_ns u_ctu_sctag3_cken( .din (ctu_sctag3_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_sctag3_cken_cl));
dffrl_ns u_ctu_dram02_cken( .din (ctu_dram02_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_dram02_cken_cl));
dffrl_ns u_ctu_dram13_cken( .din (ctu_dram13_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_dram13_cken_cl));
dffrl_ns u_ctu_ccx_cken( .din (ctu_ccx_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_ccx_cken_cl));
dffrl_ns u_ctu_fpu_cken( .din (ctu_fpu_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_fpu_cken_cl));
dffrl_ns u_ctu_ddr0_cken( .din (ctu_ddr0_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_ddr0_cken_cl));
dffrl_ns u_ctu_ddr1_cken( .din (ctu_ddr1_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_ddr1_cken_cl));
dffrl_ns u_ctu_ddr2_cken( .din (ctu_ddr2_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_ddr2_cken_cl));
dffrl_ns u_ctu_ddr3_cken( .din (ctu_ddr3_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_ddr3_cken_cl));
dffrl_ns u_ctu_jbi_cken( .din (ctu_jbi_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_jbi_cken_cl));
assign ctu_jbusr_cken_cl_nxt = start_clk_cl ? ctu_jbusr_cken_nxt: 1'b1;
dffsl_async_ns u_ctu_jbusr_cken( .din (ctu_jbusr_cken_cl_nxt),
.clk (cmp_clk),
.set_l(io_pwron_rst_l),
.q(ctu_jbusr_cken_cl));
assign ctu_jbusl_cken_cl_nxt = start_clk_cl ? ctu_jbusl_cken_nxt: 1'b1;
dffsl_async_ns u_ctu_jbusl_cken( .din (ctu_jbusl_cken_cl_nxt),
.clk (cmp_clk),
.set_l(io_pwron_rst_l),
.q(ctu_jbusl_cken_cl));
dffrl_ns u_ctu_iob_cken( .din (ctu_iob_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_iob_cken_cl));
dffrl_ns u_ctu_efc_cken( .din (ctu_efc_cken_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(ctu_efc_cken_cl));
assign ctu_dbg_cken_cl_nxt = start_clk_cl ? ctu_dbg_cken_nxt: 1'b1;
dffsl_async_ns u_ctu_dbg_cken( .din (ctu_dbg_cken_cl_nxt),
.clk (cmp_clk),
.set_l(io_pwron_rst_l),
.q(ctu_dbg_cken_cl));
assign ctu_misc_cken_cl_nxt = start_clk_cl ? ctu_misc_cken_nxt: 1'b1;
dffsl_async_ns u_ctu_misc_cken( .din (ctu_misc_cken_cl_nxt),
.clk (cmp_clk),
.set_l(io_pwron_rst_l),
.q(ctu_misc_cken_cl));
//-----------------------------------------------------------------------
//
// Check if all component are done
//
//-----------------------------------------------------------------------
// reset by pll locked ; set by all of cctrlsm states processed
// clkctrl_dn is reset by pll_locked after reset , or idle state
assign clkctrl_dn_cl_nxt = seq_dn | clk_stop ? 1'b1:
rstctrl_idle_cl ? 1'b0:
clkctrl_dn_cl;
dffrl_ns u_clkctrl_dn_cl(
.din (clkctrl_dn_cl_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(clkctrl_dn_cl));
// signal to tell when cctrlsm is active
assign cctrl_enable_nxt = seq_dn ? 1'b0:
(clk_start_seq | clk_stop_seq) & ~cctrl_enable ? 1'b1:
cctrl_enable;
dffrl_ns u_cctrl_enable(
.din (cctrl_enable_nxt),
.clk (cmp_clk),
.rst_l(start_clk_cl),
.q(cctrl_enable));
dff_ns u_cctrl_enable_dly(
.din (cctrl_enable),
.clk (cmp_clk),
.q(cctrl_enable_dly));
assign cctrl_enable_1st_sht = cctrl_enable & ~cctrl_enable_dly;
//---------------------------------------------------------------------------
//
// Register : Clock control
//
//---------------------------------------------------------------------------
// OSSDIS 63
// CLKDIS 62
// SRARM 61
// CLKSTOPDLY 54:48
// MISC 34
// RTBI 33
// IOB 31
// JBUSR 30
// JBUSL 29
// JBI 27
// DDR 23:20
// FPU 19
// CCX 18
// DRAM 17:16
// SCTAG 15:12
// SCDATA 11:8
// SPARCORE 7:0
assign clsp_ctrl_ossdis_nxt = update_clkctrl_reg_cl ? clkctrl_data_in_reg[63]:
clsp_ctrl_ossdis_cl;
dffsl_async_ns u_clsp_ctrl_ossdis_cl_ff (.din(clsp_ctrl_ossdis_nxt),
.clk(cmp_clk),
.set_l (io_pwron_rst_l),
.q (clsp_ctrl_ossdis_cl)
);
assign clsp_ctrl_clkdis_nxt = update_clkctrl_reg_cl ? clkctrl_data_in_reg[62]:
clsp_ctrl_clkdis_cl;
dffrl_async_ns u_clsp_ctrl_clkdis_cl_ff (.din(clsp_ctrl_clkdis_nxt),
.clk(cmp_clk),
.rst_l (io_pwron_rst_l),
.q (clsp_ctrl_clkdis_cl)
);
assign clsp_ctrl_srarm_nxt = update_clkctrl_reg_cl ? clkctrl_data_in_reg[61]:
clsp_ctrl_srarm_cl;
dffrl_async_ns u_clsp_ctrl_srarm_cl_ff (.din(clsp_ctrl_srarm_nxt),
.clk(cmp_clk),
.rst_l (io_pwron_rst_l),
.q (clsp_ctrl_srarm_cl)
);
assign clsp_ctrl_clkstop_dly_nxt = update_clkctrl_reg_cl ? clkctrl_data_in_reg[54:48]:
clsp_ctrl_clkstop_dly_cl;
dffsl_async_ns #(7) u_clsp_ctrl_clkstop_dly (.din(clsp_ctrl_clkstop_dly_nxt),
.clk(cmp_clk),
.set_l (io_pwron_rst_l),
.q (clsp_ctrl_clkstop_dly_cl)
);
//---------------------------------------------------------------------------
//
// Clock enable csr control
//
//---------------------------------------------------------------------------
// default to 1 before clock start
assign clsp_ctrl_misc_en_nxt = ~start_clk_cl? 1'b1:
// after received dbg trigger and csr is programmed to stop in seq
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_MISC_POS]) |
// after received dbg trigger and csr is programmed to stop in one shot
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
// update csr register
update_clkctrl_reg_cl ? clkctrl_data_in_reg[34] :
clsp_ctrl_misc_en_cl;
dffsl_async_ns u_clsp_ctrl_misc_en_ff ( .din(clsp_ctrl_misc_en_nxt ),
.clk(cmp_clk),
.set_l (io_pwron_rst_l),
.q (clsp_ctrl_misc_en_cl)
);
assign clsp_ctrl_efc_en_nxt = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_EFC_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[32]:
clsp_ctrl_efc_en_cl;
dffsl_async_ns u_clsp_ctrl_efc_en_ff ( .din(clsp_ctrl_efc_en_nxt ),
.clk(cmp_clk),
.set_l (io_pwron_rst_l),
.q (clsp_ctrl_efc_en_cl)
);
assign clsp_ctrl_dbg_en_nxt = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_DBG_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[33]:
clsp_ctrl_dbg_en_cl;
dffsl_async_ns u_clsp_ctrl_dbg_en_ff ( .din(clsp_ctrl_dbg_en_nxt ),
.clk(cmp_clk),
.set_l (io_pwron_rst_l),
.q (clsp_ctrl_dbg_en_cl)
);
assign clsp_ctrl_iob_en_nxt = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_IOB_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[31]:
clsp_ctrl_iob_en_cl;
dffsl_async_ns u_clsp_ctrl_iob_en_ff ( .din(clsp_ctrl_iob_en_nxt ),
.clk(cmp_clk),
.set_l (io_pwron_rst_l),
.q (clsp_ctrl_iob_en_cl)
);
assign clsp_ctrl_jbusr_en_nxt = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_JBUSR_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[30]
: clsp_ctrl_jbusr_en_cl;
dffsl_async_ns u_clsp_ctrl_jbusr_en_ff (.din(clsp_ctrl_jbusr_en_nxt ),
.clk(cmp_clk),
.set_l (io_pwron_rst_l),
.q (clsp_ctrl_jbusr_en_cl)
);
assign clsp_ctrl_jbusl_en_nxt = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_JBUSL_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[29]
: clsp_ctrl_jbusl_en_cl;
dffsl_async_ns u_clsp_ctrl_jbusl_en_ff ( .din(clsp_ctrl_jbusl_en_nxt ),
.clk(cmp_clk),
.set_l (io_pwron_rst_l),
.q (clsp_ctrl_jbusl_en_cl)
);
assign clsp_ctrl_jbi_en_nxt = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_JBI_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[27]:
clsp_ctrl_jbi_en_cl;
dffsl_async_ns u_clsp_ctrl_jbi_en_ff ( .din(clsp_ctrl_jbi_en_nxt ),
.clk(cmp_clk),
.set_l (io_pwron_rst_l),
.q (clsp_ctrl_jbi_en_cl)
);
assign clsp_ctrl_ddr_en_nxt[3] = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_DDR3_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[23]:
clsp_ctrl_ddr_en_cl[3];
assign clsp_ctrl_ddr_en_nxt[2] = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_DDR2_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[22]:
clsp_ctrl_ddr_en_cl[2];
assign clsp_ctrl_ddr_en_nxt[1] = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_DDR1_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[21]:
clsp_ctrl_ddr_en_cl[1];
assign clsp_ctrl_ddr_en_nxt[0] = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_DDR0_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[20]:
clsp_ctrl_ddr_en_cl[0];
dffsl_async_ns #(4) u_clsp_ctrl_ddr_en_ff ( .din(clsp_ctrl_ddr_en_nxt ),
.clk(cmp_clk),
.set_l (io_pwron_rst_l),
.q (clsp_ctrl_ddr_en_cl)
);
assign clsp_ctrl_fpu_en_nxt = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_FPU_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[19]:
clsp_ctrl_fpu_en_cl;
dffsl_async_ns u_clsp_ctrl_fpu_en_ff ( .din(clsp_ctrl_fpu_en_nxt ),
.clk(cmp_clk),
.set_l (io_pwron_rst_l),
.q (clsp_ctrl_fpu_en_cl)
);
assign clsp_ctrl_ccx_en_nxt = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_CCX_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[18]:
clsp_ctrl_ccx_en_cl;
dffsl_async_ns u_clsp_ctrl_ccx_en_ff ( .din(clsp_ctrl_ccx_en_nxt ),
.clk(cmp_clk),
.set_l (io_pwron_rst_l),
.q (clsp_ctrl_ccx_en_cl)
);
assign clsp_ctrl_dram_en_nxt[1] = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_DRAM13_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[17]:
clsp_ctrl_dram_en_cl[1];
assign clsp_ctrl_dram_en_nxt[0] = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_DRAM02_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[16]:
clsp_ctrl_dram_en_cl[0];
dffsl_async_ns #(2) u_clsp_ctrl_dram_en_ff ( .din(clsp_ctrl_dram_en_nxt ),
.clk(cmp_clk),
.set_l (io_pwron_rst_l),
.q (clsp_ctrl_dram_en_cl)
);
assign clsp_ctrl_sctag_en_nxt[3] = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_SCTAG3_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[15]:
clsp_ctrl_sctag_en_cl[3];
assign clsp_ctrl_sctag_en_nxt[2] = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_SCTAG2_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[14]:
clsp_ctrl_sctag_en_cl[2];
assign clsp_ctrl_sctag_en_nxt[1] = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_SCTAG1_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[13]:
clsp_ctrl_sctag_en_cl[1];
assign clsp_ctrl_sctag_en_nxt[0] = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_SCTAG0_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[12]:
clsp_ctrl_sctag_en_cl[0];
dffsl_async_ns #(4) u_clsp_ctrl_sctag_en_ff ( .din(clsp_ctrl_sctag_en_nxt ),
.clk(cmp_clk),
.set_l (io_pwron_rst_l),
.q (clsp_ctrl_sctag_en_cl)
);
assign clsp_ctrl_scdata_en_nxt[3] = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_SCDATA3_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[11]:
clsp_ctrl_scdata_en_cl[3];
assign clsp_ctrl_scdata_en_nxt[2] = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_SCDATA2_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[10]:
clsp_ctrl_scdata_en_cl[2];
assign clsp_ctrl_scdata_en_nxt[1] = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_SCDATA1_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[9]:
clsp_ctrl_scdata_en_cl[1];
assign clsp_ctrl_scdata_en_nxt[0] = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_SCDATA0_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[8]:
clsp_ctrl_scdata_en_cl[0];
dffsl_async_ns #(4) u_clsp_ctrl_scdata_en_ff ( .din(clsp_ctrl_scdata_en_nxt ),
.clk(cmp_clk),
.set_l (io_pwron_rst_l),
.q (clsp_ctrl_scdata_en_cl)
);
assign clsp_ctrl_sparc_en_nxt[7] = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_SPARC7_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[7]:
clsp_ctrl_sparc_en_cl[7];
assign clsp_ctrl_sparc_en_nxt[6] = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_SPARC6_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[6]:
clsp_ctrl_sparc_en_cl[6];
assign clsp_ctrl_sparc_en_nxt[5] = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_SPARC5_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[5]:
clsp_ctrl_sparc_en_cl[5];
assign clsp_ctrl_sparc_en_nxt[4] = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_SPARC4_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[4]:
clsp_ctrl_sparc_en_cl[4];
assign clsp_ctrl_sparc_en_nxt[3] = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_SPARC3_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[3]:
clsp_ctrl_sparc_en_cl[3];
assign clsp_ctrl_sparc_en_nxt[2] = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_SPARC2_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[2]:
clsp_ctrl_sparc_en_cl[2];
assign clsp_ctrl_sparc_en_nxt[1] = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_SPARC1_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[1]:
clsp_ctrl_sparc_en_cl[1];
assign clsp_ctrl_sparc_en_nxt[0] = ~start_clk_cl? 1'b1:
(clk_stop_seq & ~rstctrl_disclk_cl & cctrlsm[`CCTRL_SPARC0_POS]) |
(dbg_trig_stop_clk & clsp_ctrl_ossdis_cl) ? 1'b0:
update_clkctrl_reg_cl ? clkctrl_data_in_reg[0]:
clsp_ctrl_sparc_en_cl[0];
dffsl_async_ns #(8) u_clsp_ctrl_sparc_en_ff ( .din(clsp_ctrl_sparc_en_nxt ),
.clk(cmp_clk),
.set_l (io_pwron_rst_l),
.q (clsp_ctrl_sparc_en_cl)
);
dff_ns u_rd_clkctrl_reg_1sht ( .din(~rd_clkctrl_reg_cl),
.clk(cmp_clk),
.q (rd_clkctrl_reg_cl_dly_l)
);
assign rd_clkctrl_reg_1sht = rd_clkctrl_reg_cl & rd_clkctrl_reg_cl_dly_l;
assign clsp_ctrl_rd_bus_nxt = { clsp_ctrl_ossdis_cl,
clsp_ctrl_clkdis_cl,
clsp_ctrl_srarm_cl,
6'b000000,
clsp_ctrl_clkstop_dly_cl[6:0],
13'b0000000000000,
clsp_ctrl_misc_en_cl,
clsp_ctrl_dbg_en_cl,
clsp_ctrl_efc_en_cl,
clsp_ctrl_iob_en_cl,
clsp_ctrl_jbusr_en_cl,
clsp_ctrl_jbusl_en_cl,
1'b0,
clsp_ctrl_jbi_en_cl,
3'b000,
clsp_ctrl_ddr_en_cl[3:0],
clsp_ctrl_fpu_en_cl,
clsp_ctrl_ccx_en_cl,
clsp_ctrl_dram_en_cl[1:0],
clsp_ctrl_sctag_en_cl[3:0],
clsp_ctrl_scdata_en_cl[3:0],
clsp_ctrl_sparc_en_cl[7:0]};
dffrle_ns #(64) u_clsp_ctrl_rd_bus ( .din(clsp_ctrl_rd_bus_nxt),
.clk(cmp_clk),
.en(rd_clkctrl_reg_1sht),
.rst_l(start_clk_cl),
.q (clsp_ctrl_rd_bus_cl)
);
assign dummy_unused = &{clkctrl_data_in_reg[60:55],clkctrl_data_in_reg[47:24]};
//-----------------------------------------------------------------------
//
// Multicycle path checks
//
//-----------------------------------------------------------------------
// synopsys translate_off
reg [`CCTRLSM_MAX_ST-1:0] prev_stop_id_decoded;
//top_id_decoded needs to hold at least 2 cmp clocks
always @(stop_id_vld_cl)
begin
prev_stop_id_decoded <= stop_id_decoded;
@(posedge cmp_clk)
if( (start_clk_cl === 1'b1) &
(`CTU_PATH.pll_bypass === 1'b0) & ( `CTU_PATH.testmode_l === 1'b1) &
( prev_stop_id_decoded !== stop_id_decoded)
)
`ifdef MODELSIM
$display ( "CTU_mpath_check_error", "stop_id_decoded should hold for at least 2 cmp cycles");
`else
$error ( "CTU_mpath_check_error", "stop_id_decoded should hold for at least 2 cmp cycles");
`endif
@(posedge cmp_clk)
if( (start_clk_cl === 1'b1) &
(`CTU_PATH.pll_bypass === 1'b0) & ( `CTU_PATH.testmode_l === 1'b1) &
( prev_stop_id_decoded !== stop_id_decoded)
)
`ifdef MODELSIM
$display ( "CTU_mpath_check_error", "stop_id_decoded should hold for at least 2 cmp cycles");
`else
$error ( "CTU_mpath_check_error", "stop_id_decoded should hold for at least 2 cmp cycles");
`endif
end
// clk_stop and clk_stop_seq should be exclusive
always @(/*AUTOSENSE*/clk_stop or clk_stop_seq
or `CTU_PATH.pll_bypass or `CTU_PATH.testmode_l or start_clk_cl)
begin
if( (start_clk_cl === 1'b1) &
(`CTU_PATH.pll_bypass === 1'b0) & ( `CTU_PATH.testmode_l === 1'b1) &
(clk_stop === 1'b1) & (clk_stop_seq=== 1'b1) )
`ifdef MODELSIM
$display ( "CTU_logic_check_err", " clk_stop & clk_stop_seq cannot be 1 at the same time");
`else
$error ( "CTU_logic_check_err", " clk_stop & clk_stop_seq cannot be 1 at the same time");
`endif
end
// synopsys translate_on
endmodule // clkctrl
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3B_BEHAVIORAL_V
`define SKY130_FD_SC_HS__NOR3B_BEHAVIORAL_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , C_N, nor0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3B_BEHAVIORAL_V |
`timescale 1ns/1ns
`include "ctldefine.v"
module forward_ctl (instrD,instrE,instrM,instrW,
ForwardRSD,ForwardRTD,
ForwardRSE,ForwardRTE,
ForwardRTM);
input [31:0] instrD,instrE,instrM,instrW;
output [2:0] ForwardRSD,ForwardRTD;
output [2:0] ForwardRSE,ForwardRTE;
output [1:0] ForwardRTM;
wire cal_r_d,cal_i_d,jorb_d,brs_d,brt_d,jr_d,ld_d,st_d,jal_d,muldiv_d,mfc0_d,mtc0_d;
wire cal_r_e,cal_i_e,jorb_e,brs_e,brt_e,jr_e,st_e,ld_e,jal_e,muldiv_e,mfc0_e,mtc0_e;
wire cal_r_m,cal_i_m,jorb_m,brs_m,brt_m,jr_m,st_m,ld_m,jal_m,muldiv_m,mfc0_m,mtc0_m;
wire cal_r_w,cal_i_w,jorb_w,brs_w,brt_w,jr_w,st_w,ld_w,jal_w,muldiv_w,mfc0_w,mtc0_w;
processInstr pinstrD(instrD,cal_r_d,cal_i_d,ld_d,st_d,brs_d,brt_d,jr_d,jal_d,muldiv_d,mtc0_d,mfc0_d);
processInstr pinstrE(instrE,cal_r_e,cal_i_e,ld_e,st_e,brs_e,brt_e,jr_e,jal_e,muldiv_e,mtc0_e,mfc0_e);
processInstr pinstrM(instrM,cal_r_m,cal_i_m,ld_m,st_m,brs_m,brt_m,jr_m,jal_m,muldiv_m,mtc0_m,mfc0_m);
processInstr pinstrW(instrW,cal_r_w,cal_i_w,ld_w,st_w,brs_w,brt_w,jr_w,jal_w,muldiv_w,mtc0_w,mfc0_w);
assign jorb_d = brs_d | jr_d;
assign jorb_e = brs_d | jr_e;
assign jorb_m = brs_d | jr_m;
assign jorb_w = brs_d | jr_w;
assign ForwardRSD = jorb_d & instrD[`RS]==5'h0 ? 0:
jorb_d & cal_r_m & instrD[`RS]==instrM[`RD] ? 1:
jorb_d & cal_i_m & instrD[`RS]==instrM[`RT] ? 1:
jorb_d & jal_m & instrD[`RS]==5'd31 ? 3:
jorb_d & cal_r_w & instrD[`RS]==instrW[`RD] ? 2:
jorb_d & cal_i_w & instrD[`RS]==instrW[`RT] ? 2:
jorb_d & (ld_w | mfc0_w) & instrD[`RS]==instrW[`RT] ? 2:
jorb_d & jal_w & instrD[`RS]==5'd31 ? 4:
0;
assign ForwardRTD = brt_d & instrD[`RT]==5'h0 ? 0:
brt_d & cal_r_m & instrD[`RT]==instrM[`RD] ? 1:
brt_d & (cal_i_m | mfc0_m) & instrD[`RT]==instrM[`RT] ? 1:
brt_d & jal_m & instrD[`RT]==5'd31 ? 3:
brt_d & cal_r_w & instrD[`RT]==instrW[`RD] ? 2:
brt_d & (cal_i_w | mfc0_w) & instrD[`RT]==instrW[`RT] ? 2:
brt_d & ld_w & instrD[`RT]==instrW[`RT] ? 2:
brt_d & jal_w & instrD[`RT]==5'd31 ? 4:
0;
assign ForwardRSE = (cal_r_e | cal_i_e | ld_e | st_e) & instrE[`RS]==5'h0 ? 0:
(cal_r_e | cal_i_e | ld_e | st_e) & cal_r_m & instrE[`RS]==instrM[`RD] ? 1:
(cal_r_e | cal_i_e | ld_e | st_e) & (cal_i_m | mfc0_m) & instrE[`RS]==instrM[`RT] ? 1:
(cal_r_e | cal_i_e | ld_e | st_e) & jal_m & instrE[`RS]==5'd31 ? 3:
(cal_r_e | cal_i_e | ld_e | st_e) & cal_r_w & instrE[`RS]==instrW[`RD] ? 2:
(cal_r_e | cal_i_e | ld_e | st_e) & (cal_i_w | mfc0_w) & instrE[`RS]==instrW[`RT] ? 2:
(cal_r_e | cal_i_e | ld_e | st_e) & ld_w & instrE[`RS]==instrW[`RT] ? 2:
(cal_r_e | cal_i_e | ld_e | st_e) & jal_w & instrE[`RS]==5'd31 ? 4:
0;
assign ForwardRTE = (cal_r_e | st_e) & instrE[`RT]==5'h0 ? 0:
(cal_r_e | st_e) & cal_r_m & instrE[`RT]==instrM[`RD] ? 1:
(cal_r_e | st_e) & (cal_i_m | mfc0_m) & instrE[`RT]==instrM[`RT] ? 1:
(cal_r_e | st_e) & jal_m & instrE[`RT]==5'd31 ? 3:
(cal_r_e | st_e) & cal_r_w & instrE[`RT]==instrW[`RD] ? 2:
(cal_r_e | st_e) & (cal_i_w | mfc0_w) & instrE[`RT]==instrW[`RT] ? 2:
(cal_r_e | st_e) & ld_w & instrE[`RT]==instrW[`RT] ? 2:
(cal_r_e | st_e) & jal_w & instrE[`RT]==5'd31 ? 4:
0;
assign ForwardRTM = (mtc0_m | st_m) & instrM[`RT]==5'h0 ? 0:
(mtc0_m | st_m) & cal_r_w & instrM[`RT]==instrW[`RD] ? 1:
(mtc0_m | st_m) & (cal_i_w | mfc0_w) & instrM[`RT]==instrW[`RT] ? 1:
(mtc0_m | st_m) & (ld_w | mfc0_w) & instrM[`RT]==instrW[`RT] ? 1:
(mtc0_m | st_m) & jal_w & instrM[`RT]==5'd31 ? 2:
0;
endmodule // forward_ctl
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:16:30 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64,
n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78,
n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92,
n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105,
n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116,
n117, n118, n119, n120, n121, n122, n123, n124, n125, n126, n127,
n128, n129, n130, n131, n132, n133, n134, n135, n136, n137, n138,
n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149,
n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, n160,
n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171,
n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182,
n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, n193,
n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, n204,
n205, n206, n207, n208, n209, n210, n211, n212, n213, n214, n215,
n216, n217, n218, n219, n220, n221, n222, n223, n224, n225, n226,
n227, n228, n229, n230, n231, n232, n233, n234, n235, n236, n237,
n238, n239, n240, n241, n242, n243, n244, n245, n246, n247, n248,
n249, n250, n251, n252, n253, n254, n255, n256, n257, n258, n259,
n260, n261, n262, n263, n264, n265, n266, n267, n268, n269, n270,
n271, n272, n273, n274, n275, n276, n277, n278, n279, n280, n281,
n282, n283, n284, n285, n286, n287, n288, n289, n290, n291, n292,
n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, n303,
n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, n314,
n315, n316, n317, n318, n319, n320, n321, n322, n323, n324, n325,
n326, n327, n328, n329, n330, n331, n332, n333, n334, n335, n336,
n337, n338, n339, n340, n341, n342, n343, n344, n345, n346, n347,
n348, n349, n350, n351, n352, n353, n354, n355, n356, n357, n358,
n359, n360, n361, n362, n363, n364, n365, n366, n367, n368, n369;
NAND2X1TS U79 ( .A(n197), .B(n144), .Y(n198) );
NAND2X1TS U80 ( .A(n166), .B(n171), .Y(n168) );
NAND2X1TS U81 ( .A(n193), .B(n192), .Y(n194) );
NAND2X1TS U82 ( .A(n201), .B(n200), .Y(n202) );
NAND2XLTS U83 ( .A(n62), .B(n208), .Y(n209) );
NAND2X1TS U84 ( .A(n216), .B(n215), .Y(n217) );
NAND2X1TS U85 ( .A(n184), .B(n183), .Y(n185) );
OAI21X1TS U86 ( .A0(n238), .A1(n225), .B0(n224), .Y(n230) );
OAI21X1TS U87 ( .A0(n238), .A1(n231), .B0(n235), .Y(n234) );
CLKINVX6TS U88 ( .A(n188), .Y(n203) );
CLKMX2X4TS U89 ( .A(n178), .B(in2[31]), .S0(n266), .Y(n179) );
OAI2BB1X1TS U90 ( .A0N(n351), .A1N(n360), .B0(n350), .Y(n363) );
NAND2X1TS U91 ( .A(n329), .B(in1[4]), .Y(n330) );
NOR2X1TS U92 ( .A(n332), .B(in1[5]), .Y(n305) );
NAND2X1TS U93 ( .A(n274), .B(in1[3]), .Y(n366) );
OR3X1TS U94 ( .A(n362), .B(n367), .C(n361), .Y(n275) );
NAND2X1TS U95 ( .A(n316), .B(in1[10]), .Y(n313) );
NAND2X2TS U96 ( .A(n167), .B(in1[30]), .Y(n171) );
MXI2X2TS U97 ( .A(n292), .B(in2[9]), .S0(n320), .Y(n346) );
CLKMX2X2TS U98 ( .A(n165), .B(in2[30]), .S0(n266), .Y(n167) );
MX2X1TS U99 ( .A(n162), .B(in2[29]), .S0(n271), .Y(n163) );
NAND2X1TS U100 ( .A(n273), .B(n272), .Y(n361) );
NOR2X1TS U101 ( .A(n274), .B(in1[3]), .Y(n367) );
NOR2X1TS U102 ( .A(n176), .B(in2[30]), .Y(n177) );
CLKMX2X2TS U103 ( .A(n152), .B(in2[28]), .S0(n271), .Y(n157) );
OR2X4TS U104 ( .A(n138), .B(in1[25]), .Y(n62) );
INVX4TS U105 ( .A(n196), .Y(n201) );
NAND2X2TS U106 ( .A(n137), .B(in1[24]), .Y(n215) );
NOR2X2TS U107 ( .A(n136), .B(in1[23]), .Y(n211) );
NAND2X2TS U108 ( .A(n138), .B(in1[25]), .Y(n208) );
INVX2TS U109 ( .A(n242), .Y(n105) );
NAND2X6TS U110 ( .A(n95), .B(n250), .Y(n249) );
NAND2X6TS U111 ( .A(n53), .B(n55), .Y(n95) );
NAND2X4TS U112 ( .A(n119), .B(in1[21]), .Y(n232) );
XNOR2X1TS U113 ( .A(n161), .B(in2[24]), .Y(n135) );
NOR2X2TS U114 ( .A(n118), .B(in1[20]), .Y(n231) );
INVX2TS U115 ( .A(in2[4]), .Y(n299) );
XNOR2X1TS U116 ( .A(n142), .B(in2[27]), .Y(n143) );
MX2X4TS U117 ( .A(n111), .B(in2[21]), .S0(n266), .Y(n119) );
NOR2X2TS U118 ( .A(n161), .B(n150), .Y(n142) );
NOR2X2TS U119 ( .A(n161), .B(in2[24]), .Y(n128) );
CLKINVX3TS U120 ( .A(n161), .Y(n146) );
NAND2X1TS U121 ( .A(n145), .B(n148), .Y(n150) );
XNOR2X2TS U122 ( .A(n130), .B(in2[20]), .Y(n113) );
XNOR2X2TS U123 ( .A(n100), .B(in2[18]), .Y(n102) );
INVX2TS U124 ( .A(in2[19]), .Y(n52) );
NAND2X2TS U125 ( .A(n83), .B(in1[14]), .Y(n256) );
NOR2X1TS U126 ( .A(in2[25]), .B(in2[24]), .Y(n145) );
NOR2X1TS U127 ( .A(in2[23]), .B(in2[22]), .Y(n125) );
NOR2X2TS U128 ( .A(in2[21]), .B(in2[20]), .Y(n131) );
AND2X2TS U129 ( .A(n109), .B(n108), .Y(n126) );
MX2X4TS U130 ( .A(n78), .B(in2[13]), .S0(n266), .Y(n338) );
XNOR2X2TS U131 ( .A(n81), .B(in2[14]), .Y(n82) );
BUFX6TS U132 ( .A(n91), .Y(n271) );
BUFX6TS U133 ( .A(n91), .Y(n266) );
INVX2TS U134 ( .A(add_sub), .Y(n91) );
INVX4TS U135 ( .A(in2[12]), .Y(n72) );
NOR2X6TS U136 ( .A(in2[5]), .B(in2[4]), .Y(n66) );
NOR2X6TS U137 ( .A(in2[3]), .B(in2[2]), .Y(n65) );
NOR2XLTS U138 ( .A(in2[19]), .B(in2[18]), .Y(n108) );
BUFX6TS U139 ( .A(n70), .Y(n86) );
NAND2X2TS U140 ( .A(n61), .B(n63), .Y(n107) );
NOR2X2TS U141 ( .A(n302), .B(in2[5]), .Y(n318) );
NAND2X1TS U142 ( .A(n275), .B(n366), .Y(n328) );
BUFX4TS U143 ( .A(n91), .Y(n320) );
AND2X4TS U144 ( .A(n338), .B(in1[13]), .Y(n57) );
NAND2X4TS U145 ( .A(n136), .B(in1[23]), .Y(n212) );
NAND2X1TS U146 ( .A(in2[0]), .B(in1[0]), .Y(n360) );
INVX2TS U147 ( .A(n223), .Y(n238) );
NAND2X2TS U148 ( .A(n94), .B(in1[16]), .Y(n250) );
OR2X4TS U149 ( .A(n119), .B(in1[21]), .Y(n51) );
INVX2TS U150 ( .A(n239), .Y(n240) );
INVX2TS U151 ( .A(n200), .Y(n156) );
NAND2X1TS U152 ( .A(n51), .B(n232), .Y(n233) );
OR2X4TS U153 ( .A(n167), .B(in1[30]), .Y(n166) );
INVX1TS U154 ( .A(n342), .Y(n327) );
NAND2X2TS U155 ( .A(n300), .B(n299), .Y(n302) );
NOR2X2TS U156 ( .A(n190), .B(n191), .Y(n158) );
AOI21X2TS U157 ( .A0(n166), .A1(n173), .B0(n172), .Y(n174) );
NAND2X1TS U158 ( .A(n228), .B(n227), .Y(n229) );
INVX2TS U159 ( .A(n226), .Y(n228) );
NAND2X2TS U160 ( .A(n62), .B(n207), .Y(n141) );
NAND2X2TS U161 ( .A(n166), .B(n184), .Y(n175) );
OR2X4TS U162 ( .A(n179), .B(in1[31]), .Y(n56) );
XNOR2X2TS U163 ( .A(n147), .B(in2[26]), .Y(n149) );
NAND2X2TS U164 ( .A(n146), .B(n145), .Y(n147) );
INVX2TS U165 ( .A(n130), .Y(n114) );
NAND3X2TS U166 ( .A(n86), .B(n85), .C(n84), .Y(n87) );
XNOR2X1TS U167 ( .A(n234), .B(n233), .Y(res[21]) );
XNOR2X1TS U168 ( .A(n230), .B(n229), .Y(res[22]) );
NOR2X4TS U169 ( .A(n211), .B(n214), .Y(n207) );
INVX2TS U170 ( .A(n197), .Y(n155) );
INVX4TS U171 ( .A(n245), .Y(n241) );
NAND2X4TS U172 ( .A(n118), .B(in1[20]), .Y(n235) );
XNOR2X2TS U173 ( .A(n115), .B(in2[22]), .Y(n117) );
NAND2BX2TS U174 ( .AN(in2[29]), .B(n164), .Y(n176) );
OR2X4TS U175 ( .A(n89), .B(in1[15]), .Y(n59) );
NOR2X4TS U176 ( .A(n130), .B(in2[20]), .Y(n110) );
NOR2X4TS U177 ( .A(n83), .B(in1[14]), .Y(n255) );
INVX2TS U178 ( .A(n363), .Y(n365) );
NOR2X2TS U179 ( .A(n263), .B(in2[3]), .Y(n300) );
XNOR2X2TS U180 ( .A(n195), .B(n194), .Y(res[28]) );
XOR2X1TS U181 ( .A(n244), .B(n243), .Y(res[19]) );
XOR2X1TS U182 ( .A(n238), .B(n237), .Y(res[20]) );
NAND2X4TS U183 ( .A(n179), .B(in1[31]), .Y(n180) );
XOR2X1TS U184 ( .A(n348), .B(n347), .Y(res[9]) );
INVX2TS U185 ( .A(n208), .Y(n139) );
INVX4TS U186 ( .A(n231), .Y(n236) );
OR2X6TS U187 ( .A(n154), .B(in1[27]), .Y(n144) );
CLKMX2X2TS U188 ( .A(n307), .B(n355), .S0(n353), .Y(n308) );
MX2X4TS U189 ( .A(n143), .B(in2[27]), .S0(n271), .Y(n154) );
NOR2X6TS U190 ( .A(n137), .B(in1[24]), .Y(n214) );
XOR2X1TS U191 ( .A(n298), .B(n297), .Y(res[11]) );
MX2X4TS U192 ( .A(n133), .B(in2[23]), .S0(n266), .Y(n136) );
XOR2X1TS U193 ( .A(n335), .B(n288), .Y(res[12]) );
NOR2X2TS U194 ( .A(n357), .B(in1[7]), .Y(n323) );
OR2X4TS U195 ( .A(n103), .B(in1[18]), .Y(n63) );
OAI21X1TS U196 ( .A0(n329), .A1(n279), .B0(n278), .Y(res[4]) );
MX2X4TS U197 ( .A(n129), .B(in2[25]), .S0(n266), .Y(n138) );
INVX2TS U198 ( .A(n252), .Y(n90) );
OAI21X1TS U199 ( .A0(n316), .A1(n315), .B0(n314), .Y(res[10]) );
MX2X4TS U200 ( .A(n99), .B(in2[19]), .S0(n266), .Y(n104) );
CLKMX2X2TS U201 ( .A(n313), .B(n312), .S0(n311), .Y(n314) );
NAND2X2TS U202 ( .A(n114), .B(n131), .Y(n115) );
OAI21X1TS U203 ( .A0(n329), .A1(in1[4]), .B0(n328), .Y(n331) );
CLKMX2X2TS U204 ( .A(n277), .B(n330), .S0(n328), .Y(n278) );
XNOR2X2TS U205 ( .A(n132), .B(in2[23]), .Y(n133) );
NAND2X4TS U206 ( .A(n89), .B(in1[15]), .Y(n252) );
XOR2X1TS U207 ( .A(n369), .B(n368), .Y(res[3]) );
OAI21X1TS U208 ( .A0(n311), .A1(n295), .B0(n313), .Y(n298) );
XOR2X1TS U209 ( .A(n311), .B(in1[10]), .Y(n315) );
OAI21X1TS U210 ( .A0(n365), .A1(in1[2]), .B0(n364), .Y(n369) );
XOR2X1TS U211 ( .A(n296), .B(in1[11]), .Y(n297) );
NOR2X4TS U212 ( .A(n100), .B(in2[18]), .Y(n98) );
MXI2X4TS U213 ( .A(n82), .B(n84), .S0(n271), .Y(n83) );
XOR2X2TS U214 ( .A(n87), .B(in2[15]), .Y(n88) );
NOR2X1TS U215 ( .A(n316), .B(in1[10]), .Y(n295) );
NAND2X2TS U216 ( .A(n318), .B(n317), .Y(n319) );
OAI21X1TS U217 ( .A0(n363), .A1(n362), .B0(n361), .Y(n364) );
NAND2BX1TS U218 ( .AN(n367), .B(n366), .Y(n368) );
NOR2X1TS U219 ( .A(n342), .B(in1[8]), .Y(n324) );
XOR2XLTS U220 ( .A(n261), .B(n360), .Y(res[1]) );
OAI21X1TS U221 ( .A0(n360), .A1(n351), .B0(n349), .Y(n350) );
NOR2X2TS U222 ( .A(in2[17]), .B(in2[16]), .Y(n109) );
OR2X6TS U223 ( .A(n104), .B(in1[19]), .Y(n61) );
NAND2X4TS U224 ( .A(n51), .B(n236), .Y(n225) );
XOR2X4TS U225 ( .A(n98), .B(n52), .Y(n99) );
XOR2X1TS U226 ( .A(n210), .B(n209), .Y(res[25]) );
OR2X6TS U227 ( .A(n94), .B(in1[16]), .Y(n55) );
NAND2X4TS U228 ( .A(n96), .B(in1[17]), .Y(n247) );
NAND2X6TS U229 ( .A(n127), .B(n126), .Y(n130) );
MXI2X4TS U230 ( .A(n113), .B(n112), .S0(n320), .Y(n118) );
MXI2X4TS U231 ( .A(n102), .B(n101), .S0(n320), .Y(n103) );
NAND2X2TS U232 ( .A(n103), .B(in1[18]), .Y(n245) );
OAI21X4TS U233 ( .A0(n203), .A1(n190), .B0(n189), .Y(n195) );
NAND2X4TS U234 ( .A(n153), .B(in1[26]), .Y(n200) );
NAND2X8TS U235 ( .A(n70), .B(n85), .Y(n81) );
CLKMX2X4TS U236 ( .A(n69), .B(in2[17]), .S0(n266), .Y(n96) );
XNOR2X4TS U237 ( .A(n68), .B(in2[17]), .Y(n69) );
NOR2X8TS U238 ( .A(in2[7]), .B(in2[6]), .Y(n64) );
NOR3X8TS U239 ( .A(n290), .B(n280), .C(n76), .Y(n70) );
MXI2X4TS U240 ( .A(n117), .B(n116), .S0(n271), .Y(n122) );
XNOR2X1TS U241 ( .A(n186), .B(n185), .Y(res[29]) );
NOR2X4TS U242 ( .A(n153), .B(in1[26]), .Y(n196) );
MXI2X4TS U243 ( .A(n149), .B(n148), .S0(n271), .Y(n153) );
CLKXOR2X2TS U244 ( .A(n127), .B(in2[16]), .Y(n93) );
NOR2X1TS U245 ( .A(n161), .B(n160), .Y(n151) );
NAND4X6TS U246 ( .A(n127), .B(n126), .C(n131), .D(n125), .Y(n161) );
XOR2X1TS U247 ( .A(n218), .B(n217), .Y(res[24]) );
AOI21X4TS U248 ( .A0(n241), .A1(n61), .B0(n105), .Y(n106) );
NAND2X4TS U249 ( .A(n74), .B(n73), .Y(n280) );
NOR2X4TS U250 ( .A(n67), .B(in2[16]), .Y(n68) );
NOR2X2TS U251 ( .A(n225), .B(n226), .Y(n124) );
OAI21X2TS U252 ( .A0(n224), .A1(n226), .B0(n227), .Y(n123) );
INVX8TS U253 ( .A(n159), .Y(n182) );
INVX2TS U254 ( .A(n247), .Y(n97) );
INVX2TS U255 ( .A(in1[1]), .Y(n351) );
NOR2X2TS U256 ( .A(n342), .B(n341), .Y(n343) );
INVX2TS U257 ( .A(n212), .Y(n213) );
INVX2TS U258 ( .A(n211), .Y(n219) );
INVX4TS U259 ( .A(n205), .Y(n221) );
INVX2TS U260 ( .A(n183), .Y(n173) );
NAND2X2TS U261 ( .A(n127), .B(n109), .Y(n100) );
INVX2TS U262 ( .A(in2[9]), .Y(n73) );
INVX2TS U263 ( .A(n127), .Y(n67) );
INVX2TS U264 ( .A(n171), .Y(n172) );
NOR2XLTS U265 ( .A(n290), .B(in2[8]), .Y(n291) );
OR2X4TS U266 ( .A(n96), .B(in1[17]), .Y(n60) );
NAND2X2TS U267 ( .A(n104), .B(in1[19]), .Y(n242) );
NOR2X4TS U268 ( .A(n122), .B(in1[22]), .Y(n226) );
INVX2TS U269 ( .A(n235), .Y(n121) );
INVX2TS U270 ( .A(n232), .Y(n120) );
NAND2X2TS U271 ( .A(n122), .B(in1[22]), .Y(n227) );
CLKBUFX2TS U272 ( .A(n222), .Y(n223) );
NAND2X2TS U273 ( .A(n154), .B(in1[27]), .Y(n197) );
NOR2X4TS U274 ( .A(n157), .B(in1[28]), .Y(n191) );
NAND2X2TS U275 ( .A(n144), .B(n201), .Y(n190) );
NAND2X2TS U276 ( .A(n157), .B(in1[28]), .Y(n192) );
INVX2TS U277 ( .A(n170), .Y(n184) );
NOR2X2TS U278 ( .A(n163), .B(in1[29]), .Y(n170) );
NAND2X2TS U279 ( .A(n163), .B(in1[29]), .Y(n183) );
NAND2X1TS U280 ( .A(n331), .B(n330), .Y(n334) );
XOR2X1TS U281 ( .A(n346), .B(in1[9]), .Y(n347) );
AOI21X1TS U282 ( .A0(n345), .A1(n344), .B0(n343), .Y(n348) );
NAND2X1TS U283 ( .A(n342), .B(n341), .Y(n344) );
OAI21XLTS U284 ( .A0(n337), .A1(in1[12]), .B0(n335), .Y(n336) );
NAND2X1TS U285 ( .A(n257), .B(n256), .Y(n259) );
NAND2X1TS U286 ( .A(n252), .B(n59), .Y(n253) );
NAND2X1TS U287 ( .A(n250), .B(n55), .Y(n251) );
XNOR2X1TS U288 ( .A(n249), .B(n248), .Y(res[17]) );
NAND2X1TS U289 ( .A(n247), .B(n60), .Y(n248) );
NAND2X1TS U290 ( .A(n61), .B(n242), .Y(n243) );
AOI21X1TS U291 ( .A0(n240), .A1(n63), .B0(n241), .Y(n244) );
NAND2X1TS U292 ( .A(n236), .B(n235), .Y(n237) );
NAND2X1TS U293 ( .A(n219), .B(n212), .Y(n220) );
AOI21X2TS U294 ( .A0(n221), .A1(n219), .B0(n213), .Y(n218) );
INVX2TS U295 ( .A(n214), .Y(n216) );
AOI21X2TS U296 ( .A0(n221), .A1(n207), .B0(n206), .Y(n210) );
INVX2TS U297 ( .A(n182), .Y(n186) );
AND2X2TS U298 ( .A(n56), .B(n180), .Y(n58) );
AO21X4TS U299 ( .A0(n254), .A1(n59), .B0(n90), .Y(n53) );
OA21X4TS U300 ( .A0(n189), .A1(n191), .B0(n192), .Y(n54) );
OR2X4TS U301 ( .A(in2[11]), .B(in2[10]), .Y(n76) );
NAND4X8TS U302 ( .A(n268), .B(n66), .C(n65), .D(n64), .Y(n290) );
OAI2BB1X1TS U303 ( .A0N(in1[12]), .A1N(n337), .B0(n336), .Y(n340) );
XOR2XLTS U304 ( .A(n337), .B(in1[12]), .Y(n288) );
NAND3X2TS U305 ( .A(n74), .B(n73), .C(n72), .Y(n75) );
XOR2XLTS U306 ( .A(n259), .B(n258), .Y(res[14]) );
XNOR2X1TS U307 ( .A(n254), .B(n253), .Y(res[15]) );
NOR2X8TS U308 ( .A(in2[0]), .B(in2[1]), .Y(n268) );
MXI2X8TS U309 ( .A(n71), .B(n72), .S0(n271), .Y(n337) );
AOI21X2TS U310 ( .A0(n62), .A1(n206), .B0(n139), .Y(n140) );
INVX2TS U311 ( .A(n255), .Y(n257) );
INVX2TS U312 ( .A(n191), .Y(n193) );
NAND2X1TS U313 ( .A(n63), .B(n245), .Y(n246) );
XNOR2X1TS U314 ( .A(n240), .B(n246), .Y(res[18]) );
INVX2TS U315 ( .A(in2[8]), .Y(n74) );
NOR2X2TS U316 ( .A(in2[12]), .B(in2[13]), .Y(n85) );
NOR3X8TS U317 ( .A(n81), .B(in2[15]), .C(in2[14]), .Y(n127) );
XOR2X4TS U318 ( .A(n86), .B(in2[12]), .Y(n71) );
AND2X8TS U319 ( .A(n337), .B(in1[12]), .Y(n80) );
NOR3X4TS U320 ( .A(n290), .B(n76), .C(n75), .Y(n77) );
XNOR2X4TS U321 ( .A(n77), .B(in2[13]), .Y(n78) );
OR2X8TS U322 ( .A(n338), .B(in1[13]), .Y(n79) );
AOI21X4TS U323 ( .A0(n80), .A1(n79), .B0(n57), .Y(n258) );
INVX2TS U324 ( .A(in2[14]), .Y(n84) );
OAI21X4TS U325 ( .A0(n258), .A1(n255), .B0(n256), .Y(n254) );
MX2X4TS U326 ( .A(n88), .B(in2[15]), .S0(n266), .Y(n89) );
INVX2TS U327 ( .A(in2[16]), .Y(n92) );
MXI2X4TS U328 ( .A(n93), .B(n92), .S0(n320), .Y(n94) );
AOI21X4TS U329 ( .A0(n60), .A1(n249), .B0(n97), .Y(n239) );
INVX2TS U330 ( .A(in2[18]), .Y(n101) );
OAI21X4TS U331 ( .A0(n239), .A1(n107), .B0(n106), .Y(n222) );
XNOR2X4TS U332 ( .A(n110), .B(in2[21]), .Y(n111) );
INVX2TS U333 ( .A(in2[20]), .Y(n112) );
INVX2TS U334 ( .A(in2[22]), .Y(n116) );
AOI21X4TS U335 ( .A0(n121), .A1(n51), .B0(n120), .Y(n224) );
AOI21X4TS U336 ( .A0(n222), .A1(n124), .B0(n123), .Y(n204) );
XNOR2X1TS U337 ( .A(n128), .B(in2[25]), .Y(n129) );
NOR3BX2TS U338 ( .AN(n131), .B(n130), .C(in2[22]), .Y(n132) );
INVX2TS U339 ( .A(in2[24]), .Y(n134) );
MXI2X4TS U340 ( .A(n135), .B(n134), .S0(n271), .Y(n137) );
OAI21X4TS U341 ( .A0(n212), .A1(n214), .B0(n215), .Y(n206) );
OAI21X4TS U342 ( .A0(n204), .A1(n141), .B0(n140), .Y(n187) );
INVX2TS U343 ( .A(in2[26]), .Y(n148) );
OR2X2TS U344 ( .A(n150), .B(in2[27]), .Y(n160) );
XNOR2X1TS U345 ( .A(n151), .B(in2[28]), .Y(n152) );
AOI21X4TS U346 ( .A0(n156), .A1(n144), .B0(n155), .Y(n189) );
OAI2BB1X4TS U347 ( .A0N(n187), .A1N(n158), .B0(n54), .Y(n159) );
NOR3X4TS U348 ( .A(n161), .B(in2[28]), .C(n160), .Y(n164) );
XNOR2X1TS U349 ( .A(n164), .B(in2[29]), .Y(n162) );
OAI21X4TS U350 ( .A0(n182), .A1(n170), .B0(n183), .Y(n169) );
XOR2X1TS U351 ( .A(n176), .B(in2[30]), .Y(n165) );
XNOR2X2TS U352 ( .A(n169), .B(n168), .Y(res[30]) );
OAI21X4TS U353 ( .A0(n182), .A1(n175), .B0(n174), .Y(n181) );
XNOR2X1TS U354 ( .A(n177), .B(in2[31]), .Y(n178) );
XOR2X2TS U355 ( .A(n181), .B(n58), .Y(res[31]) );
OAI2BB1X4TS U356 ( .A0N(n56), .A1N(n181), .B0(n180), .Y(res[32]) );
BUFX3TS U357 ( .A(n187), .Y(n188) );
OAI21X4TS U358 ( .A0(n203), .A1(n196), .B0(n200), .Y(n199) );
XNOR2X2TS U359 ( .A(n199), .B(n198), .Y(res[27]) );
XOR2X1TS U360 ( .A(n203), .B(n202), .Y(res[26]) );
BUFX3TS U361 ( .A(n204), .Y(n205) );
XNOR2X1TS U362 ( .A(n221), .B(n220), .Y(res[23]) );
XNOR2X1TS U363 ( .A(n251), .B(n53), .Y(res[16]) );
XOR2X1TS U364 ( .A(in2[0]), .B(in2[1]), .Y(n260) );
MXI2X2TS U365 ( .A(n260), .B(in2[1]), .S0(n320), .Y(n349) );
XNOR2X1TS U366 ( .A(n351), .B(n349), .Y(n261) );
INVX2TS U367 ( .A(in2[2]), .Y(n270) );
NAND2X1TS U368 ( .A(n268), .B(n270), .Y(n263) );
XNOR2X1TS U369 ( .A(n299), .B(n300), .Y(n262) );
MXI2X4TS U370 ( .A(n262), .B(n299), .S0(n320), .Y(n329) );
INVX2TS U371 ( .A(in1[2]), .Y(n362) );
XOR2X1TS U372 ( .A(in2[3]), .B(n263), .Y(n267) );
INVX2TS U373 ( .A(in2[3]), .Y(n264) );
NAND2X1TS U374 ( .A(n271), .B(n264), .Y(n265) );
OA21X2TS U375 ( .A0(n267), .A1(n266), .B0(n265), .Y(n274) );
XNOR2X1TS U376 ( .A(n268), .B(n270), .Y(n269) );
NAND2X1TS U377 ( .A(n269), .B(add_sub), .Y(n273) );
NAND2X1TS U378 ( .A(n271), .B(n270), .Y(n272) );
XNOR2X1TS U379 ( .A(n328), .B(in1[4]), .Y(n279) );
INVX2TS U380 ( .A(in1[4]), .Y(n276) );
NAND2X1TS U381 ( .A(n329), .B(n276), .Y(n277) );
NOR2X1TS U382 ( .A(n290), .B(n280), .Y(n284) );
INVX2TS U383 ( .A(in2[10]), .Y(n285) );
NAND2X1TS U384 ( .A(n284), .B(n285), .Y(n281) );
XNOR2X1TS U385 ( .A(n281), .B(in2[11]), .Y(n283) );
INVX2TS U386 ( .A(in2[11]), .Y(n282) );
MXI2X2TS U387 ( .A(n283), .B(n282), .S0(n320), .Y(n296) );
NOR2X1TS U388 ( .A(n296), .B(in1[11]), .Y(n287) );
XOR2X1TS U389 ( .A(n284), .B(in2[10]), .Y(n286) );
MXI2X4TS U390 ( .A(n286), .B(n285), .S0(n320), .Y(n316) );
OAI2BB2X2TS U391 ( .B0(n287), .B1(n313), .A0N(in1[11]), .A1N(n296), .Y(n335)
);
XOR2X1TS U392 ( .A(n290), .B(in2[8]), .Y(n289) );
MXI2X4TS U393 ( .A(in2[8]), .B(n289), .S0(add_sub), .Y(n342) );
INVX2TS U394 ( .A(in1[8]), .Y(n341) );
XNOR2X1TS U395 ( .A(n291), .B(in2[9]), .Y(n292) );
NAND2BX1TS U396 ( .AN(in1[9]), .B(n346), .Y(n294) );
INVX2TS U397 ( .A(n346), .Y(n293) );
AOI22X2TS U398 ( .A0(n343), .A1(n294), .B0(n293), .B1(in1[9]), .Y(n311) );
INVX2TS U399 ( .A(in2[6]), .Y(n317) );
XOR2X1TS U400 ( .A(n318), .B(in2[6]), .Y(n301) );
MXI2X4TS U401 ( .A(n317), .B(n301), .S0(add_sub), .Y(n354) );
XNOR2X1TS U402 ( .A(n302), .B(in2[5]), .Y(n304) );
INVX2TS U403 ( .A(in2[5]), .Y(n303) );
MXI2X2TS U404 ( .A(n304), .B(n303), .S0(n320), .Y(n332) );
OAI2BB2X2TS U405 ( .B0(n305), .B1(n330), .A0N(in1[5]), .A1N(n332), .Y(n353)
);
XNOR2X1TS U406 ( .A(n353), .B(in1[6]), .Y(n309) );
INVX2TS U407 ( .A(in1[6]), .Y(n306) );
NAND2X1TS U408 ( .A(n354), .B(n306), .Y(n307) );
NAND2X2TS U409 ( .A(n354), .B(in1[6]), .Y(n355) );
OAI21X1TS U410 ( .A0(n354), .A1(n309), .B0(n308), .Y(res[6]) );
INVX2TS U411 ( .A(in1[10]), .Y(n310) );
NAND2X1TS U412 ( .A(n316), .B(n310), .Y(n312) );
XNOR2X1TS U413 ( .A(n319), .B(in2[7]), .Y(n322) );
INVX2TS U414 ( .A(in2[7]), .Y(n321) );
MXI2X2TS U415 ( .A(n322), .B(n321), .S0(n320), .Y(n357) );
OAI2BB2X4TS U416 ( .B0(n323), .B1(n355), .A0N(in1[7]), .A1N(n357), .Y(n345)
);
XNOR2X1TS U417 ( .A(n345), .B(in1[8]), .Y(n326) );
MXI2X1TS U418 ( .A(n324), .B(n343), .S0(n345), .Y(n325) );
OAI21X1TS U419 ( .A0(n327), .A1(n326), .B0(n325), .Y(res[8]) );
XNOR2X1TS U420 ( .A(n332), .B(in1[5]), .Y(n333) );
XNOR2X1TS U421 ( .A(n334), .B(n333), .Y(res[5]) );
XNOR2X1TS U422 ( .A(n338), .B(in1[13]), .Y(n339) );
XNOR2X1TS U423 ( .A(n340), .B(n339), .Y(res[13]) );
XOR2X1TS U424 ( .A(n362), .B(n361), .Y(n352) );
XNOR2X1TS U425 ( .A(n363), .B(n352), .Y(res[2]) );
OAI21X1TS U426 ( .A0(n354), .A1(in1[6]), .B0(n353), .Y(n356) );
NAND2X1TS U427 ( .A(n356), .B(n355), .Y(n359) );
XNOR2X1TS U428 ( .A(n357), .B(in1[7]), .Y(n358) );
XNOR2X1TS U429 ( .A(n359), .B(n358), .Y(res[7]) );
OA21XLTS U430 ( .A0(in2[0]), .A1(in1[0]), .B0(n360), .Y(res[0]) );
initial $sdf_annotate("Approx_adder_ACAIIN16Q4_syn.sdf");
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:49:19 05/27/2016
// Design Name:
// Module Name: prueba_lectura_rtc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module prueba_lectura_rtc_2
(
input wire clk, reset,
input wire sw,
inout [7:0]dato,
output wire AD, CS, WR, RD,
output [7:0] RGB,
output hsync, vsync
);
//Conexiones internas
reg [7:0]in_port;
wire [7:0]out_port;
wire [7:0]port_id;
wire write_strobe;
wire k_write_strobe;
wire read_strobe;
wire interrupt;
// conexiones banco de registros a VGA
wire [7:0]out_seg_hora,out_min_hora,out_hora_hora;
wire [7:0]out_dia_fecha,out_mes_fecha,out_jahr_fecha;
wire [7:0]out_seg_timer,out_min_timer,out_hora_timer;
///////////////////////////// hold's
wire hold_seg_hora;
wire hold_min_hora;
wire hold_hora_hora;
wire hold_dia_fecha;
wire hold_mes_fecha;
wire hold_jahr_fecha;
wire hold_dia_semana;
wire hold_seg_timer;
wire hold_min_timer;
wire hold_hora_timer;
// wire hold_banderas_config;
//////////////////////
//Conexiones de controlador RTC
wire fin_lectura_escritura;
wire [7:0] out_dato;
assign interrupt = 1'b0;
wire wire_sw;
assign wire_sw = {7'b0,sw};
microcontrolador instancia_microcontrolador
(
.clk(clk),
.reset(reset),
.interrupt(interrupt),
.in_port(in_port),
.write_strobe(write_strobe),
.k_write_strobe(k_write_strobe),
.read_strobe(read_strobe),
.interrupt_ack(),
.port_id(port_id),
.out_port(out_port)
);
controlador_VGA instancia_controlador_VGA
(
.clock(clk),
.reset(reset),
.digit0_HH(out_hora_hora[3:0]), .digit1_HH(out_hora_hora[7:4]), .digit0_MM(out_min_hora[3:0]), .digit1_MM(out_min_hora[7:4]), .digit0_SS(out_seg_hora[3:0]), .digit1_SS(out_seg_hora[7:4]),//
.digit0_DAY(out_dia_fecha[3:0]), .digit1_DAY(out_dia_fecha[7:4]), .digit0_MES(out_mes_fecha[3:0]), .digit1_MES(out_mes_fecha[7:4]), .digit0_YEAR(out_jahr_fecha[3:0]), .digit1_YEAR(out_jahr_fecha[7:4]),//
.digit0_HH_T(out_hora_timer[3:0]), .digit1_HH_T(out_hora_timer[7:4]), .digit0_MM_T(out_min_timer[3:0]), .digit1_MM_T(out_min_timer[7:4]), .digit0_SS_T(out_seg_timer[3:0]), .digit1_SS_T(out_seg_timer[7:4]),//Decenas y unidades para los números en pantalla (18 inputs de 3 bits)
.AM_PM(1'b0),
.config_mode(2'b0),
.cursor_location(2'b0),
.formato_hora(1'b1),
.estado_alarma(1'b0),
.hsync(hsync),
.vsync(vsync),
.RGB(RGB)
);
memoria_registros_VGA instancia_memoria_registros_VGA
(
.clk(clk),
.reset(reset),
.cs_seg_hora(1'b0),
.cs_min_hora(1'b0),
.cs_hora_hora(1'b0),
.cs_dia_fecha(1'b0),
.cs_mes_fecha(1'b0),
.cs_jahr_fecha(1'b0),
.cs_seg_timer(1'b0),
.cs_min_timer(1'b0),
.cs_hora_timer(1'b0),
.hold_seg_hora(hold_seg_hora),
.hold_min_hora(hold_min_hora),
.hold_hora_hora(hold_hora_hora),
.hold_dia_fecha(hold_dia_fecha),
.hold_mes_fecha(hold_mes_fecha),
.hold_jahr_fecha(hold_jahr_fecha),
.hold_seg_timer(hold_seg_timer),
.hold_min_timer(hold_min_timer),
.hold_hora_timer(hold_hora_timer),
.hold_banderas_config(1'b1),
.data_PicoBlaze(out_port),
.count_seg_hora(8'b0),
.count_min_hora(8'b0),
.count_hora_hora(8'b0),
.count_dia_fecha(8'b0),
.count_mes_fecha(8'b0),
.count_jahr_fecha(8'b0),
.count_seg_timer(8'b0),
.count_min_timer(8'b0),
.count_hora_timer(8'b0),
.out_seg_hora(out_seg_hora),
.out_min_hora(out_min_hora),
.out_hora_hora(out_hora_hora),
.out_dia_fecha(out_dia_fecha),
.out_mes_fecha(out_mes_fecha),
.out_jahr_fecha(out_jahr_fecha),
.out_seg_timer(out_seg_timer),
.out_min_timer(out_min_timer),
.out_hora_timer(out_hora_timer),
.out_banderas_config()
);
deco_hold_registros instancia_deco_hold_registros (
.write_strobe(write_strobe),
.port_id(port_id),
.hold_seg_hora(hold_seg_hora),
.hold_min_hora(hold_min_hora),
.hold_hora_hora(hold_hora_hora),
.hold_dia_fecha(hold_dia_fecha),
.hold_mes_fecha(hold_mes_fecha),
.hold_jahr_fecha(hold_jahr_fecha),
.hold_seg_timer(hold_seg_timer),
.hold_min_timer(hold_min_timer),
.hold_hora_timer(hold_hora_timer)
);
escritor_lector_rtc_2 instancia_escritor_lector_rtc_2 (
.clk(clk),
.reset(reset),
.in_dato(out_port),
.port_id(port_id),
.write_strobe(write_strobe),
.k_write_strobe(k_write_strobe),
.read_strobe(read_strobe),
.reg_a_d(AD),
.reg_cs(CS),
.reg_rd(RD),
.reg_wr(WR),
.out_dato(out_dato),
.flag_done(fin_lectura_escritura),
.dato(dato)
);
//Decodificación del puerto de entrada del microcontrolador
always@(posedge clk)
begin
case (port_id)
8'h0F : in_port <= fin_lectura_escritura;
8'h10 : in_port <= out_dato;
8'h02 : in_port <= wire_sw;
default : in_port <= 8'bXXXXXXXX;
endcase
end
endmodule
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: Ram_Real.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 us / 1 ps
// synopsys translate_on
module Ram_Real (
address,
byteena,
clock,
data,
wren,
q);
input [9:0] address;
input [3:0] byteena;
input clock;
input [31:0] data;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (address),
.byteena_a (byteena),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "TRUE",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "TRUE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: byteena 0 0 4 0 INPUT VCC "byteena[3..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL Ram_Real.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Ram_Real.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Ram_Real.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Ram_Real.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Ram_Real_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Ram_Real_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
module ClkRecoverSetCounter_tb ();
parameter TARGET_PERIOD = 10;
reg clk; // System clock
reg rst; // Reset; synchronous and active high
reg en; // Enable bit
reg [7:0] dataIn; // Data to transmit
reg writeStrobe; // Write data to transmit FIFO
wire dataPresent; // FIFO has data still in it
wire halfFull; // FIFO halfway full
wire full; // FIFO is completely full. Don't write to it.
wire tx; // Transmit bit
wire clkStrobe; ///< Recovered clock strobe
wire rxClocked; ///< Synchronized rx data
integer i;
integer enCounter;
always #1 clk = ~clk;
always @(posedge clk) begin
if (enCounter == TARGET_PERIOD-1) begin
enCounter <= 'd0;
en <= 1'b1;
end
else begin
enCounter <= enCounter + 1;
en <= 1'b0;
end
end
initial begin
clk = 1'b0;
rst = 1'b1;
en = 1'b0;
enCounter = 'd0;
dataIn = 'd0;
writeStrobe = 1'b0;
@(posedge clk)
@(posedge clk)
rst = 1'b0;
for (i=0; i<50000; i=i+1) begin
wait(~full);
@(posedge clk) dataIn <= $random(); writeStrobe = 1'b1;
@(posedge clk) writeStrobe = 1'b0;
@(posedge clk);
end
$stop(2);
end
Tx8b10b #(
.FILL_WORD_RD0(10'b0011111010), // Send when no data present & RD=-1
.FILL_WORD_RD1(10'b1100000101), // Send when no data present & RD=1
.FILL_WORD_FLIP(1'b1), // Flip status of Running Disparity when using fill word
.LOG2_DEPTH(4) // log2(depth of FIFO buffer). Must be an integer.
)
txTest (
.clk(clk), // System clock
.rst(rst), // Reset, synchronous and active high
.en(en), // Enable strobe for transmitting
.dataIn(dataIn), // [7:0] Data to transmit
.writeStrobe(writeStrobe), // Write data to transmit FIFO
.dataPresent(dataPresent), // FIFO has data still in it
.halfFull(halfFull), // FIFO halfway full
.full(full), // FIFO is completely full. Don't write to it.
.tx(tx) // Transmit bit
);
ClkRecoverSetCounter #(
.TARGET_PERIOD(TARGET_PERIOD) ///< Expected # clks for recovered clock
)
uut (
// Inputs
.clk(clk), ///< System clock
.rst(rst), ///< Reset, synchronous and active high
.rx(tx), ///< Input serial signal
// Outputs
.clkStrobe(clkStrobe), ///< Recovered clock strobe
.rxClocked(rxClocked) ///< Synchronized rx data
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAHCIN_PP_SYMBOL_V
`define SKY130_FD_SC_HD__FAHCIN_PP_SYMBOL_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__fahcin (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAHCIN_PP_SYMBOL_V
|
/*
* Copyright (c) 2008 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
`include "defines.v"
module regfile (
`ifdef DEBUG
output [15:0] ax,
output [15:0] dx,
output [15:0] bp,
output [15:0] si,
output [15:0] es,
`endif
output [15:0] a,
output [15:0] b,
output [15:0] c,
output [15:0] cs,
output [15:0] ip,
input [31:0] d,
output [15:0] s,
output reg [8:0] flags,
input wr,
input wrfl,
input wrhi,
input clk,
input rst,
input [ 3:0] addr_a,
input [ 3:0] addr_b,
input [ 3:0] addr_c,
input [ 3:0] addr_d,
input [ 1:0] addr_s,
input [ 8:0] iflags,
input word_op,
input a_byte,
input b_byte,
input c_byte,
output cx_zero,
input wr_ip0
);
// Net declarations
reg [15:0] r[15:0];
wire [7:0] a8, b8, c8;
// Assignments
`ifdef DEBUG
assign ax = r[0];
assign dx = r[2];
assign bp = r[5];
assign si = r[6];
assign es = r[8];
`endif
assign a = (a_byte & ~addr_a[3]) ? { {8{a8[7]}}, a8} : r[addr_a];
assign a8 = addr_a[2] ? r[addr_a[1:0]][15:8] : r[addr_a][7:0];
assign b = (b_byte & ~addr_b[3]) ? { {8{b8[7]}}, b8} : r[addr_b];
assign b8 = addr_b[2] ? r[addr_b[1:0]][15:8] : r[addr_b][7:0];
assign c = (c_byte & ~addr_c[3]) ? { {8{c8[7]}}, c8} : r[addr_c];
assign c8 = addr_c[2] ? r[addr_c[1:0]][15:8] : r[addr_c][7:0];
assign s = r[{2'b10,addr_s}];
assign cs = r[9];
assign cx_zero = (addr_d==4'd1) ? (d==16'd0) : (r[1]==16'd0);
assign ip = r[15];
// Behaviour
always @(posedge clk)
if (rst) begin
r[0] <= 16'd0; r[1] <= 16'd0;
r[2] <= 16'd0; r[3] <= 16'd0;
r[4] <= 16'd0; r[5] <= 16'd0;
r[6] <= 16'd0; r[7] <= 16'd0;
r[8] <= 16'd0; r[9] <= 16'hf000;
r[10] <= 16'd0; r[11] <= 16'd0;
r[12] <= 16'd0; r[13] <= 16'd0;
r[14] <= 16'd0; r[15] <= 16'hfff0;
flags <= 9'd0;
end else
begin
if (wr) begin
if (word_op | addr_d[3:2]==2'b10)
r[addr_d] <= word_op ? d[15:0] : {{8{d[7]}},d[7:0]};
else if (addr_d[3]~^addr_d[2]) r[addr_d][7:0] <= d[7:0];
else r[{2'b0,addr_d[1:0]}][15:8] <= d[7:0];
end
if (wrfl) flags <= iflags;
if (wrhi) r[4'd2] <= d[31:16];
if (wr_ip0) r[14] <= ip;
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211AI_1_V
`define SKY130_FD_SC_LP__O211AI_1_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o211ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o211ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o211ai_1 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211AI_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EDFXBP_SYMBOL_V
`define SKY130_FD_SC_HD__EDFXBP_SYMBOL_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__edfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{control|Control Signals}}
input DE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EDFXBP_SYMBOL_V
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
* rcn bus master interface with 32 entry request buffer.
*
*/
module tawas_rcn_master_buf
(
input rst,
input clk,
input [68:0] rcn_in,
output [68:0] rcn_out,
input cs,
input [4:0] seq,
input wr,
input [3:0] mask,
input [23:0] addr,
input [31:0] wdata,
output full,
output rdone,
output wdone,
output [4:0] rsp_seq,
output [3:0] rsp_mask,
output [23:0] rsp_addr,
output [31:0] rsp_data
);
parameter MASTER_GROUP_8 = 0;
parameter DEPTH = 16; // max 64
reg [63:0] req_buf[(DEPTH - 1):0];
reg [5:0] write_ptr;
reg [5:0] read_ptr;
reg [6:0] req_cnt;
assign full = (req_cnt >= (DEPTH - 5));
wire req_push = cs && (req_cnt != DEPTH);
wire req_pop;
always @ (posedge clk or posedge rst)
if (rst)
req_cnt <= 7'd0;
else
case ({req_push, req_pop})
2'b10: req_cnt <= req_cnt + 7'd1;
2'd01: req_cnt <= req_cnt - 7'd1;
default: ;
endcase
always @ (posedge clk or posedge rst)
if (rst)
write_ptr <= 6'd0;
else if (req_push)
write_ptr <= (write_ptr == (DEPTH - 1)) ? 6'd0 : write_ptr + 6'd1;
always @ (posedge clk or posedge rst)
if (rst)
read_ptr <= 6'd0;
else if (req_pop)
read_ptr <= (read_ptr == (DEPTH - 1)) ? 6'd0 : read_ptr + 6'd1;
always @ (posedge clk)
if (req_push)
req_buf[write_ptr] <= {seq, wr, mask[3:0], addr[23:2], wdata[31:0]};
wire req_vld = (req_cnt != 0);
wire [63:0] req = req_buf[read_ptr][63:0];
wire req_busy;
assign req_pop = req_vld && !req_busy;
tawas_rcn_master #(.MASTER_GROUP_8(MASTER_GROUP_8)) rcn_master
(
.rst(rst),
.clk(clk),
.rcn_in(rcn_in),
.rcn_out(rcn_out),
.cs(req_vld),
.seq(req[63:59]),
.busy(req_busy),
.wr(req[58]),
.mask(req[57:54]),
.addr({req[53:32], 2'd0}),
.wdata(req[31:0]),
.rdone(rdone),
.wdone(wdone),
.rsp_seq(rsp_seq),
.rsp_mask(rsp_mask),
.rsp_addr(rsp_addr),
.rsp_data(rsp_data)
);
endmodule
|
//top file
module Floating_Point_Addition(clk,reset,x,y);
input clk,reset;
input [31:0] x,y;
//???????????????
wire[8:0] exp_diff; //????????????
wire mux_1_en; //???1 ????
wire mux_2_en; //???2 ????
wire mux_3_en; //???3 ????
wire[7:0] mux_1_output; //???1 ?????
wire[31:0] mux_2_output; //???2 ?????
wire[31:0] mux_3_output; //???3 ?????
wire[7:0] shift_right_bit; //????????????????
wire[26:0] shift_right_output; //?????????
wire[27:0] big_alu_result; //????????????
wire[7:0] shift_right_bits; //?????????????
wire[7:0] shift_left_bits; //?????????????
wire shift_right_en; //???????????????
wire shift_left_en; //???????????????
wire[27:0] mux_4_output; //???4 ?????
wire mux_4_en; //???4 ????
wire[27:0] shift_left_right_output; //??????????????????
wire[7:0] incre_bit; //??????????
wire[7:0] decre_bit; //??????????
wire incre_en; //????????????
wire decre_en; //????????????
wire mux_5_en; //???5 ????
wire[7:0] mux_5_output; //???5 ?????
wire[7:0] rounding_exp_result; //????????????
wire[8:0] incre_decre_output; //??????????????
wire[27:0] fra_result; //????
wire[31:0] result;
wire overflow; //?????
//?????????????????
Small_Alu
Small_Alu_instance(
//????
clk,
reset,
x,
y,
//????
exp_diff //????????????????
);
//???
Control
Control_instance(
clk,
reset,
exp_diff,
big_alu_result,
fra_result,
shift_right_bits,
shift_left_bits,
shift_right_en,
shift_left_en,
shift_right_bit,
incre_bit,
decre_bit,
incre_en,
decre_en,
mux_1_en,
mux_2_en,
mux_3_en,
mux_4_en,
mux_5_en
);
//???1
Mux_1
Mux_1_instance(
clk,
reset,
x,
y,
mux_1_en,
mux_1_output
);
//???2
Mux_2
Mux_2_instance(
clk,
reset,
x,
y,
mux_2_en,
mux_2_output
);
//???3
Mux_3
Mux_3_instance(
clk,
reset,
x,
y,
mux_3_en,
mux_3_output
);
Shift_Right //????????????????
Shift_Right_instance(
clk,
reset,
shift_right_bit,
mux_2_output,
shift_right_output //??shift_right_bit??mux_2_output ????
);
//???????????
Big_Alu
Big_Alu_instance(
clk,
reset,
shift_right_output,
mux_3_output,
big_alu_result //mux_3_output ?shift_right_output ????????big_alu_result
);
//???4
Mux_4
Mux_4_instance(
clk,
reset,
mux_4_en,
big_alu_result,
fra_result,
mux_4_output
);
Shift_Left_Right //???????????
Shift_Left_Right_instance(
clk,
reset,
shift_left_bits,
shift_right_bits,
shift_left_en,
shift_right_en,
mux_4_output,
shift_left_right_output
);
//???5
Mux_5
Mux_5_instance(
clk,
reset,
mux_5_en,
mux_1_output,
rounding_exp_result,
mux_5_output
);
Incre_Decre //???????????
Incre_Decre_instance(
clk,
reset,
incre_bit,
decre_bit,
incre_en,
decre_en,
mux_5_output,
incre_decre_output //??incre_bit ?incre_en??mux_5_output??????decre_bit ?decre_en??mux_5_output ???
);
//??????
Rounding
Rounding_instance(
clk,
reset,
shift_left_right_output,
incre_decre_output,
rounding_exp_result,
fra_result, //????
result,
overflow //????
);
endmodule |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of rs_cfg_fe1
//
// Generated
// by: lutscher
// on: Wed Dec 14 16:43:27 2005
// cmd: /home/lutscher/work/MIX/mix_0.pl -strip -nodelta ../../reg_shell.sxc
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: lutscher $
// $Id: rs_cfg_fe1.v,v 1.8 2005/12/14 15:43:45 lutscher Exp $
// $Date: 2005/12/14 15:43:45 $
// $Log: rs_cfg_fe1.v,v $
// Revision 1.8 2005/12/14 15:43:45 lutscher
// updated
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.72 2005/11/30 14:01:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.43 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of rs_cfg_fe1
//
// No user `defines in this module
`define tie0_1_c 1'b0
module rs_cfg_fe1
//
// Generated module rs_cfg_fe1_i
//
(
input wire clk_f20,
input wire res_f20_n_i,
input wire test_i,
input wire [13:0] addr_i,
input wire trans_start,
input wire [31:0] wr_data_i,
input wire rd_wr_i,
output wire [31:0] rd_data_o,
output wire rd_err_o,
output wire trans_done_o,
output wire Cvbsdetect_par_o,
input wire Cvbsdetect_set_p_i,
input wire ycdetect_par_i,
input wire usr_r_test_par_i,
input wire usr_r_test_trans_done_p_i,
output reg usr_r_test_rd_p_o,
input wire [7:0] sha_r_test_par_i,
output wire [4:0] mvstart_par_o,
output reg [5:0] mvstop_par_o,
output wire [3:0] usr_rw_test_par_o,
input wire [3:0] usr_rw_test_par_i,
input wire usr_rw_test_trans_done_p_i,
output reg usr_rw_test_rd_p_o,
output reg usr_rw_test_wr_p_o,
output reg [31:0] sha_rw2_par_o,
output wire [15:0] wd_16_test_par_o,
output wire [7:0] wd_16_test2_par_o,
input wire upd_rw_en_i,
input wire upd_rw_force_i,
input wire upd_rw_i,
input wire upd_r_en_i,
input wire upd_r_force_i,
input wire upd_r_i
);
// Module parameters:
parameter sync = 0;
parameter cgtransp = 0;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire int_upd_r_p;
wire int_upd_rw_p;
wire tie0_1;
wire u6_sync_generic_i_trans_start_p;
wire u7_sync_rst_i_int_rst_n;
wire u8_ccgc_iwr_clk;
wire u8_ccgc_iwr_clk_en;
wire u9_ccgc_ishdw_clk;
wire u9_ccgc_ishdw_clk_en;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign tie0_1 = `tie0_1_c;
/*
Generator information:
used package Micronas::Reg is version 1.16
this module is version 1.20
*/
/*
local definitions
*/
`define REG_00_OFFS 0 // reg_0x0
`define REG_04_OFFS 1 // reg_0x4
`define REG_08_OFFS 2 // reg_0x8
`define REG_0C_OFFS 3 // reg_0xC
`define REG_10_OFFS 4 // reg_0x10
`define REG_14_OFFS 5 // reg_0x14
`define REG_18_OFFS 6 // reg_0x18
`define REG_1C_OFFS 7 // reg_0x1C
`define REG_20_OFFS 8 // reg_0x20
`define REG_28_OFFS 10 // reg_0x28
/*
local wire or register declarations
*/
reg [31:0] REG_00;
reg [31:0] REG_04;
reg [31:0] REG_08;
reg [7:0] sha_r_test_shdw;
reg [31:0] REG_0C;
wire [5:0] mvstop_shdw;
reg [31:0] REG_10;
reg [31:0] REG_14;
wire [31:0] sha_rw2_shdw;
reg [31:0] REG_18;
reg [31:0] REG_1C;
reg [31:0] REG_20;
reg [31:0] REG_28;
reg int_upd_rw;
reg int_upd_r;
wire wr_p;
wire rd_p;
reg int_trans_done;
wire [3:0] iaddr;
wire addr_overshoot;
wire trans_done_p;
reg rd_done_p;
reg wr_done_p;
reg fwd_txn;
wire [1:0] fwd_decode_vec;
wire [1:0] fwd_done_vec;
reg [31:0] mux_rd_data;
reg mux_rd_err;
/*
local wire and output assignments
*/
assign Cvbsdetect_par_o = REG_04[0];
assign mvstop_shdw = REG_0C[10:5];
assign mvstart_par_o = REG_0C[4:0];
assign sha_rw2_shdw = REG_14;
assign wd_16_test_par_o = REG_18[15:0];
assign wd_16_test2_par_o = REG_1C[7:0];
assign usr_rw_test_par_o = wr_data_i[14:11];
// clip address to decoded range
assign iaddr = addr_i[5:2];
assign addr_overshoot = |addr_i[13:6];
/*
clock enable signals
*/
assign u8_ccgc_iwr_clk_en = wr_p; // write-clock enable
assign u9_ccgc_ishdw_clk_en = int_upd_rw | int_upd_r; // shadow-clock enable
// write txn start pulse
assign wr_p = ~rd_wr_i & u6_sync_generic_i_trans_start_p;
// read txn start pulse
assign rd_p = rd_wr_i & u6_sync_generic_i_trans_start_p;
/*
generate txn done signals
*/
assign fwd_done_vec = {usr_r_test_trans_done_p_i, usr_rw_test_trans_done_p_i}; // ack for forwarded txns
assign trans_done_p = ((wr_done_p | rd_done_p) & ~fwd_txn) | ((fwd_done_vec != 0) & fwd_txn);
always @(posedge clk_f20 or negedge u7_sync_rst_i_int_rst_n) begin
if (~u7_sync_rst_i_int_rst_n) begin
int_trans_done <= 0;
wr_done_p <= 0;
rd_done_p <= 0;
end
else begin
wr_done_p <= wr_p;
rd_done_p <= rd_p;
if (trans_done_p)
int_trans_done <= ~int_trans_done;
end
end
assign trans_done_o = int_trans_done;
/*
write process
*/
always @(posedge u8_ccgc_iwr_clk or negedge u7_sync_rst_i_int_rst_n) begin
if (~u7_sync_rst_i_int_rst_n) begin
REG_0C[10:5] <= 'hc;
REG_0C[4:0] <= 'h7;
REG_14 <= 'h0;
REG_18[15:0] <= 'ha;
REG_1C[7:0] <= 'hff;
end
else begin
case (iaddr)
`REG_0C_OFFS: begin
REG_0C[10:5] <= wr_data_i[10:5];
REG_0C[4:0] <= wr_data_i[4:0];
end
`REG_14_OFFS: begin
REG_14 <= wr_data_i;
end
`REG_18_OFFS: begin
REG_18[15:0] <= wr_data_i[15:0];
end
`REG_1C_OFFS: begin
REG_1C[7:0] <= wr_data_i[7:0];
end
endcase
end
end
/*
write process for status registers
*/
always @(posedge clk_f20 or negedge u7_sync_rst_i_int_rst_n) begin
if (~u7_sync_rst_i_int_rst_n) begin
REG_04[0] <= 'h0;
end
else begin
if (Cvbsdetect_set_p_i)
REG_04[0] <= 1;
else if (wr_p && iaddr == `REG_04_OFFS)
REG_04[0] <= REG_04[0] & ~wr_data_i[0];
end
end
/*
txn forwarding process
*/
// decode addresses of USR registers and read/write
assign fwd_decode_vec = {(iaddr == `REG_08_OFFS) & rd_wr_i, (iaddr == `REG_10_OFFS)};
always @(posedge clk_f20 or negedge u7_sync_rst_i_int_rst_n) begin
if (~u7_sync_rst_i_int_rst_n) begin
fwd_txn <= 0;
usr_r_test_rd_p_o <= 0;
usr_rw_test_rd_p_o <= 0;
usr_rw_test_wr_p_o <= 0;
end
else begin
usr_r_test_rd_p_o <= 0;
usr_rw_test_rd_p_o <= 0;
usr_rw_test_wr_p_o <= 0;
if (u6_sync_generic_i_trans_start_p) begin
fwd_txn <= |fwd_decode_vec; // set flag for forwarded txn
usr_r_test_rd_p_o <= fwd_decode_vec[1] & rd_wr_i;
usr_rw_test_rd_p_o <= fwd_decode_vec[0] & rd_wr_i;
usr_rw_test_wr_p_o <= fwd_decode_vec[0] & ~rd_wr_i;
end
else if (trans_done_p)
fwd_txn <= 0; // reset flag for forwarded transaction
end
end
/*
shadowing for update signal 'upd_rw'
*/
// generate internal update signal
always @(posedge clk_f20 or negedge u7_sync_rst_i_int_rst_n) begin
if (~u7_sync_rst_i_int_rst_n)
int_upd_rw <= 1;
else
int_upd_rw <= (int_upd_rw_p & upd_rw_en_i) | upd_rw_force_i;
end
// shadow process
always @(posedge u9_ccgc_ishdw_clk) begin
if (int_upd_rw) begin
mvstop_par_o <= mvstop_shdw;
sha_rw2_par_o <= sha_rw2_shdw;
end
end
/*
shadowing for update signal 'upd_r'
*/
// generate internal update signal
always @(posedge clk_f20 or negedge u7_sync_rst_i_int_rst_n) begin
if (~u7_sync_rst_i_int_rst_n)
int_upd_r <= 1;
else
int_upd_r <= (int_upd_r_p & upd_r_en_i) | upd_r_force_i;
end
// shadow process
always @(posedge u9_ccgc_ishdw_clk) begin
if (int_upd_r) begin
sha_r_test_shdw <= sha_r_test_par_i;
end
end
/*
read logic and mux process
*/
assign rd_data_o = mux_rd_data;
assign rd_err_o = mux_rd_err | addr_overshoot;
always @(REG_04 or REG_0C or REG_18 or iaddr or mvstop_shdw or sha_r_test_shdw or sha_rw2_shdw or usr_r_test_par_i or usr_rw_test_par_i or ycdetect_par_i) begin
mux_rd_err <= 0;
mux_rd_data <= 0;
case (iaddr)
`REG_04_OFFS : begin
mux_rd_data[0] <= REG_04[0];
end
`REG_08_OFFS : begin
mux_rd_data[1] <= ycdetect_par_i;
mux_rd_data[2] <= usr_r_test_par_i;
mux_rd_data[10:3] <= sha_r_test_shdw;
end
`REG_0C_OFFS : begin
mux_rd_data[4:0] <= REG_0C[4:0];
mux_rd_data[10:5] <= mvstop_shdw;
end
`REG_10_OFFS : begin
mux_rd_data[14:11] <= usr_rw_test_par_i;
end
`REG_14_OFFS : begin
mux_rd_data <= sha_rw2_shdw;
end
`REG_18_OFFS : begin
mux_rd_data[15:0] <= REG_18[15:0];
end
default: begin
mux_rd_err <= 1; // no decode
end
endcase
end
/*
checking code
*/
`ifdef ASSERT_ON
property p_pos_pulse_check (sig); // check for positive pulse
@(posedge clk_f20) disable iff (~u7_sync_rst_i_int_rst_n)
sig |=> ~sig;
endproperty
assert property(p_pos_pulse_check(Cvbsdetect_set_p_i));
assert property(p_pos_pulse_check(usr_r_test_trans_done_p_i));
assert property(p_pos_pulse_check(usr_rw_test_trans_done_p_i));
p_fwd_done_expected: assert property
(
@(posedge clk_f20) disable iff (~u7_sync_rst_i_int_rst_n)
usr_r_test_trans_done_p_i || usr_rw_test_trans_done_p_i |-> fwd_txn
);
p_fwd_done_onehot: assert property
(
@(posedge clk_f20) disable iff (~u7_sync_rst_i_int_rst_n)
usr_r_test_trans_done_p_i || usr_rw_test_trans_done_p_i |-> onehot(fwd_done_vec)
);
p_fwd_done_only_when_fwd_txn: assert property
(
@(posedge clk_f20) disable iff (~u7_sync_rst_i_int_rst_n)
fwd_done_vec != 0 |-> fwd_txn
);
function onehot (input [1:0] vec); // not built-in to SV yet
integer i,j;
begin
j = 0;
for (i=0; i<2; i=i+1) j = j + vec[i] ? 1 : 0;
onehot = (j==1) ? 1 : 0;
end
endfunction
`endif
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for u10_sync_generic_i
sync_generic #(
.act(1),
.kind(3),
.rstact(0),
.rstval(0),
.sync(1)
) u10_sync_generic_i ( // Synchronizer for update-signal upd_rw
.clk_r(clk_f20),
.clk_s(tie0_1),
.rcv_o(int_upd_rw_p),
.rst_r(res_f20_n_i),
.rst_s(tie0_1),
.snd_i(upd_rw_i)
);
// End of Generated Instance Port Map for u10_sync_generic_i
// Generated Instance Port Map for u11_sync_generic_i
sync_generic #(
.act(1),
.kind(3),
.rstact(0),
.rstval(0),
.sync(1)
) u11_sync_generic_i ( // Synchronizer for update-signal upd_r
.clk_r(clk_f20),
.clk_s(tie0_1),
.rcv_o(int_upd_r_p),
.rst_r(res_f20_n_i),
.rst_s(tie0_1),
.snd_i(upd_r_i)
);
// End of Generated Instance Port Map for u11_sync_generic_i
// Generated Instance Port Map for u6_sync_generic_i
sync_generic #(
.act(1),
.kind(2),
.rstact(0),
.rstval(0),
.sync(0)
) u6_sync_generic_i ( // Synchronizer for trans_done signal
.clk_r(clk_f20),
.clk_s(tie0_1),
.rcv_o(u6_sync_generic_i_trans_start_p),
.rst_r(res_f20_n_i),
.rst_s(tie0_1),
.snd_i(trans_start)
);
// End of Generated Instance Port Map for u6_sync_generic_i
// Generated Instance Port Map for u7_sync_rst_i
sync_rst #(
.act(0),
.sync(0)
) u7_sync_rst_i ( // Reset synchronizer
.clk_r(clk_f20),
.rst_i(res_f20_n_i),
.rst_o(u7_sync_rst_i_int_rst_n)
);
// End of Generated Instance Port Map for u7_sync_rst_i
// Generated Instance Port Map for u8_ccgc_i
ccgc #(
.cgtransp(cgtransp) // __W_ILLEGAL_PARAM
) u8_ccgc_i ( // Clock-gating cell for write-clock
.clk_i(clk_f20),
.clk_o(u8_ccgc_iwr_clk),
.enable_i(u8_ccgc_iwr_clk_en),
.test_i(test_i)
);
// End of Generated Instance Port Map for u8_ccgc_i
// Generated Instance Port Map for u9_ccgc_i
ccgc #(
.cgtransp(cgtransp) // __W_ILLEGAL_PARAM
) u9_ccgc_i ( // Clock-gating cell for shadow-clock
.clk_i(clk_f20),
.clk_o(u9_ccgc_ishdw_clk),
.enable_i(u9_ccgc_ishdw_clk_en),
.test_i(test_i)
);
// End of Generated Instance Port Map for u9_ccgc_i
endmodule
//
// End of Generated Module rtl of rs_cfg_fe1
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4B_4_V
`define SKY130_FD_SC_HDLL__NOR4B_4_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog wrapper for nor4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4b_4 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4b_4 (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4B_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLRTN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__DLRTN_BEHAVIORAL_PP_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__dlrtn (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire GATE ;
reg notifier ;
wire D_delayed ;
wire GATE_N_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (GATE , GATE_N_delayed );
sky130_fd_sc_hdll__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLRTN_BEHAVIORAL_PP_V |
`timescale 1ns/1ps
//TODO: create gold model
module linked_fifo_tb;
`define WIDTH 8
`define DEPTH 32
`define FIFOS 8
`define LOG2_FIFO log2(`FIFOS-1)
reg rst, clk;
reg push;
reg [2:0] push_fifo;
reg pop;
reg [2:0] pop_fifo;
reg [7:0] d;
wire [7:0] q;
wire empty;
wire full;
wire [3*8-1:0] count;
wire [7:0] q_gold;
wire empty_gold;
wire full_gold;
wire [3*8-1:0] count_gold;
wire almost_full;
//TODO: add free
linked_fifo #(`WIDTH, `DEPTH, `FIFOS) dut(rst, clk, push, push_fifo, pop, pop_fifo, d, q, empty, full,,almost_full);
linked_fifo_gold #(`WIDTH, `DEPTH, `FIFOS) gold(rst, clk, push, push_fifo, pop, pop_fifo, d, q_gold, empty_gold, full_gold,);
always @(posedge clk) begin
//if(almost_full)
// $display("almost full");
end
integer timeout;
integer i;
task print_linked_info;
begin
$display("linked_ram:");
for(i = 0; i < 16; i = i + 1)
$display("%d : %d", i, dut.linked_ram[i]);
$display("r_beg:");
for(i = 0; i < 8; i = i + 1)
$display("%d : %d", i, dut.r_beg[i]);
$display("r_end:");
for(i = 0; i < 8; i = i + 1)
$display("%d : %d", i, dut.r_end[i]);
end
endtask
initial begin
clk <= 0;
forever #5 clk=~clk;
end
initial begin
rst <= 1;
push <= 0;
push_fifo <= 0;
pop <= 0;
pop_fifo <= 0;
d <= 0;
#101 rst <= 0;
#1000 push <= 1;
$display("first push at %d", $time);
d <= 5;
#10 push <= 0;
#10 push <= 1;
d <= 6;
#10 push <= 0;
#30 pop <= 1;
#20 pop <= 0;
#100 push <= 1;
push_fifo <= 1;
d <= 1;
#10 push <= 0;
timeout = 0;
#10 push <= 1;
//TODO: display everything
#10 push <= 0;
$display("conituous push");
while(!full && timeout != 64) begin
push <= 1;
#10;
timeout = timeout+1;
end
$display("conituous push end");
push <= 0;
push_fifo <= 1;
d <= 1;
#10 push <= 0;
timeout = 0;
$display("conituous push");
while(!full && timeout != 8) begin
push <= 1;
#10;
timeout = timeout+1;
end
$display("conituous push end");
timeout = 0;
while(timeout != 8*64) begin
pop_fifo = pop_fifo + 1;
#1;
if(!empty)
pop = 1;
else
pop = 0;
#9 timeout = timeout + 1;
end
timeout = 0;
while(timeout != 1000*1000) begin
pop_fifo = $random;
push_fifo = $random;
d = $random;
#1 if(!full)
push = $random;
else
push = 0;
if(!empty)
pop = $random;
else
pop = 0;
#9 timeout = timeout + 1;
end
#100;
$display("finished NO ERRORS");
$finish;
end
reg [6:0] linked_ram_delay [0:2**6 - 1];
reg [3:0] r_beg_delay [0:7];
reg [3:0] r_end_delay [0:7];
reg pop_delay;
reg push_delay;
reg full_delay;
reg empty_delay;
always @(posedge clk) begin
pop_delay <= pop;
push_delay <= push;
full_delay <= full;
empty_delay <= empty;
for(i = 0; i < 2**6; i = i + 1)
linked_ram_delay[i] = dut.linked_ram[i];
for(i = 0; i < 8; i = i + 1)
r_beg_delay[i] = dut.r_beg[i];
for(i = 0; i < 8; i = i + 1)
r_end_delay[i] = dut.r_end[i];
end
always @(posedge clk) begin
if(dut.error == 1) begin
$display("ERROR:");
$display("delayed:");
$display("pop_delay: %H", pop_delay);
$display("push_delay: %H", push_delay);
$display("full_delay: %H", full_delay);
$display("empty_delay: %H", empty_delay);
$display("current:");
print_linked_info();
$finish;
end
end
//TODO: check
always @(posedge clk) begin
if(pop_delay && q != q_gold) begin
$display("ERROR: output does not match gold model at %d", $time);
$display("GOLD: %d ACTUAL: %d", q_gold, q);
end
if(pop_delay) begin
//$display("GOLD: %d ACTUAL: %d", q_gold, q);
end
end
endmodule
|
(** * Norm: Normalization of STLC *)
(* Chapter written and maintained by Andrew Tolmach *)
(** This optional chapter is based on chapter 12 of _Types and
Programming Languages_ (Pierce). It may be useful to look at the
two together, as that chapter includes explanations and informal
proofs that are not repeated here.
In this chapter, we consider another fundamental theoretical
property of the simply typed lambda-calculus: the fact that the
evaluation of a well-typed program is guaranteed to halt in a
finite number of steps---i.e., every well-typed term is
_normalizable_.
Unlike the type-safety properties we have considered so far, the
normalization property does not extend to full-blown programming
languages, because these languages nearly always extend the simply
typed lambda-calculus with constructs, such as general
recursion (see the [MoreStlc] chapter) or recursive types, that
can be used to write nonterminating programs. However, the issue
of normalization reappears at the level of _types_ when we
consider the metatheory of polymorphic versions of the lambda
calculus such as System F-omega: in this system, the language of
types effectively contains a copy of the simply typed
lambda-calculus, and the termination of the typechecking algorithm
will hinge on the fact that a "normalization" operation on type
expressions is guaranteed to terminate.
Another reason for studying normalization proofs is that they are
some of the most beautiful---and mind-blowing---mathematics to be
found in the type theory literature, often (as here) involving the
fundamental proof technique of _logical relations_.
The calculus we shall consider here is the simply typed
lambda-calculus over a single base type [bool] and with
pairs. We'll give most details of the development for the basic
lambda-calculus terms treating [bool] as an uninterpreted base
type, and leave the extension to the boolean operators and pairs
to the reader. Even for the base calculus, normalization is not
entirely trivial to prove, since each reduction of a term can
duplicate redexes in subterms. *)
(** **** Exercise: 2 starsM (norm_fail) *)
(** Where do we fail if we attempt to prove normalization by a
straightforward induction on the size of a well-typed term? *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 5 stars, recommended (norm) *)
(** The best ways to understand an intricate proof like this is
are (1) to help fill it in and (2) to extend it. We've left out some
parts of the following development, including some proofs of lemmas
and the all the cases involving products and conditionals. Fill them
in. *)
(** [] *)
(* ################################################################# *)
(** * Language *)
(** We begin by repeating the relevant language definition, which is
similar to those in the [MoreStlc] chapter, plus supporting
results including type preservation and step determinism. (We
won't need progress.) You may just wish to skip down to the
Normalization section... *)
(* ----------------------------------------------------------------- *)
(** *** Syntax and Operational Semantics *)
Require Import Coq.Lists.List.
Import ListNotations.
Require Import Maps.
Require Import Smallstep.
Hint Constructors multi.
Inductive ty : Type :=
| TBool : ty
| TArrow : ty -> ty -> ty
| TProd : ty -> ty -> ty
.
Inductive tm : Type :=
(* pure STLC *)
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
(* pairs *)
| tpair : tm -> tm -> tm
| tfst : tm -> tm
| tsnd : tm -> tm
(* booleans *)
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
(* i.e., [if t0 then t1 else t2] *)
(* ----------------------------------------------------------------- *)
(** *** Substitution *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar y => if beq_id x y then s else t
| tabs y T t1 =>
tabs y T (if beq_id x y then t1 else (subst x s t1))
| tapp t1 t2 => tapp (subst x s t1) (subst x s t2)
| tpair t1 t2 => tpair (subst x s t1) (subst x s t2)
| tfst t1 => tfst (subst x s t1)
| tsnd t1 => tsnd (subst x s t1)
| ttrue => ttrue
| tfalse => tfalse
| tif t0 t1 t2 =>
tif (subst x s t0) (subst x s t1) (subst x s t2)
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ----------------------------------------------------------------- *)
(** *** Reduction *)
Inductive value : tm -> Prop :=
| v_abs : forall x T11 t12,
value (tabs x T11 t12)
| v_pair : forall v1 v2,
value v1 ->
value v2 ->
value (tpair v1 v2)
| v_true : value ttrue
| v_false : value tfalse
.
Hint Constructors value.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T11 t12 v2,
value v2 ->
(tapp (tabs x T11 t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
(tapp t1 t2) ==> (tapp t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tapp v1 t2) ==> (tapp v1 t2')
(* pairs *)
| ST_Pair1 : forall t1 t1' t2,
t1 ==> t1' ->
(tpair t1 t2) ==> (tpair t1' t2)
| ST_Pair2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tpair v1 t2) ==> (tpair v1 t2')
| ST_Fst : forall t1 t1',
t1 ==> t1' ->
(tfst t1) ==> (tfst t1')
| ST_FstPair : forall v1 v2,
value v1 ->
value v2 ->
(tfst (tpair v1 v2)) ==> v1
| ST_Snd : forall t1 t1',
t1 ==> t1' ->
(tsnd t1) ==> (tsnd t1')
| ST_SndPair : forall v1 v2,
value v1 ->
value v2 ->
(tsnd (tpair v1 v2)) ==> v2
(* booleans *)
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t0 t0' t1 t2,
t0 ==> t0' ->
(tif t0 t1 t2) ==> (tif t0' t1 t2)
where "t1 '==>' t2" := (step t1 t2).
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
Hint Constructors step.
Notation step_normal_form := (normal_form step).
Lemma value__normal : forall t, value t -> step_normal_form t.
Proof with eauto.
intros t H; induction H; intros [t' ST]; inversion ST...
Qed.
(* ----------------------------------------------------------------- *)
(** *** Typing *)
Definition context := partial_map ty.
Inductive has_type : context -> tm -> ty -> Prop :=
(* Typing rules for proper terms *)
| T_Var : forall Gamma x T,
Gamma x = Some T ->
has_type Gamma (tvar x) T
| T_Abs : forall Gamma x T11 T12 t12,
has_type (update Gamma x T11) t12 T12 ->
has_type Gamma (tabs x T11 t12) (TArrow T11 T12)
| T_App : forall T1 T2 Gamma t1 t2,
has_type Gamma t1 (TArrow T1 T2) ->
has_type Gamma t2 T1 ->
has_type Gamma (tapp t1 t2) T2
(* pairs *)
| T_Pair : forall Gamma t1 t2 T1 T2,
has_type Gamma t1 T1 ->
has_type Gamma t2 T2 ->
has_type Gamma (tpair t1 t2) (TProd T1 T2)
| T_Fst : forall Gamma t T1 T2,
has_type Gamma t (TProd T1 T2) ->
has_type Gamma (tfst t) T1
| T_Snd : forall Gamma t T1 T2,
has_type Gamma t (TProd T1 T2) ->
has_type Gamma (tsnd t) T2
(* booleans *)
| T_True : forall Gamma,
has_type Gamma ttrue TBool
| T_False : forall Gamma,
has_type Gamma tfalse TBool
| T_If : forall Gamma t0 t1 t2 T,
has_type Gamma t0 TBool ->
has_type Gamma t1 T ->
has_type Gamma t2 T ->
has_type Gamma (tif t0 t1 t2) T
.
Hint Constructors has_type.
Hint Extern 2 (has_type _ (tapp _ _) _) => eapply T_App; auto.
Hint Extern 2 (_ = _) => compute; reflexivity.
(* ----------------------------------------------------------------- *)
(** *** Context Invariance *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
(* pairs *)
| afi_pair1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tpair t1 t2)
| afi_pair2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tpair t1 t2)
| afi_fst : forall x t,
appears_free_in x t ->
appears_free_in x (tfst t)
| afi_snd : forall x t,
appears_free_in x t ->
appears_free_in x (tsnd t)
(* booleans *)
| afi_if0 : forall x t0 t1 t2,
appears_free_in x t0 ->
appears_free_in x (tif t0 t1 t2)
| afi_if1 : forall x t0 t1 t2,
appears_free_in x t1 ->
appears_free_in x (tif t0 t1 t2)
| afi_if2 : forall x t0 t1 t2,
appears_free_in x t2 ->
appears_free_in x (tif t0 t1 t2)
.
Hint Constructors appears_free_in.
Definition closed (t:tm) :=
forall x, ~ appears_free_in x t.
Lemma context_invariance : forall Gamma Gamma' t S,
has_type Gamma t S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
has_type Gamma' t S.
Proof with eauto.
intros. generalize dependent Gamma'.
induction H;
intros Gamma' Heqv...
- (* T_Var *)
apply T_Var... rewrite <- Heqv...
- (* T_Abs *)
apply T_Abs... apply IHhas_type. intros y Hafi.
unfold update, t_update. destruct (beq_idP x y)...
- (* T_Pair *)
apply T_Pair...
- (* T_If *)
eapply T_If...
Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
has_type Gamma t T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros x t T Gamma Hafi Htyp.
induction Htyp; inversion Hafi; subst...
- (* T_Abs *)
destruct IHHtyp as [T' Hctx]... exists T'.
unfold update, t_update in Hctx.
rewrite false_beq_id in Hctx...
Qed.
Corollary typable_empty__closed : forall t T,
has_type empty t T ->
closed t.
Proof.
intros. unfold closed. intros x H1.
destruct (free_in_context _ _ _ _ H1 H) as [T' C].
inversion C. Qed.
(* ----------------------------------------------------------------- *)
(** *** Preservation *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
has_type (update Gamma x U) t S ->
has_type empty v U ->
has_type Gamma ([x:=v]t) S.
Proof with eauto.
(* Theorem: If Gamma,x:U |- t : S and empty |- v : U, then
Gamma |- ([x:=v]t) S. *)
intros Gamma x U v t S Htypt Htypv.
generalize dependent Gamma. generalize dependent S.
(* Proof: By induction on the term t. Most cases follow directly
from the IH, with the exception of tvar and tabs.
The former aren't automatic because we must reason about how the
variables interact. *)
induction t;
intros S Gamma Htypt; simpl; inversion Htypt; subst...
- (* tvar *)
simpl. rename i into y.
(* If t = y, we know that
[empty |- v : U] and
[Gamma,x:U |- y : S]
and, by inversion, [update Gamma x U y = Some S]. We want to
show that [Gamma |- [x:=v]y : S].
There are two cases to consider: either [x=y] or [x<>y]. *)
unfold update, t_update in H1.
destruct (beq_idP x y).
+ (* x=y *)
(* If [x = y], then we know that [U = S], and that [[x:=v]y = v].
So what we really must show is that if [empty |- v : U] then
[Gamma |- v : U]. We have already proven a more general version
of this theorem, called context invariance. *)
subst.
inversion H1; subst. clear H1.
eapply context_invariance...
intros x Hcontra.
destruct (free_in_context _ _ S empty Hcontra) as [T' HT']...
inversion HT'.
+ (* x<>y *)
(* If [x <> y], then [Gamma y = Some S] and the substitution has no
effect. We can show that [Gamma |- y : S] by [T_Var]. *)
apply T_Var...
- (* tabs *)
rename i into y. rename t into T11.
(* If [t = tabs y T11 t0], then we know that
[Gamma,x:U |- tabs y T11 t0 : T11->T12]
[Gamma,x:U,y:T11 |- t0 : T12]
[empty |- v : U]
As our IH, we know that forall S Gamma,
[Gamma,x:U |- t0 : S -> Gamma |- [x:=v]t0 S].
We can calculate that
[x:=v]t = tabs y T11 (if beq_id x y then t0 else [x:=v]t0)
And we must show that [Gamma |- [x:=v]t : T11->T12]. We know
we will do so using [T_Abs], so it remains to be shown that:
[Gamma,y:T11 |- if beq_id x y then t0 else [x:=v]t0 : T12]
We consider two cases: [x = y] and [x <> y].
*)
apply T_Abs...
destruct (beq_idP x y).
+ (* x=y *)
(* If [x = y], then the substitution has no effect. Context
invariance shows that [Gamma,y:U,y:T11] and [Gamma,y:T11] are
equivalent. Since the former context shows that [t0 : T12], so
does the latter. *)
eapply context_invariance...
subst.
intros x Hafi. unfold update, t_update.
destruct (beq_id y x)...
+ (* x<>y *)
(* If [x <> y], then the IH and context invariance allow us to show that
[Gamma,x:U,y:T11 |- t0 : T12] =>
[Gamma,y:T11,x:U |- t0 : T12] =>
[Gamma,y:T11 |- [x:=v]t0 : T12] *)
apply IHt. eapply context_invariance...
intros z Hafi. unfold update, t_update.
destruct (beq_idP y z)...
subst. rewrite false_beq_id...
Qed.
Theorem preservation : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof with eauto.
intros t t' T HT.
(* Theorem: If [empty |- t : T] and [t ==> t'], then [empty |- t' : T]. *)
remember (@empty ty) as Gamma. generalize dependent HeqGamma.
generalize dependent t'.
(* Proof: By induction on the given typing derivation. Many cases are
contradictory ([T_Var], [T_Abs]). We show just the interesting ones. *)
induction HT;
intros t' HeqGamma HE; subst; inversion HE; subst...
- (* T_App *)
(* If the last rule used was [T_App], then [t = t1 t2], and three rules
could have been used to show [t ==> t']: [ST_App1], [ST_App2], and
[ST_AppAbs]. In the first two cases, the result follows directly from
the IH. *)
inversion HE; subst...
+ (* ST_AppAbs *)
(* For the third case, suppose
[t1 = tabs x T11 t12]
and
[t2 = v2].
We must show that [empty |- [x:=v2]t12 : T2].
We know by assumption that
[empty |- tabs x T11 t12 : T1->T2]
and by inversion
[x:T1 |- t12 : T2]
We have already proven that substitution_preserves_typing and
[empty |- v2 : T1]
by assumption, so we are done. *)
apply substitution_preserves_typing with T1...
inversion HT1...
- (* T_Fst *)
inversion HT...
- (* T_Snd *)
inversion HT...
Qed.
(* ----------------------------------------------------------------- *)
(** *** Determinism *)
Lemma step_deterministic :
deterministic step.
Proof with eauto.
unfold deterministic.
intros t t' t'' E1 E2.
generalize dependent t''.
induction E1; intros t'' E2; inversion E2; subst; clear E2...
(* ST_AppAbs *)
- inversion H3.
- exfalso; apply value__normal in H...
(* ST_App1 *)
- inversion E1.
- f_equal...
- exfalso; apply value__normal in H1...
(* ST_App2 *)
- exfalso; apply value__normal in H3...
- exfalso; apply value__normal in H...
- f_equal...
(* ST_Pair1 *)
- f_equal...
- exfalso; apply value__normal in H1...
(* ST_Pair2 *)
- exfalso; apply value__normal in H...
- f_equal...
(* ST_Fst *)
- f_equal...
- exfalso.
inversion E1; subst.
+ apply value__normal in H0...
+ apply value__normal in H1...
(* ST_FstPair *)
- exfalso.
inversion H2; subst.
+ apply value__normal in H...
+ apply value__normal in H0...
(* ST_Snd *)
- f_equal...
- exfalso.
inversion E1; subst.
+ apply value__normal in H0...
+ apply value__normal in H1...
(* ST_SndPair *)
- exfalso.
inversion H2; subst.
+ apply value__normal in H...
+ apply value__normal in H0...
- (* ST_IfTrue *)
inversion H3.
- (* ST_IfFalse *)
inversion H3.
(* ST_If *)
- inversion E1.
- inversion E1.
- f_equal...
Qed.
(* ################################################################# *)
(** * Normalization *)
(** Now for the actual normalization proof.
Our goal is to prove that every well-typed term reduces to a
normal form. In fact, it turns out to be convenient to prove
something slightly stronger, namely that every well-typed term
reduces to a _value_. This follows from the weaker property
anyway via Progress (why?) but otherwise we don't need Progress,
and we didn't bother re-proving it above.
Here's the key definition: *)
Definition halts (t:tm) : Prop := exists t', t ==>* t' /\ value t'.
(** A trivial fact: *)
Lemma value_halts : forall v, value v -> halts v.
Proof.
intros v H. unfold halts.
exists v. split.
apply multi_refl.
assumption.
Qed.
(** The key issue in the normalization proof (as in many proofs by
induction) is finding a strong enough induction hypothesis. To
this end, we begin by defining, for each type [T], a set [R_T] of
closed terms of type [T]. We will specify these sets using a
relation [R] and write [R T t] when [t] is in [R_T]. (The sets
[R_T] are sometimes called _saturated sets_ or _reducibility
candidates_.)
Here is the definition of [R] for the base language:
- [R bool t] iff [t] is a closed term of type [bool] and [t] halts
in a value
- [R (T1 -> T2) t] iff [t] is a closed term of type [T1 -> T2] and
[t] halts in a value _and_ for any term [s] such that [R T1 s],
we have [R T2 (t s)]. *)
(** This definition gives us the strengthened induction hypothesis that we
need. Our primary goal is to show that all _programs_ ---i.e., all
closed terms of base type---halt. But closed terms of base type can
contain subterms of functional type, so we need to know something
about these as well. Moreover, it is not enough to know that these
subterms halt, because the application of a normalized function to a
normalized argument involves a substitution, which may enable more
reduction steps. So we need a stronger condition for terms of
functional type: not only should they halt themselves, but, when
applied to halting arguments, they should yield halting results.
The form of [R] is characteristic of the _logical relations_ proof
technique. (Since we are just dealing with unary relations here, we
could perhaps more properly say _logical properties_.) If we want to
prove some property [P] of all closed terms of type [A], we proceed by
proving, by induction on types, that all terms of type [A] _possess_
property [P], all terms of type [A->A] _preserve_ property [P], all
terms of type [(A->A)->(A->A)] _preserve the property of preserving_
property [P], and so on. We do this by defining a family of
properties, indexed by types. For the base type [A], the property is
just [P]. For functional types, it says that the function should map
values satisfying the property at the input type to values satisfying
the property at the output type.
When we come to formalize the definition of [R] in Coq, we hit a
problem. The most obvious formulation would be as a parameterized
Inductive proposition like this:
Inductive R : ty -> tm -> Prop :=
| R_bool : forall b t, has_type empty t TBool ->
halts t ->
R TBool t
| R_arrow : forall T1 T2 t, has_type empty t (TArrow T1 T2) ->
halts t ->
(forall s, R T1 s -> R T2 (tapp t s)) ->
R (TArrow T1 T2) t.
Unfortunately, Coq rejects this definition because it violates the
_strict positivity requirement_ for inductive definitions, which says
that the type being defined must not occur to the left of an arrow in
the type of a constructor argument. Here, it is the third argument to
[R_arrow], namely [(forall s, R T1 s -> R TS (tapp t s))], and
specifically the [R T1 s] part, that violates this rule. (The
outermost arrows separating the constructor arguments don't count when
applying this rule; otherwise we could never have genuinely inductive
properties at all!) The reason for the rule is that types defined
with non-positive recursion can be used to build non-terminating
functions, which as we know would be a disaster for Coq's logical
soundness. Even though the relation we want in this case might be
perfectly innocent, Coq still rejects it because it fails the
positivity test.
Fortunately, it turns out that we _can_ define [R] using a
[Fixpoint]: *)
Fixpoint R (T:ty) (t:tm) {struct T} : Prop :=
has_type empty t T /\ halts t /\
(match T with
| TBool => True
| TArrow T1 T2 => (forall s, R T1 s -> R T2 (tapp t s))
(* ... edit the next line when dealing with products *)
| TProd T1 T2 => False
end).
(** As immediate consequences of this definition, we have that every
element of every set [R_T] halts in a value and is closed with type
[t] :*)
Lemma R_halts : forall {T} {t}, R T t -> halts t.
Proof.
intros. destruct T; unfold R in H; inversion H; inversion H1; assumption.
Qed.
Lemma R_typable_empty : forall {T} {t}, R T t -> has_type empty t T.
Proof.
intros. destruct T; unfold R in H; inversion H; inversion H1; assumption.
Qed.
(** Now we proceed to show the main result, which is that every
well-typed term of type [T] is an element of [R_T]. Together with
[R_halts], that will show that every well-typed term halts in a
value. *)
(* ================================================================= *)
(** ** Membership in [R_T] Is Invariant Under Reduction *)
(** We start with a preliminary lemma that shows a kind of strong
preservation property, namely that membership in [R_T] is _invariant_
under reduction. We will need this property in both directions,
i.e., both to show that a term in [R_T] stays in [R_T] when it takes a
forward step, and to show that any term that ends up in [R_T] after a
step must have been in [R_T] to begin with.
First of all, an easy preliminary lemma. Note that in the forward
direction the proof depends on the fact that our language is
determinstic. This lemma might still be true for nondeterministic
languages, but the proof would be harder! *)
Lemma step_preserves_halting : forall t t', (t ==> t') -> (halts t <-> halts t').
Proof.
intros t t' ST. unfold halts.
split.
- (* -> *)
intros [t'' [STM V]].
inversion STM; subst.
exfalso. apply value__normal in V. unfold normal_form in V. apply V. exists t'. auto.
rewrite (step_deterministic _ _ _ ST H). exists t''. split; assumption.
- (* <- *)
intros [t'0 [STM V]].
exists t'0. split; eauto.
Qed.
(** Now the main lemma, which comes in two parts, one for each
direction. Each proceeds by induction on the structure of the type
[T]. In fact, this is where we make fundamental use of the
structure of types.
One requirement for staying in [R_T] is to stay in type [T]. In the
forward direction, we get this from ordinary type Preservation. *)
Lemma step_preserves_R : forall T t t', (t ==> t') -> R T t -> R T t'.
Proof.
induction T; intros t t' E Rt; unfold R; fold R; unfold R in Rt; fold R in Rt;
destruct Rt as [typable_empty_t [halts_t RRt]].
(* TBool *)
split. eapply preservation; eauto.
split. apply (step_preserves_halting _ _ E); eauto.
auto.
(* TArrow *)
split. eapply preservation; eauto.
split. apply (step_preserves_halting _ _ E); eauto.
intros.
eapply IHT2.
apply ST_App1. apply E.
apply RRt; auto.
(* FILL IN HERE *) Admitted.
(** The generalization to multiple steps is trivial: *)
Lemma multistep_preserves_R : forall T t t',
(t ==>* t') -> R T t -> R T t'.
Proof.
intros T t t' STM; induction STM; intros.
assumption.
apply IHSTM. eapply step_preserves_R. apply H. assumption.
Qed.
(** In the reverse direction, we must add the fact that [t] has type
[T] before stepping as an additional hypothesis. *)
Lemma step_preserves_R' : forall T t t',
has_type empty t T -> (t ==> t') -> R T t' -> R T t.
Proof.
(* FILL IN HERE *) Admitted.
Lemma multistep_preserves_R' : forall T t t',
has_type empty t T -> (t ==>* t') -> R T t' -> R T t.
Proof.
intros T t t' HT STM.
induction STM; intros.
assumption.
eapply step_preserves_R'. assumption. apply H. apply IHSTM.
eapply preservation; eauto. auto.
Qed.
(* ================================================================= *)
(** ** Closed Instances of Terms of Type [t] Belong to [R_T] *)
(** Now we proceed to show that every term of type [T] belongs to
[R_T]. Here, the induction will be on typing derivations (it would be
surprising to see a proof about well-typed terms that did not
somewhere involve induction on typing derivations!). The only
technical difficulty here is in dealing with the abstraction case.
Since we are arguing by induction, the demonstration that a term
[tabs x T1 t2] belongs to [R_(T1->T2)] should involve applying the
induction hypothesis to show that [t2] belongs to [R_(T2)]. But
[R_(T2)] is defined to be a set of _closed_ terms, while [t2] may
contain [x] free, so this does not make sense.
This problem is resolved by using a standard trick to suitably
generalize the induction hypothesis: instead of proving a statement
involving a closed term, we generalize it to cover all closed
_instances_ of an open term [t]. Informally, the statement of the
lemma will look like this:
If [x1:T1,..xn:Tn |- t : T] and [v1,...,vn] are values such that
[R T1 v1], [R T2 v2], ..., [R Tn vn], then
[R T ([x1:=v1][x2:=v2]...[xn:=vn]t)].
The proof will proceed by induction on the typing derivation
[x1:T1,..xn:Tn |- t : T]; the most interesting case will be the one
for abstraction. *)
(* ----------------------------------------------------------------- *)
(** *** Multisubstitutions, Multi-Extensions, and Instantiations *)
(** However, before we can proceed to formalize the statement and
proof of the lemma, we'll need to build some (rather tedious)
machinery to deal with the fact that we are performing _multiple_
substitutions on term [t] and _multiple_ extensions of the typing
context. In particular, we must be precise about the order in which
the substitutions occur and how they act on each other. Often these
details are simply elided in informal paper proofs, but of course Coq
won't let us do that. Since here we are substituting closed terms, we
don't need to worry about how one substitution might affect the term
put in place by another. But we still do need to worry about the
_order_ of substitutions, because it is quite possible for the same
identifier to appear multiple times among the [x1,...xn] with
different associated [vi] and [Ti].
To make everything precise, we will assume that environments are
extended from left to right, and multiple substitutions are performed
from right to left. To see that this is consistent, suppose we have
an environment written as [...,y:bool,...,y:nat,...] and a
corresponding term substitution written as [...[y:=(tbool
true)]...[y:=(tnat 3)]...t]. Since environments are extended from
left to right, the binding [y:nat] hides the binding [y:bool]; since
substitutions are performed right to left, we do the substitution
[y:=(tnat 3)] first, so that the substitution [y:=(tbool true)] has
no effect. Substitution thus correctly preserves the type of the term.
With these points in mind, the following definitions should make sense.
A _multisubstitution_ is the result of applying a list of
substitutions, which we call an _environment_. *)
Definition env := list (id * tm).
Fixpoint msubst (ss:env) (t:tm) {struct ss} : tm :=
match ss with
| nil => t
| ((x,s)::ss') => msubst ss' ([x:=s]t)
end.
(** We need similar machinery to talk about repeated extension of a
typing context using a list of (identifier, type) pairs, which we
call a _type assignment_. *)
Definition tass := list (id * ty).
Fixpoint mupdate (Gamma : context) (xts : tass) :=
match xts with
| nil => Gamma
| ((x,v)::xts') => update (mupdate Gamma xts') x v
end.
(** We will need some simple operations that work uniformly on
environments and type assigments *)
Fixpoint lookup {X:Set} (k : id) (l : list (id * X)) {struct l}
: option X :=
match l with
| nil => None
| (j,x) :: l' =>
if beq_id j k then Some x else lookup k l'
end.
Fixpoint drop {X:Set} (n:id) (nxs:list (id * X)) {struct nxs}
: list (id * X) :=
match nxs with
| nil => nil
| ((n',x)::nxs') =>
if beq_id n' n then drop n nxs'
else (n',x)::(drop n nxs')
end.
(** An _instantiation_ combines a type assignment and a value
environment with the same domains, where corresponding elements are
in R. *)
Inductive instantiation : tass -> env -> Prop :=
| V_nil :
instantiation nil nil
| V_cons : forall x T v c e,
value v -> R T v ->
instantiation c e ->
instantiation ((x,T)::c) ((x,v)::e).
(** We now proceed to prove various properties of these definitions. *)
(* ----------------------------------------------------------------- *)
(** *** More Substitution Facts *)
(** First we need some additional lemmas on (ordinary) substitution. *)
Lemma vacuous_substitution : forall t x,
~ appears_free_in x t ->
forall t', [x:=t']t = t.
Proof with eauto.
(* FILL IN HERE *) Admitted.
Lemma subst_closed: forall t,
closed t ->
forall x t', [x:=t']t = t.
Proof.
intros. apply vacuous_substitution. apply H. Qed.
Lemma subst_not_afi : forall t x v,
closed v -> ~ appears_free_in x ([x:=v]t).
Proof with eauto. (* rather slow this way *)
unfold closed, not.
induction t; intros x v P A; simpl in A.
- (* tvar *)
destruct (beq_idP x i)...
inversion A; subst. auto.
- (* tapp *)
inversion A; subst...
- (* tabs *)
destruct (beq_idP x i)...
+ inversion A; subst...
+ inversion A; subst...
- (* tpair *)
inversion A; subst...
- (* tfst *)
inversion A; subst...
- (* tsnd *)
inversion A; subst...
- (* ttrue *)
inversion A.
- (* tfalse *)
inversion A.
- (* tif *)
inversion A; subst...
Qed.
Lemma duplicate_subst : forall t' x t v,
closed v -> [x:=t]([x:=v]t') = [x:=v]t'.
Proof.
intros. eapply vacuous_substitution. apply subst_not_afi. auto.
Qed.
Lemma swap_subst : forall t x x1 v v1,
x <> x1 ->
closed v -> closed v1 ->
[x1:=v1]([x:=v]t) = [x:=v]([x1:=v1]t).
Proof with eauto.
induction t; intros; simpl.
- (* tvar *)
destruct (beq_idP x i); destruct (beq_idP x1 i).
+ subst. exfalso...
+ subst. simpl. rewrite <- beq_id_refl. apply subst_closed...
+ subst. simpl. rewrite <- beq_id_refl. rewrite subst_closed...
+ simpl. rewrite false_beq_id... rewrite false_beq_id...
(* FILL IN HERE *) Admitted.
(* ----------------------------------------------------------------- *)
(** *** Properties of Multi-Substitutions *)
Lemma msubst_closed: forall t, closed t -> forall ss, msubst ss t = t.
Proof.
induction ss.
reflexivity.
destruct a. simpl. rewrite subst_closed; assumption.
Qed.
(** Closed environments are those that contain only closed terms. *)
Fixpoint closed_env (env:env) {struct env} :=
match env with
| nil => True
| (x,t)::env' => closed t /\ closed_env env'
end.
(** Next come a series of lemmas charcterizing how [msubst] of closed terms
distributes over [subst] and over each term form *)
Lemma subst_msubst: forall env x v t, closed v -> closed_env env ->
msubst env ([x:=v]t) = [x:=v](msubst (drop x env) t).
Proof.
induction env0; intros; auto.
destruct a. simpl.
inversion H0. fold closed_env in H2.
destruct (beq_idP i x).
- subst. rewrite duplicate_subst; auto.
- simpl. rewrite swap_subst; eauto.
Qed.
Lemma msubst_var: forall ss x, closed_env ss ->
msubst ss (tvar x) =
match lookup x ss with
| Some t => t
| None => tvar x
end.
Proof.
induction ss; intros.
reflexivity.
destruct a.
simpl. destruct (beq_id i x).
apply msubst_closed. inversion H; auto.
apply IHss. inversion H; auto.
Qed.
Lemma msubst_abs: forall ss x T t,
msubst ss (tabs x T t) = tabs x T (msubst (drop x ss) t).
Proof.
induction ss; intros.
reflexivity.
destruct a.
simpl. destruct (beq_id i x); simpl; auto.
Qed.
Lemma msubst_app : forall ss t1 t2, msubst ss (tapp t1 t2) = tapp (msubst ss t1) (msubst ss t2).
Proof.
induction ss; intros.
reflexivity.
destruct a.
simpl. rewrite <- IHss. auto.
Qed.
(** You'll need similar functions for the other term constructors. *)
(* FILL IN HERE *)
(* ----------------------------------------------------------------- *)
(** *** Properties of Multi-Extensions *)
(** We need to connect the behavior of type assignments with that of
their corresponding contexts. *)
Lemma mupdate_lookup : forall (c : tass) (x:id),
lookup x c = (mupdate empty c) x.
Proof.
induction c; intros.
auto.
destruct a. unfold lookup, mupdate, update, t_update. destruct (beq_id i x); auto.
Qed.
Lemma mupdate_drop : forall (c: tass) Gamma x x',
mupdate Gamma (drop x c) x'
= if beq_id x x' then Gamma x' else mupdate Gamma c x'.
Proof.
induction c; intros.
- destruct (beq_idP x x'); auto.
- destruct a. simpl.
destruct (beq_idP i x).
+ subst. rewrite IHc.
unfold update, t_update. destruct (beq_idP x x'); auto.
+ simpl. unfold update, t_update. destruct (beq_idP i x'); auto.
subst. rewrite false_beq_id; congruence.
Qed.
(* ----------------------------------------------------------------- *)
(** *** Properties of Instantiations *)
(** These are strightforward. *)
Lemma instantiation_domains_match: forall {c} {e},
instantiation c e ->
forall {x} {T},
lookup x c = Some T -> exists t, lookup x e = Some t.
Proof.
intros c e V. induction V; intros x0 T0 C.
solve_by_invert.
simpl in *.
destruct (beq_id x x0); eauto.
Qed.
Lemma instantiation_env_closed : forall c e,
instantiation c e -> closed_env e.
Proof.
intros c e V; induction V; intros.
econstructor.
unfold closed_env. fold closed_env.
split. eapply typable_empty__closed. eapply R_typable_empty. eauto.
auto.
Qed.
Lemma instantiation_R : forall c e,
instantiation c e ->
forall x t T,
lookup x c = Some T ->
lookup x e = Some t -> R T t.
Proof.
intros c e V. induction V; intros x' t' T' G E.
solve_by_invert.
unfold lookup in *. destruct (beq_id x x').
inversion G; inversion E; subst. auto.
eauto.
Qed.
Lemma instantiation_drop : forall c env,
instantiation c env ->
forall x, instantiation (drop x c) (drop x env).
Proof.
intros c e V. induction V.
intros. simpl. constructor.
intros. unfold drop. destruct (beq_id x x0); auto. constructor; eauto.
Qed.
(* ----------------------------------------------------------------- *)
(** *** Congruence Lemmas on Multistep *)
(** We'll need just a few of these; add them as the demand arises. *)
Lemma multistep_App2 : forall v t t',
value v -> (t ==>* t') -> (tapp v t) ==>* (tapp v t').
Proof.
intros v t t' V STM. induction STM.
apply multi_refl.
eapply multi_step.
apply ST_App2; eauto. auto.
Qed.
(* FILL IN HERE *)
(* ----------------------------------------------------------------- *)
(** *** The R Lemma. *)
(** We can finally put everything together.
The key lemma about preservation of typing under substitution can
be lifted to multi-substitutions: *)
Lemma msubst_preserves_typing : forall c e,
instantiation c e ->
forall Gamma t S, has_type (mupdate Gamma c) t S ->
has_type Gamma (msubst e t) S.
Proof.
induction 1; intros.
simpl in H. simpl. auto.
simpl in H2. simpl.
apply IHinstantiation.
eapply substitution_preserves_typing; eauto.
apply (R_typable_empty H0).
Qed.
(** And at long last, the main lemma. *)
Lemma msubst_R : forall c env t T,
has_type (mupdate empty c) t T ->
instantiation c env ->
R T (msubst env t).
Proof.
intros c env0 t T HT V.
generalize dependent env0.
(* We need to generalize the hypothesis a bit before setting up the induction. *)
remember (mupdate empty c) as Gamma.
assert (forall x, Gamma x = lookup x c).
intros. rewrite HeqGamma. rewrite mupdate_lookup. auto.
clear HeqGamma.
generalize dependent c.
induction HT; intros.
- (* T_Var *)
rewrite H0 in H. destruct (instantiation_domains_match V H) as [t P].
eapply instantiation_R; eauto.
rewrite msubst_var. rewrite P. auto. eapply instantiation_env_closed; eauto.
- (* T_Abs *)
rewrite msubst_abs.
(* We'll need variants of the following fact several times, so its simplest to
establish it just once. *)
assert (WT: has_type empty (tabs x T11 (msubst (drop x env0) t12)) (TArrow T11 T12)).
{ eapply T_Abs. eapply msubst_preserves_typing.
{ eapply instantiation_drop; eauto. }
eapply context_invariance.
{ apply HT. }
intros.
unfold update, t_update. rewrite mupdate_drop. destruct (beq_idP x x0).
+ auto.
+ rewrite H.
clear - c n. induction c.
simpl. rewrite false_beq_id; auto.
simpl. destruct a. unfold update, t_update.
destruct (beq_id i x0); auto. }
unfold R. fold R. split.
auto.
split. apply value_halts. apply v_abs.
intros.
destruct (R_halts H0) as [v [P Q]].
pose proof (multistep_preserves_R _ _ _ P H0).
apply multistep_preserves_R' with (msubst ((x,v)::env0) t12).
eapply T_App. eauto.
apply R_typable_empty; auto.
eapply multi_trans. eapply multistep_App2; eauto.
eapply multi_R.
simpl. rewrite subst_msubst.
eapply ST_AppAbs; eauto.
eapply typable_empty__closed.
apply (R_typable_empty H1).
eapply instantiation_env_closed; eauto.
eapply (IHHT ((x,T11)::c)).
intros. unfold update, t_update, lookup. destruct (beq_id x x0); auto.
constructor; auto.
- (* T_App *)
rewrite msubst_app.
destruct (IHHT1 c H env0 V) as [_ [_ P1]].
pose proof (IHHT2 c H env0 V) as P2. fold R in P1. auto.
(* FILL IN HERE *) Admitted.
(* ----------------------------------------------------------------- *)
(** *** Normalization Theorem *)
Theorem normalization : forall t T, has_type empty t T -> halts t.
Proof.
intros.
replace t with (msubst nil t) by reflexivity.
apply (@R_halts T).
apply (msubst_R nil); eauto.
eapply V_nil.
Qed.
(** $Date: 2016-10-19 09:26:05 -0400 (Wed, 19 Oct 2016) $ *)
|
// bsg_fsb_node_level_shift_node_domain
//
// This module is design to level shift all signals that connect the FSB to a
// node. This allows FSB nodes to exist in different power domains than the FSB.
// There are 2 types of level shifters:
//
// 1) Source - level shifting cell must be in the same power domain as the
// signal's source
// 2) Sink - level shifting cell must be in the same power doamin as the
// signal's destination
//
// This is 1 of 4 modules that shift all the signals between the FSB and
// a node. Each of the modules has a different strategy about which power
// domain the level-shifters should be in:
//
// 1) bsg_fsb_node_level_shift_all_sink
// -- All level shifters in same power domain as the input pin
// 2) bsg_fsb_node_level_shift_all_source
// -- All level shifters in same power domain as the output pin
// 3) bsg_fsb_node_level_shift_fsb_domain
// -- All level shifters in same power domain as the fsb module
// * 4) bsg_fsb_node_level_shift_node_domain
// -- All level shifters in same power domain as the node module
//
`include "bsg_defines.v"
module bsg_fsb_node_level_shift_node_domain #(parameter `BSG_INV_PARAM(ring_width_p ))
(
input en_ls_i,
input clk_i,
input reset_i,
output clk_o,
output reset_o,
//----- ATTACHED TO FSB -----//
output fsb_v_i_o,
output [ring_width_p-1:0] fsb_data_i_o,
input fsb_yumi_o_i,
input fsb_v_o_i,
input [ring_width_p-1:0] fsb_data_o_i,
output fsb_ready_i_o,
//----- ATTACHED TO NODE -----//
output node_v_i_o,
output [ring_width_p-1:0] node_data_i_o,
input node_ready_o_i,
input node_v_o_i,
input [ring_width_p-1:0] node_data_o_i,
output node_yumi_i_o
);
// Level Shift Clock
bsg_level_shift_up_down_sink #(.width_p(1)) clk_ls_inst
(
.v1_en_i(1'b1),
.v0_data_i(clk_i),
.v1_data_o(clk_o)
);
// Level Shift Reset
bsg_level_shift_up_down_sink #(.width_p(1)) reset_ls_inst
(
.v1_en_i(1'b1),
.v0_data_i(reset_i),
.v1_data_o(reset_o)
);
// NODE v_o --> FSB v_i
bsg_level_shift_up_down_source #(.width_p(1)) n2f_v_ls_inst
(
.v0_en_i(en_ls_i),
.v0_data_i(node_v_o_i),
.v1_data_o(fsb_v_i_o)
);
// NODE data_o --> FSB data_i
bsg_level_shift_up_down_source #(.width_p(ring_width_p)) n2f_data_ls_inst
(
.v0_en_i(en_ls_i),
.v0_data_i(node_data_o_i),
.v1_data_o(fsb_data_i_o)
);
// FSB yumi_o --> NODE yumi_i
bsg_level_shift_up_down_sink #(.width_p(1)) f2n_yumi_ls_inst
(
.v1_en_i(en_ls_i),
.v0_data_i(fsb_yumi_o_i),
.v1_data_o(node_yumi_i_o)
);
// FSB v_o --> NODE v_i
bsg_level_shift_up_down_sink #(.width_p(1)) f2n_v_ls_inst
(
.v1_en_i(en_ls_i),
.v0_data_i(fsb_v_o_i),
.v1_data_o(node_v_i_o)
);
// FSB data_o --> NODE data_i
bsg_level_shift_up_down_sink #(.width_p(ring_width_p)) f2n_data_ls_inst
(
.v1_en_i(en_ls_i),
.v0_data_i(fsb_data_o_i),
.v1_data_o(node_data_i_o)
);
// NODE ready_o --> FSB ready_i
bsg_level_shift_up_down_source #(.width_p(1)) n2f_ready_ls_inst
(
.v0_en_i(en_ls_i),
.v0_data_i(node_ready_o_i),
.v1_data_o(fsb_ready_i_o)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_fsb_node_level_shift_node_domain)
|
// alu.v
//
// AVM alu in Verilog
//
// This is an implementation of AVM in C for experimenation purposes.
// It is both an AVM interpretr and an assembler for the instruction set.
//
// (C) 2016 David J. Goehrig
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE.
//
`include "avm.vh"
module alu (
input clock,
input [7:0] opcode,
input [`BITS-1:0] tos,
input [`BITS-1:0] nos,
output [`BITS-1:0] alu_tos,
output [`BITS-1:0] alu_nos);
reg [`BITS-1:0] _tos;
reg [`BITS-1:0] _nos;
reg [`BITS*2-1:0] _mul;
assign alu_tos = _tos;
assign alu_nos = _nos;
always @(posedge clock) begin
case(opcode)
// math
8'b0000_0100:
_tos <= - tos;
8'b0000_0101:
_tos <= nos + tos;
8'b0000_0110:
begin
_mul = nos * tos;
_tos <= _mul[`BITS-1:0];
_nos <= _mul[(`BITS*2)-1:`BITS];
end
8'b0000_0111:
begin
_tos <= nos / tos;
_nos <= nos % tos;
end
// logic
8'b0000_1000:
_tos <= ~ tos;
8'b0000_1001:
_tos <= nos & tos;
8'b0000_1010:
_tos <= nos | tos;
8'b0000_1011:
_tos <= nos ^ tos;
default:
_tos <= tos;
endcase
end
endmodule
|
// megafunction wizard: %LPM_FIFO+%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_40x128.v
// Megafunction Name(s):
// scfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 148 04/26/2005 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_40x128 (
data,
wrreq,
rdreq,
clock,
aclr,
q,
full,
empty,
usedw);
input [39:0] data;
input wrreq;
input rdreq;
input clock;
input aclr;
output [39:0] q;
output full;
output empty;
output [6:0] usedw;
wire [6:0] sub_wire0;
wire sub_wire1;
wire [39:0] sub_wire2;
wire sub_wire3;
wire [6:0] usedw = sub_wire0[6:0];
wire empty = sub_wire1;
wire [39:0] q = sub_wire2[39:0];
wire full = sub_wire3;
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2),
.full (sub_wire3)
// synopsys translate_off
,
.almost_empty (),
.almost_full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.lpm_width = 40,
scfifo_component.lpm_numwords = 128,
scfifo_component.lpm_widthu = 7,
scfifo_component.intended_device_family = "Cyclone II",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_showahead = "OFF",
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON",
scfifo_component.add_ram_output_register = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "40"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "40"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: USED_PORT: data 0 0 40 0 INPUT NODEFVAL data[39..0]
// Retrieval info: USED_PORT: q 0 0 40 0 OUTPUT NODEFVAL q[39..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: usedw 0 0 7 0 OUTPUT NODEFVAL usedw[6..0]
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: CONNECT: @data 0 0 40 0 data 0 0 40 0
// Retrieval info: CONNECT: q 0 0 40 0 @q 0 0 40 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 7 0 @usedw 0 0 7 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_40x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_40x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_40x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_40x128.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_40x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_40x128_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_40x128_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_40x128_wave*.jpg FALSE
|
module user_design(clk, rst, exception, input_timer, input_rs232_rx, input_ps2, input_i2c, input_switches, input_eth_rx, input_buttons, input_timer_stb, input_rs232_rx_stb, input_ps2_stb, input_i2c_stb, input_switches_stb, input_eth_rx_stb, input_buttons_stb, input_timer_ack, input_rs232_rx_ack, input_ps2_ack, input_i2c_ack, input_switches_ack, input_eth_rx_ack, input_buttons_ack, output_seven_segment_annode, output_eth_tx, output_rs232_tx, output_leds, output_audio, output_led_g, output_seven_segment_cathode, output_led_b, output_i2c, output_vga, output_led_r, output_seven_segment_annode_stb, output_eth_tx_stb, output_rs232_tx_stb, output_leds_stb, output_audio_stb, output_led_g_stb, output_seven_segment_cathode_stb, output_led_b_stb, output_i2c_stb, output_vga_stb, output_led_r_stb, output_seven_segment_annode_ack, output_eth_tx_ack, output_rs232_tx_ack, output_leds_ack, output_audio_ack, output_led_g_ack, output_seven_segment_cathode_ack, output_led_b_ack, output_i2c_ack, output_vga_ack, output_led_r_ack);
input clk;
input rst;
output exception;
input [31:0] input_timer;
input input_timer_stb;
output input_timer_ack;
input [31:0] input_rs232_rx;
input input_rs232_rx_stb;
output input_rs232_rx_ack;
input [31:0] input_ps2;
input input_ps2_stb;
output input_ps2_ack;
input [31:0] input_i2c;
input input_i2c_stb;
output input_i2c_ack;
input [31:0] input_switches;
input input_switches_stb;
output input_switches_ack;
input [31:0] input_eth_rx;
input input_eth_rx_stb;
output input_eth_rx_ack;
input [31:0] input_buttons;
input input_buttons_stb;
output input_buttons_ack;
output [31:0] output_seven_segment_annode;
output output_seven_segment_annode_stb;
input output_seven_segment_annode_ack;
output [31:0] output_eth_tx;
output output_eth_tx_stb;
input output_eth_tx_ack;
output [31:0] output_rs232_tx;
output output_rs232_tx_stb;
input output_rs232_tx_ack;
output [31:0] output_leds;
output output_leds_stb;
input output_leds_ack;
output [31:0] output_audio;
output output_audio_stb;
input output_audio_ack;
output [31:0] output_led_g;
output output_led_g_stb;
input output_led_g_ack;
output [31:0] output_seven_segment_cathode;
output output_seven_segment_cathode_stb;
input output_seven_segment_cathode_ack;
output [31:0] output_led_b;
output output_led_b_stb;
input output_led_b_ack;
output [31:0] output_i2c;
output output_i2c_stb;
input output_i2c_ack;
output [31:0] output_vga;
output output_vga_stb;
input output_vga_ack;
output [31:0] output_led_r;
output output_led_r_stb;
input output_led_r_ack;
wire [31:0] wire_139931284558480;
wire wire_139931284558480_stb;
wire wire_139931284558480_ack;
wire [31:0] wire_139931284559128;
wire wire_139931284559128_stb;
wire wire_139931284559128_ack;
wire [31:0] wire_139931284558336;
wire wire_139931284558336_stb;
wire wire_139931284558336_ack;
wire [31:0] wire_139931284559920;
wire wire_139931284559920_stb;
wire wire_139931284559920_ack;
wire exception_139931284560784;
wire exception_139931279976424;
wire exception_139931274821216;
wire exception_139931278281472;
wire exception_139931285563872;
wire exception_139931273273072;
wire exception_139931279435176;
wire exception_139931272744328;
wire exception_139931284127824;
wire exception_139931284769536;
wire exception_139931277660032;
wire exception_139931277767888;
wire exception_139931277629632;
wire exception_139931284131640;
main_0 main_0_139931284560784(
.clk(clk),
.rst(rst),
.exception(exception_139931284560784),
.input_in1(wire_139931284558336),
.input_in1_stb(wire_139931284558336_stb),
.input_in1_ack(wire_139931284558336_ack),
.input_in2(wire_139931284559920),
.input_in2_stb(wire_139931284559920_stb),
.input_in2_ack(wire_139931284559920_ack),
.output_out(output_rs232_tx),
.output_out_stb(output_rs232_tx_stb),
.output_out_ack(output_rs232_tx_ack));
main_1 main_1_139931279976424(
.clk(clk),
.rst(rst),
.exception(exception_139931279976424),
.input_switches(input_switches),
.input_switches_stb(input_switches_stb),
.input_switches_ack(input_switches_ack),
.input_buttons(input_buttons),
.input_buttons_stb(input_buttons_stb),
.input_buttons_ack(input_buttons_ack),
.input_socket(wire_139931284559128),
.input_socket_stb(wire_139931284559128_stb),
.input_socket_ack(wire_139931284559128_ack),
.input_rs232_rx(input_rs232_rx),
.input_rs232_rx_stb(input_rs232_rx_stb),
.input_rs232_rx_ack(input_rs232_rx_ack),
.output_rs232_tx(wire_139931284558336),
.output_rs232_tx_stb(wire_139931284558336_stb),
.output_rs232_tx_ack(wire_139931284558336_ack),
.output_leds(output_leds),
.output_leds_stb(output_leds_stb),
.output_leds_ack(output_leds_ack),
.output_socket(wire_139931284558480),
.output_socket_stb(wire_139931284558480_stb),
.output_socket_ack(wire_139931284558480_ack));
main_2 main_2_139931274821216(
.clk(clk),
.rst(rst),
.exception(exception_139931274821216),
.input_eth_rx(input_eth_rx),
.input_eth_rx_stb(input_eth_rx_stb),
.input_eth_rx_ack(input_eth_rx_ack),
.input_socket(wire_139931284558480),
.input_socket_stb(wire_139931284558480_stb),
.input_socket_ack(wire_139931284558480_ack),
.output_rs232_tx(wire_139931284559920),
.output_rs232_tx_stb(wire_139931284559920_stb),
.output_rs232_tx_ack(wire_139931284559920_ack),
.output_socket(wire_139931284559128),
.output_socket_stb(wire_139931284559128_stb),
.output_socket_ack(wire_139931284559128_ack),
.output_eth_tx(output_eth_tx),
.output_eth_tx_stb(output_eth_tx_stb),
.output_eth_tx_ack(output_eth_tx_ack));
main_3 main_3_139931278281472(
.clk(clk),
.rst(rst),
.exception(exception_139931278281472),
.input_in(input_timer),
.input_in_stb(input_timer_stb),
.input_in_ack(input_timer_ack));
main_4 main_4_139931285563872(
.clk(clk),
.rst(rst),
.exception(exception_139931285563872),
.input_in(input_ps2),
.input_in_stb(input_ps2_stb),
.input_in_ack(input_ps2_ack));
main_5 main_5_139931273273072(
.clk(clk),
.rst(rst),
.exception(exception_139931273273072),
.input_in(input_i2c),
.input_in_stb(input_i2c_stb),
.input_in_ack(input_i2c_ack));
main_6 main_6_139931279435176(
.clk(clk),
.rst(rst),
.exception(exception_139931279435176),
.output_out(output_seven_segment_annode),
.output_out_stb(output_seven_segment_annode_stb),
.output_out_ack(output_seven_segment_annode_ack));
main_7 main_7_139931272744328(
.clk(clk),
.rst(rst),
.exception(exception_139931272744328),
.output_out(output_audio),
.output_out_stb(output_audio_stb),
.output_out_ack(output_audio_ack));
main_8 main_8_139931284127824(
.clk(clk),
.rst(rst),
.exception(exception_139931284127824),
.output_out(output_led_g),
.output_out_stb(output_led_g_stb),
.output_out_ack(output_led_g_ack));
main_9 main_9_139931284769536(
.clk(clk),
.rst(rst),
.exception(exception_139931284769536),
.output_out(output_seven_segment_cathode),
.output_out_stb(output_seven_segment_cathode_stb),
.output_out_ack(output_seven_segment_cathode_ack));
main_10 main_10_139931277660032(
.clk(clk),
.rst(rst),
.exception(exception_139931277660032),
.output_out(output_led_b),
.output_out_stb(output_led_b_stb),
.output_out_ack(output_led_b_ack));
main_11 main_11_139931277767888(
.clk(clk),
.rst(rst),
.exception(exception_139931277767888),
.output_out(output_i2c),
.output_out_stb(output_i2c_stb),
.output_out_ack(output_i2c_ack));
main_12 main_12_139931277629632(
.clk(clk),
.rst(rst),
.exception(exception_139931277629632),
.output_out(output_vga),
.output_out_stb(output_vga_stb),
.output_out_ack(output_vga_ack));
main_13 main_13_139931284131640(
.clk(clk),
.rst(rst),
.exception(exception_139931284131640),
.output_out(output_led_r),
.output_out_stb(output_led_r_stb),
.output_out_ack(output_led_r_ack));
assign exception = exception_139931284560784 || exception_139931279976424 || exception_139931274821216 || exception_139931278281472 || exception_139931285563872 || exception_139931273273072 || exception_139931279435176 || exception_139931272744328 || exception_139931284127824 || exception_139931284769536 || exception_139931277660032 || exception_139931277767888 || exception_139931277629632 || exception_139931284131640;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO1P_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__LSBUFISO1P_PP_BLACKBOX_V
/**
* lsbufiso1p: ????.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__lsbufiso1p (
X ,
A ,
SLEEP ,
DESTPWR,
VPWR ,
VGND ,
DESTVPB,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP ;
input DESTPWR;
input VPWR ;
input VGND ;
input DESTVPB;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO1P_PP_BLACKBOX_V
|
//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
//Date : Wed Apr 20 13:37:39 2016
//Host : WK116 running 64-bit major release (build 9200)
//Command : generate_target PmodHYGRO.bd
//Design : PmodHYGRO
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module PmodHYGRO
(AXI_LITE_IIC_araddr,
AXI_LITE_IIC_arready,
AXI_LITE_IIC_arvalid,
AXI_LITE_IIC_awaddr,
AXI_LITE_IIC_awready,
AXI_LITE_IIC_awvalid,
AXI_LITE_IIC_bready,
AXI_LITE_IIC_bresp,
AXI_LITE_IIC_bvalid,
AXI_LITE_IIC_rdata,
AXI_LITE_IIC_rready,
AXI_LITE_IIC_rresp,
AXI_LITE_IIC_rvalid,
AXI_LITE_IIC_wdata,
AXI_LITE_IIC_wready,
AXI_LITE_IIC_wstrb,
AXI_LITE_IIC_wvalid,
I2C_Interrupt,
Pmod_out_pin10_i,
Pmod_out_pin10_o,
Pmod_out_pin10_t,
Pmod_out_pin1_i,
Pmod_out_pin1_o,
Pmod_out_pin1_t,
Pmod_out_pin2_i,
Pmod_out_pin2_o,
Pmod_out_pin2_t,
Pmod_out_pin3_i,
Pmod_out_pin3_o,
Pmod_out_pin3_t,
Pmod_out_pin4_i,
Pmod_out_pin4_o,
Pmod_out_pin4_t,
Pmod_out_pin7_i,
Pmod_out_pin7_o,
Pmod_out_pin7_t,
Pmod_out_pin8_i,
Pmod_out_pin8_o,
Pmod_out_pin8_t,
Pmod_out_pin9_i,
Pmod_out_pin9_o,
Pmod_out_pin9_t,
s_axi_aclk,
s_axi_aresetn);
input [8:0]AXI_LITE_IIC_araddr;
output AXI_LITE_IIC_arready;
input AXI_LITE_IIC_arvalid;
input [8:0]AXI_LITE_IIC_awaddr;
output AXI_LITE_IIC_awready;
input AXI_LITE_IIC_awvalid;
input AXI_LITE_IIC_bready;
output [1:0]AXI_LITE_IIC_bresp;
output AXI_LITE_IIC_bvalid;
output [31:0]AXI_LITE_IIC_rdata;
input AXI_LITE_IIC_rready;
output [1:0]AXI_LITE_IIC_rresp;
output AXI_LITE_IIC_rvalid;
input [31:0]AXI_LITE_IIC_wdata;
output AXI_LITE_IIC_wready;
input [3:0]AXI_LITE_IIC_wstrb;
input AXI_LITE_IIC_wvalid;
output I2C_Interrupt;
input Pmod_out_pin10_i;
output Pmod_out_pin10_o;
output Pmod_out_pin10_t;
input Pmod_out_pin1_i;
output Pmod_out_pin1_o;
output Pmod_out_pin1_t;
input Pmod_out_pin2_i;
output Pmod_out_pin2_o;
output Pmod_out_pin2_t;
input Pmod_out_pin3_i;
output Pmod_out_pin3_o;
output Pmod_out_pin3_t;
input Pmod_out_pin4_i;
output Pmod_out_pin4_o;
output Pmod_out_pin4_t;
input Pmod_out_pin7_i;
output Pmod_out_pin7_o;
output Pmod_out_pin7_t;
input Pmod_out_pin8_i;
output Pmod_out_pin8_o;
output Pmod_out_pin8_t;
input Pmod_out_pin9_i;
output Pmod_out_pin9_o;
output Pmod_out_pin9_t;
input s_axi_aclk;
input s_axi_aresetn;
wire [8:0]S_AXI_1_ARADDR;
wire S_AXI_1_ARREADY;
wire S_AXI_1_ARVALID;
wire [8:0]S_AXI_1_AWADDR;
wire S_AXI_1_AWREADY;
wire S_AXI_1_AWVALID;
wire S_AXI_1_BREADY;
wire [1:0]S_AXI_1_BRESP;
wire S_AXI_1_BVALID;
wire [31:0]S_AXI_1_RDATA;
wire S_AXI_1_RREADY;
wire [1:0]S_AXI_1_RRESP;
wire S_AXI_1_RVALID;
wire [31:0]S_AXI_1_WDATA;
wire S_AXI_1_WREADY;
wire [3:0]S_AXI_1_WSTRB;
wire S_AXI_1_WVALID;
wire axi_iic_0_IIC_SCL_I;
wire axi_iic_0_IIC_SCL_O;
wire axi_iic_0_IIC_SCL_T;
wire axi_iic_0_IIC_SDA_I;
wire axi_iic_0_IIC_SDA_O;
wire axi_iic_0_IIC_SDA_T;
wire [1:0]axi_iic_0_gpo;
wire axi_iic_0_iic2intc_irpt;
wire pmod_bridge_0_Pmod_out_PIN10_I;
wire pmod_bridge_0_Pmod_out_PIN10_O;
wire pmod_bridge_0_Pmod_out_PIN10_T;
wire pmod_bridge_0_Pmod_out_PIN1_I;
wire pmod_bridge_0_Pmod_out_PIN1_O;
wire pmod_bridge_0_Pmod_out_PIN1_T;
wire pmod_bridge_0_Pmod_out_PIN2_I;
wire pmod_bridge_0_Pmod_out_PIN2_O;
wire pmod_bridge_0_Pmod_out_PIN2_T;
wire pmod_bridge_0_Pmod_out_PIN3_I;
wire pmod_bridge_0_Pmod_out_PIN3_O;
wire pmod_bridge_0_Pmod_out_PIN3_T;
wire pmod_bridge_0_Pmod_out_PIN4_I;
wire pmod_bridge_0_Pmod_out_PIN4_O;
wire pmod_bridge_0_Pmod_out_PIN4_T;
wire pmod_bridge_0_Pmod_out_PIN7_I;
wire pmod_bridge_0_Pmod_out_PIN7_O;
wire pmod_bridge_0_Pmod_out_PIN7_T;
wire pmod_bridge_0_Pmod_out_PIN8_I;
wire pmod_bridge_0_Pmod_out_PIN8_O;
wire pmod_bridge_0_Pmod_out_PIN8_T;
wire pmod_bridge_0_Pmod_out_PIN9_I;
wire pmod_bridge_0_Pmod_out_PIN9_O;
wire pmod_bridge_0_Pmod_out_PIN9_T;
wire s_axi_aclk_1;
wire s_axi_aresetn_1;
wire [1:0]xlconstant_0_dout;
assign AXI_LITE_IIC_arready = S_AXI_1_ARREADY;
assign AXI_LITE_IIC_awready = S_AXI_1_AWREADY;
assign AXI_LITE_IIC_bresp[1:0] = S_AXI_1_BRESP;
assign AXI_LITE_IIC_bvalid = S_AXI_1_BVALID;
assign AXI_LITE_IIC_rdata[31:0] = S_AXI_1_RDATA;
assign AXI_LITE_IIC_rresp[1:0] = S_AXI_1_RRESP;
assign AXI_LITE_IIC_rvalid = S_AXI_1_RVALID;
assign AXI_LITE_IIC_wready = S_AXI_1_WREADY;
assign I2C_Interrupt = axi_iic_0_iic2intc_irpt;
assign Pmod_out_pin10_o = pmod_bridge_0_Pmod_out_PIN10_O;
assign Pmod_out_pin10_t = pmod_bridge_0_Pmod_out_PIN10_T;
assign Pmod_out_pin1_o = pmod_bridge_0_Pmod_out_PIN1_O;
assign Pmod_out_pin1_t = pmod_bridge_0_Pmod_out_PIN1_T;
assign Pmod_out_pin2_o = pmod_bridge_0_Pmod_out_PIN2_O;
assign Pmod_out_pin2_t = pmod_bridge_0_Pmod_out_PIN2_T;
assign Pmod_out_pin3_o = pmod_bridge_0_Pmod_out_PIN3_O;
assign Pmod_out_pin3_t = pmod_bridge_0_Pmod_out_PIN3_T;
assign Pmod_out_pin4_o = pmod_bridge_0_Pmod_out_PIN4_O;
assign Pmod_out_pin4_t = pmod_bridge_0_Pmod_out_PIN4_T;
assign Pmod_out_pin7_o = pmod_bridge_0_Pmod_out_PIN7_O;
assign Pmod_out_pin7_t = pmod_bridge_0_Pmod_out_PIN7_T;
assign Pmod_out_pin8_o = pmod_bridge_0_Pmod_out_PIN8_O;
assign Pmod_out_pin8_t = pmod_bridge_0_Pmod_out_PIN8_T;
assign Pmod_out_pin9_o = pmod_bridge_0_Pmod_out_PIN9_O;
assign Pmod_out_pin9_t = pmod_bridge_0_Pmod_out_PIN9_T;
assign S_AXI_1_ARADDR = AXI_LITE_IIC_araddr[8:0];
assign S_AXI_1_ARVALID = AXI_LITE_IIC_arvalid;
assign S_AXI_1_AWADDR = AXI_LITE_IIC_awaddr[8:0];
assign S_AXI_1_AWVALID = AXI_LITE_IIC_awvalid;
assign S_AXI_1_BREADY = AXI_LITE_IIC_bready;
assign S_AXI_1_RREADY = AXI_LITE_IIC_rready;
assign S_AXI_1_WDATA = AXI_LITE_IIC_wdata[31:0];
assign S_AXI_1_WSTRB = AXI_LITE_IIC_wstrb[3:0];
assign S_AXI_1_WVALID = AXI_LITE_IIC_wvalid;
assign pmod_bridge_0_Pmod_out_PIN10_I = Pmod_out_pin10_i;
assign pmod_bridge_0_Pmod_out_PIN1_I = Pmod_out_pin1_i;
assign pmod_bridge_0_Pmod_out_PIN2_I = Pmod_out_pin2_i;
assign pmod_bridge_0_Pmod_out_PIN3_I = Pmod_out_pin3_i;
assign pmod_bridge_0_Pmod_out_PIN4_I = Pmod_out_pin4_i;
assign pmod_bridge_0_Pmod_out_PIN7_I = Pmod_out_pin7_i;
assign pmod_bridge_0_Pmod_out_PIN8_I = Pmod_out_pin8_i;
assign pmod_bridge_0_Pmod_out_PIN9_I = Pmod_out_pin9_i;
assign s_axi_aclk_1 = s_axi_aclk;
assign s_axi_aresetn_1 = s_axi_aresetn;
PmodHYGRO_axi_iic_0_0 axi_iic_0
(.gpo(axi_iic_0_gpo),
.iic2intc_irpt(axi_iic_0_iic2intc_irpt),
.s_axi_aclk(s_axi_aclk_1),
.s_axi_araddr(S_AXI_1_ARADDR),
.s_axi_aresetn(s_axi_aresetn_1),
.s_axi_arready(S_AXI_1_ARREADY),
.s_axi_arvalid(S_AXI_1_ARVALID),
.s_axi_awaddr(S_AXI_1_AWADDR),
.s_axi_awready(S_AXI_1_AWREADY),
.s_axi_awvalid(S_AXI_1_AWVALID),
.s_axi_bready(S_AXI_1_BREADY),
.s_axi_bresp(S_AXI_1_BRESP),
.s_axi_bvalid(S_AXI_1_BVALID),
.s_axi_rdata(S_AXI_1_RDATA),
.s_axi_rready(S_AXI_1_RREADY),
.s_axi_rresp(S_AXI_1_RRESP),
.s_axi_rvalid(S_AXI_1_RVALID),
.s_axi_wdata(S_AXI_1_WDATA),
.s_axi_wready(S_AXI_1_WREADY),
.s_axi_wstrb(S_AXI_1_WSTRB),
.s_axi_wvalid(S_AXI_1_WVALID),
.scl_i(axi_iic_0_IIC_SCL_I),
.scl_o(axi_iic_0_IIC_SCL_O),
.scl_t(axi_iic_0_IIC_SCL_T),
.sda_i(axi_iic_0_IIC_SDA_I),
.sda_o(axi_iic_0_IIC_SDA_O),
.sda_t(axi_iic_0_IIC_SDA_T));
PmodHYGRO_pmod_bridge_0_0 pmod_bridge_0
(.in2_I(axi_iic_0_IIC_SCL_I),
.in2_O(axi_iic_0_IIC_SCL_O),
.in2_T(axi_iic_0_IIC_SCL_T),
.in3_I(axi_iic_0_IIC_SDA_I),
.in3_O(axi_iic_0_IIC_SDA_O),
.in3_T(axi_iic_0_IIC_SDA_T),
.in_top_i2c_gpio_bus_O(axi_iic_0_gpo),
.in_top_i2c_gpio_bus_T(xlconstant_0_dout),
.out0_I(pmod_bridge_0_Pmod_out_PIN1_I),
.out0_O(pmod_bridge_0_Pmod_out_PIN1_O),
.out0_T(pmod_bridge_0_Pmod_out_PIN1_T),
.out1_I(pmod_bridge_0_Pmod_out_PIN2_I),
.out1_O(pmod_bridge_0_Pmod_out_PIN2_O),
.out1_T(pmod_bridge_0_Pmod_out_PIN2_T),
.out2_I(pmod_bridge_0_Pmod_out_PIN3_I),
.out2_O(pmod_bridge_0_Pmod_out_PIN3_O),
.out2_T(pmod_bridge_0_Pmod_out_PIN3_T),
.out3_I(pmod_bridge_0_Pmod_out_PIN4_I),
.out3_O(pmod_bridge_0_Pmod_out_PIN4_O),
.out3_T(pmod_bridge_0_Pmod_out_PIN4_T),
.out4_I(pmod_bridge_0_Pmod_out_PIN7_I),
.out4_O(pmod_bridge_0_Pmod_out_PIN7_O),
.out4_T(pmod_bridge_0_Pmod_out_PIN7_T),
.out5_I(pmod_bridge_0_Pmod_out_PIN8_I),
.out5_O(pmod_bridge_0_Pmod_out_PIN8_O),
.out5_T(pmod_bridge_0_Pmod_out_PIN8_T),
.out6_I(pmod_bridge_0_Pmod_out_PIN9_I),
.out6_O(pmod_bridge_0_Pmod_out_PIN9_O),
.out6_T(pmod_bridge_0_Pmod_out_PIN9_T),
.out7_I(pmod_bridge_0_Pmod_out_PIN10_I),
.out7_O(pmod_bridge_0_Pmod_out_PIN10_O),
.out7_T(pmod_bridge_0_Pmod_out_PIN10_T));
PmodHYGRO_xlconstant_0_0 xlconstant_0
(.dout(xlconstant_0_dout));
endmodule
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