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`timescale 1ns / 1ps
//AND Gate
module andgate(a, b, out);
input a, b;
output out;
assign out = a & b;
endmodule
//Testbench definition for AND Gate
module andgate_tb;
wire t_out;
reg t_a, t_b;
andgate my_gate( .a(t_a), .b(t_b), .out(t_out) );
initial
begin
$monitor(t_a, t_b, t_out);
t_a = 1'b0;
t_b = 1'b0;
#5
t_a = 1'b0;
t_b = 1'b1;
#5
t_a = 1'b1;
t_b = 1'b0;
#5
t_a = 1'b1;
t_b = 1'b1;
end
endmodule
// AND Gate 16
module andgate16(a, b, out);
input [15:0] a, b;
output [15:0] out;
assign out = a & b;
endmodule
//Testbench definition for AND Gate
module andgate16_tb;
wire [15:0] t_out;
reg [15:0] t_a, t_b;
andgate16 my_gate( .a(t_a), .b(t_b), .out(t_out) );
initial
begin
$monitor(t_a, t_b, t_out);
t_a = 16'b0;
t_b = 16'b0;
#5
t_a = 16'b0;
t_b = 16'b1111111111111111;
#5
t_a = 16'b1111111111111111;
t_b = 16'b0;
#5
t_a = 16'b1111111111111111;
t_b = 16'b1111111111111111;
end
endmodule
// Mux8Way16
module mux8way16(a, b, c, d, e ,f, g, h, sel, out);
input [15:0] a, b, c, d, e, f, g, h;
input [2:0] sel;
output reg [15:0] out;
always @(sel)
begin
case (sel)
3'b000 : out = a;
3'b001 : out = b;
3'b010 : out = c;
3'b011 : out = d;
3'b100 : out = e;
3'b101 : out = f;
3'b110 : out = g;
3'b111 : out = h;
default out = 3'b000;
endcase
end
endmodule
//Testbench definition for Mux8Way16
module mux8way16_tb;
wire [15:0] t_out;
reg [15:0] t_a, t_b, t_c, t_d, t_e, t_f, t_g, t_h;
reg [2:0] t_sel;
mux8way16 my_gate( .a(t_a), .b(t_b), .c(t_c), .d(t_d), .e(t_e), .f(t_f), .g(t_g), .h(t_h), .sel(t_sel), .out(t_out) );
initial
begin
$monitor(t_a, t_b, t_c, t_d, t_e, t_f, t_g, t_h, t_out);
t_a = 16'b0000000000000000;
t_b = 16'b0000000000000011;
t_c = 16'b0000000000001100;
t_d = 16'b0000000000110000;
t_e = 16'b0000000011000000;
t_f = 16'b0000001100000000;
t_g = 16'b0000110000000000;
t_h = 16'b0011000000000000;
t_sel = 3'b000;
#5
t_sel = 3'b000;
#5
t_sel = 3'b001;
#5
t_sel = 3'b010;
#5
t_sel = 3'b011;
#5
t_sel = 3'b010;
#5
t_sel = 3'b011;
#5
t_sel = 3'b100;
#5
t_sel = 3'b101;
#5
t_sel = 3'b111;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XOR2_PP_SYMBOL_V
`define SKY130_FD_SC_HS__XOR2_PP_SYMBOL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__xor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__XOR2_PP_SYMBOL_V
|
module hc161_like ( //Этот модуль описывает только одну часть маппера UNROM:
//регистр, в который CPU записывает номер текущего банка памяти PRG ROM.
//Вторая часть - микросхема содержащая сборку из четырех ИЛИ элементов, реализована графически.
//This module only a part of an UNROM mapper. Register keeps a PRG ROM bank number.
//The second part is 4 x OR chip. It's implemented graphically.
input wire [3:0] cpu_d
, input wire cpu_rw
, input wire Ncpu_romsel
, output wire hc161_out0
, output wire hc161_out1
, output wire hc161_out2
, output wire hc161_out3
);
reg [3:0] hc161_krn; //сам регистр, хранящий четырехбитное число - номер банка
//register for a bank number
assign hc161_out0 = hc161_krn [0:0];
assign hc161_out1 = hc161_krn [1:1];
assign hc161_out2 = hc161_krn [2:2];
assign hc161_out3 = hc161_krn [3:3]; //выходы регистра
//register outputs
always @(posedge Ncpu_romsel) //сигнал обращения CPU к картриджу
//Ncpu_romsel is a cartridge selecting signal
begin
if (!cpu_rw) //низкий уровень сигнала - CPU производит запись
//low level - CPU make write to the cartridge
begin
hc161_krn <= cpu_d;
end
end
endmodule
|
/****************************************
MIST1032 - Core
****************************************/
`default_nettype none
module core
#(
parameter CORE_ID = 32'h0
)(
/****************************************
System
****************************************/
input wire iCLOCK,
input wire inRESET,
/****************************************
Core
****************************************/
//oCORE_FLASH,
output wire oFREE_TLB_FLUSH,
/****************************************
GCI Controll
****************************************/
//Interrupt Controll
output wire oIO_IRQ_CONFIG_TABLE_REQ,
output wire [5:0] oIO_IRQ_CONFIG_TABLE_ENTRY,
output wire oIO_IRQ_CONFIG_TABLE_FLAG_MASK,
output wire oIO_IRQ_CONFIG_TABLE_FLAG_VALID,
output wire [1:0] oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL,
/****************************************
Instruction Memory
****************************************/
//Req
output wire oINST_REQ,
input wire iINST_LOCK,
output wire [1:0] oINST_MMUMOD,
output wire [2:0] oINST_MMUPS,
output wire [31:0] oINST_PDT,
output wire [13:0] oINST_ASID,
output wire [31:0] oINST_ADDR,
//RAM -> This
input wire iINST_VALID,
output wire oINST_BUSY,
input wire [63:0] iINST_DATA,
input wire [23:0] iINST_MMU_FLAGS,
/****************************************
Data Memory
****************************************/
//Req
output wire oDATA_REQ,
input wire iDATA_LOCK,
output wire [1:0] oDATA_ORDER,
output wire [3:0] oDATA_MASK,
output wire oDATA_RW, //0=Write 1=Read
output wire [13:0] oDATA_ASID,
output wire [1:0] oDATA_MMUMOD,
output wire [2:0] oDATA_MMUPS,
output wire [31:0] oDATA_PDT,
output wire [31:0] oDATA_ADDR,
//This -> Data RAM
output wire [31:0] oDATA_DATA,
//Data RAM -> This
input wire iDATA_VALID,
input wire [63:0] iDATA_DATA,
input wire [23:0] iDATA_MMU_FLAGS,
/****************************************
IO
****************************************/
//Req
output wire oIO_REQ,
input wire iIO_BUSY,
output wire [1:0] oIO_ORDER,
output wire oIO_RW, //0=Write 1=Read
output wire [31:0] oIO_ADDR,
//Write
output wire [31:0] oIO_DATA,
//Rec
input wire iIO_VALID,
input wire [31:0] iIO_DATA,
/****************************************
Interrupt
****************************************/
input wire iINTERRUPT_VALID,
output wire oINTERRUPT_ACK,
input wire [5:0] iINTERRUPT_NUM,
/****************************************
System Infomation
****************************************/
input wire iSYSINFO_IOSR_VALID,
input wire [31:0] iSYSINFO_IOSR,
/****************************************
Debug
****************************************/
output wire [31:0] oDEBUG_PC,
input wire iDEBUG_CMD_REQ,
output wire oDEBUG_CMD_BUSY,
input wire [3:0] iDEBUG_CMD_COMMAND,
input wire [7:0] iDEBUG_CMD_TARGET,
input wire [31:0] iDEBUG_CMD_DATA,
output wire oDEBUG_CMD_VALID,
output wire oDEBUG_CMD_ERROR,
output wire [31:0] oDEBUG_CMD_DATA
);
/************************************************************************************
Wire and Register
************************************************************************************/
wire [31:0] debug0;
/************************************************************************************
Core - Main Pipeline
************************************************************************************/
core_pipeline #(CORE_ID) CORE_PIPELINE(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Core
.oFREE_TLB_FLUSH(oFREE_TLB_FLUSH),
//GCI Interrupt Controll
//Interrupt Control
.oIO_IRQ_CONFIG_TABLE_REQ(oIO_IRQ_CONFIG_TABLE_REQ),
.oIO_IRQ_CONFIG_TABLE_ENTRY(oIO_IRQ_CONFIG_TABLE_ENTRY),
.oIO_IRQ_CONFIG_TABLE_FLAG_MASK(oIO_IRQ_CONFIG_TABLE_FLAG_MASK),
.oIO_IRQ_CONFIG_TABLE_FLAG_VALID(oIO_IRQ_CONFIG_TABLE_FLAG_VALID),
.oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL(oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL),
//Instruction Memory Request
.oINST_FETCH_REQ(oINST_REQ),
.iINST_FETCH_BUSY(iINST_LOCK),
.oINST_FETCH_MMUMOD(oINST_MMUMOD),
.oINST_FETCH_MMUPS(oINST_MMUPS),
.oINST_FETCH_PDT(oINST_PDT),
.oINST_FETCH_ASID(oINST_ASID),
.oINST_FETCH_ADDR(oINST_ADDR),
.iINST_VALID(iINST_VALID),
.oINST_BUSY(oINST_BUSY),
.iINST_DATA(iINST_DATA),
.iINST_MMU_FLAGS(iINST_MMU_FLAGS),
/****************************************
Data Memory
****************************************/
//Req
.oDATA_REQ(oDATA_REQ),
.iDATA_LOCK(iDATA_LOCK),
.oDATA_ORDER(oDATA_ORDER), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.oDATA_MASK(oDATA_MASK),
.oDATA_RW(oDATA_RW), //1=Write 0=Read
.oDATA_ASID(oDATA_ASID),
.oDATA_MMUMOD(oDATA_MMUMOD),
.oDATA_MMUPS(oDATA_MMUPS),
.oDATA_PDT(oDATA_PDT),
.oDATA_ADDR(oDATA_ADDR),
//This -> Data RAM
.oDATA_DATA(oDATA_DATA),
//Data RAM -> This
.iDATA_VALID(iDATA_VALID),
.iDATA_DATA(iDATA_DATA),
.iDATA_MMU_FLAGS(iDATA_MMU_FLAGS),
/****************************************
IO
****************************************/
//Req
.oIO_REQ(oIO_REQ),
.iIO_BUSY(iIO_BUSY),
.oIO_ORDER(oIO_ORDER), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.oIO_RW(oIO_RW), //0=Write 1=Read
.oIO_ADDR(oIO_ADDR),
//Write
.oIO_DATA(oIO_DATA),
//Rec
.iIO_VALID(iIO_VALID),
.iIO_DATA(iIO_DATA),
//Interrupt
.iINTERRUPT_VALID(iINTERRUPT_VALID),
.oINTERRUPT_ACK(oINTERRUPT_ACK),
.iINTERRUPT_NUM(iINTERRUPT_NUM),
.iSYSINFO_IOSR_VALID(iSYSINFO_IOSR_VALID),
.iSYSINFO_IOSR(iSYSINFO_IOSR),
.oDEBUG_PC(oDEBUG_PC),
/****************************************
Debug
****************************************/
.iDEBUG_CMD_REQ(iDEBUG_CMD_REQ),
.oDEBUG_CMD_BUSY(oDEBUG_CMD_BUSY),
.iDEBUG_CMD_COMMAND(iDEBUG_CMD_COMMAND),
.iDEBUG_CMD_TARGET(iDEBUG_CMD_TARGET),
.iDEBUG_CMD_DATA(iDEBUG_CMD_DATA),
.oDEBUG_CMD_VALID(oDEBUG_CMD_VALID),
.oDEBUG_CMD_ERROR(oDEBUG_CMD_ERROR),
.oDEBUG_CMD_DATA(oDEBUG_CMD_DATA)
);
endmodule
`default_nettype wire
|
// system_acl_iface_acl_kernel_interface_mm_interconnect_1.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module system_acl_iface_acl_kernel_interface_mm_interconnect_1 (
input wire clk_reset_clk_clk, // clk_reset_clk.clk
input wire kernel_clk_out_clk_clk, // kernel_clk_out_clk.clk
input wire address_span_extender_0_reset_reset_bridge_in_reset_reset, // address_span_extender_0_reset_reset_bridge_in_reset.reset
input wire kernel_cntrl_reset_reset_bridge_in_reset_reset, // kernel_cntrl_reset_reset_bridge_in_reset.reset
input wire sw_reset_clk_reset_reset_bridge_in_reset_reset, // sw_reset_clk_reset_reset_bridge_in_reset.reset
input wire [13:0] kernel_cntrl_m0_address, // kernel_cntrl_m0.address
output wire kernel_cntrl_m0_waitrequest, // .waitrequest
input wire [0:0] kernel_cntrl_m0_burstcount, // .burstcount
input wire [3:0] kernel_cntrl_m0_byteenable, // .byteenable
input wire kernel_cntrl_m0_read, // .read
output wire [31:0] kernel_cntrl_m0_readdata, // .readdata
output wire kernel_cntrl_m0_readdatavalid, // .readdatavalid
input wire kernel_cntrl_m0_write, // .write
input wire [31:0] kernel_cntrl_m0_writedata, // .writedata
input wire kernel_cntrl_m0_debugaccess, // .debugaccess
output wire address_span_extender_0_cntl_write, // address_span_extender_0_cntl.write
output wire address_span_extender_0_cntl_read, // .read
input wire [63:0] address_span_extender_0_cntl_readdata, // .readdata
output wire [63:0] address_span_extender_0_cntl_writedata, // .writedata
output wire [7:0] address_span_extender_0_cntl_byteenable, // .byteenable
output wire [9:0] address_span_extender_0_windowed_slave_address, // address_span_extender_0_windowed_slave.address
output wire address_span_extender_0_windowed_slave_write, // .write
output wire address_span_extender_0_windowed_slave_read, // .read
input wire [31:0] address_span_extender_0_windowed_slave_readdata, // .readdata
output wire [31:0] address_span_extender_0_windowed_slave_writedata, // .writedata
output wire [0:0] address_span_extender_0_windowed_slave_burstcount, // .burstcount
output wire [3:0] address_span_extender_0_windowed_slave_byteenable, // .byteenable
input wire address_span_extender_0_windowed_slave_readdatavalid, // .readdatavalid
input wire address_span_extender_0_windowed_slave_waitrequest, // .waitrequest
output wire irq_ena_0_s_write, // irq_ena_0_s.write
output wire irq_ena_0_s_read, // .read
input wire [31:0] irq_ena_0_s_readdata, // .readdata
output wire [31:0] irq_ena_0_s_writedata, // .writedata
output wire [3:0] irq_ena_0_s_byteenable, // .byteenable
input wire irq_ena_0_s_waitrequest, // .waitrequest
output wire mem_org_mode_s_write, // mem_org_mode_s.write
output wire mem_org_mode_s_read, // .read
input wire [31:0] mem_org_mode_s_readdata, // .readdata
output wire [31:0] mem_org_mode_s_writedata, // .writedata
input wire mem_org_mode_s_waitrequest, // .waitrequest
output wire sw_reset_s_write, // sw_reset_s.write
output wire sw_reset_s_read, // .read
input wire [63:0] sw_reset_s_readdata, // .readdata
output wire [63:0] sw_reset_s_writedata, // .writedata
output wire [7:0] sw_reset_s_byteenable, // .byteenable
input wire sw_reset_s_waitrequest, // .waitrequest
output wire [8:0] sys_description_rom_s1_address, // sys_description_rom_s1.address
output wire sys_description_rom_s1_write, // .write
input wire [63:0] sys_description_rom_s1_readdata, // .readdata
output wire [63:0] sys_description_rom_s1_writedata, // .writedata
output wire [7:0] sys_description_rom_s1_byteenable, // .byteenable
output wire sys_description_rom_s1_chipselect, // .chipselect
output wire sys_description_rom_s1_clken, // .clken
output wire sys_description_rom_s1_debugaccess, // .debugaccess
output wire version_id_0_s_read, // version_id_0_s.read
input wire [31:0] version_id_0_s_readdata // .readdata
);
wire kernel_cntrl_m0_translator_avalon_universal_master_0_waitrequest; // kernel_cntrl_m0_agent:av_waitrequest -> kernel_cntrl_m0_translator:uav_waitrequest
wire [31:0] kernel_cntrl_m0_translator_avalon_universal_master_0_readdata; // kernel_cntrl_m0_agent:av_readdata -> kernel_cntrl_m0_translator:uav_readdata
wire kernel_cntrl_m0_translator_avalon_universal_master_0_debugaccess; // kernel_cntrl_m0_translator:uav_debugaccess -> kernel_cntrl_m0_agent:av_debugaccess
wire [13:0] kernel_cntrl_m0_translator_avalon_universal_master_0_address; // kernel_cntrl_m0_translator:uav_address -> kernel_cntrl_m0_agent:av_address
wire kernel_cntrl_m0_translator_avalon_universal_master_0_read; // kernel_cntrl_m0_translator:uav_read -> kernel_cntrl_m0_agent:av_read
wire [3:0] kernel_cntrl_m0_translator_avalon_universal_master_0_byteenable; // kernel_cntrl_m0_translator:uav_byteenable -> kernel_cntrl_m0_agent:av_byteenable
wire kernel_cntrl_m0_translator_avalon_universal_master_0_readdatavalid; // kernel_cntrl_m0_agent:av_readdatavalid -> kernel_cntrl_m0_translator:uav_readdatavalid
wire kernel_cntrl_m0_translator_avalon_universal_master_0_lock; // kernel_cntrl_m0_translator:uav_lock -> kernel_cntrl_m0_agent:av_lock
wire kernel_cntrl_m0_translator_avalon_universal_master_0_write; // kernel_cntrl_m0_translator:uav_write -> kernel_cntrl_m0_agent:av_write
wire [31:0] kernel_cntrl_m0_translator_avalon_universal_master_0_writedata; // kernel_cntrl_m0_translator:uav_writedata -> kernel_cntrl_m0_agent:av_writedata
wire [2:0] kernel_cntrl_m0_translator_avalon_universal_master_0_burstcount; // kernel_cntrl_m0_translator:uav_burstcount -> kernel_cntrl_m0_agent:av_burstcount
wire [31:0] address_span_extender_0_windowed_slave_agent_m0_readdata; // address_span_extender_0_windowed_slave_translator:uav_readdata -> address_span_extender_0_windowed_slave_agent:m0_readdata
wire address_span_extender_0_windowed_slave_agent_m0_waitrequest; // address_span_extender_0_windowed_slave_translator:uav_waitrequest -> address_span_extender_0_windowed_slave_agent:m0_waitrequest
wire address_span_extender_0_windowed_slave_agent_m0_debugaccess; // address_span_extender_0_windowed_slave_agent:m0_debugaccess -> address_span_extender_0_windowed_slave_translator:uav_debugaccess
wire [13:0] address_span_extender_0_windowed_slave_agent_m0_address; // address_span_extender_0_windowed_slave_agent:m0_address -> address_span_extender_0_windowed_slave_translator:uav_address
wire [3:0] address_span_extender_0_windowed_slave_agent_m0_byteenable; // address_span_extender_0_windowed_slave_agent:m0_byteenable -> address_span_extender_0_windowed_slave_translator:uav_byteenable
wire address_span_extender_0_windowed_slave_agent_m0_read; // address_span_extender_0_windowed_slave_agent:m0_read -> address_span_extender_0_windowed_slave_translator:uav_read
wire address_span_extender_0_windowed_slave_agent_m0_readdatavalid; // address_span_extender_0_windowed_slave_translator:uav_readdatavalid -> address_span_extender_0_windowed_slave_agent:m0_readdatavalid
wire address_span_extender_0_windowed_slave_agent_m0_lock; // address_span_extender_0_windowed_slave_agent:m0_lock -> address_span_extender_0_windowed_slave_translator:uav_lock
wire [31:0] address_span_extender_0_windowed_slave_agent_m0_writedata; // address_span_extender_0_windowed_slave_agent:m0_writedata -> address_span_extender_0_windowed_slave_translator:uav_writedata
wire address_span_extender_0_windowed_slave_agent_m0_write; // address_span_extender_0_windowed_slave_agent:m0_write -> address_span_extender_0_windowed_slave_translator:uav_write
wire [2:0] address_span_extender_0_windowed_slave_agent_m0_burstcount; // address_span_extender_0_windowed_slave_agent:m0_burstcount -> address_span_extender_0_windowed_slave_translator:uav_burstcount
wire address_span_extender_0_windowed_slave_agent_rf_source_valid; // address_span_extender_0_windowed_slave_agent:rf_source_valid -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_valid
wire [89:0] address_span_extender_0_windowed_slave_agent_rf_source_data; // address_span_extender_0_windowed_slave_agent:rf_source_data -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_data
wire address_span_extender_0_windowed_slave_agent_rf_source_ready; // address_span_extender_0_windowed_slave_agent_rsp_fifo:in_ready -> address_span_extender_0_windowed_slave_agent:rf_source_ready
wire address_span_extender_0_windowed_slave_agent_rf_source_startofpacket; // address_span_extender_0_windowed_slave_agent:rf_source_startofpacket -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_startofpacket
wire address_span_extender_0_windowed_slave_agent_rf_source_endofpacket; // address_span_extender_0_windowed_slave_agent:rf_source_endofpacket -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_endofpacket
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_valid; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_valid -> address_span_extender_0_windowed_slave_agent:rf_sink_valid
wire [89:0] address_span_extender_0_windowed_slave_agent_rsp_fifo_out_data; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_data -> address_span_extender_0_windowed_slave_agent:rf_sink_data
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_ready; // address_span_extender_0_windowed_slave_agent:rf_sink_ready -> address_span_extender_0_windowed_slave_agent_rsp_fifo:out_ready
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_startofpacket; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_startofpacket -> address_span_extender_0_windowed_slave_agent:rf_sink_startofpacket
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_endofpacket; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_endofpacket -> address_span_extender_0_windowed_slave_agent:rf_sink_endofpacket
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_src_valid; // address_span_extender_0_windowed_slave_agent:rdata_fifo_src_valid -> address_span_extender_0_windowed_slave_agent_rdata_fifo:in_valid
wire [33:0] address_span_extender_0_windowed_slave_agent_rdata_fifo_src_data; // address_span_extender_0_windowed_slave_agent:rdata_fifo_src_data -> address_span_extender_0_windowed_slave_agent_rdata_fifo:in_data
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_src_ready; // address_span_extender_0_windowed_slave_agent_rdata_fifo:in_ready -> address_span_extender_0_windowed_slave_agent:rdata_fifo_src_ready
wire cmd_mux_src_valid; // cmd_mux:src_valid -> address_span_extender_0_windowed_slave_agent:cp_valid
wire [88:0] cmd_mux_src_data; // cmd_mux:src_data -> address_span_extender_0_windowed_slave_agent:cp_data
wire cmd_mux_src_ready; // address_span_extender_0_windowed_slave_agent:cp_ready -> cmd_mux:src_ready
wire [6:0] cmd_mux_src_channel; // cmd_mux:src_channel -> address_span_extender_0_windowed_slave_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> address_span_extender_0_windowed_slave_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> address_span_extender_0_windowed_slave_agent:cp_endofpacket
wire [63:0] address_span_extender_0_cntl_agent_m0_readdata; // address_span_extender_0_cntl_translator:uav_readdata -> address_span_extender_0_cntl_agent:m0_readdata
wire address_span_extender_0_cntl_agent_m0_waitrequest; // address_span_extender_0_cntl_translator:uav_waitrequest -> address_span_extender_0_cntl_agent:m0_waitrequest
wire address_span_extender_0_cntl_agent_m0_debugaccess; // address_span_extender_0_cntl_agent:m0_debugaccess -> address_span_extender_0_cntl_translator:uav_debugaccess
wire [13:0] address_span_extender_0_cntl_agent_m0_address; // address_span_extender_0_cntl_agent:m0_address -> address_span_extender_0_cntl_translator:uav_address
wire [7:0] address_span_extender_0_cntl_agent_m0_byteenable; // address_span_extender_0_cntl_agent:m0_byteenable -> address_span_extender_0_cntl_translator:uav_byteenable
wire address_span_extender_0_cntl_agent_m0_read; // address_span_extender_0_cntl_agent:m0_read -> address_span_extender_0_cntl_translator:uav_read
wire address_span_extender_0_cntl_agent_m0_readdatavalid; // address_span_extender_0_cntl_translator:uav_readdatavalid -> address_span_extender_0_cntl_agent:m0_readdatavalid
wire address_span_extender_0_cntl_agent_m0_lock; // address_span_extender_0_cntl_agent:m0_lock -> address_span_extender_0_cntl_translator:uav_lock
wire [63:0] address_span_extender_0_cntl_agent_m0_writedata; // address_span_extender_0_cntl_agent:m0_writedata -> address_span_extender_0_cntl_translator:uav_writedata
wire address_span_extender_0_cntl_agent_m0_write; // address_span_extender_0_cntl_agent:m0_write -> address_span_extender_0_cntl_translator:uav_write
wire [3:0] address_span_extender_0_cntl_agent_m0_burstcount; // address_span_extender_0_cntl_agent:m0_burstcount -> address_span_extender_0_cntl_translator:uav_burstcount
wire address_span_extender_0_cntl_agent_rf_source_valid; // address_span_extender_0_cntl_agent:rf_source_valid -> address_span_extender_0_cntl_agent_rsp_fifo:in_valid
wire [125:0] address_span_extender_0_cntl_agent_rf_source_data; // address_span_extender_0_cntl_agent:rf_source_data -> address_span_extender_0_cntl_agent_rsp_fifo:in_data
wire address_span_extender_0_cntl_agent_rf_source_ready; // address_span_extender_0_cntl_agent_rsp_fifo:in_ready -> address_span_extender_0_cntl_agent:rf_source_ready
wire address_span_extender_0_cntl_agent_rf_source_startofpacket; // address_span_extender_0_cntl_agent:rf_source_startofpacket -> address_span_extender_0_cntl_agent_rsp_fifo:in_startofpacket
wire address_span_extender_0_cntl_agent_rf_source_endofpacket; // address_span_extender_0_cntl_agent:rf_source_endofpacket -> address_span_extender_0_cntl_agent_rsp_fifo:in_endofpacket
wire address_span_extender_0_cntl_agent_rsp_fifo_out_valid; // address_span_extender_0_cntl_agent_rsp_fifo:out_valid -> address_span_extender_0_cntl_agent:rf_sink_valid
wire [125:0] address_span_extender_0_cntl_agent_rsp_fifo_out_data; // address_span_extender_0_cntl_agent_rsp_fifo:out_data -> address_span_extender_0_cntl_agent:rf_sink_data
wire address_span_extender_0_cntl_agent_rsp_fifo_out_ready; // address_span_extender_0_cntl_agent:rf_sink_ready -> address_span_extender_0_cntl_agent_rsp_fifo:out_ready
wire address_span_extender_0_cntl_agent_rsp_fifo_out_startofpacket; // address_span_extender_0_cntl_agent_rsp_fifo:out_startofpacket -> address_span_extender_0_cntl_agent:rf_sink_startofpacket
wire address_span_extender_0_cntl_agent_rsp_fifo_out_endofpacket; // address_span_extender_0_cntl_agent_rsp_fifo:out_endofpacket -> address_span_extender_0_cntl_agent:rf_sink_endofpacket
wire address_span_extender_0_cntl_agent_rdata_fifo_src_valid; // address_span_extender_0_cntl_agent:rdata_fifo_src_valid -> address_span_extender_0_cntl_agent_rdata_fifo:in_valid
wire [65:0] address_span_extender_0_cntl_agent_rdata_fifo_src_data; // address_span_extender_0_cntl_agent:rdata_fifo_src_data -> address_span_extender_0_cntl_agent_rdata_fifo:in_data
wire address_span_extender_0_cntl_agent_rdata_fifo_src_ready; // address_span_extender_0_cntl_agent_rdata_fifo:in_ready -> address_span_extender_0_cntl_agent:rdata_fifo_src_ready
wire [63:0] sys_description_rom_s1_agent_m0_readdata; // sys_description_rom_s1_translator:uav_readdata -> sys_description_rom_s1_agent:m0_readdata
wire sys_description_rom_s1_agent_m0_waitrequest; // sys_description_rom_s1_translator:uav_waitrequest -> sys_description_rom_s1_agent:m0_waitrequest
wire sys_description_rom_s1_agent_m0_debugaccess; // sys_description_rom_s1_agent:m0_debugaccess -> sys_description_rom_s1_translator:uav_debugaccess
wire [13:0] sys_description_rom_s1_agent_m0_address; // sys_description_rom_s1_agent:m0_address -> sys_description_rom_s1_translator:uav_address
wire [7:0] sys_description_rom_s1_agent_m0_byteenable; // sys_description_rom_s1_agent:m0_byteenable -> sys_description_rom_s1_translator:uav_byteenable
wire sys_description_rom_s1_agent_m0_read; // sys_description_rom_s1_agent:m0_read -> sys_description_rom_s1_translator:uav_read
wire sys_description_rom_s1_agent_m0_readdatavalid; // sys_description_rom_s1_translator:uav_readdatavalid -> sys_description_rom_s1_agent:m0_readdatavalid
wire sys_description_rom_s1_agent_m0_lock; // sys_description_rom_s1_agent:m0_lock -> sys_description_rom_s1_translator:uav_lock
wire [63:0] sys_description_rom_s1_agent_m0_writedata; // sys_description_rom_s1_agent:m0_writedata -> sys_description_rom_s1_translator:uav_writedata
wire sys_description_rom_s1_agent_m0_write; // sys_description_rom_s1_agent:m0_write -> sys_description_rom_s1_translator:uav_write
wire [3:0] sys_description_rom_s1_agent_m0_burstcount; // sys_description_rom_s1_agent:m0_burstcount -> sys_description_rom_s1_translator:uav_burstcount
wire sys_description_rom_s1_agent_rf_source_valid; // sys_description_rom_s1_agent:rf_source_valid -> sys_description_rom_s1_agent_rsp_fifo:in_valid
wire [125:0] sys_description_rom_s1_agent_rf_source_data; // sys_description_rom_s1_agent:rf_source_data -> sys_description_rom_s1_agent_rsp_fifo:in_data
wire sys_description_rom_s1_agent_rf_source_ready; // sys_description_rom_s1_agent_rsp_fifo:in_ready -> sys_description_rom_s1_agent:rf_source_ready
wire sys_description_rom_s1_agent_rf_source_startofpacket; // sys_description_rom_s1_agent:rf_source_startofpacket -> sys_description_rom_s1_agent_rsp_fifo:in_startofpacket
wire sys_description_rom_s1_agent_rf_source_endofpacket; // sys_description_rom_s1_agent:rf_source_endofpacket -> sys_description_rom_s1_agent_rsp_fifo:in_endofpacket
wire sys_description_rom_s1_agent_rsp_fifo_out_valid; // sys_description_rom_s1_agent_rsp_fifo:out_valid -> sys_description_rom_s1_agent:rf_sink_valid
wire [125:0] sys_description_rom_s1_agent_rsp_fifo_out_data; // sys_description_rom_s1_agent_rsp_fifo:out_data -> sys_description_rom_s1_agent:rf_sink_data
wire sys_description_rom_s1_agent_rsp_fifo_out_ready; // sys_description_rom_s1_agent:rf_sink_ready -> sys_description_rom_s1_agent_rsp_fifo:out_ready
wire sys_description_rom_s1_agent_rsp_fifo_out_startofpacket; // sys_description_rom_s1_agent_rsp_fifo:out_startofpacket -> sys_description_rom_s1_agent:rf_sink_startofpacket
wire sys_description_rom_s1_agent_rsp_fifo_out_endofpacket; // sys_description_rom_s1_agent_rsp_fifo:out_endofpacket -> sys_description_rom_s1_agent:rf_sink_endofpacket
wire [63:0] sw_reset_s_agent_m0_readdata; // sw_reset_s_translator:uav_readdata -> sw_reset_s_agent:m0_readdata
wire sw_reset_s_agent_m0_waitrequest; // sw_reset_s_translator:uav_waitrequest -> sw_reset_s_agent:m0_waitrequest
wire sw_reset_s_agent_m0_debugaccess; // sw_reset_s_agent:m0_debugaccess -> sw_reset_s_translator:uav_debugaccess
wire [13:0] sw_reset_s_agent_m0_address; // sw_reset_s_agent:m0_address -> sw_reset_s_translator:uav_address
wire [7:0] sw_reset_s_agent_m0_byteenable; // sw_reset_s_agent:m0_byteenable -> sw_reset_s_translator:uav_byteenable
wire sw_reset_s_agent_m0_read; // sw_reset_s_agent:m0_read -> sw_reset_s_translator:uav_read
wire sw_reset_s_agent_m0_readdatavalid; // sw_reset_s_translator:uav_readdatavalid -> sw_reset_s_agent:m0_readdatavalid
wire sw_reset_s_agent_m0_lock; // sw_reset_s_agent:m0_lock -> sw_reset_s_translator:uav_lock
wire [63:0] sw_reset_s_agent_m0_writedata; // sw_reset_s_agent:m0_writedata -> sw_reset_s_translator:uav_writedata
wire sw_reset_s_agent_m0_write; // sw_reset_s_agent:m0_write -> sw_reset_s_translator:uav_write
wire [3:0] sw_reset_s_agent_m0_burstcount; // sw_reset_s_agent:m0_burstcount -> sw_reset_s_translator:uav_burstcount
wire sw_reset_s_agent_rf_source_valid; // sw_reset_s_agent:rf_source_valid -> sw_reset_s_agent_rsp_fifo:in_valid
wire [125:0] sw_reset_s_agent_rf_source_data; // sw_reset_s_agent:rf_source_data -> sw_reset_s_agent_rsp_fifo:in_data
wire sw_reset_s_agent_rf_source_ready; // sw_reset_s_agent_rsp_fifo:in_ready -> sw_reset_s_agent:rf_source_ready
wire sw_reset_s_agent_rf_source_startofpacket; // sw_reset_s_agent:rf_source_startofpacket -> sw_reset_s_agent_rsp_fifo:in_startofpacket
wire sw_reset_s_agent_rf_source_endofpacket; // sw_reset_s_agent:rf_source_endofpacket -> sw_reset_s_agent_rsp_fifo:in_endofpacket
wire sw_reset_s_agent_rsp_fifo_out_valid; // sw_reset_s_agent_rsp_fifo:out_valid -> sw_reset_s_agent:rf_sink_valid
wire [125:0] sw_reset_s_agent_rsp_fifo_out_data; // sw_reset_s_agent_rsp_fifo:out_data -> sw_reset_s_agent:rf_sink_data
wire sw_reset_s_agent_rsp_fifo_out_ready; // sw_reset_s_agent:rf_sink_ready -> sw_reset_s_agent_rsp_fifo:out_ready
wire sw_reset_s_agent_rsp_fifo_out_startofpacket; // sw_reset_s_agent_rsp_fifo:out_startofpacket -> sw_reset_s_agent:rf_sink_startofpacket
wire sw_reset_s_agent_rsp_fifo_out_endofpacket; // sw_reset_s_agent_rsp_fifo:out_endofpacket -> sw_reset_s_agent:rf_sink_endofpacket
wire [31:0] mem_org_mode_s_agent_m0_readdata; // mem_org_mode_s_translator:uav_readdata -> mem_org_mode_s_agent:m0_readdata
wire mem_org_mode_s_agent_m0_waitrequest; // mem_org_mode_s_translator:uav_waitrequest -> mem_org_mode_s_agent:m0_waitrequest
wire mem_org_mode_s_agent_m0_debugaccess; // mem_org_mode_s_agent:m0_debugaccess -> mem_org_mode_s_translator:uav_debugaccess
wire [13:0] mem_org_mode_s_agent_m0_address; // mem_org_mode_s_agent:m0_address -> mem_org_mode_s_translator:uav_address
wire [3:0] mem_org_mode_s_agent_m0_byteenable; // mem_org_mode_s_agent:m0_byteenable -> mem_org_mode_s_translator:uav_byteenable
wire mem_org_mode_s_agent_m0_read; // mem_org_mode_s_agent:m0_read -> mem_org_mode_s_translator:uav_read
wire mem_org_mode_s_agent_m0_readdatavalid; // mem_org_mode_s_translator:uav_readdatavalid -> mem_org_mode_s_agent:m0_readdatavalid
wire mem_org_mode_s_agent_m0_lock; // mem_org_mode_s_agent:m0_lock -> mem_org_mode_s_translator:uav_lock
wire [31:0] mem_org_mode_s_agent_m0_writedata; // mem_org_mode_s_agent:m0_writedata -> mem_org_mode_s_translator:uav_writedata
wire mem_org_mode_s_agent_m0_write; // mem_org_mode_s_agent:m0_write -> mem_org_mode_s_translator:uav_write
wire [2:0] mem_org_mode_s_agent_m0_burstcount; // mem_org_mode_s_agent:m0_burstcount -> mem_org_mode_s_translator:uav_burstcount
wire mem_org_mode_s_agent_rf_source_valid; // mem_org_mode_s_agent:rf_source_valid -> mem_org_mode_s_agent_rsp_fifo:in_valid
wire [89:0] mem_org_mode_s_agent_rf_source_data; // mem_org_mode_s_agent:rf_source_data -> mem_org_mode_s_agent_rsp_fifo:in_data
wire mem_org_mode_s_agent_rf_source_ready; // mem_org_mode_s_agent_rsp_fifo:in_ready -> mem_org_mode_s_agent:rf_source_ready
wire mem_org_mode_s_agent_rf_source_startofpacket; // mem_org_mode_s_agent:rf_source_startofpacket -> mem_org_mode_s_agent_rsp_fifo:in_startofpacket
wire mem_org_mode_s_agent_rf_source_endofpacket; // mem_org_mode_s_agent:rf_source_endofpacket -> mem_org_mode_s_agent_rsp_fifo:in_endofpacket
wire mem_org_mode_s_agent_rsp_fifo_out_valid; // mem_org_mode_s_agent_rsp_fifo:out_valid -> mem_org_mode_s_agent:rf_sink_valid
wire [89:0] mem_org_mode_s_agent_rsp_fifo_out_data; // mem_org_mode_s_agent_rsp_fifo:out_data -> mem_org_mode_s_agent:rf_sink_data
wire mem_org_mode_s_agent_rsp_fifo_out_ready; // mem_org_mode_s_agent:rf_sink_ready -> mem_org_mode_s_agent_rsp_fifo:out_ready
wire mem_org_mode_s_agent_rsp_fifo_out_startofpacket; // mem_org_mode_s_agent_rsp_fifo:out_startofpacket -> mem_org_mode_s_agent:rf_sink_startofpacket
wire mem_org_mode_s_agent_rsp_fifo_out_endofpacket; // mem_org_mode_s_agent_rsp_fifo:out_endofpacket -> mem_org_mode_s_agent:rf_sink_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> mem_org_mode_s_agent:cp_valid
wire [88:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> mem_org_mode_s_agent:cp_data
wire cmd_mux_004_src_ready; // mem_org_mode_s_agent:cp_ready -> cmd_mux_004:src_ready
wire [6:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> mem_org_mode_s_agent:cp_channel
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> mem_org_mode_s_agent:cp_startofpacket
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> mem_org_mode_s_agent:cp_endofpacket
wire [31:0] version_id_0_s_agent_m0_readdata; // version_id_0_s_translator:uav_readdata -> version_id_0_s_agent:m0_readdata
wire version_id_0_s_agent_m0_waitrequest; // version_id_0_s_translator:uav_waitrequest -> version_id_0_s_agent:m0_waitrequest
wire version_id_0_s_agent_m0_debugaccess; // version_id_0_s_agent:m0_debugaccess -> version_id_0_s_translator:uav_debugaccess
wire [13:0] version_id_0_s_agent_m0_address; // version_id_0_s_agent:m0_address -> version_id_0_s_translator:uav_address
wire [3:0] version_id_0_s_agent_m0_byteenable; // version_id_0_s_agent:m0_byteenable -> version_id_0_s_translator:uav_byteenable
wire version_id_0_s_agent_m0_read; // version_id_0_s_agent:m0_read -> version_id_0_s_translator:uav_read
wire version_id_0_s_agent_m0_readdatavalid; // version_id_0_s_translator:uav_readdatavalid -> version_id_0_s_agent:m0_readdatavalid
wire version_id_0_s_agent_m0_lock; // version_id_0_s_agent:m0_lock -> version_id_0_s_translator:uav_lock
wire [31:0] version_id_0_s_agent_m0_writedata; // version_id_0_s_agent:m0_writedata -> version_id_0_s_translator:uav_writedata
wire version_id_0_s_agent_m0_write; // version_id_0_s_agent:m0_write -> version_id_0_s_translator:uav_write
wire [2:0] version_id_0_s_agent_m0_burstcount; // version_id_0_s_agent:m0_burstcount -> version_id_0_s_translator:uav_burstcount
wire version_id_0_s_agent_rf_source_valid; // version_id_0_s_agent:rf_source_valid -> version_id_0_s_agent_rsp_fifo:in_valid
wire [89:0] version_id_0_s_agent_rf_source_data; // version_id_0_s_agent:rf_source_data -> version_id_0_s_agent_rsp_fifo:in_data
wire version_id_0_s_agent_rf_source_ready; // version_id_0_s_agent_rsp_fifo:in_ready -> version_id_0_s_agent:rf_source_ready
wire version_id_0_s_agent_rf_source_startofpacket; // version_id_0_s_agent:rf_source_startofpacket -> version_id_0_s_agent_rsp_fifo:in_startofpacket
wire version_id_0_s_agent_rf_source_endofpacket; // version_id_0_s_agent:rf_source_endofpacket -> version_id_0_s_agent_rsp_fifo:in_endofpacket
wire version_id_0_s_agent_rsp_fifo_out_valid; // version_id_0_s_agent_rsp_fifo:out_valid -> version_id_0_s_agent:rf_sink_valid
wire [89:0] version_id_0_s_agent_rsp_fifo_out_data; // version_id_0_s_agent_rsp_fifo:out_data -> version_id_0_s_agent:rf_sink_data
wire version_id_0_s_agent_rsp_fifo_out_ready; // version_id_0_s_agent:rf_sink_ready -> version_id_0_s_agent_rsp_fifo:out_ready
wire version_id_0_s_agent_rsp_fifo_out_startofpacket; // version_id_0_s_agent_rsp_fifo:out_startofpacket -> version_id_0_s_agent:rf_sink_startofpacket
wire version_id_0_s_agent_rsp_fifo_out_endofpacket; // version_id_0_s_agent_rsp_fifo:out_endofpacket -> version_id_0_s_agent:rf_sink_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> version_id_0_s_agent:cp_valid
wire [88:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> version_id_0_s_agent:cp_data
wire cmd_mux_005_src_ready; // version_id_0_s_agent:cp_ready -> cmd_mux_005:src_ready
wire [6:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> version_id_0_s_agent:cp_channel
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> version_id_0_s_agent:cp_startofpacket
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> version_id_0_s_agent:cp_endofpacket
wire [31:0] irq_ena_0_s_agent_m0_readdata; // irq_ena_0_s_translator:uav_readdata -> irq_ena_0_s_agent:m0_readdata
wire irq_ena_0_s_agent_m0_waitrequest; // irq_ena_0_s_translator:uav_waitrequest -> irq_ena_0_s_agent:m0_waitrequest
wire irq_ena_0_s_agent_m0_debugaccess; // irq_ena_0_s_agent:m0_debugaccess -> irq_ena_0_s_translator:uav_debugaccess
wire [13:0] irq_ena_0_s_agent_m0_address; // irq_ena_0_s_agent:m0_address -> irq_ena_0_s_translator:uav_address
wire [3:0] irq_ena_0_s_agent_m0_byteenable; // irq_ena_0_s_agent:m0_byteenable -> irq_ena_0_s_translator:uav_byteenable
wire irq_ena_0_s_agent_m0_read; // irq_ena_0_s_agent:m0_read -> irq_ena_0_s_translator:uav_read
wire irq_ena_0_s_agent_m0_readdatavalid; // irq_ena_0_s_translator:uav_readdatavalid -> irq_ena_0_s_agent:m0_readdatavalid
wire irq_ena_0_s_agent_m0_lock; // irq_ena_0_s_agent:m0_lock -> irq_ena_0_s_translator:uav_lock
wire [31:0] irq_ena_0_s_agent_m0_writedata; // irq_ena_0_s_agent:m0_writedata -> irq_ena_0_s_translator:uav_writedata
wire irq_ena_0_s_agent_m0_write; // irq_ena_0_s_agent:m0_write -> irq_ena_0_s_translator:uav_write
wire [2:0] irq_ena_0_s_agent_m0_burstcount; // irq_ena_0_s_agent:m0_burstcount -> irq_ena_0_s_translator:uav_burstcount
wire irq_ena_0_s_agent_rf_source_valid; // irq_ena_0_s_agent:rf_source_valid -> irq_ena_0_s_agent_rsp_fifo:in_valid
wire [89:0] irq_ena_0_s_agent_rf_source_data; // irq_ena_0_s_agent:rf_source_data -> irq_ena_0_s_agent_rsp_fifo:in_data
wire irq_ena_0_s_agent_rf_source_ready; // irq_ena_0_s_agent_rsp_fifo:in_ready -> irq_ena_0_s_agent:rf_source_ready
wire irq_ena_0_s_agent_rf_source_startofpacket; // irq_ena_0_s_agent:rf_source_startofpacket -> irq_ena_0_s_agent_rsp_fifo:in_startofpacket
wire irq_ena_0_s_agent_rf_source_endofpacket; // irq_ena_0_s_agent:rf_source_endofpacket -> irq_ena_0_s_agent_rsp_fifo:in_endofpacket
wire irq_ena_0_s_agent_rsp_fifo_out_valid; // irq_ena_0_s_agent_rsp_fifo:out_valid -> irq_ena_0_s_agent:rf_sink_valid
wire [89:0] irq_ena_0_s_agent_rsp_fifo_out_data; // irq_ena_0_s_agent_rsp_fifo:out_data -> irq_ena_0_s_agent:rf_sink_data
wire irq_ena_0_s_agent_rsp_fifo_out_ready; // irq_ena_0_s_agent:rf_sink_ready -> irq_ena_0_s_agent_rsp_fifo:out_ready
wire irq_ena_0_s_agent_rsp_fifo_out_startofpacket; // irq_ena_0_s_agent_rsp_fifo:out_startofpacket -> irq_ena_0_s_agent:rf_sink_startofpacket
wire irq_ena_0_s_agent_rsp_fifo_out_endofpacket; // irq_ena_0_s_agent_rsp_fifo:out_endofpacket -> irq_ena_0_s_agent:rf_sink_endofpacket
wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> irq_ena_0_s_agent:cp_valid
wire [88:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> irq_ena_0_s_agent:cp_data
wire cmd_mux_006_src_ready; // irq_ena_0_s_agent:cp_ready -> cmd_mux_006:src_ready
wire [6:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> irq_ena_0_s_agent:cp_channel
wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> irq_ena_0_s_agent:cp_startofpacket
wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> irq_ena_0_s_agent:cp_endofpacket
wire kernel_cntrl_m0_agent_cp_valid; // kernel_cntrl_m0_agent:cp_valid -> router:sink_valid
wire [88:0] kernel_cntrl_m0_agent_cp_data; // kernel_cntrl_m0_agent:cp_data -> router:sink_data
wire kernel_cntrl_m0_agent_cp_ready; // router:sink_ready -> kernel_cntrl_m0_agent:cp_ready
wire kernel_cntrl_m0_agent_cp_startofpacket; // kernel_cntrl_m0_agent:cp_startofpacket -> router:sink_startofpacket
wire kernel_cntrl_m0_agent_cp_endofpacket; // kernel_cntrl_m0_agent:cp_endofpacket -> router:sink_endofpacket
wire address_span_extender_0_windowed_slave_agent_rp_valid; // address_span_extender_0_windowed_slave_agent:rp_valid -> router_001:sink_valid
wire [88:0] address_span_extender_0_windowed_slave_agent_rp_data; // address_span_extender_0_windowed_slave_agent:rp_data -> router_001:sink_data
wire address_span_extender_0_windowed_slave_agent_rp_ready; // router_001:sink_ready -> address_span_extender_0_windowed_slave_agent:rp_ready
wire address_span_extender_0_windowed_slave_agent_rp_startofpacket; // address_span_extender_0_windowed_slave_agent:rp_startofpacket -> router_001:sink_startofpacket
wire address_span_extender_0_windowed_slave_agent_rp_endofpacket; // address_span_extender_0_windowed_slave_agent:rp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> rsp_demux:sink_valid
wire [88:0] router_001_src_data; // router_001:src_data -> rsp_demux:sink_data
wire router_001_src_ready; // rsp_demux:sink_ready -> router_001:src_ready
wire [6:0] router_001_src_channel; // router_001:src_channel -> rsp_demux:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
wire address_span_extender_0_cntl_agent_rp_valid; // address_span_extender_0_cntl_agent:rp_valid -> router_002:sink_valid
wire [124:0] address_span_extender_0_cntl_agent_rp_data; // address_span_extender_0_cntl_agent:rp_data -> router_002:sink_data
wire address_span_extender_0_cntl_agent_rp_ready; // router_002:sink_ready -> address_span_extender_0_cntl_agent:rp_ready
wire address_span_extender_0_cntl_agent_rp_startofpacket; // address_span_extender_0_cntl_agent:rp_startofpacket -> router_002:sink_startofpacket
wire address_span_extender_0_cntl_agent_rp_endofpacket; // address_span_extender_0_cntl_agent:rp_endofpacket -> router_002:sink_endofpacket
wire sys_description_rom_s1_agent_rp_valid; // sys_description_rom_s1_agent:rp_valid -> router_003:sink_valid
wire [124:0] sys_description_rom_s1_agent_rp_data; // sys_description_rom_s1_agent:rp_data -> router_003:sink_data
wire sys_description_rom_s1_agent_rp_ready; // router_003:sink_ready -> sys_description_rom_s1_agent:rp_ready
wire sys_description_rom_s1_agent_rp_startofpacket; // sys_description_rom_s1_agent:rp_startofpacket -> router_003:sink_startofpacket
wire sys_description_rom_s1_agent_rp_endofpacket; // sys_description_rom_s1_agent:rp_endofpacket -> router_003:sink_endofpacket
wire sw_reset_s_agent_rp_valid; // sw_reset_s_agent:rp_valid -> router_004:sink_valid
wire [124:0] sw_reset_s_agent_rp_data; // sw_reset_s_agent:rp_data -> router_004:sink_data
wire sw_reset_s_agent_rp_ready; // router_004:sink_ready -> sw_reset_s_agent:rp_ready
wire sw_reset_s_agent_rp_startofpacket; // sw_reset_s_agent:rp_startofpacket -> router_004:sink_startofpacket
wire sw_reset_s_agent_rp_endofpacket; // sw_reset_s_agent:rp_endofpacket -> router_004:sink_endofpacket
wire mem_org_mode_s_agent_rp_valid; // mem_org_mode_s_agent:rp_valid -> router_005:sink_valid
wire [88:0] mem_org_mode_s_agent_rp_data; // mem_org_mode_s_agent:rp_data -> router_005:sink_data
wire mem_org_mode_s_agent_rp_ready; // router_005:sink_ready -> mem_org_mode_s_agent:rp_ready
wire mem_org_mode_s_agent_rp_startofpacket; // mem_org_mode_s_agent:rp_startofpacket -> router_005:sink_startofpacket
wire mem_org_mode_s_agent_rp_endofpacket; // mem_org_mode_s_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_004:sink_valid
wire [88:0] router_005_src_data; // router_005:src_data -> rsp_demux_004:sink_data
wire router_005_src_ready; // rsp_demux_004:sink_ready -> router_005:src_ready
wire [6:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_004:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire version_id_0_s_agent_rp_valid; // version_id_0_s_agent:rp_valid -> router_006:sink_valid
wire [88:0] version_id_0_s_agent_rp_data; // version_id_0_s_agent:rp_data -> router_006:sink_data
wire version_id_0_s_agent_rp_ready; // router_006:sink_ready -> version_id_0_s_agent:rp_ready
wire version_id_0_s_agent_rp_startofpacket; // version_id_0_s_agent:rp_startofpacket -> router_006:sink_startofpacket
wire version_id_0_s_agent_rp_endofpacket; // version_id_0_s_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_005:sink_valid
wire [88:0] router_006_src_data; // router_006:src_data -> rsp_demux_005:sink_data
wire router_006_src_ready; // rsp_demux_005:sink_ready -> router_006:src_ready
wire [6:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_005:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire irq_ena_0_s_agent_rp_valid; // irq_ena_0_s_agent:rp_valid -> router_007:sink_valid
wire [88:0] irq_ena_0_s_agent_rp_data; // irq_ena_0_s_agent:rp_data -> router_007:sink_data
wire irq_ena_0_s_agent_rp_ready; // router_007:sink_ready -> irq_ena_0_s_agent:rp_ready
wire irq_ena_0_s_agent_rp_startofpacket; // irq_ena_0_s_agent:rp_startofpacket -> router_007:sink_startofpacket
wire irq_ena_0_s_agent_rp_endofpacket; // irq_ena_0_s_agent:rp_endofpacket -> router_007:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_006:sink_valid
wire [88:0] router_007_src_data; // router_007:src_data -> rsp_demux_006:sink_data
wire router_007_src_ready; // rsp_demux_006:sink_ready -> router_007:src_ready
wire [6:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_006:sink_channel
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_006:sink_startofpacket
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_006:sink_endofpacket
wire router_src_valid; // router:src_valid -> kernel_cntrl_m0_limiter:cmd_sink_valid
wire [88:0] router_src_data; // router:src_data -> kernel_cntrl_m0_limiter:cmd_sink_data
wire router_src_ready; // kernel_cntrl_m0_limiter:cmd_sink_ready -> router:src_ready
wire [6:0] router_src_channel; // router:src_channel -> kernel_cntrl_m0_limiter:cmd_sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> kernel_cntrl_m0_limiter:cmd_sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> kernel_cntrl_m0_limiter:cmd_sink_endofpacket
wire [88:0] kernel_cntrl_m0_limiter_cmd_src_data; // kernel_cntrl_m0_limiter:cmd_src_data -> cmd_demux:sink_data
wire kernel_cntrl_m0_limiter_cmd_src_ready; // cmd_demux:sink_ready -> kernel_cntrl_m0_limiter:cmd_src_ready
wire [6:0] kernel_cntrl_m0_limiter_cmd_src_channel; // kernel_cntrl_m0_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire kernel_cntrl_m0_limiter_cmd_src_startofpacket; // kernel_cntrl_m0_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire kernel_cntrl_m0_limiter_cmd_src_endofpacket; // kernel_cntrl_m0_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> kernel_cntrl_m0_limiter:rsp_sink_valid
wire [88:0] rsp_mux_src_data; // rsp_mux:src_data -> kernel_cntrl_m0_limiter:rsp_sink_data
wire rsp_mux_src_ready; // kernel_cntrl_m0_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire [6:0] rsp_mux_src_channel; // rsp_mux:src_channel -> kernel_cntrl_m0_limiter:rsp_sink_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> kernel_cntrl_m0_limiter:rsp_sink_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> kernel_cntrl_m0_limiter:rsp_sink_endofpacket
wire kernel_cntrl_m0_limiter_rsp_src_valid; // kernel_cntrl_m0_limiter:rsp_src_valid -> kernel_cntrl_m0_agent:rp_valid
wire [88:0] kernel_cntrl_m0_limiter_rsp_src_data; // kernel_cntrl_m0_limiter:rsp_src_data -> kernel_cntrl_m0_agent:rp_data
wire kernel_cntrl_m0_limiter_rsp_src_ready; // kernel_cntrl_m0_agent:rp_ready -> kernel_cntrl_m0_limiter:rsp_src_ready
wire [6:0] kernel_cntrl_m0_limiter_rsp_src_channel; // kernel_cntrl_m0_limiter:rsp_src_channel -> kernel_cntrl_m0_agent:rp_channel
wire kernel_cntrl_m0_limiter_rsp_src_startofpacket; // kernel_cntrl_m0_limiter:rsp_src_startofpacket -> kernel_cntrl_m0_agent:rp_startofpacket
wire kernel_cntrl_m0_limiter_rsp_src_endofpacket; // kernel_cntrl_m0_limiter:rsp_src_endofpacket -> kernel_cntrl_m0_agent:rp_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire [88:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire [6:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire [88:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire [6:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
wire [88:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data
wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
wire [6:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
wire [88:0] cmd_demux_src5_data; // cmd_demux:src5_data -> cmd_mux_005:sink0_data
wire cmd_demux_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
wire [6:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_src6_valid; // cmd_demux:src6_valid -> cmd_mux_006:sink0_valid
wire [88:0] cmd_demux_src6_data; // cmd_demux:src6_data -> cmd_mux_006:sink0_data
wire cmd_demux_src6_ready; // cmd_mux_006:sink0_ready -> cmd_demux:src6_ready
wire [6:0] cmd_demux_src6_channel; // cmd_demux:src6_channel -> cmd_mux_006:sink0_channel
wire cmd_demux_src6_startofpacket; // cmd_demux:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
wire cmd_demux_src6_endofpacket; // cmd_demux:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire [88:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire [6:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire [88:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire [6:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
wire [88:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data
wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
wire [6:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
wire [88:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux:sink5_data
wire rsp_demux_005_src0_ready; // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
wire [6:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> rsp_mux:sink6_valid
wire [88:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> rsp_mux:sink6_data
wire rsp_demux_006_src0_ready; // rsp_mux:sink6_ready -> rsp_demux_006:src0_ready
wire [6:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> rsp_mux:sink6_channel
wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> rsp_mux:sink6_startofpacket
wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> rsp_mux:sink6_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> address_span_extender_0_cntl_cmd_width_adapter:in_valid
wire [88:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> address_span_extender_0_cntl_cmd_width_adapter:in_data
wire cmd_mux_001_src_ready; // address_span_extender_0_cntl_cmd_width_adapter:in_ready -> cmd_mux_001:src_ready
wire [6:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> address_span_extender_0_cntl_cmd_width_adapter:in_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> address_span_extender_0_cntl_cmd_width_adapter:in_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> address_span_extender_0_cntl_cmd_width_adapter:in_endofpacket
wire address_span_extender_0_cntl_cmd_width_adapter_src_valid; // address_span_extender_0_cntl_cmd_width_adapter:out_valid -> address_span_extender_0_cntl_agent:cp_valid
wire [124:0] address_span_extender_0_cntl_cmd_width_adapter_src_data; // address_span_extender_0_cntl_cmd_width_adapter:out_data -> address_span_extender_0_cntl_agent:cp_data
wire address_span_extender_0_cntl_cmd_width_adapter_src_ready; // address_span_extender_0_cntl_agent:cp_ready -> address_span_extender_0_cntl_cmd_width_adapter:out_ready
wire [6:0] address_span_extender_0_cntl_cmd_width_adapter_src_channel; // address_span_extender_0_cntl_cmd_width_adapter:out_channel -> address_span_extender_0_cntl_agent:cp_channel
wire address_span_extender_0_cntl_cmd_width_adapter_src_startofpacket; // address_span_extender_0_cntl_cmd_width_adapter:out_startofpacket -> address_span_extender_0_cntl_agent:cp_startofpacket
wire address_span_extender_0_cntl_cmd_width_adapter_src_endofpacket; // address_span_extender_0_cntl_cmd_width_adapter:out_endofpacket -> address_span_extender_0_cntl_agent:cp_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> sys_description_rom_s1_cmd_width_adapter:in_valid
wire [88:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> sys_description_rom_s1_cmd_width_adapter:in_data
wire cmd_mux_002_src_ready; // sys_description_rom_s1_cmd_width_adapter:in_ready -> cmd_mux_002:src_ready
wire [6:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> sys_description_rom_s1_cmd_width_adapter:in_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> sys_description_rom_s1_cmd_width_adapter:in_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> sys_description_rom_s1_cmd_width_adapter:in_endofpacket
wire sys_description_rom_s1_cmd_width_adapter_src_valid; // sys_description_rom_s1_cmd_width_adapter:out_valid -> sys_description_rom_s1_agent:cp_valid
wire [124:0] sys_description_rom_s1_cmd_width_adapter_src_data; // sys_description_rom_s1_cmd_width_adapter:out_data -> sys_description_rom_s1_agent:cp_data
wire sys_description_rom_s1_cmd_width_adapter_src_ready; // sys_description_rom_s1_agent:cp_ready -> sys_description_rom_s1_cmd_width_adapter:out_ready
wire [6:0] sys_description_rom_s1_cmd_width_adapter_src_channel; // sys_description_rom_s1_cmd_width_adapter:out_channel -> sys_description_rom_s1_agent:cp_channel
wire sys_description_rom_s1_cmd_width_adapter_src_startofpacket; // sys_description_rom_s1_cmd_width_adapter:out_startofpacket -> sys_description_rom_s1_agent:cp_startofpacket
wire sys_description_rom_s1_cmd_width_adapter_src_endofpacket; // sys_description_rom_s1_cmd_width_adapter:out_endofpacket -> sys_description_rom_s1_agent:cp_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> sw_reset_s_cmd_width_adapter:in_valid
wire [88:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> sw_reset_s_cmd_width_adapter:in_data
wire cmd_mux_003_src_ready; // sw_reset_s_cmd_width_adapter:in_ready -> cmd_mux_003:src_ready
wire [6:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> sw_reset_s_cmd_width_adapter:in_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> sw_reset_s_cmd_width_adapter:in_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> sw_reset_s_cmd_width_adapter:in_endofpacket
wire sw_reset_s_cmd_width_adapter_src_valid; // sw_reset_s_cmd_width_adapter:out_valid -> sw_reset_s_agent:cp_valid
wire [124:0] sw_reset_s_cmd_width_adapter_src_data; // sw_reset_s_cmd_width_adapter:out_data -> sw_reset_s_agent:cp_data
wire sw_reset_s_cmd_width_adapter_src_ready; // sw_reset_s_agent:cp_ready -> sw_reset_s_cmd_width_adapter:out_ready
wire [6:0] sw_reset_s_cmd_width_adapter_src_channel; // sw_reset_s_cmd_width_adapter:out_channel -> sw_reset_s_agent:cp_channel
wire sw_reset_s_cmd_width_adapter_src_startofpacket; // sw_reset_s_cmd_width_adapter:out_startofpacket -> sw_reset_s_agent:cp_startofpacket
wire sw_reset_s_cmd_width_adapter_src_endofpacket; // sw_reset_s_cmd_width_adapter:out_endofpacket -> sw_reset_s_agent:cp_endofpacket
wire router_002_src_valid; // router_002:src_valid -> address_span_extender_0_cntl_rsp_width_adapter:in_valid
wire [124:0] router_002_src_data; // router_002:src_data -> address_span_extender_0_cntl_rsp_width_adapter:in_data
wire router_002_src_ready; // address_span_extender_0_cntl_rsp_width_adapter:in_ready -> router_002:src_ready
wire [6:0] router_002_src_channel; // router_002:src_channel -> address_span_extender_0_cntl_rsp_width_adapter:in_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> address_span_extender_0_cntl_rsp_width_adapter:in_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> address_span_extender_0_cntl_rsp_width_adapter:in_endofpacket
wire address_span_extender_0_cntl_rsp_width_adapter_src_valid; // address_span_extender_0_cntl_rsp_width_adapter:out_valid -> rsp_demux_001:sink_valid
wire [88:0] address_span_extender_0_cntl_rsp_width_adapter_src_data; // address_span_extender_0_cntl_rsp_width_adapter:out_data -> rsp_demux_001:sink_data
wire address_span_extender_0_cntl_rsp_width_adapter_src_ready; // rsp_demux_001:sink_ready -> address_span_extender_0_cntl_rsp_width_adapter:out_ready
wire [6:0] address_span_extender_0_cntl_rsp_width_adapter_src_channel; // address_span_extender_0_cntl_rsp_width_adapter:out_channel -> rsp_demux_001:sink_channel
wire address_span_extender_0_cntl_rsp_width_adapter_src_startofpacket; // address_span_extender_0_cntl_rsp_width_adapter:out_startofpacket -> rsp_demux_001:sink_startofpacket
wire address_span_extender_0_cntl_rsp_width_adapter_src_endofpacket; // address_span_extender_0_cntl_rsp_width_adapter:out_endofpacket -> rsp_demux_001:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> sys_description_rom_s1_rsp_width_adapter:in_valid
wire [124:0] router_003_src_data; // router_003:src_data -> sys_description_rom_s1_rsp_width_adapter:in_data
wire router_003_src_ready; // sys_description_rom_s1_rsp_width_adapter:in_ready -> router_003:src_ready
wire [6:0] router_003_src_channel; // router_003:src_channel -> sys_description_rom_s1_rsp_width_adapter:in_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> sys_description_rom_s1_rsp_width_adapter:in_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> sys_description_rom_s1_rsp_width_adapter:in_endofpacket
wire sys_description_rom_s1_rsp_width_adapter_src_valid; // sys_description_rom_s1_rsp_width_adapter:out_valid -> rsp_demux_002:sink_valid
wire [88:0] sys_description_rom_s1_rsp_width_adapter_src_data; // sys_description_rom_s1_rsp_width_adapter:out_data -> rsp_demux_002:sink_data
wire sys_description_rom_s1_rsp_width_adapter_src_ready; // rsp_demux_002:sink_ready -> sys_description_rom_s1_rsp_width_adapter:out_ready
wire [6:0] sys_description_rom_s1_rsp_width_adapter_src_channel; // sys_description_rom_s1_rsp_width_adapter:out_channel -> rsp_demux_002:sink_channel
wire sys_description_rom_s1_rsp_width_adapter_src_startofpacket; // sys_description_rom_s1_rsp_width_adapter:out_startofpacket -> rsp_demux_002:sink_startofpacket
wire sys_description_rom_s1_rsp_width_adapter_src_endofpacket; // sys_description_rom_s1_rsp_width_adapter:out_endofpacket -> rsp_demux_002:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> sw_reset_s_rsp_width_adapter:in_valid
wire [124:0] router_004_src_data; // router_004:src_data -> sw_reset_s_rsp_width_adapter:in_data
wire router_004_src_ready; // sw_reset_s_rsp_width_adapter:in_ready -> router_004:src_ready
wire [6:0] router_004_src_channel; // router_004:src_channel -> sw_reset_s_rsp_width_adapter:in_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> sw_reset_s_rsp_width_adapter:in_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> sw_reset_s_rsp_width_adapter:in_endofpacket
wire sw_reset_s_rsp_width_adapter_src_valid; // sw_reset_s_rsp_width_adapter:out_valid -> rsp_demux_003:sink_valid
wire [88:0] sw_reset_s_rsp_width_adapter_src_data; // sw_reset_s_rsp_width_adapter:out_data -> rsp_demux_003:sink_data
wire sw_reset_s_rsp_width_adapter_src_ready; // rsp_demux_003:sink_ready -> sw_reset_s_rsp_width_adapter:out_ready
wire [6:0] sw_reset_s_rsp_width_adapter_src_channel; // sw_reset_s_rsp_width_adapter:out_channel -> rsp_demux_003:sink_channel
wire sw_reset_s_rsp_width_adapter_src_startofpacket; // sw_reset_s_rsp_width_adapter:out_startofpacket -> rsp_demux_003:sink_startofpacket
wire sw_reset_s_rsp_width_adapter_src_endofpacket; // sw_reset_s_rsp_width_adapter:out_endofpacket -> rsp_demux_003:sink_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> crosser:in_valid
wire [88:0] cmd_demux_src0_data; // cmd_demux:src0_data -> crosser:in_data
wire cmd_demux_src0_ready; // crosser:in_ready -> cmd_demux:src0_ready
wire [6:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> crosser:in_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> crosser:in_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> crosser:in_endofpacket
wire crosser_out_valid; // crosser:out_valid -> cmd_mux:sink0_valid
wire [88:0] crosser_out_data; // crosser:out_data -> cmd_mux:sink0_data
wire crosser_out_ready; // cmd_mux:sink0_ready -> crosser:out_ready
wire [6:0] crosser_out_channel; // crosser:out_channel -> cmd_mux:sink0_channel
wire crosser_out_startofpacket; // crosser:out_startofpacket -> cmd_mux:sink0_startofpacket
wire crosser_out_endofpacket; // crosser:out_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> crosser_001:in_valid
wire [88:0] cmd_demux_src1_data; // cmd_demux:src1_data -> crosser_001:in_data
wire cmd_demux_src1_ready; // crosser_001:in_ready -> cmd_demux:src1_ready
wire [6:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> crosser_001:in_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> crosser_001:in_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> crosser_001:in_endofpacket
wire crosser_001_out_valid; // crosser_001:out_valid -> cmd_mux_001:sink0_valid
wire [88:0] crosser_001_out_data; // crosser_001:out_data -> cmd_mux_001:sink0_data
wire crosser_001_out_ready; // cmd_mux_001:sink0_ready -> crosser_001:out_ready
wire [6:0] crosser_001_out_channel; // crosser_001:out_channel -> cmd_mux_001:sink0_channel
wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> cmd_mux_001:sink0_startofpacket
wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> cmd_mux_001:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> crosser_002:in_valid
wire [88:0] rsp_demux_src0_data; // rsp_demux:src0_data -> crosser_002:in_data
wire rsp_demux_src0_ready; // crosser_002:in_ready -> rsp_demux:src0_ready
wire [6:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> crosser_002:in_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> crosser_002:in_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> crosser_002:in_endofpacket
wire crosser_002_out_valid; // crosser_002:out_valid -> rsp_mux:sink0_valid
wire [88:0] crosser_002_out_data; // crosser_002:out_data -> rsp_mux:sink0_data
wire crosser_002_out_ready; // rsp_mux:sink0_ready -> crosser_002:out_ready
wire [6:0] crosser_002_out_channel; // crosser_002:out_channel -> rsp_mux:sink0_channel
wire crosser_002_out_startofpacket; // crosser_002:out_startofpacket -> rsp_mux:sink0_startofpacket
wire crosser_002_out_endofpacket; // crosser_002:out_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> crosser_003:in_valid
wire [88:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> crosser_003:in_data
wire rsp_demux_001_src0_ready; // crosser_003:in_ready -> rsp_demux_001:src0_ready
wire [6:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> crosser_003:in_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> crosser_003:in_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> crosser_003:in_endofpacket
wire crosser_003_out_valid; // crosser_003:out_valid -> rsp_mux:sink1_valid
wire [88:0] crosser_003_out_data; // crosser_003:out_data -> rsp_mux:sink1_data
wire crosser_003_out_ready; // rsp_mux:sink1_ready -> crosser_003:out_ready
wire [6:0] crosser_003_out_channel; // crosser_003:out_channel -> rsp_mux:sink1_channel
wire crosser_003_out_startofpacket; // crosser_003:out_startofpacket -> rsp_mux:sink1_startofpacket
wire crosser_003_out_endofpacket; // crosser_003:out_endofpacket -> rsp_mux:sink1_endofpacket
wire [6:0] kernel_cntrl_m0_limiter_cmd_valid_data; // kernel_cntrl_m0_limiter:cmd_src_valid -> cmd_demux:sink_valid
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_out_valid; // address_span_extender_0_windowed_slave_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
wire [33:0] address_span_extender_0_windowed_slave_agent_rdata_fifo_out_data; // address_span_extender_0_windowed_slave_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_out_ready; // avalon_st_adapter:in_0_ready -> address_span_extender_0_windowed_slave_agent_rdata_fifo:out_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> address_span_extender_0_windowed_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> address_span_extender_0_windowed_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // address_span_extender_0_windowed_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> address_span_extender_0_windowed_slave_agent:rdata_fifo_sink_error
wire address_span_extender_0_cntl_agent_rdata_fifo_out_valid; // address_span_extender_0_cntl_agent_rdata_fifo:out_valid -> avalon_st_adapter_001:in_0_valid
wire [65:0] address_span_extender_0_cntl_agent_rdata_fifo_out_data; // address_span_extender_0_cntl_agent_rdata_fifo:out_data -> avalon_st_adapter_001:in_0_data
wire address_span_extender_0_cntl_agent_rdata_fifo_out_ready; // avalon_st_adapter_001:in_0_ready -> address_span_extender_0_cntl_agent_rdata_fifo:out_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> address_span_extender_0_cntl_agent:rdata_fifo_sink_valid
wire [65:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> address_span_extender_0_cntl_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // address_span_extender_0_cntl_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> address_span_extender_0_cntl_agent:rdata_fifo_sink_error
wire sys_description_rom_s1_agent_rdata_fifo_src_valid; // sys_description_rom_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
wire [65:0] sys_description_rom_s1_agent_rdata_fifo_src_data; // sys_description_rom_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
wire sys_description_rom_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_002:in_0_ready -> sys_description_rom_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> sys_description_rom_s1_agent:rdata_fifo_sink_valid
wire [65:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> sys_description_rom_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_002_out_0_ready; // sys_description_rom_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> sys_description_rom_s1_agent:rdata_fifo_sink_error
wire sw_reset_s_agent_rdata_fifo_src_valid; // sw_reset_s_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid
wire [65:0] sw_reset_s_agent_rdata_fifo_src_data; // sw_reset_s_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data
wire sw_reset_s_agent_rdata_fifo_src_ready; // avalon_st_adapter_003:in_0_ready -> sw_reset_s_agent:rdata_fifo_src_ready
wire avalon_st_adapter_003_out_0_valid; // avalon_st_adapter_003:out_0_valid -> sw_reset_s_agent:rdata_fifo_sink_valid
wire [65:0] avalon_st_adapter_003_out_0_data; // avalon_st_adapter_003:out_0_data -> sw_reset_s_agent:rdata_fifo_sink_data
wire avalon_st_adapter_003_out_0_ready; // sw_reset_s_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
wire [0:0] avalon_st_adapter_003_out_0_error; // avalon_st_adapter_003:out_0_error -> sw_reset_s_agent:rdata_fifo_sink_error
wire mem_org_mode_s_agent_rdata_fifo_src_valid; // mem_org_mode_s_agent:rdata_fifo_src_valid -> avalon_st_adapter_004:in_0_valid
wire [33:0] mem_org_mode_s_agent_rdata_fifo_src_data; // mem_org_mode_s_agent:rdata_fifo_src_data -> avalon_st_adapter_004:in_0_data
wire mem_org_mode_s_agent_rdata_fifo_src_ready; // avalon_st_adapter_004:in_0_ready -> mem_org_mode_s_agent:rdata_fifo_src_ready
wire avalon_st_adapter_004_out_0_valid; // avalon_st_adapter_004:out_0_valid -> mem_org_mode_s_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_004_out_0_data; // avalon_st_adapter_004:out_0_data -> mem_org_mode_s_agent:rdata_fifo_sink_data
wire avalon_st_adapter_004_out_0_ready; // mem_org_mode_s_agent:rdata_fifo_sink_ready -> avalon_st_adapter_004:out_0_ready
wire [0:0] avalon_st_adapter_004_out_0_error; // avalon_st_adapter_004:out_0_error -> mem_org_mode_s_agent:rdata_fifo_sink_error
wire version_id_0_s_agent_rdata_fifo_src_valid; // version_id_0_s_agent:rdata_fifo_src_valid -> avalon_st_adapter_005:in_0_valid
wire [33:0] version_id_0_s_agent_rdata_fifo_src_data; // version_id_0_s_agent:rdata_fifo_src_data -> avalon_st_adapter_005:in_0_data
wire version_id_0_s_agent_rdata_fifo_src_ready; // avalon_st_adapter_005:in_0_ready -> version_id_0_s_agent:rdata_fifo_src_ready
wire avalon_st_adapter_005_out_0_valid; // avalon_st_adapter_005:out_0_valid -> version_id_0_s_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_005_out_0_data; // avalon_st_adapter_005:out_0_data -> version_id_0_s_agent:rdata_fifo_sink_data
wire avalon_st_adapter_005_out_0_ready; // version_id_0_s_agent:rdata_fifo_sink_ready -> avalon_st_adapter_005:out_0_ready
wire [0:0] avalon_st_adapter_005_out_0_error; // avalon_st_adapter_005:out_0_error -> version_id_0_s_agent:rdata_fifo_sink_error
wire irq_ena_0_s_agent_rdata_fifo_src_valid; // irq_ena_0_s_agent:rdata_fifo_src_valid -> avalon_st_adapter_006:in_0_valid
wire [33:0] irq_ena_0_s_agent_rdata_fifo_src_data; // irq_ena_0_s_agent:rdata_fifo_src_data -> avalon_st_adapter_006:in_0_data
wire irq_ena_0_s_agent_rdata_fifo_src_ready; // avalon_st_adapter_006:in_0_ready -> irq_ena_0_s_agent:rdata_fifo_src_ready
wire avalon_st_adapter_006_out_0_valid; // avalon_st_adapter_006:out_0_valid -> irq_ena_0_s_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_006_out_0_data; // avalon_st_adapter_006:out_0_data -> irq_ena_0_s_agent:rdata_fifo_sink_data
wire avalon_st_adapter_006_out_0_ready; // irq_ena_0_s_agent:rdata_fifo_sink_ready -> avalon_st_adapter_006:out_0_ready
wire [0:0] avalon_st_adapter_006_out_0_error; // avalon_st_adapter_006:out_0_error -> irq_ena_0_s_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (14),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) kernel_cntrl_m0_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (kernel_cntrl_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (kernel_cntrl_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (kernel_cntrl_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (kernel_cntrl_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (kernel_cntrl_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (kernel_cntrl_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (kernel_cntrl_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (kernel_cntrl_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (kernel_cntrl_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (kernel_cntrl_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (kernel_cntrl_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (kernel_cntrl_m0_address), // avalon_anti_master_0.address
.av_waitrequest (kernel_cntrl_m0_waitrequest), // .waitrequest
.av_burstcount (kernel_cntrl_m0_burstcount), // .burstcount
.av_byteenable (kernel_cntrl_m0_byteenable), // .byteenable
.av_read (kernel_cntrl_m0_read), // .read
.av_readdata (kernel_cntrl_m0_readdata), // .readdata
.av_readdatavalid (kernel_cntrl_m0_readdatavalid), // .readdatavalid
.av_write (kernel_cntrl_m0_write), // .write
.av_writedata (kernel_cntrl_m0_writedata), // .writedata
.av_debugaccess (kernel_cntrl_m0_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (10),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) address_span_extender_0_windowed_slave_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_0_windowed_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (address_span_extender_0_windowed_slave_agent_m0_burstcount), // .burstcount
.uav_read (address_span_extender_0_windowed_slave_agent_m0_read), // .read
.uav_write (address_span_extender_0_windowed_slave_agent_m0_write), // .write
.uav_waitrequest (address_span_extender_0_windowed_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_0_windowed_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_0_windowed_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (address_span_extender_0_windowed_slave_agent_m0_readdata), // .readdata
.uav_writedata (address_span_extender_0_windowed_slave_agent_m0_writedata), // .writedata
.uav_lock (address_span_extender_0_windowed_slave_agent_m0_lock), // .lock
.uav_debugaccess (address_span_extender_0_windowed_slave_agent_m0_debugaccess), // .debugaccess
.av_address (address_span_extender_0_windowed_slave_address), // avalon_anti_slave_0.address
.av_write (address_span_extender_0_windowed_slave_write), // .write
.av_read (address_span_extender_0_windowed_slave_read), // .read
.av_readdata (address_span_extender_0_windowed_slave_readdata), // .readdata
.av_writedata (address_span_extender_0_windowed_slave_writedata), // .writedata
.av_burstcount (address_span_extender_0_windowed_slave_burstcount), // .burstcount
.av_byteenable (address_span_extender_0_windowed_slave_byteenable), // .byteenable
.av_readdatavalid (address_span_extender_0_windowed_slave_readdatavalid), // .readdatavalid
.av_waitrequest (address_span_extender_0_windowed_slave_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) address_span_extender_0_cntl_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_0_cntl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (address_span_extender_0_cntl_agent_m0_burstcount), // .burstcount
.uav_read (address_span_extender_0_cntl_agent_m0_read), // .read
.uav_write (address_span_extender_0_cntl_agent_m0_write), // .write
.uav_waitrequest (address_span_extender_0_cntl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_0_cntl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_0_cntl_agent_m0_byteenable), // .byteenable
.uav_readdata (address_span_extender_0_cntl_agent_m0_readdata), // .readdata
.uav_writedata (address_span_extender_0_cntl_agent_m0_writedata), // .writedata
.uav_lock (address_span_extender_0_cntl_agent_m0_lock), // .lock
.uav_debugaccess (address_span_extender_0_cntl_agent_m0_debugaccess), // .debugaccess
.av_write (address_span_extender_0_cntl_write), // avalon_anti_slave_0.write
.av_read (address_span_extender_0_cntl_read), // .read
.av_readdata (address_span_extender_0_cntl_readdata), // .readdata
.av_writedata (address_span_extender_0_cntl_writedata), // .writedata
.av_byteenable (address_span_extender_0_cntl_byteenable), // .byteenable
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (2),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sys_description_rom_s1_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sys_description_rom_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sys_description_rom_s1_agent_m0_burstcount), // .burstcount
.uav_read (sys_description_rom_s1_agent_m0_read), // .read
.uav_write (sys_description_rom_s1_agent_m0_write), // .write
.uav_waitrequest (sys_description_rom_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sys_description_rom_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sys_description_rom_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sys_description_rom_s1_agent_m0_readdata), // .readdata
.uav_writedata (sys_description_rom_s1_agent_m0_writedata), // .writedata
.uav_lock (sys_description_rom_s1_agent_m0_lock), // .lock
.uav_debugaccess (sys_description_rom_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sys_description_rom_s1_address), // avalon_anti_slave_0.address
.av_write (sys_description_rom_s1_write), // .write
.av_readdata (sys_description_rom_s1_readdata), // .readdata
.av_writedata (sys_description_rom_s1_writedata), // .writedata
.av_byteenable (sys_description_rom_s1_byteenable), // .byteenable
.av_chipselect (sys_description_rom_s1_chipselect), // .chipselect
.av_clken (sys_description_rom_s1_clken), // .clken
.av_debugaccess (sys_description_rom_s1_debugaccess), // .debugaccess
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sw_reset_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sw_reset_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sw_reset_s_agent_m0_burstcount), // .burstcount
.uav_read (sw_reset_s_agent_m0_read), // .read
.uav_write (sw_reset_s_agent_m0_write), // .write
.uav_waitrequest (sw_reset_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sw_reset_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sw_reset_s_agent_m0_byteenable), // .byteenable
.uav_readdata (sw_reset_s_agent_m0_readdata), // .readdata
.uav_writedata (sw_reset_s_agent_m0_writedata), // .writedata
.uav_lock (sw_reset_s_agent_m0_lock), // .lock
.uav_debugaccess (sw_reset_s_agent_m0_debugaccess), // .debugaccess
.av_write (sw_reset_s_write), // avalon_anti_slave_0.write
.av_read (sw_reset_s_read), // .read
.av_readdata (sw_reset_s_readdata), // .readdata
.av_writedata (sw_reset_s_writedata), // .writedata
.av_byteenable (sw_reset_s_byteenable), // .byteenable
.av_waitrequest (sw_reset_s_waitrequest), // .waitrequest
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) mem_org_mode_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (mem_org_mode_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (mem_org_mode_s_agent_m0_burstcount), // .burstcount
.uav_read (mem_org_mode_s_agent_m0_read), // .read
.uav_write (mem_org_mode_s_agent_m0_write), // .write
.uav_waitrequest (mem_org_mode_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (mem_org_mode_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (mem_org_mode_s_agent_m0_byteenable), // .byteenable
.uav_readdata (mem_org_mode_s_agent_m0_readdata), // .readdata
.uav_writedata (mem_org_mode_s_agent_m0_writedata), // .writedata
.uav_lock (mem_org_mode_s_agent_m0_lock), // .lock
.uav_debugaccess (mem_org_mode_s_agent_m0_debugaccess), // .debugaccess
.av_write (mem_org_mode_s_write), // avalon_anti_slave_0.write
.av_read (mem_org_mode_s_read), // .read
.av_readdata (mem_org_mode_s_readdata), // .readdata
.av_writedata (mem_org_mode_s_writedata), // .writedata
.av_waitrequest (mem_org_mode_s_waitrequest), // .waitrequest
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) version_id_0_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (version_id_0_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (version_id_0_s_agent_m0_burstcount), // .burstcount
.uav_read (version_id_0_s_agent_m0_read), // .read
.uav_write (version_id_0_s_agent_m0_write), // .write
.uav_waitrequest (version_id_0_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (version_id_0_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (version_id_0_s_agent_m0_byteenable), // .byteenable
.uav_readdata (version_id_0_s_agent_m0_readdata), // .readdata
.uav_writedata (version_id_0_s_agent_m0_writedata), // .writedata
.uav_lock (version_id_0_s_agent_m0_lock), // .lock
.uav_debugaccess (version_id_0_s_agent_m0_debugaccess), // .debugaccess
.av_read (version_id_0_s_read), // avalon_anti_slave_0.read
.av_readdata (version_id_0_s_readdata), // .readdata
.av_address (), // (terminated)
.av_write (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) irq_ena_0_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (irq_ena_0_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (irq_ena_0_s_agent_m0_burstcount), // .burstcount
.uav_read (irq_ena_0_s_agent_m0_read), // .read
.uav_write (irq_ena_0_s_agent_m0_write), // .write
.uav_waitrequest (irq_ena_0_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (irq_ena_0_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (irq_ena_0_s_agent_m0_byteenable), // .byteenable
.uav_readdata (irq_ena_0_s_agent_m0_readdata), // .readdata
.uav_writedata (irq_ena_0_s_agent_m0_writedata), // .writedata
.uav_lock (irq_ena_0_s_agent_m0_lock), // .lock
.uav_debugaccess (irq_ena_0_s_agent_m0_debugaccess), // .debugaccess
.av_write (irq_ena_0_s_write), // avalon_anti_slave_0.write
.av_read (irq_ena_0_s_read), // .read
.av_readdata (irq_ena_0_s_readdata), // .readdata
.av_writedata (irq_ena_0_s_writedata), // .writedata
.av_byteenable (irq_ena_0_s_byteenable), // .byteenable
.av_waitrequest (irq_ena_0_s_waitrequest), // .waitrequest
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (88),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_QOS_H (69),
.PKT_QOS_L (69),
.PKT_DATA_SIDEBAND_H (67),
.PKT_DATA_SIDEBAND_L (67),
.PKT_ADDR_SIDEBAND_H (66),
.PKT_ADDR_SIDEBAND_L (66),
.PKT_BURST_TYPE_H (65),
.PKT_BURST_TYPE_L (64),
.PKT_CACHE_H (83),
.PKT_CACHE_L (80),
.PKT_THREAD_ID_H (76),
.PKT_THREAD_ID_L (76),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_TRANS_EXCLUSIVE (55),
.PKT_TRANS_LOCK (54),
.PKT_BEGIN_BURST (68),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.ST_DATA_W (89),
.ST_CHANNEL_W (7),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) kernel_cntrl_m0_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (kernel_cntrl_m0_translator_avalon_universal_master_0_address), // av.address
.av_write (kernel_cntrl_m0_translator_avalon_universal_master_0_write), // .write
.av_read (kernel_cntrl_m0_translator_avalon_universal_master_0_read), // .read
.av_writedata (kernel_cntrl_m0_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (kernel_cntrl_m0_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (kernel_cntrl_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (kernel_cntrl_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (kernel_cntrl_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (kernel_cntrl_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (kernel_cntrl_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (kernel_cntrl_m0_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (kernel_cntrl_m0_agent_cp_valid), // cp.valid
.cp_data (kernel_cntrl_m0_agent_cp_data), // .data
.cp_startofpacket (kernel_cntrl_m0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (kernel_cntrl_m0_agent_cp_endofpacket), // .endofpacket
.cp_ready (kernel_cntrl_m0_agent_cp_ready), // .ready
.rp_valid (kernel_cntrl_m0_limiter_rsp_src_valid), // rp.valid
.rp_data (kernel_cntrl_m0_limiter_rsp_src_data), // .data
.rp_channel (kernel_cntrl_m0_limiter_rsp_src_channel), // .channel
.rp_startofpacket (kernel_cntrl_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (kernel_cntrl_m0_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (kernel_cntrl_m0_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (88),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_TRANS_LOCK (54),
.PKT_BEGIN_BURST (68),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) address_span_extender_0_windowed_slave_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (address_span_extender_0_windowed_slave_agent_m0_address), // m0.address
.m0_burstcount (address_span_extender_0_windowed_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (address_span_extender_0_windowed_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (address_span_extender_0_windowed_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (address_span_extender_0_windowed_slave_agent_m0_lock), // .lock
.m0_readdata (address_span_extender_0_windowed_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (address_span_extender_0_windowed_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (address_span_extender_0_windowed_slave_agent_m0_read), // .read
.m0_waitrequest (address_span_extender_0_windowed_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (address_span_extender_0_windowed_slave_agent_m0_writedata), // .writedata
.m0_write (address_span_extender_0_windowed_slave_agent_m0_write), // .write
.rp_endofpacket (address_span_extender_0_windowed_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (address_span_extender_0_windowed_slave_agent_rp_ready), // .ready
.rp_valid (address_span_extender_0_windowed_slave_agent_rp_valid), // .valid
.rp_data (address_span_extender_0_windowed_slave_agent_rp_data), // .data
.rp_startofpacket (address_span_extender_0_windowed_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (address_span_extender_0_windowed_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (address_span_extender_0_windowed_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (address_span_extender_0_windowed_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (address_span_extender_0_windowed_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (address_span_extender_0_windowed_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_windowed_slave_agent_rsp_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_windowed_slave_agent_rf_source_data), // in.data
.in_valid (address_span_extender_0_windowed_slave_agent_rf_source_valid), // .valid
.in_ready (address_span_extender_0_windowed_slave_agent_rf_source_ready), // .ready
.in_startofpacket (address_span_extender_0_windowed_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (address_span_extender_0_windowed_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_windowed_slave_agent_rdata_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_data), // in.data
.in_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_valid), // .valid
.in_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_ready), // .ready
.out_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_data), // out.data
.out_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (124),
.PKT_ORI_BURST_SIZE_L (122),
.PKT_RESPONSE_STATUS_H (121),
.PKT_RESPONSE_STATUS_L (120),
.PKT_BURST_SIZE_H (99),
.PKT_BURST_SIZE_L (97),
.PKT_TRANS_LOCK (90),
.PKT_BEGIN_BURST (104),
.PKT_PROTECTION_H (115),
.PKT_PROTECTION_L (113),
.PKT_BURSTWRAP_H (96),
.PKT_BURSTWRAP_L (96),
.PKT_BYTE_CNT_H (95),
.PKT_BYTE_CNT_L (92),
.PKT_ADDR_H (85),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (86),
.PKT_TRANS_POSTED (87),
.PKT_TRANS_WRITE (88),
.PKT_TRANS_READ (89),
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_SRC_ID_H (108),
.PKT_SRC_ID_L (106),
.PKT_DEST_ID_H (111),
.PKT_DEST_ID_L (109),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (125),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) address_span_extender_0_cntl_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (address_span_extender_0_cntl_agent_m0_address), // m0.address
.m0_burstcount (address_span_extender_0_cntl_agent_m0_burstcount), // .burstcount
.m0_byteenable (address_span_extender_0_cntl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (address_span_extender_0_cntl_agent_m0_debugaccess), // .debugaccess
.m0_lock (address_span_extender_0_cntl_agent_m0_lock), // .lock
.m0_readdata (address_span_extender_0_cntl_agent_m0_readdata), // .readdata
.m0_readdatavalid (address_span_extender_0_cntl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (address_span_extender_0_cntl_agent_m0_read), // .read
.m0_waitrequest (address_span_extender_0_cntl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (address_span_extender_0_cntl_agent_m0_writedata), // .writedata
.m0_write (address_span_extender_0_cntl_agent_m0_write), // .write
.rp_endofpacket (address_span_extender_0_cntl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (address_span_extender_0_cntl_agent_rp_ready), // .ready
.rp_valid (address_span_extender_0_cntl_agent_rp_valid), // .valid
.rp_data (address_span_extender_0_cntl_agent_rp_data), // .data
.rp_startofpacket (address_span_extender_0_cntl_agent_rp_startofpacket), // .startofpacket
.cp_ready (address_span_extender_0_cntl_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (address_span_extender_0_cntl_cmd_width_adapter_src_valid), // .valid
.cp_data (address_span_extender_0_cntl_cmd_width_adapter_src_data), // .data
.cp_startofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (address_span_extender_0_cntl_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (address_span_extender_0_cntl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (address_span_extender_0_cntl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (address_span_extender_0_cntl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (address_span_extender_0_cntl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (address_span_extender_0_cntl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (address_span_extender_0_cntl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (address_span_extender_0_cntl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (address_span_extender_0_cntl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (address_span_extender_0_cntl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (address_span_extender_0_cntl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (address_span_extender_0_cntl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (126),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_cntl_agent_rsp_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_cntl_agent_rf_source_data), // in.data
.in_valid (address_span_extender_0_cntl_agent_rf_source_valid), // .valid
.in_ready (address_span_extender_0_cntl_agent_rf_source_ready), // .ready
.in_startofpacket (address_span_extender_0_cntl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (address_span_extender_0_cntl_agent_rf_source_endofpacket), // .endofpacket
.out_data (address_span_extender_0_cntl_agent_rsp_fifo_out_data), // out.data
.out_valid (address_span_extender_0_cntl_agent_rsp_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_cntl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (66),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_cntl_agent_rdata_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_cntl_agent_rdata_fifo_src_data), // in.data
.in_valid (address_span_extender_0_cntl_agent_rdata_fifo_src_valid), // .valid
.in_ready (address_span_extender_0_cntl_agent_rdata_fifo_src_ready), // .ready
.out_data (address_span_extender_0_cntl_agent_rdata_fifo_out_data), // out.data
.out_valid (address_span_extender_0_cntl_agent_rdata_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_cntl_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (124),
.PKT_ORI_BURST_SIZE_L (122),
.PKT_RESPONSE_STATUS_H (121),
.PKT_RESPONSE_STATUS_L (120),
.PKT_BURST_SIZE_H (99),
.PKT_BURST_SIZE_L (97),
.PKT_TRANS_LOCK (90),
.PKT_BEGIN_BURST (104),
.PKT_PROTECTION_H (115),
.PKT_PROTECTION_L (113),
.PKT_BURSTWRAP_H (96),
.PKT_BURSTWRAP_L (96),
.PKT_BYTE_CNT_H (95),
.PKT_BYTE_CNT_L (92),
.PKT_ADDR_H (85),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (86),
.PKT_TRANS_POSTED (87),
.PKT_TRANS_WRITE (88),
.PKT_TRANS_READ (89),
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_SRC_ID_H (108),
.PKT_SRC_ID_L (106),
.PKT_DEST_ID_H (111),
.PKT_DEST_ID_L (109),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (125),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sys_description_rom_s1_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sys_description_rom_s1_agent_m0_address), // m0.address
.m0_burstcount (sys_description_rom_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sys_description_rom_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sys_description_rom_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sys_description_rom_s1_agent_m0_lock), // .lock
.m0_readdata (sys_description_rom_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sys_description_rom_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sys_description_rom_s1_agent_m0_read), // .read
.m0_waitrequest (sys_description_rom_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sys_description_rom_s1_agent_m0_writedata), // .writedata
.m0_write (sys_description_rom_s1_agent_m0_write), // .write
.rp_endofpacket (sys_description_rom_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sys_description_rom_s1_agent_rp_ready), // .ready
.rp_valid (sys_description_rom_s1_agent_rp_valid), // .valid
.rp_data (sys_description_rom_s1_agent_rp_data), // .data
.rp_startofpacket (sys_description_rom_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (sys_description_rom_s1_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (sys_description_rom_s1_cmd_width_adapter_src_valid), // .valid
.cp_data (sys_description_rom_s1_cmd_width_adapter_src_data), // .data
.cp_startofpacket (sys_description_rom_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (sys_description_rom_s1_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (sys_description_rom_s1_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (sys_description_rom_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sys_description_rom_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sys_description_rom_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sys_description_rom_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sys_description_rom_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sys_description_rom_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sys_description_rom_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sys_description_rom_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sys_description_rom_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sys_description_rom_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error
.rdata_fifo_src_ready (sys_description_rom_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sys_description_rom_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sys_description_rom_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (126),
.FIFO_DEPTH (3),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sys_description_rom_s1_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sys_description_rom_s1_agent_rf_source_data), // in.data
.in_valid (sys_description_rom_s1_agent_rf_source_valid), // .valid
.in_ready (sys_description_rom_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sys_description_rom_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sys_description_rom_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sys_description_rom_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sys_description_rom_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sys_description_rom_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sys_description_rom_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sys_description_rom_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (124),
.PKT_ORI_BURST_SIZE_L (122),
.PKT_RESPONSE_STATUS_H (121),
.PKT_RESPONSE_STATUS_L (120),
.PKT_BURST_SIZE_H (99),
.PKT_BURST_SIZE_L (97),
.PKT_TRANS_LOCK (90),
.PKT_BEGIN_BURST (104),
.PKT_PROTECTION_H (115),
.PKT_PROTECTION_L (113),
.PKT_BURSTWRAP_H (96),
.PKT_BURSTWRAP_L (96),
.PKT_BYTE_CNT_H (95),
.PKT_BYTE_CNT_L (92),
.PKT_ADDR_H (85),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (86),
.PKT_TRANS_POSTED (87),
.PKT_TRANS_WRITE (88),
.PKT_TRANS_READ (89),
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_SRC_ID_H (108),
.PKT_SRC_ID_L (106),
.PKT_DEST_ID_H (111),
.PKT_DEST_ID_L (109),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (125),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sw_reset_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sw_reset_s_agent_m0_address), // m0.address
.m0_burstcount (sw_reset_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (sw_reset_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sw_reset_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (sw_reset_s_agent_m0_lock), // .lock
.m0_readdata (sw_reset_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (sw_reset_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sw_reset_s_agent_m0_read), // .read
.m0_waitrequest (sw_reset_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sw_reset_s_agent_m0_writedata), // .writedata
.m0_write (sw_reset_s_agent_m0_write), // .write
.rp_endofpacket (sw_reset_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sw_reset_s_agent_rp_ready), // .ready
.rp_valid (sw_reset_s_agent_rp_valid), // .valid
.rp_data (sw_reset_s_agent_rp_data), // .data
.rp_startofpacket (sw_reset_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (sw_reset_s_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (sw_reset_s_cmd_width_adapter_src_valid), // .valid
.cp_data (sw_reset_s_cmd_width_adapter_src_data), // .data
.cp_startofpacket (sw_reset_s_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (sw_reset_s_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (sw_reset_s_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (sw_reset_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sw_reset_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sw_reset_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sw_reset_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sw_reset_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sw_reset_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sw_reset_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sw_reset_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sw_reset_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sw_reset_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_003_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_003_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_003_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_003_out_0_error), // .error
.rdata_fifo_src_ready (sw_reset_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sw_reset_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sw_reset_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (126),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sw_reset_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sw_reset_s_agent_rf_source_data), // in.data
.in_valid (sw_reset_s_agent_rf_source_valid), // .valid
.in_ready (sw_reset_s_agent_rf_source_ready), // .ready
.in_startofpacket (sw_reset_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sw_reset_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (sw_reset_s_agent_rsp_fifo_out_data), // out.data
.out_valid (sw_reset_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (sw_reset_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sw_reset_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sw_reset_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (88),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_TRANS_LOCK (54),
.PKT_BEGIN_BURST (68),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) mem_org_mode_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (mem_org_mode_s_agent_m0_address), // m0.address
.m0_burstcount (mem_org_mode_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (mem_org_mode_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (mem_org_mode_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (mem_org_mode_s_agent_m0_lock), // .lock
.m0_readdata (mem_org_mode_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (mem_org_mode_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (mem_org_mode_s_agent_m0_read), // .read
.m0_waitrequest (mem_org_mode_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (mem_org_mode_s_agent_m0_writedata), // .writedata
.m0_write (mem_org_mode_s_agent_m0_write), // .write
.rp_endofpacket (mem_org_mode_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (mem_org_mode_s_agent_rp_ready), // .ready
.rp_valid (mem_org_mode_s_agent_rp_valid), // .valid
.rp_data (mem_org_mode_s_agent_rp_data), // .data
.rp_startofpacket (mem_org_mode_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (mem_org_mode_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (mem_org_mode_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (mem_org_mode_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (mem_org_mode_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (mem_org_mode_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (mem_org_mode_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (mem_org_mode_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (mem_org_mode_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (mem_org_mode_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (mem_org_mode_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_004_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_004_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_004_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_004_out_0_error), // .error
.rdata_fifo_src_ready (mem_org_mode_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (mem_org_mode_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (mem_org_mode_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) mem_org_mode_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (mem_org_mode_s_agent_rf_source_data), // in.data
.in_valid (mem_org_mode_s_agent_rf_source_valid), // .valid
.in_ready (mem_org_mode_s_agent_rf_source_ready), // .ready
.in_startofpacket (mem_org_mode_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (mem_org_mode_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (mem_org_mode_s_agent_rsp_fifo_out_data), // out.data
.out_valid (mem_org_mode_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (mem_org_mode_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (mem_org_mode_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (mem_org_mode_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (88),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_TRANS_LOCK (54),
.PKT_BEGIN_BURST (68),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) version_id_0_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (version_id_0_s_agent_m0_address), // m0.address
.m0_burstcount (version_id_0_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (version_id_0_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (version_id_0_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (version_id_0_s_agent_m0_lock), // .lock
.m0_readdata (version_id_0_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (version_id_0_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (version_id_0_s_agent_m0_read), // .read
.m0_waitrequest (version_id_0_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (version_id_0_s_agent_m0_writedata), // .writedata
.m0_write (version_id_0_s_agent_m0_write), // .write
.rp_endofpacket (version_id_0_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (version_id_0_s_agent_rp_ready), // .ready
.rp_valid (version_id_0_s_agent_rp_valid), // .valid
.rp_data (version_id_0_s_agent_rp_data), // .data
.rp_startofpacket (version_id_0_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (version_id_0_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (version_id_0_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (version_id_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (version_id_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (version_id_0_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (version_id_0_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (version_id_0_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (version_id_0_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (version_id_0_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (version_id_0_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_005_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_005_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_005_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_005_out_0_error), // .error
.rdata_fifo_src_ready (version_id_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (version_id_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (version_id_0_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) version_id_0_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (version_id_0_s_agent_rf_source_data), // in.data
.in_valid (version_id_0_s_agent_rf_source_valid), // .valid
.in_ready (version_id_0_s_agent_rf_source_ready), // .ready
.in_startofpacket (version_id_0_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (version_id_0_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (version_id_0_s_agent_rsp_fifo_out_data), // out.data
.out_valid (version_id_0_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (version_id_0_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (version_id_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (version_id_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (88),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_TRANS_LOCK (54),
.PKT_BEGIN_BURST (68),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) irq_ena_0_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (irq_ena_0_s_agent_m0_address), // m0.address
.m0_burstcount (irq_ena_0_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (irq_ena_0_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (irq_ena_0_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (irq_ena_0_s_agent_m0_lock), // .lock
.m0_readdata (irq_ena_0_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (irq_ena_0_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (irq_ena_0_s_agent_m0_read), // .read
.m0_waitrequest (irq_ena_0_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (irq_ena_0_s_agent_m0_writedata), // .writedata
.m0_write (irq_ena_0_s_agent_m0_write), // .write
.rp_endofpacket (irq_ena_0_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (irq_ena_0_s_agent_rp_ready), // .ready
.rp_valid (irq_ena_0_s_agent_rp_valid), // .valid
.rp_data (irq_ena_0_s_agent_rp_data), // .data
.rp_startofpacket (irq_ena_0_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_006_src_ready), // cp.ready
.cp_valid (cmd_mux_006_src_valid), // .valid
.cp_data (cmd_mux_006_src_data), // .data
.cp_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_006_src_channel), // .channel
.rf_sink_ready (irq_ena_0_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (irq_ena_0_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (irq_ena_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (irq_ena_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (irq_ena_0_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (irq_ena_0_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (irq_ena_0_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (irq_ena_0_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (irq_ena_0_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (irq_ena_0_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_006_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_006_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_006_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_006_out_0_error), // .error
.rdata_fifo_src_ready (irq_ena_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (irq_ena_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (irq_ena_0_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) irq_ena_0_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (irq_ena_0_s_agent_rf_source_data), // in.data
.in_valid (irq_ena_0_s_agent_rf_source_valid), // .valid
.in_ready (irq_ena_0_s_agent_rf_source_ready), // .ready
.in_startofpacket (irq_ena_0_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (irq_ena_0_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (irq_ena_0_s_agent_rsp_fifo_out_data), // out.data
.out_valid (irq_ena_0_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (irq_ena_0_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (irq_ena_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (irq_ena_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router router (
.sink_ready (kernel_cntrl_m0_agent_cp_ready), // sink.ready
.sink_valid (kernel_cntrl_m0_agent_cp_valid), // .valid
.sink_data (kernel_cntrl_m0_agent_cp_data), // .data
.sink_startofpacket (kernel_cntrl_m0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cntrl_m0_agent_cp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_001 router_001 (
.sink_ready (address_span_extender_0_windowed_slave_agent_rp_ready), // sink.ready
.sink_valid (address_span_extender_0_windowed_slave_agent_rp_valid), // .valid
.sink_data (address_span_extender_0_windowed_slave_agent_rp_data), // .data
.sink_startofpacket (address_span_extender_0_windowed_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_windowed_slave_agent_rp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_002 router_002 (
.sink_ready (address_span_extender_0_cntl_agent_rp_ready), // sink.ready
.sink_valid (address_span_extender_0_cntl_agent_rp_valid), // .valid
.sink_data (address_span_extender_0_cntl_agent_rp_data), // .data
.sink_startofpacket (address_span_extender_0_cntl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_cntl_agent_rp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_002 router_003 (
.sink_ready (sys_description_rom_s1_agent_rp_ready), // sink.ready
.sink_valid (sys_description_rom_s1_agent_rp_valid), // .valid
.sink_data (sys_description_rom_s1_agent_rp_data), // .data
.sink_startofpacket (sys_description_rom_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sys_description_rom_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_002 router_004 (
.sink_ready (sw_reset_s_agent_rp_ready), // sink.ready
.sink_valid (sw_reset_s_agent_rp_valid), // .valid
.sink_data (sw_reset_s_agent_rp_data), // .data
.sink_startofpacket (sw_reset_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sw_reset_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_001 router_005 (
.sink_ready (mem_org_mode_s_agent_rp_ready), // sink.ready
.sink_valid (mem_org_mode_s_agent_rp_valid), // .valid
.sink_data (mem_org_mode_s_agent_rp_data), // .data
.sink_startofpacket (mem_org_mode_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (mem_org_mode_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_001 router_006 (
.sink_ready (version_id_0_s_agent_rp_ready), // sink.ready
.sink_valid (version_id_0_s_agent_rp_valid), // .valid
.sink_data (version_id_0_s_agent_rp_data), // .data
.sink_startofpacket (version_id_0_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (version_id_0_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_001 router_007 (
.sink_ready (irq_ena_0_s_agent_rp_ready), // sink.ready
.sink_valid (irq_ena_0_s_agent_rp_valid), // .valid
.sink_data (irq_ena_0_s_agent_rp_data), // .data
.sink_startofpacket (irq_ena_0_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (irq_ena_0_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.MAX_OUTSTANDING_RESPONSES (5),
.PIPELINED (0),
.ST_DATA_W (89),
.ST_CHANNEL_W (7),
.VALID_WIDTH (7),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) kernel_cntrl_m0_limiter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (kernel_cntrl_m0_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (kernel_cntrl_m0_limiter_cmd_src_data), // .data
.cmd_src_channel (kernel_cntrl_m0_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (kernel_cntrl_m0_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (kernel_cntrl_m0_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (kernel_cntrl_m0_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (kernel_cntrl_m0_limiter_rsp_src_valid), // .valid
.rsp_src_data (kernel_cntrl_m0_limiter_rsp_src_data), // .data
.rsp_src_channel (kernel_cntrl_m0_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (kernel_cntrl_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (kernel_cntrl_m0_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (kernel_cntrl_m0_limiter_cmd_valid_data) // cmd_valid.data
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_demux cmd_demux (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (kernel_cntrl_m0_limiter_cmd_src_ready), // sink.ready
.sink_channel (kernel_cntrl_m0_limiter_cmd_src_channel), // .channel
.sink_data (kernel_cntrl_m0_limiter_cmd_src_data), // .data
.sink_startofpacket (kernel_cntrl_m0_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cntrl_m0_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (kernel_cntrl_m0_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_src5_ready), // src5.ready
.src5_valid (cmd_demux_src5_valid), // .valid
.src5_data (cmd_demux_src5_data), // .data
.src5_channel (cmd_demux_src5_channel), // .channel
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.src6_ready (cmd_demux_src6_ready), // src6.ready
.src6_valid (cmd_demux_src6_valid), // .valid
.src6_data (cmd_demux_src6_data), // .data
.src6_channel (cmd_demux_src6_channel), // .channel
.src6_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_demux_src6_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux cmd_mux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (crosser_out_ready), // sink0.ready
.sink0_valid (crosser_out_valid), // .valid
.sink0_channel (crosser_out_channel), // .channel
.sink0_data (crosser_out_data), // .data
.sink0_startofpacket (crosser_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_out_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux cmd_mux_001 (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (crosser_001_out_ready), // sink0.ready
.sink0_valid (crosser_001_out_valid), // .valid
.sink0_channel (crosser_001_out_channel), // .channel
.sink0_data (crosser_001_out_data), // .data
.sink0_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_001_out_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux cmd_mux_002 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux cmd_mux_003 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux cmd_mux_004 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_src4_valid), // .valid
.sink0_channel (cmd_demux_src4_channel), // .channel
.sink0_data (cmd_demux_src4_data), // .data
.sink0_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src4_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux cmd_mux_005 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_src5_valid), // .valid
.sink0_channel (cmd_demux_src5_channel), // .channel
.sink0_data (cmd_demux_src5_data), // .data
.sink0_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src5_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux cmd_mux_006 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_006_src_ready), // src.ready
.src_valid (cmd_mux_006_src_valid), // .valid
.src_data (cmd_mux_006_src_data), // .data
.src_channel (cmd_mux_006_src_channel), // .channel
.src_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src6_ready), // sink0.ready
.sink0_valid (cmd_demux_src6_valid), // .valid
.sink0_channel (cmd_demux_src6_channel), // .channel
.sink0_data (cmd_demux_src6_data), // .data
.sink0_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src6_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux rsp_demux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux rsp_demux_001 (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (address_span_extender_0_cntl_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (address_span_extender_0_cntl_rsp_width_adapter_src_channel), // .channel
.sink_data (address_span_extender_0_cntl_rsp_width_adapter_src_data), // .data
.sink_startofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (address_span_extender_0_cntl_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_002 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (sys_description_rom_s1_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (sys_description_rom_s1_rsp_width_adapter_src_channel), // .channel
.sink_data (sys_description_rom_s1_rsp_width_adapter_src_data), // .data
.sink_startofpacket (sys_description_rom_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (sys_description_rom_s1_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (sys_description_rom_s1_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_003 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (sw_reset_s_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (sw_reset_s_rsp_width_adapter_src_channel), // .channel
.sink_data (sw_reset_s_rsp_width_adapter_src_data), // .data
.sink_startofpacket (sw_reset_s_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (sw_reset_s_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (sw_reset_s_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_004 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_005 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_006 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_demux_006_src0_valid), // .valid
.src0_data (rsp_demux_006_src0_data), // .data
.src0_channel (rsp_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_mux rsp_mux (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (crosser_002_out_ready), // sink0.ready
.sink0_valid (crosser_002_out_valid), // .valid
.sink0_channel (crosser_002_out_channel), // .channel
.sink0_data (crosser_002_out_data), // .data
.sink0_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.sink1_ready (crosser_003_out_ready), // sink1.ready
.sink1_valid (crosser_003_out_valid), // .valid
.sink1_channel (crosser_003_out_channel), // .channel
.sink1_data (crosser_003_out_data), // .data
.sink1_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (rsp_demux_006_src0_ready), // sink6.ready
.sink6_valid (rsp_demux_006_src0_valid), // .valid
.sink6_channel (rsp_demux_006_src0_channel), // .channel
.sink6_data (rsp_demux_006_src0_data), // .data
.sink6_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (59),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_TRANS_WRITE (52),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (60),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (85),
.IN_PKT_RESPONSE_STATUS_L (84),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (86),
.IN_PKT_ORI_BURST_SIZE_H (88),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (85),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (95),
.OUT_PKT_BYTE_CNT_L (92),
.OUT_PKT_TRANS_COMPRESSED_READ (86),
.OUT_PKT_BURST_SIZE_H (99),
.OUT_PKT_BURST_SIZE_L (97),
.OUT_PKT_RESPONSE_STATUS_H (121),
.OUT_PKT_RESPONSE_STATUS_L (120),
.OUT_PKT_TRANS_EXCLUSIVE (91),
.OUT_PKT_BURST_TYPE_H (101),
.OUT_PKT_BURST_TYPE_L (100),
.OUT_PKT_ORI_BURST_SIZE_L (122),
.OUT_PKT_ORI_BURST_SIZE_H (124),
.OUT_ST_DATA_W (125),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) address_span_extender_0_cntl_cmd_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_001_src_valid), // sink.valid
.in_channel (cmd_mux_001_src_channel), // .channel
.in_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_001_src_ready), // .ready
.in_data (cmd_mux_001_src_data), // .data
.out_endofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (address_span_extender_0_cntl_cmd_width_adapter_src_data), // .data
.out_channel (address_span_extender_0_cntl_cmd_width_adapter_src_channel), // .channel
.out_valid (address_span_extender_0_cntl_cmd_width_adapter_src_valid), // .valid
.out_ready (address_span_extender_0_cntl_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (59),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_TRANS_WRITE (52),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (60),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (85),
.IN_PKT_RESPONSE_STATUS_L (84),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (86),
.IN_PKT_ORI_BURST_SIZE_H (88),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (85),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (95),
.OUT_PKT_BYTE_CNT_L (92),
.OUT_PKT_TRANS_COMPRESSED_READ (86),
.OUT_PKT_BURST_SIZE_H (99),
.OUT_PKT_BURST_SIZE_L (97),
.OUT_PKT_RESPONSE_STATUS_H (121),
.OUT_PKT_RESPONSE_STATUS_L (120),
.OUT_PKT_TRANS_EXCLUSIVE (91),
.OUT_PKT_BURST_TYPE_H (101),
.OUT_PKT_BURST_TYPE_L (100),
.OUT_PKT_ORI_BURST_SIZE_L (122),
.OUT_PKT_ORI_BURST_SIZE_H (124),
.OUT_ST_DATA_W (125),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sys_description_rom_s1_cmd_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_002_src_valid), // sink.valid
.in_channel (cmd_mux_002_src_channel), // .channel
.in_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_002_src_ready), // .ready
.in_data (cmd_mux_002_src_data), // .data
.out_endofpacket (sys_description_rom_s1_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sys_description_rom_s1_cmd_width_adapter_src_data), // .data
.out_channel (sys_description_rom_s1_cmd_width_adapter_src_channel), // .channel
.out_valid (sys_description_rom_s1_cmd_width_adapter_src_valid), // .valid
.out_ready (sys_description_rom_s1_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sys_description_rom_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (59),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_TRANS_WRITE (52),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (60),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (85),
.IN_PKT_RESPONSE_STATUS_L (84),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (86),
.IN_PKT_ORI_BURST_SIZE_H (88),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (85),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (95),
.OUT_PKT_BYTE_CNT_L (92),
.OUT_PKT_TRANS_COMPRESSED_READ (86),
.OUT_PKT_BURST_SIZE_H (99),
.OUT_PKT_BURST_SIZE_L (97),
.OUT_PKT_RESPONSE_STATUS_H (121),
.OUT_PKT_RESPONSE_STATUS_L (120),
.OUT_PKT_TRANS_EXCLUSIVE (91),
.OUT_PKT_BURST_TYPE_H (101),
.OUT_PKT_BURST_TYPE_L (100),
.OUT_PKT_ORI_BURST_SIZE_L (122),
.OUT_PKT_ORI_BURST_SIZE_H (124),
.OUT_ST_DATA_W (125),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sw_reset_s_cmd_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_003_src_valid), // sink.valid
.in_channel (cmd_mux_003_src_channel), // .channel
.in_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_003_src_ready), // .ready
.in_data (cmd_mux_003_src_data), // .data
.out_endofpacket (sw_reset_s_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sw_reset_s_cmd_width_adapter_src_data), // .data
.out_channel (sw_reset_s_cmd_width_adapter_src_channel), // .channel
.out_valid (sw_reset_s_cmd_width_adapter_src_valid), // .valid
.out_ready (sw_reset_s_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sw_reset_s_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (85),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (95),
.IN_PKT_BYTE_CNT_L (92),
.IN_PKT_TRANS_COMPRESSED_READ (86),
.IN_PKT_TRANS_WRITE (88),
.IN_PKT_BURSTWRAP_H (96),
.IN_PKT_BURSTWRAP_L (96),
.IN_PKT_BURST_SIZE_H (99),
.IN_PKT_BURST_SIZE_L (97),
.IN_PKT_RESPONSE_STATUS_H (121),
.IN_PKT_RESPONSE_STATUS_L (120),
.IN_PKT_TRANS_EXCLUSIVE (91),
.IN_PKT_BURST_TYPE_H (101),
.IN_PKT_BURST_TYPE_L (100),
.IN_PKT_ORI_BURST_SIZE_L (122),
.IN_PKT_ORI_BURST_SIZE_H (124),
.IN_ST_DATA_W (125),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (59),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (85),
.OUT_PKT_RESPONSE_STATUS_L (84),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (86),
.OUT_PKT_ORI_BURST_SIZE_H (88),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) address_span_extender_0_cntl_rsp_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_002_src_valid), // sink.valid
.in_channel (router_002_src_channel), // .channel
.in_startofpacket (router_002_src_startofpacket), // .startofpacket
.in_endofpacket (router_002_src_endofpacket), // .endofpacket
.in_ready (router_002_src_ready), // .ready
.in_data (router_002_src_data), // .data
.out_endofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (address_span_extender_0_cntl_rsp_width_adapter_src_data), // .data
.out_channel (address_span_extender_0_cntl_rsp_width_adapter_src_channel), // .channel
.out_valid (address_span_extender_0_cntl_rsp_width_adapter_src_valid), // .valid
.out_ready (address_span_extender_0_cntl_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (85),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (95),
.IN_PKT_BYTE_CNT_L (92),
.IN_PKT_TRANS_COMPRESSED_READ (86),
.IN_PKT_TRANS_WRITE (88),
.IN_PKT_BURSTWRAP_H (96),
.IN_PKT_BURSTWRAP_L (96),
.IN_PKT_BURST_SIZE_H (99),
.IN_PKT_BURST_SIZE_L (97),
.IN_PKT_RESPONSE_STATUS_H (121),
.IN_PKT_RESPONSE_STATUS_L (120),
.IN_PKT_TRANS_EXCLUSIVE (91),
.IN_PKT_BURST_TYPE_H (101),
.IN_PKT_BURST_TYPE_L (100),
.IN_PKT_ORI_BURST_SIZE_L (122),
.IN_PKT_ORI_BURST_SIZE_H (124),
.IN_ST_DATA_W (125),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (59),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (85),
.OUT_PKT_RESPONSE_STATUS_L (84),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (86),
.OUT_PKT_ORI_BURST_SIZE_H (88),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sys_description_rom_s1_rsp_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_003_src_valid), // sink.valid
.in_channel (router_003_src_channel), // .channel
.in_startofpacket (router_003_src_startofpacket), // .startofpacket
.in_endofpacket (router_003_src_endofpacket), // .endofpacket
.in_ready (router_003_src_ready), // .ready
.in_data (router_003_src_data), // .data
.out_endofpacket (sys_description_rom_s1_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sys_description_rom_s1_rsp_width_adapter_src_data), // .data
.out_channel (sys_description_rom_s1_rsp_width_adapter_src_channel), // .channel
.out_valid (sys_description_rom_s1_rsp_width_adapter_src_valid), // .valid
.out_ready (sys_description_rom_s1_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (sys_description_rom_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (85),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (95),
.IN_PKT_BYTE_CNT_L (92),
.IN_PKT_TRANS_COMPRESSED_READ (86),
.IN_PKT_TRANS_WRITE (88),
.IN_PKT_BURSTWRAP_H (96),
.IN_PKT_BURSTWRAP_L (96),
.IN_PKT_BURST_SIZE_H (99),
.IN_PKT_BURST_SIZE_L (97),
.IN_PKT_RESPONSE_STATUS_H (121),
.IN_PKT_RESPONSE_STATUS_L (120),
.IN_PKT_TRANS_EXCLUSIVE (91),
.IN_PKT_BURST_TYPE_H (101),
.IN_PKT_BURST_TYPE_L (100),
.IN_PKT_ORI_BURST_SIZE_L (122),
.IN_PKT_ORI_BURST_SIZE_H (124),
.IN_ST_DATA_W (125),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (59),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (85),
.OUT_PKT_RESPONSE_STATUS_L (84),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (86),
.OUT_PKT_ORI_BURST_SIZE_H (88),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sw_reset_s_rsp_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_004_src_valid), // sink.valid
.in_channel (router_004_src_channel), // .channel
.in_startofpacket (router_004_src_startofpacket), // .startofpacket
.in_endofpacket (router_004_src_endofpacket), // .endofpacket
.in_ready (router_004_src_ready), // .ready
.in_data (router_004_src_data), // .data
.out_endofpacket (sw_reset_s_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sw_reset_s_rsp_width_adapter_src_data), // .data
.out_channel (sw_reset_s_rsp_width_adapter_src_channel), // .channel
.out_valid (sw_reset_s_rsp_width_adapter_src_valid), // .valid
.out_ready (sw_reset_s_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (sw_reset_s_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser (
.in_clk (clk_reset_clk_clk), // in_clk.clk
.in_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (kernel_clk_out_clk_clk), // out_clk.clk
.out_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src0_ready), // in.ready
.in_valid (cmd_demux_src0_valid), // .valid
.in_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.in_channel (cmd_demux_src0_channel), // .channel
.in_data (cmd_demux_src0_data), // .data
.out_ready (crosser_out_ready), // out.ready
.out_valid (crosser_out_valid), // .valid
.out_startofpacket (crosser_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_out_endofpacket), // .endofpacket
.out_channel (crosser_out_channel), // .channel
.out_data (crosser_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_001 (
.in_clk (clk_reset_clk_clk), // in_clk.clk
.in_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (kernel_clk_out_clk_clk), // out_clk.clk
.out_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src1_ready), // in.ready
.in_valid (cmd_demux_src1_valid), // .valid
.in_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.in_channel (cmd_demux_src1_channel), // .channel
.in_data (cmd_demux_src1_data), // .data
.out_ready (crosser_001_out_ready), // out.ready
.out_valid (crosser_001_out_valid), // .valid
.out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.out_channel (crosser_001_out_channel), // .channel
.out_data (crosser_001_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_002 (
.in_clk (kernel_clk_out_clk_clk), // in_clk.clk
.in_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_reset_clk_clk), // out_clk.clk
.out_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_src0_ready), // in.ready
.in_valid (rsp_demux_src0_valid), // .valid
.in_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_src0_channel), // .channel
.in_data (rsp_demux_src0_data), // .data
.out_ready (crosser_002_out_ready), // out.ready
.out_valid (crosser_002_out_valid), // .valid
.out_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.out_channel (crosser_002_out_channel), // .channel
.out_data (crosser_002_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_003 (
.in_clk (kernel_clk_out_clk_clk), // in_clk.clk
.in_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_reset_clk_clk), // out_clk.clk
.out_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_001_src0_ready), // in.ready
.in_valid (rsp_demux_001_src0_valid), // .valid
.in_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_001_src0_channel), // .channel
.in_data (rsp_demux_001_src0_data), // .data
.out_ready (crosser_003_out_ready), // out.ready
.out_valid (crosser_003_out_valid), // .valid
.out_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.out_channel (crosser_003_out_channel), // .channel
.out_data (crosser_003_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
system_acl_iface_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (kernel_clk_out_clk_clk), // in_clk_0.clk
.in_rst_0_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (66),
.inUsePackets (0),
.inDataWidth (66),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (66),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (kernel_clk_out_clk_clk), // in_clk_0.clk
.in_rst_0_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (address_span_extender_0_cntl_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (address_span_extender_0_cntl_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (address_span_extender_0_cntl_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (66),
.inUsePackets (0),
.inDataWidth (66),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (66),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_002 (
.in_clk_0_clk (clk_reset_clk_clk), // in_clk_0.clk
.in_rst_0_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sys_description_rom_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (sys_description_rom_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (sys_description_rom_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_002_out_0_error) // .error
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (66),
.inUsePackets (0),
.inDataWidth (66),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (66),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_003 (
.in_clk_0_clk (clk_reset_clk_clk), // in_clk_0.clk
.in_rst_0_reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sw_reset_s_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (sw_reset_s_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (sw_reset_s_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_003_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_003_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_003_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_003_out_0_error) // .error
);
system_acl_iface_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_004 (
.in_clk_0_clk (clk_reset_clk_clk), // in_clk_0.clk
.in_rst_0_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (mem_org_mode_s_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (mem_org_mode_s_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (mem_org_mode_s_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_004_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_004_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_004_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_004_out_0_error) // .error
);
system_acl_iface_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_005 (
.in_clk_0_clk (clk_reset_clk_clk), // in_clk_0.clk
.in_rst_0_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (version_id_0_s_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (version_id_0_s_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (version_id_0_s_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_005_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_005_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_005_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_005_out_0_error) // .error
);
system_acl_iface_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_006 (
.in_clk_0_clk (clk_reset_clk_clk), // in_clk_0.clk
.in_rst_0_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (irq_ena_0_s_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (irq_ena_0_s_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (irq_ena_0_s_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_006_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_006_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_006_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_006_out_0_error) // .error
);
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2016 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Set Implicit Arguments.
Require Export Notations.
Notation "A -> B" := (forall (_ : A), B) : type_scope.
(** * Propositional connectives *)
(** [True] is the always true proposition *)
Inductive True : Prop :=
I : True.
(** [False] is the always false proposition *)
Inductive False : Prop :=.
(** [not A], written [~A], is the negation of [A] *)
Definition not (A:Prop) := A -> False.
Notation "~ x" := (not x) : type_scope.
Hint Unfold not: core.
(** [and A B], written [A /\ B], is the conjunction of [A] and [B]
[conj p q] is a proof of [A /\ B] as soon as
[p] is a proof of [A] and [q] a proof of [B]
[proj1] and [proj2] are first and second projections of a conjunction *)
Inductive and (A B:Prop) : Prop :=
conj : A -> B -> A /\ B
where "A /\ B" := (and A B) : type_scope.
Section Conjunction.
Variables A B : Prop.
Theorem proj1 : A /\ B -> A.
Proof.
destruct 1; trivial.
Qed.
Theorem proj2 : A /\ B -> B.
Proof.
destruct 1; trivial.
Qed.
End Conjunction.
(** [or A B], written [A \/ B], is the disjunction of [A] and [B] *)
Inductive or (A B:Prop) : Prop :=
| or_introl : A -> A \/ B
| or_intror : B -> A \/ B
where "A \/ B" := (or A B) : type_scope.
Arguments or_introl [A B] _, [A] B _.
Arguments or_intror [A B] _, A [B] _.
(** [iff A B], written [A <-> B], expresses the equivalence of [A] and [B] *)
Definition iff (A B:Prop) := (A -> B) /\ (B -> A).
Notation "A <-> B" := (iff A B) : type_scope.
Section Equivalence.
Theorem iff_refl : forall A:Prop, A <-> A.
Proof.
split; auto.
Qed.
Theorem iff_trans : forall A B C:Prop, (A <-> B) -> (B <-> C) -> (A <-> C).
Proof.
intros A B C [H1 H2] [H3 H4]; split; auto.
Qed.
Theorem iff_sym : forall A B:Prop, (A <-> B) -> (B <-> A).
Proof.
intros A B [H1 H2]; split; auto.
Qed.
End Equivalence.
Hint Unfold iff: extcore.
(** Backward direction of the equivalences above does not need assumptions *)
Theorem and_iff_compat_l : forall A B C : Prop,
(B <-> C) -> (A /\ B <-> A /\ C).
Proof.
intros ? ? ? [Hl Hr]; split; intros [? ?]; (split; [ assumption | ]);
[apply Hl | apply Hr]; assumption.
Qed.
Theorem and_iff_compat_r : forall A B C : Prop,
(B <-> C) -> (B /\ A <-> C /\ A).
Proof.
intros ? ? ? [Hl Hr]; split; intros [? ?]; (split; [ | assumption ]);
[apply Hl | apply Hr]; assumption.
Qed.
Theorem or_iff_compat_l : forall A B C : Prop,
(B <-> C) -> (A \/ B <-> A \/ C).
Proof.
intros ? ? ? [Hl Hr]; split; (intros [?|?]; [left; assumption| right]);
[apply Hl | apply Hr]; assumption.
Qed.
Theorem or_iff_compat_r : forall A B C : Prop,
(B <-> C) -> (B \/ A <-> C \/ A).
Proof.
intros ? ? ? [Hl Hr]; split; (intros [?|?]; [left| right; assumption]);
[apply Hl | apply Hr]; assumption.
Qed.
Theorem imp_iff_compat_l : forall A B C : Prop,
(B <-> C) -> ((A -> B) <-> (A -> C)).
Proof.
intros ? ? ? [Hl Hr]; split; intros H ?; [apply Hl | apply Hr]; apply H; assumption.
Qed.
Theorem imp_iff_compat_r : forall A B C : Prop,
(B <-> C) -> ((B -> A) <-> (C -> A)).
Proof.
intros ? ? ? [Hl Hr]; split; intros H ?; [apply H, Hr | apply H, Hl]; assumption.
Qed.
Theorem not_iff_compat : forall A B : Prop,
(A <-> B) -> (~ A <-> ~B).
Proof.
intros; apply imp_iff_compat_r; assumption.
Qed.
(** Some equivalences *)
Theorem neg_false : forall A : Prop, ~ A <-> (A <-> False).
Proof.
intro A; unfold not; split.
- intro H; split; [exact H | intro H1; elim H1].
- intros [H _]; exact H.
Qed.
Theorem and_cancel_l : forall A B C : Prop,
(B -> A) -> (C -> A) -> ((A /\ B <-> A /\ C) <-> (B <-> C)).
Proof.
intros A B C Hl Hr.
split; [ | apply and_iff_compat_l]; intros [HypL HypR]; split; intros.
+ apply HypL; split; [apply Hl | ]; assumption.
+ apply HypR; split; [apply Hr | ]; assumption.
Qed.
Theorem and_cancel_r : forall A B C : Prop,
(B -> A) -> (C -> A) -> ((B /\ A <-> C /\ A) <-> (B <-> C)).
Proof.
intros A B C Hl Hr.
split; [ | apply and_iff_compat_r]; intros [HypL HypR]; split; intros.
+ apply HypL; split; [ | apply Hl ]; assumption.
+ apply HypR; split; [ | apply Hr ]; assumption.
Qed.
Theorem and_comm : forall A B : Prop, A /\ B <-> B /\ A.
Proof.
intros; split; intros [? ?]; split; assumption.
Qed.
Theorem and_assoc : forall A B C : Prop, (A /\ B) /\ C <-> A /\ B /\ C.
Proof.
intros; split; [ intros [[? ?] ?]| intros [? [? ?]]]; repeat split; assumption.
Qed.
Theorem or_cancel_l : forall A B C : Prop,
(B -> ~ A) -> (C -> ~ A) -> ((A \/ B <-> A \/ C) <-> (B <-> C)).
Proof.
intros ? ? ? Fl Fr; split; [ | apply or_iff_compat_l]; intros [Hl Hr]; split; intros.
{ destruct Hl; [ right | destruct Fl | ]; assumption. }
{ destruct Hr; [ right | destruct Fr | ]; assumption. }
Qed.
Theorem or_cancel_r : forall A B C : Prop,
(B -> ~ A) -> (C -> ~ A) -> ((B \/ A <-> C \/ A) <-> (B <-> C)).
Proof.
intros ? ? ? Fl Fr; split; [ | apply or_iff_compat_r]; intros [Hl Hr]; split; intros.
{ destruct Hl; [ left | | destruct Fl ]; assumption. }
{ destruct Hr; [ left | | destruct Fr ]; assumption. }
Qed.
Theorem or_comm : forall A B : Prop, (A \/ B) <-> (B \/ A).
Proof.
intros; split; (intros [? | ?]; [ right | left ]; assumption).
Qed.
Theorem or_assoc : forall A B C : Prop, (A \/ B) \/ C <-> A \/ B \/ C.
Proof.
intros; split; [ intros [[?|?]|?]| intros [?|[?|?]]].
+ left; assumption.
+ right; left; assumption.
+ right; right; assumption.
+ left; left; assumption.
+ left; right; assumption.
+ right; assumption.
Qed.
Lemma iff_and : forall A B : Prop, (A <-> B) -> (A -> B) /\ (B -> A).
Proof.
intros A B []; split; trivial.
Qed.
Lemma iff_to_and : forall A B : Prop, (A <-> B) <-> (A -> B) /\ (B -> A).
Proof.
intros; split; intros [Hl Hr]; (split; intros; [ apply Hl | apply Hr]); assumption.
Qed.
(** [(IF_then_else P Q R)], written [IF P then Q else R] denotes
either [P] and [Q], or [~P] and [R] *)
Definition IF_then_else (P Q R:Prop) := P /\ Q \/ ~ P /\ R.
Notation "'IF' c1 'then' c2 'else' c3" := (IF_then_else c1 c2 c3)
(at level 200, right associativity) : type_scope.
(** * First-order quantifiers *)
(** [ex P], or simply [exists x, P x], or also [exists x:A, P x],
expresses the existence of an [x] of some type [A] in [Set] which
satisfies the predicate [P]. This is existential quantification.
[ex2 P Q], or simply [exists2 x, P x & Q x], or also
[exists2 x:A, P x & Q x], expresses the existence of an [x] of
type [A] which satisfies both predicates [P] and [Q].
Universal quantification is primitively written [forall x:A, Q]. By
symmetry with existential quantification, the construction [all P]
is provided too.
*)
Inductive ex (A:Type) (P:A -> Prop) : Prop :=
ex_intro : forall x:A, P x -> ex (A:=A) P.
Inductive ex2 (A:Type) (P Q:A -> Prop) : Prop :=
ex_intro2 : forall x:A, P x -> Q x -> ex2 (A:=A) P Q.
Definition all (A:Type) (P:A -> Prop) := forall x:A, P x.
(* Rule order is important to give printing priority to fully typed exists *)
Notation "'exists' x .. y , p" := (ex (fun x => .. (ex (fun y => p)) ..))
(at level 200, x binder, right associativity,
format "'[' 'exists' '/ ' x .. y , '/ ' p ']'")
: type_scope.
Notation "'exists2' x , p & q" := (ex2 (fun x => p) (fun x => q))
(at level 200, x ident, p at level 200, right associativity) : type_scope.
Notation "'exists2' x : A , p & q" := (ex2 (A:=A) (fun x => p) (fun x => q))
(at level 200, x ident, A at level 200, p at level 200, right associativity,
format "'[' 'exists2' '/ ' x : A , '/ ' '[' p & '/' q ']' ']'")
: type_scope.
(** Derived rules for universal quantification *)
Section universal_quantification.
Variable A : Type.
Variable P : A -> Prop.
Theorem inst : forall x:A, all (fun x => P x) -> P x.
Proof.
unfold all; auto.
Qed.
Theorem gen : forall (B:Prop) (f:forall y:A, B -> P y), B -> all P.
Proof.
red; auto.
Qed.
End universal_quantification.
(** * Equality *)
(** [eq x y], or simply [x=y] expresses the equality of [x] and
[y]. Both [x] and [y] must belong to the same type [A].
The definition is inductive and states the reflexivity of the equality.
The others properties (symmetry, transitivity, replacement of
equals by equals) are proved below. The type of [x] and [y] can be
made explicit using the notation [x = y :> A]. This is Leibniz equality
as it expresses that [x] and [y] are equal iff every property on
[A] which is true of [x] is also true of [y] *)
Inductive eq (A:Type) (x:A) : A -> Prop :=
eq_refl : x = x :>A
where "x = y :> A" := (@eq A x y) : type_scope.
Notation "x = y" := (x = y :>_) : type_scope.
Notation "x <> y :> T" := (~ x = y :>T) : type_scope.
Notation "x <> y" := (x <> y :>_) : type_scope.
Arguments eq {A} x _.
Arguments eq_refl {A x} , [A] x.
Arguments eq_ind [A] x P _ y _.
Arguments eq_rec [A] x P _ y _.
Arguments eq_rect [A] x P _ y _.
Hint Resolve I conj or_introl or_intror : core.
Hint Resolve eq_refl: core.
Hint Resolve ex_intro ex_intro2: core.
Section Logic_lemmas.
Theorem absurd : forall A C:Prop, A -> ~ A -> C.
Proof.
unfold not; intros A C h1 h2.
destruct (h2 h1).
Qed.
Section equality.
Variables A B : Type.
Variable f : A -> B.
Variables x y z : A.
Theorem eq_sym : x = y -> y = x.
Proof.
destruct 1; trivial.
Defined.
Theorem eq_trans : x = y -> y = z -> x = z.
Proof.
destruct 2; trivial.
Defined.
Theorem f_equal : x = y -> f x = f y.
Proof.
destruct 1; trivial.
Defined.
Theorem not_eq_sym : x <> y -> y <> x.
Proof.
red; intros h1 h2; apply h1; destruct h2; trivial.
Qed.
End equality.
Definition eq_ind_r :
forall (A:Type) (x:A) (P:A -> Prop), P x -> forall y:A, y = x -> P y.
intros A x P H y H0. elim eq_sym with (1 := H0); assumption.
Defined.
Definition eq_rec_r :
forall (A:Type) (x:A) (P:A -> Set), P x -> forall y:A, y = x -> P y.
intros A x P H y H0; elim eq_sym with (1 := H0); assumption.
Defined.
Definition eq_rect_r :
forall (A:Type) (x:A) (P:A -> Type), P x -> forall y:A, y = x -> P y.
intros A x P H y H0; elim eq_sym with (1 := H0); assumption.
Defined.
End Logic_lemmas.
Module EqNotations.
Notation "'rew' H 'in' H'" := (eq_rect _ _ H' _ H)
(at level 10, H' at level 10,
format "'[' 'rew' H in '/' H' ']'").
Notation "'rew' [ P ] H 'in' H'" := (eq_rect _ P H' _ H)
(at level 10, H' at level 10,
format "'[' 'rew' [ P ] '/ ' H in '/' H' ']'").
Notation "'rew' <- H 'in' H'" := (eq_rect_r _ H' H)
(at level 10, H' at level 10,
format "'[' 'rew' <- H in '/' H' ']'").
Notation "'rew' <- [ P ] H 'in' H'" := (eq_rect_r P H' H)
(at level 10, H' at level 10,
format "'[' 'rew' <- [ P ] '/ ' H in '/' H' ']'").
Notation "'rew' -> H 'in' H'" := (eq_rect _ _ H' _ H)
(at level 10, H' at level 10, only parsing).
Notation "'rew' -> [ P ] H 'in' H'" := (eq_rect _ P H' _ H)
(at level 10, H' at level 10, only parsing).
End EqNotations.
Import EqNotations.
Lemma rew_opp_r : forall A (P:A->Type) (x y:A) (H:x=y) (a:P y), rew H in rew <- H in a = a.
Proof.
intros.
destruct H.
reflexivity.
Defined.
Lemma rew_opp_l : forall A (P:A->Type) (x y:A) (H:x=y) (a:P x), rew <- H in rew H in a = a.
Proof.
intros.
destruct H.
reflexivity.
Defined.
Theorem f_equal2 :
forall (A1 A2 B:Type) (f:A1 -> A2 -> B) (x1 y1:A1)
(x2 y2:A2), x1 = y1 -> x2 = y2 -> f x1 x2 = f y1 y2.
Proof.
destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal3 :
forall (A1 A2 A3 B:Type) (f:A1 -> A2 -> A3 -> B) (x1 y1:A1)
(x2 y2:A2) (x3 y3:A3),
x1 = y1 -> x2 = y2 -> x3 = y3 -> f x1 x2 x3 = f y1 y2 y3.
Proof.
destruct 1; destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal4 :
forall (A1 A2 A3 A4 B:Type) (f:A1 -> A2 -> A3 -> A4 -> B)
(x1 y1:A1) (x2 y2:A2) (x3 y3:A3) (x4 y4:A4),
x1 = y1 -> x2 = y2 -> x3 = y3 -> x4 = y4 -> f x1 x2 x3 x4 = f y1 y2 y3 y4.
Proof.
destruct 1; destruct 1; destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal5 :
forall (A1 A2 A3 A4 A5 B:Type) (f:A1 -> A2 -> A3 -> A4 -> A5 -> B)
(x1 y1:A1) (x2 y2:A2) (x3 y3:A3) (x4 y4:A4) (x5 y5:A5),
x1 = y1 ->
x2 = y2 ->
x3 = y3 -> x4 = y4 -> x5 = y5 -> f x1 x2 x3 x4 x5 = f y1 y2 y3 y4 y5.
Proof.
destruct 1; destruct 1; destruct 1; destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal_compose : forall A B C (a b:A) (f:A->B) (g:B->C) (e:a=b),
f_equal g (f_equal f e) = f_equal (fun a => g (f a)) e.
Proof.
destruct e. reflexivity.
Defined.
(** The goupoid structure of equality *)
Theorem eq_trans_refl_l : forall A (x y:A) (e:x=y), eq_trans eq_refl e = e.
Proof.
destruct e. reflexivity.
Defined.
Theorem eq_trans_refl_r : forall A (x y:A) (e:x=y), eq_trans e eq_refl = e.
Proof.
destruct e. reflexivity.
Defined.
Theorem eq_sym_involutive : forall A (x y:A) (e:x=y), eq_sym (eq_sym e) = e.
Proof.
destruct e; reflexivity.
Defined.
Theorem eq_trans_sym_inv_l : forall A (x y:A) (e:x=y), eq_trans (eq_sym e) e = eq_refl.
Proof.
destruct e; reflexivity.
Defined.
Theorem eq_trans_sym_inv_r : forall A (x y:A) (e:x=y), eq_trans e (eq_sym e) = eq_refl.
Proof.
destruct e; reflexivity.
Defined.
Theorem eq_trans_assoc : forall A (x y z t:A) (e:x=y) (e':y=z) (e'':z=t),
eq_trans e (eq_trans e' e'') = eq_trans (eq_trans e e') e''.
Proof.
destruct e''; reflexivity.
Defined.
(** Extra properties of equality *)
Theorem eq_id_comm_l : forall A (f:A->A) (Hf:forall a, a = f a), forall a, f_equal f (Hf a) = Hf (f a).
Proof.
intros.
unfold f_equal.
rewrite <- (eq_trans_sym_inv_l (Hf a)).
destruct (Hf a) at 1 2.
destruct (Hf a).
reflexivity.
Defined.
Theorem eq_id_comm_r : forall A (f:A->A) (Hf:forall a, f a = a), forall a, f_equal f (Hf a) = Hf (f a).
Proof.
intros.
unfold f_equal.
rewrite <- (eq_trans_sym_inv_l (Hf (f (f a)))).
set (Hfsymf := fun a => eq_sym (Hf a)).
change (eq_sym (Hf (f (f a)))) with (Hfsymf (f (f a))).
pattern (Hfsymf (f (f a))).
destruct (eq_id_comm_l f Hfsymf (f a)).
destruct (eq_id_comm_l f Hfsymf a).
unfold Hfsymf.
destruct (Hf a). simpl.
rewrite eq_trans_refl_l.
reflexivity.
Defined.
Lemma eq_trans_map_distr : forall A B x y z (f:A->B) (e:x=y) (e':y=z), f_equal f (eq_trans e e') = eq_trans (f_equal f e) (f_equal f e').
Proof.
destruct e'.
reflexivity.
Defined.
Lemma eq_sym_map_distr : forall A B (x y:A) (f:A->B) (e:x=y), eq_sym (f_equal f e) = f_equal f (eq_sym e).
Proof.
destruct e.
reflexivity.
Defined.
Lemma eq_trans_sym_distr : forall A (x y z:A) (e:x=y) (e':y=z), eq_sym (eq_trans e e') = eq_trans (eq_sym e') (eq_sym e).
Proof.
destruct e, e'.
reflexivity.
Defined.
(* Aliases *)
Notation sym_eq := eq_sym (compat "8.3").
Notation trans_eq := eq_trans (compat "8.3").
Notation sym_not_eq := not_eq_sym (compat "8.3").
Notation refl_equal := eq_refl (compat "8.3").
Notation sym_equal := eq_sym (compat "8.3").
Notation trans_equal := eq_trans (compat "8.3").
Notation sym_not_equal := not_eq_sym (compat "8.3").
Hint Immediate eq_sym not_eq_sym: core.
(** Basic definitions about relations and properties *)
Definition subrelation (A B : Type) (R R' : A->B->Prop) :=
forall x y, R x y -> R' x y.
Definition unique (A : Type) (P : A->Prop) (x:A) :=
P x /\ forall (x':A), P x' -> x=x'.
Definition uniqueness (A:Type) (P:A->Prop) := forall x y, P x -> P y -> x = y.
(** Unique existence *)
Notation "'exists' ! x .. y , p" :=
(ex (unique (fun x => .. (ex (unique (fun y => p))) ..)))
(at level 200, x binder, right associativity,
format "'[' 'exists' ! '/ ' x .. y , '/ ' p ']'")
: type_scope.
Lemma unique_existence : forall (A:Type) (P:A->Prop),
((exists x, P x) /\ uniqueness P) <-> (exists! x, P x).
Proof.
intros A P; split.
- intros ((x,Hx),Huni); exists x; red; auto.
- intros (x,(Hx,Huni)); split.
+ exists x; assumption.
+ intros x' x'' Hx' Hx''; transitivity x.
symmetry; auto.
auto.
Qed.
Lemma forall_exists_unique_domain_coincide :
forall A (P:A->Prop), (exists! x, P x) ->
forall Q:A->Prop, (forall x, P x -> Q x) <-> (exists x, P x /\ Q x).
Proof.
intros A P (x & Hp & Huniq); split.
- intro; exists x; auto.
- intros (x0 & HPx0 & HQx0) x1 HPx1.
assert (H : x0 = x1) by (transitivity x; [symmetry|]; auto).
destruct H.
assumption.
Qed.
Lemma forall_exists_coincide_unique_domain :
forall A (P:A->Prop),
(forall Q:A->Prop, (forall x, P x -> Q x) <-> (exists x, P x /\ Q x))
-> (exists! x, P x).
Proof.
intros A P H.
destruct H with (Q:=P) as ((x & Hx & _),_); [trivial|].
exists x. split; [trivial|].
destruct H with (Q:=fun x'=>x=x') as (_,Huniq).
apply Huniq. exists x; auto.
Qed.
(** * Being inhabited *)
(** The predicate [inhabited] can be used in different contexts. If [A] is
thought as a type, [inhabited A] states that [A] is inhabited. If [A] is
thought as a computationally relevant proposition, then
[inhabited A] weakens [A] so as to hide its computational meaning.
The so-weakened proof remains computationally relevant but only in
a propositional context.
*)
Inductive inhabited (A:Type) : Prop := inhabits : A -> inhabited A.
Hint Resolve inhabits: core.
Lemma exists_inhabited : forall (A:Type) (P:A->Prop),
(exists x, P x) -> inhabited A.
Proof.
destruct 1; auto.
Qed.
Lemma inhabited_covariant (A B : Type) : (A -> B) -> inhabited A -> inhabited B.
Proof.
intros f [x];exact (inhabits (f x)).
Qed.
(** Declaration of stepl and stepr for eq and iff *)
Lemma eq_stepl : forall (A : Type) (x y z : A), x = y -> x = z -> z = y.
Proof.
intros A x y z H1 H2. rewrite <- H2; exact H1.
Qed.
Declare Left Step eq_stepl.
Declare Right Step eq_trans.
Lemma iff_stepl : forall A B C : Prop, (A <-> B) -> (A <-> C) -> (C <-> B).
Proof.
intros ? ? ? [? ?] [? ?]; split; intros; auto.
Qed.
Declare Left Step iff_stepl.
Declare Right Step iff_trans.
|
//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2015.2.1 (lin64) Build 1302555 Wed Aug 5 13:06:02 MDT 2015
//Date : Wed Aug 17 16:30:57 2016
//Host : HomeMegaUbuntu running 64-bit Ubuntu 16.04.1 LTS
//Command : generate_target elink2_top_wrapper.bd
//Design : elink2_top_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module elink2_top_wrapper
(CCLK_N,
CCLK_P,
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
DSP_RESET_N,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
GPIO_N,
GPIO_P,
HDMI_CLK,
HDMI_D,
HDMI_DE,
HDMI_HSYNC,
HDMI_INT,
HDMI_SPDIF,
HDMI_VSYNC,
I2C_SCL,
I2C_SDA,
RX_data_n,
RX_data_p,
RX_frame_n,
RX_frame_p,
RX_lclk_n,
RX_lclk_p,
RX_rd_wait_n,
RX_rd_wait_p,
RX_wr_wait_n,
RX_wr_wait_p,
TX_data_n,
TX_data_p,
TX_frame_n,
TX_frame_p,
TX_lclk_n,
TX_lclk_p,
TX_wr_wait_n,
TX_wr_wait_p,
TXi_rd_wait_n,
TXi_rd_wait_p);
output CCLK_N;
output CCLK_P;
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
output [0:0]DSP_RESET_N;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout [23:0]GPIO_N;
inout [23:0]GPIO_P;
output HDMI_CLK;
output [15:0]HDMI_D;
output HDMI_DE;
output HDMI_HSYNC;
input [0:0]HDMI_INT;
output HDMI_SPDIF;
output HDMI_VSYNC;
inout I2C_SCL;
inout I2C_SDA;
input [7:0]RX_data_n;
input [7:0]RX_data_p;
input RX_frame_n;
input RX_frame_p;
input RX_lclk_n;
input RX_lclk_p;
output RX_rd_wait_n;
output RX_rd_wait_p;
output RX_wr_wait_n;
output RX_wr_wait_p;
output [7:0]TX_data_n;
output [7:0]TX_data_p;
output TX_frame_n;
output TX_frame_p;
output TX_lclk_n;
output TX_lclk_p;
input TX_wr_wait_n;
input TX_wr_wait_p;
input TXi_rd_wait_n;
input TXi_rd_wait_p;
wire CCLK_N;
wire CCLK_P;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire [0:0]DSP_RESET_N;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire [23:0]GPIO_N;
wire [23:0]GPIO_P;
wire HDMI_CLK;
wire [15:0]HDMI_D;
wire HDMI_DE;
wire HDMI_HSYNC;
wire [0:0]HDMI_INT;
wire HDMI_SPDIF;
wire HDMI_VSYNC;
wire I2C_SCL;
wire I2C_SDA;
wire [7:0]RX_data_n;
wire [7:0]RX_data_p;
wire RX_frame_n;
wire RX_frame_p;
wire RX_lclk_n;
wire RX_lclk_p;
wire RX_rd_wait_n;
wire RX_rd_wait_p;
wire RX_wr_wait_n;
wire RX_wr_wait_p;
wire [7:0]TX_data_n;
wire [7:0]TX_data_p;
wire TX_frame_n;
wire TX_frame_p;
wire TX_lclk_n;
wire TX_lclk_p;
wire TX_wr_wait_n;
wire TX_wr_wait_p;
wire TXi_rd_wait_n;
wire TXi_rd_wait_p;
elink2_top elink2_top_i
(.CCLK_N(CCLK_N),
.CCLK_P(CCLK_P),
.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.DSP_RESET_N(DSP_RESET_N),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.GPIO_N(GPIO_N),
.GPIO_P(GPIO_P),
.HDMI_CLK(HDMI_CLK),
.HDMI_D(HDMI_D),
.HDMI_DE(HDMI_DE),
.HDMI_HSYNC(HDMI_HSYNC),
.HDMI_INT(HDMI_INT),
.HDMI_SPDIF(HDMI_SPDIF),
.HDMI_VSYNC(HDMI_VSYNC),
.I2C_SCL(I2C_SCL),
.I2C_SDA(I2C_SDA),
.RX_data_n(RX_data_n),
.RX_data_p(RX_data_p),
.RX_frame_n(RX_frame_n),
.RX_frame_p(RX_frame_p),
.RX_lclk_n(RX_lclk_n),
.RX_lclk_p(RX_lclk_p),
.RX_rd_wait_n(RX_rd_wait_n),
.RX_rd_wait_p(RX_rd_wait_p),
.RX_wr_wait_n(RX_wr_wait_n),
.RX_wr_wait_p(RX_wr_wait_p),
.TX_data_n(TX_data_n),
.TX_data_p(TX_data_p),
.TX_frame_n(TX_frame_n),
.TX_frame_p(TX_frame_p),
.TX_lclk_n(TX_lclk_n),
.TX_lclk_p(TX_lclk_p),
.TX_wr_wait_n(TX_wr_wait_n),
.TX_wr_wait_p(TX_wr_wait_p),
.TXi_rd_wait_n(TXi_rd_wait_n),
.TXi_rd_wait_p(TXi_rd_wait_p));
endmodule
|
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`timescale 1 ns / 1 ps
//
// Simple SPI flash simulation model
//
// This model samples io input signals 1ns before the SPI clock edge and
// updates output signals 1ns after the SPI clock edge.
//
// Supported commands:
// AB, B9, FF, 03, BB, EB, ED
//
// Well written SPI flash data sheets:
// Cypress S25FL064L http://www.cypress.com/file/316661/download
// Cypress S25FL128L http://www.cypress.com/file/316171/download
//
module spiflash (
input csb,
input clk,
inout io0, // MOSI
inout io1, // MISO
inout io2,
inout io3
);
localparam verbose = 0;
localparam integer latency = 8;
reg [7:0] buffer;
integer bitcount = 0;
integer bytecount = 0;
integer dummycount = 0;
reg [7:0] spi_cmd;
reg [7:0] xip_cmd = 0;
reg [23:0] spi_addr;
reg [7:0] spi_in;
reg [7:0] spi_out;
reg spi_io_vld;
reg powered_up = 0;
localparam [3:0] mode_spi = 1;
localparam [3:0] mode_dspi_rd = 2;
localparam [3:0] mode_dspi_wr = 3;
localparam [3:0] mode_qspi_rd = 4;
localparam [3:0] mode_qspi_wr = 5;
localparam [3:0] mode_qspi_ddr_rd = 6;
localparam [3:0] mode_qspi_ddr_wr = 7;
reg [3:0] mode = 0;
reg [3:0] next_mode = 0;
reg io0_oe = 0;
reg io1_oe = 0;
reg io2_oe = 0;
reg io3_oe = 0;
reg io0_dout = 0;
reg io1_dout = 0;
reg io2_dout = 0;
reg io3_dout = 0;
assign #1 io0 = io0_oe ? io0_dout : 1'bz;
assign #1 io1 = io1_oe ? io1_dout : 1'bz;
assign #1 io2 = io2_oe ? io2_dout : 1'bz;
assign #1 io3 = io3_oe ? io3_dout : 1'bz;
wire io0_delayed;
wire io1_delayed;
wire io2_delayed;
wire io3_delayed;
assign #1 io0_delayed = io0;
assign #1 io1_delayed = io1;
assign #1 io2_delayed = io2;
assign #1 io3_delayed = io3;
// 16 MB (128Mb) Flash
reg [7:0] memory [0:16*1024*1024-1];
reg [1023:0] firmware_file;
initial begin
if (!$value$plusargs("firmware=%s", firmware_file))
firmware_file = "firmware.hex";
$readmemh(firmware_file, memory);
end
task spi_action;
begin
spi_in = buffer;
if (bytecount == 1) begin
spi_cmd = buffer;
if (spi_cmd == 8'h ab)
powered_up = 1;
if (spi_cmd == 8'h b9)
powered_up = 0;
if (spi_cmd == 8'h ff)
xip_cmd = 0;
end
if (powered_up && spi_cmd == 'h 03) begin
if (bytecount == 2)
spi_addr[23:16] = buffer;
if (bytecount == 3)
spi_addr[15:8] = buffer;
if (bytecount == 4)
spi_addr[7:0] = buffer;
if (bytecount >= 4) begin
buffer = memory[spi_addr];
spi_addr = spi_addr + 1;
end
end
if (powered_up && spi_cmd == 'h bb) begin
if (bytecount == 1)
mode = mode_dspi_rd;
if (bytecount == 2)
spi_addr[23:16] = buffer;
if (bytecount == 3)
spi_addr[15:8] = buffer;
if (bytecount == 4)
spi_addr[7:0] = buffer;
if (bytecount == 5) begin
xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
mode = mode_dspi_wr;
dummycount = latency;
end
if (bytecount >= 5) begin
buffer = memory[spi_addr];
spi_addr = spi_addr + 1;
end
end
if (powered_up && spi_cmd == 'h eb) begin
if (bytecount == 1)
mode = mode_qspi_rd;
if (bytecount == 2)
spi_addr[23:16] = buffer;
if (bytecount == 3)
spi_addr[15:8] = buffer;
if (bytecount == 4)
spi_addr[7:0] = buffer;
if (bytecount == 5) begin
xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
mode = mode_qspi_wr;
dummycount = latency;
end
if (bytecount >= 5) begin
buffer = memory[spi_addr];
spi_addr = spi_addr + 1;
end
end
if (powered_up && spi_cmd == 'h ed) begin
if (bytecount == 1)
next_mode = mode_qspi_ddr_rd;
if (bytecount == 2)
spi_addr[23:16] = buffer;
if (bytecount == 3)
spi_addr[15:8] = buffer;
if (bytecount == 4)
spi_addr[7:0] = buffer;
if (bytecount == 5) begin
xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
mode = mode_qspi_ddr_wr;
dummycount = latency;
end
if (bytecount >= 5) begin
buffer = memory[spi_addr];
spi_addr = spi_addr + 1;
end
end
spi_out = buffer;
spi_io_vld = 1;
if (verbose) begin
if (bytecount == 1)
$write("<SPI-START>");
$write("<SPI:%02x:%02x>", spi_in, spi_out);
end
end
endtask
task ddr_rd_edge;
begin
buffer = {buffer, io3_delayed, io2_delayed, io1_delayed, io0_delayed};
bitcount = bitcount + 4;
if (bitcount == 8) begin
bitcount = 0;
bytecount = bytecount + 1;
spi_action;
end
end
endtask
task ddr_wr_edge;
begin
io0_oe = 1;
io1_oe = 1;
io2_oe = 1;
io3_oe = 1;
io0_dout = buffer[4];
io1_dout = buffer[5];
io2_dout = buffer[6];
io3_dout = buffer[7];
buffer = {buffer, 4'h 0};
bitcount = bitcount + 4;
if (bitcount == 8) begin
bitcount = 0;
bytecount = bytecount + 1;
spi_action;
end
end
endtask
always @(csb) begin
if (csb) begin
if (verbose) begin
$display("");
$fflush;
end
buffer = 0;
bitcount = 0;
bytecount = 0;
mode = mode_spi;
io0_oe = 0;
io1_oe = 0;
io2_oe = 0;
io3_oe = 0;
end else
if (xip_cmd) begin
buffer = xip_cmd;
bitcount = 0;
bytecount = 1;
spi_action;
end
end
always @(csb, clk) begin
spi_io_vld = 0;
if (!csb && !clk) begin
if (dummycount > 0) begin
io0_oe = 0;
io1_oe = 0;
io2_oe = 0;
io3_oe = 0;
end else
case (mode)
mode_spi: begin
io0_oe = 0;
io1_oe = 1;
io2_oe = 0;
io3_oe = 0;
io1_dout = buffer[7];
end
mode_dspi_rd: begin
io0_oe = 0;
io1_oe = 0;
io2_oe = 0;
io3_oe = 0;
end
mode_dspi_wr: begin
io0_oe = 1;
io1_oe = 1;
io2_oe = 0;
io3_oe = 0;
io0_dout = buffer[6];
io1_dout = buffer[7];
end
mode_qspi_rd: begin
io0_oe = 0;
io1_oe = 0;
io2_oe = 0;
io3_oe = 0;
end
mode_qspi_wr: begin
io0_oe = 1;
io1_oe = 1;
io2_oe = 1;
io3_oe = 1;
io0_dout = buffer[4];
io1_dout = buffer[5];
io2_dout = buffer[6];
io3_dout = buffer[7];
end
mode_qspi_ddr_rd: begin
ddr_rd_edge;
end
mode_qspi_ddr_wr: begin
ddr_wr_edge;
end
endcase
if (next_mode) begin
case (next_mode)
mode_qspi_ddr_rd: begin
io0_oe = 0;
io1_oe = 0;
io2_oe = 0;
io3_oe = 0;
end
mode_qspi_ddr_wr: begin
io0_oe = 1;
io1_oe = 1;
io2_oe = 1;
io3_oe = 1;
io0_dout = buffer[4];
io1_dout = buffer[5];
io2_dout = buffer[6];
io3_dout = buffer[7];
end
endcase
mode = next_mode;
next_mode = 0;
end
end
end
always @(posedge clk) begin
if (!csb) begin
if (dummycount > 0) begin
dummycount = dummycount - 1;
end else
case (mode)
mode_spi: begin
buffer = {buffer, io0};
bitcount = bitcount + 1;
if (bitcount == 8) begin
bitcount = 0;
bytecount = bytecount + 1;
spi_action;
end
end
mode_dspi_rd, mode_dspi_wr: begin
buffer = {buffer, io1, io0};
bitcount = bitcount + 2;
if (bitcount == 8) begin
bitcount = 0;
bytecount = bytecount + 1;
spi_action;
end
end
mode_qspi_rd, mode_qspi_wr: begin
buffer = {buffer, io3, io2, io1, io0};
bitcount = bitcount + 4;
if (bitcount == 8) begin
bitcount = 0;
bytecount = bytecount + 1;
spi_action;
end
end
mode_qspi_ddr_rd: begin
ddr_rd_edge;
end
mode_qspi_ddr_wr: begin
ddr_wr_edge;
end
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
/*
-- Module Name: West First Minimal
-- Description: Algoritmo parcialmente adaptativo para el calculo de
de ruta en NoCs con topologia Mesh.
El algoritmo esta basado en el "Turn Model". Se puede
encontrar mas informacion en:
The turn model for adaptive routing
Christopher J. Glass
Lionel M. Ni
ProceedingsISCA '92 Proceedings of the 19th annual
international symposium on Computer architecture
Pages 278-287
Forma parte del modulo "Link Controller".
-- Dependencies: -- system.vh
-- Parameters: -- PORT_DIR: Direccion del puerto de entrada
conectado a este modulo {x+, y+
x-, y-}.
-- X_LOCAL: Direccion en dimension "x" del nodo
en la red.
-- Y_LOCAL: Direccion en dimension "y" del nodo
en la red.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
(05/06/2015): Esta es una implementacion modificada del algoritmo
WF. Require modificarse para pasar la alteracion al
modulo wrapper (route_planner.v)
-- History:
-- Creacion 05 de Junio 2015
*/
`include "system.vh"
module dor_xy #(
parameter PORT_DIR = `X_POS,
parameter X_LOCAL = 2,
parameter Y_LOCAL = 2
)
(
// -- inputs --------------------------------------------- >>>>>
input wire done_field_din,
input wire [`ADDR_FIELD-1:0] x_field_din,
input wire [`ADDR_FIELD-1:0] y_field_din,
// -- outputs -------------------------------------------- >>>>>
output reg [3:0] valid_channels_dout
);
/*
-- Calculo de diferencia entre la direccion del nodo actual con la
direccion del nodo objetivo.
Banderas zero_x y zero_y indican que la diferencia es "0" en sus
respectivas dimensiones.
Banderas Xoffset y Yoffset el resultado de la diferencia entre la
direccion actual y la objetivo. Puede ser positiva o negativa.
*/
// -- Dimension X -------------------------------------------- >>>>>
wire Xoffset;
wire zero_x;
assign Xoffset = (x_field_din > X_LOCAL) ? 1'b1 : 1'b0;
assign zero_x = (x_field_din == X_LOCAL) ? 1'b1 : 1'b0;
// -- Dimension Y -------------------------------------------- >>>>>
wire Yoffset;
wire zero_y;
assign Yoffset = (y_field_din > Y_LOCAL) ? 1'b1 : 1'b0;
assign zero_y = (y_field_din == Y_LOCAL) ? 1'b1 : 1'b0;
/*
-- En base a la diferencia de la direccion actual y objetivo, se
selecciona las direcciones de salida que acercan al paquete a su
destino.
Existen 4 casos dependiendo del puerto de entrada ligado al
planificador de ruta. El caso activo se determina con el parametro
PORT_DIR. Solo las asignaciones del caso activo se toman
encuenta al momento de la sintesis.
Para detalles sobre la toma de desiciones del algoritmo consultar el
el paper citado en la cabecera de este archivo.
*/
// -- Seleccion de puertos de salida productivos ----------------- >>>>>
always @(*)
// -- Route Planner :: LC | PE ------------------------------- >>>>>
if (PORT_DIR == `PE)
begin
valid_channels_dout [`PE_YPOS] = (Yoffset) ? 1'b1 : 1'b0;
valid_channels_dout [`PE_YNEG] = (~Yoffset) ? 1'b1 : 1'b0;
valid_channels_dout [`PE_XPOS] = (zero_y & Xoffset) ? 1'b1 : 1'b0;
valid_channels_dout [`PE_XNEG] = (zero_y & ~Xoffset) ? 1'b1 : 1'b0;
end
// -- Route Planner :: LC | X+ ------------------------------- >>>>>
else if(PORT_DIR == `X_POS)
begin
valid_channels_dout [`XPOS_PE] = ~done_field_din;
valid_channels_dout [`XPOS_YPOS] = (Yoffset) ? 1'b1 : 1'b0;
valid_channels_dout [`XPOS_YNEG] = (~Yoffset) ? 1'b1 : 1'b0;
valid_channels_dout [`XPOS_XNEG] = (zero_y & ~Xoffset) ? 1'b1 : 1'b0;
end
// -- Route Planner :: LC | Y+ ------------------------------- >>>>>
else if(PORT_DIR == `Y_POS)
begin
valid_channels_dout [`YPOS_PE] = ~done_field_din;
valid_channels_dout [`YPOS_YNEG] = (~Yoffset) ? 1'b1 : 1'b0;
valid_channels_dout [`YPOS_XPOS] = (zero_y & Xoffset) ? 1'b1 : 1'b0;
valid_channels_dout [`YPOS_XNEG] = (zero_y & ~Xoffset) ? 1'b1 : 1'b0;
end
// -- Route Planner :: LC | X- ------------------------------- >>>>>
else if(PORT_DIR == `X_NEG)
begin
valid_channels_dout [`XNEG_PE] = ~done_field_din;
valid_channels_dout [`XNEG_YPOS] = (Yoffset) ? 1'b1 : 1'b0;
valid_channels_dout [`XNEG_YNEG] = (~Yoffset) ? 1'b1 : 1'b0;
valid_channels_dout [`XNEG_XPOS] = (zero_y & ~Xoffset) ? 1'b1 : 1'b0;
end
// -- Route Planner :: LC | Y- ------------------------------- >>>>>
else if(PORT_DIR == `Y_NEG)
begin
valid_channels_dout [`YNEG_PE] = ~done_field_din;
valid_channels_dout [`YNEG_YPOS] = (Yoffset) ? 1'b1 : 1'b0;
valid_channels_dout [`YNEG_XPOS] = (Yoffset) ? 1'b1 : 1'b0;
valid_channels_dout [`YNEG_XNEG] = (~Yoffset) ? 1'b1 : 1'b0;
end
endmodule // west_first_minimal
/* -- Plantilla de Instancia ------------------------------------- >>>>>
wire [3:0] valid_channels;
mdor_yx
#( .PORT_DIR (PORT_DIR),
.X_LOCAL (X_LOCAL),
.Y_LOCAL (Y_LOCAL)
)
dor_yx
(
// -- inputs --------------------------------------------- >>>>>
.done_field_din (done_field_din),
.x_field_din (x_field_din),
.y_field_din (y_field_din),
// -- outputs -------------------------------------------- >>>>>
.valid_channels_dout (valid_channels)
);
*/ |
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
(* KEEP_HIERARCHY *)
module roi(input clk, input [255:0] din, output [255:0] dout);
clb_a clb_a (.clk(clk), .din(din[ 0 +: 16]), .dout(dout[ 0 +: 16]));
clb_b clb_b (.clk(clk), .din(din[ 16 +: 16]), .dout(dout[ 16 +: 16]));
clb_c clb_c (.clk(clk), .din(din[ 32 +: 16]), .dout(dout[ 32 +: 16]));
clb_d clb_d (.clk(clk), .din(din[ 48 +: 16]), .dout(dout[ 48 +: 16]));
clb_e clb_e (.clk(clk), .din(din[ 64 +: 16]), .dout(dout[ 64 +: 16]));
clb_f clb_f (.clk(clk), .din(din[ 80 +: 16]), .dout(dout[ 80 +: 16]));
clb_g clb_g (.clk(clk), .din(din[ 96 +: 16]), .dout(dout[ 96 +: 16]));
clb_h clb_h (.clk(clk), .din(din[112 +: 16]), .dout(dout[112 +: 16]));
clb_i clb_i (.clk(clk), .din(din[128 +: 16]), .dout(dout[128 +: 16]));
clb_j clb_j (.clk(clk), .din(din[144 +: 16]), .dout(dout[144 +: 16]));
clb_k clb_k (.clk(clk), .din(din[160 +: 16]), .dout(dout[160 +: 16]));
clb_l clb_l (.clk(clk), .din(din[176 +: 16]), .dout(dout[176 +: 16]));
clb_m clb_m (.clk(clk), .din(din[192 +: 16]), .dout(dout[192 +: 16]));
clb_n clb_n (.clk(clk), .din(din[208 +: 16]), .dout(dout[208 +: 16]));
clb_o clb_o (.clk(clk), .din(din[224 +: 16]), .dout(dout[224 +: 16]));
clb_p clb_p (.clk(clk), .din(din[240 +: 16]), .dout(dout[240 +: 16]));
endmodule
// ---------------------------------------------------------------------
module clb_a (input clk, input [15:0] din, output [15:0] dout);
(* LOC="SLICE_X0Y240", BEL="AFF", DONT_TOUCH *)
FDRE ff (
.C(clk),
.Q(dout[0]),
.CE(din[0]),
.R(din[1]),
.D(din[2])
);
assign dout[15:1] = 0;
endmodule
module clb_b (input clk, input [15:0] din, output [15:0] dout);
(* LOC="SLICE_X0Y241", BEL="AFF", DONT_TOUCH *)
FDSE ff (
.C(clk),
.Q(dout[0]),
.CE(din[0]),
.S(din[1]),
.D(din[2])
);
assign dout[15:1] = 0;
endmodule
module clb_c (input clk, input [15:0] din, output [15:0] dout);
(* LOC="SLICE_X0Y242", BEL="AFF", DONT_TOUCH *)
FDCE ff (
.C(clk),
.Q(dout[0]),
.CE(din[0]),
.CLR(din[1]),
.D(din[2])
);
assign dout[15:1] = 0;
endmodule
module clb_d (input clk, input [15:0] din, output [15:0] dout);
(* LOC="SLICE_X0Y243", BEL="AFF", DONT_TOUCH *)
FDPE ff (
.C(clk),
.Q(dout[0]),
.CE(din[0]),
.PRE(din[1]),
.D(din[2])
);
assign dout[15:1] = 0;
endmodule
// ---------------------------------------------------------------------
module clb_e (input clk, input [15:0] din, output [15:0] dout);
wire tmp;
(* LOC="SLICE_X0Y244", BEL="D6LUT", LOCK_PINS="I0:A1", DONT_TOUCH *)
LUT1 #(
.INIT(2'b01)
) lut (
.I0(din[2]),
.O(tmp)
);
(* LOC="SLICE_X0Y244", BEL="BFF", DONT_TOUCH *)
FDRE ff (
.C(clk),
.Q(dout[0]),
.CE(din[0]),
.R(din[1]),
.D(tmp)
);
assign dout[15:1] = 0;
endmodule
module clb_f (input clk, input [15:0] din, output [15:0] dout);
wire tmp;
(* LOC="SLICE_X0Y245", BEL="D5LUT", LOCK_PINS="I0:A1", DONT_TOUCH *)
LUT1 #(
.INIT(2'b01)
) lut (
.I0(din[2]),
.O(tmp)
);
(* LOC="SLICE_X0Y245", BEL="BFF", DONT_TOUCH *)
FDRE ff (
.C(clk),
.Q(dout[0]),
.CE(din[0]),
.R(din[1]),
.D(tmp)
);
assign dout[15:1] = 0;
endmodule
module clb_g (input clk, input [15:0] din, output [15:0] dout);
wire a, b, c;
(* LOC="SLICE_X0Y246", BEL="D6LUT", LOCK_PINS="I0:A1", DONT_TOUCH *)
LUT1 #(
.INIT(2'b01)
) lut (
.I0(din[2]),
.O(a)
);
(* LOC="SLICE_X0Y246", BEL="F7MUX_CD", DONT_TOUCH *)
MUXF7 mux1 (
.I0(a),
.I1(din[3]),
.S(din[4]),
.O(b)
);
(* LOC="SLICE_X0Y246", BEL="F8MUX_BOT", DONT_TOUCH *)
MUXF8 mux2 (
.I0(b),
.I1(din[5]),
.S(din[6]),
.O(c)
);
(* LOC="SLICE_X0Y246", BEL="BFF", DONT_TOUCH *)
FDRE ff (
.C(clk),
.Q(dout[0]),
.CE(din[0]),
.R(din[1]),
.D(c)
);
assign dout[15:1] = 0;
endmodule
module clb_h (input clk, input [15:0] din, output [15:0] dout);
wire a, b, c;
(* LOC="SLICE_X0Y247", BEL="D5LUT", LOCK_PINS="I0:A1", DONT_TOUCH *)
LUT1 #(
.INIT(2'b01)
) lut (
.I0(din[2]),
.O(a)
);
(* LOC="SLICE_X0Y247", BEL="F7MUX_CD", DONT_TOUCH *)
MUXF7 mux1 (
.I0(a),
.I1(din[3]),
.S(din[4]),
.O(b)
);
(* LOC="SLICE_X0Y247", BEL="F8MUX_BOT", DONT_TOUCH *)
MUXF8 mux2 (
.I0(b),
.I1(din[5]),
.S(din[6]),
.O(c)
);
(* LOC="SLICE_X0Y247", BEL="BFF", DONT_TOUCH *)
FDRE ff (
.C(clk),
.Q(dout[0]),
.CE(din[0]),
.R(din[1]),
.D(c)
);
assign dout[15:1] = 0;
endmodule
// ---------------------------------------------------------------------
module clb_i (input clk, input [15:0] din, output [15:0] dout);
assign dout = 0;
endmodule
module clb_j (input clk, input [15:0] din, output [15:0] dout);
assign dout = 0;
endmodule
module clb_k (input clk, input [15:0] din, output [15:0] dout);
assign dout = 0;
endmodule
module clb_l (input clk, input [15:0] din, output [15:0] dout);
assign dout = 0;
endmodule
module clb_m (input clk, input [15:0] din, output [15:0] dout);
assign dout = 0;
endmodule
module clb_n (input clk, input [15:0] din, output [15:0] dout);
assign dout = 0;
endmodule
module clb_o (input clk, input [15:0] din, output [15:0] dout);
assign dout = 0;
endmodule
module clb_p (input clk, input [15:0] din, output [15:0] dout);
assign dout = 0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3B_4_V
`define SKY130_FD_SC_LS__OR3B_4_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or3b_4 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or3b_4 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3B_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22OI_2_V
`define SKY130_FD_SC_HS__A22OI_2_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a22oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a22oi_2 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22OI_2_V
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: RAM16_s36_s36_altera.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module RAM16_s36_s36_altera (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [9:0] address_a;
input [9:0] address_b;
input clock_a;
input clock_b;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "5"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
// Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
// Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]"
// Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
// Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
// Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
// Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_wave*.jpg TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_syn.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
module cache_test();
reg clk;
reg re, we, we2, we3;
reg [31:0] address, writedata;
wire [31:0] readdatacache;
wire hit, miss, dirty;
// test
memory_system DUT(clk, re, we, we2, we3, address, writedata, readdatacache, hit, miss, dirty);
// generate clock to sequence tests
always begin
clk <= 1;
#5;
clk <= 0;
# 5;
end
// check results
initial begin
re <= 1'b0;
we <= 1'b0;
we2 <=1'b0;
we3 <= 1'b0;
address <= 32'h0;
writedata <= 32'b0;
#10;
// Write Hit: if in cache, write in cache
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h50;
writedata <= 32'h7;
#10;
we <= 1'b0;
#10;
// Read Hit: Hit generated, no need to go to main memory, read out of cache valid
re <= 1'b1;
we <= 1'b0;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h50;
writedata <= 32'hxxxxxxxx;
#10;
re <= 1'b0;
#10;
// Write Hit: if in cache, write in cache
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h54;
writedata <= 32'h7;
#10;
we <= 1'b0;
#200;
/*
// Write Miss: Miss generated, gets main memory, write this data to this cache value
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00001006;
writedata <= 32'h12345678;
#10;
we <= 1'b0;
#200;
we2 <= 1'b1;
#5;
we2 <= 1'b0;
#5;
// Read Hit: Hit generated, no need to go to main memory, read out of cache valid
re <= 1'b1;
we <= 1'b0;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00001006;
writedata <= 32'hxxxxxxxx;
#10;
re <= 1'b0;
#10;
// Read Miss: !Hit generated, gets main memory, read out of cache is initialized mainmemory value after writing new cache value
re <= 1'b1;
we <= 1'b0;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00002006;
writedata <= 32'hxxxxxxxx;
#10;
re <= 1'b0;
#200;
we3 <= 1'b1;
#10;
we3 <= 1'b0;
#20;
// Write Hit: if in cache, write in cache
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00002005;
writedata <= 32'h87654321;
#10;
we <= 1'b0;
#200;
*/
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S4S_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DLYMETAL6S4S_PP_SYMBOL_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlymetal6s4s (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S4S_PP_SYMBOL_V
|
`timescale 1ns/1ps
module tester(
output reg clk,
output reg [7:0] data
);
initial
begin
clk <= 1;
repeat (100000000)
begin
#1 clk = ~clk ;
end
end
reg [7:0] datas [0:32];
initial
begin
datas[0] = 8'h0A;
datas[1] = 8'h1A;
datas[2] = 8'h2A;
datas[3] = 8'h3A;
datas[4] = 8'h4A;
datas[5] = 8'h5A;
datas[6] = 8'h6A;
datas[7] = 8'h7A;
datas[8] = 8'h8A;
datas[9] = 8'h9B;
datas[10] = 8'h0B;
datas[11] = 8'h1B;
datas[12] = 8'h2B;
datas[13] = 8'h3B;
datas[14] = 8'h4B;
datas[15] = 8'h5B;
datas[16] = 8'h6B;
datas[17] = 8'h7B;
datas[18] = 8'h9B;
datas[19] = 8'h1C;
datas[20] = 8'h2C;
datas[21] = 8'h3C;
datas[22] = 8'h4C;
datas[23] = 8'h5C;
datas[24] = 8'h6C;
datas[25] = 8'h7C;
datas[26] = 8'h8C;
datas[27] = 8'h9C;
datas[28] = 8'h1D;
datas[29] = 8'h2D;
datas[30] = 8'h3D;
datas[31] = 8'h4D;
end
initial
begin
data <= datas[0];
data <= datas[1];
data <= datas[2];
data <= datas[3];
data <= datas[4];
data <= datas[5];
data <= datas[6];
data <= datas[7];
data <= datas[8];
data <= datas[9];
data <= datas[10];
data <= datas[11];
data <= datas[12];
data <= datas[13];
data <= datas[14];
data <= datas[15];
data <= datas[16];
data <= datas[17];
data <= datas[18];
data <= datas[19];
data <= datas[20];
data <= datas[21];
data <= datas[22];
data <= datas[23];
data <= datas[24];
data <= datas[25];
data <= datas[26];
data <= datas[27];
data <= datas[28];
data <= datas[29];
data <= datas[30];
data <= datas[31];
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFSTP_BLACKBOX_V
`define SKY130_FD_SC_LP__SRSDFSTP_BLACKBOX_V
/**
* srsdfstp: Scan flop with sleep mode, inverted set, non-inverted
* clock, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srsdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B ,
SLEEP_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B ;
input SLEEP_B;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFSTP_BLACKBOX_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's DC TAG RAMs ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instatiation of data cache tag rams. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dc_tag.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.5 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.4 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.2.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_dc_tag(
// Clock and reset
clk, rst,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Internal i/f
addr, en, we, datain, tag_v, tag
);
parameter dw = `OR1200_DCTAG_W;
parameter aw = `OR1200_DCTAG;
//
// I/O
//
input clk;
input rst;
input [aw-1:0] addr;
input en;
input we;
input [dw-1:0] datain;
output tag_v;
output [dw-2:0] tag;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
`ifdef OR1200_NO_DC
//
// Data cache not implemented
//
assign tag = {dw-1{1'b0}};
assign tag_v = 1'b0;
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// Instantiation of TAG RAM block
//
`ifdef OR1200_DC_1W_4KB
or1200_spram_256x21 dc_tag0(
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram_512x20 dc_tag0(
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
.ce(en),
.we(we),
.oe(1'b1),
.addr(addr),
.di(datain),
.doq({tag, tag_v})
);
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A32OI_1_V
`define SKY130_FD_SC_HD__A32OI_1_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a32oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a32oi_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a32oi_1 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A32OI_1_V
|
//****************************************************************************************************
//*---------------Copyright (c) 2016 C-L-G.FPGA1988.lichangbeiju. All rights reserved-----------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : chip_top.v
//Project Name : azpr_soc
//Description : the digital top of the chip.
//Github Address : github.com/C-L-G/azpr_soc/trunk/ic/digital/rtl/chip.v
//License : Apache-2.0
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 2016-11-22 17:00
//First Author : lichangbeiju
//Last Modify : 2016-11-23 14:20
//Last Author : lichangbeiju
//Version Number : 12 commits
//****************************************************************************************************
//Change History(latest change first)
//yyyy.mm.dd - Author - Your log of change
//****************************************************************************************************
//2016.12.08 - lichangbeiju - Change the include.
//2016.11.23 - lichangbeiju - Change the coding style.
//2016.11.22 - lichangbeiju - Add io port.
//****************************************************************************************************
`include "../sys_include.h"
`include "isa.h"
`include "cpu.h"
module id_stage (
input wire clk,
input wire reset,
input wire [`WordDataBus] gpr_rd_data_0,
input wire [`WordDataBus] gpr_rd_data_1,
output wire [`RegAddrBus] gpr_rd_addr_0,
output wire [`RegAddrBus] gpr_rd_addr_1,
input wire ex_en,
input wire [`WordDataBus] ex_fwd_data,
input wire [`RegAddrBus] ex_dst_addr,
input wire ex_gpr_we_n,
input wire [`WordDataBus] mem_fwd_data,
input wire [`CpuExeModeBus] exe_mode,
input wire [`WordDataBus] creg_rd_data,
output wire [`RegAddrBus] creg_rd_addr,
input wire stall,
input wire flush,
output wire [`WordAddrBus] br_addr,
output wire br_taken,
output wire ld_hazard,
input wire [`WordAddrBus] if_pc,
input wire [`WordDataBus] if_insn,
input wire if_en,
output wire [`WordAddrBus] id_pc,
output wire id_en,
output wire [`AluOpBus] id_alu_op,
output wire [`WordDataBus] id_alu_in_0,
output wire [`WordDataBus] id_alu_in_1,
output wire id_br_flag,
output wire [`MemOpBus] id_mem_op,
output wire [`WordDataBus] id_mem_wr_data,
output wire [`CtrlOpBus] id_ctrl_op,
output wire [`RegAddrBus] id_dst_addr,
output wire id_gpr_we_n,
output wire [`IsaExpBus] id_exp_code
);
wire [`AluOpBus] alu_op;
wire [`WordDataBus] alu_in_0;
wire [`WordDataBus] alu_in_1;
wire br_flag;
wire [`MemOpBus] mem_op;
wire [`WordDataBus] mem_wr_data;
wire [`CtrlOpBus] ctrl_op;
wire [`RegAddrBus] dst_addr;
wire gpr_we_n;
wire [`IsaExpBus] exp_code;
decoder decoder (
.if_pc (if_pc ),
.if_insn (if_insn ),
.if_en (if_en ),
.gpr_rd_data_0 (gpr_rd_data_0),
.gpr_rd_data_1 (gpr_rd_data_1),
.gpr_rd_addr_0 (gpr_rd_addr_0),
.gpr_rd_addr_1 (gpr_rd_addr_1),
.id_en (id_en),
.id_dst_addr (id_dst_addr),
.id_gpr_we_n (id_gpr_we_n),
.id_mem_op (id_mem_op),
.ex_en (ex_en),
.ex_fwd_data (ex_fwd_data),
.ex_dst_addr (ex_dst_addr),
.ex_gpr_we_n (ex_gpr_we_n),
.mem_fwd_data (mem_fwd_data),
.exe_mode (exe_mode),
.creg_rd_data (creg_rd_data),
.creg_rd_addr (creg_rd_addr),
.alu_op (alu_op),
.alu_in_0 (alu_in_0),
.alu_in_1 (alu_in_1),
.br_addr (br_addr),
.br_taken (br_taken),
.br_flag (br_flag),
.mem_op (mem_op),
.mem_wr_data (mem_wr_data),
.ctrl_op (ctrl_op),
.dst_addr (dst_addr),
.gpr_we_n (gpr_we_n),
.exp_code (exp_code),
.ld_hazard (ld_hazard)
);
id_reg id_reg (
.clk (clk),
.reset (reset),
.alu_op (alu_op),
.alu_in_0 (alu_in_0),
.alu_in_1 (alu_in_1),
.br_flag (br_flag),
.mem_op (mem_op),
.mem_wr_data (mem_wr_data),
.ctrl_op (ctrl_op),
.dst_addr (dst_addr),
.gpr_we_n (gpr_we_n),
.exp_code (exp_code),
.stall (stall),
.flush (flush),
.if_pc (if_pc),
.if_en (if_en),
.id_pc (id_pc),
.id_en (id_en),
.id_alu_op (id_alu_op),
.id_alu_in_0 (id_alu_in_0),
.id_alu_in_1 (id_alu_in_1),
.id_br_flag (id_br_flag),
.id_mem_op (id_mem_op),
.id_mem_wr_data (id_mem_wr_data),
.id_ctrl_op (id_ctrl_op),
.id_dst_addr (id_dst_addr),
.id_gpr_we_n (id_gpr_we_n),
.id_exp_code (id_exp_code)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAH_PP_SYMBOL_V
`define SKY130_FD_SC_LS__FAH_PP_SYMBOL_V
/**
* fah: Full adder.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fah (
//# {{data|Data Signals}}
input A ,
input B ,
input CI ,
output COUT,
output SUM ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAH_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND2_PP_SYMBOL_V
`define SKY130_FD_SC_HD__NAND2_PP_SYMBOL_V
/**
* nand2: 2-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND2_PP_SYMBOL_V
|
/**
* bsg_lru_pseudo_tree_backup.v
*
* tree pseudo LRU backup finder.
*
* Given the bit vector of disabled ways, it will tell
* you bit-mask and data to modify the original LRU bits to obtain
* the backup LRU.
*
* The algorithm to find backup_LRU is:
* start from the root of the LRU tree, and traverse down the tree in the
* direction of the LRU bits, if there is at least one unlocked way in that
* direction. If not, take the opposite direction.
*
*
* ==== Example ==============================================
*
* rank=0 [0]
* 0
* / \
* rank=1 [1] [2]
* 1 0
* / \ / \
* rank=2 [3] [4] [5] [6]
* 1 0 1 1
* / \ / \ / \ / \
* way w0 w1 w2 w3 w4 w5 w6 w7
*
*
* Let say LRU bits were 7'b110_1010 so that LRU way is w2.
* If the disabled ways are {w2}, then backup_LRU = w3.
* If the disabled are {w2,w3}, then backup_LRU = w1
* If the disabled are {w0,w1,w2,w3}, the backup_LRU = w5.
*
* ============================================================
*
* @author tommy
*
*
*/
`include "bsg_defines.v"
module bsg_lru_pseudo_tree_backup
#(parameter `BSG_INV_PARAM(ways_p)
, parameter lg_ways_lp=`BSG_SAFE_CLOG2(ways_p)
)
(
input [ways_p-1:0] disabled_ways_i
, output logic [`BSG_SAFE_MINUS(ways_p, 2):0] modify_mask_o
, output logic [`BSG_SAFE_MINUS(ways_p, 2):0] modify_data_o
);
// If direct-mapped there is no meaning to backup LRU
if (ways_p == 1) begin: no_lru
assign modify_mask_o = 1'b1;
assign modify_data_o = 1'b0;
end
else begin: lru
// backup LRU logic
// i = rank
for (genvar i = 0; i < lg_ways_lp; i++) begin
logic [(2**(i+1))-1:0] and_reduce;
// j = bucket
for (genvar j = 0; j < (2**(i+1)); j++)
assign and_reduce[j] = &disabled_ways_i[(ways_p/(2**(i+1)))*j+:(ways_p/(2**(i+1)))];
// k = start index in LRU bits
for (genvar k = 0; k < (2**(i+1))/2; k++) begin
assign modify_data_o[(2**i)-1+k] = and_reduce[2*k];
assign modify_mask_o[(2**i)-1+k] = |and_reduce[2*k+:2];
end
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_lru_pseudo_tree_backup)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2_BEHAVIORAL_V
`define SKY130_FD_SC_HS__NOR2_BEHAVIORAL_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor2 (
Y ,
A ,
B ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
// Local signals
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2_BEHAVIORAL_V |
// Gris InterConnect slave
// This module acts as a Wishbone master and receives operations from
// the GIC Master which acts as a Wishbone slave.
module gic_slave #(
parameter idle = 4'b1111
) (
output [31:0] wbm_adr_o,
output wbm_stb_o,
output wbm_cyc_o,
output [3:0] wbm_sel_o,
output wbm_we_o,
output [2:0] wbm_cti_o,
output [1:0] wbm_bte_o,
output [31:0] wbm_dat_o,
input wbm_err_i,
input wbm_ack_i,
input [31:0] wbm_dat_i,
input wbm_rty_i,
input wbm_clk_i,
input wbm_rst_i,
input [3:0] gic_dat_i,
output [3:0] gic_dat_o
);
localparam master_initiate = 4'b1010;
localparam slave_initiate = 4'b0101;
localparam state_m_init = 0;
localparam state_m_cmd = 1;
localparam state_m_sel = 2;
localparam state_m_adr = 3;
localparam state_m_dat = 4;
localparam state_m_cksum = 5;
localparam state_s_init = 6;
localparam state_s_resp = 7;
localparam state_s_dat = 8;
localparam state_s_cksum = 9;
reg [3:0] state_r = state_m_init;
reg [3:0] next_state_r = state_m_init;
reg [2:0] cntr_r = 0;
reg [3:0] gic_dat_r = 0;
reg [3:0] gic_chksum_r = 0;
reg data_correct_r = 1'b0;
reg wb_we_r = 1'b0;
reg [31:0] wb_adr_r = 0;
reg [31:0] wb_dat_r = 0;
reg [31:0] wbm_dat_r = 0;
reg [3:0] wb_sel_r = 0;
reg wb_cycle_r = 1'b0;
// We invert part of last checksum to make the bus cycle
// with all 1/0's invalid.
wire [3:0] chksum_operand = (cntr_r == 0) ? 4'b1100 : 4'b0000;
assign wbm_adr_o = wb_adr_r;
assign wbm_dat_o = wb_dat_r;
assign wbm_we_o = wb_we_r;
assign wbm_stb_o = wb_cycle_r & data_correct_r;
assign wbm_cyc_o = wb_cycle_r & data_correct_r;
assign wbm_sel_o = wb_sel_r;
assign wbm_cti_o = 3'b000; // We only support classic cycles
assign wbm_cti_o = 3'b000;
assign wbm_bte_o = 2'b00;
wire cycle_complete = wbm_ack_i | wbm_err_i | wbm_rty_i;
assign gic_dat_o = gic_dat_r;
// Mealy FSM
always @(posedge wbm_clk_i)
begin
if (wbm_rst_i) begin
state_r <= state_m_init;
end else begin
state_r <= next_state_r;
end
end
// Data/address position counter
always @(posedge wbm_clk_i)
begin
if (wbm_rst_i) begin
cntr_r <= 7;
end else begin
cntr_r <= 7;
if ((state_r == state_m_adr) | (state_r == state_m_dat) |
(state_r == state_s_dat)) begin
// Since we're in each of the above states for 8 cycles we will
// overflow and up at 7 again, so the transition from m_adr -> m_dat.
cntr_r <= cntr_r - 1;
end
end
end
// Checksum calculator
always @(posedge wbm_clk_i)
begin
gic_chksum_r <= gic_chksum_r;
case (state_r)
state_m_sel:
gic_chksum_r <= gic_dat_i;
state_m_adr | state_m_dat:
gic_chksum_r <= gic_chksum_r ^ gic_dat_i ^ chksum_operand;
state_s_resp:
gic_chksum_r <= 0;
state_s_dat:
gic_chksum_r <= gic_chksum_r ^ wbm_dat_r[cntr_r*4+:4] ^ chksum_operand;
endcase
end
// Checksum validator
always @(state_r)
begin
data_correct_r <= 1'b1;
// TODO(bluecmd)
end
// GIC Data driver
always @(state_r or cntr_r or cycle_complete)
begin
gic_dat_r <= idle;
case (state_r)
state_s_init:
if (cycle_complete)
gic_dat_r <= slave_initiate;
state_s_resp:
gic_dat_r <= 4'bxxxx;
state_s_dat:
gic_dat_r <= wbm_dat_r[cntr_r*4+:4];
state_s_cksum:
gic_dat_r <= gic_chksum_r;
endcase
end
// Wishbone driver
always @(posedge wbm_clk_i)
begin
wb_adr_r <= wb_adr_r;
wb_dat_r <= wb_dat_r;
wb_sel_r <= wb_sel_r;
wb_cycle_r <= wb_cycle_r;
wb_we_r <= wb_we_r;
case (state_r)
state_m_cmd:
wb_we_r <= gic_dat_i[3];
state_m_sel:
wb_sel_r <= gic_dat_i;
state_m_adr:
wb_adr_r[cntr_r*4+:4] <= gic_dat_i;
state_m_dat:
wb_dat_r[cntr_r*4+:4] <= gic_dat_i;
state_m_cksum:
wb_cycle_r <= 1'b1;
state_s_init:
wb_cycle_r <= ~cycle_complete;
endcase
end
// Wishbone input capture
always @(posedge wbm_clk_i)
begin
wbm_dat_r <= wbm_dat_r;
case (state_r)
state_s_init:
if (cycle_complete)
wbm_dat_r <= wbm_dat_i;
endcase
end
always @(state_r or cntr_r or cycle_complete)
begin
next_state_r <= state_r;
case (state_r)
state_m_init:
if (gic_dat_i == master_initiate)
next_state_r <= state_m_cmd;
state_m_cmd:
next_state_r <= state_m_sel;
state_m_sel:
next_state_r <= state_m_adr;
state_m_adr:
if (cntr_r == 0)
next_state_r <= wb_we_r ? state_m_dat : state_m_cksum;
state_m_dat:
if (cntr_r == 0)
next_state_r <= state_m_cksum;
state_m_cksum:
next_state_r <= state_s_init;
state_s_init:
if (cycle_complete)
next_state_r <= state_s_resp;
state_s_resp:
next_state_r <= wb_we_r ? state_m_init : state_s_dat;
state_s_dat:
if (cntr_r == 0)
next_state_r <= state_s_cksum;
state_s_cksum:
next_state_r <= state_m_init;
endcase
end
`ifdef DEBUG_GIC_SLAVE
always @(posedge wbm_clk_i)
begin
if (cycle_complete & (state_r == state_s_init)) begin
$display("Finished wishbone cycle: 0x%08x", wb_adr_r);
$display("Data returned: 0x%08x", wbm_dat_i);
$display("Status: ACK %b ERR %b RTY %b", wbm_ack_i, wbm_err_i, wbm_rty_i);
end else if (state_r == state_s_dat) begin
$display("Checksum: %4b", gic_chksum_r);
end else if (state_r == state_s_cksum) begin
$display("Final Checksum: %4b", gic_chksum_r);
end
end
`endif
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIEBus_pipe_drp.v
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : pipe_drp.v
// Description : PIPE DRP Module for 7 Series Transceiver
// Version : 20.0
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE DRP Module ---------------------------------------------------
module PCIEBus_pipe_drp #
(
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_AUX_CDR_GEN3_EN = "TRUE", // PCIe AUX CDR Gen3 enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
parameter LOAD_CNT_MAX = 2'd1, // Load max count
parameter INDEX_MAX = 5'd21 // Index max count
)
(
//---------- Input -------------------------------------
input DRP_CLK,
input DRP_RST_N,
input DRP_GTXRESET,
input [ 1:0] DRP_RATE,
input DRP_X16X20_MODE,
input DRP_X16,
input DRP_START,
input [15:0] DRP_DO,
input DRP_RDY,
//---------- Output ------------------------------------
output [ 8:0] DRP_ADDR,
output DRP_EN,
output [15:0] DRP_DI,
output DRP_WE,
output DRP_DONE,
output [ 2:0] DRP_FSM
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gtxreset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16x20_mode_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gtxreset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16x20_mode_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg2;
//---------- Internal Signals --------------------------
reg [ 1:0] load_cnt = 2'd0;
reg [ 4:0] index = 5'd0;
reg mode = 1'd0;
reg [ 8:0] addr_reg = 9'd0;
reg [15:0] di_reg = 16'd0;
//---------- Output Registers --------------------------
reg done = 1'd0;
reg [ 2:0] fsm = 0;
//---------- DRP Address -------------------------------
// DRP access for *RXCDR_EIDLE includes
// - [11] RXCDR_HOLD_DURING_EIDLE
// - [12] RXCDR_FR_RESET_ON_EIDLE
// - [13] RXCDR_PH_RESET_ON_EIDLE
//------------------------------------------------------
localparam ADDR_PCS_RSVD_ATTR = 9'h06F;
localparam ADDR_TXOUT_DIV = 9'h088;
localparam ADDR_RXOUT_DIV = 9'h088;
localparam ADDR_TX_DATA_WIDTH = 9'h06B;
localparam ADDR_TX_INT_DATAWIDTH = 9'h06B;
localparam ADDR_RX_DATA_WIDTH = 9'h011;
localparam ADDR_RX_INT_DATAWIDTH = 9'h011;
localparam ADDR_TXBUF_EN = 9'h01C;
localparam ADDR_RXBUF_EN = 9'h09D;
localparam ADDR_TX_XCLK_SEL = 9'h059;
localparam ADDR_RX_XCLK_SEL = 9'h059;
localparam ADDR_CLK_CORRECT_USE = 9'h044;
localparam ADDR_TX_DRIVE_MODE = 9'h019;
localparam ADDR_RXCDR_EIDLE = 9'h0A7;
localparam ADDR_RX_DFE_LPM_EIDLE = 9'h01E;
localparam ADDR_PMA_RSV_A = 9'h099;
localparam ADDR_PMA_RSV_B = 9'h09A;
localparam ADDR_RXCDR_CFG_A = 9'h0A8;
localparam ADDR_RXCDR_CFG_B = 9'h0A9;
localparam ADDR_RXCDR_CFG_C = 9'h0AA;
localparam ADDR_RXCDR_CFG_D = 9'h0AB;
localparam ADDR_RXCDR_CFG_E = 9'h0AC;
localparam ADDR_RXCDR_CFG_F = 9'h0AD; // GTH only
//---------- DRP Mask ----------------------------------
localparam MASK_PCS_RSVD_ATTR = 16'b1111111111111001; // Unmask bit [ 2: 1]
localparam MASK_TXOUT_DIV = 16'b1111111110001111; // Unmask bit [ 6: 4]
localparam MASK_RXOUT_DIV = 16'b1111111111111000; // Unmask bit [ 2: 0]
localparam MASK_TX_DATA_WIDTH = 16'b1111111111111000; // Unmask bit [ 2: 0]
localparam MASK_TX_INT_DATAWIDTH = 16'b1111111111101111; // Unmask bit [ 4]
localparam MASK_RX_DATA_WIDTH = 16'b1100011111111111; // Unmask bit [13:11]
localparam MASK_X16X20_RX_DATA_WIDTH = 16'b1111011111111111; // Unmask bit [ 11] // for x16 or x20 mode only
localparam MASK_RX_INT_DATAWIDTH = 16'b1011111111111111; // Unmask bit [ 14]
localparam MASK_TXBUF_EN = 16'b1011111111111111; // Unmask bit [ 14]
localparam MASK_RXBUF_EN = 16'b1111111111111101; // Unmask bit [ 1]
localparam MASK_TX_XCLK_SEL = 16'b1111111101111111; // Unmask bit [ 7]
localparam MASK_RX_XCLK_SEL = 16'b1111111110111111; // Unmask bit [ 6]
localparam MASK_CLK_CORRECT_USE = 16'b1011111111111111; // Unmask bit [ 14]
localparam MASK_TX_DRIVE_MODE = 16'b1111111111100000; // Unmask bit [ 4:0]
localparam MASK_RXCDR_EIDLE = 16'b1111011111111111; // Unmask bit [ 11]
localparam MASK_RX_DFE_LPM_EIDLE = 16'b1011111111111111; // Unmask bit [ 14]
localparam MASK_PMA_RSV_A = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_PMA_RSV_B = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_A = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_B = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_C = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_D = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_E_GTX = 16'b1111111100000000; // Unmask bit [ 7: 0]
localparam MASK_RXCDR_CFG_E_GTH = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_F_GTX = 16'b1111111111111111; // Unmask bit [ ]
localparam MASK_RXCDR_CFG_F_GTH = 16'b1111111111111000; // Unmask bit [ 2: 0]
//---------- DRP Data for PCIe Gen1 and Gen2 -----------
localparam GEN12_TXOUT_DIV = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000100000 : 16'b0000000000010000; // Divide by 4 or 2
localparam GEN12_RXOUT_DIV = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000000010 : 16'b0000000000000001; // Divide by 4 or 2
localparam GEN12_TX_DATA_WIDTH = 16'b0000000000000011; // 2-byte (16-bit) external data width
localparam GEN12_TX_INT_DATAWIDTH = 16'b0000000000000000; // 2-byte (20-bit) internal data width
localparam GEN12_RX_DATA_WIDTH = 16'b0001100000000000; // 2-byte (16-bit) external data width
localparam GEN12_RX_INT_DATAWIDTH = 16'b0000000000000000; // 2-byte (20-bit) internal data width
localparam GEN12_TXBUF_EN = 16'b0100000000000000; // Use TX buffer if PCIE_TXBUF_EN == "TRUE"
localparam GEN12_RXBUF_EN = 16'b0000000000000010; // Use RX buffer
localparam GEN12_TX_XCLK_SEL = 16'b0000000000000000; // Use TXOUT if PCIE_TXBUF_EN == "TRUE"
localparam GEN12_RX_XCLK_SEL = 16'b0000000000000000; // Use RXREC
localparam GEN12_CLK_CORRECT_USE = 16'b0100000000000000; // Use clock correction
localparam GEN12_TX_DRIVE_MODE = 16'b0000000000000001; // Use PIPE Gen1 and Gen2 mode
localparam GEN12_RXCDR_EIDLE = 16'b0000100000000000; // Hold RXCDR during electrical idle
localparam GEN12_RX_DFE_LPM_EIDLE = 16'b0100000000000000; // Hold RX DFE or LPM during electrical idle
localparam GEN12_PMA_RSV_A_GTX = 16'b1000010010000000; // 16'h8480
localparam GEN12_PMA_RSV_B_GTX = 16'b0000000000000001; // 16'h0001
localparam GEN12_PMA_RSV_A_GTH = 16'b0000000000001000; // 16'h0008
localparam GEN12_PMA_RSV_B_GTH = 16'b0000000000000000; // 16'h0000
//----------
localparam GEN12_RXCDR_CFG_A_GTX = 16'h0020; // 16'h0020
localparam GEN12_RXCDR_CFG_B_GTX = 16'h1020; // 16'h1020
localparam GEN12_RXCDR_CFG_C_GTX = 16'h23FF; // 16'h23FF
localparam GEN12_RXCDR_CFG_D_GTX_S = 16'h0000; // 16'h0000 Sync
localparam GEN12_RXCDR_CFG_D_GTX_A = 16'h8000; // 16'h8000 Async
localparam GEN12_RXCDR_CFG_E_GTX = 16'h0003; // 16'h0003
localparam GEN12_RXCDR_CFG_F_GTX = 16'h0000; // 16'h0000
//----------
localparam GEN12_RXCDR_CFG_A_GTH_S = 16'h0018; // 16'h0018 Sync
localparam GEN12_RXCDR_CFG_A_GTH_A = 16'h8018; // 16'h8018 Async
localparam GEN12_RXCDR_CFG_B_GTH = 16'hC208; // 16'hC208
localparam GEN12_RXCDR_CFG_C_GTH = 16'h2000; // 16'h2000
localparam GEN12_RXCDR_CFG_D_GTH = 16'h07FE; // 16'h07FE
localparam GEN12_RXCDR_CFG_E_GTH = 16'h0020; // 16'h0020
localparam GEN12_RXCDR_CFG_F_GTH = 16'h0000; // 16'h0000
//---------- DRP Data for PCIe Gen3 --------------------
localparam GEN3_TXOUT_DIV = 16'b0000000000000000; // Divide by 1
localparam GEN3_RXOUT_DIV = 16'b0000000000000000; // Divide by 1
localparam GEN3_TX_DATA_WIDTH = 16'b0000000000000100; // 4-byte (32-bit) external data width
localparam GEN3_TX_INT_DATAWIDTH = 16'b0000000000010000; // 4-byte (32-bit) internal data width
localparam GEN3_RX_DATA_WIDTH = 16'b0010000000000000; // 4-byte (32-bit) external data width
localparam GEN3_RX_INT_DATAWIDTH = 16'b0100000000000000; // 4-byte (32-bit) internal data width
localparam GEN3_TXBUF_EN = 16'b0000000000000000; // Bypass TX buffer
localparam GEN3_RXBUF_EN = 16'b0000000000000000; // Bypass RX buffer
localparam GEN3_TX_XCLK_SEL = 16'b0000000010000000; // Use TXUSR
localparam GEN3_RX_XCLK_SEL = 16'b0000000001000000; // Use RXUSR
localparam GEN3_CLK_CORRECT_USE = 16'b0000000000000000; // Bypass clock correction
localparam GEN3_TX_DRIVE_MODE = 16'b0000000000000010; // Use PIPE Gen3 mode
localparam GEN3_RXCDR_EIDLE = 16'b0000000000000000; // Disable Hold RXCDR during electrical idle
localparam GEN3_RX_DFE_LPM_EIDLE = 16'b0000000000000000; // Disable RX DFE or LPM during electrical idle
localparam GEN3_PMA_RSV_A_GTX = 16'b0111000010000000; // 16'h7080
localparam GEN3_PMA_RSV_B_GTX = 16'b0000000000011110; // 16'h001E
localparam GEN3_PMA_RSV_A_GTH = 16'b0000000000001000; // 16'h0008
localparam GEN3_PMA_RSV_B_GTH = 16'b0000000000000000; // 16'h0000
//----------
localparam GEN3_RXCDR_CFG_A_GTX = 16'h0080; // 16'h0080
localparam GEN3_RXCDR_CFG_B_GTX = 16'h1010; // 16'h1010
localparam GEN3_RXCDR_CFG_C_GTX = 16'h0BFF; // 16'h0BFF
localparam GEN3_RXCDR_CFG_D_GTX_S = 16'h0000; // 16'h0000 Sync
localparam GEN3_RXCDR_CFG_D_GTX_A = 16'h8000; // 16'h8000 Async
localparam GEN3_RXCDR_CFG_E_GTX = 16'h000B; // 16'h000B
localparam GEN3_RXCDR_CFG_F_GTX = 16'h0000; // 16'h0000
//----------
//localparam GEN3_RXCDR_CFG_A_GTH_S = 16'h0018; // 16'h0018 Sync
//localparam GEN3_RXCDR_CFG_A_GTH_A = 16'h8018; // 16'h8018 Async
//localparam GEN3_RXCDR_CFG_B_GTH = 16'hC208; // 16'hC848
//localparam GEN3_RXCDR_CFG_C_GTH = 16'h2000; // 16'h1000
//localparam GEN3_RXCDR_CFG_D_GTH = 16'h07FE; // 16'h07FE v1.0 silicon
//localparam GEN3_RXCDR_CFG_D_GTH_AUX = 16'h0FFE; // 16'h07FE v2.0 silicon, [62:59] AUX CDR configuration
//localparam GEN3_RXCDR_CFG_E_GTH = 16'h0020; // 16'h0010
//localparam GEN3_RXCDR_CFG_F_GTH = 16'h0000; // 16'h0000 v1.0 silicon
//localparam GEN3_RXCDR_CFG_F_GTH_AUX = 16'h0002; // 16'h0000 v2.0 silicon, [81] AUX CDR enable
//----------
localparam GEN3_RXCDR_CFG_A_GTH_S = 16'h0018; // 16'h0018 Sync
localparam GEN3_RXCDR_CFG_A_GTH_A = 16'h8018; // 16'h8018 Async
localparam GEN3_RXCDR_CFG_B_GTH = 16'hC848; // 16'hC848
localparam GEN3_RXCDR_CFG_C_GTH = 16'h1000; // 16'h1000
localparam GEN3_RXCDR_CFG_D_GTH = 16'h07FE; // 16'h07FE v1.0 silicon
localparam GEN3_RXCDR_CFG_D_GTH_AUX = 16'h0FFE; // 16'h07FE v2.0 silicon, [62:59] AUX CDR configuration
localparam GEN3_RXCDR_CFG_E_GTH = 16'h0010; // 16'h0010
localparam GEN3_RXCDR_CFG_F_GTH = 16'h0000; // 16'h0000 v1.0 silicon
localparam GEN3_RXCDR_CFG_F_GTH_AUX = 16'h0002; // 16'h0000 v2.0 silicon, [81] AUX CDR enable
//---------- DRP Data for PCIe Gen1, Gen2 and Gen3 -----
localparam GEN123_PCS_RSVD_ATTR_A = 16'b0000000000000000; // Auto TX and RX sync mode
localparam GEN123_PCS_RSVD_ATTR_M_TX = 16'b0000000000000010; // Manual TX sync mode
localparam GEN123_PCS_RSVD_ATTR_M_RX = 16'b0000000000000100; // Manual RX sync mode
//---------- DRP Data for x16 --------------------------
localparam X16_RX_DATAWIDTH = 16'b0000000000000000; // 2-byte (16-bit) internal data width
//---------- DRP Data for x20 --------------------------
localparam X20_RX_DATAWIDTH = 16'b0000100000000000; // 2-byte (20-bit) internal data width
//---------- DRP Data ----------------------------------
wire [15:0] data_txout_div;
wire [15:0] data_rxout_div;
wire [15:0] data_tx_data_width;
wire [15:0] data_tx_int_datawidth;
wire [15:0] data_rx_data_width;
wire [15:0] data_rx_int_datawidth;
wire [15:0] data_txbuf_en;
wire [15:0] data_rxbuf_en;
wire [15:0] data_tx_xclk_sel;
wire [15:0] data_rx_xclk_sel;
wire [15:0] data_clk_correction_use;
wire [15:0] data_tx_drive_mode;
wire [15:0] data_rxcdr_eidle;
wire [15:0] data_rx_dfe_lpm_eidle;
wire [15:0] data_pma_rsv_a;
wire [15:0] data_pma_rsv_b;
wire [15:0] data_rxcdr_cfg_a;
wire [15:0] data_rxcdr_cfg_b;
wire [15:0] data_rxcdr_cfg_c;
wire [15:0] data_rxcdr_cfg_d;
wire [15:0] data_rxcdr_cfg_e;
wire [15:0] data_rxcdr_cfg_f;
wire [15:0] data_pcs_rsvd_attr_a;
wire [15:0] data_pcs_rsvd_attr_m_tx;
wire [15:0] data_pcs_rsvd_attr_m_rx;
wire [15:0] data_pcs_rsvd_attr_m;
wire [15:0] data_x16x20_rx_datawidth;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 0;
localparam FSM_LOAD = 1;
localparam FSM_READ = 2;
localparam FSM_RRDY = 3;
localparam FSM_WRITE = 4;
localparam FSM_WRDY = 5;
localparam FSM_DONE = 6;
//---------- Input FF ----------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
//---------- 1st Stage FF --------------------------
gtxreset_reg1 <= 1'd0;
rate_reg1 <= 2'd0;
x16x20_mode_reg1 <= 1'd0;
x16_reg1 <= 1'd0;
do_reg1 <= 16'd0;
rdy_reg1 <= 1'd0;
start_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
gtxreset_reg2 <= 1'd0;
rate_reg2 <= 2'd0;
x16x20_mode_reg2 <= 1'd0;
x16_reg2 <= 1'd0;
do_reg2 <= 16'd0;
rdy_reg2 <= 1'd0;
start_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
gtxreset_reg1 <= DRP_GTXRESET;
rate_reg1 <= DRP_RATE;
x16x20_mode_reg1 <= DRP_X16X20_MODE;
x16_reg1 <= DRP_X16;
do_reg1 <= DRP_DO;
rdy_reg1 <= DRP_RDY;
start_reg1 <= DRP_START;
//---------- 2nd Stage FF --------------------------
gtxreset_reg2 <= gtxreset_reg1;
rate_reg2 <= rate_reg1;
x16x20_mode_reg2 <= x16x20_mode_reg1;
x16_reg2 <= x16_reg1;
do_reg2 <= do_reg1;
rdy_reg2 <= rdy_reg1;
start_reg2 <= start_reg1;
end
end
//---------- Select DRP Data ---------------------------------------------------
assign data_txout_div = (rate_reg2 == 2'd2) ? GEN3_TXOUT_DIV : GEN12_TXOUT_DIV;
assign data_rxout_div = (rate_reg2 == 2'd2) ? GEN3_RXOUT_DIV : GEN12_RXOUT_DIV;
assign data_tx_data_width = (rate_reg2 == 2'd2) ? GEN3_TX_DATA_WIDTH : GEN12_TX_DATA_WIDTH;
assign data_tx_int_datawidth = (rate_reg2 == 2'd2) ? GEN3_TX_INT_DATAWIDTH : GEN12_TX_INT_DATAWIDTH;
assign data_rx_data_width = (rate_reg2 == 2'd2) ? GEN3_RX_DATA_WIDTH : GEN12_RX_DATA_WIDTH;
assign data_rx_int_datawidth = (rate_reg2 == 2'd2) ? GEN3_RX_INT_DATAWIDTH : GEN12_RX_INT_DATAWIDTH;
assign data_txbuf_en = ((rate_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? GEN3_TXBUF_EN : GEN12_TXBUF_EN;
assign data_rxbuf_en = ((rate_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE")) ? GEN3_RXBUF_EN : GEN12_RXBUF_EN;
assign data_tx_xclk_sel = ((rate_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? GEN3_TX_XCLK_SEL : GEN12_TX_XCLK_SEL;
assign data_rx_xclk_sel = ((rate_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE")) ? GEN3_RX_XCLK_SEL : GEN12_RX_XCLK_SEL;
assign data_clk_correction_use = (rate_reg2 == 2'd2) ? GEN3_CLK_CORRECT_USE : GEN12_CLK_CORRECT_USE;
assign data_tx_drive_mode = (rate_reg2 == 2'd2) ? GEN3_TX_DRIVE_MODE : GEN12_TX_DRIVE_MODE;
assign data_rxcdr_eidle = (rate_reg2 == 2'd2) ? GEN3_RXCDR_EIDLE : GEN12_RXCDR_EIDLE;
assign data_rx_dfe_lpm_eidle = (rate_reg2 == 2'd2) ? GEN3_RX_DFE_LPM_EIDLE : GEN12_RX_DFE_LPM_EIDLE;
assign data_pma_rsv_a = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_PMA_RSV_A_GTH : GEN3_PMA_RSV_A_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_PMA_RSV_A_GTH : GEN12_PMA_RSV_A_GTX);
assign data_pma_rsv_b = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_PMA_RSV_B_GTH : GEN3_PMA_RSV_B_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_PMA_RSV_B_GTH : GEN12_PMA_RSV_B_GTX);
assign data_rxcdr_cfg_a = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_A_GTH_A : GEN3_RXCDR_CFG_A_GTH_S) : GEN3_RXCDR_CFG_A_GTX) :
((PCIE_GT_DEVICE == "GTH") ? ((PCIE_ASYNC_EN == "TRUE") ? GEN12_RXCDR_CFG_A_GTH_A : GEN12_RXCDR_CFG_A_GTH_S) : GEN12_RXCDR_CFG_A_GTX);
assign data_rxcdr_cfg_b = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_RXCDR_CFG_B_GTH : GEN3_RXCDR_CFG_B_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_B_GTH : GEN12_RXCDR_CFG_B_GTX);
assign data_rxcdr_cfg_c = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_RXCDR_CFG_C_GTH : GEN3_RXCDR_CFG_C_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_C_GTH : GEN12_RXCDR_CFG_C_GTX);
assign data_rxcdr_cfg_d = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_AUX_CDR_GEN3_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTH_AUX : GEN3_RXCDR_CFG_D_GTH) : ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTX_A : GEN3_RXCDR_CFG_D_GTX_S)) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_D_GTH : ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTX_A : GEN3_RXCDR_CFG_D_GTX_S));
assign data_rxcdr_cfg_e = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_RXCDR_CFG_E_GTH : GEN3_RXCDR_CFG_E_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_E_GTH : GEN12_RXCDR_CFG_E_GTX);
assign data_rxcdr_cfg_f = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_AUX_CDR_GEN3_EN == "TRUE") ? GEN3_RXCDR_CFG_F_GTH_AUX : GEN3_RXCDR_CFG_F_GTH) : GEN3_RXCDR_CFG_F_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_F_GTH : GEN12_RXCDR_CFG_F_GTX);
assign data_pcs_rsvd_attr_a = GEN123_PCS_RSVD_ATTR_A;
assign data_pcs_rsvd_attr_m_tx = PCIE_TXSYNC_MODE ? GEN123_PCS_RSVD_ATTR_A : GEN123_PCS_RSVD_ATTR_M_TX;
assign data_pcs_rsvd_attr_m_rx = PCIE_RXSYNC_MODE ? GEN123_PCS_RSVD_ATTR_A : GEN123_PCS_RSVD_ATTR_M_RX;
assign data_pcs_rsvd_attr_m = data_pcs_rsvd_attr_m_tx | data_pcs_rsvd_attr_m_rx;
assign data_x16x20_rx_datawidth = x16_reg2 ? X16_RX_DATAWIDTH : X20_RX_DATAWIDTH;
//---------- Load Counter ------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
load_cnt <= 2'd0;
else
//---------- Increment Load Counter ----------------
if ((fsm == FSM_LOAD) && (load_cnt < LOAD_CNT_MAX))
load_cnt <= load_cnt + 2'd1;
//---------- Hold Load Counter ---------------------
else if ((fsm == FSM_LOAD) && (load_cnt == LOAD_CNT_MAX))
load_cnt <= load_cnt;
//---------- Reset Load Counter --------------------
else
load_cnt <= 2'd0;
end
//---------- Update DRP Address and Data ---------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
addr_reg <= 9'd0;
di_reg <= 16'd0;
end
else
begin
case (index)
//--------------------------------------------------
5'd0:
begin
addr_reg <= mode ? ADDR_PCS_RSVD_ATTR :
x16x20_mode_reg2 ? ADDR_RX_DATA_WIDTH : ADDR_TXOUT_DIV;
di_reg <= mode ? ((do_reg2 & MASK_PCS_RSVD_ATTR) | data_pcs_rsvd_attr_a) :
x16x20_mode_reg2 ? ((do_reg2 & MASK_X16X20_RX_DATA_WIDTH) | data_x16x20_rx_datawidth) :
((do_reg2 & MASK_TXOUT_DIV) | data_txout_div);
end
//--------------------------------------------------
5'd1:
begin
addr_reg <= mode ? ADDR_PCS_RSVD_ATTR : ADDR_RXOUT_DIV;
di_reg <= mode ? ((do_reg2 & MASK_PCS_RSVD_ATTR) | data_pcs_rsvd_attr_m) :
((do_reg2 & MASK_RXOUT_DIV) | data_rxout_div);
end
//--------------------------------------------------
5'd2 :
begin
addr_reg <= ADDR_TX_DATA_WIDTH;
di_reg <= (do_reg2 & MASK_TX_DATA_WIDTH) | data_tx_data_width;
end
//--------------------------------------------------
5'd3 :
begin
addr_reg <= ADDR_TX_INT_DATAWIDTH;
di_reg <= (do_reg2 & MASK_TX_INT_DATAWIDTH) | data_tx_int_datawidth;
end
//--------------------------------------------------
5'd4 :
begin
addr_reg <= ADDR_RX_DATA_WIDTH;
di_reg <= (do_reg2 & MASK_RX_DATA_WIDTH) | data_rx_data_width;
end
//--------------------------------------------------
5'd5 :
begin
addr_reg <= ADDR_RX_INT_DATAWIDTH;
di_reg <= (do_reg2 & MASK_RX_INT_DATAWIDTH) | data_rx_int_datawidth;
end
//--------------------------------------------------
5'd6 :
begin
addr_reg <= ADDR_TXBUF_EN;
di_reg <= (do_reg2 & MASK_TXBUF_EN) | data_txbuf_en;
end
//--------------------------------------------------
5'd7 :
begin
addr_reg <= ADDR_RXBUF_EN;
di_reg <= (do_reg2 & MASK_RXBUF_EN) | data_rxbuf_en;
end
//--------------------------------------------------
5'd8 :
begin
addr_reg <= ADDR_TX_XCLK_SEL;
di_reg <= (do_reg2 & MASK_TX_XCLK_SEL) | data_tx_xclk_sel;
end
//--------------------------------------------------
5'd9 :
begin
addr_reg <= ADDR_RX_XCLK_SEL;
di_reg <= (do_reg2 & MASK_RX_XCLK_SEL) | data_rx_xclk_sel;
end
//--------------------------------------------------
5'd10 :
begin
addr_reg <= ADDR_CLK_CORRECT_USE;
di_reg <= (do_reg2 & MASK_CLK_CORRECT_USE) | data_clk_correction_use;
end
//--------------------------------------------------
5'd11 :
begin
addr_reg <= ADDR_TX_DRIVE_MODE;
di_reg <= (do_reg2 & MASK_TX_DRIVE_MODE) | data_tx_drive_mode;
end
//--------------------------------------------------
5'd12 :
begin
addr_reg <= ADDR_RXCDR_EIDLE;
di_reg <= (do_reg2 & MASK_RXCDR_EIDLE) | data_rxcdr_eidle;
end
//--------------------------------------------------
5'd13 :
begin
addr_reg <= ADDR_RX_DFE_LPM_EIDLE;
di_reg <= (do_reg2 & MASK_RX_DFE_LPM_EIDLE) | data_rx_dfe_lpm_eidle;
end
//--------------------------------------------------
5'd14 :
begin
addr_reg <= ADDR_PMA_RSV_A;
di_reg <= (do_reg2 & MASK_PMA_RSV_A) | data_pma_rsv_a;
end
//--------------------------------------------------
5'd15 :
begin
addr_reg <= ADDR_PMA_RSV_B;
di_reg <= (do_reg2 & MASK_PMA_RSV_B) | data_pma_rsv_b;
end
//--------------------------------------------------
5'd16 :
begin
addr_reg <= ADDR_RXCDR_CFG_A;
di_reg <= (do_reg2 & MASK_RXCDR_CFG_A) | data_rxcdr_cfg_a;
end
//--------------------------------------------------
5'd17 :
begin
addr_reg <= ADDR_RXCDR_CFG_B;
di_reg <= (do_reg2 & MASK_RXCDR_CFG_B) | data_rxcdr_cfg_b;
end
//--------------------------------------------------
5'd18 :
begin
addr_reg <= ADDR_RXCDR_CFG_C;
di_reg <= (do_reg2 & MASK_RXCDR_CFG_C) | data_rxcdr_cfg_c;
end
//--------------------------------------------------
5'd19 :
begin
addr_reg <= ADDR_RXCDR_CFG_D;
di_reg <= (do_reg2 & MASK_RXCDR_CFG_D) | data_rxcdr_cfg_d;
end
//--------------------------------------------------
5'd20 :
begin
addr_reg <= ADDR_RXCDR_CFG_E;
di_reg <= (do_reg2 & ((PCIE_GT_DEVICE == "GTH") ? MASK_RXCDR_CFG_E_GTH : MASK_RXCDR_CFG_E_GTX)) | data_rxcdr_cfg_e;
end
//--------------------------------------------------
5'd21 :
begin
addr_reg <= ADDR_RXCDR_CFG_F;
di_reg <= (do_reg2 & ((PCIE_GT_DEVICE == "GTH") ? MASK_RXCDR_CFG_F_GTH : MASK_RXCDR_CFG_F_GTX)) | data_rxcdr_cfg_f;
end
//--------------------------------------------------
default :
begin
addr_reg <= 9'd0;
di_reg <= 16'd0;
end
endcase
end
end
//---------- PIPE DRP FSM ------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
fsm <= FSM_IDLE;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
//---------- Reset or Rate Change --------------
if (start_reg2)
begin
fsm <= FSM_LOAD;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd0;
end
//---------- GTXRESET --------------------------
else if ((gtxreset_reg2 && !gtxreset_reg1) && ((PCIE_TXSYNC_MODE == 0) || (PCIE_RXSYNC_MODE == 0)) && (PCIE_USE_MODE == "1.0"))
begin
fsm <= FSM_LOAD;
index <= 5'd0;
mode <= 1'd1;
done <= 1'd0;
end
//---------- Idle ------------------------------
else
begin
fsm <= FSM_IDLE;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd1;
end
end
//---------- Load DRP Address ---------------------
FSM_LOAD :
begin
fsm <= (load_cnt == LOAD_CNT_MAX) ? FSM_READ : FSM_LOAD;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Read DRP ------------------------------
FSM_READ :
begin
fsm <= FSM_RRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Read DRP Ready ------------------------
FSM_RRDY :
begin
fsm <= rdy_reg2 ? FSM_WRITE : FSM_RRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Write DRP -----------------------------
FSM_WRITE :
begin
fsm <= FSM_WRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Write DRP Ready -----------------------
FSM_WRDY :
begin
fsm <= rdy_reg2 ? FSM_DONE : FSM_WRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- DRP Done ------------------------------
FSM_DONE :
begin
if ((index == INDEX_MAX) || (mode && (index == 5'd1)) || (x16x20_mode_reg2 && (index == 5'd0)))
begin
fsm <= FSM_IDLE;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd0;
end
else
begin
fsm <= FSM_LOAD;
index <= index + 5'd1;
mode <= mode;
done <= 1'd0;
end
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd0;
end
endcase
end
end
//---------- PIPE DRP Output ---------------------------------------------------
assign DRP_ADDR = addr_reg;
assign DRP_EN = (fsm == FSM_READ) || (fsm == FSM_WRITE);
assign DRP_DI = di_reg;
assign DRP_WE = (fsm == FSM_WRITE);
assign DRP_DONE = done;
assign DRP_FSM = fsm;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND3_PP_SYMBOL_V
`define SKY130_FD_SC_MS__NAND3_PP_SYMBOL_V
/**
* nand3: 3-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND3_PP_SYMBOL_V
|
/*
* Copyright 2010, Aleksander Osman, [email protected]. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are
* permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module early_boot(
input CLK_I,
input RST_I,
output reg CYC_O,
output reg [31:0] DAT_O,
output reg STB_O,
output reg WE_O,
output reg [31:2] ADR_O,
output [3:0] SEL_O,
input [31:0] DAT_I,
input ACK_I,
input ERR_I,
input RTY_I,
//****************** OTHER
//finished loading
output loading_finished_o
);
assign SEL_O = 4'b1111;
assign loading_finished_o = (state == S_FINISHED) ? 1'b1 : 1'b0;
reg [3:0] state;
reg [9:0] wait_counter;
parameter [3:0]
S_CHECK_STATUS = 4'd0,
S_CHECK_STATUS_2 = 4'd1,
S_CHECK_STATUS_3 = 4'd2,
S_SET_SIZE = 4'd3,
S_SET_SIZE_2 = 4'd4,
S_SET_CONTROL = 4'd5,
S_SET_CONTROL_2 = 4'd6,
S_CHECK_FINISHED = 4'd7,
S_CHECK_FINISHED_2 = 4'd8,
S_CHECK_FINISHED_3 = 4'd9,
S_FINISHED = 4'd10;
always @(posedge CLK_I) begin
if(RST_I == 1'b1) begin
CYC_O <= 1'b0;
DAT_O <= 32'd0;
STB_O <= 1'b0;
WE_O <= 1'b0;
ADR_O <= 30'd0;
state <= S_CHECK_STATUS;
wait_counter <= 10'd0;
end
else if(state == S_CHECK_STATUS) begin
CYC_O <= 1'b1;
DAT_O <= 32'd0;
STB_O <= 1'b1;
WE_O <= 1'b0;
ADR_O <= 30'h30000000;
state <= S_CHECK_STATUS_2;
end
else if(state == S_CHECK_STATUS_2) begin
if(ACK_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
if(DAT_I == 32'd2) begin
state <= S_SET_SIZE;
end
else begin
state <= S_CHECK_STATUS_3;
end
end
end
else if(state == S_CHECK_STATUS_3) begin
if(wait_counter == 10'd1023) begin
wait_counter <= 10'd0;
state <= S_CHECK_STATUS;
end
else wait_counter <= wait_counter + 10'd1;
end
else if(state == S_SET_SIZE) begin
CYC_O <= 1'b1;
DAT_O <= 32'd2048;
STB_O <= 1'b1;
WE_O <= 1'b1;
ADR_O <= 30'h30000002;
state <= S_SET_SIZE_2;
end
else if(state == S_SET_SIZE_2) begin
if(ACK_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
state <= S_SET_CONTROL;
end
end
else if(state == S_SET_CONTROL) begin
CYC_O <= 1'b1;
DAT_O <= 32'd2;
STB_O <= 1'b1;
WE_O <= 1'b1;
ADR_O <= 30'h30000003;
state <= S_SET_CONTROL_2;
end
else if(state == S_SET_CONTROL_2) begin
if(ACK_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
state <= S_CHECK_FINISHED;
end
end
else if(state == S_CHECK_FINISHED) begin
CYC_O <= 1'b1;
DAT_O <= 32'd0;
STB_O <= 1'b1;
WE_O <= 1'b0;
ADR_O <= 30'h30000000;
state <= S_CHECK_FINISHED_2;
end
else if(state == S_CHECK_FINISHED_2) begin
if(ACK_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
if(DAT_I == 32'd2) begin //idle
state <= S_FINISHED;
end
else begin
state <= S_CHECK_FINISHED_3;
end
end
end
else if(state == S_CHECK_FINISHED_3) begin
if(wait_counter == 10'd1023) begin
wait_counter <= 10'd0;
state <= S_CHECK_FINISHED;
end
else wait_counter <= wait_counter + 10'd1;
end
else if(state == S_FINISHED) begin
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A41O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A41O_BEHAVIORAL_PP_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a41o (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A41O_BEHAVIORAL_PP_V |
// -*- Mode: Verilog -*-
// Filename : adxl362_fifo.v
// Description : ADXL362 512 element FIFO
// Author : Philip Tracton
// Created On : Thu Jun 23 20:54:03 2016
// Last Modified By: Philip Tracton
// Last Modified On: Thu Jun 23 20:54:03 2016
// Update Count : 0
// Status : Unknown, Use with caution!
module adxl362_fifo (/*AUTOARG*/
// Outputs
data_read, full, empty,
// Inputs
data_write, clk, rst, flush, read, write
) ;
parameter WIDTH = 16;
parameter DEPTH = 512;
parameter INDEX_WIDTH = $clog2(DEPTH);
output wire [WIDTH-1:0] data_read;
output wire full;
output wire empty;
input wire [WIDTH-1:0] data_write;
input wire clk;
input wire rst;
input wire flush;
input wire read;
input wire write;
//
// This is the memory that holds the data
//
reg [WIDTH-1:0] fifo [0:DEPTH-1];
//
// Pointer of where to read from the fifo memory
//
reg [INDEX_WIDTH-1:0] read_ptr;
wire [INDEX_WIDTH-1:0] read_ptr1;
//
// Pointer to where to write to the fifo memory
//
reg [INDEX_WIDTH-1:0] write_ptr;
wire [INDEX_WIDTH-1:0] write_ptr1;
//
// Guarding bit for the empty/full wrap around situation
//
reg guard;
//
// On reset or flush, put the write pointer back to 0
// On a write register the pointer's next address
//
always @(posedge clk)
if (rst) begin
write_ptr <= 0;
end else if (flush) begin
write_ptr <= 0;
end else if (write) begin
write_ptr <= write_ptr1;
end
//
// On a write this becomes the new write ptr
//
assign write_ptr1 = write_ptr + 1;
//
// Store data in the FIFO
//
always @(posedge write)
if (write) begin
fifo[write_ptr] <= data_write;
end
//
// On reset or flush, put the write pointer back to 0
// On a read register the pointer's next address
//
always @(posedge clk)
if (rst) begin
read_ptr <= 0;
end else if (flush) begin
read_ptr <= 0;
end else if (read) begin
read_ptr <= read_ptr1;
end
//
// Pointer to the next read location
//
assign read_ptr1 = read_ptr + 1;
//
// Always present the latest data to be read by the next block
//
assign data_read = fifo[read_ptr];
//
// Guard Bit Logic
//
always @(posedge clk)
if (rst) begin
guard <= 0;
end else if (flush) begin
guard <= 0;
end else if ((write_ptr1 == read_ptr) && write) begin
guard <= 1;
end else if (read) begin
guard <= 0;
end
//
// Read the last element and we are now empty
//
assign empty = (write_ptr == read_ptr) & !guard;
//
// Wrote the last available location, now full
//
assign full = (write_ptr == read_ptr) & guard;
endmodule // adxl362_fifo
|
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2018, Darryl Ring.
//
// This program is free software: you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation, either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <https://www.gnu.org/licenses/>.
//
// Additional permission under GNU GPL version 3 section 7:
// If you modify this program, or any covered work, by linking or combining it
// with independent modules provided by the FPGA vendor only (this permission
// does not extend to any 3rd party modules, "soft cores" or macros) under
// different license terms solely for the purpose of generating binary
// "bitstream" files and/or simulating the code, the copyright holders of this
// program give you the right to distribute the covered work without those
// independent modules as long as the source code for them is available from
// the FPGA vendor free of charge, and there is no dependence on any encrypted
// modules for simulating of the combined code. This permission applies to you
// if the distributed code contains all the components and scripts required to
// completely simulate it with at least one of the Free Software programs.
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 1 ps
module axis_phase_generator #
(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer PHASE_WIDTH = 30
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [PHASE_WIDTH-1:0] cfg_data,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
reg [PHASE_WIDTH-1:0] int_cntr_reg = 0, int_cntr_next;
reg int_enbl_reg = 1'b0, int_enbl_next;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_cntr_reg <= {(PHASE_WIDTH){1'b0}};
int_enbl_reg <= 1'b0;
end
else
begin
int_cntr_reg <= int_cntr_next;
int_enbl_reg <= int_enbl_next;
end
end
always @*
begin
int_cntr_next = int_cntr_reg;
int_enbl_next = int_enbl_reg;
if(~int_enbl_reg)
begin
int_enbl_next = 1'b1;
end
if(int_enbl_reg & m_axis_tready)
begin
int_cntr_next = int_cntr_reg + cfg_data;
end
end
assign m_axis_tdata = {{(AXIS_TDATA_WIDTH-PHASE_WIDTH){int_cntr_reg[PHASE_WIDTH-1]}}, int_cntr_reg};
assign m_axis_tvalid = int_enbl_reg;
endmodule |
/*
--------------------------------------------------------------------------
Pegasus - Copyright (C) 2012 Gregory Matthew James.
This file is part of Pegasus.
Pegasus is free; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
Pegasus is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------
*/
/*
--------------------------------------------------------------------------
-- Project Code : pegasus
-- Module Name : peg_l2_mac_tx
-- Author : mammenx
-- Associated modules:
-- Function : Wrapper for L2 MAC TX.
--------------------------------------------------------------------------
*/
`timescale 1ns / 10ps
`inlcude "pkt_intf_defines.sv"
module peg_l2_mac_tx #(
parameter PKT_DATA_W = 8,
parameter PKT_SIZE_W = 16
)
(
input clk,
input rst_n,
//Inputs from L2 MAC RX
input mac_pause_en,
//MAC Logic Link Control packet interface
`pkt_intf_ports_s(llc_tx_,,PKT_DATA_W),
//RS packet interface
pkt_intf_ports_m(rs_tx_,,PKT_DATA_W)
);
//----------------------- Global parameters Declarations ------------------
//----------------------- Input Declarations ------------------------------
//----------------------- Inout Declarations ------------------------------
//----------------------- Output Declarations -----------------------------
//----------------------- Output Register Declaration ---------------------
//----------------------- Internal Register Declarations ------------------
//----------------------- Internal Wire Declarations ----------------------
//----------------------- Input/Output Registers --------------------------
//----------------------- Start of Code -----------------------------------
peg_l2_mac_tx_framer #(
.PKT_DATA_W(PKT_DATA_W),
.PKT_SIZE_W(PKT_SIZE_W)
)
u_l2_mac_tx_framer
(
.clk (clk),
.rst_n (rst_n),
//Config interface
.config_l2_mac_tx_en (),
.config_l2_mac_tx_padding_en (),
.config_l2_mac_tx_fcs_en (),
.config_l2_mac_addr (),
.config_l2_mac_tx_pause_gen (),
.config_l2_mac_tx_pause_time (),
//Status interface
.l2_mac_tx_fsm_state (),
//Pause Interface from MAC RX
.mac_pause_en (mac_pause_en),
//MAC Logic Link Control packet interface
`pkt_intf_port_connect(llc_tx_,,llc_tx_,),
//RS packet interface
`pkt_intf_port_connect(rs_tx_,,rs_tx_,)
);
endmodule // peg_l2_mac_tx
/*
--------------------------------------------------------------------------
-- <Header>
-- <Log>
[28-07-2014 04:18:29 PM][mammenx] Created basic wrapper
[28-05-14 20:18:21] [mammenx] Moved log section to bottom of file
--------------------------------------------------------------------------
*/
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
//
// This file is part of Descrypt Ztex Bruteforcer
// Copyright (C) 2014 Alexey Osipov <giftsungiv3n at gmail dot com>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////
module Delay(
input [31:0] Din,
output [31:0] Dout,
input CLK
);
reg [31:0]tmp_out [1:0];
reg CE;
always @(posedge CLK)
begin
tmp_out[0] <= Din;
tmp_out[1] <= tmp_out[0];
end
assign Dout = tmp_out[1];
endmodule
module Delay2(
input [31:0] Din,
output [31:0] Dout,
input CLK
);
reg [31:0]tmp_out ;
always @(posedge CLK)
begin
tmp_out <= Din;
end
assign Dout = tmp_out;
endmodule
// ============================================================
module Delay3_salt(
input [67:0] Din,
output [67:0] Dout,
input CLK
);
reg [67:0]tmp_out [1:0];
always @(posedge CLK)
begin
tmp_out[0] <= Din;
tmp_out[1] <= tmp_out[0];
end
assign Dout = tmp_out[1];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDLCLKP_2_V
`define SKY130_FD_SC_LS__SDLCLKP_2_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog wrapper for sdlclkp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdlclkp_2 (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdlclkp_2 (
GCLK,
SCE ,
GATE,
CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDLCLKP_2_V
|
//======================================================================
//
// rosc_entropy.v
// --------------
// Fake ring oscillator based entropy source. This module SHOULD ONLY
// be used during simulation of the Cryptech True Random Number
// Generator (trng). The module DOES NOT provide any real entropy.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module rosc_entropy(
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire error,
input wire discard,
input wire test_mode,
output wire security_error,
output wire entropy_enabled,
output wire [31 : 0] entropy_data,
output wire entropy_valid,
input wire entropy_ack,
output wire [7 : 0] debug,
input wire debug_update
);
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = 32'h00000000;
assign error = 0;
assign security_error = 0;
assign entropy_enabled = 1;
assign entropy_data = 32'haa55aa55;
assign entropy_valid = 1;
assign debug = 8'h42;
endmodule // ringosc_entropy
//======================================================================
// EOF ringosc_entropy.v
//======================================================================
|
(**` * Basics: Functional Programming in Coq *)
(* REMINDER:
#####################################################
### PLEASE DO NOT DISTRIBUTE SOLUTIONS PUBLICLY ###
#####################################################
(See the [Preface] for why.)
*)
(* [Admitted] is Coq's "escape hatch" that says accept this definition
without proof. We use it to mark the 'holes' in the development
that should be completed as part of your homework exercises. In
practice, [Admitted] is useful when you're incrementally developing
large proofs. *)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
simple, everyday mathematics: If a procedure or method has no side
effects, then (ignoring efficiency) all we need to understand
about it is how it maps inputs to outputs -- that is, we can think
of it as just a concrete method for computing a mathematical
function. This is one sense of the word "functional" in
"functional programming." The direct connection between programs
and simple mathematical objects supports both formal correctness
proofs and sound informal reasoning about program behavior.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, included in
data structures, etc. The recognition that functions can be
treated as data in this way enables a host of useful and powerful
idioms.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to
construct and manipulate rich data structures, and sophisticated
_polymorphic type systems_ supporting abstraction and code reuse.
Coq shares all of these features.
The first half of this chapter introduces the most essential
elements of Coq's functional programming language. The second
half introduces some basic _tactics_ that can be used to prove
simple properties of Coq programs. *)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers a powerful mechanism for defining new
data types from scratch, from which all these familiar types arise
as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions. To
illustrate this, we will explicitly recapitulate all the
definitions we need in this course, rather than just getting them
implicitly from the library.
To see how this definition mechanism works, let's start with a
very simple example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second and following lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often figure out these types for
itself when they are not given explicitly -- i.e., it performs
_type inference_ -- but we'll include them to make reading
easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq.
First, we can use the command [Compute] to evaluate a compound
expression involving [next_weekday]. *)
Compute (next_weekday friday).
(* ==> monday : day *)
Compute (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** (We show Coq's responses in comments, but, if you have a
computer handy, this would be an excellent moment to fire up the
Coq interpreter under your favorite IDE -- either CoqIde or Proof
General -- and try this for yourself. Load this file, [Basics.v],
from the book's accompanying Coq sources, find the above example,
submit it to Coq, and observe the result.)
Second, we can record what we _expect_ the result to be in the
form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later.
Having made the assertion, we can also ask Coq to verify it, like
this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification."
Third, we can ask Coq to _extract_, from our [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the standard type [bool] of
booleans, with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library.
Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate Coq's syntax for multi-argument
function definitions. The corresponding multi-argument
application syntax is illustrated by the following four "unit
tests," which constitute a complete specification -- a truth
table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. simpl. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. simpl. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. simpl. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. simpl. reflexivity. Qed.
(** We can also introduce some familiar syntax for the boolean
operations we have just defined. The [Infix] command defines new,
infix notation for an existing definition. *)
Infix "&&" := andb.
Infix "||" := orb.
Example test_orb5: false || false || true = true.
Proof. simpl. reflexivity. Qed.
(** _A note on notation_: In [.v] files, we use square brackets to
delimit fragments of Coq code within comments; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font].
The special phrases [Admitted] and [admit] can be used as a
placeholder for an incomplete definition or proof. We'll use them
in exercises, to indicate the parts that we're leaving for you --
i.e., your job is to replace [admit] or [Admitted] with real
definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Remove [admit] and complete the definition of the following
function; then make sure that the [Example] assertions below can
each be verified by Coq. (Remove "[Admitted.]" and fill in each
proof, following the model of the [orb] tests above.) The function
should return [true] if either or both of its inputs are
[false]. *)
Definition nandb (b1:bool) (b2:bool) : bool :=
match b1, b2 with
| true, true => false
| _, _ => true
end.
Example test_nandb1: (nandb true false) = true.
Proof. reflexivity. Qed.
Example test_nandb2: (nandb false false) = true.
Proof. reflexivity. Qed.
Example test_nandb3: (nandb false true) = true.
Proof. reflexivity. Qed.
Example test_nandb4: (nandb true true) = false.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool :=
(andb b1 (andb b2 b3)).
Example test_andb31: (andb3 true true true) = true.
Proof. reflexivity. Qed.
Example test_andb32: (andb3 false true true) = false.
Proof. reflexivity. Qed.
Example test_andb33: (andb3 true false true) = false.
Proof. reflexivity. Qed.
Example test_andb34: (andb3 true true false) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** Every expression in Coq has a type, describing what sort of
thing it computes. The [Check] command asks Coq to print the type
of an expression. *)
(** For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Modules *)
(** Coq provides a _module system_, to aid in organizing large
developments. In this course we won't need most of its features,
but one is useful: If we enclose a collection of declarations
between [Module X] and [End X] markers, then, in the remainder of
the file after the [End], these definitions are referred to by
names like [X.foo] instead of just [foo]. Here, we use this
feature to introduce the definition of the type [nat] in an inner
module so that it does not interfere with the one from the
standard library, which comes with a bit of special notational
magic. *)
Module Playground1.
(* ###################################################################### *)
(** ** Numbers *)
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of _inductive rules_ describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O],"
not the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, indicating that they don't take any
arguments.
These three conditions are the precise force of the [Inductive]
declaration. They imply that the expression [O], the expression
[S O], the expression [S (S O)], the expression [S (S (S O))], and
so on all belong to the set [nat], while other expressions like
[true], [andb true false], and [S (S false)] do not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
(* ===> 4 : nat *)
Compute (minustwo 4).
(* ===> 2 : nat *)
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference between the
first one and the other two: functions like [pred] and [minustwo]
come with _computation rules_ -- e.g., the definition of [pred]
says that [pred 2] can be simplified to [1] -- while the
definition of [S] has no such behavior attached. Although it is
like a function in the sense that it can be applied to an
argument, it does not _do_ anything at all!
For most function definitions over numbers, just pattern matching
is not enough: we also need recursion. For example, to check that
a number [n] is even, we may need to recursively check whether
[n-2] is even. To write such functions, we use the keyword
[Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that is a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: oddb 1 = true.
Proof. simpl. reflexivity. Qed.
Example test_oddb2: oddb 4 = false.
Proof. simpl. reflexivity. Qed.
(** (You will notice if you step through these proofs that
[simpl] actually has no effect on the goal -- all of the work is
done by [reflexivity]. We'll see more about why that is shortly.)
Naturally, we can also define multi-argument functions by
recursion. *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Compute (plus 3 2).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))]
by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))]
by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))]
by the second clause of the [match]
==> [S (S (S (S (S O))))]
by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. simpl. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard mathematical factorial function:
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
| O => 1
| S n' => mult n (factorial n')
end.
Example test_factorial1: (factorial 3) = 6.
Proof. reflexivity. Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
Proof. reflexivity. Qed.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing _notations_ for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
optional "More on Notation" section at the end of this chapter.)
Note that these do not change the definitions we've already made:
they are simply instructions to the Coq parser to accept [x + y]
in place of [plus x y] and, conversely, to the Coq pretty-printer
to display [plus x y] as [x + y].
When we say that Coq comes with nothing built-in, we really mean
it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** The [leb] function tests whether its first argument is less than or
equal to its second argument, yielding a boolean. *)
Fixpoint leb (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => leb n' m'
end
end.
Example test_leb1: (leb 2 2) = true.
Proof. simpl. reflexivity. Qed.
Example test_leb2: (leb 2 4) = true.
Proof. simpl. reflexivity. Qed.
Example test_leb3: (leb 4 2) = false.
Proof. simpl. reflexivity. Qed.
(** **** Exercise: 1 star (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function. *)
Definition blt_nat (n m : nat) : bool :=
(andb (leb n m) (negb (beq_nat n m))).
Example test_blt_nat1: (blt_nat 2 2) = false.
Proof. reflexivity. Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to stating and proving properties of their behavior.
Actually, we've already started doing this: each [Example] in the
previous sections makes a precise claim about the behavior of some
function on some particular inputs. The proofs of these claims
were always the same: use [simpl] to simplify both sides of the
equation, then use [reflexivity] to check that both sides contain
identical values.
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved just
by observing that [0 + n] reduces to [n] no matter what [n] is, a
fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. simpl. reflexivity. Qed.
(** (You may notice that the above statement looks different in
the [.v] file in your IDE than it does in the HTML rendition in
your browser, if you are viewing both. In [.v] files, we write the
[forall] universal quantifier using the reserved identifier
"forall." When the [.v] files are converted to HTML, this gets
transformed into an upside-down-A symbol.) *)
(** This is a good place to mention that [reflexivity] is a bit
more powerful than we have admitted. In the examples we have seen,
the calls to [simpl] were actually not needed, because
[reflexivity] can perform some simplification automatically when
checking that two sides are equal; [simpl] was just added so that
we could see the intermediate state -- after simplification but
before finishing the proof. Here is a shorter proof of the
theorem: *)
Theorem plus_O_n' : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** Moreover, it will be useful later to know that [reflexivity]
does somewhat _more_ simplification than [simpl] does -- for
example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
if reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
created by all this simplification and unfolding; by contrast,
[simpl] is used in situations where we may have to read and
understand the new goal that it creates, so we would not want it
blindly expanding definitions and leaving the goal in a messy
state. *)
(** The form of the theorem we just stated and its proof are
almost exactly the same as the simpler examples we saw earlier;
there are just a few differences.
First, we've used the keyword [Theorem] instead of [Example].
This difference is purely a matter of style; the keywords
[Example] and [Theorem] (and a few others, including [Lemma],
[Fact], and [Remark]) mean exactly the same thing to Coq.
Second, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a _context_ of current assumptions. In effect, we
start the proof by saying "Suppose [n] is some arbitrary
number..."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to guide the process of checking some claim we are making.
We will see several more tactics in the rest of this chapter and
yet more in future chapters.
Other similar theorems can be proved with the same pattern. *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(** It is worth stepping through these proofs to observe how the
context and the goal change. *)
(** You may want to add calls to [simpl] before [reflexivity] to
see the simplifications that Coq performs on the terms before
checking that they are equal.
Although simplification is powerful enough to prove some fairly
general facts, there are many statements that cannot be handled by
simplification alone. For instance, we cannot use it to prove
that [0] is also a neutral element for [+] _on the right_. *)
Theorem plus_n_O : forall n, n = n + 0.
Proof.
intros n. simpl. (* Doesn't do anything! *)
(** (Can you explain why this happens? Step through both proofs
with Coq and notice how the goal and context change.)
When stuck in the middle of a proof, we can use the [Abort]
command to give up on it for the moment. *)
Abort.
(** The next chapter will introduce _induction_, a powerful
technique that can be used for proving this goal. For the moment,
though, let's look at a few more simple tactics. *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** This theorem is a bit more interesting than the others we've
seen: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a universal claim about all numbers [n] and [m],
it talks about a more specialized property that only holds when [n
= m]. The arrow symbol is pronounced "implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
(* move both quantifiers into the context: *)
intros n m.
(* move the hypothesis into the context: *)
intros H.
(* rewrite the goal using the hypothesis: *)
rewrite -> H.
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the name [H].
The third tells Coq to rewrite the current goal ([n + n = m + m])
by replacing the left side of the equality hypothesis [H] with the
right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
intros n m o H0 H1.
rewrite -> H0.
rewrite -> H1.
reflexivity.
Qed.
(** [] *)
(** The [Admitted] command tells Coq that we want to skip trying
to prove this theorem and just accept it as a given. This can be
useful for developing longer proofs, since we can state subsidiary
lemmas that we believe will be useful for making some larger
argument, use [Admitted] to accept them on faith for the moment,
and continue working on the main argument until we are sure it
makes sense; then we can go back and fill in the proofs we
skipped. Be careful, though: every time you say [Admitted] (or
[admit]) you are leaving a door open for total nonsense to enter
Coq's nice, rigorous, formally checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. If the statement
of the previously proved theorem involves quantified variables,
as in the example below, Coq tries to instantiate them
by matching with the current goal. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
intros n m H.
rewrite -> H.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation and rewriting: In general, unknown, hypothetical
values (arbitrary numbers, booleans, lists, etc.) can block
simplification. For example, if we try to prove the following
fact using the [simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
To make progress, we need to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false]. And
if [n = S n'] for some [n'], then, although we don't know exactly
what number [n + 1] yields, we can calculate that, at least, it
will begin with one [S], and this is enough to calculate that,
again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
- reflexivity.
- reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem. The
annotation "[as [| n']]" is called an _intro pattern_. It tells
Coq what variable names to introduce in each subgoal. In general,
what goes between the square brackets is a _list of lists_ of
names, separated by [|]. In this case, the first component is
empty, since the [O] constructor is nullary (it doesn't have any
arguments). The second component gives a single name, [n'], since
[S] is a unary constructor.
The [-] signs on the second and third lines are called _bullets_,
and they mark the parts of the proof that correspond to each
generated subgoal. The proof script that comes after a bullet is
the entire proof for a subgoal. In this example, each of the
subgoals is easily proved by a single use of [reflexivity], which
itself performs some simplification -- e.g., the first one
simplifies [beq_nat (S n' + 1) 0] to [false] by first rewriting
[(S n' + 1)] to [S (n' + 1)], then unfolding [beq_nat], and then
simplifying the [match].
Marking cases with bullets is entirely optional: if bullets are
not present, Coq simply asks you to prove each subgoal in
sequence, one at a time. But it is a good idea to use bullets.
For one thing, they make the structure of a proof apparent, making
it more readable. Also, bullets instruct Coq to ensure that a
subgoal is complete before trying to verify the next one,
preventing proofs for different subgoals from getting mixed
up. These issues become especially important in large
developments, where fragile proofs lead to long debugging
sessions.
There are no hard and fast rules for how proofs should be
formatted in Coq -- in particular, where lines should be broken
and how sections of the proof should be indented to indicate their
nested structure. However, if the places where multiple subgoals
are generated are marked with explicit bullets at the beginning of
lines, then the proof will be readable almost no matter what
choices are made about other aspects of layout.
This is also a good place to mention one other piece of somewhat
obvious advice about line lengths. Beginning Coq users sometimes
tend to the extremes, either writing each tactic on its own line
or writing entire proofs on one line. Good style lies somewhere
in the middle. One reasonable convention is to limit yourself to
80-character lines.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it next to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
- reflexivity.
- reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. This is generally considered bad style, since Coq
often makes confusing choices of names when left to its own
devices.
It is sometimes useful to invoke [destruct] inside a subgoal,
generating yet more proof obligations. In this case, we use
different kinds of bullets to mark goals on different "levels."
For example: *)
Theorem andb_commutative : forall b c, andb b c = andb c b.
Proof.
intros b c. destruct b.
- destruct c.
+ reflexivity.
+ reflexivity.
- destruct c.
+ reflexivity.
+ reflexivity.
Qed.
(** Each pair of calls to [reflexivity] corresponds to the
subgoals that were generated after the execution of the [destruct
c] line right above it. Besides [-] and [+], Coq proofs can also
use [*] (asterisk) as a third kind of bullet. If we ever encounter
a proof that generates more than three levels of subgoals, we can
also enclose individual subgoals in curly braces ([{ ... }]): *)
Theorem andb_commutative' : forall b c, andb b c = andb c b.
Proof.
intros b c. destruct b.
{ destruct c.
{ reflexivity. }
{ reflexivity. } }
{ destruct c.
{ reflexivity. }
{ reflexivity. } }
Qed.
(** Since curly braces mark both the beginning and the end of a
proof, they can be used for multiple subgoal levels, as this
example shows. Furthermore, curly braces allow us to reuse the
same bullet shapes at multiple levels in a proof: *)
Theorem andb3_exchange :
forall b c d, andb (andb b c) d = andb (andb b d) c.
Proof.
intros b c d. destruct b.
- destruct c.
{ destruct d.
- reflexivity.
- reflexivity. }
{ destruct d.
- reflexivity.
- reflexivity. }
- destruct c.
{ destruct d.
- reflexivity.
- reflexivity. }
{ destruct d.
- reflexivity.
- reflexivity. }
Qed.
(** Before closing the chapter, let's mention one final
convenience. As you may have noticed, many proofs perform case
analysis on a variable right after introducing it:
intros x y. destruct y as [|y].
This pattern is so common that Coq provides a shorthand for it: we
can perform case analysis on a variable when introducing it by
using an intro pattern instead of a variable name. For instance,
here is a shorter proof of the [plus_1_neq_0] theorem above. *)
Theorem plus_1_neq_0' : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros [|n].
- reflexivity.
- reflexivity. Qed.
(** If there are no arguments to name, we can just write [[]]. *)
Theorem andb_commutative'' :
forall b c, andb b c = andb c b.
Proof.
intros [] [].
- reflexivity.
- reflexivity.
- reflexivity.
- reflexivity.
Qed.
(** **** Exercise: 2 stars (andb_true_elim2) *)
(** Prove the following claim, marking cases (and subcases) with
bullets when you use [destruct]. *)
Theorem andb_true_elim2 : forall b c : bool,
andb b c = true -> c = true.
Proof.
intros. destruct b.
- destruct c.
+ reflexivity.
+ inversion H.
- destruct c.
+ reflexivity.
+ inversion H.
Qed.
(** [] *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
intros n.
destruct n.
- reflexivity.
- reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** ** More on Notation (Optional) *)
(** (In general, sections marked Optional are not needed to follow the
rest of the book, except possibly other Optional sections. On a
first reading, you might want to skim these sections so that you
know what's there for future reference.)
Recall the notation definitions for infix plus and times: *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation symbol in Coq, we can specify its _precedence
level_ and its _associativity_. The precedence level [n] is
specified by writing [at level n]; this helps Coq parse compound
expressions. The associativity setting helps to disambiguate
expressions containing multiple occurrences of the same
symbol. For example, the parameters specified above for [+] and
[*] say that the expression [1+2*3*4] is shorthand for
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity. We will see more examples
of this later, e.g., in the [Lists]
chapter.
Each notation symbol is also associated with a _notation scope_.
Coq tries to guess what scope is meant from context, so when it
sees [S(O*O)] it guesses [nat_scope], but when it sees the
cartesian product (tuple) type [bool*bool] it guesses
[type_scope]. Occasionally, it is necessary to help it out with
percent-notation by writing [(x*y)%nat], and sometimes in what Coq
prints it will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation ([3], [4], [5],
etc.), so you may sometimes see [0%nat], which means [O] (the
natural number [0] that we're using in this chapter), or [0%Z],
which means the Integer zero (which comes from a different part of
the standard library). *)
(* ###################################################################### *)
(** ** Fixpoints and Structural Recursion (Optional) *)
(** Here is a copy of the definition of addition: *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing."
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will reject because
of this restriction. *)
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean_functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f H.
destruct b.
- rewrite H. rewrite H. reflexivity.
- rewrite H. rewrite H. reflexivity.
Qed.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
Theorem negation_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = negb x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f H b.
destruct b.
- rewrite -> H. rewrite -> H. reflexivity.
- rewrite -> H. rewrite -> H. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two. Alternatively, remember that you do
not have to introduce all hypotheses at the same time.) *)
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
intros b c.
destruct b.
- simpl. intros H. rewrite -> H. reflexivity.
- simpl. intros H. rewrite <- H. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function [incr] for binary numbers,
and a function [bin_to_nat] to convert binary numbers to unary numbers.
(c) Write five unit tests [test_bin_incr1], [test_bin_incr2], etc.
for your increment and binary-to-unary functions. Notice that
incrementing a binary number and then converting it to unary
should yield the same result as first converting it to unary and
then incrementing.
*)
Inductive bin : Type :=
| B0 : bin
| B2 : bin -> bin
| B2p1 : bin -> bin.
Fixpoint incr (b:bin) : bin :=
match b with
| B0 => B2p1 B0
| B2 b' => B2p1 b'
| B2p1 b' => B2 (incr b')
end.
Example test_bin_incr1: incr (B2 (B2 (B2p1 B0))) = B2p1 (B2 (B2p1 B0)).
Proof. reflexivity. Qed.
Example test_bin_incr2: incr (B2p1 (B2p1 (B2p1 B0))) = B2 (B2 (B2 (B2p1 B0))).
Proof. reflexivity. Qed.
Example test_bin_incr3: incr (B2p1 (B2 (B2 (B2p1 B0)))) = B2 (B2p1 (B2 (B2p1 B0))).
Proof. reflexivity. Qed.
Example test_bin_incr4: incr (B2p1 (B2p1 (B2 (B2p1 B0)))) = B2 (B2 (B2p1 (B2p1 B0))).
Proof. reflexivity. Qed.
Fixpoint bin_to_nat (b:bin) : nat :=
match b with
| B0 => O
| B2 b' => mult 2 (bin_to_nat b')
| B2p1 b' => S (mult 2 (bin_to_nat b'))
end.
Example test_bin_to_nat1: bin_to_nat (B2 (B2 (B2p1 B0))) = 4.
Proof. reflexivity. Qed.
Example test_bin_to_nat2: bin_to_nat (B2 (B2 (B2 (B2p1 B0)))) = 8.
Proof. reflexivity. Qed.
Example test_bin_to_nat3: bin_to_nat (B2 (B2p1 (B2 (B2p1 B0)))) = 10.
Proof. reflexivity. Qed.
Example test_bin_to_nat4: bin_to_nat (B2p1 (B2 (B2p1 (B2p1 B0)))) = 13.
Proof. reflexivity. Qed.
(** [] *)
(** $Date: 2016-05-26 16:17:19 -0400 (Thu, 26 May 2016) $ *)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPMET1_BEHAVIORAL_V
`define SKY130_FD_SC_MS__TAPMET1_BEHAVIORAL_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__tapmet1 ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPMET1_BEHAVIORAL_V |
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY BER monitor
*/
module eth_phy_10g_rx_ber_mon #
(
parameter HDR_WIDTH = 2,
parameter COUNT_125US = 125000/6.4
)
(
input wire clk,
input wire rst,
/*
* SERDES interface
*/
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
/*
* Status
*/
output wire rx_high_ber
);
// bus width assertions
initial begin
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
parameter COUNT_WIDTH = $clog2(COUNT_125US);
localparam [1:0]
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
reg [COUNT_WIDTH-1:0] time_count_reg = COUNT_125US, time_count_next;
reg [3:0] ber_count_reg = 4'd0, ber_count_next;
reg rx_high_ber_reg = 1'b0, rx_high_ber_next;
assign rx_high_ber = rx_high_ber_reg;
always @* begin
if (time_count_reg > 0) begin
time_count_next = time_count_reg-1;
end else begin
time_count_next = time_count_reg;
end
ber_count_next = ber_count_reg;
rx_high_ber_next = rx_high_ber_reg;
if (serdes_rx_hdr == SYNC_CTRL || serdes_rx_hdr == SYNC_DATA) begin
// valid header
if (ber_count_reg != 4'd15) begin
if (time_count_reg == 0) begin
rx_high_ber_next = 1'b0;
end
end
end else begin
// invalid header
if (ber_count_reg == 4'd15) begin
rx_high_ber_next = 1'b1;
end else begin
ber_count_next = ber_count_reg + 1;
if (time_count_reg == 0) begin
rx_high_ber_next = 1'b0;
end
end
end
if (time_count_reg == 0) begin
// 125 us timer expired
ber_count_next = 4'd0;
time_count_next = COUNT_125US;
end
end
always @(posedge clk) begin
time_count_reg <= time_count_next;
ber_count_reg <= ber_count_next;
rx_high_ber_reg <= rx_high_ber_next;
if (rst) begin
time_count_reg <= COUNT_125US;
ber_count_reg <= 4'd0;
rx_high_ber_reg <= 1'b0;
end
end
endmodule
`resetall
|
module regFile (busW, clk, wE, rW, rA, rB, busA, busB, test_addr, test_data, rst);
input [31:0] busW;
input [4:0] rW, rA, rB;
input clk;
input [1:0] wE;
output [31:0] busA, busB;
input rst;
input [4 :0] test_addr;
output [31:0] test_data;
reg [31:0] register[0:31];
initial begin
register[0] <= 0;// $zero;
register[8] <= 0;// $t0;
register[9] <= 1;// $t1;
register[10] <= 2;// $t2;
register[11] <= 3;// $t3;
register[12] <= 4;// $t4;
register[13] <= 5;// $t5;
register[14] <= 6;// $t6;
register[15] <= 7;// $t7;
register[16] <= 0;// $s0;
register[17] <= 0;// $s1;
register[18] <= 0;// $s2;
register[19] <= 0;// $s3;
end
assign busA = (rA != 0)? register[rA]: 0;
assign busB = (rB != 0)? register[rB]: 0;
always @ ( posedge clk ) begin
if ((wE == 2'b01) && (rW != 0)) begin
register[rW] = busW;
end
if (!rst) begin
register[0] <= 0;// $zero;
register[8] <= 0;// $t0;
register[9] <= 1;// $t1;
register[10] <= 2;// $t2;
register[11] <= 3;// $t3;
register[12] <= 4;// $t4;
register[13] <= 5;// $t5;
register[14] <= 6;// $t6;
register[15] <= 7;// $t7;
register[16] <= 0;// $s0;
register[17] <= 0;// $s1;
register[18] <= 0;// $s2;
register[19] <= 0;// $s3;
end
end
assign test_data = register[test_addr];
endmodule // Register File
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22A_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__O22A_PP_BLACKBOX_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__o22a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22A_PP_BLACKBOX_V
|
`timescale 1 ns / 1 ps
module myip_v1_0_S01_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of ID for for write address, write data, read address and read data
parameter integer C_S_AXI_ID_WIDTH = 1,
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 6,
// Width of optional user defined signal in write address channel
parameter integer C_S_AXI_AWUSER_WIDTH = 0,
// Width of optional user defined signal in read address channel
parameter integer C_S_AXI_ARUSER_WIDTH = 0,
// Width of optional user defined signal in write data channel
parameter integer C_S_AXI_WUSER_WIDTH = 0,
// Width of optional user defined signal in read data channel
parameter integer C_S_AXI_RUSER_WIDTH = 0,
// Width of optional user defined signal in write response channel
parameter integer C_S_AXI_BUSER_WIDTH = 0
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write Address ID
input wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_AWID,
// Write address
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Burst length. The burst length gives the exact number of transfers in a burst
input wire [7 : 0] S_AXI_AWLEN,
// Burst size. This signal indicates the size of each transfer in the burst
input wire [2 : 0] S_AXI_AWSIZE,
// Burst type. The burst type and the size information,
// determine how the address for each transfer within the burst is calculated.
input wire [1 : 0] S_AXI_AWBURST,
// Lock type. Provides additional information about the
// atomic characteristics of the transfer.
input wire S_AXI_AWLOCK,
// Memory type. This signal indicates how transactions
// are required to progress through a system.
input wire [3 : 0] S_AXI_AWCACHE,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Quality of Service, QoS identifier sent for each
// write transaction.
input wire [3 : 0] S_AXI_AWQOS,
// Region identifier. Permits a single physical interface
// on a slave to be used for multiple logical interfaces.
input wire [3 : 0] S_AXI_AWREGION,
// Optional User-defined signal in the write address channel.
input wire [C_S_AXI_AWUSER_WIDTH-1 : 0] S_AXI_AWUSER,
// Write address valid. This signal indicates that
// the channel is signaling valid write address and
// control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that
// the slave is ready to accept an address and associated
// control signals.
output wire S_AXI_AWREADY,
// Write Data
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte
// lanes hold valid data. There is one write strobe
// bit for each eight bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write last. This signal indicates the last transfer
// in a write burst.
input wire S_AXI_WLAST,
// Optional User-defined signal in the write data channel.
input wire [C_S_AXI_WUSER_WIDTH-1 : 0] S_AXI_WUSER,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Response ID tag. This signal is the ID tag of the
// write response.
output wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_BID,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Optional User-defined signal in the write response channel.
output wire [C_S_AXI_BUSER_WIDTH-1 : 0] S_AXI_BUSER,
// Write response valid. This signal indicates that the
// channel is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address ID. This signal is the identification
// tag for the read address group of signals.
input wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_ARID,
// Read address. This signal indicates the initial
// address of a read burst transaction.
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Burst length. The burst length gives the exact number of transfers in a burst
input wire [7 : 0] S_AXI_ARLEN,
// Burst size. This signal indicates the size of each transfer in the burst
input wire [2 : 0] S_AXI_ARSIZE,
// Burst type. The burst type and the size information,
// determine how the address for each transfer within the burst is calculated.
input wire [1 : 0] S_AXI_ARBURST,
// Lock type. Provides additional information about the
// atomic characteristics of the transfer.
input wire S_AXI_ARLOCK,
// Memory type. This signal indicates how transactions
// are required to progress through a system.
input wire [3 : 0] S_AXI_ARCACHE,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Quality of Service, QoS identifier sent for each
// read transaction.
input wire [3 : 0] S_AXI_ARQOS,
// Region identifier. Permits a single physical interface
// on a slave to be used for multiple logical interfaces.
input wire [3 : 0] S_AXI_ARREGION,
// Optional User-defined signal in the read address channel.
input wire [C_S_AXI_ARUSER_WIDTH-1 : 0] S_AXI_ARUSER,
// Write address valid. This signal indicates that
// the channel is signaling valid read address and
// control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that
// the slave is ready to accept an address and associated
// control signals.
output wire S_AXI_ARREADY,
// Read ID tag. This signal is the identification tag
// for the read data group of signals generated by the slave.
output wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_RID,
// Read Data
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of
// the read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read last. This signal indicates the last transfer
// in a read burst.
output wire S_AXI_RLAST,
// Optional User-defined signal in the read address channel.
output wire [C_S_AXI_RUSER_WIDTH-1 : 0] S_AXI_RUSER,
// Read valid. This signal indicates that the channel
// is signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4FULL signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg [C_S_AXI_BUSER_WIDTH-1 : 0] axi_buser;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rlast;
reg [C_S_AXI_RUSER_WIDTH-1 : 0] axi_ruser;
reg axi_rvalid;
// aw_wrap_en determines wrap boundary and enables wrapping
wire aw_wrap_en;
// ar_wrap_en determines wrap boundary and enables wrapping
wire ar_wrap_en;
// aw_wrap_size is the size of the write transfer, the
// write address wraps to a lower address if upper address
// limit is reached
wire integer aw_wrap_size ;
// ar_wrap_size is the size of the read transfer, the
// read address wraps to a lower address if upper address
// limit is reached
wire integer ar_wrap_size ;
// The axi_awv_awr_flag flag marks the presence of write address valid
reg axi_awv_awr_flag;
//The axi_arv_arr_flag flag marks the presence of read address valid
reg axi_arv_arr_flag;
// The axi_awlen_cntr internal write address counter to keep track of beats in a burst transaction
reg [7:0] axi_awlen_cntr;
//The axi_arlen_cntr internal read address counter to keep track of beats in a burst transaction
reg [7:0] axi_arlen_cntr;
//local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
//ADDR_LSB is used for addressing 32/64 bit registers/memories
//ADDR_LSB = 2 for 32 bits (n downto 2)
//ADDR_LSB = 3 for 42 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32)+ 1;
localparam integer OPT_MEM_ADDR_BITS = 3;
localparam integer USER_NUM_MEM = 1;
//----------------------------------------------
//-- Signals for user logic memory space example
//------------------------------------------------
wire [OPT_MEM_ADDR_BITS:0] mem_address;
wire [USER_NUM_MEM-1:0] mem_select;
reg [C_S_AXI_DATA_WIDTH-1:0] mem_data_out[0 : USER_NUM_MEM-1];
genvar i;
genvar j;
genvar mem_byte_index;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BUSER = axi_buser;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RLAST = axi_rlast;
assign S_AXI_RUSER = axi_ruser;
assign S_AXI_RVALID = axi_rvalid;
assign S_AXI_BID = S_AXI_AWID;
assign S_AXI_RID = S_AXI_ARID;
assign aw_wrap_size = (C_S_AXI_DATA_WIDTH/8 * (S_AXI_AWLEN));
assign ar_wrap_size = (C_S_AXI_DATA_WIDTH/8 * (S_AXI_ARLEN));
assign aw_wrap_en = ((axi_awaddr & aw_wrap_size) == aw_wrap_size)? 1'b1: 1'b0;
assign ar_wrap_en = ((axi_araddr & ar_wrap_size) == ar_wrap_size)? 1'b1: 1'b0;
assign S_AXI_BUSER = 0;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
axi_awv_awr_flag <= 1'b0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && ~axi_awv_awr_flag && ~axi_arv_arr_flag)
begin
// slave is ready to accept an address and
// associated control signals
axi_awready <= 1'b1;
axi_awv_awr_flag <= 1'b1;
// used for generation of bresp() and bvalid
end
else if (S_AXI_WLAST && axi_wready)
// preparing to accept next address after current write burst tx completion
begin
axi_awv_awr_flag <= 1'b0;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
axi_awlen_cntr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && ~axi_awv_awr_flag)
begin
// address latching
axi_awaddr <= S_AXI_AWADDR[C_S_AXI_ADDR_WIDTH - 1:0];
// start address of transfer
axi_awlen_cntr <= 0;
end
else if((axi_awlen_cntr <= S_AXI_AWLEN) && axi_wready && S_AXI_WVALID)
begin
axi_awlen_cntr <= axi_awlen_cntr + 1;
case (S_AXI_AWBURST)
2'b00: // fixed burst
// The write address for all the beats in the transaction are fixed
begin
axi_awaddr <= axi_awaddr;
//for awsize = 4 bytes (010)
end
2'b01: //incremental burst
// The write address for all the beats in the transaction are increments by awsize
begin
axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
//awaddr aligned to 4 byte boundary
axi_awaddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
//for awsize = 4 bytes (010)
end
2'b10: //Wrapping burst
// The write address wraps when the address reaches wrap boundary
if (aw_wrap_en)
begin
axi_awaddr <= (axi_awaddr - aw_wrap_size);
end
else
begin
axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
axi_awaddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
end
default: //reserved (incremental burst for example)
begin
axi_awaddr <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
//for awsize = 4 bytes (010)
end
endcase
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if ( ~axi_wready && S_AXI_WVALID && axi_awv_awr_flag)
begin
// slave can accept the write data
axi_wready <= 1'b1;
end
//else if (~axi_awv_awr_flag)
else if (S_AXI_WLAST && axi_wready)
begin
axi_wready <= 1'b0;
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awv_awr_flag && axi_wready && S_AXI_WVALID && ~axi_bvalid && S_AXI_WLAST )
begin
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0;
// 'OKAY' response
end
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_arv_arr_flag <= 1'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID && ~axi_awv_awr_flag && ~axi_arv_arr_flag)
begin
axi_arready <= 1'b1;
axi_arv_arr_flag <= 1'b1;
end
else if (axi_rvalid && S_AXI_RREADY && axi_arlen_cntr == S_AXI_ARLEN)
// preparing to accept next address after current read completion
begin
axi_arv_arr_flag <= 1'b0;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_araddr latching
//This process is used to latch the address when both
//S_AXI_ARVALID and S_AXI_RVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_araddr <= 0;
axi_arlen_cntr <= 0;
axi_rlast <= 1'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID && ~axi_arv_arr_flag)
begin
// address latching
axi_araddr <= S_AXI_ARADDR[C_S_AXI_ADDR_WIDTH - 1:0];
// start address of transfer
axi_arlen_cntr <= 0;
axi_rlast <= 1'b0;
end
else if((axi_arlen_cntr <= S_AXI_ARLEN) && axi_rvalid && S_AXI_RREADY)
begin
axi_arlen_cntr <= axi_arlen_cntr + 1;
axi_rlast <= 1'b0;
case (S_AXI_ARBURST)
2'b00: // fixed burst
// The read address for all the beats in the transaction are fixed
begin
axi_araddr <= axi_araddr;
//for arsize = 4 bytes (010)
end
2'b01: //incremental burst
// The read address for all the beats in the transaction are increments by awsize
begin
axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
//araddr aligned to 4 byte boundary
axi_araddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
//for awsize = 4 bytes (010)
end
2'b10: //Wrapping burst
// The read address wraps when the address reaches wrap boundary
if (ar_wrap_en)
begin
axi_araddr <= (axi_araddr - ar_wrap_size);
end
else
begin
axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
//araddr aligned to 4 byte boundary
axi_araddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
end
default: //reserved (incremental burst for example)
begin
axi_araddr <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB]+1;
//for arsize = 4 bytes (010)
end
endcase
end
else if((axi_arlen_cntr == S_AXI_ARLEN) && ~axi_rlast && axi_arv_arr_flag )
begin
axi_rlast <= 1'b1;
end
else if (S_AXI_RREADY)
begin
axi_rlast <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arv_arr_flag && ~axi_rvalid)
begin
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0;
// 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
axi_rvalid <= 1'b0;
end
end
end
// ------------------------------------------
// -- Example code to access user logic memory region
// ------------------------------------------
generate
if (USER_NUM_MEM >= 1)
begin
assign mem_select = 1;
assign mem_address = (axi_arv_arr_flag? axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]:(axi_awv_awr_flag? axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]:0));
end
endgenerate
// implement Block RAM(s)
generate
for(i=0; i<= USER_NUM_MEM-1; i=i+1)
begin:BRAM_GEN
wire mem_rden;
wire mem_wren;
assign mem_wren = axi_wready && S_AXI_WVALID ;
assign mem_rden = axi_arv_arr_flag ; //& ~axi_rvalid
for(mem_byte_index=0; mem_byte_index<= (C_S_AXI_DATA_WIDTH/8-1); mem_byte_index=mem_byte_index+1)
begin:BYTE_BRAM_GEN
wire [8-1:0] data_in ;
wire [8-1:0] data_out;
reg [8-1:0] byte_ram [0 : 15];
integer j;
//assigning 8 bit data
assign data_in = S_AXI_WDATA[(mem_byte_index*8+7) -: 8];
assign data_out = byte_ram[mem_address];
always @( posedge S_AXI_ACLK )
begin
if (mem_wren && S_AXI_WSTRB[mem_byte_index])
begin
byte_ram[mem_address] <= data_in;
end
end
always @( posedge S_AXI_ACLK )
begin
if (mem_rden)
begin
mem_data_out[i][(mem_byte_index*8+7) -: 8] <= data_out;
end
end
end
end
endgenerate
//Output register or memory read data
always @( mem_data_out, axi_rvalid)
begin
if (axi_rvalid)
begin
// Read address mux
axi_rdata <= mem_data_out[0];
end
else
begin
axi_rdata <= 32'h00000000;
end
end
// Add user logic here
// User logic ends
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XOR3_SYMBOL_V
`define SKY130_FD_SC_HD__XOR3_SYMBOL_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__xor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__XOR3_SYMBOL_V
|
module vga_text(
clk25mhz,
hindex,
vindex,
standard,
emphasized,
background,
char_data,
font_data,
char_address,
font_address,
color
);
// Inputs
input wire clk25mhz;
input wire[9:0] hindex;
input wire[9:0] vindex;
input wire[13:0] font_data;
input wire[7:0] char_data;
input wire[3:0] standard;
input wire[3:0] emphasized;
input wire[3:0] background;
// Outputs
output wire[7:0] color;
output reg[9:0] font_address;
output reg[11:0] char_address = 12'b000000000000; // 0-3199
// State
reg[2:0] char_col = 3'b000; // 0-7, the column within a character
reg[3:0] char_row = 4'b0000; // 0-11, the row within a character
reg[2:0] dark = 3'b000;
reg[2:0] bright = 3'b000;
reg[3:0] foreground;
// Interconnect
wire[3:0] pixel_color;
// Combinational
assign color[7] = dark[2];
assign color[6] = bright[2];
assign color[5] = 0;
assign color[4] = dark[1];
assign color[3] = bright[1];
assign color[2] = 0;
assign color[1] = dark[0];
assign color[0] = bright[0];
assign pixel_color = (font_data[char_row] == 1) ? foreground : background;
// Process
always @ (posedge clk25mhz) begin: char_addressing
if(vindex >= 2 && vindex < 478) begin
if(hindex < 640) begin
// pixels 0-639, increment character index normally
if(char_col == 7) begin
char_col <= 0;
char_address <= char_address + 1;
end else begin
char_col <= char_col + 1;
end
end else if(hindex == 640) begin
if(char_row == 13) begin
// Last row, character was already incremented
char_row <= 0;
if(char_address == 2720) begin
char_address <= 0;
end
end else begin
// Not last row, move back to first char in line
char_row <= char_row + 1;
char_address <= char_address - 80;
end
end
end
end
always @ (posedge clk25mhz) begin: font_addressing
font_address <= {char_data[6:0], char_col};
foreground <= (char_data[7] == 1) ? emphasized : standard;
end
always @ (posedge clk25mhz) begin: indexes
if(hindex > 0 && hindex < 641 && vindex < 480) begin
dark <= pixel_color[2:0];
if(pixel_color[3] == 1) begin
if(pixel_color[2:0] == 0) begin
// Special case for bright gray (1000)
bright <= 3'b111; // (dark still 000)
end else begin
bright <= pixel_color[2:0];
end
end else begin
bright <= 3'b000;
end
end else begin
dark <= 3'b000;
bright <= 3'b000;
end
end
endmodule
|
// mbt 2-16-16
`include "bsg_defines.v"
module bsg_rocket_core_fsb
import bsg_fsb_packet::RingPacketType;
#(parameter nasti_destid_p="invalid"
, parameter htif_destid_p ="invalid"
, parameter htif_width_p = 16
, parameter ring_width_lp=$size(RingPacketType))
(input clk_i
, input reset_i
, input enable_i
// 0 = nasti, 1 = htif
, input [1:0] v_i
, input [1:0][ring_width_lp-1:0] data_i
, output [1:0] ready_o
, output [1:0] v_o
, output [1:0] [ring_width_lp-1:0] data_o
, input [1:0] yumi_i
);
wire w_ready, aw_ready, ar_ready, rd_ready, wr_ready;
bsg_nasti_write_data_channel_s w;
bsg_nasti_addr_channel_s ar;
bsg_nasti_addr_channel_s aw;
bsg_nasti_read_data_channel_s rd;
bsg_nasti_write_response_channel_s wr;
bsg_fsb_to_nasti_master_connector #(.destid_p(nasti_destid_p)) bsg_fsb_nasti_master
(.clk_i (clk_i )
,.reset_i (reset_i )
,.nasti_read_addr_ch_i (ar )
,.nasti_read_addr_ch_ready_o (ar_ready)
,.nasti_write_addr_ch_i (aw )
,.nasti_write_addr_ch_ready_o (aw_ready)
,.nasti_write_data_ch_i (w )
,.nasti_write_data_ch_ready_o (w_ready )
,.nasti_read_data_ch_o (rd )
,.nasti_read_data_ch_ready_i (rd_ready)
,.nasti_write_resp_ch_o (wr )
,.nasti_write_resp_ch_ready_i (rd_ready)
,.fsb_v_i (v_i [0])
,.fsb_data_i (data_i [0]) // --> from FSB
,.fsb_ready_o(ready_o[0])
,.fsb_v_o (v_o [0] )
,.fsb_data_o (data_o [0]) // --> to FSB
,.fsb_yumi_i (yumi_i [0])
);
wire htif_in_valid, htif_out_valid;
wire htif_in_ready, htif_out_ready;
wire [htif_width_p-1:0] htif_in_data;
wire [htif_width_p-1:0] htif_out_data;
bsg_fsb_to_htif_connector #(.destid_p(htif_destid_p)
,.htif_width_p(htif_width_p)
)
(.clk_i ( clk_i )
,.reset_i( reset_i )
// FSB interface
,.fsb_v_i ( v_i [1] )
,.fsb_data_i ( data_i [1] )
,.fsb_ready_o( ready_o[1] )
,.fsb_v_o ( v_o [1] )
,.fsb_data_o ( data_o [1] )
,.fsb_yumi_i ( yumi_i [1] )
// htif interface
,.htif_v_i ( htif_in_valid )
,.htif_data_i ( htif_in_data )
,.htif_ready_o ( htif_in_ready )
,.htif_v_o ( htif_out_valid )
,.htif_data_o ( htif_out_data )
,.htif_ready_o ( htif_out_ready )
);
top rocket
(.clk(clk_i)
,.reset(reset_i)
,.io_mem_0_ar_valid ( ar.v )
,.io_mem_0_ar_ready ( ar_ready )
,.io_mem_0_ar_bits_addr ( ar.addr )
,.io_mem_0_ar_bits_id ( ar.id )
,.io_mem_0_ar_bits_size ( ar.size )
,.io_mem_0_ar_bits_len ( ar.len )
,.io_mem_0_ar_bits_burst ()
,.io_mem_0_ar_bits_lock ()
,.io_mem_0_ar_bits_cache ()
,.io_mem_0_ar_bits_prot ()
,.io_mem_0_ar_bits_qos ()
,.io_mem_0_ar_bits_region ()
,.io_mem_0_ar_bits_user ()
,.io_mem_0_aw_valid ( aw.v )
,.io_mem_0_aw_ready ( aw_ready )
,.io_mem_0_aw_bits_addr ( aw.addr )
,.io_mem_0_aw_bits_id ( aw.id )
,.io_mem_0_aw_bits_size ( aw.size )
,.io_mem_0_aw_bits_len ( aw.len )
,.io_mem_0_aw_bits_burst ()
,.io_mem_0_aw_bits_lock ()
,.io_mem_0_aw_bits_cache ()
,.io_mem_0_aw_bits_prot ()
,.io_mem_0_aw_bits_qos ()
,.io_mem_0_aw_bits_region()
,.io_mem_0_aw_bits_user ()
,.io_mem_0_w_valid ( w.v )
,.io_mem_0_w_ready ( w_ready )
,.io_mem_0_w_bits_strb ( w.strb )
,.io_mem_0_w_bits_data ( w.data )
,.io_mem_0_w_bits_last ( w.last )
,.io_mem_0_w_bits_user ()
,.io_mem_0_r_valid ( r.v )
,.io_mem_0_r_ready ( r_ready )
,.io_mem_0_r_bits_resp ( r.resp )
,.io_mem_0_r_bits_id ( r.id )
,.io_mem_0_r_bits_data ( r.data )
,.io_mem_0_r_bits_last ( r.last )
,.io_mem_0_r_bits_user ( 1'b0 )
,.io_mem_0_b_valid ( wr.v )
,.io_mem_0_b_ready ( wr_ready )
,.io_mem_0_b_bits_resp ( wr.resp )
,.io_mem_0_b_bits_id ( wr.id )
,.io_mem_0_b_bits_user ( 1'b0 )
// we follow the "FPGA plan", because Berkeley "chip plan" currently broken
,.io_host_clk ()
,.io_host_clk_edge ()
,.io_host_debug_stats_csr ()
,.io_mem_backup_ctrl_en (1'b0)
,.io_mem_backup_ctrl_in_valid (1'b0)
,.io_mem_backup_ctrl_out_ready (1'b0)
,.io_mem_backup_ctrl_out_valid ()
// end "FPGA plan"
// this is the hostif; we need to attach it to the FSB as well
,.io_host_in_valid ( htif_in_valid )
,.io_host_in_ready ( htif_in_ready )
,.io_host_in_bits ( htif_in_bits )
,.io_host_out_valid ( htif_out_valid )
,.io_host_out_ready ( htif_out_ready )
,.io_host_out_bits ( htif_out_bits )
);
endmodule
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx0;
wire unxcomplemented_resetxx1;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 12] <= 1'b0;
sr[11 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_win_unchange (clock, reset, enable, start_event, test_expr, end_event, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input start_event;
input [width-1:0] test_expr;
input end_event;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_WIN_UNCHANGE";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/ovl_win_unchange_logic.v"
`endif
`ifdef OVL_SVA
`include "./sva05/ovl_win_unchange_logic.sv"
`endif
`ifdef OVL_PSL
`include "./psl05/assert_win_unchange_psl_logic.v"
`else
assign fire = {fire_cover, fire_xcheck, fire_2state};
`endmodule // ovl_win_unchange
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRBP_TB_V
`define SKY130_FD_SC_HS__DLRBP_TB_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlrbp.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 RESET_B = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 RESET_B = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 RESET_B = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 RESET_B = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hs__dlrbp dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .Q(Q), .Q_N(Q_N), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRBP_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFSBP_FUNCTIONAL_V
`define SKY130_FD_SC_MS__SDFSBP_FUNCTIONAL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps/sky130_fd_sc_ms__udp_dff_ps.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ms__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ms__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFSBP_FUNCTIONAL_V |
`timescale 1 ps / 1 ps
module onetswitch_top(
inout [14:0] DDR_addr,
inout [2:0] DDR_ba,
inout DDR_cas_n,
inout DDR_ck_n,
inout DDR_ck_p,
inout DDR_cke,
inout DDR_cs_n,
inout [3:0] DDR_dm,
inout [31:0] DDR_dq,
inout [3:0] DDR_dqs_n,
inout [3:0] DDR_dqs_p,
inout DDR_odt,
inout DDR_ras_n,
inout DDR_reset_n,
inout DDR_we_n,
inout FIXED_IO_ddr_vrn,
inout FIXED_IO_ddr_vrp,
inout [53:0] FIXED_IO_mio,
inout FIXED_IO_ps_clk,
inout FIXED_IO_ps_porb,
inout FIXED_IO_ps_srstb,
output gtx_pcie_txp ,
output gtx_pcie_txn ,
input gtx_pcie_rxp ,
input gtx_pcie_rxn ,
input gtx_pcie_clk_100m_p ,
input gtx_pcie_clk_100m_n ,
input pcie_wake_b ,
input pcie_clkreq_b ,
output pcie_perst_b ,
output pcie_w_disable_b ,
input ext_btn_rst ,
output [1:0] pl_led ,
output [1:0] pl_pmod
);
wire bd_fclk0_125m ;
wire bd_fclk1_75m ;
wire bd_fclk2_200m ;
wire bd_sys_rstn ;
wire pcie_dbg_clk ;
wire pcie_dbg_mmcm_lock ;
reg [23:0] cnt_0;
reg [23:0] cnt_1;
reg [23:0] cnt_2;
reg [23:0] cnt_3;
always @(posedge bd_fclk0_125m) begin
cnt_0 <= cnt_0 + 1'b1;
end
always @(posedge bd_fclk1_75m) begin
cnt_1 <= cnt_1 + 1'b1;
end
always @(posedge bd_fclk2_200m) begin
cnt_2 <= cnt_2 + 1'b1;
end
always @(posedge pcie_dbg_clk) begin
cnt_3 <= cnt_3 + 1'b1;
end
//assign pl_led[0] = cnt_0[23];
//assign pl_led[1] = cnt_1[23];
assign pl_led[0] = pcie_dbg_mmcm_lock;
assign pl_led[1] = bd_sys_rstn;
assign pl_pmod[0] = cnt_2[23];
assign pl_pmod[1] = cnt_3[23];
assign pcie_perst_b = bd_sys_rstn ;
assign pcie_w_disable_b = bd_sys_rstn ;
wire gtx_pcie_refclk;
IBUFDS_GTE2 refclk_ibuf_pcie (.O(gtx_pcie_refclk), .ODIV2(), .I(gtx_pcie_clk_100m_p), .CEB(1'b0), .IB(gtx_pcie_clk_100m_n));
onets_bd_wrapper i_onets_bd_wrapper(
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.pcie_7x_mgt_rxn ( gtx_pcie_rxn ),
.pcie_7x_mgt_rxp ( gtx_pcie_rxp ),
.pcie_7x_mgt_txn ( gtx_pcie_txn ),
.pcie_7x_mgt_txp ( gtx_pcie_txp ),
.pcie_msi_en ( 'b0),
.pcie_msi_gnt ( ),
.pcie_msi_req ( 'b0 ),
.pcie_msi_vec_num ( 'b0),
.pcie_msi_vec_width ( ),
.pcie_refclk ( gtx_pcie_refclk ),
.pcie_dbg_clk ( pcie_dbg_clk ),
.pcie_dbg_mmcm_lock ( pcie_dbg_mmcm_lock ),
.bd_fclk0_125m ( bd_fclk0_125m ),
.bd_fclk1_75m ( bd_fclk1_75m ),
.bd_fclk2_200m ( bd_fclk2_200m ),
.bd_sys_rstn ( bd_sys_rstn ),
.bd_ext_rstn ( ext_btn_rst )
);
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// A test of the +verilog1995ext+ and +verilog2001ext+ flags.
//
// This source code contains constructs that are valid in Verilog 2001 and
// SystemVerilog 2005/2009, but not in Verilog 1995. So it should fail if we
// set the language to be 1995, but not 2001.
//
// Compile only test, so no need for "All Finished" output.
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Jeremy Bennett.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [1:0] res;
// Instantiate the test
test test_i (// Outputs
.res (res[1:0]),
// Inputs
.clk (clk),
.in (1'b1));
endmodule
module test (// Outputs
res,
// Inputs
clk,
in
);
output reg [1:0] res;
input clk;
input in;
// This is a Verilog 2001 test
generate
genvar i;
for (i=0; i<2; i=i+1) begin
always @(posedge clk) begin
res[i:i] <= in;
end
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/26 16:07:35
// Design Name:
// Module Name: lab3_2_1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lab3_2_1(
input [7:0] v,
input en_in_n,
output reg [2:0] y,
output reg en_out,gs
);
always
@(v or en_in_n)
if(en_in_n == 1)
begin
y=7;
en_out = 1;
gs = 1;
end
else if(en_in_n == 0&&v == 255)
begin
y = 7;
en_out = 0;
gs = 1;
end
else if(en_in_n == 0&&v[7] == 0)
begin
y = 0;
en_out = 1;
gs = 0;
end
else if(en_in_n == 0&&v[6] == 0)
begin
y = 1;
en_out = 1;
gs = 0;
end
else if(en_in_n == 0&&v[5] == 0)
begin
y = 2;
en_out = 1;
gs = 0;
end
else if(en_in_n == 0&&v[4] == 0)
begin
y = 3;
en_out = 1;
gs = 0;
end
else if(en_in_n == 0&&v[3] == 0)
begin
y = 4;
en_out = 1;
gs = 0;
end
else if(en_in_n == 0&&v[2] == 0)
begin
y = 5;
en_out = 1;
gs = 0;
end
else if(en_in_n == 0&&v[1] == 0)
begin
y = 6;
en_out = 1;
gs = 0;
end
else if(en_in_n == 0&&v[0] == 0)
begin
y = 7;
en_out = 1;
gs = 0;
end
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_onchip_sram (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "soc_system_onchip_sram.hex";
output [ 31: 0] readdata;
input [ 16: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 90112,
the_altsyncram.numwords_a = 90112,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 17;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
// usb_system.v
// Generated using ACDS version 14.0 200 at 2014.10.01.12:57:13
`timescale 1 ps / 1 ps
module usb_system (
input wire clk_clk, // clk.clk
input wire reset_reset_n, // reset.reset_n
output wire [12:0] sdram_wire_addr, // sdram_wire.addr
output wire [1:0] sdram_wire_ba, // .ba
output wire sdram_wire_cas_n, // .cas_n
output wire sdram_wire_cke, // .cke
output wire sdram_wire_cs_n, // .cs_n
inout wire [31:0] sdram_wire_dq, // .dq
output wire [3:0] sdram_wire_dqm, // .dqm
output wire sdram_wire_ras_n, // .ras_n
output wire sdram_wire_we_n, // .we_n
output wire [7:0] keycode_export, // keycode.export
inout wire [15:0] usb_DATA, // usb.DATA
output wire [1:0] usb_ADDR, // .ADDR
output wire usb_RD_N, // .RD_N
output wire usb_WR_N, // .WR_N
output wire usb_CS_N, // .CS_N
output wire usb_RST_N, // .RST_N
input wire usb_INT, // .INT
output wire sdram_out_clk_clk, // sdram_out_clk.clk
output wire usb_out_clk_clk // usb_out_clk.clk
);
wire cpu_instruction_master_waitrequest; // mm_interconnect_0:cpu_instruction_master_waitrequest -> cpu:i_waitrequest
wire [28:0] cpu_instruction_master_address; // cpu:i_address -> mm_interconnect_0:cpu_instruction_master_address
wire cpu_instruction_master_read; // cpu:i_read -> mm_interconnect_0:cpu_instruction_master_read
wire [31:0] cpu_instruction_master_readdata; // mm_interconnect_0:cpu_instruction_master_readdata -> cpu:i_readdata
wire cpu_data_master_waitrequest; // mm_interconnect_0:cpu_data_master_waitrequest -> cpu:d_waitrequest
wire [31:0] cpu_data_master_writedata; // cpu:d_writedata -> mm_interconnect_0:cpu_data_master_writedata
wire [28:0] cpu_data_master_address; // cpu:d_address -> mm_interconnect_0:cpu_data_master_address
wire cpu_data_master_write; // cpu:d_write -> mm_interconnect_0:cpu_data_master_write
wire cpu_data_master_read; // cpu:d_read -> mm_interconnect_0:cpu_data_master_read
wire [31:0] cpu_data_master_readdata; // mm_interconnect_0:cpu_data_master_readdata -> cpu:d_readdata
wire cpu_data_master_debugaccess; // cpu:jtag_debug_module_debugaccess_to_roms -> mm_interconnect_0:cpu_data_master_debugaccess
wire [3:0] cpu_data_master_byteenable; // cpu:d_byteenable -> mm_interconnect_0:cpu_data_master_byteenable
wire mm_interconnect_0_cpu_jtag_debug_module_waitrequest; // cpu:jtag_debug_module_waitrequest -> mm_interconnect_0:cpu_jtag_debug_module_waitrequest
wire [31:0] mm_interconnect_0_cpu_jtag_debug_module_writedata; // mm_interconnect_0:cpu_jtag_debug_module_writedata -> cpu:jtag_debug_module_writedata
wire [8:0] mm_interconnect_0_cpu_jtag_debug_module_address; // mm_interconnect_0:cpu_jtag_debug_module_address -> cpu:jtag_debug_module_address
wire mm_interconnect_0_cpu_jtag_debug_module_write; // mm_interconnect_0:cpu_jtag_debug_module_write -> cpu:jtag_debug_module_write
wire mm_interconnect_0_cpu_jtag_debug_module_read; // mm_interconnect_0:cpu_jtag_debug_module_read -> cpu:jtag_debug_module_read
wire [31:0] mm_interconnect_0_cpu_jtag_debug_module_readdata; // cpu:jtag_debug_module_readdata -> mm_interconnect_0:cpu_jtag_debug_module_readdata
wire mm_interconnect_0_cpu_jtag_debug_module_debugaccess; // mm_interconnect_0:cpu_jtag_debug_module_debugaccess -> cpu:jtag_debug_module_debugaccess
wire [3:0] mm_interconnect_0_cpu_jtag_debug_module_byteenable; // mm_interconnect_0:cpu_jtag_debug_module_byteenable -> cpu:jtag_debug_module_byteenable
wire mm_interconnect_0_sdram_s1_waitrequest; // sdram:za_waitrequest -> mm_interconnect_0:sdram_s1_waitrequest
wire [31:0] mm_interconnect_0_sdram_s1_writedata; // mm_interconnect_0:sdram_s1_writedata -> sdram:az_data
wire [24:0] mm_interconnect_0_sdram_s1_address; // mm_interconnect_0:sdram_s1_address -> sdram:az_addr
wire mm_interconnect_0_sdram_s1_chipselect; // mm_interconnect_0:sdram_s1_chipselect -> sdram:az_cs
wire mm_interconnect_0_sdram_s1_write; // mm_interconnect_0:sdram_s1_write -> sdram:az_wr_n
wire mm_interconnect_0_sdram_s1_read; // mm_interconnect_0:sdram_s1_read -> sdram:az_rd_n
wire [31:0] mm_interconnect_0_sdram_s1_readdata; // sdram:za_data -> mm_interconnect_0:sdram_s1_readdata
wire mm_interconnect_0_sdram_s1_readdatavalid; // sdram:za_valid -> mm_interconnect_0:sdram_s1_readdatavalid
wire [3:0] mm_interconnect_0_sdram_s1_byteenable; // mm_interconnect_0:sdram_s1_byteenable -> sdram:az_be_n
wire [31:0] mm_interconnect_0_clocks_pll_slave_writedata; // mm_interconnect_0:clocks_pll_slave_writedata -> clocks:writedata
wire [1:0] mm_interconnect_0_clocks_pll_slave_address; // mm_interconnect_0:clocks_pll_slave_address -> clocks:address
wire mm_interconnect_0_clocks_pll_slave_write; // mm_interconnect_0:clocks_pll_slave_write -> clocks:write
wire mm_interconnect_0_clocks_pll_slave_read; // mm_interconnect_0:clocks_pll_slave_read -> clocks:read
wire [31:0] mm_interconnect_0_clocks_pll_slave_readdata; // clocks:readdata -> mm_interconnect_0:clocks_pll_slave_readdata
wire [31:0] mm_interconnect_0_keycode_s1_writedata; // mm_interconnect_0:keycode_s1_writedata -> keycode:writedata
wire [1:0] mm_interconnect_0_keycode_s1_address; // mm_interconnect_0:keycode_s1_address -> keycode:address
wire mm_interconnect_0_keycode_s1_chipselect; // mm_interconnect_0:keycode_s1_chipselect -> keycode:chipselect
wire mm_interconnect_0_keycode_s1_write; // mm_interconnect_0:keycode_s1_write -> keycode:write_n
wire [31:0] mm_interconnect_0_keycode_s1_readdata; // keycode:readdata -> mm_interconnect_0:keycode_s1_readdata
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest; // jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
wire [0:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata; // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
wire mm_interconnect_0_clock_crossing_io_s0_waitrequest; // clock_crossing_io:s0_waitrequest -> mm_interconnect_0:clock_crossing_io_s0_waitrequest
wire [0:0] mm_interconnect_0_clock_crossing_io_s0_burstcount; // mm_interconnect_0:clock_crossing_io_s0_burstcount -> clock_crossing_io:s0_burstcount
wire [31:0] mm_interconnect_0_clock_crossing_io_s0_writedata; // mm_interconnect_0:clock_crossing_io_s0_writedata -> clock_crossing_io:s0_writedata
wire [21:0] mm_interconnect_0_clock_crossing_io_s0_address; // mm_interconnect_0:clock_crossing_io_s0_address -> clock_crossing_io:s0_address
wire mm_interconnect_0_clock_crossing_io_s0_write; // mm_interconnect_0:clock_crossing_io_s0_write -> clock_crossing_io:s0_write
wire mm_interconnect_0_clock_crossing_io_s0_read; // mm_interconnect_0:clock_crossing_io_s0_read -> clock_crossing_io:s0_read
wire [31:0] mm_interconnect_0_clock_crossing_io_s0_readdata; // clock_crossing_io:s0_readdata -> mm_interconnect_0:clock_crossing_io_s0_readdata
wire mm_interconnect_0_clock_crossing_io_s0_debugaccess; // mm_interconnect_0:clock_crossing_io_s0_debugaccess -> clock_crossing_io:s0_debugaccess
wire mm_interconnect_0_clock_crossing_io_s0_readdatavalid; // clock_crossing_io:s0_readdatavalid -> mm_interconnect_0:clock_crossing_io_s0_readdatavalid
wire [3:0] mm_interconnect_0_clock_crossing_io_s0_byteenable; // mm_interconnect_0:clock_crossing_io_s0_byteenable -> clock_crossing_io:s0_byteenable
wire [0:0] clock_crossing_io_m0_burstcount; // clock_crossing_io:m0_burstcount -> mm_interconnect_1:clock_crossing_io_m0_burstcount
wire clock_crossing_io_m0_waitrequest; // mm_interconnect_1:clock_crossing_io_m0_waitrequest -> clock_crossing_io:m0_waitrequest
wire [21:0] clock_crossing_io_m0_address; // clock_crossing_io:m0_address -> mm_interconnect_1:clock_crossing_io_m0_address
wire [31:0] clock_crossing_io_m0_writedata; // clock_crossing_io:m0_writedata -> mm_interconnect_1:clock_crossing_io_m0_writedata
wire clock_crossing_io_m0_write; // clock_crossing_io:m0_write -> mm_interconnect_1:clock_crossing_io_m0_write
wire clock_crossing_io_m0_read; // clock_crossing_io:m0_read -> mm_interconnect_1:clock_crossing_io_m0_read
wire [31:0] clock_crossing_io_m0_readdata; // mm_interconnect_1:clock_crossing_io_m0_readdata -> clock_crossing_io:m0_readdata
wire clock_crossing_io_m0_debugaccess; // clock_crossing_io:m0_debugaccess -> mm_interconnect_1:clock_crossing_io_m0_debugaccess
wire [3:0] clock_crossing_io_m0_byteenable; // clock_crossing_io:m0_byteenable -> mm_interconnect_1:clock_crossing_io_m0_byteenable
wire clock_crossing_io_m0_readdatavalid; // mm_interconnect_1:clock_crossing_io_m0_readdatavalid -> clock_crossing_io:m0_readdatavalid
wire [31:0] mm_interconnect_1_cy7c67200_if_0_hpi_writedata; // mm_interconnect_1:CY7C67200_IF_0_hpi_writedata -> CY7C67200_IF_0:iDATA
wire [1:0] mm_interconnect_1_cy7c67200_if_0_hpi_address; // mm_interconnect_1:CY7C67200_IF_0_hpi_address -> CY7C67200_IF_0:iADDR
wire mm_interconnect_1_cy7c67200_if_0_hpi_chipselect; // mm_interconnect_1:CY7C67200_IF_0_hpi_chipselect -> CY7C67200_IF_0:iCS_N
wire mm_interconnect_1_cy7c67200_if_0_hpi_write; // mm_interconnect_1:CY7C67200_IF_0_hpi_write -> CY7C67200_IF_0:iWR_N
wire mm_interconnect_1_cy7c67200_if_0_hpi_read; // mm_interconnect_1:CY7C67200_IF_0_hpi_read -> CY7C67200_IF_0:iRD_N
wire [31:0] mm_interconnect_1_cy7c67200_if_0_hpi_readdata; // CY7C67200_IF_0:oDATA -> mm_interconnect_1:CY7C67200_IF_0_hpi_readdata
wire irq_mapper_receiver0_irq; // jtag_uart:av_irq -> irq_mapper:receiver0_irq
wire [31:0] cpu_d_irq_irq; // irq_mapper:sender_irq -> cpu:d_irq
wire irq_mapper_receiver1_irq; // irq_synchronizer:sender_irq -> irq_mapper:receiver1_irq
wire [0:0] irq_synchronizer_receiver_irq; // CY7C67200_IF_0:oINT -> irq_synchronizer:receiver_irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [mm_interconnect_0:sdram_reset_reset_bridge_in_reset_reset, sdram:reset_n]
wire cpu_jtag_debug_module_reset_reset; // cpu:jtag_debug_module_resetrequest -> [rst_controller:reset_in1, rst_controller_001:reset_in1, rst_controller_002:reset_in1]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [clock_crossing_io:s0_reset, clocks:reset, cpu:reset_n, irq_mapper:reset, irq_synchronizer:sender_reset, jtag_uart:rst_n, keycode:reset_n, mm_interconnect_0:cpu_reset_n_reset_bridge_in_reset_reset, rst_translator:in_reset]
wire rst_controller_001_reset_out_reset_req; // rst_controller_001:reset_req -> [cpu:reset_req, rst_translator:reset_req_in]
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> [CY7C67200_IF_0:iRST_N, clock_crossing_io:m0_reset, irq_synchronizer:receiver_reset, mm_interconnect_1:clock_crossing_io_m0_reset_reset_bridge_in_reset_reset]
usb_system_sdram sdram (
.clk (sdram_out_clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.az_addr (mm_interconnect_0_sdram_s1_address), // s1.address
.az_be_n (~mm_interconnect_0_sdram_s1_byteenable), // .byteenable_n
.az_cs (mm_interconnect_0_sdram_s1_chipselect), // .chipselect
.az_data (mm_interconnect_0_sdram_s1_writedata), // .writedata
.az_rd_n (~mm_interconnect_0_sdram_s1_read), // .read_n
.az_wr_n (~mm_interconnect_0_sdram_s1_write), // .write_n
.za_data (mm_interconnect_0_sdram_s1_readdata), // .readdata
.za_valid (mm_interconnect_0_sdram_s1_readdatavalid), // .readdatavalid
.za_waitrequest (mm_interconnect_0_sdram_s1_waitrequest), // .waitrequest
.zs_addr (sdram_wire_addr), // wire.export
.zs_ba (sdram_wire_ba), // .export
.zs_cas_n (sdram_wire_cas_n), // .export
.zs_cke (sdram_wire_cke), // .export
.zs_cs_n (sdram_wire_cs_n), // .export
.zs_dq (sdram_wire_dq), // .export
.zs_dqm (sdram_wire_dqm), // .export
.zs_ras_n (sdram_wire_ras_n), // .export
.zs_we_n (sdram_wire_we_n) // .export
);
usb_system_jtag_uart jtag_uart (
.clk (clk_clk), // clk.clk
.rst_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver0_irq) // irq.irq
);
usb_system_cpu cpu (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset_n.reset_n
.reset_req (rst_controller_001_reset_out_reset_req), // .reset_req
.d_address (cpu_data_master_address), // data_master.address
.d_byteenable (cpu_data_master_byteenable), // .byteenable
.d_read (cpu_data_master_read), // .read
.d_readdata (cpu_data_master_readdata), // .readdata
.d_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.d_write (cpu_data_master_write), // .write
.d_writedata (cpu_data_master_writedata), // .writedata
.jtag_debug_module_debugaccess_to_roms (cpu_data_master_debugaccess), // .debugaccess
.i_address (cpu_instruction_master_address), // instruction_master.address
.i_read (cpu_instruction_master_read), // .read
.i_readdata (cpu_instruction_master_readdata), // .readdata
.i_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.d_irq (cpu_d_irq_irq), // d_irq.irq
.jtag_debug_module_resetrequest (cpu_jtag_debug_module_reset_reset), // jtag_debug_module_reset.reset
.jtag_debug_module_address (mm_interconnect_0_cpu_jtag_debug_module_address), // jtag_debug_module.address
.jtag_debug_module_byteenable (mm_interconnect_0_cpu_jtag_debug_module_byteenable), // .byteenable
.jtag_debug_module_debugaccess (mm_interconnect_0_cpu_jtag_debug_module_debugaccess), // .debugaccess
.jtag_debug_module_read (mm_interconnect_0_cpu_jtag_debug_module_read), // .read
.jtag_debug_module_readdata (mm_interconnect_0_cpu_jtag_debug_module_readdata), // .readdata
.jtag_debug_module_waitrequest (mm_interconnect_0_cpu_jtag_debug_module_waitrequest), // .waitrequest
.jtag_debug_module_write (mm_interconnect_0_cpu_jtag_debug_module_write), // .write
.jtag_debug_module_writedata (mm_interconnect_0_cpu_jtag_debug_module_writedata), // .writedata
.no_ci_readra () // custom_instruction_master.readra
);
usb_system_clocks clocks (
.clk (clk_clk), // inclk_interface.clk
.reset (rst_controller_001_reset_out_reset), // inclk_interface_reset.reset
.read (mm_interconnect_0_clocks_pll_slave_read), // pll_slave.read
.write (mm_interconnect_0_clocks_pll_slave_write), // .write
.address (mm_interconnect_0_clocks_pll_slave_address), // .address
.readdata (mm_interconnect_0_clocks_pll_slave_readdata), // .readdata
.writedata (mm_interconnect_0_clocks_pll_slave_writedata), // .writedata
.c0 (sdram_out_clk_clk), // c0.clk
.c1 (usb_out_clk_clk), // c1.clk
.areset (), // areset_conduit.export
.locked (), // locked_conduit.export
.phasedone () // phasedone_conduit.export
);
usb_system_keycode keycode (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_keycode_s1_address), // s1.address
.write_n (~mm_interconnect_0_keycode_s1_write), // .write_n
.writedata (mm_interconnect_0_keycode_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_keycode_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_keycode_s1_readdata), // .readdata
.out_port (keycode_export) // external_connection.export
);
CY7C67200_IF cy7c67200_if_0 (
.oDATA (mm_interconnect_1_cy7c67200_if_0_hpi_readdata), // hpi.readdata
.iADDR (mm_interconnect_1_cy7c67200_if_0_hpi_address), // .address
.iRD_N (~mm_interconnect_1_cy7c67200_if_0_hpi_read), // .read_n
.iWR_N (~mm_interconnect_1_cy7c67200_if_0_hpi_write), // .write_n
.iCS_N (~mm_interconnect_1_cy7c67200_if_0_hpi_chipselect), // .chipselect_n
.iDATA (mm_interconnect_1_cy7c67200_if_0_hpi_writedata), // .writedata
.iCLK (usb_out_clk_clk), // clock_sink.clk
.iRST_N (~rst_controller_002_reset_out_reset), // clock_sink_reset.reset_n
.oINT (irq_synchronizer_receiver_irq), // interrupt_sender.irq
.HPI_DATA (usb_DATA), // conduit_end.export
.HPI_ADDR (usb_ADDR), // .export
.HPI_RD_N (usb_RD_N), // .export
.HPI_WR_N (usb_WR_N), // .export
.HPI_CS_N (usb_CS_N), // .export
.HPI_RST_N (usb_RST_N), // .export
.HPI_INT (usb_INT) // .export
);
altera_avalon_mm_clock_crossing_bridge #(
.DATA_WIDTH (32),
.SYMBOL_WIDTH (8),
.HDL_ADDR_WIDTH (22),
.BURSTCOUNT_WIDTH (1),
.COMMAND_FIFO_DEPTH (32),
.RESPONSE_FIFO_DEPTH (256),
.MASTER_SYNC_DEPTH (3),
.SLAVE_SYNC_DEPTH (3)
) clock_crossing_io (
.m0_clk (usb_out_clk_clk), // m0_clk.clk
.m0_reset (rst_controller_002_reset_out_reset), // m0_reset.reset
.s0_clk (clk_clk), // s0_clk.clk
.s0_reset (rst_controller_001_reset_out_reset), // s0_reset.reset
.s0_waitrequest (mm_interconnect_0_clock_crossing_io_s0_waitrequest), // s0.waitrequest
.s0_readdata (mm_interconnect_0_clock_crossing_io_s0_readdata), // .readdata
.s0_readdatavalid (mm_interconnect_0_clock_crossing_io_s0_readdatavalid), // .readdatavalid
.s0_burstcount (mm_interconnect_0_clock_crossing_io_s0_burstcount), // .burstcount
.s0_writedata (mm_interconnect_0_clock_crossing_io_s0_writedata), // .writedata
.s0_address (mm_interconnect_0_clock_crossing_io_s0_address), // .address
.s0_write (mm_interconnect_0_clock_crossing_io_s0_write), // .write
.s0_read (mm_interconnect_0_clock_crossing_io_s0_read), // .read
.s0_byteenable (mm_interconnect_0_clock_crossing_io_s0_byteenable), // .byteenable
.s0_debugaccess (mm_interconnect_0_clock_crossing_io_s0_debugaccess), // .debugaccess
.m0_waitrequest (clock_crossing_io_m0_waitrequest), // m0.waitrequest
.m0_readdata (clock_crossing_io_m0_readdata), // .readdata
.m0_readdatavalid (clock_crossing_io_m0_readdatavalid), // .readdatavalid
.m0_burstcount (clock_crossing_io_m0_burstcount), // .burstcount
.m0_writedata (clock_crossing_io_m0_writedata), // .writedata
.m0_address (clock_crossing_io_m0_address), // .address
.m0_write (clock_crossing_io_m0_write), // .write
.m0_read (clock_crossing_io_m0_read), // .read
.m0_byteenable (clock_crossing_io_m0_byteenable), // .byteenable
.m0_debugaccess (clock_crossing_io_m0_debugaccess) // .debugaccess
);
usb_system_mm_interconnect_0 mm_interconnect_0 (
.clk_clk_clk (clk_clk), // clk_clk.clk
.clocks_c0_clk (sdram_out_clk_clk), // clocks_c0.clk
.cpu_reset_n_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // cpu_reset_n_reset_bridge_in_reset.reset
.sdram_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // sdram_reset_reset_bridge_in_reset.reset
.cpu_data_master_address (cpu_data_master_address), // cpu_data_master.address
.cpu_data_master_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.cpu_data_master_byteenable (cpu_data_master_byteenable), // .byteenable
.cpu_data_master_read (cpu_data_master_read), // .read
.cpu_data_master_readdata (cpu_data_master_readdata), // .readdata
.cpu_data_master_write (cpu_data_master_write), // .write
.cpu_data_master_writedata (cpu_data_master_writedata), // .writedata
.cpu_data_master_debugaccess (cpu_data_master_debugaccess), // .debugaccess
.cpu_instruction_master_address (cpu_instruction_master_address), // cpu_instruction_master.address
.cpu_instruction_master_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.cpu_instruction_master_read (cpu_instruction_master_read), // .read
.cpu_instruction_master_readdata (cpu_instruction_master_readdata), // .readdata
.clock_crossing_io_s0_address (mm_interconnect_0_clock_crossing_io_s0_address), // clock_crossing_io_s0.address
.clock_crossing_io_s0_write (mm_interconnect_0_clock_crossing_io_s0_write), // .write
.clock_crossing_io_s0_read (mm_interconnect_0_clock_crossing_io_s0_read), // .read
.clock_crossing_io_s0_readdata (mm_interconnect_0_clock_crossing_io_s0_readdata), // .readdata
.clock_crossing_io_s0_writedata (mm_interconnect_0_clock_crossing_io_s0_writedata), // .writedata
.clock_crossing_io_s0_burstcount (mm_interconnect_0_clock_crossing_io_s0_burstcount), // .burstcount
.clock_crossing_io_s0_byteenable (mm_interconnect_0_clock_crossing_io_s0_byteenable), // .byteenable
.clock_crossing_io_s0_readdatavalid (mm_interconnect_0_clock_crossing_io_s0_readdatavalid), // .readdatavalid
.clock_crossing_io_s0_waitrequest (mm_interconnect_0_clock_crossing_io_s0_waitrequest), // .waitrequest
.clock_crossing_io_s0_debugaccess (mm_interconnect_0_clock_crossing_io_s0_debugaccess), // .debugaccess
.clocks_pll_slave_address (mm_interconnect_0_clocks_pll_slave_address), // clocks_pll_slave.address
.clocks_pll_slave_write (mm_interconnect_0_clocks_pll_slave_write), // .write
.clocks_pll_slave_read (mm_interconnect_0_clocks_pll_slave_read), // .read
.clocks_pll_slave_readdata (mm_interconnect_0_clocks_pll_slave_readdata), // .readdata
.clocks_pll_slave_writedata (mm_interconnect_0_clocks_pll_slave_writedata), // .writedata
.cpu_jtag_debug_module_address (mm_interconnect_0_cpu_jtag_debug_module_address), // cpu_jtag_debug_module.address
.cpu_jtag_debug_module_write (mm_interconnect_0_cpu_jtag_debug_module_write), // .write
.cpu_jtag_debug_module_read (mm_interconnect_0_cpu_jtag_debug_module_read), // .read
.cpu_jtag_debug_module_readdata (mm_interconnect_0_cpu_jtag_debug_module_readdata), // .readdata
.cpu_jtag_debug_module_writedata (mm_interconnect_0_cpu_jtag_debug_module_writedata), // .writedata
.cpu_jtag_debug_module_byteenable (mm_interconnect_0_cpu_jtag_debug_module_byteenable), // .byteenable
.cpu_jtag_debug_module_waitrequest (mm_interconnect_0_cpu_jtag_debug_module_waitrequest), // .waitrequest
.cpu_jtag_debug_module_debugaccess (mm_interconnect_0_cpu_jtag_debug_module_debugaccess), // .debugaccess
.jtag_uart_avalon_jtag_slave_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // jtag_uart_avalon_jtag_slave.address
.jtag_uart_avalon_jtag_slave_write (mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write
.jtag_uart_avalon_jtag_slave_read (mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read
.jtag_uart_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.jtag_uart_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.jtag_uart_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.jtag_uart_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
.keycode_s1_address (mm_interconnect_0_keycode_s1_address), // keycode_s1.address
.keycode_s1_write (mm_interconnect_0_keycode_s1_write), // .write
.keycode_s1_readdata (mm_interconnect_0_keycode_s1_readdata), // .readdata
.keycode_s1_writedata (mm_interconnect_0_keycode_s1_writedata), // .writedata
.keycode_s1_chipselect (mm_interconnect_0_keycode_s1_chipselect), // .chipselect
.sdram_s1_address (mm_interconnect_0_sdram_s1_address), // sdram_s1.address
.sdram_s1_write (mm_interconnect_0_sdram_s1_write), // .write
.sdram_s1_read (mm_interconnect_0_sdram_s1_read), // .read
.sdram_s1_readdata (mm_interconnect_0_sdram_s1_readdata), // .readdata
.sdram_s1_writedata (mm_interconnect_0_sdram_s1_writedata), // .writedata
.sdram_s1_byteenable (mm_interconnect_0_sdram_s1_byteenable), // .byteenable
.sdram_s1_readdatavalid (mm_interconnect_0_sdram_s1_readdatavalid), // .readdatavalid
.sdram_s1_waitrequest (mm_interconnect_0_sdram_s1_waitrequest), // .waitrequest
.sdram_s1_chipselect (mm_interconnect_0_sdram_s1_chipselect) // .chipselect
);
usb_system_mm_interconnect_1 mm_interconnect_1 (
.clocks_c1_clk (usb_out_clk_clk), // clocks_c1.clk
.clock_crossing_io_m0_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset), // clock_crossing_io_m0_reset_reset_bridge_in_reset.reset
.clock_crossing_io_m0_address (clock_crossing_io_m0_address), // clock_crossing_io_m0.address
.clock_crossing_io_m0_waitrequest (clock_crossing_io_m0_waitrequest), // .waitrequest
.clock_crossing_io_m0_burstcount (clock_crossing_io_m0_burstcount), // .burstcount
.clock_crossing_io_m0_byteenable (clock_crossing_io_m0_byteenable), // .byteenable
.clock_crossing_io_m0_read (clock_crossing_io_m0_read), // .read
.clock_crossing_io_m0_readdata (clock_crossing_io_m0_readdata), // .readdata
.clock_crossing_io_m0_readdatavalid (clock_crossing_io_m0_readdatavalid), // .readdatavalid
.clock_crossing_io_m0_write (clock_crossing_io_m0_write), // .write
.clock_crossing_io_m0_writedata (clock_crossing_io_m0_writedata), // .writedata
.clock_crossing_io_m0_debugaccess (clock_crossing_io_m0_debugaccess), // .debugaccess
.CY7C67200_IF_0_hpi_address (mm_interconnect_1_cy7c67200_if_0_hpi_address), // CY7C67200_IF_0_hpi.address
.CY7C67200_IF_0_hpi_write (mm_interconnect_1_cy7c67200_if_0_hpi_write), // .write
.CY7C67200_IF_0_hpi_read (mm_interconnect_1_cy7c67200_if_0_hpi_read), // .read
.CY7C67200_IF_0_hpi_readdata (mm_interconnect_1_cy7c67200_if_0_hpi_readdata), // .readdata
.CY7C67200_IF_0_hpi_writedata (mm_interconnect_1_cy7c67200_if_0_hpi_writedata), // .writedata
.CY7C67200_IF_0_hpi_chipselect (mm_interconnect_1_cy7c67200_if_0_hpi_chipselect) // .chipselect
);
usb_system_irq_mapper irq_mapper (
.clk (clk_clk), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.sender_irq (cpu_d_irq_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer (
.receiver_clk (usb_out_clk_clk), // receiver_clk.clk
.sender_clk (clk_clk), // sender_clk.clk
.receiver_reset (rst_controller_002_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_001_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_receiver1_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (sdram_out_clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_001_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (usb_out_clk_clk), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
// Copyright 2018 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// Verilog implementation of the Econet wire protocol.
// This is traditionally implemented using a MC68B54 chip:
// https://www.heyrick.co.uk/econet/mc6854fixed.pdf
// All Econet transactions use a 'four way handshake':
//
// Scout frame:
// A sends: <flag> <B> <B> <A> <A> <ctrl> <port> <CRC> <CRC> <flag>
//
// Ack frame:
// B sends: <flag> <flag> <flag> ... (while busy)
// then: <flag> <A> <A> <B> <B> <CRC> <CRC> <flag>
//
// Data frame:
// A sends: <flag> <B> <B> <A> <A> <data...> <CRC> <CRC> <flag>
//
// Second ack frame:
// B sends: <flag> <A> <A> <B> <B> <CRC> <CRC> <flag>
// Bytes are sent LSB-first.
// Zero insertion/deletion: after transmitting 11111, a zero is inserted.
// After receiving 11111, a zero is deleted.
// 01111110 = flag
// 1111111 = abort (and line idles at 1)
// We communicate with the MCU over a synchronous serial interface, which in
// practice is half-duplex because there's no need to transmit information in
// the opposite direction from the Econet line.
// mcu_is_transmitting line selects the direction. When it transitions,
// everything gets reset.
// Right now this uses 64/72 MCs in an XC9572XL device.
module econet(
// to MCU
input wire clock_24m, // 24 MHz serial clock
output reg serial_cpld_to_mcu = 1'b1, // USRT txd (connect to MCU's rxd)
input wire serial_mcu_to_cpld, // USRT rxd (connect to MCU's txd)
input wire mcu_is_transmitting, // direction select for the USRT; 1=mcu transmitting, 0 = cpld can transmit
output reg outputting_frame = 1'b0, // 1 when we're sending a frame, 0 when idle or underrun
output wire serial_buffer_empty, // 1 when the MCU can send a new byte
input wire drive_econet_clock, // 1 when the MCU wants us to drive econet_clock_D with econet_clock_from_mcu
input wire econet_clock_from_mcu, // clock signal from MCU to copy to econet_clock_D
// to sn65c1168 dual differential transceiver
input wire econet_data_R, // received data
output wire econet_data_D, // transmitted data
output wire econet_data_DE, // 1 to transmit data, 0 otherwise
input wire econet_clock_R, // received clock
output wire econet_clock_D, // transmitted clock
output wire econet_clock_DE, // 1 to transmit clock, 0 otherwise
// to collision detect circuit
input wire collision_detect,
// Econet module pins, left to right on bottom of board
// These are currently used to output debug signals
input wire nNETINT,
input wire RnW,
input wire nADLC,
input wire PHI2,
input wire A0,
input wire A1,
output wire [7:0] D, // D0..D7 from left to right
output wire nRESET,
// ... followed by GND, and 5V is in the bottom right corner
// Dummy inputs for unused pins that connect to the MCU
input wire PA18,
input wire PA19,
input wire PA22,
input wire PA23
);
// So... how should this be implemented in the CPLD? Matching the input for
// the 'flag' and 'abort' codes is fairly straightforward.
// --- INPUT SYNC ---
reg [2:0] econet_clock_sync = 3'b0;
reg [2:0] econet_data_sync = 3'b0;
reg [2:0] mcu_is_transmitting_sync = 3'b0;
// --- SERIAL PORT ---
reg [9:0] serial_shifter = 10'b1111111111; // Start bit + 9 data bits
reg [3:0] serial_bit_count = 4'b0; // Send/receive countdown from 11 (start + 9 + stop)
reg serial_input_buffer_full = 1'b0;
assign serial_buffer_empty = !serial_input_buffer_full && (serial_bit_count == 0);
// --- ECONET ---
// The ATSAMD21 USRT supports 9-bit words, so the CPLD can send 9'b0xxxxxxxx
// for a data word and 9'b1xxxxxxxx for anything else (9'b101111110 for a
// flag, 9'b1xxxxxxxx for an abort or any garbage). When the MCU wants to
// send a flag, it can send 9'b101111110 ("send raw 01111110") and when it
// wants to send data it can send 9'b011111111 (which results in 111110111
// actually getting sent).
// Implement bit stuffing by generally thinking in bytes but having a 'raw'
// flag that is sent as a 9th bit from the MCU.
reg [2:0] econet_bit_count = 0; // Bit # we're currently sending or receiving
reg [2:0] econet_ones_count = 0; // # of ones seen in a row (0-7)
reg [7:0] econet_shifter = 0; // 8-bit output shift register
reg econet_output_raw = 1'b0; // If 1, don't bit stuff
reg econet_transmitting = 1'b0; // Flag to say we're currently outputting from the shift register
reg econet_initiate_abort = 1'b0; // Something went wrong: send an abort (raw 0xFF)
wire econet_clock_out;
reg econet_data_out = 1'b1; // Passed through to econet_data_D
// rev1 PCB is buggy and has data input and clock input and output inverted.
// (Data output is the only correct one.)
reg buggy_rev1_pcb = 1'b1;
assign econet_data_DE = outputting_frame;
assign econet_data_D = econet_data_out;
assign econet_clock_DE = drive_econet_clock;
assign econet_clock_out = econet_clock_from_mcu;
assign econet_clock_D = econet_clock_out ^ buggy_rev1_pcb;
wire econet_clock;
assign econet_clock = drive_econet_clock ? econet_clock_from_mcu : (econet_clock_R ^ buggy_rev1_pcb);
// A bunch of debug outputs using the Econet module pins along the bottom of the board
assign nRESET = mcu_is_transmitting_sync[2]; //DEBUG
assign D[7] = serial_mcu_to_cpld; //DEBUG
assign D[6] = serial_cpld_to_mcu; //serial_buffer_empty; //DEBUG
assign D[5] = serial_input_buffer_full; //DEBUG
assign D[4] = econet_initiate_abort; //DEBUG
assign D[3] = econet_transmitting; //DEBUG
assign D[2] = outputting_frame; //DEBUG
always @(negedge clock_24m) begin
// FALLING edge of serial clock: update value on serial_cpld_to_mcu
serial_cpld_to_mcu <= mcu_is_transmitting_sync[2] ? 1'b1 : serial_shifter[0];
// if (!mcu_is_transmitting && serial_bit_count != 0) $display("outputting bit to serial port: %b", serial_shifter[0]);
end
always @(posedge clock_24m) begin
// RISING edge of serial clock: sample value on serial_mcu_to_cpld
// To save on CPLD space, the entire system is half-duplex, driven by the
// mcu_is_transmitting line. When this line changes, the whole system is
// reset, throwing away any half-transmitted or half-received data.
// Synchronize signals from the Econet line. tRDS = 50ns and tRDH = 60ns,
// and our clock period is 42ns, so we'll have a tight enough sample.
econet_clock_sync <= {econet_clock_sync[1:0], econet_clock};
econet_data_sync <= {econet_data_sync[1:0], (econet_data_R ^ buggy_rev1_pcb)};
mcu_is_transmitting_sync <= {mcu_is_transmitting_sync[1:0], mcu_is_transmitting};
if (mcu_is_transmitting_sync[2] != mcu_is_transmitting_sync[1]) begin // DIRECTION CHANGE
serial_bit_count <= 0;
serial_input_buffer_full <= 1'b0;
serial_shifter[0] <= 1'b1;
econet_initiate_abort <= 1'b0;
econet_transmitting <= 1'b0;
econet_bit_count <= 0;
econet_ones_count <= 7;
end else if (mcu_is_transmitting_sync[2] == 1'b1) begin // RECEIVE FROM MCU, TRANSMIT TO ECONET
// TODO figure out if we need to synchronize mcu_is_transmitting, or
// if it's already synchronous w.r.t the USRT clock
// SERIAL PORT RECEIVER
if (serial_bit_count == 0) begin
if (serial_mcu_to_cpld == 1'b0) begin
// Received a start bit; start a transfer
serial_bit_count <= 10;
end
end else if (serial_bit_count == 1) begin
// Receiving a stop bit
if (serial_mcu_to_cpld == 1'b1) begin
// Received data!
if (serial_input_buffer_full == 1'b1) begin
// Buffer overrun; abort the frame.
econet_initiate_abort <= 1'b1;
end else begin
serial_input_buffer_full <= 1'b1;
end
end else begin
// Frame error; ignore byte and crash
//TODO
end
serial_bit_count <= 0;
end else begin
// Receiving 9 bits from the serial port, LSB-first
serial_shifter <= {serial_mcu_to_cpld, serial_shifter[8:1]};
serial_bit_count <= serial_bit_count - 1;
end
// COPY FROM SERIAL PORT TO ECONET REGISTER
// Push a byte into the output shift register if necessary
if (econet_transmitting == 1'b0) begin
if (econet_initiate_abort == 1'b1) begin
// We're sending an abort, probably because we got a buffer
// overrun (on receiption). This will cancel the current frame.
// If we get a buffer underrun on transmission, we probably
// just bomb out and let the line idle state abort our frame.
serial_input_buffer_full <= 1'b0;
outputting_frame <= 1'b1;
econet_transmitting <= 1'b1;
econet_output_raw <= 1'b1;
econet_shifter <= 8'b11111111;
econet_bit_count <= 3'b0;
end else if (serial_input_buffer_full == 1'b1) begin
// We've received a byte from the MCU and want to transmit it.
// Make room for the next byte from the MCU.
serial_input_buffer_full <= 1'b0;
// When we're not transmitting, we ignore anything without
// the 'raw' byte.
if (serial_shifter[8] == 1'b1) begin
// new frames always start with a raw (flag) byte
outputting_frame <= 1'b1;
end
econet_transmitting <= 1'b1;
// 0x1XX = 8 raw bits; 0x0XX = 8 bits with zero stuffing
econet_output_raw <= serial_shifter[8];
econet_shifter <= serial_shifter[7:0];
econet_bit_count <= 3'b0;
end
end
// ECONET TRANSMITTER
if (econet_clock_sync[2] == 1'b1 && econet_clock_sync[1] == 1'b0) begin
// FALLING ECONET CLOCK EDGE: FLIP OUTPUT
if (outputting_frame == 1'b1) begin
if (econet_transmitting == 1'b0) begin
// Buffer underrun: we're in a frame and it's time to output a bit, but we have nothing
outputting_frame <= 1'b0;
// Reset line to '1' when idling, so we don't get a glitch when we start driving again
econet_data_out <= 1'b1;
end
end
if (econet_transmitting == 1'b0) begin
// econet_data_D should idle high
// econet_data_out <= 1'b1;
end else begin
// Transmit even if we're not inside a frame, to avoid deadlocks
// shift out a bit (LSB first) and increment/zero ones count as necessary
econet_data_out <= econet_shifter[0];
// TODO verify that this always sends a 0 after five 1 bits,
// even at the end of a transmission (i.e. verify that sending
// 00011111 then a flag results in 000111110 01111110).
// See: https://stardot.org.uk/forums/viewtopic.php?p=130412#p130412
if (econet_output_raw == 1'b0 && econet_ones_count == 4 && econet_shifter[0] == 1'b1) begin
// set next bit to 0 for stuffing
econet_ones_count <= 0;
econet_shifter[0] <= 1'b0;
end else begin
if (econet_shifter[0] == 1'b1) begin
econet_ones_count <= econet_ones_count + 1;
end else begin
econet_ones_count <= 0;
end
econet_shifter <= {1'b1, econet_shifter[7:1]};
econet_bit_count <= econet_bit_count + 1;
end
// econet_bit_count counts from 0-7 as the 8 bits are shifted out.
if (econet_bit_count == 7) begin
// we just finished transmitting a byte. signal to controller
// that we need our shifter refilled.
econet_transmitting <= 1'b0;
end
end
end
end else begin // mcu_is_transmitting == 1'b0; TRANSMIT TO MCU, RECEIVE FROM ECONET
// SERIAL PORT TRANSMITTER
if (serial_bit_count != 0) begin
// --- MCU is receiving; we can drive serial_cpld_to_mcu ---
serial_shifter <= {1'b1, serial_shifter[9:1]};
serial_bit_count <= serial_bit_count - 1;
end
// ECONET RECEIVER
if (econet_clock_sync[2] == 1'b0 && econet_clock_sync[1] == 1'b1) begin
// RISING ECONET CLOCK EDGE: SAMPLE INPUT
if (econet_ones_count == 7 && econet_data_sync[2] == 1'b1) begin
// Stay in reset
end else if (econet_ones_count == 6 && econet_data_sync[2] == 1'b1) begin
// Reset!
econet_ones_count <= econet_ones_count + 1;
econet_bit_count <= 0;
end else if (econet_ones_count == 6 && econet_data_sync[2] == 1'b0) begin
// Just received a flag
// Probably safe to assume this will never cause a serial overrun, as this would require an Econet line rate over 2MHz.
$display("received flag: put 1+%02x (1+%b) in serial shifter", {econet_shifter[6:0], 1'b0}, {econet_shifter[6:0], 1'b0});
serial_shifter <= {
1'b1, // it's a flag
{econet_data_sync[2],
econet_shifter[0],
econet_shifter[1],
econet_shifter[2],
econet_shifter[3],
econet_shifter[4],
econet_shifter[5],
econet_shifter[6]}, // flag byte
1'b0 // start bit
};
serial_bit_count <= 11;
econet_ones_count <= 1'b0;
econet_bit_count <= 0;
end else if (econet_ones_count == 5 && econet_data_sync[2] == 1'b0) begin
// Just read a stuffed zero
// Reset ones count and skip this bit
econet_ones_count <= 0;
end else begin
// Read a normal bit
// Increment or reset ones count
if (econet_data_sync[2] == 1'b1) begin
econet_ones_count <= econet_ones_count + 1;
end else begin
econet_ones_count <= 0;
end
// Shift it into the receive register
econet_shifter <= {econet_shifter[6:0], econet_data_sync[2]};
// $display("econet_shifter about to be %b", {econet_shifter[6:0], econet_data_sync[2]});
econet_bit_count <= econet_bit_count + 1;
if (econet_bit_count == 7) begin
// Probably safe to assume this will never cause a serial overrun, as this would require an Econet line rate over 2MHz.
$display("received byte: put 0+%02x (0+%b) in serial shifter", {econet_shifter[6:0], econet_data_sync[2]}, {econet_shifter[6:0], econet_data_sync[2]});
serial_shifter <= {
1'b0, // it's data (not a flag)
{econet_data_sync[2],
econet_shifter[0],
econet_shifter[1],
econet_shifter[2],
econet_shifter[3],
econet_shifter[4],
econet_shifter[5],
econet_shifter[6]}, // data byte
1'b0 // start bit
};
serial_bit_count <= 11;
end
end
end // rising econet_clock edge
end // !mcu_is_transmitting
end
endmodule
|
//-----------------------------------------------------------------------------
// processing_system7
// processor sub system wrapper
//-----------------------------------------------------------------------------
//
// ************************************************************************
// ** DISCLAIMER OF LIABILITY **
// ** **
// ** This file contains proprietary and confidential information of **
// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
// ** from Xilinx, and may be used, copied and/or diSCLosed only **
// ** pursuant to the terms of a valid license agreement with Xilinx. **
// ** **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
// ** does not warrant that functions included in the Materials will **
// ** meet the requirements of Licensee, or that the operation of the **
// ** Materials will be uninterrupted or error-free, or that defects **
// ** in the Materials will be corrected. Furthermore, Xilinx does **
// ** not warrant or make any representations regarding use, or the **
// ** results of the use, of the Materials in terms of correctness, **
// ** accuracy, reliability or otherwise. **
// ** **
// ** Xilinx products are not designed or intended to be fail-safe, **
// ** or for use in any application requiring fail-safe performance, **
// ** such as life-support or safety devices or systems, Class III **
// ** medical devices, nuclear facilities, applications related to **
// ** the deployment of airbags, or any other applications that could **
// ** lead to death, personal injury or severe property or **
// ** environmental damage (individually and collectively, "critical **
// ** applications"). Customer assumes the sole risk and liability **
// ** of any use of Xilinx products in critical applications, **
// ** subject only to applicable laws and regulations governing **
// ** limitations on product liability. **
// ** **
// ** Copyright 2010 Xilinx, Inc. **
// ** All rights reserved. **
// ** **
// ** This disclaimer and copyright notice must be retained as part **
// ** of this file at all times. **
// ************************************************************************
//
//-----------------------------------------------------------------------------
// Filename: processing_system7_v5_5_processing_system7.v
// Version: v1.00.a
// Description: This is the wrapper file for PSS.
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7_v5_5_processing_system7.v
// --PS7.v - Unisim component
//-----------------------------------------------------------------------------
// Author: SD
//
// History:
//
// SD 09/20/11 -- First version
// ~~~~~~
// Created the first version v2.00.a
// ^^^^^^
//------------------------------------------------------------------------------
// ^^^^^^
// SR 11/25/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// 1. Changed all clock, reset and clktrig ports to be individual
// signals instead of vectors. This is required for modeling of tools.
// 2. Interrupts are now defined as individual signals as well.
// 3. Added Clk buffer logic for FCLK_CLK
// 4. Includes the ACP related changes done
//
// TODO:
// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
// number of interrupt ports connected for IRQ_F2P.
//
//------------------------------------------------------------------------------
// ^^^^^^
// KP 12/07/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/09/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated
// to STRING and fix for CR 640523
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/13/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// Updated IRQ_F2P logic to address CR 641523.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/01/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Updated SDIO logic to address CR 636210.
// |
// Added C_PS7_SI_REV parameter to track SI Rev
// Removed compress/decompress logic to address CR 642527.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/27/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual
// ports as fix for CR 646379
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/05/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Added/updated compress/decompress logic to address 648393
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/14/12 -- v4.00.a version
// ~~~~~~~
// Unused parameters deleted CR 651120
// Addressed CR 651751
//------------------------------------------------------------------------------
// ^^^^^^
// NR 04/17/12 -- v4.01.a version
// ~~~~~~~
// Added FTM trace buffer functionality
// Added support for ACP AxUSER ports local update
//------------------------------------------------------------------------------
// ^^^^^^
// VR 05/18/12 -- v4.01.a version
// ~~~~~~~
// Fixed CR#659157
//------------------------------------------------------------------------------
// ^^^^^^
// VR 07/25/12 -- v4.01.a version
// ~~~~~~~
// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model
// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
//------------------------------------------------------------------------------
// ^^^^^^
// VR 11/06/12 -- v5.00 version
// ~~~~~~~
// CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={867} load={0.5} /><MEMORY name={code} memType={LPDDR2} dataWidth={32} clockFreq={400} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={26} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={SPI} ioStandard={LVCMOS18} bidis={5} ioBank={Vcco_p1} clockFreq={166.666489} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={49.999947} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p0} clockFreq={99.999893} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p1} clockFreq={99.999893} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1733.332} /><PLL domain={Memory} vco={1599.998} /><PLL domain={IO} vco={1999.998} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={49} usageRate={0.5} />/>" *)
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=400, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=14, PCW_UIPARAM_DDR_COL_ADDR_COUNT=11, PCW_UIPARAM_DDR_CL=6, PCW_UIPARAM_DDR_T_RCD=8, PCW_UIPARAM_DDR_T_RP=9, PCW_UIPARAM_DDR_T_RC=63.0, PCW_UIPARAM_DDR_T_RAS_MIN=42.0, PCW_UIPARAM_DDR_T_FAW=50.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.004, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.004, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=0.004, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=0.004, PCW_UIPARAM_DDR_BOARD_DELAY0=0.436, PCW_UIPARAM_DDR_BOARD_DELAY1=0.436, PCW_UIPARAM_DDR_BOARD_DELAY2=0.436, PCW_UIPARAM_DDR_BOARD_DELAY3=0.436, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=105.056, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=66.904, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=89.1715, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=113.63, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=98.503, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=68.5855, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=90.295, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=103.977, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=80.4535, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=80.4535, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=80.4535, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=80.4535, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160\
, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.3333, PCW_APU_PERIPHERAL_FREQMHZ=867, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200.000000, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=100, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=50, PCW_FPGA1_PERIPHERAL_FREQMHZ=100, PCW_FPGA2_PERIPHERAL_FREQMHZ=150, PCW_FPGA3_PERIPHERAL_FREQMHZ=200, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=52, PCW_IOPLL_CTRL_FBDIV=60, PCW_DDRPLL_CTRL_FBDIV=48, PCW_CPU_CPU_PLL_FREQMHZ=1733.332, PCW_IO_IO_PLL_FREQMHZ=1999.998, PCW_DDR_DDR_PLL_FREQMHZ=1599.998, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=49, PCW_M_AXI_GP1_FREQMHZ=10\
, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_FTM_CTI_IN0=DISABLED, PCW_FTM_CTI_IN1=DISABLED, PCW_FTM_CTI_IN2=DISABLED, PCW_FTM_CTI_IN3=DISABLED, PCW_FTM_CTI_OUT0=DISABLED, PCW_FTM_CTI_OUT1=DISABLED, PCW_FTM_CTI_OUT2=DISABLED, PCW_FTM_CTI_OUT3=DISABLED, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 1.8V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=LPDDR 2, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=Custom, PCW_UIPARAM_DDR_DRAM_WIDTH=32 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=8192 MBits, PCW_UIPARAM_DDR_SPEED_BIN=LPDDR2_1066, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=0, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=0, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0\
, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=1, PCW_QSPI_GRP_FBCLK_IO=MIO 8, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_SINGLE_QSPI_DATA_MODE=x4, PCW_ENET0_PERIPHERAL_ENABLE=0, PCW_ENET0_GRP_MDIO_ENABLE=0, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=0, PCW_SD0_GRP_WP_ENABLE=0, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=1, PCW_SD1_SD1_IO=MIO 10 .. 15, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=1, PCW_UART0_UART0_IO=MIO 50 .. 51, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=0, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=1, PCW_SPI1_SPI1_IO=MIO 46 .. 51, PCW_SPI1_GRP_SS0_ENABLE=1, PCW_SPI1_GRP_SS0_IO=MIO 49, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0\
, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=0, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=0, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=0, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=1, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=1, PCW_GPIO_EMIO_GPIO_IO=64, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X\
, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=1, PCW_FPGA_FCLK2_ENABLE=1, PCW_FPGA_FCLK3_ENABLE=1, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11, PCW_NOR_CS1_T_RC=11, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=11, PCW_NAND_CYCLES_T_RC=11 }" *)
(* HW_HANDOFF = "gcd_zynq_snick_processing_system7_0_0.hwdef" *)
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0,
// Enable and disable AFI Secure transaction
parameter C_USE_AXI_NONSECURE = 0,
//parameters for HP enable ports
parameter C_USE_S_AXI_HP0 = 0,
parameter C_USE_S_AXI_HP1 = 0,
parameter C_USE_S_AXI_HP2 = 0,
parameter C_USE_S_AXI_HP3 = 0,
//parameters for GP and ACP enable ports */
parameter C_USE_M_AXI_GP0 = 0,
parameter C_USE_M_AXI_GP1 = 0,
parameter C_USE_S_AXI_GP0 = 0,
parameter C_USE_S_AXI_GP1 = 0,
parameter C_USE_S_AXI_ACP = 0,
parameter C_GP0_EN_MODIFIABLE_TXN=0,
parameter C_GP1_EN_MODIFIABLE_TXN=0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN = 'b0,
output reg ENET0_GMII_TX_ER = 'b0,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN = 'b0,
output reg ENET1_GMII_TX_ER = 'b0,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
wire [3:0] M_AXI_GP0_ARCACHE_t;
wire [3:0] M_AXI_GP1_ARCACHE_t;
wire [3:0] M_AXI_GP0_AWCACHE_t;
wire [3:0] M_AXI_GP1_AWCACHE_t;
// Wires for connecting to the PS7
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
wire FCLK_CLK0_temp;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire S_AXI_HP0_ACLK_temp;
wire S_AXI_HP1_ACLK_temp;
wire S_AXI_HP2_ACLK_temp;
wire S_AXI_HP3_ACLK_temp;
wire M_AXI_GP0_ACLK_temp;
wire M_AXI_GP1_ACLK_temp;
wire S_AXI_GP0_ACLK_temp;
wire S_AXI_GP1_ACLK_temp;
wire S_AXI_ACP_ACLK_temp;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
(* keep = "true" *) reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
(* keep = "true" *) reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
end
end
else
begin
always @*
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= 1'b0;
TRACE_DATA_PIPE[j-1] <= 1'b0;
end
TRACE_CLK_OUT <= 1'b0;
end
end
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
if (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
end else begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
else
always@*
begin
ENET0_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= 'b0;
ENET0_GMII_CRS_i <= 'b0;
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET0_GMII_RXD_i <= 0;
ENET0_GMII_RX_DV_i <= 0;
ENET0_GMII_RX_ER_i <= 0;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
else
begin
always@*
begin
ENET1_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET1_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET1_GMII_COL_i <= 0;
ENET1_GMII_CRS_i <= 0;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET1_GMII_RXD_i <= 'b0;
ENET1_GMII_RX_DV_i <= 'b0;
ENET1_GMII_RX_ER_i <= 'b0;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
else
begin
assign FTMD_TRACEIN_DATA_i = 1'b0;
assign FTMD_TRACEIN_VALID_i = 1'b0;
assign FTMD_TRACEIN_ATID_i = 1'b0;
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
OBUFT jtag_obuft_inst (
.O(PJTAG_TDO),
.I(PJTAG_TDO_O),
.T(PJTAG_TDO_T)
);
end
else
begin
assign PJTAG_TDO = 1'b0;
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0_temp = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
assign FCLK_CLK0 = FCLK_CLK0_temp;
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
// Connect FCLK in case of disable the AXI port for non Secure Transaction
//Start
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP0 == 0) begin
assign S_AXI_HP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP0_ACLK_temp = S_AXI_HP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP1 == 0) begin
assign S_AXI_HP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP1_ACLK_temp = S_AXI_HP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP2 == 0) begin
assign S_AXI_HP2_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP2_ACLK_temp = S_AXI_HP2_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP3 == 0) begin
assign S_AXI_HP3_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP3_ACLK_temp = S_AXI_HP3_ACLK;
end
endgenerate
//Start
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP0 == 0) begin
assign M_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP0_ACLK_temp = M_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP1 == 0) begin
assign M_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP1_ACLK_temp = M_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP0 == 0) begin
assign S_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP0_ACLK_temp = S_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP1 == 0) begin
assign S_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP1_ACLK_temp = S_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_ACP == 0) begin
assign S_AXI_ACP_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_ACP_ACLK_temp = S_AXI_ACP_ACLK;
end
endgenerate
assign M_AXI_GP0_ARCACHE=(C_GP0_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP0_ARCACHE_t[3:2]},{1'b1},{M_AXI_GP0_ARCACHE_t[0]}}:M_AXI_GP0_ARCACHE_t ;
assign M_AXI_GP1_ARCACHE=(C_GP1_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP1_ARCACHE_t[3:2]},{1'b1},{M_AXI_GP1_ARCACHE_t[0]}}:M_AXI_GP1_ARCACHE_t ;
assign M_AXI_GP0_AWCACHE=(C_GP0_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP0_AWCACHE_t[3:2]},{1'b1},{M_AXI_GP0_AWCACHE_t[0]}}:M_AXI_GP0_AWCACHE_t ;
assign M_AXI_GP1_AWCACHE=(C_GP1_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP1_AWCACHE_t[3:2]},{1'b1},{M_AXI_GP1_AWCACHE_t[0]}}:M_AXI_GP1_AWCACHE_t ;
//END
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), //(ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE_t),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE_t),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE_t),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE_t),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), // (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE_t),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE_t),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE_t),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE_t),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK_temp),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/jp.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Joypad controller block.
***************************************************************************************************/
`timescale 1ps / 1ps
module jp(
input clk, // 100MHz system clock signal
input rst, // reset signal
input i_wr, // i_write enable signal
input [15:0] i_addr, // 16-bit memory i_address
input i_din, // data input bus
output reg [7:0] o_dout, // data output bus
input [7:0] i_jp1_state, //state of the joy pad 1
input [7:0] i_jp2_state //state of the joy pad 2
);
//Local Parameters
localparam [15:0] JOYPAD1_MMR_ADDR = 16'h4016;
localparam [15:0] JOYPAD2_MMR_ADDR = 16'h4017;
//Registers/Wires
reg [15:0] r_prev_addr;
wire w_new_addr;
reg r_wrote_1_flag;
reg [8:0] r_jp1_state;
reg [8:0] r_jp2_state;
//Submodules
//Asynchronous Logic
assign w_new_addr = (r_prev_addr != i_addr);
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_dout <= 0;
r_prev_addr <= 0;
r_wrote_1_flag <= 0;
r_jp1_state <= 0;
r_jp2_state <= 0;
end
else begin
//Only process a command when i_address changes from not this i_address to this i_address
if (i_addr[15:1] == JOYPAD1_MMR_ADDR[15:1]) begin
//User has accessed the joypad register(s), depeni_ding on the last
//bit send the appropriate joystick information (1 or 2)
o_dout <= { 7'h00, ((i_addr[0]) ? r_jp2_state[0] : r_jp1_state[0]) };
if (w_new_addr) begin
if (i_wr && !i_addr[0]) begin
if (!r_wrote_1_flag) begin
if (i_din == 1'b1) begin
r_wrote_1_flag <= 1;
end
end
else begin
if (i_din == 1'b0) begin
r_wrote_1_flag <= 0;
r_jp1_state <= {i_jp1_state, 1'b0};
r_jp2_state <= {i_jp2_state, 1'b0};
end
end
end
//Shift appropriate JP read state on every read, after 8 reads, all subsequent reads should be 1
else if (!i_wr && !i_addr[0]) begin
r_jp1_state <= {1'b1, r_jp1_state[8:1]};
end
else if (!i_wr && i_addr[0]) begin
r_jp2_state <= {1'b1, r_jp2_state[8:1]};
end
end
end
r_prev_addr <= i_addr;
end
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 14:38:02 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_FSM_Mult_Function ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W48 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W24 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W24 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W32_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_6 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_FPU_Interface2_W32_EW8_SW23_SWR26_EWR5_1 ( CLK, EN,
ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
module FPU_Interface2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result,
busy );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready, busy;
wire NaN_reg, ready_add_subt, underflow_flag_mult, overflow_flag_addsubt,
underflow_flag_addsubt, FPSENCOS_fmtted_Result_31_,
FPSENCOS_enab_d_ff4_Xn, FPSENCOS_enab_d_ff4_Yn,
FPSENCOS_d_ff3_sign_out, FPSENCOS_d_ff1_shift_region_flag_out_0_,
FPSENCOS_d_ff1_operation_out, FPSENCOS_enab_d_ff5_data_out,
FPSENCOS_enab_RB3, FPSENCOS_enab_d_ff_RB1, FPSENCOS_enab_d_ff4_Zn,
FPMULT_FSM_selector_C, FPMULT_FSM_selector_A,
FPMULT_FSM_exp_operation_A_S, FPMULT_FSM_barrel_shifter_load,
FPMULT_FSM_final_result_load, FPMULT_FSM_adder_round_norm_load,
FPMULT_FSM_load_second_step, FPMULT_FSM_exp_operation_load_result,
FPMULT_FSM_first_phase_load, FPMULT_FSM_add_overflow_flag,
FPADDSUB_N60, FPADDSUB_N59, FPADDSUB_SIGN_FLAG_SFG, FPADDSUB__19_net_,
FPADDSUB_SIGN_FLAG_NRM, FPADDSUB_SIGN_FLAG_SHT1SHT2,
FPADDSUB_ADD_OVRFLW_NRM2, FPADDSUB_OP_FLAG_SHT2,
FPADDSUB_SIGN_FLAG_SHT2, FPADDSUB_bit_shift_SHT2,
FPADDSUB_left_right_SHT2, FPADDSUB__6_net_, FPADDSUB_ADD_OVRFLW_NRM,
FPADDSUB_OP_FLAG_SHT1, FPADDSUB_SIGN_FLAG_SHT1, FPADDSUB_OP_FLAG_EXP,
FPADDSUB_SIGN_FLAG_EXP, FPADDSUB_Shift_reg_FLAGS_7_5,
FPADDSUB_Shift_reg_FLAGS_7_6, FPADDSUB_enable_Pipeline_input,
FPSENCOS_ITER_CONT_net8272393, FPSENCOS_ITER_CONT_N5,
FPSENCOS_ITER_CONT_N4, FPSENCOS_ITER_CONT_N3,
FPMULT_FS_Module_net8272339, FPMULT_Exp_module_Overflow_flag_A,
FPMULT_Exp_module_Overflow_A,
FPMULT_final_result_ieee_Module_Sign_S_mux,
FPADDSUB_inst_ShiftRegister_net8272231,
FPADDSUB_SFT2FRMT_STAGE_VARS_net8272141,
FPSENCOS_d_ff5_data_out_net8272357,
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069,
FPADDSUB_SGF_STAGE_DMP_net8272123,
FPADDSUB_NRM_STAGE_Raw_mant_net8272105, FPSENCOS_reg_Z0_net8272357,
FPSENCOS_reg_val_muxZ_2stage_net8272357,
FPSENCOS_reg_shift_y_net8272357, FPSENCOS_d_ff4_Xn_net8272357,
FPSENCOS_d_ff4_Yn_net8272357, FPSENCOS_d_ff4_Zn_net8272357,
FPADDSUB_INPUT_STAGE_OPERANDY_net8272069,
FPADDSUB_EXP_STAGE_DMP_net8272123, FPADDSUB_SHT1_STAGE_DMP_net8272123,
FPADDSUB_SHT2_STAGE_DMP_net8272123,
FPADDSUB_SHT2_SHIFT_DATA_net8272105,
FPMULT_Exp_module_exp_result_m_net8272303,
FPMULT_Sgf_operation_EVEN1_left_N23,
FPMULT_Sgf_operation_EVEN1_left_N22,
FPMULT_Sgf_operation_EVEN1_left_N21,
FPMULT_Sgf_operation_EVEN1_left_N20,
FPMULT_Sgf_operation_EVEN1_left_N19,
FPMULT_Sgf_operation_EVEN1_left_N18,
FPMULT_Sgf_operation_EVEN1_left_N17,
FPMULT_Sgf_operation_EVEN1_left_N16,
FPMULT_Sgf_operation_EVEN1_left_N15,
FPMULT_Sgf_operation_EVEN1_left_N14,
FPMULT_Sgf_operation_EVEN1_left_N13,
FPMULT_Sgf_operation_EVEN1_left_N12,
FPMULT_Sgf_operation_EVEN1_left_N11,
FPMULT_Sgf_operation_EVEN1_left_N10,
FPMULT_Sgf_operation_EVEN1_left_N9,
FPMULT_Sgf_operation_EVEN1_left_N8,
FPMULT_Sgf_operation_EVEN1_left_N7,
FPMULT_Sgf_operation_EVEN1_left_N6,
FPMULT_Sgf_operation_EVEN1_left_N5,
FPMULT_Sgf_operation_EVEN1_left_N4,
FPMULT_Sgf_operation_EVEN1_left_N3,
FPMULT_Sgf_operation_EVEN1_left_N2,
FPMULT_Sgf_operation_EVEN1_left_N1,
FPMULT_Sgf_operation_EVEN1_middle_N25,
FPMULT_Sgf_operation_EVEN1_middle_N24,
FPMULT_Sgf_operation_EVEN1_middle_N23,
FPMULT_Sgf_operation_EVEN1_middle_N22,
FPMULT_Sgf_operation_EVEN1_middle_N21,
FPMULT_Sgf_operation_EVEN1_middle_N20,
FPMULT_Sgf_operation_EVEN1_middle_N19,
FPMULT_Sgf_operation_EVEN1_middle_N18,
FPMULT_Sgf_operation_EVEN1_middle_N17,
FPMULT_Sgf_operation_EVEN1_middle_N16,
FPMULT_Sgf_operation_EVEN1_middle_N15,
FPMULT_Sgf_operation_EVEN1_middle_N14,
FPMULT_Sgf_operation_EVEN1_middle_N13,
FPMULT_Sgf_operation_EVEN1_middle_N12,
FPMULT_Sgf_operation_EVEN1_middle_N11,
FPMULT_Sgf_operation_EVEN1_middle_N10,
FPMULT_Sgf_operation_EVEN1_middle_N9,
FPMULT_Sgf_operation_EVEN1_middle_N8,
FPMULT_Sgf_operation_EVEN1_middle_N7,
FPMULT_Sgf_operation_EVEN1_middle_N6,
FPMULT_Sgf_operation_EVEN1_middle_N5,
FPMULT_Sgf_operation_EVEN1_middle_N4,
FPMULT_Sgf_operation_EVEN1_middle_N3,
FPMULT_Sgf_operation_EVEN1_middle_N2,
FPMULT_Sgf_operation_EVEN1_middle_N1,
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285,
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267,
FPMULT_Adder_M_Add_Subt_Result_net8272249,
FPMULT_Sgf_operation_EVEN1_right_N23,
FPMULT_Sgf_operation_EVEN1_right_N22,
FPMULT_Sgf_operation_EVEN1_right_N21,
FPMULT_Sgf_operation_EVEN1_right_N20,
FPMULT_Sgf_operation_EVEN1_right_N19,
FPMULT_Sgf_operation_EVEN1_right_N18,
FPMULT_Sgf_operation_EVEN1_right_N17,
FPMULT_Sgf_operation_EVEN1_right_N16,
FPMULT_Sgf_operation_EVEN1_right_N15,
FPMULT_Sgf_operation_EVEN1_right_N14,
FPMULT_Sgf_operation_EVEN1_right_N13,
FPMULT_Sgf_operation_EVEN1_right_N12,
FPMULT_Sgf_operation_EVEN1_right_N11,
FPMULT_Sgf_operation_EVEN1_right_N10,
FPMULT_Sgf_operation_EVEN1_right_N9,
FPMULT_Sgf_operation_EVEN1_right_N8,
FPMULT_Sgf_operation_EVEN1_right_N7,
FPMULT_Sgf_operation_EVEN1_right_N6,
FPMULT_Sgf_operation_EVEN1_right_N5,
FPMULT_Sgf_operation_EVEN1_right_N4,
FPMULT_Sgf_operation_EVEN1_right_N3,
FPMULT_Sgf_operation_EVEN1_right_N2,
FPMULT_Sgf_operation_EVEN1_right_N1,
FPMULT_Operands_load_reg_XMRegister_net8272321,
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069, n30,
n106, n107, n810, n813, n816, n819, n829, n830, n834, n842, n843,
n844, n846, n848, n849, n850, n851, n852, n853, n854, n855, n856,
n857, n859, n860, n861, n862, n863, n864, n865, n874, n875,
DP_OP_26J321_124_9022_n18, DP_OP_26J321_124_9022_n17,
DP_OP_26J321_124_9022_n16, DP_OP_26J321_124_9022_n15,
DP_OP_26J321_124_9022_n14, DP_OP_26J321_124_9022_n8,
DP_OP_26J321_124_9022_n7, DP_OP_26J321_124_9022_n6,
DP_OP_26J321_124_9022_n5, DP_OP_26J321_124_9022_n4,
DP_OP_26J321_124_9022_n3, DP_OP_26J321_124_9022_n2,
DP_OP_26J321_124_9022_n1, DP_OP_234J321_127_8543_n22,
DP_OP_234J321_127_8543_n21, DP_OP_234J321_127_8543_n20,
DP_OP_234J321_127_8543_n19, DP_OP_234J321_127_8543_n18,
DP_OP_234J321_127_8543_n17, DP_OP_234J321_127_8543_n16,
DP_OP_234J321_127_8543_n15, DP_OP_234J321_127_8543_n9,
DP_OP_234J321_127_8543_n8, DP_OP_234J321_127_8543_n7,
DP_OP_234J321_127_8543_n6, DP_OP_234J321_127_8543_n5,
DP_OP_234J321_127_8543_n4, DP_OP_234J321_127_8543_n3,
DP_OP_234J321_127_8543_n2, DP_OP_234J321_127_8543_n1,
intadd_1082_B_24_, intadd_1082_B_23_, intadd_1082_B_22_,
intadd_1082_B_21_, intadd_1082_B_20_, intadd_1082_B_19_,
intadd_1082_B_18_, intadd_1082_B_17_, intadd_1082_B_16_,
intadd_1082_B_15_, intadd_1082_B_14_, intadd_1082_B_13_,
intadd_1082_B_12_, intadd_1082_B_11_, intadd_1082_B_10_,
intadd_1082_B_9_, intadd_1082_B_8_, intadd_1082_B_7_,
intadd_1082_B_6_, intadd_1082_B_5_, intadd_1082_B_4_,
intadd_1082_B_3_, intadd_1082_B_2_, intadd_1082_B_1_,
intadd_1082_B_0_, intadd_1082_CI, intadd_1082_n25, intadd_1082_n24,
intadd_1082_n23, intadd_1082_n22, intadd_1082_n21, intadd_1082_n20,
intadd_1082_n19, intadd_1082_n18, intadd_1082_n17, intadd_1082_n16,
intadd_1082_n15, intadd_1082_n14, intadd_1082_n13, intadd_1082_n12,
intadd_1082_n11, intadd_1082_n10, intadd_1082_n9, intadd_1082_n8,
intadd_1082_n7, intadd_1082_n6, intadd_1082_n5, intadd_1082_n4,
intadd_1082_n3, intadd_1082_n2, intadd_1082_n1, intadd_1083_A_24_,
intadd_1083_A_23_, intadd_1083_A_22_, intadd_1083_A_21_,
intadd_1083_A_20_, intadd_1083_A_19_, intadd_1083_A_18_,
intadd_1083_A_17_, intadd_1083_A_16_, intadd_1083_A_15_,
intadd_1083_A_14_, intadd_1083_A_13_, intadd_1083_A_12_,
intadd_1083_A_11_, intadd_1083_A_10_, intadd_1083_A_9_,
intadd_1083_A_8_, intadd_1083_A_7_, intadd_1083_A_6_,
intadd_1083_A_5_, intadd_1083_A_4_, intadd_1083_A_3_,
intadd_1083_A_2_, intadd_1083_B_24_, intadd_1083_B_23_,
intadd_1083_B_22_, intadd_1083_B_21_, intadd_1083_B_20_,
intadd_1083_B_19_, intadd_1083_B_18_, intadd_1083_B_17_,
intadd_1083_B_16_, intadd_1083_B_15_, intadd_1083_B_14_,
intadd_1083_B_13_, intadd_1083_B_12_, intadd_1083_B_11_,
intadd_1083_B_10_, intadd_1083_B_9_, intadd_1083_B_8_,
intadd_1083_B_7_, intadd_1083_B_6_, intadd_1083_B_5_,
intadd_1083_B_4_, intadd_1083_B_3_, intadd_1083_B_2_,
intadd_1083_B_1_, intadd_1083_B_0_, intadd_1083_SUM_24_,
intadd_1083_SUM_23_, intadd_1083_SUM_22_, intadd_1083_SUM_21_,
intadd_1083_SUM_20_, intadd_1083_SUM_19_, intadd_1083_SUM_18_,
intadd_1083_SUM_17_, intadd_1083_SUM_16_, intadd_1083_SUM_15_,
intadd_1083_SUM_14_, intadd_1083_SUM_13_, intadd_1083_SUM_12_,
intadd_1083_SUM_11_, intadd_1083_SUM_10_, intadd_1083_SUM_9_,
intadd_1083_SUM_8_, intadd_1083_SUM_7_, intadd_1083_SUM_6_,
intadd_1083_SUM_5_, intadd_1083_SUM_4_, intadd_1083_SUM_3_,
intadd_1083_SUM_2_, intadd_1083_SUM_1_, intadd_1083_SUM_0_,
intadd_1083_n25, intadd_1083_n24, intadd_1083_n23, intadd_1083_n22,
intadd_1083_n21, intadd_1083_n20, intadd_1083_n19, intadd_1083_n18,
intadd_1083_n17, intadd_1083_n16, intadd_1083_n15, intadd_1083_n14,
intadd_1083_n13, intadd_1083_n12, intadd_1083_n11, intadd_1083_n10,
intadd_1083_n9, intadd_1083_n8, intadd_1083_n7, intadd_1083_n6,
intadd_1083_n5, intadd_1083_n4, intadd_1083_n3, intadd_1083_n2,
intadd_1083_n1, intadd_1084_CI, intadd_1084_n3, intadd_1084_n2,
intadd_1084_n1, intadd_1085_CI, intadd_1085_n3, intadd_1085_n2,
intadd_1085_n1, intadd_1086_CI, intadd_1086_SUM_2_,
intadd_1086_SUM_1_, intadd_1086_SUM_0_, intadd_1086_n3,
intadd_1086_n2, intadd_1086_n1, DP_OP_454J321_123_2743_n453,
DP_OP_454J321_123_2743_n367, DP_OP_454J321_123_2743_n252,
DP_OP_454J321_123_2743_n251, DP_OP_454J321_123_2743_n250,
DP_OP_454J321_123_2743_n249, DP_OP_454J321_123_2743_n248,
DP_OP_454J321_123_2743_n247, DP_OP_454J321_123_2743_n246,
DP_OP_454J321_123_2743_n245, DP_OP_454J321_123_2743_n240,
DP_OP_454J321_123_2743_n236, DP_OP_454J321_123_2743_n235,
DP_OP_454J321_123_2743_n234, DP_OP_454J321_123_2743_n233,
DP_OP_454J321_123_2743_n232, DP_OP_454J321_123_2743_n231,
DP_OP_454J321_123_2743_n227, DP_OP_454J321_123_2743_n223,
DP_OP_454J321_123_2743_n219, DP_OP_454J321_123_2743_n218,
DP_OP_454J321_123_2743_n217, DP_OP_454J321_123_2743_n216,
DP_OP_454J321_123_2743_n215, DP_OP_454J321_123_2743_n214,
DP_OP_454J321_123_2743_n213, DP_OP_454J321_123_2743_n212,
DP_OP_454J321_123_2743_n210, DP_OP_454J321_123_2743_n204,
DP_OP_454J321_123_2743_n203, DP_OP_454J321_123_2743_n202,
DP_OP_454J321_123_2743_n200, DP_OP_454J321_123_2743_n199,
DP_OP_454J321_123_2743_n198, DP_OP_454J321_123_2743_n197,
DP_OP_454J321_123_2743_n196, DP_OP_454J321_123_2743_n195,
DP_OP_454J321_123_2743_n191, DP_OP_454J321_123_2743_n188,
DP_OP_454J321_123_2743_n187, DP_OP_454J321_123_2743_n186,
DP_OP_454J321_123_2743_n185, DP_OP_454J321_123_2743_n184,
DP_OP_454J321_123_2743_n183, DP_OP_454J321_123_2743_n182,
DP_OP_454J321_123_2743_n181, DP_OP_454J321_123_2743_n180,
DP_OP_454J321_123_2743_n179, DP_OP_454J321_123_2743_n178,
DP_OP_454J321_123_2743_n177, DP_OP_454J321_123_2743_n176,
DP_OP_454J321_123_2743_n175, DP_OP_454J321_123_2743_n172,
DP_OP_454J321_123_2743_n171, DP_OP_454J321_123_2743_n170,
DP_OP_454J321_123_2743_n169, DP_OP_454J321_123_2743_n168,
DP_OP_454J321_123_2743_n167, DP_OP_454J321_123_2743_n166,
DP_OP_454J321_123_2743_n165, DP_OP_454J321_123_2743_n164,
DP_OP_454J321_123_2743_n163, DP_OP_454J321_123_2743_n162,
DP_OP_454J321_123_2743_n156, DP_OP_454J321_123_2743_n155,
DP_OP_454J321_123_2743_n148, DP_OP_454J321_123_2743_n145,
DP_OP_454J321_123_2743_n144, DP_OP_454J321_123_2743_n143,
DP_OP_454J321_123_2743_n142, DP_OP_454J321_123_2743_n140,
DP_OP_454J321_123_2743_n139, DP_OP_454J321_123_2743_n138,
DP_OP_454J321_123_2743_n137, DP_OP_454J321_123_2743_n135,
DP_OP_454J321_123_2743_n134, DP_OP_454J321_123_2743_n133,
DP_OP_454J321_123_2743_n131, DP_OP_454J321_123_2743_n130,
DP_OP_454J321_123_2743_n129, DP_OP_454J321_123_2743_n128,
DP_OP_454J321_123_2743_n127, DP_OP_454J321_123_2743_n126,
DP_OP_454J321_123_2743_n125, DP_OP_454J321_123_2743_n124,
DP_OP_454J321_123_2743_n123, DP_OP_454J321_123_2743_n122,
DP_OP_454J321_123_2743_n121, DP_OP_454J321_123_2743_n120,
DP_OP_454J321_123_2743_n119, DP_OP_454J321_123_2743_n117,
DP_OP_454J321_123_2743_n116, DP_OP_454J321_123_2743_n115,
DP_OP_454J321_123_2743_n114, DP_OP_454J321_123_2743_n113,
DP_OP_454J321_123_2743_n112, DP_OP_454J321_123_2743_n111,
DP_OP_454J321_123_2743_n109, DP_OP_454J321_123_2743_n108,
DP_OP_454J321_123_2743_n107, DP_OP_454J321_123_2743_n106,
DP_OP_454J321_123_2743_n105, DP_OP_454J321_123_2743_n104,
DP_OP_454J321_123_2743_n103, DP_OP_454J321_123_2743_n102,
DP_OP_454J321_123_2743_n101, DP_OP_454J321_123_2743_n100,
DP_OP_454J321_123_2743_n99, DP_OP_454J321_123_2743_n98,
DP_OP_454J321_123_2743_n97, DP_OP_454J321_123_2743_n96,
DP_OP_454J321_123_2743_n94, DP_OP_454J321_123_2743_n93,
DP_OP_454J321_123_2743_n92, DP_OP_454J321_123_2743_n91,
DP_OP_454J321_123_2743_n90, DP_OP_454J321_123_2743_n89,
DP_OP_454J321_123_2743_n88, DP_OP_454J321_123_2743_n87,
DP_OP_454J321_123_2743_n84, DP_OP_454J321_123_2743_n83,
DP_OP_454J321_123_2743_n82, DP_OP_454J321_123_2743_n81,
DP_OP_454J321_123_2743_n80, DP_OP_454J321_123_2743_n79,
DP_OP_454J321_123_2743_n78, DP_OP_454J321_123_2743_n77,
DP_OP_454J321_123_2743_n76, DP_OP_454J321_123_2743_n75,
DP_OP_454J321_123_2743_n74, DP_OP_454J321_123_2743_n73,
DP_OP_454J321_123_2743_n72, DP_OP_454J321_123_2743_n71,
DP_OP_454J321_123_2743_n70, DP_OP_454J321_123_2743_n69,
DP_OP_454J321_123_2743_n68, DP_OP_454J321_123_2743_n67,
DP_OP_454J321_123_2743_n66, DP_OP_454J321_123_2743_n65,
DP_OP_454J321_123_2743_n64, DP_OP_454J321_123_2743_n63,
DP_OP_454J321_123_2743_n62, DP_OP_454J321_123_2743_n61,
DP_OP_454J321_123_2743_n60, DP_OP_454J321_123_2743_n59,
DP_OP_454J321_123_2743_n58, DP_OP_454J321_123_2743_n57,
DP_OP_454J321_123_2743_n56, DP_OP_454J321_123_2743_n55,
DP_OP_454J321_123_2743_n52, DP_OP_454J321_123_2743_n51,
DP_OP_454J321_123_2743_n50, DP_OP_454J321_123_2743_n49,
DP_OP_454J321_123_2743_n48, DP_OP_454J321_123_2743_n47,
DP_OP_454J321_123_2743_n46, DP_OP_454J321_123_2743_n45,
DP_OP_454J321_123_2743_n44, DP_OP_454J321_123_2743_n43,
DP_OP_454J321_123_2743_n42, DP_OP_454J321_123_2743_n41,
DP_OP_454J321_123_2743_n40, DP_OP_454J321_123_2743_n39,
DP_OP_454J321_123_2743_n38, DP_OP_454J321_123_2743_n37,
DP_OP_454J321_123_2743_n36, DP_OP_454J321_123_2743_n35,
mult_x_254_n232, mult_x_254_n228, mult_x_254_n220, mult_x_254_n219,
mult_x_254_n216, mult_x_254_n215, mult_x_254_n213, mult_x_254_n212,
mult_x_254_n211, mult_x_254_n208, mult_x_254_n207, mult_x_254_n206,
mult_x_254_n205, mult_x_254_n204, mult_x_254_n203, mult_x_254_n202,
mult_x_254_n200, mult_x_254_n199, mult_x_254_n198, mult_x_254_n197,
mult_x_254_n196, mult_x_254_n195, mult_x_254_n194, mult_x_254_n192,
mult_x_254_n191, mult_x_254_n190, mult_x_254_n189, mult_x_254_n186,
mult_x_254_n185, mult_x_254_n183, mult_x_254_n180, mult_x_254_n179,
mult_x_254_n178, mult_x_254_n176, mult_x_254_n175, mult_x_254_n174,
mult_x_254_n173, mult_x_254_n170, mult_x_254_n169, mult_x_254_n168,
mult_x_254_n167, mult_x_254_n166, mult_x_254_n165, mult_x_254_n164,
mult_x_254_n163, mult_x_254_n162, mult_x_254_n161, mult_x_254_n160,
mult_x_254_n159, mult_x_254_n158, mult_x_254_n157, mult_x_254_n151,
mult_x_254_n149, mult_x_254_n136, mult_x_254_n133, mult_x_254_n132,
mult_x_254_n131, mult_x_254_n130, mult_x_254_n129, mult_x_254_n128,
mult_x_254_n127, mult_x_254_n126, mult_x_254_n125, mult_x_254_n124,
mult_x_254_n123, mult_x_254_n122, mult_x_254_n121, mult_x_254_n120,
mult_x_254_n119, mult_x_254_n118, mult_x_254_n117, mult_x_254_n116,
mult_x_254_n115, mult_x_254_n114, mult_x_254_n113, mult_x_254_n112,
mult_x_254_n111, mult_x_254_n110, mult_x_254_n109, mult_x_254_n108,
mult_x_254_n107, mult_x_254_n106, mult_x_254_n105, mult_x_254_n104,
mult_x_254_n103, mult_x_254_n102, mult_x_254_n101, mult_x_254_n100,
mult_x_254_n99, mult_x_254_n98, mult_x_254_n97, mult_x_254_n96,
mult_x_254_n95, mult_x_254_n94, mult_x_254_n93, mult_x_254_n92,
mult_x_254_n90, mult_x_254_n89, mult_x_254_n88, mult_x_254_n87,
mult_x_254_n86, mult_x_254_n85, mult_x_254_n84, mult_x_254_n83,
mult_x_254_n80, mult_x_254_n79, mult_x_254_n78, mult_x_254_n77,
mult_x_254_n76, mult_x_254_n75, mult_x_254_n74, mult_x_254_n73,
mult_x_254_n72, mult_x_254_n71, mult_x_254_n70, mult_x_254_n69,
mult_x_254_n68, mult_x_254_n67, mult_x_254_n66, mult_x_254_n65,
mult_x_254_n64, mult_x_254_n63, mult_x_254_n62, mult_x_254_n61,
mult_x_254_n60, mult_x_254_n59, mult_x_254_n58, mult_x_254_n57,
mult_x_254_n56, mult_x_254_n55, mult_x_254_n54, mult_x_254_n53,
mult_x_254_n52, mult_x_254_n51, mult_x_254_n48, mult_x_254_n47,
mult_x_254_n46, mult_x_254_n45, mult_x_254_n44, mult_x_254_n43,
mult_x_254_n42, mult_x_254_n41, mult_x_254_n40, mult_x_254_n39,
mult_x_254_n38, mult_x_254_n37, mult_x_254_n36, mult_x_254_n35,
mult_x_254_n34, mult_x_254_n33, mult_x_254_n32, mult_x_254_n31,
mult_x_219_n226, mult_x_219_n222, mult_x_219_n214, mult_x_219_n213,
mult_x_219_n210, mult_x_219_n209, mult_x_219_n207, mult_x_219_n206,
mult_x_219_n205, mult_x_219_n202, mult_x_219_n201, mult_x_219_n200,
mult_x_219_n199, mult_x_219_n198, mult_x_219_n197, mult_x_219_n196,
mult_x_219_n194, mult_x_219_n193, mult_x_219_n192, mult_x_219_n191,
mult_x_219_n190, mult_x_219_n189, mult_x_219_n188, mult_x_219_n186,
mult_x_219_n185, mult_x_219_n184, mult_x_219_n183, mult_x_219_n180,
mult_x_219_n179, mult_x_219_n177, mult_x_219_n174, mult_x_219_n173,
mult_x_219_n172, mult_x_219_n170, mult_x_219_n169, mult_x_219_n168,
mult_x_219_n167, mult_x_219_n164, mult_x_219_n163, mult_x_219_n162,
mult_x_219_n161, mult_x_219_n160, mult_x_219_n159, mult_x_219_n158,
mult_x_219_n157, mult_x_219_n156, mult_x_219_n155, mult_x_219_n154,
mult_x_219_n153, mult_x_219_n152, mult_x_219_n151, mult_x_219_n136,
mult_x_219_n133, mult_x_219_n132, mult_x_219_n131, mult_x_219_n130,
mult_x_219_n129, mult_x_219_n128, mult_x_219_n127, mult_x_219_n126,
mult_x_219_n125, mult_x_219_n124, mult_x_219_n123, mult_x_219_n122,
mult_x_219_n121, mult_x_219_n120, mult_x_219_n119, mult_x_219_n118,
mult_x_219_n117, mult_x_219_n116, mult_x_219_n115, mult_x_219_n114,
mult_x_219_n113, mult_x_219_n112, mult_x_219_n111, mult_x_219_n110,
mult_x_219_n109, mult_x_219_n108, mult_x_219_n107, mult_x_219_n106,
mult_x_219_n105, mult_x_219_n104, mult_x_219_n103, mult_x_219_n102,
mult_x_219_n101, mult_x_219_n100, mult_x_219_n99, mult_x_219_n98,
mult_x_219_n97, mult_x_219_n96, mult_x_219_n95, mult_x_219_n94,
mult_x_219_n93, mult_x_219_n92, mult_x_219_n90, mult_x_219_n89,
mult_x_219_n88, mult_x_219_n87, mult_x_219_n86, mult_x_219_n85,
mult_x_219_n84, mult_x_219_n83, mult_x_219_n80, mult_x_219_n79,
mult_x_219_n78, mult_x_219_n77, mult_x_219_n76, mult_x_219_n75,
mult_x_219_n74, mult_x_219_n73, mult_x_219_n72, mult_x_219_n71,
mult_x_219_n70, mult_x_219_n69, mult_x_219_n68, mult_x_219_n67,
mult_x_219_n66, mult_x_219_n65, mult_x_219_n62, mult_x_219_n61,
mult_x_219_n60, mult_x_219_n59, mult_x_219_n58, mult_x_219_n57,
mult_x_219_n56, mult_x_219_n55, mult_x_219_n54, mult_x_219_n53,
mult_x_219_n52, mult_x_219_n51, mult_x_219_n48, mult_x_219_n47,
mult_x_219_n46, mult_x_219_n45, mult_x_219_n44, mult_x_219_n43,
mult_x_219_n42, mult_x_219_n41, mult_x_219_n40, mult_x_219_n39,
mult_x_219_n36, mult_x_219_n35, mult_x_219_n34, mult_x_219_n33,
mult_x_219_n32, mult_x_219_n31, n910, n911, n912, n913, n914, n915,
n916, n917, n918, n919, n920, n921, n922, n923, n924, n925, n926,
n927, n928, n929, n930, n931, n932, n933, n934, n935, n936, n937,
n938, n939, n940, n941, n942, n943, n944, n945, n946, n947, n948,
n949, n950, n951, n952, n953, n954, n955, n956, n957, n958, n959,
n960, n961, n962, n963, n964, n966, n967, n968, n969, n970, n971,
n972, n973, n974, n975, n976, n977, n978, n979, n980, n981, n982,
n983, n984, n985, n986, n987, n988, n989, n990, n991, n992, n993,
n994, n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004,
n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014,
n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024,
n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034,
n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044,
n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054,
n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064,
n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074,
n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084,
n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094,
n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104,
n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114,
n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124,
n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134,
n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144,
n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1155,
n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165,
n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175,
n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185,
n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195,
n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205,
n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215,
n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225,
n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235,
n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245,
n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255,
n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265,
n1266, n1267, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276,
n1277, n1278, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287,
n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1296, n1297, n1298,
n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308,
n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318,
n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328,
n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338,
n1339, n1340, n1341, n1343, n1344, n1345, n1346, n1347, n1348, n1349,
n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359,
n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369,
n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379,
n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389,
n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399,
n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409,
n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419,
n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429,
n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439,
n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449,
n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459,
n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469,
n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479,
n1480, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490,
n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500,
n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510,
n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520,
n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530,
n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540,
n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550,
n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560,
n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570,
n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580,
n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590,
n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600,
n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610,
n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620,
n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630,
n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640,
n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650,
n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660,
n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670,
n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680,
n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690,
n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700,
n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710,
n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720,
n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730,
n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740,
n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750,
n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760,
n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770,
n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780,
n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790,
n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800,
n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810,
n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820,
n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830,
n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840,
n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850,
n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860,
n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870,
n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880,
n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890,
n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900,
n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910,
n1911, n1912, n1913, n1914, n1915, n1917, n1918, n1919, n1920, n1921,
n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931,
n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941,
n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951,
n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961,
n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971,
n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981,
n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991,
n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001,
n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011,
n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021,
n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031,
n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041,
n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051,
n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061,
n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071,
n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081,
n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091,
n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101,
n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111,
n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121,
n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131,
n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141,
n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151,
n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161,
n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171,
n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181,
n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191,
n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201,
n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211,
n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221,
n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231,
n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241,
n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251,
n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261,
n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271,
n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281,
n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291,
n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301,
n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311,
n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321,
n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331,
n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341,
n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351,
n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361,
n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371,
n2372, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382,
n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392,
n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402,
n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412,
n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422,
n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432,
n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442,
n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452,
n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462,
n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472,
n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482,
n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492,
n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502,
n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512,
n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522,
n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532,
n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542,
n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552,
n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562,
n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572,
n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582,
n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592,
n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602,
n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612,
n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622,
n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632,
n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642,
n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652,
n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662,
n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672,
n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682,
n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692,
n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702,
n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712,
n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722,
n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732,
n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742,
n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752,
n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762,
n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772,
n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782,
n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792,
n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802,
n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812,
n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822,
n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832,
n2834, n2835, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844,
n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854,
n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862;
wire [1:0] operation_reg;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] add_subt_data1;
wire [30:0] add_subt_data2;
wire [31:0] cordic_result;
wire [31:0] result_add_subt;
wire [31:0] mult_result;
wire [30:0] FPSENCOS_mux_sal;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:0] FPSENCOS_d_ff3_sh_y_out;
wire [31:0] FPSENCOS_d_ff3_sh_x_out;
wire [25:4] FPSENCOS_data_out_LUT;
wire [7:0] FPSENCOS_sh_exp_y;
wire [7:0] FPSENCOS_sh_exp_x;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [31:0] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_first_mux_Z;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_first_mux_Y;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_first_mux_X;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [1:0] FPSENCOS_cont_var_out;
wire [3:0] FPSENCOS_cont_iter_out;
wire [22:0] FPMULT_Sgf_normalized_result;
wire [23:0] FPMULT_Add_result;
wire [8:0] FPMULT_S_Oper_A_exp;
wire [8:0] FPMULT_exp_oper_result;
wire [30:0] FPMULT_Op_MY;
wire [30:1] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [47:23] FPMULT_P_Sgf;
wire [31:0] FPADDSUB_formatted_number_W;
wire [25:1] FPADDSUB_Raw_mant_SGF;
wire [24:2] FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] FPADDSUB_DMP_SFG;
wire [7:0] FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] FPADDSUB_LZD_output_NRM2_EW;
wire [25:0] FPADDSUB_sftr_odat_SHT2_SWR;
wire [7:0] FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] FPADDSUB_DMP_SHT2_EWSW;
wire [51:0] FPADDSUB_Data_array_SWR;
wire [25:0] FPADDSUB_Raw_mant_NRM_SWR;
wire [4:2] FPADDSUB_shft_value_mux_o_EWR;
wire [4:0] FPADDSUB_LZD_raw_out_EWR;
wire [4:0] FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] FPADDSUB_DMP_SHT1_EWSW;
wire [4:0] FPADDSUB_Shift_amount_EXP_EW;
wire [27:0] FPADDSUB_DmP_EXP_EWSW;
wire [30:0] FPADDSUB_DMP_EXP_EWSW;
wire [27:0] FPADDSUB_DmP_INIT_EWSW;
wire [30:0] FPADDSUB_DMP_INIT_EWSW;
wire [28:0] FPADDSUB_intDY_EWSW;
wire [31:0] FPADDSUB_intDX_EWSW;
wire [3:0] FPADDSUB_Shift_reg_FLAGS_7;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_next;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_reg;
wire [3:0] FPMULT_FS_Module_state_next;
wire [3:1] FPMULT_FS_Module_state_reg;
wire [8:0] FPMULT_Exp_module_Data_S;
wire [47:0] FPMULT_Sgf_operation_Result;
wire [25:1] FPMULT_Sgf_operation_EVEN1_Q_middle;
wire [23:12] FPMULT_Sgf_operation_EVEN1_Q_right;
wire [23:0] FPMULT_Sgf_operation_EVEN1_Q_left;
wire [24:1] FPMULT_Adder_M_result_A_adder;
wire [22:0] FPMULT_final_result_ieee_Module_Sgf_S_mux;
wire [7:0] FPMULT_final_result_ieee_Module_Exp_S_mux;
wire [2:0] FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4 FPSENCOS_ITER_CONT_clk_gate_temp_reg (
.CLK(clk), .EN(n989), .ENCLK(FPSENCOS_ITER_CONT_net8272393), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_FSM_Mult_Function FPMULT_FS_Module_clk_gate_state_reg_reg (
.CLK(clk), .EN(n846), .ENCLK(FPMULT_FS_Module_net8272339), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7 FPADDSUB_inst_ShiftRegister_clk_gate_Q_reg (
.CLK(clk), .EN(n875), .ENCLK(FPADDSUB_inst_ShiftRegister_net8272231),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13 FPADDSUB_SFT2FRMT_STAGE_VARS_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7[1]), .ENCLK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8272141), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_0 FPSENCOS_d_ff5_data_out_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff5_data_out), .ENCLK(
FPSENCOS_d_ff5_data_out_net8272357), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_0 FPADDSUB_FRMT_STAGE_DATAOUT_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7[0]), .ENCLK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_0 FPADDSUB_SGF_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB__19_net_), .ENCLK(
FPADDSUB_SGF_STAGE_DMP_net8272123), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_0 FPADDSUB_NRM_STAGE_Raw_mant_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7[2]), .ENCLK(
FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_9 FPSENCOS_reg_Z0_clk_gate_Q_reg ( .CLK(
clk), .EN(FPSENCOS_enab_d_ff_RB1), .ENCLK(FPSENCOS_reg_Z0_net8272357),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_6 FPSENCOS_reg_val_muxZ_2stage_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .ENCLK(
FPSENCOS_reg_val_muxZ_2stage_net8272357), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_4 FPSENCOS_reg_shift_y_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_RB3), .ENCLK(
FPSENCOS_reg_shift_y_net8272357), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_3 FPSENCOS_d_ff4_Xn_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff4_Xn), .ENCLK(
FPSENCOS_d_ff4_Xn_net8272357), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_2 FPSENCOS_d_ff4_Yn_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff4_Yn), .ENCLK(
FPSENCOS_d_ff4_Yn_net8272357), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_1 FPSENCOS_d_ff4_Zn_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff4_Zn), .ENCLK(
FPSENCOS_d_ff4_Zn_net8272357), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_2 FPADDSUB_INPUT_STAGE_OPERANDY_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_enable_Pipeline_input), .ENCLK(
FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_3 FPADDSUB_EXP_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7_6), .ENCLK(
FPADDSUB_EXP_STAGE_DMP_net8272123), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_2 FPADDSUB_SHT1_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7_5), .ENCLK(
FPADDSUB_SHT1_STAGE_DMP_net8272123), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_1 FPADDSUB_SHT2_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(busy), .ENCLK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .TE(
1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_2 FPADDSUB_SHT2_SHIFT_DATA_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB__6_net_), .ENCLK(
FPADDSUB_SHT2_SHIFT_DATA_net8272105), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W9 FPMULT_Exp_module_exp_result_m_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_exp_operation_load_result), .ENCLK(
FPMULT_Exp_module_exp_result_m_net8272303), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W48 FPMULT_Sgf_operation_EVEN1_finalreg_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_load_second_step), .ENCLK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W24 FPMULT_Barrel_Shifter_module_Output_Reg_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_barrel_shifter_load), .ENCLK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W24 FPMULT_Adder_M_Add_Subt_Result_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_adder_round_norm_load), .ENCLK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W32_0_1 FPMULT_Operands_load_reg_XMRegister_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_first_phase_load), .ENCLK(
FPMULT_Operands_load_reg_XMRegister_net8272321), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_1 FPMULT_final_result_ieee_Module_Final_Result_IEEE_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_final_result_load), .ENCLK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .TE(
1'b0) );
DFFRXLTS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(clk), .RN(n963), .Q(
dataA[25]) );
DFFRXLTS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(clk), .RN(n2795), .Q(
dataA[26]) );
DFFRXLTS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(clk), .RN(n2816), .Q(
dataA[27]) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(clk), .RN(n2816), .Q(
dataA[31]) );
DFFRXLTS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n2814), .Q(
dataB[24]) );
DFFRXLTS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n2812), .Q(
dataB[25]) );
DFFRXLTS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n2815), .Q(
dataB[26]) );
DFFRXLTS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(clk), .RN(n2814), .Q(
dataB[29]) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(clk), .RN(n2812), .Q(
dataB[31]) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(clk), .RN(n2815), .Q(NaN_flag)
);
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n2838), .CK(
FPADDSUB_inst_ShiftRegister_net8272231), .RN(n2750), .Q(
FPADDSUB_Shift_reg_FLAGS_7_6) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7_6), .CK(
FPADDSUB_inst_ShiftRegister_net8272231), .RN(n2759), .Q(
FPADDSUB_Shift_reg_FLAGS_7_5) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(busy), .CK(
FPADDSUB_inst_ShiftRegister_net8272231), .RN(n2770), .Q(
FPADDSUB_Shift_reg_FLAGS_7[3]) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[3]), .CK(
FPADDSUB_inst_ShiftRegister_net8272231), .RN(n2743), .Q(
FPADDSUB_Shift_reg_FLAGS_7[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[4]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2757), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[3]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2765), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[2]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2768), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[1]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2755), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[0]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2752), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRXLTS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(region_flag[0]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2814), .Q(
FPSENCOS_d_ff1_shift_region_flag_out_0_), .QN(n1030) );
DFFRXLTS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(region_flag[1]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2813), .QN(n946) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n852), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2813), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n862), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2813), .Q(
FPSENCOS_d_ff3_LUT_out[1]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n856), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2813), .Q(
FPSENCOS_d_ff3_LUT_out[2]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n864), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2813), .Q(
FPSENCOS_d_ff3_LUT_out[3]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(FPSENCOS_data_out_LUT[4]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2813), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n853), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2813), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n855), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2813), .Q(
FPSENCOS_d_ff3_LUT_out[6]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n859), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2813), .Q(
FPSENCOS_d_ff3_LUT_out[7]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n2598), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2813), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n861), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2815), .Q(
FPSENCOS_d_ff3_LUT_out[9]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n854), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2813), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n860), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2790), .Q(
FPSENCOS_d_ff3_LUT_out[12]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n851), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2790), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n863), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2790), .Q(
FPSENCOS_d_ff3_LUT_out[15]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n865), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2790), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n850), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2790), .Q(
FPSENCOS_d_ff3_LUT_out[21]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n849), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2814), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n848), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2815), .Q(
FPSENCOS_d_ff3_LUT_out[24]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(FPSENCOS_data_out_LUT[25]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2815), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n857), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2790), .Q(
FPSENCOS_d_ff3_LUT_out[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(Data_1[0]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2790), .Q(FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(Data_1[1]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2790), .Q(FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(Data_1[2]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2814), .Q(FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(Data_1[3]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2812), .Q(FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(Data_1[4]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2815), .Q(FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(Data_1[5]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2814), .Q(FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(Data_1[6]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2812), .Q(FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(Data_1[7]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2815), .Q(FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(Data_1[8]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2814), .Q(FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(Data_1[9]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2812), .Q(FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(Data_1[10]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2815), .Q(FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(Data_1[11]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2814), .Q(FPSENCOS_d_ff1_Z[11]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(Data_1[12]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2812), .Q(FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(Data_1[13]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2815), .Q(FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(Data_1[14]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2808), .Q(FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(Data_1[15]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2806), .Q(FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(Data_1[16]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2803), .Q(FPSENCOS_d_ff1_Z[16]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(Data_1[17]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2809), .Q(FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(Data_1[18]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2807), .Q(FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(Data_1[19]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2801), .Q(FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(Data_1[20]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2808), .Q(FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(Data_1[21]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2799), .Q(FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(Data_1[22]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2806), .Q(FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(Data_1[23]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2803), .Q(FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(Data_1[24]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2809), .Q(FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(Data_1[25]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2807), .Q(FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(Data_1[26]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2805), .Q(FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(Data_1[27]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2810), .Q(FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(Data_1[28]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2818), .Q(FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(Data_1[29]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2804), .Q(FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(Data_1[30]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2802), .Q(FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(Data_1[31]), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2796), .Q(FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(FPSENCOS_sh_exp_x[0]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2818), .Q(
FPSENCOS_d_ff3_sh_x_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(FPSENCOS_sh_exp_x[1]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2805), .Q(
FPSENCOS_d_ff3_sh_x_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(FPSENCOS_sh_exp_x[2]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2802), .Q(
FPSENCOS_d_ff3_sh_x_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(FPSENCOS_sh_exp_x[3]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2815), .Q(
FPSENCOS_d_ff3_sh_x_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(FPSENCOS_sh_exp_x[4]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2804), .Q(
FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(FPSENCOS_sh_exp_x[5]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2810), .Q(
FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(FPSENCOS_sh_exp_x[6]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2803), .Q(
FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(FPSENCOS_sh_exp_x[7]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2806), .Q(
FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(FPSENCOS_sh_exp_y[0]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2811), .Q(
FPSENCOS_d_ff3_sh_y_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(FPSENCOS_sh_exp_y[1]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2811), .Q(
FPSENCOS_d_ff3_sh_y_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(FPSENCOS_sh_exp_y[2]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2799), .Q(
FPSENCOS_d_ff3_sh_y_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(FPSENCOS_sh_exp_y[3]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2806), .Q(
FPSENCOS_d_ff3_sh_y_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(FPSENCOS_sh_exp_y[4]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2803), .Q(
FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(FPSENCOS_sh_exp_y[5]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2803), .Q(
FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(FPSENCOS_sh_exp_y[6]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2807), .Q(
FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(FPSENCOS_sh_exp_y[7]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2808), .Q(
FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2799), .Q(FPSENCOS_d_ff_Xn[23]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2801), .Q(FPSENCOS_d_ff_Xn[24]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2801), .Q(FPSENCOS_d_ff_Xn[25]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2808), .Q(FPSENCOS_d_ff_Xn[26]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2811), .Q(FPSENCOS_d_ff_Xn[27]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2806), .Q(FPSENCOS_d_ff_Xn[28]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2803), .Q(FPSENCOS_d_ff_Xn[29]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2806), .Q(FPSENCOS_d_ff_Xn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_X[30]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2803), .Q(FPSENCOS_d_ff2_X[30]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2809), .Q(FPSENCOS_d_ff_Yn[23]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(FPSENCOS_mux_sal[23]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2806), .Q(cordic_result[23])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2801), .Q(FPSENCOS_d_ff_Yn[24]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(FPSENCOS_mux_sal[24]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2808), .Q(cordic_result[24])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2811), .Q(FPSENCOS_d_ff_Yn[25]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(FPSENCOS_mux_sal[25]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2806), .Q(cordic_result[25])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2803), .Q(FPSENCOS_d_ff_Yn[26]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(FPSENCOS_mux_sal[26]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2811), .Q(cordic_result[26])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2799), .Q(FPSENCOS_d_ff_Yn[27]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(FPSENCOS_mux_sal[27]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2806), .Q(cordic_result[27])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2803), .Q(FPSENCOS_d_ff_Yn[28]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(FPSENCOS_mux_sal[28]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2809), .Q(cordic_result[28])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2807), .Q(FPSENCOS_d_ff_Yn[29]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(FPSENCOS_mux_sal[29]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2801), .Q(cordic_result[29])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2799), .Q(FPSENCOS_d_ff_Yn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_Y[30]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2803), .Q(FPSENCOS_d_ff2_Y[30]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(FPSENCOS_mux_sal[30]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2805), .Q(cordic_result[30])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n1691), .Q(FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_Z[23]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2811), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2804), .Q(FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_Z[24]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2796), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2798), .Q(FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_Z[25]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2805), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2802), .Q(FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_Z[26]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2797), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2804), .Q(FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_Z[27]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n1691), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2802), .Q(FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_Z[28]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2796), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2817), .Q(FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_Z[29]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2805), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2802), .Q(FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_Z[30]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2794), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRXLTS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(add_subt_data1[24]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2744), .QN(n945)
);
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_23_ ( .D(FPADDSUB_DmP_INIT_EWSW[23]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2746), .Q(
FPADDSUB_DmP_EXP_EWSW[23]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_24_ ( .D(FPADDSUB_DmP_INIT_EWSW[24]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2745), .Q(
FPADDSUB_DmP_EXP_EWSW[24]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_25_ ( .D(FPADDSUB_DmP_INIT_EWSW[25]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2758), .Q(
FPADDSUB_DmP_EXP_EWSW[25]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_26_ ( .D(FPADDSUB_DmP_INIT_EWSW[26]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2756), .Q(
FPADDSUB_DmP_EXP_EWSW[26]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(FPADDSUB_DmP_INIT_EWSW[27]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2758), .Q(
FPADDSUB_DmP_EXP_EWSW[27]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_INIT_EWSW[23]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n1690), .Q(
FPADDSUB_DMP_EXP_EWSW[23]), .QN(n1014) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_INIT_EWSW[27]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2751), .Q(
FPADDSUB_DMP_EXP_EWSW[27]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_INIT_EWSW[28]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2751), .Q(
FPADDSUB_DMP_EXP_EWSW[28]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_INIT_EWSW[29]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2749), .Q(
FPADDSUB_DMP_EXP_EWSW[29]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_INIT_EWSW[30]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2771), .Q(
FPADDSUB_DMP_EXP_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_EXP_EWSW[23]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2758), .Q(
FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_EXP_EWSW[24]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2746), .Q(
FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_EXP_EWSW[25]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2743), .Q(
FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_EXP_EWSW[26]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n1690), .Q(
FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_EXP_EWSW[27]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2760), .Q(
FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_EXP_EWSW[28]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2747), .Q(
FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_EXP_EWSW[29]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2760), .Q(
FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_EXP_EWSW[30]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2769), .Q(
FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_SHT1_EWSW[23]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2747), .Q(
FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_SHT2_EWSW[23]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2771), .Q(
FPADDSUB_DMP_SFG[23]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(FPADDSUB_DMP_SFG[23]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2771), .Q(
FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[0]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8272141), .RN(n2771), .Q(
FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_SHT1_EWSW[24]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2762), .Q(
FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_SHT2_EWSW[24]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2765), .Q(
FPADDSUB_DMP_SFG[24]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(FPADDSUB_DMP_SFG[24]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2757), .Q(
FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[1]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8272141), .RN(n2743), .Q(
FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_SHT1_EWSW[25]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2756), .Q(
FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_SHT2_EWSW[25]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2752), .Q(
FPADDSUB_DMP_SFG[25]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(FPADDSUB_DMP_SFG[25]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2764), .Q(
FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[2]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8272141), .RN(n2763), .Q(
FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_SHT1_EWSW[26]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2749), .Q(
FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_SHT2_EWSW[26]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2744), .Q(
FPADDSUB_DMP_SFG[26]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(FPADDSUB_DMP_SFG[26]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2768), .Q(
FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[3]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8272141), .RN(n2755), .Q(
FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_SHT1_EWSW[27]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2763), .Q(
FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_SHT2_EWSW[27]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2764), .Q(
FPADDSUB_DMP_SFG[27]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(FPADDSUB_DMP_SFG[27]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2763), .Q(
FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[4]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8272141), .RN(n2765), .Q(
FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_SHT1_EWSW[28]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2749), .Q(
FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_SHT2_EWSW[28]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2773), .Q(
FPADDSUB_DMP_SFG[28]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(FPADDSUB_DMP_SFG[28]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2773), .Q(
FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[5]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8272141), .RN(n2773), .Q(
FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_SHT1_EWSW[29]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2756), .Q(
FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_SHT2_EWSW[29]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2773), .Q(
FPADDSUB_DMP_SFG[29]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(FPADDSUB_DMP_SFG[29]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2773), .Q(
FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[6]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8272141), .RN(n2773), .Q(
FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_SHT1_EWSW[30]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2767), .Q(
FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_SHT2_EWSW[30]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2773), .Q(
FPADDSUB_DMP_SFG[30]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(FPADDSUB_DMP_SFG[30]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2773), .Q(
FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[7]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8272141), .RN(n2773), .Q(
FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(FPADDSUB_Data_array_SWR[25]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2759), .Q(
FPADDSUB_Data_array_SWR[51]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2804), .Q(FPSENCOS_d_ff_Xn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_X[22]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2810), .Q(FPSENCOS_d_ff2_X[22]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(FPSENCOS_d_ff2_X[22]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n1691), .Q(
FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2818), .Q(FPSENCOS_d_ff_Yn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_Y[22]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2805), .Q(FPSENCOS_d_ff2_Y[22]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(FPSENCOS_d_ff2_Y[22]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2810), .Q(
FPSENCOS_d_ff3_sh_y_out[22]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(FPSENCOS_mux_sal[22]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2808), .Q(cordic_result[22])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2806), .Q(FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_Z[22]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2803), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(FPADDSUB_DmP_INIT_EWSW[22]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2743), .Q(
FPADDSUB_DmP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(
FPADDSUB_DmP_EXP_EWSW[22]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8272123),
.RN(n2757), .Q(FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2809), .Q(FPSENCOS_d_ff_Xn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_X[19]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2807), .Q(FPSENCOS_d_ff2_X[19]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(FPSENCOS_d_ff2_X[19]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2801), .Q(
FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2808), .Q(FPSENCOS_d_ff_Yn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_Y[19]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2811), .Q(FPSENCOS_d_ff2_Y[19]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(FPSENCOS_d_ff2_Y[19]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2806), .Q(
FPSENCOS_d_ff3_sh_y_out[19]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(FPSENCOS_mux_sal[19]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2803), .Q(cordic_result[19])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2809), .Q(FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_Z[19]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2807), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(FPADDSUB_DmP_INIT_EWSW[19]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2770), .Q(
FPADDSUB_DmP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(
FPADDSUB_DmP_EXP_EWSW[19]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8272123),
.RN(n2765), .Q(FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(FPADDSUB_Data_array_SWR[2]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2769), .Q(
FPADDSUB_Data_array_SWR[28]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2814), .Q(FPSENCOS_d_ff_Xn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_X[21]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2804), .Q(FPSENCOS_d_ff2_X[21]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(FPSENCOS_d_ff2_X[21]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2796), .Q(
FPSENCOS_d_ff3_sh_x_out[21]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2802), .Q(FPSENCOS_d_ff_Yn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_Y[21]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2806), .Q(FPSENCOS_d_ff2_Y[21]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(FPSENCOS_d_ff2_Y[21]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2805), .Q(
FPSENCOS_d_ff3_sh_y_out[21]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(FPSENCOS_mux_sal[21]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2796), .Q(cordic_result[21])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2818), .Q(FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_Z[21]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2804), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(FPADDSUB_DmP_INIT_EWSW[21]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2745), .Q(
FPADDSUB_DmP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(
FPADDSUB_DmP_EXP_EWSW[21]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8272123),
.RN(n2766), .Q(FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n1691), .Q(FPSENCOS_d_ff_Xn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_X[2]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2810), .Q(
FPSENCOS_d_ff2_X[2]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(FPSENCOS_d_ff2_X[2]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2794), .Q(
FPSENCOS_d_ff3_sh_x_out[2]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2818), .Q(FPSENCOS_d_ff_Yn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_Y[2]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2805), .Q(
FPSENCOS_d_ff2_Y[2]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(FPSENCOS_d_ff2_Y[2]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2796), .Q(
FPSENCOS_d_ff3_sh_y_out[2]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(FPSENCOS_mux_sal[2]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2793), .Q(cordic_result[2])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2804), .Q(FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_Z[2]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n1691), .Q(
FPSENCOS_d_ff2_Z[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(FPADDSUB_DmP_INIT_EWSW[2]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2753), .Q(
FPADDSUB_DmP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(FPADDSUB_DmP_EXP_EWSW[2]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n1786), .Q(
FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2810), .Q(FPSENCOS_d_ff_Xn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_X[16]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2808), .Q(FPSENCOS_d_ff2_X[16]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(FPSENCOS_d_ff2_X[16]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2805), .Q(
FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n1691), .Q(FPSENCOS_d_ff_Yn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_Y[16]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2818), .Q(FPSENCOS_d_ff2_Y[16]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(FPSENCOS_d_ff2_Y[16]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2804), .Q(
FPSENCOS_d_ff3_sh_y_out[16]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(FPSENCOS_mux_sal[16]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2809), .Q(cordic_result[16])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2807), .Q(FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_Z[16]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2811), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(FPADDSUB_DmP_INIT_EWSW[16]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2752), .Q(
FPADDSUB_DmP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(
FPADDSUB_DmP_EXP_EWSW[16]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8272123),
.RN(n2755), .Q(FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2811), .Q(FPSENCOS_d_ff_Xn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_X[18]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2799), .Q(FPSENCOS_d_ff2_X[18]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(FPSENCOS_d_ff2_X[18]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2806), .Q(
FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2803), .Q(FPSENCOS_d_ff_Yn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_Y[18]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2809), .Q(FPSENCOS_d_ff2_Y[18]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(FPSENCOS_d_ff2_Y[18]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2807), .Q(
FPSENCOS_d_ff3_sh_y_out[18]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(FPSENCOS_mux_sal[18]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2801), .Q(cordic_result[18])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2799), .Q(FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_Z[18]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2808), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(FPADDSUB_DmP_INIT_EWSW[18]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2744), .Q(
FPADDSUB_DmP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(
FPADDSUB_DmP_EXP_EWSW[18]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8272123),
.RN(n2750), .Q(FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(FPADDSUB_Data_array_SWR[3]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2761), .Q(
FPADDSUB_Data_array_SWR[29]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n1688), .Q(FPSENCOS_d_ff_Xn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_X[20]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n964), .Q(FPSENCOS_d_ff2_X[20]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(FPSENCOS_d_ff2_X[20]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2791), .Q(
FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n1688), .Q(FPSENCOS_d_ff_Yn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_Y[20]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n1688), .Q(FPSENCOS_d_ff2_Y[20]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(FPSENCOS_d_ff2_Y[20]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2798), .Q(
FPSENCOS_d_ff3_sh_y_out[20]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(FPSENCOS_mux_sal[20]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2793), .Q(cordic_result[20])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2791), .Q(FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_Z[20]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2791), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(FPADDSUB_DmP_INIT_EWSW[20]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n1690), .Q(
FPADDSUB_DmP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(
FPADDSUB_DmP_EXP_EWSW[20]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8272123),
.RN(n1786), .Q(FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2817), .Q(FPSENCOS_d_ff_Xn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_X[17]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n964), .Q(FPSENCOS_d_ff2_X[17]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(FPSENCOS_d_ff2_X[17]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n963), .Q(
FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2800), .Q(FPSENCOS_d_ff_Yn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_Y[17]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2800), .Q(FPSENCOS_d_ff2_Y[17]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(FPSENCOS_d_ff2_Y[17]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2800), .Q(
FPSENCOS_d_ff3_sh_y_out[17]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(FPSENCOS_mux_sal[17]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2800), .Q(cordic_result[17])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2800), .Q(FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_Z[17]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2800), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(FPADDSUB_DmP_INIT_EWSW[17]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2746), .Q(
FPADDSUB_DmP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(
FPADDSUB_DmP_EXP_EWSW[17]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8272123),
.RN(n2750), .Q(FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2800), .Q(FPSENCOS_d_ff_Xn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_X[4]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2800), .Q(
FPSENCOS_d_ff2_X[4]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(FPSENCOS_d_ff2_X[4]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2800), .Q(
FPSENCOS_d_ff3_sh_x_out[4]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2800), .Q(FPSENCOS_d_ff_Yn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_Y[4]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2798), .Q(
FPSENCOS_d_ff2_Y[4]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(FPSENCOS_d_ff2_Y[4]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2798), .Q(
FPSENCOS_d_ff3_sh_y_out[4]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(FPSENCOS_mux_sal[4]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n1687), .Q(cordic_result[4])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2791), .Q(FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_Z[4]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n1688), .Q(
FPSENCOS_d_ff2_Z[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(FPADDSUB_DmP_INIT_EWSW[4]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2764), .Q(
FPADDSUB_DmP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(FPADDSUB_DmP_EXP_EWSW[4]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2752), .Q(
FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n1688), .Q(FPSENCOS_d_ff_Xn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_X[15]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n1688), .Q(FPSENCOS_d_ff2_X[15]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(FPSENCOS_d_ff2_X[15]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2790), .Q(
FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2805), .Q(FPSENCOS_d_ff_Yn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_Y[15]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n964), .Q(FPSENCOS_d_ff2_Y[15]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(FPSENCOS_d_ff2_Y[15]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n963), .Q(
FPSENCOS_d_ff3_sh_y_out[15]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(FPSENCOS_mux_sal[15]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2817), .Q(cordic_result[15])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2791), .Q(FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_Z[15]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2810), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(FPADDSUB_DmP_INIT_EWSW[15]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2755), .Q(
FPADDSUB_DmP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(
FPADDSUB_DmP_EXP_EWSW[15]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8272123),
.RN(n2768), .Q(FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2811), .Q(FPSENCOS_d_ff_Xn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_X[5]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2808), .Q(
FPSENCOS_d_ff2_X[5]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(FPSENCOS_d_ff2_X[5]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2799), .Q(
FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2811), .Q(FPSENCOS_d_ff_Yn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_Y[5]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2808), .Q(
FPSENCOS_d_ff2_Y[5]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(FPSENCOS_d_ff2_Y[5]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2799), .Q(
FPSENCOS_d_ff3_sh_y_out[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(FPSENCOS_mux_sal[5]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2811), .Q(cordic_result[5])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2808), .Q(FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_Z[5]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2799), .Q(
FPSENCOS_d_ff2_Z[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(FPADDSUB_DmP_INIT_EWSW[5]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2746), .Q(
FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(FPADDSUB_DmP_EXP_EWSW[5]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2753), .Q(
FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2811), .Q(FPSENCOS_d_ff_Xn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_X[13]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2808), .Q(FPSENCOS_d_ff2_X[13]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(FPSENCOS_d_ff2_X[13]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2799), .Q(
FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2816), .Q(FPSENCOS_d_ff_Yn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_Y[13]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2816), .Q(FPSENCOS_d_ff2_Y[13]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(FPSENCOS_d_ff2_Y[13]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2816), .Q(
FPSENCOS_d_ff3_sh_y_out[13]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(FPSENCOS_mux_sal[13]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2816), .Q(cordic_result[13])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2816), .Q(FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_Z[13]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2816), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(FPADDSUB_DmP_INIT_EWSW[13]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2751), .Q(
FPADDSUB_DmP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(
FPADDSUB_DmP_EXP_EWSW[13]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8272123),
.RN(n2745), .Q(FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2816), .Q(FPSENCOS_d_ff_Xn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_X[14]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2816), .Q(FPSENCOS_d_ff2_X[14]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(FPSENCOS_d_ff2_X[14]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2793), .Q(
FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2816), .Q(FPSENCOS_d_ff_Yn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_Y[14]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2816), .Q(FPSENCOS_d_ff2_Y[14]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(FPSENCOS_d_ff2_Y[14]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2793), .Q(
FPSENCOS_d_ff3_sh_y_out[14]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(FPSENCOS_mux_sal[14]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2798), .Q(cordic_result[14])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2798), .Q(FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_Z[14]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2798), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(FPADDSUB_DmP_INIT_EWSW[14]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2746), .Q(
FPADDSUB_DmP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(
FPADDSUB_DmP_EXP_EWSW[14]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8272123),
.RN(n2743), .Q(FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2798), .Q(FPSENCOS_d_ff_Xn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_X[11]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2798), .Q(FPSENCOS_d_ff2_X[11]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(FPSENCOS_d_ff2_X[11]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2798), .Q(
FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2798), .Q(FPSENCOS_d_ff_Yn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_Y[11]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2798), .Q(FPSENCOS_d_ff2_Y[11]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(FPSENCOS_d_ff2_Y[11]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2798), .Q(
FPSENCOS_d_ff3_sh_y_out[11]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(FPSENCOS_mux_sal[11]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2798), .Q(cordic_result[11])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2798), .Q(FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_Z[11]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2798), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(FPADDSUB_DmP_INIT_EWSW[11]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2746), .Q(
FPADDSUB_DmP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(
FPADDSUB_DmP_EXP_EWSW[11]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8272123),
.RN(n2747), .Q(FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2818), .Q(FPSENCOS_d_ff_Xn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_X[8]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2794), .Q(
FPSENCOS_d_ff2_X[8]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(FPSENCOS_d_ff2_X[8]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2811), .Q(
FPSENCOS_d_ff3_sh_x_out[8]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2818), .Q(FPSENCOS_d_ff_Yn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_Y[8]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2794), .Q(
FPSENCOS_d_ff2_Y[8]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(FPSENCOS_d_ff2_Y[8]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2803), .Q(
FPSENCOS_d_ff3_sh_y_out[8]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(FPSENCOS_mux_sal[8]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2818), .Q(cordic_result[8])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2797), .Q(FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_Z[8]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2806), .Q(
FPSENCOS_d_ff2_Z[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(FPADDSUB_DmP_INIT_EWSW[8]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2744), .Q(
FPADDSUB_DmP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(FPADDSUB_DmP_EXP_EWSW[8]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2750), .Q(
FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2818), .Q(FPSENCOS_d_ff_Xn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_X[10]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2797), .Q(FPSENCOS_d_ff2_X[10]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(FPSENCOS_d_ff2_X[10]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n1691), .Q(
FPSENCOS_d_ff3_sh_x_out[10]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2797), .Q(FPSENCOS_d_ff_Yn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_Y[10]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2797), .Q(FPSENCOS_d_ff2_Y[10]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(FPSENCOS_d_ff2_Y[10]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2797), .Q(
FPSENCOS_d_ff3_sh_y_out[10]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(FPSENCOS_mux_sal[10]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2797), .Q(cordic_result[10])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2797), .Q(FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_Z[10]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2797), .Q(FPSENCOS_d_ff2_Z[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(FPADDSUB_DmP_INIT_EWSW[10]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2759), .Q(
FPADDSUB_DmP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(
FPADDSUB_DmP_EXP_EWSW[10]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8272123),
.RN(n2770), .Q(FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2797), .Q(FPSENCOS_d_ff_Xn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_X[12]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2797), .Q(FPSENCOS_d_ff2_X[12]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(FPSENCOS_d_ff2_X[12]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2797), .Q(
FPSENCOS_d_ff3_sh_x_out[12]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2797), .Q(FPSENCOS_d_ff_Yn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_Y[12]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2797), .Q(FPSENCOS_d_ff2_Y[12]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(FPSENCOS_d_ff2_Y[12]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2797), .Q(
FPSENCOS_d_ff3_sh_y_out[12]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(FPSENCOS_mux_sal[12]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2802), .Q(cordic_result[12])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2796), .Q(FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_Z[12]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n1691), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(FPADDSUB_DmP_INIT_EWSW[12]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2764), .Q(
FPADDSUB_DmP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(
FPADDSUB_DmP_EXP_EWSW[12]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8272123),
.RN(n2770), .Q(FPADDSUB_DmP_mant_SHT1_SW[12]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2810), .Q(FPSENCOS_d_ff_Xn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_X[9]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2802), .Q(
FPSENCOS_d_ff2_X[9]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(FPSENCOS_d_ff2_X[9]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2796), .Q(
FPSENCOS_d_ff3_sh_x_out[9]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n1691), .Q(FPSENCOS_d_ff_Yn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_Y[9]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2810), .Q(
FPSENCOS_d_ff2_Y[9]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(FPSENCOS_d_ff2_Y[9]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2802), .Q(
FPSENCOS_d_ff3_sh_y_out[9]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(FPSENCOS_mux_sal[9]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2796), .Q(cordic_result[9])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2810), .Q(FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_Z[9]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n1691), .Q(
FPSENCOS_d_ff2_Z[9]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2795), .Q(FPSENCOS_d_ff_Xn[31]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_X[31]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2795), .Q(FPSENCOS_d_ff2_X[31]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(FPSENCOS_d_ff2_X[31]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2795), .Q(
FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2795), .Q(FPSENCOS_d_ff_Yn[31]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(FPSENCOS_fmtted_Result_31_),
.CK(FPSENCOS_d_ff5_data_out_net8272357), .RN(n2795), .Q(
cordic_result[31]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_Y[31]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2795), .Q(FPSENCOS_d_ff2_Y[31]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(FPSENCOS_d_ff2_Y[31]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2795), .Q(
FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2795), .Q(FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_Z[31]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2795), .Q(FPSENCOS_d_ff2_Z[31]) );
DFFRXLTS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(add_subt_data1[31]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2758), .Q(
FPADDSUB_intDX_EWSW[31]) );
DFFRXLTS FPSENCOS_reg_sign_Q_reg_0_ ( .D(FPSENCOS_d_ff2_Z[31]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2795), .Q(
FPSENCOS_d_ff3_sign_out) );
DFFRXLTS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n2787), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n1786), .Q(
FPADDSUB_left_right_SHT2) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(
FPADDSUB_LZD_raw_out_EWR[3]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8272141), .RN(n2771), .Q(
FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(
FPADDSUB_LZD_raw_out_EWR[0]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8272141), .RN(n2771), .Q(
FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(
FPADDSUB_LZD_raw_out_EWR[2]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8272141), .RN(n2771), .Q(
FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(
FPADDSUB_LZD_raw_out_EWR[1]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8272141), .RN(n2771), .Q(
FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(
FPADDSUB_LZD_raw_out_EWR[4]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8272141), .RN(n2771), .Q(
FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2795), .Q(FPSENCOS_d_ff_Xn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_X[0]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2795), .Q(
FPSENCOS_d_ff2_X[0]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(FPSENCOS_d_ff2_X[0]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2794), .Q(
FPSENCOS_d_ff3_sh_x_out[0]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2794), .Q(FPSENCOS_d_ff_Yn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_Y[0]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2794), .Q(
FPSENCOS_d_ff2_Y[0]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(FPSENCOS_d_ff2_Y[0]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2794), .Q(
FPSENCOS_d_ff3_sh_y_out[0]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(FPSENCOS_mux_sal[0]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2794), .Q(cordic_result[0])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2794), .Q(FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_Z[0]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2794), .Q(
FPSENCOS_d_ff2_Z[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(FPADDSUB_DmP_INIT_EWSW[0]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2743), .Q(
FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(FPADDSUB_DmP_EXP_EWSW[0]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2757), .Q(
FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_INIT_EWSW[0]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2765), .Q(
FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_EXP_EWSW[0]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2763), .Q(
FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_SHT1_EWSW[0]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2764), .Q(
FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2794), .Q(FPSENCOS_d_ff_Xn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_X[1]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2794), .Q(
FPSENCOS_d_ff2_X[1]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(FPSENCOS_d_ff2_X[1]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2794), .Q(
FPSENCOS_d_ff3_sh_x_out[1]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2794), .Q(FPSENCOS_d_ff_Yn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_Y[1]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2794), .Q(
FPSENCOS_d_ff2_Y[1]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(FPSENCOS_d_ff2_Y[1]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2792), .Q(
FPSENCOS_d_ff3_sh_y_out[1]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(FPSENCOS_mux_sal[1]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n964), .Q(cordic_result[1])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2817), .Q(FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_Z[1]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n963), .Q(
FPSENCOS_d_ff2_Z[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(FPADDSUB_DmP_INIT_EWSW[1]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2762), .Q(
FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(FPADDSUB_DmP_EXP_EWSW[1]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2761), .Q(
FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_INIT_EWSW[1]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2756), .Q(
FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_EXP_EWSW[1]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2761), .Q(
FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_SHT1_EWSW[1]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2745), .Q(
FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n964), .Q(FPSENCOS_d_ff_Xn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_X[3]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2792), .Q(
FPSENCOS_d_ff2_X[3]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(FPSENCOS_d_ff2_X[3]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2817), .Q(
FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2792), .Q(FPSENCOS_d_ff_Yn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_Y[3]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2790), .Q(
FPSENCOS_d_ff2_Y[3]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(FPSENCOS_d_ff2_Y[3]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n963), .Q(
FPSENCOS_d_ff3_sh_y_out[3]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(FPSENCOS_mux_sal[3]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2791), .Q(cordic_result[3])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2817), .Q(FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_Z[3]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2818), .Q(
FPSENCOS_d_ff2_Z[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(FPADDSUB_DmP_INIT_EWSW[3]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2749), .Q(
FPADDSUB_DmP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(FPADDSUB_DmP_EXP_EWSW[3]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2758), .Q(
FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_INIT_EWSW[3]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2759), .Q(
FPADDSUB_DMP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_EXP_EWSW[3]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2761), .Q(
FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_SHT1_EWSW[3]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2762), .Q(
FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2804), .Q(FPSENCOS_d_ff_Xn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_X[6]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n1687), .Q(
FPSENCOS_d_ff2_X[6]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(FPSENCOS_d_ff2_X[6]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2797), .Q(
FPSENCOS_d_ff3_sh_x_out[6]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2795), .Q(FPSENCOS_d_ff_Yn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_Y[6]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n1687), .Q(
FPSENCOS_d_ff2_Y[6]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(FPSENCOS_d_ff2_Y[6]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n963), .Q(
FPSENCOS_d_ff3_sh_y_out[6]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(FPSENCOS_mux_sal[6]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2802), .Q(cordic_result[6])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2808), .Q(FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_Z[6]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2805), .Q(
FPSENCOS_d_ff2_Z[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(FPADDSUB_DmP_INIT_EWSW[6]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2749), .Q(
FPADDSUB_DmP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(FPADDSUB_DmP_EXP_EWSW[6]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2756), .Q(
FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_INIT_EWSW[6]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2756), .Q(
FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_EXP_EWSW[6]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2762), .Q(
FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_SHT1_EWSW[6]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n1690), .Q(
FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(
FPSENCOS_d_ff4_Xn_net8272357), .RN(n2796), .Q(FPSENCOS_d_ff_Xn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_X[7]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2814), .Q(
FPSENCOS_d_ff2_X[7]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(FPSENCOS_d_ff2_X[7]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2793), .Q(
FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(
FPSENCOS_d_ff4_Yn_net8272357), .RN(n2793), .Q(FPSENCOS_d_ff_Yn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_Y[7]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2793), .Q(
FPSENCOS_d_ff2_Y[7]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(FPSENCOS_d_ff2_Y[7]), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2793), .Q(
FPSENCOS_d_ff3_sh_y_out[7]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(FPSENCOS_mux_sal[7]), .CK(
FPSENCOS_d_ff5_data_out_net8272357), .RN(n2793), .Q(cordic_result[7])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(
FPSENCOS_d_ff4_Zn_net8272357), .RN(n2793), .Q(FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_Z[7]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2793), .Q(
FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(FPADDSUB_DmP_INIT_EWSW[7]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2747), .Q(
FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(FPADDSUB_DmP_EXP_EWSW[7]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n1690), .Q(
FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_INIT_EWSW[7]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2753), .Q(
FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_EXP_EWSW[7]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2751), .Q(
FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_SHT1_EWSW[7]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2751), .Q(
FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(FPADDSUB_DmP_INIT_EWSW[9]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n1690), .Q(
FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(FPADDSUB_DmP_EXP_EWSW[9]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2766), .Q(
FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_INIT_EWSW[9]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2743), .Q(
FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_EXP_EWSW[9]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2757), .Q(
FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_SHT1_EWSW[9]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2770), .Q(
FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_INIT_EWSW[12]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2765), .Q(
FPADDSUB_DMP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_EXP_EWSW[12]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2763), .Q(
FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_SHT1_EWSW[12]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2764), .Q(
FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_INIT_EWSW[10]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2752), .Q(
FPADDSUB_DMP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_EXP_EWSW[10]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2755), .Q(
FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_SHT1_EWSW[10]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2768), .Q(
FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_INIT_EWSW[8]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2744), .Q(
FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_EXP_EWSW[8]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2750), .Q(
FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_SHT1_EWSW[8]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2759), .Q(
FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_INIT_EWSW[11]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2770), .Q(
FPADDSUB_DMP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_EXP_EWSW[11]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2743), .Q(
FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_SHT1_EWSW[11]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2757), .Q(
FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_INIT_EWSW[14]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2765), .Q(
FPADDSUB_DMP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_EXP_EWSW[14]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2763), .Q(
FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_SHT1_EWSW[14]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2764), .Q(
FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_INIT_EWSW[13]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2763), .Q(
FPADDSUB_DMP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_EXP_EWSW[13]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2764), .Q(
FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_SHT1_EWSW[13]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2752), .Q(
FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_INIT_EWSW[5]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2755), .Q(
FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_EXP_EWSW[5]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2768), .Q(
FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_SHT1_EWSW[5]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2744), .Q(
FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_INIT_EWSW[15]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2750), .Q(
FPADDSUB_DMP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_EXP_EWSW[15]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2759), .Q(
FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_SHT1_EWSW[15]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2743), .Q(
FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_INIT_EWSW[4]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2766), .Q(
FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_EXP_EWSW[4]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2766), .Q(
FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_SHT1_EWSW[4]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2766), .Q(
FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_INIT_EWSW[17]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2766), .Q(
FPADDSUB_DMP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_EXP_EWSW[17]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2766), .Q(
FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_SHT1_EWSW[17]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2766), .Q(
FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_INIT_EWSW[20]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2766), .Q(
FPADDSUB_DMP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_EXP_EWSW[20]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2766), .Q(
FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_SHT1_EWSW[20]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2766), .Q(
FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_INIT_EWSW[18]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2756), .Q(
FPADDSUB_DMP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_EXP_EWSW[18]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2753), .Q(
FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_SHT1_EWSW[18]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2769), .Q(
FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_INIT_EWSW[16]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2767), .Q(
FPADDSUB_DMP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_EXP_EWSW[16]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2760), .Q(
FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_SHT1_EWSW[16]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2746), .Q(
FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_INIT_EWSW[2]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2760), .Q(
FPADDSUB_DMP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_EXP_EWSW[2]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2762), .Q(
FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_SHT1_EWSW[2]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2767), .Q(
FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_INIT_EWSW[21]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2767), .Q(
FPADDSUB_DMP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_EXP_EWSW[21]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2767), .Q(
FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_SHT1_EWSW[21]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2767), .Q(
FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_INIT_EWSW[19]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2767), .Q(
FPADDSUB_DMP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_EXP_EWSW[19]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2767), .Q(
FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_SHT1_EWSW[19]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2767), .Q(
FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(FPADDSUB_Data_array_SWR[1]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2767), .Q(
FPADDSUB_Data_array_SWR[27]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(FPADDSUB_Data_array_SWR[0]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2767), .Q(
FPADDSUB_Data_array_SWR[26]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_INIT_EWSW[22]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2757), .Q(
FPADDSUB_DMP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_EXP_EWSW[22]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2770), .Q(
FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_SHT1_EWSW[22]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8272123), .RN(n2765), .Q(
FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[1]), .CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2763), .Q(FPADDSUB_N60) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_47_ ( .D(
FPMULT_Sgf_operation_Result[47]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n2793), .Q(
FPMULT_P_Sgf[47]) );
DFFRXLTS FPMULT_FS_Module_state_reg_reg_0_ ( .D(
FPMULT_FS_Module_state_next[0]), .CK(FPMULT_FS_Module_net8272339),
.RN(n2793), .QN(n1028) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(Data_2[30]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2782), .Q(
FPMULT_Op_MY[30]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(Data_2[29]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2774), .Q(
FPMULT_Op_MY[29]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(Data_2[28]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2777), .Q(
FPMULT_Op_MY[28]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(Data_2[27]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2774), .Q(
FPMULT_Op_MY[27]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(Data_2[26]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2785), .Q(
FPMULT_Op_MY[26]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(Data_2[25]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2785), .Q(
FPMULT_Op_MY[25]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(Data_2[24]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2775), .Q(
FPMULT_Op_MY[24]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(Data_2[23]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2784), .Q(
FPMULT_Op_MY[23]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_22_ ( .D(Data_2[22]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2778), .Q(
FPMULT_Op_MY[22]), .QN(n938) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_11_ ( .D(Data_2[11]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2775), .Q(
FPMULT_Op_MY[11]), .QN(n920) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_7_ ( .D(Data_2[7]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2784), .Q(
FPMULT_Op_MY[7]), .QN(n937) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_6_ ( .D(Data_2[6]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2778), .Q(
FPMULT_Op_MY[6]), .QN(n935) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_5_ ( .D(Data_2[5]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2786), .Q(
FPMULT_Op_MY[5]), .QN(n932) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_3_ ( .D(Data_2[3]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2776), .Q(
FPMULT_Op_MY[3]), .QN(n928) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_2_ ( .D(Data_2[2]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2782), .Q(
FPMULT_Op_MY[2]), .QN(n931) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(Data_1[28]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2779), .Q(
FPMULT_Op_MX[28]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(Data_1[27]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2781), .Q(
FPMULT_Op_MX[27]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(Data_1[24]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2785), .Q(
FPMULT_Op_MX[24]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_21_ ( .D(Data_1[21]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2784), .QN(
n919) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_17_ ( .D(Data_1[17]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2778), .QN(
n925) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_15_ ( .D(Data_1[15]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2786), .QN(
n917) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_9_ ( .D(Data_1[9]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2782), .QN(n936)
);
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_3_ ( .D(Data_1[3]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2774), .QN(n924)
);
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_0_ ( .D(Data_1[0]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2785), .QN(n916)
);
DFFRXLTS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n106), .CK(
n2835), .RN(n2775), .QN(n956) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n2623), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n2775), .Q(
FPMULT_Add_result[0]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(
FPMULT_Sgf_operation_Result[23]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n2790), .Q(
FPMULT_P_Sgf[23]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_8_ ( .D(
FPMULT_Exp_module_Data_S[8]), .CK(
FPMULT_Exp_module_exp_result_m_net8272303), .RN(n2784), .Q(
FPMULT_exp_oper_result[8]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(
FPMULT_Exp_module_Data_S[7]), .CK(
FPMULT_Exp_module_exp_result_m_net8272303), .RN(n2778), .Q(
FPMULT_exp_oper_result[7]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(
FPMULT_Exp_module_Data_S[6]), .CK(
FPMULT_Exp_module_exp_result_m_net8272303), .RN(n2786), .Q(
FPMULT_exp_oper_result[6]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(
FPMULT_Exp_module_Data_S[5]), .CK(
FPMULT_Exp_module_exp_result_m_net8272303), .RN(n2782), .Q(
FPMULT_exp_oper_result[5]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(
FPMULT_Exp_module_Data_S[4]), .CK(
FPMULT_Exp_module_exp_result_m_net8272303), .RN(n2774), .Q(
FPMULT_exp_oper_result[4]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(
FPMULT_Exp_module_Data_S[3]), .CK(
FPMULT_Exp_module_exp_result_m_net8272303), .RN(n2776), .Q(
FPMULT_exp_oper_result[3]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(
FPMULT_Exp_module_Data_S[2]), .CK(
FPMULT_Exp_module_exp_result_m_net8272303), .RN(n966), .Q(
FPMULT_exp_oper_result[2]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(
FPMULT_Exp_module_Data_S[1]), .CK(
FPMULT_Exp_module_exp_result_m_net8272303), .RN(n2779), .Q(
FPMULT_exp_oper_result[1]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(
FPMULT_Exp_module_Data_S[0]), .CK(
FPMULT_Exp_module_exp_result_m_net8272303), .RN(n2781), .Q(
FPMULT_exp_oper_result[0]) );
DFFRXLTS FPMULT_Exp_module_Oflow_A_m_Q_reg_0_ ( .D(
FPMULT_Exp_module_Overflow_A), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n2777), .Q(
FPMULT_Exp_module_Overflow_flag_A) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n2862), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .RN(n2782), .QN(
n1013) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n2860), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .RN(n2774), .Q(
FPMULT_Sgf_normalized_result[21]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n2858), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .RN(n2777), .Q(
FPMULT_Sgf_normalized_result[19]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n2856), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .RN(n2785), .Q(
FPMULT_Sgf_normalized_result[17]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n2854), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .RN(n2775), .Q(
FPMULT_Sgf_normalized_result[15]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n2852), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .RN(n2784), .Q(
FPMULT_Sgf_normalized_result[13]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n2850), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .RN(n2778), .Q(
FPMULT_Sgf_normalized_result[11]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n2848), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .RN(n2776), .Q(
FPMULT_Sgf_normalized_result[9]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n2846), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .RN(n966), .Q(
FPMULT_Sgf_normalized_result[7]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n2844), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .RN(n2779), .Q(
FPMULT_Sgf_normalized_result[5]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n2842), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .RN(n2781), .Q(
FPMULT_Sgf_normalized_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[0]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2782), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[1]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2786), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[2]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2782), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[3]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2774), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[4]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2776), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[5]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n966), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[6]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2779), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[7]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2781), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[8]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2777), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[9]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2782), .Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[10]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2774), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[11]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2785), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[12]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2775), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[13]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2789), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[14]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2789), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[15]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2789), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[16]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2789), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[17]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2780), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[18]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2789), .Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[19]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2789), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[20]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n966), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[21]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2781), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[22]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2782), .Q(mult_result[22]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[0]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2774), .Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[1]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2777), .Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[2]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2784), .Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[3]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2778), .Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[4]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2786), .Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[5]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2776), .Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[6]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n966), .Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[7]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2779), .Q(mult_result[30]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
FPMULT_final_result_ieee_Module_Sign_S_mux), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8272069), .RN(
n2781), .Q(mult_result[31]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n2830), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2771), .Q(
underflow_flag_addsubt) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n2831), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2771), .Q(
overflow_flag_addsubt) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n2829), .CK(
FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2769), .Q(
FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(FPADDSUB_SIGN_FLAG_EXP),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2769), .Q(
FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n819), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2769), .Q(
FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(FPADDSUB_SIGN_FLAG_SHT2),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2769), .Q(
FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_SIGN_FLAG_SFG),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2769), .Q(
FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n816), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2755), .Q(
FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n30), .CK(
FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2769), .Q(
FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_OP_FLAG_EXP), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8272123), .RN(n2763), .Q(
FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n813), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2764), .Q(
FPADDSUB_OP_FLAG_SHT2) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_1_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N1), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[1]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_2_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N2), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[2]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_3_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N3), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_4_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N4), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_5_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N5), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_6_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N6), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_7_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N7), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_8_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N8), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_9_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N9), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_10_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N10), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[10]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_11_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N11), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[11]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_12_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N12), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[12]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_13_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N13), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[13]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_14_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N14), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[14]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_15_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N15), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[15]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_16_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N16), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[16]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_17_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N17), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[17]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_18_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N18), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[18]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_19_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N19), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[19]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_20_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N20), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[20]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_21_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N21), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[21]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_22_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N22), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[22]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_23_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N23), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[23]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_1_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N1), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[1]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_2_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N2), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[2]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_3_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N3), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_4_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N4), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_5_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N5), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_6_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N6), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_7_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N7), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_8_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N8), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_9_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N9), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_10_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N10), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[10]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_11_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N11), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[11]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_12_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N12), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[12]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_13_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N13), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[13]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_14_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N14), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[14]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_15_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N15), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[15]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_16_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N16), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[16]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_17_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N17), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[17]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_18_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N18), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[18]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_19_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N19), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[19]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_20_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N20), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[20]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_21_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N21), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[21]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_22_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N22), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[22]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_23_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N23), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[23]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_24_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N24), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[24]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_25_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N25), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[25]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_1_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N1), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[1]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_2_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N2), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[2]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_3_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N3), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_4_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N4), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_5_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N5), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_6_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N6), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_7_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N7), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_8_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N8), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_9_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N9), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_10_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N10), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[10]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_11_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N11), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[11]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_12_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N12), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[12]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_13_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N13), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[13]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_14_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N14), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[14]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_15_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N15), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[15]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_16_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N16), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[16]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_17_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N17), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[17]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_18_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N18), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[18]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_19_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N19), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[19]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_20_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N20), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[20]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_21_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N21), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[21]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_22_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N22), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[22]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_23_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N23), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[23]) );
SNPS_CLOCK_GATE_HIGH_FPU_Interface2_W32_EW8_SW23_SWR26_EWR5_1 clk_gate_FPMULT_Exp_module_Underflow_m_Q_reg (
.CLK(clk), .EN(n107), .ENCLK(n2835), .TE(1'b0) );
CMPR32X2TS DP_OP_26J321_124_9022_U9 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
n910), .C(DP_OP_26J321_124_9022_n18), .CO(DP_OP_26J321_124_9022_n8),
.S(FPADDSUB_exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_26J321_124_9022_U8 ( .A(DP_OP_26J321_124_9022_n17), .B(
FPADDSUB_DMP_exp_NRM2_EW[1]), .C(DP_OP_26J321_124_9022_n8), .CO(
DP_OP_26J321_124_9022_n7), .S(FPADDSUB_exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_26J321_124_9022_U7 ( .A(DP_OP_26J321_124_9022_n16), .B(
FPADDSUB_DMP_exp_NRM2_EW[2]), .C(DP_OP_26J321_124_9022_n7), .CO(
DP_OP_26J321_124_9022_n6), .S(FPADDSUB_exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_26J321_124_9022_U6 ( .A(DP_OP_26J321_124_9022_n15), .B(
FPADDSUB_DMP_exp_NRM2_EW[3]), .C(DP_OP_26J321_124_9022_n6), .CO(
DP_OP_26J321_124_9022_n5), .S(FPADDSUB_exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS intadd_1082_U26 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[13]), .B(
intadd_1082_B_0_), .C(intadd_1082_CI), .CO(intadd_1082_n25), .S(
FPMULT_Sgf_operation_Result[13]) );
CMPR32X2TS intadd_1082_U24 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[15]), .B(
intadd_1082_B_2_), .C(intadd_1082_n24), .CO(intadd_1082_n23), .S(
FPMULT_Sgf_operation_Result[15]) );
CMPR32X2TS intadd_1082_U23 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[16]), .B(
intadd_1082_B_3_), .C(intadd_1082_n23), .CO(intadd_1082_n22), .S(
FPMULT_Sgf_operation_Result[16]) );
CMPR32X2TS intadd_1082_U22 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[17]), .B(
intadd_1082_B_4_), .C(intadd_1082_n22), .CO(intadd_1082_n21), .S(
FPMULT_Sgf_operation_Result[17]) );
CMPR32X2TS intadd_1082_U21 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[18]), .B(
intadd_1082_B_5_), .C(intadd_1082_n21), .CO(intadd_1082_n20), .S(
FPMULT_Sgf_operation_Result[18]) );
CMPR32X2TS intadd_1082_U20 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[19]), .B(
intadd_1082_B_6_), .C(intadd_1082_n20), .CO(intadd_1082_n19), .S(
FPMULT_Sgf_operation_Result[19]) );
CMPR32X2TS intadd_1082_U19 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[20]), .B(
intadd_1082_B_7_), .C(intadd_1082_n19), .CO(intadd_1082_n18), .S(
FPMULT_Sgf_operation_Result[20]) );
CMPR32X2TS intadd_1082_U18 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[21]), .B(
intadd_1082_B_8_), .C(intadd_1082_n18), .CO(intadd_1082_n17), .S(
FPMULT_Sgf_operation_Result[21]) );
CMPR32X2TS intadd_1082_U17 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[22]), .B(
intadd_1082_B_9_), .C(intadd_1082_n17), .CO(intadd_1082_n16), .S(
FPMULT_Sgf_operation_Result[22]) );
CMPR32X2TS intadd_1082_U16 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[23]), .B(
intadd_1082_B_10_), .C(intadd_1082_n16), .CO(intadd_1082_n15), .S(
FPMULT_Sgf_operation_Result[23]) );
CMPR32X2TS intadd_1082_U4 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[11]), .B(
intadd_1082_B_22_), .C(intadd_1082_n4), .CO(intadd_1082_n3), .S(
FPMULT_Sgf_operation_Result[35]) );
CMPR32X2TS intadd_1082_U3 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[12]), .B(
intadd_1082_B_23_), .C(intadd_1082_n3), .CO(intadd_1082_n2), .S(
FPMULT_Sgf_operation_Result[36]) );
CMPR32X2TS intadd_1082_U2 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[13]), .B(
intadd_1082_B_24_), .C(intadd_1082_n2), .CO(intadd_1082_n1), .S(
FPMULT_Sgf_operation_Result[37]) );
CMPR32X2TS intadd_1083_U26 ( .A(FPMULT_Sgf_operation_Result[0]), .B(
intadd_1083_B_0_), .C(FPMULT_Sgf_operation_EVEN1_Q_left[0]), .CO(
intadd_1083_n25), .S(intadd_1083_SUM_0_) );
CMPR32X2TS intadd_1083_U25 ( .A(FPMULT_Sgf_operation_Result[1]), .B(
intadd_1083_B_1_), .C(intadd_1083_n25), .CO(intadd_1083_n24), .S(
intadd_1083_SUM_1_) );
CMPR32X2TS intadd_1083_U24 ( .A(intadd_1083_A_2_), .B(intadd_1083_B_2_), .C(
intadd_1083_n24), .CO(intadd_1083_n23), .S(intadd_1083_SUM_2_) );
CMPR32X2TS intadd_1083_U23 ( .A(intadd_1083_A_3_), .B(intadd_1083_B_3_), .C(
intadd_1083_n23), .CO(intadd_1083_n22), .S(intadd_1083_SUM_3_) );
CMPR32X2TS intadd_1083_U22 ( .A(intadd_1083_A_4_), .B(intadd_1083_B_4_), .C(
intadd_1083_n22), .CO(intadd_1083_n21), .S(intadd_1083_SUM_4_) );
CMPR32X2TS intadd_1083_U21 ( .A(intadd_1083_A_5_), .B(intadd_1083_B_5_), .C(
intadd_1083_n21), .CO(intadd_1083_n20), .S(intadd_1083_SUM_5_) );
CMPR32X2TS intadd_1083_U20 ( .A(intadd_1083_A_6_), .B(intadd_1083_B_6_), .C(
intadd_1083_n20), .CO(intadd_1083_n19), .S(intadd_1083_SUM_6_) );
CMPR32X2TS intadd_1083_U19 ( .A(intadd_1083_A_7_), .B(intadd_1083_B_7_), .C(
intadd_1083_n19), .CO(intadd_1083_n18), .S(intadd_1083_SUM_7_) );
CMPR32X2TS intadd_1083_U18 ( .A(intadd_1083_A_8_), .B(intadd_1083_B_8_), .C(
intadd_1083_n18), .CO(intadd_1083_n17), .S(intadd_1083_SUM_8_) );
CMPR32X2TS intadd_1083_U17 ( .A(intadd_1083_A_9_), .B(intadd_1083_B_9_), .C(
intadd_1083_n17), .CO(intadd_1083_n16), .S(intadd_1083_SUM_9_) );
CMPR32X2TS intadd_1083_U16 ( .A(intadd_1083_A_10_), .B(intadd_1083_B_10_),
.C(intadd_1083_n16), .CO(intadd_1083_n15), .S(intadd_1083_SUM_10_) );
CMPR32X2TS intadd_1083_U15 ( .A(intadd_1083_A_11_), .B(intadd_1083_B_11_),
.C(intadd_1083_n15), .CO(intadd_1083_n14), .S(intadd_1083_SUM_11_) );
CMPR32X2TS intadd_1083_U14 ( .A(intadd_1083_A_12_), .B(intadd_1083_B_12_),
.C(intadd_1083_n14), .CO(intadd_1083_n13), .S(intadd_1083_SUM_12_) );
CMPR32X2TS intadd_1083_U13 ( .A(intadd_1083_A_13_), .B(intadd_1083_B_13_),
.C(intadd_1083_n13), .CO(intadd_1083_n12), .S(intadd_1083_SUM_13_) );
CMPR32X2TS intadd_1083_U12 ( .A(intadd_1083_A_14_), .B(intadd_1083_B_14_),
.C(intadd_1083_n12), .CO(intadd_1083_n11), .S(intadd_1083_SUM_14_) );
CMPR32X2TS intadd_1083_U11 ( .A(intadd_1083_A_15_), .B(intadd_1083_B_15_),
.C(intadd_1083_n11), .CO(intadd_1083_n10), .S(intadd_1083_SUM_15_) );
CMPR32X2TS intadd_1083_U10 ( .A(intadd_1083_A_16_), .B(intadd_1083_B_16_),
.C(intadd_1083_n10), .CO(intadd_1083_n9), .S(intadd_1083_SUM_16_) );
CMPR32X2TS intadd_1083_U9 ( .A(intadd_1083_A_17_), .B(intadd_1083_B_17_),
.C(intadd_1083_n9), .CO(intadd_1083_n8), .S(intadd_1083_SUM_17_) );
CMPR32X2TS intadd_1083_U8 ( .A(intadd_1083_A_18_), .B(intadd_1083_B_18_),
.C(intadd_1083_n8), .CO(intadd_1083_n7), .S(intadd_1083_SUM_18_) );
CMPR32X2TS intadd_1083_U7 ( .A(intadd_1083_A_19_), .B(intadd_1083_B_19_),
.C(intadd_1083_n7), .CO(intadd_1083_n6), .S(intadd_1083_SUM_19_) );
CMPR32X2TS intadd_1083_U6 ( .A(intadd_1083_A_20_), .B(intadd_1083_B_20_),
.C(intadd_1083_n6), .CO(intadd_1083_n5), .S(intadd_1083_SUM_20_) );
CMPR32X2TS intadd_1083_U5 ( .A(intadd_1083_A_21_), .B(intadd_1083_B_21_),
.C(intadd_1083_n5), .CO(intadd_1083_n4), .S(intadd_1083_SUM_21_) );
CMPR32X2TS intadd_1083_U4 ( .A(intadd_1083_A_22_), .B(intadd_1083_B_22_),
.C(intadd_1083_n4), .CO(intadd_1083_n3), .S(intadd_1083_SUM_22_) );
CMPR32X2TS intadd_1083_U3 ( .A(intadd_1083_A_23_), .B(intadd_1083_B_23_),
.C(intadd_1083_n3), .CO(intadd_1083_n2), .S(intadd_1083_SUM_23_) );
CMPR32X2TS intadd_1083_U2 ( .A(intadd_1083_A_24_), .B(intadd_1083_B_24_),
.C(intadd_1083_n2), .CO(intadd_1083_n1), .S(intadd_1083_SUM_24_) );
CMPR32X2TS intadd_1086_U4 ( .A(FPADDSUB_DmP_EXP_EWSW[24]), .B(n2698), .C(
intadd_1086_CI), .CO(intadd_1086_n3), .S(intadd_1086_SUM_0_) );
CMPR32X2TS intadd_1086_U3 ( .A(FPADDSUB_DmP_EXP_EWSW[25]), .B(n2724), .C(
intadd_1086_n3), .CO(intadd_1086_n2), .S(intadd_1086_SUM_1_) );
CMPR32X2TS intadd_1086_U2 ( .A(FPADDSUB_DmP_EXP_EWSW[26]), .B(n2723), .C(
intadd_1086_n2), .CO(intadd_1086_n1), .S(intadd_1086_SUM_2_) );
DFFSX2TS R_17 ( .D(n2732), .CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069),
.SN(n2762), .Q(n2828) );
DFFSX2TS R_19 ( .D(n2731), .CK(clk), .SN(n2810), .Q(n2822) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(1'b1), .CK(
FPSENCOS_reg_shift_y_net8272357), .RN(n2816), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_X[28]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2807), .Q(FPSENCOS_d_ff2_X[28]), .QN(n2728) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_Y[28]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2803), .Q(FPSENCOS_d_ff2_Y[28]), .QN(n2727) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(add_subt_data2[0]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2755), .Q(
FPADDSUB_intDY_EWSW[0]), .QN(n2721) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(add_subt_data2[26]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2744), .Q(
FPADDSUB_intDY_EWSW[26]), .QN(n2719) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(add_subt_data2[1]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2757), .Q(
FPADDSUB_intDY_EWSW[1]), .QN(n2718) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(add_subt_data2[18]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2763), .Q(
FPADDSUB_intDY_EWSW[18]), .QN(n2717) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(add_subt_data2[8]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2748), .Q(
FPADDSUB_intDY_EWSW[8]), .QN(n2716) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(add_subt_data2[25]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2746), .Q(
FPADDSUB_intDY_EWSW[25]), .QN(n2715) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(add_subt_data2[17]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n1690), .Q(
FPADDSUB_intDY_EWSW[17]), .QN(n2714) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(add_subt_data2[11]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2761), .Q(
FPADDSUB_intDY_EWSW[11]), .QN(n2712) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(add_subt_data2[20]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2753), .Q(
FPADDSUB_intDY_EWSW[20]), .QN(n2711) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(add_subt_data2[21]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2761), .Q(
FPADDSUB_intDY_EWSW[21]), .QN(n2710) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(add_subt_data2[27]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n1690), .Q(
FPADDSUB_intDY_EWSW[27]), .QN(n2709) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(add_subt_data2[9]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2770), .Q(
FPADDSUB_intDY_EWSW[9]), .QN(n2708) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(add_subt_data2[24]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2756), .Q(
FPADDSUB_intDY_EWSW[24]), .QN(n2707) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(add_subt_data2[2]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2751), .Q(
FPADDSUB_intDY_EWSW[2]), .QN(n2706) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(add_subt_data2[13]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2745), .Q(
FPADDSUB_intDY_EWSW[13]), .QN(n2705) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(add_subt_data2[4]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2754), .Q(
FPADDSUB_intDY_EWSW[4]), .QN(n2704) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(add_subt_data2[16]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2765), .Q(
FPADDSUB_intDY_EWSW[16]), .QN(n2703) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(add_subt_data2[6]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2760), .Q(
FPADDSUB_intDY_EWSW[6]), .QN(n2702) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(add_subt_data2[10]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2754), .Q(
FPADDSUB_intDY_EWSW[10]), .QN(n2701) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(add_subt_data1[12]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2757), .Q(
FPADDSUB_intDX_EWSW[12]), .QN(n2700) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n2840), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .RN(n2778), .Q(
FPMULT_Sgf_normalized_result[1]), .QN(n2699) );
DFFRX1TS FPMULT_Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(
FPMULT_Adder_M_result_A_adder[24]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n2781), .Q(
FPMULT_FSM_add_overflow_flag), .QN(n2697) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_SHT2_EWSW[22]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2765), .Q(
FPADDSUB_DMP_SFG[22]), .QN(n2692) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(FPADDSUB_Data_array_SWR[20]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2760), .Q(
FPADDSUB_Data_array_SWR[46]), .QN(n2690) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(FPADDSUB_Data_array_SWR[23]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n1690), .Q(
FPADDSUB_Data_array_SWR[49]), .QN(n2689) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(FPADDSUB_Data_array_SWR[22]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2758), .Q(
FPADDSUB_Data_array_SWR[48]), .QN(n2688) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(add_subt_data2[28]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2760), .Q(
FPADDSUB_intDY_EWSW[28]), .QN(n2687) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[23]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2769), .Q(
FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n2686) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_SHT2_EWSW[20]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2752), .Q(
FPADDSUB_DMP_SFG[20]), .QN(n2685) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(add_subt_data1[14]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2753), .Q(
FPADDSUB_intDX_EWSW[14]), .QN(n2684) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(n2838), .CK(
clk), .RN(n2770), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]),
.QN(n2682) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(add_subt_data1[20]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2751), .Q(
FPADDSUB_intDX_EWSW[20]), .QN(n2681) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(add_subt_data1[18]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2764), .Q(
FPADDSUB_intDX_EWSW[18]), .QN(n2680) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n834), .CK(FPMULT_FS_Module_net8272339),
.RN(n966), .Q(FPMULT_FSM_selector_C), .QN(n2676) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(add_subt_data1[17]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2762), .Q(
FPADDSUB_intDX_EWSW[17]), .QN(n2675) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(add_subt_data1[1]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2744), .Q(
FPADDSUB_intDX_EWSW[1]), .QN(n2674) );
DFFRX1TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(
FPMULT_FS_Module_state_next[3]), .CK(FPMULT_FS_Module_net8272339),
.RN(n2793), .Q(FPMULT_FS_Module_state_reg[3]), .QN(n2670) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(add_subt_data1[3]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2747), .Q(
FPADDSUB_intDX_EWSW[3]), .QN(n2668) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(add_subt_data1[8]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2772), .Q(
FPADDSUB_intDX_EWSW[8]), .QN(n2667) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(add_subt_data1[15]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2772), .Q(
FPADDSUB_intDX_EWSW[15]), .QN(n2666) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(add_subt_data1[11]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2767), .Q(
FPADDSUB_intDX_EWSW[11]), .QN(n2664) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[2]), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2745), .Q(
FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n2663) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[21]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2769), .Q(
FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n2661) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_SHT2_EWSW[18]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2745), .Q(
FPADDSUB_DMP_SFG[18]), .QN(n2660) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[19]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2771), .Q(
FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n2658) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_SHT2_EWSW[16]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2747), .Q(
FPADDSUB_DMP_SFG[16]), .QN(n2657) );
DFFRX1TS FPMULT_Sel_B_Q_reg_0_ ( .D(n830), .CK(FPMULT_FS_Module_net8272339),
.RN(n2779), .Q(FPMULT_FSM_selector_B[0]), .QN(n2656) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(
FPADDSUB_Raw_mant_SGF[20]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2747), .Q(FPADDSUB_Raw_mant_NRM_SWR[20]), .QN(n2655) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(
FPADDSUB_Raw_mant_SGF[12]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2743), .Q(FPADDSUB_Raw_mant_NRM_SWR[12]), .QN(n2654) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(
FPADDSUB_Raw_mant_SGF[14]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2770), .Q(FPADDSUB_Raw_mant_NRM_SWR[14]), .QN(n2653) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[17]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2766), .Q(
FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n2650) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n2815), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .QN(n2648) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(
FPADDSUB_Raw_mant_SGF[17]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2764), .Q(FPADDSUB_Raw_mant_NRM_SWR[17]), .QN(n2647) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(
FPADDSUB_Raw_mant_SGF[25]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n1690), .Q(FPADDSUB_Raw_mant_NRM_SWR[25]), .QN(n2646) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[15]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n1690), .Q(
FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n2644) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_SHT2_EWSW[14]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2759), .Q(
FPADDSUB_DMP_SFG[14]), .QN(n2643) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_SHT2_EWSW[12]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2764), .Q(
FPADDSUB_DMP_SFG[12]), .QN(n2640) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[13]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2761), .Q(
FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n2639) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_SHT2_EWSW[10]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2763), .Q(
FPADDSUB_DMP_SFG[10]), .QN(n2638) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_SHT2_EWSW[8]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2744), .Q(
FPADDSUB_DMP_SFG[8]), .QN(n2635) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_SHT2_EWSW[6]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2749), .Q(
FPADDSUB_DMP_SFG[6]), .QN(n2634) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[11]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2758), .Q(
FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n2633) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_SHT2_EWSW[4]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2766), .Q(
FPADDSUB_DMP_SFG[4]), .QN(n2632) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_SHT2_EWSW[2]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2767), .Q(
FPADDSUB_DMP_SFG[2]), .QN(n2631) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_SHT2_EWSW[0]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2768), .Q(
FPADDSUB_DMP_SFG[0]), .QN(n2630) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[9]), .CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2758), .Q(FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n2629) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[7]), .CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2759), .Q(FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n2628) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[5]), .CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2750), .Q(FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n2627) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_SHT2_EWSW[1]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2756), .Q(
FPADDSUB_DMP_SFG[1]), .QN(n2626) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(add_subt_data2[19]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2754), .Q(
FPADDSUB_intDY_EWSW[19]), .QN(n2624) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n2839), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .RN(n2784), .Q(
FPMULT_Sgf_normalized_result[0]), .QN(n2623) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(FPADDSUB_Data_array_SWR[24]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2761), .Q(
FPADDSUB_Data_array_SWR[50]), .QN(n2622) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(add_subt_data2[14]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2751), .Q(
FPADDSUB_intDY_EWSW[14]), .QN(n2621) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_SHT2_EWSW[21]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2767), .Q(
FPADDSUB_DMP_SFG[21]), .QN(n2620) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(add_subt_data1[0]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2752), .Q(
FPADDSUB_intDX_EWSW[0]), .QN(n2619) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(add_subt_data1[5]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2749), .QN(n2618)
);
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(add_subt_data1[7]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2746), .QN(n2617)
);
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(add_subt_data1[21]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2762), .Q(
FPADDSUB_intDX_EWSW[21]), .QN(n2616) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(add_subt_data1[13]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2753), .Q(
FPADDSUB_intDX_EWSW[13]), .QN(n2615) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(add_subt_data1[9]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2743), .Q(
FPADDSUB_intDX_EWSW[9]), .QN(n2614) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(add_subt_data1[2]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2745), .Q(
FPADDSUB_intDX_EWSW[2]), .QN(n2613) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_SHT2_EWSW[19]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2767), .Q(
FPADDSUB_DMP_SFG[19]), .QN(n2612) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_SHT2_EWSW[17]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2766), .Q(
FPADDSUB_DMP_SFG[17]), .QN(n2611) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(
FPADDSUB_Raw_mant_SGF[22]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2760), .Q(FPADDSUB_Raw_mant_NRM_SWR[22]), .QN(n2610) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_SHT2_EWSW[15]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2766), .Q(
FPADDSUB_DMP_SFG[15]), .QN(n2609) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_SHT2_EWSW[13]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2768), .Q(
FPADDSUB_DMP_SFG[13]), .QN(n2607) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_SHT2_EWSW[11]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2750), .Q(
FPADDSUB_DMP_SFG[11]), .QN(n2606) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_SHT2_EWSW[9]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2765), .Q(
FPADDSUB_DMP_SFG[9]), .QN(n2605) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_SHT2_EWSW[7]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2756), .Q(
FPADDSUB_DMP_SFG[7]), .QN(n2604) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_SHT2_EWSW[5]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2755), .Q(
FPADDSUB_DMP_SFG[5]), .QN(n2603) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_SHT2_EWSW[3]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2764), .Q(
FPADDSUB_DMP_SFG[3]), .QN(n2602) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[3]), .CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2744), .Q(FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n2601) );
CMPR32X2TS DP_OP_234J321_127_8543_U2 ( .A(FPMULT_FSM_exp_operation_A_S), .B(
FPMULT_S_Oper_A_exp[8]), .C(DP_OP_234J321_127_8543_n2), .CO(
DP_OP_234J321_127_8543_n1), .S(FPMULT_Exp_module_Data_S[8]) );
CMPR32X2TS DP_OP_234J321_127_8543_U9 ( .A(DP_OP_234J321_127_8543_n21), .B(
FPMULT_S_Oper_A_exp[1]), .C(DP_OP_234J321_127_8543_n9), .CO(
DP_OP_234J321_127_8543_n8), .S(FPMULT_Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_234J321_127_8543_U8 ( .A(DP_OP_234J321_127_8543_n20), .B(
FPMULT_S_Oper_A_exp[2]), .C(DP_OP_234J321_127_8543_n8), .CO(
DP_OP_234J321_127_8543_n7), .S(FPMULT_Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_234J321_127_8543_U7 ( .A(DP_OP_234J321_127_8543_n19), .B(
FPMULT_S_Oper_A_exp[3]), .C(DP_OP_234J321_127_8543_n7), .CO(
DP_OP_234J321_127_8543_n6), .S(FPMULT_Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_234J321_127_8543_U6 ( .A(DP_OP_234J321_127_8543_n18), .B(
FPMULT_S_Oper_A_exp[4]), .C(DP_OP_234J321_127_8543_n6), .CO(
DP_OP_234J321_127_8543_n5), .S(FPMULT_Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_234J321_127_8543_U5 ( .A(DP_OP_234J321_127_8543_n17), .B(
FPMULT_S_Oper_A_exp[5]), .C(DP_OP_234J321_127_8543_n5), .CO(
DP_OP_234J321_127_8543_n4), .S(FPMULT_Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_234J321_127_8543_U4 ( .A(DP_OP_234J321_127_8543_n16), .B(
FPMULT_S_Oper_A_exp[6]), .C(DP_OP_234J321_127_8543_n4), .CO(
DP_OP_234J321_127_8543_n3), .S(FPMULT_Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_234J321_127_8543_U3 ( .A(DP_OP_234J321_127_8543_n15), .B(
FPMULT_S_Oper_A_exp[7]), .C(DP_OP_234J321_127_8543_n3), .CO(
DP_OP_234J321_127_8543_n2), .S(FPMULT_Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_26J321_124_9022_U5 ( .A(DP_OP_26J321_124_9022_n14), .B(
FPADDSUB_DMP_exp_NRM2_EW[4]), .C(DP_OP_26J321_124_9022_n5), .CO(
DP_OP_26J321_124_9022_n4), .S(FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_26J321_124_9022_U4 ( .A(n910), .B(
FPADDSUB_DMP_exp_NRM2_EW[5]), .C(DP_OP_26J321_124_9022_n4), .CO(
DP_OP_26J321_124_9022_n3), .S(FPADDSUB_exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_26J321_124_9022_U3 ( .A(n910), .B(
FPADDSUB_DMP_exp_NRM2_EW[6]), .C(DP_OP_26J321_124_9022_n3), .CO(
DP_OP_26J321_124_9022_n2), .S(FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_26J321_124_9022_U2 ( .A(n910), .B(
FPADDSUB_DMP_exp_NRM2_EW[7]), .C(DP_OP_26J321_124_9022_n2), .CO(
DP_OP_26J321_124_9022_n1), .S(FPADDSUB_exp_rslt_NRM2_EW1[7]) );
CMPR42X1TS DP_OP_454J321_123_2743_U75 ( .A(DP_OP_454J321_123_2743_n240), .B(
DP_OP_454J321_123_2743_n227), .C(DP_OP_454J321_123_2743_n148), .D(
DP_OP_454J321_123_2743_n252), .ICI(DP_OP_454J321_123_2743_n214), .S(
DP_OP_454J321_123_2743_n145), .ICO(DP_OP_454J321_123_2743_n143), .CO(
DP_OP_454J321_123_2743_n144) );
CMPR42X1TS DP_OP_454J321_123_2743_U73 ( .A(DP_OP_454J321_123_2743_n143), .B(
DP_OP_454J321_123_2743_n251), .C(DP_OP_454J321_123_2743_n142), .D(
DP_OP_454J321_123_2743_n213), .ICI(DP_OP_454J321_123_2743_n156), .S(
DP_OP_454J321_123_2743_n140), .ICO(DP_OP_454J321_123_2743_n138), .CO(
DP_OP_454J321_123_2743_n139) );
CMPR42X1TS DP_OP_454J321_123_2743_U71 ( .A(DP_OP_454J321_123_2743_n212), .B(
DP_OP_454J321_123_2743_n137), .C(DP_OP_454J321_123_2743_n138), .D(
DP_OP_454J321_123_2743_n250), .ICI(DP_OP_454J321_123_2743_n200), .S(
DP_OP_454J321_123_2743_n135), .ICO(DP_OP_454J321_123_2743_n133), .CO(
DP_OP_454J321_123_2743_n134) );
CMPR42X1TS DP_OP_454J321_123_2743_U68 ( .A(DP_OP_454J321_123_2743_n133), .B(
DP_OP_454J321_123_2743_n249), .C(DP_OP_454J321_123_2743_n130), .D(
DP_OP_454J321_123_2743_n199), .ICI(DP_OP_454J321_123_2743_n155), .S(
DP_OP_454J321_123_2743_n128), .ICO(DP_OP_454J321_123_2743_n126), .CO(
DP_OP_454J321_123_2743_n127) );
CMPR42X1TS DP_OP_454J321_123_2743_U67 ( .A(DP_OP_454J321_123_2743_n223), .B(
DP_OP_454J321_123_2743_n210), .C(DP_OP_454J321_123_2743_n131), .D(
DP_OP_454J321_123_2743_n236), .ICI(DP_OP_454J321_123_2743_n129), .S(
DP_OP_454J321_123_2743_n125), .ICO(DP_OP_454J321_123_2743_n123), .CO(
DP_OP_454J321_123_2743_n124) );
CMPR42X1TS DP_OP_454J321_123_2743_U66 ( .A(DP_OP_454J321_123_2743_n198), .B(
DP_OP_454J321_123_2743_n248), .C(DP_OP_454J321_123_2743_n187), .D(
DP_OP_454J321_123_2743_n126), .ICI(DP_OP_454J321_123_2743_n125), .S(
DP_OP_454J321_123_2743_n122), .ICO(DP_OP_454J321_123_2743_n120), .CO(
DP_OP_454J321_123_2743_n121) );
CMPR42X1TS DP_OP_454J321_123_2743_U64 ( .A(DP_OP_454J321_123_2743_n123), .B(
DP_OP_454J321_123_2743_n235), .C(DP_OP_454J321_123_2743_n119), .D(
DP_OP_454J321_123_2743_n197), .ICI(DP_OP_454J321_123_2743_n124), .S(
DP_OP_454J321_123_2743_n117), .ICO(DP_OP_454J321_123_2743_n115), .CO(
DP_OP_454J321_123_2743_n116) );
CMPR42X1TS DP_OP_454J321_123_2743_U63 ( .A(DP_OP_454J321_123_2743_n120), .B(
DP_OP_454J321_123_2743_n117), .C(DP_OP_454J321_123_2743_n247), .D(
DP_OP_454J321_123_2743_n121), .ICI(DP_OP_454J321_123_2743_n186), .S(
DP_OP_454J321_123_2743_n114), .ICO(DP_OP_454J321_123_2743_n112), .CO(
DP_OP_454J321_123_2743_n113) );
CMPR42X1TS DP_OP_454J321_123_2743_U61 ( .A(DP_OP_454J321_123_2743_n196), .B(
DP_OP_454J321_123_2743_n111), .C(DP_OP_454J321_123_2743_n115), .D(
DP_OP_454J321_123_2743_n234), .ICI(DP_OP_454J321_123_2743_n116), .S(
DP_OP_454J321_123_2743_n109), .ICO(DP_OP_454J321_123_2743_n107), .CO(
DP_OP_454J321_123_2743_n108) );
CMPR42X1TS DP_OP_454J321_123_2743_U60 ( .A(DP_OP_454J321_123_2743_n246), .B(
DP_OP_454J321_123_2743_n172), .C(DP_OP_454J321_123_2743_n185), .D(
DP_OP_454J321_123_2743_n109), .ICI(DP_OP_454J321_123_2743_n112), .S(
DP_OP_454J321_123_2743_n106), .ICO(DP_OP_454J321_123_2743_n104), .CO(
DP_OP_454J321_123_2743_n105) );
CMPR42X1TS DP_OP_454J321_123_2743_U58 ( .A(DP_OP_454J321_123_2743_n195), .B(
DP_OP_454J321_123_2743_n245), .C(DP_OP_454J321_123_2743_n103), .D(
DP_OP_454J321_123_2743_n107), .ICI(DP_OP_454J321_123_2743_n233), .S(
DP_OP_454J321_123_2743_n101), .ICO(DP_OP_454J321_123_2743_n99), .CO(
DP_OP_454J321_123_2743_n100) );
CMPR42X1TS DP_OP_454J321_123_2743_U57 ( .A(DP_OP_454J321_123_2743_n108), .B(
DP_OP_454J321_123_2743_n171), .C(DP_OP_454J321_123_2743_n184), .D(
DP_OP_454J321_123_2743_n101), .ICI(DP_OP_454J321_123_2743_n104), .S(
DP_OP_454J321_123_2743_n98), .ICO(DP_OP_454J321_123_2743_n96), .CO(
DP_OP_454J321_123_2743_n97) );
CMPR42X1TS DP_OP_454J321_123_2743_U54 ( .A(DP_OP_454J321_123_2743_n219), .B(
DP_OP_454J321_123_2743_n102), .C(DP_OP_454J321_123_2743_n94), .D(
DP_OP_454J321_123_2743_n99), .ICI(DP_OP_454J321_123_2743_n232), .S(
DP_OP_454J321_123_2743_n92), .ICO(DP_OP_454J321_123_2743_n90), .CO(
DP_OP_454J321_123_2743_n91) );
CMPR42X1TS DP_OP_454J321_123_2743_U53 ( .A(DP_OP_454J321_123_2743_n170), .B(
DP_OP_454J321_123_2743_n183), .C(DP_OP_454J321_123_2743_n100), .D(
DP_OP_454J321_123_2743_n96), .ICI(DP_OP_454J321_123_2743_n92), .S(
DP_OP_454J321_123_2743_n89), .ICO(DP_OP_454J321_123_2743_n87), .CO(
DP_OP_454J321_123_2743_n88) );
CMPR42X1TS DP_OP_454J321_123_2743_U50 ( .A(DP_OP_454J321_123_2743_n231), .B(
DP_OP_454J321_123_2743_n93), .C(DP_OP_454J321_123_2743_n84), .D(
DP_OP_454J321_123_2743_n90), .ICI(DP_OP_454J321_123_2743_n218), .S(
DP_OP_454J321_123_2743_n82), .ICO(DP_OP_454J321_123_2743_n80), .CO(
DP_OP_454J321_123_2743_n81) );
CMPR42X1TS DP_OP_454J321_123_2743_U49 ( .A(DP_OP_454J321_123_2743_n169), .B(
DP_OP_454J321_123_2743_n182), .C(DP_OP_454J321_123_2743_n91), .D(
DP_OP_454J321_123_2743_n87), .ICI(DP_OP_454J321_123_2743_n82), .S(
DP_OP_454J321_123_2743_n79), .ICO(DP_OP_454J321_123_2743_n77), .CO(
DP_OP_454J321_123_2743_n78) );
CMPR42X1TS DP_OP_454J321_123_2743_U47 ( .A(DP_OP_454J321_123_2743_n204), .B(
DP_OP_454J321_123_2743_n83), .C(DP_OP_454J321_123_2743_n76), .D(
DP_OP_454J321_123_2743_n80), .ICI(DP_OP_454J321_123_2743_n217), .S(
DP_OP_454J321_123_2743_n74), .ICO(DP_OP_454J321_123_2743_n72), .CO(
DP_OP_454J321_123_2743_n73) );
CMPR42X1TS DP_OP_454J321_123_2743_U46 ( .A(DP_OP_454J321_123_2743_n168), .B(
DP_OP_454J321_123_2743_n181), .C(DP_OP_454J321_123_2743_n81), .D(
DP_OP_454J321_123_2743_n74), .ICI(DP_OP_454J321_123_2743_n77), .S(
DP_OP_454J321_123_2743_n71), .ICO(DP_OP_454J321_123_2743_n69), .CO(
DP_OP_454J321_123_2743_n70) );
CMPR42X1TS DP_OP_454J321_123_2743_U44 ( .A(DP_OP_454J321_123_2743_n68), .B(
DP_OP_454J321_123_2743_n216), .C(DP_OP_454J321_123_2743_n75), .D(
DP_OP_454J321_123_2743_n72), .ICI(DP_OP_454J321_123_2743_n203), .S(
DP_OP_454J321_123_2743_n66), .ICO(DP_OP_454J321_123_2743_n64), .CO(
DP_OP_454J321_123_2743_n65) );
CMPR42X1TS DP_OP_454J321_123_2743_U43 ( .A(DP_OP_454J321_123_2743_n167), .B(
DP_OP_454J321_123_2743_n180), .C(DP_OP_454J321_123_2743_n73), .D(
DP_OP_454J321_123_2743_n66), .ICI(DP_OP_454J321_123_2743_n69), .S(
DP_OP_454J321_123_2743_n63), .ICO(DP_OP_454J321_123_2743_n61), .CO(
DP_OP_454J321_123_2743_n62) );
CMPR42X1TS DP_OP_454J321_123_2743_U42 ( .A(DP_OP_454J321_123_2743_n215), .B(
DP_OP_454J321_123_2743_n67), .C(DP_OP_454J321_123_2743_n191), .D(
DP_OP_454J321_123_2743_n64), .ICI(DP_OP_454J321_123_2743_n202), .S(
DP_OP_454J321_123_2743_n60), .ICO(DP_OP_454J321_123_2743_n58), .CO(
DP_OP_454J321_123_2743_n59) );
CMPR42X1TS DP_OP_454J321_123_2743_U41 ( .A(DP_OP_454J321_123_2743_n166), .B(
DP_OP_454J321_123_2743_n179), .C(DP_OP_454J321_123_2743_n65), .D(
DP_OP_454J321_123_2743_n60), .ICI(DP_OP_454J321_123_2743_n61), .S(
DP_OP_454J321_123_2743_n57), .ICO(DP_OP_454J321_123_2743_n55), .CO(
DP_OP_454J321_123_2743_n56) );
CMPR42X1TS DP_OP_454J321_123_2743_U38 ( .A(DP_OP_454J321_123_2743_n165), .B(
DP_OP_454J321_123_2743_n178), .C(DP_OP_454J321_123_2743_n52), .D(
DP_OP_454J321_123_2743_n59), .ICI(DP_OP_454J321_123_2743_n55), .S(
DP_OP_454J321_123_2743_n50), .ICO(DP_OP_454J321_123_2743_n48), .CO(
DP_OP_454J321_123_2743_n49) );
CMPR42X1TS DP_OP_454J321_123_2743_U36 ( .A(DP_OP_454J321_123_2743_n164), .B(
DP_OP_454J321_123_2743_n177), .C(DP_OP_454J321_123_2743_n51), .D(
DP_OP_454J321_123_2743_n47), .ICI(DP_OP_454J321_123_2743_n48), .S(
DP_OP_454J321_123_2743_n45), .ICO(DP_OP_454J321_123_2743_n43), .CO(
DP_OP_454J321_123_2743_n44) );
CMPR42X1TS DP_OP_454J321_123_2743_U34 ( .A(DP_OP_454J321_123_2743_n42), .B(
DP_OP_454J321_123_2743_n163), .C(DP_OP_454J321_123_2743_n176), .D(
DP_OP_454J321_123_2743_n46), .ICI(DP_OP_454J321_123_2743_n43), .S(
DP_OP_454J321_123_2743_n40), .ICO(DP_OP_454J321_123_2743_n38), .CO(
DP_OP_454J321_123_2743_n39) );
CMPR42X1TS DP_OP_454J321_123_2743_U33 ( .A(DP_OP_454J321_123_2743_n188), .B(
DP_OP_454J321_123_2743_n41), .C(DP_OP_454J321_123_2743_n162), .D(
DP_OP_454J321_123_2743_n175), .ICI(DP_OP_454J321_123_2743_n38), .S(
DP_OP_454J321_123_2743_n37), .ICO(DP_OP_454J321_123_2743_n35), .CO(
DP_OP_454J321_123_2743_n36) );
CMPR42X1TS mult_x_254_U69 ( .A(mult_x_254_n196), .B(mult_x_254_n232), .C(
mult_x_254_n220), .D(mult_x_254_n208), .ICI(mult_x_254_n136), .S(
mult_x_254_n133), .ICO(mult_x_254_n131), .CO(mult_x_254_n132) );
CMPR42X1TS mult_x_254_U67 ( .A(mult_x_254_n219), .B(mult_x_254_n195), .C(
mult_x_254_n207), .D(mult_x_254_n131), .ICI(mult_x_254_n130), .S(
mult_x_254_n128), .ICO(mult_x_254_n126), .CO(mult_x_254_n127) );
CMPR42X1TS mult_x_254_U65 ( .A(mult_x_254_n206), .B(mult_x_254_n194), .C(
mult_x_254_n129), .D(mult_x_254_n126), .ICI(mult_x_254_n125), .S(
mult_x_254_n123), .ICO(mult_x_254_n121), .CO(mult_x_254_n122) );
CMPR42X1TS mult_x_254_U62 ( .A(mult_x_254_n205), .B(mult_x_254_n124), .C(
mult_x_254_n120), .D(mult_x_254_n118), .ICI(mult_x_254_n121), .S(
mult_x_254_n116), .ICO(mult_x_254_n114), .CO(mult_x_254_n115) );
CMPR42X1TS mult_x_254_U61 ( .A(mult_x_254_n168), .B(mult_x_254_n228), .C(
mult_x_254_n216), .D(mult_x_254_n204), .ICI(mult_x_254_n180), .S(
mult_x_254_n113), .ICO(mult_x_254_n111), .CO(mult_x_254_n112) );
CMPR42X1TS mult_x_254_U60 ( .A(mult_x_254_n192), .B(mult_x_254_n119), .C(
mult_x_254_n117), .D(mult_x_254_n114), .ICI(mult_x_254_n113), .S(
mult_x_254_n110), .ICO(mult_x_254_n108), .CO(mult_x_254_n109) );
CMPR42X1TS mult_x_254_U58 ( .A(mult_x_254_n215), .B(mult_x_254_n167), .C(
mult_x_254_n203), .D(mult_x_254_n179), .ICI(mult_x_254_n107), .S(
mult_x_254_n105), .ICO(mult_x_254_n103), .CO(mult_x_254_n104) );
CMPR42X1TS mult_x_254_U57 ( .A(mult_x_254_n191), .B(mult_x_254_n111), .C(
mult_x_254_n108), .D(mult_x_254_n112), .ICI(mult_x_254_n105), .S(
mult_x_254_n102), .ICO(mult_x_254_n100), .CO(mult_x_254_n101) );
CMPR42X1TS mult_x_254_U55 ( .A(mult_x_254_n202), .B(mult_x_254_n166), .C(
mult_x_254_n190), .D(mult_x_254_n178), .ICI(mult_x_254_n99), .S(
mult_x_254_n97), .ICO(mult_x_254_n95), .CO(mult_x_254_n96) );
CMPR42X1TS mult_x_254_U54 ( .A(mult_x_254_n106), .B(mult_x_254_n103), .C(
mult_x_254_n104), .D(mult_x_254_n97), .ICI(mult_x_254_n100), .S(
mult_x_254_n94), .ICO(mult_x_254_n92), .CO(mult_x_254_n93) );
CMPR42X1TS mult_x_254_U51 ( .A(mult_x_254_n189), .B(mult_x_254_n165), .C(
mult_x_254_n213), .D(n2597), .ICI(mult_x_254_n90), .S(mult_x_254_n88),
.ICO(mult_x_254_n86), .CO(mult_x_254_n87) );
CMPR42X1TS mult_x_254_U50 ( .A(mult_x_254_n95), .B(mult_x_254_n98), .C(
mult_x_254_n96), .D(mult_x_254_n88), .ICI(mult_x_254_n92), .S(
mult_x_254_n85), .ICO(mult_x_254_n83), .CO(mult_x_254_n84) );
CMPR42X1TS mult_x_254_U47 ( .A(mult_x_254_n176), .B(mult_x_254_n212), .C(
mult_x_254_n200), .D(mult_x_254_n164), .ICI(mult_x_254_n89), .S(
mult_x_254_n78), .ICO(mult_x_254_n76), .CO(mult_x_254_n77) );
CMPR42X1TS mult_x_254_U46 ( .A(mult_x_254_n86), .B(mult_x_254_n80), .C(
mult_x_254_n87), .D(mult_x_254_n78), .ICI(mult_x_254_n83), .S(
mult_x_254_n75), .ICO(mult_x_254_n73), .CO(mult_x_254_n74) );
CMPR42X1TS mult_x_254_U44 ( .A(mult_x_254_n175), .B(mult_x_254_n163), .C(
mult_x_254_n199), .D(mult_x_254_n211), .ICI(mult_x_254_n72), .S(
mult_x_254_n70), .ICO(mult_x_254_n68), .CO(mult_x_254_n69) );
CMPR42X1TS mult_x_254_U43 ( .A(mult_x_254_n76), .B(mult_x_254_n79), .C(
mult_x_254_n77), .D(mult_x_254_n70), .ICI(mult_x_254_n73), .S(
mult_x_254_n67), .ICO(mult_x_254_n65), .CO(mult_x_254_n66) );
CMPR42X1TS mult_x_254_U41 ( .A(mult_x_254_n64), .B(mult_x_254_n174), .C(
mult_x_254_n186), .D(mult_x_254_n162), .ICI(mult_x_254_n198), .S(
mult_x_254_n62), .ICO(mult_x_254_n60), .CO(mult_x_254_n61) );
CMPR42X1TS mult_x_254_U40 ( .A(mult_x_254_n68), .B(mult_x_254_n71), .C(
mult_x_254_n69), .D(mult_x_254_n62), .ICI(mult_x_254_n65), .S(
mult_x_254_n59), .ICO(mult_x_254_n57), .CO(mult_x_254_n58) );
CMPR42X1TS mult_x_254_U39 ( .A(mult_x_254_n63), .B(mult_x_254_n151), .C(
mult_x_254_n185), .D(mult_x_254_n173), .ICI(mult_x_254_n161), .S(
mult_x_254_n56), .ICO(mult_x_254_n54), .CO(mult_x_254_n55) );
CMPR42X1TS mult_x_254_U38 ( .A(mult_x_254_n197), .B(mult_x_254_n60), .C(
mult_x_254_n61), .D(mult_x_254_n56), .ICI(mult_x_254_n57), .S(
mult_x_254_n53), .ICO(mult_x_254_n51), .CO(mult_x_254_n52) );
CMPR42X1TS mult_x_254_U35 ( .A(mult_x_254_n160), .B(mult_x_254_n54), .C(
mult_x_254_n48), .D(mult_x_254_n55), .ICI(mult_x_254_n51), .S(
mult_x_254_n46), .ICO(mult_x_254_n44), .CO(mult_x_254_n45) );
CMPR42X1TS mult_x_254_U33 ( .A(mult_x_254_n159), .B(mult_x_254_n183), .C(
mult_x_254_n43), .D(mult_x_254_n47), .ICI(mult_x_254_n44), .S(
mult_x_254_n41), .ICO(mult_x_254_n39), .CO(mult_x_254_n40) );
CMPR42X1TS mult_x_254_U31 ( .A(mult_x_254_n38), .B(mult_x_254_n170), .C(
mult_x_254_n158), .D(mult_x_254_n42), .ICI(mult_x_254_n39), .S(
mult_x_254_n36), .ICO(mult_x_254_n34), .CO(mult_x_254_n35) );
CMPR42X1TS mult_x_254_U30 ( .A(mult_x_254_n37), .B(mult_x_254_n149), .C(
mult_x_254_n157), .D(mult_x_254_n169), .ICI(mult_x_254_n34), .S(
mult_x_254_n33), .ICO(mult_x_254_n31), .CO(mult_x_254_n32) );
CMPR42X1TS mult_x_219_U69 ( .A(mult_x_219_n190), .B(mult_x_219_n226), .C(
mult_x_219_n214), .D(mult_x_219_n202), .ICI(mult_x_219_n136), .S(
mult_x_219_n133), .ICO(mult_x_219_n131), .CO(mult_x_219_n132) );
CMPR42X1TS mult_x_219_U67 ( .A(mult_x_219_n213), .B(mult_x_219_n189), .C(
mult_x_219_n201), .D(mult_x_219_n131), .ICI(mult_x_219_n130), .S(
mult_x_219_n128), .ICO(mult_x_219_n126), .CO(mult_x_219_n127) );
CMPR42X1TS mult_x_219_U65 ( .A(mult_x_219_n200), .B(mult_x_219_n188), .C(
mult_x_219_n129), .D(mult_x_219_n126), .ICI(mult_x_219_n125), .S(
mult_x_219_n123), .ICO(mult_x_219_n121), .CO(mult_x_219_n122) );
CMPR42X1TS mult_x_219_U62 ( .A(mult_x_219_n199), .B(mult_x_219_n124), .C(
mult_x_219_n120), .D(mult_x_219_n118), .ICI(mult_x_219_n121), .S(
mult_x_219_n116), .ICO(mult_x_219_n114), .CO(mult_x_219_n115) );
CMPR42X1TS mult_x_219_U61 ( .A(mult_x_219_n162), .B(mult_x_219_n222), .C(
mult_x_219_n210), .D(mult_x_219_n198), .ICI(mult_x_219_n174), .S(
mult_x_219_n113), .ICO(mult_x_219_n111), .CO(mult_x_219_n112) );
CMPR42X1TS mult_x_219_U60 ( .A(mult_x_219_n186), .B(mult_x_219_n119), .C(
mult_x_219_n117), .D(mult_x_219_n114), .ICI(mult_x_219_n113), .S(
mult_x_219_n110), .ICO(mult_x_219_n108), .CO(mult_x_219_n109) );
CMPR42X1TS mult_x_219_U58 ( .A(mult_x_219_n209), .B(mult_x_219_n161), .C(
mult_x_219_n197), .D(mult_x_219_n173), .ICI(mult_x_219_n107), .S(
mult_x_219_n105), .ICO(mult_x_219_n103), .CO(mult_x_219_n104) );
CMPR42X1TS mult_x_219_U57 ( .A(mult_x_219_n185), .B(mult_x_219_n111), .C(
mult_x_219_n108), .D(mult_x_219_n112), .ICI(mult_x_219_n105), .S(
mult_x_219_n102), .ICO(mult_x_219_n100), .CO(mult_x_219_n101) );
CMPR42X1TS mult_x_219_U55 ( .A(mult_x_219_n196), .B(mult_x_219_n160), .C(
mult_x_219_n184), .D(mult_x_219_n172), .ICI(mult_x_219_n99), .S(
mult_x_219_n97), .ICO(mult_x_219_n95), .CO(mult_x_219_n96) );
CMPR42X1TS mult_x_219_U54 ( .A(mult_x_219_n106), .B(mult_x_219_n103), .C(
mult_x_219_n104), .D(mult_x_219_n97), .ICI(mult_x_219_n100), .S(
mult_x_219_n94), .ICO(mult_x_219_n92), .CO(mult_x_219_n93) );
CMPR42X1TS mult_x_219_U51 ( .A(mult_x_219_n183), .B(mult_x_219_n159), .C(
mult_x_219_n207), .D(n2596), .ICI(mult_x_219_n90), .S(mult_x_219_n88),
.ICO(mult_x_219_n86), .CO(mult_x_219_n87) );
CMPR42X1TS mult_x_219_U50 ( .A(mult_x_219_n95), .B(mult_x_219_n98), .C(
mult_x_219_n96), .D(mult_x_219_n88), .ICI(mult_x_219_n92), .S(
mult_x_219_n85), .ICO(mult_x_219_n83), .CO(mult_x_219_n84) );
CMPR42X1TS mult_x_219_U47 ( .A(mult_x_219_n170), .B(mult_x_219_n206), .C(
mult_x_219_n194), .D(mult_x_219_n158), .ICI(mult_x_219_n89), .S(
mult_x_219_n78), .ICO(mult_x_219_n76), .CO(mult_x_219_n77) );
CMPR42X1TS mult_x_219_U46 ( .A(mult_x_219_n86), .B(mult_x_219_n80), .C(
mult_x_219_n87), .D(mult_x_219_n78), .ICI(mult_x_219_n83), .S(
mult_x_219_n75), .ICO(mult_x_219_n73), .CO(mult_x_219_n74) );
CMPR42X1TS mult_x_219_U44 ( .A(mult_x_219_n169), .B(mult_x_219_n157), .C(
mult_x_219_n193), .D(mult_x_219_n205), .ICI(mult_x_219_n72), .S(
mult_x_219_n70), .ICO(mult_x_219_n68), .CO(mult_x_219_n69) );
CMPR42X1TS mult_x_219_U43 ( .A(mult_x_219_n76), .B(mult_x_219_n79), .C(
mult_x_219_n77), .D(mult_x_219_n70), .ICI(mult_x_219_n73), .S(
mult_x_219_n67), .ICO(mult_x_219_n65), .CO(mult_x_219_n66) );
CMPR42X1TS mult_x_219_U41 ( .A(n933), .B(mult_x_219_n168), .C(
mult_x_219_n180), .D(mult_x_219_n156), .ICI(mult_x_219_n192), .S(
mult_x_219_n62), .ICO(mult_x_219_n60), .CO(mult_x_219_n61) );
CMPR42X1TS mult_x_219_U40 ( .A(mult_x_219_n68), .B(mult_x_219_n71), .C(
mult_x_219_n69), .D(mult_x_219_n62), .ICI(mult_x_219_n65), .S(
mult_x_219_n59), .ICO(mult_x_219_n57), .CO(mult_x_219_n58) );
CMPR42X1TS mult_x_219_U39 ( .A(FPMULT_Op_MY[16]), .B(n981), .C(
mult_x_219_n179), .D(mult_x_219_n167), .ICI(mult_x_219_n155), .S(
mult_x_219_n56), .ICO(mult_x_219_n54), .CO(mult_x_219_n55) );
CMPR42X1TS mult_x_219_U38 ( .A(mult_x_219_n191), .B(mult_x_219_n60), .C(
mult_x_219_n61), .D(mult_x_219_n56), .ICI(mult_x_219_n57), .S(
mult_x_219_n53), .ICO(mult_x_219_n51), .CO(mult_x_219_n52) );
CMPR42X1TS mult_x_219_U35 ( .A(mult_x_219_n154), .B(mult_x_219_n54), .C(
mult_x_219_n48), .D(mult_x_219_n55), .ICI(mult_x_219_n51), .S(
mult_x_219_n46), .ICO(mult_x_219_n44), .CO(mult_x_219_n45) );
CMPR42X1TS mult_x_219_U33 ( .A(mult_x_219_n153), .B(mult_x_219_n177), .C(
mult_x_219_n43), .D(mult_x_219_n47), .ICI(mult_x_219_n44), .S(
mult_x_219_n41), .ICO(mult_x_219_n39), .CO(mult_x_219_n40) );
CMPR42X1TS mult_x_219_U31 ( .A(n1026), .B(mult_x_219_n164), .C(
mult_x_219_n152), .D(mult_x_219_n42), .ICI(mult_x_219_n39), .S(
mult_x_219_n36), .ICO(mult_x_219_n34), .CO(mult_x_219_n35) );
CMPR42X1TS mult_x_219_U30 ( .A(FPMULT_Op_MY[20]), .B(n1000), .C(
mult_x_219_n151), .D(mult_x_219_n163), .ICI(mult_x_219_n34), .S(
mult_x_219_n33), .ICO(mult_x_219_n31), .CO(mult_x_219_n32) );
DFFSXLTS R_16 ( .D(n2733), .CK(
FPMULT_Operands_load_reg_XMRegister_net8272321), .SN(n2774), .Q(n2827),
.QN(n2722) );
DFFSXLTS R_4 ( .D(n2738), .CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .SN(n2817), .Q(n2826) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_0_ ( .D(n2608), .CK(
FPSENCOS_ITER_CONT_net8272393), .RN(n2814), .Q(
FPSENCOS_cont_iter_out[0]), .QN(n2608) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7_5), .CK(
FPADDSUB_inst_ShiftRegister_net8272231), .RN(n2772), .Q(busy), .QN(
n2693) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_2_ ( .D(FPSENCOS_ITER_CONT_N4), .CK(
FPSENCOS_ITER_CONT_net8272393), .RN(n2815), .Q(
FPSENCOS_cont_iter_out[2]), .QN(n2598) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_2_ ( .D(
FPMULT_FS_Module_state_next[2]), .CK(FPMULT_FS_Module_net8272339),
.RN(n2793), .Q(FPMULT_FS_Module_state_reg[2]), .QN(n2599) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_3_ ( .D(FPSENCOS_ITER_CONT_N5), .CK(
FPSENCOS_ITER_CONT_net8272393), .RN(n2812), .Q(
FPSENCOS_cont_iter_out[3]), .QN(n2600) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n829), .CK(FPMULT_FS_Module_net8272339),
.RN(n2783), .Q(FPMULT_FSM_selector_B[1]), .QN(n2652) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(FPADDSUB_Raw_mant_SGF[5]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2745), .Q(
FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n2694) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_0_ ( .D(n843), .CK(clk), .RN(n2814), .Q(
FPSENCOS_cont_var_out[0]), .QN(n2649) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(
FPMULT_FS_Module_state_next[1]), .CK(FPMULT_FS_Module_net8272339),
.RN(n2793), .Q(FPMULT_FS_Module_state_reg[1]), .QN(n2669) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(add_subt_data2[12]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2772), .Q(
FPADDSUB_intDY_EWSW[12]), .QN(n2673) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(add_subt_data2[7]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2756), .Q(
FPADDSUB_intDY_EWSW[7]), .QN(n2695) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(add_subt_data2[5]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2746), .Q(
FPADDSUB_intDY_EWSW[5]), .QN(n2696) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(add_subt_data2[3]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2760), .Q(
FPADDSUB_intDY_EWSW[3]), .QN(n2720) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(add_subt_data2[15]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2772), .Q(
FPADDSUB_intDY_EWSW[15]), .QN(n2713) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(add_subt_data1[16]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2754), .Q(
FPADDSUB_intDX_EWSW[16]), .QN(n2679) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(add_subt_data1[10]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2772), .Q(
FPADDSUB_intDX_EWSW[10]), .QN(n2665) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(add_subt_data1[6]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2761), .Q(
FPADDSUB_intDX_EWSW[6]), .QN(n2678) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(add_subt_data1[4]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2748), .Q(
FPADDSUB_intDX_EWSW[4]), .QN(n2677) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(add_subt_data2[23]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2750), .Q(
FPADDSUB_intDY_EWSW[23]), .QN(n2742) );
DFFTRX1TS FPMULT_Sgf_operation_EVEN1_right_DatO_reg_0_ ( .D(FPMULT_Op_MY[0]),
.RN(n1005), .CK(clk), .Q(FPMULT_Sgf_operation_Result[0]) );
DFFTRX1TS FPMULT_Sgf_operation_EVEN1_middle_DatO_reg_0_ ( .D(
DP_OP_454J321_123_2743_n367), .RN(DP_OP_454J321_123_2743_n453), .CK(
clk), .QN(intadd_1083_B_0_) );
DFFTRX1TS FPMULT_Sgf_operation_EVEN1_left_DatO_reg_0_ ( .D(FPMULT_Op_MY[12]),
.RN(FPMULT_Op_MX[12]), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[0]) );
DFFSX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n2791), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]) );
DFFSXLTS R_21 ( .D(n2729), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .SN(n1687), .Q(n2825)
);
DFFRXLTS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(
FPADDSUB_Raw_mant_SGF[18]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2768), .Q(FPADDSUB_Raw_mant_NRM_SWR[18]), .QN(n2645) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(add_subt_data1[23]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2765), .Q(
FPADDSUB_intDX_EWSW[23]), .QN(n2683) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(FPADDSUB_Data_array_SWR[21]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2772), .Q(
FPADDSUB_Data_array_SWR[47]), .QN(n2691) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_12_ ( .D(Data_2[12]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2774), .Q(
FPMULT_Op_MY[12]), .QN(n927) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_0_ ( .D(Data_2[0]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2783), .Q(
FPMULT_Op_MY[0]), .QN(n930) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_1_ ( .D(Data_1[1]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2783), .Q(
FPMULT_Op_MX[1]), .QN(n1025) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_16_ ( .D(Data_2[16]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n966), .Q(
FPMULT_Op_MY[16]), .QN(n933) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_18_ ( .D(Data_2[18]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2779), .Q(
FPMULT_Op_MY[18]), .QN(n934) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_20_ ( .D(Data_2[20]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2781), .Q(
FPMULT_Op_MY[20]), .QN(n1026) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_14_ ( .D(Data_2[14]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2782), .Q(
FPMULT_Op_MY[14]), .QN(n1018) );
DFFRX4TS FPMULT_Sel_A_Q_reg_0_ ( .D(1'b1), .CK(n2835), .RN(n2783), .Q(
FPMULT_FSM_selector_A) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_1_ ( .D(n842), .CK(clk), .RN(n2815), .Q(
FPSENCOS_cont_var_out[1]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(
FPADDSUB_Raw_mant_SGF[11]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2754), .Q(FPADDSUB_Raw_mant_NRM_SWR[11]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(
FPADDSUB_Raw_mant_SGF[23]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n1690), .Q(FPADDSUB_Raw_mant_NRM_SWR[23]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n2814), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[24]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2769), .Q(
FPADDSUB_DmP_mant_SFG_SWR[24]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_10_ ( .D(Data_1[10]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2781), .Q(
FPMULT_Op_MX[10]), .QN(n1008) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(
FPADDSUB_Raw_mant_SGF[24]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2755), .Q(FPADDSUB_Raw_mant_NRM_SWR[24]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[8]), .CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2765), .Q(FPADDSUB_DmP_mant_SFG_SWR[8]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[6]), .CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2754), .Q(FPADDSUB_DmP_mant_SFG_SWR[6]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[4]), .CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2748), .Q(FPADDSUB_DmP_mant_SFG_SWR[4]) );
DFFRX2TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n844), .CK(clk), .RN(n2748), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[22]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2769), .Q(
FPADDSUB_DmP_mant_SFG_SWR[22]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[20]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2769), .Q(
FPADDSUB_DmP_mant_SFG_SWR[20]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[18]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n1690), .Q(
FPADDSUB_DmP_mant_SFG_SWR[18]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[16]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2762), .Q(
FPADDSUB_DmP_mant_SFG_SWR[16]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[14]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2753), .Q(
FPADDSUB_DmP_mant_SFG_SWR[14]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[12]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2758), .Q(
FPADDSUB_DmP_mant_SFG_SWR[12]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[10]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2756), .Q(
FPADDSUB_DmP_mant_SFG_SWR[10]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(
FPADDSUB_Raw_mant_SGF[21]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2749), .Q(FPADDSUB_Raw_mant_NRM_SWR[21]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[3]), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n1690), .Q(
FPADDSUB_shift_value_SHT2_EWR[3]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(
FPADDSUB_Raw_mant_SGF[10]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2772), .Q(FPADDSUB_Raw_mant_NRM_SWR[10]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(
FPADDSUB_Raw_mant_SGF[16]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2748), .Q(FPADDSUB_Raw_mant_NRM_SWR[16]) );
DFFRX4TS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_OP_FLAG_SHT2), .CK(
FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2754), .Q(n1031), .QN(n2788)
);
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_14_ ( .D(Data_1[14]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2779), .Q(
FPMULT_Op_MX[14]), .QN(n1016) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(FPADDSUB_Data_array_SWR[17]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2745), .Q(
FPADDSUB_Data_array_SWR[43]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(FPADDSUB_Data_array_SWR[16]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2748), .Q(
FPADDSUB_Data_array_SWR[42]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_18_ ( .D(Data_1[18]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2774), .Q(
FPMULT_Op_MX[18]), .QN(n1022) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_16_ ( .D(Data_1[16]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2776), .Q(
FPMULT_Op_MX[16]), .QN(n1024) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_6_ ( .D(Data_1[6]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2786), .Q(
FPMULT_Op_MX[6]), .QN(n1010) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(FPADDSUB_Raw_mant_SGF[7]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n1690), .Q(
FPADDSUB_Raw_mant_NRM_SWR[7]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(
FPADDSUB_Raw_mant_SGF[19]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2757), .Q(FPADDSUB_Raw_mant_NRM_SWR[19]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[2]), .CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2763), .Q(FPADDSUB_DmP_mant_SFG_SWR[2]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(FPADDSUB_Data_array_SWR[18]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2770), .Q(
FPADDSUB_Data_array_SWR[44]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(FPADDSUB_Data_array_SWR[19]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2746), .Q(
FPADDSUB_Data_array_SWR[45]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(FPADDSUB_Raw_mant_SGF[8]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2768), .Q(
FPADDSUB_Raw_mant_NRM_SWR[8]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_Y[27]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2806), .Q(FPSENCOS_d_ff2_Y[27]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n2812), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_X[27]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2809), .Q(FPSENCOS_d_ff2_X[27]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(add_subt_data1[29]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2763), .Q(
FPADDSUB_intDX_EWSW[29]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(
FPADDSUB_formatted_number_W[7]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n1690), .Q(
result_add_subt[7]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(
FPADDSUB_formatted_number_W[6]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2746), .Q(
result_add_subt[6]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(
FPADDSUB_formatted_number_W[3]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2767), .Q(
result_add_subt[3]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(
FPADDSUB_formatted_number_W[1]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2750), .Q(
result_add_subt[1]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(
FPADDSUB_formatted_number_W[0]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2759), .Q(
result_add_subt[0]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(
FPADDSUB_formatted_number_W[31]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2765), .Q(
result_add_subt[31]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(
FPADDSUB_formatted_number_W[9]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2763), .Q(
result_add_subt[9]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(
FPADDSUB_formatted_number_W[12]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2764), .Q(
result_add_subt[12]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(
FPADDSUB_formatted_number_W[10]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2748), .Q(
result_add_subt[10]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(
FPADDSUB_formatted_number_W[8]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2754), .Q(
result_add_subt[8]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(
FPADDSUB_formatted_number_W[11]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2746), .Q(
result_add_subt[11]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(
FPADDSUB_formatted_number_W[14]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2747), .Q(
result_add_subt[14]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(
FPADDSUB_formatted_number_W[13]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2747), .Q(
result_add_subt[13]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(
FPADDSUB_formatted_number_W[5]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2761), .Q(
result_add_subt[5]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(
FPADDSUB_formatted_number_W[15]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2754), .Q(
result_add_subt[15]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(
FPADDSUB_formatted_number_W[4]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2772), .Q(
result_add_subt[4]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(
FPADDSUB_formatted_number_W[17]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2760), .Q(
result_add_subt[17]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(
FPADDSUB_formatted_number_W[20]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2762), .Q(
result_add_subt[20]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(
FPADDSUB_formatted_number_W[18]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2743), .Q(
result_add_subt[18]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(
FPADDSUB_formatted_number_W[16]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2757), .Q(
result_add_subt[16]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(
FPADDSUB_formatted_number_W[2]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2753), .Q(
result_add_subt[2]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(
FPADDSUB_formatted_number_W[21]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n1690), .Q(
result_add_subt[21]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(
FPADDSUB_formatted_number_W[19]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2748), .Q(
result_add_subt[19]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(
FPADDSUB_formatted_number_W[22]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2754), .Q(
result_add_subt[22]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(
FPADDSUB_formatted_number_W[30]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2771), .Q(
result_add_subt[30]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(
FPADDSUB_formatted_number_W[29]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2770), .Q(
result_add_subt[29]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(
FPADDSUB_formatted_number_W[28]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2743), .Q(
result_add_subt[28]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(
FPADDSUB_formatted_number_W[27]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2757), .Q(
result_add_subt[27]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(
FPADDSUB_formatted_number_W[26]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2750), .Q(
result_add_subt[26]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(
FPADDSUB_formatted_number_W[25]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2759), .Q(
result_add_subt[25]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(
FPADDSUB_formatted_number_W[24]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2765), .Q(
result_add_subt[24]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(
FPADDSUB_formatted_number_W[23]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8272069), .RN(n2763), .Q(
result_add_subt[23]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(add_subt_data1[25]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2764), .Q(
FPADDSUB_intDX_EWSW[25]), .QN(n952) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(add_subt_data1[26]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2770), .Q(
FPADDSUB_intDX_EWSW[26]), .QN(n953) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(FPADDSUB_Data_array_SWR[9]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2749), .Q(
FPADDSUB_Data_array_SWR[35]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(add_subt_data1[19]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2772), .Q(
FPADDSUB_intDX_EWSW[19]), .QN(n951) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(FPADDSUB_Data_array_SWR[8]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2752), .Q(
FPADDSUB_Data_array_SWR[34]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(FPADDSUB_Data_array_SWR[11]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2770), .Q(
FPADDSUB_Data_array_SWR[37]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(FPADDSUB_Data_array_SWR[10]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2772), .Q(
FPADDSUB_Data_array_SWR[36]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n915), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2753), .Q(
FPADDSUB_bit_shift_SHT2) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n2837), .CK(
FPSENCOS_reg_Z0_net8272357), .RN(n2790), .Q(
FPSENCOS_d_ff1_operation_out) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_Y[29]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2808), .Q(FPSENCOS_d_ff2_Y[29]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_X[29]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2803), .Q(FPSENCOS_d_ff2_X[29]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(add_subt_data1[27]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2743), .Q(
FPADDSUB_intDX_EWSW[27]), .QN(n922) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(operation[1]), .CK(clk), .RN(n963), .Q(
operation_reg[0]) );
DFFRX1TS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(clk), .RN(n964), .Q(
operation_reg[1]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n2841), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .RN(n2775), .Q(
FPMULT_Sgf_normalized_result[2]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(add_subt_data1[22]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2748), .Q(
FPADDSUB_intDX_EWSW[22]), .QN(n913) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n2843), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .RN(n2785), .Q(
FPMULT_Sgf_normalized_result[4]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n2845), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .RN(n2777), .Q(
FPMULT_Sgf_normalized_result[6]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n2847), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .RN(n2774), .Q(
FPMULT_Sgf_normalized_result[8]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n2849), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .RN(n2782), .Q(
FPMULT_Sgf_normalized_result[10]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n2851), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .RN(n966), .Q(
FPMULT_Sgf_normalized_result[12]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n2853), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .RN(n2779), .Q(
FPMULT_Sgf_normalized_result[14]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n2855), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .RN(n2774), .Q(
FPMULT_Sgf_normalized_result[16]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n2857), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .RN(n2782), .Q(
FPMULT_Sgf_normalized_result[18]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n2859), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .RN(n2776), .Q(
FPMULT_Sgf_normalized_result[20]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n2861), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8272267), .RN(n2786), .Q(
FPMULT_Sgf_normalized_result[22]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[0]), .CK(FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2764), .Q(FPADDSUB_N59) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(FPADDSUB_N59), .CK(
FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2749), .Q(
FPADDSUB_Raw_mant_NRM_SWR[0]), .QN(n2725) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[1]), .CK(
FPADDSUB_inst_ShiftRegister_net8272231), .RN(n2757), .Q(
FPADDSUB_Shift_reg_FLAGS_7[0]) );
DFFRX1TS FPADDSUB_Ready_reg_Q_reg_0_ ( .D(FPADDSUB_Shift_reg_FLAGS_7[0]),
.CK(clk), .RN(n2743), .Q(ready_add_subt), .QN(n954) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(FPADDSUB_Raw_mant_SGF[4]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2768), .Q(
FPADDSUB_Raw_mant_NRM_SWR[4]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_13_ ( .D(Data_1[13]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2783), .Q(
FPMULT_Op_MX[13]), .QN(n1027) );
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_1_ ( .D(FPSENCOS_ITER_CONT_N3), .CK(
FPSENCOS_ITER_CONT_net8272393), .RN(n2814), .Q(
FPSENCOS_cont_iter_out[1]), .QN(n2651) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_8_ ( .D(Data_2[8]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2783), .Q(
FPMULT_Op_MY[8]), .QN(n943) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_4_ ( .D(Data_2[4]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2783), .Q(
FPMULT_Op_MY[4]), .QN(n939) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_10_ ( .D(Data_2[10]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2777), .Q(
FPMULT_Op_MY[10]), .QN(n944) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(Data_1[25]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2782), .Q(
FPMULT_Op_MX[25]) );
DFFRX1TS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n2812), .Q(
dataB[23]) );
DFFRX1TS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(clk), .RN(n2815), .Q(
dataB[30]) );
DFFRX1TS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(clk), .RN(n2814), .Q(
dataB[28]) );
DFFRX1TS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(clk), .RN(n2812), .Q(
dataB[27]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_Y[24]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2807), .Q(FPSENCOS_d_ff2_Y[24]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_X[24]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2806), .Q(FPSENCOS_d_ff2_X[24]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_Y[25]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2809), .Q(FPSENCOS_d_ff2_Y[25]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_X[26]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2811), .Q(FPSENCOS_d_ff2_X[26]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_X[25]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2811), .Q(FPSENCOS_d_ff2_X[25]) );
DFFSX1TS R_7 ( .D(n2736), .CK(clk), .SN(n1688), .Q(n2824) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n2815), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(clk), .RN(n2795), .Q(
dataA[29]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(add_subt_data1[30]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2757), .Q(
FPADDSUB_intDX_EWSW[30]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_12_ ( .D(Data_1[12]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2783), .Q(
FPMULT_Op_MX[12]), .QN(n918) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_21_ ( .D(Data_2[21]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2783), .QN(
n1021) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_17_ ( .D(Data_2[17]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2786), .QN(
n1019) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_19_ ( .D(Data_2[19]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2778), .QN(
n1017) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_15_ ( .D(Data_2[15]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2784), .QN(
n1020) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(
FPADDSUB_Raw_mant_SGF[13]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2754), .Q(FPADDSUB_Raw_mant_NRM_SWR[13]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(FPADDSUB_Raw_mant_SGF[2]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2769), .Q(
FPADDSUB_Raw_mant_NRM_SWR[2]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_2_ ( .D(Data_1[2]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n966), .Q(
FPMULT_Op_MX[2]), .QN(n1012) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_4_ ( .D(Data_1[4]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2779), .Q(
FPMULT_Op_MX[4]), .QN(n1011) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_8_ ( .D(Data_1[8]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2784), .Q(
FPMULT_Op_MX[8]), .QN(n1009) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(FPADDSUB_Data_array_SWR[13]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2756), .Q(
FPADDSUB_Data_array_SWR[39]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_20_ ( .D(Data_1[20]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2777), .Q(
FPMULT_Op_MX[20]), .QN(n1023) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(FPADDSUB_Data_array_SWR[12]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2748), .Q(
FPADDSUB_Data_array_SWR[38]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_11_ ( .D(Data_1[11]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2775), .Q(
FPMULT_Op_MX[11]), .QN(n941) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(FPADDSUB_Data_array_SWR[14]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2743), .Q(
FPADDSUB_Data_array_SWR[40]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(FPADDSUB_Data_array_SWR[15]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n1690), .Q(
FPADDSUB_Data_array_SWR[41]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(
FPADDSUB_Raw_mant_SGF[15]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2755), .Q(FPADDSUB_Raw_mant_NRM_SWR[15]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(FPADDSUB_Raw_mant_SGF[9]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2752), .Q(
FPADDSUB_Raw_mant_NRM_SWR[9]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n2814), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]) );
DFFRX4TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[4]), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n1690), .Q(
FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n2662) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_13_ ( .D(Data_2[13]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2785), .Q(
FPMULT_Op_MY[13]), .QN(n926) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_19_ ( .D(Data_1[19]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2781), .Q(
FPMULT_Op_MX[19]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_1_ ( .D(Data_2[1]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2775), .Q(
FPMULT_Op_MY[1]), .QN(n929) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n874), .CK(clk), .RN(n2744), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .CK(clk), .RN(n2815), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .QN(n1029) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n2812), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[25]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8272123), .RN(n2769), .QN(n1015) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_40_ ( .D(
FPMULT_Sgf_operation_Result[40]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n2792), .Q(
FPMULT_P_Sgf[40]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_39_ ( .D(
FPMULT_Sgf_operation_Result[39]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n2792), .Q(
FPMULT_P_Sgf[39]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_38_ ( .D(
FPMULT_Sgf_operation_Result[38]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n2792), .Q(
FPMULT_P_Sgf[38]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_37_ ( .D(
FPMULT_Sgf_operation_Result[37]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n2792), .Q(
FPMULT_P_Sgf[37]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_36_ ( .D(
FPMULT_Sgf_operation_Result[36]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n2792), .Q(
FPMULT_P_Sgf[36]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_35_ ( .D(
FPMULT_Sgf_operation_Result[35]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n2792), .Q(
FPMULT_P_Sgf[35]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_46_ ( .D(
FPMULT_Sgf_operation_Result[46]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n2792), .Q(
FPMULT_P_Sgf[46]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_45_ ( .D(
FPMULT_Sgf_operation_Result[45]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n2791), .Q(
FPMULT_P_Sgf[45]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_44_ ( .D(
FPMULT_Sgf_operation_Result[44]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n964), .Q(
FPMULT_P_Sgf[44]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_43_ ( .D(
FPMULT_Sgf_operation_Result[43]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n963), .Q(
FPMULT_P_Sgf[43]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_42_ ( .D(
FPMULT_Sgf_operation_Result[42]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n2817), .Q(
FPMULT_P_Sgf[42]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_41_ ( .D(
FPMULT_Sgf_operation_Result[41]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n2791), .Q(
FPMULT_P_Sgf[41]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_Y[26]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2801), .Q(FPSENCOS_d_ff2_Y[26]) );
DFFRX1TS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n2832), .CK(
FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2752), .Q(
FPADDSUB_ADD_OVRFLW_NRM) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(FPADDSUB_Data_array_SWR[6]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2763), .Q(
FPADDSUB_Data_array_SWR[32]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(
FPMULT_Adder_M_result_A_adder[22]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n2778), .Q(
FPMULT_Add_result[22]) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(clk), .RN(n2817), .Q(
dataA[30]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(FPADDSUB_Data_array_SWR[5]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2768), .Q(
FPADDSUB_Data_array_SWR[31]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(FPADDSUB_Data_array_SWR[7]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2766), .Q(
FPADDSUB_Data_array_SWR[33]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(FPADDSUB_Data_array_SWR[4]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2757), .Q(
FPADDSUB_Data_array_SWR[30]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(
FPMULT_Adder_M_result_A_adder[23]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n2784), .Q(
FPMULT_Add_result[23]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(
FPMULT_Adder_M_result_A_adder[21]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n2786), .Q(
FPMULT_Add_result[21]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(
FPMULT_Adder_M_result_A_adder[20]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n2774), .Q(
FPMULT_Add_result[20]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(
FPMULT_Adder_M_result_A_adder[19]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n2776), .Q(
FPMULT_Add_result[19]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(
FPMULT_Adder_M_result_A_adder[18]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n2782), .Q(
FPMULT_Add_result[18]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(
FPMULT_Adder_M_result_A_adder[17]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n2774), .Q(
FPMULT_Add_result[17]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(
FPMULT_Adder_M_result_A_adder[16]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n2777), .Q(
FPMULT_Add_result[16]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(
FPMULT_Adder_M_result_A_adder[15]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n2785), .Q(
FPMULT_Add_result[15]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(
FPMULT_Adder_M_result_A_adder[14]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n2775), .Q(
FPMULT_Add_result[14]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(
FPMULT_Adder_M_result_A_adder[13]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n2784), .Q(
FPMULT_Add_result[13]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(
FPMULT_Adder_M_result_A_adder[12]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n2778), .Q(
FPMULT_Add_result[12]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(
FPMULT_Adder_M_result_A_adder[11]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n2786), .Q(
FPMULT_Add_result[11]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(
FPMULT_Adder_M_result_A_adder[10]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n2776), .Q(
FPMULT_Add_result[10]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(
FPMULT_Adder_M_result_A_adder[9]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n2782), .Q(
FPMULT_Add_result[9]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(
FPMULT_Adder_M_result_A_adder[8]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n2786), .Q(
FPMULT_Add_result[8]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(
FPMULT_Adder_M_result_A_adder[7]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n2776), .Q(
FPMULT_Add_result[7]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(
FPMULT_Adder_M_result_A_adder[6]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n2782), .Q(
FPMULT_Add_result[6]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(
FPMULT_Adder_M_result_A_adder[5]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n966), .Q(
FPMULT_Add_result[5]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(
FPMULT_Adder_M_result_A_adder[4]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n2779), .Q(
FPMULT_Add_result[4]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(
FPMULT_Adder_M_result_A_adder[3]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n2781), .Q(
FPMULT_Add_result[3]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(
FPMULT_Adder_M_result_A_adder[2]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n2777), .Q(
FPMULT_Add_result[2]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(
FPMULT_Adder_M_result_A_adder[1]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8272249), .RN(n2785), .Q(
FPMULT_Add_result[1]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_34_ ( .D(
FPMULT_Sgf_operation_Result[34]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n1687), .Q(
FPMULT_P_Sgf[34]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_33_ ( .D(
FPMULT_Sgf_operation_Result[33]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n2817), .Q(
FPMULT_P_Sgf[33]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_32_ ( .D(
FPMULT_Sgf_operation_Result[32]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n2791), .Q(
FPMULT_P_Sgf[32]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_31_ ( .D(
FPMULT_Sgf_operation_Result[31]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n2790), .Q(
FPMULT_P_Sgf[31]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_30_ ( .D(
FPMULT_Sgf_operation_Result[30]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n964), .Q(
FPMULT_P_Sgf[30]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_29_ ( .D(
FPMULT_Sgf_operation_Result[29]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n963), .Q(
FPMULT_P_Sgf[29]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_28_ ( .D(
FPMULT_Sgf_operation_Result[28]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n2795), .Q(
FPMULT_P_Sgf[28]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_27_ ( .D(
FPMULT_Sgf_operation_Result[27]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n2816), .Q(
FPMULT_P_Sgf[27]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_26_ ( .D(
FPMULT_Sgf_operation_Result[26]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n2817), .Q(
FPMULT_P_Sgf[26]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_25_ ( .D(
FPMULT_Sgf_operation_Result[25]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n1687), .Q(
FPMULT_P_Sgf[25]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(
FPMULT_Sgf_operation_Result[24]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8272285), .RN(n2791), .Q(
FPMULT_P_Sgf[24]) );
DFFRX1TS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(clk), .RN(n1687), .Q(
dataA[28]) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(clk), .RN(n2790), .Q(
dataA[23]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(Data_1[29]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n966), .Q(
FPMULT_Op_MX[29]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(Data_1[23]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2775), .Q(
FPMULT_Op_MX[23]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(Data_1[30]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2774), .Q(
FPMULT_Op_MX[30]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(Data_1[26]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2777), .Q(
FPMULT_Op_MX[26]) );
DFFRX1TS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(clk), .RN(n964), .Q(
dataA[24]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_9_ ( .D(Data_2[9]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2776), .Q(
FPMULT_Op_MY[9]), .QN(n942) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_22_ ( .D(Data_1[22]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2783), .Q(
FPMULT_Op_MX[22]), .QN(n940) );
DFFSX1TS R_6 ( .D(n2737), .CK(clk), .SN(n1687), .Q(n2823) );
DFFSX1TS R_8 ( .D(n2735), .CK(clk), .SN(n2791), .Q(n2819) );
DFFSX1TS R_9 ( .D(n2734), .CK(clk), .SN(n2817), .Q(n2820) );
DFFRX1TS R_20 ( .D(n2730), .CK(clk), .RN(n2790), .Q(n2821) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_X[23]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2808), .Q(FPSENCOS_d_ff2_X[23]), .QN(n2672) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_Y[23]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8272357), .RN(n2801), .Q(FPSENCOS_d_ff2_Y[23]), .QN(n2671) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(FPADDSUB_Raw_mant_SGF[3]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2773), .Q(
FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n2641) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(FPADDSUB_Raw_mant_SGF[1]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2747), .Q(
FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n2642) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(FPADDSUB_Raw_mant_SGF[6]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8272105), .RN(n2751), .Q(
FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n2636) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_INIT_EWSW[26]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2746), .Q(
FPADDSUB_DMP_EXP_EWSW[26]), .QN(n2723) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_INIT_EWSW[25]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n2751), .Q(
FPADDSUB_DMP_EXP_EWSW[25]), .QN(n2724) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_INIT_EWSW[24]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8272123), .RN(n1690), .Q(
FPADDSUB_DMP_EXP_EWSW[24]), .QN(n2698) );
DFFRXLTS FPMULT_Exp_module_Underflow_m_Q_reg_0_ ( .D(n2834), .CK(n2835),
.RN(n2783), .Q(underflow_flag_mult), .QN(n2726) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(add_subt_data2[30]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2758), .QN(n2741)
);
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(add_subt_data2[22]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2748), .Q(
FPADDSUB_intDY_EWSW[22]), .QN(n2625) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(add_subt_data1[28]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2759), .Q(
FPADDSUB_intDX_EWSW[28]), .QN(n2659) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(add_subt_data2[29]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8272069), .RN(n2756), .QN(n2740)
);
ADDFX1TS intadd_1082_U25 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[14]), .B(
intadd_1082_B_1_), .CI(intadd_1082_n25), .CO(intadd_1082_n24), .S(
FPMULT_Sgf_operation_Result[14]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_5_ ( .D(Data_1[5]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2785), .Q(
FPMULT_Op_MX[5]), .QN(n912) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_7_ ( .D(Data_1[7]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8272321), .RN(n2778), .Q(
FPMULT_Op_MX[7]), .QN(n911) );
CMPR32X2TS intadd_1082_U15 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[0]), .B(
intadd_1082_B_11_), .C(intadd_1082_n15), .CO(intadd_1082_n14), .S(
FPMULT_Sgf_operation_Result[24]) );
CMPR32X2TS intadd_1082_U14 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[1]), .B(
intadd_1082_B_12_), .C(intadd_1082_n14), .CO(intadd_1082_n13), .S(
FPMULT_Sgf_operation_Result[25]) );
CMPR32X2TS intadd_1082_U13 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[2]), .B(
intadd_1082_B_13_), .C(intadd_1082_n13), .CO(intadd_1082_n12), .S(
FPMULT_Sgf_operation_Result[26]) );
CMPR32X2TS intadd_1082_U12 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[3]), .B(
intadd_1082_B_14_), .C(intadd_1082_n12), .CO(intadd_1082_n11), .S(
FPMULT_Sgf_operation_Result[27]) );
CMPR32X2TS intadd_1082_U11 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[4]), .B(
intadd_1082_B_15_), .C(intadd_1082_n11), .CO(intadd_1082_n10), .S(
FPMULT_Sgf_operation_Result[28]) );
CMPR32X2TS intadd_1082_U10 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[5]), .B(
intadd_1082_B_16_), .C(intadd_1082_n10), .CO(intadd_1082_n9), .S(
FPMULT_Sgf_operation_Result[29]) );
CMPR32X2TS intadd_1082_U9 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[6]), .B(
intadd_1082_B_17_), .C(intadd_1082_n9), .CO(intadd_1082_n8), .S(
FPMULT_Sgf_operation_Result[30]) );
CMPR32X2TS intadd_1082_U8 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[7]), .B(
intadd_1082_B_18_), .C(intadd_1082_n8), .CO(intadd_1082_n7), .S(
FPMULT_Sgf_operation_Result[31]) );
CMPR32X2TS intadd_1082_U7 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[8]), .B(
intadd_1082_B_19_), .C(intadd_1082_n7), .CO(intadd_1082_n6), .S(
FPMULT_Sgf_operation_Result[32]) );
DFFRX4TS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n810), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8272105), .RN(n2771), .Q(
FPADDSUB_ADD_OVRFLW_NRM2), .QN(n910) );
CMPR32X2TS intadd_1082_U6 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[9]), .B(
intadd_1082_B_20_), .C(intadd_1082_n6), .CO(intadd_1082_n5), .S(
FPMULT_Sgf_operation_Result[33]) );
CMPR32X2TS intadd_1082_U5 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[10]), .B(
intadd_1082_B_21_), .C(intadd_1082_n5), .CO(intadd_1082_n4), .S(
FPMULT_Sgf_operation_Result[34]) );
CMPR32X2TS DP_OP_234J321_127_8543_U10 ( .A(FPMULT_S_Oper_A_exp[0]), .B(
FPMULT_FSM_exp_operation_A_S), .C(DP_OP_234J321_127_8543_n22), .CO(
DP_OP_234J321_127_8543_n9), .S(FPMULT_Exp_module_Data_S[0]) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[2]), .CK(
FPADDSUB_inst_ShiftRegister_net8272231), .RN(n2773), .Q(
FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n2637) );
CMPR32X2TS intadd_1084_U4 ( .A(n2651), .B(FPSENCOS_d_ff2_X[24]), .C(
intadd_1084_CI), .CO(intadd_1084_n3), .S(FPSENCOS_sh_exp_x[1]) );
CMPR32X2TS intadd_1085_U4 ( .A(n2651), .B(FPSENCOS_d_ff2_Y[24]), .C(
intadd_1085_CI), .CO(intadd_1085_n3), .S(FPSENCOS_sh_exp_y[1]) );
CMPR32X2TS intadd_1085_U3 ( .A(FPSENCOS_d_ff2_Y[25]), .B(n2598), .C(
intadd_1085_n3), .CO(intadd_1085_n2), .S(FPSENCOS_sh_exp_y[2]) );
CMPR32X2TS intadd_1084_U3 ( .A(FPSENCOS_d_ff2_X[25]), .B(n2598), .C(
intadd_1084_n3), .CO(intadd_1084_n2), .S(FPSENCOS_sh_exp_x[2]) );
CMPR32X2TS intadd_1084_U2 ( .A(FPSENCOS_d_ff2_X[26]), .B(n2600), .C(
intadd_1084_n2), .CO(intadd_1084_n1), .S(FPSENCOS_sh_exp_x[3]) );
CMPR32X2TS intadd_1085_U2 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n2600), .C(
intadd_1085_n2), .CO(intadd_1085_n1), .S(FPSENCOS_sh_exp_y[3]) );
NAND2X4TS U1399 ( .A(n1899), .B(n1887), .Y(n1885) );
CLKINVX6TS U1400 ( .A(n2559), .Y(n2548) );
AOI222X4TS U1401 ( .A0(FPADDSUB_DMP_SFG[10]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[12]), .B0(FPADDSUB_DMP_SFG[10]), .B1(n1978),
.C0(FPADDSUB_DmP_mant_SFG_SWR[12]), .C1(n1978), .Y(n2321) );
NAND2X4TS U1402 ( .A(n1424), .B(FPMULT_Op_MX[11]), .Y(n1425) );
NAND2X4TS U1403 ( .A(n1166), .B(n940), .Y(n1084) );
AOI222X4TS U1404 ( .A0(FPADDSUB_DMP_SFG[4]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[6]), .B0(FPADDSUB_DMP_SFG[4]), .B1(n1828),
.C0(FPADDSUB_DmP_mant_SFG_SWR[6]), .C1(n1828), .Y(n1859) );
CMPR32X2TS U1405 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MY[20]), .C(n1420),
.CO(n1426), .S(n1577) );
CMPR32X2TS U1406 ( .A(FPMULT_Op_MX[8]), .B(FPMULT_Op_MX[20]), .C(n1413),
.CO(n1386), .S(n1415) );
CMPR32X2TS U1407 ( .A(n993), .B(n973), .C(n1421), .CO(n1420), .S(n1563) );
CLKINVX6TS U1408 ( .A(n919), .Y(n971) );
CLKINVX6TS U1409 ( .A(n936), .Y(n978) );
CMPR32X2TS U1410 ( .A(n999), .B(FPMULT_Op_MY[18]), .C(n1427), .CO(n1421),
.S(n1580) );
CMPR32X2TS U1411 ( .A(n995), .B(n981), .C(n1407), .CO(n1427), .S(n1553) );
CMPR32X2TS U1412 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[18]), .C(n1409),
.CO(n1408), .S(n1411) );
CMPR32X2TS U1413 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MY[16]), .C(n1379),
.CO(n1407), .S(n1519) );
CMPR32X2TS U1414 ( .A(n997), .B(n972), .C(n1359), .CO(n1379), .S(n1521) );
CMPR32X2TS U1415 ( .A(FPMULT_Op_MX[4]), .B(FPMULT_Op_MX[16]), .C(n1354),
.CO(n1384), .S(n1355) );
CLKINVX6TS U1416 ( .A(n925), .Y(n977) );
CMPR32X2TS U1417 ( .A(n991), .B(FPMULT_Op_MY[14]), .C(n1364), .CO(n1359),
.S(n1457) );
CLKINVX6TS U1418 ( .A(n917), .Y(n976) );
CLKINVX6TS U1419 ( .A(n924), .Y(n979) );
CMPR32X2TS U1420 ( .A(n970), .B(n984), .C(n1357), .CO(n1364), .S(n1450) );
XOR2X1TS U1421 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[22]), .B(n2082), .Y(
FPMULT_Sgf_operation_Result[46]) );
CLKINVX6TS U1422 ( .A(n1973), .Y(n1886) );
INVX4TS U1423 ( .A(n1940), .Y(n1895) );
CLKBUFX3TS U1424 ( .A(n2375), .Y(n982) );
INVX3TS U1425 ( .A(n1425), .Y(n1500) );
NAND2BX1TS U1426 ( .AN(n2014), .B(FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(n2023)
);
CLKINVX6TS U1427 ( .A(n2186), .Y(n2366) );
OAI221X4TS U1428 ( .A0(n1365), .A1(n1516), .B0(n1419), .B1(n1517), .C0(n1530), .Y(n1366) );
NAND2BX1TS U1429 ( .AN(n2024), .B(FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n2019)
);
NOR2X1TS U1430 ( .A(FPADDSUB_Raw_mant_NRM_SWR[10]), .B(n2024), .Y(n1606) );
INVX3TS U1431 ( .A(n1120), .Y(n1085) );
CMPR32X2TS U1432 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MX[14]), .C(n1361),
.CO(n1352), .S(n1365) );
INVX4TS U1433 ( .A(n1604), .Y(n1362) );
CLKINVX6TS U1434 ( .A(n2379), .Y(n914) );
NOR2X4TS U1435 ( .A(n1852), .B(n1725), .Y(n1722) );
NAND2X4TS U1436 ( .A(n1852), .B(n2662), .Y(n1696) );
NAND2X4TS U1437 ( .A(n1846), .B(n2662), .Y(n1721) );
NOR2X6TS U1438 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n1745), .Y(n1699)
);
INVX3TS U1439 ( .A(n2352), .Y(n2317) );
NOR2X6TS U1440 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n1746), .Y(n1700)
);
OR2X4TS U1441 ( .A(FPSENCOS_cont_iter_out[2]), .B(n2280), .Y(n1693) );
INVX2TS U1442 ( .A(n990), .Y(n991) );
INVX2TS U1443 ( .A(n996), .Y(n997) );
NOR2X4TS U1444 ( .A(n1846), .B(n1725), .Y(n1704) );
NAND2X4TS U1445 ( .A(n2726), .B(n2279), .Y(n1787) );
INVX3TS U1446 ( .A(n1003), .Y(n1004) );
INVX2TS U1447 ( .A(n994), .Y(n995) );
OR2X2TS U1448 ( .A(FPADDSUB_ADD_OVRFLW_NRM), .B(n2637), .Y(n1897) );
INVX3TS U1449 ( .A(n983), .Y(n984) );
INVX3TS U1450 ( .A(n1001), .Y(n1002) );
BUFX4TS U1451 ( .A(n2474), .Y(n2482) );
INVX3TS U1452 ( .A(n1021), .Y(n1000) );
CLKINVX3TS U1453 ( .A(n2037), .Y(n915) );
INVX3TS U1454 ( .A(n1019), .Y(n981) );
NOR2X2TS U1455 ( .A(n2424), .B(n1622), .Y(n2473) );
NOR2X4TS U1456 ( .A(n2424), .B(n2399), .Y(n1779) );
NOR2X4TS U1457 ( .A(n961), .B(operation[2]), .Y(n2551) );
CLKINVX1TS U1458 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[16]), .Y(n2079) );
CLKINVX1TS U1459 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[18]), .Y(n2076) );
CLKINVX1TS U1460 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[20]), .Y(n2073) );
NOR2X4TS U1461 ( .A(n960), .B(operation[2]), .Y(n2540) );
BUFX4TS U1462 ( .A(n1687), .Y(n2790) );
BUFX4TS U1463 ( .A(n1687), .Y(n2816) );
INVX4TS U1464 ( .A(rst), .Y(n1687) );
OAI32X1TS U1465 ( .A0(n1325), .A1(n1287), .A2(n1218), .B0(n1331), .B1(n1286),
.Y(mult_x_254_n167) );
NAND2BXLTS U1466 ( .AN(FPADDSUB_intDX_EWSW[19]), .B(FPADDSUB_intDY_EWSW[19]),
.Y(n2169) );
NAND2BXLTS U1467 ( .AN(FPADDSUB_intDX_EWSW[27]), .B(FPADDSUB_intDY_EWSW[27]),
.Y(n2123) );
OAI32X1TS U1468 ( .A0(n958), .A1(FPMULT_Op_MY[0]), .A2(n1331), .B0(n1218),
.B1(n959), .Y(n1332) );
OAI32X1TS U1469 ( .A0(n911), .A1(FPMULT_Op_MY[0]), .A2(n1335), .B0(n1236),
.B1(n911), .Y(n1336) );
INVX2TS U1470 ( .A(n1497), .Y(n1490) );
INVX2TS U1471 ( .A(n1563), .Y(n1562) );
INVX2TS U1472 ( .A(n1580), .Y(n1581) );
INVX2TS U1473 ( .A(n1471), .Y(n1489) );
CLKINVX6TS U1474 ( .A(n1582), .Y(n1579) );
BUFX4TS U1475 ( .A(n1414), .Y(n1602) );
ADDHXLTS U1476 ( .A(n1592), .B(n1591), .CO(n1586), .S(
DP_OP_454J321_123_2743_n142) );
BUFX4TS U1477 ( .A(n1410), .Y(n1598) );
CLKINVX6TS U1478 ( .A(n1550), .Y(n1551) );
BUFX4TS U1479 ( .A(n1353), .Y(n1561) );
NOR2XLTS U1480 ( .A(n2596), .B(n918), .Y(n1083) );
OAI32X1TS U1481 ( .A0(FPMULT_Op_MX[12]), .A1(n1002), .A2(n1027), .B0(
FPMULT_Op_MX[13]), .B1(n918), .Y(n1155) );
OAI32X1TS U1482 ( .A0(FPMULT_Op_MX[12]), .A1(n1000), .A2(n1027), .B0(n1136),
.B1(n918), .Y(mult_x_219_n222) );
OAI32X1TS U1483 ( .A0(FPMULT_Op_MX[12]), .A1(FPMULT_Op_MY[20]), .A2(n1027),
.B0(n1165), .B1(n918), .Y(n1168) );
OAI32X1TS U1484 ( .A0(n1166), .A1(FPMULT_Op_MY[12]), .A2(n1170), .B0(n1073),
.B1(n1166), .Y(n1167) );
OAI32X1TS U1485 ( .A0(FPMULT_Op_MX[12]), .A1(FPMULT_Op_MY[18]), .A2(n1027),
.B0(n1160), .B1(n918), .Y(n1164) );
NAND2BXLTS U1486 ( .AN(n968), .B(FPADDSUB_intDY_EWSW[24]), .Y(n2178) );
INVX2TS U1487 ( .A(n992), .Y(n993) );
CLKAND2X2TS U1488 ( .A(intadd_1082_n1), .B(
FPMULT_Sgf_operation_EVEN1_Q_left[14]), .Y(n2081) );
CLKAND2X2TS U1489 ( .A(FPADDSUB_DmP_mant_SFG_SWR[4]), .B(n2631), .Y(n1807)
);
AO21XLTS U1490 ( .A0(n1750), .A1(FPADDSUB_Data_array_SWR[51]), .B0(n1749),
.Y(n947) );
CLKAND2X2TS U1491 ( .A(FPADDSUB_DmP_mant_SFG_SWR[8]), .B(n2634), .Y(n1879)
);
CLKAND2X2TS U1492 ( .A(FPADDSUB_DmP_mant_SFG_SWR[6]), .B(n2632), .Y(n1827)
);
OAI211X1TS U1493 ( .A0(n2662), .A1(n962), .B0(n1752), .C0(n1751), .Y(n1758)
);
AOI211X1TS U1494 ( .A0(n1699), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n1744),
.C0(n1732), .Y(n1761) );
AOI211X1TS U1495 ( .A0(FPADDSUB_Data_array_SWR[44]), .A1(n1699), .B0(n1744),
.C0(n1728), .Y(n1737) );
BUFX4TS U1496 ( .A(n2473), .Y(n2493) );
OAI32X1TS U1497 ( .A0(n1005), .A1(n995), .A2(n2597), .B0(n1277), .B1(n1343),
.Y(mult_x_254_n232) );
OAI32X1TS U1498 ( .A0(n912), .A1(FPMULT_Op_MY[0]), .A2(n1292), .B0(n1178),
.B1(n912), .Y(n1284) );
NOR2XLTS U1499 ( .A(n1499), .B(n1602), .Y(DP_OP_454J321_123_2743_n200) );
NOR2XLTS U1500 ( .A(n1499), .B(n1598), .Y(DP_OP_454J321_123_2743_n214) );
CLKINVX6TS U1501 ( .A(n1516), .Y(n1517) );
OAI32X1TS U1502 ( .A0(FPMULT_Op_MX[12]), .A1(n981), .A2(n1027), .B0(n1135),
.B1(n918), .Y(mult_x_219_n226) );
OAI32X1TS U1503 ( .A0(FPMULT_Op_MX[12]), .A1(FPMULT_Op_MY[16]), .A2(n1027),
.B0(n1042), .B1(n918), .Y(n1147) );
NOR2X1TS U1504 ( .A(n1768), .B(n1788), .Y(n2561) );
INVX2TS U1505 ( .A(FPMULT_Sgf_normalized_result[7]), .Y(n2107) );
NAND2BXLTS U1506 ( .AN(FPADDSUB_Raw_mant_NRM_SWR[23]), .B(n2610), .Y(n1610)
);
AOI222X4TS U1507 ( .A0(n2637), .A1(FPADDSUB_DmP_mant_SHT1_SW[1]), .B0(n1912),
.B1(FPADDSUB_Raw_mant_NRM_SWR[22]), .C0(FPADDSUB_Raw_mant_NRM_SWR[3]),
.C1(n2739), .Y(n1932) );
AOI222X4TS U1508 ( .A0(n2637), .A1(FPADDSUB_DmP_mant_SHT1_SW[0]), .B0(n1912),
.B1(FPADDSUB_Raw_mant_NRM_SWR[23]), .C0(FPADDSUB_Raw_mant_NRM_SWR[2]),
.C1(n2739), .Y(n1942) );
OAI211XLTS U1509 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
n2682), .B0(n2564), .C0(n2278), .Y(n875) );
AOI2BB1XLTS U1510 ( .A0N(intadd_1082_n1), .A1N(
FPMULT_Sgf_operation_EVEN1_Q_left[14]), .B0(n2081), .Y(
FPMULT_Sgf_operation_Result[38]) );
AO22XLTS U1511 ( .A0(n2787), .A1(FPADDSUB_LZD_raw_out_EWR[4]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[4]), .B1(n2589), .Y(
FPADDSUB_shft_value_mux_o_EWR[4]) );
OAI21XLTS U1512 ( .A0(n1948), .A1(n1885), .B0(n1941), .Y(
FPADDSUB_Data_array_SWR[19]) );
OAI21XLTS U1513 ( .A0(n1948), .A1(n2371), .B0(n1915), .Y(
FPADDSUB_Data_array_SWR[18]) );
XOR2XLTS U1514 ( .A(n2340), .B(n2339), .Y(FPADDSUB_Raw_mant_SGF[19]) );
OAI21XLTS U1515 ( .A0(n1951), .A1(n1885), .B0(n1950), .Y(
FPADDSUB_Data_array_SWR[16]) );
OAI21XLTS U1516 ( .A0(n1947), .A1(n1885), .B0(n1920), .Y(
FPADDSUB_Data_array_SWR[17]) );
AO22XLTS U1517 ( .A0(n2787), .A1(FPADDSUB_LZD_raw_out_EWR[3]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[3]), .B1(n2589), .Y(
FPADDSUB_shft_value_mux_o_EWR[3]) );
XOR2XLTS U1518 ( .A(n2345), .B(n2344), .Y(FPADDSUB_Raw_mant_SGF[21]) );
XOR2XLTS U1519 ( .A(n2356), .B(n2355), .Y(FPADDSUB_Raw_mant_SGF[24]) );
XOR2XLTS U1520 ( .A(n2350), .B(n2349), .Y(FPADDSUB_Raw_mant_SGF[23]) );
OAI31X1TS U1521 ( .A0(n2567), .A1(FPSENCOS_cont_var_out[1]), .A2(n2649),
.B0(n2038), .Y(n842) );
OAI21XLTS U1522 ( .A0(n1970), .A1(n1885), .B0(n1924), .Y(
FPADDSUB_Data_array_SWR[21]) );
OAI21XLTS U1523 ( .A0(n2005), .A1(n2033), .B0(n2004), .Y(n2003) );
XOR2XLTS U1524 ( .A(n2036), .B(n1015), .Y(FPADDSUB_Raw_mant_SGF[25]) );
OAI21XLTS U1525 ( .A0(n1999), .A1(n2001), .B0(n1998), .Y(n1997) );
AO22XLTS U1526 ( .A0(n2787), .A1(FPADDSUB_LZD_raw_out_EWR[2]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[2]), .B1(n2589), .Y(
FPADDSUB_shft_value_mux_o_EWR[2]) );
OAI21XLTS U1527 ( .A0(n2374), .A1(n1895), .B0(n1902), .Y(
FPADDSUB_Data_array_SWR[22]) );
OAI21XLTS U1528 ( .A0(n1975), .A1(n1885), .B0(n1974), .Y(
FPADDSUB_Data_array_SWR[20]) );
XOR2XLTS U1529 ( .A(n1267), .B(n1266), .Y(
FPMULT_Sgf_operation_EVEN1_right_N23) );
OAI32X1TS U1530 ( .A0(n1005), .A1(n970), .A2(n2597), .B0(n1196), .B1(n1343),
.Y(n1329) );
OAI21XLTS U1531 ( .A0(n1504), .A1(n1425), .B0(n1482), .Y(n1480) );
NOR2XLTS U1532 ( .A(n1499), .B(n1530), .Y(n1406) );
OAI32X1TS U1533 ( .A0(FPMULT_Op_MX[12]), .A1(n984), .A2(n2596), .B0(n1051),
.B1(n918), .Y(n1159) );
OAI211XLTS U1534 ( .A0(n1942), .A1(n1886), .B0(n1946), .C0(n1888), .Y(
FPADDSUB_Data_array_SWR[0]) );
OAI21XLTS U1535 ( .A0(n1946), .A1(n1885), .B0(n1945), .Y(
FPADDSUB_Data_array_SWR[1]) );
NAND2BXLTS U1536 ( .AN(n989), .B(n1688), .Y(n1689) );
OAI21XLTS U1537 ( .A0(n1942), .A1(n1885), .B0(n1918), .Y(
FPADDSUB_Data_array_SWR[2]) );
OAI21XLTS U1538 ( .A0(n2374), .A1(n1885), .B0(n2037), .Y(
FPADDSUB_Data_array_SWR[25]) );
NAND2BXLTS U1539 ( .AN(FPADDSUB_intDX_EWSW[30]), .B(n2741), .Y(
FPADDSUB_DMP_INIT_EWSW[30]) );
BUFX6TS U1540 ( .A(n1786), .Y(n1690) );
OR4X2TS U1541 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .C(n1782), .D(n2648), .Y(
n921) );
OR2X1TS U1542 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MY[10]), .Y(n923) );
BUFX3TS U1543 ( .A(n1706), .Y(n2375) );
OR2X1TS U1544 ( .A(n2676), .B(n2229), .Y(n948) );
OR2X1TS U1545 ( .A(FPMULT_FSM_selector_C), .B(n2229), .Y(n949) );
OA21XLTS U1546 ( .A0(n2645), .A1(n2037), .B0(n1913), .Y(n950) );
CLKBUFX3TS U1547 ( .A(n915), .Y(n2739) );
OR2X1TS U1548 ( .A(FPMULT_Op_MY[9]), .B(FPMULT_Op_MY[8]), .Y(n955) );
CLKBUFX2TS U1549 ( .A(n2789), .Y(n2780) );
INVX4TS U1550 ( .A(n1689), .Y(n1786) );
INVX2TS U1551 ( .A(n941), .Y(n957) );
INVX2TS U1552 ( .A(n957), .Y(n958) );
INVX4TS U1553 ( .A(n957), .Y(n959) );
INVX2TS U1554 ( .A(operation[1]), .Y(n960) );
INVX2TS U1555 ( .A(n960), .Y(n961) );
OAI221X1TS U1556 ( .A0(n2674), .A1(FPADDSUB_intDY_EWSW[1]), .B0(n2619), .B1(
FPADDSUB_intDY_EWSW[0]), .C0(n2189), .Y(n2192) );
OAI221X1TS U1557 ( .A0(n2675), .A1(FPADDSUB_intDY_EWSW[17]), .B0(n2679),
.B1(FPADDSUB_intDY_EWSW[16]), .C0(n2197), .Y(n2200) );
OAI21X1TS U1558 ( .A0(n1746), .A1(n2689), .B0(n1716), .Y(n1697) );
OAI21X1TS U1559 ( .A0(n1746), .A1(n2688), .B0(n1716), .Y(n1707) );
NOR2X1TS U1560 ( .A(n1002), .B(n1084), .Y(mult_x_219_n151) );
OAI21XLTS U1561 ( .A0(n1963), .A1(n1885), .B0(n1962), .Y(
FPADDSUB_Data_array_SWR[4]) );
OAI21XLTS U1562 ( .A0(n1959), .A1(n1885), .B0(n1934), .Y(
FPADDSUB_Data_array_SWR[7]) );
OAI21XLTS U1563 ( .A0(n1958), .A1(n1885), .B0(n1926), .Y(
FPADDSUB_Data_array_SWR[5]) );
OAI21XLTS U1564 ( .A0(n1959), .A1(n2371), .B0(n1911), .Y(
FPADDSUB_Data_array_SWR[6]) );
AOI221X4TS U1565 ( .A0(FPADDSUB_intDX_EWSW[30]), .A1(n2741), .B0(
FPADDSUB_intDX_EWSW[29]), .B1(n2740), .C0(n2128), .Y(n2130) );
NOR4X2TS U1566 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .Y(n1776) );
NAND3X2TS U1567 ( .A(n2600), .B(n2608), .C(n2651), .Y(n2280) );
NOR2X2TS U1568 ( .A(n1716), .B(n2663), .Y(n1748) );
OAI32X1TS U1569 ( .A0(n1005), .A1(FPMULT_Op_MY[8]), .A2(n1025), .B0(n1338),
.B1(n1343), .Y(n1341) );
OAI32X1TS U1570 ( .A0(n1005), .A1(n999), .A2(n1025), .B0(n1334), .B1(n1343),
.Y(n1337) );
OAI32X1TS U1571 ( .A0(n1005), .A1(FPMULT_Op_MY[10]), .A2(n2597), .B0(n1330),
.B1(n1343), .Y(n1333) );
INVX2TS U1572 ( .A(n947), .Y(n962) );
NOR2X2TS U1573 ( .A(n2653), .B(n1613), .Y(n2016) );
NOR2X2TS U1574 ( .A(n2110), .B(n2114), .Y(n2109) );
NOR2X2TS U1575 ( .A(n2107), .B(n2108), .Y(n2106) );
NOR2X2TS U1576 ( .A(n2104), .B(n2105), .Y(n2103) );
NOR2X2TS U1577 ( .A(n2101), .B(n2102), .Y(n2100) );
NOR2X2TS U1578 ( .A(n2098), .B(n2099), .Y(n2097) );
NOR2X2TS U1579 ( .A(n2095), .B(n2096), .Y(n2094) );
NOR2X2TS U1580 ( .A(n2092), .B(n2093), .Y(n2091) );
NOR2X2TS U1581 ( .A(n2089), .B(n2090), .Y(n2088) );
NOR2X2TS U1582 ( .A(n2086), .B(n2087), .Y(n2085) );
BUFX4TS U1583 ( .A(n964), .Y(n2797) );
BUFX4TS U1584 ( .A(n2801), .Y(n2795) );
BUFX4TS U1585 ( .A(n963), .Y(n2794) );
BUFX3TS U1586 ( .A(n1687), .Y(n963) );
BUFX3TS U1587 ( .A(n1687), .Y(n964) );
NOR4X1TS U1588 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[29]), .C(
FPMULT_Op_MY[28]), .D(FPMULT_Op_MY[27]), .Y(n2569) );
NOR4X1TS U1589 ( .A(n984), .B(FPMULT_Op_MY[12]), .C(n999), .D(n995), .Y(
n2573) );
NOR4X1TS U1590 ( .A(n997), .B(n991), .C(n993), .D(FPMULT_Op_MY[0]), .Y(n2571) );
BUFX3TS U1591 ( .A(n2809), .Y(n1691) );
BUFX4TS U1592 ( .A(n2757), .Y(n2767) );
BUFX4TS U1593 ( .A(n2761), .Y(n2766) );
OAI21X2TS U1594 ( .A0(FPMULT_FS_Module_state_reg[2]), .A1(
FPMULT_FSM_add_overflow_flag), .B0(n2225), .Y(n2229) );
BUFX4TS U1595 ( .A(n2745), .Y(n2771) );
NOR4X1TS U1596 ( .A(n973), .B(FPMULT_Op_MY[18]), .C(n1002), .D(n1000), .Y(
n2576) );
NOR4X1TS U1597 ( .A(n1004), .B(n981), .C(FPMULT_Op_MY[16]), .D(n972), .Y(
n2572) );
OAI211X1TS U1598 ( .A0(n2662), .A1(n1817), .B0(n1734), .C0(n1733), .Y(n1764)
);
AOI21X2TS U1599 ( .A0(n1750), .A1(FPADDSUB_Data_array_SWR[50]), .B0(n1749),
.Y(n1817) );
BUFX4TS U1600 ( .A(n2816), .Y(n2793) );
BUFX4TS U1601 ( .A(n2801), .Y(n2798) );
BUFX4TS U1602 ( .A(n2810), .Y(n2808) );
BUFX4TS U1603 ( .A(n2796), .Y(n2811) );
BUFX4TS U1604 ( .A(n1691), .Y(n2806) );
BUFX4TS U1605 ( .A(n2804), .Y(n2803) );
BUFX4TS U1606 ( .A(n2765), .Y(n2769) );
OAI211X1TS U1607 ( .A0(n2662), .A1(n1840), .B0(n1839), .C0(n1838), .Y(n1851)
);
AOI21X2TS U1608 ( .A0(n1750), .A1(FPADDSUB_Data_array_SWR[49]), .B0(n1749),
.Y(n1840) );
NOR2X2TS U1609 ( .A(n2111), .B(n2112), .Y(n2115) );
INVX2TS U1610 ( .A(FPMULT_Sgf_normalized_result[3]), .Y(n2111) );
AOI21X2TS U1611 ( .A0(FPADDSUB_Data_array_SWR[48]), .A1(n1750), .B0(n1749),
.Y(n1845) );
BUFX3TS U1612 ( .A(n1695), .Y(n1750) );
AOI21X2TS U1613 ( .A0(n1750), .A1(FPADDSUB_Data_array_SWR[46]), .B0(n1715),
.Y(n1833) );
OAI21X1TS U1614 ( .A0(n1746), .A1(n2622), .B0(n1716), .Y(n1715) );
AOI21X2TS U1615 ( .A0(n1750), .A1(FPADDSUB_Data_array_SWR[47]), .B0(n1717),
.Y(n1837) );
OAI21X1TS U1616 ( .A0(n1746), .A1(n1739), .B0(n1716), .Y(n1717) );
BUFX4TS U1617 ( .A(n964), .Y(n2814) );
NOR2X4TS U1618 ( .A(n2598), .B(n2600), .Y(n2552) );
AOI211XLTS U1619 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n2679), .B0(n2172),
.C0(n2173), .Y(n2164) );
OAI211X2TS U1620 ( .A0(FPADDSUB_intDX_EWSW[20]), .A1(n2711), .B0(n2196),
.C0(n2163), .Y(n2172) );
CLKINVX3TS U1621 ( .A(n1742), .Y(n1698) );
OAI221X4TS U1622 ( .A0(FPMULT_Op_MX[6]), .A1(FPMULT_Op_MX[7]), .B0(n1010),
.B1(n911), .C0(n1335), .Y(n1236) );
BUFX4TS U1623 ( .A(n2548), .Y(n2524) );
CLKINVX6TS U1624 ( .A(n1846), .Y(n1852) );
BUFX6TS U1625 ( .A(FPADDSUB_left_right_SHT2), .Y(n1846) );
NOR3X2TS U1626 ( .A(n2669), .B(n2225), .C(n1788), .Y(n107) );
BUFX3TS U1627 ( .A(n2789), .Y(n966) );
BUFX4TS U1628 ( .A(n2789), .Y(n2782) );
BUFX4TS U1629 ( .A(n2789), .Y(n2774) );
CLKINVX6TS U1630 ( .A(n979), .Y(n1280) );
BUFX4TS U1631 ( .A(n2482), .Y(n2507) );
BUFX4TS U1632 ( .A(n1786), .Y(n2746) );
BUFX4TS U1633 ( .A(n1786), .Y(n2756) );
NAND2BX1TS U1634 ( .AN(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n2278) );
NAND2X1TS U1635 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n2682),
.Y(n2564) );
OAI22X2TS U1636 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .B0(FPADDSUB_LZD_raw_out_EWR[0]),
.B1(n1897), .Y(n1887) );
BUFX6TS U1637 ( .A(n2473), .Y(n2499) );
INVX2TS U1638 ( .A(n946), .Y(n967) );
BUFX6TS U1639 ( .A(n2482), .Y(n2501) );
INVX2TS U1640 ( .A(n945), .Y(n968) );
CLKINVX3TS U1641 ( .A(n1693), .Y(n2381) );
INVX2TS U1642 ( .A(FPMULT_Op_MY[1]), .Y(n969) );
CLKINVX3TS U1643 ( .A(n969), .Y(n970) );
NOR4X1TS U1644 ( .A(FPMULT_Op_MX[13]), .B(FPMULT_Op_MX[12]), .C(
FPMULT_Op_MX[5]), .D(FPMULT_Op_MX[7]), .Y(n2581) );
NOR4X1TS U1645 ( .A(FPMULT_Op_MX[19]), .B(FPMULT_Op_MX[18]), .C(
FPMULT_Op_MX[22]), .D(n971), .Y(n2584) );
CLKINVX6TS U1646 ( .A(n971), .Y(n1166) );
CLKINVX3TS U1647 ( .A(n1020), .Y(n972) );
OAI221X4TS U1648 ( .A0(FPMULT_Op_MX[8]), .A1(n978), .B0(n1009), .B1(n1339),
.C0(n1345), .Y(n1229) );
OAI32X1TS U1649 ( .A0(n1339), .A1(FPMULT_Op_MY[0]), .A2(n1345), .B0(n1229),
.B1(n1339), .Y(n1340) );
BUFX4TS U1650 ( .A(n1228), .Y(n1345) );
OAI221X4TS U1651 ( .A0(FPMULT_Op_MX[4]), .A1(FPMULT_Op_MX[5]), .B0(n1011),
.B1(n912), .C0(n1292), .Y(n1178) );
BUFX4TS U1652 ( .A(n1177), .Y(n1292) );
OAI221X4TS U1653 ( .A0(FPMULT_Op_MX[16]), .A1(n977), .B0(n1024), .B1(n1126),
.C0(n1111), .Y(n1033) );
OAI32X1TS U1654 ( .A0(n1126), .A1(FPMULT_Op_MY[12]), .A2(n1111), .B0(n1033),
.B1(n1126), .Y(n1146) );
BUFX4TS U1655 ( .A(n1032), .Y(n1111) );
CLKINVX3TS U1656 ( .A(n1017), .Y(n973) );
INVX2TS U1657 ( .A(n1885), .Y(n974) );
INVX2TS U1658 ( .A(n974), .Y(n975) );
NOR2X1TS U1659 ( .A(n1331), .B(n930), .Y(mult_x_254_n168) );
BUFX4TS U1660 ( .A(n1217), .Y(n1331) );
OAI221X4TS U1661 ( .A0(FPMULT_Op_MX[20]), .A1(n971), .B0(n1023), .B1(n1166),
.C0(n1170), .Y(n1073) );
NOR2XLTS U1662 ( .A(n927), .B(n1170), .Y(n1175) );
BUFX4TS U1663 ( .A(n1072), .Y(n1170) );
OAI21X2TS U1664 ( .A0(n2636), .A1(n2037), .B0(n1909), .Y(n1961) );
INVX2TS U1665 ( .A(n950), .Y(n980) );
OAI21X2TS U1666 ( .A0(n2653), .A1(n2037), .B0(n1903), .Y(n1967) );
OAI221X4TS U1667 ( .A0(FPMULT_Op_MX[18]), .A1(n1139), .B0(n1022), .B1(n1162),
.C0(n1161), .Y(n1076) );
NOR2X1TS U1668 ( .A(n927), .B(n1161), .Y(mult_x_219_n190) );
OAI32X1TS U1669 ( .A0(n1162), .A1(FPMULT_Op_MY[12]), .A2(n1161), .B0(n1076),
.B1(n1162), .Y(n1163) );
BUFX4TS U1670 ( .A(n1075), .Y(n1161) );
NOR2X2TS U1671 ( .A(n2599), .B(FPMULT_FS_Module_state_reg[3]), .Y(n1790) );
NOR2X1TS U1672 ( .A(n927), .B(n1085), .Y(mult_x_219_n162) );
CLKINVX6TS U1673 ( .A(n2379), .Y(n2378) );
INVX2TS U1674 ( .A(n2379), .Y(n2377) );
BUFX4TS U1675 ( .A(n1701), .Y(n1842) );
INVX2TS U1676 ( .A(FPMULT_Op_MY[13]), .Y(n983) );
CLKINVX6TS U1677 ( .A(n2366), .Y(n2369) );
CLKINVX6TS U1678 ( .A(n2366), .Y(n2364) );
CLKINVX6TS U1679 ( .A(n2366), .Y(n2365) );
OAI32X1TS U1680 ( .A0(n1005), .A1(n991), .A2(n2597), .B0(n1191), .B1(n1343),
.Y(n1195) );
OAI32X1TS U1681 ( .A0(n1005), .A1(n997), .A2(n2597), .B0(n1182), .B1(n1343),
.Y(n1190) );
OAI32X1TS U1682 ( .A0(n1005), .A1(FPMULT_Op_MY[4]), .A2(n1025), .B0(n1187),
.B1(n1343), .Y(n1285) );
INVX3TS U1683 ( .A(n1005), .Y(n1343) );
BUFX4TS U1684 ( .A(n2637), .Y(n2589) );
INVX3TS U1685 ( .A(n1897), .Y(n1912) );
CLKINVX3TS U1686 ( .A(n948), .Y(n985) );
INVX3TS U1687 ( .A(n948), .Y(n986) );
CLKINVX3TS U1688 ( .A(n949), .Y(n987) );
INVX3TS U1689 ( .A(n949), .Y(n988) );
OAI221X4TS U1690 ( .A0(FPMULT_Op_MX[10]), .A1(n1306), .B0(n1008), .B1(n958),
.C0(n1331), .Y(n1218) );
INVX2TS U1691 ( .A(n921), .Y(n989) );
NOR2X1TS U1692 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n2025) );
NOR4X1TS U1693 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C(FPADDSUB_Raw_mant_NRM_SWR[11]), .D(
n2021), .Y(n1637) );
NOR3X1TS U1694 ( .A(FPADDSUB_Raw_mant_NRM_SWR[15]), .B(
FPADDSUB_Raw_mant_NRM_SWR[16]), .C(FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(
n2015) );
OAI21XLTS U1695 ( .A0(n1965), .A1(n975), .B0(n1938), .Y(
FPADDSUB_Data_array_SWR[15]) );
OAI21XLTS U1696 ( .A0(n1965), .A1(n2371), .B0(n1905), .Y(
FPADDSUB_Data_array_SWR[14]) );
NOR4X1TS U1697 ( .A(FPMULT_Op_MX[11]), .B(n977), .C(FPMULT_Op_MX[16]), .D(
n976), .Y(n2580) );
BUFX4TS U1698 ( .A(FPMULT_Op_MX[11]), .Y(n1306) );
OAI21XLTS U1699 ( .A0(n1964), .A1(n975), .B0(n1929), .Y(
FPADDSUB_Data_array_SWR[13]) );
NOR4X1TS U1700 ( .A(FPMULT_Op_MX[4]), .B(FPMULT_Op_MX[10]), .C(n978), .D(
FPMULT_Op_MX[8]), .Y(n2582) );
NOR4X1TS U1701 ( .A(n979), .B(FPMULT_Op_MX[2]), .C(FPMULT_Op_MX[6]), .D(
n1005), .Y(n2579) );
OAI221X4TS U1702 ( .A0(FPMULT_Op_MX[2]), .A1(n979), .B0(n1012), .B1(n1280),
.C0(n1348), .Y(n1181) );
NOR3X1TS U1703 ( .A(FPADDSUB_Raw_mant_NRM_SWR[12]), .B(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C(FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(
n2022) );
INVX2TS U1704 ( .A(FPMULT_Op_MY[2]), .Y(n990) );
INVX2TS U1705 ( .A(FPMULT_Op_MY[7]), .Y(n992) );
INVX2TS U1706 ( .A(FPMULT_Op_MY[5]), .Y(n994) );
INVX2TS U1707 ( .A(FPMULT_Op_MY[3]), .Y(n996) );
INVX2TS U1708 ( .A(FPMULT_Op_MY[6]), .Y(n998) );
CLKINVX3TS U1709 ( .A(n998), .Y(n999) );
OAI32X1TS U1710 ( .A0(FPMULT_Op_MX[12]), .A1(n972), .A2(n2596), .B0(n1037),
.B1(n918), .Y(n1045) );
INVX2TS U1711 ( .A(FPMULT_Op_MY[22]), .Y(n1001) );
INVX2TS U1712 ( .A(FPMULT_Op_MY[11]), .Y(n1003) );
INVX4TS U1713 ( .A(n916), .Y(n1005) );
ADDHX4TS U1714 ( .A(FPMULT_Op_MX[12]), .B(n1005), .CO(n1358), .S(
DP_OP_454J321_123_2743_n453) );
OAI32X1TS U1715 ( .A0(FPMULT_Op_MX[12]), .A1(FPMULT_Op_MY[14]), .A2(n2596),
.B0(n1046), .B1(n918), .Y(n1050) );
OAI221X1TS U1716 ( .A0(n2741), .A1(FPADDSUB_intDX_EWSW[30]), .B0(n2681),
.B1(FPADDSUB_intDY_EWSW[20]), .C0(n2203), .Y(n2218) );
OAI221X1TS U1717 ( .A0(n2618), .A1(FPADDSUB_intDY_EWSW[5]), .B0(n2677), .B1(
FPADDSUB_intDY_EWSW[4]), .C0(n2195), .Y(n2202) );
NOR2X1TS U1718 ( .A(n930), .B(n1335), .Y(mult_x_254_n196) );
BUFX4TS U1719 ( .A(n1235), .Y(n1335) );
CLKINVX6TS U1720 ( .A(n1473), .Y(n1468) );
NOR4X2TS U1721 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n1686) );
NOR4X1TS U1722 ( .A(FPMULT_Sgf_operation_Result[2]), .B(
FPMULT_Sgf_operation_Result[10]), .C(n1678), .D(
FPMULT_Sgf_operation_Result[14]), .Y(n2738) );
NOR4X1TS U1723 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n2737) );
NOR4X1TS U1724 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n2735) );
NOR4X1TS U1725 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n2736) );
NOR4X1TS U1726 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n2734) );
NOR4X1TS U1727 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n1621),
.Y(n2731) );
NOR3X6TS U1728 ( .A(n1646), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .C(n1643),
.Y(n2830) );
XNOR2X2TS U1729 ( .A(DP_OP_26J321_124_9022_n1), .B(FPADDSUB_ADD_OVRFLW_NRM2),
.Y(n1646) );
BUFX4TS U1730 ( .A(n963), .Y(n2815) );
NOR4X1TS U1731 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_Op_MX[26]), .C(
FPMULT_Op_MX[23]), .D(FPMULT_Op_MX[27]), .Y(n2578) );
NOR2XLTS U1732 ( .A(n923), .B(n955), .Y(n2574) );
NOR2X4TS U1733 ( .A(n2608), .B(n2651), .Y(n2511) );
NOR2X2TS U1734 ( .A(n2670), .B(FPMULT_FS_Module_state_reg[2]), .Y(n1789) );
OAI211X2TS U1735 ( .A0(FPADDSUB_intDX_EWSW[12]), .A1(n2673), .B0(n2158),
.C0(n2144), .Y(n2160) );
BUFX4TS U1736 ( .A(n2493), .Y(n2468) );
BUFX4TS U1737 ( .A(n2540), .Y(n2549) );
NOR3X2TS U1738 ( .A(FPADDSUB_Raw_mant_NRM_SWR[5]), .B(
FPADDSUB_Raw_mant_NRM_SWR[4]), .C(n2014), .Y(n2011) );
NOR3X2TS U1739 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n2224), .C(n1783),
.Y(n2562) );
NOR2X2TS U1740 ( .A(FPMULT_Sgf_normalized_result[4]), .B(n2115), .Y(n2114)
);
NOR3X2TS U1741 ( .A(FPMULT_Sgf_normalized_result[2]), .B(
FPMULT_Sgf_normalized_result[1]), .C(FPMULT_Sgf_normalized_result[0]),
.Y(n2112) );
OAI32X4TS U1742 ( .A0(n1030), .A1(FPSENCOS_d_ff1_operation_out), .A2(n967),
.B0(FPSENCOS_d_ff1_shift_region_flag_out_0_), .B1(n2359), .Y(n2360) );
OAI21XLTS U1743 ( .A0(n1953), .A1(n2371), .B0(n1908), .Y(
FPADDSUB_Data_array_SWR[10]) );
OAI21XLTS U1744 ( .A0(n1953), .A1(n975), .B0(n1936), .Y(
FPADDSUB_Data_array_SWR[11]) );
OAI21XLTS U1745 ( .A0(n1957), .A1(n975), .B0(n1956), .Y(
FPADDSUB_Data_array_SWR[8]) );
OAI21XLTS U1746 ( .A0(n1952), .A1(n975), .B0(n1922), .Y(
FPADDSUB_Data_array_SWR[9]) );
AOI21X2TS U1747 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(n2600), .B0(n1694),
.Y(n1805) );
OAI21X2TS U1748 ( .A0(n1897), .A1(n2641), .B0(n1896), .Y(n1972) );
BUFX4TS U1749 ( .A(n2753), .Y(n2765) );
BUFX4TS U1750 ( .A(n2751), .Y(n2743) );
BUFX4TS U1751 ( .A(n2749), .Y(n2763) );
BUFX4TS U1752 ( .A(n2760), .Y(n2764) );
BUFX4TS U1753 ( .A(n2758), .Y(n2757) );
BUFX4TS U1754 ( .A(n2747), .Y(n2770) );
NOR2X4TS U1755 ( .A(n1887), .B(n1899), .Y(n1940) );
NOR2X4TS U1756 ( .A(n1899), .B(n1898), .Y(n1973) );
AOI22X2TS U1757 ( .A0(n1912), .A1(FPADDSUB_LZD_raw_out_EWR[1]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[1]), .B1(n2637), .Y(n1899) );
OAI221X1TS U1758 ( .A0(n2740), .A1(FPADDSUB_intDX_EWSW[29]), .B0(n2680),
.B1(FPADDSUB_intDY_EWSW[18]), .C0(n2187), .Y(n2194) );
CLKAND2X4TS U1759 ( .A(n1790), .B(n1767), .Y(FPMULT_FSM_exp_operation_A_S)
);
AOI21X2TS U1760 ( .A0(n1750), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n1697),
.Y(n1850) );
AOI21X2TS U1761 ( .A0(n1750), .A1(FPADDSUB_Data_array_SWR[44]), .B0(n1707),
.Y(n1854) );
NOR3BX2TS U1762 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(n1685),
.C(n1774), .Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]) );
NOR4BX2TS U1763 ( .AN(n1686), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]),
.C(n1685), .D(n1029), .Y(FPSENCOS_enab_RB3) );
AOI222X4TS U1764 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[2]), .A1(n2630), .B0(
FPADDSUB_DmP_mant_SFG_SWR[2]), .B1(n2307), .C0(n2630), .C1(n2307), .Y(
n1801) );
NOR3X1TS U1765 ( .A(FPADDSUB_Raw_mant_NRM_SWR[19]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .C(FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(
n2009) );
NOR2X2TS U1766 ( .A(FPADDSUB_Raw_mant_NRM_SWR[7]), .B(n1607), .Y(n2028) );
AOI211X4TS U1767 ( .A0(FPADDSUB_Data_array_SWR[42]), .A1(n1750), .B0(n1748),
.C0(n1747), .Y(n1813) );
AOI211X4TS U1768 ( .A0(FPADDSUB_Data_array_SWR[43]), .A1(n1750), .B0(n1748),
.C0(n1711), .Y(n1766) );
NOR4X1TS U1769 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[30]), .C(
FPMULT_Op_MX[29]), .D(FPMULT_Op_MX[28]), .Y(n2577) );
OAI221X4TS U1770 ( .A0(FPMULT_Op_MX[14]), .A1(n976), .B0(n1016), .B1(n1142),
.C0(n1173), .Y(n1036) );
CLKINVX6TS U1771 ( .A(n2561), .Y(n2789) );
INVX4TS U1772 ( .A(n2386), .Y(n2385) );
CLKINVX3TS U1773 ( .A(n2358), .Y(n2386) );
BUFX3TS U1774 ( .A(n2226), .Y(n1006) );
BUFX3TS U1775 ( .A(n2226), .Y(n2274) );
NOR2X1TS U1776 ( .A(n2227), .B(n2676), .Y(n2226) );
BUFX3TS U1777 ( .A(n2228), .Y(n1007) );
BUFX3TS U1778 ( .A(n2228), .Y(n2275) );
NOR2X1TS U1779 ( .A(FPMULT_FSM_selector_C), .B(n2227), .Y(n2228) );
OAI2BB1X1TS U1780 ( .A0N(FPADDSUB_Raw_mant_NRM_SWR[10]), .A1N(n2739), .B0(
n1906), .Y(n1955) );
NAND2X2TS U1781 ( .A(FPADDSUB_bit_shift_SHT2), .B(
FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n1716) );
NAND3X2TS U1782 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .C(n2662), .Y(n1742) );
OAI32X1TS U1783 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[23]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[21]), .A2(n2655), .B0(n2610), .B1(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n1638) );
AOI222X4TS U1784 ( .A0(FPADDSUB_DMP_SFG[8]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[10]), .B0(FPADDSUB_DMP_SFG[8]), .B1(n1891),
.C0(FPADDSUB_DmP_mant_SFG_SWR[10]), .C1(n1891), .Y(n2315) );
AOI222X4TS U1785 ( .A0(FPADDSUB_DMP_SFG[12]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[14]), .B0(FPADDSUB_DMP_SFG[12]), .B1(n1984),
.C0(FPADDSUB_DmP_mant_SFG_SWR[14]), .C1(n1984), .Y(n2326) );
AOI222X4TS U1786 ( .A0(FPADDSUB_DMP_SFG[14]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[16]), .B0(FPADDSUB_DMP_SFG[14]), .B1(n1990),
.C0(FPADDSUB_DmP_mant_SFG_SWR[16]), .C1(n1990), .Y(n2331) );
AOI222X4TS U1787 ( .A0(FPADDSUB_DMP_SFG[16]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[18]), .B0(FPADDSUB_DMP_SFG[16]), .B1(n1996),
.C0(FPADDSUB_DmP_mant_SFG_SWR[18]), .C1(n1996), .Y(n2336) );
AOI222X4TS U1788 ( .A0(FPADDSUB_DMP_SFG[18]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[20]), .B0(FPADDSUB_DMP_SFG[18]), .B1(n2002),
.C0(FPADDSUB_DmP_mant_SFG_SWR[20]), .C1(n2002), .Y(n2341) );
AOI222X4TS U1789 ( .A0(FPADDSUB_DMP_SFG[20]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[22]), .B0(FPADDSUB_DMP_SFG[20]), .B1(n2034),
.C0(FPADDSUB_DmP_mant_SFG_SWR[22]), .C1(n2034), .Y(n2346) );
AOI222X4TS U1790 ( .A0(FPADDSUB_DMP_SFG[2]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[4]), .B0(FPADDSUB_DMP_SFG[2]), .B1(n1808),
.C0(FPADDSUB_DmP_mant_SFG_SWR[4]), .C1(n1808), .Y(n1822) );
AOI222X4TS U1791 ( .A0(FPADDSUB_DMP_SFG[6]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[8]), .B0(FPADDSUB_DMP_SFG[6]), .B1(n1880),
.C0(FPADDSUB_DmP_mant_SFG_SWR[8]), .C1(n1880), .Y(n2310) );
NOR4X2TS U1792 ( .A(FPADDSUB_Raw_mant_NRM_SWR[24]), .B(
FPADDSUB_Raw_mant_NRM_SWR[25]), .C(FPADDSUB_Raw_mant_NRM_SWR[22]), .D(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n2006) );
AOI222X4TS U1793 ( .A0(FPADDSUB_DMP_SFG[22]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[24]), .B0(FPADDSUB_DMP_SFG[22]), .B1(n2353),
.C0(FPADDSUB_DmP_mant_SFG_SWR[24]), .C1(n2353), .Y(n2117) );
AOI31XLTS U1794 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n1635), .A2(n2654),
.B0(n1634), .Y(n1617) );
NOR3BX2TS U1795 ( .AN(FPSENCOS_cont_var_out[1]), .B(n954), .C(
FPSENCOS_cont_var_out[0]), .Y(FPSENCOS_enab_d_ff4_Zn) );
ADDHX4TS U1796 ( .A(FPMULT_Op_MY[12]), .B(FPMULT_Op_MY[0]), .CO(n1357), .S(
DP_OP_454J321_123_2743_n367) );
INVX2TS U1797 ( .A(rst), .Y(n1688) );
OAI21XLTS U1798 ( .A0(FPADDSUB_intDX_EWSW[1]), .A1(n2718), .B0(
FPADDSUB_intDX_EWSW[0]), .Y(n2134) );
OAI21XLTS U1799 ( .A0(FPADDSUB_intDX_EWSW[15]), .A1(n2713), .B0(
FPADDSUB_intDX_EWSW[14]), .Y(n2154) );
NOR2XLTS U1800 ( .A(n2167), .B(FPADDSUB_intDY_EWSW[16]), .Y(n2168) );
OAI21XLTS U1801 ( .A0(FPADDSUB_intDX_EWSW[23]), .A1(n2742), .B0(
FPADDSUB_intDX_EWSW[22]), .Y(n2174) );
OAI21XLTS U1802 ( .A0(n1362), .A1(n1419), .B0(n1516), .Y(n1423) );
NOR2XLTS U1803 ( .A(n959), .B(n928), .Y(n1304) );
NOR2XLTS U1804 ( .A(n930), .B(n1345), .Y(n1350) );
INVX2TS U1805 ( .A(n1577), .Y(n1574) );
CLKINVX6TS U1806 ( .A(n1575), .Y(n1576) );
OAI21XLTS U1807 ( .A0(n2596), .A1(n1016), .B0(n976), .Y(mult_x_219_n205) );
OAI21XLTS U1808 ( .A0(n911), .A1(n1009), .B0(n978), .Y(mult_x_254_n169) );
BUFX4TS U1809 ( .A(n1025), .Y(n2597) );
NOR2XLTS U1810 ( .A(n1499), .B(n1561), .Y(n1367) );
OAI21XLTS U1811 ( .A0(n940), .A1(n1166), .B0(n1124), .Y(n1123) );
BUFX4TS U1812 ( .A(n1027), .Y(n2596) );
OAI21XLTS U1813 ( .A0(n1993), .A1(n1995), .B0(n1992), .Y(n1991) );
OAI21XLTS U1814 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[17]), .A1(n2609), .B0(n2333),
.Y(n2334) );
INVX2TS U1815 ( .A(FPMULT_Sgf_normalized_result[5]), .Y(n2110) );
INVX2TS U1816 ( .A(FPMULT_Sgf_normalized_result[15]), .Y(n2095) );
AOI31XLTS U1817 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[16]), .A1(n1636), .A2(n2647),
.B0(n2016), .Y(n1641) );
OAI21XLTS U1818 ( .A0(n1987), .A1(n1989), .B0(n1986), .Y(n1985) );
OAI21XLTS U1819 ( .A0(n1862), .A1(n1879), .B0(n1861), .Y(n1860) );
NOR3XLTS U1820 ( .A(FPMULT_Exp_module_Data_S[8]), .B(
FPMULT_Exp_module_Data_S[7]), .C(n1866), .Y(n2834) );
OR2X1TS U1821 ( .A(FPSENCOS_d_ff_Xn[28]), .B(n914), .Y(
FPSENCOS_first_mux_X[28]) );
NOR2XLTS U1822 ( .A(n2086), .B(n1787), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[21]) );
NOR2XLTS U1823 ( .A(n2095), .B(n2376), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[15]) );
OAI21XLTS U1824 ( .A0(n962), .A1(n1696), .B0(n1814), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[25]) );
OR2X1TS U1825 ( .A(FPSENCOS_d_ff_Xn[3]), .B(n2381), .Y(
FPSENCOS_first_mux_X[3]) );
OAI21XLTS U1826 ( .A0(n1969), .A1(n975), .B0(n1968), .Y(
FPADDSUB_Data_array_SWR[12]) );
OAI21XLTS U1827 ( .A0(n1932), .A1(n1885), .B0(n1931), .Y(
FPADDSUB_Data_array_SWR[3]) );
OAI21XLTS U1828 ( .A0(n2592), .A1(n2727), .B0(n2591), .Y(
FPSENCOS_sh_exp_y[5]) );
OAI21XLTS U1829 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n2672), .B0(
intadd_1084_CI), .Y(FPSENCOS_sh_exp_x[0]) );
OR2X1TS U1830 ( .A(n2830), .B(FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(
FPADDSUB_formatted_number_W[28]) );
OAI21XLTS U1831 ( .A0(FPADDSUB_DmP_EXP_EWSW[23]), .A1(n1014), .B0(n1797),
.Y(FPADDSUB_Shift_amount_EXP_EW[0]) );
INVX4TS U1832 ( .A(n976), .Y(n1142) );
AOI22X1TS U1833 ( .A0(n976), .A1(n1024), .B0(FPMULT_Op_MX[16]), .B1(n1142),
.Y(n1032) );
INVX4TS U1834 ( .A(n977), .Y(n1126) );
AOI22X1TS U1835 ( .A0(n977), .A1(n983), .B0(n984), .B1(n1126), .Y(n1109) );
AOI22X1TS U1836 ( .A0(FPMULT_Op_MY[12]), .A1(n1126), .B0(n977), .B1(n927),
.Y(n1034) );
OAI22X1TS U1837 ( .A0(n1111), .A1(n1109), .B0(n1033), .B1(n1034), .Y(n1041)
);
AOI22X1TS U1838 ( .A0(FPMULT_Op_MX[13]), .A1(n1016), .B0(FPMULT_Op_MX[14]),
.B1(n2596), .Y(n1035) );
BUFX4TS U1839 ( .A(n1035), .Y(n1173) );
AOI22X1TS U1840 ( .A0(n976), .A1(n1020), .B0(n972), .B1(n1142), .Y(n1115) );
AOI22X1TS U1841 ( .A0(n976), .A1(n1018), .B0(FPMULT_Op_MY[14]), .B1(n1142),
.Y(n1038) );
OAI22X1TS U1842 ( .A0(n1173), .A1(n1115), .B0(n1036), .B1(n1038), .Y(n1040)
);
AOI22X1TS U1843 ( .A0(FPMULT_Op_MX[13]), .A1(n933), .B0(FPMULT_Op_MY[16]),
.B1(n2596), .Y(n1037) );
NOR2XLTS U1844 ( .A(n927), .B(n1111), .Y(n1044) );
AOI22X1TS U1845 ( .A0(n976), .A1(n926), .B0(n984), .B1(n1142), .Y(n1048) );
OAI22X1TS U1846 ( .A0(n1173), .A1(n1038), .B0(n1036), .B1(n1048), .Y(n1043)
);
CMPR32X2TS U1847 ( .A(n1041), .B(n1040), .C(n1039), .CO(n1069), .S(n1145) );
AOI22X1TS U1848 ( .A0(FPMULT_Op_MX[13]), .A1(n1019), .B0(n981), .B1(n2596),
.Y(n1042) );
CMPR32X2TS U1849 ( .A(n1045), .B(n1044), .C(n1043), .CO(n1039), .S(n1153) );
AOI22X1TS U1850 ( .A0(FPMULT_Op_MX[13]), .A1(n1020), .B0(n972), .B1(n2596),
.Y(n1046) );
AOI22X1TS U1851 ( .A0(FPMULT_Op_MY[12]), .A1(n1142), .B0(n976), .B1(n927),
.Y(n1047) );
OAI22X1TS U1852 ( .A0(n1173), .A1(n1048), .B0(n1036), .B1(n1047), .Y(n1049)
);
ADDHXLTS U1853 ( .A(n1050), .B(n1049), .CO(n1152), .S(n1150) );
OAI32X1TS U1854 ( .A0(n1142), .A1(FPMULT_Op_MY[12]), .A2(n1173), .B0(n1036),
.B1(n1142), .Y(n1149) );
AOI22X1TS U1855 ( .A0(FPMULT_Op_MX[13]), .A1(n1018), .B0(FPMULT_Op_MY[14]),
.B1(n2596), .Y(n1051) );
NOR2XLTS U1856 ( .A(n927), .B(n1173), .Y(n1158) );
AOI21X1TS U1857 ( .A0(FPMULT_Op_MY[12]), .A1(FPMULT_Op_MX[12]), .B0(n2596),
.Y(n1071) );
NAND2X1TS U1858 ( .A(FPMULT_Op_MX[13]), .B(n918), .Y(n1053) );
AOI22X1TS U1859 ( .A0(FPMULT_Op_MX[13]), .A1(n983), .B0(n984), .B1(n2596),
.Y(n1052) );
OAI22X1TS U1860 ( .A0(FPMULT_Op_MY[12]), .A1(n1053), .B0(n1052), .B1(n918),
.Y(n1070) );
CMPR32X2TS U1861 ( .A(mult_x_219_n40), .B(mult_x_219_n36), .C(n1054), .CO(
n1117), .S(FPMULT_Sgf_operation_EVEN1_left_N20) );
CMPR32X2TS U1862 ( .A(mult_x_219_n45), .B(mult_x_219_n41), .C(n1055), .CO(
n1054), .S(FPMULT_Sgf_operation_EVEN1_left_N19) );
CMPR32X2TS U1863 ( .A(mult_x_219_n46), .B(mult_x_219_n52), .C(n1056), .CO(
n1055), .S(FPMULT_Sgf_operation_EVEN1_left_N18) );
CMPR32X2TS U1864 ( .A(mult_x_219_n53), .B(mult_x_219_n58), .C(n1057), .CO(
n1056), .S(FPMULT_Sgf_operation_EVEN1_left_N17) );
CMPR32X2TS U1865 ( .A(mult_x_219_n59), .B(mult_x_219_n66), .C(n1058), .CO(
n1057), .S(FPMULT_Sgf_operation_EVEN1_left_N16) );
CMPR32X2TS U1866 ( .A(mult_x_219_n67), .B(mult_x_219_n74), .C(n1059), .CO(
n1058), .S(FPMULT_Sgf_operation_EVEN1_left_N15) );
CMPR32X2TS U1867 ( .A(mult_x_219_n75), .B(mult_x_219_n84), .C(n1060), .CO(
n1059), .S(FPMULT_Sgf_operation_EVEN1_left_N14) );
CMPR32X2TS U1868 ( .A(mult_x_219_n85), .B(mult_x_219_n93), .C(n1061), .CO(
n1060), .S(FPMULT_Sgf_operation_EVEN1_left_N13) );
CMPR32X2TS U1869 ( .A(mult_x_219_n94), .B(mult_x_219_n101), .C(n1062), .CO(
n1061), .S(FPMULT_Sgf_operation_EVEN1_left_N12) );
CMPR32X2TS U1870 ( .A(mult_x_219_n102), .B(mult_x_219_n109), .C(n1063), .CO(
n1062), .S(FPMULT_Sgf_operation_EVEN1_left_N11) );
CMPR32X2TS U1871 ( .A(mult_x_219_n110), .B(mult_x_219_n115), .C(n1064), .CO(
n1063), .S(FPMULT_Sgf_operation_EVEN1_left_N10) );
CMPR32X2TS U1872 ( .A(mult_x_219_n116), .B(mult_x_219_n122), .C(n1065), .CO(
n1064), .S(FPMULT_Sgf_operation_EVEN1_left_N9) );
CMPR32X2TS U1873 ( .A(mult_x_219_n123), .B(mult_x_219_n127), .C(n1066), .CO(
n1065), .S(FPMULT_Sgf_operation_EVEN1_left_N8) );
CMPR32X2TS U1874 ( .A(mult_x_219_n128), .B(mult_x_219_n132), .C(n1067), .CO(
n1066), .S(FPMULT_Sgf_operation_EVEN1_left_N7) );
CMPR32X2TS U1875 ( .A(mult_x_219_n133), .B(n1069), .C(n1068), .CO(n1067),
.S(FPMULT_Sgf_operation_EVEN1_left_N6) );
ADDHXLTS U1876 ( .A(n1071), .B(n1070), .CO(n1157), .S(
FPMULT_Sgf_operation_EVEN1_left_N1) );
BUFX4TS U1877 ( .A(FPMULT_Op_MX[19]), .Y(n1139) );
INVX4TS U1878 ( .A(n1139), .Y(n1162) );
AOI22X1TS U1879 ( .A0(n1139), .A1(n1023), .B0(FPMULT_Op_MX[20]), .B1(n1162),
.Y(n1072) );
AOI22X1TS U1880 ( .A0(n971), .A1(n1001), .B0(n1002), .B1(n1166), .Y(n1138)
);
OAI22X1TS U1881 ( .A0(n971), .A1(n1170), .B0(n1138), .B1(n1073), .Y(n1074)
);
CMPR32X2TS U1882 ( .A(n973), .B(FPMULT_Op_MY[18]), .C(n1074), .CO(
mult_x_219_n42), .S(mult_x_219_n43) );
AOI22X1TS U1883 ( .A0(n977), .A1(n1022), .B0(FPMULT_Op_MX[18]), .B1(n1126),
.Y(n1075) );
AOI22X1TS U1884 ( .A0(n1139), .A1(n1021), .B0(n1000), .B1(n1162), .Y(n1093)
);
AOI22X1TS U1885 ( .A0(n1139), .A1(n1026), .B0(FPMULT_Op_MY[20]), .B1(n1162),
.Y(n1078) );
OAI22X1TS U1886 ( .A0(n1161), .A1(n1093), .B0(n1076), .B1(n1078), .Y(n1077)
);
CMPR32X2TS U1887 ( .A(n972), .B(n984), .C(n1077), .CO(mult_x_219_n71), .S(
mult_x_219_n72) );
AOI22X1TS U1888 ( .A0(n1139), .A1(n1017), .B0(n973), .B1(n1162), .Y(n1095)
);
OAI22X1TS U1889 ( .A0(n1161), .A1(n1078), .B0(n1076), .B1(n1095), .Y(n1079)
);
CMPR32X2TS U1890 ( .A(n983), .B(FPMULT_Op_MY[14]), .C(n1079), .CO(
mult_x_219_n79), .S(mult_x_219_n80) );
AOI22X1TS U1891 ( .A0(n971), .A1(n1019), .B0(n981), .B1(n1166), .Y(n1088) );
AOI22X1TS U1892 ( .A0(n971), .A1(n933), .B0(FPMULT_Op_MY[16]), .B1(n1166),
.Y(n1090) );
OAI22X1TS U1893 ( .A0(n1170), .A1(n1088), .B0(n1073), .B1(n1090), .Y(n1081)
);
AOI22X1TS U1894 ( .A0(n977), .A1(n1021), .B0(n1000), .B1(n1126), .Y(n1101)
);
AOI22X1TS U1895 ( .A0(n977), .A1(n1026), .B0(FPMULT_Op_MY[20]), .B1(n1126),
.Y(n1103) );
OAI22X1TS U1896 ( .A0(n1111), .A1(n1101), .B0(n1033), .B1(n1103), .Y(n1080)
);
CMPR32X2TS U1897 ( .A(n1081), .B(n983), .C(n1080), .CO(mult_x_219_n89), .S(
mult_x_219_n90) );
AOI22X1TS U1898 ( .A0(n976), .A1(n1001), .B0(n1002), .B1(n1142), .Y(n1112)
);
AOI22X1TS U1899 ( .A0(n976), .A1(n1021), .B0(n1000), .B1(n1142), .Y(n1113)
);
OAI22X1TS U1900 ( .A0(n1173), .A1(n1112), .B0(n1036), .B1(n1113), .Y(n1082)
);
CMPR32X2TS U1901 ( .A(n1083), .B(FPMULT_Op_MY[12]), .C(n1082), .CO(
mult_x_219_n98), .S(mult_x_219_n99) );
AOI22X1TS U1902 ( .A0(n971), .A1(FPMULT_Op_MX[22]), .B0(n940), .B1(n1166),
.Y(n1120) );
OAI22X1TS U1903 ( .A0(n1000), .A1(n1084), .B0(n1002), .B1(n1085), .Y(
mult_x_219_n152) );
OAI22X1TS U1904 ( .A0(FPMULT_Op_MY[20]), .A1(n1084), .B0(n1000), .B1(n1085),
.Y(mult_x_219_n153) );
OAI22X1TS U1905 ( .A0(n973), .A1(n1084), .B0(FPMULT_Op_MY[20]), .B1(n1085),
.Y(mult_x_219_n154) );
OAI22X1TS U1906 ( .A0(FPMULT_Op_MY[18]), .A1(n1084), .B0(n973), .B1(n1085),
.Y(mult_x_219_n155) );
OAI22X1TS U1907 ( .A0(n981), .A1(n1084), .B0(FPMULT_Op_MY[18]), .B1(n1085),
.Y(mult_x_219_n156) );
OAI22X1TS U1908 ( .A0(FPMULT_Op_MY[16]), .A1(n1084), .B0(n981), .B1(n1085),
.Y(mult_x_219_n157) );
OAI22X1TS U1909 ( .A0(n972), .A1(n1084), .B0(FPMULT_Op_MY[16]), .B1(n1085),
.Y(mult_x_219_n158) );
OAI22X1TS U1910 ( .A0(FPMULT_Op_MY[14]), .A1(n1084), .B0(n972), .B1(n1085),
.Y(mult_x_219_n159) );
OAI22X1TS U1911 ( .A0(n984), .A1(n1084), .B0(FPMULT_Op_MY[14]), .B1(n1085),
.Y(mult_x_219_n160) );
OAI22X1TS U1912 ( .A0(n984), .A1(n1085), .B0(FPMULT_Op_MY[12]), .B1(n1084),
.Y(mult_x_219_n161) );
AOI22X1TS U1913 ( .A0(n971), .A1(n1170), .B0(n1073), .B1(n1166), .Y(
mult_x_219_n164) );
AOI22X1TS U1914 ( .A0(n971), .A1(n1021), .B0(n1000), .B1(n1166), .Y(n1137)
);
AOI22X1TS U1915 ( .A0(n971), .A1(n1026), .B0(FPMULT_Op_MY[20]), .B1(n1166),
.Y(n1086) );
OAI22X1TS U1916 ( .A0(n1170), .A1(n1137), .B0(n1073), .B1(n1086), .Y(
mult_x_219_n167) );
AOI22X1TS U1917 ( .A0(n971), .A1(n1017), .B0(n973), .B1(n1166), .Y(n1087) );
OAI22X1TS U1918 ( .A0(n1170), .A1(n1086), .B0(n1073), .B1(n1087), .Y(
mult_x_219_n168) );
AOI22X1TS U1919 ( .A0(n971), .A1(n934), .B0(FPMULT_Op_MY[18]), .B1(n1166),
.Y(n1089) );
OAI22X1TS U1920 ( .A0(n1170), .A1(n1087), .B0(n1073), .B1(n1089), .Y(
mult_x_219_n169) );
OAI22X1TS U1921 ( .A0(n1170), .A1(n1089), .B0(n1073), .B1(n1088), .Y(
mult_x_219_n170) );
AOI22X1TS U1922 ( .A0(n971), .A1(n1020), .B0(n972), .B1(n1166), .Y(n1091) );
OAI22X1TS U1923 ( .A0(n1170), .A1(n1090), .B0(n1073), .B1(n1091), .Y(
mult_x_219_n172) );
AOI22X1TS U1924 ( .A0(n971), .A1(n1018), .B0(FPMULT_Op_MY[14]), .B1(n1166),
.Y(n1092) );
OAI22X1TS U1925 ( .A0(n1170), .A1(n1091), .B0(n1073), .B1(n1092), .Y(
mult_x_219_n173) );
AOI22X1TS U1926 ( .A0(n971), .A1(n983), .B0(n984), .B1(n1166), .Y(n1128) );
OAI22X1TS U1927 ( .A0(n1170), .A1(n1092), .B0(n1073), .B1(n1128), .Y(
mult_x_219_n174) );
AOI22X1TS U1928 ( .A0(n1139), .A1(n1001), .B0(n1002), .B1(n1162), .Y(n1094)
);
OAI22X1TS U1929 ( .A0(n1139), .A1(n1161), .B0(n1094), .B1(n1076), .Y(
mult_x_219_n179) );
OAI22X1TS U1930 ( .A0(n1161), .A1(n1094), .B0(n1076), .B1(n1093), .Y(
mult_x_219_n180) );
AOI22X1TS U1931 ( .A0(n1139), .A1(n934), .B0(FPMULT_Op_MY[18]), .B1(n1162),
.Y(n1096) );
OAI22X1TS U1932 ( .A0(n1161), .A1(n1095), .B0(n1076), .B1(n1096), .Y(
mult_x_219_n183) );
AOI22X1TS U1933 ( .A0(n1139), .A1(n1019), .B0(n981), .B1(n1162), .Y(n1097)
);
OAI22X1TS U1934 ( .A0(n1161), .A1(n1096), .B0(n1076), .B1(n1097), .Y(
mult_x_219_n184) );
AOI22X1TS U1935 ( .A0(n1139), .A1(n933), .B0(FPMULT_Op_MY[16]), .B1(n1162),
.Y(n1098) );
OAI22X1TS U1936 ( .A0(n1161), .A1(n1097), .B0(n1076), .B1(n1098), .Y(
mult_x_219_n185) );
AOI22X1TS U1937 ( .A0(n1139), .A1(n1020), .B0(n972), .B1(n1162), .Y(n1131)
);
OAI22X1TS U1938 ( .A0(n1161), .A1(n1098), .B0(n1076), .B1(n1131), .Y(
mult_x_219_n186) );
AOI22X1TS U1939 ( .A0(n1139), .A1(n1018), .B0(FPMULT_Op_MY[14]), .B1(n1162),
.Y(n1130) );
AOI22X1TS U1940 ( .A0(n1139), .A1(n983), .B0(n984), .B1(n1162), .Y(n1100) );
OAI22X1TS U1941 ( .A0(n1161), .A1(n1130), .B0(n1076), .B1(n1100), .Y(
mult_x_219_n188) );
AOI22X1TS U1942 ( .A0(FPMULT_Op_MY[12]), .A1(n1162), .B0(n1139), .B1(n927),
.Y(n1099) );
OAI22X1TS U1943 ( .A0(n1161), .A1(n1100), .B0(n1076), .B1(n1099), .Y(
mult_x_219_n189) );
AOI22X1TS U1944 ( .A0(n977), .A1(n1111), .B0(n1033), .B1(n1126), .Y(
mult_x_219_n192) );
AOI22X1TS U1945 ( .A0(n977), .A1(n1001), .B0(n1002), .B1(n1126), .Y(n1102)
);
OAI22X1TS U1946 ( .A0(n977), .A1(n1111), .B0(n1102), .B1(n1033), .Y(
mult_x_219_n193) );
OAI22X1TS U1947 ( .A0(n1111), .A1(n1102), .B0(n1033), .B1(n1101), .Y(
mult_x_219_n194) );
AOI22X1TS U1948 ( .A0(n977), .A1(n1017), .B0(n973), .B1(n1126), .Y(n1104) );
OAI22X1TS U1949 ( .A0(n1111), .A1(n1103), .B0(n1033), .B1(n1104), .Y(
mult_x_219_n196) );
AOI22X1TS U1950 ( .A0(n977), .A1(n934), .B0(FPMULT_Op_MY[18]), .B1(n1126),
.Y(n1105) );
OAI22X1TS U1951 ( .A0(n1111), .A1(n1104), .B0(n1033), .B1(n1105), .Y(
mult_x_219_n197) );
AOI22X1TS U1952 ( .A0(n977), .A1(n1019), .B0(n981), .B1(n1126), .Y(n1106) );
OAI22X1TS U1953 ( .A0(n1111), .A1(n1105), .B0(n1033), .B1(n1106), .Y(
mult_x_219_n198) );
AOI22X1TS U1954 ( .A0(n977), .A1(n933), .B0(FPMULT_Op_MY[16]), .B1(n1126),
.Y(n1107) );
OAI22X1TS U1955 ( .A0(n1111), .A1(n1106), .B0(n1033), .B1(n1107), .Y(
mult_x_219_n199) );
AOI22X1TS U1956 ( .A0(n977), .A1(n1020), .B0(n972), .B1(n1126), .Y(n1108) );
OAI22X1TS U1957 ( .A0(n1111), .A1(n1107), .B0(n1033), .B1(n1108), .Y(
mult_x_219_n200) );
AOI22X1TS U1958 ( .A0(n977), .A1(n1018), .B0(FPMULT_Op_MY[14]), .B1(n1126),
.Y(n1110) );
OAI22X1TS U1959 ( .A0(n1111), .A1(n1108), .B0(n1033), .B1(n1110), .Y(
mult_x_219_n201) );
OAI22X1TS U1960 ( .A0(n1111), .A1(n1110), .B0(n1033), .B1(n1109), .Y(
mult_x_219_n202) );
AOI22X1TS U1961 ( .A0(n976), .A1(n1173), .B0(n1036), .B1(n1142), .Y(
mult_x_219_n206) );
OAI22X1TS U1962 ( .A0(n976), .A1(n1173), .B0(n1112), .B1(n1036), .Y(
mult_x_219_n207) );
AOI22X1TS U1963 ( .A0(n976), .A1(n1026), .B0(FPMULT_Op_MY[20]), .B1(n1142),
.Y(n1114) );
OAI22X1TS U1964 ( .A0(n1173), .A1(n1113), .B0(n1036), .B1(n1114), .Y(
mult_x_219_n209) );
AOI22X1TS U1965 ( .A0(n976), .A1(n1017), .B0(n973), .B1(n1142), .Y(n1129) );
OAI22X1TS U1966 ( .A0(n1173), .A1(n1114), .B0(n1036), .B1(n1129), .Y(
mult_x_219_n210) );
AOI22X1TS U1967 ( .A0(n976), .A1(n1019), .B0(n981), .B1(n1142), .Y(n1171) );
AOI22X1TS U1968 ( .A0(n976), .A1(n933), .B0(FPMULT_Op_MY[16]), .B1(n1142),
.Y(n1116) );
OAI22X1TS U1969 ( .A0(n1173), .A1(n1171), .B0(n1036), .B1(n1116), .Y(
mult_x_219_n213) );
OAI22X1TS U1970 ( .A0(n1173), .A1(n1116), .B0(n1036), .B1(n1115), .Y(
mult_x_219_n214) );
CMPR32X2TS U1971 ( .A(mult_x_219_n35), .B(mult_x_219_n33), .C(n1117), .CO(
n1118), .S(FPMULT_Sgf_operation_EVEN1_left_N21) );
CMPR32X2TS U1972 ( .A(mult_x_219_n32), .B(n1119), .C(n1118), .CO(n1122), .S(
FPMULT_Sgf_operation_EVEN1_left_N22) );
CMPR32X2TS U1973 ( .A(n1120), .B(n1001), .C(mult_x_219_n31), .CO(n1121), .S(
n1119) );
XOR2X1TS U1974 ( .A(n1122), .B(n1121), .Y(n1124) );
OAI31X1TS U1975 ( .A0(n1124), .A1(n940), .A2(n1166), .B0(n1123), .Y(n1125)
);
XNOR2X1TS U1976 ( .A(n1002), .B(n1125), .Y(
FPMULT_Sgf_operation_EVEN1_left_N23) );
OAI21X1TS U1977 ( .A0(n1126), .A1(n1022), .B0(n1139), .Y(mult_x_219_n177) );
AOI22X1TS U1978 ( .A0(n971), .A1(n927), .B0(FPMULT_Op_MY[12]), .B1(n1166),
.Y(n1127) );
OAI22X1TS U1979 ( .A0(n1170), .A1(n1128), .B0(n1073), .B1(n1127), .Y(n1134)
);
AOI22X1TS U1980 ( .A0(n976), .A1(n934), .B0(FPMULT_Op_MY[18]), .B1(n1142),
.Y(n1172) );
OAI22X1TS U1981 ( .A0(n1173), .A1(n1129), .B0(n1036), .B1(n1172), .Y(n1133)
);
OAI22X1TS U1982 ( .A0(n1161), .A1(n1131), .B0(n1076), .B1(n1130), .Y(n1132)
);
CMPR32X2TS U1983 ( .A(n1134), .B(n1133), .C(n1132), .CO(mult_x_219_n117),
.S(mult_x_219_n118) );
AOI22X1TS U1984 ( .A0(FPMULT_Op_MX[13]), .A1(n934), .B0(FPMULT_Op_MY[18]),
.B1(n2596), .Y(n1135) );
AOI22X1TS U1985 ( .A0(FPMULT_Op_MX[13]), .A1(n938), .B0(n1002), .B1(n2596),
.Y(n1136) );
OAI22X1TS U1986 ( .A0(n1170), .A1(n1138), .B0(n1073), .B1(n1137), .Y(n1141)
);
AOI22X1TS U1987 ( .A0(n1139), .A1(n1161), .B0(n1076), .B1(n1162), .Y(n1140)
);
CMPR32X2TS U1988 ( .A(n1141), .B(n934), .C(n1140), .CO(mult_x_219_n47), .S(
mult_x_219_n48) );
OAI21X1TS U1989 ( .A0(n1142), .A1(n1024), .B0(n977), .Y(mult_x_219_n191) );
CMPR32X2TS U1990 ( .A(n1145), .B(n1144), .C(n1143), .CO(n1068), .S(
FPMULT_Sgf_operation_EVEN1_left_N5) );
ADDHXLTS U1991 ( .A(n1147), .B(n1146), .CO(mult_x_219_n136), .S(n1144) );
CMPR32X2TS U1992 ( .A(n1150), .B(n1149), .C(n1148), .CO(n1151), .S(
FPMULT_Sgf_operation_EVEN1_left_N3) );
CMPR32X2TS U1993 ( .A(n1153), .B(n1152), .C(n1151), .CO(n1143), .S(
FPMULT_Sgf_operation_EVEN1_left_N4) );
OAI21XLTS U1994 ( .A0(FPMULT_Op_MY[12]), .A1(n1085), .B0(n1084), .Y(n1156)
);
ADDHXLTS U1995 ( .A(n1156), .B(n1155), .CO(mult_x_219_n106), .S(
mult_x_219_n107) );
CMPR32X2TS U1996 ( .A(n1159), .B(n1158), .C(n1157), .CO(n1148), .S(
FPMULT_Sgf_operation_EVEN1_left_N2) );
OAI21XLTS U1997 ( .A0(n1162), .A1(n1023), .B0(n971), .Y(mult_x_219_n163) );
AOI22X1TS U1998 ( .A0(FPMULT_Op_MX[13]), .A1(n1017), .B0(n973), .B1(n2596),
.Y(n1160) );
ADDHXLTS U1999 ( .A(n1164), .B(n1163), .CO(mult_x_219_n129), .S(
mult_x_219_n130) );
AOI22X1TS U2000 ( .A0(FPMULT_Op_MX[13]), .A1(n1021), .B0(n1000), .B1(n2596),
.Y(n1165) );
ADDHXLTS U2001 ( .A(n1168), .B(n1167), .CO(mult_x_219_n119), .S(
mult_x_219_n120) );
AOI22X1TS U2002 ( .A0(FPMULT_Op_MX[13]), .A1(n1026), .B0(FPMULT_Op_MY[20]),
.B1(n2596), .Y(n1169) );
OAI32X1TS U2003 ( .A0(FPMULT_Op_MX[12]), .A1(n973), .A2(n1027), .B0(n1169),
.B1(n918), .Y(n1176) );
OAI22X1TS U2004 ( .A0(n1173), .A1(n1172), .B0(n1036), .B1(n1171), .Y(n1174)
);
CMPR32X2TS U2005 ( .A(n1176), .B(n1175), .C(n1174), .CO(mult_x_219_n124),
.S(mult_x_219_n125) );
AOI22X1TS U2006 ( .A0(n979), .A1(n1011), .B0(FPMULT_Op_MX[4]), .B1(n1280),
.Y(n1177) );
AOI22X1TS U2007 ( .A0(FPMULT_Op_MX[5]), .A1(n969), .B0(n970), .B1(n912), .Y(
n1250) );
AOI22X1TS U2008 ( .A0(FPMULT_Op_MY[0]), .A1(n912), .B0(FPMULT_Op_MX[5]),
.B1(n930), .Y(n1179) );
OAI22X1TS U2009 ( .A0(n1292), .A1(n1250), .B0(n1178), .B1(n1179), .Y(n1186)
);
AOI22X1TS U2010 ( .A0(FPMULT_Op_MX[1]), .A1(n1012), .B0(FPMULT_Op_MX[2]),
.B1(n2597), .Y(n1180) );
BUFX4TS U2011 ( .A(n1180), .Y(n1348) );
AOI22X1TS U2012 ( .A0(n979), .A1(n996), .B0(n997), .B1(n1280), .Y(n1254) );
AOI22X1TS U2013 ( .A0(n979), .A1(n990), .B0(n991), .B1(n1280), .Y(n1183) );
OAI22X1TS U2014 ( .A0(n1348), .A1(n1254), .B0(n1181), .B1(n1183), .Y(n1185)
);
AOI22X1TS U2015 ( .A0(FPMULT_Op_MX[1]), .A1(n939), .B0(FPMULT_Op_MY[4]),
.B1(n2597), .Y(n1182) );
NOR2XLTS U2016 ( .A(n930), .B(n1292), .Y(n1189) );
AOI22X1TS U2017 ( .A0(n979), .A1(n929), .B0(n970), .B1(n1280), .Y(n1193) );
OAI22X1TS U2018 ( .A0(n1348), .A1(n1183), .B0(n1181), .B1(n1193), .Y(n1188)
);
CMPR32X2TS U2019 ( .A(n1186), .B(n1185), .C(n1184), .CO(n1214), .S(n1283) );
AOI22X1TS U2020 ( .A0(FPMULT_Op_MX[1]), .A1(n932), .B0(n995), .B1(n2597),
.Y(n1187) );
CMPR32X2TS U2021 ( .A(n1190), .B(n1189), .C(n1188), .CO(n1184), .S(n1321) );
AOI22X1TS U2022 ( .A0(FPMULT_Op_MX[1]), .A1(n928), .B0(n997), .B1(n2597),
.Y(n1191) );
AOI22X1TS U2023 ( .A0(FPMULT_Op_MY[0]), .A1(n1280), .B0(n979), .B1(n930),
.Y(n1192) );
OAI22X1TS U2024 ( .A0(n1348), .A1(n1193), .B0(n1181), .B1(n1192), .Y(n1194)
);
ADDHXLTS U2025 ( .A(n1195), .B(n1194), .CO(n1320), .S(n1318) );
OAI32X1TS U2026 ( .A0(n1280), .A1(FPMULT_Op_MY[0]), .A2(n1348), .B0(n1181),
.B1(n1280), .Y(n1317) );
AOI22X1TS U2027 ( .A0(FPMULT_Op_MX[1]), .A1(n931), .B0(n991), .B1(n2597),
.Y(n1196) );
NOR2XLTS U2028 ( .A(n930), .B(n1348), .Y(n1328) );
AOI21X1TS U2029 ( .A0(FPMULT_Op_MY[0]), .A1(n1005), .B0(n2597), .Y(n1216) );
NAND2X1TS U2030 ( .A(FPMULT_Op_MX[1]), .B(n1343), .Y(n1198) );
AOI22X1TS U2031 ( .A0(FPMULT_Op_MX[1]), .A1(n969), .B0(n970), .B1(n2597),
.Y(n1197) );
OAI22X1TS U2032 ( .A0(FPMULT_Op_MY[0]), .A1(n1198), .B0(n1197), .B1(n1343),
.Y(n1215) );
CMPR32X2TS U2033 ( .A(mult_x_254_n40), .B(mult_x_254_n36), .C(n1199), .CO(
n1257), .S(FPMULT_Sgf_operation_EVEN1_right_N20) );
CMPR32X2TS U2034 ( .A(mult_x_254_n45), .B(mult_x_254_n41), .C(n1200), .CO(
n1199), .S(FPMULT_Sgf_operation_EVEN1_right_N19) );
CMPR32X2TS U2035 ( .A(mult_x_254_n46), .B(mult_x_254_n52), .C(n1201), .CO(
n1200), .S(FPMULT_Sgf_operation_EVEN1_right_N18) );
CMPR32X2TS U2036 ( .A(mult_x_254_n53), .B(mult_x_254_n58), .C(n1202), .CO(
n1201), .S(FPMULT_Sgf_operation_EVEN1_right_N17) );
CMPR32X2TS U2037 ( .A(mult_x_254_n59), .B(mult_x_254_n66), .C(n1203), .CO(
n1202), .S(FPMULT_Sgf_operation_EVEN1_right_N16) );
CMPR32X2TS U2038 ( .A(mult_x_254_n67), .B(mult_x_254_n74), .C(n1204), .CO(
n1203), .S(FPMULT_Sgf_operation_EVEN1_right_N15) );
CMPR32X2TS U2039 ( .A(mult_x_254_n75), .B(mult_x_254_n84), .C(n1205), .CO(
n1204), .S(FPMULT_Sgf_operation_EVEN1_right_N14) );
CMPR32X2TS U2040 ( .A(mult_x_254_n85), .B(mult_x_254_n93), .C(n1206), .CO(
n1205), .S(FPMULT_Sgf_operation_EVEN1_right_N13) );
CMPR32X2TS U2041 ( .A(mult_x_254_n94), .B(mult_x_254_n101), .C(n1207), .CO(
n1206), .S(FPMULT_Sgf_operation_EVEN1_right_N12) );
CMPR32X2TS U2042 ( .A(mult_x_254_n102), .B(mult_x_254_n109), .C(n1208), .CO(
n1207), .S(FPMULT_Sgf_operation_EVEN1_right_N11) );
CMPR32X2TS U2043 ( .A(mult_x_254_n110), .B(mult_x_254_n115), .C(n1209), .CO(
n1208), .S(FPMULT_Sgf_operation_EVEN1_right_N10) );
CMPR32X2TS U2044 ( .A(mult_x_254_n116), .B(mult_x_254_n122), .C(n1210), .CO(
n1209), .S(FPMULT_Sgf_operation_EVEN1_right_N9) );
CMPR32X2TS U2045 ( .A(mult_x_254_n123), .B(mult_x_254_n127), .C(n1211), .CO(
n1210), .S(FPMULT_Sgf_operation_EVEN1_right_N8) );
CMPR32X2TS U2046 ( .A(mult_x_254_n128), .B(mult_x_254_n132), .C(n1212), .CO(
n1211), .S(FPMULT_Sgf_operation_EVEN1_right_N7) );
CMPR32X2TS U2047 ( .A(mult_x_254_n133), .B(n1214), .C(n1213), .CO(n1212),
.S(FPMULT_Sgf_operation_EVEN1_right_N6) );
ADDHXLTS U2048 ( .A(n1216), .B(n1215), .CO(n1327), .S(
FPMULT_Sgf_operation_EVEN1_right_N1) );
INVX4TS U2049 ( .A(n978), .Y(n1339) );
AOI22X1TS U2050 ( .A0(FPMULT_Op_MX[10]), .A1(n1339), .B0(n978), .B1(n1008),
.Y(n1217) );
AOI22X1TS U2051 ( .A0(n1306), .A1(n1003), .B0(n1004), .B1(n959), .Y(n1256)
);
AOI22X1TS U2052 ( .A0(n1306), .A1(n944), .B0(FPMULT_Op_MY[10]), .B1(n959),
.Y(n1219) );
OAI22X1TS U2053 ( .A0(n1331), .A1(n1256), .B0(n1218), .B1(n1219), .Y(
mult_x_254_n157) );
AOI22X1TS U2054 ( .A0(n1306), .A1(n942), .B0(FPMULT_Op_MY[9]), .B1(n959),
.Y(n1220) );
OAI22X1TS U2055 ( .A0(n1331), .A1(n1219), .B0(n1218), .B1(n1220), .Y(
mult_x_254_n158) );
AOI22X1TS U2056 ( .A0(n1306), .A1(n943), .B0(FPMULT_Op_MY[8]), .B1(n959),
.Y(n1221) );
OAI22X1TS U2057 ( .A0(n1331), .A1(n1220), .B0(n1218), .B1(n1221), .Y(
mult_x_254_n159) );
AOI22X1TS U2058 ( .A0(n1306), .A1(n992), .B0(n993), .B1(n959), .Y(n1222) );
OAI22X1TS U2059 ( .A0(n1331), .A1(n1221), .B0(n1218), .B1(n1222), .Y(
mult_x_254_n160) );
AOI22X1TS U2060 ( .A0(n1306), .A1(n998), .B0(n999), .B1(n959), .Y(n1223) );
OAI22X1TS U2061 ( .A0(n1331), .A1(n1222), .B0(n1218), .B1(n1223), .Y(
mult_x_254_n161) );
AOI22X1TS U2062 ( .A0(n1306), .A1(n994), .B0(n995), .B1(n959), .Y(n1224) );
OAI22X1TS U2063 ( .A0(n1331), .A1(n1223), .B0(n1218), .B1(n1224), .Y(
mult_x_254_n162) );
AOI22X1TS U2064 ( .A0(n1306), .A1(n939), .B0(FPMULT_Op_MY[4]), .B1(n959),
.Y(n1225) );
OAI22X1TS U2065 ( .A0(n1331), .A1(n1224), .B0(n1218), .B1(n1225), .Y(
mult_x_254_n163) );
AOI22X1TS U2066 ( .A0(n1306), .A1(n996), .B0(n997), .B1(n958), .Y(n1226) );
OAI22X1TS U2067 ( .A0(n1331), .A1(n1225), .B0(n1218), .B1(n1226), .Y(
mult_x_254_n164) );
AOI22X1TS U2068 ( .A0(n1306), .A1(n990), .B0(n991), .B1(n958), .Y(n1227) );
OAI22X1TS U2069 ( .A0(n1331), .A1(n1226), .B0(n1218), .B1(n1227), .Y(
mult_x_254_n165) );
AOI22X1TS U2070 ( .A0(n1306), .A1(n969), .B0(n970), .B1(n958), .Y(n1286) );
OAI22X1TS U2071 ( .A0(n1331), .A1(n1227), .B0(n1218), .B1(n1286), .Y(
mult_x_254_n166) );
AOI22X1TS U2072 ( .A0(FPMULT_Op_MX[7]), .A1(n1009), .B0(FPMULT_Op_MX[8]),
.B1(n911), .Y(n1228) );
AOI22X1TS U2073 ( .A0(n978), .A1(n1003), .B0(n1004), .B1(n1339), .Y(n1312)
);
OAI22X1TS U2074 ( .A0(n1339), .A1(n1345), .B0(n1229), .B1(n1312), .Y(
mult_x_254_n170) );
AOI22X1TS U2075 ( .A0(n978), .A1(n942), .B0(FPMULT_Op_MY[9]), .B1(n1339),
.Y(n1305) );
AOI22X1TS U2076 ( .A0(n978), .A1(n943), .B0(FPMULT_Op_MY[8]), .B1(n1339),
.Y(n1230) );
OAI22X1TS U2077 ( .A0(n1345), .A1(n1305), .B0(n1229), .B1(n1230), .Y(
mult_x_254_n173) );
AOI22X1TS U2078 ( .A0(n978), .A1(n992), .B0(n993), .B1(n1339), .Y(n1231) );
OAI22X1TS U2079 ( .A0(n1345), .A1(n1230), .B0(n1229), .B1(n1231), .Y(
mult_x_254_n174) );
AOI22X1TS U2080 ( .A0(n978), .A1(n998), .B0(n999), .B1(n1339), .Y(n1232) );
OAI22X1TS U2081 ( .A0(n1345), .A1(n1231), .B0(n1229), .B1(n1232), .Y(
mult_x_254_n175) );
AOI22X1TS U2082 ( .A0(n978), .A1(n994), .B0(n995), .B1(n1339), .Y(n1289) );
OAI22X1TS U2083 ( .A0(n1345), .A1(n1232), .B0(n1229), .B1(n1289), .Y(
mult_x_254_n176) );
AOI22X1TS U2084 ( .A0(n978), .A1(n939), .B0(FPMULT_Op_MY[4]), .B1(n1339),
.Y(n1288) );
AOI22X1TS U2085 ( .A0(n978), .A1(n996), .B0(n997), .B1(n1339), .Y(n1233) );
OAI22X1TS U2086 ( .A0(n1345), .A1(n1288), .B0(n1229), .B1(n1233), .Y(
mult_x_254_n178) );
AOI22X1TS U2087 ( .A0(n978), .A1(n990), .B0(n991), .B1(n1339), .Y(n1234) );
OAI22X1TS U2088 ( .A0(n1345), .A1(n1233), .B0(n1229), .B1(n1234), .Y(
mult_x_254_n179) );
AOI22X1TS U2089 ( .A0(n978), .A1(n969), .B0(n970), .B1(n1339), .Y(n1270) );
OAI22X1TS U2090 ( .A0(n1345), .A1(n1234), .B0(n1229), .B1(n1270), .Y(
mult_x_254_n180) );
AOI22X1TS U2091 ( .A0(FPMULT_Op_MX[5]), .A1(n1010), .B0(FPMULT_Op_MX[6]),
.B1(n912), .Y(n1235) );
AOI22X1TS U2092 ( .A0(n1004), .A1(n911), .B0(FPMULT_Op_MX[7]), .B1(n1003),
.Y(n1307) );
AOI22X1TS U2093 ( .A0(FPMULT_Op_MY[10]), .A1(n911), .B0(FPMULT_Op_MX[7]),
.B1(n944), .Y(n1237) );
OAI22X1TS U2094 ( .A0(n1335), .A1(n1307), .B0(n1236), .B1(n1237), .Y(
mult_x_254_n185) );
AOI22X1TS U2095 ( .A0(FPMULT_Op_MX[7]), .A1(n942), .B0(FPMULT_Op_MY[9]),
.B1(n911), .Y(n1301) );
OAI22X1TS U2096 ( .A0(n1335), .A1(n1237), .B0(n1236), .B1(n1301), .Y(
mult_x_254_n186) );
AOI22X1TS U2097 ( .A0(FPMULT_Op_MX[7]), .A1(n992), .B0(n993), .B1(n911), .Y(
n1296) );
AOI22X1TS U2098 ( .A0(FPMULT_Op_MX[7]), .A1(n998), .B0(n999), .B1(n911), .Y(
n1238) );
OAI22X1TS U2099 ( .A0(n1335), .A1(n1296), .B0(n1236), .B1(n1238), .Y(
mult_x_254_n189) );
AOI22X1TS U2100 ( .A0(FPMULT_Op_MX[7]), .A1(n994), .B0(n995), .B1(n911), .Y(
n1239) );
OAI22X1TS U2101 ( .A0(n1335), .A1(n1238), .B0(n1236), .B1(n1239), .Y(
mult_x_254_n190) );
AOI22X1TS U2102 ( .A0(FPMULT_Op_MX[7]), .A1(n939), .B0(FPMULT_Op_MY[4]),
.B1(n911), .Y(n1240) );
OAI22X1TS U2103 ( .A0(n1335), .A1(n1239), .B0(n1236), .B1(n1240), .Y(
mult_x_254_n191) );
AOI22X1TS U2104 ( .A0(FPMULT_Op_MX[7]), .A1(n996), .B0(n997), .B1(n911), .Y(
n1273) );
OAI22X1TS U2105 ( .A0(n1335), .A1(n1240), .B0(n1236), .B1(n1273), .Y(
mult_x_254_n192) );
AOI22X1TS U2106 ( .A0(FPMULT_Op_MX[7]), .A1(n990), .B0(n991), .B1(n911), .Y(
n1272) );
AOI22X1TS U2107 ( .A0(FPMULT_Op_MX[7]), .A1(n969), .B0(n970), .B1(n911), .Y(
n1242) );
OAI22X1TS U2108 ( .A0(n1335), .A1(n1272), .B0(n1236), .B1(n1242), .Y(
mult_x_254_n194) );
AOI22X1TS U2109 ( .A0(FPMULT_Op_MY[0]), .A1(n911), .B0(FPMULT_Op_MX[7]),
.B1(n930), .Y(n1241) );
OAI22X1TS U2110 ( .A0(n1335), .A1(n1242), .B0(n1236), .B1(n1241), .Y(
mult_x_254_n195) );
AOI22X1TS U2111 ( .A0(n1004), .A1(n912), .B0(FPMULT_Op_MX[5]), .B1(n1003),
.Y(n1243) );
OAI22X1TS U2112 ( .A0(n912), .A1(n1292), .B0(n1178), .B1(n1243), .Y(
mult_x_254_n198) );
AOI22X1TS U2113 ( .A0(FPMULT_Op_MY[10]), .A1(n912), .B0(FPMULT_Op_MX[5]),
.B1(n944), .Y(n1244) );
OAI22X1TS U2114 ( .A0(n1292), .A1(n1243), .B0(n1178), .B1(n1244), .Y(
mult_x_254_n199) );
AOI22X1TS U2115 ( .A0(FPMULT_Op_MX[5]), .A1(n942), .B0(FPMULT_Op_MY[9]),
.B1(n912), .Y(n1291) );
OAI22X1TS U2116 ( .A0(n1292), .A1(n1244), .B0(n1178), .B1(n1291), .Y(
mult_x_254_n200) );
AOI22X1TS U2117 ( .A0(FPMULT_Op_MX[5]), .A1(n943), .B0(FPMULT_Op_MY[8]),
.B1(n912), .Y(n1290) );
AOI22X1TS U2118 ( .A0(FPMULT_Op_MX[5]), .A1(n992), .B0(n993), .B1(n912), .Y(
n1245) );
OAI22X1TS U2119 ( .A0(n1292), .A1(n1290), .B0(n1178), .B1(n1245), .Y(
mult_x_254_n202) );
AOI22X1TS U2120 ( .A0(FPMULT_Op_MX[5]), .A1(n998), .B0(n999), .B1(n912), .Y(
n1246) );
OAI22X1TS U2121 ( .A0(n1292), .A1(n1245), .B0(n1178), .B1(n1246), .Y(
mult_x_254_n203) );
AOI22X1TS U2122 ( .A0(FPMULT_Op_MX[5]), .A1(n994), .B0(n995), .B1(n912), .Y(
n1247) );
OAI22X1TS U2123 ( .A0(n1292), .A1(n1246), .B0(n1178), .B1(n1247), .Y(
mult_x_254_n204) );
AOI22X1TS U2124 ( .A0(FPMULT_Op_MX[5]), .A1(n939), .B0(FPMULT_Op_MY[4]),
.B1(n912), .Y(n1248) );
OAI22X1TS U2125 ( .A0(n1292), .A1(n1247), .B0(n1178), .B1(n1248), .Y(
mult_x_254_n205) );
AOI22X1TS U2126 ( .A0(FPMULT_Op_MX[5]), .A1(n996), .B0(n997), .B1(n912), .Y(
n1249) );
OAI22X1TS U2127 ( .A0(n1292), .A1(n1248), .B0(n1178), .B1(n1249), .Y(
mult_x_254_n206) );
AOI22X1TS U2128 ( .A0(FPMULT_Op_MX[5]), .A1(n990), .B0(n991), .B1(n912), .Y(
n1251) );
OAI22X1TS U2129 ( .A0(n1292), .A1(n1249), .B0(n1178), .B1(n1251), .Y(
mult_x_254_n207) );
OAI22X1TS U2130 ( .A0(n1292), .A1(n1251), .B0(n1178), .B1(n1250), .Y(
mult_x_254_n208) );
AOI22X1TS U2131 ( .A0(n1004), .A1(n1280), .B0(n979), .B1(n920), .Y(n1252) );
OAI22X1TS U2132 ( .A0(n1280), .A1(n1348), .B0(n1181), .B1(n1252), .Y(
mult_x_254_n212) );
AOI22X1TS U2133 ( .A0(FPMULT_Op_MY[10]), .A1(n1280), .B0(n979), .B1(n944),
.Y(n1323) );
OAI22X1TS U2134 ( .A0(n1348), .A1(n1252), .B0(n1181), .B1(n1323), .Y(
mult_x_254_n213) );
AOI22X1TS U2135 ( .A0(n979), .A1(n942), .B0(FPMULT_Op_MY[9]), .B1(n1280),
.Y(n1322) );
AOI22X1TS U2136 ( .A0(n979), .A1(n943), .B0(FPMULT_Op_MY[8]), .B1(n1280),
.Y(n1253) );
OAI22X1TS U2137 ( .A0(n1348), .A1(n1322), .B0(n1181), .B1(n1253), .Y(
mult_x_254_n215) );
AOI22X1TS U2138 ( .A0(n979), .A1(n992), .B0(n993), .B1(n1280), .Y(n1271) );
OAI22X1TS U2139 ( .A0(n1348), .A1(n1253), .B0(n1181), .B1(n1271), .Y(
mult_x_254_n216) );
AOI22X1TS U2140 ( .A0(n979), .A1(n994), .B0(n995), .B1(n1280), .Y(n1346) );
AOI22X1TS U2141 ( .A0(n979), .A1(n939), .B0(FPMULT_Op_MY[4]), .B1(n1280),
.Y(n1255) );
OAI22X1TS U2142 ( .A0(n1348), .A1(n1346), .B0(n1181), .B1(n1255), .Y(
mult_x_254_n219) );
OAI22X1TS U2143 ( .A0(n1348), .A1(n1255), .B0(n1181), .B1(n1254), .Y(
mult_x_254_n220) );
OAI22X1TS U2144 ( .A0(n959), .A1(n1331), .B0(n1218), .B1(n1256), .Y(n1263)
);
NAND2X1TS U2145 ( .A(n1306), .B(FPMULT_Op_MY[10]), .Y(n1262) );
CMPR32X2TS U2146 ( .A(mult_x_254_n35), .B(mult_x_254_n33), .C(n1257), .CO(
n1260), .S(FPMULT_Sgf_operation_EVEN1_right_N21) );
AOI21X1TS U2147 ( .A0(FPMULT_Op_MX[10]), .A1(n978), .B0(n959), .Y(n1259) );
OAI221XLTS U2148 ( .A0(FPMULT_Op_MY[10]), .A1(n1004), .B0(n944), .B1(n1003),
.C0(n1306), .Y(n1258) );
XNOR2X1TS U2149 ( .A(n1259), .B(n1258), .Y(n1267) );
CMPR32X2TS U2150 ( .A(mult_x_254_n32), .B(n1261), .C(n1260), .CO(n1265), .S(
FPMULT_Sgf_operation_EVEN1_right_N22) );
CMPR32X2TS U2151 ( .A(n1263), .B(n1262), .C(mult_x_254_n31), .CO(n1264), .S(
n1261) );
XNOR2X1TS U2152 ( .A(n1265), .B(n1264), .Y(n1266) );
OAI21XLTS U2153 ( .A0(n1025), .A1(n1012), .B0(n979), .Y(mult_x_254_n211) );
OAI21X1TS U2154 ( .A0(n912), .A1(n1010), .B0(FPMULT_Op_MX[7]), .Y(
mult_x_254_n183) );
AOI22X1TS U2155 ( .A0(n978), .A1(n930), .B0(FPMULT_Op_MY[0]), .B1(n1339),
.Y(n1269) );
OAI22X1TS U2156 ( .A0(n1345), .A1(n1270), .B0(n1229), .B1(n1269), .Y(n1276)
);
AOI22X1TS U2157 ( .A0(n979), .A1(n998), .B0(n999), .B1(n1280), .Y(n1347) );
OAI22X1TS U2158 ( .A0(n1348), .A1(n1271), .B0(n1181), .B1(n1347), .Y(n1275)
);
OAI22X1TS U2159 ( .A0(n1335), .A1(n1273), .B0(n1236), .B1(n1272), .Y(n1274)
);
CMPR32X2TS U2160 ( .A(n1276), .B(n1275), .C(n1274), .CO(mult_x_254_n117),
.S(mult_x_254_n118) );
AOI22X1TS U2161 ( .A0(FPMULT_Op_MX[1]), .A1(n935), .B0(n999), .B1(n2597),
.Y(n1277) );
AOI22X1TS U2162 ( .A0(FPMULT_Op_MY[10]), .A1(n1025), .B0(FPMULT_Op_MX[1]),
.B1(n944), .Y(n1278) );
OAI32X1TS U2163 ( .A0(n1005), .A1(FPMULT_Op_MY[9]), .A2(n1025), .B0(n1278),
.B1(n1343), .Y(mult_x_254_n228) );
NAND2X1TS U2164 ( .A(n1306), .B(FPMULT_Op_MY[4]), .Y(mult_x_254_n64) );
NAND2X1TS U2165 ( .A(n1306), .B(FPMULT_Op_MY[8]), .Y(mult_x_254_n38) );
OAI21X1TS U2166 ( .A0(n1280), .A1(n1011), .B0(FPMULT_Op_MX[5]), .Y(
mult_x_254_n197) );
CMPR32X2TS U2167 ( .A(n1283), .B(n1282), .C(n1281), .CO(n1213), .S(
FPMULT_Sgf_operation_EVEN1_right_N5) );
ADDHXLTS U2168 ( .A(n1285), .B(n1284), .CO(mult_x_254_n136), .S(n1282) );
NOR2X1TS U2169 ( .A(n958), .B(n930), .Y(n1325) );
NOR2XLTS U2170 ( .A(n1306), .B(FPMULT_Op_MY[0]), .Y(n1287) );
OAI22X1TS U2171 ( .A0(n1345), .A1(n1289), .B0(n1229), .B1(n1288), .Y(n1294)
);
NAND2X1TS U2172 ( .A(n1306), .B(n970), .Y(n1299) );
OAI22X1TS U2173 ( .A0(n1292), .A1(n1291), .B0(n1178), .B1(n1290), .Y(n1293)
);
CMPR32X2TS U2174 ( .A(n1294), .B(n1299), .C(n1293), .CO(mult_x_254_n89), .S(
mult_x_254_n90) );
NOR2XLTS U2175 ( .A(n959), .B(n990), .Y(n1298) );
AOI22X1TS U2176 ( .A0(FPMULT_Op_MX[7]), .A1(n943), .B0(FPMULT_Op_MY[8]),
.B1(n911), .Y(n1300) );
OAI22X1TS U2177 ( .A0(n1335), .A1(n1300), .B0(n1236), .B1(n1296), .Y(n1297)
);
CMPR32X2TS U2178 ( .A(n1299), .B(n1298), .C(n1297), .CO(mult_x_254_n79), .S(
mult_x_254_n80) );
INVX2TS U2179 ( .A(n1299), .Y(n1303) );
OAI22X1TS U2180 ( .A0(n1335), .A1(n1301), .B0(n1236), .B1(n1300), .Y(n1302)
);
CMPR32X2TS U2181 ( .A(n1304), .B(n1303), .C(n1302), .CO(mult_x_254_n71), .S(
mult_x_254_n72) );
AOI22X1TS U2182 ( .A0(n978), .A1(n944), .B0(FPMULT_Op_MY[10]), .B1(n1339),
.Y(n1311) );
OAI22X1TS U2183 ( .A0(n1345), .A1(n1311), .B0(n1229), .B1(n1305), .Y(n1309)
);
NAND2X1TS U2184 ( .A(n1306), .B(n999), .Y(n1310) );
OAI22X1TS U2185 ( .A0(n911), .A1(n1335), .B0(n1236), .B1(n1307), .Y(n1308)
);
CMPR32X2TS U2186 ( .A(n1309), .B(n1310), .C(n1308), .CO(mult_x_254_n47), .S(
mult_x_254_n48) );
NOR2X1TS U2187 ( .A(n959), .B(n994), .Y(mult_x_254_n151) );
NOR2XLTS U2188 ( .A(n959), .B(n937), .Y(n1315) );
INVX2TS U2189 ( .A(n1310), .Y(n1314) );
OAI22X1TS U2190 ( .A0(n1345), .A1(n1312), .B0(n1229), .B1(n1311), .Y(n1313)
);
CMPR32X2TS U2191 ( .A(n1315), .B(n1314), .C(n1313), .CO(mult_x_254_n42), .S(
mult_x_254_n43) );
NOR2X1TS U2192 ( .A(n959), .B(n942), .Y(mult_x_254_n149) );
CMPR32X2TS U2193 ( .A(n1318), .B(n1317), .C(n1316), .CO(n1319), .S(
FPMULT_Sgf_operation_EVEN1_right_N3) );
CMPR32X2TS U2194 ( .A(n1321), .B(n1320), .C(n1319), .CO(n1281), .S(
FPMULT_Sgf_operation_EVEN1_right_N4) );
AOI21X1TS U2195 ( .A0(n1004), .A1(n1343), .B0(n2597), .Y(n1326) );
OAI22X1TS U2196 ( .A0(n1348), .A1(n1323), .B0(n1181), .B1(n1322), .Y(n1324)
);
CMPR32X2TS U2197 ( .A(n1326), .B(n1325), .C(n1324), .CO(mult_x_254_n98), .S(
mult_x_254_n99) );
INVX2TS U2198 ( .A(mult_x_254_n64), .Y(mult_x_254_n63) );
INVX2TS U2199 ( .A(mult_x_254_n38), .Y(mult_x_254_n37) );
CMPR32X2TS U2200 ( .A(n1329), .B(n1328), .C(n1327), .CO(n1316), .S(
FPMULT_Sgf_operation_EVEN1_right_N2) );
AOI22X1TS U2201 ( .A0(n1004), .A1(n1025), .B0(FPMULT_Op_MX[1]), .B1(n920),
.Y(n1330) );
ADDHXLTS U2202 ( .A(n1333), .B(n1332), .CO(mult_x_254_n106), .S(
mult_x_254_n107) );
AOI22X1TS U2203 ( .A0(FPMULT_Op_MX[1]), .A1(n937), .B0(n993), .B1(n2597),
.Y(n1334) );
ADDHXLTS U2204 ( .A(n1337), .B(n1336), .CO(mult_x_254_n129), .S(
mult_x_254_n130) );
AOI22X1TS U2205 ( .A0(FPMULT_Op_MX[1]), .A1(n942), .B0(FPMULT_Op_MY[9]),
.B1(n2597), .Y(n1338) );
ADDHXLTS U2206 ( .A(n1341), .B(n1340), .CO(mult_x_254_n119), .S(
mult_x_254_n120) );
AOI22X1TS U2207 ( .A0(FPMULT_Op_MX[1]), .A1(n943), .B0(FPMULT_Op_MY[8]),
.B1(n2597), .Y(n1344) );
OAI32X1TS U2208 ( .A0(n1005), .A1(n993), .A2(n1025), .B0(n1344), .B1(n1343),
.Y(n1351) );
OAI22X1TS U2209 ( .A0(n1348), .A1(n1347), .B0(n1181), .B1(n1346), .Y(n1349)
);
CMPR32X2TS U2210 ( .A(n1351), .B(n1350), .C(n1349), .CO(mult_x_254_n124),
.S(mult_x_254_n125) );
CMPR32X4TS U2211 ( .A(n979), .B(n976), .C(n1352), .CO(n1354), .S(n1516) );
INVX2TS U2212 ( .A(n1355), .Y(n1505) );
AOI22X1TS U2213 ( .A0(n1516), .A1(n1505), .B0(n1355), .B1(n1517), .Y(n1353)
);
INVX2TS U2214 ( .A(n1450), .Y(n1449) );
AOI22X1TS U2215 ( .A0(n1450), .A1(n1551), .B0(n1550), .B1(n1449), .Y(n1458)
);
OAI221X4TS U2216 ( .A0(n1355), .A1(n1550), .B0(n1505), .B1(n1551), .C0(n1561), .Y(n1559) );
INVX3TS U2217 ( .A(DP_OP_454J321_123_2743_n367), .Y(n1499) );
AOI22X1TS U2218 ( .A0(DP_OP_454J321_123_2743_n367), .A1(n1551), .B0(n1550),
.B1(n1499), .Y(n1356) );
OAI22X1TS U2219 ( .A0(n1561), .A1(n1458), .B0(n1559), .B1(n1356), .Y(n1383)
);
CMPR32X4TS U2220 ( .A(FPMULT_Op_MX[1]), .B(FPMULT_Op_MX[13]), .C(n1358),
.CO(n1361), .S(n1604) );
BUFX4TS U2221 ( .A(n1362), .Y(n1493) );
INVX2TS U2222 ( .A(n1519), .Y(n1518) );
AOI22X1TS U2223 ( .A0(n1519), .A1(n1493), .B0(n1604), .B1(n1518), .Y(n1360)
);
INVX4TS U2224 ( .A(DP_OP_454J321_123_2743_n453), .Y(n1495) );
OAI32X1TS U2225 ( .A0(DP_OP_454J321_123_2743_n453), .A1(n1521), .A2(n1493),
.B0(n1360), .B1(n1495), .Y(n1369) );
INVX2TS U2226 ( .A(n1365), .Y(n1419) );
AOI22X1TS U2227 ( .A0(n1604), .A1(n1419), .B0(n1365), .B1(n1362), .Y(n1363)
);
BUFX4TS U2228 ( .A(n1363), .Y(n1530) );
INVX2TS U2229 ( .A(n1457), .Y(n1456) );
AOI22X1TS U2230 ( .A0(n1457), .A1(n1517), .B0(n1516), .B1(n1456), .Y(n1378)
);
AOI22X1TS U2231 ( .A0(n1450), .A1(n1517), .B0(n1516), .B1(n1449), .Y(n1372)
);
OAI22X1TS U2232 ( .A0(n1530), .A1(n1378), .B0(n1366), .B1(n1372), .Y(n1368)
);
OAI32X1TS U2233 ( .A0(n1551), .A1(DP_OP_454J321_123_2743_n367), .A2(n1561),
.B0(n1559), .B1(n1551), .Y(n1381) );
CMPR32X2TS U2234 ( .A(n1369), .B(n1368), .C(n1367), .CO(n1382), .S(n1509) );
INVX2TS U2235 ( .A(n1521), .Y(n1520) );
AOI22X1TS U2236 ( .A0(n1521), .A1(n1493), .B0(n1604), .B1(n1520), .Y(n1370)
);
OAI32X1TS U2237 ( .A0(DP_OP_454J321_123_2743_n453), .A1(n1457), .A2(n1362),
.B0(n1370), .B1(n1495), .Y(n1377) );
AOI22X1TS U2238 ( .A0(DP_OP_454J321_123_2743_n367), .A1(n1517), .B0(n1516),
.B1(n1499), .Y(n1371) );
OAI22X1TS U2239 ( .A0(n1530), .A1(n1372), .B0(n1366), .B1(n1371), .Y(n1376)
);
OAI32X1TS U2240 ( .A0(n1517), .A1(DP_OP_454J321_123_2743_n367), .A2(n1530),
.B0(n1366), .B1(n1517), .Y(n1536) );
AOI22X1TS U2241 ( .A0(n1457), .A1(n1493), .B0(n1604), .B1(n1456), .Y(n1373)
);
OAI32X1TS U2242 ( .A0(DP_OP_454J321_123_2743_n453), .A1(n1450), .A2(n1362),
.B0(n1373), .B1(n1495), .Y(n1405) );
AOI21X1TS U2243 ( .A0(DP_OP_454J321_123_2743_n367), .A1(
DP_OP_454J321_123_2743_n453), .B0(n1362), .Y(n1547) );
NAND2X1TS U2244 ( .A(n1604), .B(n1495), .Y(n1375) );
AOI22X1TS U2245 ( .A0(n1450), .A1(n1493), .B0(n1604), .B1(n1449), .Y(n1374)
);
OAI22X1TS U2246 ( .A0(DP_OP_454J321_123_2743_n367), .A1(n1375), .B0(n1374),
.B1(n1495), .Y(n1546) );
ADDHXLTS U2247 ( .A(n1377), .B(n1376), .CO(n1508), .S(n1534) );
AOI22X1TS U2248 ( .A0(n1521), .A1(n1517), .B0(n1516), .B1(n1520), .Y(n1464)
);
OAI22X1TS U2249 ( .A0(n1530), .A1(n1464), .B0(n1366), .B1(n1378), .Y(n1549)
);
INVX2TS U2250 ( .A(n1553), .Y(n1552) );
AOI22X1TS U2251 ( .A0(n1553), .A1(n1493), .B0(n1604), .B1(n1552), .Y(n1380)
);
OAI32X1TS U2252 ( .A0(DP_OP_454J321_123_2743_n453), .A1(n1519), .A2(n1493),
.B0(n1380), .B1(n1495), .Y(n1548) );
CMPR32X2TS U2253 ( .A(n1383), .B(n1382), .C(n1381), .CO(n1511), .S(n1537) );
CMPR32X4TS U2254 ( .A(FPMULT_Op_MX[5]), .B(n977), .C(n1384), .CO(n1409), .S(
n1550) );
XNOR2X1TS U2255 ( .A(n1424), .B(FPMULT_Op_MX[11]), .Y(n1385) );
BUFX4TS U2256 ( .A(n1385), .Y(n1473) );
CMPR32X4TS U2257 ( .A(n978), .B(n971), .C(n1386), .CO(n1387), .S(n1582) );
CMPR32X2TS U2258 ( .A(FPMULT_Op_MX[10]), .B(FPMULT_Op_MX[22]), .C(n1387),
.CO(n1424), .S(n1389) );
INVX2TS U2259 ( .A(n1389), .Y(n1474) );
AOI22X1TS U2260 ( .A0(n1582), .A1(n1474), .B0(n1389), .B1(n1579), .Y(n1388)
);
BUFX4TS U2261 ( .A(n1388), .Y(n1498) );
OAI221X4TS U2262 ( .A0(n1389), .A1(n1473), .B0(n1474), .B1(n1468), .C0(n1498), .Y(n1466) );
OAI32X1TS U2263 ( .A0(n1468), .A1(DP_OP_454J321_123_2743_n367), .A2(n1498),
.B0(n1466), .B1(n1468), .Y(n1512) );
CMPR32X2TS U2264 ( .A(DP_OP_454J321_123_2743_n40), .B(
DP_OP_454J321_123_2743_n44), .C(n1390), .CO(n1469), .S(
FPMULT_Sgf_operation_EVEN1_middle_N21) );
CMPR32X2TS U2265 ( .A(DP_OP_454J321_123_2743_n49), .B(
DP_OP_454J321_123_2743_n45), .C(n1391), .CO(n1390), .S(
FPMULT_Sgf_operation_EVEN1_middle_N20) );
CMPR32X2TS U2266 ( .A(DP_OP_454J321_123_2743_n50), .B(
DP_OP_454J321_123_2743_n56), .C(n1392), .CO(n1391), .S(
FPMULT_Sgf_operation_EVEN1_middle_N19) );
CMPR32X2TS U2267 ( .A(DP_OP_454J321_123_2743_n57), .B(
DP_OP_454J321_123_2743_n62), .C(n1393), .CO(n1392), .S(
FPMULT_Sgf_operation_EVEN1_middle_N18) );
CMPR32X2TS U2268 ( .A(DP_OP_454J321_123_2743_n63), .B(
DP_OP_454J321_123_2743_n70), .C(n1394), .CO(n1393), .S(
FPMULT_Sgf_operation_EVEN1_middle_N17) );
CMPR32X2TS U2269 ( .A(DP_OP_454J321_123_2743_n71), .B(
DP_OP_454J321_123_2743_n78), .C(n1395), .CO(n1394), .S(
FPMULT_Sgf_operation_EVEN1_middle_N16) );
CMPR32X2TS U2270 ( .A(DP_OP_454J321_123_2743_n79), .B(
DP_OP_454J321_123_2743_n88), .C(n1396), .CO(n1395), .S(
FPMULT_Sgf_operation_EVEN1_middle_N15) );
CMPR32X2TS U2271 ( .A(DP_OP_454J321_123_2743_n89), .B(
DP_OP_454J321_123_2743_n97), .C(n1397), .CO(n1396), .S(
FPMULT_Sgf_operation_EVEN1_middle_N14) );
CMPR32X2TS U2272 ( .A(DP_OP_454J321_123_2743_n98), .B(
DP_OP_454J321_123_2743_n105), .C(n1398), .CO(n1397), .S(
FPMULT_Sgf_operation_EVEN1_middle_N13) );
CMPR32X2TS U2273 ( .A(DP_OP_454J321_123_2743_n106), .B(
DP_OP_454J321_123_2743_n113), .C(n1399), .CO(n1398), .S(
FPMULT_Sgf_operation_EVEN1_middle_N12) );
CMPR32X2TS U2274 ( .A(DP_OP_454J321_123_2743_n122), .B(
DP_OP_454J321_123_2743_n127), .C(n1400), .CO(n1513), .S(
FPMULT_Sgf_operation_EVEN1_middle_N10) );
CMPR32X2TS U2275 ( .A(DP_OP_454J321_123_2743_n128), .B(
DP_OP_454J321_123_2743_n134), .C(n1401), .CO(n1400), .S(
FPMULT_Sgf_operation_EVEN1_middle_N9) );
CMPR32X2TS U2276 ( .A(DP_OP_454J321_123_2743_n135), .B(
DP_OP_454J321_123_2743_n139), .C(n1402), .CO(n1401), .S(
FPMULT_Sgf_operation_EVEN1_middle_N8) );
CMPR32X2TS U2277 ( .A(n1403), .B(DP_OP_454J321_123_2743_n144), .C(
DP_OP_454J321_123_2743_n140), .CO(n1402), .S(
FPMULT_Sgf_operation_EVEN1_middle_N7) );
CMPR32X2TS U2278 ( .A(n1406), .B(n1405), .C(n1404), .CO(n1535), .S(
FPMULT_Sgf_operation_EVEN1_middle_N2) );
NOR2X4TS U2279 ( .A(n1004), .B(n1412), .Y(n1504) );
CMPR32X4TS U2280 ( .A(FPMULT_Op_MX[7]), .B(FPMULT_Op_MX[19]), .C(n1408),
.CO(n1413), .S(n1575) );
INVX2TS U2281 ( .A(n1504), .Y(n1503) );
AOI22X1TS U2282 ( .A0(n1504), .A1(n1575), .B0(n1576), .B1(n1503), .Y(n1446)
);
INVX2TS U2283 ( .A(n1411), .Y(n1540) );
AOI22X1TS U2284 ( .A0(n1411), .A1(n1551), .B0(n1550), .B1(n1540), .Y(n1410)
);
OAI221X4TS U2285 ( .A0(n1411), .A1(n1575), .B0(n1540), .B1(n1576), .C0(n1598), .Y(n1596) );
OAI22X1TS U2286 ( .A0(n1446), .A1(n1596), .B0(n1576), .B1(n1598), .Y(n1545)
);
INVX2TS U2287 ( .A(n1545), .Y(n1418) );
CLKXOR2X4TS U2288 ( .A(n1004), .B(n1412), .Y(n1471) );
AOI22X1TS U2289 ( .A0(n1582), .A1(n1471), .B0(n1489), .B1(n1579), .Y(n1541)
);
INVX2TS U2290 ( .A(n1415), .Y(n1506) );
AOI22X1TS U2291 ( .A0(n1415), .A1(n1576), .B0(n1575), .B1(n1506), .Y(n1414)
);
OAI221X4TS U2292 ( .A0(n1415), .A1(n1582), .B0(n1506), .B1(n1579), .C0(n1602), .Y(n1600) );
CMPR32X2TS U2293 ( .A(FPMULT_Op_MY[10]), .B(n1002), .C(n1416), .CO(n1412),
.S(n1494) );
INVX2TS U2294 ( .A(n1494), .Y(n1492) );
AOI22X1TS U2295 ( .A0(n1582), .A1(n1492), .B0(n1494), .B1(n1579), .Y(n1440)
);
OAI22X1TS U2296 ( .A0(n1541), .A1(n1602), .B0(n1600), .B1(n1440), .Y(n1417)
);
CMPR32X2TS U2297 ( .A(n1418), .B(DP_OP_454J321_123_2743_n58), .C(n1417),
.CO(DP_OP_454J321_123_2743_n51), .S(DP_OP_454J321_123_2743_n52) );
AOI22X1TS U2298 ( .A0(n1582), .A1(n1574), .B0(n1577), .B1(n1579), .Y(n1501)
);
AOI22X1TS U2299 ( .A0(n1582), .A1(n1562), .B0(n1563), .B1(n1579), .Y(n1583)
);
OAI22X1TS U2300 ( .A0(n1602), .A1(n1501), .B0(n1600), .B1(n1583), .Y(n1422)
);
CMPR32X2TS U2301 ( .A(n1423), .B(n1493), .C(n1422), .CO(
DP_OP_454J321_123_2743_n75), .S(DP_OP_454J321_123_2743_n76) );
CMPR32X2TS U2302 ( .A(FPMULT_Op_MY[9]), .B(n1000), .C(n1426), .CO(n1416),
.S(n1497) );
AOI22X1TS U2303 ( .A0(n1500), .A1(n1490), .B0(n1492), .B1(n1425), .Y(
DP_OP_454J321_123_2743_n162) );
AOI22X1TS U2304 ( .A0(n1500), .A1(n1574), .B0(n1490), .B1(n1425), .Y(
DP_OP_454J321_123_2743_n163) );
AOI22X1TS U2305 ( .A0(n1500), .A1(n1562), .B0(n1574), .B1(n1425), .Y(
DP_OP_454J321_123_2743_n164) );
AOI22X1TS U2306 ( .A0(n1500), .A1(n1581), .B0(n1562), .B1(n1425), .Y(
DP_OP_454J321_123_2743_n165) );
AOI22X1TS U2307 ( .A0(n1500), .A1(n1552), .B0(n1581), .B1(n1425), .Y(
DP_OP_454J321_123_2743_n166) );
AOI22X1TS U2308 ( .A0(n1500), .A1(n1518), .B0(n1552), .B1(n1425), .Y(
DP_OP_454J321_123_2743_n167) );
AOI22X1TS U2309 ( .A0(n1500), .A1(n1520), .B0(n1518), .B1(n1425), .Y(
DP_OP_454J321_123_2743_n168) );
AOI22X1TS U2310 ( .A0(n1500), .A1(n1456), .B0(n1520), .B1(n1425), .Y(
DP_OP_454J321_123_2743_n169) );
AOI22X1TS U2311 ( .A0(n1500), .A1(n1449), .B0(n1456), .B1(n1425), .Y(
DP_OP_454J321_123_2743_n170) );
AOI22X1TS U2312 ( .A0(n1500), .A1(n1499), .B0(n1449), .B1(n1425), .Y(
DP_OP_454J321_123_2743_n171) );
AOI22X1TS U2313 ( .A0(n1468), .A1(n1503), .B0(n1504), .B1(n1473), .Y(n1467)
);
AOI22X1TS U2314 ( .A0(n1468), .A1(n1489), .B0(n1471), .B1(n1473), .Y(n1428)
);
OAI22X1TS U2315 ( .A0(n1498), .A1(n1467), .B0(n1466), .B1(n1428), .Y(
DP_OP_454J321_123_2743_n175) );
AOI22X1TS U2316 ( .A0(n1468), .A1(n1494), .B0(n1492), .B1(n1473), .Y(n1429)
);
OAI22X1TS U2317 ( .A0(n1429), .A1(n1466), .B0(n1498), .B1(n1428), .Y(
DP_OP_454J321_123_2743_n176) );
AOI22X1TS U2318 ( .A0(n1468), .A1(n1497), .B0(n1490), .B1(n1473), .Y(n1430)
);
OAI22X1TS U2319 ( .A0(n1429), .A1(n1498), .B0(n1430), .B1(n1466), .Y(
DP_OP_454J321_123_2743_n177) );
AOI22X1TS U2320 ( .A0(n1468), .A1(n1577), .B0(n1574), .B1(n1473), .Y(n1431)
);
OAI22X1TS U2321 ( .A0(n1430), .A1(n1498), .B0(n1431), .B1(n1466), .Y(
DP_OP_454J321_123_2743_n178) );
AOI22X1TS U2322 ( .A0(n1468), .A1(n1563), .B0(n1562), .B1(n1473), .Y(n1432)
);
OAI22X1TS U2323 ( .A0(n1431), .A1(n1498), .B0(n1432), .B1(n1466), .Y(
DP_OP_454J321_123_2743_n179) );
AOI22X1TS U2324 ( .A0(n1468), .A1(n1580), .B0(n1581), .B1(n1473), .Y(n1433)
);
OAI22X1TS U2325 ( .A0(n1432), .A1(n1498), .B0(n1433), .B1(n1466), .Y(
DP_OP_454J321_123_2743_n180) );
AOI22X1TS U2326 ( .A0(n1468), .A1(n1553), .B0(n1552), .B1(n1473), .Y(n1434)
);
OAI22X1TS U2327 ( .A0(n1433), .A1(n1498), .B0(n1434), .B1(n1466), .Y(
DP_OP_454J321_123_2743_n181) );
AOI22X1TS U2328 ( .A0(n1468), .A1(n1519), .B0(n1518), .B1(n1473), .Y(n1435)
);
OAI22X1TS U2329 ( .A0(n1434), .A1(n1498), .B0(n1435), .B1(n1466), .Y(
DP_OP_454J321_123_2743_n182) );
AOI22X1TS U2330 ( .A0(n1468), .A1(n1521), .B0(n1520), .B1(n1473), .Y(n1436)
);
OAI22X1TS U2331 ( .A0(n1435), .A1(n1498), .B0(n1436), .B1(n1466), .Y(
DP_OP_454J321_123_2743_n183) );
AOI22X1TS U2332 ( .A0(n1468), .A1(n1457), .B0(n1456), .B1(n1473), .Y(n1437)
);
OAI22X1TS U2333 ( .A0(n1436), .A1(n1498), .B0(n1437), .B1(n1466), .Y(
DP_OP_454J321_123_2743_n184) );
AOI22X1TS U2334 ( .A0(n1468), .A1(n1450), .B0(n1449), .B1(n1473), .Y(n1439)
);
OAI22X1TS U2335 ( .A0(n1437), .A1(n1498), .B0(n1439), .B1(n1466), .Y(
DP_OP_454J321_123_2743_n185) );
AOI22X1TS U2336 ( .A0(n1468), .A1(DP_OP_454J321_123_2743_n367), .B0(n1499),
.B1(n1473), .Y(n1438) );
OAI22X1TS U2337 ( .A0(n1439), .A1(n1498), .B0(n1466), .B1(n1438), .Y(
DP_OP_454J321_123_2743_n186) );
AOI22X1TS U2338 ( .A0(n1582), .A1(n1490), .B0(n1497), .B1(n1579), .Y(n1502)
);
OAI22X1TS U2339 ( .A0(n1602), .A1(n1440), .B0(n1600), .B1(n1502), .Y(
DP_OP_454J321_123_2743_n191) );
AOI22X1TS U2340 ( .A0(n1582), .A1(n1552), .B0(n1553), .B1(n1579), .Y(n1599)
);
AOI22X1TS U2341 ( .A0(n1582), .A1(n1518), .B0(n1519), .B1(n1579), .Y(n1441)
);
OAI22X1TS U2342 ( .A0(n1602), .A1(n1599), .B0(n1600), .B1(n1441), .Y(
DP_OP_454J321_123_2743_n195) );
AOI22X1TS U2343 ( .A0(n1582), .A1(n1520), .B0(n1521), .B1(n1579), .Y(n1442)
);
OAI22X1TS U2344 ( .A0(n1602), .A1(n1441), .B0(n1600), .B1(n1442), .Y(
DP_OP_454J321_123_2743_n196) );
AOI22X1TS U2345 ( .A0(n1582), .A1(n1456), .B0(n1457), .B1(n1579), .Y(n1443)
);
OAI22X1TS U2346 ( .A0(n1602), .A1(n1442), .B0(n1600), .B1(n1443), .Y(
DP_OP_454J321_123_2743_n197) );
AOI22X1TS U2347 ( .A0(n1582), .A1(n1449), .B0(n1450), .B1(n1579), .Y(n1445)
);
OAI22X1TS U2348 ( .A0(n1602), .A1(n1443), .B0(n1600), .B1(n1445), .Y(
DP_OP_454J321_123_2743_n198) );
AOI22X1TS U2349 ( .A0(DP_OP_454J321_123_2743_n367), .A1(n1579), .B0(n1582),
.B1(n1499), .Y(n1444) );
OAI22X1TS U2350 ( .A0(n1602), .A1(n1445), .B0(n1600), .B1(n1444), .Y(
DP_OP_454J321_123_2743_n199) );
AOI22X1TS U2351 ( .A0(n1471), .A1(n1575), .B0(n1576), .B1(n1489), .Y(n1447)
);
OAI22X1TS U2352 ( .A0(n1446), .A1(n1598), .B0(n1447), .B1(n1596), .Y(
DP_OP_454J321_123_2743_n202) );
AOI22X1TS U2353 ( .A0(n1494), .A1(n1576), .B0(n1575), .B1(n1492), .Y(n1448)
);
OAI22X1TS U2354 ( .A0(n1447), .A1(n1598), .B0(n1596), .B1(n1448), .Y(
DP_OP_454J321_123_2743_n203) );
AOI22X1TS U2355 ( .A0(n1497), .A1(n1576), .B0(n1575), .B1(n1490), .Y(n1578)
);
OAI22X1TS U2356 ( .A0(n1598), .A1(n1448), .B0(n1596), .B1(n1578), .Y(
DP_OP_454J321_123_2743_n204) );
AOI22X1TS U2357 ( .A0(n1519), .A1(n1576), .B0(n1575), .B1(n1518), .Y(n1556)
);
AOI22X1TS U2358 ( .A0(n1521), .A1(n1576), .B0(n1575), .B1(n1520), .Y(n1515)
);
OAI22X1TS U2359 ( .A0(n1598), .A1(n1556), .B0(n1596), .B1(n1515), .Y(
DP_OP_454J321_123_2743_n210) );
AOI22X1TS U2360 ( .A0(n1457), .A1(n1576), .B0(n1575), .B1(n1456), .Y(n1514)
);
AOI22X1TS U2361 ( .A0(n1450), .A1(n1576), .B0(n1575), .B1(n1449), .Y(n1452)
);
OAI22X1TS U2362 ( .A0(n1598), .A1(n1514), .B0(n1596), .B1(n1452), .Y(
DP_OP_454J321_123_2743_n212) );
AOI22X1TS U2363 ( .A0(DP_OP_454J321_123_2743_n367), .A1(n1576), .B0(n1575),
.B1(n1499), .Y(n1451) );
OAI22X1TS U2364 ( .A0(n1598), .A1(n1452), .B0(n1596), .B1(n1451), .Y(
DP_OP_454J321_123_2743_n213) );
AOI22X1TS U2365 ( .A0(n1504), .A1(n1550), .B0(n1551), .B1(n1503), .Y(n1453)
);
OAI22X1TS U2366 ( .A0(n1453), .A1(n1559), .B0(n1551), .B1(n1561), .Y(
DP_OP_454J321_123_2743_n216) );
AOI22X1TS U2367 ( .A0(n1471), .A1(n1550), .B0(n1551), .B1(n1489), .Y(n1454)
);
OAI22X1TS U2368 ( .A0(n1453), .A1(n1561), .B0(n1454), .B1(n1559), .Y(
DP_OP_454J321_123_2743_n217) );
AOI22X1TS U2369 ( .A0(n1494), .A1(n1551), .B0(n1550), .B1(n1492), .Y(n1455)
);
OAI22X1TS U2370 ( .A0(n1454), .A1(n1561), .B0(n1559), .B1(n1455), .Y(
DP_OP_454J321_123_2743_n218) );
AOI22X1TS U2371 ( .A0(n1497), .A1(n1551), .B0(n1550), .B1(n1490), .Y(n1560)
);
OAI22X1TS U2372 ( .A0(n1561), .A1(n1455), .B0(n1559), .B1(n1560), .Y(
DP_OP_454J321_123_2743_n219) );
AOI22X1TS U2373 ( .A0(n1580), .A1(n1551), .B0(n1550), .B1(n1581), .Y(n1554)
);
AOI22X1TS U2374 ( .A0(n1553), .A1(n1551), .B0(n1550), .B1(n1552), .Y(n1527)
);
OAI22X1TS U2375 ( .A0(n1561), .A1(n1554), .B0(n1559), .B1(n1527), .Y(
DP_OP_454J321_123_2743_n223) );
AOI22X1TS U2376 ( .A0(n1457), .A1(n1551), .B0(n1550), .B1(n1456), .Y(n1524)
);
OAI22X1TS U2377 ( .A0(n1561), .A1(n1524), .B0(n1559), .B1(n1458), .Y(
DP_OP_454J321_123_2743_n227) );
AOI22X1TS U2378 ( .A0(n1504), .A1(n1516), .B0(n1517), .B1(n1503), .Y(n1459)
);
OAI22X1TS U2379 ( .A0(n1459), .A1(n1366), .B0(n1517), .B1(n1530), .Y(
DP_OP_454J321_123_2743_n231) );
AOI22X1TS U2380 ( .A0(n1471), .A1(n1516), .B0(n1517), .B1(n1489), .Y(n1460)
);
OAI22X1TS U2381 ( .A0(n1459), .A1(n1530), .B0(n1460), .B1(n1366), .Y(
DP_OP_454J321_123_2743_n232) );
AOI22X1TS U2382 ( .A0(n1494), .A1(n1517), .B0(n1516), .B1(n1492), .Y(n1461)
);
OAI22X1TS U2383 ( .A0(n1460), .A1(n1530), .B0(n1366), .B1(n1461), .Y(
DP_OP_454J321_123_2743_n233) );
AOI22X1TS U2384 ( .A0(n1497), .A1(n1517), .B0(n1516), .B1(n1490), .Y(n1462)
);
OAI22X1TS U2385 ( .A0(n1530), .A1(n1461), .B0(n1366), .B1(n1462), .Y(
DP_OP_454J321_123_2743_n234) );
AOI22X1TS U2386 ( .A0(n1577), .A1(n1517), .B0(n1516), .B1(n1574), .Y(n1463)
);
OAI22X1TS U2387 ( .A0(n1530), .A1(n1462), .B0(n1366), .B1(n1463), .Y(
DP_OP_454J321_123_2743_n235) );
AOI22X1TS U2388 ( .A0(n1563), .A1(n1517), .B0(n1516), .B1(n1562), .Y(n1529)
);
OAI22X1TS U2389 ( .A0(n1530), .A1(n1463), .B0(n1366), .B1(n1529), .Y(
DP_OP_454J321_123_2743_n236) );
AOI22X1TS U2390 ( .A0(n1519), .A1(n1517), .B0(n1516), .B1(n1518), .Y(n1522)
);
OAI22X1TS U2391 ( .A0(n1530), .A1(n1522), .B0(n1366), .B1(n1464), .Y(
DP_OP_454J321_123_2743_n240) );
AOI21X1TS U2392 ( .A0(n1503), .A1(n1495), .B0(n1362), .Y(
DP_OP_454J321_123_2743_n245) );
AOI22X1TS U2393 ( .A0(n1471), .A1(n1604), .B0(n1362), .B1(n1489), .Y(n1465)
);
OAI32X1TS U2394 ( .A0(DP_OP_454J321_123_2743_n453), .A1(n1494), .A2(n1362),
.B0(n1465), .B1(n1495), .Y(DP_OP_454J321_123_2743_n247) );
OAI22X1TS U2395 ( .A0(n1425), .A1(n1494), .B0(n1489), .B1(n1500), .Y(n1472)
);
OAI22X1TS U2396 ( .A0(n1468), .A1(n1498), .B0(n1467), .B1(n1466), .Y(n1470)
);
CMPR32X2TS U2397 ( .A(DP_OP_454J321_123_2743_n37), .B(
DP_OP_454J321_123_2743_n39), .C(n1469), .CO(n1475), .S(
FPMULT_Sgf_operation_EVEN1_middle_N22) );
CMPR32X2TS U2398 ( .A(n1472), .B(n1470), .C(DP_OP_454J321_123_2743_n35),
.CO(n1573), .S(n1476) );
AOI22X1TS U2399 ( .A0(n1500), .A1(n1471), .B0(n1504), .B1(n1425), .Y(n1479)
);
INVX2TS U2400 ( .A(n1472), .Y(n1478) );
OAI21XLTS U2401 ( .A0(n1579), .A1(n1474), .B0(n1473), .Y(n1477) );
CMPR32X2TS U2402 ( .A(n1476), .B(DP_OP_454J321_123_2743_n36), .C(n1475),
.CO(n1571), .S(FPMULT_Sgf_operation_EVEN1_middle_N23) );
CMPR32X2TS U2403 ( .A(n1479), .B(n1478), .C(n1477), .CO(n1482), .S(n1572) );
OAI31X1TS U2404 ( .A0(n1504), .A1(n1482), .A2(n1425), .B0(n1480), .Y(n1483)
);
XNOR2X1TS U2405 ( .A(n1484), .B(n1483), .Y(
FPMULT_Sgf_operation_EVEN1_middle_N25) );
AOI22X1TS U2406 ( .A0(n1580), .A1(n1493), .B0(n1604), .B1(n1581), .Y(n1485)
);
OAI32X1TS U2407 ( .A0(DP_OP_454J321_123_2743_n453), .A1(n1553), .A2(n1362),
.B0(n1485), .B1(n1495), .Y(DP_OP_454J321_123_2743_n252) );
AOI22X1TS U2408 ( .A0(n1563), .A1(n1493), .B0(n1604), .B1(n1562), .Y(n1486)
);
OAI32X1TS U2409 ( .A0(DP_OP_454J321_123_2743_n453), .A1(n1580), .A2(n1493),
.B0(n1486), .B1(n1495), .Y(DP_OP_454J321_123_2743_n251) );
AOI22X1TS U2410 ( .A0(n1577), .A1(n1493), .B0(n1604), .B1(n1574), .Y(n1487)
);
OAI32X1TS U2411 ( .A0(DP_OP_454J321_123_2743_n453), .A1(n1563), .A2(n1362),
.B0(n1487), .B1(n1495), .Y(DP_OP_454J321_123_2743_n250) );
AOI22X1TS U2412 ( .A0(n1504), .A1(n1604), .B0(n1362), .B1(n1503), .Y(n1488)
);
OAI32X1TS U2413 ( .A0(DP_OP_454J321_123_2743_n453), .A1(n1489), .A2(n1362),
.B0(n1488), .B1(n1495), .Y(DP_OP_454J321_123_2743_n246) );
AOI22X1TS U2414 ( .A0(n1497), .A1(n1493), .B0(n1604), .B1(n1490), .Y(n1491)
);
OAI32X1TS U2415 ( .A0(DP_OP_454J321_123_2743_n453), .A1(n1577), .A2(n1362),
.B0(n1491), .B1(n1495), .Y(DP_OP_454J321_123_2743_n249) );
AOI22X1TS U2416 ( .A0(n1494), .A1(n1493), .B0(n1604), .B1(n1492), .Y(n1496)
);
OAI32X1TS U2417 ( .A0(DP_OP_454J321_123_2743_n453), .A1(n1497), .A2(n1362),
.B0(n1496), .B1(n1495), .Y(DP_OP_454J321_123_2743_n248) );
NOR2X1TS U2418 ( .A(n1499), .B(n1498), .Y(DP_OP_454J321_123_2743_n187) );
NOR2X1TS U2419 ( .A(n1500), .B(n1499), .Y(DP_OP_454J321_123_2743_n172) );
OAI22X1TS U2420 ( .A0(n1602), .A1(n1502), .B0(n1600), .B1(n1501), .Y(
DP_OP_454J321_123_2743_n67) );
INVX2TS U2421 ( .A(DP_OP_454J321_123_2743_n67), .Y(
DP_OP_454J321_123_2743_n68) );
AOI22X1TS U2422 ( .A0(n1582), .A1(n1504), .B0(n1503), .B1(n1579), .Y(n1542)
);
OAI22X1TS U2423 ( .A0(n1542), .A1(n1600), .B0(n1579), .B1(n1602), .Y(
DP_OP_454J321_123_2743_n41) );
INVX2TS U2424 ( .A(DP_OP_454J321_123_2743_n41), .Y(
DP_OP_454J321_123_2743_n42) );
OAI21X1TS U2425 ( .A0(n1517), .A1(n1505), .B0(n1550), .Y(
DP_OP_454J321_123_2743_n215) );
OAI21X1TS U2426 ( .A0(n1506), .A1(n1576), .B0(n1582), .Y(
DP_OP_454J321_123_2743_n188) );
CMPR32X2TS U2427 ( .A(n1509), .B(n1508), .C(n1507), .CO(n1539), .S(
FPMULT_Sgf_operation_EVEN1_middle_N4) );
CMPR32X2TS U2428 ( .A(DP_OP_454J321_123_2743_n145), .B(n1511), .C(n1510),
.CO(n1403), .S(FPMULT_Sgf_operation_EVEN1_middle_N6) );
CMPR32X2TS U2429 ( .A(n1513), .B(n1512), .C(DP_OP_454J321_123_2743_n114),
.CO(n1399), .S(FPMULT_Sgf_operation_EVEN1_middle_N11) );
OAI22X1TS U2430 ( .A0(n1598), .A1(n1515), .B0(n1596), .B1(n1514), .Y(n1533)
);
AOI22X1TS U2431 ( .A0(n1580), .A1(n1517), .B0(n1516), .B1(n1581), .Y(n1528)
);
AOI22X1TS U2432 ( .A0(n1553), .A1(n1517), .B0(n1516), .B1(n1552), .Y(n1523)
);
OAI22X1TS U2433 ( .A0(n1530), .A1(n1528), .B0(n1366), .B1(n1523), .Y(n1588)
);
AOI22X1TS U2434 ( .A0(n1519), .A1(n1551), .B0(n1550), .B1(n1518), .Y(n1526)
);
AOI22X1TS U2435 ( .A0(n1521), .A1(n1551), .B0(n1550), .B1(n1520), .Y(n1525)
);
OAI22X1TS U2436 ( .A0(n1561), .A1(n1526), .B0(n1559), .B1(n1525), .Y(n1587)
);
OAI22X1TS U2437 ( .A0(n1530), .A1(n1523), .B0(n1366), .B1(n1522), .Y(n1592)
);
OAI22X1TS U2438 ( .A0(n1561), .A1(n1525), .B0(n1559), .B1(n1524), .Y(n1591)
);
OAI22X1TS U2439 ( .A0(n1561), .A1(n1527), .B0(n1559), .B1(n1526), .Y(n1590)
);
OAI22X1TS U2440 ( .A0(n1530), .A1(n1529), .B0(n1366), .B1(n1528), .Y(n1589)
);
CMPR32X2TS U2441 ( .A(n1533), .B(n1532), .C(n1531), .CO(
DP_OP_454J321_123_2743_n129), .S(DP_OP_454J321_123_2743_n130) );
OAI32X1TS U2442 ( .A0(n1576), .A1(DP_OP_454J321_123_2743_n367), .A2(n1598),
.B0(n1596), .B1(n1576), .Y(DP_OP_454J321_123_2743_n156) );
OAI32X1TS U2443 ( .A0(n1579), .A1(DP_OP_454J321_123_2743_n367), .A2(n1602),
.B0(n1600), .B1(n1579), .Y(DP_OP_454J321_123_2743_n155) );
CMPR32X2TS U2444 ( .A(n1536), .B(n1535), .C(n1534), .CO(n1507), .S(
FPMULT_Sgf_operation_EVEN1_middle_N3) );
CMPR32X2TS U2445 ( .A(n1539), .B(n1538), .C(n1537), .CO(n1510), .S(
FPMULT_Sgf_operation_EVEN1_middle_N5) );
OAI21X1TS U2446 ( .A0(n1540), .A1(n1551), .B0(n1575), .Y(n1544) );
OAI22X1TS U2447 ( .A0(n1542), .A1(n1602), .B0(n1541), .B1(n1600), .Y(n1543)
);
CMPR32X2TS U2448 ( .A(n1545), .B(n1544), .C(n1543), .CO(
DP_OP_454J321_123_2743_n46), .S(DP_OP_454J321_123_2743_n47) );
ADDHXLTS U2449 ( .A(n1547), .B(n1546), .CO(n1404), .S(
FPMULT_Sgf_operation_EVEN1_middle_N1) );
ADDHXLTS U2450 ( .A(n1549), .B(n1548), .CO(DP_OP_454J321_123_2743_n148), .S(
n1538) );
AOI22X1TS U2451 ( .A0(n1577), .A1(n1551), .B0(n1550), .B1(n1574), .Y(n1558)
);
AOI22X1TS U2452 ( .A0(n1563), .A1(n1551), .B0(n1550), .B1(n1562), .Y(n1555)
);
OAI22X1TS U2453 ( .A0(n1561), .A1(n1558), .B0(n1559), .B1(n1555), .Y(n1567)
);
AOI22X1TS U2454 ( .A0(n1580), .A1(n1576), .B0(n1575), .B1(n1581), .Y(n1564)
);
AOI22X1TS U2455 ( .A0(n1553), .A1(n1576), .B0(n1575), .B1(n1552), .Y(n1557)
);
OAI22X1TS U2456 ( .A0(n1598), .A1(n1564), .B0(n1596), .B1(n1557), .Y(n1566)
);
OAI22X1TS U2457 ( .A0(n1561), .A1(n1555), .B0(n1559), .B1(n1554), .Y(n1594)
);
OAI22X1TS U2458 ( .A0(n1598), .A1(n1557), .B0(n1596), .B1(n1556), .Y(n1593)
);
OAI22X1TS U2459 ( .A0(n1561), .A1(n1560), .B0(n1559), .B1(n1558), .Y(n1570)
);
AOI22X1TS U2460 ( .A0(n1563), .A1(n1576), .B0(n1575), .B1(n1562), .Y(n1595)
);
OAI22X1TS U2461 ( .A0(n1598), .A1(n1595), .B0(n1596), .B1(n1564), .Y(n1569)
);
CMPR32X2TS U2462 ( .A(n1567), .B(n1566), .C(n1565), .CO(n1568), .S(
DP_OP_454J321_123_2743_n111) );
CMPR32X2TS U2463 ( .A(n1570), .B(n1569), .C(n1568), .CO(
DP_OP_454J321_123_2743_n102), .S(DP_OP_454J321_123_2743_n103) );
CMPR32X2TS U2464 ( .A(n1573), .B(n1572), .C(n1571), .CO(n1484), .S(
FPMULT_Sgf_operation_EVEN1_middle_N24) );
AOI22X1TS U2465 ( .A0(n1577), .A1(n1576), .B0(n1575), .B1(n1574), .Y(n1597)
);
OAI22X1TS U2466 ( .A0(n1598), .A1(n1578), .B0(n1596), .B1(n1597), .Y(n1585)
);
AOI22X1TS U2467 ( .A0(n1582), .A1(n1581), .B0(n1580), .B1(n1579), .Y(n1601)
);
OAI22X1TS U2468 ( .A0(n1602), .A1(n1583), .B0(n1600), .B1(n1601), .Y(n1584)
);
CMPR32X2TS U2469 ( .A(n1585), .B(n1604), .C(n1584), .CO(
DP_OP_454J321_123_2743_n83), .S(DP_OP_454J321_123_2743_n84) );
CMPR32X2TS U2470 ( .A(n1588), .B(n1587), .C(n1586), .CO(n1532), .S(
DP_OP_454J321_123_2743_n137) );
ADDHXLTS U2471 ( .A(n1590), .B(n1589), .CO(DP_OP_454J321_123_2743_n131), .S(
n1531) );
ADDHXLTS U2472 ( .A(n1594), .B(n1593), .CO(n1565), .S(
DP_OP_454J321_123_2743_n119) );
OAI22X1TS U2473 ( .A0(n1598), .A1(n1597), .B0(n1596), .B1(n1595), .Y(n1605)
);
OAI22X1TS U2474 ( .A0(n1602), .A1(n1601), .B0(n1600), .B1(n1599), .Y(n1603)
);
CMPR32X2TS U2475 ( .A(n1605), .B(n1604), .C(n1603), .CO(
DP_OP_454J321_123_2743_n93), .S(DP_OP_454J321_123_2743_n94) );
NAND2X1TS U2476 ( .A(n2009), .B(n2006), .Y(n1616) );
NOR2X1TS U2477 ( .A(FPADDSUB_Raw_mant_NRM_SWR[18]), .B(n1616), .Y(n2018) );
NAND2X1TS U2478 ( .A(n2018), .B(n2015), .Y(n1613) );
NOR2X1TS U2479 ( .A(FPADDSUB_Raw_mant_NRM_SWR[14]), .B(n1613), .Y(n1615) );
NAND2X1TS U2480 ( .A(n2022), .B(n1615), .Y(n2024) );
NAND2X1TS U2481 ( .A(n2025), .B(n1606), .Y(n1607) );
NAND2X1TS U2482 ( .A(n2028), .B(n2636), .Y(n2014) );
OA21XLTS U2483 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[3]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[2]), .B0(n2011), .Y(n1609) );
INVX2TS U2484 ( .A(n1607), .Y(n1608) );
OAI31X1TS U2485 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(n1609), .A2(
FPADDSUB_Raw_mant_NRM_SWR[6]), .B0(n1608), .Y(n2030) );
NOR2XLTS U2486 ( .A(FPADDSUB_Raw_mant_NRM_SWR[20]), .B(
FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n1612) );
NOR2X1TS U2487 ( .A(FPADDSUB_Raw_mant_NRM_SWR[24]), .B(
FPADDSUB_Raw_mant_NRM_SWR[25]), .Y(n1611) );
AOI32X1TS U2488 ( .A0(n1612), .A1(n1611), .A2(FPADDSUB_Raw_mant_NRM_SWR[19]),
.B0(n1610), .B1(n1611), .Y(n1619) );
INVX2TS U2489 ( .A(n1616), .Y(n1636) );
NOR2XLTS U2490 ( .A(FPADDSUB_Raw_mant_NRM_SWR[16]), .B(
FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n1614) );
AOI31XLTS U2491 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n1636), .A2(n1614),
.B0(n2016), .Y(n1618) );
INVX2TS U2492 ( .A(n1615), .Y(n2021) );
NOR2X1TS U2493 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(n2021), .Y(n1635) );
OAI21X1TS U2494 ( .A0(n1616), .A1(n2645), .B0(n2019), .Y(n1634) );
NAND4X1TS U2495 ( .A(n2030), .B(n1619), .C(n1618), .D(n1617), .Y(
FPADDSUB_LZD_raw_out_EWR[1]) );
INVX2TS U2496 ( .A(n1028), .Y(n2224) );
NOR2X1TS U2497 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n2224), .Y(n1767) );
NAND2X2TS U2498 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM), .Y(n2037) );
NAND2X1TS U2499 ( .A(n2669), .B(n2224), .Y(n1794) );
INVX2TS U2500 ( .A(n1794), .Y(n1680) );
NAND2X1TS U2501 ( .A(n1680), .B(n1790), .Y(n1796) );
AOI2BB2XLTS U2502 ( .B0(n956), .B1(FPMULT_FSM_exp_operation_A_S), .A0N(
FPMULT_P_Sgf[47]), .A1N(n1796), .Y(n1620) );
OAI21XLTS U2503 ( .A0(n2224), .A1(FPMULT_FS_Module_state_reg[2]), .B0(n1620),
.Y(FPMULT_FS_Module_state_next[0]) );
OR4X2TS U2504 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n1621) );
INVX2TS U2505 ( .A(Data_2[22]), .Y(n1624) );
BUFX4TS U2506 ( .A(n960), .Y(n2424) );
NOR3X1TS U2507 ( .A(FPSENCOS_cont_var_out[1]), .B(n2424), .C(n2649), .Y(
n2474) );
NAND2X1TS U2508 ( .A(FPSENCOS_cont_var_out[1]), .B(n2649), .Y(n1622) );
AOI22X1TS U2509 ( .A0(n2501), .A1(FPSENCOS_d_ff3_sh_y_out[22]), .B0(n2499),
.B1(FPSENCOS_d_ff3_sh_x_out[22]), .Y(n1623) );
NAND2X1TS U2510 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.Y(n2399) );
BUFX4TS U2511 ( .A(n1779), .Y(n2455) );
NAND2X1TS U2512 ( .A(n2455), .B(FPSENCOS_d_ff3_LUT_out[19]), .Y(n1629) );
OAI211XLTS U2513 ( .A0(operation[1]), .A1(n1624), .B0(n1623), .C0(n1629),
.Y(add_subt_data2[22]) );
INVX2TS U2514 ( .A(Data_2[18]), .Y(n1626) );
AOI22X1TS U2515 ( .A0(n2501), .A1(FPSENCOS_d_ff3_sh_y_out[18]), .B0(n2499),
.B1(FPSENCOS_d_ff3_sh_x_out[18]), .Y(n1625) );
NAND2X1TS U2516 ( .A(n2455), .B(FPSENCOS_d_ff3_LUT_out[13]), .Y(n1654) );
OAI211XLTS U2517 ( .A0(operation[1]), .A1(n1626), .B0(n1625), .C0(n1654),
.Y(add_subt_data2[18]) );
INVX2TS U2518 ( .A(Data_2[7]), .Y(n1628) );
AOI22X1TS U2519 ( .A0(n2501), .A1(FPSENCOS_d_ff3_sh_y_out[7]), .B0(n2493),
.B1(FPSENCOS_d_ff3_sh_x_out[7]), .Y(n1627) );
NAND2X1TS U2520 ( .A(n2455), .B(FPSENCOS_d_ff3_LUT_out[7]), .Y(n1647) );
OAI211XLTS U2521 ( .A0(operation[1]), .A1(n1628), .B0(n1627), .C0(n1647),
.Y(add_subt_data2[7]) );
INVX2TS U2522 ( .A(Data_2[19]), .Y(n1631) );
AOI22X1TS U2523 ( .A0(n2479), .A1(FPSENCOS_d_ff3_sh_y_out[19]), .B0(n2499),
.B1(FPSENCOS_d_ff3_sh_x_out[19]), .Y(n1630) );
OAI211XLTS U2524 ( .A0(operation[1]), .A1(n1631), .B0(n1630), .C0(n1629),
.Y(add_subt_data2[19]) );
AOI21X1TS U2525 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n2642), .B0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n1632) );
NAND2X1TS U2526 ( .A(n2011), .B(n2641), .Y(n2031) );
OAI22X1TS U2527 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[5]), .A1(n2023), .B0(n1632),
.B1(n2031), .Y(n1633) );
AOI211X1TS U2528 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n1635), .B0(n1634), .C0(n1633), .Y(n2013) );
AOI22X1TS U2529 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[8]), .A1(n1637), .B0(
FPADDSUB_Raw_mant_NRM_SWR[6]), .B1(n2028), .Y(n1640) );
OAI21XLTS U2530 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[24]), .A1(n1638), .B0(n2646),
.Y(n1639) );
NAND4X1TS U2531 ( .A(n2013), .B(n1641), .C(n1640), .D(n1639), .Y(
FPADDSUB_LZD_raw_out_EWR[0]) );
OR4X2TS U2532 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n1642) );
OR4X2TS U2533 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n1642), .Y(n1643) );
AND4X1TS U2534 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n1644) );
AND4X1TS U2535 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n1644), .Y(n1645) );
AND3X1TS U2536 ( .A(n1646), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .C(n1645),
.Y(n2831) );
INVX2TS U2537 ( .A(Data_2[11]), .Y(n1649) );
AOI22X1TS U2538 ( .A0(n2482), .A1(FPSENCOS_d_ff3_sh_y_out[11]), .B0(n2493),
.B1(FPSENCOS_d_ff3_sh_x_out[11]), .Y(n1648) );
OAI211XLTS U2539 ( .A0(operation[1]), .A1(n1649), .B0(n1648), .C0(n1647),
.Y(add_subt_data2[11]) );
INVX2TS U2540 ( .A(Data_2[16]), .Y(n1651) );
AOI22X1TS U2541 ( .A0(n2501), .A1(FPSENCOS_d_ff3_sh_y_out[16]), .B0(n2493),
.B1(FPSENCOS_d_ff3_sh_x_out[16]), .Y(n1650) );
NAND2X1TS U2542 ( .A(n2455), .B(FPSENCOS_d_ff3_LUT_out[3]), .Y(n1660) );
OAI211XLTS U2543 ( .A0(operation[1]), .A1(n1651), .B0(n1650), .C0(n1660),
.Y(add_subt_data2[16]) );
INVX2TS U2544 ( .A(Data_2[14]), .Y(n1653) );
AOI22X1TS U2545 ( .A0(n2501), .A1(FPSENCOS_d_ff3_sh_y_out[14]), .B0(n2493),
.B1(FPSENCOS_d_ff3_sh_x_out[14]), .Y(n1652) );
NAND2X1TS U2546 ( .A(n2455), .B(FPSENCOS_d_ff3_LUT_out[5]), .Y(n1657) );
OAI211XLTS U2547 ( .A0(operation[1]), .A1(n1653), .B0(n1652), .C0(n1657),
.Y(add_subt_data2[14]) );
INVX2TS U2548 ( .A(Data_2[13]), .Y(n1656) );
AOI22X1TS U2549 ( .A0(n2501), .A1(FPSENCOS_d_ff3_sh_y_out[13]), .B0(n2493),
.B1(FPSENCOS_d_ff3_sh_x_out[13]), .Y(n1655) );
OAI211XLTS U2550 ( .A0(operation[1]), .A1(n1656), .B0(n1655), .C0(n1654),
.Y(add_subt_data2[13]) );
INVX2TS U2551 ( .A(Data_2[5]), .Y(n1659) );
AOI22X1TS U2552 ( .A0(n2482), .A1(FPSENCOS_d_ff3_sh_y_out[5]), .B0(n2493),
.B1(FPSENCOS_d_ff3_sh_x_out[5]), .Y(n1658) );
OAI211XLTS U2553 ( .A0(operation[1]), .A1(n1659), .B0(n1658), .C0(n1657),
.Y(add_subt_data2[5]) );
INVX2TS U2554 ( .A(Data_2[3]), .Y(n1662) );
AOI22X1TS U2555 ( .A0(n2482), .A1(FPSENCOS_d_ff3_sh_y_out[3]), .B0(n2493),
.B1(FPSENCOS_d_ff3_sh_x_out[3]), .Y(n1661) );
OAI211XLTS U2556 ( .A0(operation[1]), .A1(n1662), .B0(n1661), .C0(n1660),
.Y(add_subt_data2[3]) );
INVX2TS U2557 ( .A(Data_2[17]), .Y(n1664) );
AOI22X1TS U2558 ( .A0(n2501), .A1(FPSENCOS_d_ff3_sh_y_out[17]), .B0(n2493),
.B1(FPSENCOS_d_ff3_sh_x_out[17]), .Y(n1663) );
NAND2X1TS U2559 ( .A(n2455), .B(FPSENCOS_d_ff3_LUT_out[15]), .Y(n1667) );
OAI211XLTS U2560 ( .A0(operation[1]), .A1(n1664), .B0(n1663), .C0(n1667),
.Y(add_subt_data2[17]) );
INVX2TS U2561 ( .A(Data_2[20]), .Y(n1666) );
AOI22X1TS U2562 ( .A0(n2501), .A1(FPSENCOS_d_ff3_sh_y_out[20]), .B0(n2499),
.B1(FPSENCOS_d_ff3_sh_x_out[20]), .Y(n1665) );
OAI211XLTS U2563 ( .A0(operation[1]), .A1(n1666), .B0(n1665), .C0(n1667),
.Y(add_subt_data2[20]) );
INVX2TS U2564 ( .A(Data_2[15]), .Y(n1669) );
AOI22X1TS U2565 ( .A0(n2501), .A1(FPSENCOS_d_ff3_sh_y_out[15]), .B0(n2493),
.B1(FPSENCOS_d_ff3_sh_x_out[15]), .Y(n1668) );
OAI211XLTS U2566 ( .A0(operation[1]), .A1(n1669), .B0(n1668), .C0(n1667),
.Y(add_subt_data2[15]) );
INVX2TS U2567 ( .A(Data_2[27]), .Y(n1671) );
AOI22X1TS U2568 ( .A0(n2479), .A1(FPSENCOS_d_ff3_sh_y_out[27]), .B0(n2499),
.B1(FPSENCOS_d_ff3_sh_x_out[27]), .Y(n1670) );
NAND2X1TS U2569 ( .A(n2455), .B(FPSENCOS_d_ff3_LUT_out[27]), .Y(n1674) );
OAI211XLTS U2570 ( .A0(operation[1]), .A1(n1671), .B0(n1670), .C0(n1674),
.Y(add_subt_data2[27]) );
INVX2TS U2571 ( .A(Data_2[28]), .Y(n1673) );
AOI22X1TS U2572 ( .A0(n2479), .A1(FPSENCOS_d_ff3_sh_y_out[28]), .B0(n2499),
.B1(FPSENCOS_d_ff3_sh_x_out[28]), .Y(n1672) );
OAI211XLTS U2573 ( .A0(operation[1]), .A1(n1673), .B0(n1672), .C0(n1674),
.Y(add_subt_data2[28]) );
INVX2TS U2574 ( .A(Data_2[29]), .Y(n1676) );
AOI22X1TS U2575 ( .A0(n2479), .A1(FPSENCOS_d_ff3_sh_y_out[29]), .B0(n2493),
.B1(FPSENCOS_d_ff3_sh_x_out[29]), .Y(n1675) );
OAI211XLTS U2576 ( .A0(operation[1]), .A1(n1676), .B0(n1675), .C0(n1674),
.Y(add_subt_data2[29]) );
INVX2TS U2577 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[12]), .Y(n1677) );
NOR2X1TS U2578 ( .A(n1677), .B(intadd_1083_SUM_0_), .Y(intadd_1082_B_0_) );
AOI21X1TS U2579 ( .A0(intadd_1083_SUM_0_), .A1(n1677), .B0(intadd_1082_B_0_),
.Y(n1678) );
INVX2TS U2580 ( .A(n2224), .Y(n2225) );
NAND3XLTS U2581 ( .A(n2669), .B(n2225), .C(n1789), .Y(n1683) );
INVX2TS U2582 ( .A(n1683), .Y(n1681) );
AOI22X1TS U2583 ( .A0(n2826), .A1(n2825), .B0(r_mode[0]), .B1(r_mode[1]),
.Y(n1679) );
OAI221X1TS U2584 ( .A0(n2722), .A1(r_mode[1]), .B0(n2827), .B1(r_mode[0]),
.C0(n1679), .Y(n1684) );
NAND2X1TS U2585 ( .A(FPMULT_FS_Module_state_reg[3]), .B(
FPMULT_FS_Module_state_reg[2]), .Y(n1783) );
AOI22X1TS U2586 ( .A0(n1681), .A1(n1684), .B0(n1680), .B1(n1783), .Y(n1682)
);
OAI31X1TS U2587 ( .A0(n2224), .A1(FPMULT_FS_Module_state_reg[2]), .A2(n2669),
.B0(n1682), .Y(FPMULT_FS_Module_state_next[1]) );
NAND2X1TS U2588 ( .A(n2511), .B(n2598), .Y(n1791) );
OAI31X1TS U2589 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(
FPSENCOS_cont_iter_out[1]), .A2(n2598), .B0(n1791), .Y(n856) );
NAND2X1TS U2590 ( .A(n2670), .B(n2599), .Y(n1788) );
INVX2TS U2591 ( .A(n2552), .Y(n865) );
OAI31X4TS U2592 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(
FPSENCOS_cont_iter_out[3]), .A2(n2608), .B0(n865), .Y(n2554) );
NAND2X1TS U2593 ( .A(n2598), .B(FPSENCOS_cont_iter_out[3]), .Y(n1792) );
OAI21XLTS U2594 ( .A0(n2651), .A1(n2554), .B0(n1792), .Y(n860) );
INVX2TS U2595 ( .A(n1792), .Y(n1694) );
NAND2X1TS U2596 ( .A(n865), .B(FPSENCOS_cont_iter_out[0]), .Y(n2557) );
INVX2TS U2597 ( .A(n2557), .Y(n2556) );
NOR2X1TS U2598 ( .A(n1694), .B(n2556), .Y(n2553) );
OAI211X1TS U2599 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n2608), .B0(n2598),
.C0(n2651), .Y(n2555) );
OAI21XLTS U2600 ( .A0(n2553), .A1(n2651), .B0(n2555), .Y(n854) );
OAI21XLTS U2601 ( .A0(n1684), .A1(n1683), .B0(n2676), .Y(n834) );
OR2X1TS U2602 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .Y(n1685) );
NAND2X1TS U2603 ( .A(n1686), .B(n1029), .Y(n1774) );
BUFX3TS U2604 ( .A(n2790), .Y(n2818) );
BUFX3TS U2605 ( .A(n1687), .Y(n2791) );
BUFX3TS U2606 ( .A(n2816), .Y(n2800) );
BUFX3TS U2607 ( .A(n1687), .Y(n2792) );
BUFX3TS U2608 ( .A(n2792), .Y(n2796) );
BUFX3TS U2609 ( .A(n1691), .Y(n2799) );
BUFX3TS U2610 ( .A(n2801), .Y(n2805) );
NAND2BXLTS U2611 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(n1776),
.Y(n1782) );
BUFX3TS U2612 ( .A(n1687), .Y(n2817) );
BUFX3TS U2613 ( .A(n963), .Y(n2813) );
BUFX3TS U2614 ( .A(n1786), .Y(n2747) );
BUFX3TS U2615 ( .A(n964), .Y(n2812) );
BUFX3TS U2616 ( .A(n2816), .Y(n2810) );
BUFX3TS U2617 ( .A(n2771), .Y(n2768) );
BUFX3TS U2618 ( .A(n2807), .Y(n2804) );
BUFX3TS U2619 ( .A(n2756), .Y(n2755) );
BUFX3TS U2620 ( .A(n2800), .Y(n2802) );
BUFX3TS U2621 ( .A(n2746), .Y(n2759) );
BUFX3TS U2622 ( .A(n2804), .Y(n2809) );
BUFX3TS U2623 ( .A(n2802), .Y(n2807) );
BUFX3TS U2624 ( .A(n2762), .Y(n2750) );
BUFX3TS U2625 ( .A(n2771), .Y(n2748) );
BUFX3TS U2626 ( .A(n2770), .Y(n2773) );
BUFX3TS U2627 ( .A(n2762), .Y(n2752) );
BUFX3TS U2628 ( .A(n2770), .Y(n2754) );
BUFX3TS U2629 ( .A(n2756), .Y(n2744) );
BUFX3TS U2630 ( .A(n2746), .Y(n2772) );
BUFX3TS U2631 ( .A(n2796), .Y(n2801) );
NOR2X1TS U2632 ( .A(FPMULT_Exp_module_Overflow_flag_A), .B(
FPMULT_exp_oper_result[8]), .Y(n2279) );
OR2X1TS U2633 ( .A(n1787), .B(FPMULT_exp_oper_result[0]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[0]) );
OR2X1TS U2634 ( .A(n1787), .B(FPMULT_exp_oper_result[7]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[7]) );
OR2X1TS U2635 ( .A(n1787), .B(FPMULT_exp_oper_result[6]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[6]) );
OR2X1TS U2636 ( .A(n1787), .B(FPMULT_exp_oper_result[2]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[2]) );
OR2X1TS U2637 ( .A(n1787), .B(FPMULT_exp_oper_result[4]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[4]) );
OR2X1TS U2638 ( .A(n1787), .B(FPMULT_exp_oper_result[3]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[3]) );
OR2X1TS U2639 ( .A(n1787), .B(FPMULT_exp_oper_result[1]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[1]) );
OR2X1TS U2640 ( .A(n1787), .B(FPMULT_exp_oper_result[5]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[5]) );
INVX2TS U2641 ( .A(n1790), .Y(n1692) );
OAI32X1TS U2642 ( .A0(n2669), .A1(FPMULT_FS_Module_state_reg[2]), .A2(n2225),
.B0(FPMULT_FS_Module_state_reg[1]), .B1(n1692), .Y(
FPMULT_FS_Module_state_next[2]) );
NAND3XLTS U2643 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n1789), .C(n2225),
.Y(n2391) );
OAI22X1TS U2644 ( .A0(n2224), .A1(n1692), .B0(n2391), .B1(n2697), .Y(
FPMULT_FSM_load_second_step) );
OR2X1TS U2645 ( .A(n107), .B(FPMULT_FSM_load_second_step), .Y(
FPMULT_FSM_exp_operation_load_result) );
BUFX3TS U2646 ( .A(n1693), .Y(n2380) );
AO22XLTS U2647 ( .A0(n2381), .A1(FPSENCOS_d_ff1_Z[28]), .B0(n2379), .B1(
FPSENCOS_d_ff_Zn[28]), .Y(FPSENCOS_first_mux_Z[28]) );
INVX4TS U2648 ( .A(n2380), .Y(n2382) );
AO22XLTS U2649 ( .A0(n2382), .A1(FPSENCOS_d_ff1_Z[29]), .B0(n2379), .B1(
FPSENCOS_d_ff_Zn[29]), .Y(FPSENCOS_first_mux_Z[29]) );
AO22XLTS U2650 ( .A0(n2382), .A1(FPSENCOS_d_ff1_Z[30]), .B0(n2379), .B1(
FPSENCOS_d_ff_Zn[30]), .Y(FPSENCOS_first_mux_Z[30]) );
NAND2X1TS U2651 ( .A(n1805), .B(n2557), .Y(n851) );
NOR2XLTS U2652 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n1695) );
NOR2BX2TS U2653 ( .AN(FPADDSUB_bit_shift_SHT2), .B(n1750), .Y(n1749) );
NAND2BX2TS U2654 ( .AN(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n1746) );
NAND2X1TS U2655 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n2663), .Y(n1745)
);
AOI22X1TS U2656 ( .A0(n1698), .A1(FPADDSUB_Data_array_SWR[41]), .B0(n1699),
.B1(FPADDSUB_Data_array_SWR[37]), .Y(n1703) );
NOR2BX1TS U2657 ( .AN(n1750), .B(FPADDSUB_shift_value_SHT2_EWR[4]), .Y(n1701) );
AOI22X1TS U2658 ( .A0(n1700), .A1(FPADDSUB_Data_array_SWR[33]), .B0(n1842),
.B1(FPADDSUB_Data_array_SWR[29]), .Y(n1702) );
OAI211X1TS U2659 ( .A0(n1850), .A1(n2662), .B0(n1703), .C0(n1702), .Y(n1723)
);
NAND2X1TS U2660 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(
FPADDSUB_bit_shift_SHT2), .Y(n1725) );
AOI21X1TS U2661 ( .A0(n1846), .A1(n1723), .B0(n1704), .Y(n1705) );
OAI21X1TS U2662 ( .A0(n1845), .A1(n1696), .B0(n1705), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[22]) );
NOR2X1TS U2663 ( .A(n2830), .B(n2831), .Y(n1706) );
CLKAND2X2TS U2664 ( .A(n2375), .B(FPADDSUB_sftr_odat_SHT2_SWR[22]), .Y(
FPADDSUB_formatted_number_W[20]) );
AOI22X1TS U2665 ( .A0(n1698), .A1(FPADDSUB_Data_array_SWR[40]), .B0(n1699),
.B1(FPADDSUB_Data_array_SWR[36]), .Y(n1709) );
AOI22X1TS U2666 ( .A0(n1700), .A1(FPADDSUB_Data_array_SWR[32]), .B0(n1842),
.B1(FPADDSUB_Data_array_SWR[28]), .Y(n1708) );
OAI211X1TS U2667 ( .A0(n1854), .A1(n2662), .B0(n1709), .C0(n1708), .Y(n1756)
);
AOI21X1TS U2668 ( .A0(n1846), .A1(n1756), .B0(n1704), .Y(n1710) );
OAI21X1TS U2669 ( .A0(n1840), .A1(n1696), .B0(n1710), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[23]) );
CLKAND2X2TS U2670 ( .A(n2375), .B(FPADDSUB_sftr_odat_SHT2_SWR[23]), .Y(
FPADDSUB_formatted_number_W[21]) );
INVX1TS U2671 ( .A(FPADDSUB_Data_array_SWR[51]), .Y(n1739) );
OAI22X1TS U2672 ( .A0(n1746), .A1(n2691), .B0(n1745), .B1(n1739), .Y(n1711)
);
AOI22X1TS U2673 ( .A0(n1700), .A1(FPADDSUB_Data_array_SWR[31]), .B0(n1842),
.B1(FPADDSUB_Data_array_SWR[27]), .Y(n1713) );
AOI22X1TS U2674 ( .A0(n1698), .A1(FPADDSUB_Data_array_SWR[39]), .B0(n1699),
.B1(FPADDSUB_Data_array_SWR[35]), .Y(n1712) );
OAI211X1TS U2675 ( .A0(n1766), .A1(n2662), .B0(n1713), .C0(n1712), .Y(n1815)
);
AOI21X1TS U2676 ( .A0(n1846), .A1(n1815), .B0(n1704), .Y(n1714) );
OAI21X1TS U2677 ( .A0(n1817), .A1(n1696), .B0(n1714), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[24]) );
CLKAND2X2TS U2678 ( .A(n2375), .B(FPADDSUB_sftr_odat_SHT2_SWR[24]), .Y(
FPADDSUB_formatted_number_W[22]) );
AOI22X1TS U2679 ( .A0(n1698), .A1(FPADDSUB_Data_array_SWR[43]), .B0(n1699),
.B1(FPADDSUB_Data_array_SWR[39]), .Y(n1719) );
AOI22X1TS U2680 ( .A0(n1700), .A1(FPADDSUB_Data_array_SWR[35]), .B0(n1842),
.B1(FPADDSUB_Data_array_SWR[31]), .Y(n1718) );
OAI211X1TS U2681 ( .A0(n1837), .A1(n2662), .B0(n1719), .C0(n1718), .Y(n1754)
);
AOI21X1TS U2682 ( .A0(n1846), .A1(n1754), .B0(n1704), .Y(n1720) );
OAI21X1TS U2683 ( .A0(n1833), .A1(n1696), .B0(n1720), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[20]) );
CLKAND2X2TS U2684 ( .A(n2375), .B(FPADDSUB_sftr_odat_SHT2_SWR[20]), .Y(
FPADDSUB_formatted_number_W[18]) );
AOI21X1TS U2685 ( .A0(n1852), .A1(n1723), .B0(n1722), .Y(n1724) );
OAI21X1TS U2686 ( .A0(n1721), .A1(n1845), .B0(n1724), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[3]) );
CLKAND2X2TS U2687 ( .A(n2375), .B(FPADDSUB_sftr_odat_SHT2_SWR[3]), .Y(
FPADDSUB_formatted_number_W[1]) );
INVX2TS U2688 ( .A(n1725), .Y(n1744) );
OR2X1TS U2689 ( .A(n1748), .B(n1744), .Y(n1730) );
AO22XLTS U2690 ( .A0(n1700), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n1842),
.B1(FPADDSUB_Data_array_SWR[41]), .Y(n1726) );
AOI211X1TS U2691 ( .A0(n1699), .A1(FPADDSUB_Data_array_SWR[49]), .B0(n1730),
.C0(n1726), .Y(n1736) );
AOI22X1TS U2692 ( .A0(n1700), .A1(FPADDSUB_Data_array_SWR[40]), .B0(n1842),
.B1(FPADDSUB_Data_array_SWR[36]), .Y(n1727) );
OAI21XLTS U2693 ( .A0(n2688), .A1(n1742), .B0(n1727), .Y(n1728) );
AOI22X1TS U2694 ( .A0(n1846), .A1(n1736), .B0(n1737), .B1(n1852), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[10]) );
CLKAND2X2TS U2695 ( .A(n2375), .B(FPADDSUB_sftr_odat_SHT2_SWR[10]), .Y(
FPADDSUB_formatted_number_W[8]) );
AO22XLTS U2696 ( .A0(FPADDSUB_Data_array_SWR[44]), .A1(n1700), .B0(n1842),
.B1(FPADDSUB_Data_array_SWR[40]), .Y(n1729) );
AOI211X1TS U2697 ( .A0(FPADDSUB_Data_array_SWR[48]), .A1(n1699), .B0(n1730),
.C0(n1729), .Y(n1760) );
AOI22X1TS U2698 ( .A0(n1700), .A1(FPADDSUB_Data_array_SWR[41]), .B0(n1842),
.B1(FPADDSUB_Data_array_SWR[37]), .Y(n1731) );
OAI21XLTS U2699 ( .A0(n1742), .A1(n2689), .B0(n1731), .Y(n1732) );
AOI22X1TS U2700 ( .A0(n1846), .A1(n1760), .B0(n1761), .B1(n1852), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[11]) );
CLKAND2X2TS U2701 ( .A(n2375), .B(FPADDSUB_sftr_odat_SHT2_SWR[11]), .Y(
FPADDSUB_formatted_number_W[9]) );
AOI22X1TS U2702 ( .A0(n1698), .A1(FPADDSUB_Data_array_SWR[46]), .B0(n1699),
.B1(FPADDSUB_Data_array_SWR[42]), .Y(n1734) );
AOI22X1TS U2703 ( .A0(n1700), .A1(FPADDSUB_Data_array_SWR[38]), .B0(n1842),
.B1(FPADDSUB_Data_array_SWR[34]), .Y(n1733) );
AOI21X1TS U2704 ( .A0(n1846), .A1(n1764), .B0(n1704), .Y(n1735) );
OAI21X1TS U2705 ( .A0(n1766), .A1(n1696), .B0(n1735), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[17]) );
CLKAND2X2TS U2706 ( .A(n2375), .B(FPADDSUB_sftr_odat_SHT2_SWR[17]), .Y(
FPADDSUB_formatted_number_W[15]) );
AOI22X1TS U2707 ( .A0(n1846), .A1(n1737), .B0(n1736), .B1(n1852), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[15]) );
CLKAND2X2TS U2708 ( .A(n2375), .B(FPADDSUB_sftr_odat_SHT2_SWR[15]), .Y(
FPADDSUB_formatted_number_W[13]) );
AOI22X1TS U2709 ( .A0(n1700), .A1(FPADDSUB_Data_array_SWR[43]), .B0(n1842),
.B1(FPADDSUB_Data_array_SWR[39]), .Y(n1738) );
OAI21XLTS U2710 ( .A0(n1742), .A1(n1739), .B0(n1738), .Y(n1740) );
AOI211X1TS U2711 ( .A0(n1699), .A1(FPADDSUB_Data_array_SWR[47]), .B0(n1744),
.C0(n1740), .Y(n1762) );
AOI22X1TS U2712 ( .A0(n1700), .A1(FPADDSUB_Data_array_SWR[42]), .B0(n1842),
.B1(FPADDSUB_Data_array_SWR[38]), .Y(n1741) );
OAI21XLTS U2713 ( .A0(n1742), .A1(n2622), .B0(n1741), .Y(n1743) );
AOI211X1TS U2714 ( .A0(n1699), .A1(FPADDSUB_Data_array_SWR[46]), .B0(n1744),
.C0(n1743), .Y(n1763) );
AOI22X1TS U2715 ( .A0(n1846), .A1(n1762), .B0(n1763), .B1(n1852), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[12]) );
CLKAND2X2TS U2716 ( .A(n2375), .B(FPADDSUB_sftr_odat_SHT2_SWR[12]), .Y(
FPADDSUB_formatted_number_W[10]) );
OAI22X1TS U2717 ( .A0(n1746), .A1(n2690), .B0(n1745), .B1(n2622), .Y(n1747)
);
AOI22X1TS U2718 ( .A0(n1700), .A1(FPADDSUB_Data_array_SWR[39]), .B0(n1699),
.B1(FPADDSUB_Data_array_SWR[43]), .Y(n1752) );
AOI22X1TS U2719 ( .A0(n1842), .A1(FPADDSUB_Data_array_SWR[35]), .B0(n1698),
.B1(FPADDSUB_Data_array_SWR[47]), .Y(n1751) );
AOI21X1TS U2720 ( .A0(n1846), .A1(n1758), .B0(n1704), .Y(n1753) );
OAI21X1TS U2721 ( .A0(n1813), .A1(n1696), .B0(n1753), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[16]) );
CLKAND2X2TS U2722 ( .A(n1706), .B(FPADDSUB_sftr_odat_SHT2_SWR[16]), .Y(
FPADDSUB_formatted_number_W[14]) );
AOI21X1TS U2723 ( .A0(n1852), .A1(n1754), .B0(n1722), .Y(n1755) );
OAI21X1TS U2724 ( .A0(n1833), .A1(n1721), .B0(n1755), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[5]) );
CLKAND2X2TS U2725 ( .A(n2375), .B(FPADDSUB_sftr_odat_SHT2_SWR[5]), .Y(
FPADDSUB_formatted_number_W[3]) );
AOI21X1TS U2726 ( .A0(n1852), .A1(n1756), .B0(n1722), .Y(n1757) );
OAI21X1TS U2727 ( .A0(n1840), .A1(n1721), .B0(n1757), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[2]) );
CLKAND2X2TS U2728 ( .A(n982), .B(FPADDSUB_sftr_odat_SHT2_SWR[2]), .Y(
FPADDSUB_formatted_number_W[0]) );
AOI21X1TS U2729 ( .A0(n1852), .A1(n1758), .B0(n1722), .Y(n1759) );
OAI21X1TS U2730 ( .A0(n1813), .A1(n1721), .B0(n1759), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[9]) );
CLKAND2X2TS U2731 ( .A(n982), .B(FPADDSUB_sftr_odat_SHT2_SWR[9]), .Y(
FPADDSUB_formatted_number_W[7]) );
AOI22X1TS U2732 ( .A0(n1846), .A1(n1761), .B0(n1760), .B1(n1852), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[14]) );
CLKAND2X2TS U2733 ( .A(n982), .B(FPADDSUB_sftr_odat_SHT2_SWR[14]), .Y(
FPADDSUB_formatted_number_W[12]) );
AOI22X1TS U2734 ( .A0(n1846), .A1(n1763), .B0(n1762), .B1(n1852), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[13]) );
CLKAND2X2TS U2735 ( .A(n982), .B(FPADDSUB_sftr_odat_SHT2_SWR[13]), .Y(
FPADDSUB_formatted_number_W[11]) );
AOI21X1TS U2736 ( .A0(n1852), .A1(n1764), .B0(n1722), .Y(n1765) );
OAI21X1TS U2737 ( .A0(n1766), .A1(n1721), .B0(n1765), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[8]) );
CLKAND2X2TS U2738 ( .A(n982), .B(FPADDSUB_sftr_odat_SHT2_SWR[8]), .Y(
FPADDSUB_formatted_number_W[6]) );
INVX2TS U2739 ( .A(n1767), .Y(n1768) );
NOR4X1TS U2740 ( .A(FPMULT_Sgf_operation_Result[7]), .B(
FPMULT_Sgf_operation_Result[9]), .C(FPMULT_Sgf_operation_Result[11]),
.D(FPMULT_Sgf_operation_Result[6]), .Y(n1773) );
OR4X2TS U2741 ( .A(FPMULT_Sgf_operation_Result[15]), .B(
FPMULT_Sgf_operation_Result[19]), .C(FPMULT_Sgf_operation_Result[13]),
.D(FPMULT_Sgf_operation_Result[22]), .Y(n1769) );
NOR4X1TS U2742 ( .A(FPMULT_Sgf_operation_Result[8]), .B(
FPMULT_Sgf_operation_Result[17]), .C(FPMULT_Sgf_operation_Result[16]),
.D(n1769), .Y(n1772) );
NOR4X1TS U2743 ( .A(FPMULT_Sgf_operation_Result[3]), .B(
FPMULT_Sgf_operation_Result[5]), .C(FPMULT_Sgf_operation_Result[21]),
.D(FPMULT_Sgf_operation_Result[0]), .Y(n1771) );
NOR4X1TS U2744 ( .A(FPMULT_Sgf_operation_Result[4]), .B(
FPMULT_Sgf_operation_Result[18]), .C(FPMULT_Sgf_operation_Result[20]),
.D(FPMULT_Sgf_operation_Result[1]), .Y(n1770) );
AND4X1TS U2745 ( .A(n1773), .B(n1772), .C(n1771), .D(n1770), .Y(n2729) );
NOR2X1TS U2746 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(n1774),
.Y(n1875) );
NAND3BXLTS U2747 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(n1875), .Y(n1863) );
NOR2XLTS U2748 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .Y(n1775) );
NAND4X1TS U2749 ( .A(n1776), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]),
.C(n1775), .D(n2648), .Y(n2396) );
NAND2X1TS U2750 ( .A(n1863), .B(n2396), .Y(FPSENCOS_enab_d_ff_RB1) );
AOI22X1TS U2751 ( .A0(FPSENCOS_d_ff3_sh_x_out[0]), .A1(n2468), .B0(Data_2[0]), .B1(n2424), .Y(n1778) );
BUFX3TS U2752 ( .A(n2455), .Y(n2500) );
AOI22X1TS U2753 ( .A0(n2507), .A1(FPSENCOS_d_ff3_sh_y_out[0]), .B0(n2500),
.B1(FPSENCOS_d_ff3_LUT_out[0]), .Y(n1777) );
NAND2X1TS U2754 ( .A(n1778), .B(n1777), .Y(add_subt_data2[0]) );
BUFX4TS U2755 ( .A(n2424), .Y(n2496) );
AOI22X1TS U2756 ( .A0(FPSENCOS_d_ff2_Y[9]), .A1(n2468), .B0(Data_1[9]), .B1(
n2496), .Y(n1781) );
BUFX3TS U2757 ( .A(n2482), .Y(n2479) );
AOI22X1TS U2758 ( .A0(n2479), .A1(FPSENCOS_d_ff2_X[9]), .B0(n1779), .B1(
FPSENCOS_d_ff2_Z[9]), .Y(n1780) );
NAND2X1TS U2759 ( .A(n1781), .B(n1780), .Y(add_subt_data1[9]) );
INVX4TS U2760 ( .A(n1897), .Y(n2787) );
NOR2X1TS U2761 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(n1782),
.Y(n1874) );
NAND3BX1TS U2762 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .C(n1874), .Y(n2392) );
INVX2TS U2763 ( .A(n2392), .Y(n1785) );
BUFX3TS U2764 ( .A(n2551), .Y(n2542) );
NAND2X1TS U2765 ( .A(n960), .B(operation[2]), .Y(n2559) );
AOI22X1TS U2766 ( .A0(n2542), .A1(ready_add_subt), .B0(n2562), .B1(n2548),
.Y(n1784) );
OAI2BB1X1TS U2767 ( .A0N(n1785), .A1N(n2540), .B0(n1784), .Y(operation_ready) );
BUFX3TS U2768 ( .A(n2789), .Y(n2783) );
BUFX3TS U2769 ( .A(n2789), .Y(n2784) );
BUFX3TS U2770 ( .A(n2789), .Y(n2785) );
BUFX3TS U2771 ( .A(n2789), .Y(n2775) );
BUFX3TS U2772 ( .A(n2789), .Y(n2777) );
BUFX3TS U2773 ( .A(n2789), .Y(n2776) );
BUFX3TS U2774 ( .A(n2789), .Y(n2781) );
BUFX3TS U2775 ( .A(n1786), .Y(n2753) );
BUFX3TS U2776 ( .A(n1786), .Y(n2762) );
BUFX3TS U2777 ( .A(n1786), .Y(n2745) );
BUFX3TS U2778 ( .A(n1786), .Y(n2749) );
BUFX3TS U2779 ( .A(n1786), .Y(n2761) );
BUFX3TS U2780 ( .A(n2789), .Y(n2778) );
BUFX3TS U2781 ( .A(n1786), .Y(n2751) );
BUFX3TS U2782 ( .A(n1786), .Y(n2760) );
BUFX3TS U2783 ( .A(n1786), .Y(n2758) );
BUFX3TS U2784 ( .A(n2789), .Y(n2779) );
NAND2X1TS U2785 ( .A(n2671), .B(FPSENCOS_cont_iter_out[0]), .Y(
intadd_1085_CI) );
OAI21XLTS U2786 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n2671), .B0(
intadd_1085_CI), .Y(FPSENCOS_sh_exp_y[0]) );
NAND2X1TS U2787 ( .A(n2672), .B(FPSENCOS_cont_iter_out[0]), .Y(
intadd_1084_CI) );
NAND2X1TS U2788 ( .A(n2699), .B(n2623), .Y(n2113) );
OAI21XLTS U2789 ( .A0(n2623), .A1(n2699), .B0(n2113), .Y(
FPMULT_Adder_M_result_A_adder[1]) );
NAND2X1TS U2790 ( .A(FPADDSUB_DmP_EXP_EWSW[23]), .B(n1014), .Y(n1797) );
NOR2XLTS U2791 ( .A(n2699), .B(n1787), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[1]) );
NOR2XLTS U2792 ( .A(n2111), .B(n1787), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[3]) );
NOR2XLTS U2793 ( .A(n2110), .B(n1787), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[5]) );
INVX2TS U2794 ( .A(FPMULT_Sgf_normalized_result[21]), .Y(n2086) );
NOR2XLTS U2795 ( .A(n2107), .B(n1787), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[7]) );
NOR2XLTS U2796 ( .A(n2623), .B(n1787), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[0]) );
INVX2TS U2797 ( .A(FPMULT_Sgf_normalized_result[13]), .Y(n2098) );
BUFX4TS U2798 ( .A(n1787), .Y(n2376) );
NOR2XLTS U2799 ( .A(n2098), .B(n2376), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[13]) );
INVX2TS U2800 ( .A(FPMULT_Sgf_normalized_result[9]), .Y(n2104) );
NOR2XLTS U2801 ( .A(n2104), .B(n2376), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[9]) );
INVX2TS U2802 ( .A(FPMULT_Sgf_normalized_result[11]), .Y(n2101) );
NOR2XLTS U2803 ( .A(n2101), .B(n2376), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[11]) );
INVX2TS U2804 ( .A(FPMULT_Sgf_normalized_result[19]), .Y(n2089) );
NOR2XLTS U2805 ( .A(n2089), .B(n2376), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[19]) );
INVX2TS U2806 ( .A(FPMULT_Sgf_normalized_result[17]), .Y(n2092) );
NOR2XLTS U2807 ( .A(n2092), .B(n2376), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[17]) );
NOR2XLTS U2808 ( .A(n1794), .B(n1788), .Y(FPMULT_FSM_first_phase_load) );
INVX2TS U2809 ( .A(n1789), .Y(n1795) );
NOR3XLTS U2810 ( .A(n2669), .B(n2225), .C(n1795), .Y(
FPMULT_FSM_final_result_load) );
INVX2TS U2811 ( .A(intadd_1086_SUM_0_), .Y(FPADDSUB_Shift_amount_EXP_EW[1])
);
INVX2TS U2812 ( .A(FPMULT_FSM_exp_operation_A_S), .Y(n2039) );
NAND2X1TS U2813 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n1790), .Y(n2390) );
OAI211XLTS U2814 ( .A0(n2039), .A1(n956), .B0(n1795), .C0(n2390), .Y(
FPMULT_FS_Module_state_next[3]) );
NOR2X1TS U2815 ( .A(FPSENCOS_cont_iter_out[0]), .B(FPSENCOS_cont_iter_out[1]), .Y(n1793) );
NOR2XLTS U2816 ( .A(n2511), .B(n1793), .Y(FPSENCOS_ITER_CONT_N3) );
OAI21XLTS U2817 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
n2564), .B0(n2278), .Y(n874) );
OAI21XLTS U2818 ( .A0(n2552), .A1(FPSENCOS_cont_iter_out[1]), .B0(n1805),
.Y(n864) );
INVX2TS U2819 ( .A(intadd_1086_SUM_1_), .Y(FPADDSUB_Shift_amount_EXP_EW[2])
);
OAI211XLTS U2820 ( .A0(n1793), .A1(n1792), .B0(n1791), .C0(n2280), .Y(n855)
);
NOR2X1TS U2821 ( .A(n1795), .B(n1794), .Y(FPMULT_FSM_adder_round_norm_load)
);
NOR2BX1TS U2822 ( .AN(FPMULT_P_Sgf[47]), .B(n1796), .Y(n2046) );
NOR2X1TS U2823 ( .A(n107), .B(FPMULT_FSM_adder_round_norm_load), .Y(n2047)
);
OAI21XLTS U2824 ( .A0(n2046), .A1(n2656), .B0(n2047), .Y(n830) );
INVX2TS U2825 ( .A(intadd_1086_SUM_2_), .Y(FPADDSUB_Shift_amount_EXP_EW[3])
);
NOR2X1TS U2826 ( .A(FPSENCOS_d_ff2_Y[27]), .B(intadd_1085_n1), .Y(n2592) );
OR3X1TS U2827 ( .A(FPSENCOS_d_ff2_Y[27]), .B(FPSENCOS_d_ff2_Y[28]), .C(
intadd_1085_n1), .Y(n2591) );
NOR2X1TS U2828 ( .A(FPSENCOS_d_ff2_X[27]), .B(intadd_1084_n1), .Y(n2595) );
OR3X1TS U2829 ( .A(FPSENCOS_d_ff2_X[27]), .B(FPSENCOS_d_ff2_X[28]), .C(
intadd_1084_n1), .Y(n2594) );
OAI21XLTS U2830 ( .A0(n2595), .A1(n2728), .B0(n2594), .Y(
FPSENCOS_sh_exp_x[5]) );
INVX2TS U2831 ( .A(n1797), .Y(intadd_1086_CI) );
CLKBUFX2TS U2832 ( .A(n2788), .Y(n2352) );
OR2X1TS U2833 ( .A(FPADDSUB_N60), .B(FPADDSUB_N59), .Y(n2307) );
NAND2X1TS U2834 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n2306) );
AOI22X1TS U2835 ( .A0(n2317), .A1(n1801), .B0(n2306), .B1(n2352), .Y(n1799)
);
NAND2X1TS U2836 ( .A(FPADDSUB_DmP_mant_SFG_SWR[3]), .B(n2626), .Y(n1800) );
OAI21XLTS U2837 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[3]), .A1(n2626), .B0(n1800),
.Y(n1798) );
XOR2XLTS U2838 ( .A(n1799), .B(n1798), .Y(FPADDSUB_Raw_mant_SGF[3]) );
NAND2X1TS U2839 ( .A(FPSENCOS_cont_iter_out[2]), .B(n2511), .Y(n2510) );
CLKAND2X2TS U2840 ( .A(n2510), .B(n2600), .Y(n857) );
NOR2X1TS U2841 ( .A(n2600), .B(n2510), .Y(n1864) );
NOR2XLTS U2842 ( .A(n1864), .B(n857), .Y(FPSENCOS_ITER_CONT_N5) );
OR2X1TS U2843 ( .A(FPSENCOS_d_ff_Xn[1]), .B(n2381), .Y(
FPSENCOS_first_mux_X[1]) );
OR2X1TS U2844 ( .A(FPSENCOS_d_ff_Xn[2]), .B(n2381), .Y(
FPSENCOS_first_mux_X[2]) );
OR2X1TS U2845 ( .A(FPSENCOS_d_ff_Xn[5]), .B(n2381), .Y(
FPSENCOS_first_mux_X[5]) );
OR2X1TS U2846 ( .A(FPSENCOS_d_ff_Xn[10]), .B(n2381), .Y(
FPSENCOS_first_mux_X[10]) );
OR2X1TS U2847 ( .A(FPSENCOS_d_ff_Xn[6]), .B(n2381), .Y(
FPSENCOS_first_mux_X[6]) );
OR2X1TS U2848 ( .A(FPSENCOS_d_ff_Xn[12]), .B(n2381), .Y(
FPSENCOS_first_mux_X[12]) );
OR2X1TS U2849 ( .A(FPSENCOS_d_ff_Xn[7]), .B(n2381), .Y(
FPSENCOS_first_mux_X[7]) );
OAI21XLTS U2850 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n865), .B0(n2557), .Y(
n849) );
BUFX3TS U2851 ( .A(n1693), .Y(n2379) );
OR2X1TS U2852 ( .A(FPSENCOS_d_ff_Xn[25]), .B(n914), .Y(
FPSENCOS_first_mux_X[25]) );
OR2X1TS U2853 ( .A(FPSENCOS_d_ff_Xn[29]), .B(n914), .Y(
FPSENCOS_first_mux_X[29]) );
OR2X1TS U2854 ( .A(FPSENCOS_d_ff_Xn[26]), .B(n914), .Y(
FPSENCOS_first_mux_X[26]) );
OR2X1TS U2855 ( .A(FPSENCOS_d_ff_Xn[19]), .B(n914), .Y(
FPSENCOS_first_mux_X[19]) );
OR2X1TS U2856 ( .A(FPSENCOS_d_ff_Xn[13]), .B(n914), .Y(
FPSENCOS_first_mux_X[13]) );
OR2X1TS U2857 ( .A(FPSENCOS_d_ff_Xn[17]), .B(n914), .Y(
FPSENCOS_first_mux_X[17]) );
OR2X1TS U2858 ( .A(FPSENCOS_d_ff_Xn[16]), .B(n914), .Y(
FPSENCOS_first_mux_X[16]) );
OR2X1TS U2859 ( .A(FPSENCOS_d_ff_Xn[27]), .B(n914), .Y(
FPSENCOS_first_mux_X[27]) );
OR2X1TS U2860 ( .A(FPSENCOS_d_ff_Xn[14]), .B(n2377), .Y(
FPSENCOS_first_mux_X[14]) );
OR2X1TS U2861 ( .A(FPSENCOS_d_ff_Xn[20]), .B(n2378), .Y(
FPSENCOS_first_mux_X[20]) );
OR2X1TS U2862 ( .A(FPSENCOS_d_ff_Xn[24]), .B(n914), .Y(
FPSENCOS_first_mux_X[24]) );
OAI21XLTS U2863 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n2554), .B0(n1805),
.Y(n862) );
NOR2X1TS U2864 ( .A(FPADDSUB_DmP_mant_SFG_SWR[4]), .B(n2631), .Y(n1804) );
AOI22X1TS U2865 ( .A0(FPADDSUB_DMP_SFG[1]), .A1(n2601), .B0(n1801), .B1(
n1800), .Y(n1806) );
AOI222X4TS U2866 ( .A0(n2626), .A1(n2306), .B0(n2626), .B1(n2601), .C0(n2306), .C1(n2601), .Y(n1808) );
AOI22X1TS U2867 ( .A0(n2317), .A1(n1806), .B0(n1808), .B1(n2788), .Y(n1803)
);
OAI21XLTS U2868 ( .A0(n1804), .A1(n1807), .B0(n1803), .Y(n1802) );
OAI31X1TS U2869 ( .A0(n1804), .A1(n1803), .A2(n1807), .B0(n1802), .Y(
FPADDSUB_Raw_mant_SGF[4]) );
OAI21X1TS U2870 ( .A0(n2552), .A1(n2651), .B0(n1805), .Y(n863) );
OR2X1TS U2871 ( .A(n863), .B(n2556), .Y(n850) );
OAI22X1TS U2872 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[4]), .A1(n2631), .B0(n1807),
.B1(n1806), .Y(n1820) );
AOI22X1TS U2873 ( .A0(n2317), .A1(n1820), .B0(n1822), .B1(n2788), .Y(n1810)
);
NAND2X1TS U2874 ( .A(FPADDSUB_DmP_mant_SFG_SWR[5]), .B(n2602), .Y(n1821) );
OAI21XLTS U2875 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[5]), .A1(n2602), .B0(n1821),
.Y(n1809) );
XOR2XLTS U2876 ( .A(n1810), .B(n1809), .Y(FPADDSUB_Raw_mant_SGF[5]) );
AOI22X1TS U2877 ( .A0(n1700), .A1(FPADDSUB_Data_array_SWR[30]), .B0(n1699),
.B1(FPADDSUB_Data_array_SWR[34]), .Y(n1812) );
AOI22X1TS U2878 ( .A0(n1842), .A1(FPADDSUB_Data_array_SWR[26]), .B0(n1698),
.B1(FPADDSUB_Data_array_SWR[38]), .Y(n1811) );
OAI211X1TS U2879 ( .A0(n1813), .A1(n2662), .B0(n1812), .C0(n1811), .Y(n1818)
);
AOI21X1TS U2880 ( .A0(n1846), .A1(n1818), .B0(n1704), .Y(n1814) );
AOI21X1TS U2881 ( .A0(n1852), .A1(n1815), .B0(n1722), .Y(n1816) );
OAI21XLTS U2882 ( .A0(n1721), .A1(n1817), .B0(n1816), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[1]) );
AOI21X1TS U2883 ( .A0(n1852), .A1(n1818), .B0(n1722), .Y(n1819) );
OAI21XLTS U2884 ( .A0(n1721), .A1(n962), .B0(n1819), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[0]) );
NOR2X1TS U2885 ( .A(FPADDSUB_DmP_mant_SFG_SWR[6]), .B(n2632), .Y(n1825) );
AOI22X1TS U2886 ( .A0(FPADDSUB_DMP_SFG[3]), .A1(n2627), .B0(n1821), .B1(
n1820), .Y(n1826) );
AOI222X4TS U2887 ( .A0(n1822), .A1(n2602), .B0(n1822), .B1(n2627), .C0(n2602), .C1(n2627), .Y(n1828) );
AOI22X1TS U2888 ( .A0(n2317), .A1(n1826), .B0(n1828), .B1(n2788), .Y(n1824)
);
OAI21XLTS U2889 ( .A0(n1825), .A1(n1827), .B0(n1824), .Y(n1823) );
OAI31X1TS U2890 ( .A0(n1825), .A1(n1824), .A2(n1827), .B0(n1823), .Y(
FPADDSUB_Raw_mant_SGF[6]) );
OAI22X1TS U2891 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[6]), .A1(n2632), .B0(n1827),
.B1(n1826), .Y(n1857) );
AOI22X1TS U2892 ( .A0(n2317), .A1(n1857), .B0(n1859), .B1(n2788), .Y(n1830)
);
NAND2X1TS U2893 ( .A(FPADDSUB_DmP_mant_SFG_SWR[7]), .B(n2603), .Y(n1858) );
OAI21XLTS U2894 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[7]), .A1(n2603), .B0(n1858),
.Y(n1829) );
XOR2XLTS U2895 ( .A(n1830), .B(n1829), .Y(FPADDSUB_Raw_mant_SGF[7]) );
OR2X1TS U2896 ( .A(n2830), .B(FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(
FPADDSUB_formatted_number_W[25]) );
OR2X1TS U2897 ( .A(n2830), .B(FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(
FPADDSUB_formatted_number_W[24]) );
OR2X1TS U2898 ( .A(n2830), .B(FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(
FPADDSUB_formatted_number_W[26]) );
OR2X1TS U2899 ( .A(n2830), .B(FPADDSUB_exp_rslt_NRM2_EW1[4]), .Y(
FPADDSUB_formatted_number_W[27]) );
OR2X1TS U2900 ( .A(n2830), .B(FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(
FPADDSUB_formatted_number_W[23]) );
OR2X1TS U2901 ( .A(n2830), .B(FPADDSUB_exp_rslt_NRM2_EW1[6]), .Y(
FPADDSUB_formatted_number_W[29]) );
AOI22X1TS U2902 ( .A0(n1698), .A1(FPADDSUB_Data_array_SWR[42]), .B0(n1699),
.B1(FPADDSUB_Data_array_SWR[38]), .Y(n1832) );
AOI22X1TS U2903 ( .A0(n1700), .A1(FPADDSUB_Data_array_SWR[34]), .B0(n1842),
.B1(FPADDSUB_Data_array_SWR[30]), .Y(n1831) );
OAI211X1TS U2904 ( .A0(n1833), .A1(n2662), .B0(n1832), .C0(n1831), .Y(n1835)
);
AOI21X1TS U2905 ( .A0(n1846), .A1(n1835), .B0(n1704), .Y(n1834) );
OAI21X1TS U2906 ( .A0(n1837), .A1(n1696), .B0(n1834), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[21]) );
AOI21X1TS U2907 ( .A0(n1852), .A1(n1835), .B0(n1722), .Y(n1836) );
OAI21X1TS U2908 ( .A0(n1837), .A1(n1721), .B0(n1836), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[4]) );
AOI22X1TS U2909 ( .A0(n1698), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n1699),
.B1(FPADDSUB_Data_array_SWR[41]), .Y(n1839) );
AOI22X1TS U2910 ( .A0(n1700), .A1(FPADDSUB_Data_array_SWR[37]), .B0(n1842),
.B1(FPADDSUB_Data_array_SWR[33]), .Y(n1838) );
AOI21X1TS U2911 ( .A0(n1846), .A1(n1851), .B0(n1704), .Y(n1841) );
OAI21X1TS U2912 ( .A0(n1854), .A1(n1696), .B0(n1841), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[18]) );
AOI22X1TS U2913 ( .A0(FPADDSUB_Data_array_SWR[44]), .A1(n1698), .B0(
FPADDSUB_Data_array_SWR[40]), .B1(n1699), .Y(n1844) );
AOI22X1TS U2914 ( .A0(n1700), .A1(FPADDSUB_Data_array_SWR[36]), .B0(
FPADDSUB_Data_array_SWR[32]), .B1(n1842), .Y(n1843) );
OAI211X1TS U2915 ( .A0(n2662), .A1(n1845), .B0(n1844), .C0(n1843), .Y(n1848)
);
AOI21X1TS U2916 ( .A0(n1846), .A1(n1848), .B0(n1704), .Y(n1847) );
OAI21X1TS U2917 ( .A0(n1850), .A1(n1696), .B0(n1847), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[19]) );
AOI21X1TS U2918 ( .A0(n1852), .A1(n1848), .B0(n1722), .Y(n1849) );
OAI21X1TS U2919 ( .A0(n1850), .A1(n1721), .B0(n1849), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[6]) );
AOI21X1TS U2920 ( .A0(n1852), .A1(n1851), .B0(n1722), .Y(n1853) );
OAI21X1TS U2921 ( .A0(n1854), .A1(n1721), .B0(n1853), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[7]) );
NOR2BX1TS U2922 ( .AN(FPADDSUB_LZD_output_NRM2_EW[3]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n1855) );
XOR2X1TS U2923 ( .A(n910), .B(n1855), .Y(DP_OP_26J321_124_9022_n15) );
NOR2BX1TS U2924 ( .AN(FPADDSUB_LZD_output_NRM2_EW[4]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n1856) );
XOR2X1TS U2925 ( .A(n910), .B(n1856), .Y(DP_OP_26J321_124_9022_n14) );
NOR2X1TS U2926 ( .A(FPADDSUB_DmP_mant_SFG_SWR[8]), .B(n2634), .Y(n1862) );
AOI22X1TS U2927 ( .A0(FPADDSUB_DMP_SFG[5]), .A1(n2628), .B0(n1858), .B1(
n1857), .Y(n1878) );
AOI222X4TS U2928 ( .A0(n1859), .A1(n2603), .B0(n1859), .B1(n2628), .C0(n2603), .C1(n2628), .Y(n1880) );
AOI22X1TS U2929 ( .A0(n2317), .A1(n1878), .B0(n1880), .B1(n2788), .Y(n1861)
);
OAI31X1TS U2930 ( .A0(n1862), .A1(n1861), .A2(n1879), .B0(n1860), .Y(
FPADDSUB_Raw_mant_SGF[8]) );
OAI21XLTS U2931 ( .A0(n1864), .A1(n921), .B0(n1863), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]) );
AND4X1TS U2932 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_Exp_module_Data_S[2]), .C(FPMULT_Exp_module_Data_S[0]), .D(
FPMULT_Exp_module_Data_S[1]), .Y(n1865) );
AND4X1TS U2933 ( .A(FPMULT_Exp_module_Data_S[6]), .B(
FPMULT_Exp_module_Data_S[5]), .C(FPMULT_Exp_module_Data_S[4]), .D(
n1865), .Y(n1866) );
MX2X1TS U2934 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[0]) );
MX2X1TS U2935 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_exp_oper_result[1]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[1]) );
OR2X2TS U2936 ( .A(FPMULT_FSM_selector_B[1]), .B(n2656), .Y(n2040) );
OAI2BB1X1TS U2937 ( .A0N(FPMULT_Op_MY[24]), .A1N(n2652), .B0(n2040), .Y(
n1867) );
XOR2X1TS U2938 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1867), .Y(
DP_OP_234J321_127_8543_n21) );
MX2X1TS U2939 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[2]) );
OAI2BB1X1TS U2940 ( .A0N(FPMULT_Op_MY[25]), .A1N(n2652), .B0(n2040), .Y(
n1868) );
XOR2X1TS U2941 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1868), .Y(
DP_OP_234J321_127_8543_n20) );
MX2X1TS U2942 ( .A(FPMULT_Op_MX[26]), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[3]) );
OAI2BB1X1TS U2943 ( .A0N(FPMULT_Op_MY[26]), .A1N(n2652), .B0(n2040), .Y(
n1869) );
XOR2X1TS U2944 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1869), .Y(
DP_OP_234J321_127_8543_n19) );
MX2X1TS U2945 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_exp_oper_result[4]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[4]) );
OAI2BB1X1TS U2946 ( .A0N(FPMULT_Op_MY[27]), .A1N(n2652), .B0(n2040), .Y(
n1870) );
XOR2X1TS U2947 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1870), .Y(
DP_OP_234J321_127_8543_n18) );
MX2X1TS U2948 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[5]) );
OAI2BB1X1TS U2949 ( .A0N(FPMULT_Op_MY[28]), .A1N(n2652), .B0(n2040), .Y(
n1871) );
XOR2X1TS U2950 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1871), .Y(
DP_OP_234J321_127_8543_n17) );
MX2X1TS U2951 ( .A(FPMULT_Op_MX[29]), .B(FPMULT_exp_oper_result[6]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[6]) );
OAI2BB1X1TS U2952 ( .A0N(FPMULT_Op_MY[29]), .A1N(n2652), .B0(n2040), .Y(
n1872) );
XOR2X1TS U2953 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1872), .Y(
DP_OP_234J321_127_8543_n16) );
MX2X1TS U2954 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[7]) );
NOR3BX1TS U2955 ( .AN(FPMULT_Op_MY[30]), .B(FPMULT_FSM_selector_B[0]), .C(
FPMULT_FSM_selector_B[1]), .Y(n1873) );
XOR2X1TS U2956 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1873), .Y(
DP_OP_234J321_127_8543_n15) );
CLKAND2X2TS U2957 ( .A(FPMULT_FSM_selector_A), .B(FPMULT_exp_oper_result[8]),
.Y(FPMULT_S_Oper_A_exp[8]) );
INVX2TS U2958 ( .A(n2278), .Y(n2566) );
NAND3BX1TS U2959 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .C(n1874), .Y(n2401) );
NAND3BX1TS U2960 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(n1875),
.C(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .Y(n2400) );
NAND2X1TS U2961 ( .A(n2401), .B(n2400), .Y(n1876) );
AOI22X1TS U2962 ( .A0(n961), .A1(n1876), .B0(begin_operation), .B1(n2551),
.Y(n2563) );
INVX2TS U2963 ( .A(n2564), .Y(n1877) );
AOI211XLTS U2964 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n2566), .B0(n2563), .C0(n1877), .Y(FPADDSUB_enable_Pipeline_input) );
NOR2X1TS U2965 ( .A(FPADDSUB_DmP_mant_SFG_SWR[10]), .B(n2635), .Y(n1883) );
NAND2X1TS U2966 ( .A(FPADDSUB_DmP_mant_SFG_SWR[9]), .B(n2604), .Y(n2312) );
OAI22X1TS U2967 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[8]), .A1(n2634), .B0(n1879),
.B1(n1878), .Y(n2311) );
AOI22X1TS U2968 ( .A0(FPADDSUB_DMP_SFG[7]), .A1(n2629), .B0(n2312), .B1(
n2311), .Y(n1889) );
AOI222X4TS U2969 ( .A0(n2310), .A1(n2604), .B0(n2310), .B1(n2629), .C0(n2604), .C1(n2629), .Y(n1891) );
AOI22X1TS U2970 ( .A0(n2317), .A1(n1889), .B0(n1891), .B1(n2788), .Y(n1882)
);
CLKAND2X2TS U2971 ( .A(FPADDSUB_DmP_mant_SFG_SWR[10]), .B(n2635), .Y(n1890)
);
OAI21XLTS U2972 ( .A0(n1883), .A1(n1890), .B0(n1882), .Y(n1881) );
OAI31X1TS U2973 ( .A0(n1883), .A1(n1882), .A2(n1890), .B0(n1881), .Y(
FPADDSUB_Raw_mant_SGF[10]) );
AOI222X1TS U2974 ( .A0(n2424), .A1(Data_2[30]), .B0(n2493), .B1(
FPSENCOS_d_ff3_sh_x_out[30]), .C0(FPSENCOS_d_ff3_sh_y_out[30]), .C1(
n2482), .Y(n1884) );
INVX2TS U2975 ( .A(n1884), .Y(add_subt_data2[30]) );
AOI221X4TS U2976 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n1912), .B0(
FPADDSUB_Raw_mant_NRM_SWR[25]), .B1(n1897), .C0(n2637), .Y(n2374) );
INVX2TS U2977 ( .A(n1887), .Y(n1898) );
AOI22X1TS U2978 ( .A0(n1912), .A1(FPADDSUB_Raw_mant_NRM_SWR[24]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[1]), .B1(n2739), .Y(n1946) );
INVX2TS U2979 ( .A(n1932), .Y(n1944) );
AOI22X1TS U2980 ( .A0(n1912), .A1(FPADDSUB_Raw_mant_NRM_SWR[25]), .B0(n1940),
.B1(n1944), .Y(n1888) );
NOR2X1TS U2981 ( .A(FPADDSUB_DmP_mant_SFG_SWR[12]), .B(n2638), .Y(n1894) );
NAND2X1TS U2982 ( .A(FPADDSUB_DmP_mant_SFG_SWR[11]), .B(n2605), .Y(n2318) );
OAI22X1TS U2983 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[10]), .A1(n2635), .B0(n1890),
.B1(n1889), .Y(n2316) );
AOI22X1TS U2984 ( .A0(FPADDSUB_DMP_SFG[9]), .A1(n2633), .B0(n2318), .B1(
n2316), .Y(n1976) );
AOI222X4TS U2985 ( .A0(n2315), .A1(n2605), .B0(n2315), .B1(n2633), .C0(n2605), .C1(n2633), .Y(n1978) );
AOI22X1TS U2986 ( .A0(n1031), .A1(n1976), .B0(n1978), .B1(n2788), .Y(n1893)
);
CLKAND2X2TS U2987 ( .A(FPADDSUB_DmP_mant_SFG_SWR[12]), .B(n2638), .Y(n1977)
);
OAI21XLTS U2988 ( .A0(n1894), .A1(n1977), .B0(n1893), .Y(n1892) );
OAI31X1TS U2989 ( .A0(n1894), .A1(n1893), .A2(n1977), .B0(n1892), .Y(
FPADDSUB_Raw_mant_SGF[12]) );
AOI22X1TS U2990 ( .A0(n2739), .A1(FPADDSUB_Raw_mant_NRM_SWR[22]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[20]), .B1(n2637), .Y(n1896) );
AOI222X4TS U2991 ( .A0(n2589), .A1(FPADDSUB_DmP_mant_SHT1_SW[22]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[24]), .B1(n2739), .C0(
FPADDSUB_Raw_mant_NRM_SWR[1]), .C1(n2787), .Y(n2370) );
AOI222X4TS U2992 ( .A0(n2589), .A1(FPADDSUB_DmP_mant_SHT1_SW[21]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[23]), .B1(n2739), .C0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .C1(n2787), .Y(n2372) );
NAND2X1TS U2993 ( .A(n1899), .B(n1898), .Y(n1900) );
BUFX4TS U2994 ( .A(n1900), .Y(n2371) );
OAI22X1TS U2995 ( .A0(n2370), .A1(n1886), .B0(n2372), .B1(n2371), .Y(n1901)
);
AOI21X1TS U2996 ( .A0(n974), .A1(n1972), .B0(n1901), .Y(n1902) );
AOI222X4TS U2997 ( .A0(n2589), .A1(FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(n1912), .B1(FPADDSUB_Raw_mant_NRM_SWR[10]), .C0(FPADDSUB_Raw_mant_NRM_SWR[15]), .C1(
n915), .Y(n1965) );
AOI22X1TS U2998 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n1912), .B0(
FPADDSUB_DmP_mant_SHT1_SW[12]), .B1(n2637), .Y(n1903) );
AOI222X4TS U2999 ( .A0(n2589), .A1(FPADDSUB_DmP_mant_SHT1_SW[15]), .B0(n1912), .B1(FPADDSUB_Raw_mant_NRM_SWR[8]), .C0(FPADDSUB_Raw_mant_NRM_SWR[17]), .C1(
n915), .Y(n1947) );
AOI222X4TS U3000 ( .A0(n2589), .A1(FPADDSUB_DmP_mant_SHT1_SW[14]), .B0(n1912), .B1(FPADDSUB_Raw_mant_NRM_SWR[9]), .C0(FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(
n915), .Y(n1951) );
OAI22X1TS U3001 ( .A0(n1947), .A1(n1895), .B0(n1951), .B1(n1886), .Y(n1904)
);
AOI21X1TS U3002 ( .A0(n974), .A1(n1967), .B0(n1904), .Y(n1905) );
AOI222X4TS U3003 ( .A0(n2589), .A1(FPADDSUB_DmP_mant_SHT1_SW[9]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[11]), .B1(n915), .C0(
FPADDSUB_Raw_mant_NRM_SWR[14]), .C1(n2787), .Y(n1953) );
AOI22X1TS U3004 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n1912), .B0(
FPADDSUB_DmP_mant_SHT1_SW[8]), .B1(n2637), .Y(n1906) );
AOI222X4TS U3005 ( .A0(n2589), .A1(FPADDSUB_DmP_mant_SHT1_SW[11]), .B0(n2787), .B1(FPADDSUB_Raw_mant_NRM_SWR[12]), .C0(FPADDSUB_Raw_mant_NRM_SWR[13]), .C1(
n915), .Y(n1964) );
AOI222X4TS U3006 ( .A0(n2589), .A1(FPADDSUB_DmP_mant_SHT1_SW[10]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[12]), .B1(n915), .C0(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C1(n2787), .Y(n1969) );
OAI22X1TS U3007 ( .A0(n1964), .A1(n1895), .B0(n1969), .B1(n1886), .Y(n1907)
);
AOI21X1TS U3008 ( .A0(n974), .A1(n1955), .B0(n1907), .Y(n1908) );
AOI222X4TS U3009 ( .A0(n2637), .A1(FPADDSUB_DmP_mant_SHT1_SW[5]), .B0(n2787),
.B1(FPADDSUB_Raw_mant_NRM_SWR[18]), .C0(FPADDSUB_Raw_mant_NRM_SWR[7]),
.C1(n915), .Y(n1959) );
AOI22X1TS U3010 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[19]), .A1(n1912), .B0(
FPADDSUB_DmP_mant_SHT1_SW[4]), .B1(n2637), .Y(n1909) );
AOI222X4TS U3011 ( .A0(n2637), .A1(FPADDSUB_DmP_mant_SHT1_SW[7]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n915), .C0(
FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(n2787), .Y(n1952) );
AOI222X4TS U3012 ( .A0(n2589), .A1(FPADDSUB_DmP_mant_SHT1_SW[6]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[8]), .B1(n2739), .C0(
FPADDSUB_Raw_mant_NRM_SWR[17]), .C1(n2787), .Y(n1957) );
OAI22X1TS U3013 ( .A0(n1952), .A1(n1895), .B0(n1957), .B1(n1886), .Y(n1910)
);
AOI21X1TS U3014 ( .A0(n974), .A1(n1961), .B0(n1910), .Y(n1911) );
AOI222X4TS U3015 ( .A0(n2589), .A1(FPADDSUB_DmP_mant_SHT1_SW[17]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[19]), .B1(n2739), .C0(
FPADDSUB_Raw_mant_NRM_SWR[6]), .C1(n2787), .Y(n1948) );
AOI22X1TS U3016 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(n1912), .B0(
FPADDSUB_DmP_mant_SHT1_SW[16]), .B1(n2637), .Y(n1913) );
AOI222X4TS U3017 ( .A0(n2589), .A1(FPADDSUB_DmP_mant_SHT1_SW[19]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[21]), .B1(n2739), .C0(
FPADDSUB_Raw_mant_NRM_SWR[4]), .C1(n2787), .Y(n1970) );
AOI222X4TS U3018 ( .A0(n2589), .A1(FPADDSUB_DmP_mant_SHT1_SW[18]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[20]), .B1(n2739), .C0(
FPADDSUB_Raw_mant_NRM_SWR[5]), .C1(n2787), .Y(n1975) );
OAI22X1TS U3019 ( .A0(n1970), .A1(n1895), .B0(n1975), .B1(n1886), .Y(n1914)
);
AOI21X1TS U3020 ( .A0(n974), .A1(n980), .B0(n1914), .Y(n1915) );
INVX2TS U3021 ( .A(n2371), .Y(n1928) );
AOI222X4TS U3022 ( .A0(n2637), .A1(FPADDSUB_DmP_mant_SHT1_SW[3]), .B0(n2787),
.B1(FPADDSUB_Raw_mant_NRM_SWR[20]), .C0(FPADDSUB_Raw_mant_NRM_SWR[5]),
.C1(n915), .Y(n1958) );
AOI222X4TS U3023 ( .A0(n2637), .A1(FPADDSUB_DmP_mant_SHT1_SW[2]), .B0(n2787),
.B1(FPADDSUB_Raw_mant_NRM_SWR[21]), .C0(FPADDSUB_Raw_mant_NRM_SWR[4]),
.C1(n915), .Y(n1963) );
OAI22X1TS U3024 ( .A0(n1958), .A1(n1895), .B0(n1963), .B1(n1886), .Y(n1917)
);
AOI21X1TS U3025 ( .A0(n1928), .A1(n1944), .B0(n1917), .Y(n1918) );
OAI22X1TS U3026 ( .A0(n1975), .A1(n1895), .B0(n1948), .B1(n1886), .Y(n1919)
);
AOI21X1TS U3027 ( .A0(n1928), .A1(n980), .B0(n1919), .Y(n1920) );
OAI22X1TS U3028 ( .A0(n1969), .A1(n1895), .B0(n1953), .B1(n1886), .Y(n1921)
);
AOI21X1TS U3029 ( .A0(n1928), .A1(n1955), .B0(n1921), .Y(n1922) );
OAI22X1TS U3030 ( .A0(n2370), .A1(n1895), .B0(n2372), .B1(n1886), .Y(n1923)
);
AOI21X1TS U3031 ( .A0(n1928), .A1(n1972), .B0(n1923), .Y(n1924) );
OAI22X1TS U3032 ( .A0(n1957), .A1(n1895), .B0(n1959), .B1(n1886), .Y(n1925)
);
AOI21X1TS U3033 ( .A0(n1928), .A1(n1961), .B0(n1925), .Y(n1926) );
OAI22X1TS U3034 ( .A0(n1951), .A1(n1895), .B0(n1965), .B1(n1886), .Y(n1927)
);
AOI21X1TS U3035 ( .A0(n1928), .A1(n1967), .B0(n1927), .Y(n1929) );
OAI22X1TS U3036 ( .A0(n1958), .A1(n1886), .B0(n1963), .B1(n2371), .Y(n1930)
);
AOI21X1TS U3037 ( .A0(n1940), .A1(n1961), .B0(n1930), .Y(n1931) );
OAI22X1TS U3038 ( .A0(n1952), .A1(n1886), .B0(n1957), .B1(n2371), .Y(n1933)
);
AOI21X1TS U3039 ( .A0(n1940), .A1(n1955), .B0(n1933), .Y(n1934) );
OAI22X1TS U3040 ( .A0(n1964), .A1(n1886), .B0(n1969), .B1(n2371), .Y(n1935)
);
AOI21X1TS U3041 ( .A0(n1940), .A1(n1967), .B0(n1935), .Y(n1936) );
OAI22X1TS U3042 ( .A0(n1947), .A1(n1886), .B0(n1951), .B1(n2371), .Y(n1937)
);
AOI21X1TS U3043 ( .A0(n1940), .A1(n980), .B0(n1937), .Y(n1938) );
OAI22X1TS U3044 ( .A0(n1970), .A1(n1886), .B0(n1975), .B1(n2371), .Y(n1939)
);
AOI21X1TS U3045 ( .A0(n1940), .A1(n1972), .B0(n1939), .Y(n1941) );
OAI22X1TS U3046 ( .A0(n1963), .A1(n1895), .B0(n1942), .B1(n2371), .Y(n1943)
);
AOI21X1TS U3047 ( .A0(n1973), .A1(n1944), .B0(n1943), .Y(n1945) );
OAI22X1TS U3048 ( .A0(n1948), .A1(n1895), .B0(n1947), .B1(n2371), .Y(n1949)
);
AOI21X1TS U3049 ( .A0(n1973), .A1(n980), .B0(n1949), .Y(n1950) );
OAI22X1TS U3050 ( .A0(n1953), .A1(n1895), .B0(n1952), .B1(n2371), .Y(n1954)
);
AOI21X1TS U3051 ( .A0(n1973), .A1(n1955), .B0(n1954), .Y(n1956) );
OAI22X1TS U3052 ( .A0(n1959), .A1(n1895), .B0(n1958), .B1(n2371), .Y(n1960)
);
AOI21X1TS U3053 ( .A0(n1973), .A1(n1961), .B0(n1960), .Y(n1962) );
OAI22X1TS U3054 ( .A0(n1965), .A1(n1895), .B0(n1964), .B1(n2371), .Y(n1966)
);
AOI21X1TS U3055 ( .A0(n1973), .A1(n1967), .B0(n1966), .Y(n1968) );
OAI22X1TS U3056 ( .A0(n2372), .A1(n1895), .B0(n1970), .B1(n2371), .Y(n1971)
);
AOI21X1TS U3057 ( .A0(n1973), .A1(n1972), .B0(n1971), .Y(n1974) );
NOR2X1TS U3058 ( .A(FPADDSUB_DmP_mant_SFG_SWR[14]), .B(n2640), .Y(n1981) );
NAND2X1TS U3059 ( .A(FPADDSUB_DmP_mant_SFG_SWR[13]), .B(n2606), .Y(n2323) );
OAI22X1TS U3060 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[12]), .A1(n2638), .B0(n1977),
.B1(n1976), .Y(n2322) );
AOI22X1TS U3061 ( .A0(FPADDSUB_DMP_SFG[11]), .A1(n2639), .B0(n2323), .B1(
n2322), .Y(n1982) );
AOI222X4TS U3062 ( .A0(n2321), .A1(n2606), .B0(n2321), .B1(n2639), .C0(n2606), .C1(n2639), .Y(n1984) );
AOI22X1TS U3063 ( .A0(n1031), .A1(n1982), .B0(n1984), .B1(n2788), .Y(n1980)
);
CLKAND2X2TS U3064 ( .A(FPADDSUB_DmP_mant_SFG_SWR[14]), .B(n2640), .Y(n1983)
);
OAI21XLTS U3065 ( .A0(n1981), .A1(n1983), .B0(n1980), .Y(n1979) );
OAI31X1TS U3066 ( .A0(n1981), .A1(n1980), .A2(n1983), .B0(n1979), .Y(
FPADDSUB_Raw_mant_SGF[14]) );
NAND2X1TS U3067 ( .A(FPMULT_Sgf_normalized_result[6]), .B(n2109), .Y(n2108)
);
NAND2X1TS U3068 ( .A(FPMULT_Sgf_normalized_result[8]), .B(n2106), .Y(n2105)
);
NAND2X1TS U3069 ( .A(FPMULT_Sgf_normalized_result[10]), .B(n2103), .Y(n2102)
);
NAND2X1TS U3070 ( .A(FPMULT_Sgf_normalized_result[12]), .B(n2100), .Y(n2099)
);
NAND2X1TS U3071 ( .A(FPMULT_Sgf_normalized_result[14]), .B(n2097), .Y(n2096)
);
NAND2X1TS U3072 ( .A(FPMULT_Sgf_normalized_result[16]), .B(n2094), .Y(n2093)
);
NAND2X1TS U3073 ( .A(FPMULT_Sgf_normalized_result[18]), .B(n2091), .Y(n2090)
);
NAND2X1TS U3074 ( .A(FPMULT_Sgf_normalized_result[20]), .B(n2088), .Y(n2087)
);
NAND2X1TS U3075 ( .A(FPMULT_Sgf_normalized_result[22]), .B(n2085), .Y(n2084)
);
NOR2X1TS U3076 ( .A(n2084), .B(n1013), .Y(FPMULT_Adder_M_result_A_adder[24])
);
NOR2X1TS U3077 ( .A(FPADDSUB_DmP_mant_SFG_SWR[16]), .B(n2643), .Y(n1987) );
NAND2X1TS U3078 ( .A(FPADDSUB_DmP_mant_SFG_SWR[15]), .B(n2607), .Y(n2328) );
OAI22X1TS U3079 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[14]), .A1(n2640), .B0(n1983),
.B1(n1982), .Y(n2327) );
AOI22X1TS U3080 ( .A0(FPADDSUB_DMP_SFG[13]), .A1(n2644), .B0(n2328), .B1(
n2327), .Y(n1988) );
AOI222X4TS U3081 ( .A0(n2326), .A1(n2607), .B0(n2326), .B1(n2644), .C0(n2607), .C1(n2644), .Y(n1990) );
AOI22X1TS U3082 ( .A0(n1031), .A1(n1988), .B0(n1990), .B1(n2788), .Y(n1986)
);
CLKAND2X2TS U3083 ( .A(FPADDSUB_DmP_mant_SFG_SWR[16]), .B(n2643), .Y(n1989)
);
OAI31X1TS U3084 ( .A0(n1987), .A1(n1986), .A2(n1989), .B0(n1985), .Y(
FPADDSUB_Raw_mant_SGF[16]) );
NOR2X1TS U3085 ( .A(FPADDSUB_DmP_mant_SFG_SWR[18]), .B(n2657), .Y(n1993) );
NAND2X1TS U3086 ( .A(FPADDSUB_DmP_mant_SFG_SWR[17]), .B(n2609), .Y(n2333) );
OAI22X1TS U3087 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[16]), .A1(n2643), .B0(n1989),
.B1(n1988), .Y(n2332) );
AOI22X1TS U3088 ( .A0(FPADDSUB_DMP_SFG[15]), .A1(n2650), .B0(n2333), .B1(
n2332), .Y(n1994) );
AOI222X4TS U3089 ( .A0(n2331), .A1(n2609), .B0(n2331), .B1(n2650), .C0(n2609), .C1(n2650), .Y(n1996) );
AOI22X1TS U3090 ( .A0(n1031), .A1(n1994), .B0(n1996), .B1(n2788), .Y(n1992)
);
CLKAND2X2TS U3091 ( .A(FPADDSUB_DmP_mant_SFG_SWR[18]), .B(n2657), .Y(n1995)
);
OAI31X1TS U3092 ( .A0(n1993), .A1(n1992), .A2(n1995), .B0(n1991), .Y(
FPADDSUB_Raw_mant_SGF[18]) );
NOR2X1TS U3093 ( .A(FPADDSUB_DmP_mant_SFG_SWR[20]), .B(n2660), .Y(n1999) );
NAND2X1TS U3094 ( .A(FPADDSUB_DmP_mant_SFG_SWR[19]), .B(n2611), .Y(n2338) );
OAI22X1TS U3095 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[18]), .A1(n2657), .B0(n1995),
.B1(n1994), .Y(n2337) );
AOI22X1TS U3096 ( .A0(FPADDSUB_DMP_SFG[17]), .A1(n2658), .B0(n2338), .B1(
n2337), .Y(n2000) );
AOI222X4TS U3097 ( .A0(n2336), .A1(n2611), .B0(n2336), .B1(n2658), .C0(n2611), .C1(n2658), .Y(n2002) );
AOI22X1TS U3098 ( .A0(n1031), .A1(n2000), .B0(n2002), .B1(n2788), .Y(n1998)
);
CLKAND2X2TS U3099 ( .A(FPADDSUB_DmP_mant_SFG_SWR[20]), .B(n2660), .Y(n2001)
);
OAI31X1TS U3100 ( .A0(n1999), .A1(n1998), .A2(n2001), .B0(n1997), .Y(
FPADDSUB_Raw_mant_SGF[20]) );
INVX2TS U3101 ( .A(intadd_1083_SUM_1_), .Y(intadd_1082_CI) );
INVX2TS U3102 ( .A(intadd_1083_SUM_2_), .Y(intadd_1082_B_1_) );
INVX2TS U3103 ( .A(intadd_1083_SUM_3_), .Y(intadd_1082_B_2_) );
INVX2TS U3104 ( .A(intadd_1083_SUM_4_), .Y(intadd_1082_B_3_) );
INVX2TS U3105 ( .A(intadd_1083_SUM_5_), .Y(intadd_1082_B_4_) );
INVX2TS U3106 ( .A(intadd_1083_SUM_6_), .Y(intadd_1082_B_5_) );
INVX2TS U3107 ( .A(intadd_1083_SUM_7_), .Y(intadd_1082_B_6_) );
INVX2TS U3108 ( .A(intadd_1083_SUM_8_), .Y(intadd_1082_B_7_) );
INVX2TS U3109 ( .A(intadd_1083_SUM_9_), .Y(intadd_1082_B_8_) );
INVX2TS U3110 ( .A(intadd_1083_SUM_10_), .Y(intadd_1082_B_9_) );
INVX2TS U3111 ( .A(intadd_1083_SUM_11_), .Y(intadd_1082_B_10_) );
INVX2TS U3112 ( .A(intadd_1083_SUM_12_), .Y(intadd_1082_B_11_) );
INVX2TS U3113 ( .A(intadd_1083_SUM_13_), .Y(intadd_1082_B_12_) );
INVX2TS U3114 ( .A(intadd_1083_SUM_14_), .Y(intadd_1082_B_13_) );
INVX2TS U3115 ( .A(intadd_1083_SUM_15_), .Y(intadd_1082_B_14_) );
INVX2TS U3116 ( .A(intadd_1083_SUM_16_), .Y(intadd_1082_B_15_) );
INVX2TS U3117 ( .A(intadd_1083_SUM_17_), .Y(intadd_1082_B_16_) );
INVX2TS U3118 ( .A(intadd_1083_SUM_18_), .Y(intadd_1082_B_17_) );
INVX2TS U3119 ( .A(intadd_1083_SUM_19_), .Y(intadd_1082_B_18_) );
INVX2TS U3120 ( .A(intadd_1083_SUM_20_), .Y(intadd_1082_B_19_) );
INVX2TS U3121 ( .A(intadd_1083_SUM_21_), .Y(intadd_1082_B_20_) );
INVX2TS U3122 ( .A(intadd_1083_SUM_22_), .Y(intadd_1082_B_21_) );
INVX2TS U3123 ( .A(intadd_1083_SUM_23_), .Y(intadd_1082_B_22_) );
INVX2TS U3124 ( .A(intadd_1083_SUM_24_), .Y(intadd_1082_B_23_) );
INVX2TS U3125 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[24]), .Y(
intadd_1083_A_24_) );
NOR2X1TS U3126 ( .A(FPADDSUB_DmP_mant_SFG_SWR[22]), .B(n2685), .Y(n2005) );
NAND2X1TS U3127 ( .A(FPADDSUB_DmP_mant_SFG_SWR[21]), .B(n2612), .Y(n2343) );
OAI22X1TS U3128 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[20]), .A1(n2660), .B0(n2001),
.B1(n2000), .Y(n2342) );
AOI22X1TS U3129 ( .A0(FPADDSUB_DMP_SFG[19]), .A1(n2661), .B0(n2343), .B1(
n2342), .Y(n2032) );
AOI222X4TS U3130 ( .A0(n2341), .A1(n2612), .B0(n2341), .B1(n2661), .C0(n2612), .C1(n2661), .Y(n2034) );
AOI22X1TS U3131 ( .A0(n1031), .A1(n2032), .B0(n2034), .B1(n2352), .Y(n2004)
);
CLKAND2X2TS U3132 ( .A(FPADDSUB_DmP_mant_SFG_SWR[22]), .B(n2685), .Y(n2033)
);
OAI31X1TS U3133 ( .A0(n2005), .A1(n2004), .A2(n2033), .B0(n2003), .Y(
FPADDSUB_Raw_mant_SGF[22]) );
INVX2TS U3134 ( .A(n2006), .Y(n2008) );
NOR2XLTS U3135 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(
FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n2007) );
OAI22X1TS U3136 ( .A0(n2009), .A1(n2008), .B0(n2007), .B1(n2021), .Y(n2010)
);
AOI21X1TS U3137 ( .A0(n2011), .A1(FPADDSUB_Raw_mant_NRM_SWR[3]), .B0(n2010),
.Y(n2012) );
OAI211X1TS U3138 ( .A0(n2014), .A1(n2694), .B0(n2013), .C0(n2012), .Y(
FPADDSUB_LZD_raw_out_EWR[2]) );
INVX2TS U3139 ( .A(n2015), .Y(n2017) );
NOR3X1TS U3140 ( .A(FPADDSUB_Raw_mant_NRM_SWR[2]), .B(n2031), .C(n2642), .Y(
n2027) );
AOI211X1TS U3141 ( .A0(n2018), .A1(n2017), .B0(n2016), .C0(n2027), .Y(n2020)
);
OAI211X1TS U3142 ( .A0(n2022), .A1(n2021), .B0(n2020), .C0(n2019), .Y(
FPADDSUB_LZD_raw_out_EWR[3]) );
OAI31X1TS U3143 ( .A0(n2025), .A1(FPADDSUB_Raw_mant_NRM_SWR[10]), .A2(n2024),
.B0(n2023), .Y(n2026) );
AOI211X1TS U3144 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[5]), .A1(n2028), .B0(n2027),
.C0(n2026), .Y(n2029) );
OAI211X1TS U3145 ( .A0(n2725), .A1(n2031), .B0(n2030), .C0(n2029), .Y(
FPADDSUB_LZD_raw_out_EWR[4]) );
NOR2X1TS U3146 ( .A(FPADDSUB_DmP_mant_SFG_SWR[24]), .B(n2692), .Y(n2351) );
NAND2X1TS U3147 ( .A(FPADDSUB_DmP_mant_SFG_SWR[23]), .B(n2620), .Y(n2348) );
OAI22X1TS U3148 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[22]), .A1(n2685), .B0(n2033),
.B1(n2032), .Y(n2347) );
AOI22X1TS U3149 ( .A0(FPADDSUB_DMP_SFG[21]), .A1(n2686), .B0(n2348), .B1(
n2347), .Y(n2354) );
AOI21X1TS U3150 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(n2692), .B0(n2354),
.Y(n2035) );
AOI222X4TS U3151 ( .A0(n2346), .A1(n2620), .B0(n2346), .B1(n2686), .C0(n2620), .C1(n2686), .Y(n2353) );
OAI32X1TS U3152 ( .A0(n2352), .A1(n2351), .A2(n2035), .B0(n2117), .B1(n2317),
.Y(n2036) );
NOR3XLTS U3153 ( .A(FPSENCOS_cont_var_out[1]), .B(n2649), .C(n954), .Y(
FPSENCOS_enab_d_ff4_Yn) );
NOR3XLTS U3154 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.C(n954), .Y(FPSENCOS_enab_d_ff4_Xn) );
OAI21XLTS U3155 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(n910), .B0(n2037),
.Y(n810) );
OAI21XLTS U3156 ( .A0(n2552), .A1(n2651), .B0(n2554), .Y(n859) );
INVX2TS U3157 ( .A(n2400), .Y(n2398) );
NOR2X1TS U3158 ( .A(n989), .B(n2398), .Y(n2394) );
NAND2X1TS U3159 ( .A(n2394), .B(n954), .Y(n2568) );
INVX2TS U3160 ( .A(n2568), .Y(n2567) );
OAI21XLTS U3161 ( .A0(n2567), .A1(n2649), .B0(FPSENCOS_cont_var_out[1]), .Y(
n2038) );
XNOR2X1TS U3162 ( .A(DP_OP_234J321_127_8543_n1), .B(n2039), .Y(
FPMULT_Exp_module_Overflow_A) );
NOR2XLTS U3163 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n2041) );
OAI21XLTS U3164 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n2041), .B0(n2040), .Y(
n2042) );
XOR2X1TS U3165 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n2042), .Y(
DP_OP_234J321_127_8543_n22) );
NOR2BX1TS U3166 ( .AN(FPADDSUB_LZD_output_NRM2_EW[2]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2043) );
XOR2X1TS U3167 ( .A(n910), .B(n2043), .Y(DP_OP_26J321_124_9022_n16) );
NOR2BX1TS U3168 ( .AN(FPADDSUB_LZD_output_NRM2_EW[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2044) );
XOR2X1TS U3169 ( .A(n910), .B(n2044), .Y(DP_OP_26J321_124_9022_n17) );
OR2X1TS U3170 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .B(
FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n2045) );
XOR2X1TS U3171 ( .A(n910), .B(n2045), .Y(DP_OP_26J321_124_9022_n18) );
BUFX3TS U3172 ( .A(n2789), .Y(n2786) );
AO21XLTS U3173 ( .A0(n2047), .A1(FPMULT_FSM_selector_B[1]), .B0(n2046), .Y(
n829) );
NOR2BX1TS U3174 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B(n2831), .Y(
FPADDSUB_formatted_number_W[30]) );
AOI2BB1XLTS U3175 ( .A0N(n2830), .A1N(FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(
n2831), .Y(FPADDSUB_formatted_number_W[31]) );
INVX2TS U3176 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[1]), .Y(n2048) );
NOR2X1TS U3177 ( .A(n2048), .B(FPMULT_Sgf_operation_EVEN1_Q_middle[1]), .Y(
intadd_1083_A_2_) );
AOI21X1TS U3178 ( .A0(FPMULT_Sgf_operation_EVEN1_Q_middle[1]), .A1(n2048),
.B0(intadd_1083_A_2_), .Y(intadd_1083_B_1_) );
INVX2TS U3179 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[2]), .Y(n2049) );
CMPR32X2TS U3180 ( .A(FPMULT_Sgf_operation_Result[2]), .B(n2049), .C(
FPMULT_Sgf_operation_EVEN1_Q_left[2]), .CO(intadd_1083_B_3_), .S(
intadd_1083_B_2_) );
INVX2TS U3181 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[3]), .Y(n2050) );
CMPR32X2TS U3182 ( .A(FPMULT_Sgf_operation_Result[3]), .B(n2050), .C(
FPMULT_Sgf_operation_EVEN1_Q_left[3]), .CO(intadd_1083_B_4_), .S(
intadd_1083_A_3_) );
INVX2TS U3183 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[4]), .Y(n2051) );
CMPR32X2TS U3184 ( .A(FPMULT_Sgf_operation_Result[4]), .B(n2051), .C(
FPMULT_Sgf_operation_EVEN1_Q_left[4]), .CO(intadd_1083_B_5_), .S(
intadd_1083_A_4_) );
INVX2TS U3185 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[5]), .Y(n2052) );
CMPR32X2TS U3186 ( .A(FPMULT_Sgf_operation_Result[5]), .B(n2052), .C(
FPMULT_Sgf_operation_EVEN1_Q_left[5]), .CO(intadd_1083_B_6_), .S(
intadd_1083_A_5_) );
INVX2TS U3187 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[6]), .Y(n2053) );
CMPR32X2TS U3188 ( .A(FPMULT_Sgf_operation_Result[6]), .B(n2053), .C(
FPMULT_Sgf_operation_EVEN1_Q_left[6]), .CO(intadd_1083_B_7_), .S(
intadd_1083_A_6_) );
INVX2TS U3189 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[7]), .Y(n2054) );
CMPR32X2TS U3190 ( .A(FPMULT_Sgf_operation_Result[7]), .B(n2054), .C(
FPMULT_Sgf_operation_EVEN1_Q_left[7]), .CO(intadd_1083_B_8_), .S(
intadd_1083_A_7_) );
INVX2TS U3191 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[8]), .Y(n2055) );
CMPR32X2TS U3192 ( .A(FPMULT_Sgf_operation_Result[8]), .B(n2055), .C(
FPMULT_Sgf_operation_EVEN1_Q_left[8]), .CO(intadd_1083_B_9_), .S(
intadd_1083_A_8_) );
INVX2TS U3193 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[9]), .Y(n2056) );
CMPR32X2TS U3194 ( .A(FPMULT_Sgf_operation_Result[9]), .B(n2056), .C(
FPMULT_Sgf_operation_EVEN1_Q_left[9]), .CO(intadd_1083_B_10_), .S(
intadd_1083_A_9_) );
INVX2TS U3195 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[10]), .Y(n2057) );
CMPR32X2TS U3196 ( .A(FPMULT_Sgf_operation_Result[10]), .B(n2057), .C(
FPMULT_Sgf_operation_EVEN1_Q_left[10]), .CO(intadd_1083_B_11_), .S(
intadd_1083_A_10_) );
INVX2TS U3197 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[11]), .Y(n2058) );
CMPR32X2TS U3198 ( .A(FPMULT_Sgf_operation_Result[11]), .B(n2058), .C(
FPMULT_Sgf_operation_EVEN1_Q_left[11]), .CO(intadd_1083_B_12_), .S(
intadd_1083_A_11_) );
INVX2TS U3199 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[12]), .Y(n2059) );
CMPR32X2TS U3200 ( .A(n2059), .B(FPMULT_Sgf_operation_EVEN1_Q_right[12]),
.C(FPMULT_Sgf_operation_EVEN1_Q_left[12]), .CO(intadd_1083_B_13_), .S(
intadd_1083_A_12_) );
INVX2TS U3201 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[13]), .Y(n2060) );
CMPR32X2TS U3202 ( .A(n2060), .B(FPMULT_Sgf_operation_EVEN1_Q_right[13]),
.C(FPMULT_Sgf_operation_EVEN1_Q_left[13]), .CO(intadd_1083_B_14_), .S(
intadd_1083_A_13_) );
INVX2TS U3203 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[14]), .Y(n2061) );
CMPR32X2TS U3204 ( .A(n2061), .B(FPMULT_Sgf_operation_EVEN1_Q_right[14]),
.C(FPMULT_Sgf_operation_EVEN1_Q_left[14]), .CO(intadd_1083_B_15_), .S(
intadd_1083_A_14_) );
INVX2TS U3205 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[15]), .Y(n2062) );
CMPR32X2TS U3206 ( .A(n2062), .B(FPMULT_Sgf_operation_EVEN1_Q_right[15]),
.C(FPMULT_Sgf_operation_EVEN1_Q_left[15]), .CO(intadd_1083_B_16_), .S(
intadd_1083_A_15_) );
INVX2TS U3207 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[16]), .Y(n2063) );
CMPR32X2TS U3208 ( .A(n2063), .B(FPMULT_Sgf_operation_EVEN1_Q_right[16]),
.C(FPMULT_Sgf_operation_EVEN1_Q_left[16]), .CO(intadd_1083_B_17_), .S(
intadd_1083_A_16_) );
INVX2TS U3209 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[17]), .Y(n2064) );
CMPR32X2TS U3210 ( .A(n2064), .B(FPMULT_Sgf_operation_EVEN1_Q_right[17]),
.C(FPMULT_Sgf_operation_EVEN1_Q_left[17]), .CO(intadd_1083_B_18_), .S(
intadd_1083_A_17_) );
INVX2TS U3211 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[18]), .Y(n2065) );
CMPR32X2TS U3212 ( .A(n2065), .B(FPMULT_Sgf_operation_EVEN1_Q_right[18]),
.C(FPMULT_Sgf_operation_EVEN1_Q_left[18]), .CO(intadd_1083_B_19_), .S(
intadd_1083_A_18_) );
INVX2TS U3213 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[19]), .Y(n2066) );
CMPR32X2TS U3214 ( .A(n2066), .B(FPMULT_Sgf_operation_EVEN1_Q_right[19]),
.C(FPMULT_Sgf_operation_EVEN1_Q_left[19]), .CO(intadd_1083_B_20_), .S(
intadd_1083_A_19_) );
INVX2TS U3215 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[20]), .Y(n2067) );
CMPR32X2TS U3216 ( .A(n2067), .B(FPMULT_Sgf_operation_EVEN1_Q_right[20]),
.C(FPMULT_Sgf_operation_EVEN1_Q_left[20]), .CO(intadd_1083_B_21_), .S(
intadd_1083_A_20_) );
INVX2TS U3217 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[21]), .Y(n2068) );
CMPR32X2TS U3218 ( .A(n2068), .B(FPMULT_Sgf_operation_EVEN1_Q_right[21]),
.C(FPMULT_Sgf_operation_EVEN1_Q_left[21]), .CO(intadd_1083_B_22_), .S(
intadd_1083_A_21_) );
INVX2TS U3219 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[22]), .Y(n2069) );
CMPR32X2TS U3220 ( .A(n2069), .B(FPMULT_Sgf_operation_EVEN1_Q_right[22]),
.C(FPMULT_Sgf_operation_EVEN1_Q_left[22]), .CO(intadd_1083_B_23_), .S(
intadd_1083_A_22_) );
INVX2TS U3221 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[23]), .Y(n2070) );
CMPR32X2TS U3222 ( .A(n2070), .B(FPMULT_Sgf_operation_EVEN1_Q_left[23]), .C(
FPMULT_Sgf_operation_EVEN1_Q_right[23]), .CO(intadd_1083_B_24_), .S(
intadd_1083_A_23_) );
XOR2X1TS U3223 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[25]), .B(
intadd_1083_n1), .Y(intadd_1082_B_24_) );
NAND3X1TS U3224 ( .A(intadd_1082_n1), .B(
FPMULT_Sgf_operation_EVEN1_Q_left[14]), .C(
FPMULT_Sgf_operation_EVEN1_Q_left[15]), .Y(n2080) );
NOR2X2TS U3225 ( .A(n2079), .B(n2080), .Y(n2078) );
NAND2X1TS U3226 ( .A(n2078), .B(FPMULT_Sgf_operation_EVEN1_Q_left[17]), .Y(
n2077) );
NOR2X2TS U3227 ( .A(n2076), .B(n2077), .Y(n2075) );
NAND2X1TS U3228 ( .A(n2075), .B(FPMULT_Sgf_operation_EVEN1_Q_left[19]), .Y(
n2074) );
NOR2X2TS U3229 ( .A(n2073), .B(n2074), .Y(n2072) );
NAND2X1TS U3230 ( .A(n2072), .B(FPMULT_Sgf_operation_EVEN1_Q_left[21]), .Y(
n2071) );
INVX2TS U3231 ( .A(n2071), .Y(n2082) );
OA21XLTS U3232 ( .A0(n2072), .A1(FPMULT_Sgf_operation_EVEN1_Q_left[21]),
.B0(n2071), .Y(FPMULT_Sgf_operation_Result[45]) );
AOI21X1TS U3233 ( .A0(n2074), .A1(n2073), .B0(n2072), .Y(
FPMULT_Sgf_operation_Result[44]) );
OA21XLTS U3234 ( .A0(n2075), .A1(FPMULT_Sgf_operation_EVEN1_Q_left[19]),
.B0(n2074), .Y(FPMULT_Sgf_operation_Result[43]) );
AOI21X1TS U3235 ( .A0(n2077), .A1(n2076), .B0(n2075), .Y(
FPMULT_Sgf_operation_Result[42]) );
OA21XLTS U3236 ( .A0(n2078), .A1(FPMULT_Sgf_operation_EVEN1_Q_left[17]),
.B0(n2077), .Y(FPMULT_Sgf_operation_Result[41]) );
AOI21X1TS U3237 ( .A0(n2080), .A1(n2079), .B0(n2078), .Y(
FPMULT_Sgf_operation_Result[40]) );
OA21XLTS U3238 ( .A0(n2081), .A1(FPMULT_Sgf_operation_EVEN1_Q_left[15]),
.B0(n2080), .Y(FPMULT_Sgf_operation_Result[39]) );
NAND2X1TS U3239 ( .A(n2082), .B(FPMULT_Sgf_operation_EVEN1_Q_left[22]), .Y(
n2083) );
XNOR2X1TS U3240 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[23]), .B(n2083), .Y(
FPMULT_Sgf_operation_Result[47]) );
AOI21X1TS U3241 ( .A0(n2084), .A1(n1013), .B0(
FPMULT_Adder_M_result_A_adder[24]), .Y(
FPMULT_Adder_M_result_A_adder[23]) );
OA21XLTS U3242 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n2085), .B0(
n2084), .Y(FPMULT_Adder_M_result_A_adder[22]) );
AOI21X1TS U3243 ( .A0(n2086), .A1(n2087), .B0(n2085), .Y(
FPMULT_Adder_M_result_A_adder[21]) );
OA21XLTS U3244 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n2088), .B0(
n2087), .Y(FPMULT_Adder_M_result_A_adder[20]) );
AOI21X1TS U3245 ( .A0(n2089), .A1(n2090), .B0(n2088), .Y(
FPMULT_Adder_M_result_A_adder[19]) );
OA21XLTS U3246 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n2091), .B0(
n2090), .Y(FPMULT_Adder_M_result_A_adder[18]) );
AOI21X1TS U3247 ( .A0(n2092), .A1(n2093), .B0(n2091), .Y(
FPMULT_Adder_M_result_A_adder[17]) );
OA21XLTS U3248 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n2094), .B0(
n2093), .Y(FPMULT_Adder_M_result_A_adder[16]) );
AOI21X1TS U3249 ( .A0(n2095), .A1(n2096), .B0(n2094), .Y(
FPMULT_Adder_M_result_A_adder[15]) );
OA21XLTS U3250 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n2097), .B0(
n2096), .Y(FPMULT_Adder_M_result_A_adder[14]) );
AOI21X1TS U3251 ( .A0(n2098), .A1(n2099), .B0(n2097), .Y(
FPMULT_Adder_M_result_A_adder[13]) );
OA21XLTS U3252 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n2100), .B0(
n2099), .Y(FPMULT_Adder_M_result_A_adder[12]) );
AOI21X1TS U3253 ( .A0(n2101), .A1(n2102), .B0(n2100), .Y(
FPMULT_Adder_M_result_A_adder[11]) );
OA21XLTS U3254 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n2103), .B0(
n2102), .Y(FPMULT_Adder_M_result_A_adder[10]) );
AOI21X1TS U3255 ( .A0(n2104), .A1(n2105), .B0(n2103), .Y(
FPMULT_Adder_M_result_A_adder[9]) );
OA21XLTS U3256 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n2106), .B0(n2105), .Y(FPMULT_Adder_M_result_A_adder[8]) );
AOI21X1TS U3257 ( .A0(n2107), .A1(n2108), .B0(n2106), .Y(
FPMULT_Adder_M_result_A_adder[7]) );
OA21XLTS U3258 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n2109), .B0(n2108), .Y(FPMULT_Adder_M_result_A_adder[6]) );
AOI21X1TS U3259 ( .A0(n2114), .A1(n2110), .B0(n2109), .Y(
FPMULT_Adder_M_result_A_adder[5]) );
AOI21X1TS U3260 ( .A0(n2112), .A1(n2111), .B0(n2115), .Y(
FPMULT_Adder_M_result_A_adder[3]) );
AO21XLTS U3261 ( .A0(FPMULT_Sgf_normalized_result[2]), .A1(n2113), .B0(n2112), .Y(FPMULT_Adder_M_result_A_adder[2]) );
AO21XLTS U3262 ( .A0(n2115), .A1(FPMULT_Sgf_normalized_result[4]), .B0(n2114), .Y(FPMULT_Adder_M_result_A_adder[4]) );
XOR2XLTS U3263 ( .A(FPADDSUB_DMP_EXP_EWSW[27]), .B(FPADDSUB_DmP_EXP_EWSW[27]), .Y(n2116) );
XOR2XLTS U3264 ( .A(intadd_1086_n1), .B(n2116), .Y(
FPADDSUB_Shift_amount_EXP_EW[4]) );
AOI21X1TS U3265 ( .A0(n2117), .A1(n1015), .B0(n2317), .Y(n2832) );
BUFX4TS U3266 ( .A(n2424), .Y(n2504) );
NOR2BX1TS U3267 ( .AN(operation[0]), .B(n2504), .Y(n2837) );
AOI2BB2XLTS U3268 ( .B0(FPSENCOS_cont_var_out[0]), .B1(
FPSENCOS_d_ff3_sign_out), .A0N(FPSENCOS_d_ff3_sign_out), .A1N(
FPSENCOS_cont_var_out[0]), .Y(n2118) );
AO22XLTS U3269 ( .A0(operation[1]), .A1(n2118), .B0(n2504), .B1(operation[0]), .Y(n2121) );
AOI222X1TS U3270 ( .A0(n2424), .A1(Data_2[31]), .B0(n2493), .B1(
FPSENCOS_d_ff3_sh_x_out[31]), .C0(FPSENCOS_d_ff3_sh_y_out[31]), .C1(
n2482), .Y(n2119) );
INVX2TS U3271 ( .A(n2119), .Y(n2120) );
XNOR2X1TS U3272 ( .A(n2121), .B(n2120), .Y(n2732) );
NOR2X1TS U3273 ( .A(n2715), .B(FPADDSUB_intDX_EWSW[25]), .Y(n2180) );
NOR2XLTS U3274 ( .A(n2180), .B(FPADDSUB_intDY_EWSW[24]), .Y(n2122) );
AOI22X1TS U3275 ( .A0(FPADDSUB_intDX_EWSW[25]), .A1(n2715), .B0(n968), .B1(
n2122), .Y(n2126) );
OAI21X1TS U3276 ( .A0(FPADDSUB_intDX_EWSW[26]), .A1(n2719), .B0(n2123), .Y(
n2181) );
NAND3XLTS U3277 ( .A(n2719), .B(n2123), .C(FPADDSUB_intDX_EWSW[26]), .Y(
n2125) );
NAND2BXLTS U3278 ( .AN(FPADDSUB_intDY_EWSW[27]), .B(FPADDSUB_intDX_EWSW[27]),
.Y(n2124) );
OAI211XLTS U3279 ( .A0(n2126), .A1(n2181), .B0(n2125), .C0(n2124), .Y(n2131)
);
NOR2X1TS U3280 ( .A(n2741), .B(FPADDSUB_intDX_EWSW[30]), .Y(n2129) );
NOR2X1TS U3281 ( .A(n2740), .B(FPADDSUB_intDX_EWSW[29]), .Y(n2127) );
AOI211X1TS U3282 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n2659), .B0(n2129),
.C0(n2127), .Y(n2179) );
NOR3XLTS U3283 ( .A(n2659), .B(n2127), .C(FPADDSUB_intDY_EWSW[28]), .Y(n2128) );
AOI2BB2X1TS U3284 ( .B0(n2131), .B1(n2179), .A0N(n2130), .A1N(n2129), .Y(
n2185) );
NOR2X1TS U3285 ( .A(n2714), .B(FPADDSUB_intDX_EWSW[17]), .Y(n2167) );
NAND2BXLTS U3286 ( .AN(FPADDSUB_intDX_EWSW[9]), .B(FPADDSUB_intDY_EWSW[9]),
.Y(n2148) );
NOR2X1TS U3287 ( .A(n2712), .B(FPADDSUB_intDX_EWSW[11]), .Y(n2146) );
AOI21X1TS U3288 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n2665), .B0(n2146), .Y(
n2151) );
OAI211XLTS U3289 ( .A0(FPADDSUB_intDX_EWSW[8]), .A1(n2716), .B0(n2148), .C0(
n2151), .Y(n2162) );
OAI2BB1X1TS U3290 ( .A0N(n2618), .A1N(FPADDSUB_intDY_EWSW[5]), .B0(
FPADDSUB_intDX_EWSW[4]), .Y(n2132) );
OAI22X1TS U3291 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n2132), .B0(n2618), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n2143) );
OAI2BB1X1TS U3292 ( .A0N(n2617), .A1N(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDX_EWSW[6]), .Y(n2133) );
OAI22X1TS U3293 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n2133), .B0(n2617), .B1(
FPADDSUB_intDY_EWSW[7]), .Y(n2142) );
OAI2BB2XLTS U3294 ( .B0(FPADDSUB_intDY_EWSW[0]), .B1(n2134), .A0N(
FPADDSUB_intDX_EWSW[1]), .A1N(n2718), .Y(n2136) );
NAND2BXLTS U3295 ( .AN(FPADDSUB_intDX_EWSW[2]), .B(FPADDSUB_intDY_EWSW[2]),
.Y(n2135) );
OAI211XLTS U3296 ( .A0(n2720), .A1(FPADDSUB_intDX_EWSW[3]), .B0(n2136), .C0(
n2135), .Y(n2139) );
OAI21XLTS U3297 ( .A0(FPADDSUB_intDX_EWSW[3]), .A1(n2720), .B0(
FPADDSUB_intDX_EWSW[2]), .Y(n2137) );
AOI2BB2XLTS U3298 ( .B0(FPADDSUB_intDX_EWSW[3]), .B1(n2720), .A0N(
FPADDSUB_intDY_EWSW[2]), .A1N(n2137), .Y(n2138) );
AOI222X1TS U3299 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n2677), .B0(n2139), .B1(
n2138), .C0(FPADDSUB_intDY_EWSW[5]), .C1(n2618), .Y(n2141) );
AOI22X1TS U3300 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n2617), .B0(
FPADDSUB_intDY_EWSW[6]), .B1(n2678), .Y(n2140) );
OAI32X1TS U3301 ( .A0(n2143), .A1(n2142), .A2(n2141), .B0(n2140), .B1(n2142),
.Y(n2161) );
OA22X1TS U3302 ( .A0(n2621), .A1(FPADDSUB_intDX_EWSW[14]), .B0(n2713), .B1(
FPADDSUB_intDX_EWSW[15]), .Y(n2158) );
NAND2BXLTS U3303 ( .AN(FPADDSUB_intDX_EWSW[13]), .B(FPADDSUB_intDY_EWSW[13]),
.Y(n2144) );
OAI21XLTS U3304 ( .A0(FPADDSUB_intDX_EWSW[13]), .A1(n2705), .B0(
FPADDSUB_intDX_EWSW[12]), .Y(n2145) );
OAI2BB2XLTS U3305 ( .B0(FPADDSUB_intDY_EWSW[12]), .B1(n2145), .A0N(
FPADDSUB_intDX_EWSW[13]), .A1N(n2705), .Y(n2157) );
NOR2XLTS U3306 ( .A(n2146), .B(FPADDSUB_intDY_EWSW[10]), .Y(n2147) );
AOI22X1TS U3307 ( .A0(FPADDSUB_intDX_EWSW[11]), .A1(n2712), .B0(
FPADDSUB_intDX_EWSW[10]), .B1(n2147), .Y(n2153) );
NAND2BXLTS U3308 ( .AN(FPADDSUB_intDY_EWSW[9]), .B(FPADDSUB_intDX_EWSW[9]),
.Y(n2150) );
NAND3XLTS U3309 ( .A(n2716), .B(n2148), .C(FPADDSUB_intDX_EWSW[8]), .Y(n2149) );
AOI21X1TS U3310 ( .A0(n2150), .A1(n2149), .B0(n2160), .Y(n2152) );
OAI2BB2XLTS U3311 ( .B0(n2153), .B1(n2160), .A0N(n2152), .A1N(n2151), .Y(
n2156) );
OAI2BB2XLTS U3312 ( .B0(FPADDSUB_intDY_EWSW[14]), .B1(n2154), .A0N(
FPADDSUB_intDX_EWSW[15]), .A1N(n2713), .Y(n2155) );
AOI211X1TS U3313 ( .A0(n2158), .A1(n2157), .B0(n2156), .C0(n2155), .Y(n2159)
);
OAI31X1TS U3314 ( .A0(n2162), .A1(n2161), .A2(n2160), .B0(n2159), .Y(n2165)
);
OA22X1TS U3315 ( .A0(n2625), .A1(FPADDSUB_intDX_EWSW[22]), .B0(n2742), .B1(
FPADDSUB_intDX_EWSW[23]), .Y(n2196) );
NAND2BXLTS U3316 ( .AN(FPADDSUB_intDX_EWSW[21]), .B(FPADDSUB_intDY_EWSW[21]),
.Y(n2163) );
OAI21X1TS U3317 ( .A0(FPADDSUB_intDX_EWSW[18]), .A1(n2717), .B0(n2169), .Y(
n2173) );
NAND3BXLTS U3318 ( .AN(n2167), .B(n2165), .C(n2164), .Y(n2184) );
OAI21XLTS U3319 ( .A0(FPADDSUB_intDX_EWSW[21]), .A1(n2710), .B0(
FPADDSUB_intDX_EWSW[20]), .Y(n2166) );
OAI2BB2XLTS U3320 ( .B0(FPADDSUB_intDY_EWSW[20]), .B1(n2166), .A0N(
FPADDSUB_intDX_EWSW[21]), .A1N(n2710), .Y(n2177) );
AOI22X1TS U3321 ( .A0(FPADDSUB_intDX_EWSW[17]), .A1(n2714), .B0(
FPADDSUB_intDX_EWSW[16]), .B1(n2168), .Y(n2171) );
AOI32X1TS U3322 ( .A0(n2717), .A1(n2169), .A2(FPADDSUB_intDX_EWSW[18]), .B0(
FPADDSUB_intDX_EWSW[19]), .B1(n2624), .Y(n2170) );
OAI32X1TS U3323 ( .A0(n2173), .A1(n2172), .A2(n2171), .B0(n2170), .B1(n2172),
.Y(n2176) );
OAI2BB2XLTS U3324 ( .B0(FPADDSUB_intDY_EWSW[22]), .B1(n2174), .A0N(
FPADDSUB_intDX_EWSW[23]), .A1N(n2742), .Y(n2175) );
AOI211X1TS U3325 ( .A0(n2196), .A1(n2177), .B0(n2176), .C0(n2175), .Y(n2183)
);
NAND4BBX1TS U3326 ( .AN(n2181), .BN(n2180), .C(n2179), .D(n2178), .Y(n2182)
);
AOI32X1TS U3327 ( .A0(n2185), .A1(n2184), .A2(n2183), .B0(n2182), .B1(n2185),
.Y(n2186) );
NAND2X1TS U3328 ( .A(FPADDSUB_intDY_EWSW[18]), .B(n2680), .Y(n2187) );
AOI22X1TS U3329 ( .A0(n2687), .A1(FPADDSUB_intDX_EWSW[28]), .B0(n2678), .B1(
FPADDSUB_intDY_EWSW[6]), .Y(n2188) );
OAI221XLTS U3330 ( .A0(n2687), .A1(FPADDSUB_intDX_EWSW[28]), .B0(n2678),
.B1(FPADDSUB_intDY_EWSW[6]), .C0(n2188), .Y(n2193) );
AOI22X1TS U3331 ( .A0(n2674), .A1(FPADDSUB_intDY_EWSW[1]), .B0(n2619), .B1(
FPADDSUB_intDY_EWSW[0]), .Y(n2189) );
AOI22X1TS U3332 ( .A0(n953), .A1(FPADDSUB_intDY_EWSW[26]), .B0(n2668), .B1(
FPADDSUB_intDY_EWSW[3]), .Y(n2190) );
OAI221XLTS U3333 ( .A0(n953), .A1(FPADDSUB_intDY_EWSW[26]), .B0(n2668), .B1(
FPADDSUB_intDY_EWSW[3]), .C0(n2190), .Y(n2191) );
NOR4X1TS U3334 ( .A(n2194), .B(n2193), .C(n2192), .D(n2191), .Y(n2221) );
AOI22X1TS U3335 ( .A0(n2618), .A1(FPADDSUB_intDY_EWSW[5]), .B0(n2677), .B1(
FPADDSUB_intDY_EWSW[4]), .Y(n2195) );
OAI221XLTS U3336 ( .A0(n2683), .A1(FPADDSUB_intDY_EWSW[23]), .B0(n913), .B1(
FPADDSUB_intDY_EWSW[22]), .C0(n2196), .Y(n2201) );
AOI22X1TS U3337 ( .A0(n2675), .A1(FPADDSUB_intDY_EWSW[17]), .B0(n2679), .B1(
FPADDSUB_intDY_EWSW[16]), .Y(n2197) );
AOI22X1TS U3338 ( .A0(n2616), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n2667), .B1(
FPADDSUB_intDY_EWSW[8]), .Y(n2198) );
OAI221XLTS U3339 ( .A0(n2616), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n2667),
.B1(FPADDSUB_intDY_EWSW[8]), .C0(n2198), .Y(n2199) );
NOR4X1TS U3340 ( .A(n2202), .B(n2201), .C(n2200), .D(n2199), .Y(n2220) );
NAND2X1TS U3341 ( .A(FPADDSUB_intDY_EWSW[20]), .B(n2681), .Y(n2203) );
INVX2TS U3342 ( .A(n968), .Y(n2367) );
AOI22X1TS U3343 ( .A0(n952), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n2367), .B1(
FPADDSUB_intDY_EWSW[24]), .Y(n2204) );
OAI221XLTS U3344 ( .A0(n952), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n2367), .B1(
FPADDSUB_intDY_EWSW[24]), .C0(n2204), .Y(n2217) );
OAI22X1TS U3345 ( .A0(n951), .A1(FPADDSUB_intDY_EWSW[19]), .B0(n922), .B1(
FPADDSUB_intDY_EWSW[27]), .Y(n2205) );
AOI221X1TS U3346 ( .A0(n951), .A1(FPADDSUB_intDY_EWSW[19]), .B0(
FPADDSUB_intDY_EWSW[27]), .B1(n922), .C0(n2205), .Y(n2206) );
OAI221XLTS U3347 ( .A0(FPADDSUB_intDX_EWSW[14]), .A1(n2621), .B0(n2684),
.B1(FPADDSUB_intDY_EWSW[14]), .C0(n2206), .Y(n2216) );
OAI22X1TS U3348 ( .A0(n2673), .A1(FPADDSUB_intDX_EWSW[12]), .B0(n2613), .B1(
FPADDSUB_intDY_EWSW[2]), .Y(n2207) );
AOI221X1TS U3349 ( .A0(n2673), .A1(FPADDSUB_intDX_EWSW[12]), .B0(
FPADDSUB_intDY_EWSW[2]), .B1(n2613), .C0(n2207), .Y(n2214) );
OAI22X1TS U3350 ( .A0(n2617), .A1(FPADDSUB_intDY_EWSW[7]), .B0(n2614), .B1(
FPADDSUB_intDY_EWSW[9]), .Y(n2208) );
AOI221X1TS U3351 ( .A0(n2617), .A1(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDY_EWSW[9]), .B1(n2614), .C0(n2208), .Y(n2213) );
OAI22X1TS U3352 ( .A0(n2665), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n2664), .B1(
FPADDSUB_intDY_EWSW[11]), .Y(n2209) );
AOI221X1TS U3353 ( .A0(n2665), .A1(FPADDSUB_intDY_EWSW[10]), .B0(
FPADDSUB_intDY_EWSW[11]), .B1(n2664), .C0(n2209), .Y(n2212) );
OAI22X1TS U3354 ( .A0(n2666), .A1(FPADDSUB_intDY_EWSW[15]), .B0(n2615), .B1(
FPADDSUB_intDY_EWSW[13]), .Y(n2210) );
AOI221X1TS U3355 ( .A0(n2666), .A1(FPADDSUB_intDY_EWSW[15]), .B0(
FPADDSUB_intDY_EWSW[13]), .B1(n2615), .C0(n2210), .Y(n2211) );
NAND4XLTS U3356 ( .A(n2214), .B(n2213), .C(n2212), .D(n2211), .Y(n2215) );
NOR4X1TS U3357 ( .A(n2218), .B(n2217), .C(n2215), .D(n2216), .Y(n2219) );
AOI31XLTS U3358 ( .A0(n2221), .A1(n2220), .A2(n2219), .B0(n2186), .Y(n2222)
);
AOI2BB2XLTS U3359 ( .B0(n2366), .B1(n2828), .A0N(FPADDSUB_intDX_EWSW[31]),
.A1N(n2222), .Y(n2829) );
AOI22X1TS U3362 ( .A0(FPMULT_FSM_selector_C), .A1(FPMULT_Add_result[23]),
.B0(FPMULT_P_Sgf[46]), .B1(n2676), .Y(n2223) );
AOI22X1TS U3363 ( .A0(n2599), .A1(n2224), .B0(n2229), .B1(n2223), .Y(n2862)
);
AOI32X1TS U3364 ( .A0(n2225), .A1(n2599), .A2(n2697), .B0(n2224), .B1(
FPMULT_FS_Module_state_reg[2]), .Y(n2227) );
AOI22X1TS U3365 ( .A0(n2274), .A1(FPMULT_Add_result[22]), .B0(n986), .B1(
FPMULT_Add_result[23]), .Y(n2231) );
AOI22X1TS U3366 ( .A0(n2275), .A1(FPMULT_P_Sgf[45]), .B0(n988), .B1(
FPMULT_P_Sgf[46]), .Y(n2230) );
NAND2X1TS U3367 ( .A(n2231), .B(n2230), .Y(n2861) );
AOI22X1TS U3368 ( .A0(n2274), .A1(FPMULT_Add_result[21]), .B0(
FPMULT_Add_result[22]), .B1(n985), .Y(n2233) );
AOI22X1TS U3369 ( .A0(n2275), .A1(FPMULT_P_Sgf[44]), .B0(FPMULT_P_Sgf[45]),
.B1(n987), .Y(n2232) );
NAND2X1TS U3370 ( .A(n2233), .B(n2232), .Y(n2860) );
AOI22X1TS U3371 ( .A0(n2274), .A1(FPMULT_Add_result[20]), .B0(n986), .B1(
FPMULT_Add_result[21]), .Y(n2235) );
AOI22X1TS U3372 ( .A0(n2275), .A1(FPMULT_P_Sgf[43]), .B0(n988), .B1(
FPMULT_P_Sgf[44]), .Y(n2234) );
NAND2X1TS U3373 ( .A(n2235), .B(n2234), .Y(n2859) );
AOI22X1TS U3374 ( .A0(n2274), .A1(FPMULT_Add_result[19]), .B0(n985), .B1(
FPMULT_Add_result[20]), .Y(n2237) );
AOI22X1TS U3375 ( .A0(n2275), .A1(FPMULT_P_Sgf[42]), .B0(n987), .B1(
FPMULT_P_Sgf[43]), .Y(n2236) );
NAND2X1TS U3376 ( .A(n2237), .B(n2236), .Y(n2858) );
AOI22X1TS U3377 ( .A0(n2274), .A1(FPMULT_Add_result[18]), .B0(n986), .B1(
FPMULT_Add_result[19]), .Y(n2239) );
AOI22X1TS U3378 ( .A0(n2275), .A1(FPMULT_P_Sgf[41]), .B0(n988), .B1(
FPMULT_P_Sgf[42]), .Y(n2238) );
NAND2X1TS U3379 ( .A(n2239), .B(n2238), .Y(n2857) );
AOI22X1TS U3380 ( .A0(n2274), .A1(FPMULT_Add_result[17]), .B0(n985), .B1(
FPMULT_Add_result[18]), .Y(n2241) );
AOI22X1TS U3381 ( .A0(n2275), .A1(FPMULT_P_Sgf[40]), .B0(n987), .B1(
FPMULT_P_Sgf[41]), .Y(n2240) );
NAND2X1TS U3382 ( .A(n2241), .B(n2240), .Y(n2856) );
AOI22X1TS U3383 ( .A0(n2274), .A1(FPMULT_Add_result[16]), .B0(n986), .B1(
FPMULT_Add_result[17]), .Y(n2243) );
AOI22X1TS U3384 ( .A0(n2275), .A1(FPMULT_P_Sgf[39]), .B0(n988), .B1(
FPMULT_P_Sgf[40]), .Y(n2242) );
NAND2X1TS U3385 ( .A(n2243), .B(n2242), .Y(n2855) );
AOI22X1TS U3386 ( .A0(n2274), .A1(FPMULT_Add_result[15]), .B0(n985), .B1(
FPMULT_Add_result[16]), .Y(n2245) );
AOI22X1TS U3387 ( .A0(n2275), .A1(FPMULT_P_Sgf[38]), .B0(n987), .B1(
FPMULT_P_Sgf[39]), .Y(n2244) );
NAND2X1TS U3388 ( .A(n2245), .B(n2244), .Y(n2854) );
AOI22X1TS U3389 ( .A0(n2274), .A1(FPMULT_Add_result[14]), .B0(n986), .B1(
FPMULT_Add_result[15]), .Y(n2247) );
AOI22X1TS U3390 ( .A0(n2275), .A1(FPMULT_P_Sgf[37]), .B0(n988), .B1(
FPMULT_P_Sgf[38]), .Y(n2246) );
NAND2X1TS U3391 ( .A(n2247), .B(n2246), .Y(n2853) );
AOI22X1TS U3392 ( .A0(n1006), .A1(FPMULT_Add_result[13]), .B0(n985), .B1(
FPMULT_Add_result[14]), .Y(n2249) );
AOI22X1TS U3393 ( .A0(n1007), .A1(FPMULT_P_Sgf[36]), .B0(n987), .B1(
FPMULT_P_Sgf[37]), .Y(n2248) );
NAND2X1TS U3394 ( .A(n2249), .B(n2248), .Y(n2852) );
AOI22X1TS U3395 ( .A0(n1006), .A1(FPMULT_Add_result[12]), .B0(n986), .B1(
FPMULT_Add_result[13]), .Y(n2251) );
AOI22X1TS U3396 ( .A0(n1007), .A1(FPMULT_P_Sgf[35]), .B0(n988), .B1(
FPMULT_P_Sgf[36]), .Y(n2250) );
NAND2X1TS U3397 ( .A(n2251), .B(n2250), .Y(n2851) );
AOI22X1TS U3398 ( .A0(n1006), .A1(FPMULT_Add_result[11]), .B0(n985), .B1(
FPMULT_Add_result[12]), .Y(n2253) );
AOI22X1TS U3399 ( .A0(n1007), .A1(FPMULT_P_Sgf[34]), .B0(n987), .B1(
FPMULT_P_Sgf[35]), .Y(n2252) );
NAND2X1TS U3400 ( .A(n2253), .B(n2252), .Y(n2850) );
AOI22X1TS U3401 ( .A0(n1006), .A1(FPMULT_Add_result[10]), .B0(n986), .B1(
FPMULT_Add_result[11]), .Y(n2255) );
AOI22X1TS U3402 ( .A0(n1007), .A1(FPMULT_P_Sgf[33]), .B0(n988), .B1(
FPMULT_P_Sgf[34]), .Y(n2254) );
NAND2X1TS U3403 ( .A(n2255), .B(n2254), .Y(n2849) );
AOI22X1TS U3404 ( .A0(n1006), .A1(FPMULT_Add_result[9]), .B0(n985), .B1(
FPMULT_Add_result[10]), .Y(n2257) );
AOI22X1TS U3405 ( .A0(n1007), .A1(FPMULT_P_Sgf[32]), .B0(n987), .B1(
FPMULT_P_Sgf[33]), .Y(n2256) );
NAND2X1TS U3406 ( .A(n2257), .B(n2256), .Y(n2848) );
AOI22X1TS U3407 ( .A0(n1006), .A1(FPMULT_Add_result[8]), .B0(n986), .B1(
FPMULT_Add_result[9]), .Y(n2259) );
AOI22X1TS U3408 ( .A0(n1007), .A1(FPMULT_P_Sgf[31]), .B0(n988), .B1(
FPMULT_P_Sgf[32]), .Y(n2258) );
NAND2X1TS U3409 ( .A(n2259), .B(n2258), .Y(n2847) );
AOI22X1TS U3410 ( .A0(n1006), .A1(FPMULT_Add_result[7]), .B0(n985), .B1(
FPMULT_Add_result[8]), .Y(n2261) );
AOI22X1TS U3411 ( .A0(n1007), .A1(FPMULT_P_Sgf[30]), .B0(n987), .B1(
FPMULT_P_Sgf[31]), .Y(n2260) );
NAND2X1TS U3412 ( .A(n2261), .B(n2260), .Y(n2846) );
AOI22X1TS U3413 ( .A0(n1006), .A1(FPMULT_Add_result[6]), .B0(n986), .B1(
FPMULT_Add_result[7]), .Y(n2263) );
AOI22X1TS U3414 ( .A0(n1007), .A1(FPMULT_P_Sgf[29]), .B0(n988), .B1(
FPMULT_P_Sgf[30]), .Y(n2262) );
NAND2X1TS U3415 ( .A(n2263), .B(n2262), .Y(n2845) );
AOI22X1TS U3416 ( .A0(n1006), .A1(FPMULT_Add_result[5]), .B0(n985), .B1(
FPMULT_Add_result[6]), .Y(n2265) );
AOI22X1TS U3417 ( .A0(n1007), .A1(FPMULT_P_Sgf[28]), .B0(n987), .B1(
FPMULT_P_Sgf[29]), .Y(n2264) );
NAND2X1TS U3418 ( .A(n2265), .B(n2264), .Y(n2844) );
AOI22X1TS U3419 ( .A0(n1006), .A1(FPMULT_Add_result[4]), .B0(n986), .B1(
FPMULT_Add_result[5]), .Y(n2267) );
AOI22X1TS U3420 ( .A0(n1007), .A1(FPMULT_P_Sgf[27]), .B0(n988), .B1(
FPMULT_P_Sgf[28]), .Y(n2266) );
NAND2X1TS U3421 ( .A(n2267), .B(n2266), .Y(n2843) );
AOI22X1TS U3422 ( .A0(n1006), .A1(FPMULT_Add_result[3]), .B0(n985), .B1(
FPMULT_Add_result[4]), .Y(n2269) );
AOI22X1TS U3423 ( .A0(n1007), .A1(FPMULT_P_Sgf[26]), .B0(n987), .B1(
FPMULT_P_Sgf[27]), .Y(n2268) );
NAND2X1TS U3424 ( .A(n2269), .B(n2268), .Y(n2842) );
AOI22X1TS U3425 ( .A0(n1006), .A1(FPMULT_Add_result[2]), .B0(n986), .B1(
FPMULT_Add_result[3]), .Y(n2271) );
AOI22X1TS U3426 ( .A0(n1007), .A1(FPMULT_P_Sgf[25]), .B0(n988), .B1(
FPMULT_P_Sgf[26]), .Y(n2270) );
NAND2X1TS U3427 ( .A(n2271), .B(n2270), .Y(n2841) );
AOI22X1TS U3428 ( .A0(n2274), .A1(FPMULT_Add_result[1]), .B0(n985), .B1(
FPMULT_Add_result[2]), .Y(n2273) );
AOI22X1TS U3429 ( .A0(n2275), .A1(FPMULT_P_Sgf[24]), .B0(n987), .B1(
FPMULT_P_Sgf[25]), .Y(n2272) );
NAND2X1TS U3430 ( .A(n2273), .B(n2272), .Y(n2840) );
AOI22X1TS U3431 ( .A0(n2274), .A1(FPMULT_Add_result[0]), .B0(n986), .B1(
FPMULT_Add_result[1]), .Y(n2277) );
AOI22X1TS U3432 ( .A0(n2275), .A1(FPMULT_P_Sgf[23]), .B0(n988), .B1(
FPMULT_P_Sgf[24]), .Y(n2276) );
NAND2X1TS U3433 ( .A(n2277), .B(n2276), .Y(n2839) );
AOI22X1TS U3434 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n2278), .B1(n2682),
.Y(n2838) );
XNOR2X1TS U3435 ( .A(Data_2[31]), .B(Data_1[31]), .Y(n2733) );
INVX2TS U3436 ( .A(n2279), .Y(n2431) );
AOI2BB1XLTS U3437 ( .A0N(n2722), .A1N(underflow_flag_mult), .B0(n2431), .Y(
FPMULT_final_result_ieee_Module_Sign_S_mux) );
AOI32X1TS U3438 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n2280), .A2(n2651),
.B0(FPSENCOS_cont_iter_out[2]), .B1(n2280), .Y(
FPSENCOS_data_out_LUT[4]) );
OAI22X1TS U3439 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n2510), .B0(
FPSENCOS_cont_iter_out[2]), .B1(n2511), .Y(FPSENCOS_data_out_LUT[25])
);
NOR4X1TS U3440 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n2287) );
NOR4X1TS U3441 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n2286) );
NOR4X1TS U3442 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n2284) );
NOR3XLTS U3443 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n2283) );
NOR4X1TS U3444 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n2282) );
NOR4X1TS U3445 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n2281) );
AND4X1TS U3446 ( .A(n2284), .B(n2283), .C(n2282), .D(n2281), .Y(n2285) );
NAND3XLTS U3447 ( .A(n2287), .B(n2286), .C(n2285), .Y(n2730) );
NAND4XLTS U3448 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n2289) );
NAND4XLTS U3449 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n2288) );
NOR3X1TS U3450 ( .A(n2821), .B(n2289), .C(n2288), .Y(n2294) );
NOR4X1TS U3451 ( .A(dataB[30]), .B(dataB[23]), .C(dataB[28]), .D(dataB[24]),
.Y(n2291) );
NOR3XLTS U3452 ( .A(dataB[26]), .B(dataB[29]), .C(dataB[25]), .Y(n2290) );
NAND4XLTS U3453 ( .A(n2294), .B(operation_reg[1]), .C(n2291), .D(n2290), .Y(
n2292) );
NOR3XLTS U3454 ( .A(operation_reg[0]), .B(dataB[31]), .C(n2292), .Y(n2293)
);
OAI211XLTS U3455 ( .A0(dataB[27]), .A1(n2293), .B0(n2820), .C0(n2819), .Y(
n2304) );
NOR4X1TS U3456 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[28]), .D(dataA[26]),
.Y(n2297) );
NOR4BX1TS U3457 ( .AN(operation_reg[1]), .B(dataA[31]), .C(dataA[24]), .D(
dataA[25]), .Y(n2296) );
NOR4X1TS U3458 ( .A(n2821), .B(dataA[30]), .C(operation_reg[0]), .D(
dataA[27]), .Y(n2295) );
NOR2BX1TS U3459 ( .AN(n2294), .B(operation_reg[1]), .Y(n2302) );
AOI31XLTS U3460 ( .A0(n2297), .A1(n2296), .A2(n2295), .B0(n2302), .Y(n2300)
);
NAND3XLTS U3461 ( .A(dataB[28]), .B(dataB[23]), .C(dataB[25]), .Y(n2299) );
NAND4XLTS U3462 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n2298) );
OAI31X1TS U3463 ( .A0(n2300), .A1(n2299), .A2(n2298), .B0(dataB[27]), .Y(
n2301) );
NAND4XLTS U3464 ( .A(n2824), .B(n2823), .C(n2822), .D(n2301), .Y(n2303) );
OAI2BB2XLTS U3465 ( .B0(n2304), .B1(n2303), .A0N(n2302), .A1N(
operation_reg[0]), .Y(NaN_reg) );
NAND2X1TS U3466 ( .A(FPADDSUB_N59), .B(n2317), .Y(n2305) );
XNOR2X1TS U3467 ( .A(n2305), .B(FPADDSUB_N60), .Y(FPADDSUB_Raw_mant_SGF[1])
);
OAI21XLTS U3468 ( .A0(FPADDSUB_DMP_SFG[0]), .A1(FPADDSUB_DmP_mant_SFG_SWR[2]), .B0(n2306), .Y(n2309) );
NAND2X1TS U3469 ( .A(n2307), .B(n2317), .Y(n2308) );
XOR2XLTS U3470 ( .A(n2309), .B(n2308), .Y(FPADDSUB_Raw_mant_SGF[2]) );
AOI22X1TS U3471 ( .A0(n2317), .A1(n2311), .B0(n2310), .B1(n2788), .Y(n2314)
);
OAI21XLTS U3472 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[9]), .A1(n2604), .B0(n2312),
.Y(n2313) );
XOR2XLTS U3473 ( .A(n2314), .B(n2313), .Y(FPADDSUB_Raw_mant_SGF[9]) );
AOI22X1TS U3474 ( .A0(n2317), .A1(n2316), .B0(n2315), .B1(n2788), .Y(n2320)
);
OAI21XLTS U3475 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[11]), .A1(n2605), .B0(n2318),
.Y(n2319) );
XOR2XLTS U3476 ( .A(n2320), .B(n2319), .Y(FPADDSUB_Raw_mant_SGF[11]) );
AOI22X1TS U3477 ( .A0(n1031), .A1(n2322), .B0(n2321), .B1(n2788), .Y(n2325)
);
OAI21XLTS U3478 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[13]), .A1(n2606), .B0(n2323),
.Y(n2324) );
XOR2XLTS U3479 ( .A(n2325), .B(n2324), .Y(FPADDSUB_Raw_mant_SGF[13]) );
AOI22X1TS U3480 ( .A0(n1031), .A1(n2327), .B0(n2326), .B1(n2788), .Y(n2330)
);
OAI21XLTS U3481 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[15]), .A1(n2607), .B0(n2328),
.Y(n2329) );
XOR2XLTS U3482 ( .A(n2330), .B(n2329), .Y(FPADDSUB_Raw_mant_SGF[15]) );
AOI22X1TS U3483 ( .A0(n1031), .A1(n2332), .B0(n2331), .B1(n2788), .Y(n2335)
);
XOR2XLTS U3484 ( .A(n2335), .B(n2334), .Y(FPADDSUB_Raw_mant_SGF[17]) );
AOI22X1TS U3485 ( .A0(n1031), .A1(n2337), .B0(n2336), .B1(n2352), .Y(n2340)
);
OAI21XLTS U3486 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[19]), .A1(n2611), .B0(n2338),
.Y(n2339) );
AOI22X1TS U3487 ( .A0(n1031), .A1(n2342), .B0(n2341), .B1(n2788), .Y(n2345)
);
OAI21XLTS U3488 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[21]), .A1(n2612), .B0(n2343),
.Y(n2344) );
AOI22X1TS U3489 ( .A0(n1031), .A1(n2347), .B0(n2346), .B1(n2788), .Y(n2350)
);
OAI21XLTS U3490 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[23]), .A1(n2620), .B0(n2348),
.Y(n2349) );
AOI21X1TS U3491 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(n2692), .B0(n2351),
.Y(n2356) );
AOI22X1TS U3492 ( .A0(n1031), .A1(n2354), .B0(n2353), .B1(n2352), .Y(n2355)
);
NAND2X1TS U3493 ( .A(FPSENCOS_d_ff1_operation_out), .B(n967), .Y(n2359) );
OAI21XLTS U3494 ( .A0(FPSENCOS_d_ff1_operation_out), .A1(n967), .B0(n2359),
.Y(n2357) );
XOR2X1TS U3495 ( .A(n1030), .B(n2357), .Y(n2358) );
BUFX3TS U3496 ( .A(n2386), .Y(n2384) );
AOI22X1TS U3497 ( .A0(n2387), .A1(FPSENCOS_d_ff_Yn[31]), .B0(
FPSENCOS_d_ff_Xn[31]), .B1(n2384), .Y(n2361) );
XNOR2X1TS U3498 ( .A(n2361), .B(n2360), .Y(FPSENCOS_fmtted_Result_31_) );
AOI22X1TS U3499 ( .A0(n2365), .A1(n2721), .B0(n2619), .B1(n2366), .Y(
FPADDSUB_DmP_INIT_EWSW[0]) );
AOI22X1TS U3500 ( .A0(n2369), .A1(n2718), .B0(n2674), .B1(n2366), .Y(
FPADDSUB_DmP_INIT_EWSW[1]) );
AOI22X1TS U3501 ( .A0(n2364), .A1(n2706), .B0(n2613), .B1(n2366), .Y(
FPADDSUB_DmP_INIT_EWSW[2]) );
BUFX4TS U3502 ( .A(n2366), .Y(n2368) );
AOI22X1TS U3503 ( .A0(n2365), .A1(n2720), .B0(n2668), .B1(n2368), .Y(
FPADDSUB_DmP_INIT_EWSW[3]) );
BUFX3TS U3504 ( .A(n2366), .Y(n2362) );
AOI22X1TS U3505 ( .A0(n2369), .A1(n2704), .B0(n2677), .B1(n2362), .Y(
FPADDSUB_DmP_INIT_EWSW[4]) );
AOI22X1TS U3506 ( .A0(n2369), .A1(n2696), .B0(n2618), .B1(n2362), .Y(
FPADDSUB_DmP_INIT_EWSW[5]) );
BUFX3TS U3507 ( .A(n2366), .Y(n2363) );
AOI22X1TS U3508 ( .A0(n2364), .A1(n2702), .B0(n2678), .B1(n2363), .Y(
FPADDSUB_DmP_INIT_EWSW[6]) );
AOI22X1TS U3509 ( .A0(n2369), .A1(n2695), .B0(n2617), .B1(n2363), .Y(
FPADDSUB_DmP_INIT_EWSW[7]) );
AOI22X1TS U3510 ( .A0(n2369), .A1(n2716), .B0(n2667), .B1(n2368), .Y(
FPADDSUB_DmP_INIT_EWSW[8]) );
AOI22X1TS U3511 ( .A0(n2365), .A1(n2708), .B0(n2614), .B1(n2368), .Y(
FPADDSUB_DmP_INIT_EWSW[9]) );
AOI22X1TS U3512 ( .A0(n2364), .A1(n2701), .B0(n2665), .B1(n2362), .Y(
FPADDSUB_DmP_INIT_EWSW[10]) );
AOI22X1TS U3513 ( .A0(n2369), .A1(n2712), .B0(n2664), .B1(n2363), .Y(
FPADDSUB_DmP_INIT_EWSW[11]) );
AOI22X1TS U3514 ( .A0(n2365), .A1(n2673), .B0(n2700), .B1(n2368), .Y(
FPADDSUB_DmP_INIT_EWSW[12]) );
AOI22X1TS U3515 ( .A0(n2369), .A1(n2705), .B0(n2615), .B1(n2362), .Y(
FPADDSUB_DmP_INIT_EWSW[13]) );
AOI22X1TS U3516 ( .A0(n2364), .A1(n2621), .B0(n2684), .B1(n2362), .Y(
FPADDSUB_DmP_INIT_EWSW[14]) );
AOI22X1TS U3517 ( .A0(n2369), .A1(n2713), .B0(n2666), .B1(n2362), .Y(
FPADDSUB_DmP_INIT_EWSW[15]) );
AOI22X1TS U3518 ( .A0(n2365), .A1(n2703), .B0(n2679), .B1(n2362), .Y(
FPADDSUB_DmP_INIT_EWSW[16]) );
AOI22X1TS U3519 ( .A0(n2364), .A1(n2714), .B0(n2675), .B1(n2362), .Y(
FPADDSUB_DmP_INIT_EWSW[17]) );
AOI22X1TS U3520 ( .A0(n2365), .A1(n2717), .B0(n2680), .B1(n2362), .Y(
FPADDSUB_DmP_INIT_EWSW[18]) );
AOI22X1TS U3521 ( .A0(n2364), .A1(n2624), .B0(n951), .B1(n2362), .Y(
FPADDSUB_DmP_INIT_EWSW[19]) );
AOI22X1TS U3522 ( .A0(n2365), .A1(n2711), .B0(n2681), .B1(n2362), .Y(
FPADDSUB_DmP_INIT_EWSW[20]) );
AOI22X1TS U3523 ( .A0(n2364), .A1(n2710), .B0(n2616), .B1(n2362), .Y(
FPADDSUB_DmP_INIT_EWSW[21]) );
AOI22X1TS U3524 ( .A0(n2365), .A1(n2625), .B0(n913), .B1(n2362), .Y(
FPADDSUB_DmP_INIT_EWSW[22]) );
AOI22X1TS U3525 ( .A0(n2364), .A1(n2742), .B0(n2683), .B1(n2363), .Y(
FPADDSUB_DmP_INIT_EWSW[23]) );
AOI22X1TS U3526 ( .A0(n2365), .A1(n2707), .B0(n2367), .B1(n2363), .Y(
FPADDSUB_DmP_INIT_EWSW[24]) );
AOI22X1TS U3527 ( .A0(n2364), .A1(n2715), .B0(n952), .B1(n2363), .Y(
FPADDSUB_DmP_INIT_EWSW[25]) );
AOI22X1TS U3528 ( .A0(n2365), .A1(n2719), .B0(n953), .B1(n2363), .Y(
FPADDSUB_DmP_INIT_EWSW[26]) );
AOI22X1TS U3529 ( .A0(n2364), .A1(n2709), .B0(n922), .B1(n2363), .Y(
FPADDSUB_DmP_INIT_EWSW[27]) );
AOI22X1TS U3530 ( .A0(n2365), .A1(n2619), .B0(n2721), .B1(n2363), .Y(
FPADDSUB_DMP_INIT_EWSW[0]) );
AOI22X1TS U3531 ( .A0(n2365), .A1(n2674), .B0(n2718), .B1(n2363), .Y(
FPADDSUB_DMP_INIT_EWSW[1]) );
AOI22X1TS U3532 ( .A0(n2364), .A1(n2613), .B0(n2706), .B1(n2363), .Y(
FPADDSUB_DMP_INIT_EWSW[2]) );
AOI22X1TS U3533 ( .A0(n2364), .A1(n2668), .B0(n2720), .B1(n2363), .Y(
FPADDSUB_DMP_INIT_EWSW[3]) );
AOI22X1TS U3534 ( .A0(n2364), .A1(n2677), .B0(n2704), .B1(n2363), .Y(
FPADDSUB_DMP_INIT_EWSW[4]) );
AOI22X1TS U3535 ( .A0(n2365), .A1(n2618), .B0(n2696), .B1(n2368), .Y(
FPADDSUB_DMP_INIT_EWSW[5]) );
AOI22X1TS U3536 ( .A0(n2364), .A1(n2678), .B0(n2702), .B1(n2368), .Y(
FPADDSUB_DMP_INIT_EWSW[6]) );
AOI22X1TS U3537 ( .A0(n2365), .A1(n2617), .B0(n2695), .B1(n2368), .Y(
FPADDSUB_DMP_INIT_EWSW[7]) );
AOI22X1TS U3538 ( .A0(n2365), .A1(n2667), .B0(n2716), .B1(n2368), .Y(
FPADDSUB_DMP_INIT_EWSW[8]) );
AOI22X1TS U3539 ( .A0(n2364), .A1(n2614), .B0(n2708), .B1(n2368), .Y(
FPADDSUB_DMP_INIT_EWSW[9]) );
AOI22X1TS U3540 ( .A0(n2364), .A1(n2665), .B0(n2701), .B1(n2368), .Y(
FPADDSUB_DMP_INIT_EWSW[10]) );
AOI22X1TS U3541 ( .A0(n2365), .A1(n2664), .B0(n2712), .B1(n2368), .Y(
FPADDSUB_DMP_INIT_EWSW[11]) );
AOI22X1TS U3542 ( .A0(n2365), .A1(n2700), .B0(n2673), .B1(n2368), .Y(
FPADDSUB_DMP_INIT_EWSW[12]) );
AOI22X1TS U3543 ( .A0(n2364), .A1(n2615), .B0(n2705), .B1(n2368), .Y(
FPADDSUB_DMP_INIT_EWSW[13]) );
AOI22X1TS U3544 ( .A0(n2369), .A1(n2684), .B0(n2621), .B1(n2368), .Y(
FPADDSUB_DMP_INIT_EWSW[14]) );
AOI22X1TS U3545 ( .A0(n2369), .A1(n2666), .B0(n2713), .B1(n2368), .Y(
FPADDSUB_DMP_INIT_EWSW[15]) );
AOI22X1TS U3546 ( .A0(n2369), .A1(n2679), .B0(n2703), .B1(n2366), .Y(
FPADDSUB_DMP_INIT_EWSW[16]) );
AOI22X1TS U3547 ( .A0(n2369), .A1(n2675), .B0(n2714), .B1(n2366), .Y(
FPADDSUB_DMP_INIT_EWSW[17]) );
AOI22X1TS U3548 ( .A0(n2369), .A1(n2680), .B0(n2717), .B1(n2366), .Y(
FPADDSUB_DMP_INIT_EWSW[18]) );
AOI22X1TS U3549 ( .A0(n2365), .A1(n951), .B0(n2624), .B1(n2366), .Y(
FPADDSUB_DMP_INIT_EWSW[19]) );
AOI22X1TS U3550 ( .A0(n2369), .A1(n2681), .B0(n2711), .B1(n2366), .Y(
FPADDSUB_DMP_INIT_EWSW[20]) );
AOI22X1TS U3551 ( .A0(n2369), .A1(n2616), .B0(n2710), .B1(n2366), .Y(
FPADDSUB_DMP_INIT_EWSW[21]) );
AOI22X1TS U3552 ( .A0(n2365), .A1(n913), .B0(n2625), .B1(n2366), .Y(
FPADDSUB_DMP_INIT_EWSW[22]) );
AOI22X1TS U3553 ( .A0(n2364), .A1(n2683), .B0(n2742), .B1(n2366), .Y(
FPADDSUB_DMP_INIT_EWSW[23]) );
AOI22X1TS U3554 ( .A0(n2369), .A1(n2367), .B0(n2707), .B1(n2366), .Y(
FPADDSUB_DMP_INIT_EWSW[24]) );
AOI22X1TS U3555 ( .A0(n2369), .A1(n952), .B0(n2715), .B1(n2368), .Y(
FPADDSUB_DMP_INIT_EWSW[25]) );
AOI22X1TS U3556 ( .A0(n2369), .A1(n953), .B0(n2719), .B1(n2368), .Y(
FPADDSUB_DMP_INIT_EWSW[26]) );
AOI22X1TS U3557 ( .A0(n2365), .A1(n922), .B0(n2709), .B1(n2368), .Y(
FPADDSUB_DMP_INIT_EWSW[27]) );
OAI2BB2XLTS U3558 ( .B0(n2369), .B1(n2687), .A0N(n2369), .A1N(
FPADDSUB_intDX_EWSW[28]), .Y(FPADDSUB_DMP_INIT_EWSW[28]) );
OAI2BB2XLTS U3559 ( .B0(n2364), .B1(n2740), .A0N(n2364), .A1N(
FPADDSUB_intDX_EWSW[29]), .Y(FPADDSUB_DMP_INIT_EWSW[29]) );
OAI22X1TS U3560 ( .A0(n2370), .A1(n1885), .B0(n2374), .B1(n2371), .Y(
FPADDSUB_Data_array_SWR[24]) );
OAI222X1TS U3561 ( .A0(n1886), .A1(n2374), .B0(n1885), .B1(n2372), .C0(n2371), .C1(n2370), .Y(FPADDSUB_Data_array_SWR[23]) );
NAND3XLTS U3562 ( .A(n989), .B(n2552), .C(n2511), .Y(n2402) );
NAND2X1TS U3563 ( .A(n2392), .B(n2402), .Y(FPSENCOS_enab_d_ff5_data_out) );
CLKAND2X2TS U3564 ( .A(n982), .B(FPADDSUB_sftr_odat_SHT2_SWR[4]), .Y(
FPADDSUB_formatted_number_W[2]) );
CLKAND2X2TS U3565 ( .A(n982), .B(FPADDSUB_sftr_odat_SHT2_SWR[6]), .Y(
FPADDSUB_formatted_number_W[4]) );
CLKAND2X2TS U3566 ( .A(n982), .B(FPADDSUB_sftr_odat_SHT2_SWR[7]), .Y(
FPADDSUB_formatted_number_W[5]) );
CLKAND2X2TS U3567 ( .A(n982), .B(FPADDSUB_sftr_odat_SHT2_SWR[18]), .Y(
FPADDSUB_formatted_number_W[16]) );
CLKAND2X2TS U3568 ( .A(n982), .B(FPADDSUB_sftr_odat_SHT2_SWR[19]), .Y(
FPADDSUB_formatted_number_W[17]) );
CLKAND2X2TS U3569 ( .A(n982), .B(FPADDSUB_sftr_odat_SHT2_SWR[21]), .Y(
FPADDSUB_formatted_number_W[19]) );
NOR2BX1TS U3570 ( .AN(FPMULT_Sgf_normalized_result[2]), .B(n2376), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[2]) );
NOR2BX1TS U3571 ( .AN(FPMULT_Sgf_normalized_result[4]), .B(n2376), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[4]) );
NOR2BX1TS U3572 ( .AN(FPMULT_Sgf_normalized_result[6]), .B(n2376), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[6]) );
NOR2BX1TS U3573 ( .AN(FPMULT_Sgf_normalized_result[8]), .B(n2376), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[8]) );
NOR2BX1TS U3574 ( .AN(FPMULT_Sgf_normalized_result[10]), .B(n2376), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[10]) );
NOR2BX1TS U3575 ( .AN(FPMULT_Sgf_normalized_result[12]), .B(n2376), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[12]) );
NOR2BX1TS U3576 ( .AN(FPMULT_Sgf_normalized_result[14]), .B(n2376), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[14]) );
NOR2BX1TS U3577 ( .AN(FPMULT_Sgf_normalized_result[16]), .B(n2376), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[16]) );
NOR2BX1TS U3578 ( .AN(FPMULT_Sgf_normalized_result[18]), .B(n2376), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[18]) );
NOR2BX1TS U3579 ( .AN(FPMULT_Sgf_normalized_result[20]), .B(n2376), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[20]) );
NOR2BX1TS U3580 ( .AN(FPMULT_Sgf_normalized_result[22]), .B(n2376), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[22]) );
NOR2BX1TS U3581 ( .AN(FPSENCOS_d_ff_Xn[0]), .B(n2378), .Y(
FPSENCOS_first_mux_X[0]) );
NOR2BX1TS U3582 ( .AN(FPSENCOS_d_ff_Xn[4]), .B(n2378), .Y(
FPSENCOS_first_mux_X[4]) );
NOR2BX1TS U3583 ( .AN(FPSENCOS_d_ff_Xn[8]), .B(n914), .Y(
FPSENCOS_first_mux_X[8]) );
NOR2BX1TS U3584 ( .AN(FPSENCOS_d_ff_Xn[9]), .B(n2377), .Y(
FPSENCOS_first_mux_X[9]) );
NOR2BX1TS U3585 ( .AN(FPSENCOS_d_ff_Xn[11]), .B(n2378), .Y(
FPSENCOS_first_mux_X[11]) );
NOR2BX1TS U3586 ( .AN(FPSENCOS_d_ff_Xn[15]), .B(n2377), .Y(
FPSENCOS_first_mux_X[15]) );
NOR2BX1TS U3587 ( .AN(FPSENCOS_d_ff_Xn[18]), .B(n2378), .Y(
FPSENCOS_first_mux_X[18]) );
NOR2BX1TS U3588 ( .AN(FPSENCOS_d_ff_Xn[21]), .B(n2378), .Y(
FPSENCOS_first_mux_X[21]) );
NOR2BX1TS U3589 ( .AN(FPSENCOS_d_ff_Xn[22]), .B(n914), .Y(
FPSENCOS_first_mux_X[22]) );
NOR2BX1TS U3590 ( .AN(FPSENCOS_d_ff_Xn[23]), .B(n2377), .Y(
FPSENCOS_first_mux_X[23]) );
NOR2BX1TS U3591 ( .AN(FPSENCOS_d_ff_Xn[30]), .B(n2377), .Y(
FPSENCOS_first_mux_X[30]) );
NOR2BX1TS U3592 ( .AN(FPSENCOS_d_ff_Xn[31]), .B(n914), .Y(
FPSENCOS_first_mux_X[31]) );
NOR2BX1TS U3593 ( .AN(FPSENCOS_d_ff_Yn[0]), .B(n2378), .Y(
FPSENCOS_first_mux_Y[0]) );
NOR2BX1TS U3594 ( .AN(FPSENCOS_d_ff_Yn[1]), .B(n914), .Y(
FPSENCOS_first_mux_Y[1]) );
NOR2BX1TS U3595 ( .AN(FPSENCOS_d_ff_Yn[2]), .B(n2377), .Y(
FPSENCOS_first_mux_Y[2]) );
NOR2BX1TS U3596 ( .AN(FPSENCOS_d_ff_Yn[3]), .B(n2378), .Y(
FPSENCOS_first_mux_Y[3]) );
NOR2BX1TS U3597 ( .AN(FPSENCOS_d_ff_Yn[4]), .B(n2378), .Y(
FPSENCOS_first_mux_Y[4]) );
NOR2BX1TS U3598 ( .AN(FPSENCOS_d_ff_Yn[5]), .B(n914), .Y(
FPSENCOS_first_mux_Y[5]) );
NOR2BX1TS U3599 ( .AN(FPSENCOS_d_ff_Yn[6]), .B(n2378), .Y(
FPSENCOS_first_mux_Y[6]) );
NOR2BX1TS U3600 ( .AN(FPSENCOS_d_ff_Yn[7]), .B(n2377), .Y(
FPSENCOS_first_mux_Y[7]) );
NOR2BX1TS U3601 ( .AN(FPSENCOS_d_ff_Yn[8]), .B(n2378), .Y(
FPSENCOS_first_mux_Y[8]) );
NOR2BX1TS U3602 ( .AN(FPSENCOS_d_ff_Yn[9]), .B(n2378), .Y(
FPSENCOS_first_mux_Y[9]) );
NOR2BX1TS U3603 ( .AN(FPSENCOS_d_ff_Yn[10]), .B(n2378), .Y(
FPSENCOS_first_mux_Y[10]) );
NOR2BX1TS U3604 ( .AN(FPSENCOS_d_ff_Yn[11]), .B(n2378), .Y(
FPSENCOS_first_mux_Y[11]) );
NOR2BX1TS U3605 ( .AN(FPSENCOS_d_ff_Yn[12]), .B(n914), .Y(
FPSENCOS_first_mux_Y[12]) );
NOR2BX1TS U3606 ( .AN(FPSENCOS_d_ff_Yn[13]), .B(n2383), .Y(
FPSENCOS_first_mux_Y[13]) );
NOR2BX1TS U3607 ( .AN(FPSENCOS_d_ff_Yn[14]), .B(n2377), .Y(
FPSENCOS_first_mux_Y[14]) );
NOR2BX1TS U3608 ( .AN(FPSENCOS_d_ff_Yn[15]), .B(n2383), .Y(
FPSENCOS_first_mux_Y[15]) );
NOR2BX1TS U3609 ( .AN(FPSENCOS_d_ff_Yn[16]), .B(n2378), .Y(
FPSENCOS_first_mux_Y[16]) );
NOR2BX1TS U3610 ( .AN(FPSENCOS_d_ff_Yn[17]), .B(n2383), .Y(
FPSENCOS_first_mux_Y[17]) );
NOR2BX1TS U3611 ( .AN(FPSENCOS_d_ff_Yn[18]), .B(n914), .Y(
FPSENCOS_first_mux_Y[18]) );
NOR2BX1TS U3612 ( .AN(FPSENCOS_d_ff_Yn[19]), .B(n2383), .Y(
FPSENCOS_first_mux_Y[19]) );
NOR2BX1TS U3613 ( .AN(FPSENCOS_d_ff_Yn[20]), .B(n2377), .Y(
FPSENCOS_first_mux_Y[20]) );
NOR2BX1TS U3614 ( .AN(FPSENCOS_d_ff_Yn[21]), .B(n2378), .Y(
FPSENCOS_first_mux_Y[21]) );
NOR2BX1TS U3615 ( .AN(FPSENCOS_d_ff_Yn[22]), .B(n914), .Y(
FPSENCOS_first_mux_Y[22]) );
NOR2BX1TS U3616 ( .AN(FPSENCOS_d_ff_Yn[23]), .B(n2378), .Y(
FPSENCOS_first_mux_Y[23]) );
NOR2BX1TS U3617 ( .AN(FPSENCOS_d_ff_Yn[24]), .B(n2378), .Y(
FPSENCOS_first_mux_Y[24]) );
NOR2BX1TS U3618 ( .AN(FPSENCOS_d_ff_Yn[25]), .B(n2383), .Y(
FPSENCOS_first_mux_Y[25]) );
NOR2BX1TS U3619 ( .AN(FPSENCOS_d_ff_Yn[26]), .B(n2378), .Y(
FPSENCOS_first_mux_Y[26]) );
NOR2BX1TS U3620 ( .AN(FPSENCOS_d_ff_Yn[27]), .B(n2383), .Y(
FPSENCOS_first_mux_Y[27]) );
NOR2BX1TS U3621 ( .AN(FPSENCOS_d_ff_Yn[28]), .B(n914), .Y(
FPSENCOS_first_mux_Y[28]) );
NOR2BX1TS U3622 ( .AN(FPSENCOS_d_ff_Yn[29]), .B(n2383), .Y(
FPSENCOS_first_mux_Y[29]) );
NOR2BX1TS U3623 ( .AN(FPSENCOS_d_ff_Yn[30]), .B(n2377), .Y(
FPSENCOS_first_mux_Y[30]) );
NOR2BX1TS U3624 ( .AN(FPSENCOS_d_ff_Yn[31]), .B(n2383), .Y(
FPSENCOS_first_mux_Y[31]) );
AO22XLTS U3625 ( .A0(n914), .A1(FPSENCOS_d_ff1_Z[0]), .B0(n2379), .B1(
FPSENCOS_d_ff_Zn[0]), .Y(FPSENCOS_first_mux_Z[0]) );
INVX4TS U3626 ( .A(n2380), .Y(n2383) );
AO22XLTS U3627 ( .A0(n2382), .A1(FPSENCOS_d_ff1_Z[1]), .B0(n1693), .B1(
FPSENCOS_d_ff_Zn[1]), .Y(FPSENCOS_first_mux_Z[1]) );
AO22XLTS U3628 ( .A0(n2382), .A1(FPSENCOS_d_ff1_Z[2]), .B0(n2379), .B1(
FPSENCOS_d_ff_Zn[2]), .Y(FPSENCOS_first_mux_Z[2]) );
AO22XLTS U3629 ( .A0(n2382), .A1(FPSENCOS_d_ff1_Z[3]), .B0(n2379), .B1(
FPSENCOS_d_ff_Zn[3]), .Y(FPSENCOS_first_mux_Z[3]) );
AO22XLTS U3630 ( .A0(n2382), .A1(FPSENCOS_d_ff1_Z[4]), .B0(n2379), .B1(
FPSENCOS_d_ff_Zn[4]), .Y(FPSENCOS_first_mux_Z[4]) );
AO22XLTS U3631 ( .A0(n2382), .A1(FPSENCOS_d_ff1_Z[5]), .B0(n2379), .B1(
FPSENCOS_d_ff_Zn[5]), .Y(FPSENCOS_first_mux_Z[5]) );
AO22XLTS U3632 ( .A0(n2382), .A1(FPSENCOS_d_ff1_Z[6]), .B0(n2380), .B1(
FPSENCOS_d_ff_Zn[6]), .Y(FPSENCOS_first_mux_Z[6]) );
AO22XLTS U3633 ( .A0(n2383), .A1(FPSENCOS_d_ff1_Z[7]), .B0(n2380), .B1(
FPSENCOS_d_ff_Zn[7]), .Y(FPSENCOS_first_mux_Z[7]) );
AO22XLTS U3634 ( .A0(n2383), .A1(FPSENCOS_d_ff1_Z[8]), .B0(n2380), .B1(
FPSENCOS_d_ff_Zn[8]), .Y(FPSENCOS_first_mux_Z[8]) );
AO22XLTS U3635 ( .A0(n2383), .A1(FPSENCOS_d_ff1_Z[9]), .B0(n2380), .B1(
FPSENCOS_d_ff_Zn[9]), .Y(FPSENCOS_first_mux_Z[9]) );
AO22XLTS U3636 ( .A0(n2383), .A1(FPSENCOS_d_ff1_Z[10]), .B0(n2380), .B1(
FPSENCOS_d_ff_Zn[10]), .Y(FPSENCOS_first_mux_Z[10]) );
AO22XLTS U3637 ( .A0(n2382), .A1(FPSENCOS_d_ff1_Z[11]), .B0(n2380), .B1(
FPSENCOS_d_ff_Zn[11]), .Y(FPSENCOS_first_mux_Z[11]) );
AO22XLTS U3638 ( .A0(n2383), .A1(FPSENCOS_d_ff1_Z[12]), .B0(n2380), .B1(
FPSENCOS_d_ff_Zn[12]), .Y(FPSENCOS_first_mux_Z[12]) );
AO22XLTS U3639 ( .A0(n2383), .A1(FPSENCOS_d_ff1_Z[13]), .B0(n2380), .B1(
FPSENCOS_d_ff_Zn[13]), .Y(FPSENCOS_first_mux_Z[13]) );
AO22XLTS U3640 ( .A0(n2382), .A1(FPSENCOS_d_ff1_Z[14]), .B0(n2380), .B1(
FPSENCOS_d_ff_Zn[14]), .Y(FPSENCOS_first_mux_Z[14]) );
AO22XLTS U3641 ( .A0(n2383), .A1(FPSENCOS_d_ff1_Z[15]), .B0(n2380), .B1(
FPSENCOS_d_ff_Zn[15]), .Y(FPSENCOS_first_mux_Z[15]) );
AO22XLTS U3642 ( .A0(n2381), .A1(FPSENCOS_d_ff1_Z[16]), .B0(n2380), .B1(
FPSENCOS_d_ff_Zn[16]), .Y(FPSENCOS_first_mux_Z[16]) );
AO22XLTS U3643 ( .A0(n2382), .A1(FPSENCOS_d_ff1_Z[17]), .B0(n1693), .B1(
FPSENCOS_d_ff_Zn[17]), .Y(FPSENCOS_first_mux_Z[17]) );
AO22XLTS U3644 ( .A0(n2382), .A1(FPSENCOS_d_ff1_Z[18]), .B0(n1693), .B1(
FPSENCOS_d_ff_Zn[18]), .Y(FPSENCOS_first_mux_Z[18]) );
AO22XLTS U3645 ( .A0(n2382), .A1(FPSENCOS_d_ff1_Z[19]), .B0(n1693), .B1(
FPSENCOS_d_ff_Zn[19]), .Y(FPSENCOS_first_mux_Z[19]) );
AO22XLTS U3646 ( .A0(n2382), .A1(FPSENCOS_d_ff1_Z[20]), .B0(n1693), .B1(
FPSENCOS_d_ff_Zn[20]), .Y(FPSENCOS_first_mux_Z[20]) );
AO22XLTS U3647 ( .A0(n2381), .A1(FPSENCOS_d_ff1_Z[21]), .B0(n1693), .B1(
FPSENCOS_d_ff_Zn[21]), .Y(FPSENCOS_first_mux_Z[21]) );
AO22XLTS U3648 ( .A0(n2383), .A1(FPSENCOS_d_ff1_Z[22]), .B0(n1693), .B1(
FPSENCOS_d_ff_Zn[22]), .Y(FPSENCOS_first_mux_Z[22]) );
AO22XLTS U3649 ( .A0(n2382), .A1(FPSENCOS_d_ff1_Z[23]), .B0(n1693), .B1(
FPSENCOS_d_ff_Zn[23]), .Y(FPSENCOS_first_mux_Z[23]) );
AO22XLTS U3650 ( .A0(n2382), .A1(FPSENCOS_d_ff1_Z[24]), .B0(n1693), .B1(
FPSENCOS_d_ff_Zn[24]), .Y(FPSENCOS_first_mux_Z[24]) );
AO22XLTS U3651 ( .A0(n2382), .A1(FPSENCOS_d_ff1_Z[25]), .B0(n1693), .B1(
FPSENCOS_d_ff_Zn[25]), .Y(FPSENCOS_first_mux_Z[25]) );
AO22XLTS U3652 ( .A0(n2381), .A1(FPSENCOS_d_ff1_Z[26]), .B0(n1693), .B1(
FPSENCOS_d_ff_Zn[26]), .Y(FPSENCOS_first_mux_Z[26]) );
AO22XLTS U3653 ( .A0(n2382), .A1(FPSENCOS_d_ff1_Z[27]), .B0(n1693), .B1(
FPSENCOS_d_ff_Zn[27]), .Y(FPSENCOS_first_mux_Z[27]) );
AO22XLTS U3654 ( .A0(n2383), .A1(FPSENCOS_d_ff1_Z[31]), .B0(n1693), .B1(
FPSENCOS_d_ff_Zn[31]), .Y(FPSENCOS_first_mux_Z[31]) );
BUFX3TS U3655 ( .A(n2384), .Y(n2388) );
AO22XLTS U3656 ( .A0(n2385), .A1(FPSENCOS_d_ff_Yn[0]), .B0(n2388), .B1(
FPSENCOS_d_ff_Xn[0]), .Y(FPSENCOS_mux_sal[0]) );
AO22XLTS U3657 ( .A0(n2385), .A1(FPSENCOS_d_ff_Yn[1]), .B0(n2384), .B1(
FPSENCOS_d_ff_Xn[1]), .Y(FPSENCOS_mux_sal[1]) );
AO22XLTS U3658 ( .A0(n2385), .A1(FPSENCOS_d_ff_Yn[2]), .B0(n2384), .B1(
FPSENCOS_d_ff_Xn[2]), .Y(FPSENCOS_mux_sal[2]) );
AO22XLTS U3659 ( .A0(n2385), .A1(FPSENCOS_d_ff_Yn[3]), .B0(n2384), .B1(
FPSENCOS_d_ff_Xn[3]), .Y(FPSENCOS_mux_sal[3]) );
AO22XLTS U3660 ( .A0(n2385), .A1(FPSENCOS_d_ff_Yn[4]), .B0(n2384), .B1(
FPSENCOS_d_ff_Xn[4]), .Y(FPSENCOS_mux_sal[4]) );
AO22XLTS U3661 ( .A0(n2385), .A1(FPSENCOS_d_ff_Yn[5]), .B0(n2384), .B1(
FPSENCOS_d_ff_Xn[5]), .Y(FPSENCOS_mux_sal[5]) );
AO22XLTS U3662 ( .A0(n2385), .A1(FPSENCOS_d_ff_Yn[6]), .B0(n2384), .B1(
FPSENCOS_d_ff_Xn[6]), .Y(FPSENCOS_mux_sal[6]) );
AO22XLTS U3663 ( .A0(n2385), .A1(FPSENCOS_d_ff_Yn[7]), .B0(n2384), .B1(
FPSENCOS_d_ff_Xn[7]), .Y(FPSENCOS_mux_sal[7]) );
AO22XLTS U3664 ( .A0(n2385), .A1(FPSENCOS_d_ff_Yn[8]), .B0(n2384), .B1(
FPSENCOS_d_ff_Xn[8]), .Y(FPSENCOS_mux_sal[8]) );
AO22XLTS U3665 ( .A0(n2385), .A1(FPSENCOS_d_ff_Yn[9]), .B0(n2384), .B1(
FPSENCOS_d_ff_Xn[9]), .Y(FPSENCOS_mux_sal[9]) );
AO22XLTS U3666 ( .A0(n2385), .A1(FPSENCOS_d_ff_Yn[10]), .B0(n2384), .B1(
FPSENCOS_d_ff_Xn[10]), .Y(FPSENCOS_mux_sal[10]) );
AO22XLTS U3667 ( .A0(n2385), .A1(FPSENCOS_d_ff_Yn[11]), .B0(n2386), .B1(
FPSENCOS_d_ff_Xn[11]), .Y(FPSENCOS_mux_sal[11]) );
AO22XLTS U3668 ( .A0(n2385), .A1(FPSENCOS_d_ff_Yn[12]), .B0(n2386), .B1(
FPSENCOS_d_ff_Xn[12]), .Y(FPSENCOS_mux_sal[12]) );
INVX2TS U3669 ( .A(n2386), .Y(n2387) );
AO22XLTS U3670 ( .A0(n2385), .A1(FPSENCOS_d_ff_Yn[13]), .B0(n2386), .B1(
FPSENCOS_d_ff_Xn[13]), .Y(FPSENCOS_mux_sal[13]) );
AO22XLTS U3671 ( .A0(n2385), .A1(FPSENCOS_d_ff_Yn[14]), .B0(n2386), .B1(
FPSENCOS_d_ff_Xn[14]), .Y(FPSENCOS_mux_sal[14]) );
AO22XLTS U3672 ( .A0(n2385), .A1(FPSENCOS_d_ff_Yn[15]), .B0(n2386), .B1(
FPSENCOS_d_ff_Xn[15]), .Y(FPSENCOS_mux_sal[15]) );
AO22XLTS U3673 ( .A0(n2385), .A1(FPSENCOS_d_ff_Yn[16]), .B0(n2386), .B1(
FPSENCOS_d_ff_Xn[16]), .Y(FPSENCOS_mux_sal[16]) );
AO22XLTS U3674 ( .A0(n2385), .A1(FPSENCOS_d_ff_Yn[17]), .B0(n2386), .B1(
FPSENCOS_d_ff_Xn[17]), .Y(FPSENCOS_mux_sal[17]) );
AO22XLTS U3675 ( .A0(n2387), .A1(FPSENCOS_d_ff_Yn[18]), .B0(n2384), .B1(
FPSENCOS_d_ff_Xn[18]), .Y(FPSENCOS_mux_sal[18]) );
AO22XLTS U3676 ( .A0(n2387), .A1(FPSENCOS_d_ff_Yn[19]), .B0(n2388), .B1(
FPSENCOS_d_ff_Xn[19]), .Y(FPSENCOS_mux_sal[19]) );
AO22XLTS U3677 ( .A0(n2387), .A1(FPSENCOS_d_ff_Yn[20]), .B0(n2388), .B1(
FPSENCOS_d_ff_Xn[20]), .Y(FPSENCOS_mux_sal[20]) );
AO22XLTS U3678 ( .A0(n2387), .A1(FPSENCOS_d_ff_Yn[21]), .B0(n2388), .B1(
FPSENCOS_d_ff_Xn[21]), .Y(FPSENCOS_mux_sal[21]) );
AO22XLTS U3679 ( .A0(n2387), .A1(FPSENCOS_d_ff_Yn[22]), .B0(n2388), .B1(
FPSENCOS_d_ff_Xn[22]), .Y(FPSENCOS_mux_sal[22]) );
AO22XLTS U3680 ( .A0(n2387), .A1(FPSENCOS_d_ff_Yn[23]), .B0(n2388), .B1(
FPSENCOS_d_ff_Xn[23]), .Y(FPSENCOS_mux_sal[23]) );
AO22XLTS U3681 ( .A0(n2387), .A1(FPSENCOS_d_ff_Yn[24]), .B0(n2388), .B1(
FPSENCOS_d_ff_Xn[24]), .Y(FPSENCOS_mux_sal[24]) );
AO22XLTS U3682 ( .A0(n2387), .A1(FPSENCOS_d_ff_Yn[25]), .B0(n2388), .B1(
FPSENCOS_d_ff_Xn[25]), .Y(FPSENCOS_mux_sal[25]) );
AO22XLTS U3683 ( .A0(n2387), .A1(FPSENCOS_d_ff_Yn[26]), .B0(n2388), .B1(
FPSENCOS_d_ff_Xn[26]), .Y(FPSENCOS_mux_sal[26]) );
INVX2TS U3684 ( .A(n2384), .Y(n2389) );
AO22XLTS U3685 ( .A0(n2389), .A1(FPSENCOS_d_ff_Yn[27]), .B0(n2388), .B1(
FPSENCOS_d_ff_Xn[27]), .Y(FPSENCOS_mux_sal[27]) );
AO22XLTS U3686 ( .A0(n2389), .A1(FPSENCOS_d_ff_Yn[28]), .B0(n2388), .B1(
FPSENCOS_d_ff_Xn[28]), .Y(FPSENCOS_mux_sal[28]) );
AO22XLTS U3687 ( .A0(n2389), .A1(FPSENCOS_d_ff_Yn[29]), .B0(n2388), .B1(
FPSENCOS_d_ff_Xn[29]), .Y(FPSENCOS_mux_sal[29]) );
AO22XLTS U3688 ( .A0(n2389), .A1(FPSENCOS_d_ff_Yn[30]), .B0(n2388), .B1(
FPSENCOS_d_ff_Xn[30]), .Y(FPSENCOS_mux_sal[30]) );
NAND2X1TS U3689 ( .A(n2391), .B(n2390), .Y(FPMULT_FSM_barrel_shifter_load)
);
AOI21X1TS U3690 ( .A0(operation[1]), .A1(ack_operation), .B0(n2392), .Y(
n2403) );
NOR3XLTS U3691 ( .A(FPSENCOS_enab_RB3), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .C(FPSENCOS_enab_d_ff_RB1),
.Y(n2393) );
NAND3XLTS U3692 ( .A(n2394), .B(n2401), .C(n2393), .Y(n2395) );
NOR2BX1TS U3693 ( .AN(begin_operation), .B(n2496), .Y(n2397) );
OAI22X1TS U3694 ( .A0(n2403), .A1(n2395), .B0(n2397), .B1(n2396), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]) );
NOR2BX1TS U3695 ( .AN(n2397), .B(n2396), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]) );
AO21XLTS U3696 ( .A0(n2398), .A1(n2399), .B0(FPSENCOS_enab_RB3), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]) );
OAI22X1TS U3697 ( .A0(FPSENCOS_enab_d_ff4_Zn), .A1(n2401), .B0(n2400), .B1(
n2399), .Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]) );
NOR2BX1TS U3698 ( .AN(FPSENCOS_enab_d_ff4_Zn), .B(n2401), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]) );
NAND2BXLTS U3699 ( .AN(n2403), .B(n2402), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]) );
BUFX3TS U3700 ( .A(n2493), .Y(n2505) );
AOI22X1TS U3701 ( .A0(FPSENCOS_d_ff3_sh_x_out[1]), .A1(n2505), .B0(Data_2[1]), .B1(n2424), .Y(n2405) );
AOI22X1TS U3702 ( .A0(n2482), .A1(FPSENCOS_d_ff3_sh_y_out[1]), .B0(n2455),
.B1(FPSENCOS_d_ff3_LUT_out[1]), .Y(n2404) );
NAND2X1TS U3703 ( .A(n2405), .B(n2404), .Y(add_subt_data2[1]) );
AOI22X1TS U3704 ( .A0(FPSENCOS_d_ff3_sh_x_out[2]), .A1(n2499), .B0(Data_2[2]), .B1(n2424), .Y(n2407) );
AOI22X1TS U3705 ( .A0(n2482), .A1(FPSENCOS_d_ff3_sh_y_out[2]), .B0(n2455),
.B1(FPSENCOS_d_ff3_LUT_out[2]), .Y(n2406) );
NAND2X1TS U3706 ( .A(n2407), .B(n2406), .Y(add_subt_data2[2]) );
AOI22X1TS U3707 ( .A0(FPSENCOS_d_ff3_sh_x_out[4]), .A1(n2499), .B0(Data_2[4]), .B1(n2424), .Y(n2409) );
AOI22X1TS U3708 ( .A0(n2482), .A1(FPSENCOS_d_ff3_sh_y_out[4]), .B0(n2455),
.B1(FPSENCOS_d_ff3_LUT_out[4]), .Y(n2408) );
NAND2X1TS U3709 ( .A(n2409), .B(n2408), .Y(add_subt_data2[4]) );
AOI22X1TS U3710 ( .A0(FPSENCOS_d_ff3_sh_x_out[6]), .A1(n2499), .B0(Data_2[6]), .B1(n2424), .Y(n2411) );
AOI22X1TS U3711 ( .A0(n2482), .A1(FPSENCOS_d_ff3_sh_y_out[6]), .B0(n2455),
.B1(FPSENCOS_d_ff3_LUT_out[6]), .Y(n2410) );
NAND2X1TS U3712 ( .A(n2411), .B(n2410), .Y(add_subt_data2[6]) );
AOI22X1TS U3713 ( .A0(FPSENCOS_d_ff3_sh_x_out[8]), .A1(n2499), .B0(Data_2[8]), .B1(n2424), .Y(n2413) );
AOI22X1TS U3714 ( .A0(n2482), .A1(FPSENCOS_d_ff3_sh_y_out[8]), .B0(n2455),
.B1(FPSENCOS_d_ff3_LUT_out[8]), .Y(n2412) );
NAND2X1TS U3715 ( .A(n2413), .B(n2412), .Y(add_subt_data2[8]) );
AOI22X1TS U3716 ( .A0(FPSENCOS_d_ff3_sh_x_out[9]), .A1(n2499), .B0(Data_2[9]), .B1(n2424), .Y(n2415) );
AOI22X1TS U3717 ( .A0(n2482), .A1(FPSENCOS_d_ff3_sh_y_out[9]), .B0(n2455),
.B1(FPSENCOS_d_ff3_LUT_out[9]), .Y(n2414) );
NAND2X1TS U3718 ( .A(n2415), .B(n2414), .Y(add_subt_data2[9]) );
AOI22X1TS U3719 ( .A0(FPSENCOS_d_ff3_sh_x_out[10]), .A1(n2499), .B0(
Data_2[10]), .B1(n2424), .Y(n2417) );
AOI22X1TS U3720 ( .A0(n2482), .A1(FPSENCOS_d_ff3_sh_y_out[10]), .B0(n2455),
.B1(FPSENCOS_d_ff3_LUT_out[10]), .Y(n2416) );
NAND2X1TS U3721 ( .A(n2417), .B(n2416), .Y(add_subt_data2[10]) );
AOI22X1TS U3722 ( .A0(FPSENCOS_d_ff3_sh_x_out[12]), .A1(n2499), .B0(
Data_2[12]), .B1(n2424), .Y(n2419) );
BUFX4TS U3723 ( .A(n1779), .Y(n2506) );
AOI22X1TS U3724 ( .A0(n2501), .A1(FPSENCOS_d_ff3_sh_y_out[12]), .B0(n2506),
.B1(FPSENCOS_d_ff3_LUT_out[12]), .Y(n2418) );
NAND2X1TS U3725 ( .A(n2419), .B(n2418), .Y(add_subt_data2[12]) );
AOI22X1TS U3726 ( .A0(FPSENCOS_d_ff3_sh_x_out[21]), .A1(n2468), .B0(
Data_2[21]), .B1(n2504), .Y(n2421) );
AOI22X1TS U3727 ( .A0(n2501), .A1(FPSENCOS_d_ff3_sh_y_out[21]), .B0(n2506),
.B1(FPSENCOS_d_ff3_LUT_out[21]), .Y(n2420) );
NAND2X1TS U3728 ( .A(n2421), .B(n2420), .Y(add_subt_data2[21]) );
AOI22X1TS U3729 ( .A0(FPSENCOS_d_ff3_sh_x_out[23]), .A1(n2505), .B0(
Data_2[23]), .B1(n2424), .Y(n2423) );
AOI22X1TS U3730 ( .A0(n2501), .A1(FPSENCOS_d_ff3_sh_y_out[23]), .B0(n2506),
.B1(FPSENCOS_d_ff3_LUT_out[23]), .Y(n2422) );
NAND2X1TS U3731 ( .A(n2423), .B(n2422), .Y(add_subt_data2[23]) );
AOI22X1TS U3732 ( .A0(FPSENCOS_d_ff3_sh_x_out[24]), .A1(n2505), .B0(
Data_2[24]), .B1(n2424), .Y(n2426) );
AOI22X1TS U3733 ( .A0(n2501), .A1(FPSENCOS_d_ff3_sh_y_out[24]), .B0(n2506),
.B1(FPSENCOS_d_ff3_LUT_out[24]), .Y(n2425) );
NAND2X1TS U3734 ( .A(n2426), .B(n2425), .Y(add_subt_data2[24]) );
AOI22X1TS U3735 ( .A0(FPSENCOS_d_ff3_sh_x_out[25]), .A1(n2468), .B0(
Data_2[25]), .B1(n2504), .Y(n2428) );
AOI22X1TS U3736 ( .A0(n2507), .A1(FPSENCOS_d_ff3_sh_y_out[25]), .B0(n2506),
.B1(FPSENCOS_d_ff3_LUT_out[25]), .Y(n2427) );
NAND2X1TS U3737 ( .A(n2428), .B(n2427), .Y(add_subt_data2[25]) );
AOI22X1TS U3738 ( .A0(FPSENCOS_d_ff3_sh_x_out[26]), .A1(n2468), .B0(
Data_2[26]), .B1(n2504), .Y(n2430) );
AOI22X1TS U3739 ( .A0(n2507), .A1(FPSENCOS_d_ff3_sh_y_out[26]), .B0(n2506),
.B1(FPSENCOS_d_ff3_LUT_out[26]), .Y(n2429) );
NAND2X1TS U3740 ( .A(n2430), .B(n2429), .Y(add_subt_data2[26]) );
INVX2TS U3741 ( .A(operation[2]), .Y(n2432) );
AO22XLTS U3742 ( .A0(operation[2]), .A1(n2431), .B0(n2432), .B1(
overflow_flag_addsubt), .Y(overflow_flag) );
AO22XLTS U3743 ( .A0(operation[2]), .A1(underflow_flag_mult), .B0(n2432),
.B1(underflow_flag_addsubt), .Y(underflow_flag) );
AOI22X1TS U3744 ( .A0(FPSENCOS_d_ff2_Y[0]), .A1(n2505), .B0(Data_1[0]), .B1(
n2504), .Y(n2434) );
AOI22X1TS U3745 ( .A0(n2507), .A1(FPSENCOS_d_ff2_X[0]), .B0(n2506), .B1(
FPSENCOS_d_ff2_Z[0]), .Y(n2433) );
NAND2X1TS U3746 ( .A(n2434), .B(n2433), .Y(add_subt_data1[0]) );
AOI22X1TS U3747 ( .A0(FPSENCOS_d_ff2_Y[1]), .A1(n2505), .B0(Data_1[1]), .B1(
n2504), .Y(n2436) );
AOI22X1TS U3748 ( .A0(n2507), .A1(FPSENCOS_d_ff2_X[1]), .B0(n2506), .B1(
FPSENCOS_d_ff2_Z[1]), .Y(n2435) );
NAND2X1TS U3749 ( .A(n2436), .B(n2435), .Y(add_subt_data1[1]) );
AOI22X1TS U3750 ( .A0(FPSENCOS_d_ff2_Y[2]), .A1(n2505), .B0(Data_1[2]), .B1(
n2504), .Y(n2438) );
AOI22X1TS U3751 ( .A0(n2507), .A1(FPSENCOS_d_ff2_X[2]), .B0(n2506), .B1(
FPSENCOS_d_ff2_Z[2]), .Y(n2437) );
NAND2X1TS U3752 ( .A(n2438), .B(n2437), .Y(add_subt_data1[2]) );
AOI22X1TS U3753 ( .A0(FPSENCOS_d_ff2_Y[3]), .A1(n2505), .B0(Data_1[3]), .B1(
n2504), .Y(n2440) );
AOI22X1TS U3754 ( .A0(n2507), .A1(FPSENCOS_d_ff2_X[3]), .B0(n2506), .B1(
FPSENCOS_d_ff2_Z[3]), .Y(n2439) );
NAND2X1TS U3755 ( .A(n2440), .B(n2439), .Y(add_subt_data1[3]) );
AOI22X1TS U3756 ( .A0(FPSENCOS_d_ff2_Y[4]), .A1(n2505), .B0(Data_1[4]), .B1(
n2504), .Y(n2442) );
AOI22X1TS U3757 ( .A0(n2479), .A1(FPSENCOS_d_ff2_X[4]), .B0(n2506), .B1(
FPSENCOS_d_ff2_Z[4]), .Y(n2441) );
NAND2X1TS U3758 ( .A(n2442), .B(n2441), .Y(add_subt_data1[4]) );
AOI22X1TS U3759 ( .A0(FPSENCOS_d_ff2_Y[5]), .A1(n2505), .B0(Data_1[5]), .B1(
n2504), .Y(n2444) );
AOI22X1TS U3760 ( .A0(n2479), .A1(FPSENCOS_d_ff2_X[5]), .B0(n2506), .B1(
FPSENCOS_d_ff2_Z[5]), .Y(n2443) );
NAND2X1TS U3761 ( .A(n2444), .B(n2443), .Y(add_subt_data1[5]) );
AOI22X1TS U3762 ( .A0(FPSENCOS_d_ff2_Y[6]), .A1(n2468), .B0(Data_1[6]), .B1(
n2504), .Y(n2446) );
AOI22X1TS U3763 ( .A0(n2479), .A1(FPSENCOS_d_ff2_X[6]), .B0(n2506), .B1(
FPSENCOS_d_ff2_Z[6]), .Y(n2445) );
NAND2X1TS U3764 ( .A(n2446), .B(n2445), .Y(add_subt_data1[6]) );
AOI22X1TS U3765 ( .A0(FPSENCOS_d_ff2_Y[7]), .A1(n2468), .B0(Data_1[7]), .B1(
n2504), .Y(n2448) );
AOI22X1TS U3766 ( .A0(n2479), .A1(FPSENCOS_d_ff2_X[7]), .B0(n2506), .B1(
FPSENCOS_d_ff2_Z[7]), .Y(n2447) );
NAND2X1TS U3767 ( .A(n2448), .B(n2447), .Y(add_subt_data1[7]) );
AOI22X1TS U3768 ( .A0(FPSENCOS_d_ff2_Y[8]), .A1(n2468), .B0(Data_1[8]), .B1(
n2504), .Y(n2450) );
AOI22X1TS U3769 ( .A0(n2479), .A1(FPSENCOS_d_ff2_X[8]), .B0(n2455), .B1(
FPSENCOS_d_ff2_Z[8]), .Y(n2449) );
NAND2X1TS U3770 ( .A(n2450), .B(n2449), .Y(add_subt_data1[8]) );
AOI22X1TS U3771 ( .A0(FPSENCOS_d_ff2_Y[10]), .A1(n2468), .B0(Data_1[10]),
.B1(n2496), .Y(n2452) );
AOI22X1TS U3772 ( .A0(n2479), .A1(FPSENCOS_d_ff2_X[10]), .B0(n1779), .B1(
FPSENCOS_d_ff2_Z[10]), .Y(n2451) );
NAND2X1TS U3773 ( .A(n2452), .B(n2451), .Y(add_subt_data1[10]) );
AOI22X1TS U3774 ( .A0(FPSENCOS_d_ff2_Y[11]), .A1(n2468), .B0(Data_1[11]),
.B1(n2496), .Y(n2454) );
AOI22X1TS U3775 ( .A0(n2507), .A1(FPSENCOS_d_ff2_X[11]), .B0(n2455), .B1(
FPSENCOS_d_ff2_Z[11]), .Y(n2453) );
NAND2X1TS U3776 ( .A(n2454), .B(n2453), .Y(add_subt_data1[11]) );
AOI22X1TS U3777 ( .A0(FPSENCOS_d_ff2_Y[12]), .A1(n2468), .B0(Data_1[12]),
.B1(n2496), .Y(n2457) );
AOI22X1TS U3778 ( .A0(n2507), .A1(FPSENCOS_d_ff2_X[12]), .B0(n2455), .B1(
FPSENCOS_d_ff2_Z[12]), .Y(n2456) );
NAND2X1TS U3779 ( .A(n2457), .B(n2456), .Y(add_subt_data1[12]) );
AOI22X1TS U3780 ( .A0(FPSENCOS_d_ff2_Y[13]), .A1(n2468), .B0(Data_1[13]),
.B1(n2496), .Y(n2459) );
AOI22X1TS U3781 ( .A0(n2507), .A1(FPSENCOS_d_ff2_X[13]), .B0(n2506), .B1(
FPSENCOS_d_ff2_Z[13]), .Y(n2458) );
NAND2X1TS U3782 ( .A(n2459), .B(n2458), .Y(add_subt_data1[13]) );
AOI22X1TS U3783 ( .A0(FPSENCOS_d_ff2_Y[14]), .A1(n2468), .B0(Data_1[14]),
.B1(n2496), .Y(n2461) );
AOI22X1TS U3784 ( .A0(n2507), .A1(FPSENCOS_d_ff2_X[14]), .B0(n2506), .B1(
FPSENCOS_d_ff2_Z[14]), .Y(n2460) );
NAND2X1TS U3785 ( .A(n2461), .B(n2460), .Y(add_subt_data1[14]) );
AOI22X1TS U3786 ( .A0(FPSENCOS_d_ff2_Y[15]), .A1(n2468), .B0(Data_1[15]),
.B1(n2496), .Y(n2463) );
AOI22X1TS U3787 ( .A0(n2507), .A1(FPSENCOS_d_ff2_X[15]), .B0(n2506), .B1(
FPSENCOS_d_ff2_Z[15]), .Y(n2462) );
NAND2X1TS U3788 ( .A(n2463), .B(n2462), .Y(add_subt_data1[15]) );
AOI22X1TS U3789 ( .A0(FPSENCOS_d_ff2_Y[16]), .A1(n2468), .B0(Data_1[16]),
.B1(n2496), .Y(n2465) );
AOI22X1TS U3790 ( .A0(n2479), .A1(FPSENCOS_d_ff2_X[16]), .B0(n1779), .B1(
FPSENCOS_d_ff2_Z[16]), .Y(n2464) );
NAND2X1TS U3791 ( .A(n2465), .B(n2464), .Y(add_subt_data1[16]) );
AOI22X1TS U3792 ( .A0(FPSENCOS_d_ff2_Y[17]), .A1(n2468), .B0(Data_1[17]),
.B1(n2496), .Y(n2467) );
AOI22X1TS U3793 ( .A0(n2507), .A1(FPSENCOS_d_ff2_X[17]), .B0(n1779), .B1(
FPSENCOS_d_ff2_Z[17]), .Y(n2466) );
NAND2X1TS U3794 ( .A(n2467), .B(n2466), .Y(add_subt_data1[17]) );
AOI22X1TS U3795 ( .A0(FPSENCOS_d_ff2_Y[18]), .A1(n2468), .B0(Data_1[18]),
.B1(n2496), .Y(n2470) );
AOI22X1TS U3796 ( .A0(n2507), .A1(FPSENCOS_d_ff2_X[18]), .B0(n1779), .B1(
FPSENCOS_d_ff2_Z[18]), .Y(n2469) );
NAND2X1TS U3797 ( .A(n2470), .B(n2469), .Y(add_subt_data1[18]) );
AOI22X1TS U3798 ( .A0(FPSENCOS_d_ff2_Y[19]), .A1(n2499), .B0(Data_1[19]),
.B1(n2504), .Y(n2472) );
AOI22X1TS U3799 ( .A0(n2501), .A1(FPSENCOS_d_ff2_X[19]), .B0(n2500), .B1(
FPSENCOS_d_ff2_Z[19]), .Y(n2471) );
NAND2X1TS U3800 ( .A(n2472), .B(n2471), .Y(add_subt_data1[19]) );
AOI22X1TS U3801 ( .A0(FPSENCOS_d_ff2_Y[20]), .A1(n2473), .B0(Data_1[20]),
.B1(n2496), .Y(n2476) );
AOI22X1TS U3802 ( .A0(n2474), .A1(FPSENCOS_d_ff2_X[20]), .B0(n2500), .B1(
FPSENCOS_d_ff2_Z[20]), .Y(n2475) );
NAND2X1TS U3803 ( .A(n2476), .B(n2475), .Y(add_subt_data1[20]) );
AOI22X1TS U3804 ( .A0(FPSENCOS_d_ff2_Y[21]), .A1(n2505), .B0(Data_1[21]),
.B1(n2496), .Y(n2478) );
AOI22X1TS U3805 ( .A0(n2501), .A1(FPSENCOS_d_ff2_X[21]), .B0(n2500), .B1(
FPSENCOS_d_ff2_Z[21]), .Y(n2477) );
NAND2X1TS U3806 ( .A(n2478), .B(n2477), .Y(add_subt_data1[21]) );
AOI22X1TS U3807 ( .A0(FPSENCOS_d_ff2_Y[22]), .A1(n2499), .B0(Data_1[22]),
.B1(n2496), .Y(n2481) );
AOI22X1TS U3808 ( .A0(n2507), .A1(FPSENCOS_d_ff2_X[22]), .B0(n2500), .B1(
FPSENCOS_d_ff2_Z[22]), .Y(n2480) );
NAND2X1TS U3809 ( .A(n2481), .B(n2480), .Y(add_subt_data1[22]) );
AOI22X1TS U3810 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n2499), .B0(Data_1[23]),
.B1(n960), .Y(n2484) );
AOI22X1TS U3811 ( .A0(n2482), .A1(FPSENCOS_d_ff2_X[23]), .B0(n2500), .B1(
FPSENCOS_d_ff2_Z[23]), .Y(n2483) );
NAND2X1TS U3812 ( .A(n2484), .B(n2483), .Y(add_subt_data1[23]) );
AOI22X1TS U3813 ( .A0(FPSENCOS_d_ff2_Y[24]), .A1(n2499), .B0(Data_1[24]),
.B1(n2496), .Y(n2486) );
AOI22X1TS U3814 ( .A0(n2501), .A1(FPSENCOS_d_ff2_X[24]), .B0(n2500), .B1(
FPSENCOS_d_ff2_Z[24]), .Y(n2485) );
NAND2X1TS U3815 ( .A(n2486), .B(n2485), .Y(add_subt_data1[24]) );
AOI22X1TS U3816 ( .A0(FPSENCOS_d_ff2_Y[25]), .A1(n2473), .B0(Data_1[25]),
.B1(n2504), .Y(n2488) );
AOI22X1TS U3817 ( .A0(n2501), .A1(FPSENCOS_d_ff2_X[25]), .B0(n2500), .B1(
FPSENCOS_d_ff2_Z[25]), .Y(n2487) );
NAND2X1TS U3818 ( .A(n2488), .B(n2487), .Y(add_subt_data1[25]) );
AOI22X1TS U3819 ( .A0(FPSENCOS_d_ff2_Y[26]), .A1(n2499), .B0(Data_1[26]),
.B1(n2496), .Y(n2490) );
AOI22X1TS U3820 ( .A0(n2482), .A1(FPSENCOS_d_ff2_X[26]), .B0(n2500), .B1(
FPSENCOS_d_ff2_Z[26]), .Y(n2489) );
NAND2X1TS U3821 ( .A(n2490), .B(n2489), .Y(add_subt_data1[26]) );
AOI22X1TS U3822 ( .A0(FPSENCOS_d_ff2_Y[27]), .A1(n2493), .B0(Data_1[27]),
.B1(n2496), .Y(n2492) );
AOI22X1TS U3823 ( .A0(n2482), .A1(FPSENCOS_d_ff2_X[27]), .B0(n2500), .B1(
FPSENCOS_d_ff2_Z[27]), .Y(n2491) );
NAND2X1TS U3824 ( .A(n2492), .B(n2491), .Y(add_subt_data1[27]) );
AOI22X1TS U3825 ( .A0(FPSENCOS_d_ff2_Y[28]), .A1(n2493), .B0(Data_1[28]),
.B1(n960), .Y(n2495) );
AOI22X1TS U3826 ( .A0(n2501), .A1(FPSENCOS_d_ff2_X[28]), .B0(n2500), .B1(
FPSENCOS_d_ff2_Z[28]), .Y(n2494) );
NAND2X1TS U3827 ( .A(n2495), .B(n2494), .Y(add_subt_data1[28]) );
AOI22X1TS U3828 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n2499), .B0(Data_1[29]),
.B1(n2496), .Y(n2498) );
AOI22X1TS U3829 ( .A0(n2501), .A1(FPSENCOS_d_ff2_X[29]), .B0(n2500), .B1(
FPSENCOS_d_ff2_Z[29]), .Y(n2497) );
NAND2X1TS U3830 ( .A(n2498), .B(n2497), .Y(add_subt_data1[29]) );
AOI22X1TS U3831 ( .A0(FPSENCOS_d_ff2_Y[30]), .A1(n2499), .B0(Data_1[30]),
.B1(n2504), .Y(n2503) );
AOI22X1TS U3832 ( .A0(n2501), .A1(FPSENCOS_d_ff2_X[30]), .B0(n2500), .B1(
FPSENCOS_d_ff2_Z[30]), .Y(n2502) );
NAND2X1TS U3833 ( .A(n2503), .B(n2502), .Y(add_subt_data1[30]) );
AOI22X1TS U3834 ( .A0(FPSENCOS_d_ff2_Y[31]), .A1(n2505), .B0(Data_1[31]),
.B1(n2504), .Y(n2509) );
AOI22X1TS U3835 ( .A0(n2507), .A1(FPSENCOS_d_ff2_X[31]), .B0(n2506), .B1(
FPSENCOS_d_ff2_Z[31]), .Y(n2508) );
NAND2X1TS U3836 ( .A(n2509), .B(n2508), .Y(add_subt_data1[31]) );
OA21XLTS U3837 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(n2511), .B0(n2510), .Y(
FPSENCOS_ITER_CONT_N4) );
BUFX3TS U3838 ( .A(n2540), .Y(n2546) );
AOI22X1TS U3839 ( .A0(n2546), .A1(cordic_result[31]), .B0(n2524), .B1(
mult_result[31]), .Y(n2512) );
OAI2BB1X1TS U3840 ( .A0N(n2551), .A1N(result_add_subt[31]), .B0(n2512), .Y(
op_result[31]) );
AOI22X1TS U3841 ( .A0(n2546), .A1(cordic_result[30]), .B0(n2524), .B1(
mult_result[30]), .Y(n2513) );
OAI2BB1X1TS U3842 ( .A0N(n2542), .A1N(result_add_subt[30]), .B0(n2513), .Y(
op_result[30]) );
AOI22X1TS U3843 ( .A0(n2546), .A1(cordic_result[29]), .B0(n2524), .B1(
mult_result[29]), .Y(n2514) );
OAI2BB1X1TS U3844 ( .A0N(n2542), .A1N(result_add_subt[29]), .B0(n2514), .Y(
op_result[29]) );
AOI22X1TS U3845 ( .A0(n2546), .A1(cordic_result[28]), .B0(n2524), .B1(
mult_result[28]), .Y(n2515) );
OAI2BB1X1TS U3846 ( .A0N(n2542), .A1N(result_add_subt[28]), .B0(n2515), .Y(
op_result[28]) );
AOI22X1TS U3847 ( .A0(n2546), .A1(cordic_result[27]), .B0(n2524), .B1(
mult_result[27]), .Y(n2516) );
OAI2BB1X1TS U3848 ( .A0N(n2542), .A1N(result_add_subt[27]), .B0(n2516), .Y(
op_result[27]) );
AOI22X1TS U3849 ( .A0(n2546), .A1(cordic_result[26]), .B0(n2524), .B1(
mult_result[26]), .Y(n2517) );
OAI2BB1X1TS U3850 ( .A0N(n2542), .A1N(result_add_subt[26]), .B0(n2517), .Y(
op_result[26]) );
AOI22X1TS U3851 ( .A0(n2546), .A1(cordic_result[25]), .B0(n2524), .B1(
mult_result[25]), .Y(n2518) );
OAI2BB1X1TS U3852 ( .A0N(n2542), .A1N(result_add_subt[25]), .B0(n2518), .Y(
op_result[25]) );
BUFX3TS U3853 ( .A(n2551), .Y(n2539) );
AOI22X1TS U3854 ( .A0(n2546), .A1(cordic_result[24]), .B0(n2524), .B1(
mult_result[24]), .Y(n2519) );
OAI2BB1X1TS U3855 ( .A0N(n2539), .A1N(result_add_subt[24]), .B0(n2519), .Y(
op_result[24]) );
AOI22X1TS U3856 ( .A0(n2546), .A1(cordic_result[23]), .B0(n2524), .B1(
mult_result[23]), .Y(n2520) );
OAI2BB1X1TS U3857 ( .A0N(n2539), .A1N(result_add_subt[23]), .B0(n2520), .Y(
op_result[23]) );
AOI22X1TS U3858 ( .A0(n2546), .A1(cordic_result[22]), .B0(n2524), .B1(
mult_result[22]), .Y(n2521) );
OAI2BB1X1TS U3859 ( .A0N(n2539), .A1N(result_add_subt[22]), .B0(n2521), .Y(
op_result[22]) );
AOI22X1TS U3860 ( .A0(n2546), .A1(cordic_result[21]), .B0(n2524), .B1(
mult_result[21]), .Y(n2522) );
OAI2BB1X1TS U3861 ( .A0N(n2539), .A1N(result_add_subt[21]), .B0(n2522), .Y(
op_result[21]) );
AOI22X1TS U3862 ( .A0(n2549), .A1(cordic_result[20]), .B0(n2524), .B1(
mult_result[20]), .Y(n2523) );
OAI2BB1X1TS U3863 ( .A0N(n2539), .A1N(result_add_subt[20]), .B0(n2523), .Y(
op_result[20]) );
AOI22X1TS U3864 ( .A0(n2549), .A1(cordic_result[19]), .B0(n2524), .B1(
mult_result[19]), .Y(n2525) );
OAI2BB1X1TS U3865 ( .A0N(n2539), .A1N(result_add_subt[19]), .B0(n2525), .Y(
op_result[19]) );
AOI22X1TS U3866 ( .A0(n2549), .A1(cordic_result[18]), .B0(n2548), .B1(
mult_result[18]), .Y(n2526) );
OAI2BB1X1TS U3867 ( .A0N(n2539), .A1N(result_add_subt[18]), .B0(n2526), .Y(
op_result[18]) );
AOI22X1TS U3868 ( .A0(n2549), .A1(cordic_result[17]), .B0(n2548), .B1(
mult_result[17]), .Y(n2527) );
OAI2BB1X1TS U3869 ( .A0N(n2539), .A1N(result_add_subt[17]), .B0(n2527), .Y(
op_result[17]) );
AOI22X1TS U3870 ( .A0(n2549), .A1(cordic_result[16]), .B0(n2548), .B1(
mult_result[16]), .Y(n2528) );
OAI2BB1X1TS U3871 ( .A0N(n2539), .A1N(result_add_subt[16]), .B0(n2528), .Y(
op_result[16]) );
AOI22X1TS U3872 ( .A0(n2549), .A1(cordic_result[15]), .B0(n2548), .B1(
mult_result[15]), .Y(n2529) );
OAI2BB1X1TS U3873 ( .A0N(n2539), .A1N(result_add_subt[15]), .B0(n2529), .Y(
op_result[15]) );
AOI22X1TS U3874 ( .A0(n2549), .A1(cordic_result[14]), .B0(n2548), .B1(
mult_result[14]), .Y(n2530) );
OAI2BB1X1TS U3875 ( .A0N(n2539), .A1N(result_add_subt[14]), .B0(n2530), .Y(
op_result[14]) );
AOI22X1TS U3876 ( .A0(n2549), .A1(cordic_result[13]), .B0(n2548), .B1(
mult_result[13]), .Y(n2531) );
OAI2BB1X1TS U3877 ( .A0N(n2539), .A1N(result_add_subt[13]), .B0(n2531), .Y(
op_result[13]) );
AOI22X1TS U3878 ( .A0(n2549), .A1(cordic_result[12]), .B0(n2548), .B1(
mult_result[12]), .Y(n2532) );
OAI2BB1X1TS U3879 ( .A0N(n2539), .A1N(result_add_subt[12]), .B0(n2532), .Y(
op_result[12]) );
AOI22X1TS U3880 ( .A0(n2549), .A1(cordic_result[11]), .B0(n2548), .B1(
mult_result[11]), .Y(n2533) );
OAI2BB1X1TS U3881 ( .A0N(n2542), .A1N(result_add_subt[11]), .B0(n2533), .Y(
op_result[11]) );
AOI22X1TS U3882 ( .A0(n2549), .A1(cordic_result[10]), .B0(n2548), .B1(
mult_result[10]), .Y(n2534) );
OAI2BB1X1TS U3883 ( .A0N(n2542), .A1N(result_add_subt[10]), .B0(n2534), .Y(
op_result[10]) );
AOI22X1TS U3884 ( .A0(n2549), .A1(cordic_result[9]), .B0(n2548), .B1(
mult_result[9]), .Y(n2535) );
OAI2BB1X1TS U3885 ( .A0N(n2542), .A1N(result_add_subt[9]), .B0(n2535), .Y(
op_result[9]) );
AOI22X1TS U3886 ( .A0(n2549), .A1(cordic_result[8]), .B0(n2548), .B1(
mult_result[8]), .Y(n2536) );
OAI2BB1X1TS U3887 ( .A0N(n2542), .A1N(result_add_subt[8]), .B0(n2536), .Y(
op_result[8]) );
AOI22X1TS U3888 ( .A0(n2549), .A1(cordic_result[7]), .B0(n2548), .B1(
mult_result[7]), .Y(n2537) );
OAI2BB1X1TS U3889 ( .A0N(n2539), .A1N(result_add_subt[7]), .B0(n2537), .Y(
op_result[7]) );
AOI22X1TS U3890 ( .A0(n2549), .A1(cordic_result[6]), .B0(n2524), .B1(
mult_result[6]), .Y(n2538) );
OAI2BB1X1TS U3891 ( .A0N(n2539), .A1N(result_add_subt[6]), .B0(n2538), .Y(
op_result[6]) );
AOI22X1TS U3892 ( .A0(n2540), .A1(cordic_result[5]), .B0(n2548), .B1(
mult_result[5]), .Y(n2541) );
OAI2BB1X1TS U3893 ( .A0N(n2542), .A1N(result_add_subt[5]), .B0(n2541), .Y(
op_result[5]) );
AOI22X1TS U3894 ( .A0(n2540), .A1(cordic_result[4]), .B0(n2548), .B1(
mult_result[4]), .Y(n2543) );
OAI2BB1X1TS U3895 ( .A0N(n2551), .A1N(result_add_subt[4]), .B0(n2543), .Y(
op_result[4]) );
AOI22X1TS U3896 ( .A0(n2540), .A1(cordic_result[3]), .B0(n2548), .B1(
mult_result[3]), .Y(n2544) );
OAI2BB1X1TS U3897 ( .A0N(n2551), .A1N(result_add_subt[3]), .B0(n2544), .Y(
op_result[3]) );
AOI22X1TS U3898 ( .A0(n2540), .A1(cordic_result[2]), .B0(n2548), .B1(
mult_result[2]), .Y(n2545) );
OAI2BB1X1TS U3899 ( .A0N(n2551), .A1N(result_add_subt[2]), .B0(n2545), .Y(
op_result[2]) );
AOI22X1TS U3900 ( .A0(n2549), .A1(cordic_result[1]), .B0(n2548), .B1(
mult_result[1]), .Y(n2547) );
OAI2BB1X1TS U3901 ( .A0N(n2551), .A1N(result_add_subt[1]), .B0(n2547), .Y(
op_result[1]) );
AOI22X1TS U3902 ( .A0(n2549), .A1(cordic_result[0]), .B0(n2548), .B1(
mult_result[0]), .Y(n2550) );
OAI2BB1X1TS U3903 ( .A0N(n2551), .A1N(result_add_subt[0]), .B0(n2550), .Y(
op_result[0]) );
AOI22X1TS U3904 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n2554), .B0(n2552),
.B1(n2651), .Y(n861) );
AOI22X1TS U3905 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n2554), .B0(n2553),
.B1(n2651), .Y(n853) );
OAI2BB1X1TS U3906 ( .A0N(FPSENCOS_cont_iter_out[1]), .A1N(n851), .B0(n2555),
.Y(n852) );
AOI22X1TS U3907 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n2557), .B0(n2556),
.B1(n2651), .Y(n848) );
INVX2TS U3908 ( .A(n2562), .Y(n2558) );
AOI22X1TS U3909 ( .A0(ack_operation), .A1(n2780), .B0(begin_operation), .B1(
n2558), .Y(n2560) );
OAI22X1TS U3910 ( .A0(n2562), .A1(n2561), .B0(n2560), .B1(n2559), .Y(n846)
);
AO22XLTS U3911 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n2682), .B1(n2563),
.Y(n2565) );
OAI22X1TS U3912 ( .A0(n2566), .A1(n2565), .B0(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B1(n2564), .Y(n844) );
AOI22X1TS U3913 ( .A0(FPSENCOS_cont_var_out[0]), .A1(n2568), .B0(n2567),
.B1(n2649), .Y(n843) );
NAND2X1TS U3914 ( .A(n2589), .B(n2693), .Y(FPADDSUB__6_net_) );
NOR4X1TS U3915 ( .A(FPMULT_Op_MY[26]), .B(FPMULT_Op_MY[25]), .C(
FPMULT_Op_MY[30]), .D(FPMULT_Op_MY[24]), .Y(n2570) );
NAND4XLTS U3916 ( .A(n2572), .B(n2571), .C(n2570), .D(n2569), .Y(n2588) );
NOR3XLTS U3917 ( .A(FPMULT_Op_MY[23]), .B(FPMULT_Op_MY[20]), .C(n970), .Y(
n2575) );
NAND4XLTS U3918 ( .A(n2576), .B(n2575), .C(n2574), .D(n2573), .Y(n2587) );
NAND4XLTS U3919 ( .A(n2580), .B(n2579), .C(n2578), .D(n2577), .Y(n2586) );
NOR3XLTS U3920 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_Op_MX[20]), .C(
FPMULT_Op_MX[1]), .Y(n2583) );
NAND4XLTS U3921 ( .A(n2584), .B(n2583), .C(n2582), .D(n2581), .Y(n2585) );
OAI22X1TS U3922 ( .A0(n2588), .A1(n2587), .B0(n2586), .B1(n2585), .Y(n106)
);
AO22XLTS U3923 ( .A0(busy), .A1(FPADDSUB_SIGN_FLAG_SHT1), .B0(n2693), .B1(
FPADDSUB_SIGN_FLAG_SHT2), .Y(n819) );
AO22XLTS U3924 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_SIGN_FLAG_NRM), .B0(n2589), .B1(FPADDSUB_SIGN_FLAG_SHT1SHT2),
.Y(n816) );
XNOR2X1TS U3925 ( .A(FPADDSUB_intDX_EWSW[31]), .B(n2828), .Y(n30) );
AO22XLTS U3926 ( .A0(busy), .A1(FPADDSUB_OP_FLAG_SHT1), .B0(n2693), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n813) );
NOR2BX1TS U3927 ( .AN(FPADDSUB_Shift_reg_FLAGS_7[3]), .B(
FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(FPADDSUB__19_net_) );
NOR2XLTS U3928 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n2591), .Y(n2590) );
XOR2XLTS U3929 ( .A(n2590), .B(FPSENCOS_d_ff2_Y[30]), .Y(
FPSENCOS_sh_exp_y[7]) );
XNOR2X1TS U3930 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n2591), .Y(
FPSENCOS_sh_exp_y[6]) );
AO21XLTS U3931 ( .A0(intadd_1085_n1), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n2592),
.Y(FPSENCOS_sh_exp_y[4]) );
NOR2XLTS U3932 ( .A(FPSENCOS_d_ff2_X[29]), .B(n2594), .Y(n2593) );
XOR2XLTS U3933 ( .A(n2593), .B(FPSENCOS_d_ff2_X[30]), .Y(
FPSENCOS_sh_exp_x[7]) );
XNOR2X1TS U3934 ( .A(FPSENCOS_d_ff2_X[29]), .B(n2594), .Y(
FPSENCOS_sh_exp_x[6]) );
AO21XLTS U3935 ( .A0(intadd_1084_n1), .A1(FPSENCOS_d_ff2_X[27]), .B0(n2595),
.Y(FPSENCOS_sh_exp_x[4]) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_KOA_2STAGE_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRBP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SDFRBP_PP_BLACKBOX_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRBP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFXBP_TB_V
`define SKY130_FD_SC_HD__DFXBP_TB_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfxbp.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__dfxbp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFXBP_TB_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/13/2015 03:30:05 PM
// Design Name:
// Module Name: loop_ctrl
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module loop_ctrl(
input clk100,
input rst,
input [3:0] btns, //btns = [back, stop/delete, play/record, next]
output reg [7:0] playing,
output reg [7:0] recording,
output reg [7:0] active,
output reg delete,
output reg [2:0] delete_bank,
input delete_clear,
output reg [2:0] bank,
input [22:0]current_max,
output reg set_max,
output reg reset_max
);
//State Machine states
parameter DEFAULT = 4'b0000;
parameter PLAY = 4'b0001;
parameter RECORD = 4'b0010;
parameter DELETE = 4'b0011;
parameter STOP = 4'b0100;
parameter PBTNDB = 4'b0101;
parameter PDELBTNDB = 4'b0110;
parameter DELETEOTHERS = 4'b0111;
parameter DEFAULT_DB = 4'b1000;
`define BACK 0
`define STOP 1
`define PLAY 2
`define FORWARD 3
initial delete = 1'b0;
initial delete_bank = 1'b0;
initial playing = 4'b0000;
initial recording = 4'b0000;
initial active = 4'b0000;
initial bank = 3'b000;
reg [3:0] pstate = DEFAULT;
reg [3:0] nstate = DEFAULT;
//Delete counter stuff
parameter count_max = 150000000;
reg delay_en = 0;
reg delay_done = 0;
reg [27:0] counter=0;
//Main State Machine
always @ (posedge (clk100))
begin
if (rst == 1)begin
pstate <= DEFAULT;
reset_max <= 1;
set_max <= 0;
active <= 4'b0000;
delay_en <= 0;
playing <= 4'b0000;
recording <= 4'b0000;
delete <= 1'b0;
delete_bank <= 1'b0;
bank<=3'b000;
end
else begin
if(delete_clear)delete<=1'b0;
case (pstate)
DEFAULT: begin
reset_max <= 0;
set_max <= 0;
if((btns[`BACK] == 1))begin //Back bank button
bank<=bank-1;
pstate <= DEFAULT_DB;
end
else if (btns[`FORWARD] == 1) begin //Forward bank button pressed
bank<=bank+1;
pstate <= DEFAULT_DB;
end
else if (btns[`STOP] == 1) begin
pstate <= STOP;
end
else if (btns[`PLAY] == 1) begin
if (active[bank] == 0) //The current bank is not recorded on yet
pstate <= RECORD; //So record onto it
else begin //The current bank is recorded on already
if (playing[bank] == 0)//If the current bank is not playing
pstate <= PLAY;
else //The current bank is playing already
pstate <= RECORD;
end
end
end //End DEFAULT
DEFAULT_DB: begin
if (btns==0) //Wait until button is released
pstate <= DEFAULT;
end
PLAY: begin
playing[bank] <= 1;
recording[bank] <= 0;
set_max<=0;
if(btns[`PLAY] == 0)begin
pstate <= nstate;
end
end
RECORD: begin //Play button is held down still
recording[bank] <= 1;
playing[bank] <= 0;
if(btns[`PLAY] == 0)begin //Play button is released, go to the db state
pstate <= PBTNDB;
end
else if(btns[`STOP])begin
pstate <= DELETE;
end
end
PBTNDB: begin //Play button is released, still recording
if (btns[`STOP]==1)//Stop button pressed, delete the bank
pstate<=DELETE;
else if(btns[`PLAY] == 1)begin //Play button is pressed again
active[bank] <= 1; //This bank is now active
if(current_max == 0)begin //If there is no other banks recorded on (max is 0 still) delete the other banks!
set_max <= 1;//Set the max flag
delete_bank<=bank+1;//Delete the other banks
delete<=1;//Turn on delete
nstate <=DELETEOTHERS;//After the play state, we will go to the DELETEOTHERS state instead of default
end
pstate<=PLAY;//Then go to PLAY state to start the track
end
end
DELETEOTHERS: begin
nstate<=DEFAULT;//Reset nstate
if (delete==0)begin//If done deleting
delete_bank=delete_bank+1;//Increment delete_bank
if (active[delete_bank]==0)begin//If the new bank isn't recorded on
delete<=1;//Delete the old data on that bank
end
else//If the new bank is recorded on, we know it is the first loop, so return
pstate<= DEFAULT;
end
end
DELETE: begin
delete <= 1;
delete_bank <= bank;
recording[bank] <= 0;
active[bank] <= 0;
pstate <= PDELBTNDB;
end
PDELBTNDB: begin
if(active == 8'b00000000)begin//All of the banks are erased
reset_max <= 1;//Reset_max flag is set for one cycle
end
if (btns[`STOP]==0)//Debounce, wait until the stop button is released
pstate<=DEFAULT;
end
STOP: begin
delay_en <= 1;//Start delay counter
playing[bank] <= 0;//Stop playing the bank
if(btns[`STOP] == 0)begin //If the stop button is released before 1.5 seconds
delay_en <= 0;//Stop and reset the delete counter
pstate <= DEFAULT;//Return to DEFAULT
end
else if(delay_done == 1)begin //If the stop button is held for 1.5 seconds, delete
delay_en <= 0;//Turn off the delete counter
pstate <= DELETE;//Delete the bank
end
end
endcase
end//End else if reset
end
//Delete hold timer
always @(posedge (clk100))begin
if(delay_en==0)begin
counter <= 0;
delay_done <= 0;
end
else if(counter < count_max) begin
counter <= counter + 1;
delay_done <= 0;
end
else begin
counter <= 0;
delay_done <= 1;
end
end
endmodule
|
//
// Copyright (C) 2013 Chris McClelland
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module
top_level(
// USB interface -----------------------------------------------------------------------------
input wire sysClk_in, // 50MHz system clock
input wire serClk_in, // serial clock (async to sysClk_in)
input wire serData_in, // serial data in
output wire serData_out, // serial data out
// Onboard peripherals -----------------------------------------------------------------------
output wire[7:0] sseg_out, // seven-segment display cathodes (one for each segment)
output wire[3:0] anode_out, // seven-segment display anodes (one for each digit)
output wire[7:0] led_out, // eight LEDs
input wire[7:0] sw_in // eight switches
);
// Channel read/write interface -----------------------------------------------------------------
wire[6:0] chanAddr; // the selected channel (0-127)
// Host >> FPGA pipe:
wire[7:0] h2fData; // data lines used when the host writes to a channel
wire h2fValid; // '1' means "on the next clock rising edge, please accept the data on h2fData"
wire h2fReady; // channel logic can drive this low to say "I'm not ready for more data yet"
// Host << FPGA pipe:
wire[7:0] f2hData; // data lines used when the host reads from a channel
wire f2hValid; // channel logic can drive this low to say "I don't have data ready for you"
wire f2hReady; // '1' means "on the next clock rising edge, put your next byte of data on f2hData"
// ----------------------------------------------------------------------------------------------
// CommFPGA module
comm_fpga_ss comm_fpga_ss(
.clk_in(sysClk_in),
.reset_in(1'b0),
// USB interface
.serClk_in(serClk_in),
.serData_in(serData_in),
.serData_out(serData_out),
// DVR interface -> Connects to application module
.chanAddr_out(chanAddr),
.h2fData_out(h2fData),
.h2fValid_out(h2fValid),
.h2fReady_in(h2fReady),
.f2hData_in(f2hData),
.f2hValid_in(f2hValid),
.f2hReady_out(f2hReady)
);
// Switches & LEDs application
swled swled_app(
.clk_in(sysClk_in),
.reset_in(1'b0),
// DVR interface -> Connects to comm_fpga module
.chanAddr_in(chanAddr),
.h2fData_in(h2fData),
.h2fValid_in(h2fValid),
.h2fReady_out(h2fReady),
.f2hData_out(f2hData),
.f2hValid_out(f2hValid),
.f2hReady_in(f2hReady),
// External interface
.sseg_out(sseg_out),
.anode_out(anode_out),
.led_out(led_out),
.sw_in(sw_in)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD1_BEHAVIORAL_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD1_BEHAVIORAL_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__clkdlyinv5sd1 (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD1_BEHAVIORAL_V |
/*
* Copyright 2013, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* "is_last" == 0 means byte number is 8, no matter what value "byte_num" is. */
/* if "in_ready" == 0, then "is_last" should be 0. */
/* the user switch to next "in" only if "ack" == 1. */
module padder(clk, reset, in, in_ready, is_last, byte_num, buffer_full, out, out_ready, f_ack);
input clk, reset;
input [63:0] in;
input in_ready, is_last;
input [2:0] byte_num;
output buffer_full; /* to "user" module */
output reg [575:0] out; /* to "f_permutation" module */
output out_ready; /* to "f_permutation" module */
input f_ack; /* from "f_permutation" module */
reg state; /* state == 0: user will send more input data
* state == 1: user will not send any data */
reg done; /* == 1: out_ready should be 0 */
reg [8:0] i; /* length of "out" buffer */
wire [63:0] v0; /* output of module "padder1" */
reg [63:0] v1; /* to be shifted into register "out" */
wire accept, /* accept user input? */
update;
assign buffer_full = i[8];
assign out_ready = buffer_full;
assign accept = (~ state) & in_ready & (~ buffer_full); // if state == 1, do not eat input
assign update = (accept | (state & (~ buffer_full))) & (~ done); // don't fill buffer if done
always @ (posedge clk)
if (reset)
out <= 0;
else if (update)
out <= {out[575-64:0], v1};
always @ (posedge clk)
if (reset)
i <= 0;
else if (f_ack | update)
i <= {i[7:0], 1'b1} & {9{~ f_ack}};
/* if (f_ack) i <= 0; */
/* if (update) i <= {i[7:0], 1'b1}; // increase length */
always @ (posedge clk)
if (reset)
state <= 0;
else if (is_last)
state <= 1;
always @ (posedge clk)
if (reset)
done <= 0;
else if (state & out_ready)
done <= 1;
padder1 p0 (in, byte_num, v0);
always @ (*)
begin
if (state)
begin
v1 = 0;
v1[7] = v1[7] | i[7]; /* "v1[7]" is the MSB of its last byte */
end
else if (is_last == 0)
v1 = in;
else
begin
v1 = v0;
v1[7] = v1[7] | i[7];
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08/06/2014 01:08:23 PM
// Design Name:
// Module Name: seg_scroll_QU
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Seg_Scroll_QU(
input clk,
input clr,
input [19:0] scroll_datain_QU,
output [15:0] scroll_dataout_QU
);
reg [26:0] q;
reg [23:0] msg_array;
always @(posedge clk_3 or posedge clr)
begin
if(clr==1)
begin
msg_array [19:0] <= scroll_datain_QU[19:0];
msg_array [23:20] <= 'hC;
end
else
begin
msg_array [19:0] <= msg_array[23:4];
msg_array [23:20] <= msg_array[3:0];
end
end
assign scroll_dataout_QU[15:0] = msg_array[15:0];
// 3 Hz scroll clk generator
always @(posedge clk or posedge clr)
begin
if(clr==1)
q<=0;
else
q<=q+1;
end
assign clk_3 = q[26];
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:29:54 03/26/2014
// Design Name:
// Module Name: div
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module div(/*AUTOARG*/
// Outputs
data_q, data_r, done,
// Inputs
clk, start, data_a, data_b, sign
);
input clk, start;
input [31:0] data_a, data_b;
input sign; /* sign or unsigned */
output [31:0] data_q, data_r;
output done;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg done;
// End of automatics
/*AUTOWIRE*/
wire [32:0] sub_add;
wire [31:0] data_r_t;
reg [31:0] reg_q;
reg [31:0] reg_r;
reg [31:0] reg_b;
reg [5:0] count;
reg r_sign;
reg isneg;
always @(posedge clk) begin
if(start) begin
reg_r <= 32'b0;
reg_q <= (data_a[31] & sign) ? {~data_a[31:0] + 1} : data_a;
reg_b <= (data_b[31] & sign) ? {~data_b[31:0] + 1} : data_b;
count <= 6'b0;
r_sign <= 0;
done <= 0;
isneg <= data_a[31] ^ data_b[31];
end else if(~done) begin
reg_r <= sub_add[31:0];
r_sign <= sub_add[32];
reg_q <= {reg_q[30:0], ~sub_add[32]};
count <= count + 6'b000001;
if (count == 6'b011111) done <= 1;
end
end
assign sub_add = r_sign ? {reg_r, reg_q[31]} + {1'b0, reg_b} : {reg_r, reg_q[31]} - {1'b0, reg_b};
assign data_r_t = r_sign ? reg_r + reg_b : reg_r;
assign data_r = data_a[31] ? ~data_r_t + 1 : data_r_t;
assign data_q = (isneg & sign) ? {~reg_q[31:0] + 1} : reg_q;
endmodule
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 17872 $
// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module TriState
(
// Outputs
O,
// Inouts
IO,
// Inputs
OE, I
);
parameter width = 1;
input OE;
input [width-1:0] I;
output [width-1:0] O;
inout [width-1:0] IO;
assign IO = (OE) ? I : { width { 1'bz } };
assign O = IO;
endmodule // TriState
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_charFromReceiver (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 7: 0] in_port;
input reset_n;
wire clk_en;
wire [ 7: 0] data_in;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2018 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Local Clock Buffer for I/O
// /___/ /\ Filename : BUFIO.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 03/23/04 - Initial version.
// 05/30/07 - Changed timescale to 1 ps / 1 ps.
// 12/13/11 - 524859 - Added `celldefine and `endcelldefine
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFIO
`ifdef XIL_TIMING
#(
parameter LOC = "UNPLACED"
)
`endif
(
output O,
input I
);
// define constants
localparam MODULE_NAME = "BUFIO";
`ifdef XIL_TIMING
reg notifier;
`endif
// begin behavioral model
buf B1 (O, I);
// end behavioral model
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
$period (negedge I, 0:0:0, notifier);
$period (posedge I, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
`endif
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRBP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__SDFRBP_PP_SYMBOL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRBP_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB4TO1_BLACKBOX_V
`define SKY130_FD_SC_HDLL__MUXB4TO1_BLACKBOX_V
/**
* muxb4to1: Buffered 4-input multiplexer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__muxb4to1 (
Z,
D,
S
);
output Z;
input [3:0] D;
input [3:0] S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB4TO1_BLACKBOX_V
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Matrix Arbiter
*
* See Dally/Towles (p.359) for implementation details and full description
*
* Multistage Options
* ==================
*
* [multistage=0] Arbiter state is updated whenever a request is granted.
*
* [multistage=1] This arbiter is meant for situations where the initial
* request must progress through multiple stages of arbitration. An
* additional input to the arbiter (success) ensures that the state of
* the arbiter is only updated if the request is finally granted (at the
* last stage of arbitration).
*
* || This assumes 'success' is produced before the end of the current clock
* || cycle.
*
* [multistage=2] Used in situations where multistage=1 would be, but when
* 'success' is not available until the next clock cycle.
*
*
*/
module comb_matrix_arb_next_state (state, grant, new_state);
parameter size=4;
input [size*size-1:0] state;
input [size-1:0] grant;
output [size*size-1:0] new_state;
genvar i,j;
generate
for (i=0; i<size; i=i+1) begin:ol2
for (j=0; j<size; j=j+1) begin:il2
assign new_state[j*size+i]= (state[j*size+i]&&!grant[j])||(grant[i]);
end
end
endgenerate
endmodule // comb_matrix_arb_next_state
module matrix_arb (request, grant, success, clk, rst_n);
parameter size= 4;
parameter multistage = 0;
parameter grant_hold = 0;
input [size-1:0] request;
output [size-1:0] grant;
input success;
input clk, rst_n;
genvar i,j;
logic [size-1:0] req;
logic [size-1:0] newgrant;
logic [size*size-1:0] next_state, current_state;
logic [size-1:0] pri [size-1:0];
logic [size*size-1:0] new_state;
logic [size*size-1:0] state;
logic update;
genvar r;
integer k;
assign req=request;
// ##########################################
// Generate grants
// ##########################################
generate
for (i=0; i<size; i=i+1) begin:ol1
// generate grant i
for (j=0; j<size; j=j+1) begin:il1
if (j==i)
// request i wins if requesting and....
assign pri[i][j]=req[i];
else
// ....no other request with higher priority
if (j>i)
// j beats i
assign pri[i][j]=!(req[j]&&state[j*size+i]);
else
// !(i beats j)
assign pri[i][j]=!(req[j]&&!state[i*size+j]);
end
assign grant[i]=&pri[i];
end
endgenerate
generate
if (multistage==2) begin
assign state = success ? next_state : current_state;
end else begin
assign state = current_state;
end
endgenerate
//
// calculate next matrix state based on current requests and grants
//
comb_matrix_arb_next_state #(size) calc_next (.*);
always@(posedge clk) begin
if (!rst_n) begin
current_state<='1; //-1;
next_state<='1; //-1;
end else begin
// **************************************************
// Multistage Arbiter with Late Success Notification (multistage==2)
// **************************************************
if (multistage==2) begin
update<=|req;
if (|req) begin
// This 'next_state' will only be used on next clock cycle if
// 'success' is asserted
next_state <= new_state;
end
if (update) begin
current_state <= state;
end
end else begin
// ************************************
// Multistage Arbiter (multistage==1)
// ************************************
// check request was ultimately successful before updating arbiter state
// we know about success before the next clock cycle.
if ((multistage==1)&!success) begin
// request was not ultimately successful, don't update priorities
end else begin
// **********************************
// Basic Arbiter (multistage==0)
// **********************************
// Update state whenever at least one request has been made
if (|req) begin
current_state<=new_state;
end
end
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2BB2A_TB_V
`define SKY130_FD_SC_HD__O2BB2A_TB_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o2bb2a.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1_N = 1'b1;
#200 A2_N = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1_N = 1'b0;
#360 A2_N = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2_N = 1'b1;
#640 A1_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2_N = 1'bx;
#800 A1_N = 1'bx;
end
sky130_fd_sc_hd__o2bb2a dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2BB2A_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2BB2OI_2_V
`define SKY130_FD_SC_HD__A2BB2OI_2_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a2bb2oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a2bb2oi_2 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a2bb2oi_2 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2BB2OI_2_V
|
// -*- Mode: Verilog -*-
// Filename : wb_master_interface.v
// Description : Wishbone Bus Master
// Author : Philip Tracton
// Created On : Fri Nov 27 16:22:45 2015
// Last Modified By: Philip Tracton
// Last Modified On: Fri Nov 27 16:22:45 2015
// Update Count : 0
// Status : Unknown, Use with caution!
module wb_master_interface (/*AUTOARG*/
// Outputs
wb_adr_o, wb_dat_o, wb_sel_o, wb_we_o, wb_cyc_o, wb_stb_o,
wb_cti_o, wb_bte_o, data_rd, active,
// Inputs
wb_clk, wb_rst, wb_dat_i, wb_ack_i, wb_err_i, wb_rty_i, start,
address, selection, write, data_wr
) ;
parameter dw = 32;
parameter aw = 32;
parameter DEBUG = 0;
input wb_clk;
input wb_rst;
output reg [aw-1:0] wb_adr_o;
output reg [dw-1:0] wb_dat_o;
output reg [3:0] wb_sel_o;
output reg wb_we_o ;
output reg wb_cyc_o;
output reg wb_stb_o;
output reg [2:0] wb_cti_o;
output reg [1:0] wb_bte_o;
input [dw-1:0] wb_dat_i;
input wb_ack_i;
input wb_err_i;
input wb_rty_i;
input start;
input [aw-1:0] address;
input [3:0] selection;
input write;
input [dw-1:0] data_wr;
output reg [dw-1:0] data_rd;
output reg active;
reg [1:0] state;
reg [1:0] next_state;
parameter STATE_IDLE = 2'h0;
parameter STATE_WAIT_ACK = 2'h1;
parameter STATE_ERROR = 2'h3;
always @(posedge wb_clk)
if (wb_rst) begin
state <= STATE_IDLE;
end else begin
state <= next_state;
end
always @(*)
if (wb_rst) begin
next_state = STATE_IDLE;
active = 0;
wb_adr_o <= 0;
wb_dat_o <= 0;
wb_sel_o <= 0;
wb_we_o <= 0;
wb_cyc_o <= 0;
wb_stb_o <= 0;
wb_cti_o <= 0;
wb_bte_o <= 0;
data_rd <= 0;
end else begin // if (wb_rst)
case (state)
STATE_IDLE: begin
active = 0;
wb_adr_o = 0;
wb_dat_o = 0;
wb_sel_o = 0;
wb_we_o = 0;
wb_cyc_o = 0;
wb_stb_o = 0;
wb_cti_o = 0;
wb_bte_o = 0;
if (start) begin
next_state = STATE_WAIT_ACK;
wb_adr_o = address;
wb_dat_o = data_wr;
wb_sel_o = selection;
wb_we_o = write;
wb_cyc_o = 1;
wb_stb_o = 1;
wb_cti_o = 0;
wb_bte_o = 0;
active = 1;
data_rd =0;
end else begin
next_state = STATE_IDLE;
end
end // case: STATE_IDLE
STATE_WAIT_ACK: begin
if (wb_err_i || wb_rty_i) begin
next_state = STATE_ERROR;
end else if (wb_ack_i) begin
if (! wb_we_o)
data_rd = wb_dat_i;
next_state = STATE_IDLE;
end else begin
next_state = STATE_WAIT_ACK;
end
end // case: STATE_WAIT_ACK
STATE_ERROR: begin
next_state = STATE_IDLE;
end
default: begin
next_state = STATE_IDLE;
end
endcase // case (state)
end
`ifdef SIM
reg [32*8-1:0] state_name;
always @(*)
case (state)
STATE_IDLE: state_name = "IDLE";
STATE_WAIT_ACK: state_name = "WAIT ACK";
STATE_ERROR:state_name = "ERROR";
default: state_name = "DEFAULT";
endcase // case (state)
`endif
endmodule // testing_wb_master
|
/*******************************************************
MIST32 Standard Device : Display Device
- Support Display Area
-640*480 (60Hz) : 25MHz
-800x480 (60Hz) : 33.2MHz
-800x600 (75Hz) : 49MHz
-1024x768 (70Hz) : 75MHz
- Charactor Size : 14*8
- Display Size(Charactor Count)
80
|---------------|
| |
34 | |
| |
|---------------|
- Memory MAP
0~3FF : Node Special Memory
400 : 1Line Charactor Set (Data : ANSI Charactor = 7bit) {BackColor[31:20], CharactorColor[19:8], none[7], Charactor[6:0]}
800 : 2Line Charactor Set (Data : ANSI Charactor = 7bit) {BackColor[31:20], CharactorColor[19:8], none[7], Charactor[6:0]}
~
8400 : 32Line Charactor Set (Data : ANSI Charactor = 7bit) {BackColor[31:20], CharactorColor[19:8], none[7], Charactor[6:0]}
C000 : Display Clear CMD (Data : Collor 16bit = 5R6G5B) {none[31:16], Color[15:0]}
C400 : Bitmap 0 (Data : Collor 15bit = 5R6G5B) {none[31:16], Color[15:0]}
~
1383FC : Bitmap 307199 (Data : Collor 15bit = 5R6G5B) {none[31:16], Color[15:0]}
Make : 2011/07/17
Update : 2011/10/08
2011/10/08
Bug Fix : (Final Line Bug)
Charactor Color & Charactor Back Color Adding
2011/10/01
Memory Access Timing Miss Fix
2011/09/25
Memory Write Timing Optimization
*******************************************************/
`default_nettype none
/*
`define IRQCODE_MEMOVER 24'h000000 //Charactor Display Device Memory Size Over Access
`define IRQCODE_READACC 24'h000001 //Read Access
*/
module gci_std_display(
//System
input wire iCLOCK,
input wire inRESET,
//BUS(DATA)-Input
input wire iDEV_REQ,
output wire oDEV_BUSY,
input wire iDEV_RW,
input wire [31:0] iDEV_ADDR, //Byte Address
input wire [31:0] iDEV_DATA,
//BUS(DATA)-Output
output wire oDEV_REQ,
input wire iDEV_BUSY,
output wire [31:0] oDEV_DATA,
//IRQ
output wire oDEV_IRQ_REQ,
input wire iDEV_IRQ_BUSY,
output wire [23:0] oDEV_IRQ_DATA,
input wire iDEV_IRQ_ACK,
//Display Clock
input wire iVGA_CLOCK,
`ifdef GCI_STD_DISPLAY_SRAM
//SRAM
output wire onSRAM_CE,
output wire onSRAM_WE,
output wire onSRAM_OE,
output wire onSRAM_UB,
output wire onSRAM_LB,
output wire [19:0] oSRAM_ADDR,
inout wire [15:0] ioSRAM_DATA,
`elsif GCI_STD_DISPLAY_SSRAM
//SSRAM
output wire oSSRAM_CLOCK,
output wire onSSRAM_ADSC,
output wire onSSRAM_ADSP,
output wire onSSRAM_ADV,
output wire onSSRAM_GW,
output wire onSSRAM_OE,
output wire onSSRAM_WE,
output wire [3:0] onSSRAM_BE,
output wire onSSRAM_CE1,
output wire oSSRAM_CE2,
output wire onSSRAM_CE3,
output wire [18:0] oSSRAM_ADDR,
inout wire [31:0] ioSSRAM_DATA,
inout wire [3:0] ioSSRAM_PARITY,
`endif
//Display
output wire oDISP_CLOCK,
output wire onDISP_RESET,
output wire oDISP_ENA,
output wire oDISP_BLANK,
output wire onDISP_HSYNC,
output wire onDISP_VSYNC,
output wire [9:0] oDISP_DATA_R,
output wire [9:0] oDISP_DATA_G,
output wire [9:0] oDISP_DATA_B
);
/************************************************************
Wire
************************************************************/
//Display Controllor
wire displaycontroller_wait;
//Condition
wire special_addr_use_condition;
wire display_addr_wr_condition;
//Special Memory
wire [31:0] special_memory_rd_data;
//Data Output Buffer
reg b_req;
reg [31:0] b_data;
/************************************************************
Condition
************************************************************/
assign special_addr_use_condition = iDEV_REQ && (iDEV_ADDR < 32'h00000400) && !displaycontroller_wait;
assign display_addr_wr_condition = iDEV_REQ && (iDEV_ADDR >= 32'h00000400) && !displaycontroller_wait;
/************************************************************
Special Memory
************************************************************/
gci_std_display_device_special_memory #(32'h001383FC + 32'h4, 32'h00000000, 32'h00000002) VGA640X480_60HZ_SPECIAL_MEM(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iSPECIAL_REQ(special_addr_use_condition),
.iSPECIAL_RW(iDEV_RW),
.iSPECIAL_ADDR(iDEV_ADDR[9:2]),
.iSPECIAL_DATA(iDEV_DATA),
.oSPECIAL_DATA(special_memory_rd_data)
);
/************************************************************
Display Controller
************************************************************/
gci_std_display_display_controller DISPLAY_MODULE(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Display Clock
.iDISP_CLOCK(iVGA_CLOCK),
//Write Reqest
.iIF_WR_REQ(display_addr_wr_condition),
.oIF_WR_BUSY(displaycontroller_wait),
.iIF_WR_ADDR({2'h0, iDEV_ADDR[31:2]}),
.iIF_WR_DATA(iDEV_DATA),
//SRAM
`ifdef GCI_STD_DISPLAY_SRAM
.onSRAM_CE(onSRAM_CE),
.onSRAM_WE(onSRAM_WE),
.onSRAM_OE(onSRAM_OE),
.onSRAM_UB(onSRAM_UB),
.onSRAM_LB(onSRAM_LB),
.oSRAM_ADDR(oSRAM_ADDR),
.ioSRAM_DATA(ioSRAM_DATA),
//SSRAM
`elsif GCI_STD_DISPLAY_SSRAM
.oSSRAM_CLOCK(oSSRAM_CLOCK),
.onSSRAM_ADSC(onSSRAM_ADSC),
.onSSRAM_ADSP(onSSRAM_ADSP),
.onSSRAM_ADV(onSSRAM_ADV),
.onSSRAM_GW(onSSRAM_GW),
.onSSRAM_OE(onSSRAM_OE),
.onSSRAM_WE(onSSRAM_WE),
.onSSRAM_BE(onSSRAM_BE),
.onSSRAM_CE1(onSSRAM_CE1),
.oSSRAM_CE2(oSSRAM_CE2),
.onSSRAM_CE3(onSSRAM_CE3),
.oSSRAM_ADDR(oSSRAM_ADDR),
.ioSSRAM_DATA(ioSSRAM_DATA),
.ioSSRAM_PARITY(ioSSRAM_PARITY),
`endif
//Display
.oDISP_CLOCK(oDISP_CLOCK),
.onDISP_RESET(onDISP_RESET),
.oDISP_ENA(oDISP_ENA),
.oDISP_BLANK(oDISP_BLANK),
.onDISP_HSYNC(onDISP_HSYNC),
.onDISP_VSYNC(onDISP_VSYNC),
.oDISP_DATA_R(oDISP_DATA_R),
.oDISP_DATA_G(oDISP_DATA_G),
.oDISP_DATA_B(oDISP_DATA_B)
);
/************************************************************
Output Buffer
************************************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_req <= 1'b0;
b_data <= {32{1'b0}};
end
else begin
b_req <= (special_addr_use_condition || display_addr_wr_condition);
b_data <= (special_addr_use_condition)? special_memory_rd_data : {32{1'b0}};
end
end
/************************************************************
Assign
************************************************************/
assign oDEV_BUSY = displaycontroller_wait;
assign oDEV_REQ = b_req;
assign oDEV_DATA = b_data;
assign oDEV_IRQ_REQ = 1'b0;
assign oDEV_IRQ_DATA = {24{1'b0}};
endmodule
`default_nettype wire
|
`define VD 1'b1
`define IN 1'b0
module decode_core(
collated_instr,
collate_done,
collate_required,
fu,
opcode,
imm_value0,
imm_value1,
s1_field,
s2_field,
s3_field,
s4_field,
dest1_field,
dest2_field
);
input [63:0] collated_instr;
input collate_done;
output collate_required;
output [1:0] fu;
output [31:0] opcode;
output [15:0] imm_value0;
output [31:0] imm_value1;
output [9:0] s1_field;
output [9:0] s2_field;
output [9:0] s3_field;
output [9:0] s4_field;
output [9:0] dest1_field;
output [9:0] dest2_field;
reg collate_required;
reg wf_halt;
reg wf_barrier;
reg wf_branch;
reg [1:0] fu;
reg [31:0] opcode;
reg [15:0] imm_value0;
reg [31:0] imm_value1;
reg scc_write;
reg scc_read;
reg vcc_write;
reg vcc_read;
reg exec_read;
reg [9:0] s1_field;
reg [9:0] s2_field;
reg [9:0] s3_field;
reg [9:0] s4_field;
reg [9:0] dest1_field;
reg [9:0] dest2_field;
always @(collated_instr or collate_done)
begin
casex(collated_instr[31:0]) //for 64bit instructions lower word is decoded
//SOPP
32'b1011_1111_1???_????_????_????_????_????:
begin
collate_required <= 1'b0;
fu <= 2'b10;
opcode[31:24] <= 8'd1;
opcode[23:0] <= {17'b0,collated_instr[22:16]};
imm_value0 <= collated_instr[15:0];
imm_value1 <= {32{1'bx}};
s1_field <= {`IN,{9{1'bx}}};
s2_field <= {`IN,{9{1'bx}}};
s3_field <= {`IN,{9{1'bx}}};
s4_field <= {`IN,{9{1'bx}}};
dest1_field <= {`IN,{9{1'bx}}};
dest2_field <= {`IN,{9{1'bx}}};
end
//SOP1
32'b1011_1110_1???_????_????_????_????_????:
begin
collate_required <= 1'b0;
fu <= 2'b10;
opcode[31:24] <= 8'd2;
opcode[23:0] <= {16'b0,collated_instr[15:8]};
imm_value0 <= {16{1'bx}};
imm_value1 <= collate_done ? collated_instr[63:32] : {32{1'bx}};
s1_field <= {`VD,1'b0,collated_instr[7:0]}; //SSRC8
s2_field <= {`IN,{9{1'bx}}};
s3_field <= {`IN,{9{1'bx}}};
s4_field <= {`IN,{9{1'bx}}};
dest1_field <= {`VD,2'b0,collated_instr[22:16]}; //SDST7
dest2_field <= {`IN,{9{1'bx}}};
end
//SOPC
32'b1011_1111_0???_????_????_????_????_????:
begin
collate_required <= 1'b0;
fu <= 2'b10;
opcode[31:24] <= 8'd4;
opcode[23:0] <= {17'b0,collated_instr[22:16]};
imm_value0 <= {16{1'bx}};
imm_value1 <= collate_done ? collated_instr[63:32] : {32{1'bx}};
s1_field <= {`VD,1'b0,collated_instr[7:0]}; //SSRC8
s2_field <= {`VD,1'b0,collated_instr[15:8]}; //SSRC8
s3_field <= {`IN,{9{1'bx}}};
s4_field <= {`IN,{9{1'bx}}};
dest1_field <= {`IN,{9{1'bx}}};
dest2_field <= {`IN,{9{1'bx}}};
end
//SOPK
32'b1011_????_????_????_????_????_????_????:
begin
collate_required <= 1'b0;
fu <= 2'b10;
opcode[31:24] <= 8'd16;
opcode[23:0] <= {19'b0,collated_instr[27:23]};
imm_value0 <= collated_instr[15:0];
imm_value1 <= {32{1'bx}};
s1_field <= {`IN,{9{1'bx}}};
s2_field <= {`IN,{9{1'bx}}};
s3_field <= {`IN,{9{1'bx}}};
s4_field <= {`IN,{9{1'bx}}};
dest1_field <= {`VD,2'b0,collated_instr[22:16]}; //SDST7
dest2_field <= {`IN,{9{1'bx}}};
end
//SOP2
32'b10??_????_????_????_????_????_????_????:
begin
collate_required <= 1'b0;
fu <= 2'b10;
opcode[31:24] <= 8'd8;
opcode[23:0] <= {17'b0,collated_instr[29:23]};
imm_value0 <= {16{1'bx}};
imm_value1 <= collate_done ? collated_instr[63:32] : {32{1'bx}};
s1_field <= {`VD,1'b0,collated_instr[7:0]}; //SSRC8
s2_field <= {`VD,1'b0,collated_instr[15:8]}; //SSRC8
s3_field <= {`IN,{9{1'bx}}};
s4_field <= {`IN,{9{1'bx}}};
dest1_field <= {`VD,2'b0,collated_instr[22:16]}; //SDST7
dest2_field <= {`IN,{9{1'bx}}};
end
//Vector formats
//VOPC
32'b0111_110?_????_????_????_????_????_????:
begin
collate_required <= 1'b0;
fu <= 2'b01;
opcode[31:24] <= 8'd1;
opcode[23:0] <= {16'b0,collated_instr[24:17]};
imm_value0 <= {16{1'bx}};
imm_value1 <= collate_done ? collated_instr[63:32] : {32{1'bx}};
s1_field <= {`VD,collated_instr[8:0]}; //SRC9
s2_field <= {`VD,1'b1,collated_instr[16:9]}; //VSRC8
s3_field <= {`IN,{9{1'bx}}};
s4_field <= {`IN,{9{1'bx}}};
dest1_field <= {`IN,{9{1'bx}}};
dest2_field <= {`IN,{9{1'bx}}};
end
//VOP1
32'b0111_111?_????_????_????_????_????_????:
begin
collate_required <= 1'b0;
fu <= 2'b01;
opcode[31:24] <= 8'd2;
opcode[23:0] <= {16'b0,collated_instr[16:9]};
imm_value0 <= {16{1'bx}};
imm_value1 <= collate_done ? collated_instr[63:32] : {32{1'bx}};
s1_field <= {`VD,collated_instr[8:0]}; //SRC9
s2_field <= {`IN,{9{1'bx}}};
s3_field <= {`IN,{9{1'bx}}};
s4_field <= {`IN,{9{1'bx}}};
dest1_field <= {`VD,1'b1,collated_instr[24:17]}; //VDST8
dest2_field <= {`IN,{9{1'bx}}};
end
//VOP2
32'b0???_????_????_????_????_????_????_????:
begin
collate_required <= 1'b0;
fu <= 2'b01;
opcode[31:24] <= 8'd4;
opcode[23:0] <= {18'b0,collated_instr[30:25]};
imm_value0 <= {16{1'bx}};
imm_value1 <= collate_done ? collated_instr[63:32] : {32{1'bx}};
s1_field <= {`VD,collated_instr[8:0]}; //SRC9
s2_field <= {`VD,1'b1,collated_instr[16:9]}; //VSRC8
s3_field <= {`IN,{9{1'bx}}};
s4_field <= {`IN,{9{1'bx}}};
dest1_field <= {`VD,1'b1,collated_instr[24:17]}; //VDST8
dest2_field <= {`IN,{9{1'bx}}};
end
//VOP3a and VOP3b
32'b1101_00??_????_????_????_????_????_????:
begin
casex(collate_done)
//Only first word available
1'b0:
begin
collate_required <= 1'b1;
fu <= 2'b0; //Unused fu
opcode[31:24] <= {8{1'bx}};
opcode[23:0] <= {24{1'bx}};
imm_value0 <= {16{1'bx}};
imm_value1 <= {32{1'bx}};
s1_field <= {`IN,{9{1'bx}}};
s2_field <= {`IN,{9{1'bx}}};
s3_field <= {`IN,{9{1'bx}}};
s4_field <= {`IN,{9{1'bx}}};
dest1_field <= {`IN,{9{1'bx}}};
dest2_field <= {`IN,{9{1'bx}}};
end
//Both words are available
1'b1:
begin
//VOP3b
if((collated_instr[25:17] >= 9'h125) && (collated_instr[25:17] <= 9'h12a))
begin
collate_required <= 1'b0;
fu <= 2'b01;
opcode[31:24] <= 8'd8;
opcode[23:0] <= {collated_instr[63:59],10'b0,collated_instr[25:17]};
imm_value0 <= {16{1'bx}};
imm_value1 <= {32{1'bx}};
s1_field <= {`VD,collated_instr[40:32]}; //SRC9
s2_field <= {`VD,collated_instr[49:41]}; //SRC9
s3_field <= {`VD,collated_instr[58:50]}; //SRC9
s4_field <= {`IN,{9{1'bx}}};
dest1_field <= {`VD,1'b1,collated_instr[7:0]}; //VDST8
dest2_field <= {`VD,2'b0,collated_instr[14:8]}; //SDST7
end
//VOP3a
else
begin
collate_required <= 1'b0;
fu <= 2'b01;
opcode[31:24] <= 8'd16;
opcode[23:0] <= {collated_instr[63:59],collated_instr[11:8],6'b0,collated_instr[25:17]};
imm_value0 <= {16{1'bx}};
imm_value1 <= {32{1'bx}};
s1_field <= {`VD,collated_instr[40:32]}; //SRC9
s2_field <= {`VD,collated_instr[49:41]}; //SRC9
s3_field <= {`VD,collated_instr[58:50]}; //SRC9
s4_field <= {`IN,{9{1'bx}}};
dest1_field <= {`VD,1'b1,collated_instr[7:0]}; //VDST8
dest2_field <= {`IN,{9{1'bx}}};
end
end
//Error Condition
default:
begin
collate_required <= 1'bx;
fu <= {2{1'bx}};
opcode[31:24] <= {8{1'bx}};
opcode[23:0] <= {24{1'bx}};
imm_value0 <= {16{1'bx}};
imm_value1 <= {32{1'bx}};
s1_field <= {10{1'bx}};
s2_field <= {10{1'bx}};
s3_field <= {10{1'bx}};
s4_field <= {10{1'bx}};
dest1_field <= {10{1'bx}};
dest2_field <= {10{1'bx}};
end
endcase
end
//SMRD
32'b1100_0???_????_????_????_????_????_????:
begin
collate_required <= 1'b0;
fu <= 2'b11;
opcode[31:24] <= 8'd1;
opcode[23:0] <= {collated_instr[8],18'b0,collated_instr[26:22]};
imm_value0 <= collated_instr[8] ? {8'b0,collated_instr[7:0]} : {16{1'bx}}; //OFFSET8 if IMM=1
imm_value1 <= collate_done ? collated_instr[63:32] : {32{1'bx}};
s1_field <= collated_instr[8] ? {`IN,{9{1'bx}}} : {`VD,1'b0,collated_instr[7:0]}; //OFFSET8 if IMM=0
s2_field <= {`VD,2'b0,collated_instr[14:9],1'b0}; //SBASE6
s3_field <= {`IN,{9{1'bx}}};
s4_field <= {`IN,{9{1'bx}}};
dest1_field <= {`VD,2'b0,collated_instr[21:15]}; //SDST7
dest2_field <= {`IN,{9{1'bx}}};
end
//LDS/GDS
32'b1101_10??_????_????_????_????_????_????:
begin
casex(collate_done)
//Only first word available
1'b0:
begin
collate_required <= 1'b1;
fu <= 2'b0; //Unused fu
opcode[31:24] <= {8{1'bx}};
opcode[23:0] <= {24{1'bx}};
imm_value0 <= {16{1'bx}};
imm_value1 <= {32{1'bx}};
s1_field <= {`IN,{9{1'bx}}};
s2_field <= {`IN,{9{1'bx}}};
s3_field <= {`IN,{9{1'bx}}};
s4_field <= {`IN,{9{1'bx}}};
dest1_field <= {`IN,{9{1'bx}}};
dest2_field <= {`IN,{9{1'bx}}};
end
//Both words are available
1'b1:
begin
collate_required <= 1'b0;
fu <= 2'b11;
opcode[31:24] <= 8'd2;
opcode[23:0] <= {collated_instr[17],15'b0,collated_instr[25:18]};
imm_value0 <= collated_instr[7:0];
imm_value1 <= collated_instr[15:8];
s1_field <= {`VD,1'b1,collated_instr[39:32]}; //ADDR8 (only VGPR)
s2_field <= {`VD,1'b1,collated_instr[47:40]}; //DATA0 (only VGPR)
s3_field <= {`VD,1'b1,collated_instr[55:48]}; //DATA1 (only VGPR)
s4_field <= {`IN,{9{1'bx}}};
dest1_field <= {`VD,1'b1,collated_instr[63:56]}; //VDST8
dest2_field <= {`IN,{9{1'bx}}};
end
//Error Condition
default:
begin
collate_required <= 1'bx;
fu <= {2{1'bx}};
opcode[31:24] <= {8{1'bx}};
opcode[23:0] <= {24{1'bx}};
imm_value0 <= {16{1'bx}};
imm_value1 <= {32{1'bx}};
s1_field <= {10{1'bx}};
s2_field <= {10{1'bx}};
s3_field <= {10{1'bx}};
s4_field <= {10{1'bx}};
dest1_field <= {10{1'bx}};
dest2_field <= {10{1'bx}};
end
endcase
end
//MTBUF
32'b1110_10??_????_????_????_????_????_????:
begin
casex(collate_done)
//Only first word available
1'b0:
begin
collate_required <= 1'b1;
fu <= 2'b0; //Unused fu
opcode[31:24] <= {8{1'bx}};
opcode[23:0] <= {24{1'bx}};
imm_value0 <= {16{1'bx}};
imm_value1 <= {32{1'bx}};
s1_field <= {`IN,{9{1'bx}}};
s2_field <= {`IN,{9{1'bx}}};
s3_field <= {`IN,{9{1'bx}}};
s4_field <= {`IN,{9{1'bx}}};
dest1_field <= {`IN,{9{1'bx}}};
dest2_field <= {`IN,{9{1'bx}}};
end
//Both words are available
1'b1:
begin
collate_required <= 1'b0;
fu <= 2'b11;
opcode[31:24] <= 8'd4;
opcode[23:0] <= {collated_instr[55:54],collated_instr[25:19],collated_instr[15:12],8'b0,collated_instr[18:16]};
imm_value0 <= {4'd0,collated_instr[11:0]}; //The ISA does not suggest this offset to be optional.
imm_value1 <= {24'd0,collated_instr[63:56]};
s1_field <= {`VD,1'b0,collated_instr[63:56]}; //SOFFSET8
s2_field <= {`VD,1'b1,collated_instr[47:40]}; //VDATA8 if store
s3_field <= {`VD,1'b1,collated_instr[39:32]}; //VADDR8
s4_field <= {`VD,2'b0,collated_instr[52:48],2'b0}; //SRSRC5
dest1_field <= {`VD,1'b1,collated_instr[47:40]}; //VDATA8 if load
dest2_field <= {`IN,{9{1'bx}}};
end
//Error Condition
default:
begin
collate_required <= 1'bx;
fu <= {2{1'bx}};
opcode[31:24] <= {8{1'bx}};
opcode[23:0] <= {24{1'bx}};
imm_value0 <= {16{1'bx}};
imm_value1 <= {32{1'bx}};
s1_field <= {10{1'bx}};
s2_field <= {10{1'bx}};
s3_field <= {10{1'bx}};
s4_field <= {10{1'bx}};
dest1_field <= {10{1'bx}};
dest2_field <= {10{1'bx}};
end
endcase
end
//Error condition
default:
begin
collate_required <= 1'bx;
fu <= {2{1'bx}};
opcode[31:24] <= {8{1'bx}};
opcode[23:0] <= {24{1'bx}};
imm_value0 <= {16{1'bx}};
imm_value1 <= {32{1'bx}};
s1_field <= {10{1'bx}};
s2_field <= {10{1'bx}};
s3_field <= {10{1'bx}};
s4_field <= {10{1'bx}};
dest1_field <= {10{1'bx}};
dest2_field <= {10{1'bx}};
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31AI_1_V
`define SKY130_FD_SC_LP__O31AI_1_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o31ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31ai_1 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31AI_1_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2.0
// \ \ Application : MIG
// / / Filename : mig_7series_0_mig.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:36:27 $
// \ \ / \ Date Created : Fri Jan 14 2011
// \___\/\___\
//
// Device : 7 Series
// Design Name : QDRII+ SDRAM
// Purpose :
// Top-level module. This module can be instantiated in the
// system and interconnect as shown in user design wrapper file (user top module).
// In addition to the memory controller, the module instantiates:
// 1. Clock generation/distribution, reset logic
// 2. IDELAY control block
// 3. Debug logic
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_0_mig #
(
parameter MEM_TYPE = "QDR2PLUS",
// # of CK/CK# outputs to memory.
parameter DATA_WIDTH = 36,
// # of DQ (data)
parameter BW_WIDTH = 4,
// # of byte writes (data_width/9)
parameter ADDR_WIDTH = 19,
// Address Width
parameter NUM_DEVICES = 1,
// # of memory components connected
parameter MEM_RD_LATENCY = 2.5,
// Value of Memory part read latency
parameter CPT_CLK_CQ_ONLY = "TRUE",
// whether CQ and its inverse are used for the data capture
parameter INTER_BANK_SKEW = 0,
// Clock skew between two adjacent banks
parameter PHY_CONTROL_MASTER_BANK = 1,
// The bank index where master PHY_CONTROL resides,
// equal to the PLL residing bank
//***************************************************************************
// The following parameters are mode register settings
//***************************************************************************
parameter BURST_LEN = 4,
// Burst Length of the design (4 or 2).
parameter FIXED_LATENCY_MODE = 0,
// Enable Fixed Latency
parameter PHY_LATENCY = 0,
// Value for Fixed Latency Mode
// Expected Latency
//***************************************************************************
// The following parameters are multiplier and divisor factors for MMCM.
// Based on the selected design frequency these parameters vary.
//***************************************************************************
parameter CLKIN_PERIOD = 5000,
// Input Clock Period
parameter CLKFBOUT_MULT = 4,
// write PLL VCO multiplier
parameter DIVCLK_DIVIDE = 1,
// write PLL VCO divisor
parameter CLKOUT0_DIVIDE = 2,
// VCO output divisor for PLL output clock (CLKOUT0)
parameter CLKOUT1_DIVIDE = 2,
// VCO output divisor for PLL output clock (CLKOUT1)
parameter CLKOUT2_DIVIDE = 32,
// VCO output divisor for PLL output clock (CLKOUT2)
parameter CLKOUT3_DIVIDE = 4,
// VCO output divisor for PLL output clock (CLKOUT3)
//***************************************************************************
// Simulation parameters
//***************************************************************************
parameter SIM_BYPASS_INIT_CAL = "FAST",
// # = "OFF" - Complete memory init &
// calibration sequence
// # = "FAST" - Skip memory init & use
// abbreviated calib sequence
parameter SIMULATION = "TRUE",
// Should be TRUE during design simulations and
// FALSE during implementations
//***************************************************************************
// The following parameters varies based on the pin out entered in MIG GUI.
// Do not change any of these parameters directly by editing the RTL.
// Any changes required should be done through GUI and the design regenerated.
//***************************************************************************
parameter BYTE_LANES_B0 = 4'b1111,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B1 = 4'b1111,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B2 = 4'b1100,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B3 = 4'b0000,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B4 = 4'b0000,
// Byte lanes used in an IO column.
parameter DATA_CTL_B0 = 4'b1111,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B1 = 4'b1111,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B2 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B3 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B4 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
// this parameter specifies the location of the capture clock with respect
// to read data.
// Each byte refers to the information needed for data capture in the corresponding byte lane
// Lower order nibble - is either 4'h1 or 4'h2. This refers to the capture clock in T1 or T2 byte lane
// Higher order nibble - 4'h0 refers to clock present in the bank below the read data,
// 4'h1 refers to clock present in the same bank as the read data,
// 4'h2 refers to clock present in the bank above the read data.
parameter CPT_CLK_SEL_B0 = 32'h11_11_11_11,
parameter CPT_CLK_SEL_B1 = 32'h00_00_00_00,
parameter CPT_CLK_SEL_B2 = 32'h00_00_00_00,
parameter PHY_0_BITLANES = 48'hFF8_FF1_D3F_EFC,
// The bits used inside the Bank0 out of 48 pins.
parameter PHY_1_BITLANES = 48'h3FE_FFE_CFF_FFC,
// The bits used inside the Bank1 out of 48 pins.
parameter PHY_2_BITLANES = 48'hEFE_FFD_000_000,
// The bits used inside the Bank2 out of 48 pins.
parameter PHY_3_BITLANES = 48'h000_000_000_000,
// The bits used inside the Bank3 out of 48 pins.
parameter PHY_4_BITLANES = 48'h000_000_000_000,
// The bits used inside the Bank4 out of 48 pins.
// Differentiates the INPUT and OUTPUT bytelates (1-input, 0-output)
parameter BYTE_GROUP_TYPE_B0 = 4'b1111,
parameter BYTE_GROUP_TYPE_B1 = 4'b0000,
parameter BYTE_GROUP_TYPE_B2 = 4'b0000,
parameter BYTE_GROUP_TYPE_B3 = 4'b0000,
parameter BYTE_GROUP_TYPE_B4 = 4'b0000,
// mapping for K/K# clocks. This parameter needs to have an 8-bit value per component
// since the phy drives a K/K# clock pair to each memory it interfaces to. A 3 component
// interface is supported for now. This parameter needs to be used in conjunction with
// NUM_DEVICES parameter which provides information on the number. of components being
// interfaced to.
// the 8 bit for each component is defined as follows:
// [7:4] - bank number ; [3:0] - byte lane number
parameter K_MAP = 48'h00_00_00_00_00_13,
// mapping for CQ/CQ# clocks. This parameter needs to have an 4-bit value per component
// since the phy drives a CQ/CQ# clock pair to each memory it interfaces to. A 3 component
// interface is supported for now. This parameter needs to be used in conjunction with
// NUM_DEVICES parameter which provides information on the number. of components being
// interfaced to.
// the 4 bit for each component is defined as follows:
// [3:0] - bank number
parameter CQ_MAP = 48'h00_00_00_00_00_01,
//**********************************************************************************************
// Each of the following parameter contains the byte_lane and bit position information for
// the address/control, data write and data read signals. Each bit has 12 bits and the details are
// [3:0] - Bit position within a byte lane .
// [7:4] - Byte lane position within a bank. [5:4] have the byte lane position and others reserved.
// [11:8] - Bank position. [10:8] have the bank position. [11] tied to zero .
//**********************************************************************************************
// Mapping for address and control signals.
parameter RD_MAP = 12'h220, // Mapping for read enable signal
parameter WR_MAP = 12'h222, // Mapping for write enable signal
// Mapping for address signals. Supports upto 22 bits of address bits (22*12)
parameter ADD_MAP = 264'h000_000_000_223_236_22B_23B_235_234_225_229_224_232_228_23A_231_237_239_233_227_22A_226,
// Mapping for the byte lanes used for address/control signals. Supports a maximum of 3 banks.
parameter ADDR_CTL_MAP = 32'h00_00_23_22,
// Mapping for data WRITE signals
// Mapping for data write bytes (9*12)
parameter D0_MAP = 108'h137_134_136_135_132_133_131_138_139, //byte 0
parameter D1_MAP = 108'h121_124_125_122_126_127_12A_123_12B, //byte 1
parameter D2_MAP = 108'h102_103_108_104_106_105_107_10A_10B, //byte 2
parameter D3_MAP = 108'h116_117_115_11A_114_113_111_112_110, //byte 3
parameter D4_MAP = 108'h000_000_000_000_000_000_000_000_000, //byte 4
parameter D5_MAP = 108'h000_000_000_000_000_000_000_000_000, //byte 5
parameter D6_MAP = 108'h000_000_000_000_000_000_000_000_000, //byte 6
parameter D7_MAP = 108'h000_000_000_000_000_000_000_000_000, //byte 7
// Mapping for byte write signals (8*12)
parameter BW_MAP = 84'h000_000_000_11B_109_128_129,
// Mapping for data READ signals
// Mapping for data read bytes (9*12)
parameter Q0_MAP = 108'h033_039_034_036_035_03A_03B_037_038, //byte 0
parameter Q1_MAP = 108'h029_020_028_026_027_02A_02B_024_025, //byte 1
parameter Q2_MAP = 108'h015_014_01A_01B_011_010_013_012_018, //byte 2
parameter Q3_MAP = 108'h00B_003_007_002_005_004_009_006_00A, //byte 3
parameter Q4_MAP = 108'h000_000_000_000_000_000_000_000_000, //byte 4
parameter Q5_MAP = 108'h000_000_000_000_000_000_000_000_000, //byte 5
parameter Q6_MAP = 108'h000_000_000_000_000_000_000_000_000, //byte 6
parameter Q7_MAP = 108'h000_000_000_000_000_000_000_000_000, //byte 7
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter IODELAY_HP_MODE = "ON",
// to phy_top
parameter IBUF_LPWR_MODE = "OFF",
// to phy_top
parameter TCQ = 100,
parameter IODELAY_GRP = "MIG_7SERIES_0_IODELAY_MIG",
// It is associated to a set of IODELAYs with
// an IDELAYCTRL that have same IODELAY CONTROLLER
// clock frequency.
parameter SYSCLK_TYPE = "SINGLE_ENDED",
// System clock type DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER
parameter REFCLK_TYPE = "USE_SYSTEM_CLOCK",
// Reference clock type DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER, USE_SYSTEM_CLOCK
parameter SYS_RST_PORT = "FALSE",
// "TRUE" - if pin is selected for sys_rst
// and IBUF will be instantiated.
// "FALSE" - if pin is not selected for sys_rst
// Number of taps in target IDELAY
parameter integer DEVICE_TAPS = 32,
//***************************************************************************
// Referece clock frequency parameters
//***************************************************************************
parameter REFCLK_FREQ = 200.0,
// IODELAYCTRL reference clock frequency
parameter DIFF_TERM_REFCLK = "TRUE",
// Differential Termination for idelay
// reference clock input pins
//***************************************************************************
// System clock frequency parameters
//***************************************************************************
parameter CLK_PERIOD = 2500,
// memory tCK paramter.
// # = Clock Period in pS.
parameter nCK_PER_CLK = 2,
// # of memory CKs per fabric CLK
parameter DIFF_TERM_SYSCLK = "FALSE",
// Differential Termination for System
// clock input pins
//***************************************************************************
// Wait period for the read strobe (CQ) to become stable
//***************************************************************************
parameter CLK_STABLE = (20*1000*1000/(CLK_PERIOD*2)),
// Cycles till CQ/CQ# is stable
//***************************************************************************
// Debug parameter
//***************************************************************************
parameter DEBUG_PORT = "OFF",
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
parameter RST_ACT_LOW = 1
// =1 for active low reset,
// =0 for active high.
)
(
// Single-ended system clock
input sys_clk_i,
input [NUM_DEVICES-1:0] qdriip_cq_p, //Memory Interface
input [NUM_DEVICES-1:0] qdriip_cq_n,
input [DATA_WIDTH-1:0] qdriip_q,
output wire [NUM_DEVICES-1:0] qdriip_k_p,
output wire [NUM_DEVICES-1:0] qdriip_k_n,
output wire [DATA_WIDTH-1:0] qdriip_d,
output wire [ADDR_WIDTH-1:0] qdriip_sa,
output wire qdriip_w_n,
output wire qdriip_r_n,
output wire [BW_WIDTH-1:0] qdriip_bw_n,
output wire qdriip_dll_off_n,
// User Interface signals of Channel-0
input app_wr_cmd0,
input [ADDR_WIDTH-1:0] app_wr_addr0,
input [(DATA_WIDTH*BURST_LEN)-1:0] app_wr_data0,
input [(BW_WIDTH*BURST_LEN)-1:0] app_wr_bw_n0,
input app_rd_cmd0,
input [ADDR_WIDTH-1:0] app_rd_addr0,
output wire app_rd_valid0,
output wire [(DATA_WIDTH*BURST_LEN)-1:0] app_rd_data0,
// User Interface signals of Channel-1. It is useful only for BL2 designs.
// All inputs of Channel-1 can be grounded for BL4 designs.
input app_wr_cmd1,
input [ADDR_WIDTH-1:0] app_wr_addr1,
input [(DATA_WIDTH*2)-1:0] app_wr_data1,
input [(BW_WIDTH*2)-1:0] app_wr_bw_n1,
input app_rd_cmd1,
input [ADDR_WIDTH-1:0] app_rd_addr1,
output wire app_rd_valid1,
output wire [(DATA_WIDTH*2)-1:0] app_rd_data1,
output wire clk,
output wire rst_clk,
output init_calib_complete,
// System reset - Default polarity of sys_rst pin is Active Low.
// System reset polarity will change based on the option
// selected in GUI.
input sys_rst
);
// clogb2 function - ceiling of log base 2
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction
localparam integer N_DATA_LANES = DATA_WIDTH / 9;
// Number of bits needed to represent DEVICE_TAPS
localparam integer TAP_BITS = clogb2(DEVICE_TAPS - 1);
// Number of bits to represent number of cq/cq#'s
localparam integer CQ_BITS = clogb2(DATA_WIDTH/9 - 1);
// Number of bits needed to represent number of q's
localparam integer Q_BITS = clogb2(DATA_WIDTH - 1);
// Wire declarations
wire freq_refclk ;
wire mem_refclk ;
wire pll_locked ;
wire sync_pulse;
wire rst_wr_clk;
wire ref_dll_lock;
wire rst_phaser_ref;
wire cmp_err; // Reserve for ERROR from test bench
wire [CQ_BITS-1:0] dbg_byte_sel;
wire [Q_BITS-1:0] dbg_bit_sel;
wire dbg_pi_f_inc;
wire dbg_pi_f_dec;
wire dbg_po_f_inc;
wire dbg_po_f_dec;
wire dbg_idel_up_all;
wire dbg_idel_down_all;
wire dbg_idel_up;
wire dbg_idel_down;
wire [(TAP_BITS*DATA_WIDTH)-1:0] dbg_idel_tap_cnt;
wire [TAP_BITS-1:0] dbg_idel_tap_cnt_sel;
wire [2:0] dbg_select_rdata;
//wire [5:0] dbg_pi_tap_cnt;
//wire [5:0] dbg_po_tap_cnt;
//wire [(TAP_BITS*DATA_WIDTH)-1:0] dbg_cpt_first_edge_cnt;
//wire [(TAP_BITS*DATA_WIDTH)-1:0] dbg_cpt_second_edge_cnt;
//ChipScope Readpath Debug Signals
wire [1:0] dbg_phy_wr_cmd_n; //cs debug - wr command
wire [2:0] dbg_byte_sel_cnt;
wire [(ADDR_WIDTH*4)-1:0] dbg_phy_addr; //cs debug - address
wire [1:0] dbg_phy_rd_cmd_n; //cs debug - rd command
wire [(DATA_WIDTH*4)-1:0] dbg_phy_wr_data; //cs debug - wr data
wire dbg_phy_init_wr_only;
wire dbg_phy_init_rd_only;
wire [8:0] dbg_po_counter_read_val;
wire vio_sel_rise_chk;
wire [(TAP_BITS*N_DATA_LANES)-1:0] dbg_cq_tapcnt; // tap count for each cq
wire [(TAP_BITS*N_DATA_LANES)-1:0] dbg_cqn_tapcnt; // tap count for each cq#
wire [CQ_BITS-1:0] dbg_cq_num; // current cq/cq# being calibrated
wire [4:0] dbg_valid_lat; // latency of the system
wire [N_DATA_LANES-1:0] dbg_inc_latency; // increase latency for dcb
wire [(4*DATA_WIDTH)-1:0] dbg_dcb_din; // dcb data in
wire [(4*DATA_WIDTH)-1:0] dbg_dcb_dout; // dcb data out
wire [N_DATA_LANES-1:0] dbg_error_max_latency; // stage 2 cal max latency error
wire dbg_error_adj_latency; // stage 2 cal latency adjustment error
wire [DATA_WIDTH-1:0] dbg_align_rd0;
wire [DATA_WIDTH-1:0] dbg_align_rd1;
wire [DATA_WIDTH-1:0] dbg_align_fd0;
wire [DATA_WIDTH-1:0] dbg_align_fd1;
wire [8:0] dbg_align_rd0_r;
wire [8:0] dbg_align_rd1_r;
wire [8:0] dbg_align_fd0_r;
wire [8:0] dbg_align_fd1_r;
reg rd_valid0_r;
reg rd_valid1_r;
wire [7:0] dbg_phy_status;
wire dbg_SM_No_Pause;
wire dbg_SM_en;
//wire [(TAP_BITS*DATA_WIDTH)-1:0] dbg_q_tapcnt; // tap count for each q
//wire [Q_BITS-1:0] dbg_q_bit; // current q being calibrated
wire [(DATA_WIDTH*2)-1:0] mux_wr_data0;
wire [(DATA_WIDTH*2)-1:0] mux_wr_data1;
wire [(BW_WIDTH*2)-1:0] mux_wr_bw_n0;
wire [(BW_WIDTH*2)-1:0] mux_wr_bw_n1;
wire [(DATA_WIDTH*2)-1:0] rd_data0;
wire [(DATA_WIDTH*2)-1:0] rd_data1;
wire sys_clk_p;
wire sys_clk_n;
wire mmcm_clk;
wire clk_ref_p;
wire clk_ref_n;
wire clk_ref_i;
wire clk_ref_in;
wire iodelay_ctrl_rdy;
wire clk_ref;
wire sys_rst_o;
wire [5:0] dbg_pi_counter_read_val;
wire [255:0] dbg_rd_stage1_cal;
wire [127:0] dbg_stage2_cal;
wire [255:0] dbg_wr_init;
//***************************************************************************
assign sys_clk_p = 1'b0;
assign sys_clk_n = 1'b0;
assign clk_ref_i = 1'b0;
generate
if (BURST_LEN == 4) begin: mux_data_bl4
assign mux_wr_data0 = app_wr_data0[DATA_WIDTH*4-1:DATA_WIDTH*2];
assign mux_wr_bw_n0 = app_wr_bw_n0[BW_WIDTH*4-1:BW_WIDTH*2];
end else begin: mux_data_bl2
assign mux_wr_data0 = app_wr_data0;
assign mux_wr_bw_n0 = app_wr_bw_n0;
end
endgenerate
assign mux_wr_data1 = (BURST_LEN == 4) ? app_wr_data0[DATA_WIDTH*2-1:0] : app_wr_data1;
assign mux_wr_bw_n1 = (BURST_LEN == 4) ? app_wr_bw_n0[BW_WIDTH*2-1:0] : app_wr_bw_n1;
assign app_rd_data0 = (BURST_LEN == 4) ? {rd_data0, rd_data1} : rd_data0;
assign app_rd_data1 = rd_data1;
generate
if (REFCLK_TYPE == "USE_SYSTEM_CLOCK")
assign clk_ref_in = mmcm_clk;
else
assign clk_ref_in = clk_ref_i;
endgenerate
mig_7series_v2_0_iodelay_ctrl #
(
.TCQ (TCQ),
.IODELAY_GRP (IODELAY_GRP),
.REFCLK_TYPE (REFCLK_TYPE),
.SYSCLK_TYPE (SYSCLK_TYPE),
.SYS_RST_PORT (SYS_RST_PORT),
.RST_ACT_LOW (RST_ACT_LOW),
.DIFF_TERM_REFCLK (DIFF_TERM_REFCLK)
)
u_iodelay_ctrl
(
// Outputs
.iodelay_ctrl_rdy (iodelay_ctrl_rdy),
.sys_rst_o (sys_rst_o),
// Inputs
.clk_ref_p (clk_ref_p),
.clk_ref_n (clk_ref_n),
.clk_ref_i (clk_ref_in),
.clk_ref (clk_ref),
.sys_rst (sys_rst)
);
mig_7series_v2_0_clk_ibuf#
(
.SYSCLK_TYPE (SYSCLK_TYPE),
.DIFF_TERM_SYSCLK (DIFF_TERM_SYSCLK)
)
u_clk_ibuf
(
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
.sys_clk_i (sys_clk_i),
.mmcm_clk (mmcm_clk)
);
mig_7series_v2_0_infrastructure #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLKIN_PERIOD (CLKIN_PERIOD),
.SYSCLK_TYPE (SYSCLK_TYPE),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKOUT0_DIVIDE (CLKOUT0_DIVIDE),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
.RST_ACT_LOW (RST_ACT_LOW)
)
u_infrastructure
(
// Outputs
.rstdiv0 (rst_wr_clk),
.clk (clk),
.mem_refclk (mem_refclk),
.freq_refclk (freq_refclk),
.sync_pulse (sync_pulse),
.auxout_clk (),
.ui_addn_clk_0 (),
.ui_addn_clk_1 (),
.ui_addn_clk_2 (),
.ui_addn_clk_3 (),
.ui_addn_clk_4 (),
.pll_locked (pll_locked),
.mmcm_locked (),
.rst_phaser_ref (rst_phaser_ref),
// Inputs
.mmcm_clk (mmcm_clk),
.sys_rst (sys_rst_o),
.iodelay_ctrl_rdy (iodelay_ctrl_rdy),
.ref_dll_lock (ref_dll_lock)
);
mig_7series_v2_0_qdr_phy_top #
(
.MEM_TYPE (MEM_TYPE), //Memory Type (QDR2PLUS, QDR2)
.CLK_PERIOD (CLK_PERIOD),
.nCK_PER_CLK (nCK_PER_CLK),
.REFCLK_FREQ (REFCLK_FREQ),
.IODELAY_GRP (IODELAY_GRP),
.RST_ACT_LOW (RST_ACT_LOW),
.CLK_STABLE (CLK_STABLE ), //Cycles till CQ/CQ# is stable
.ADDR_WIDTH (ADDR_WIDTH ), //Adress Width
.DATA_WIDTH (DATA_WIDTH ), //Data Width
.BW_WIDTH (BW_WIDTH), //Byte Write Width
.BURST_LEN (BURST_LEN), //Burst Length
.NUM_DEVICES (NUM_DEVICES), //Memory Devices
.N_DATA_LANES (N_DATA_LANES),
.FIXED_LATENCY_MODE (FIXED_LATENCY_MODE), //Fixed Latency for data reads
.PHY_LATENCY (PHY_LATENCY), //Value for Fixed Latency Mode
.MEM_RD_LATENCY (MEM_RD_LATENCY), //Value of Memory part read latency
.CPT_CLK_CQ_ONLY (CPT_CLK_CQ_ONLY), //Only CQ is used for data capture and no CQ#
.SIMULATION (SIMULATION), //TRUE during design simulation
.MASTER_PHY_CTL (PHY_CONTROL_MASTER_BANK),
.PLL_LOC (PHY_CONTROL_MASTER_BANK),
.INTER_BANK_SKEW (INTER_BANK_SKEW),
.CQ_BITS (CQ_BITS), //clogb2(NUM_DEVICES - 1)
.Q_BITS (Q_BITS), //clogb2(DATA_WIDTH - 1)
.DEVICE_TAPS (DEVICE_TAPS), // Number of taps in the IDELAY chain
.TAP_BITS (TAP_BITS), // clogb2(DEVICE_TAPS - 1)
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE ), //Input buffer low power mode
.IODELAY_HP_MODE (IODELAY_HP_MODE), //IODELAY High Performance Mode
.DATA_CTL_B0 (DATA_CTL_B0), //Data write/read bits in all banks
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.ADDR_CTL_MAP (ADDR_CTL_MAP),
.BYTE_LANES_B0 (BYTE_LANES_B0), //Byte lanes used for the complete design
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.BYTE_GROUP_TYPE_B0 (BYTE_GROUP_TYPE_B0), //Differentiates data write and read byte lanes
.BYTE_GROUP_TYPE_B1 (BYTE_GROUP_TYPE_B1),
.BYTE_GROUP_TYPE_B2 (BYTE_GROUP_TYPE_B2),
.BYTE_GROUP_TYPE_B3 (BYTE_GROUP_TYPE_B3),
.BYTE_GROUP_TYPE_B4 (BYTE_GROUP_TYPE_B4),
.CPT_CLK_SEL_B0 (CPT_CLK_SEL_B0), //Capture clock placement parameters
.CPT_CLK_SEL_B1 (CPT_CLK_SEL_B1),
.CPT_CLK_SEL_B2 (CPT_CLK_SEL_B2),
.BIT_LANES_B0 (PHY_0_BITLANES), //Bits used for the complete design
.BIT_LANES_B1 (PHY_1_BITLANES),
.BIT_LANES_B2 (PHY_2_BITLANES),
.BIT_LANES_B3 (PHY_3_BITLANES),
.BIT_LANES_B4 (PHY_4_BITLANES),
.ADD_MAP (ADD_MAP), // Address bits mapping
.RD_MAP (RD_MAP),
.WR_MAP (WR_MAP),
.D0_MAP (D0_MAP), // Data write bits mapping
.D1_MAP (D1_MAP),
.D2_MAP (D2_MAP),
.D3_MAP (D3_MAP),
.D4_MAP (D4_MAP),
.D5_MAP (D5_MAP),
.D6_MAP (D6_MAP),
.D7_MAP (D7_MAP),
.BW_MAP (BW_MAP),
.K_MAP (K_MAP),
.Q0_MAP (Q0_MAP), // Data read bits mapping
.Q1_MAP (Q1_MAP),
.Q2_MAP (Q2_MAP),
.Q3_MAP (Q3_MAP),
.Q4_MAP (Q4_MAP),
.Q5_MAP (Q5_MAP),
.Q6_MAP (Q6_MAP),
.Q7_MAP (Q7_MAP),
.CQ_MAP (CQ_MAP),
.DEBUG_PORT (DEBUG_PORT), // Debug using Chipscope controls
.TCQ (TCQ) //Register Delay
)
u_qdr_phy_top
(
// clocking and reset
.clk (clk), //Fabric logic clock
.rst_wr_clk (rst_wr_clk), // fabric reset based on PLL lock and system input reset.
.clk_ref (clk_ref), // Idelay_ctrl reference clock
.clk_mem (mem_refclk), // Memory clock to hard PHY
.freq_refclk (freq_refclk),
.sync_pulse (sync_pulse),
.pll_lock (pll_locked),
.rst_clk (rst_clk), //output generated based on read clocks being stable
.sys_rst (sys_rst_o), // input system reset
.ref_dll_lock (ref_dll_lock),
.rst_phaser_ref (rst_phaser_ref),
//PHY Write Path Interface
.wr_cmd0 (app_wr_cmd0), //wr command 0
.wr_cmd1 (app_wr_cmd1), //wr command 1
.wr_addr0 (app_wr_addr0), //wr address 0
.wr_addr1 (app_wr_addr1), //wr address 1
.rd_cmd0 (app_rd_cmd0), //rd command 0
.rd_cmd1 (app_rd_cmd1), //rd command 1
.rd_addr0 (app_rd_addr0), //rd address 0
.rd_addr1 (app_rd_addr1), //rd address 1
.wr_data0 (mux_wr_data0), //app write data 0
.wr_data1 (mux_wr_data1), //app write data 1
.wr_bw_n0 (mux_wr_bw_n0), //app byte writes 0
.wr_bw_n1 (mux_wr_bw_n1), //app byte writes 1
//PHY Read Path Interface
.init_calib_complete (init_calib_complete), //Calibration complete
.rd_valid0 (app_rd_valid0), //Read valid for rd_data0
.rd_valid1 (app_rd_valid1), //Read valid for rd_data1
.rd_data0 (rd_data0), //Read data 0
.rd_data1 (rd_data1), //Read data 1
//Memory Interface
.qdr_dll_off_n (qdriip_dll_off_n), //QDR - turn off dll in mem
.qdr_k_p (qdriip_k_p), //QDR clock K
.qdr_k_n (qdriip_k_n), //QDR clock K#
.qdr_sa (qdriip_sa), //QDR Memory Address
.qdr_w_n (qdriip_w_n), //QDR Write
.qdr_r_n (qdriip_r_n), //QDR Read
.qdr_bw_n (qdriip_bw_n), //QDR Byte Writes to Mem
.qdr_d (qdriip_d), //QDR Data to Memory
.qdr_q (qdriip_q), //QDR Data from Memory
.qdr_cq_p (qdriip_cq_p), //QDR echo clock CQ
.qdr_cq_n (qdriip_cq_n), //QDR echo clock CQ#
//Debug interface
.dbg_phy_status (dbg_phy_status),
//.dbg_SM_en (dbg_SM_en),
//.dbg_SM_No_Pause (dbg_SM_No_Pause),
.dbg_po_counter_read_val (dbg_po_counter_read_val),
.dbg_pi_counter_read_val (dbg_pi_counter_read_val),
.dbg_phy_init_wr_only (dbg_phy_init_wr_only),
.dbg_phy_init_rd_only (dbg_phy_init_rd_only),
.dbg_byte_sel (dbg_byte_sel),
.dbg_bit_sel (dbg_bit_sel),
.dbg_pi_f_inc (dbg_pi_f_inc),
.dbg_pi_f_dec (dbg_pi_f_dec),
.dbg_po_f_inc (dbg_po_f_inc),
.dbg_po_f_dec (dbg_po_f_dec),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up (dbg_idel_up),
.dbg_idel_down (dbg_idel_down),
.dbg_idel_tap_cnt (dbg_idel_tap_cnt),
.dbg_idel_tap_cnt_sel (dbg_idel_tap_cnt_sel),
.dbg_select_rdata (dbg_select_rdata),
.dbg_align_rd0_r (dbg_align_rd0_r),
.dbg_align_rd1_r (dbg_align_rd1_r),
.dbg_align_fd0_r (dbg_align_fd0_r),
.dbg_align_fd1_r (dbg_align_fd1_r),
.dbg_align_rd0 (dbg_align_rd0),
.dbg_align_rd1 (dbg_align_rd1),
.dbg_align_fd0 (dbg_align_fd0),
.dbg_align_fd1 (dbg_align_fd1),
.dbg_byte_sel_cnt (dbg_byte_sel_cnt),
.dbg_phy_wr_cmd_n (dbg_phy_wr_cmd_n),
.dbg_phy_addr (dbg_phy_addr),
.dbg_phy_rd_cmd_n (dbg_phy_rd_cmd_n),
.dbg_phy_wr_data (dbg_phy_wr_data),
.dbg_wr_init (dbg_wr_init),
.dbg_rd_stage1_cal (dbg_rd_stage1_cal),
.dbg_stage2_cal (dbg_stage2_cal),
.dbg_valid_lat (dbg_valid_lat),
.dbg_inc_latency (dbg_inc_latency),
.dbg_error_max_latency (dbg_error_max_latency),
.error_adj_latency (dbg_error_adj_latency)
);
//*********************************************************************
// Resetting all RTL debug inputs as the debug ports are not enabled
//*********************************************************************
assign dbg_phy_init_wr_only = 1'b0;
assign dbg_phy_init_rd_only = 1'b0;
assign dbg_byte_sel = 'b0;
assign dbg_bit_sel = 'b0;
assign dbg_pi_f_inc = 1'b0;
assign dbg_pi_f_dec = 1'b0;
assign dbg_po_f_inc = 1'b0;
assign dbg_po_f_dec = 1'b0;
assign dbg_idel_up_all = 1'b0;
assign dbg_idel_down_all = 1'b0;
assign dbg_idel_up = 1'b0;
assign dbg_idel_down = 1'b0;
assign dbg_SM_en = 1'b1;
assign dbg_SM_No_Pause = 1'b1;
endmodule
|
//==============================================================================
// Copyright (C) John-Philip Taylor
// [email protected]
//
// This file is part of a library
//
// This file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>
//==============================================================================
module UART_Sender #(
parameter N = 5,
parameter Full = 5'd29 // Clk / BAUD - 1
)(
input Clk,
input Reset,
input [7:0]Data,
input Send,
output reg Busy,
output reg Tx // Tx line on the board.
);
//------------------------------------------------------------------------------
reg tSend;
reg [ 7:0]Temp;
reg [N-1:0]Count;
reg [ 2:0]BitCount;
//------------------------------------------------------------------------------
reg [1:0]State;
localparam Idle = 2'b00;
localparam Sending = 2'b01;
localparam StopBit = 2'b11;
localparam Done = 2'b10;
//------------------------------------------------------------------------------
reg tReset;
always @(posedge Clk) begin
tReset <= Reset;
if(tReset) begin
Busy <= 1'b0;
Tx <= 1'b1;
tSend <= 0;
Count <= 0;
BitCount <= 0;
State <= Idle;
//------------------------------------------------------------------------------
end else begin
tSend <= Send;
if(~|Count) begin
case(State)
Idle: begin
if(tSend) begin
Count <= Full;
BitCount <= 3'd7;
{Temp, Tx} <= {Data, 1'b0};
Busy <= 1'b1;
State <= Sending;
end
end
//------------------------------------------------------------------------------
Sending: begin
Count <= Full;
{Temp[6:0], Tx} <= Temp;
if(~|BitCount) State <= StopBit;
BitCount <= BitCount - 1'b1;
end
//------------------------------------------------------------------------------
StopBit: begin
Tx <= 1'b1;
Count <= Full;
State <= Done;
end
//------------------------------------------------------------------------------
Done: begin
if(~tSend) begin
Busy <= 1'b0;
Count <= 0;
State <= Idle;
end
end
//------------------------------------------------------------------------------
default:;
endcase
end else begin
Count <= Count - 1'b1;
end
end
end
//------------------------------------------------------------------------------
endmodule |
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module SD_DAT (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
bidir_port,
readdata
)
;
inout bidir_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire bidir_port;
wire clk_en;
reg data_dir;
wire data_in;
reg data_out;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({1 {(address == 0)}} & data_in) |
({1 {(address == 1)}} & data_dir);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {{{32 - 1}{1'b0}},read_mux_out};
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign bidir_port = data_dir ? data_out : 1'bZ;
assign data_in = bidir_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_dir <= 0;
else if (chipselect && ~write_n && (address == 1))
data_dir <= writedata;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND3B_1_V
`define SKY130_FD_SC_MS__AND3B_1_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and3b_1 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and3b_1 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND3B_1_V
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: dma_engine_alignment.v
// Project: CPCI (PCI Control FPGA)
// Description: Re-alignment module to handle unaligned transfers
//
// Note: read and write are from the perspective of the driver.
// Read means retrieve a packet from the CNET and place in memory.
// Write means send a packet from memory to CNET.
//
// Change history: 12/08/07 - Split the alignment block from the main
// processing block to aid in readability
// and maintainability
//
// Issues to address:
//
///////////////////////////////////////////////////////////////////////////////
module dma_engine_alignment (
// PCI Signals
input [`PCI_DATA_WIDTH-1:0] pci_data, // Data being read from host
input dma_data_vld, // Indicates data should be captured
// from pci_data during a read or
// that a data transaction has
// occured during a write.
// CPCI register interface signals
input host_is_le, // The host is little endian
// CNET DMA interface signals
input [31:0] dma_data_frm_cnet, // DMA data to be transfered
output dma_rd_en, // Read a word from the buffer
input dma_empty, // Is the buffer empty?
// DMA engine signals
output [`PCI_DATA_WIDTH - 1 : 0] wr_buf_data, // Output of the write buffer
output [`PCI_DATA_WIDTH - 1 : 0] rd_buf_data, // Output of the read buffer
input xfer_is_rd, // Transfer direction
input last_word_pci, // Transfering last word on the PCI bus
input first_word_pci,// Transfering first word on the PCI bus
input last_word_from_cnet, // Transferring last word from CNET
input rd_full, // The read FIFO is full
input discard, // Discard a word from the read fifo
// (ignore it in processint
output reg wr_data_rdy, // Write data is being output in this cycle
output rd_data_rdy, // Read data is being output in this cycle
input [1:0] non_aligned_bytes, // Number of non-aligned bytes
output read_from_cnet,// Indicates read of word from CNET
input ld_xfer_cnt,
input [8:0] xfer_cnt_start, // Number of words to transfer
input [8:0] to_cnet_cnt_start, // Number of words to transfer
// Miscelaneous signals
input cnet_reprog, // Indicates that the CNET is
// currently being reprogrammed
input reset,
input clk
);
// ==================================================================
// Local
// ==================================================================
// Is there currently data being OP on dma_data_frm_cnet?
reg data_frm_cnet_ready;
// Byte swaped version of data from PCI bus
wire [`PCI_DATA_WIDTH-1:0] pci_data_swapped;
// Byte swapped version of data from cnet
wire [31:0] dma_data_frm_cnet_swapped;
// Instruct the read buffer to write a word
wire rdb_wr_en;
// Deal with non-aligned DMA transfers
reg [55:0] wr_realign_buf, rd_realign_buf;
reg wr_pci_done;
reg wr_dma_done;
reg rd_cnet_done;
reg rd_fifo_done;
// Input to the read and write FIFOs
reg [`PCI_DATA_WIDTH - 1 : 0] wr_buf_data_swapped;
reg [`PCI_DATA_WIDTH - 1 : 0] rd_buf_data_swapped;
// Word available in write/read buffers
reg rdb_data_avail;
// Transfer counters
reg [8:0] to_wr_fifo_cnt;
reg [8:0] to_rd_fifo_cnt;
// Last word being written into write or read FIFO
wire last_word_to_wr_fifo;
wire last_word_to_rd_fifo;
// ==================================================================
// Sample the write data for non-aligned transfers
// ==================================================================
assign pci_data_swapped = host_is_le ?
{pci_data[7:0], pci_data[15:8], pci_data[23:16], pci_data[31:24]} :
pci_data;
always @(posedge clk)
begin
if (reset || cnet_reprog)
begin
wr_data_rdy <= 1'b0;
wr_pci_done <= 1'b0;
wr_dma_done <= 1'b0;
end
else
begin
// Shift data in the realignment buffer when either:
// - we're doing a write over the PCI bus
// - the PCI transaction has finished and we've still got data
// to transfer over the DMA bus
if ((dma_data_vld && !xfer_is_rd) ||
(wr_pci_done && !wr_dma_done ))
wr_realign_buf <= {wr_realign_buf[31:0], pci_data_swapped};
// Record that there's data ready to push out of the module when:
// - a PCI write has occurred and the transfer is aligned
// - a PCI write has occurred and there's already data in the buffer
// - PCI transaction is done, DMA transfer is not done and we're not
// currently writing
// - PCI transaction is done, DMA transfer is not done and we're
// transfering something other than the last word
if (dma_data_vld && !xfer_is_rd)
wr_data_rdy <= (non_aligned_bytes == 2'b00) || !first_word_pci;
else if (wr_data_rdy || wr_pci_done)
wr_data_rdy <= wr_pci_done && !wr_dma_done &&
(!wr_data_rdy || !last_word_to_wr_fifo);
// Record when we've transferred the last word over the PCI and DMA
// buses
if (dma_data_vld && !xfer_is_rd)
wr_pci_done <= last_word_pci;
if (dma_data_vld && !xfer_is_rd || wr_data_rdy)
wr_dma_done <= last_word_to_wr_fifo || (wr_dma_done && wr_data_rdy);
end
end
// ==================================================================
// Sample the read data for non-aligned transfers
// ==================================================================
always @(posedge clk)
begin
if (reset || cnet_reprog)
begin
rdb_data_avail <= 1'b0;
rd_cnet_done <= 1'b0;
end
else
begin
// Shift data into the buffer when we've got a word from the CNET or
// when we need to do a shift of the last word to ensure we push all
// data to the host.
if (rdb_wr_en || rd_data_rdy)
case (non_aligned_bytes)
2'b01 : rd_realign_buf <= {rd_realign_buf[23:0], dma_data_frm_cnet_swapped};
2'b10 : rd_realign_buf <= {rd_realign_buf[23:8], dma_data_frm_cnet_swapped, 8'b0};
2'b11 : rd_realign_buf <= {rd_realign_buf[23:16], dma_data_frm_cnet_swapped, 16'b0};
default : rd_realign_buf <= {dma_data_frm_cnet_swapped, 24'b0};
endcase
// Record when there is data available
if (rdb_wr_en)
rdb_data_avail <= 1'b1;
else if (rd_data_rdy)
rdb_data_avail <= rd_cnet_done && !rd_fifo_done &&
(!rdb_data_avail || !last_word_to_rd_fifo);
// Record when we've transferred the last word from the CNET and to
// the read FIFO
if (rdb_wr_en)
rd_cnet_done <= last_word_from_cnet;
if (rdb_wr_en || rd_data_rdy)
rd_fifo_done <= last_word_to_rd_fifo || (rd_data_rdy && rd_fifo_done);
end
end
// ==================================================================
// Work out the data to input into the Write FIFO
// ==================================================================
always @*
begin
case (non_aligned_bytes)
2'b00 : wr_buf_data_swapped <= wr_realign_buf[31:0];
2'b01 : wr_buf_data_swapped <= wr_realign_buf[39:8];
2'b10 : wr_buf_data_swapped <= wr_realign_buf[47:16];
default : wr_buf_data_swapped <= wr_realign_buf[55:24];
endcase
end
assign wr_buf_data = {wr_buf_data_swapped[7:0],
wr_buf_data_swapped[15:8],
wr_buf_data_swapped[23:16],
wr_buf_data_swapped[31:24]};
// ==================================================================
// Work out the data to input into the Read FIFO
// ==================================================================
always @*
rd_buf_data_swapped <= rd_realign_buf[55:24];
assign rd_buf_data = host_is_le ?
{rd_buf_data_swapped[7:0],
rd_buf_data_swapped[15:8],
rd_buf_data_swapped[23:16],
rd_buf_data_swapped[31:24]} :
rd_buf_data_swapped;
assign dma_data_frm_cnet_swapped = {
dma_data_frm_cnet[7:0],
dma_data_frm_cnet[15:8],
dma_data_frm_cnet[23:16],
dma_data_frm_cnet[31:24]
};
// ==================================================================
// Rd/Wr FIFO transfer counters
// ==================================================================
always @(posedge clk)
begin
if (reset || cnet_reprog)
to_wr_fifo_cnt <= 'h0;
else if (ld_xfer_cnt)
to_wr_fifo_cnt <= to_cnet_cnt_start;
else if (wr_data_rdy)
to_wr_fifo_cnt <= to_wr_fifo_cnt - 'h1;
end
always @(posedge clk)
begin
if (reset || cnet_reprog)
to_rd_fifo_cnt <= 'h0;
else if (ld_xfer_cnt)
to_rd_fifo_cnt <= xfer_cnt_start;
else if (rd_data_rdy)
to_rd_fifo_cnt <= to_rd_fifo_cnt - 'h1;
end
assign last_word_to_wr_fifo = to_wr_fifo_cnt == 'h1;
assign last_word_to_rd_fifo = to_rd_fifo_cnt == 'h1;
// ==================================================================
// Miscelaneous signal generation
// ==================================================================
// Record when there is data available from the CNET
always @(posedge clk)
begin
if (reset || cnet_reprog)
data_frm_cnet_ready <= 1'b0;
else if (dma_rd_en)
data_frm_cnet_ready <= 1'b1;
else if (rd_data_rdy || discard)
data_frm_cnet_ready <= 1'b0;
end
// Write a word into the read buffer if data is available and we're not
// discarding and the output fifo isn't backed up
assign rdb_wr_en = data_frm_cnet_ready && !discard && !rd_full;
assign read_from_cnet = rdb_wr_en;
// Generate the read ready signal
assign rd_data_rdy = rdb_data_avail && !rd_full;
// Pull the next word from the CNET if there's data available and either:
// - we don't currently have any data
// - we're discarding the current word
// - we're writing the current word into the realign buffer
assign dma_rd_en = !dma_empty &&
(!data_frm_cnet_ready || discard || rdb_wr_en);
endmodule // dma_engine_alignment
|
//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the N64 RGB/YPbPr DAC project.
//
// Copyright (C) 2015-2021 by Peter Bartmann <[email protected]>
//
// N64 RGB/YPbPr DAC is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//////////////////////////////////////////////////////////////////////////////////
//
// Company: Circuit-Board.de
// Engineer: borti4938
//
// Module Name: n64adv_top
// Project Name: N64 Advanced RGB/YPbPr DAC Mod
// Target Devices: Cyclone IV: EP4CE10E22
// Cyclone 10 LP: 10CL010YE144
// Tool versions: Altera Quartus Prime
//
// Revision: 1.33
// Features: see repository readme
//
//////////////////////////////////////////////////////////////////////////////////
module n64adv_top (
// N64 Video Input
VCLK,
nVDSYNC,
VD_i,
// System CLK, Controller and Reset
SYS_CLK,
CTRL_i,
nRST,
// Video Output to ADV712x
CLK_ADV712x,
nCSYNC_ADV712x,
// nBLANK_ADV712x,
VD_o, // video component data vector
// Sync / Debug / Filter AddOn Output
nCSYNC,
nVSYNC_or_F2,
nHSYNC_or_F1,
// Jumper VGA Sync / Filter AddOn
UseVGA_HVSync, // (J1) use Filter out if '0'; use /HS and /VS if '1'
nFilterBypass, // (J1) bypass filter if '0'; set filter as output if '1'
// (only applicable if UseVGA_HVSync is '0')
// Jumper Video Output Type and Scanlines
nEN_RGsB, // (J2) generate RGsB if '0'
nEN_YPbPr, // (J2) generate RGsB if '0' (no RGB, no RGsB (overrides nEN_RGsB))
SL_str, // (J3) Scanline strength (only for line multiplication and not for 480i bob-deint.)
n240p, // (J4) no linemultiplication for 240p if '0' (beats n480i_bob)
n480i_bob // (J4) bob de-interlacing of 480i material if '0'
);
parameter [3:0] hdl_fw_main = 4'd1;
parameter [7:0] hdl_fw_sub = 8'd67;
`include "vh/n64adv_vparams.vh"
input VCLK;
input nVDSYNC;
input [color_width_i-1:0] VD_i;
input SYS_CLK;
input CTRL_i;
inout nRST;
output CLK_ADV712x;
output nCSYNC_ADV712x;
// output nBLANK_ADV712x;
output [3*color_width_o-1:0] VD_o;
output nCSYNC;
output nVSYNC_or_F2;
output nHSYNC_or_F1;
input UseVGA_HVSync;
input nFilterBypass;
input nEN_RGsB;
input nEN_YPbPr;
input [1:0] SL_str;
input n240p;
input n480i_bob;
// input registering
wire VCLK_w = VCLK;
wire nVDSYNC_w;
wire [6:0] VD_w;
register_sync #(
.reg_width(8),
.reg_preset(8'h00)
) inp_vregs_u(
.clk(VCLK_w),
.clk_en(1'b1),
.nrst(1'b1),
.reg_i({nVDSYNC,VD_i}),
.reg_o({nVDSYNC_w,VD_w})
);
// housekeeping of clocks and resets
wire [1:0] MANAGE_VPLL;
wire VCLK_PLL_LOCKED;
wire [1:0] VCLK_Tx_select_w;
wire nVRST, VCLK_Tx_w, nVRST_Tx_w;
wire [2:0] CLKs_controller, nSRST;
n64adv_clk_n_rst_hk clk_n_rst_hk_u(
.VCLK(VCLK_w),
.SYS_CLK(SYS_CLK),
.nRST(nRST),
.nVRST(nVRST),
.VCLK_PLL_LOCKED(VCLK_PLL_LOCKED),
.VCLK_select(VCLK_Tx_select_w),
.VCLK_Tx(VCLK_Tx_w),
.nVRST_Tx(nVRST_Tx_w),
.CLKs_controller(CLKs_controller),
.nSRST(nSRST)
);
// controller module
wire [12:0] PPUState;
wire [ 7:0] JumperCfgSet = {UseVGA_HVSync,~nFilterBypass,n240p,~n480i_bob,~SL_str,~nEN_YPbPr,(nEN_YPbPr & ~nEN_RGsB)}; // (~nEN_YPbPr | nEN_RGsB) ensures that not both jumpers are set and passed through the NIOS II
wire USE_VPLL;
wire [68:0] PPUConfigSet;
wire OSD_VSync;
wire [24:0] OSDWrVector;
wire [ 1:0] OSDInfo;
n64adv_controller #({hdl_fw_main,hdl_fw_sub}) n64adv_controller_u(
.CLKs(CLKs_controller),
.nRST(nRST),
.nSRST(nSRST),
.CTRL(CTRL_i),
.PPUState({PPUState[12:10],VCLK_PLL_LOCKED,PPUState[8:0]}),
.JumperCfgSet(JumperCfgSet),
.USE_VPLL(USE_VPLL),
.PPUConfigSet(PPUConfigSet),
.OSD_VSync(OSD_VSync),
.OSDWrVector(OSDWrVector),
.OSDInfo(OSDInfo),
.VCLK(VCLK_w),
.nVDSYNC(nVDSYNC_w),
.VD_VSi(VD_w[3]),
.nVRST(nVRST)
);
// picture processing module
n64adv_ppu_top n64adv_ppu_u(
.VCLK(VCLK_w),
.nVRST(nVRST),
.nVDSYNC(nVDSYNC_w),
.VD_i(VD_w),
.PPUState(PPUState),
.ConfigSet(PPUConfigSet),
.OSDCLK(CLKs_controller[0]),
.OSD_VSync(OSD_VSync),
.OSDWrVector(OSDWrVector),
.OSDInfo(OSDInfo),
.USE_VPLL(USE_VPLL),
.VCLK_Tx_select(VCLK_Tx_select_w),
.VCLK_Tx(VCLK_Tx_w),
.nVRST_Tx(nVRST_Tx_w),
// .nBLANK(nBLANK_ADV712x),
.VD_o(VD_o),
.nCSYNC({nCSYNC,nCSYNC_ADV712x}),
.UseVGA_HVSync(UseVGA_HVSync),
.nVSYNC_or_F2(nVSYNC_or_F2),
.nHSYNC_or_F1(nHSYNC_or_F1)
);
assign CLK_ADV712x = VCLK_Tx_w;
endmodule
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: ddr3_s4_amphy_phy_alt_mem_phy_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 208 07/03/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module ddr3_s4_amphy_phy_alt_mem_phy_pll (
areset,
inclk0,
phasecounterselect,
phasestep,
phaseupdown,
scanclk,
c0,
c1,
c2,
c3,
c4,
c5,
c6,
locked,
phasedone);
input areset;
input inclk0;
input [3:0] phasecounterselect;
input phasestep;
input phaseupdown;
input scanclk;
output c0;
output c1;
output c2;
output c3;
output c4;
output c5;
output c6;
output locked;
output phasedone;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [3:0] phasecounterselect;
tri0 phasestep;
tri0 phaseupdown;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "2"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR5 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR6 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE5 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE6 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "150.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE5 STRING "150.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE6 STRING "150.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT5 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT6 STRING "deg"
// Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_EDIT STRING "83.00000000"
// Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_UNIT STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR5 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR6 NUMERIC "2"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "150.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ5 STRING "150.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ6 STRING "150.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE5 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE6 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT5 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT6 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "1"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "30.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "60.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-90.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT5 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT6 STRING "240.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "1"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT5 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT6 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "alt_mem_phy_pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK5 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK6 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
// Retrieval info: PRIVATE: USE_CLK5 STRING "1"
// Retrieval info: PRIVATE: USE_CLK6 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "556"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "556"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-833"
// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK5_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK5_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK5_MULTIPLY_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK5_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK6_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK6_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK6_MULTIPLY_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK6_PHASE_SHIFT STRING "4444"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: VCO_FREQUENCY_CONTROL STRING "MANUAL_PHASE"
// Retrieval info: CONSTANT: VCO_PHASE_SHIFT_STEP NUMERIC "83"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "10"
// Retrieval info: USED_PORT: @clk 0 0 10 0 OUTPUT_CLK_EXT VCC "@clk[9..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
// Retrieval info: USED_PORT: c5 0 0 0 0 OUTPUT_CLK_EXT VCC "c5"
// Retrieval info: USED_PORT: c6 0 0 0 0 OUTPUT_CLK_EXT VCC "c6"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: USED_PORT: phasecounterselect 0 0 4 0 INPUT GND "phasecounterselect[3..0]"
// Retrieval info: USED_PORT: phasedone 0 0 0 0 OUTPUT GND "phasedone"
// Retrieval info: USED_PORT: phasestep 0 0 0 0 INPUT GND "phasestep"
// Retrieval info: USED_PORT: phaseupdown 0 0 0 0 INPUT GND "phaseupdown"
// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: @phasecounterselect 0 0 4 0 phasecounterselect 0 0 4 0
// Retrieval info: CONNECT: @phasestep 0 0 0 0 phasestep 0 0 0 0
// Retrieval info: CONNECT: @phaseupdown 0 0 0 0 phaseupdown 0 0 0 0
// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
// Retrieval info: CONNECT: c5 0 0 0 0 @clk 0 0 1 5
// Retrieval info: CONNECT: c6 0 0 0 0 @clk 0 0 1 6
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: phasedone 0 0 0 0 @phasedone 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_amphy_phy_alt_mem_phy_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_amphy_phy_alt_mem_phy_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_amphy_phy_alt_mem_phy_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_amphy_phy_alt_mem_phy_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_amphy_phy_alt_mem_phy_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_amphy_phy_alt_mem_phy_pll_bb.v TRUE
|
module PressCount(clock0,clock180,reset,countu,countd,nr_presses,vga_hsync,vga_vsync,vga_r,vga_g,vga_b);
input wire clock0;
input wire clock180;
input wire reset;
input wire countu;
input wire countd;
output wire [7:0] nr_presses;
output wire vga_hsync;
output wire vga_vsync;
output wire vga_r;
output wire vga_g;
output wire vga_b;
wire [7:0] seq_next;
wire [11:0] seq_oreg;
wire [7:0] seq_oreg_wen;
wire [19:0] coderom_data_o;
wire [4095:0] coderomtext_data_o;
wire [7:0] alu_result;
wire pushbtnu_button_status;
wire pushbtnd_button_status;
wire [7:0] ledbank_leds;
assign nr_presses = ledbank_leds;
Seq
seq (.clock(clock0),
.reset(reset),
.inst(coderom_data_o),
.inst_text(coderomtext_data_o),
.inst_en(1),
.ireg_0(alu_result),
.ireg_1({7'h0,pushbtnu_button_status}),
.ireg_2({7'h0,pushbtnd_button_status}),
.ireg_3(8'h00),
.next(seq_next),
.oreg(seq_oreg),
.oreg_wen(seq_oreg_wen));
PressCountRom
coderom (.addr(seq_next),
.data_o(coderom_data_o));
`ifdef SIM
PressCountRomText
coderomtext (.addr(seq_next),
.data_o(coderomtext_data_o));
`endif
Alu
alu (.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[0]),
.result(alu_result));
PushBtn #(.DebounceWait(40000),
.DebounceSize(16))
pushbtnu (.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[1]),
.button(countu),
.button_status(pushbtnu_button_status));
PushBtn #(.DebounceWait(40000),
.DebounceSize(16))
pushbtnd (.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[2]),
.button(countd),
.button_status(pushbtnd_button_status));
LedBank
ledbank (.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[3]),
.leds(ledbank_leds));
VGA1
vga (.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[4]),
.vga_hsync(vga_hsync),
.vga_vsync(vga_vsync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b));
endmodule // PressCount
|
// Test bench for our 6 bit shift register.
module main;
reg clk, rst_n, in;
wire [5:0] q;
wire d;
strober st (clk, rst_n, d);
shift sh (clk, rst_n, d, q);
always #10 clk = ~clk;
task assert(input condition);
if(!condition)
$finish(2);
endtask // assert
initial begin
clk = 0;
rst_n = 0;
#5 rst_n = 1;
#5
$display("q = %d rst_n = %d, d = %d", q, rst_n, d);
assert(q == 6'd0);
#10
$display("q = %d rst_n = %d, d = %d", q, rst_n, d);
assert(q == 6'd1);
#20 $display("q = %d rst_n = %d, d = %d", q, rst_n, d);
assert(q == 6'd2);
#20 $display("q = %d rst_n = %d, d = %d", q, rst_n, d);
assert(q == 6'd4);
#20 $display("q = %d rst_n = %d, d = %d", q, rst_n, d);
assert(q == 6'd8);
#20 $display("q = %d rst_n = %d, d = %d", q, rst_n, d);
assert(q == 6'd16);
#20 $display("q = %d rst_n = %d, d = %d", q, rst_n, d);
assert(q == 6'd32);
#20 $display("q = %d rst_n = %d, d = %d", q, rst_n, d);
assert(q == 6'd1);
#20 $display("q = %d rst_n = %d, d = %d", q, rst_n, d);
assert(q == 6'd2);
#20 $display("q = %d rst_n = %d, d = %d", q, rst_n, d);
assert(q == 6'd4);
$finish;
end // initial begin
endmodule // main
|
module trafficlight_controller (input wire clk,
input wire rst,
output reg light1_green,
output reg light1_red,
output reg light1_yellow,
output reg light2_green,
output reg light2_red,
output reg light2_yellow);
reg [1:0] current_state;
reg [1:0] next_state;
reg [15:0] counter_value;
localparam F100HZ_DELAY_60SEC_CC_CNT = 16'd6000;
localparam F100HZ_DELAY_5SEC_CC_CNT = 16'd500;
localparam STATE_GR = 2'b00;
localparam STATE_YR = 2'b01;
localparam STATE_RG = 2'b10;
localparam STATE_RY = 2'b11;
// Current state s(k) = delay[s(k+1)], where s(k+1) = next state
always @ ( posedge clk, posedge rst ) begin
if( rst )
begin
current_state <= STATE_GR;
end
else
begin
current_state <= next_state;
end
end
// Counter for time delays
always @ ( posedge clk, posedge rst ) begin
if( rst )
begin
counter_value <= 16'b0;
end
else
begin
case (current_state)
STATE_GR, STATE_RG:
// Wait for 60 sec
if( counter_value < F100HZ_DELAY_60SEC_CC_CNT )
counter_value <= counter_value + 1'b1;
else
counter_value <= 16'b0;
STATE_YR, STATE_RY:
// Wait for 5 sec
if( counter_value < F100HZ_DELAY_5SEC_CC_CNT )
counter_value <= counter_value + 1'b1;
else
counter_value <= 16'b0;
endcase
end
end
// Next State function: s(k+1) = f[i(k), s(k)]
always @ ( * ) begin
case (current_state)
STATE_GR:
// Wait for 60 sec
if( counter_value < F100HZ_DELAY_60SEC_CC_CNT )
next_state <= STATE_GR;
else
next_state <= STATE_YR;
STATE_YR:
// Wait for 5 sec
if( counter_value < F100HZ_DELAY_5SEC_CC_CNT )
next_state <= STATE_YR;
else
next_state <= STATE_RG;
STATE_RG:
// Wait for 60 sec
if( counter_value < F100HZ_DELAY_60SEC_CC_CNT )
next_state <= STATE_RG;
else
next_state <= STATE_RY;
STATE_RY:
// Wait for 5 sec
if( counter_value < F100HZ_DELAY_5SEC_CC_CNT )
next_state <= STATE_RY;
else
next_state <= STATE_GR;
default:
next_state <= STATE_GR;
endcase
end
// Output function : o(k) = g[s(k)]
always @ ( * ) begin
// default all lights OFF
light1_green <= 1'b0;
light1_red <= 1'b0;
light1_yellow <= 1'b0;
light2_green <= 1'b0;
light2_red <= 1'b0;
light2_yellow <= 1'b0;
case (current_state)
STATE_GR:
begin
light1_green <= 1'b1;
light2_red <= 1'b1;
end
STATE_YR:
begin
light1_yellow <= 1'b1;
light2_red <= 1'b1;
end
STATE_RG:
begin
light1_red <= 1'b1;
light2_green <=1'b1;
end
STATE_RY:
begin
light1_red <= 1'b1;
light2_yellow <= 1'b1;
end
default:
begin
light1_green <= 1'b1;
light1_red <= 1'b1;
light1_yellow <= 1'b1;
light2_green <= 1'b1;
light2_red <= 1'b1;
light2_yellow <= 1'b1;
end
endcase
end
endmodule //
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_regs.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Registers of the uart 16550 core ////
//// ////
//// Known problems (limits): ////
//// Inserts 1 wait state in all WISHBONE transfers ////
//// ////
//// To Do: ////
//// Nothing or verification. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: (See log for the revision history ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.41 2004/05/21 11:44:41 tadejm
// Added synchronizer flops for RX input.
//
// Revision 1.40 2003/06/11 16:37:47 gorban
// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
//
// Revision 1.39 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.38 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.37 2001/12/27 13:24:09 mohor
// lsr[7] was not showing overrun errors.
//
// Revision 1.36 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.35 2001/12/19 08:03:34 mohor
// Warnings cleared.
//
// Revision 1.34 2001/12/19 07:33:54 mohor
// Synplicity was having troubles with the comment.
//
// Revision 1.33 2001/12/17 10:14:43 mohor
// Things related to msr register changed. After THRE IRQ occurs, and one
// character is written to the transmit fifo, the detection of the THRE bit in the
// LSR is delayed for one character time.
//
// Revision 1.32 2001/12/14 13:19:24 mohor
// MSR register fixed.
//
// Revision 1.31 2001/12/14 10:06:58 mohor
// After reset modem status register MSR should be reset.
//
// Revision 1.30 2001/12/13 10:09:13 mohor
// thre irq should be cleared only when being source of interrupt.
//
// Revision 1.29 2001/12/12 09:05:46 mohor
// LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).
//
// Revision 1.28 2001/12/10 19:52:41 gorban
// Scratch register added
//
// Revision 1.27 2001/12/06 14:51:04 gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.26 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.25 2001/11/28 19:36:39 gorban
// Fixed: timeout and break didn't pay attention to current data format when counting time
//
// Revision 1.24 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.23 2001/11/12 21:57:29 gorban
// fixed more typo bugs
//
// Revision 1.22 2001/11/12 15:02:28 mohor
// lsr1r error fixed.
//
// Revision 1.21 2001/11/12 14:57:27 mohor
// ti_int_pnd error fixed.
//
// Revision 1.20 2001/11/12 14:50:27 mohor
// ti_int_d error fixed.
//
// Revision 1.19 2001/11/10 12:43:21 gorban
// Logic Synthesis bugs fixed. Some other minor changes
//
// Revision 1.18 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.17 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.16 2001/11/02 09:55:16 mohor
// no message
//
// Revision 1.15 2001/10/31 15:19:22 gorban
// Fixes to break and timeout conditions
//
// Revision 1.14 2001/10/29 17:00:46 gorban
// fixed parity sending and tx_fifo resets over- and underrun
//
// Revision 1.13 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.12 2001/10/19 16:21:40 gorban
// Changes data_out to be synchronous again as it should have been.
//
// Revision 1.11 2001/10/18 20:35:45 gorban
// small fix
//
// Revision 1.10 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.9 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.10 2001/06/23 11:21:48 gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.9 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.8 2001/05/29 20:05:04 gorban
// Fixed some bugs and synthesis problems.
//
// Revision 1.7 2001/05/27 17:37:49 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.6 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
//
// Revision 1.5 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:11+02 jacob
// Initial revision
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
`define UART_DL1 7:0
`define UART_DL2 15:8
module uart_regs (clk,
wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_re_i,
// additional signals
modem_inputs,
stx_pad_o, srx_pad_i,
`ifdef DATA_BUS_WIDTH_8
`else
// debug interface signals enabled
ier, iir, fcr, mcr, lcr, msr, lsr, rf_count, tf_count, tstate, rstate,
`endif
rts_pad_o, dtr_pad_o, int_o,
tx_ready,
rx_ready
`ifdef UART_HAS_BAUDRATE_OUTPUT
, baud_o
`endif
);
input clk;
input wb_rst_i;
input [`UART_ADDR_WIDTH-1:0] wb_addr_i;
input [7:0] wb_dat_i;
output [7:0] wb_dat_o;
input wb_we_i;
input wb_re_i;
output stx_pad_o;
input srx_pad_i;
input [3:0] modem_inputs;
output rts_pad_o;
output dtr_pad_o;
output int_o;
output tx_ready;
output rx_ready;
`ifdef UART_HAS_BAUDRATE_OUTPUT
output baud_o;
`endif
`ifdef DATA_BUS_WIDTH_8
`else
// if 32-bit databus and debug interface are enabled
output [3:0] ier;
output [3:0] iir;
output [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
output [4:0] mcr;
output [7:0] lcr;
output [7:0] msr;
output [7:0] lsr;
output [`UART_FIFO_COUNTER_W-1:0] rf_count;
output [`UART_FIFO_COUNTER_W-1:0] tf_count;
output [2:0] tstate;
output [3:0] rstate;
`endif
wire [3:0] modem_inputs;
reg enable;
`ifdef UART_HAS_BAUDRATE_OUTPUT
assign baud_o = enable; // baud_o is actually the enable signal
`endif
wire stx_pad_o; // received from transmitter module
wire srx_pad_i;
wire srx_pad;
reg [7:0] wb_dat_o;
wire [`UART_ADDR_WIDTH-1:0] wb_addr_i;
wire [7:0] wb_dat_i;
reg [3:0] ier;
reg [3:0] iir;
reg [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
reg [4:0] mcr;
reg [7:0] lcr;
reg [7:0] msr;
reg [15:0] dl; // 32-bit divisor latch
reg [7:0] scratch; // UART scratch register
reg start_dlc; // activate dlc on writing to UART_DL1
reg lsr_mask_d; // delay for lsr_mask condition
reg msi_reset; // reset MSR 4 lower bits indicator
//reg threi_clear; // THRE interrupt clear flag
reg [15:0] dlc; // 32-bit divisor latch counter
reg int_o;
reg [3:0] trigger_level; // trigger level of the receiver FIFO
reg rx_reset;
reg tx_reset;
wire dlab; // divisor latch access bit
wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; // modem status bits
wire loopback; // loopback bit (MCR bit 4)
wire cts, dsr, ri, dcd; // effective signals
wire cts_c, dsr_c, ri_c, dcd_c; // Complement effective signals (considering loopback)
wire rts_pad_o, dtr_pad_o; // modem control outputs
// LSR bits wires and regs
wire [7:0] lsr;
wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7;
reg lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r;
wire lsr_mask; // lsr_mask
//
// ASSINGS
//
assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r };
assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs;
assign {cts, dsr, ri, dcd} = ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
assign {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]}
: {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
assign dlab = lcr[`UART_LC_DL];
assign loopback = mcr[4];
// assign modem outputs
assign rts_pad_o = mcr[`UART_MC_RTS];
assign dtr_pad_o = mcr[`UART_MC_DTR];
// Interrupt signals
wire rls_int; // receiver line status interrupt
wire rda_int; // receiver data available interrupt
wire ti_int; // timeout indicator interrupt
wire thre_int; // transmitter holding register empty interrupt
wire ms_int; // modem status interrupt
// FIFO signals
reg tf_push;
reg rf_pop;
wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
wire rf_error_bit; // an error (parity or framing) is inside the fifo
wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
wire [2:0] tstate;
wire [3:0] rstate;
wire [9:0] counter_t;
wire thre_set_en; // THRE status is delayed one character time when a character is written to fifo.
reg [7:0] block_cnt; // While counter counts, THRE status is blocked (delayed one character cycle)
reg [7:0] block_value; // One character length minus stop bit
// Transmitter Instance
wire serial_out;
uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, serial_out, tstate, tf_count, tx_reset, lsr_mask);
// Synchronizing and sampling serial RX input
uart_sync_flops i_uart_sync_flops
(
.rst_i (wb_rst_i),
.clk_i (clk),
.stage1_rst_i (1'b0),
.stage1_clk_en_i (1'b1),
.async_dat_i (srx_pad_i),
.sync_dat_o (srx_pad)
);
defparam i_uart_sync_flops.width = 1;
defparam i_uart_sync_flops.init_value = 1'b1;
// handle loopback
wire serial_in = loopback ? serial_out : srx_pad;
assign stx_pad_o = loopback ? 1'b1 : serial_out;
// Receiver Instance
uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, serial_in, enable,
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
// Asynchronous reading here because the outputs are sampled in uart_wb.v file
always @(dl or dlab or ier or iir or scratch
or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) // asynchrounous reading
begin
case (wb_addr_i)
`UART_REG_RB : wb_dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3];
`UART_REG_IE : wb_dat_o = dlab ? dl[`UART_DL2] : ier;
`UART_REG_II : wb_dat_o = {4'b1100,iir};
`UART_REG_LC : wb_dat_o = lcr;
`UART_REG_LS : wb_dat_o = lsr;
`UART_REG_MS : wb_dat_o = msr;
`UART_REG_SR : wb_dat_o = scratch;
default: wb_dat_o = 8'b0; // ??
endcase // case(wb_addr_i)
end // always @ (dl or dlab or ier or iir or scratch...
// rf_pop signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
rf_pop <= #1 0;
else
if (rf_pop) // restore the signal to 0 after one clock cycle
rf_pop <= #1 0;
else
if (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab)
rf_pop <= #1 1; // advance read pointer
end
wire lsr_mask_condition;
wire iir_read;
wire msr_read;
wire fifo_read;
wire fifo_write;
assign lsr_mask_condition = (wb_re_i && wb_addr_i == `UART_REG_LS && !dlab);
assign iir_read = (wb_re_i && wb_addr_i == `UART_REG_II && !dlab);
assign msr_read = (wb_re_i && wb_addr_i == `UART_REG_MS && !dlab);
assign fifo_read = (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab);
assign fifo_write = (wb_we_i && wb_addr_i == `UART_REG_TR && !dlab);
// lsr_mask_d delayed signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
lsr_mask_d <= #1 0;
else // reset bits in the Line Status Register
lsr_mask_d <= #1 lsr_mask_condition;
end
// lsr_mask is rise detected
assign lsr_mask = lsr_mask_condition && ~lsr_mask_d;
// msi_reset signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
msi_reset <= #1 1;
else
if (msi_reset)
msi_reset <= #1 0;
else
if (msr_read)
msi_reset <= #1 1; // reset bits in Modem Status Register
end
//
// WRITES AND RESETS //
//
// Line Control Register
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
lcr <= #1 8'b00000011; // 8n1 setting
else
if (wb_we_i && wb_addr_i==`UART_REG_LC)
lcr <= #1 wb_dat_i;
// Interrupt Enable Register or UART_DL2
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
begin
ier <= #1 4'b0000; // no interrupts after reset
dl[`UART_DL2] <= #1 8'b0;
end
else
if (wb_we_i && wb_addr_i==`UART_REG_IE)
if (dlab)
begin
dl[`UART_DL2] <= #1 wb_dat_i;
end
else
ier <= #1 wb_dat_i[3:0]; // ier uses only 4 lsb
// FIFO Control Register and rx_reset, tx_reset signals
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
fcr <= #1 2'b11;
rx_reset <= #1 0;
tx_reset <= #1 0;
end else
if (wb_we_i && wb_addr_i==`UART_REG_FC) begin
fcr <= #1 wb_dat_i[7:6];
rx_reset <= #1 wb_dat_i[1];
tx_reset <= #1 wb_dat_i[2];
end else begin
rx_reset <= #1 0;
tx_reset <= #1 0;
end
// Modem Control Register
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
mcr <= #1 5'b0;
else
if (wb_we_i && wb_addr_i==`UART_REG_MC)
mcr <= #1 wb_dat_i[4:0];
// Scratch register
// Line Control Register
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
scratch <= #1 0; // 8n1 setting
else
if (wb_we_i && wb_addr_i==`UART_REG_SR)
scratch <= #1 wb_dat_i;
// TX_FIFO or UART_DL1
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
begin
dl[`UART_DL1] <= #1 8'b0;
tf_push <= #1 1'b0;
start_dlc <= #1 1'b0;
end
else
if (wb_we_i && wb_addr_i==`UART_REG_TR)
if (dlab)
begin
dl[`UART_DL1] <= #1 wb_dat_i;
start_dlc <= #1 1'b1; // enable DL counter
tf_push <= #1 1'b0;
end
else
begin
tf_push <= #1 1'b1;
start_dlc <= #1 1'b0;
end // else: !if(dlab)
else
begin
start_dlc <= #1 1'b0;
tf_push <= #1 1'b0;
end // else: !if(dlab)
// Receiver FIFO trigger level selection logic (asynchronous mux)
always @(fcr)
case (fcr[`UART_FC_TL])
2'b00 : trigger_level = 1;
2'b01 : trigger_level = 4;
2'b10 : trigger_level = 8;
2'b11 : trigger_level = 14;
endcase // case(fcr[`UART_FC_TL])
//
// STATUS REGISTERS //
//
// Modem Status Register
reg [3:0] delayed_modem_signals;
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
begin
msr <= #1 0;
delayed_modem_signals[3:0] <= #1 0;
end
else begin
msr[`UART_MS_DDCD:`UART_MS_DCTS] <= #1 msi_reset ? 4'b0 :
msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]);
msr[`UART_MS_CDCD:`UART_MS_CCTS] <= #1 {dcd_c, ri_c, dsr_c, cts_c};
delayed_modem_signals[3:0] <= #1 {dcd, ri, dsr, cts};
end
end
// Line Status Register
// activation conditions
assign lsr0 = (rf_count==0 && rf_push_pulse); // data in receiver fifo available set condition
assign lsr1 = rf_overrun; // Receiver overrun error
assign lsr2 = rf_data_out[1]; // parity error bit
assign lsr3 = rf_data_out[0]; // framing error bit
assign lsr4 = rf_data_out[2]; // break error in the character
assign lsr5 = (tf_count==5'b0 && thre_set_en); // transmitter fifo is empty
assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == /*`S_IDLE */ 0)); // transmitter empty
assign lsr7 = rf_error_bit | rf_overrun;
reg [3:0] tf_full;
always @(posedge clk or posedge wb_rst_i) begin
if (wb_rst_i) begin
tf_full <= 0;
end else begin
case (tf_full)
2'b11: tf_full <= 15;
2'b10: tf_full <= 7;
2'b01: tf_full <= 3;
2'b00: tf_full <= 1;
endcase
end
end
reg rx_ready_r1;
reg rx_ready_r2;
reg rx_ready_r3;
reg rx_ready_r4;
assign rx_ready = rx_ready_r4 && (rf_count > 1 || (rf_count == 1 && rf_pop == 0));
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
rx_ready_r1 <= 0;
rx_ready_r2 <= 0;
rx_ready_r3 <= 0;
rx_ready_r4 <= 0;
end else begin
rx_ready_r1 <= (rf_count != 0);
rx_ready_r2 <= rx_ready_r1;
rx_ready_r3 <= rx_ready_r2;
rx_ready_r4 <= rx_ready_r3;
end
assign tx_ready = (tf_count < tf_full);
// lsr bit0 (receiver data available)
reg lsr0_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr0_d <= #1 0;
else lsr0_d <= #1 lsr0;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr0r <= #1 0;
else lsr0r <= #1 (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 0 : // deassert condition
lsr0r || (lsr0 && ~lsr0_d); // set on rise of lsr0 and keep asserted until deasserted
// lsr bit 1 (receiver overrun)
reg lsr1_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr1_d <= #1 0;
else lsr1_d <= #1 lsr1;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr1r <= #1 0;
else lsr1r <= #1 lsr_mask ? 0 : lsr1r || (lsr1 && ~lsr1_d); // set on rise
// lsr bit 2 (parity error)
reg lsr2_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr2_d <= #1 0;
else lsr2_d <= #1 lsr2;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr2r <= #1 0;
else lsr2r <= #1 lsr_mask ? 0 : lsr2r || (lsr2 && ~lsr2_d); // set on rise
// lsr bit 3 (framing error)
reg lsr3_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr3_d <= #1 0;
else lsr3_d <= #1 lsr3;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr3r <= #1 0;
else lsr3r <= #1 lsr_mask ? 0 : lsr3r || (lsr3 && ~lsr3_d); // set on rise
// lsr bit 4 (break indicator)
reg lsr4_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr4_d <= #1 0;
else lsr4_d <= #1 lsr4;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr4r <= #1 0;
else lsr4r <= #1 lsr_mask ? 0 : lsr4r || (lsr4 && ~lsr4_d);
// lsr bit 5 (transmitter fifo is empty)
reg lsr5_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr5_d <= #1 1;
else lsr5_d <= #1 lsr5;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr5r <= #1 1;
else lsr5r <= #1 (fifo_write) ? 0 : lsr5r || (lsr5 && ~lsr5_d);
// lsr bit 6 (transmitter empty indicator)
reg lsr6_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr6_d <= #1 1;
else lsr6_d <= #1 lsr6;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr6r <= #1 1;
else lsr6r <= #1 (fifo_write) ? 0 : lsr6r || (lsr6 && ~lsr6_d);
// lsr bit 7 (error in fifo)
reg lsr7_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr7_d <= #1 0;
else lsr7_d <= #1 lsr7;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr7r <= #1 0;
else lsr7r <= #1 lsr_mask ? 0 : lsr7r || (lsr7 && ~lsr7_d);
// Frequency divider
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
dlc <= #1 0;
else
if (start_dlc | ~ (|dlc))
dlc <= #1 dl - 1; // preset counter
else
dlc <= #1 dlc - 1; // decrement counter
end
// Enable signal generation logic
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
enable <= #1 1'b0;
else
if (|dl & ~(|dlc)) // dl>0 & dlc==0
enable <= #1 1'b1;
else
enable <= #1 1'b0;
end
// Delaying THRE status for one character cycle after a character is written to an empty fifo.
always @(lcr)
case (lcr[3:0])
4'b0000 : block_value = 95; // 6 bits
4'b0100 : block_value = 103; // 6.5 bits
4'b0001, 4'b1000 : block_value = 111; // 7 bits
4'b1100 : block_value = 119; // 7.5 bits
4'b0010, 4'b0101, 4'b1001 : block_value = 127; // 8 bits
4'b0011, 4'b0110, 4'b1010, 4'b1101 : block_value = 143; // 9 bits
4'b0111, 4'b1011, 4'b1110 : block_value = 159; // 10 bits
4'b1111 : block_value = 175; // 11 bits
endcase // case(lcr[3:0])
// Counting time of one character minus stop bit
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
block_cnt <= #1 8'd0;
else
if(lsr5r & fifo_write) // THRE bit set & write to fifo occured
block_cnt <= #1 block_value;
else
if (enable & block_cnt != 8'b0) // only work on enable times
block_cnt <= #1 block_cnt - 1; // decrement break counter
end // always of break condition detection
// Generating THRE status enable signal
assign thre_set_en = ~(|block_cnt);
//
// INTERRUPT LOGIC
//
assign rls_int = ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]);
assign rda_int = ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level});
assign thre_int = ier[`UART_IE_THRE] && lsr[`UART_LS_TFE];
assign ms_int = ier[`UART_IE_MS] && (| msr[3:0]);
assign ti_int = ier[`UART_IE_RDA] && (counter_t == 10'b0) && (|rf_count);
reg rls_int_d;
reg thre_int_d;
reg ms_int_d;
reg ti_int_d;
reg rda_int_d;
// delay lines
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rls_int_d <= #1 0;
else rls_int_d <= #1 rls_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rda_int_d <= #1 0;
else rda_int_d <= #1 rda_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) thre_int_d <= #1 0;
else thre_int_d <= #1 thre_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ms_int_d <= #1 0;
else ms_int_d <= #1 ms_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ti_int_d <= #1 0;
else ti_int_d <= #1 ti_int;
// rise detection signals
wire rls_int_rise;
wire thre_int_rise;
wire ms_int_rise;
wire ti_int_rise;
wire rda_int_rise;
assign rda_int_rise = rda_int & ~rda_int_d;
assign rls_int_rise = rls_int & ~rls_int_d;
assign thre_int_rise = thre_int & ~thre_int_d;
assign ms_int_rise = ms_int & ~ms_int_d;
assign ti_int_rise = ti_int & ~ti_int_d;
// interrupt pending flags
reg rls_int_pnd;
reg rda_int_pnd;
reg thre_int_pnd;
reg ms_int_pnd;
reg ti_int_pnd;
// interrupt pending flags assignments
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rls_int_pnd <= #1 0;
else
rls_int_pnd <= #1 lsr_mask ? 0 : // reset condition
rls_int_rise ? 1 : // latch condition
rls_int_pnd && ier[`UART_IE_RLS]; // default operation: remove if masked
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rda_int_pnd <= #1 0;
else
rda_int_pnd <= #1 ((rf_count == {1'b0,trigger_level}) && fifo_read) ? 0 : // reset condition
rda_int_rise ? 1 : // latch condition
rda_int_pnd && ier[`UART_IE_RDA]; // default operation: remove if masked
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) thre_int_pnd <= #1 0;
else
thre_int_pnd <= #1 fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 0 :
thre_int_rise ? 1 :
thre_int_pnd && ier[`UART_IE_THRE];
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ms_int_pnd <= #1 0;
else
ms_int_pnd <= #1 msr_read ? 0 :
ms_int_rise ? 1 :
ms_int_pnd && ier[`UART_IE_MS];
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ti_int_pnd <= #1 0;
else
ti_int_pnd <= #1 fifo_read ? 0 :
ti_int_rise ? 1 :
ti_int_pnd && ier[`UART_IE_RDA];
// end of pending flags
// INT_O logic
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
int_o <= #1 1'b0;
else
int_o <= #1
rls_int_pnd ? ~lsr_mask :
rda_int_pnd ? 1 :
ti_int_pnd ? ~fifo_read :
thre_int_pnd ? !(fifo_write & iir_read) :
ms_int_pnd ? ~msr_read :
0; // if no interrupt are pending
end
// Interrupt Identification register
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
iir <= #1 1;
else
if (rls_int_pnd) // interrupt is pending
begin
iir[`UART_II_II] <= #1 `UART_II_RLS; // set identification register to correct value
iir[`UART_II_IP] <= #1 1'b0; // and clear the IIR bit 0 (interrupt pending)
end else // the sequence of conditions determines priority of interrupt identification
if (rda_int)
begin
iir[`UART_II_II] <= #1 `UART_II_RDA;
iir[`UART_II_IP] <= #1 1'b0;
end
else if (ti_int_pnd)
begin
iir[`UART_II_II] <= #1 `UART_II_TI;
iir[`UART_II_IP] <= #1 1'b0;
end
else if (thre_int_pnd)
begin
iir[`UART_II_II] <= #1 `UART_II_THRE;
iir[`UART_II_IP] <= #1 1'b0;
end
else if (ms_int_pnd)
begin
iir[`UART_II_II] <= #1 `UART_II_MS;
iir[`UART_II_IP] <= #1 1'b0;
end else // no interrupt is pending
begin
iir[`UART_II_II] <= #1 0;
iir[`UART_II_IP] <= #1 1'b1;
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 11:21:00 10/17/2016
// Module Name: CONTROL
// Project Name: MIPS
// Description: Control module of the DECODE stage.
//
// Dependencies: None
//
////////////////////////////////////////////////////////////////////////////////
module CONTROL(input [5:0] opcode, output reg [1:0] WB, output reg [2:0] M,
output reg [3:0] EX);
always @ *
begin
case (opcode)
6'b000000: // R-format
begin
WB <= 2'b10;
M <= 3'b000;
EX <= 4'b1100;
end
6'b100011: // I-Format: Load Word
begin
WB <= 2'b11;
M <= 3'b010;
EX <= 4'b0001;
end
6'b101011: // I-Format: Store Word
begin
WB <= 2'b0x;
M <= 3'b001;
EX <= 4'bx001;
end
6'b000100: // J-Format: Branch on Equal
begin
WB <= 2'b0x;
M <= 3'b100;
EX <= 4'bx010;
end
6'b100000: // NOP
begin
WB <= 2'b00;
M <= 3'b000;
EX <= 4'b0000;
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUFBUF_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__BUFBUF_BEHAVIORAL_PP_V
/**
* bufbuf: Double buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__bufbuf (
VPWR,
VGND,
X ,
A
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUFBUF_BEHAVIORAL_PP_V |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file ROM01.v when simulating
// the core, ROM01. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module ROM01(
clka,
ena,
addra,
douta
);
input clka;
input ena;
input [7 : 0] addra;
output [15 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(8),
.C_ADDRB_WIDTH(8),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("ROM01.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(256),
.C_READ_DEPTH_B(256),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(256),
.C_WRITE_DEPTH_B(256),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ENA(ena),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O41AI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__O41AI_BEHAVIORAL_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o41ai (
Y ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O41AI_BEHAVIORAL_V |
//Legal Notice: (C)2021 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//Register map:
//addr register type
//0 read data r
//1 write data w
//2 status r/w
//3 control r/w
//4 reserved
//5 slave-enable r/w
//6 end-of-packet-value r/w
//INPUT_CLOCK: 62500000
//ISMASTER: 1
//DATABITS: 8
//TARGETCLOCK: 2000000
//NUMSLAVES: 1
//CPOL: 0
//CPHA: 0
//LSBFIRST: 0
//EXTRADELAY: 0
//TARGETSSDELAY: 0
module nios_tester_spi_0 (
// inputs:
MISO,
clk,
data_from_cpu,
mem_addr,
read_n,
reset_n,
spi_select,
write_n,
// outputs:
MOSI,
SCLK,
SS_n,
data_to_cpu,
dataavailable,
endofpacket,
irq,
readyfordata
)
;
output MOSI;
output SCLK;
output SS_n;
output [ 15: 0] data_to_cpu;
output dataavailable;
output endofpacket;
output irq;
output readyfordata;
input MISO;
input clk;
input [ 15: 0] data_from_cpu;
input [ 2: 0] mem_addr;
input read_n;
input reset_n;
input spi_select;
input write_n;
wire E;
reg EOP;
reg MISO_reg;
wire MOSI;
reg ROE;
reg RRDY;
wire SCLK;
reg SCLK_reg;
reg SSO_reg;
wire SS_n;
wire TMT;
reg TOE;
wire TRDY;
wire control_wr_strobe;
reg data_rd_strobe;
reg [ 15: 0] data_to_cpu;
reg data_wr_strobe;
wire dataavailable;
wire ds_MISO;
wire enableSS;
wire endofpacket;
reg [ 15: 0] endofpacketvalue_reg;
wire endofpacketvalue_wr_strobe;
reg iEOP_reg;
reg iE_reg;
reg iROE_reg;
reg iRRDY_reg;
reg iTMT_reg;
reg iTOE_reg;
reg iTRDY_reg;
wire irq;
reg irq_reg;
wire p1_data_rd_strobe;
wire [ 15: 0] p1_data_to_cpu;
wire p1_data_wr_strobe;
wire p1_rd_strobe;
wire [ 4: 0] p1_slowcount;
wire p1_wr_strobe;
reg rd_strobe;
wire readyfordata;
reg [ 7: 0] rx_holding_reg;
reg [ 7: 0] shift_reg;
wire slaveselect_wr_strobe;
wire slowclock;
reg [ 4: 0] slowcount;
wire [ 10: 0] spi_control;
reg [ 15: 0] spi_slave_select_holding_reg;
reg [ 15: 0] spi_slave_select_reg;
wire [ 10: 0] spi_status;
reg [ 4: 0] state;
reg stateZero;
wire status_wr_strobe;
reg transmitting;
reg tx_holding_primed;
reg [ 7: 0] tx_holding_reg;
reg wr_strobe;
wire write_shift_reg;
wire write_tx_holding;
//spi_control_port, which is an e_avalon_slave
assign p1_rd_strobe = ~rd_strobe & spi_select & ~read_n;
// Read is a two-cycle event.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rd_strobe <= 0;
else
rd_strobe <= p1_rd_strobe;
end
assign p1_data_rd_strobe = p1_rd_strobe & (mem_addr == 0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_rd_strobe <= 0;
else
data_rd_strobe <= p1_data_rd_strobe;
end
assign p1_wr_strobe = ~wr_strobe & spi_select & ~write_n;
// Write is a two-cycle event.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wr_strobe <= 0;
else
wr_strobe <= p1_wr_strobe;
end
assign p1_data_wr_strobe = p1_wr_strobe & (mem_addr == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_wr_strobe <= 0;
else
data_wr_strobe <= p1_data_wr_strobe;
end
assign control_wr_strobe = wr_strobe & (mem_addr == 3);
assign status_wr_strobe = wr_strobe & (mem_addr == 2);
assign slaveselect_wr_strobe = wr_strobe & (mem_addr == 5);
assign endofpacketvalue_wr_strobe = wr_strobe & (mem_addr == 6);
assign TMT = ~transmitting & ~tx_holding_primed;
assign E = ROE | TOE;
assign spi_status = {EOP, E, RRDY, TRDY, TMT, TOE, ROE, 3'b0};
// Streaming data ready for pickup.
assign dataavailable = RRDY;
// Ready to accept streaming data.
assign readyfordata = TRDY;
// Endofpacket condition detected.
assign endofpacket = EOP;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
iEOP_reg <= 0;
iE_reg <= 0;
iRRDY_reg <= 0;
iTRDY_reg <= 0;
iTMT_reg <= 0;
iTOE_reg <= 0;
iROE_reg <= 0;
SSO_reg <= 0;
end
else if (control_wr_strobe)
begin
iEOP_reg <= data_from_cpu[9];
iE_reg <= data_from_cpu[8];
iRRDY_reg <= data_from_cpu[7];
iTRDY_reg <= data_from_cpu[6];
iTMT_reg <= data_from_cpu[5];
iTOE_reg <= data_from_cpu[4];
iROE_reg <= data_from_cpu[3];
SSO_reg <= data_from_cpu[10];
end
end
assign spi_control = {SSO_reg, iEOP_reg, iE_reg, iRRDY_reg, iTRDY_reg, 1'b0, iTOE_reg, iROE_reg, 3'b0};
// IRQ output.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_reg <= 0;
else
irq_reg <= (EOP & iEOP_reg) | ((TOE | ROE) & iE_reg) | (RRDY & iRRDY_reg) | (TRDY & iTRDY_reg) | (TOE & iTOE_reg) | (ROE & iROE_reg);
end
assign irq = irq_reg;
// Slave select register.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
spi_slave_select_reg <= 1;
else if (write_shift_reg || control_wr_strobe & data_from_cpu[10] & ~SSO_reg)
spi_slave_select_reg <= spi_slave_select_holding_reg;
end
// Slave select holding register.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
spi_slave_select_holding_reg <= 1;
else if (slaveselect_wr_strobe)
spi_slave_select_holding_reg <= data_from_cpu;
end
// slowclock is active once every 16 system clock pulses.
assign slowclock = slowcount == 5'hF;
assign p1_slowcount = ({5 {(transmitting && !slowclock)}} & (slowcount + 1)) |
({5 {(~((transmitting && !slowclock)))}} & 0);
// Divide counter for SPI clock.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
slowcount <= 0;
else
slowcount <= p1_slowcount;
end
// End-of-packet value register.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
endofpacketvalue_reg <= 0;
else if (endofpacketvalue_wr_strobe)
endofpacketvalue_reg <= data_from_cpu;
end
assign p1_data_to_cpu = ((mem_addr == 2))? spi_status :
((mem_addr == 3))? spi_control :
((mem_addr == 6))? endofpacketvalue_reg :
((mem_addr == 5))? spi_slave_select_reg :
rx_holding_reg;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_to_cpu <= 0;
else
// Data to cpu.
data_to_cpu <= p1_data_to_cpu;
end
// 'state' counts from 0 to 17.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
state <= 0;
stateZero <= 1;
end
else if (transmitting & slowclock)
begin
stateZero <= state == 17;
if (state == 17)
state <= 0;
else
state <= state + 1;
end
end
assign enableSS = transmitting & ~stateZero;
assign MOSI = shift_reg[7];
assign SS_n = (enableSS | SSO_reg) ? ~spi_slave_select_reg : {1 {1'b1} };
assign SCLK = SCLK_reg;
// As long as there's an empty spot somewhere,
//it's safe to write data.
assign TRDY = ~(transmitting & tx_holding_primed);
// Enable write to tx_holding_register.
assign write_tx_holding = data_wr_strobe & TRDY;
// Enable write to shift register.
assign write_shift_reg = tx_holding_primed & ~transmitting;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
shift_reg <= 0;
rx_holding_reg <= 0;
EOP <= 0;
RRDY <= 0;
ROE <= 0;
TOE <= 0;
tx_holding_reg <= 0;
tx_holding_primed <= 0;
transmitting <= 0;
SCLK_reg <= 0;
MISO_reg <= 0;
end
else
begin
if (write_tx_holding)
begin
tx_holding_reg <= data_from_cpu;
tx_holding_primed <= 1;
end
if (data_wr_strobe & ~TRDY)
// You wrote when I wasn't ready.
TOE <= 1;
// EOP must be updated by the last (2nd) cycle of access.
if ((p1_data_rd_strobe && (rx_holding_reg == endofpacketvalue_reg)) || (p1_data_wr_strobe && (data_from_cpu[7 : 0] == endofpacketvalue_reg)))
EOP <= 1;
if (write_shift_reg)
begin
shift_reg <= tx_holding_reg;
transmitting <= 1;
end
if (write_shift_reg & ~write_tx_holding)
// Clear tx_holding_primed
tx_holding_primed <= 0;
if (data_rd_strobe)
// On data read, clear the RRDY bit.
RRDY <= 0;
if (status_wr_strobe)
begin
// On status write, clear all status bits (ignore the data).
EOP <= 0;
RRDY <= 0;
ROE <= 0;
TOE <= 0;
end
if (slowclock)
begin
if (state == 17)
begin
transmitting <= 0;
RRDY <= 1;
rx_holding_reg <= shift_reg;
SCLK_reg <= 0;
if (RRDY)
ROE <= 1;
end
else if (state != 0)
if (transmitting)
SCLK_reg <= ~SCLK_reg;
if (SCLK_reg ^ 0 ^ 0)
begin
if (1)
shift_reg <= {shift_reg[6 : 0], MISO_reg};
end
else
MISO_reg <= ds_MISO;
end
end
end
assign ds_MISO = MISO;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311AI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O311AI_PP_SYMBOL_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o311ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311AI_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SEDFXTP_2_V
`define SKY130_FD_SC_HD__SEDFXTP_2_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog wrapper for sedfxtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sedfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sedfxtp_2 (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sedfxtp_2 (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__SEDFXTP_2_V
|
module sample_multiplexer(
clk,
sample, sample_rdy, sample_req,
data, data_rdy, data_ack
);
input clk;
input [47:0] sample;
input sample_rdy;
output sample_req;
input data_ack;
output [7:0] data;
output data_rdy;
wire [7:0] data;
reg [1:0] state;
reg [2:0] byte_idx;
initial state = 0;
always @(posedge clk)
case (state)
0: // Wait for sample to become available
if (sample_rdy)
begin
state <= 1;
byte_idx <= 0;
end
1: // Request a record from the fifo
state <= 2;
2: // Send bytes
if (data_ack)
begin
if (byte_idx == 3'd5)
state <= 0;
else
byte_idx <= byte_idx + 3'd1;
end
endcase
assign data[7:0] =
(byte_idx == 3'd0) ? sample[47:40] :
(byte_idx == 3'd1) ? sample[39:32] :
(byte_idx == 3'd2) ? sample[31:24] :
(byte_idx == 3'd3) ? sample[23:16] :
(byte_idx == 3'd4) ? sample[15:8] :
(byte_idx == 3'd5) ? sample[7:0] :
8'b0;
assign data_rdy = (state == 2);
assign sample_req = (state == 1);
endmodule
|
module xillybus_core
(
input bus_clk_w,
input [7:0] cfg_bus_number_w,
input [15:0] cfg_dcommand_w,
input [4:0] cfg_device_number_w,
input [15:0] cfg_dstatus_w,
input [2:0] cfg_function_number_w,
input cfg_interrupt_rdy_n_w,
input [15:0] cfg_lcommand_w,
input [63:0] m_axis_rx_tdata_w,
input [7:0] m_axis_rx_tkeep_w,
input m_axis_rx_tlast_w,
input m_axis_rx_tvalid_w,
input s_axis_tx_tready_w,
input [11:0] trn_fc_cpld_w,
input [7:0] trn_fc_cplh_w,
input trn_lnk_up_n_w,
input trn_rerrfwd_n_w,
input trn_reset_n_w,
input trn_terr_drop_n_w,
input [15:0] user_r_control_regs_16_data_w,
input user_r_control_regs_16_empty_w,
input user_r_control_regs_16_eof_w,
input [31:0] user_r_neural_data_32_data_w,
input user_r_neural_data_32_empty_w,
input user_r_neural_data_32_eof_w,
input [15:0] user_r_status_regs_16_data_w,
input user_r_status_regs_16_empty_w,
input user_r_status_regs_16_eof_w,
input user_w_auxcmd1_membank_16_full_w,
input user_w_auxcmd2_membank_16_full_w,
input user_w_auxcmd3_membank_16_full_w,
input user_w_control_regs_16_full_w,
output [3:0] GPIO_LED_w,
output cfg_interrupt_n_w,
output m_axis_rx_tready_w,
output quiesce_w,
output [63:0] s_axis_tx_tdata_w,
output [7:0] s_axis_tx_tkeep_w,
output s_axis_tx_tlast_w,
output s_axis_tx_tvalid_w,
output user_auxcmd1_membank_16_addr_update_w,
output [15:0] user_auxcmd1_membank_16_addr_w,
output user_auxcmd2_membank_16_addr_update_w,
output [15:0] user_auxcmd2_membank_16_addr_w,
output user_auxcmd3_membank_16_addr_update_w,
output [15:0] user_auxcmd3_membank_16_addr_w,
output user_control_regs_16_addr_update_w,
output [4:0] user_control_regs_16_addr_w,
output user_r_control_regs_16_open_w,
output user_r_control_regs_16_rden_w,
output user_r_neural_data_32_open_w,
output user_r_neural_data_32_rden_w,
output user_r_status_regs_16_open_w,
output user_r_status_regs_16_rden_w,
output user_status_regs_16_addr_update_w,
output [4:0] user_status_regs_16_addr_w,
output [15:0] user_w_auxcmd1_membank_16_data_w,
output user_w_auxcmd1_membank_16_open_w,
output user_w_auxcmd1_membank_16_wren_w,
output [15:0] user_w_auxcmd2_membank_16_data_w,
output user_w_auxcmd2_membank_16_open_w,
output user_w_auxcmd2_membank_16_wren_w,
output [15:0] user_w_auxcmd3_membank_16_data_w,
output user_w_auxcmd3_membank_16_open_w,
output user_w_auxcmd3_membank_16_wren_w,
output [15:0] user_w_control_regs_16_data_w,
output user_w_control_regs_16_open_w,
output user_w_control_regs_16_wren_w
);
endmodule
|
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 3
*/
//`include "/auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v"
// Behavioral model for the SIPO convertor
module SIPO(data_out, out_valid, serial_in, in_valid, reset_b, clk);
// Output signals representing the end of the transaction
// Output of the SIPO convertor
output [7:0] data_out;
/**
* Indicate if the data is valid at data_out
* out_valid = 1 when data is valid; it is ZERO otherwise
*/
output out_valid;
// ===============================================================
// Input signals
// Input data bit coming in to the SIPO convertor
input serial_in;
// Clock signal to facilitate state transitions
input clk;
// Active low reset signal to bring all outputs to ZERO
input reset_b;
/**
* Active high flag to enable data to be loaded at the positive
* edge of the clock
*/
input in_valid;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg out_valid; // Output signal
reg [7:0] data_out; // Output signal
// Outputs of the D flip-flops in the SIPO converter
reg [7:0] q_dff; // Output of the D flip-flops
// Flag to indicate if the flip-flops have their outputs set
reg flag1; // flag of the 1st D flip-flop
reg flag2; // flag of the 2nd D flip-flop
reg flag3; // flag of the 3rd D flip-flop
reg flag4; // flag of the 4th D flip-flop
reg flag5; // flag of the 5th D flip-flop
reg flag6; // flag of the 6th D flip-flop
reg flag7; // flag of the 7th D flip-flop
reg flag8; // flag of the 8th D flip-flop
// ===============================================================
// Definitions for the states in the SIPO convertor
// parameter PARAM_NAME = VALUE;
// ===============================================================
// Logic for active low reset signal to reset the SIPO convertor
always @(~reset_b)
begin
// When "reset_b" goes low, out_valid=0
out_valid<=1'd0;
// Set the output of the SIPO convertor to ZERO
data_out<=8'd0;
// Set the output of the D flip-flops to ZERO
q_dff<=8'd0;
// Set the flags for the flip-flops to zero
flag1<=1'd1;
flag2<=1'd1;
flag3<=1'd1;
flag4<=1'd1;
flag5<=1'd1;
flag6<=1'd1;
flag7<=1'd1;
flag8<=1'd1;
end
// ===============================================================
// 1st D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(in_valid && reset_b && (~out_valid))
begin
if(flag1==1)
begin
$display($time,"Process input #1",serial_in);
q_dff[0]<=serial_in;
flag1<=1'd0;
end
end
end
// ===============================================================
// 2nd D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(in_valid && reset_b && (~out_valid))
begin
if((flag2==1) && (flag1==0))
begin
$display($time,"Process input #2",serial_in);
q_dff[1]<=serial_in;
flag2<=1'd0;
end
end
end
// ===============================================================
// 3rd D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(in_valid && reset_b && (~out_valid))
begin
if((flag3==1) && (flag2==0))
begin
$display($time,"Process input #3",serial_in);
q_dff[2]<=serial_in;
flag3<=1'd0;
end
end
end
// ===============================================================
// 4th D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(in_valid && reset_b && (~out_valid))
begin
if((flag4==1) && (flag3==0))
begin
$display($time,"Process input #4",serial_in);
q_dff[3]<=serial_in;
flag4<=1'd0;
end
end
end
// ===============================================================
// 5th D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(in_valid && reset_b && (~out_valid))
begin
if((flag5==1) && (flag4==0))
begin
$display($time,"Process input #5",serial_in);
q_dff[4]<=serial_in;
flag5<=1'd0;
end
end
end
// ===============================================================
// 6th D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(in_valid && reset_b && (~out_valid))
begin
if((flag6==1) && (flag5==0))
begin
$display($time,"Process input #6",serial_in);
q_dff[5]<=serial_in;
flag6<=1'd0;
end
end
end
// ===============================================================
// 7th D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(in_valid && reset_b && (~out_valid))
begin
if((flag7==1) && (flag6==0))
begin
$display($time,"Process input #7",serial_in);
q_dff[6]<=serial_in;
flag7<=1'd0;
end
end
end
// ===============================================================
// 8th/Final/Last D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(in_valid && reset_b && (~out_valid))
begin
if((flag8==1) && (flag7==0))
begin
$display($time,"Process input #8",serial_in);
q_dff[7]<=serial_in;
flag8<=1'd0;
out_valid<=1'd1;
end
end
else if(out_valid)
begin
$display($time,"Produce the output and reset data",serial_in);
data_out<=q_dff;
flag1<=1'd1;
flag2<=1'd1;
flag3<=1'd1;
flag4<=1'd1;
flag5<=1'd1;
flag6<=1'd1;
flag7<=1'd1;
flag8<=1'd1;
out_valid<=1'd0;
q_dff<=8'd0;
end
end
endmodule
|
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)me_cells.v
***
****************************************************************************
****************************************************************************/
/*
PRIMATIVES
Latches
Combinational logic gates
Multiplexors
Pads
Clock buffers
MACROS -- use seperate file macros.v
Registers
Wide multiplexors
Bus drivers
Shifters
Alus
Adders
Rams
Roms
*/
/* Latches
ME_LD1 simple d latch, active LOW clock
ME_FD1 fimple ff active on positive clock edge
ME_FD1E FD2 with a data load enable
ME_FD1E2 FD2 with two data inputs, each with is own enable.
FJK1 JK flip flop, pos edge load.
FJK2 JK flip flop, pos edge load, with active low clear.
*/
/* logic Gates
NAND{n} n input nand gate
NOR{n} n input nor gate
AND{n} n input and gate
OR{n} n input or gate
ME_INVA invertor
ME_BUFF buffer
ME_DELBUFF buffer with approx 3ns delay
ME_TSBUFF tristate buffer
ME_XOR2 2 input xor gate
ME_XNOR2 2 input xnor
ME_ADD2 half adder
ME_ADD3 full adder
*/
/* Matrix Gates
ME_AnOmI And-Or-Invert gates
ME_OnAmI Or-And-Invert gates
*/
/* Multiplexors/selectors
MUX{n} n input multiplexor with seperate selectors
NMUX{n} n input inverting multiplexor with seperate selectors
MUX{n)B binary coded selectors.
NMUX{n)B binary coded selectors, inverting
ME_NMUX2BA as NMUX2B except you must supply true and false of control inputs
*/
/* Pads */
/* MACROS */
/* registers
DREG_{x}_{y} x bit wide register with y inputs. transparent when clock high
FREG_{x}_{y} x bit wide register with y inputs. edge trigger on posedge strobe
MUX_{x}_{y} x bit wide multiplexor with y inputs
*/
/* function blocks
ALU_{x} x bit wide ALU
ME_ADD_{x} x bit wide add/subtract
*/
/* roms and roms
ME_ROM_{x}_{y} x bit wide rom with y address bits
ME_RAM_{x}_{y} x bit wide ram with y address bits
ME_RAM3_{x}_{y} x bit wide 3 port ram with y address bits
*/
/* Actual modules */
module ME_FD1 (cp, d, q, qn);
input d, cp;
output q, qn ;
// N1Z000 gnd(GND);
// ASFFA dff (.Q(q), .XQ(qn), .D(d), .SM(GND), .SI(GND), .CK(cp));
Mflipflop_noop dff (.out(q), .in(d), .clock(cp) );
assign qn = ~q;
endmodule
module ME_FD1_B (cp, d, q, qn);
input d, cp;
output q, qn ;
// N1Z000 gnd(GND);
// ASFFA dff (.Q(q), .XQ(qn), .D(d), .SM(GND), .SI(GND), .CK(cp));
Mflipflop_noop dff (.out(q), .in(d), .clock(cp) );
assign qn = ~q;
endmodule
module ME_FD1P (cp, d, q, qn); // should be a high drive version of ME_FD1;
input d, cp; // for simulation, they are the same.
output q, qn ;
// N1Z000 gnd(GND);
// ASFFA dff (.Q(q), .XQ(qn), .D(d), .SM(GND), .SI(GND), .CK(cp));
Mflipflop_noop dff (.out(q), .in(d), .clock(cp) );
assign qn = ~q;
endmodule
module ME_FDS2LP (d, cp, cr, ld, q, qn);
// ld is active high, cr is active low
input d, cp, cr, ld;
output q, qn;
// N1Z000 gnd(GND);
// wire hold;
// JINVA i0 ( .O(hold), .A(ld) );
// ASFFRHA dff ( .Q(q), .XQ(qn), .D(d), .SM(GND), .SI(GND),
// .H(hold), .R(cr), .CK(cp) ) ;
wire load_l;
assign load_l = ~ld;
Mflipflop_rh dff (.out(q), .in(d), .enable_l(load_l), .reset_l(cr), .clock(cp));
assign qn = ~q;
endmodule
module ME_FD1E (cp, te, d, q, qn);
// like FD1 but with enable
// note enable is active high
input d, cp, te;
output q, qn ;
// N1Z000 gnd(GND);
// wire hold;
// JINVA i0 ( .O(hold), .A(te) );
// ASFFHA dff ( .Q(q), .XQ(qn), .D(d), .SM(GND), .SI(GND),
// .H(hold), .CK(cp)) ;
wire load_l;
assign load_l = ~te;
Mflipflop dff (.out(q), .in(d), .clock(cp), .enable_l(load_l));
assign qn = ~q;
endmodule
module ME_FD1E_B (cp, te, d, q, qn);
// like FD1 but with enable
// note enable is active high
input d, cp, te;
output q, qn ;
// N1Z000 gnd(GND);
// wire hold;
// JINVA i0 ( .O(hold), .A(te) );
// ASFFHA dff ( .Q(q), .XQ(qn), .D(d), .SM(GND), .SI(GND),
// .H(hold), .CK(cp)) ;
wire load_l;
assign load_l = ~te;
Mflipflop dff (.out(q), .in(d), .clock(cp), .enable_l(load_l));
assign qn = ~q;
endmodule
module ME_FD1R (d, cp, cr, q, qn);
// CR (reset) is active low
input d, cp, cr;
output q, qn;
// N1Z000 gnd(GND);
// ASFFRA dff ( .Q(q), .XQ(qn), .D(d), .SM(GND), .SI(GND),
// .R(cr), .CK(cp) ) ;
Mflipflop_r dff (.out(q), .in(d), .reset_l(cr), .clock(cp));
assign qn = ~q;
endmodule
// Logic Gates
module ME_INV_A (a, x); // Meanest gate
input a;
output x;
JINVA i (.O(x), .A(a) );
endmodule
module ME_INVA (a, x);
input a;
output x;
JINVA i (.O(x), .A(a) );
endmodule
module ME_INV_B (a, x);
input a;
output x;
JINVB i (.O(x), .A(a) );
endmodule
module ME_INV_C (a, x);
input a;
output x;
JINVC i (.O(x), .A(a) );
endmodule
module ME_INV_D (a, x);
input a;
output x;
JINVD i (.O(x), .A(a) );
endmodule
module ME_INV_A_10 (A, Z);
input [9:0] A;
output [9:0] Z;
JINVA g0 (.O(Z[0]), .A(A[0]) );
JINVA g1 (.O(Z[1]), .A(A[1]) );
JINVA g2 (.O(Z[2]), .A(A[2]) );
JINVA g3 (.O(Z[3]), .A(A[3]) );
JINVA g4 (.O(Z[4]), .A(A[4]) );
JINVA g5 (.O(Z[5]), .A(A[5]) );
JINVA g6 (.O(Z[6]), .A(A[6]) );
JINVA g7 (.O(Z[7]), .A(A[7]) );
JINVA g8 (.O(Z[8]), .A(A[8]) );
JINVA g9 (.O(Z[9]), .A(A[9]) );
endmodule
module ME_INV_A_58 (A, Z);
input [57:0] A;
output [57:0] Z;
ME_INV_A_10 h0 (A[9:0], Z[9:0]);
ME_INV_A_10 h2 (A[19:10], Z[19:10]);
ME_INV_A_10 h3 (A[29:20], Z[29:20]);
ME_INV_A_10 h4 (A[39:30], Z[39:30]);
ME_INV_A_10 h5 (A[49:40], Z[49:40]);
ME_INV_A g0 (A[50], Z[50]);
ME_INV_A g1 (A[51], Z[51]);
ME_INV_A g2 (A[52], Z[52]);
ME_INV_A g3 (A[53], Z[53]);
ME_INV_A g4 (A[54], Z[54]);
ME_INV_A g5 (A[55], Z[55]);
ME_INV_A g6 (A[56], Z[56]);
ME_INV_A g7 (A[57], Z[57]);
endmodule
module ME_BUFF (a, x);
input a;
output x;
JBUFC i (.O(x), .A(a) );
endmodule
module ME_BUF_B (a, x); // Same as ME_BUFF
input a;
output x;
JBUFD i (.O(x), .A(a) );
endmodule
module ME_BUF_C (a, x); // Same as ME_BUFF
input a;
output x;
JBUFD i (.O(x), .A(a) );
endmodule
module ME_BUF_D (a, x); // Same as ME_BUFF
input a;
output x;
JBUFE i (.O(x), .A(a) );
endmodule
module ME_BUF3_4 ( a, x );
input [3:0] a;
output [3:0] x;
ME_BUF_C i0 (a[0], x[0]);
ME_BUF_C i1 (a[1], x[1]);
ME_BUF_C i2 (a[2], x[2]);
ME_BUF_C i3 (a[3], x[3]);
endmodule
module ME_BUF32_C ( a, x );
input [31:0] a;
output [31:0] x;
JBUFC i0 (.O(x[0]), .A(a[0]) );
JBUFC i1 (.O(x[1]), .A(a[1]) );
JBUFC i2 (.O(x[2]), .A(a[2]) );
JBUFC i3 (.O(x[3]), .A(a[3]) );
JBUFC i4 (.O(x[4]), .A(a[4]) );
JBUFC i5 (.O(x[5]), .A(a[5]) );
JBUFC i6 (.O(x[6]), .A(a[6]) );
JBUFC i7 (.O(x[7]), .A(a[7]) );
JBUFC i8 (.O(x[8]), .A(a[8]) );
JBUFC i9 (.O(x[9]), .A(a[9]) );
JBUFC i10 (.O(x[10]), .A(a[10]) );
JBUFC i11 (.O(x[11]), .A(a[11]) );
JBUFC i12 (.O(x[12]), .A(a[12]) );
JBUFC i13 (.O(x[13]), .A(a[13]) );
JBUFC i14 (.O(x[14]), .A(a[14]) );
JBUFC i15 (.O(x[15]), .A(a[15]) );
JBUFC i16 (.O(x[16]), .A(a[16]) );
JBUFC i17 (.O(x[17]), .A(a[17]) );
JBUFC i18 (.O(x[18]), .A(a[18]) );
JBUFC i19 (.O(x[19]), .A(a[19]) );
JBUFC i20 (.O(x[20]), .A(a[20]) );
JBUFC i21 (.O(x[21]), .A(a[21]) );
JBUFC i22 (.O(x[22]), .A(a[22]) );
JBUFC i23 (.O(x[23]), .A(a[23]) );
JBUFC i24 (.O(x[24]), .A(a[24]) );
JBUFC i25 (.O(x[25]), .A(a[25]) );
JBUFC i26 (.O(x[26]), .A(a[26]) );
JBUFC i27 (.O(x[27]), .A(a[27]) );
JBUFC i28 (.O(x[28]), .A(a[28]) );
JBUFC i29 (.O(x[29]), .A(a[29]) );
JBUFC i30 (.O(x[30]), .A(a[30]) );
JBUFC i31 (.O(x[31]), .A(a[31]) );
endmodule
module ME_NAND2 (a, b, z);
input a, b;
output z;
JNAND2A i (.O(z), .A1(a), .A2(b) );
endmodule
module ME_NAND2_B (a, b, z);
input a, b;
output z;
JNAND2B i (.O(z), .A1(a), .A2(b) );
endmodule
module ME_NAND3 (a, b, c, z);
input a, b, c;
output z ;
JNAND3A i (.O(z), .A1(a), .A2(b), .A3(c) );
endmodule
module ME_NAND3_B (a, b, c, z);
input a, b, c;
output z ;
JNAND3B i (.O(z), .A1(a), .A2(b), .A3(c) );
endmodule
module ME_NAND4 (a, b, c, d, z);
input a, b, c, d;
output z ;
JNAND4A i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d) );
endmodule
module ME_NAND5 (a, b, c, d, e, z);
input a, b, c, d, e;
output z ;
ANAND5C i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e) );
endmodule
module ME_NAND6_B (a, b, c, d, e, f, z);
input a, b, c, d, e, f;
output z ;
JNAND6C i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f) );
endmodule
module ME_NAND8 (a, b, c, d, e, f, g, h, z);
input a, b, c, d, e, f, g, h ;
output z ;
JNAND8C i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f),
.A7(g), .A8(h) );
endmodule
module ME_NAND8_B (a, b, c, d, e, f, g, h, z);
input a, b, c, d, e, f, g, h ;
output z ;
JNAND8C i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f),
.A7(g), .A8(h) );
endmodule
// AND gates
module ME_AND2 (a, b, z);
input a, b;
output z;
JAND2B i (.O(z), .A1(a), .A2(b) );
endmodule
module ME_AND2_B (a, b, z);
input a, b;
output z;
JAND2B i (.O(z), .A1(a), .A2(b) );
endmodule
module ME_AND3 (a, b, c, z);
input a, b, c;
output z;
JAND3B i (.O(z), .A1(a), .A2(b), .A3(c) );
endmodule
module ME_AND3_B (a, b, c, z);
input a, b, c;
output z;
JAND3B i (.O(z), .A1(a), .A2(b), .A3(c) );
endmodule
module ME_AND4 (a, b, c, d, z);
input a, b, c, d;
output z;
JAND4B i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d) );
endmodule
module ME_AND4_B (a, b, c, d, z);
input a, b, c, d;
output z;
JAND4B i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d) );
endmodule
module ME_AND7 ( a1, a2, a3, a4, a5, a6, a7, z );
input a1, a2, a3, a4, a5, a6, a7 ;
output z ;
wire x1, x2;
JNAND3A i0 (.O(x1), .A1(a1), .A2(a2), .A3(a3) );
JNAND4A i1 (.O(x2), .A1(a4), .A2(a5), .A3(a6), .A4(a7) );
JNOR2A i2 (.O(z), .A1(x1), .A2(x2) );
endmodule
module ME_AND8 (a, b, c, d, e, f, g, h, z);
input a, b, c, d, e, f, g, h ;
output z ;
JAND8B i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f),
.A7(g), .A8(h) );
endmodule
// nor gates
module ME_NOR2 (a, b, z);
input a, b ;
output z;
JNOR2A i (.O(z), .A1(a), .A2(b) );
endmodule
module ME_NOR2_B (a, b, z);
input a, b ;
output z;
JNOR2C i (.O(z), .A1(a), .A2(b) );
endmodule
module ME_NOR2_D (a, b, z);
input a, b ;
output z;
JNOR2D i (.O(z), .A1(a), .A2(b) );
endmodule
module ME_NOR3 (a, b, c, z);
input a, b, c ;
output z;
JNOR3C i (.O(z), .A1(a), .A2(b), .A3(c) );
endmodule
module ME_NOR4 (a, b, c, d, z);
input a, b, c, d ;
output z;
JNOR4B i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d) );
endmodule
module ME_NOR6_B (a, b, c, d, e, f, z);
input a, b, c, d, e, f ;
output z;
JNOR6C i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f) );
endmodule
module ME_OR2 (a, b, z);
input a, b ;
output z;
JOR2B i (.O(z), .A1(a), .A2(b) );
endmodule
module ME_OR2_B (a, b, z);
input a, b ;
output z;
JOR2B i (.O(z), .A1(a), .A2(b) );
endmodule
module ME_OR3 (a, b, c, z);
input a, b, c ;
output z;
JOR3B i (.O(z), .A1(a), .A2(b), .A3(c) );
endmodule
module ME_OR3_B (a, b, c, z);
input a, b, c ;
output z;
JOR3B i (.O(z), .A1(a), .A2(b), .A3(c) );
endmodule
module ME_OR4 (a, b, c, d, z);
input a, b, c, d ;
output z;
JOR4B i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d) );
endmodule
module ME_OR6 (a, b, c, d, e, f, X);
input a, b, c, d, e, f ;
output X ;
JOR6B i (.O(X), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f) );
endmodule
module ME_OR8 (a, b, c, d, e, f, g, h, X);
input a, b, c, d, e, f, g, h ;
output X ;
JOR8B i (.O(X), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f),
.A7(g), .A8(h) );
endmodule
module ME_OR11 (a, b, c, d, e, f, g, h, i, j, k, X);
input a, b, c, d, e, f, g, h, i, j, k;
output X ;
wire x0, x1;
JNOR8C u0 (.O(x0), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f),
.A7(g), .A8(h) );
JNOR3A u1 (.O(x1), .A1(i), .A2(j), .A3(k) );
JNAND2A u2 (.O(X), .A1(x0), .A2(x1) );
endmodule
module ME_OR12 (a, b, c, d, e, f, g, h, i, j, k, l, X);
input a, b, c, d, e, f, g, h, i, j, k, l;
output X ;
wire x0, x1;
JNOR8C u0 (.O(x0), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f),
.A7(g), .A8(h) );
JNOR4B u1 (.O(x1), .A1(i), .A2(j), .A3(k), .A4(l) );
JNAND2A u2 (.O(X), .A1(x0), .A2(x1) );
endmodule
module ME_XNOR2 (a, b, z);
input a, b;
output z;
JXNOR2A i (.O(z), .A1(a), .A2(b) );
endmodule
module ME_XNOR2_B (a, b, z);
input a, b;
output z;
JXNOR2B i (.O(z), .A1(a), .A2(b) );
endmodule
module ME_XOR2 (a, b, z);
input a, b;
output z;
JXOR2A i (.O(z), .A1(a), .A2(b) );
endmodule
module ME_XOR2_B (a, b, z);
input a, b;
output z;
JXOR2B i (.O(z), .A1(a), .A2(b) );
endmodule
module ME_XOR3_B (a, b, c, z);
input a, b, c;
output z;
JXOR3A i (.O(z), .A1(a), .A2(b), .A3(c) );
endmodule
// Matrix gates
module ME_A2O1_B (a, b, c, z); // z = (a&b) | c
input a, b, c;
output z;
JDB21A i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule
module ME_AI2O1_C (a, b, c, z); // z = (a & ~b) | c
input a, b, c;
output z;
ADBI21C i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule
module ME_AI2O1_D (a, b, c, z); // z = (a & ~b) | c
input a, b, c;
output z;
ADBI21D i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule
module ME_A22O1_B (a1, a2, b1, b2, c, z); // z = (a1&a2) | (b1&b2) | c;
input a1, a2, b1, b2, c;
output z;
JDB122A i (.O(z), .A1(a1), .A2(a2), .B1(b1), .B2(b2), .C(c) );
endmodule
module ME_AI22O1_C (a1, a2, b1, b2, c, z); // z= (a1 & ~a2) | (b1&b2) | c;
input a1, a2, b1, b2, c;
output z;
ADBI122C i (.O(z), .A1(a1), .A2(a2), .B1(b1), .B2(b2), .C(c) );
endmodule
module ME_AI22O1_D (a1, a2, b1, b2, c, z); // z= (a1 & ~a2) | (b1&b2) | c;
input a1, a2, b1, b2, c;
output z;
ADBI122D i (.O(z), .A1(a1), .A2(a2), .B1(b1), .B2(b2), .C(c) );
endmodule
module ME_AI22O1_C_2 (a1, a2, b1, b2, c, z);
input [1:0] a1, a2, b1, b2, c;
output [1:0] z;
ADBI122C u0 (.O(z[0]), .A1(a1[0]), .A2(a2[0]), .B1(b1[0]), .B2(b2[0]),
.C(c[0]) );
ADBI122C u1 (.O(z[1]), .A1(a1[1]), .A2(a2[1]), .B1(b1[1]), .B2(b2[1]),
.C(c[1]) );
endmodule
module ME_AI22O1_C_5 (a1, a2, b1, b2, c, z);
input [4:0] a1, a2, b1, b2, c;
output [4:0] z;
ADBI122C u0 (.O(z[0]), .A1(a1[0]), .A2(a2[0]), .B1(b1[0]), .B2(b2[0]),
.C(c[0]) );
ADBI122C u1 (.O(z[1]), .A1(a1[1]), .A2(a2[1]), .B1(b1[1]), .B2(b2[1]),
.C(c[1]) );
ADBI122C u2 (.O(z[2]), .A1(a1[2]), .A2(a2[2]), .B1(b1[2]), .B2(b2[2]),
.C(c[2]) );
ADBI122C u3 (.O(z[3]), .A1(a1[3]), .A2(a2[3]), .B1(b1[3]), .B2(b2[3]),
.C(c[3]) );
ADBI122C u4 (.O(z[4]), .A1(a1[4]), .A2(a2[4]), .B1(b1[4]), .B2(b2[4]),
.C(c[4]) );
endmodule
module ME_A2O2I (a, b, c, d, z);
input a, b, c, d;
output z;
JD211A u1 (.O(z), .A1(a), .A2(b), .B1(c), .B2(d) );
endmodule
module ME_A2O2I_B (a, b, c, d, z);
input a, b, c, d;
output z;
JD211A u1 (.O(z), .A1(a), .A2(b), .B1(c), .B2(d) );
endmodule
module ME_A22OI (a, b, c, d, z);
input a, b, c, d;
output z;
JD22A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d) );
endmodule
module ME_A22OI_B (a, b, c, d, z);
input a, b, c, d;
output z;
JD22A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d) );
endmodule
module ME_O2A2I (a, b, c, d, z);
input a, b, c, d;
output z;
JG112A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d) );
endmodule
module ME_O2A2I_B (a, b, c, d, z);
input a, b, c, d;
output z;
JG112A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d) );
endmodule
module ME_O22AI (a, b, c, d, z);
input a, b, c, d;
output z;
JG22A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d) );
endmodule
module ME_O22AI_B (a, b, c, d, z);
input a, b, c, d;
output z;
JG22A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d) );
endmodule
module ME_A2O1I (a, b, c, z);
input a, b, c;
output z;
JD21A i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule
module ME_A2O1I_B (a, b, c, z);
input a, b, c;
output z;
JD21A i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule
module ME_O2A1 (a, b, c, z);
input a, b, c;
output z; // z = (a|b)&c
JGB12A i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule
module ME_O2A1_D (a, b, c, z);
input a, b, c;
output z; // z = (a|b)&c
AGB12D i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule
module ME_O22A1 (a1, a2, b1, b2, c, z);
input a1, a2, b1, b2, c;
output z; // z = (a1 | a2) & (b1 | b2) & c
JGB221A i (.O(z), .A1(a1), .A2(a2), .B1(b1), .B2(b2), .C(c) );
endmodule
module ME_O2A1I (a, b, c, z);
input a, b, c;
output z;
JG12A i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule
module ME_O2A1I_B (a, b, c, z);
input a, b, c;
output z;
JG12A i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule
module ME_A222OI (a, b, c, d, e, f, z);
input a, b, c, d, e, f;
output z;
JD222A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d), .C1(e), .C2(f) );
endmodule
module ME_A222OI_B (a, b, c, d, e, f, z);
input a, b, c, d, e, f;
output z;
JD222A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d), .C1(e), .C2(f) );
endmodule
module ME_O2222AI (a, b, c, d, e, f, g, h, z);
input a, b, c, d, e, f, g, h;
output z;
AG2222A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d), .C1(e), .C2(f),
.D1(g), .D2(h) );
endmodule
module ME_O2222AI_B (a, b, c, d, e, f, g, h, z);
input a, b, c, d, e, f, g, h;
output z;
AG2222A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d), .C1(e), .C2(f),
.D1(g), .D2(h) );
endmodule
module ME_ADD2 (a, b, s, c);
input a, b;
output s,c;
JHAD1A u0 (.CO(c), .S(s), .A(a), .B(b) );
endmodule
module ME_ADD3 (a, b, ci, s, co);
input a, b, ci ;
output s, co ;
JFAD1A u0 (.CO(co), .S(s), .A(a), .B(b), .CI(ci) );
endmodule
module ME_ADD3_B (a, b, ci, s, co);
input a, b, ci ;
output s, co ;
JFAD1A u0 (.CO(co), .S(s), .A(a), .B(b), .CI(ci) );
endmodule
// comparators
module ME_COMP3 (a, b, z);
input [2:0] a, b;
output z;
ACOMP3A u0 (.A0(a[0]), .A1(a[1]), .A2(a[2]),
.B0(b[0]), .B1(b[1]), .B2(b[2]), .O(z) );
endmodule
module ME_COMP4 (a, b, z);
input [3:0] a, b;
output z;
ACOMP4A u0 (.A0(a[0]), .A1(a[1]), .A2(a[2]), .A3(a[3]),
.B0(b[0]), .B1(b[1]), .B2(b[2]), .B3(b[3]), .O(z) );
endmodule
module ME_COMP5 (a, b, z);
input [4:0] a, b;
output z;
ACOMP5A u0 (.A0(a[0]), .A1(a[1]), .A2(a[2]), .A3(a[3]), .A4(a[4]),
.B0(b[0]), .B1(b[1]), .B2(b[2]), .B3(b[3]), .B4(b[4]), .O(z) );
endmodule
// multiplexors
// Binary encoded muxes
module ME_MUX2B (s, a, b, z);
input s, a, b ;
output z ;
AMUX2A u0 (.O(z), .A(a), .B(b), .S(s) );
endmodule
module ME_MUX2B_B (s, a, b, z);
input s, a, b ;
output z ;
AMUX2A u0 (.O(z), .A(a), .B(b), .S(s) );
endmodule
module ME_NMUX2B (s, a, b, z); // inverting mux
input s, a, b ;
output z ;
JMUX2A u0 (.O(z), .A(a), .B(b), .S(s) );
endmodule
module ME_NMUX2B_B (s, a, b, z); // inverting mux
input s, a, b ;
output z ;
JMUX2A u0 (.O(z), .A(a), .B(b), .S(s) );
endmodule
module ME_NMUX2BA (nota, a, d0, d1, notX);
// A very important special case
// use with care as A being on at the same time as notA burns power.
// note the order of the inputs which is choosen so that this is compatable
// with an NMUX2 although the behaviour is only the same if both a driven
// from true and inverse of a signal
input a, nota, d0, d1 ;
output notX ;
JD22A i (.O(notX), .A1(nota), .A2(d0), .B1(a), .B2(d1) );
endmodule
module ME_NMUX2BA_B (nota, a, d0, d1, notX);
// A very important special case
// use with care as A being on at the same time as notA burns power.
// note the order of the inputs which is choosen so that this is compatable
// with an NMUX2 although the behaviour is only the same if both a driven
// from true and inverse of a signal
input a, nota, d0, d1 ;
output notX ;
JD22A i (.O(notX), .A1(nota), .A2(d0), .B1(a), .B2(d1) );
endmodule
module ME_MUX4B (a, b, d0, d1, d2, d3, z);
input a, b, d0, d1, d2, d3 ;
output z ;
// note A is least significant select line.
// A B Selected
// 00 d0
// 10 d1
// 01 d2
// 11 d3
AMUX4A m0 (.S0(a), .S1(b), .I1(d0), .I2(d1), .I3(d2), .I4(d3), .O(z) );
endmodule
module ME_MUX4B_B (a, b, d0, d1, d2, d3, z);
input a, b, d0, d1, d2, d3 ;
output z ;
// note A is least significant select line.
// A B Selected
// 00 d0
// 10 d1
// 01 d2
// 11 d3
AMUX4A m0 (.S0(a), .S1(b), .I1(d0), .I2(d1), .I3(d2), .I4(d3), .O(z) );
endmodule
module ME_NMUX5B (A, B, C, D0, D1, D2, D3, D4, notXout);
input A, B, C, D0, D1, D2, D3, D4 ;
output notXout ;
// note A is least significant select line.
// A B C Selected
// 000 d0
// 100 d1
// 010 d2
// 110 d3
// ??1 d4
ME_MUX4B m2 (A, B, D0, D1, D2, D3, T0);
ME_NMUX2B m1 (C, T0, D4, notXout) ;
endmodule
module ME_MUX8B (a, b, c, d0, d1, d2, d3, d4, d5, d6, d7, f);
input a, b, c, d0, d1, d2, d3, d4, d5, d6, d7 ;
output f ;
// note A is least significant select line.
ME_MUX4B m0 (a, b, d0, d1, d2, d3, z0);
ME_MUX4B m1 (a, b, d4, d5, d6, d7, z1);
ME_MUX2B m2 (c, z0, z1, f);
endmodule
module ME_MUX8B_B (a, b, c, d0, d1, d2, d3, d4, d5, d6, d7, f);
input a, b, c, d0, d1, d2, d3, d4, d5, d6, d7 ;
output f ;
// note A is least significant select line.
ME_MUX4B_B m0 (a, b, d0, d1, d2, d3, z0);
ME_MUX4B_B m1 (a, b, d4, d5, d6, d7, z1);
ME_MUX2B_B m2 (c, z0, z1, f);
endmodule
module ME_MUX_2Bbit ( notA, A, D0, D1, Xout ) ;
input notA, A;
input D0, D1;
output Xout;
JDB22A g0 ( .A1(notA), .A2(D0), .B1(A), .B2(D1), .O(Xout) );
endmodule
module ME_MUX_2B_Bbit ( notA, A, D0, D1, Xout ) ;
input notA, A;
input D0, D1;
output Xout;
JDB22A g0 ( .A1(notA), .A2(D0), .B1(A), .B2(D1), .O(Xout) );
endmodule
module ME_NMUX_2Bbit ( notA, A, D0, D1, Xout ) ;
input notA, A;
input D0, D1;
output Xout;
ME_NMUX2BA_B g0 ( .nota(notA), .a(A), .d0(D0), .d1(D1), .notX(Xout) );
endmodule
module ME_MUX_2B_Bbyte ( notA, A, D0, D1, Xout ) ;
input notA, A;
input [7:0] D0, D1;
output [7:0] Xout;
ME_MUX_2B_Bbit g10 ( notA, A, D0[0], D1[0], Xout[0] );
ME_MUX_2B_Bbit g11 ( notA, A, D0[1], D1[1], Xout[1] );
ME_MUX_2B_Bbit g12 ( notA, A, D0[2], D1[2], Xout[2] );
ME_MUX_2B_Bbit g13 ( notA, A, D0[3], D1[3], Xout[3] );
ME_MUX_2B_Bbit g14 ( notA, A, D0[4], D1[4], Xout[4] );
ME_MUX_2B_Bbit g15 ( notA, A, D0[5], D1[5], Xout[5] );
ME_MUX_2B_Bbit g16 ( notA, A, D0[6], D1[6], Xout[6] );
ME_MUX_2B_Bbit g17 ( notA, A, D0[7], D1[7], Xout[7] );
endmodule
module ME_MUX_2Bbyte ( notA, A, D0, D1, Xout ) ;
input notA, A;
input [7:0] D0, D1;
output [7:0] Xout;
ME_MUX_2Bbit g10 ( notA, A, D0[0], D1[0], Xout[0] );
ME_MUX_2Bbit g11 ( notA, A, D0[1], D1[1], Xout[1] );
ME_MUX_2Bbit g12 ( notA, A, D0[2], D1[2], Xout[2] );
ME_MUX_2Bbit g13 ( notA, A, D0[3], D1[3], Xout[3] );
ME_MUX_2Bbit g14 ( notA, A, D0[4], D1[4], Xout[4] );
ME_MUX_2Bbit g15 ( notA, A, D0[5], D1[5], Xout[5] );
ME_MUX_2Bbit g16 ( notA, A, D0[6], D1[6], Xout[6] );
ME_MUX_2Bbit g17 ( notA, A, D0[7], D1[7], Xout[7] );
endmodule
module ME_NMUX_2Bbyte ( notA, A, D0, D1, Xout ) ;
input notA, A;
input [7:0] D0, D1;
output [7:0] Xout;
ME_NMUX_2Bbit g10 ( notA, A, D0[0], D1[0], Xout[0] );
ME_NMUX_2Bbit g11 ( notA, A, D0[1], D1[1], Xout[1] );
ME_NMUX_2Bbit g12 ( notA, A, D0[2], D1[2], Xout[2] );
ME_NMUX_2Bbit g13 ( notA, A, D0[3], D1[3], Xout[3] );
ME_NMUX_2Bbit g14 ( notA, A, D0[4], D1[4], Xout[4] );
ME_NMUX_2Bbit g15 ( notA, A, D0[5], D1[5], Xout[5] );
ME_NMUX_2Bbit g16 ( notA, A, D0[6], D1[6], Xout[6] );
ME_NMUX_2Bbit g17 ( notA, A, D0[7], D1[7], Xout[7] );
endmodule
module ME_NMUX_2B_8 (A, D0, D1, Xout);
input A ;
input [7:0] D0, D1 ;
output [7:0] Xout ;
ME_INV_B g10 ( A, notA1 ) ;
ME_INV_B g11 ( notA1, Abuf ) ;
ME_INV_B g12 ( A, notAbuf ) ;
ME_NMUX_2Bbyte m13 ( notAbuf, Abuf, D0[7:0], D1[7:0], Xout[7:0] ) ;
endmodule
module ME_MUX_2B_32 ( A, D0, D1, Xout );
input A ;
input [31:0] D0, D1 ;
output [31:0] Xout ;
ME_INV_B g10 ( A, _A ) ;
ME_INV_C g11 ( _A, buffA ) ;
ME_INV_C g12 ( A, notA ) ;
ME_MUX_2Bbyte m10 ( notA, buffA, D0[7:0], D1[7:0], Xout[7:0] ) ;
ME_MUX_2Bbyte m11 ( notA, buffA, D0[15:8], D1[15:8], Xout[15:8] ) ;
ME_MUX_2Bbyte m12 ( notA, buffA, D0[23:16], D1[23:16], Xout[23:16] ) ;
ME_MUX_2Bbyte m13 ( notA, buffA, D0[31:24], D1[31:24], Xout[31:24] ) ;
endmodule
module ME_MUX_2B_52 ( A, D0, D1, Xout );
input A ;
input [51:0] D0, D1 ;
output [51:0] Xout ;
ME_INV_B g10 ( A, _A ) ;
ME_INV_C g11 ( _A, buffA ) ;
ME_INV_C g12 ( A, notA ) ;
ME_MUX_2Bbyte m10 ( notA, buffA, D0[7:0], D1[7:0], Xout[7:0] ) ;
ME_MUX_2Bbyte m11 ( notA, buffA, D0[15:8], D1[15:8], Xout[15:8] ) ;
ME_MUX_2Bbyte m12 ( notA, buffA, D0[23:16], D1[23:16], Xout[23:16] ) ;
ME_MUX_2Bbyte m13 ( notA, buffA, D0[31:24], D1[31:24], Xout[31:24] ) ;
ME_MUX_2Bbyte m14 ( notA, buffA, D0[39:32], D1[39:32], Xout[39:32] ) ;
ME_MUX_2Bbyte m15 ( notA, buffA, D0[47:40], D1[47:40], Xout[47:40] ) ;
ME_MUX_2Bbit m16 ( notA, buffA, D0[48], D1[48], Xout[48] ) ;
ME_MUX_2Bbit m17 ( notA, buffA, D0[49], D1[49], Xout[49] ) ;
ME_MUX_2Bbit m18 ( notA, buffA, D0[50], D1[50], Xout[50] ) ;
ME_MUX_2Bbit m19 ( notA, buffA, D0[51], D1[51], Xout[51] ) ;
endmodule
module ME_MUX_2B_4 ( A, D0, D1, Xout );
input A ;
input [3:0] D0, D1 ;
output [3:0] Xout ;
ME_BUFF g10 ( A, buffA ) ;
ME_INV_B g11 ( A, notA ) ;
ME_MUX_2Bbit m10 ( notA, buffA, D0[0], D1[0], Xout[0] ) ;
ME_MUX_2Bbit m11 ( notA, buffA, D0[1], D1[1], Xout[1] ) ;
ME_MUX_2Bbit m12 ( notA, buffA, D0[2], D1[2], Xout[2] ) ;
ME_MUX_2Bbit m13 ( notA, buffA, D0[3], D1[3], Xout[3] ) ;
endmodule
module ME_MUX_2B_3 ( A, D0, D1, Xout );
input A ;
input [2:0] D0, D1 ;
output [2:0] Xout ;
ME_BUFF g10 ( A, buffA ) ;
ME_INV_B g11 ( A, notA ) ;
ME_MUX_2Bbit m10 ( notA, buffA, D0[0], D1[0], Xout[0] ) ;
ME_MUX_2Bbit m11 ( notA, buffA, D0[1], D1[1], Xout[1] ) ;
ME_MUX_2Bbit m12 ( notA, buffA, D0[2], D1[2], Xout[2] ) ;
endmodule
module ME_MUX_2B_2 ( A, D0, D1, Xout );
input A ;
input [1:0] D0, D1 ;
output [1:0] Xout ;
ME_BUFF g10 ( A, buffA ) ;
ME_INV_B g11 ( A, notA ) ;
ME_MUX_2Bbit m10 ( notA, buffA, D0[0], D1[0], Xout[0] ) ;
ME_MUX_2Bbit m11 ( notA, buffA, D0[1], D1[1], Xout[1] ) ;
endmodule
module ME_MUX_2B_B_58 ( A, D0, D1, Xout );
input A ;
input [57:0] D0, D1 ;
output [57:0] Xout ;
ME_INV_B g10 ( A, _A ) ;
ME_INV_C g11 ( _A, buffA1 ) ;
ME_INV_C g12 ( _A, buffA2 ) ;
ME_INV_C g13 ( A, notA ) ;
ME_MUX_2B_Bbyte m10 ( notA, buffA1, D0[7:0], D1[7:0], Xout[7:0] ) ;
ME_MUX_2B_Bbyte m11 ( notA, buffA1, D0[15:8], D1[15:8], Xout[15:8] ) ;
ME_MUX_2B_Bbyte m12 ( notA, buffA1, D0[23:16], D1[23:16], Xout[23:16] ) ;
ME_MUX_2B_Bbyte m13 ( notA, buffA1, D0[31:24], D1[31:24], Xout[31:24] ) ;
ME_MUX_2B_Bbyte m14 ( notA, buffA2, D0[39:32], D1[39:32], Xout[39:32] ) ;
ME_MUX_2B_Bbyte m15 ( notA, buffA2, D0[47:40], D1[47:40], Xout[47:40] ) ;
ME_MUX_2B_Bbyte m16 ( notA, buffA2, D0[55:48], D1[55:48], Xout[55:48] ) ;
ME_MUX_2B_Bbit m17 ( notA, buffA2, D0[56], D1[56], Xout[56] ) ;
ME_MUX_2B_Bbit m18 ( notA, buffA2, D0[57], D1[57], Xout[57] ) ;
endmodule
module ME_MUX_2B_58 ( A, D0, D1, Xout );
input A ;
input [57:0] D0, D1 ;
output [57:0] Xout ;
ME_INV_B g10 ( A, _A ) ;
ME_INV_C g11 ( _A, buffA1 ) ;
ME_INV_C g12 ( _A, buffA2 ) ;
ME_INV_C g13 ( A, notA ) ;
ME_MUX_2Bbyte m10 ( notA, buffA1, D0[7:0], D1[7:0], Xout[7:0] ) ;
ME_MUX_2Bbyte m11 ( notA, buffA1, D0[15:8], D1[15:8], Xout[15:8] ) ;
ME_MUX_2Bbyte m12 ( notA, buffA1, D0[23:16], D1[23:16], Xout[23:16] ) ;
ME_MUX_2Bbyte m13 ( notA, buffA1, D0[31:24], D1[31:24], Xout[31:24] ) ;
ME_MUX_2Bbyte m14 ( notA, buffA2, D0[39:32], D1[39:32], Xout[39:32] ) ;
ME_MUX_2Bbyte m15 ( notA, buffA2, D0[47:40], D1[47:40], Xout[47:40] ) ;
ME_MUX_2Bbyte m16 ( notA, buffA2, D0[55:48], D1[55:48], Xout[55:48] ) ;
ME_MUX_2Bbit m17 ( notA, buffA2, D0[56], D1[56], Xout[56] ) ;
ME_MUX_2Bbit m18 ( notA, buffA2, D0[57], D1[57], Xout[57] ) ;
endmodule
module ME_NMUX_2B_57 ( A, D0, D1, Xout );
input A ;
input [56:0] D0, D1 ;
output [56:0] Xout ;
ME_INV_B g10 ( A, _A ) ;
ME_INV_C g11 ( _A, buffA1 ) ;
ME_INV_C g12 ( _A, buffA2 ) ;
ME_INV_C g13 ( A, notA ) ;
ME_INV_C g14 ( A, notA2 ) ;
ME_NMUX_2Bbyte m10 ( notA, buffA1, D0[7:0], D1[7:0], Xout[7:0] ) ;
ME_NMUX_2Bbyte m11 ( notA, buffA1, D0[15:8], D1[15:8], Xout[15:8] ) ;
ME_NMUX_2Bbyte m12 ( notA, buffA1, D0[23:16], D1[23:16], Xout[23:16] ) ;
ME_NMUX_2Bbyte m13 ( notA, buffA1, D0[31:24], D1[31:24], Xout[31:24] ) ;
ME_NMUX_2Bbyte m14 ( notA2, buffA2, D0[39:32], D1[39:32], Xout[39:32] ) ;
ME_NMUX_2Bbyte m15 ( notA2, buffA2, D0[47:40], D1[47:40], Xout[47:40] ) ;
ME_NMUX_2Bbyte m16 ( notA2, buffA2, D0[55:48], D1[55:48], Xout[55:48] ) ;
ME_NMUX_2Bbit m17 ( notA2, buffA2, D0[56], D1[56], Xout[56] ) ;
endmodule
module ME_NMUX_2B_58 ( A, D0, D1, Xout );
input A ;
input [57:0] D0, D1 ;
output [57:0] Xout ;
ME_INV_B g10 ( A, _A ) ;
ME_INV_C g11 ( _A, buffA1 ) ;
ME_INV_C g12 ( _A, buffA2 ) ;
ME_INV_C g13 ( A, notA ) ;
ME_INV_C g14 ( A, notA2 ) ;
ME_NMUX_2Bbyte m10 ( notA, buffA1, D0[7:0], D1[7:0], Xout[7:0] ) ;
ME_NMUX_2Bbyte m11 ( notA, buffA1, D0[15:8], D1[15:8], Xout[15:8] ) ;
ME_NMUX_2Bbyte m12 ( notA, buffA1, D0[23:16], D1[23:16], Xout[23:16] ) ;
ME_NMUX_2Bbyte m13 ( notA, buffA1, D0[31:24], D1[31:24], Xout[31:24] ) ;
ME_NMUX_2Bbyte m14 ( notA2, buffA2, D0[39:32], D1[39:32], Xout[39:32] ) ;
ME_NMUX_2Bbyte m15 ( notA2, buffA2, D0[47:40], D1[47:40], Xout[47:40] ) ;
ME_NMUX_2Bbyte m16 ( notA2, buffA2, D0[55:48], D1[55:48], Xout[55:48] ) ;
ME_NMUX_2Bbit m17 ( notA2, buffA2, D0[56], D1[56], Xout[56] ) ;
ME_NMUX_2Bbit m18 ( notA2, buffA2, D0[57], D1[57], Xout[57] ) ;
endmodule
module ME_MUX_2B_64 ( A, D0, D1, Xout );
input A ;
input [63:0] D0, D1 ;
output [63:0] Xout ;
ME_BUF_B g10 ( A, _A ) ;
ME_BUF_C g11 ( _A, buffA1 ) ;
ME_BUF_C g12 ( _A, buffA2 ) ;
ME_INV_C g13 ( A, notA ) ;
ME_MUX_2Bbyte m10 ( notA, buffA1, D0[7:0], D1[7:0], Xout[7:0] ) ;
ME_MUX_2Bbyte m11 ( notA, buffA1, D0[15:8], D1[15:8], Xout[15:8] ) ;
ME_MUX_2Bbyte m12 ( notA, buffA1, D0[23:16], D1[23:16], Xout[23:16] ) ;
ME_MUX_2Bbyte m13 ( notA, buffA1, D0[31:24], D1[31:24], Xout[31:24] ) ;
ME_MUX_2Bbyte m14 ( notA, buffA2, D0[39:32], D1[39:32], Xout[39:32] ) ;
ME_MUX_2Bbyte m15 ( notA, buffA2, D0[47:40], D1[47:40], Xout[47:40] ) ;
ME_MUX_2Bbyte m16 ( notA, buffA2, D0[55:48], D1[55:48], Xout[55:48] ) ;
ME_MUX_2Bbyte m17 ( notA, buffA2, D0[63:56], D1[63:56], Xout[63:56] ) ;
endmodule
module ME_MUX_2B_B_13 ( A, D0, D1, Xout );
input A ;
input [12:0] D0, D1 ;
output [12:0] Xout ;
ME_BUFF g10 ( A, buffA ) ;
ME_INV_B g12 ( A, notA ) ;
ME_MUX_2B_Bbyte m10 ( notA, buffA, D0[7:0], D1[7:0], Xout[7:0] ) ;
ME_MUX_2B_Bbit m11 ( notA, buffA, D0[8], D1[8], Xout[8] ) ;
ME_MUX_2B_Bbit m12 ( notA, buffA, D0[9], D1[9], Xout[9] ) ;
ME_MUX_2B_Bbit m13 ( notA, buffA, D0[10], D1[10], Xout[10] ) ;
ME_MUX_2B_Bbit m14 ( notA, buffA, D0[11], D1[11], Xout[11] ) ;
ME_MUX_2B_Bbit m15 ( notA, buffA, D0[12], D1[12], Xout[12] ) ;
endmodule
module ME_MUX_2B_13 ( A, D0, D1, Xout );
input A ;
input [12:0] D0, D1 ;
output [12:0] Xout ;
ME_BUFF g10 ( A, buffA ) ;
ME_INV_B g12 ( A, notA ) ;
ME_MUX_2Bbyte m10 ( notA, buffA, D0[7:0], D1[7:0], Xout[7:0] ) ;
ME_MUX_2Bbit m11 ( notA, buffA, D0[8], D1[8], Xout[8] ) ;
ME_MUX_2Bbit m12 ( notA, buffA, D0[9], D1[9], Xout[9] ) ;
ME_MUX_2Bbit m13 ( notA, buffA, D0[10], D1[10], Xout[10] ) ;
ME_MUX_2Bbit m14 ( notA, buffA, D0[11], D1[11], Xout[11] ) ;
ME_MUX_2Bbit m15 ( notA, buffA, D0[12], D1[12], Xout[12] ) ;
endmodule
module ME_MUX_2B_11 ( A, D0, D1, Xout );
input A ;
input [10:0] D0, D1 ;
output [10:0] Xout ;
ME_INVA i0 ( A, notA ) ;
ME_BUFF b1 ( A, buffA ) ;
ME_BUFF b2 ( notA, buffnotA ) ;
ME_MUX_2Bbyte m10 ( buffnotA, buffA, D0[7:0], D1[7:0], Xout[7:0] ) ;
ME_MUX_2Bbit m11 ( buffnotA, buffA, D0[8], D1[8], Xout[8] ) ;
ME_MUX_2Bbit m12 ( buffnotA, buffA, D0[9], D1[9], Xout[9] ) ;
ME_MUX_2Bbit m13 ( buffnotA, buffA, D0[10], D1[10], Xout[10] ) ;
endmodule
module ME_MUX_2B_8 ( A, D0, D1, Xout );
input A ;
input [7:0] D0, D1 ;
output [7:0] Xout ;
ME_INV_B g11 ( A, notA ) ;
ME_MUX_2Bbyte m10 ( notA, A, D0[7:0], D1[7:0], Xout[7:0] ) ;
endmodule
module ME_MUX_2B_9 ( A, D0, D1, Xout );
input A ;
input [8:0] D0, D1 ;
output [8:0] Xout ;
ME_BUFF g10 ( A, buffA ) ;
ME_INV_B g11 ( A, notA ) ;
ME_MUX_2Bbyte m10 ( notA, buffA, D0[7:0], D1[7:0], Xout[7:0] ) ;
ME_MUX_2Bbit m11 ( notA, buffA, D0[8], D1[8], Xout[8] ) ;
endmodule
module ME_MUX_2B_5 ( A, D0, D1, Xout );
input A ;
input [4:0] D0, D1 ;
output [4:0] Xout ;
ME_BUFF g10 ( A, buffA ) ;
ME_INV_B g11 ( A, notA ) ;
ME_MUX_2Bbit m10 ( notA, buffA, D0[0], D1[0], Xout[0] ) ;
ME_MUX_2Bbit m11 ( notA, buffA, D0[1], D1[1], Xout[1] ) ;
ME_MUX_2Bbit m12 ( notA, buffA, D0[2], D1[2], Xout[2] ) ;
ME_MUX_2Bbit m13 ( notA, buffA, D0[3], D1[3], Xout[3] ) ;
ME_MUX_2Bbit m14 ( notA, buffA, D0[4], D1[4], Xout[4] ) ;
endmodule
module ME_MUX_4Bbyte ( A, B, D0, D1, D2, D3, Xout ) ;
input A, B;
input [7:0] D0, D1, D2, D3;
output [7:0] Xout;
ME_MUX4B m0 (.a(A), .b(B), .d0(D0[0]), .d1(D1[0]), .d2(D2[0]), .d3(D3[0]), .z(Xout[0]));
ME_MUX4B m1 (.a(A), .b(B), .d0(D0[1]), .d1(D1[1]), .d2(D2[1]), .d3(D3[1]), .z(Xout[1]));
ME_MUX4B m2 (.a(A), .b(B), .d0(D0[2]), .d1(D1[2]), .d2(D2[2]), .d3(D3[2]), .z(Xout[2]));
ME_MUX4B m3 (.a(A), .b(B), .d0(D0[3]), .d1(D1[3]), .d2(D2[3]), .d3(D3[3]), .z(Xout[3]));
ME_MUX4B m4 (.a(A), .b(B), .d0(D0[4]), .d1(D1[4]), .d2(D2[4]), .d3(D3[4]), .z(Xout[4]));
ME_MUX4B m5 (.a(A), .b(B), .d0(D0[5]), .d1(D1[5]), .d2(D2[5]), .d3(D3[5]), .z(Xout[5]));
ME_MUX4B m6 (.a(A), .b(B), .d0(D0[6]), .d1(D1[6]), .d2(D2[6]), .d3(D3[6]), .z(Xout[6]));
ME_MUX4B m7 (.a(A), .b(B), .d0(D0[7]), .d1(D1[7]), .d2(D2[7]), .d3(D3[7]), .z(Xout[7]));
endmodule
module ME_MUX_4B_4 ( A, B, D0, D1, D2, D3, X );
input A, B ;
input [3:0] D0, D1, D2, D3 ;
output [3:0] X ;
ME_MUX4B m0 ( A, B, D0[0], D1[0], D2[0], D3[0], X[0] ) ;
ME_MUX4B m1 ( A, B, D0[1], D1[1], D2[1], D3[1], X[1] ) ;
ME_MUX4B m2 ( A, B, D0[2], D1[2], D2[2], D3[2], X[2] ) ;
ME_MUX4B m3 ( A, B, D0[3], D1[3], D2[3], D3[3], X[3] ) ;
endmodule
module ME_MUX_4B_10 ( A, B, D0, D1, D2, D3, X );
input A, B ;
input [9:0] D0, D1, D2, D3 ;
output [9:0] X ;
ME_BUF_C g10 ( A, buffA ) ;
ME_BUF_B g11 ( B, buffB ) ;
ME_MUX_4Bbyte m10 ( buffA, buffB, D0[7:0], D1[7:0], D2[7:0], D3[7:0], X[7:0] ) ;
ME_MUX4B m16 ( buffA, buffB, D0[8], D1[8], D2[8], D3[8], X[8] ) ;
ME_MUX4B m15 ( buffA, buffB, D0[9], D1[9], D2[9], D3[9], X[9] ) ;
endmodule
module ME_MUX_4B_13 ( A, B, D0, D1, D2, D3, X );
input A, B ;
input [12:0] D0, D1, D2, D3 ;
output [12:0] X ;
ME_BUF_C g10 ( A, buffA ) ;
ME_BUF_B g11 ( B, buffB ) ;
ME_MUX_4Bbyte m10 ( buffA, buffB, D0[7:0], D1[7:0], D2[7:0], D3[7:0], X[7:0] ) ;
ME_MUX4B m16 ( buffA, buffB, D0[8], D1[8], D2[8], D3[8], X[8] ) ;
ME_MUX4B m15 ( buffA, buffB, D0[9], D1[9], D2[9], D3[9], X[9] ) ;
ME_MUX4B m17 ( buffA, buffB, D0[10], D1[10], D2[10], D3[10], X[10] ) ;
ME_MUX4B m18 ( buffA, buffB, D0[11], D1[11], D2[11], D3[11], X[11] ) ;
ME_MUX4B m19 ( buffA, buffB, D0[12], D1[12], D2[12], D3[12], X[12] ) ;
endmodule
module ME_TIEOFF (VDD, GND);
output VDD, GND;
N1Z001 vdd(VDD);
N1Z000 gnd(GND);
endmodule
module cn1 (out, in1);
input in1 ;
output out ;
assign out = in1;
//NULL_WIRE u1 (in1, out);
endmodule
module con1 (con_in, con_out);
input con_in;
output con_out;
// buf z0 (con_out, con_in);
cn1 z0 (con_out, con_in);
endmodule
// Meiko macros
//
module ME_FD1P2 ( Q, QN, CP, D );
input [1:0] D;
input CP;
output [1:0] Q, QN ;
ME_FD1P f0(.q(Q[0]), .qn(QN[0]), .cp(CP), .d(D[0]));
ME_FD1P f1(.q(Q[1]), .qn(QN[1]), .cp(CP), .d(D[1]));
endmodule
module ME_FD1P_6 ( Q, QN, CP, D );
input CP;
input [5:0] D;
output [5:0] Q, QN ;
ME_FD1P f0(.q(Q[0]), .qn(QN[0]), .cp(CP), .d(D[0]) );
ME_FD1P f1(.q(Q[1]), .qn(QN[1]), .cp(CP), .d(D[1]) );
ME_FD1P f2(.q(Q[2]), .qn(QN[2]), .cp(CP), .d(D[2]) );
ME_FD1P f3(.q(Q[3]), .qn(QN[3]), .cp(CP), .d(D[3]) );
ME_FD1P f4(.q(Q[4]), .qn(QN[4]), .cp(CP), .d(D[4]) );
ME_FD1P f5(.q(Q[5]), .qn(QN[5]), .cp(CP), .d(D[5]) );
endmodule
module ME_FDS2LP2 ( Q, QN, CP, CR, D, LD );
input [1:0] D;
input CP, LD, CR;
output [1:0] Q, QN ;
ME_FDS2LP f0(.q(Q[0]), .qn(QN[0]), .cp(CP), .cr(CR), .d(D[0]), .ld(LD));
ME_FDS2LP f1(.q(Q[1]), .qn(QN[1]), .cp(CP), .cr(CR), .d(D[1]), .ld(LD));
endmodule
module ME_FDS2LP3 ( Q, QN, CP, CR, D, LD );
input [2:0] D;
input CP, LD, CR;
output [2:0] Q, QN;
ME_FDS2LP f0(.q(Q[0]), .qn(QN[0]), .cp(CP), .cr(CR), .d(D[0]), .ld(LD));
ME_FDS2LP f1(.q(Q[1]), .qn(QN[1]), .cp(CP), .cr(CR), .d(D[1]), .ld(LD));
ME_FDS2LP f2(.q(Q[2]), .qn(QN[2]), .cp(CP), .cr(CR), .d(D[2]), .ld(LD));
endmodule
module ME_FDS2LP4 ( Q, QN, CP, CR, D, LD );
input [3:0] D;
input CP, LD, CR;
output [3:0] Q, QN;
ME_FDS2LP f0(.q(Q[0]), .qn(QN[0]), .cp(CP), .cr(CR), .d(D[0]), .ld(LD));
ME_FDS2LP f1(.q(Q[1]), .qn(QN[1]), .cp(CP), .cr(CR), .d(D[1]), .ld(LD));
ME_FDS2LP f2(.q(Q[2]), .qn(QN[2]), .cp(CP), .cr(CR), .d(D[2]), .ld(LD));
ME_FDS2LP f3(.q(Q[3]), .qn(QN[3]), .cp(CP), .cr(CR), .d(D[3]), .ld(LD));
endmodule
module ME_FDS2LP5 ( Q, QN, CP, CR, D, LD );
input [4:0] D;
input CP, LD, CR;
output [4:0] Q, QN;
ME_FDS2LP f0(.q(Q[0]), .qn(QN[0]), .cp(CP), .cr(CR), .d(D[0]), .ld(LD));
ME_FDS2LP f1(.q(Q[1]), .qn(QN[1]), .cp(CP), .cr(CR), .d(D[1]), .ld(LD));
ME_FDS2LP f2(.q(Q[2]), .qn(QN[2]), .cp(CP), .cr(CR), .d(D[2]), .ld(LD));
ME_FDS2LP f3(.q(Q[3]), .qn(QN[3]), .cp(CP), .cr(CR), .d(D[3]), .ld(LD));
ME_FDS2LP f4(.q(Q[4]), .qn(QN[4]), .cp(CP), .cr(CR), .d(D[4]), .ld(LD));
endmodule
module ME_FDS2LP8 ( Q, QN, CP, CR, D, LD );
input [7:0] D;
input CP, LD, CR;
output [7:0] Q, QN;
ME_FDS2LP f0(.q(Q[0]), .qn(QN[0]), .cp(CP), .cr(CR), .d(D[0]), .ld(LD));
ME_FDS2LP f1(.q(Q[1]), .qn(QN[1]), .cp(CP), .cr(CR), .d(D[1]), .ld(LD));
ME_FDS2LP f2(.q(Q[2]), .qn(QN[2]), .cp(CP), .cr(CR), .d(D[2]), .ld(LD));
ME_FDS2LP f3(.q(Q[3]), .qn(QN[3]), .cp(CP), .cr(CR), .d(D[3]), .ld(LD));
ME_FDS2LP f4(.q(Q[4]), .qn(QN[4]), .cp(CP), .cr(CR), .d(D[4]), .ld(LD));
ME_FDS2LP f5(.q(Q[5]), .qn(QN[5]), .cp(CP), .cr(CR), .d(D[5]), .ld(LD));
ME_FDS2LP f6(.q(Q[6]), .qn(QN[6]), .cp(CP), .cr(CR), .d(D[6]), .ld(LD));
ME_FDS2LP f7(.q(Q[7]), .qn(QN[7]), .cp(CP), .cr(CR), .d(D[7]), .ld(LD));
endmodule
module ME_MUX2_2 (Z, A, B, S);
input [1:0] A, B;
input S;
output [1:0] Z;
AMUX2A u0 (.O(Z[0]), .A(A[0]), .B(B[0]), .S(S) );
AMUX2A u1 (.O(Z[1]), .A(A[1]), .B(B[1]), .S(S) );
endmodule
module ME_MUX2_5 (Z, A, B, S);
input [4:0] A, B;
input S;
output [4:0] Z;
AMUX2A u0 (.O(Z[0]), .A(A[0]), .B(B[0]), .S(S) );
AMUX2A u1 (.O(Z[1]), .A(A[1]), .B(B[1]), .S(S) );
AMUX2A u2 (.O(Z[2]), .A(A[2]), .B(B[2]), .S(S) );
AMUX2A u3 (.O(Z[3]), .A(A[3]), .B(B[3]), .S(S) );
AMUX2A u4 (.O(Z[4]), .A(A[4]), .B(B[4]), .S(S) );
endmodule
module ME_MUX21H23 (Z, A, B, S);
input [22:0] A, B;
input S;
output [22:0] Z;
ME_BUF_D b10 ( S, buffS ) ;
ME_INV_C b11 ( S, notS ) ;
ME_MUX_2Bbyte m10 ( notS, buffS, A[ 7: 0], B[ 7: 0], Z[ 7: 0] ) ;
ME_MUX_2Bbyte m11 ( notS, buffS, A[15: 8], B[15: 8], Z[15: 8] ) ;
ME_MUX_2Bbit m0 ( notS, buffS, A[16], B[16], Z[16] );
ME_MUX_2Bbit m1 ( notS, buffS, A[17], B[17], Z[17] );
ME_MUX_2Bbit m2 ( notS, buffS, A[18], B[18], Z[18] );
ME_MUX_2Bbit m3 ( notS, buffS, A[19], B[19], Z[19] );
ME_MUX_2Bbit m4 ( notS, buffS, A[20], B[20], Z[20] );
ME_MUX_2Bbit m5 ( notS, buffS, A[21], B[21], Z[21] );
ME_MUX_2Bbit m6 ( notS, buffS, A[22], B[22], Z[22] );
endmodule
module ME_MUX21H25 (Z, A, B, S);
input [24:0] A, B;
input S;
output [24:0] Z;
ME_BUF_D b10 ( S, buffS ) ;
ME_INV_C b11 ( S, notS ) ;
ME_MUX_2Bbyte m10 ( notS, buffS, A[ 7: 0], B[ 7: 0], Z[ 7: 0] ) ;
ME_MUX_2Bbyte m11 ( notS, buffS, A[15: 8], B[15: 8], Z[15: 8] ) ;
ME_MUX_2Bbyte m12 ( notS, buffS, A[23:16], B[23:16], Z[23:16] ) ;
ME_MUX_2Bbit m0 ( notS, buffS, A[24], B[24], Z[24] );
endmodule
module ME_MUX21H28 (Z, A, B, S, notS);
input [27:0] A, B;
input S, notS;
output [27:0] Z;
ME_INV_C b10 ( S, buffnotS_1 ) ;
ME_INV_C b11 ( notS, buffS_1 ) ;
ME_INV_C b12 ( S, buffnotS_2 ) ;
ME_INV_C b13 ( notS, buffS_2 ) ;
ME_MUX_2Bbyte m10 ( buffnotS_1, buffS_1, A[ 7: 0], B[ 7: 0], Z[ 7: 0] ) ;
ME_MUX_2Bbyte m11 ( buffnotS_1, buffS_1, A[15: 8], B[15: 8], Z[15: 8] ) ;
ME_MUX_2Bbyte m12 ( buffnotS_2, buffS_2, A[23:16], B[23:16], Z[23:16] ) ;
ME_MUX_2Bbit m0 ( buffnotS_2, buffS_2, A[24], B[24], Z[24] );
ME_MUX_2Bbit m1 ( buffnotS_2, buffS_2, A[25], B[25], Z[25] );
ME_MUX_2Bbit m2 ( buffnotS_2, buffS_2, A[26], B[26], Z[26] );
ME_MUX_2Bbit m3 ( buffnotS_2, buffS_2, A[27], B[27], Z[27] );
endmodule
module ME_MUX21H30 (Z, A, B, S);
input [29:0] A, B;
input S;
output [29:0] Z;
ME_BUF_D b10 ( S, buffS ) ;
ME_INV_C b11 ( S, notS ) ;
ME_MUX_2Bbyte m10 ( notS, buffS, A[ 7: 0], B[ 7: 0], Z[ 7: 0] ) ;
ME_MUX_2Bbyte m11 ( notS, buffS, A[15: 8], B[15: 8], Z[15: 8] ) ;
ME_MUX_2Bbyte m12 ( notS, buffS, A[23:16], B[23:16], Z[23:16] ) ;
ME_MUX_2Bbit m0 ( notS, buffS, A[24], B[24], Z[24] );
ME_MUX_2Bbit m1 ( notS, buffS, A[25], B[25], Z[25] );
ME_MUX_2Bbit m2 ( notS, buffS, A[26], B[26], Z[26] );
ME_MUX_2Bbit m3 ( notS, buffS, A[27], B[27], Z[27] );
ME_MUX_2Bbit m4 ( notS, buffS, A[28], B[28], Z[28] );
ME_MUX_2Bbit m5 ( notS, buffS, A[29], B[29], Z[29] );
endmodule
module ME_MUX21H32 (Z, A, B, S);
input [31:0] A, B;
input S;
output [31:0] Z;
ME_BUF_D b10 ( S, buffS ) ;
ME_INV_C b11 ( S, notS ) ;
ME_MUX_2Bbyte m10 ( notS, buffS, A[ 7: 0], B[ 7: 0], Z[ 7: 0] ) ;
ME_MUX_2Bbyte m11 ( notS, buffS, A[15: 8], B[15: 8], Z[15: 8] ) ;
ME_MUX_2Bbyte m12 ( notS, buffS, A[23:16], B[23:16], Z[23:16] ) ;
ME_MUX_2Bbyte m13 ( notS, buffS, A[31:24], B[31:24], Z[31:24] ) ;
endmodule
module ME_MUX21H53 (Z, A, B, S);
input [52:0] A, B;
input S;
output [52:0] Z;
ME_BUF_D b10 ( S, buffS ) ;
ME_INV_C b11 ( S, notS ) ;
ME_MUX_2Bbyte m10 ( notS, buffS, A[ 7: 0], B[ 7: 0], Z[ 7: 0] ) ;
ME_MUX_2Bbyte m11 ( notS, buffS, A[15: 8], B[15: 8], Z[15: 8] ) ;
ME_MUX_2Bbyte m12 ( notS, buffS, A[23:16], B[23:16], Z[23:16] ) ;
ME_MUX_2Bbyte m13 ( notS, buffS, A[31:24], B[31:24], Z[31:24] ) ;
ME_MUX_2Bbyte m14 ( notS, buffS, A[39:32], B[39:32], Z[39:32] ) ;
ME_MUX_2Bbyte m15 ( notS, buffS, A[47:40], B[47:40], Z[47:40] ) ;
ME_MUX_2Bbit m0 ( notS, buffS, A[48], B[48], Z[48] );
ME_MUX_2Bbit m1 ( notS, buffS, A[49], B[49], Z[49] );
ME_MUX_2Bbit m2 ( notS, buffS, A[50], B[50], Z[50] );
ME_MUX_2Bbit m3 ( notS, buffS, A[51], B[51], Z[51] );
ME_MUX_2Bbit m4 ( notS, buffS, A[52], B[52], Z[52] );
endmodule
module ME_MUX_3bit ( s0, s1, d0, d1, d2, Q ) ;
input s0, s1, d0, d1, d2;
output Q ;
// s1 s0 : Q
// 0 0 : d0
// 0 1 : d1
// 1 0 : d2
// 1 1 : d2
AMUX3A g0 (d0, d1, d2, s0, s1, Q);
endmodule
module ME_MUX_3byte ( s0, s1, d0, d1, d2, Q ) ;
input s0, s1;
input [7:0] d0, d1, d2;
output [7:0] Q ;
ME_MUX_3bit f0 ( s0, s1, d0[0], d1[0], d2[0], Q [0]) ;
ME_MUX_3bit f1 ( s0, s1, d0[1], d1[1], d2[1], Q [1]) ;
ME_MUX_3bit f2 ( s0, s1, d0[2], d1[2], d2[2], Q [2]) ;
ME_MUX_3bit f3 ( s0, s1, d0[3], d1[3], d2[3], Q [3]) ;
ME_MUX_3bit f4 ( s0, s1, d0[4], d1[4], d2[4], Q [4]) ;
ME_MUX_3bit f5 ( s0, s1, d0[5], d1[5], d2[5], Q [5]) ;
ME_MUX_3bit f6 ( s0, s1, d0[6], d1[6], d2[6], Q [6]) ;
ME_MUX_3bit f7 ( s0, s1, d0[7], d1[7], d2[7], Q [7]) ;
endmodule
/* real instances start here */
module ME_MUX3_25 ( Q, s0, s1, d0, d1, d2 ) ;
input s0, s1;
input [24:0] d0, d1, d2;
output [24:0] Q;
ME_BUF_C b0 (s0, buff1_s0);
ME_BUF_C b1 (s0, buff2_s0);
ME_BUF_C b2 (s1, buff1_s1);
ME_BUF_C b3 (s1, buff2_s1);
ME_MUX_3byte m0
(buff1_s0, buff1_s1, d0[ 7: 0], d1[ 7: 0], d2[ 7: 0], Q[ 7: 0] );
ME_MUX_3byte m1
(buff1_s0, buff1_s1, d0[15: 8], d1[15: 8], d2[15: 8], Q[15: 8] );
ME_MUX_3byte m2
(buff2_s0, buff2_s1, d0[23:16], d1[23:16], d2[23:16], Q[23:16] );
ME_MUX_3bit m3_0 (buff2_s0, buff2_s1, d0[24], d1[24], d2[24], Q[24] );
endmodule
module ME_MUX3_53 ( Q, s0, s1, d0, d1, d2 ) ;
input s0, s1;
input [52:0] d0, d1, d2;
output [52:0] Q;
ME_BUF_C b0 (s0, buff1_s0);
ME_BUF_C b1 (s0, buff2_s0);
ME_BUF_C b2 (s0, buff3_s0);
ME_BUF_C b3 (s0, buff4_s0);
ME_BUF_C b4 (s1, buff1_s1);
ME_BUF_C b5 (s1, buff2_s1);
ME_BUF_C b6 (s1, buff3_s1);
ME_BUF_C b7 (s1, buff4_s1);
ME_MUX_3byte m0
(buff1_s0, buff1_s1, d0[ 7: 0], d1[ 7: 0], d2[ 7: 0], Q[ 7: 0] );
ME_MUX_3byte m1
(buff1_s0, buff1_s1, d0[15: 8], d1[15: 8], d2[15: 8], Q[15: 8] );
ME_MUX_3byte m2
(buff2_s0, buff2_s1, d0[23:16], d1[23:16], d2[23:16], Q[23:16] );
ME_MUX_3byte m3
(buff2_s0, buff2_s1, d0[31:24], d1[31:24], d2[31:24], Q[31:24] );
ME_MUX_3byte m4
(buff3_s0, buff3_s1, d0[39:32], d1[39:32], d2[39:32], Q[39:32] );
ME_MUX_3byte m5
(buff3_s0, buff3_s1, d0[47:40], d1[47:40], d2[47:40], Q[47:40] );
ME_MUX_3bit m6_0 (buff4_s0, buff4_s1, d0[48], d1[48], d2[48], Q[48] );
ME_MUX_3bit m6_1 (buff4_s0, buff4_s1, d0[49], d1[49], d2[49], Q[49] );
ME_MUX_3bit m6_2 (buff4_s0, buff4_s1, d0[50], d1[50], d2[50], Q[50] );
ME_MUX_3bit m6_3 (buff4_s0, buff4_s1, d0[51], d1[51], d2[51], Q[51] );
ME_MUX_3bit m6_4 (buff4_s0, buff4_s1, d0[52], d1[52], d2[52], Q[52] );
endmodule
module ME_MUX41H28 ( Q, d0, d1, d2, d3, A, B ) ;
input A, B;
input [27:0] d0, d1, d2, d3;
output [27:0] Q ;
ME_BUF_C b0 ( A, buffA1 ) ;
ME_BUF_C b1 ( A, buffA2 ) ;
ME_BUF_C b2 ( B, buffB1 ) ;
ME_BUF_C b3 ( B, buffB2 ) ;
ME_MUX_4Bbyte m10 ( buffA1, buffB1,
d0[ 7: 0], d1[ 7: 0], d2[ 7: 0], d3[ 7: 0], Q[ 7: 0] ) ;
ME_MUX_4Bbyte m11 ( buffA1, buffB1,
d0[15: 8], d1[15: 8], d2[15: 8], d3[15: 8], Q[15: 8] );
ME_MUX_4Bbyte m12 ( buffA2, buffB2,
d0[23:16], d1[23:16], d2[23:16], d3[23:16], Q[23:16] ) ;
ME_MUX4B m13_0 ( buffA2, buffB2, d0[24], d1[24], d2[24], d3[24], Q[24] );
ME_MUX4B m13_1 ( buffA2, buffB2, d0[25], d1[25], d2[25], d3[25], Q[25] );
ME_MUX4B m13_2 ( buffA2, buffB2, d0[26], d1[26], d2[26], d3[26], Q[26] );
ME_MUX4B m13_3 ( buffA2, buffB2, d0[27], d1[27], d2[27], d3[27], Q[27] );
endmodule
module ME_MUX41H32 ( Q, d0, d1, d2, d3, A, B ) ;
input A, B;
input [31:0] d0, d1, d2, d3;
output [31:0] Q ;
ME_BUF_C b0 ( A, buffA1 ) ;
ME_BUF_C b1 ( A, buffA2 ) ;
ME_BUF_C b2 ( B, buffB1 ) ;
ME_BUF_C b3 ( B, buffB2 ) ;
ME_MUX_4Bbyte m10 ( buffA1, buffB1,
d0[ 7: 0], d1[ 7: 0], d2[ 7: 0], d3[ 7: 0], Q[ 7: 0] ) ;
ME_MUX_4Bbyte m11 ( buffA1, buffB1,
d0[15: 8], d1[15: 8], d2[15: 8], d3[15: 8], Q[15: 8] );
ME_MUX_4Bbyte m12 ( buffA2, buffB2,
d0[23:16], d1[23:16], d2[23:16], d3[23:16], Q[23:16] ) ;
ME_MUX_4Bbyte m13 ( buffA2, buffB2,
d0[31:24], d1[31:24], d2[31:24], d3[31:24], Q[31:24] ) ;
endmodule
module ME_MUX41H53 ( Q, d0, d1, d2, d3, sel ) ;
input [1:0] sel ;
input [52:0] d0, d1, d2, d3;
output [52:0] Q ;
ME_BUF_C b0 ( sel[0], buffA1 ) ;
ME_BUF_C b1 ( sel[0], buffA2 ) ;
ME_BUF_C b2 ( sel[0], buffA3 ) ;
ME_BUF_C b3 ( sel[0], buffA4 ) ;
ME_BUF_C b4 ( sel[1], buffB1 ) ;
ME_BUF_C b5 ( sel[1], buffB2 ) ;
ME_BUF_C b6 ( sel[1], buffB3 ) ;
ME_BUF_C b7 ( sel[1], buffB4 ) ;
ME_MUX_4Bbyte m10 ( buffA1, buffB1,
d0[7:0], d1[7:0], d2[7:0], d3[7:0], Q[7:0] ) ;
ME_MUX_4Bbyte m11 ( buffA1, buffB1,
d0[15:8], d1[15:8], d2[15:8], d3[15:8], Q[15:8] );
ME_MUX_4Bbyte m12 ( buffA2, buffB2,
d0[23:16], d1[23:16], d2[23:16], d3[23:16], Q[23:16] ) ;
ME_MUX_4Bbyte m13 ( buffA2, buffB2,
d0[31:24], d1[31:24], d2[31:24], d3[31:24], Q[31:24] ) ;
ME_MUX_4Bbyte m14 ( buffA3, buffB3,
d0[39:32], d1[39:32], d2[39:32], d3[39:32], Q[39:32] ) ;
ME_MUX_4Bbyte m15 ( buffA3, buffB3,
d0[47:40], d1[47:40], d2[47:40], d3[47:40], Q[47:40] ) ;
ME_MUX4B m16_0 ( buffA4, buffB4, d0[48], d1[48], d2[48], d3[48], Q[48] );
ME_MUX4B m16_1 ( buffA4, buffB4, d0[49], d1[49], d2[49], d3[49], Q[49] );
ME_MUX4B m16_2 ( buffA4, buffB4, d0[50], d1[50], d2[50], d3[50], Q[50] );
ME_MUX4B m16_3 ( buffA4, buffB4, d0[51], d1[51], d2[51], d3[51], Q[51] );
ME_MUX4B m16_4 ( buffA4, buffB4, d0[52], d1[52], d2[52], d3[52], Q[52] );
endmodule
// Meiko adder macros
//
module ME_ADD_13 ( sub, CarryIn, x, y, z, zbuf, Eqv ) ;
input sub, CarryIn;
input [12:0] x, y ;
output [12:0] zbuf, z ;
output Eqv ;
adder13 add ( sub, CarryIn, x, y, z, Eqv ) ;
assign zbuf = z ;
endmodule
module ME_SUB_13 ( sub, CarryIn, x, y, z );
input sub, CarryIn;
input [12:0] x, y ;
output [12:0] z ;
adder13 sub13 ( sub, CarryIn, x, y, z, ) ;
endmodule
module subtract13 ( x, y, z) ;
input [12:0] x, y ;
output [12:0] z ;
// special 1's comp. subtractor
adder13 sub13 ( 1'b1, 1'b0, x, y, z, ) ;
endmodule
module dual_adder13 ( x, y, sum_0, sum_1 ) ;
input [12:0] x, y ;
output [12:0] sum_0 ; // x+y
output [12:0] sum_1 ; // x+y+1
adder13
expadd0 (.z( sum_0[12:0] ), // x+y
.x( x[12:0] ),
.y( y[12:0]),
.sub(1'b0),
.CarryIn(1'b0)
);
adder13
expadd1 (.z( sum_1[12:0] ), // x+y+1
.x( x[12:0] ),
.y( y[12:0]),
.sub(1'b0),
.CarryIn(1'b1)
);
endmodule
module adder13 ( sub, CarryIn, x, y, z, Eqv ) ;
input sub, CarryIn;
input [12:0] x, y ;
output [12:0] z ;
output Eqv ;
wire [12:0] zbuf;
ME_INVA s1 (sub, notsub);
ME_INV_C s0 (notsub, Bsub);
acell4 bit0to3 ( x[3:0], y[3:0], Bsub, CarryIn, z[3:0], zbuf[3:0], p0, g0 ) ;
acell4 bit4to7 ( x[7:4], y[7:4], Bsub, Cin1, z[7:4], zbuf[7:4], p1, g1 ) ;
acell4 bit8to11 ( x[11:8], y[11:8], Bsub, Cin2, z[11:8], zbuf[11:8], p2, g2 ) ;
acell1 bit11 ( x[12], y[12], Bsub, Cin3, z[12], zbuf[12], p3, notp3, p3buf);
ME_NMUX2B g10 ( p1, g1, g0, notg7to0 ) ;
ME_INV_A g11 ( CarryIn, notCin ) ;
ME_INV_A g12 ( g0, notg0 ) ;
ME_NMUX2B_B g13 ( p0, notg0, notCin, Cin1 ) ;
ME_NAND2_B g14 ( p0, p1, notplo );
ME_NMUX2B_B g15 ( notplo, notCin, notg7to0, Cin2 ) ;
ME_NAND2_B g16 ( notplo, p2, notUseG7to0 );
ME_NMUX2B g17 ( p2, g2, CarryIn, notCinOrg11to8) ;
ME_NMUX2B_B g18 ( notUseG7to0, notg7to0, notCinOrg11to8, Cin3 ) ;
ME_INV_A g19 ( notplo, plo ) ;
ME_AND2 g20 ( p2, p3, phi );
ME_AND2 g21 ( phi, plo, Eqv ) ;
endmodule
module adder29 ( CarryIn, x, y, z ) ;
input CarryIn;
input [27:0] x, y ;
output [28:0] z ;
assign z = x[27:0] + y[27:0] + CarryIn ;
endmodule
module ME_ADD_58 ( notsub, CarryIn, x, y, z, zbuf, Eqv ) ;
input notsub, CarryIn ;
input [57:0] x, y ;
output [57:0] zbuf, z ;
output Eqv ;
adder58 adr ( notsub, notsub, CarryIn, x, y, z, Eqv ) ;
assign zbuf = z;
endmodule
module adder52 ( x, y, sum_0, sum_1 ) ;
input [51:0] x, y ;
output [51:0] sum_0 ; // x+y
output [51:0] sum_1 ; // x+y+1
wire [57:0] sumout_0, sumout_1 ;
adder58
add52_0 ( // only use 52 bits
.z( sumout_0[57:0] ),
.x( {6'b0, x[51:0]} ),
.y( {6'b0, y[51:0]} ),
.CarryIn(1'b0),
.notsub_0(1'b1),
.notsub_1(1'b1)
);
assign sum_0[51:0] = sumout_0[51:0] ;
adder58
add52_1 ( // only use 52 bits
.z( sumout_1[57:0] ),
.x( {6'b0, x[51:0]} ),
.y( {6'b0, y[51:0]} ),
.CarryIn(1'b1),
.notsub_0(1'b1),
.notsub_1(1'b1)
);
assign sum_1[51:0] = sumout_1[51:0] ;
endmodule
module adder58 ( notsub_0, notsub_1, CarryIn, x, y, z, Eqv ) ;
input notsub_0, notsub_1, CarryIn ;
input [57:0] x, y ;
output [57:0] z ;
output Eqv ;
wire [57:0] zbuf;
ME_INV_C s1 (notsub_0, Bsub1);
ME_INV_C s2 (notsub_1, Bsub2);
acell16 bit0to15 ( x[15:0], y[15:0], Bsub1, CarryIn, z[15:0], zbuf[15:0], p0, g0 ) ;
acell16 bit16to31 ( x[31:16], y[31:16], Bsub1, Cin1, z[31:16], zbuf[31:16], p1, g1 ) ;
acell16 bit32to47 ( x[47:32], y[47:32], Bsub2, Cin2, z[47:32], zbuf[47:32], p2, g2 ) ;
// acell10 bit47to57 ( x[57:48], y[57:48], Bnotsub2, Cin3, z[57:48], zbuf[57:48], p3, g3 ) ;
acell10 bit47to57 ( x[57:48], y[57:48], Bsub2, Cin3, z[57:48], zbuf[57:48], p3 ) ;
ME_NMUX2B_B g10 ( p1, g1, g0, notg31to0 ) ;
ME_INV_A g11 ( CarryIn, notCin ) ;
ME_INV_A g12 ( g0, notg0 ) ;
ME_NMUX2B_B g13 ( p0, notg0, notCin, Cin1 ) ;
ME_NAND2_B g14 ( p0, p1, notplo );
ME_NMUX2B_B g15 ( notplo, notCin, notg31to0, Cin2 ) ;
ME_NAND2_B g16 ( notplo, p2, notUseG31to0 );
ME_NMUX2B g17 ( p2, g2, CarryIn, notCinOrg47to32) ;
ME_NMUX2B_B g18 ( notUseG31to0, notg31to0, notCinOrg47to32, Cin3 ) ;
ME_INV_A g19 ( notplo, plo ) ;
ME_AND2 g20 ( p2, p3, phi );
ME_AND2 g21 ( phi, plo, Eqv ) ;
// ME_INV_A g22 ( notg31to0, g31to0) ; // Not intrested in CarryOut
// ME_INV_A g23 ( notCinOrg47to32, CinOrg47to32) ; // Drove nowhere
// ME_MUX2B g24 ( p3, g3, g2, g57to32 ) ; // Not intrested in CarryOut
// ME_MUX2B g25 ( phi, g57to32, g31to0, g57to0 ) ; // Not intrested in CarryOut
// ME_MUX2B g26 ( Eqv, g57to0, CarryIn, CarryOut ) ; // Not intrested in CarryOut
endmodule
module acell10 ( x, y, notsub, Cin, z, zbuf, p ) ;
input [9:0] x, y ;
input notsub, Cin ;
output [9:0] zbuf, z ;
// output p, g;
output p;
acell4a bit0 ( x[3:0], y[3:0], notsub, notCin0, z[3:0], zbuf[3:0], p0, g0) ;
acell4a bit4 ( x[7:4], y[7:4], notsub, notCin4, z[7:4], zbuf[7:4], p4, g4) ;
acell1a bit8 ( x[8], y[8], notsub, notCin8, z[8], zbuf[8], p8, notp8, pbuf8 ) ;
acell1a bit9 ( x[9], y[9], notsub, notCin9, z[9], zbuf[9], p9, notp9, pbuf9 ) ;
ME_NAND2 g10 ( p0, p4, notplo ) ;
// ME_NAND2 g11 ( p8, p9, notphi ) ;
ME_NMUX2B g12 ( p4, g4, g0, notglo ) ;
// ME_NMUX2B_B g13 ( p9, x[9], x[8], notghi ) ;
// ME_NMUX2B g14 ( notphi, notglo, notghi, g ) ;
ME_INV_B g15 ( Cin, notCin0 );
ME_NMUX2B_B g17 ( p0, g0, Cin, notCin4 ) ;
//ME_INV_A g18 ( notglo, glo );
ME_INV_A g30 ( Cin, notCin);
ME_MUX2B g19 ( notplo, notCin, notglo, notCin8 ) ;
ME_NAND3 g20 ( p0, p4, pbuf8, notp0to8 ) ;
ME_INV_A g21 ( x[8], notg8 ) ;
ME_NMUX2B g25 ( p8, notg8, notglo, gl0to8 ) ;
ME_NMUX2B g26 ( notp0to8, Cin, gl0to8, notCin9 ) ;
ME_AND4_B g27 ( p0, p4, p8, p9, p ) ;
endmodule
module acell16 ( x, y, notsub, Cin, z, zbuf, p, g ) ;
input [15:0] x, y ;
input notsub, Cin ;
output [15:0] zbuf, z ;
output p, g;
acell4a bit0 ( x[3:0], y[3:0], notsub, notCin0, z[3:0], zbuf[3:0], p0, g0) ;
acell4a bit1 ( x[7:4], y[7:4], notsub, notCin1, z[7:4], zbuf[7:4], p1, g1) ;
acell4a bit2 ( x[11:8], y[11:8], notsub, notCin2, z[11:8], zbuf[11:8], p2, g2) ;
acell4a bit3 ( x[15:12], y[15:12], notsub, notCin3, z[15:12], zbuf[15:12], p3, g3) ;
ME_NAND2 g10 ( p0, p1, notplo ) ;
ME_NAND2 g11 ( p2, p3, notphi ) ;
ME_NMUX2B g12 ( p1, g1, g0, notglo ) ;
ME_NMUX2B g13 ( p3, g3, g2, notghi ) ;
ME_NMUX2B g14 ( notphi, notglo, notghi, g ) ;
ME_INV_B g15 ( Cin, notCin0 );
ME_INV_A g16 ( g0, notg0 ) ;
ME_INV_A g17 ( notg0, g0buf ) ;
ME_NMUX2B_B g18 ( p0, g0buf, Cin, notCin1 ) ;
ME_INV_A g19 ( notglo, glo );
ME_NMUX2B_B g20 ( notplo, Cin, glo, notCin2 ) ;
ME_NAND3 g21 ( p0, p1, p2, notp0to2 ) ;
ME_INV_A g22 ( g2, notg2 ) ;
ME_INV_A g23 ( glo, notglobuf );
ME_INV_A g24 ( p2, notp2 );
ME_NMUX2B g25 ( notp2, notglobuf, notg2, gl0to2 ) ;
ME_NMUX2B_B g26 ( notp0to2, Cin, gl0to2, notCin3 ) ;
ME_AND4_B g27 ( p0, p1, p2, p3, p ) ;
endmodule
module acell4 ( x, y, notsub, Cin, z, zbuf, p, g ) ;
input [3:0] x, y ;
input notsub, Cin ;
output [3:0] z, zbuf ;
output p, g;
acell1a bit0 ( x[0], y[0], notsub, notCin0, z[0], zbuf[0], p0, notp0, pbuf0 ) ;
acell1a bit1 ( x[1], y[1], notsub, notCin1, z[1], zbuf[1], p1, notp1, pbuf1 ) ;
acell1a bit2 ( x[2], y[2], notsub, notCin2, z[2], zbuf[2], p2, notp2, pbuf2 ) ;
acell1a bit3 ( x[3], y[3], notsub, notCin3, z[3], zbuf[3], p3, notp3, pbuf3 ) ;
ME_NAND2 g10 ( pbuf0, pbuf1, notplo ) ;
ME_NAND2 g11 ( p2, p3, notphi ) ;
ME_NMUX2B_B g12 ( p1, x[1], x[0], notglo ) ;
ME_NMUX2B_B g13 ( p3, x[3], x[2], notghi ) ;
ME_NMUX2B_B g14 ( notphi, notglo, notghi, g ) ;
ME_INVA g15 ( Cin, notCin0 );
ME_INV_A g16 ( x[0], notg0 );
ME_INV_A g17 ( notg0, g0 );
ME_NMUX2B g18 ( p0, g0, Cin, notCin1 ) ;
ME_INV_A g19 ( notglo, glo );
ME_NMUX2B g20 ( notplo, Cin, glo, notCin2 ) ;
ME_NAND3 g21 ( pbuf0, pbuf1, pbuf2, notp0to2 ) ;
ME_INV_A g22 ( x[2], notg2 );
ME_INV_A g23 ( glo, notglobuf );
ME_NMUX2B g24 ( notp2, notglobuf, notg2, g0to2 ) ;
ME_NMUX2B g25 ( notp0to2, Cin, g0to2, notCin3 ) ;
ME_AND4_B g26 ( p0, p1, p2, p3, p ) ;
endmodule
module acell4a ( x, y, notsub, notCin, z, zbuf, p, g ) ;
input [3:0] x, y ;
input notsub, notCin ;
output [3:0] zbuf, z ;
output p, g;
acell1 bit0 ( x[0], y[0], notsub, Cin0, z[0], zbuf[0], p0, notp0, pbuf0 ) ;
acell1 bit1 ( x[1], y[1], notsub, Cin1, z[1], zbuf[1], p1, notp1, pbuf1 ) ;
acell1 bit2 ( x[2], y[2], notsub, Cin2, z[2], zbuf[2], p2, notp2, pbuf2 ) ;
acell1 bit3 ( x[3], y[3], notsub, Cin3, z[3], zbuf[3], p3, notp3, pbuf3 ) ;
ME_NAND2 g10 ( pbuf0, pbuf1, notplo ) ;
ME_NAND2 g11 ( p2, p3, notphi ) ;
ME_NMUX2B_B g12 ( p1, x[1], x[0], notglo ) ;
ME_NMUX2B_B g13 ( p3, x[3], x[2], notghi ) ;
ME_NMUX2B_B g14 ( notphi, notglo, notghi, g ) ;
ME_INV_A g15 ( notCin, Cin0 );
ME_INV_A g16 ( x[0], notg0 );
ME_NMUX2B g17 ( p0, notg0, notCin, Cin1 ) ;
ME_INV_A g18 ( notglo, glo );
ME_INV_A g19 ( glo, notglobuf );
ME_NMUX2B g20 ( notplo, notCin, notglobuf, Cin2 ) ;
ME_NAND3 g21 ( pbuf0, pbuf1, pbuf2, notp0to2 ) ;
ME_INV_A g22 ( x[2], notg2 );
ME_INV_A g23 ( notg2, g2 );
ME_NMUX2B g24 ( notp2, glo, g2, notg0to2 ) ;
ME_NMUX2B g25 ( notp0to2, notCin, notg0to2, Cin3 ) ;
ME_AND4_B g26 ( p0, p1, p2, p3, p ) ;
endmodule
module acell1 ( x, y, sub, Cin, z, zbuf, p, notp, pbuf ) ;
input x, y ;
input sub, Cin ;
output z, zbuf ;
output p, notp, pbuf;
// g is x for first bit
// bit 0
ME_XOR3_B g1 ( y, x, sub, p);
// ME_XOR2_B g1 ( sub, x, q);
// ME_XOR2_B g2 ( y, q, p);
ME_INV_A g3 ( p, notp );
ME_INV_A g5 ( notp, pbuf );
ME_NMUX2B_B g4 ( Cin, notp, pbuf, z) ;
ME_BUF_B g6 ( z, zbuf) ;
endmodule
module acell1a ( x, y, sub, notCin, z, zbuf, p, notp, pbuf ) ;
input x, y ;
input sub, notCin ;
output zbuf, z ;
output p, notp, pbuf;
// g is x for first bit
// bit 0
ME_XOR3_B g1 ( y, x, sub, p );
// ME_XOR2_B g1 ( sub, x, q);
// ME_XOR2_B g2 ( y, q, p);
ME_INV_A g3 ( p, notp );
ME_INV_A g5 ( notp, pbuf );
ME_NMUX2B_B g4 ( notCin, pbuf, notp, z) ;
ME_BUF_B g6 ( z, zbuf) ;
endmodule
// Meiko multiplier cells
//
module CS_bit ( SI, CI, Mul, notSiMulSR, notShift, Neg, notZero,
notSiMul, SA, CA );
input SI, CI, Mul, notSiMulSR, notShift, Neg, notZero ;
output notSiMul, SA, CA ;
ME_XNOR2_B g10 ( .a(Neg), .b(Mul), .z(notSiMul)) ;
ME_NMUX2B g11 ( .s(notShift), .a(notSiMulSR), .b(notSiMul), .z(notSiMulSh)) ;
ME_AND2_B g12 ( .a(notZero), .b(notSiMulSh), .z(Mulbit)) ;
ME_ADD3_B g13 ( .ci(SI), .a(CI), .b(Mulbit), .s(SA), .co(CA)) ;
endmodule
module CS_byte ( SI, CI, Mul, notSiMulSR, notShift, Neg, notZero,
notSiMul, SA, CA );
input [7:0] SI, CI, Mul, notSiMulSR;
input notShift, Neg, notZero ;
output [7:0] notSiMul, SA, CA ;
wire [7:0] notSiMulSh, Mulbit;
ME_XNOR2_B g00 ( .a(Neg), .b(Mul[0]), .z(notSiMul[0])) ;
ME_NMUX2B g01 ( .s(notShift), .a(notSiMulSR[0]), .b(notSiMul[0]), .z(notSiMulSh[0])) ;
ME_AND2_B g02 ( .a(notZero), .b(notSiMulSh[0]), .z(Mulbit[0])) ;
ME_ADD3_B g03 ( .ci(SI[0]), .a(CI[0]), .b(Mulbit[0]), .s(SA[0]), .co(CA[0])) ;
ME_XNOR2_B g10 ( .a(Neg), .b(Mul[1]), .z(notSiMul[1])) ;
ME_NMUX2B g11 ( .s(notShift), .a(notSiMulSR[1]), .b(notSiMul[1]), .z(notSiMulSh[1])) ;
ME_AND2_B g12 ( .a(notZero), .b(notSiMulSh[1]), .z(Mulbit[1])) ;
ME_ADD3_B g13 ( .ci(SI[1]), .a(CI[1]), .b(Mulbit[1]), .s(SA[1]), .co(CA[1])) ;
ME_XNOR2_B g20 ( .a(Neg), .b(Mul[2]), .z(notSiMul[2])) ;
ME_NMUX2B g21 ( .s(notShift), .a(notSiMulSR[2]), .b(notSiMul[2]), .z(notSiMulSh[2])) ;
ME_AND2_B g22 ( .a(notZero), .b(notSiMulSh[2]), .z(Mulbit[2])) ;
ME_ADD3_B g23 ( .ci(SI[2]), .a(CI[2]), .b(Mulbit[2]), .s(SA[2]), .co(CA[2])) ;
ME_XNOR2_B g30 ( .a(Neg), .b(Mul[3]), .z(notSiMul[3])) ;
ME_NMUX2B g31 ( .s(notShift), .a(notSiMulSR[3]), .b(notSiMul[3]), .z(notSiMulSh[3])) ;
ME_AND2_B g32 ( .a(notZero), .b(notSiMulSh[3]), .z(Mulbit[3])) ;
ME_ADD3_B g33 ( .ci(SI[3]), .a(CI[3]), .b(Mulbit[3]), .s(SA[3]), .co(CA[3])) ;
ME_XNOR2_B g40 ( .a(Neg), .b(Mul[4]), .z(notSiMul[4])) ;
ME_NMUX2B g41 ( .s(notShift), .a(notSiMulSR[4]), .b(notSiMul[4]), .z(notSiMulSh[4])) ;
ME_AND2_B g42 ( .a(notZero), .b(notSiMulSh[4]), .z(Mulbit[4])) ;
ME_ADD3_B g43 ( .ci(SI[4]), .a(CI[4]), .b(Mulbit[4]), .s(SA[4]), .co(CA[4])) ;
ME_XNOR2_B g50 ( .a(Neg), .b(Mul[5]), .z(notSiMul[5])) ;
ME_NMUX2B g51 ( .s(notShift), .a(notSiMulSR[5]), .b(notSiMul[5]), .z(notSiMulSh[5])) ;
ME_AND2_B g52 ( .a(notZero), .b(notSiMulSh[5]), .z(Mulbit[5])) ;
ME_ADD3_B g53 ( .ci(SI[5]), .a(CI[5]), .b(Mulbit[5]), .s(SA[5]), .co(CA[5])) ;
ME_XNOR2_B g60 ( .a(Neg), .b(Mul[6]), .z(notSiMul[6])) ;
ME_NMUX2B g61 ( .s(notShift), .a(notSiMulSR[6]), .b(notSiMul[6]), .z(notSiMulSh[6])) ;
ME_AND2_B g62 ( .a(notZero), .b(notSiMulSh[6]), .z(Mulbit[6])) ;
ME_ADD3_B g63 ( .ci(SI[6]), .a(CI[6]), .b(Mulbit[6]), .s(SA[6]), .co(CA[6])) ;
ME_XNOR2_B g70 ( .a(Neg), .b(Mul[7]), .z(notSiMul[7])) ;
ME_NMUX2B g71 ( .s(notShift), .a(notSiMulSR[7]), .b(notSiMul[7]), .z(notSiMulSh[7])) ;
ME_AND2_B g72 ( .a(notZero), .b(notSiMulSh[7]), .z(Mulbit[7])) ;
ME_ADD3_B g73 ( .ci(SI[7]), .a(CI[7]), .b(Mulbit[7]), .s(SA[7]), .co(CA[7])) ;
endmodule
module CS_STAGE_57 (SI, CI, D, Shift, Pos, Zero, SA, CA);
input[56:0] SI, CI, D;
input Shift, Pos, Zero;
output[56:0] SA;
output[56:0] CA;
ME_INV_C ls0 (.a(Shift), .x(_Sh));
ME_INV_B lz1 (.a(Zero), .x(_Ze));
ME_INV_C bs2 (.a(Shift), .x(B_notSh1));
ME_INV_C bs3 (.a(Shift), .x(B_notSh2) ) ;
ME_INV_B lb0 (.a(Pos), .x(Neg));
ME_INV_C g11 (.a(Pos), .x(B_Neg) ) ;
ME_INV_C g12 (.a(Zero), .x(B_nZ) ) ;
wire [56:0] notSiMul;
// Buffer first byte seperately
CS_byte c0 (SI[7:0], CI[7:0], D[7:0], notSiMul[8:1], _Sh, Neg, _Ze, notSiMul[7:0], SA[7:0], CA[7:0] );
CS_byte c1 (SI[15:8], CI[15:8], D[15:8], notSiMul[16:9], B_notSh1, B_Neg, B_nZ, notSiMul[15:8], SA[15:8], CA[15:8] );
CS_byte c2 (SI[23:16],CI[23:16], D[23:16], notSiMul[24:17], B_notSh1, B_Neg, B_nZ, notSiMul[23:16], SA[23:16], CA[23:16] );
CS_byte c3 (SI[31:24],CI[31:24], D[31:24], notSiMul[32:25], B_notSh1, B_Neg, B_nZ, notSiMul[31:24], SA[31:24], CA[31:24] );
CS_byte c4 (SI[39:32],CI[39:32], D[39:32], notSiMul[40:33], B_notSh2, B_Neg, B_nZ, notSiMul[39:32], SA[39:32], CA[39:32] );
CS_byte c5 (SI[47:40],CI[47:40], D[47:40], notSiMul[48:41], B_notSh2, B_Neg, B_nZ, notSiMul[47:40], SA[47:40], CA[47:40] );
CS_byte c6 (SI[55:48],CI[55:48], D[55:48], notSiMul[56:49], B_notSh2, B_Neg, B_nZ, notSiMul[55:48], SA[55:48], CA[55:48] );
ME_INV_C g15 (B_Neg, notSiMulMSB ) ;
CS_bit c7 (SI[56], CI[56], D[56], notSiMulMSB, B_notSh2, B_Neg, B_nZ, notSiMul[56], SA[56], CA[56] );
endmodule
// Meiko register macros
//
/* flip flop register library */
/* components followed by instances */
/* instances should be kept up to date with functional instances */
/* provided block of 1 2 4 8 32 cells to build registers from */
/* registers should also contain buffers to drive datapath lines */
module FDREG_1Bit ( clk, D, Q ) ; // free-running reg
input clk, D ;
output Q ;
ME_FD1 f0 ( .cp(clk), .d(D), .q(Q) ) ;
endmodule
module FDREG_1Byte ( clk, D, Q ) ;
input clk ;
input [7:0] D ;
output [7:0] Q ;
ME_FD1 f0 ( .cp(clk), .d(D[0]), .q(Q[0]) ) ;
ME_FD1 f1 ( .cp(clk), .d(D[1]), .q(Q[1]) ) ;
ME_FD1 f2 ( .cp(clk), .d(D[2]), .q(Q[2]) ) ;
ME_FD1 f3 ( .cp(clk), .d(D[3]), .q(Q[3]) ) ;
ME_FD1 f4 ( .cp(clk), .d(D[4]), .q(Q[4]) ) ;
ME_FD1 f5 ( .cp(clk), .d(D[5]), .q(Q[5]) ) ;
ME_FD1 f6 ( .cp(clk), .d(D[6]), .q(Q[6]) ) ;
ME_FD1 f7 ( .cp(clk), .d(D[7]), .q(Q[7]) ) ;
endmodule
module FREG_1Bit ( clk, E, D, Q ) ; // load-enable reg
input clk, D, E ;
output Q ;
ME_FD1E f0 ( .cp(clk), .te(E), .d(D), .q(Q) ) ;
endmodule
module FREG_1Byte ( clk, E, D, Q ) ;
input clk, E ;
input [7:0] D ;
output [7:0] Q ;
ME_FD1E f0 ( .cp(clk), .te(E), .d(D[0]), .q(Q[0]) ) ;
ME_FD1E f1 ( .cp(clk), .te(E), .d(D[1]), .q(Q[1]) ) ;
ME_FD1E f2 ( .cp(clk), .te(E), .d(D[2]), .q(Q[2]) ) ;
ME_FD1E f3 ( .cp(clk), .te(E), .d(D[3]), .q(Q[3]) ) ;
ME_FD1E f4 ( .cp(clk), .te(E), .d(D[4]), .q(Q[4]) ) ;
ME_FD1E f5 ( .cp(clk), .te(E), .d(D[5]), .q(Q[5]) ) ;
ME_FD1E f6 ( .cp(clk), .te(E), .d(D[6]), .q(Q[6]) ) ;
ME_FD1E f7 ( .cp(clk), .te(E), .d(D[7]), .q(Q[7]) ) ;
endmodule
/* real instances start here */
module ME_FDREG_1_57 ( clk, D, Q ) ; // free-running reg
input clk ;
input [56:0] D;
output [56:0] Q;
FDREG_1Byte m0 ( clk, D[7:0], Q[7:0] ) ;
FDREG_1Byte m1 ( clk, D[15:8], Q[15:8] ) ;
FDREG_1Byte m2 ( clk, D[23:16], Q[23:16] ) ;
FDREG_1Byte m3 ( clk, D[31:24], Q[31:24] ) ;
FDREG_1Byte m4 ( clk, D[39:32], Q[39:32] ) ;
FDREG_1Byte m5 ( clk, D[47:40], Q[47:40] ) ;
FDREG_1Byte m6 ( clk, D[55:48], Q[55:48] ) ;
FDREG_1Bit m70 ( clk, D[56], Q[56] ) ;
endmodule
module ME_FREGA_1_52 ( clk, enable, D, Q ) ;
input clk, enable ;
input [51:0] D;
output [51:0] Q;
ME_INV_B m20 ( enable, _E ) ;
ME_INV_C m21 ( _E, E1 ) ;
ME_INV_C m22 ( _E, E2 ) ;
FREG_1Byte m0 ( clk, E1, D[7:0], Q[7:0] ) ;
FREG_1Byte m1 ( clk, E1, D[15:8], Q[15:8] ) ;
FREG_1Byte m2 ( clk, E1, D[23:16], Q[23:16] ) ;
FREG_1Byte m3 ( clk, E1, D[31:24], Q[31:24] ) ;
FREG_1Byte m4 ( clk, E2, D[39:32], Q[39:32] ) ;
FREG_1Byte m5 ( clk, E2, D[47:40], Q[47:40] ) ;
FREG_1Bit m60 ( clk, E2, D[48], Q[48] ) ;
FREG_1Bit m61 ( clk, E2, D[49], Q[49] ) ;
FREG_1Bit m62 ( clk, E2, D[50], Q[50] ) ;
FREG_1Bit m63 ( clk, E2, D[51], Q[51] ) ;
endmodule
module ME_FREGA_1_54 ( clk, enable, D, Q ) ;
input clk, enable ;
input [53:0] D;
output [53:0] Q;
ME_INV_B m20 ( enable, _E ) ;
ME_INV_C m21 ( _E, E1 ) ;
ME_INV_C m22 ( _E, E2 ) ;
FREG_1Byte m0 ( clk, E1, D[7:0], Q[7:0] ) ;
FREG_1Byte m1 ( clk, E1, D[15:8], Q[15:8] ) ;
FREG_1Byte m2 ( clk, E1, D[23:16], Q[23:16] ) ;
FREG_1Byte m3 ( clk, E1, D[31:24], Q[31:24] ) ;
FREG_1Byte m4 ( clk, E2, D[39:32], Q[39:32] ) ;
FREG_1Byte m5 ( clk, E2, D[47:40], Q[47:40] ) ;
FREG_1Bit m60 ( clk, E2, D[48], Q[48] ) ;
FREG_1Bit m61 ( clk, E2, D[49], Q[49] ) ;
FREG_1Bit m62 ( clk, E2, D[50], Q[50] ) ;
FREG_1Bit m63 ( clk, E2, D[51], Q[51] ) ;
FREG_1Bit m64 ( clk, E2, D[52], Q[52] ) ;
FREG_1Bit m65 ( clk, E2, D[53], Q[53] ) ;
endmodule
module ME_FREGA_1_58 ( clk, enable, D, Q ) ;
input clk, enable ;
input [57:0] D;
output [57:0] Q;
ME_INV_B m20 ( enable, _E ) ;
ME_INV_C m21 ( _E, E1 ) ;
ME_INV_C m22 ( _E, E2 ) ;
FREG_1Byte m0 ( clk, E1, D[7:0], Q[7:0] ) ;
FREG_1Byte m1 ( clk, E1, D[15:8], Q[15:8] ) ;
FREG_1Byte m2 ( clk, E1, D[23:16], Q[23:16] ) ;
FREG_1Byte m3 ( clk, E1, D[31:24], Q[31:24] ) ;
FREG_1Byte m12 ( clk, E2, D[39:32], Q[39:32] ) ;
FREG_1Byte m13 ( clk, E2, D[47:40], Q[47:40] ) ;
FREG_1Byte m14 ( clk, E2, D[55:48], Q[55:48] ) ;
FREG_1Bit m15 ( clk, E2, D[56], Q[56] ) ;
FREG_1Bit m16 ( clk, E2, D[57], Q[57] ) ;
endmodule
module ME_FREGA_1_2 ( clk, enable, D, Q ) ;
input clk, enable ;
input [1:0] D;
output [1:0] Q;
FREG_1Bit m0 ( clk, enable, D[0], Q[0] ) ;
FREG_1Bit m1 ( clk, enable, D[1], Q[1] ) ;
endmodule
module ME_FREGA_1_3 ( clk, enable, D, Q ) ;
input clk, enable ;
input [2:0] D;
output [2:0] Q;
FREG_1Bit m0 ( clk, enable, D[0], Q[0] ) ;
FREG_1Bit m1 ( clk, enable, D[1], Q[1] ) ;
FREG_1Bit m2 ( clk, enable, D[2], Q[2] ) ;
endmodule
module ME_FREGA_1_8 ( clk, enable, D, Q ) ;
input clk, enable ;
input [7:0] D;
output [7:0] Q;
FREG_1Byte m0 ( clk, enable, D[7:0], Q[7:0] ) ;
endmodule
module ME_FREGA_1_9 ( clk, enable, D, Q ) ;
input clk, enable ;
input [8:0] D;
output [8:0] Q;
FREG_1Byte m0 ( clk, enable, D[7:0], Q[7:0] ) ;
FREG_1Bit m1 ( clk, enable, D[8], Q[8] ) ;
endmodule
module ME_FREGA_1_11 ( clk, enable, D, Q ) ;
input clk, enable ;
input [10:0] D;
output [10:0] Q;
ME_BUF_B m20 ( enable, E ) ;
FREG_1Byte m0 ( clk, E, D[7:0], Q[7:0] ) ;
FREG_1Bit m1 ( clk, E, D[8], Q[8] ) ;
FREG_1Bit m2 ( clk, E, D[9], Q[9] ) ;
FREG_1Bit m3 ( clk, E, D[10], Q[10] ) ;
endmodule
module ME_FREGA_1_13 ( clk, enable, D, Q ) ;
input clk, enable ;
input [12:0] D;
output [12:0] Q;
ME_BUF_B m20 ( enable, E ) ;
FREG_1Byte m0 ( clk, E, D[7:0], Q[7:0] ) ;
FREG_1Bit m1 ( clk, E, D[8], Q[8] ) ;
FREG_1Bit m2 ( clk, E, D[9], Q[9] ) ;
FREG_1Bit m3 ( clk, E, D[10], Q[10] ) ;
FREG_1Bit m4 ( clk, E, D[11], Q[11] ) ;
FREG_1Bit m5 ( clk, E, D[12], Q[12] ) ;
endmodule
module ME_FREGA_1_25 ( clk, enable, D, Q ) ;
input clk, enable ;
input [24:0] D;
output [24:0] Q;
ME_BUF_C m20 ( enable, E ) ;
FREG_1Byte m0 ( clk, E, D[7:0], Q[7:0] ) ;
FREG_1Byte m1 ( clk, E, D[15:8], Q[15:8] ) ;
FREG_1Byte m2 ( clk, E, D[23:16], Q[23:16] ) ;
FREG_1Bit m3 ( clk, E, D[24], Q[24] ) ;
endmodule
module ME_FREGA_1_26 ( clk, enable, D, Q ) ;
input clk, enable ;
input [25:0] D;
output [25:0] Q;
ME_BUF_C m20 ( enable, E ) ;
FREG_1Byte m0 ( clk, E, D[7:0], Q[7:0] ) ;
FREG_1Byte m1 ( clk, E, D[15:8], Q[15:8] ) ;
FREG_1Byte m2 ( clk, E, D[23:16], Q[23:16] ) ;
FREG_1Bit m3 ( clk, E, D[24], Q[24] ) ;
FREG_1Bit m4 ( clk, E, D[25], Q[25] ) ;
endmodule
module ME_FREGA_1_28 ( clk, enable, D, Q ) ;
input clk, enable ;
input [27:0] D;
output [27:0] Q;
ME_BUF_C m20 ( enable, E ) ;
FREG_1Byte m0 ( clk, E, D[7:0], Q[7:0] ) ;
FREG_1Byte m1 ( clk, E, D[15:8], Q[15:8] ) ;
FREG_1Byte m2 ( clk, E, D[23:16], Q[23:16] ) ;
FREG_1Bit m3 ( clk, E, D[24], Q[24] ) ;
FREG_1Bit m4 ( clk, E, D[25], Q[25] ) ;
FREG_1Bit m5 ( clk, E, D[26], Q[26] ) ;
FREG_1Bit m6 ( clk, E, D[27], Q[27] ) ;
endmodule
module ME_FREGA_1_30 ( clk, enable, D, Q ) ;
input clk, enable ;
input [29:0] D;
output [29:0] Q;
ME_BUF_C m20 ( enable, E ) ;
FREG_1Byte m0 ( clk, E, D[7:0], Q[7:0] ) ;
FREG_1Byte m1 ( clk, E, D[15:8], Q[15:8] ) ;
FREG_1Byte m2 ( clk, E, D[23:16], Q[23:16] ) ;
FREG_1Bit m3 ( clk, E, D[24], Q[24] ) ;
FREG_1Bit m4 ( clk, E, D[25], Q[25] ) ;
FREG_1Bit m5 ( clk, E, D[26], Q[26] ) ;
FREG_1Bit m6 ( clk, E, D[27], Q[27] ) ;
FREG_1Bit m7 ( clk, E, D[28], Q[28] ) ;
FREG_1Bit m8 ( clk, E, D[29], Q[29] ) ;
endmodule
module ME_FREGA_1_32 ( clk, enable, D, Q ) ;
input clk, enable ;
input [31:0] D;
output [31:0] Q;
ME_BUF_C m20 ( enable, E ) ;
FREG_1Byte m0 ( clk, E, D[7:0], Q[7:0] ) ;
FREG_1Byte m1 ( clk, E, D[15:8], Q[15:8] ) ;
FREG_1Byte m2 ( clk, E, D[23:16], Q[23:16] ) ;
FREG_1Byte m3 ( clk, E, D[31:24], Q[31:24] ) ;
endmodule
module ME_FREG_H_32 ( clk, H, D, Q ) ;
input clk;
input [3:0] H;
input [31:0] D;
output [31:0] Q;
// rlee: note HOLD is active low
// N1Z000 gnd(GND);
// ASFFHA f00 ( .Q( Q[ 0] ), .D( D[ 0] ), .SM(GND), .SI(GND), .H( H[ 0] ),
// .CK( clk )) ;
// ASFFHA f01 ( .Q( Q[ 1] ), .D( D[ 1] ), .SM(GND), .SI(GND), .H( H[ 0] ),
// .CK( clk )) ;
// ASFFHA f02 ( .Q( Q[ 2] ), .D( D[ 2] ), .SM(GND), .SI(GND), .H( H[ 0] ),
// .CK( clk )) ;
// ASFFHA f03 ( .Q( Q[ 3] ), .D( D[ 3] ), .SM(GND), .SI(GND), .H( H[ 0] ),
// .CK( clk )) ;
// ASFFHA f04 ( .Q( Q[ 4] ), .D( D[ 4] ), .SM(GND), .SI(GND), .H( H[ 0] ),
// .CK( clk )) ;
// ASFFHA f05 ( .Q( Q[ 5] ), .D( D[ 5] ), .SM(GND), .SI(GND), .H( H[ 0] ),
// .CK( clk )) ;
// ASFFHA f06 ( .Q( Q[ 6] ), .D( D[ 6] ), .SM(GND), .SI(GND), .H( H[ 0] ),
// .CK( clk )) ;
// ASFFHA f07 ( .Q( Q[ 7] ), .D( D[ 7] ), .SM(GND), .SI(GND), .H( H[ 0] ),
// .CK( clk )) ;
// ASFFHA f08 ( .Q( Q[ 8] ), .D( D[ 8] ), .SM(GND), .SI(GND), .H( H[ 1] ),
// .CK( clk )) ;
// ASFFHA f09 ( .Q( Q[ 9] ), .D( D[ 9] ), .SM(GND), .SI(GND), .H( H[ 1] ),
// .CK( clk )) ;
// ASFFHA f10 ( .Q( Q[10] ), .D( D[10] ), .SM(GND), .SI(GND), .H( H[ 1] ),
// .CK( clk )) ;
// ASFFHA f11 ( .Q( Q[11] ), .D( D[11] ), .SM(GND), .SI(GND), .H( H[ 1] ),
// .CK( clk )) ;
// ASFFHA f12 ( .Q( Q[12] ), .D( D[12] ), .SM(GND), .SI(GND), .H( H[ 1] ),
// .CK( clk )) ;
// ASFFHA f13 ( .Q( Q[13] ), .D( D[13] ), .SM(GND), .SI(GND), .H( H[ 1] ),
// .CK( clk )) ;
// ASFFHA f14 ( .Q( Q[14] ), .D( D[14] ), .SM(GND), .SI(GND), .H( H[ 1] ),
// .CK( clk )) ;
// ASFFHA f15 ( .Q( Q[15] ), .D( D[15] ), .SM(GND), .SI(GND), .H( H[ 1] ),
// .CK( clk )) ;
// ASFFHA f16 ( .Q( Q[16] ), .D( D[16] ), .SM(GND), .SI(GND), .H( H[ 2] ),
// .CK( clk )) ;
// ASFFHA f17 ( .Q( Q[17] ), .D( D[17] ), .SM(GND), .SI(GND), .H( H[ 2] ),
// .CK( clk )) ;
// ASFFHA f18 ( .Q( Q[18] ), .D( D[18] ), .SM(GND), .SI(GND), .H( H[ 2] ),
// .CK( clk )) ;
// ASFFHA f19 ( .Q( Q[19] ), .D( D[19] ), .SM(GND), .SI(GND), .H( H[ 2] ),
// .CK( clk )) ;
// ASFFHA f20 ( .Q( Q[20] ), .D( D[20] ), .SM(GND), .SI(GND), .H( H[ 2] ),
// .CK( clk )) ;
// ASFFHA f21 ( .Q( Q[21] ), .D( D[21] ), .SM(GND), .SI(GND), .H( H[ 2] ),
// .CK( clk )) ;
// ASFFHA f22 ( .Q( Q[22] ), .D( D[22] ), .SM(GND), .SI(GND), .H( H[ 2] ),
// .CK( clk )) ;
// ASFFHA f23 ( .Q( Q[23] ), .D( D[23] ), .SM(GND), .SI(GND), .H( H[ 2] ),
// .CK( clk )) ;
// ASFFHA f24 ( .Q( Q[24] ), .D( D[24] ), .SM(GND), .SI(GND), .H( H[ 3] ),
// .CK( clk )) ;
// ASFFHA f25 ( .Q( Q[25] ), .D( D[25] ), .SM(GND), .SI(GND), .H( H[ 3] ),
// .CK( clk )) ;
// ASFFHA f26 ( .Q( Q[26] ), .D( D[26] ), .SM(GND), .SI(GND), .H( H[ 3] ),
// .CK( clk )) ;
// ASFFHA f27 ( .Q( Q[27] ), .D( D[27] ), .SM(GND), .SI(GND), .H( H[ 3] ),
// .CK( clk )) ;
// ASFFHA f28 ( .Q( Q[28] ), .D( D[28] ), .SM(GND), .SI(GND), .H( H[ 3] ),
// .CK( clk )) ;
// ASFFHA f29 ( .Q( Q[29] ), .D( D[29] ), .SM(GND), .SI(GND), .H( H[ 3] ),
// .CK( clk )) ;
// ASFFHA f30 ( .Q( Q[30] ), .D( D[30] ), .SM(GND), .SI(GND), .H( H[ 3] ),
// .CK( clk )) ;
// ASFFHA f31 ( .Q( Q[31] ), .D( D[31] ), .SM(GND), .SI(GND), .H( H[ 3] ),
// .CK( clk )) ;
Mflipflop f00 ( .out(Q[0]), .in(D[0]), .clock(clk), .enable_l(H[0]) );
Mflipflop f01 ( .out(Q[1]), .in(D[1]), .clock(clk), .enable_l(H[0]) );
Mflipflop f02 ( .out(Q[2]), .in(D[2]), .clock(clk), .enable_l(H[0]) );
Mflipflop f03 ( .out(Q[3]), .in(D[3]), .clock(clk), .enable_l(H[0]) );
Mflipflop f04 ( .out(Q[4]), .in(D[4]), .clock(clk), .enable_l(H[0]) );
Mflipflop f05 ( .out(Q[5]), .in(D[5]), .clock(clk), .enable_l(H[0]) );
Mflipflop f06 ( .out(Q[6]), .in(D[6]), .clock(clk), .enable_l(H[0]) );
Mflipflop f07 ( .out(Q[7]), .in(D[7]), .clock(clk), .enable_l(H[0]) );
Mflipflop f08 ( .out(Q[8]), .in(D[8]), .clock(clk), .enable_l(H[1]) );
Mflipflop f09 ( .out(Q[9]), .in(D[9]), .clock(clk), .enable_l(H[1]) );
Mflipflop f10 ( .out(Q[10]), .in(D[10]), .clock(clk), .enable_l(H[1]) );
Mflipflop f11 ( .out(Q[11]), .in(D[11]), .clock(clk), .enable_l(H[1]) );
Mflipflop f12 ( .out(Q[12]), .in(D[12]), .clock(clk), .enable_l(H[1]) );
Mflipflop f13 ( .out(Q[13]), .in(D[13]), .clock(clk), .enable_l(H[1]) );
Mflipflop f14 ( .out(Q[14]), .in(D[14]), .clock(clk), .enable_l(H[1]) );
Mflipflop f15 ( .out(Q[15]), .in(D[15]), .clock(clk), .enable_l(H[1]) );
Mflipflop f16 ( .out(Q[16]), .in(D[16]), .clock(clk), .enable_l(H[2]) );
Mflipflop f17 ( .out(Q[17]), .in(D[17]), .clock(clk), .enable_l(H[2]) );
Mflipflop f18 ( .out(Q[18]), .in(D[18]), .clock(clk), .enable_l(H[2]) );
Mflipflop f19 ( .out(Q[19]), .in(D[19]), .clock(clk), .enable_l(H[2]) );
Mflipflop f20 ( .out(Q[20]), .in(D[20]), .clock(clk), .enable_l(H[2]) );
Mflipflop f21 ( .out(Q[21]), .in(D[21]), .clock(clk), .enable_l(H[2]) );
Mflipflop f22 ( .out(Q[22]), .in(D[22]), .clock(clk), .enable_l(H[2]) );
Mflipflop f23 ( .out(Q[23]), .in(D[23]), .clock(clk), .enable_l(H[2]) );
Mflipflop f24 ( .out(Q[24]), .in(D[24]), .clock(clk), .enable_l(H[3]) );
Mflipflop f25 ( .out(Q[25]), .in(D[25]), .clock(clk), .enable_l(H[3]) );
Mflipflop f26 ( .out(Q[26]), .in(D[26]), .clock(clk), .enable_l(H[3]) );
Mflipflop f27 ( .out(Q[27]), .in(D[27]), .clock(clk), .enable_l(H[3]) );
Mflipflop f28 ( .out(Q[28]), .in(D[28]), .clock(clk), .enable_l(H[3]) );
Mflipflop f29 ( .out(Q[29]), .in(D[29]), .clock(clk), .enable_l(H[3]) );
Mflipflop f30 ( .out(Q[30]), .in(D[30]), .clock(clk), .enable_l(H[3]) );
Mflipflop f31 ( .out(Q[31]), .in(D[31]), .clock(clk), .enable_l(H[3]) );
endmodule
module ME_FREGA_1_64 ( clk, enable, D, Q ) ;
input clk, enable ;
input [63:0] D;
output [63:0] Q;
ME_INV_B m20 ( enable, _E ) ;
ME_INV_C m21 ( _E, E1 ) ;
ME_INV_C m22 ( _E, E2 ) ;
FREG_1Byte m0 ( clk, E1, D[7:0], Q[7:0] ) ;
FREG_1Byte m1 ( clk, E1, D[15:8], Q[15:8] ) ;
FREG_1Byte m2 ( clk, E1, D[23:16], Q[23:16] ) ;
FREG_1Byte m3 ( clk, E1, D[31:24], Q[31:24] ) ;
FREG_1Byte m4 ( clk, E2, D[39:32], Q[39:32] ) ;
FREG_1Byte m5 ( clk, E2, D[47:40], Q[47:40] ) ;
FREG_1Byte m6 ( clk, E2, D[55:48], Q[55:48] ) ;
FREG_1Byte m7 ( clk, E2, D[63:56], Q[63:56] ) ;
endmodule
// Meiko register macros
//
/* 2 input flip flop register library */
/* components followed by instances */
/* instances should be kept up to date with functional instances */
/* provided block of 1 2 4 8 32 cells to build registers from */
/* registers should also contain buffers to drive datapath lines */
module FREG_2bit ( clk, E, notA, A, d0, d1, Q ) ;
input clk, notA, A, d0, d1, E ;
output Q ;
wire x;
ME_NMUX2BA n0 ( .nota(notA), .a(A), .d0(d0), .d1(d1), .notX(x));
ME_FD1E f0 (.cp(clk), .te(E), .d(x), .qn(Q)) ;
endmodule
/* real instances start here */
/* // 4-bit reg with 2:1 mux built in
module ME_FREGA_2_4 ( clk, hold, S, d0, d1, Q ) ;
input clk, hold, S;
input [3:0] d0, d1;
output [3:0] Q;
// N1Z000 gnd (GND);
// AMUXFFA ff ( .DA0(d0[0]), .DA1(d0[1]), .DA2(d0[2]), .DA3(d0[3]),
// .DB0(d1[0]), .DB1(d1[1]), .DB2(d1[2]), .DB3(d1[3]),
// .CK(clk), .HLD(hold), .SM(GND), .SI(GND), .S(S),
// .DO0(Q[0]), .DO1(Q[1]), .DO2(Q[2]), .DO3(Q[3]) );
reg [3:0] mux_output;
wire enable_low;
always @ (S or d0 or d1)
case (S) // synopsys parallel_case full_case
0: mux_output = d0;
1: mux_output = d1;
default mux_output = 'bx;
endcase
assign enable_low = ~hold;
Mflipflop_4 f0 (.out(Q[3:0]), .din(mux_output[3:0]), .clock(clk), .enable_l(enable_low) );
endmodule
module ME_FREGA_2_32 ( clk, hold, S, d0, d1, Q ) ;
input clk, hold, S;
input [31:0] d0, d1;
output [31:0] Q;
// N1Z000 gnd (GND);
// AMUXFFA f0 ( .DA0(d0[0]), .DA1(d0[1]), .DA2(d0[2]), .DA3(d0[3]),
// .DB0(d1[0]), .DB1(d1[1]), .DB2(d1[2]), .DB3(d1[3]),
// .CK(clk), .HLD(hold), .SM(GND), .SI(GND), .S(S),
// .DO0(Q[0]), .DO1(Q[1]), .DO2(Q[2]), .DO3(Q[3]) );
//
// AMUXFFA f1 ( .DA0(d0[4]), .DA1(d0[5]), .DA2(d0[6]), .DA3(d0[7]),
// .DB0(d1[4]), .DB1(d1[5]), .DB2(d1[6]), .DB3(d1[7]),
// .CK(clk), .HLD(hold), .SM(GND), .SI(GND), .S(S),
// .DO0(Q[4]), .DO1(Q[5]), .DO2(Q[6]), .DO3(Q[7]) );
//
// AMUXFFA f2 ( .DA0(d0[8]), .DA1(d0[9]), .DA2(d0[10]), .DA3(d0[11]),
// .DB0(d1[8]), .DB1(d1[9]), .DB2(d1[10]), .DB3(d1[11]),
// .CK(clk), .HLD(hold), .SM(GND), .SI(GND), .S(S),
// .DO0(Q[8]), .DO1(Q[9]), .DO2(Q[10]), .DO3(Q[11]) );
//
// AMUXFFA f3 ( .DA0(d0[12]), .DA1(d0[13]), .DA2(d0[14]), .DA3(d0[15]),
// .DB0(d1[12]), .DB1(d1[13]), .DB2(d1[14]), .DB3(d1[15]),
// .CK(clk), .HLD(hold), .SM(GND), .SI(GND), .S(S),
// .DO0(Q[12]), .DO1(Q[13]), .DO2(Q[14]), .DO3(Q[15]) );
//
// AMUXFFA f4 ( .DA0(d0[16]), .DA1(d0[17]), .DA2(d0[18]), .DA3(d0[19]),
// .DB0(d1[16]), .DB1(d1[17]), .DB2(d1[18]), .DB3(d1[19]),
// .CK(clk), .HLD(hold), .SM(GND), .SI(GND), .S(S),
// .DO0(Q[16]), .DO1(Q[17]), .DO2(Q[18]), .DO3(Q[19]) );
//
// AMUXFFA f5 ( .DA0(d0[20]), .DA1(d0[21]), .DA2(d0[22]), .DA3(d0[23]),
// .DB0(d1[20]), .DB1(d1[21]), .DB2(d1[22]), .DB3(d1[23]),
// .CK(clk), .HLD(hold), .SM(GND), .SI(GND), .S(S),
// .DO0(Q[20]), .DO1(Q[21]), .DO2(Q[22]), .DO3(Q[23]) );
//
// AMUXFFA f6 ( .DA0(d0[24]), .DA1(d0[25]), .DA2(d0[26]), .DA3(d0[27]),
// .DB0(d1[24]), .DB1(d1[25]), .DB2(d1[26]), .DB3(d1[27]),
// .CK(clk), .HLD(hold), .SM(GND), .SI(GND), .S(S),
// .DO0(Q[24]), .DO1(Q[25]), .DO2(Q[26]), .DO3(Q[27]) );
//
// AMUXFFA f7 ( .DA0(d0[28]), .DA1(d0[29]), .DA2(d0[30]), .DA3(d0[31]),
// .DB0(d1[28]), .DB1(d1[29]), .DB2(d1[30]), .DB3(d1[31]),
// .CK(clk), .HLD(hold), .SM(GND), .SI(GND), .S(S),
// .DO0(Q[28]), .DO1(Q[29]), .DO2(Q[30]), .DO3(Q[31]) );
reg [31:0] mux_output;
wire enable_low;
always @ (S or d0 or d1)
case (S) // synopsys parallel_case full_case
0: mux_output[31:0] = d0[31:0];
1: mux_output[31:0] = d1[31:0];
default mux_output = 'bx;
endcase
assign enable_low = ~hold;
Mflipflop_32 f0 (.out(Q[31:0]), .din(mux_output[31:0]), .clock(clk), .enable_l(enable_low) );
endmodule
*/
module ME_FREGA_2_58 ( clk, enable, A, d0, d1, Q ) ;
input clk, enable, A ;
input [57:0] d0, d1 ;
output [57:0] Q ;
ME_INV_C ia0 ( A, notA ) ;
ME_INV_B ia1 ( A, _A ) ;
ME_INV_C ba1 ( _A, Abuf1 ) ;
ME_INV_C ba2 ( _A, Abuf2 ) ;
ME_INV_B ie0 ( enable, _E ) ;
ME_INV_C ie1 ( _E, E1 ) ;
ME_INV_C ie2 ( _E, E2 ) ;
FREG_2byte f00 ( clk, E1, notA, Abuf1, d0[7:0], d1[7:0], Q[7:0] ) ;
FREG_2byte f01 ( clk, E1, notA, Abuf1, d0[15:8], d1[15:8], Q[15:8] ) ;
FREG_2byte f02 ( clk, E1, notA, Abuf1, d0[23:16], d1[23:16], Q[23:16] ) ;
FREG_2byte f03 ( clk, E1, notA, Abuf1, d0[31:24], d1[31:24], Q[31:24] ) ;
FREG_2byte m12 ( clk, E2, notA, Abuf2, d0[39:32], d1[39:32], Q[39:32] ) ;
FREG_2byte m13 ( clk, E2, notA, Abuf2, d0[47:40], d1[47:40], Q[47:40] ) ;
FREG_2byte m14 ( clk, E2, notA, Abuf2, d0[55:48], d1[55:48], Q[55:48] ) ;
FREG_2bit m15 ( clk, E2, notA, Abuf2, d0[56], d1[56], Q[56] ) ;
FREG_2bit m16 ( clk, E2, notA, Abuf2, d0[57], d1[57], Q[57] ) ;
endmodule
// Meiko register macros
//
/* 4 input flip flop register library */
/* components followed by instances */
/* instances should be kept up to date with functional instances */
/* components */
/* provided block of 1 8 cells to build registers from */
/* registers should also contain buffers to drive datapath lines */
module FREG_S_4Bit ( clk, E, A, B, d0, d1, d2, d3, Q, Qbuf ) ;
input clk, E, A, B, d0, d1, d2, d3 ;
output Q, Qbuf ;
ME_MUX4B n0 ( .a(A), .b(B), .d0(d0), .d1(d1), .d2(d2), .d3(d3), .z(x) );
ME_FD1E f0 ( .cp(clk), .te(E), .d(x), .q(Q), .qn(QN));
ME_INV_B b0 ( .a(QN), .x(Qbuf));
endmodule
module FREG_4Bit ( clk, E, A, B, d0, d1, d2, d3, Q ) ;
input clk, E, A, B, d0, d1, d2, d3 ;
output Q ;
ME_MUX4B n0 ( .a(A), .b(B), .d0(d0), .d1(d1), .d2(d2), .d3(d3), .z(x) );
ME_FD1E f0 ( .cp(clk), .te(E), .d(x), .q(Q));
endmodule
module FREG_4Byte ( clk, E, A, B, d0, d1, d2, d3, Q ) ;
input clk, E, A, B;
input [7:0] d0, d1, d2, d3 ;
output [7:0] Q ;
FREG_4Bit f0 ( clk, E, A, B, d0[0], d1[0], d2[0], d3[0], Q[0] ) ;
FREG_4Bit f1 ( clk, E, A, B, d0[1], d1[1], d2[1], d3[1], Q[1] ) ;
FREG_4Bit f2 ( clk, E, A, B, d0[2], d1[2], d2[2], d3[2], Q[2] ) ;
FREG_4Bit f3 ( clk, E, A, B, d0[3], d1[3], d2[3], d3[3], Q[3] ) ;
FREG_4Bit f4 ( clk, E, A, B, d0[4], d1[4], d2[4], d3[4], Q[4] ) ;
FREG_4Bit f5 ( clk, E, A, B, d0[5], d1[5], d2[5], d3[5], Q[5] ) ;
FREG_4Bit f6 ( clk, E, A, B, d0[6], d1[6], d2[6], d3[6], Q[6] ) ;
FREG_4Bit f7 ( clk, E, A, B, d0[7], d1[7], d2[7], d3[7], Q[7] ) ;
endmodule
/* real instances start here */
module ME_FREGA_4_13 ( clk, enable, A, B, d0, d1, d2, d3, Q ) ;
input clk, enable, A, B ;
input [12:0] d0, d1, d2, d3 ;
output [12:0] Q ;
ME_BUF_C m20 ( enable, E ) ;
ME_BUF_C m21 ( A, Abuf ) ;
ME_BUF_C m22 ( B, Bbuf ) ;
FREG_4Byte f1 ( clk, E, Abuf, Bbuf,
d0[7:0], d1[7:0], d2[7:0], d3[7:0], Q[7:0] ) ;
FREG_4Bit f3 ( clk, E, Abuf, Bbuf, d0[8], d1[8], d2[8], d3[8], Q[8] ) ;
FREG_4Bit f4 ( clk, E, Abuf, Bbuf, d0[9], d1[9], d2[9], d3[9], Q[9] ) ;
FREG_4Bit f5 ( clk, E, Abuf, Bbuf, d0[10], d1[10], d2[10], d3[10], Q[10] ) ;
FREG_4Bit f6 ( clk, E, Abuf, Bbuf, d0[11], d1[11], d2[11], d3[11], Q[11] ) ;
FREG_4Bit f7 ( clk, E, Abuf, Bbuf, d0[12], d1[12], d2[12], d3[12], Q[12] ) ;
endmodule
module ME_FREGA_S_4_13 ( clk, enable, A, B, d0, d1, d2, d3, Q, Qbuf) ;
input clk, enable, A, B ;
input [12:0] d0, d1, d2, d3 ;
output [12:0] Q, Qbuf;
ME_BUF_C m20 ( enable, E ) ;
ME_BUF_C m21 ( A, Abuf ) ;
ME_BUF_C m22 ( B, Bbuf ) ;
FREG_S_4Bit f0 ( clk, E, Abuf, Bbuf, d0[ 0], d1[ 0], d2[ 0], d3[ 0], Q[ 0], Qbuf[ 0] ) ;
FREG_S_4Bit f1 ( clk, E, Abuf, Bbuf, d0[ 1], d1[ 1], d2[ 1], d3[ 1], Q[ 1], Qbuf[ 1] ) ;
FREG_S_4Bit f2 ( clk, E, Abuf, Bbuf, d0[ 2], d1[ 2], d2[ 2], d3[ 2], Q[ 2], Qbuf[ 2] ) ;
FREG_S_4Bit f3 ( clk, E, Abuf, Bbuf, d0[ 3], d1[ 3], d2[ 3], d3[ 3], Q[ 3], Qbuf[ 3] ) ;
FREG_S_4Bit f4 ( clk, E, Abuf, Bbuf, d0[ 4], d1[ 4], d2[ 4], d3[ 4], Q[ 4], Qbuf[ 4] ) ;
FREG_S_4Bit f5 ( clk, E, Abuf, Bbuf, d0[ 5], d1[ 5], d2[ 5], d3[ 5], Q[ 5], Qbuf[ 5] ) ;
FREG_S_4Bit f6 ( clk, E, Abuf, Bbuf, d0[ 6], d1[ 6], d2[ 6], d3[ 6], Q[ 6], Qbuf[ 6] ) ;
FREG_S_4Bit f7 ( clk, E, Abuf, Bbuf, d0[ 7], d1[ 7], d2[ 7], d3[ 7], Q[ 7], Qbuf[ 7] ) ;
FREG_S_4Bit f8 ( clk, E, Abuf, Bbuf, d0[ 8], d1[ 8], d2[ 8], d3[ 8], Q[ 8], Qbuf[ 8] ) ;
FREG_S_4Bit f9 ( clk, E, Abuf, Bbuf, d0[ 9], d1[ 9], d2[ 9], d3[ 9], Q[ 9], Qbuf[ 9] ) ;
FREG_S_4Bit fa ( clk, E, Abuf, Bbuf, d0[10], d1[10], d2[10], d3[10], Q[10], Qbuf[10] ) ;
FREG_S_4Bit fb ( clk, E, Abuf, Bbuf, d0[11], d1[11], d2[11], d3[11], Q[11], Qbuf[11] ) ;
FREG_S_4Bit fc ( clk, E, Abuf, Bbuf, d0[12], d1[12], d2[12], d3[12], Q[12], Qbuf[12] ) ;
endmodule
// Meiko register macros
//
/* 5 input flip flop register library */
/* components followed by instances */
/* instances should be kept up to date with functional instances */
/* components */
/* provided block of 1 8 cells to build registers from */
/* registers should also contain buffers to drive datapath lines */
module FREG_S_5bit ( clk, E, A, B, C, d0, d1, d2, d3, d4, Q, Qbuf, QN) ;
input clk, E, A, B, C, d0, d1, d2, d3, d4 ;
output Q, Qbuf, QN ;
//ME_TIEOFF toff (vdd,);
ME_MUX4B m0 (.a(A), .b(B), .d0(d0), .d1(d1), .d2(d2), .d3(d3), .z(T0));
ME_NMUX2B n0 (.s(C), .a(T0), .b(d4), .z(x)) ;
ME_FD1E f0 (.cp(clk), .te(E), .d(x), .q(QN), .qn(Q));
ME_INV_B b0 (.a(QN), .x(Qbuf));
endmodule
module FREG_5bit ( clk, E, A, B, C, d0, d1, d2, d3, d4, Q, Qbuf) ;
input clk, E, A, B, C, d0, d1, d2, d3, d4 ;
output Q, Qbuf ;
ME_MUX4B m0 (.a(A), .b(B), .d0(d0), .d1(d1), .d2(d2), .d3(d3), .z(T0));
ME_NMUX2B n0 (.s(C), .a(T0), .b(d4), .z(x)) ;
ME_FD1E f0 (.cp(clk), .te(E), .d(x), .q(QN), .qn(Q));
ME_INV_B b0 (.a(QN), .x(Qbuf));
endmodule
module FREG_5byte ( clk, E, A, B, C, d0, d1, d2, d3, d4, Q, Qbuf) ;
input clk, E, A, B, C;
input [7:0] d0, d1, d2, d3, d4 ;
output [7:0] Q, Qbuf;
FREG_5bit f0 ( clk, E, A, B, C, d0[0], d1[0], d2[0], d3[0], d4[0], Q[0], Qbuf[0]) ;
FREG_5bit f1 ( clk, E, A, B, C, d0[1], d1[1], d2[1], d3[1], d4[1], Q[1], Qbuf[1]) ;
FREG_5bit f2 ( clk, E, A, B, C, d0[2], d1[2], d2[2], d3[2], d4[2], Q[2], Qbuf[2]) ;
FREG_5bit f3 ( clk, E, A, B, C, d0[3], d1[3], d2[3], d3[3], d4[3], Q[3], Qbuf[3]) ;
FREG_5bit f4 ( clk, E, A, B, C, d0[4], d1[4], d2[4], d3[4], d4[4], Q[4], Qbuf[4]) ;
FREG_5bit f5 ( clk, E, A, B, C, d0[5], d1[5], d2[5], d3[5], d4[5], Q[5], Qbuf[5]) ;
FREG_5bit f6 ( clk, E, A, B, C, d0[6], d1[6], d2[6], d3[6], d4[6], Q[6], Qbuf[6]) ;
FREG_5bit f7 ( clk, E, A, B, C, d0[7], d1[7], d2[7], d3[7], d4[7], Q[7], Qbuf[7]) ;
endmodule
/* real instances start here */
module ME_FREGA_5_58 ( clk, enable, A, B, C, d0, d1, d2, d3, d4, Q, Qbuf, notBSign) ;
input clk, enable, A, B, C ;
input [57:0] d0, d1, d2, d3, d4 ;
output [57:0] Q, Qbuf;
output notBSign;
ME_INV_B ie1 ( enable, _E1 ) ;
ME_INV_C ie2 ( _E1, E1 ) ;
ME_INV_C ie3 ( _E1, E2 ) ;
ME_INV_B ia0 ( A, _A ) ;
ME_INV_C ia1 ( _A, A1 ) ;
ME_INV_C ia2 ( _A, A2 ) ;
ME_INV_C ia3 ( _A, A3 ) ;
ME_INV_B ib0 ( B, _B ) ;
ME_INV_C ib1 ( _B, B1 ) ;
ME_INV_C ib2 ( _B, B2 ) ;
ME_INV_B ic0 ( C, _C ) ;
ME_INV_C ic1 ( _C, C1 ) ;
ME_INV_C ic2 ( _C, C2 ) ;
FREG_5byte f0 (clk, E1, A1, B1, C1,
d0[7:0], d1[7:0], d2[7:0], d3[7:0], d4[7:0], Q[7:0] ,Qbuf[7:0] );
FREG_5byte f1 (clk, E1, A1, B1, C1,
d0[15:8], d1[15:8], d2[15:8], d3[15:8], d4[15:8], Q[15:8] ,Qbuf[15:8] );
FREG_5byte f2 (clk, E1, A1, B1, C1,
d0[23:16],d1[23:16],d2[23:16],d3[23:16],d4[23:16],Q[23:16],Qbuf[23:16]);
FREG_5byte f3 (clk, E1, A2, B1, C1,
d0[31:24],d1[31:24],d2[31:24],d3[31:24],d4[31:24],Q[31:24],Qbuf[31:24]);
FREG_5byte f4 (clk, E2, A2, B2, C2,
d0[39:32],d1[39:32],d2[39:32],d3[39:32],d4[39:32],Q[39:32],Qbuf[39:32]);
FREG_5byte f5 (clk, E2, A2, B2, C2,
d0[47:40],d1[47:40],d2[47:40],d3[47:40],d4[47:40],Q[47:40],Qbuf[47:40]);
FREG_5byte f6 (clk, E2, A3, B2, C2,
d0[55:48],d1[55:48],d2[55:48],d3[55:48],d4[55:48],Q[55:48],Qbuf[55:48]);
FREG_5bit f7 (clk, E2, A3, B2, C2,
d0[56], d1[56], d2[56], d3[56], d4[56], Q[56] ,Qbuf[56]) ;
FREG_S_5bit f8 (clk, E2, A3, B2, C2,
d0[57], d1[57], d2[57], d3[57], d4[57], Q[57] ,Qbuf[57], notBSign) ;
endmodule
// Meiko register macros
//
/* 8 input flip flop register library */
/* components followed by instances */
/* instances should be kept up to date with functional instances */
/* components */
/* provided block of 1 8 cells to build registers from */
/* registers should also contain buffers to drive datapath lines */
module FREG_8bit ( clk, E, _A, _B, C, d0, d1, d2, d3, d4, d5, d6, d7, Q, Qbuf ) ;
input clk, E, _A, _B, C, d0, d1, d2, d3, d4, d5, d6, d7 ;
output Q, Qbuf ;
ME_INV_A i0 ( .a(_A), .x(A));
ME_INV_A i1 ( .a(_B), .x(B));
ME_MUX8B_B n0 (.a(A), .b(B), .c(C),
.d0(d0), .d1(d1), .d2(d2), .d3(d3),
.d4(d4), .d5(d5), .d6(d6), .d7(d7), .f(x));
ME_FD1E f0 (.cp(clk), .te(E), .d(x), .q(Q), .qn(QN));
ME_INV_B b0 (.a(QN), .x(Qbuf));
endmodule
module FREG_8bit_s ( clk, E, _A, _B, C, d0, d1, d2, d3, d4, d5, d6, d7, Q, Qbuf, QTs, Qs) ;
input clk, E, _A, _B, C, d0, d1, d2, d3, d4, d5, d6, d7 ;
output Q, Qbuf, QTs, Qs;
// Bit 56 is critical and so contains two extra latches which
// drive the rounding select value
ME_INV_A i0 ( _A, A);
ME_INV_A i1 ( _B, B);
ME_MUX8B_B n0 ( A, B, C, d0, d1, d2, d3, d4, d5, d6, d7, x );
ME_FD1E_B f0 ( clk, E, x, Q, QN);
ME_INV_B b0 ( QN, Qbuf);
ME_NMUX2B_B sm0 ( E, QNs, x, Ds );
ME_FD1_B sf0 ( clk, Ds, Qs, QNs);
ME_FD1E_B f1 ( clk, E, x, QTs, );
endmodule
module FREG_8byte ( clk, E, A, B, C, d0, d1, d2, d3, d4, d5, d6, d7, Q, Qbuf ) ;
input clk, E, A, B, C;
input [7:0] d0, d1, d2, d3, d4, d5, d6, d7 ;
output [7:0] Q, Qbuf ;
FREG_8bit f0 ( clk, E, A, B, C, d0[0], d1[0], d2[0], d3[0],
d4[0], d5[0], d6[0], d7[0], Q[0], Qbuf[0] ) ;
FREG_8bit f1 ( clk, E, A, B, C, d0[1], d1[1], d2[1], d3[1],
d4[1], d5[1], d6[1], d7[1], Q[1], Qbuf[1]) ;
FREG_8bit f2 ( clk, E, A, B, C, d0[2], d1[2], d2[2], d3[2],
d4[2], d5[2], d6[2], d7[2], Q[2], Qbuf[2]) ;
FREG_8bit f3 ( clk, E, A, B, C, d0[3], d1[3], d2[3], d3[3],
d4[3], d5[3], d6[3], d7[3], Q[3], Qbuf[3]) ;
FREG_8bit f4 ( clk, E, A, B, C, d0[4], d1[4], d2[4], d3[4],
d4[4], d5[4], d6[4], d7[4], Q[4], Qbuf[4]) ;
FREG_8bit f5 ( clk, E, A, B, C, d0[5], d1[5], d2[5], d3[5],
d4[5], d5[5], d6[5], d7[5], Q[5], Qbuf[5]) ;
FREG_8bit f6 ( clk, E, A, B, C, d0[6], d1[6], d2[6], d3[6],
d4[6], d5[6], d6[6], d7[6], Q[6], Qbuf[6]) ;
FREG_8bit f7 ( clk, E, A, B, C, d0[7], d1[7], d2[7], d3[7],
d4[7], d5[7], d6[7], d7[7], Q[7], Qbuf[7]) ;
endmodule
/* real instances start here */
module ME_FREGA_8_58 ( clk, enable, A, B, C, d0, d1, d2, d3, d4, d5, d6, d7, Q, Qbuf, QTs, Qs) ;
input clk, enable, A, B, C ;
input [57:0] d0, d1, d2, d3, d4, d5, d6, d7 ;
output [57:0] Q, Qbuf;
output QTs, Qs ;
ME_INV_C ie0 ( enable, _E ) ;
ME_INV_C ie1 ( _E, E1 ) ;
ME_INV_C ie2 ( _E, E2 ) ;
ME_INV_C ie3 ( _E, E3 ) ;
ME_INV_C ie4 ( _E, E4 ) ;
ME_INV_C m21 ( A, Abuf ) ;
ME_INV_C m22 ( B, Bbuf ) ;
ME_INV_B ic0 ( C, _C ) ;
ME_INV_C ic1 ( _C, C1 ) ;
ME_INV_C ic2 ( _C, C2 ) ;
FREG_8byte f00 (clk, E1, Abuf, Bbuf, C1,
d0[7:0], d1[7:0], d2[7:0], d3[7:0],
d4[7:0], d5[7:0], d6[7:0], d7[7:0], Q[7:0], Qbuf[7:0]) ;
FREG_8byte f01 (clk, E1, Abuf, Bbuf, C1,
d0[15:8], d1[15:8], d2[15:8], d3[15:8],
d4[15:8], d5[15:8], d6[15:8], d7[15:8], Q[15:8], Qbuf[15:8]);
FREG_8byte f02 (clk, E2, Abuf, Bbuf, C1,
d0[23:16], d1[23:16], d2[23:16], d3[23:16],
d4[23:16], d5[23:16], d6[23:16], d7[23:16],
Q[23:16], Qbuf[23:16]);
FREG_8byte f03 (clk, E2, Abuf, Bbuf, C1,
d0[31:24], d1[31:24], d2[31:24], d3[31:24],
d4[31:24], d5[31:24], d6[31:24], d7[31:24],
Q[31:24], Qbuf[31:24]);
FREG_8byte m12 (clk, E3, Abuf, Bbuf, C2,
d0[39:32], d1[39:32], d2[39:32], d3[39:32],
d4[39:32], d5[39:32], d6[39:32], d7[39:32],
Q[39:32], Qbuf[39:32]);
FREG_8byte m13 (clk, E3, Abuf, Bbuf, C2,
d0[47:40], d1[47:40], d2[47:40], d3[47:40],
d4[47:40], d5[47:40], d6[47:40], d7[47:40],
Q[47:40], Qbuf[47:40]);
FREG_8byte m14 (clk, E4, Abuf, Bbuf, C2,
d0[55:48], d1[55:48], d2[55:48], d3[55:48],
d4[55:48], d5[55:48], d6[55:48], d7[55:48],
Q[55:48], Qbuf[55:48]);
/* This is the special round bit */
FREG_8bit_s m15 (clk, E4, Abuf, Bbuf, C2,
d0[56], d1[56], d2[56], d3[56],
d4[56], d5[56], d6[56], d7[56], Q[56], Qbuf[56], QTs, Qs);
FREG_8bit m16 (clk, E4, Abuf, Bbuf, C2,
d0[57], d1[57], d2[57], d3[57],
d4[57], d5[57], d6[57], d7[57], Q[57], Qbuf[57]);
endmodule
// Meiko ymuxslice macros
//
module ME_Ymux_Bit (S1, S2, S3, D1, D2, D3, Z);
input S1, S2, S3;
input D1, D2, D3;
output Z;
ME_NAND2 d0 (.a(S1), .b(D1), .z(t0));
ME_NAND2 d1 (.a(S2), .b(D2), .z(t1));
ME_NAND2 d2 (.a(S3), .b(D3), .z(t2));
ME_NAND3 d3 (.a(t0), .b(t1), .c(t2), .z(Z));
endmodule
module ME_YmuxSlice (notS1, notS2, notS3,
/* dhn--01/10/91 notS1A, notS2A, notS3A, */
D1, D2, D3,
Z);
input notS1, notS2, notS3;
/* dhn--01/10/91 input notS1A, notS2A, notS3A; */
input [55:0] D1, D2, D3;
output [55:0] Z;
ME_INV_D b1 (.a(notS1), .x(S1));
ME_INV_D b2 (.a(notS2), .x(S2));
ME_INV_D b3 (.a(notS3), .x(S3));
/* dhn--01/10/91
ME_INV_D b7 (.a(notS1A), .x(BS1));
ME_INV_D b8 (.a(notS2A), .x(BS2));
ME_INV_D b9 (.a(notS3A), .x(BS3));
*/
ME_INV_D b7 (.a(notS1), .x(BS1)); /* dhn--01/10/91 */
ME_INV_D b8 (.a(notS2), .x(BS2)); /* dhn--01/10/91 */
ME_INV_D b9 (.a(notS3), .x(BS3)); /* dhn--01/10/91 */
ME_Ymux_Bit ym00 (S1, S2, S3, D1[00], D2[00], D3[00], Z[00]);
ME_Ymux_Bit ym01 (S1, S2, S3, D1[01], D2[01], D3[01], Z[01]);
ME_Ymux_Bit ym02 (S1, S2, S3, D1[02], D2[02], D3[02], Z[02]);
ME_Ymux_Bit ym03 (S1, S2, S3, D1[03], D2[03], D3[03], Z[03]);
ME_Ymux_Bit ym04 (S1, S2, S3, D1[04], D2[04], D3[04], Z[04]);
ME_Ymux_Bit ym05 (S1, S2, S3, D1[05], D2[05], D3[05], Z[05]);
ME_Ymux_Bit ym06 (S1, S2, S3, D1[06], D2[06], D3[06], Z[06]);
ME_Ymux_Bit ym07 (S1, S2, S3, D1[07], D2[07], D3[07], Z[07]);
ME_Ymux_Bit ym08 (S1, S2, S3, D1[08], D2[08], D3[08], Z[08]);
ME_Ymux_Bit ym09 (S1, S2, S3, D1[09], D2[09], D3[09], Z[09]);
ME_Ymux_Bit ym10 (S1, S2, S3, D1[10], D2[10], D3[10], Z[10]);
ME_Ymux_Bit ym11 (S1, S2, S3, D1[11], D2[11], D3[11], Z[11]);
ME_Ymux_Bit ym12 (S1, S2, S3, D1[12], D2[12], D3[12], Z[12]);
ME_Ymux_Bit ym13 (S1, S2, S3, D1[13], D2[13], D3[13], Z[13]);
ME_Ymux_Bit ym14 (S1, S2, S3, D1[14], D2[14], D3[14], Z[14]);
ME_Ymux_Bit ym15 (S1, S2, S3, D1[15], D2[15], D3[15], Z[15]);
ME_Ymux_Bit ym16 (S1, S2, S3, D1[16], D2[16], D3[16], Z[16]);
ME_Ymux_Bit ym17 (S1, S2, S3, D1[17], D2[17], D3[17], Z[17]);
ME_Ymux_Bit ym18 (S1, S2, S3, D1[18], D2[18], D3[18], Z[18]);
ME_Ymux_Bit ym19 (S1, S2, S3, D1[19], D2[19], D3[19], Z[19]);
ME_Ymux_Bit ym20 (S1, S2, S3, D1[20], D2[20], D3[20], Z[20]);
ME_Ymux_Bit ym21 (S1, S2, S3, D1[21], D2[21], D3[21], Z[21]);
ME_Ymux_Bit ym22 (S1, S2, S3, D1[22], D2[22], D3[22], Z[22]);
ME_Ymux_Bit ym23 (S1, S2, S3, D1[23], D2[23], D3[23], Z[23]);
ME_Ymux_Bit ym24 (S1, S2, S3, D1[24], D2[24], D3[24], Z[24]);
ME_Ymux_Bit ym25 (S1, S2, S3, D1[25], D2[25], D3[25], Z[25]);
ME_Ymux_Bit ym26 (BS1, BS2, BS3, D1[26], D2[26], D3[26], Z[26]);
ME_Ymux_Bit ym27 (BS1, BS2, BS3, D1[27], D2[27], D3[27], Z[27]);
ME_Ymux_Bit ym28 (BS1, BS2, BS3, D1[28], D2[28], D3[28], Z[28]);
ME_Ymux_Bit ym29 (S1, S2, S3, D1[29], D2[29], D3[29], Z[29]);
ME_Ymux_Bit ym30 (BS1, BS2, BS3, D1[30], D2[30], D3[30], Z[30]);
ME_Ymux_Bit ym31 (BS1, BS2, BS3, D1[31], D2[31], D3[31], Z[31]);
ME_Ymux_Bit ym32 (BS1, BS2, BS3, D1[32], D2[32], D3[32], Z[32]);
ME_Ymux_Bit ym33 (BS1, BS2, BS3, D1[33], D2[33], D3[33], Z[33]);
ME_Ymux_Bit ym34 (BS1, BS2, BS3, D1[34], D2[34], D3[34], Z[34]);
ME_Ymux_Bit ym35 (BS1, BS2, BS3, D1[35], D2[35], D3[35], Z[35]);
ME_Ymux_Bit ym36 (BS1, BS2, BS3, D1[36], D2[36], D3[36], Z[36]);
ME_Ymux_Bit ym37 (BS1, BS2, BS3, D1[37], D2[37], D3[37], Z[37]);
ME_Ymux_Bit ym38 (BS1, BS2, BS3, D1[38], D2[38], D3[38], Z[38]);
ME_Ymux_Bit ym39 (BS1, BS2, BS3, D1[39], D2[39], D3[39], Z[39]);
ME_Ymux_Bit ym40 (BS1, BS2, BS3, D1[40], D2[40], D3[40], Z[40]);
ME_Ymux_Bit ym41 (BS1, BS2, BS3, D1[41], D2[41], D3[41], Z[41]);
ME_Ymux_Bit ym42 (BS1, BS2, BS3, D1[42], D2[42], D3[42], Z[42]);
ME_Ymux_Bit ym43 (BS1, BS2, BS3, D1[43], D2[43], D3[43], Z[43]);
ME_Ymux_Bit ym44 (BS1, BS2, BS3, D1[44], D2[44], D3[44], Z[44]);
ME_Ymux_Bit ym45 (BS1, BS2, BS3, D1[45], D2[45], D3[45], Z[45]);
ME_Ymux_Bit ym46 (BS1, BS2, BS3, D1[46], D2[46], D3[46], Z[46]);
ME_Ymux_Bit ym47 (BS1, BS2, BS3, D1[47], D2[47], D3[47], Z[47]);
ME_Ymux_Bit ym48 (BS1, BS2, BS3, D1[48], D2[48], D3[48], Z[48]);
ME_Ymux_Bit ym49 (BS1, BS2, BS3, D1[49], D2[49], D3[49], Z[49]);
ME_Ymux_Bit ym50 (BS1, BS2, BS3, D1[50], D2[50], D3[50], Z[50]);
ME_Ymux_Bit ym51 (BS1, BS2, BS3, D1[51], D2[51], D3[51], Z[51]);
ME_Ymux_Bit ym52 (BS1, BS2, BS3, D1[52], D2[52], D3[52], Z[52]);
ME_Ymux_Bit ym53 (BS1, BS2, BS3, D1[53], D2[53], D3[53], Z[53]);
ME_Ymux_Bit ym54 (BS1, BS2, BS3, D1[54], D2[54], D3[54], Z[54]);
ME_Ymux_Bit ym55 (BS1, BS2, BS3, D1[55], D2[55], D3[55], Z[55]);
endmodule
// special purpose register used for fpu queue
module ME_FREGA_2_55 ( clk, a, b, c, d0, d1, Q ) ;
input clk, a, b, c;
input [54:0] d0, d1;
output [54:0] Q;
reg [54:0] mux_outputx;
wire enable_low;
wire hold;
wire sel;
ME_O2A1 iu_hold_gate_1 (.a(a), .b(b), .c(c), .z(hold) );
ME_NOR2_D iu_hold_gate_2 (.a(a), .b(b), .z(sel) );
always @ (sel or d0 or d1)
case (sel)
1'b0: mux_outputx[54:0] = d0[54:0];
1'b1: mux_outputx[54:0] = d1[54:0];
default mux_outputx = 'bx;
endcase
// assign enable_low = ~hold;
Mflipflop_32 f0 (.out(Q[31:0]), .din(mux_outputx[31:0]), .clock(clk), .enable_l(hold) );
Mflipflop_8 f1 (.out(Q[39:32]), .din(mux_outputx[39:32]), .clock(clk), .enable_l(hold) );
Mflipflop_8 f2 (.out(Q[47:40]), .din(mux_outputx[47:40]), .clock(clk), .enable_l(hold) );
Mflipflop_4 f3 (.out(Q[51:48]), .din(mux_outputx[51:48]), .clock(clk), .enable_l(hold) );
Mflipflop_3 f4 (.out(Q[54:52]), .din(mux_outputx[54:52]), .clock(clk), .enable_l(hold) );
endmodule
module FREG_2byte ( clk, E, notA, A, d0, d1, Q ) ;
input clk, notA, A, E;
input [7:0] d0, d1;
output [7:0] Q;
reg [7:0] mux_output1;
wire enable_low;
always @ (A or d0 or d1)
case (A)
0: mux_output1 = d0;
1: mux_output1 = d1;
default mux_output1 = 'bx;
endcase
assign enable_low = ~E;
Mflipflop_8 f0 (.out(Q), .din(mux_output1), .clock(clk), .enable_l(enable_low) );
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module image_filter_Erode_32_32_1080_1920_s (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
p_src_rows_V_read,
p_src_cols_V_read,
p_src_data_stream_0_V_dout,
p_src_data_stream_0_V_empty_n,
p_src_data_stream_0_V_read,
p_src_data_stream_1_V_dout,
p_src_data_stream_1_V_empty_n,
p_src_data_stream_1_V_read,
p_src_data_stream_2_V_dout,
p_src_data_stream_2_V_empty_n,
p_src_data_stream_2_V_read,
p_dst_data_stream_0_V_din,
p_dst_data_stream_0_V_full_n,
p_dst_data_stream_0_V_write,
p_dst_data_stream_1_V_din,
p_dst_data_stream_1_V_full_n,
p_dst_data_stream_1_V_write,
p_dst_data_stream_2_V_din,
p_dst_data_stream_2_V_full_n,
p_dst_data_stream_2_V_write
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 8'b1;
parameter ap_ST_st2_fsm_1 = 8'b10;
parameter ap_ST_st3_fsm_2 = 8'b100;
parameter ap_ST_st4_fsm_3 = 8'b1000;
parameter ap_ST_st5_fsm_4 = 8'b10000;
parameter ap_ST_st6_fsm_5 = 8'b100000;
parameter ap_ST_pp0_stg0_fsm_6 = 8'b1000000;
parameter ap_ST_st20_fsm_7 = 8'b10000000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_2 = 32'b10;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv32_4 = 32'b100;
parameter ap_const_lv32_5 = 32'b101;
parameter ap_const_lv32_6 = 32'b110;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv11_0 = 11'b00000000000;
parameter ap_const_lv32_7 = 32'b111;
parameter ap_const_lv5_1 = 5'b1;
parameter ap_const_lv2_1 = 2'b1;
parameter ap_const_lv8_0 = 8'b00000000;
parameter ap_const_lv2_2 = 2'b10;
parameter ap_const_lv11_5 = 11'b101;
parameter ap_const_lv11_2 = 11'b10;
parameter ap_const_lv11_7FD = 11'b11111111101;
parameter ap_const_lv12_3 = 12'b11;
parameter ap_const_lv11_7FF = 11'b11111111111;
parameter ap_const_lv11_1 = 11'b1;
parameter ap_const_lv11_4 = 11'b100;
parameter ap_const_lv12_FFC = 12'b111111111100;
parameter ap_const_lv32_B = 32'b1011;
parameter ap_const_lv12_FFF = 12'b111111111111;
parameter ap_const_lv12_FFB = 12'b111111111011;
parameter ap_const_lv12_FFA = 12'b111111111010;
parameter ap_const_lv32_A = 32'b1010;
parameter ap_const_lv10_0 = 10'b0000000000;
parameter ap_const_lv32_E = 32'b1110;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [11:0] p_src_rows_V_read;
input [11:0] p_src_cols_V_read;
input [7:0] p_src_data_stream_0_V_dout;
input p_src_data_stream_0_V_empty_n;
output p_src_data_stream_0_V_read;
input [7:0] p_src_data_stream_1_V_dout;
input p_src_data_stream_1_V_empty_n;
output p_src_data_stream_1_V_read;
input [7:0] p_src_data_stream_2_V_dout;
input p_src_data_stream_2_V_empty_n;
output p_src_data_stream_2_V_read;
output [7:0] p_dst_data_stream_0_V_din;
input p_dst_data_stream_0_V_full_n;
output p_dst_data_stream_0_V_write;
output [7:0] p_dst_data_stream_1_V_din;
input p_dst_data_stream_1_V_full_n;
output p_dst_data_stream_1_V_write;
output [7:0] p_dst_data_stream_2_V_din;
input p_dst_data_stream_2_V_full_n;
output p_dst_data_stream_2_V_write;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg p_src_data_stream_0_V_read;
reg p_src_data_stream_1_V_read;
reg p_src_data_stream_2_V_read;
reg p_dst_data_stream_0_V_write;
reg p_dst_data_stream_1_V_write;
reg p_dst_data_stream_2_V_write;
reg ap_done_reg = 1'b0;
(* fsm_encoding = "none" *) reg [7:0] ap_CS_fsm = 8'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_27;
reg [10:0] p_025_0_i_i_reg_656;
reg ap_sig_bdd_67;
wire [10:0] tmp_fu_884_p1;
reg [10:0] tmp_reg_2745;
wire [10:0] tmp_72_fu_888_p1;
reg [10:0] tmp_72_reg_2751;
wire [12:0] cols_assign_cast1_fu_892_p1;
reg [12:0] cols_assign_cast1_reg_2757;
wire [1:0] tmp_16_fu_896_p2;
reg ap_sig_cseq_ST_st2_fsm_1;
reg ap_sig_bdd_85;
wire [1:0] tmp_19_fu_908_p2;
reg ap_sig_cseq_ST_st3_fsm_2;
reg ap_sig_bdd_94;
wire [1:0] tmp_22_fu_920_p2;
reg ap_sig_cseq_ST_st4_fsm_3;
reg ap_sig_bdd_103;
wire [10:0] heightloop_fu_932_p2;
reg [10:0] heightloop_reg_3051;
wire [0:0] tmp_23_fu_926_p2;
wire [10:0] widthloop_fu_937_p2;
reg [10:0] widthloop_reg_3056;
wire [11:0] tmp_28_cast_fu_947_p1;
reg [11:0] tmp_28_cast_reg_3061;
wire [11:0] p_neg226_i_i_fu_951_p2;
reg [11:0] p_neg226_i_i_reg_3068;
wire [1:0] tmp_73_fu_956_p1;
reg [1:0] tmp_73_reg_3076;
wire [10:0] ref_fu_960_p2;
reg [10:0] ref_reg_3084;
wire [11:0] ref_cast_fu_965_p1;
reg [11:0] ref_cast_reg_3089;
wire [1:0] tmp_74_fu_969_p1;
reg [1:0] tmp_74_reg_3094;
wire [11:0] tmp_29_cast_cast3_fu_973_p1;
reg [11:0] tmp_29_cast_cast3_reg_3099;
reg ap_sig_cseq_ST_st5_fsm_4;
reg ap_sig_bdd_133;
wire [10:0] i_V_fu_982_p2;
reg [10:0] i_V_reg_3108;
wire [0:0] tmp_30_fu_988_p2;
reg [0:0] tmp_30_reg_3113;
wire [0:0] tmp_28_fu_977_p2;
wire [11:0] ImagLoc_y_fu_994_p2;
reg [11:0] ImagLoc_y_reg_3118;
wire [0:0] or_cond_2_fu_1021_p2;
reg [0:0] or_cond_2_reg_3126;
reg [0:0] tmp_77_reg_3131;
wire [1:0] tmp_32_fu_1035_p3;
reg [1:0] tmp_32_reg_3135;
wire [1:0] tmp_78_fu_1049_p1;
reg [1:0] tmp_78_reg_3149;
wire [1:0] tmp_79_fu_1053_p1;
reg [1:0] tmp_79_reg_3155;
wire [11:0] y_1_2_fu_1062_p2;
reg [11:0] y_1_2_reg_3162;
reg ap_sig_cseq_ST_st6_fsm_5;
reg ap_sig_bdd_162;
wire [11:0] y_1_2_1_fu_1067_p2;
reg [11:0] y_1_2_1_reg_3169;
wire [0:0] brmerge_fu_1072_p2;
reg [0:0] brmerge_reg_3176;
wire [0:0] tmp_33_fu_1081_p2;
reg [0:0] tmp_33_reg_3180;
reg ap_sig_cseq_ST_pp0_stg0_fsm_6;
reg ap_sig_bdd_175;
reg ap_reg_ppiten_pp0_it0 = 1'b0;
reg ap_reg_ppiten_pp0_it1 = 1'b0;
reg ap_reg_ppiten_pp0_it2 = 1'b0;
reg ap_reg_ppiten_pp0_it3 = 1'b0;
reg ap_reg_ppiten_pp0_it4 = 1'b0;
reg ap_reg_ppiten_pp0_it5 = 1'b0;
reg [0:0] ap_reg_ppstg_tmp_33_reg_3180_pp0_it5;
reg [0:0] or_cond2_reg_3206;
reg [0:0] ap_reg_ppstg_or_cond2_reg_3206_pp0_it5;
reg [0:0] or_cond2_1_reg_3228;
reg [0:0] ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5;
reg [0:0] or_cond2_2_reg_3248;
reg [0:0] ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5;
reg ap_sig_bdd_218;
reg ap_reg_ppiten_pp0_it6 = 1'b0;
reg ap_reg_ppiten_pp0_it7 = 1'b0;
reg ap_reg_ppiten_pp0_it8 = 1'b0;
reg ap_reg_ppiten_pp0_it9 = 1'b0;
reg ap_reg_ppiten_pp0_it10 = 1'b0;
reg ap_reg_ppiten_pp0_it11 = 1'b0;
reg [0:0] or_cond219_i_i_reg_3189;
reg [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11;
reg ap_sig_bdd_244;
reg ap_reg_ppiten_pp0_it12 = 1'b0;
reg [0:0] ap_reg_ppstg_tmp_33_reg_3180_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp_33_reg_3180_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp_33_reg_3180_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp_33_reg_3180_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp_33_reg_3180_pp0_it6;
reg [0:0] ap_reg_ppstg_tmp_33_reg_3180_pp0_it7;
reg [0:0] ap_reg_ppstg_tmp_33_reg_3180_pp0_it8;
reg [0:0] ap_reg_ppstg_tmp_33_reg_3180_pp0_it9;
wire [10:0] j_V_fu_1086_p2;
wire [0:0] or_cond219_i_i_fu_1108_p2;
reg [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it1;
reg [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it2;
reg [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it3;
reg [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it4;
reg [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it5;
reg [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it6;
reg [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it7;
reg [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it8;
reg [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it9;
reg [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it10;
wire [11:0] ImagLoc_x_fu_1113_p2;
reg [11:0] ImagLoc_x_reg_3193;
wire [0:0] tmp_37_fu_1133_p2;
reg [0:0] tmp_37_reg_3202;
reg [0:0] ap_reg_ppstg_tmp_37_reg_3202_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp_37_reg_3202_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp_37_reg_3202_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp_37_reg_3202_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp_37_reg_3202_pp0_it5;
reg [0:0] ap_reg_ppstg_tmp_37_reg_3202_pp0_it6;
wire [0:0] or_cond2_fu_1138_p2;
reg [0:0] ap_reg_ppstg_or_cond2_reg_3206_pp0_it1;
reg [0:0] ap_reg_ppstg_or_cond2_reg_3206_pp0_it2;
reg [0:0] ap_reg_ppstg_or_cond2_reg_3206_pp0_it3;
reg [0:0] ap_reg_ppstg_or_cond2_reg_3206_pp0_it4;
reg [0:0] ap_reg_ppstg_or_cond2_reg_3206_pp0_it6;
reg [0:0] tmp_84_reg_3210;
reg [0:0] ap_reg_ppstg_tmp_84_reg_3210_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp_84_reg_3210_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp_84_reg_3210_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp_84_reg_3210_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp_84_reg_3210_pp0_it5;
reg [0:0] ap_reg_ppstg_tmp_84_reg_3210_pp0_it6;
wire [0:0] tmp_38_fu_1152_p2;
reg [0:0] tmp_38_reg_3214;
reg [0:0] ap_reg_ppstg_tmp_38_reg_3214_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp_38_reg_3214_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp_38_reg_3214_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp_38_reg_3214_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp_38_reg_3214_pp0_it5;
wire [1:0] col_assign_fu_1157_p2;
reg [1:0] col_assign_reg_3218;
reg [1:0] ap_reg_ppstg_col_assign_reg_3218_pp0_it1;
reg [1:0] ap_reg_ppstg_col_assign_reg_3218_pp0_it2;
reg [1:0] ap_reg_ppstg_col_assign_reg_3218_pp0_it3;
reg [1:0] ap_reg_ppstg_col_assign_reg_3218_pp0_it4;
reg [1:0] ap_reg_ppstg_col_assign_reg_3218_pp0_it5;
wire [0:0] tmp_63_1_fu_1168_p2;
reg [0:0] tmp_63_1_reg_3224;
reg [0:0] ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it5;
reg [0:0] ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6;
wire [0:0] or_cond2_1_fu_1173_p2;
reg [0:0] ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it1;
reg [0:0] ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it2;
reg [0:0] ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it3;
reg [0:0] ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it4;
reg [0:0] ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6;
reg [0:0] tmp_89_reg_3232;
reg [0:0] ap_reg_ppstg_tmp_89_reg_3232_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp_89_reg_3232_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp_89_reg_3232_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp_89_reg_3232_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp_89_reg_3232_pp0_it5;
reg [0:0] ap_reg_ppstg_tmp_89_reg_3232_pp0_it6;
wire [0:0] tmp_66_1_fu_1187_p2;
reg [0:0] tmp_66_1_reg_3236;
reg [0:0] ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5;
wire [1:0] tmp_93_fu_1197_p1;
reg [1:0] tmp_93_reg_3240;
reg [1:0] ap_reg_ppstg_tmp_93_reg_3240_pp0_it1;
reg [1:0] ap_reg_ppstg_tmp_93_reg_3240_pp0_it2;
reg [1:0] ap_reg_ppstg_tmp_93_reg_3240_pp0_it3;
reg [1:0] ap_reg_ppstg_tmp_93_reg_3240_pp0_it4;
reg [1:0] ap_reg_ppstg_tmp_93_reg_3240_pp0_it5;
wire [0:0] tmp_63_2_fu_1207_p2;
reg [0:0] tmp_63_2_reg_3244;
reg [0:0] ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it5;
reg [0:0] ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6;
wire [0:0] or_cond2_2_fu_1212_p2;
reg [0:0] ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it1;
reg [0:0] ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it2;
reg [0:0] ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it3;
reg [0:0] ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it4;
reg [0:0] ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6;
reg [0:0] tmp_98_reg_3252;
reg [0:0] ap_reg_ppstg_tmp_98_reg_3252_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp_98_reg_3252_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp_98_reg_3252_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp_98_reg_3252_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp_98_reg_3252_pp0_it5;
reg [0:0] ap_reg_ppstg_tmp_98_reg_3252_pp0_it6;
wire [0:0] tmp_66_2_fu_1226_p2;
reg [0:0] tmp_66_2_reg_3256;
reg [0:0] ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5;
wire [1:0] tmp_102_fu_1236_p1;
reg [1:0] tmp_102_reg_3260;
reg [1:0] ap_reg_ppstg_tmp_102_reg_3260_pp0_it1;
reg [1:0] ap_reg_ppstg_tmp_102_reg_3260_pp0_it2;
reg [1:0] ap_reg_ppstg_tmp_102_reg_3260_pp0_it3;
reg [1:0] ap_reg_ppstg_tmp_102_reg_3260_pp0_it4;
reg [1:0] ap_reg_ppstg_tmp_102_reg_3260_pp0_it5;
wire [1:0] tmp_96_fu_1244_p1;
reg [1:0] tmp_96_reg_3264;
reg [1:0] ap_reg_ppstg_tmp_96_reg_3264_pp0_it2;
reg [1:0] ap_reg_ppstg_tmp_96_reg_3264_pp0_it3;
reg [1:0] ap_reg_ppstg_tmp_96_reg_3264_pp0_it4;
reg [1:0] ap_reg_ppstg_tmp_96_reg_3264_pp0_it5;
wire [1:0] tmp_105_fu_1252_p1;
reg [1:0] tmp_105_reg_3270;
reg [1:0] ap_reg_ppstg_tmp_105_reg_3270_pp0_it2;
reg [1:0] ap_reg_ppstg_tmp_105_reg_3270_pp0_it3;
reg [1:0] ap_reg_ppstg_tmp_105_reg_3270_pp0_it4;
reg [1:0] ap_reg_ppstg_tmp_105_reg_3270_pp0_it5;
wire [1:0] tmp_87_fu_1256_p1;
reg [1:0] tmp_87_reg_3276;
wire [1:0] tmp_92_fu_1260_p1;
reg [1:0] tmp_92_reg_3281;
wire [1:0] tmp_101_fu_1264_p1;
reg [1:0] tmp_101_reg_3286;
wire [14:0] grp_image_filter_borderInterpolate_fu_692_ap_return;
reg [14:0] x_reg_3291;
wire [1:0] tmp_83_fu_1268_p1;
reg [1:0] tmp_83_reg_3296;
reg [1:0] ap_reg_ppstg_tmp_83_reg_3296_pp0_it5;
wire [1:0] locy_0_2_t_fu_1272_p2;
reg [1:0] locy_0_2_t_reg_3301;
reg [1:0] ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it5;
reg [1:0] ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6;
wire [14:0] grp_image_filter_borderInterpolate_fu_700_ap_return;
reg [14:0] x_1_reg_3305;
reg [14:0] ap_reg_ppstg_x_1_reg_3305_pp0_it5;
wire [1:0] locy_1_2_t_fu_1276_p2;
reg [1:0] locy_1_2_t_reg_3313;
reg [1:0] ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it5;
reg [1:0] ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6;
wire [14:0] grp_image_filter_borderInterpolate_fu_708_ap_return;
reg [14:0] x_2_reg_3317;
reg [14:0] ap_reg_ppstg_x_2_reg_3317_pp0_it5;
wire [1:0] locy_2_2_t_fu_1280_p2;
reg [1:0] locy_2_2_t_reg_3325;
reg [1:0] ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it5;
reg [1:0] ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6;
reg [10:0] k_buf_0_val_0_addr_reg_3329;
reg [10:0] k_buf_0_val_1_addr_reg_3335;
reg [10:0] k_buf_0_val_2_addr_reg_3341;
wire [7:0] k_buf_0_val_0_q0;
reg [7:0] right_border_buf_0_val_2_0_reg_3377;
wire [7:0] k_buf_0_val_1_q0;
reg [7:0] right_border_buf_0_val_1_0_reg_3382;
wire [7:0] k_buf_0_val_2_q0;
reg [7:0] src_kernel_win_0_val_2_0_reg_3390;
wire [1:0] tmp_85_fu_1311_p1;
reg [1:0] tmp_85_reg_3397;
wire [1:0] tmp_86_fu_1315_p1;
reg [1:0] tmp_86_reg_3403;
wire [1:0] col_assign_3_fu_1319_p2;
reg [1:0] col_assign_3_reg_3409;
wire [7:0] k_buf_1_val_0_q0;
reg [7:0] right_border_buf_1_val_2_0_reg_3415;
wire [7:0] k_buf_1_val_1_q0;
reg [7:0] right_border_buf_1_val_1_0_reg_3420;
wire [7:0] k_buf_1_val_2_q0;
reg [7:0] src_kernel_win_1_val_2_0_reg_3428;
wire [1:0] tmp_90_fu_1423_p1;
reg [1:0] tmp_90_reg_3435;
wire [1:0] tmp_91_fu_1427_p1;
reg [1:0] tmp_91_reg_3441;
wire [0:0] tmp_94_fu_1440_p3;
reg [0:0] tmp_94_reg_3447;
wire [1:0] col_assign_3_1_t1_fu_1450_p2;
reg [1:0] col_assign_3_1_t1_reg_3453;
wire [7:0] col_buf_1_val_0_0_16_fu_1475_p3;
reg [7:0] col_buf_1_val_0_0_16_reg_3457;
wire [0:0] sel_tmp43_fu_1489_p2;
reg [0:0] sel_tmp43_reg_3463;
wire [0:0] sel_tmp44_fu_1495_p2;
reg [0:0] sel_tmp44_reg_3469;
wire [7:0] k_buf_2_val_0_q0;
reg [7:0] right_border_buf_2_val_2_0_reg_3474;
wire [7:0] k_buf_2_val_1_q0;
reg [7:0] right_border_buf_2_val_1_0_reg_3479;
wire [7:0] k_buf_2_val_2_q0;
reg [7:0] src_kernel_win_2_val_2_0_reg_3487;
wire [1:0] tmp_99_fu_1609_p1;
reg [1:0] tmp_99_reg_3494;
wire [1:0] tmp_100_fu_1613_p1;
reg [1:0] tmp_100_reg_3500;
wire [0:0] tmp_103_fu_1626_p3;
reg [0:0] tmp_103_reg_3506;
wire [1:0] col_assign_3_2_t1_fu_1636_p2;
reg [1:0] col_assign_3_2_t1_reg_3512;
wire [7:0] col_buf_2_val_0_0_16_fu_1661_p3;
reg [7:0] col_buf_2_val_0_0_16_reg_3516;
wire [0:0] sel_tmp55_fu_1675_p2;
reg [0:0] sel_tmp55_reg_3522;
wire [0:0] sel_tmp56_fu_1681_p2;
reg [0:0] sel_tmp56_reg_3528;
reg [7:0] src_kernel_win_0_val_0_1_12_reg_3533;
reg [7:0] ap_reg_ppstg_src_kernel_win_0_val_0_1_12_reg_3533_pp0_it8;
reg [7:0] ap_reg_ppstg_src_kernel_win_0_val_0_1_12_reg_3533_pp0_it9;
reg [7:0] ap_reg_ppstg_src_kernel_win_0_val_0_1_12_reg_3533_pp0_it10;
reg [7:0] src_kernel_win_0_val_1_1_12_reg_3540;
reg [7:0] ap_reg_ppstg_src_kernel_win_0_val_1_1_12_reg_3540_pp0_it8;
reg [7:0] src_kernel_win_1_val_0_1_12_reg_3547;
reg [7:0] ap_reg_ppstg_src_kernel_win_1_val_0_1_12_reg_3547_pp0_it8;
reg [7:0] ap_reg_ppstg_src_kernel_win_1_val_0_1_12_reg_3547_pp0_it9;
reg [7:0] ap_reg_ppstg_src_kernel_win_1_val_0_1_12_reg_3547_pp0_it10;
reg [7:0] src_kernel_win_1_val_1_1_12_reg_3554;
reg [7:0] ap_reg_ppstg_src_kernel_win_1_val_1_1_12_reg_3554_pp0_it8;
reg [7:0] src_kernel_win_2_val_0_1_12_reg_3561;
reg [7:0] ap_reg_ppstg_src_kernel_win_2_val_0_1_12_reg_3561_pp0_it8;
reg [7:0] ap_reg_ppstg_src_kernel_win_2_val_0_1_12_reg_3561_pp0_it9;
reg [7:0] ap_reg_ppstg_src_kernel_win_2_val_0_1_12_reg_3561_pp0_it10;
reg [7:0] src_kernel_win_2_val_1_1_12_reg_3568;
reg [7:0] ap_reg_ppstg_src_kernel_win_2_val_1_1_12_reg_3568_pp0_it8;
wire [7:0] temp_0_i_i_i_057_i_i_1_0_0_1_fu_1985_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_0_0_1_reg_3575;
wire [7:0] temp_0_i_i_i_057_i_i_1_1_0_1_fu_2151_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_1_0_1_reg_3581;
wire [7:0] temp_0_i_i_i_057_i_i_1_2_0_1_fu_2317_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_2_0_1_reg_3587;
reg [7:0] src_kernel_win_0_val_0_1_lo_reg_3593;
reg [7:0] ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it9;
reg [7:0] ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it10;
reg [7:0] ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it11;
reg [7:0] src_kernel_win_0_val_1_1_lo_reg_3599;
reg [7:0] ap_reg_ppstg_src_kernel_win_0_val_1_1_lo_reg_3599_pp0_it9;
reg [7:0] src_kernel_win_0_val_1_2_lo_reg_3605;
wire [7:0] temp_0_i_i_i_057_i_i_1_0_0_2_fu_2357_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_0_0_2_reg_3610;
wire [0:0] tmp_115_0_1_fu_2364_p2;
reg [0:0] tmp_115_0_1_reg_3615;
reg [7:0] src_kernel_win_1_val_0_1_lo_reg_3620;
reg [7:0] ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it9;
reg [7:0] ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it10;
reg [7:0] ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it11;
reg [7:0] src_kernel_win_1_val_1_1_lo_reg_3626;
reg [7:0] ap_reg_ppstg_src_kernel_win_1_val_1_1_lo_reg_3626_pp0_it9;
reg [7:0] src_kernel_win_1_val_1_2_lo_reg_3632;
wire [7:0] temp_0_i_i_i_057_i_i_1_1_0_2_fu_2387_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_1_0_2_reg_3637;
wire [0:0] tmp_115_1_1_fu_2394_p2;
reg [0:0] tmp_115_1_1_reg_3642;
reg [7:0] src_kernel_win_2_val_0_1_lo_reg_3647;
reg [7:0] ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it9;
reg [7:0] ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it10;
reg [7:0] ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it11;
reg [7:0] src_kernel_win_2_val_1_1_lo_reg_3653;
reg [7:0] ap_reg_ppstg_src_kernel_win_2_val_1_1_lo_reg_3653_pp0_it9;
reg [7:0] src_kernel_win_2_val_1_2_lo_reg_3659;
wire [7:0] temp_0_i_i_i_057_i_i_1_2_0_2_fu_2417_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_2_0_2_reg_3664;
wire [0:0] tmp_115_2_1_fu_2424_p2;
reg [0:0] tmp_115_2_1_reg_3669;
wire [7:0] temp_0_i_i_i_057_i_i_1_0_1_1_fu_2452_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_0_1_1_reg_3674;
wire [7:0] temp_0_i_i_i_057_i_i_1_1_1_1_fu_2469_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_1_1_1_reg_3680;
wire [7:0] temp_0_i_i_i_057_i_i_1_2_1_1_fu_2486_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_2_1_1_reg_3686;
reg [7:0] src_kernel_win_0_val_0_2_lo_reg_3692;
wire [7:0] temp_0_i_i_i_057_i_i_1_0_1_2_fu_2500_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_0_1_2_reg_3697;
wire [0:0] tmp_115_0_2_fu_2506_p2;
reg [0:0] tmp_115_0_2_reg_3702;
reg [7:0] src_kernel_win_1_val_0_2_lo_reg_3707;
wire [7:0] temp_0_i_i_i_057_i_i_1_1_1_2_fu_2519_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_1_1_2_reg_3712;
wire [0:0] tmp_115_1_2_fu_2525_p2;
reg [0:0] tmp_115_1_2_reg_3717;
reg [7:0] src_kernel_win_2_val_0_2_lo_reg_3722;
wire [7:0] temp_0_i_i_i_057_i_i_1_2_1_2_fu_2538_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_2_1_2_reg_3727;
wire [0:0] tmp_115_2_2_fu_2544_p2;
reg [0:0] tmp_115_2_2_reg_3732;
wire [7:0] temp_0_i_i_i_057_i_i_1_0_2_1_fu_2572_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_0_2_1_reg_3737;
wire [7:0] temp_0_i_i_i_057_i_i_1_1_2_1_fu_2589_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_1_2_1_reg_3743;
wire [7:0] temp_0_i_i_i_057_i_i_1_2_2_1_fu_2606_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_2_2_1_reg_3749;
wire [10:0] k_buf_0_val_0_address0;
reg k_buf_0_val_0_ce0;
wire [10:0] k_buf_0_val_0_address1;
reg k_buf_0_val_0_ce1;
reg k_buf_0_val_0_we1;
wire [7:0] k_buf_0_val_0_d1;
wire [10:0] k_buf_0_val_1_address0;
reg k_buf_0_val_1_ce0;
wire [10:0] k_buf_0_val_1_address1;
reg k_buf_0_val_1_ce1;
reg k_buf_0_val_1_we1;
wire [7:0] k_buf_0_val_1_d1;
wire [10:0] k_buf_0_val_2_address0;
reg k_buf_0_val_2_ce0;
wire [10:0] k_buf_0_val_2_address1;
reg k_buf_0_val_2_ce1;
reg k_buf_0_val_2_we1;
wire [7:0] k_buf_0_val_2_d1;
wire [10:0] k_buf_1_val_0_address0;
reg k_buf_1_val_0_ce0;
wire [10:0] k_buf_1_val_0_address1;
reg k_buf_1_val_0_ce1;
reg k_buf_1_val_0_we1;
wire [7:0] k_buf_1_val_0_d1;
wire [10:0] k_buf_1_val_1_address0;
reg k_buf_1_val_1_ce0;
reg [10:0] k_buf_1_val_1_address1;
reg k_buf_1_val_1_ce1;
reg k_buf_1_val_1_we1;
wire [7:0] k_buf_1_val_1_d1;
wire [10:0] k_buf_1_val_2_address0;
reg k_buf_1_val_2_ce0;
wire [10:0] k_buf_1_val_2_address1;
reg k_buf_1_val_2_ce1;
reg k_buf_1_val_2_we1;
wire [7:0] k_buf_1_val_2_d1;
wire [10:0] k_buf_2_val_0_address0;
reg k_buf_2_val_0_ce0;
wire [10:0] k_buf_2_val_0_address1;
reg k_buf_2_val_0_ce1;
reg k_buf_2_val_0_we1;
wire [7:0] k_buf_2_val_0_d1;
wire [10:0] k_buf_2_val_1_address0;
reg k_buf_2_val_1_ce0;
reg [10:0] k_buf_2_val_1_address1;
reg k_buf_2_val_1_ce1;
reg k_buf_2_val_1_we1;
wire [7:0] k_buf_2_val_1_d1;
wire [10:0] k_buf_2_val_2_address0;
reg k_buf_2_val_2_ce0;
wire [10:0] k_buf_2_val_2_address1;
reg k_buf_2_val_2_ce1;
reg k_buf_2_val_2_we1;
wire [7:0] k_buf_2_val_2_d1;
wire [11:0] grp_image_filter_borderInterpolate_fu_668_p;
wire [11:0] grp_image_filter_borderInterpolate_fu_668_len;
wire [4:0] grp_image_filter_borderInterpolate_fu_668_borderType;
wire [14:0] grp_image_filter_borderInterpolate_fu_668_ap_return;
reg grp_image_filter_borderInterpolate_fu_668_ap_ce;
wire [11:0] grp_image_filter_borderInterpolate_fu_676_p;
wire [11:0] grp_image_filter_borderInterpolate_fu_676_len;
wire [4:0] grp_image_filter_borderInterpolate_fu_676_borderType;
wire [14:0] grp_image_filter_borderInterpolate_fu_676_ap_return;
reg grp_image_filter_borderInterpolate_fu_676_ap_ce;
wire [11:0] grp_image_filter_borderInterpolate_fu_684_p;
wire [11:0] grp_image_filter_borderInterpolate_fu_684_len;
wire [4:0] grp_image_filter_borderInterpolate_fu_684_borderType;
wire [14:0] grp_image_filter_borderInterpolate_fu_684_ap_return;
reg grp_image_filter_borderInterpolate_fu_684_ap_ce;
wire [11:0] grp_image_filter_borderInterpolate_fu_692_p;
wire [11:0] grp_image_filter_borderInterpolate_fu_692_len;
wire [4:0] grp_image_filter_borderInterpolate_fu_692_borderType;
reg grp_image_filter_borderInterpolate_fu_692_ap_ce;
wire [11:0] grp_image_filter_borderInterpolate_fu_700_p;
wire [11:0] grp_image_filter_borderInterpolate_fu_700_len;
wire [4:0] grp_image_filter_borderInterpolate_fu_700_borderType;
reg grp_image_filter_borderInterpolate_fu_700_ap_ce;
wire [11:0] grp_image_filter_borderInterpolate_fu_708_p;
wire [11:0] grp_image_filter_borderInterpolate_fu_708_len;
wire [4:0] grp_image_filter_borderInterpolate_fu_708_borderType;
reg grp_image_filter_borderInterpolate_fu_708_ap_ce;
wire [11:0] grp_image_filter_borderInterpolate_fu_716_p;
wire [11:0] grp_image_filter_borderInterpolate_fu_716_len;
wire [4:0] grp_image_filter_borderInterpolate_fu_716_borderType;
wire [14:0] grp_image_filter_borderInterpolate_fu_716_ap_return;
reg grp_image_filter_borderInterpolate_fu_716_ap_ce;
wire [11:0] grp_image_filter_borderInterpolate_fu_724_p;
wire [11:0] grp_image_filter_borderInterpolate_fu_724_len;
wire [4:0] grp_image_filter_borderInterpolate_fu_724_borderType;
wire [14:0] grp_image_filter_borderInterpolate_fu_724_ap_return;
reg grp_image_filter_borderInterpolate_fu_724_ap_ce;
wire [11:0] grp_image_filter_borderInterpolate_fu_732_p;
wire [11:0] grp_image_filter_borderInterpolate_fu_732_len;
wire [4:0] grp_image_filter_borderInterpolate_fu_732_borderType;
wire [14:0] grp_image_filter_borderInterpolate_fu_732_ap_return;
reg grp_image_filter_borderInterpolate_fu_732_ap_ce;
wire [11:0] grp_image_filter_borderInterpolate_fu_740_p;
wire [11:0] grp_image_filter_borderInterpolate_fu_740_len;
wire [4:0] grp_image_filter_borderInterpolate_fu_740_borderType;
wire [14:0] grp_image_filter_borderInterpolate_fu_740_ap_return;
reg grp_image_filter_borderInterpolate_fu_740_ap_ce;
wire [11:0] grp_image_filter_borderInterpolate_fu_748_p;
wire [11:0] grp_image_filter_borderInterpolate_fu_748_len;
wire [4:0] grp_image_filter_borderInterpolate_fu_748_borderType;
wire [14:0] grp_image_filter_borderInterpolate_fu_748_ap_return;
reg grp_image_filter_borderInterpolate_fu_748_ap_ce;
wire [11:0] grp_image_filter_borderInterpolate_fu_756_p;
wire [11:0] grp_image_filter_borderInterpolate_fu_756_len;
wire [4:0] grp_image_filter_borderInterpolate_fu_756_borderType;
wire [14:0] grp_image_filter_borderInterpolate_fu_756_ap_return;
reg grp_image_filter_borderInterpolate_fu_756_ap_ce;
reg [1:0] tmp_15_reg_612;
wire [0:0] tmp_s_fu_902_p2;
reg [1:0] tmp_18_reg_623;
wire [0:0] tmp_20_fu_914_p2;
reg [1:0] tmp_21_reg_634;
reg [10:0] p_012_0_i_i_reg_645;
reg ap_sig_cseq_ST_st20_fsm_7;
reg ap_sig_bdd_951;
wire [63:0] tmp_35_fu_1287_p1;
wire signed [63:0] tmp_56_1_fu_1294_p1;
wire signed [63:0] tmp_56_2_fu_1300_p1;
wire [63:0] tmp_99_1_fu_1516_p1;
wire [10:0] k_buf_1_val_1_addr_1_gep_fu_554_p3;
wire [63:0] tmp_99_2_fu_1702_p1;
wire [10:0] k_buf_2_val_1_addr_1_gep_fu_594_p3;
reg [7:0] right_border_buf_0_val_0_0_fu_178;
reg [7:0] right_border_buf_0_val_0_1_fu_182;
reg [7:0] right_border_buf_0_val_0_2_fu_186;
reg [7:0] right_border_buf_1_val_0_0_fu_190;
reg [7:0] right_border_buf_1_val_0_1_fu_194;
reg [7:0] right_border_buf_1_val_0_2_fu_198;
reg [7:0] right_border_buf_2_val_0_0_fu_202;
reg [7:0] right_border_buf_2_val_0_1_fu_206;
reg [7:0] right_border_buf_2_val_0_2_fu_210;
reg [7:0] col_buf_0_val_0_0_fu_214;
reg [7:0] col_buf_1_val_0_0_fu_218;
reg [7:0] col_buf_2_val_0_0_fu_222;
reg [7:0] src_kernel_win_0_val_0_1_fu_226;
wire [7:0] src_kernel_win_0_val_0_1_9_fu_1838_p3;
wire [7:0] col_buf_0_val_0_0_16_fu_1926_p3;
reg [7:0] src_kernel_win_0_val_0_2_fu_230;
reg [7:0] col_buf_2_val_0_0_11_fu_234;
reg [7:0] src_kernel_win_0_val_2_1_fu_238;
reg [7:0] src_kernel_win_0_val_1_1_fu_242;
wire [7:0] src_kernel_win_0_val_1_1_9_fu_1870_p3;
wire [7:0] right_border_buf_0_val_1_2_20_fu_1943_p3;
reg [7:0] src_kernel_win_0_val_1_2_fu_246;
reg [7:0] col_buf_2_val_0_0_12_fu_250;
reg [7:0] src_kernel_win_0_val_2_2_fu_254;
reg [7:0] col_buf_2_val_0_0_13_fu_258;
reg [7:0] src_kernel_win_1_val_0_1_fu_262;
wire [7:0] src_kernel_win_1_val_0_1_9_fu_2017_p3;
wire [7:0] src_kernel_win_1_val_0_1_10_fu_2084_p3;
reg [7:0] src_kernel_win_1_val_0_2_fu_266;
reg [7:0] right_border_buf_2_val_1_2_12_fu_270;
wire [7:0] right_border_buf_2_val_1_2_27_fu_1763_p3;
reg [7:0] src_kernel_win_1_val_2_1_fu_274;
reg [7:0] src_kernel_win_1_val_1_1_fu_278;
wire [7:0] src_kernel_win_1_val_1_1_9_fu_2049_p3;
wire [7:0] src_kernel_win_1_val_1_1_10_fu_2105_p3;
reg [7:0] src_kernel_win_1_val_1_2_fu_282;
reg [7:0] right_border_buf_2_val_1_2_19_fu_286;
wire [7:0] right_border_buf_2_val_1_2_25_fu_1746_p3;
reg [7:0] src_kernel_win_1_val_2_2_fu_290;
reg [7:0] right_border_buf_2_val_1_2_20_fu_294;
wire [7:0] right_border_buf_2_val_1_2_23_fu_1724_p3;
reg [7:0] src_kernel_win_2_val_0_1_fu_298;
wire [7:0] src_kernel_win_2_val_0_1_9_fu_2183_p3;
wire [7:0] src_kernel_win_2_val_0_1_10_fu_2250_p3;
reg [7:0] src_kernel_win_2_val_0_2_fu_302;
reg [7:0] col_buf_1_val_0_0_11_fu_306;
reg [7:0] src_kernel_win_2_val_2_1_fu_310;
reg [7:0] src_kernel_win_2_val_1_1_fu_314;
wire [7:0] src_kernel_win_2_val_1_1_9_fu_2215_p3;
wire [7:0] src_kernel_win_2_val_1_1_10_fu_2271_p3;
reg [7:0] src_kernel_win_2_val_1_2_fu_318;
reg [7:0] col_buf_1_val_0_0_12_fu_322;
reg [7:0] src_kernel_win_2_val_2_2_fu_326;
reg [7:0] col_buf_1_val_0_0_13_fu_330;
reg [7:0] right_border_buf_0_val_1_2_14_fu_334;
wire [7:0] right_border_buf_0_val_1_2_19_fu_1391_p3;
reg [7:0] right_border_buf_0_val_1_2_15_fu_338;
wire [7:0] right_border_buf_0_val_1_2_5_fu_1382_p3;
reg [7:0] right_border_buf_0_val_1_2_16_fu_342;
wire [7:0] right_border_buf_0_val_1_2_3_fu_1365_p3;
reg [7:0] col_buf_0_val_0_0_11_fu_346;
reg [7:0] col_buf_0_val_0_0_12_fu_350;
reg [7:0] col_buf_0_val_0_0_13_fu_354;
reg [7:0] right_border_buf_1_val_1_2_12_fu_358;
wire [7:0] right_border_buf_1_val_1_2_19_fu_1577_p3;
reg [7:0] right_border_buf_1_val_1_2_15_fu_362;
wire [7:0] right_border_buf_1_val_1_2_6_74_fu_1568_p3;
reg [7:0] right_border_buf_1_val_1_2_16_fu_366;
wire [7:0] right_border_buf_1_val_1_2_4_fu_1551_p3;
wire [10:0] tmp_27_fu_942_p2;
wire [10:0] tmp_75_fu_1000_p4;
wire [0:0] icmp_fu_1010_p2;
wire [0:0] tmp_58_2_fu_1016_p2;
wire [10:0] p_i_i_fu_1042_p3;
wire [0:0] tmp_31_fu_1057_p2;
wire [9:0] tmp_80_fu_1092_p4;
wire [0:0] icmp2_fu_1102_p2;
wire [11:0] tmp_33_cast_fu_1077_p1;
wire signed [12:0] ImagLoc_x_cast2_fu_1123_p1;
wire [0:0] tmp_36_fu_1127_p2;
wire [1:0] tmp_82_fu_1119_p1;
wire [0:0] tmp_61_1_fu_1162_p2;
wire [11:0] col_assign_1_fu_1192_p2;
wire [0:0] tmp_61_2_fu_1201_p2;
wire [11:0] col_assign_s_fu_1231_p2;
wire [11:0] col_assign_4_1_fu_1240_p2;
wire [11:0] col_assign_4_2_fu_1248_p2;
wire signed [31:0] x_ext_fu_1284_p1;
wire [0:0] sel_tmp24_fu_1347_p2;
wire [0:0] sel_tmp26_fu_1360_p2;
wire [7:0] right_border_buf_0_val_1_2_2_fu_1352_p3;
wire [7:0] right_border_buf_0_val_1_2_4_fu_1374_p3;
wire [1:0] tmp_95_fu_1447_p1;
wire [0:0] sel_tmp39_fu_1455_p2;
wire [0:0] sel_tmp40_fu_1469_p2;
wire [7:0] col_buf_1_val_0_0_6_fu_1461_p3;
wire [0:0] sel_tmp42_fu_1483_p2;
wire signed [31:0] x_1_ext_fu_1415_p1;
wire [0:0] sel_tmp36_fu_1533_p2;
wire [0:0] sel_tmp38_fu_1546_p2;
wire [7:0] right_border_buf_1_val_1_2_3_fu_1538_p3;
wire [7:0] right_border_buf_1_val_1_2_5_fu_1560_p3;
wire [1:0] tmp_104_fu_1633_p1;
wire [0:0] sel_tmp51_fu_1641_p2;
wire [0:0] sel_tmp52_fu_1655_p2;
wire [7:0] col_buf_2_val_0_0_6_fu_1647_p3;
wire [0:0] sel_tmp54_fu_1669_p2;
wire signed [31:0] x_2_ext_fu_1601_p1;
wire [0:0] sel_tmp57_fu_1719_p2;
wire [0:0] sel_tmp58_fu_1733_p2;
wire [7:0] right_border_buf_2_val_1_2_24_fu_1738_p3;
wire [7:0] right_border_buf_2_val_1_2_26_fu_1755_p3;
wire [0:0] sel_tmp8_fu_1821_p2;
wire [1:0] locy_fu_1814_p2;
wire [0:0] sel_tmp10_fu_1832_p2;
wire [7:0] sel_tmp9_fu_1825_p3;
wire [0:0] sel_tmp12_fu_1853_p2;
wire [1:0] locy_0_1_t_fu_1846_p2;
wire [0:0] sel_tmp14_fu_1864_p2;
wire [7:0] sel_tmp13_fu_1857_p3;
wire [0:0] sel_tmp_fu_1908_p2;
wire [0:0] sel_tmp2_fu_1921_p2;
wire [7:0] col_buf_0_val_0_0_6_fu_1913_p3;
wire [7:0] right_border_buf_0_val_1_2_fu_1935_p3;
wire [0:0] tmp_115_0_0_1_fu_1979_p2;
wire [0:0] sel_tmp16_fu_2000_p2;
wire [1:0] locy_1_0_t_fu_1993_p2;
wire [0:0] sel_tmp18_fu_2011_p2;
wire [7:0] sel_tmp17_fu_2004_p3;
wire [0:0] sel_tmp20_fu_2032_p2;
wire [1:0] locy_1_1_t_fu_2025_p2;
wire [0:0] sel_tmp22_fu_2043_p2;
wire [7:0] sel_tmp21_fu_2036_p3;
wire [7:0] sel_tmp41_fu_2078_p3;
wire [7:0] right_border_buf_1_val_1_2_fu_2091_p3;
wire [7:0] right_border_buf_1_val_1_2_1_fu_2098_p3;
wire [0:0] tmp_115_1_0_1_fu_2145_p2;
wire [0:0] sel_tmp45_fu_2166_p2;
wire [1:0] locy_2_0_t_fu_2159_p2;
wire [0:0] sel_tmp47_fu_2177_p2;
wire [7:0] sel_tmp46_fu_2170_p3;
wire [0:0] sel_tmp48_fu_2198_p2;
wire [1:0] locy_2_1_t_fu_2191_p2;
wire [0:0] sel_tmp50_fu_2209_p2;
wire [7:0] sel_tmp49_fu_2202_p3;
wire [7:0] sel_tmp53_fu_2244_p3;
wire [7:0] right_border_buf_2_val_1_2_fu_2257_p3;
wire [7:0] right_border_buf_2_val_1_2_1_fu_2264_p3;
wire [0:0] tmp_115_2_0_1_fu_2311_p2;
wire [0:0] tmp_115_0_0_2_fu_2352_p2;
wire [0:0] tmp_115_1_0_2_fu_2382_p2;
wire [0:0] tmp_115_2_0_2_fu_2412_p2;
wire [7:0] temp_0_i_i_i_057_i_i_1_0_1_fu_2442_p3;
wire [0:0] tmp_115_0_1_1_fu_2447_p2;
wire [7:0] temp_0_i_i_i_057_i_i_1_1_1_fu_2459_p3;
wire [0:0] tmp_115_1_1_1_fu_2464_p2;
wire [7:0] temp_0_i_i_i_057_i_i_1_2_1_fu_2476_p3;
wire [0:0] tmp_115_2_1_1_fu_2481_p2;
wire [0:0] tmp_115_0_1_2_fu_2496_p2;
wire [0:0] tmp_115_1_1_2_fu_2515_p2;
wire [0:0] tmp_115_2_1_2_fu_2534_p2;
wire [7:0] temp_0_i_i_i_057_i_i_1_0_2_fu_2562_p3;
wire [0:0] tmp_115_0_2_1_fu_2567_p2;
wire [7:0] temp_0_i_i_i_057_i_i_1_1_2_fu_2579_p3;
wire [0:0] tmp_115_1_2_1_fu_2584_p2;
wire [7:0] temp_0_i_i_i_057_i_i_1_2_2_fu_2596_p3;
wire [0:0] tmp_115_2_2_1_fu_2601_p2;
wire [0:0] tmp_115_0_2_2_fu_2613_p2;
wire [0:0] tmp_115_1_2_2_fu_2624_p2;
wire [0:0] tmp_115_2_2_2_fu_2635_p2;
reg [7:0] ap_NS_fsm;
reg ap_sig_bdd_967;
reg ap_sig_bdd_979;
image_filter_Filter2D_k_buf_0_val_0 #(
.DataWidth( 8 ),
.AddressRange( 1920 ),
.AddressWidth( 11 ))
k_buf_0_val_0_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( k_buf_0_val_0_address0 ),
.ce0( k_buf_0_val_0_ce0 ),
.q0( k_buf_0_val_0_q0 ),
.address1( k_buf_0_val_0_address1 ),
.ce1( k_buf_0_val_0_ce1 ),
.we1( k_buf_0_val_0_we1 ),
.d1( k_buf_0_val_0_d1 )
);
image_filter_Filter2D_k_buf_0_val_0 #(
.DataWidth( 8 ),
.AddressRange( 1920 ),
.AddressWidth( 11 ))
k_buf_0_val_1_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( k_buf_0_val_1_address0 ),
.ce0( k_buf_0_val_1_ce0 ),
.q0( k_buf_0_val_1_q0 ),
.address1( k_buf_0_val_1_address1 ),
.ce1( k_buf_0_val_1_ce1 ),
.we1( k_buf_0_val_1_we1 ),
.d1( k_buf_0_val_1_d1 )
);
image_filter_Filter2D_k_buf_0_val_0 #(
.DataWidth( 8 ),
.AddressRange( 1920 ),
.AddressWidth( 11 ))
k_buf_0_val_2_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( k_buf_0_val_2_address0 ),
.ce0( k_buf_0_val_2_ce0 ),
.q0( k_buf_0_val_2_q0 ),
.address1( k_buf_0_val_2_address1 ),
.ce1( k_buf_0_val_2_ce1 ),
.we1( k_buf_0_val_2_we1 ),
.d1( k_buf_0_val_2_d1 )
);
image_filter_Filter2D_k_buf_0_val_0 #(
.DataWidth( 8 ),
.AddressRange( 1920 ),
.AddressWidth( 11 ))
k_buf_1_val_0_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( k_buf_1_val_0_address0 ),
.ce0( k_buf_1_val_0_ce0 ),
.q0( k_buf_1_val_0_q0 ),
.address1( k_buf_1_val_0_address1 ),
.ce1( k_buf_1_val_0_ce1 ),
.we1( k_buf_1_val_0_we1 ),
.d1( k_buf_1_val_0_d1 )
);
image_filter_Filter2D_k_buf_0_val_0 #(
.DataWidth( 8 ),
.AddressRange( 1920 ),
.AddressWidth( 11 ))
k_buf_1_val_1_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( k_buf_1_val_1_address0 ),
.ce0( k_buf_1_val_1_ce0 ),
.q0( k_buf_1_val_1_q0 ),
.address1( k_buf_1_val_1_address1 ),
.ce1( k_buf_1_val_1_ce1 ),
.we1( k_buf_1_val_1_we1 ),
.d1( k_buf_1_val_1_d1 )
);
image_filter_Filter2D_k_buf_0_val_0 #(
.DataWidth( 8 ),
.AddressRange( 1920 ),
.AddressWidth( 11 ))
k_buf_1_val_2_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( k_buf_1_val_2_address0 ),
.ce0( k_buf_1_val_2_ce0 ),
.q0( k_buf_1_val_2_q0 ),
.address1( k_buf_1_val_2_address1 ),
.ce1( k_buf_1_val_2_ce1 ),
.we1( k_buf_1_val_2_we1 ),
.d1( k_buf_1_val_2_d1 )
);
image_filter_Filter2D_k_buf_0_val_0 #(
.DataWidth( 8 ),
.AddressRange( 1920 ),
.AddressWidth( 11 ))
k_buf_2_val_0_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( k_buf_2_val_0_address0 ),
.ce0( k_buf_2_val_0_ce0 ),
.q0( k_buf_2_val_0_q0 ),
.address1( k_buf_2_val_0_address1 ),
.ce1( k_buf_2_val_0_ce1 ),
.we1( k_buf_2_val_0_we1 ),
.d1( k_buf_2_val_0_d1 )
);
image_filter_Filter2D_k_buf_0_val_0 #(
.DataWidth( 8 ),
.AddressRange( 1920 ),
.AddressWidth( 11 ))
k_buf_2_val_1_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( k_buf_2_val_1_address0 ),
.ce0( k_buf_2_val_1_ce0 ),
.q0( k_buf_2_val_1_q0 ),
.address1( k_buf_2_val_1_address1 ),
.ce1( k_buf_2_val_1_ce1 ),
.we1( k_buf_2_val_1_we1 ),
.d1( k_buf_2_val_1_d1 )
);
image_filter_Filter2D_k_buf_0_val_0 #(
.DataWidth( 8 ),
.AddressRange( 1920 ),
.AddressWidth( 11 ))
k_buf_2_val_2_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( k_buf_2_val_2_address0 ),
.ce0( k_buf_2_val_2_ce0 ),
.q0( k_buf_2_val_2_q0 ),
.address1( k_buf_2_val_2_address1 ),
.ce1( k_buf_2_val_2_ce1 ),
.we1( k_buf_2_val_2_we1 ),
.d1( k_buf_2_val_2_d1 )
);
image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_668(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p( grp_image_filter_borderInterpolate_fu_668_p ),
.len( grp_image_filter_borderInterpolate_fu_668_len ),
.borderType( grp_image_filter_borderInterpolate_fu_668_borderType ),
.ap_return( grp_image_filter_borderInterpolate_fu_668_ap_return ),
.ap_ce( grp_image_filter_borderInterpolate_fu_668_ap_ce )
);
image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_676(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p( grp_image_filter_borderInterpolate_fu_676_p ),
.len( grp_image_filter_borderInterpolate_fu_676_len ),
.borderType( grp_image_filter_borderInterpolate_fu_676_borderType ),
.ap_return( grp_image_filter_borderInterpolate_fu_676_ap_return ),
.ap_ce( grp_image_filter_borderInterpolate_fu_676_ap_ce )
);
image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_684(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p( grp_image_filter_borderInterpolate_fu_684_p ),
.len( grp_image_filter_borderInterpolate_fu_684_len ),
.borderType( grp_image_filter_borderInterpolate_fu_684_borderType ),
.ap_return( grp_image_filter_borderInterpolate_fu_684_ap_return ),
.ap_ce( grp_image_filter_borderInterpolate_fu_684_ap_ce )
);
image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_692(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p( grp_image_filter_borderInterpolate_fu_692_p ),
.len( grp_image_filter_borderInterpolate_fu_692_len ),
.borderType( grp_image_filter_borderInterpolate_fu_692_borderType ),
.ap_return( grp_image_filter_borderInterpolate_fu_692_ap_return ),
.ap_ce( grp_image_filter_borderInterpolate_fu_692_ap_ce )
);
image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_700(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p( grp_image_filter_borderInterpolate_fu_700_p ),
.len( grp_image_filter_borderInterpolate_fu_700_len ),
.borderType( grp_image_filter_borderInterpolate_fu_700_borderType ),
.ap_return( grp_image_filter_borderInterpolate_fu_700_ap_return ),
.ap_ce( grp_image_filter_borderInterpolate_fu_700_ap_ce )
);
image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_708(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p( grp_image_filter_borderInterpolate_fu_708_p ),
.len( grp_image_filter_borderInterpolate_fu_708_len ),
.borderType( grp_image_filter_borderInterpolate_fu_708_borderType ),
.ap_return( grp_image_filter_borderInterpolate_fu_708_ap_return ),
.ap_ce( grp_image_filter_borderInterpolate_fu_708_ap_ce )
);
image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_716(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p( grp_image_filter_borderInterpolate_fu_716_p ),
.len( grp_image_filter_borderInterpolate_fu_716_len ),
.borderType( grp_image_filter_borderInterpolate_fu_716_borderType ),
.ap_return( grp_image_filter_borderInterpolate_fu_716_ap_return ),
.ap_ce( grp_image_filter_borderInterpolate_fu_716_ap_ce )
);
image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_724(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p( grp_image_filter_borderInterpolate_fu_724_p ),
.len( grp_image_filter_borderInterpolate_fu_724_len ),
.borderType( grp_image_filter_borderInterpolate_fu_724_borderType ),
.ap_return( grp_image_filter_borderInterpolate_fu_724_ap_return ),
.ap_ce( grp_image_filter_borderInterpolate_fu_724_ap_ce )
);
image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_732(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p( grp_image_filter_borderInterpolate_fu_732_p ),
.len( grp_image_filter_borderInterpolate_fu_732_len ),
.borderType( grp_image_filter_borderInterpolate_fu_732_borderType ),
.ap_return( grp_image_filter_borderInterpolate_fu_732_ap_return ),
.ap_ce( grp_image_filter_borderInterpolate_fu_732_ap_ce )
);
image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_740(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p( grp_image_filter_borderInterpolate_fu_740_p ),
.len( grp_image_filter_borderInterpolate_fu_740_len ),
.borderType( grp_image_filter_borderInterpolate_fu_740_borderType ),
.ap_return( grp_image_filter_borderInterpolate_fu_740_ap_return ),
.ap_ce( grp_image_filter_borderInterpolate_fu_740_ap_ce )
);
image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_748(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p( grp_image_filter_borderInterpolate_fu_748_p ),
.len( grp_image_filter_borderInterpolate_fu_748_len ),
.borderType( grp_image_filter_borderInterpolate_fu_748_borderType ),
.ap_return( grp_image_filter_borderInterpolate_fu_748_ap_return ),
.ap_ce( grp_image_filter_borderInterpolate_fu_748_ap_ce )
);
image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_756(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p( grp_image_filter_borderInterpolate_fu_756_p ),
.len( grp_image_filter_borderInterpolate_fu_756_len ),
.borderType( grp_image_filter_borderInterpolate_fu_756_borderType ),
.ap_return( grp_image_filter_borderInterpolate_fu_756_ap_return ),
.ap_ce( grp_image_filter_borderInterpolate_fu_756_ap_ce )
);
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_done_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_done_reg
if (ap_rst == 1'b1) begin
ap_done_reg <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_continue)) begin
ap_done_reg <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) & (ap_const_lv1_0 == tmp_28_fu_977_p2))) begin
ap_done_reg <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_33_fu_1081_p2))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5)) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5)) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it10 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it10
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end
end
end
/// ap_reg_ppiten_pp0_it11 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it11
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end
end
end
/// ap_reg_ppiten_pp0_it12 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it12
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5)) begin
ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end
end
end
/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end
end
end
/// ap_reg_ppiten_pp0_it4 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end
end
end
/// ap_reg_ppiten_pp0_it5 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end
end
end
/// ap_reg_ppiten_pp0_it6 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end
end
end
/// ap_reg_ppiten_pp0_it7 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it7
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end
end
end
/// ap_reg_ppiten_pp0_it8 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it8
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
if (~(ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) begin
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
end else if ((ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) begin
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end
end
end
end
/// ap_reg_ppiten_pp0_it9 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it9
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st20_fsm_7)) begin
p_012_0_i_i_reg_645 <= i_V_reg_3108;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & ~(tmp_23_fu_926_p2 == ap_const_lv1_0))) begin
p_012_0_i_i_reg_645 <= ap_const_lv11_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2))) begin
p_025_0_i_i_reg_656 <= j_V_fu_1086_p2;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5)) begin
p_025_0_i_i_reg_656 <= ap_const_lv11_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6)))) begin
src_kernel_win_0_val_0_1_fu_226 <= right_border_buf_0_val_2_0_reg_3377;
end else if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_3202_pp0_it6) & (col_assign_3_reg_3409 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_3202_pp0_it6) & (col_assign_3_reg_3409 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_3202_pp0_it6) & ~(col_assign_3_reg_3409 == ap_const_lv2_1) & ~(col_assign_3_reg_3409 == ap_const_lv2_0)))) begin
src_kernel_win_0_val_0_1_fu_226 <= col_buf_0_val_0_0_16_fu_1926_p3;
end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_1)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_0)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_0)))) begin
src_kernel_win_0_val_0_1_fu_226 <= src_kernel_win_0_val_0_1_9_fu_1838_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6)))) begin
src_kernel_win_0_val_1_1_fu_242 <= right_border_buf_0_val_1_0_reg_3382;
end else if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_3202_pp0_it6) & (col_assign_3_reg_3409 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_3202_pp0_it6) & (col_assign_3_reg_3409 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_3202_pp0_it6) & ~(col_assign_3_reg_3409 == ap_const_lv2_1) & ~(col_assign_3_reg_3409 == ap_const_lv2_0)))) begin
src_kernel_win_0_val_1_1_fu_242 <= right_border_buf_0_val_1_2_20_fu_1943_p3;
end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_1)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_0)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_0)))) begin
src_kernel_win_0_val_1_1_fu_242 <= src_kernel_win_0_val_1_1_9_fu_1870_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_3202_pp0_it6) & ~(col_assign_3_reg_3409 == ap_const_lv2_1) & ~(col_assign_3_reg_3409 == ap_const_lv2_0))) begin
src_kernel_win_0_val_2_1_fu_238 <= right_border_buf_0_val_0_2_fu_186;
end else if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_3202_pp0_it6) & (col_assign_3_reg_3409 == ap_const_lv2_0))) begin
src_kernel_win_0_val_2_1_fu_238 <= right_border_buf_0_val_0_0_fu_178;
end else if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_3202_pp0_it6) & (col_assign_3_reg_3409 == ap_const_lv2_1))) begin
src_kernel_win_0_val_2_1_fu_238 <= right_border_buf_0_val_0_1_fu_182;
end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6)))) begin
src_kernel_win_0_val_2_1_fu_238 <= src_kernel_win_0_val_2_0_reg_3390;
end else if (((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_0))) begin
src_kernel_win_0_val_2_1_fu_238 <= col_buf_0_val_0_0_fu_214;
end else if (((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_1))) begin
src_kernel_win_0_val_2_1_fu_238 <= right_border_buf_0_val_1_0_reg_3382;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6)))) begin
src_kernel_win_1_val_0_1_fu_262 <= right_border_buf_1_val_2_0_reg_3415;
end else if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_94_reg_3447) & (col_assign_3_1_t1_reg_3453 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_94_reg_3447) & (col_assign_3_1_t1_reg_3453 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_94_reg_3447) & ~(col_assign_3_1_t1_reg_3453 == ap_const_lv2_1) & ~(col_assign_3_1_t1_reg_3453 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6) & ~(ap_const_lv1_0 == tmp_94_reg_3447)))) begin
src_kernel_win_1_val_0_1_fu_262 <= src_kernel_win_1_val_0_1_10_fu_2084_p3;
end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_1)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_0)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_0)))) begin
src_kernel_win_1_val_0_1_fu_262 <= src_kernel_win_1_val_0_1_9_fu_2017_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6)))) begin
src_kernel_win_1_val_1_1_fu_278 <= right_border_buf_1_val_1_0_reg_3420;
end else if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_94_reg_3447) & (col_assign_3_1_t1_reg_3453 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_94_reg_3447) & (col_assign_3_1_t1_reg_3453 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_94_reg_3447) & ~(col_assign_3_1_t1_reg_3453 == ap_const_lv2_1) & ~(col_assign_3_1_t1_reg_3453 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6) & ~(ap_const_lv1_0 == tmp_94_reg_3447)))) begin
src_kernel_win_1_val_1_1_fu_278 <= src_kernel_win_1_val_1_1_10_fu_2105_p3;
end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_1)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_0)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_0)))) begin
src_kernel_win_1_val_1_1_fu_278 <= src_kernel_win_1_val_1_1_9_fu_2049_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6) & ~(ap_const_lv1_0 == tmp_94_reg_3447))) begin
src_kernel_win_1_val_2_1_fu_274 <= ap_const_lv8_0;
end else if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_94_reg_3447) & ~(col_assign_3_1_t1_reg_3453 == ap_const_lv2_1) & ~(col_assign_3_1_t1_reg_3453 == ap_const_lv2_0))) begin
src_kernel_win_1_val_2_1_fu_274 <= right_border_buf_1_val_0_2_fu_198;
end else if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_94_reg_3447) & (col_assign_3_1_t1_reg_3453 == ap_const_lv2_0))) begin
src_kernel_win_1_val_2_1_fu_274 <= right_border_buf_1_val_0_0_fu_190;
end else if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_94_reg_3447) & (col_assign_3_1_t1_reg_3453 == ap_const_lv2_1))) begin
src_kernel_win_1_val_2_1_fu_274 <= right_border_buf_1_val_0_1_fu_194;
end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6)))) begin
src_kernel_win_1_val_2_1_fu_274 <= src_kernel_win_1_val_2_0_reg_3428;
end else if (((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_0))) begin
src_kernel_win_1_val_2_1_fu_274 <= col_buf_1_val_0_0_fu_218;
end else if (((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_1))) begin
src_kernel_win_1_val_2_1_fu_274 <= right_border_buf_1_val_1_0_reg_3420;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6)))) begin
src_kernel_win_2_val_0_1_fu_298 <= right_border_buf_2_val_2_0_reg_3474;
end else if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_103_reg_3506) & (col_assign_3_2_t1_reg_3512 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_103_reg_3506) & (col_assign_3_2_t1_reg_3512 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_103_reg_3506) & ~(col_assign_3_2_t1_reg_3512 == ap_const_lv2_1) & ~(col_assign_3_2_t1_reg_3512 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6) & ~(ap_const_lv1_0 == tmp_103_reg_3506)))) begin
src_kernel_win_2_val_0_1_fu_298 <= src_kernel_win_2_val_0_1_10_fu_2250_p3;
end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_1)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_0)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_0)))) begin
src_kernel_win_2_val_0_1_fu_298 <= src_kernel_win_2_val_0_1_9_fu_2183_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6)))) begin
src_kernel_win_2_val_1_1_fu_314 <= right_border_buf_2_val_1_0_reg_3479;
end else if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_103_reg_3506) & (col_assign_3_2_t1_reg_3512 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_103_reg_3506) & (col_assign_3_2_t1_reg_3512 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_103_reg_3506) & ~(col_assign_3_2_t1_reg_3512 == ap_const_lv2_1) & ~(col_assign_3_2_t1_reg_3512 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6) & ~(ap_const_lv1_0 == tmp_103_reg_3506)))) begin
src_kernel_win_2_val_1_1_fu_314 <= src_kernel_win_2_val_1_1_10_fu_2271_p3;
end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_1)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_0)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_0)))) begin
src_kernel_win_2_val_1_1_fu_314 <= src_kernel_win_2_val_1_1_9_fu_2215_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6) & ~(ap_const_lv1_0 == tmp_103_reg_3506))) begin
src_kernel_win_2_val_2_1_fu_310 <= ap_const_lv8_0;
end else if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_103_reg_3506) & ~(col_assign_3_2_t1_reg_3512 == ap_const_lv2_1) & ~(col_assign_3_2_t1_reg_3512 == ap_const_lv2_0))) begin
src_kernel_win_2_val_2_1_fu_310 <= right_border_buf_2_val_0_2_fu_210;
end else if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_103_reg_3506) & (col_assign_3_2_t1_reg_3512 == ap_const_lv2_0))) begin
src_kernel_win_2_val_2_1_fu_310 <= right_border_buf_2_val_0_0_fu_202;
end else if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_103_reg_3506) & (col_assign_3_2_t1_reg_3512 == ap_const_lv2_1))) begin
src_kernel_win_2_val_2_1_fu_310 <= right_border_buf_2_val_0_1_fu_206;
end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6)))) begin
src_kernel_win_2_val_2_1_fu_310 <= src_kernel_win_2_val_2_0_reg_3487;
end else if (((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_0))) begin
src_kernel_win_2_val_2_1_fu_310 <= col_buf_2_val_0_0_fu_222;
end else if (((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_1))) begin
src_kernel_win_2_val_2_1_fu_310 <= right_border_buf_2_val_1_0_reg_3479;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_67)) begin
tmp_15_reg_612 <= ap_const_lv2_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == tmp_s_fu_902_p2))) begin
tmp_15_reg_612 <= tmp_16_fu_896_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(ap_const_lv1_0 == tmp_s_fu_902_p2))) begin
tmp_18_reg_623 <= ap_const_lv2_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & (ap_const_lv1_0 == tmp_20_fu_914_p2))) begin
tmp_18_reg_623 <= tmp_19_fu_908_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~(ap_const_lv1_0 == tmp_20_fu_914_p2))) begin
tmp_21_reg_634 <= ap_const_lv2_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (tmp_23_fu_926_p2 == ap_const_lv1_0))) begin
tmp_21_reg_634 <= tmp_22_fu_920_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2))) begin
ImagLoc_x_reg_3193 <= ImagLoc_x_fu_1113_p2;
or_cond219_i_i_reg_3189 <= or_cond219_i_i_fu_1108_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) & ~(ap_const_lv1_0 == tmp_28_fu_977_p2))) begin
ImagLoc_y_reg_3118 <= ImagLoc_y_fu_994_p2;
or_cond_2_reg_3126 <= or_cond_2_fu_1021_p2;
tmp_30_reg_3113 <= tmp_30_fu_988_p2;
tmp_32_reg_3135 <= tmp_32_fu_1035_p3;
tmp_77_reg_3131 <= ImagLoc_y_fu_994_p2[ap_const_lv32_B];
tmp_78_reg_3149 <= tmp_78_fu_1049_p1;
tmp_79_reg_3155 <= tmp_79_fu_1053_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
ap_reg_ppstg_col_assign_reg_3218_pp0_it1 <= col_assign_reg_3218;
ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it1 <= or_cond219_i_i_reg_3189;
ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it1 <= or_cond2_1_reg_3228;
ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it1 <= or_cond2_2_reg_3248;
ap_reg_ppstg_or_cond2_reg_3206_pp0_it1 <= or_cond2_reg_3206;
ap_reg_ppstg_tmp_102_reg_3260_pp0_it1 <= tmp_102_reg_3260;
ap_reg_ppstg_tmp_33_reg_3180_pp0_it1 <= tmp_33_reg_3180;
ap_reg_ppstg_tmp_37_reg_3202_pp0_it1 <= tmp_37_reg_3202;
ap_reg_ppstg_tmp_38_reg_3214_pp0_it1 <= tmp_38_reg_3214;
ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it1 <= tmp_63_1_reg_3224;
ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it1 <= tmp_63_2_reg_3244;
ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it1 <= tmp_66_1_reg_3236;
ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it1 <= tmp_66_2_reg_3256;
ap_reg_ppstg_tmp_84_reg_3210_pp0_it1 <= tmp_84_reg_3210;
ap_reg_ppstg_tmp_89_reg_3232_pp0_it1 <= tmp_89_reg_3232;
ap_reg_ppstg_tmp_93_reg_3240_pp0_it1 <= tmp_93_reg_3240;
ap_reg_ppstg_tmp_98_reg_3252_pp0_it1 <= tmp_98_reg_3252;
tmp_33_reg_3180 <= tmp_33_fu_1081_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
ap_reg_ppstg_col_assign_reg_3218_pp0_it2 <= ap_reg_ppstg_col_assign_reg_3218_pp0_it1;
ap_reg_ppstg_col_assign_reg_3218_pp0_it3 <= ap_reg_ppstg_col_assign_reg_3218_pp0_it2;
ap_reg_ppstg_col_assign_reg_3218_pp0_it4 <= ap_reg_ppstg_col_assign_reg_3218_pp0_it3;
ap_reg_ppstg_col_assign_reg_3218_pp0_it5 <= ap_reg_ppstg_col_assign_reg_3218_pp0_it4;
ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it5 <= locy_0_2_t_reg_3301;
ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 <= ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it5;
ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it5 <= locy_1_2_t_reg_3313;
ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 <= ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it5;
ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it5 <= locy_2_2_t_reg_3325;
ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 <= ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it5;
ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it10 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it9;
ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it10;
ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it2 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it1;
ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it3 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it2;
ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it4 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it3;
ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it5 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it4;
ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it6 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it5;
ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it7 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it6;
ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it8 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it7;
ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it9 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it8;
ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it2 <= ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it1;
ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it3 <= ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it2;
ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it4 <= ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it3;
ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5 <= ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it4;
ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6 <= ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5;
ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it2 <= ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it1;
ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it3 <= ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it2;
ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it4 <= ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it3;
ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5 <= ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it4;
ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6 <= ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5;
ap_reg_ppstg_or_cond2_reg_3206_pp0_it2 <= ap_reg_ppstg_or_cond2_reg_3206_pp0_it1;
ap_reg_ppstg_or_cond2_reg_3206_pp0_it3 <= ap_reg_ppstg_or_cond2_reg_3206_pp0_it2;
ap_reg_ppstg_or_cond2_reg_3206_pp0_it4 <= ap_reg_ppstg_or_cond2_reg_3206_pp0_it3;
ap_reg_ppstg_or_cond2_reg_3206_pp0_it5 <= ap_reg_ppstg_or_cond2_reg_3206_pp0_it4;
ap_reg_ppstg_or_cond2_reg_3206_pp0_it6 <= ap_reg_ppstg_or_cond2_reg_3206_pp0_it5;
ap_reg_ppstg_src_kernel_win_0_val_0_1_12_reg_3533_pp0_it10 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_12_reg_3533_pp0_it9;
ap_reg_ppstg_src_kernel_win_0_val_0_1_12_reg_3533_pp0_it8 <= src_kernel_win_0_val_0_1_12_reg_3533;
ap_reg_ppstg_src_kernel_win_0_val_0_1_12_reg_3533_pp0_it9 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_12_reg_3533_pp0_it8;
ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it10 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it9;
ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it11 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it10;
ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it9 <= src_kernel_win_0_val_0_1_lo_reg_3593;
ap_reg_ppstg_src_kernel_win_0_val_1_1_12_reg_3540_pp0_it8 <= src_kernel_win_0_val_1_1_12_reg_3540;
ap_reg_ppstg_src_kernel_win_0_val_1_1_lo_reg_3599_pp0_it9 <= src_kernel_win_0_val_1_1_lo_reg_3599;
ap_reg_ppstg_src_kernel_win_1_val_0_1_12_reg_3547_pp0_it10 <= ap_reg_ppstg_src_kernel_win_1_val_0_1_12_reg_3547_pp0_it9;
ap_reg_ppstg_src_kernel_win_1_val_0_1_12_reg_3547_pp0_it8 <= src_kernel_win_1_val_0_1_12_reg_3547;
ap_reg_ppstg_src_kernel_win_1_val_0_1_12_reg_3547_pp0_it9 <= ap_reg_ppstg_src_kernel_win_1_val_0_1_12_reg_3547_pp0_it8;
ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it10 <= ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it9;
ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it11 <= ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it10;
ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it9 <= src_kernel_win_1_val_0_1_lo_reg_3620;
ap_reg_ppstg_src_kernel_win_1_val_1_1_12_reg_3554_pp0_it8 <= src_kernel_win_1_val_1_1_12_reg_3554;
ap_reg_ppstg_src_kernel_win_1_val_1_1_lo_reg_3626_pp0_it9 <= src_kernel_win_1_val_1_1_lo_reg_3626;
ap_reg_ppstg_src_kernel_win_2_val_0_1_12_reg_3561_pp0_it10 <= ap_reg_ppstg_src_kernel_win_2_val_0_1_12_reg_3561_pp0_it9;
ap_reg_ppstg_src_kernel_win_2_val_0_1_12_reg_3561_pp0_it8 <= src_kernel_win_2_val_0_1_12_reg_3561;
ap_reg_ppstg_src_kernel_win_2_val_0_1_12_reg_3561_pp0_it9 <= ap_reg_ppstg_src_kernel_win_2_val_0_1_12_reg_3561_pp0_it8;
ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it10 <= ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it9;
ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it11 <= ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it10;
ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it9 <= src_kernel_win_2_val_0_1_lo_reg_3647;
ap_reg_ppstg_src_kernel_win_2_val_1_1_12_reg_3568_pp0_it8 <= src_kernel_win_2_val_1_1_12_reg_3568;
ap_reg_ppstg_src_kernel_win_2_val_1_1_lo_reg_3653_pp0_it9 <= src_kernel_win_2_val_1_1_lo_reg_3653;
ap_reg_ppstg_tmp_102_reg_3260_pp0_it2 <= ap_reg_ppstg_tmp_102_reg_3260_pp0_it1;
ap_reg_ppstg_tmp_102_reg_3260_pp0_it3 <= ap_reg_ppstg_tmp_102_reg_3260_pp0_it2;
ap_reg_ppstg_tmp_102_reg_3260_pp0_it4 <= ap_reg_ppstg_tmp_102_reg_3260_pp0_it3;
ap_reg_ppstg_tmp_102_reg_3260_pp0_it5 <= ap_reg_ppstg_tmp_102_reg_3260_pp0_it4;
ap_reg_ppstg_tmp_105_reg_3270_pp0_it2 <= tmp_105_reg_3270;
ap_reg_ppstg_tmp_105_reg_3270_pp0_it3 <= ap_reg_ppstg_tmp_105_reg_3270_pp0_it2;
ap_reg_ppstg_tmp_105_reg_3270_pp0_it4 <= ap_reg_ppstg_tmp_105_reg_3270_pp0_it3;
ap_reg_ppstg_tmp_105_reg_3270_pp0_it5 <= ap_reg_ppstg_tmp_105_reg_3270_pp0_it4;
ap_reg_ppstg_tmp_33_reg_3180_pp0_it2 <= ap_reg_ppstg_tmp_33_reg_3180_pp0_it1;
ap_reg_ppstg_tmp_33_reg_3180_pp0_it3 <= ap_reg_ppstg_tmp_33_reg_3180_pp0_it2;
ap_reg_ppstg_tmp_33_reg_3180_pp0_it4 <= ap_reg_ppstg_tmp_33_reg_3180_pp0_it3;
ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 <= ap_reg_ppstg_tmp_33_reg_3180_pp0_it4;
ap_reg_ppstg_tmp_33_reg_3180_pp0_it6 <= ap_reg_ppstg_tmp_33_reg_3180_pp0_it5;
ap_reg_ppstg_tmp_33_reg_3180_pp0_it7 <= ap_reg_ppstg_tmp_33_reg_3180_pp0_it6;
ap_reg_ppstg_tmp_33_reg_3180_pp0_it8 <= ap_reg_ppstg_tmp_33_reg_3180_pp0_it7;
ap_reg_ppstg_tmp_33_reg_3180_pp0_it9 <= ap_reg_ppstg_tmp_33_reg_3180_pp0_it8;
ap_reg_ppstg_tmp_37_reg_3202_pp0_it2 <= ap_reg_ppstg_tmp_37_reg_3202_pp0_it1;
ap_reg_ppstg_tmp_37_reg_3202_pp0_it3 <= ap_reg_ppstg_tmp_37_reg_3202_pp0_it2;
ap_reg_ppstg_tmp_37_reg_3202_pp0_it4 <= ap_reg_ppstg_tmp_37_reg_3202_pp0_it3;
ap_reg_ppstg_tmp_37_reg_3202_pp0_it5 <= ap_reg_ppstg_tmp_37_reg_3202_pp0_it4;
ap_reg_ppstg_tmp_37_reg_3202_pp0_it6 <= ap_reg_ppstg_tmp_37_reg_3202_pp0_it5;
ap_reg_ppstg_tmp_38_reg_3214_pp0_it2 <= ap_reg_ppstg_tmp_38_reg_3214_pp0_it1;
ap_reg_ppstg_tmp_38_reg_3214_pp0_it3 <= ap_reg_ppstg_tmp_38_reg_3214_pp0_it2;
ap_reg_ppstg_tmp_38_reg_3214_pp0_it4 <= ap_reg_ppstg_tmp_38_reg_3214_pp0_it3;
ap_reg_ppstg_tmp_38_reg_3214_pp0_it5 <= ap_reg_ppstg_tmp_38_reg_3214_pp0_it4;
ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it2 <= ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it1;
ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it3 <= ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it2;
ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it4 <= ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it3;
ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it5 <= ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it4;
ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6 <= ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it5;
ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it2 <= ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it1;
ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it3 <= ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it2;
ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it4 <= ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it3;
ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it5 <= ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it4;
ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6 <= ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it5;
ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it2 <= ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it1;
ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it3 <= ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it2;
ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it4 <= ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it3;
ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5 <= ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it4;
ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it2 <= ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it1;
ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it3 <= ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it2;
ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it4 <= ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it3;
ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5 <= ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it4;
ap_reg_ppstg_tmp_83_reg_3296_pp0_it5 <= tmp_83_reg_3296;
ap_reg_ppstg_tmp_84_reg_3210_pp0_it2 <= ap_reg_ppstg_tmp_84_reg_3210_pp0_it1;
ap_reg_ppstg_tmp_84_reg_3210_pp0_it3 <= ap_reg_ppstg_tmp_84_reg_3210_pp0_it2;
ap_reg_ppstg_tmp_84_reg_3210_pp0_it4 <= ap_reg_ppstg_tmp_84_reg_3210_pp0_it3;
ap_reg_ppstg_tmp_84_reg_3210_pp0_it5 <= ap_reg_ppstg_tmp_84_reg_3210_pp0_it4;
ap_reg_ppstg_tmp_84_reg_3210_pp0_it6 <= ap_reg_ppstg_tmp_84_reg_3210_pp0_it5;
ap_reg_ppstg_tmp_89_reg_3232_pp0_it2 <= ap_reg_ppstg_tmp_89_reg_3232_pp0_it1;
ap_reg_ppstg_tmp_89_reg_3232_pp0_it3 <= ap_reg_ppstg_tmp_89_reg_3232_pp0_it2;
ap_reg_ppstg_tmp_89_reg_3232_pp0_it4 <= ap_reg_ppstg_tmp_89_reg_3232_pp0_it3;
ap_reg_ppstg_tmp_89_reg_3232_pp0_it5 <= ap_reg_ppstg_tmp_89_reg_3232_pp0_it4;
ap_reg_ppstg_tmp_89_reg_3232_pp0_it6 <= ap_reg_ppstg_tmp_89_reg_3232_pp0_it5;
ap_reg_ppstg_tmp_93_reg_3240_pp0_it2 <= ap_reg_ppstg_tmp_93_reg_3240_pp0_it1;
ap_reg_ppstg_tmp_93_reg_3240_pp0_it3 <= ap_reg_ppstg_tmp_93_reg_3240_pp0_it2;
ap_reg_ppstg_tmp_93_reg_3240_pp0_it4 <= ap_reg_ppstg_tmp_93_reg_3240_pp0_it3;
ap_reg_ppstg_tmp_93_reg_3240_pp0_it5 <= ap_reg_ppstg_tmp_93_reg_3240_pp0_it4;
ap_reg_ppstg_tmp_96_reg_3264_pp0_it2 <= tmp_96_reg_3264;
ap_reg_ppstg_tmp_96_reg_3264_pp0_it3 <= ap_reg_ppstg_tmp_96_reg_3264_pp0_it2;
ap_reg_ppstg_tmp_96_reg_3264_pp0_it4 <= ap_reg_ppstg_tmp_96_reg_3264_pp0_it3;
ap_reg_ppstg_tmp_96_reg_3264_pp0_it5 <= ap_reg_ppstg_tmp_96_reg_3264_pp0_it4;
ap_reg_ppstg_tmp_98_reg_3252_pp0_it2 <= ap_reg_ppstg_tmp_98_reg_3252_pp0_it1;
ap_reg_ppstg_tmp_98_reg_3252_pp0_it3 <= ap_reg_ppstg_tmp_98_reg_3252_pp0_it2;
ap_reg_ppstg_tmp_98_reg_3252_pp0_it4 <= ap_reg_ppstg_tmp_98_reg_3252_pp0_it3;
ap_reg_ppstg_tmp_98_reg_3252_pp0_it5 <= ap_reg_ppstg_tmp_98_reg_3252_pp0_it4;
ap_reg_ppstg_tmp_98_reg_3252_pp0_it6 <= ap_reg_ppstg_tmp_98_reg_3252_pp0_it5;
ap_reg_ppstg_x_1_reg_3305_pp0_it5 <= x_1_reg_3305;
ap_reg_ppstg_x_2_reg_3317_pp0_it5 <= x_2_reg_3317;
src_kernel_win_0_val_0_1_12_reg_3533 <= src_kernel_win_0_val_0_1_fu_226;
src_kernel_win_0_val_1_1_12_reg_3540 <= src_kernel_win_0_val_1_1_fu_242;
src_kernel_win_1_val_0_1_12_reg_3547 <= src_kernel_win_1_val_0_1_fu_262;
src_kernel_win_1_val_1_1_12_reg_3554 <= src_kernel_win_1_val_1_1_fu_278;
src_kernel_win_2_val_0_1_12_reg_3561 <= src_kernel_win_2_val_0_1_fu_298;
src_kernel_win_2_val_1_1_12_reg_3568 <= src_kernel_win_2_val_1_1_fu_314;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5)) begin
brmerge_reg_3176 <= brmerge_fu_1072_p2;
y_1_2_1_reg_3169 <= y_1_2_1_fu_1067_p2;
y_1_2_reg_3162 <= y_1_2_fu_1062_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it5))) begin
col_assign_3_1_t1_reg_3453 <= col_assign_3_1_t1_fu_1450_p2;
col_buf_1_val_0_0_16_reg_3457 <= col_buf_1_val_0_0_16_fu_1475_p3;
sel_tmp43_reg_3463 <= sel_tmp43_fu_1489_p2;
sel_tmp44_reg_3469 <= sel_tmp44_fu_1495_p2;
tmp_94_reg_3447 <= ap_reg_ppstg_x_1_reg_3305_pp0_it5[ap_const_lv32_E];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it5))) begin
col_assign_3_2_t1_reg_3512 <= col_assign_3_2_t1_fu_1636_p2;
col_buf_2_val_0_0_16_reg_3516 <= col_buf_2_val_0_0_16_fu_1661_p3;
sel_tmp55_reg_3522 <= sel_tmp55_fu_1675_p2;
sel_tmp56_reg_3528 <= sel_tmp56_fu_1681_p2;
tmp_103_reg_3506 <= ap_reg_ppstg_x_2_reg_3317_pp0_it5[ap_const_lv32_E];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_3202_pp0_it5))) begin
col_assign_3_reg_3409 <= col_assign_3_fu_1319_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2) & ~(ap_const_lv1_0 == or_cond2_fu_1138_p2) & (ap_const_lv1_0 == tmp_38_fu_1152_p2))) begin
col_assign_reg_3218 <= col_assign_fu_1157_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5) & (ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_0))) begin
col_buf_0_val_0_0_11_fu_346 <= k_buf_0_val_0_q0;
right_border_buf_0_val_0_0_fu_178 <= k_buf_0_val_2_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5) & (ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_1))) begin
col_buf_0_val_0_0_12_fu_350 <= k_buf_0_val_0_q0;
right_border_buf_0_val_0_1_fu_182 <= k_buf_0_val_2_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5) & ~(ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_1) & ~(ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_0))) begin
col_buf_0_val_0_0_13_fu_354 <= k_buf_0_val_0_q0;
right_border_buf_0_val_0_2_fu_186 <= k_buf_0_val_2_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
col_buf_0_val_0_0_fu_214 <= k_buf_0_val_0_q0;
col_buf_1_val_0_0_fu_218 <= k_buf_1_val_0_q0;
col_buf_2_val_0_0_fu_222 <= k_buf_2_val_0_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5) & ~(ap_reg_ppstg_tmp_96_reg_3264_pp0_it5 == ap_const_lv2_1) & ~(ap_reg_ppstg_tmp_96_reg_3264_pp0_it5 == ap_const_lv2_0))) begin
col_buf_1_val_0_0_11_fu_306 <= k_buf_1_val_0_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5) & (ap_reg_ppstg_tmp_96_reg_3264_pp0_it5 == ap_const_lv2_1))) begin
col_buf_1_val_0_0_12_fu_322 <= k_buf_1_val_0_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5) & (ap_reg_ppstg_tmp_96_reg_3264_pp0_it5 == ap_const_lv2_0))) begin
col_buf_1_val_0_0_13_fu_330 <= k_buf_1_val_0_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5) & ~(ap_reg_ppstg_tmp_105_reg_3270_pp0_it5 == ap_const_lv2_1) & ~(ap_reg_ppstg_tmp_105_reg_3270_pp0_it5 == ap_const_lv2_0))) begin
col_buf_2_val_0_0_11_fu_234 <= k_buf_2_val_0_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5) & (ap_reg_ppstg_tmp_105_reg_3270_pp0_it5 == ap_const_lv2_1))) begin
col_buf_2_val_0_0_12_fu_250 <= k_buf_2_val_0_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5) & (ap_reg_ppstg_tmp_105_reg_3270_pp0_it5 == ap_const_lv2_0))) begin
col_buf_2_val_0_0_13_fu_258 <= k_buf_2_val_0_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_67)) begin
cols_assign_cast1_reg_2757[0] <= cols_assign_cast1_fu_892_p1[0];
cols_assign_cast1_reg_2757[1] <= cols_assign_cast1_fu_892_p1[1];
cols_assign_cast1_reg_2757[2] <= cols_assign_cast1_fu_892_p1[2];
cols_assign_cast1_reg_2757[3] <= cols_assign_cast1_fu_892_p1[3];
cols_assign_cast1_reg_2757[4] <= cols_assign_cast1_fu_892_p1[4];
cols_assign_cast1_reg_2757[5] <= cols_assign_cast1_fu_892_p1[5];
cols_assign_cast1_reg_2757[6] <= cols_assign_cast1_fu_892_p1[6];
cols_assign_cast1_reg_2757[7] <= cols_assign_cast1_fu_892_p1[7];
cols_assign_cast1_reg_2757[8] <= cols_assign_cast1_fu_892_p1[8];
cols_assign_cast1_reg_2757[9] <= cols_assign_cast1_fu_892_p1[9];
cols_assign_cast1_reg_2757[10] <= cols_assign_cast1_fu_892_p1[10];
cols_assign_cast1_reg_2757[11] <= cols_assign_cast1_fu_892_p1[11];
tmp_72_reg_2751 <= tmp_72_fu_888_p1;
tmp_reg_2745 <= tmp_fu_884_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & ~(tmp_23_fu_926_p2 == ap_const_lv1_0))) begin
heightloop_reg_3051 <= heightloop_fu_932_p2;
p_neg226_i_i_reg_3068 <= p_neg226_i_i_fu_951_p2;
ref_cast_reg_3089[0] <= ref_cast_fu_965_p1[0];
ref_cast_reg_3089[1] <= ref_cast_fu_965_p1[1];
ref_cast_reg_3089[2] <= ref_cast_fu_965_p1[2];
ref_cast_reg_3089[3] <= ref_cast_fu_965_p1[3];
ref_cast_reg_3089[4] <= ref_cast_fu_965_p1[4];
ref_cast_reg_3089[5] <= ref_cast_fu_965_p1[5];
ref_cast_reg_3089[6] <= ref_cast_fu_965_p1[6];
ref_cast_reg_3089[7] <= ref_cast_fu_965_p1[7];
ref_cast_reg_3089[8] <= ref_cast_fu_965_p1[8];
ref_cast_reg_3089[9] <= ref_cast_fu_965_p1[9];
ref_cast_reg_3089[10] <= ref_cast_fu_965_p1[10];
ref_reg_3084 <= ref_fu_960_p2;
tmp_28_cast_reg_3061[0] <= tmp_28_cast_fu_947_p1[0];
tmp_28_cast_reg_3061[1] <= tmp_28_cast_fu_947_p1[1];
tmp_28_cast_reg_3061[2] <= tmp_28_cast_fu_947_p1[2];
tmp_28_cast_reg_3061[3] <= tmp_28_cast_fu_947_p1[3];
tmp_28_cast_reg_3061[4] <= tmp_28_cast_fu_947_p1[4];
tmp_28_cast_reg_3061[5] <= tmp_28_cast_fu_947_p1[5];
tmp_28_cast_reg_3061[6] <= tmp_28_cast_fu_947_p1[6];
tmp_28_cast_reg_3061[7] <= tmp_28_cast_fu_947_p1[7];
tmp_28_cast_reg_3061[8] <= tmp_28_cast_fu_947_p1[8];
tmp_28_cast_reg_3061[9] <= tmp_28_cast_fu_947_p1[9];
tmp_28_cast_reg_3061[10] <= tmp_28_cast_fu_947_p1[10];
tmp_73_reg_3076 <= tmp_73_fu_956_p1;
tmp_74_reg_3094 <= tmp_74_fu_969_p1;
widthloop_reg_3056 <= widthloop_fu_937_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) begin
i_V_reg_3108 <= i_V_fu_982_p2;
tmp_29_cast_cast3_reg_3099[0] <= tmp_29_cast_cast3_fu_973_p1[0];
tmp_29_cast_cast3_reg_3099[1] <= tmp_29_cast_cast3_fu_973_p1[1];
tmp_29_cast_cast3_reg_3099[2] <= tmp_29_cast_cast3_fu_973_p1[2];
tmp_29_cast_cast3_reg_3099[3] <= tmp_29_cast_cast3_fu_973_p1[3];
tmp_29_cast_cast3_reg_3099[4] <= tmp_29_cast_cast3_fu_973_p1[4];
tmp_29_cast_cast3_reg_3099[5] <= tmp_29_cast_cast3_fu_973_p1[5];
tmp_29_cast_cast3_reg_3099[6] <= tmp_29_cast_cast3_fu_973_p1[6];
tmp_29_cast_cast3_reg_3099[7] <= tmp_29_cast_cast3_fu_973_p1[7];
tmp_29_cast_cast3_reg_3099[8] <= tmp_29_cast_cast3_fu_973_p1[8];
tmp_29_cast_cast3_reg_3099[9] <= tmp_29_cast_cast3_fu_973_p1[9];
tmp_29_cast_cast3_reg_3099[10] <= tmp_29_cast_cast3_fu_973_p1[10];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it4))) begin
k_buf_0_val_0_addr_reg_3329 <= tmp_35_fu_1287_p1;
k_buf_0_val_1_addr_reg_3335 <= tmp_35_fu_1287_p1;
k_buf_0_val_2_addr_reg_3341 <= tmp_35_fu_1287_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it3))) begin
locy_0_2_t_reg_3301 <= locy_0_2_t_fu_1272_p2;
locy_1_2_t_reg_3313 <= locy_1_2_t_fu_1276_p2;
locy_2_2_t_reg_3325 <= locy_2_2_t_fu_1280_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2))) begin
or_cond2_1_reg_3228 <= or_cond2_1_fu_1173_p2;
or_cond2_2_reg_3248 <= or_cond2_2_fu_1212_p2;
or_cond2_reg_3206 <= or_cond2_fu_1138_p2;
tmp_37_reg_3202 <= tmp_37_fu_1133_p2;
tmp_63_1_reg_3224 <= tmp_63_1_fu_1168_p2;
tmp_63_2_reg_3244 <= tmp_63_2_fu_1207_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
right_border_buf_0_val_1_0_reg_3382 <= k_buf_0_val_1_q0;
right_border_buf_0_val_2_0_reg_3377 <= k_buf_0_val_0_q0;
right_border_buf_1_val_1_0_reg_3420 <= k_buf_1_val_1_q0;
right_border_buf_1_val_2_0_reg_3415 <= k_buf_1_val_0_q0;
right_border_buf_2_val_1_0_reg_3479 <= k_buf_2_val_1_q0;
right_border_buf_2_val_2_0_reg_3474 <= k_buf_2_val_0_q0;
src_kernel_win_0_val_2_0_reg_3390 <= k_buf_0_val_2_q0;
src_kernel_win_1_val_2_0_reg_3428 <= k_buf_1_val_2_q0;
src_kernel_win_2_val_2_0_reg_3487 <= k_buf_2_val_2_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5) & (ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5) & (ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5) & ~(ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_1) & ~(ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_0)))) begin
right_border_buf_0_val_1_2_14_fu_334 <= right_border_buf_0_val_1_2_19_fu_1391_p3;
right_border_buf_0_val_1_2_15_fu_338 <= right_border_buf_0_val_1_2_5_fu_1382_p3;
right_border_buf_0_val_1_2_16_fu_342 <= right_border_buf_0_val_1_2_3_fu_1365_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5) & (ap_reg_ppstg_tmp_93_reg_3240_pp0_it5 == ap_const_lv2_0))) begin
right_border_buf_1_val_0_0_fu_190 <= k_buf_1_val_2_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5) & (ap_reg_ppstg_tmp_93_reg_3240_pp0_it5 == ap_const_lv2_1))) begin
right_border_buf_1_val_0_1_fu_194 <= k_buf_1_val_2_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5) & ~(ap_reg_ppstg_tmp_93_reg_3240_pp0_it5 == ap_const_lv2_1) & ~(ap_reg_ppstg_tmp_93_reg_3240_pp0_it5 == ap_const_lv2_0))) begin
right_border_buf_1_val_0_2_fu_198 <= k_buf_1_val_2_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5) & ~(ap_reg_ppstg_tmp_96_reg_3264_pp0_it5 == ap_const_lv2_1) & ~(ap_reg_ppstg_tmp_96_reg_3264_pp0_it5 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5) & (ap_reg_ppstg_tmp_96_reg_3264_pp0_it5 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5) & (ap_reg_ppstg_tmp_96_reg_3264_pp0_it5 == ap_const_lv2_0)))) begin
right_border_buf_1_val_1_2_12_fu_358 <= right_border_buf_1_val_1_2_19_fu_1577_p3;
right_border_buf_1_val_1_2_15_fu_362 <= right_border_buf_1_val_1_2_6_74_fu_1568_p3;
right_border_buf_1_val_1_2_16_fu_366 <= right_border_buf_1_val_1_2_4_fu_1551_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5) & (ap_reg_ppstg_tmp_102_reg_3260_pp0_it5 == ap_const_lv2_0))) begin
right_border_buf_2_val_0_0_fu_202 <= k_buf_2_val_2_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5) & (ap_reg_ppstg_tmp_102_reg_3260_pp0_it5 == ap_const_lv2_1))) begin
right_border_buf_2_val_0_1_fu_206 <= k_buf_2_val_2_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5) & ~(ap_reg_ppstg_tmp_102_reg_3260_pp0_it5 == ap_const_lv2_1) & ~(ap_reg_ppstg_tmp_102_reg_3260_pp0_it5 == ap_const_lv2_0))) begin
right_border_buf_2_val_0_2_fu_210 <= k_buf_2_val_2_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5) & ~(ap_reg_ppstg_tmp_105_reg_3270_pp0_it5 == ap_const_lv2_1) & ~(ap_reg_ppstg_tmp_105_reg_3270_pp0_it5 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5) & (ap_reg_ppstg_tmp_105_reg_3270_pp0_it5 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5) & (ap_reg_ppstg_tmp_105_reg_3270_pp0_it5 == ap_const_lv2_0)))) begin
right_border_buf_2_val_1_2_12_fu_270 <= right_border_buf_2_val_1_2_27_fu_1763_p3;
right_border_buf_2_val_1_2_19_fu_286 <= right_border_buf_2_val_1_2_25_fu_1746_p3;
right_border_buf_2_val_1_2_20_fu_294 <= right_border_buf_2_val_1_2_23_fu_1724_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it7))) begin
src_kernel_win_0_val_0_1_lo_reg_3593 <= src_kernel_win_0_val_0_1_fu_226;
src_kernel_win_0_val_1_1_lo_reg_3599 <= src_kernel_win_0_val_1_1_fu_242;
src_kernel_win_0_val_1_2_lo_reg_3605 <= src_kernel_win_0_val_1_2_fu_246;
src_kernel_win_1_val_0_1_lo_reg_3620 <= src_kernel_win_1_val_0_1_fu_262;
src_kernel_win_1_val_1_1_lo_reg_3626 <= src_kernel_win_1_val_1_1_fu_278;
src_kernel_win_1_val_1_2_lo_reg_3632 <= src_kernel_win_1_val_1_2_fu_282;
src_kernel_win_2_val_0_1_lo_reg_3647 <= src_kernel_win_2_val_0_1_fu_298;
src_kernel_win_2_val_1_1_lo_reg_3653 <= src_kernel_win_2_val_1_1_fu_314;
src_kernel_win_2_val_1_2_lo_reg_3659 <= src_kernel_win_2_val_1_2_fu_318;
temp_0_i_i_i_057_i_i_1_0_0_2_reg_3610 <= temp_0_i_i_i_057_i_i_1_0_0_2_fu_2357_p3;
temp_0_i_i_i_057_i_i_1_1_0_2_reg_3637 <= temp_0_i_i_i_057_i_i_1_1_0_2_fu_2387_p3;
temp_0_i_i_i_057_i_i_1_2_0_2_reg_3664 <= temp_0_i_i_i_057_i_i_1_2_0_2_fu_2417_p3;
tmp_115_0_1_reg_3615 <= tmp_115_0_1_fu_2364_p2;
tmp_115_1_1_reg_3642 <= tmp_115_1_1_fu_2394_p2;
tmp_115_2_1_reg_3669 <= tmp_115_2_1_fu_2424_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it10) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it9))) begin
src_kernel_win_0_val_0_2_fu_230 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_12_reg_3533_pp0_it9;
src_kernel_win_1_val_0_2_fu_266 <= ap_reg_ppstg_src_kernel_win_1_val_0_1_12_reg_3547_pp0_it9;
src_kernel_win_2_val_0_2_fu_302 <= ap_reg_ppstg_src_kernel_win_2_val_0_1_12_reg_3561_pp0_it9;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it9))) begin
src_kernel_win_0_val_0_2_lo_reg_3692 <= src_kernel_win_0_val_0_2_fu_230;
src_kernel_win_1_val_0_2_lo_reg_3707 <= src_kernel_win_1_val_0_2_fu_266;
src_kernel_win_2_val_0_2_lo_reg_3722 <= src_kernel_win_2_val_0_2_fu_302;
temp_0_i_i_i_057_i_i_1_0_1_2_reg_3697 <= temp_0_i_i_i_057_i_i_1_0_1_2_fu_2500_p3;
temp_0_i_i_i_057_i_i_1_1_1_2_reg_3712 <= temp_0_i_i_i_057_i_i_1_1_1_2_fu_2519_p3;
temp_0_i_i_i_057_i_i_1_2_1_2_reg_3727 <= temp_0_i_i_i_057_i_i_1_2_1_2_fu_2538_p3;
tmp_115_0_2_reg_3702 <= tmp_115_0_2_fu_2506_p2;
tmp_115_1_2_reg_3717 <= tmp_115_1_2_fu_2525_p2;
tmp_115_2_2_reg_3732 <= tmp_115_2_2_fu_2544_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it8) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it7))) begin
src_kernel_win_0_val_1_2_fu_246 <= src_kernel_win_0_val_1_1_12_reg_3540;
src_kernel_win_1_val_1_2_fu_282 <= src_kernel_win_1_val_1_1_12_reg_3554;
src_kernel_win_2_val_1_2_fu_318 <= src_kernel_win_2_val_1_1_12_reg_3568;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6))) begin
src_kernel_win_0_val_2_2_fu_254 <= src_kernel_win_0_val_2_1_fu_238;
src_kernel_win_1_val_2_2_fu_290 <= src_kernel_win_1_val_2_1_fu_274;
src_kernel_win_2_val_2_2_fu_326 <= src_kernel_win_2_val_2_1_fu_310;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it6))) begin
temp_0_i_i_i_057_i_i_1_0_0_1_reg_3575 <= temp_0_i_i_i_057_i_i_1_0_0_1_fu_1985_p3;
temp_0_i_i_i_057_i_i_1_1_0_1_reg_3581 <= temp_0_i_i_i_057_i_i_1_1_0_1_fu_2151_p3;
temp_0_i_i_i_057_i_i_1_2_0_1_reg_3587 <= temp_0_i_i_i_057_i_i_1_2_0_1_fu_2317_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it8))) begin
temp_0_i_i_i_057_i_i_1_0_1_1_reg_3674 <= temp_0_i_i_i_057_i_i_1_0_1_1_fu_2452_p3;
temp_0_i_i_i_057_i_i_1_1_1_1_reg_3680 <= temp_0_i_i_i_057_i_i_1_1_1_1_fu_2469_p3;
temp_0_i_i_i_057_i_i_1_2_1_1_reg_3686 <= temp_0_i_i_i_057_i_i_1_2_1_1_fu_2486_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it10))) begin
temp_0_i_i_i_057_i_i_1_0_2_1_reg_3737 <= temp_0_i_i_i_057_i_i_1_0_2_1_fu_2572_p3;
temp_0_i_i_i_057_i_i_1_1_2_1_reg_3743 <= temp_0_i_i_i_057_i_i_1_1_2_1_fu_2589_p3;
temp_0_i_i_i_057_i_i_1_2_2_1_reg_3749 <= temp_0_i_i_i_057_i_i_1_2_2_1_fu_2606_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & (ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131))) begin
tmp_100_reg_3500 <= tmp_100_fu_1613_p1;
tmp_85_reg_3397 <= tmp_85_fu_1311_p1;
tmp_86_reg_3403 <= tmp_86_fu_1315_p1;
tmp_90_reg_3435 <= tmp_90_fu_1423_p1;
tmp_91_reg_3441 <= tmp_91_fu_1427_p1;
tmp_99_reg_3494 <= tmp_99_fu_1609_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_77_reg_3131))) begin
tmp_101_reg_3286 <= tmp_101_fu_1264_p1;
tmp_87_reg_3276 <= tmp_87_fu_1256_p1;
tmp_92_reg_3281 <= tmp_92_fu_1260_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2) & ~(ap_const_lv1_0 == or_cond2_2_fu_1212_p2) & (ap_const_lv1_0 == tmp_66_2_fu_1226_p2))) begin
tmp_102_reg_3260 <= tmp_102_fu_1236_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_reg_3180) & ~(ap_const_lv1_0 == or_cond2_2_reg_3248) & (ap_const_lv1_0 == tmp_66_2_reg_3256))) begin
tmp_105_reg_3270 <= tmp_105_fu_1252_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2) & ~(ap_const_lv1_0 == or_cond2_fu_1138_p2))) begin
tmp_38_reg_3214 <= tmp_38_fu_1152_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2) & ~(ap_const_lv1_0 == or_cond2_1_fu_1173_p2))) begin
tmp_66_1_reg_3236 <= tmp_66_1_fu_1187_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2) & ~(ap_const_lv1_0 == or_cond2_2_fu_1212_p2))) begin
tmp_66_2_reg_3256 <= tmp_66_2_fu_1226_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it3))) begin
tmp_83_reg_3296 <= tmp_83_fu_1268_p1;
x_1_reg_3305 <= grp_image_filter_borderInterpolate_fu_700_ap_return;
x_2_reg_3317 <= grp_image_filter_borderInterpolate_fu_708_ap_return;
x_reg_3291 <= grp_image_filter_borderInterpolate_fu_692_ap_return;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2) & (ap_const_lv1_0 == or_cond2_fu_1138_p2))) begin
tmp_84_reg_3210 <= ImagLoc_x_fu_1113_p2[ap_const_lv32_B];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2) & (ap_const_lv1_0 == or_cond2_1_fu_1173_p2))) begin
tmp_89_reg_3232 <= ImagLoc_x_fu_1113_p2[ap_const_lv32_B];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2) & ~(ap_const_lv1_0 == or_cond2_1_fu_1173_p2) & (ap_const_lv1_0 == tmp_66_1_fu_1187_p2))) begin
tmp_93_reg_3240 <= tmp_93_fu_1197_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_reg_3180) & ~(ap_const_lv1_0 == or_cond2_1_reg_3228) & (ap_const_lv1_0 == tmp_66_1_reg_3236))) begin
tmp_96_reg_3264 <= tmp_96_fu_1244_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2) & (ap_const_lv1_0 == or_cond2_2_fu_1212_p2))) begin
tmp_98_reg_3252 <= ImagLoc_x_fu_1113_p2[ap_const_lv32_B];
end
end
/// ap_done assign process. ///
always @ (ap_done_reg or ap_sig_cseq_ST_st5_fsm_4 or tmp_28_fu_977_p2)
begin
if (((ap_const_logic_1 == ap_done_reg) | ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) & (ap_const_lv1_0 == tmp_28_fu_977_p2)))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_sig_cseq_ST_st5_fsm_4 or tmp_28_fu_977_p2)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) & (ap_const_lv1_0 == tmp_28_fu_977_p2))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_pp0_stg0_fsm_6 assign process. ///
always @ (ap_sig_bdd_175)
begin
if (ap_sig_bdd_175) begin
ap_sig_cseq_ST_pp0_stg0_fsm_6 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_pp0_stg0_fsm_6 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_27)
begin
if (ap_sig_bdd_27) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st20_fsm_7 assign process. ///
always @ (ap_sig_bdd_951)
begin
if (ap_sig_bdd_951) begin
ap_sig_cseq_ST_st20_fsm_7 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st20_fsm_7 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st2_fsm_1 assign process. ///
always @ (ap_sig_bdd_85)
begin
if (ap_sig_bdd_85) begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st3_fsm_2 assign process. ///
always @ (ap_sig_bdd_94)
begin
if (ap_sig_bdd_94) begin
ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st4_fsm_3 assign process. ///
always @ (ap_sig_bdd_103)
begin
if (ap_sig_bdd_103) begin
ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st5_fsm_4 assign process. ///
always @ (ap_sig_bdd_133)
begin
if (ap_sig_bdd_133) begin
ap_sig_cseq_ST_st5_fsm_4 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st5_fsm_4 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st6_fsm_5 assign process. ///
always @ (ap_sig_bdd_162)
begin
if (ap_sig_bdd_162) begin
ap_sig_cseq_ST_st6_fsm_5 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st6_fsm_5 = ap_const_logic_0;
end
end
/// grp_image_filter_borderInterpolate_fu_668_ap_ce assign process. ///
always @ (tmp_77_reg_3131 or brmerge_reg_3176 or tmp_33_fu_1081_p2 or tmp_33_reg_3180 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it1 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it2)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == tmp_33_reg_3180) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it1))))) begin
grp_image_filter_borderInterpolate_fu_668_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_borderInterpolate_fu_668_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_borderInterpolate_fu_676_ap_ce assign process. ///
always @ (tmp_77_reg_3131 or brmerge_reg_3176 or tmp_33_fu_1081_p2 or tmp_33_reg_3180 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it1 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it2)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == tmp_33_reg_3180) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it1))))) begin
grp_image_filter_borderInterpolate_fu_676_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_borderInterpolate_fu_676_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_borderInterpolate_fu_684_ap_ce assign process. ///
always @ (tmp_77_reg_3131 or brmerge_reg_3176 or tmp_33_fu_1081_p2 or tmp_33_reg_3180 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it1 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it2)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == tmp_33_reg_3180) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it1))))) begin
grp_image_filter_borderInterpolate_fu_684_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_borderInterpolate_fu_684_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_borderInterpolate_fu_692_ap_ce assign process. ///
always @ (tmp_33_reg_3180 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it1 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it3)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (~(ap_const_lv1_0 == tmp_33_reg_3180) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it3) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it1)))) begin
grp_image_filter_borderInterpolate_fu_692_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_borderInterpolate_fu_692_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_borderInterpolate_fu_700_ap_ce assign process. ///
always @ (tmp_33_reg_3180 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it1 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it3)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (~(ap_const_lv1_0 == tmp_33_reg_3180) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it3) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it1)))) begin
grp_image_filter_borderInterpolate_fu_700_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_borderInterpolate_fu_700_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_borderInterpolate_fu_708_ap_ce assign process. ///
always @ (tmp_33_reg_3180 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it1 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it3)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (~(ap_const_lv1_0 == tmp_33_reg_3180) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it3) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it1)))) begin
grp_image_filter_borderInterpolate_fu_708_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_borderInterpolate_fu_708_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_borderInterpolate_fu_716_ap_ce assign process. ///
always @ (tmp_77_reg_3131 or brmerge_reg_3176 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it3 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it4)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it3)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & (ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it4))))) begin
grp_image_filter_borderInterpolate_fu_716_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_borderInterpolate_fu_716_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_borderInterpolate_fu_724_ap_ce assign process. ///
always @ (tmp_77_reg_3131 or brmerge_reg_3176 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it3 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it4)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it3)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & (ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it4))))) begin
grp_image_filter_borderInterpolate_fu_724_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_borderInterpolate_fu_724_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_borderInterpolate_fu_732_ap_ce assign process. ///
always @ (tmp_77_reg_3131 or brmerge_reg_3176 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it3 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it4)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it3)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & (ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it4))))) begin
grp_image_filter_borderInterpolate_fu_732_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_borderInterpolate_fu_732_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_borderInterpolate_fu_740_ap_ce assign process. ///
always @ (tmp_77_reg_3131 or brmerge_reg_3176 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it3 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it4)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it3)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & (ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it4))))) begin
grp_image_filter_borderInterpolate_fu_740_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_borderInterpolate_fu_740_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_borderInterpolate_fu_748_ap_ce assign process. ///
always @ (tmp_77_reg_3131 or brmerge_reg_3176 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it3 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it4)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it3)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & (ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it4))))) begin
grp_image_filter_borderInterpolate_fu_748_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_borderInterpolate_fu_748_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_borderInterpolate_fu_756_ap_ce assign process. ///
always @ (tmp_77_reg_3131 or brmerge_reg_3176 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it3 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it4)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it3)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & (ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it4))))) begin
grp_image_filter_borderInterpolate_fu_756_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_borderInterpolate_fu_756_ap_ce = ap_const_logic_0;
end
end
/// k_buf_0_val_0_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_0_val_0_ce0 = ap_const_logic_1;
end else begin
k_buf_0_val_0_ce0 = ap_const_logic_0;
end
end
/// k_buf_0_val_0_ce1 assign process. ///
always @ (ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_0_val_0_ce1 = ap_const_logic_1;
end else begin
k_buf_0_val_0_ce1 = ap_const_logic_0;
end
end
/// k_buf_0_val_0_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_reg_3206_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_0_val_0_we1 = ap_const_logic_1;
end else begin
k_buf_0_val_0_we1 = ap_const_logic_0;
end
end
/// k_buf_0_val_1_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_0_val_1_ce0 = ap_const_logic_1;
end else begin
k_buf_0_val_1_ce0 = ap_const_logic_0;
end
end
/// k_buf_0_val_1_ce1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_reg_3206_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_38_reg_3214_pp0_it5)
begin
if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5)))) begin
k_buf_0_val_1_ce1 = ap_const_logic_1;
end else begin
k_buf_0_val_1_ce1 = ap_const_logic_0;
end
end
/// k_buf_0_val_1_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_reg_3206_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_38_reg_3214_pp0_it5)
begin
if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5)))) begin
k_buf_0_val_1_we1 = ap_const_logic_1;
end else begin
k_buf_0_val_1_we1 = ap_const_logic_0;
end
end
/// k_buf_0_val_2_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_0_val_2_ce0 = ap_const_logic_1;
end else begin
k_buf_0_val_2_ce0 = ap_const_logic_0;
end
end
/// k_buf_0_val_2_ce1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_reg_3206_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_38_reg_3214_pp0_it5)
begin
if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5)))) begin
k_buf_0_val_2_ce1 = ap_const_logic_1;
end else begin
k_buf_0_val_2_ce1 = ap_const_logic_0;
end
end
/// k_buf_0_val_2_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_reg_3206_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_38_reg_3214_pp0_it5)
begin
if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5)))) begin
k_buf_0_val_2_we1 = ap_const_logic_1;
end else begin
k_buf_0_val_2_we1 = ap_const_logic_0;
end
end
/// k_buf_1_val_0_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_1_val_0_ce0 = ap_const_logic_1;
end else begin
k_buf_1_val_0_ce0 = ap_const_logic_0;
end
end
/// k_buf_1_val_0_ce1 assign process. ///
always @ (ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_1_val_0_ce1 = ap_const_logic_1;
end else begin
k_buf_1_val_0_ce1 = ap_const_logic_0;
end
end
/// k_buf_1_val_0_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_1_val_0_we1 = ap_const_logic_1;
end else begin
k_buf_1_val_0_we1 = ap_const_logic_0;
end
end
/// k_buf_1_val_1_address1 assign process. ///
always @ (ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5 or tmp_99_1_fu_1516_p1 or k_buf_1_val_1_addr_1_gep_fu_554_p3 or ap_sig_bdd_967)
begin
if (ap_sig_bdd_967) begin
if (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5)) begin
k_buf_1_val_1_address1 = k_buf_1_val_1_addr_1_gep_fu_554_p3;
end else if ((ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5)) begin
k_buf_1_val_1_address1 = tmp_99_1_fu_1516_p1;
end else begin
k_buf_1_val_1_address1 = 'bx;
end
end else begin
k_buf_1_val_1_address1 = 'bx;
end
end
/// k_buf_1_val_1_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_1_val_1_ce0 = ap_const_logic_1;
end else begin
k_buf_1_val_1_ce0 = ap_const_logic_0;
end
end
/// k_buf_1_val_1_ce1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5)
begin
if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5)))) begin
k_buf_1_val_1_ce1 = ap_const_logic_1;
end else begin
k_buf_1_val_1_ce1 = ap_const_logic_0;
end
end
/// k_buf_1_val_1_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5)
begin
if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5)))) begin
k_buf_1_val_1_we1 = ap_const_logic_1;
end else begin
k_buf_1_val_1_we1 = ap_const_logic_0;
end
end
/// k_buf_1_val_2_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_1_val_2_ce0 = ap_const_logic_1;
end else begin
k_buf_1_val_2_ce0 = ap_const_logic_0;
end
end
/// k_buf_1_val_2_ce1 assign process. ///
always @ (ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_1_val_2_ce1 = ap_const_logic_1;
end else begin
k_buf_1_val_2_ce1 = ap_const_logic_0;
end
end
/// k_buf_1_val_2_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_1_val_2_we1 = ap_const_logic_1;
end else begin
k_buf_1_val_2_we1 = ap_const_logic_0;
end
end
/// k_buf_2_val_0_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_2_val_0_ce0 = ap_const_logic_1;
end else begin
k_buf_2_val_0_ce0 = ap_const_logic_0;
end
end
/// k_buf_2_val_0_ce1 assign process. ///
always @ (ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_2_val_0_ce1 = ap_const_logic_1;
end else begin
k_buf_2_val_0_ce1 = ap_const_logic_0;
end
end
/// k_buf_2_val_0_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_2_val_0_we1 = ap_const_logic_1;
end else begin
k_buf_2_val_0_we1 = ap_const_logic_0;
end
end
/// k_buf_2_val_1_address1 assign process. ///
always @ (ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5 or tmp_99_2_fu_1702_p1 or k_buf_2_val_1_addr_1_gep_fu_594_p3 or ap_sig_bdd_979)
begin
if (ap_sig_bdd_979) begin
if (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5)) begin
k_buf_2_val_1_address1 = k_buf_2_val_1_addr_1_gep_fu_594_p3;
end else if ((ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5)) begin
k_buf_2_val_1_address1 = tmp_99_2_fu_1702_p1;
end else begin
k_buf_2_val_1_address1 = 'bx;
end
end else begin
k_buf_2_val_1_address1 = 'bx;
end
end
/// k_buf_2_val_1_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_2_val_1_ce0 = ap_const_logic_1;
end else begin
k_buf_2_val_1_ce0 = ap_const_logic_0;
end
end
/// k_buf_2_val_1_ce1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5)
begin
if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5)))) begin
k_buf_2_val_1_ce1 = ap_const_logic_1;
end else begin
k_buf_2_val_1_ce1 = ap_const_logic_0;
end
end
/// k_buf_2_val_1_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5)
begin
if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5)))) begin
k_buf_2_val_1_we1 = ap_const_logic_1;
end else begin
k_buf_2_val_1_we1 = ap_const_logic_0;
end
end
/// k_buf_2_val_2_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_2_val_2_ce0 = ap_const_logic_1;
end else begin
k_buf_2_val_2_ce0 = ap_const_logic_0;
end
end
/// k_buf_2_val_2_ce1 assign process. ///
always @ (ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_2_val_2_ce1 = ap_const_logic_1;
end else begin
k_buf_2_val_2_ce1 = ap_const_logic_0;
end
end
/// k_buf_2_val_2_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_2_val_2_we1 = ap_const_logic_1;
end else begin
k_buf_2_val_2_we1 = ap_const_logic_0;
end
end
/// p_dst_data_stream_0_V_write assign process. ///
always @ (ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
p_dst_data_stream_0_V_write = ap_const_logic_1;
end else begin
p_dst_data_stream_0_V_write = ap_const_logic_0;
end
end
/// p_dst_data_stream_1_V_write assign process. ///
always @ (ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
p_dst_data_stream_1_V_write = ap_const_logic_1;
end else begin
p_dst_data_stream_1_V_write = ap_const_logic_0;
end
end
/// p_dst_data_stream_2_V_write assign process. ///
always @ (ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
p_dst_data_stream_2_V_write = ap_const_logic_1;
end else begin
p_dst_data_stream_2_V_write = ap_const_logic_0;
end
end
/// p_src_data_stream_0_V_read assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_reg_3206_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
p_src_data_stream_0_V_read = ap_const_logic_1;
end else begin
p_src_data_stream_0_V_read = ap_const_logic_0;
end
end
/// p_src_data_stream_1_V_read assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
p_src_data_stream_1_V_read = ap_const_logic_1;
end else begin
p_src_data_stream_1_V_read = ap_const_logic_0;
end
end
/// p_src_data_stream_2_V_read assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
p_src_data_stream_2_V_read = ap_const_logic_1;
end else begin
p_src_data_stream_2_V_read = ap_const_logic_0;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_CS_fsm or ap_sig_bdd_67 or tmp_23_fu_926_p2 or tmp_28_fu_977_p2 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_reg_ppiten_pp0_it7 or ap_reg_ppiten_pp0_it8 or ap_reg_ppiten_pp0_it11 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or tmp_s_fu_902_p2 or tmp_20_fu_914_p2)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
if (~ap_sig_bdd_67) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
end
ap_ST_st2_fsm_1 :
begin
if (~(ap_const_lv1_0 == tmp_s_fu_902_p2)) begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end else begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end
end
ap_ST_st3_fsm_2 :
begin
if (~(ap_const_lv1_0 == tmp_20_fu_914_p2)) begin
ap_NS_fsm = ap_ST_st4_fsm_3;
end else begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end
end
ap_ST_st4_fsm_3 :
begin
if (~(tmp_23_fu_926_p2 == ap_const_lv1_0)) begin
ap_NS_fsm = ap_ST_st5_fsm_4;
end else begin
ap_NS_fsm = ap_ST_st4_fsm_3;
end
end
ap_ST_st5_fsm_4 :
begin
if ((ap_const_lv1_0 == tmp_28_fu_977_p2)) begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end else begin
ap_NS_fsm = ap_ST_st6_fsm_5;
end
end
ap_ST_st6_fsm_5 :
begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_6;
end
ap_ST_pp0_stg0_fsm_6 :
begin
if ((~((ap_const_logic_1 == ap_reg_ppiten_pp0_it12) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it11)) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it8)))) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_6;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it12) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it11)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it8)))) begin
ap_NS_fsm = ap_ST_st20_fsm_7;
end else begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_6;
end
end
ap_ST_st20_fsm_7 :
begin
ap_NS_fsm = ap_ST_st5_fsm_4;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ImagLoc_x_cast2_fu_1123_p1 = $signed(ImagLoc_x_fu_1113_p2);
assign ImagLoc_x_fu_1113_p2 = ($signed(tmp_33_cast_fu_1077_p1) + $signed(ap_const_lv12_FFF));
assign ImagLoc_y_fu_994_p2 = ($signed(tmp_29_cast_cast3_fu_973_p1) + $signed(ap_const_lv12_FFC));
/// ap_sig_bdd_103 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_103 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3]);
end
/// ap_sig_bdd_133 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_133 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4]);
end
/// ap_sig_bdd_162 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_162 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5]);
end
/// ap_sig_bdd_175 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_175 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_6]);
end
/// ap_sig_bdd_218 assign process. ///
always @ (p_src_data_stream_0_V_empty_n or p_src_data_stream_1_V_empty_n or p_src_data_stream_2_V_empty_n or brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_reg_3206_pp0_it5 or ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5 or ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5)
begin
ap_sig_bdd_218 = (((p_src_data_stream_0_V_empty_n == ap_const_logic_0) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & (p_src_data_stream_1_V_empty_n == ap_const_logic_0) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & (p_src_data_stream_2_V_empty_n == ap_const_logic_0) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5)));
end
/// ap_sig_bdd_244 assign process. ///
always @ (p_dst_data_stream_0_V_full_n or p_dst_data_stream_1_V_full_n or p_dst_data_stream_2_V_full_n or ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11)
begin
ap_sig_bdd_244 = (((p_dst_data_stream_0_V_full_n == ap_const_logic_0) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11)) | (~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11) & (p_dst_data_stream_1_V_full_n == ap_const_logic_0)) | (~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11) & (p_dst_data_stream_2_V_full_n == ap_const_logic_0)));
end
/// ap_sig_bdd_27 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_27 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
/// ap_sig_bdd_67 assign process. ///
always @ (ap_start or ap_done_reg)
begin
ap_sig_bdd_67 = ((ap_start == ap_const_logic_0) | (ap_done_reg == ap_const_logic_1));
end
/// ap_sig_bdd_85 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_85 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end
/// ap_sig_bdd_94 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_94 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end
/// ap_sig_bdd_951 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_951 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_7]);
end
/// ap_sig_bdd_967 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5 or ap_reg_ppiten_pp0_it6)
begin
ap_sig_bdd_967 = (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6));
end
/// ap_sig_bdd_979 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5 or ap_reg_ppiten_pp0_it6)
begin
ap_sig_bdd_979 = (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6));
end
assign brmerge_fu_1072_p2 = (tmp_31_fu_1057_p2 | or_cond_2_reg_3126);
assign col_assign_1_fu_1192_p2 = (ImagLoc_x_fu_1113_p2 + p_neg226_i_i_reg_3068);
assign col_assign_3_1_t1_fu_1450_p2 = (tmp_95_fu_1447_p1 + tmp_73_reg_3076);
assign col_assign_3_2_t1_fu_1636_p2 = (tmp_104_fu_1633_p1 + tmp_73_reg_3076);
assign col_assign_3_fu_1319_p2 = (ap_reg_ppstg_tmp_83_reg_3296_pp0_it5 + tmp_73_reg_3076);
assign col_assign_4_1_fu_1240_p2 = (ImagLoc_x_reg_3193 + p_neg226_i_i_reg_3068);
assign col_assign_4_2_fu_1248_p2 = (ImagLoc_x_reg_3193 + p_neg226_i_i_reg_3068);
assign col_assign_fu_1157_p2 = (tmp_82_fu_1119_p1 + tmp_73_reg_3076);
assign col_assign_s_fu_1231_p2 = (ImagLoc_x_fu_1113_p2 + p_neg226_i_i_reg_3068);
assign col_buf_0_val_0_0_16_fu_1926_p3 = ((sel_tmp2_fu_1921_p2)? col_buf_0_val_0_0_11_fu_346: col_buf_0_val_0_0_6_fu_1913_p3);
assign col_buf_0_val_0_0_6_fu_1913_p3 = ((sel_tmp_fu_1908_p2)? col_buf_0_val_0_0_12_fu_350: col_buf_0_val_0_0_13_fu_354);
assign col_buf_1_val_0_0_16_fu_1475_p3 = ((sel_tmp40_fu_1469_p2)? col_buf_1_val_0_0_13_fu_330: col_buf_1_val_0_0_6_fu_1461_p3);
assign col_buf_1_val_0_0_6_fu_1461_p3 = ((sel_tmp39_fu_1455_p2)? col_buf_1_val_0_0_12_fu_322: col_buf_1_val_0_0_11_fu_306);
assign col_buf_2_val_0_0_16_fu_1661_p3 = ((sel_tmp52_fu_1655_p2)? col_buf_2_val_0_0_13_fu_258: col_buf_2_val_0_0_6_fu_1647_p3);
assign col_buf_2_val_0_0_6_fu_1647_p3 = ((sel_tmp51_fu_1641_p2)? col_buf_2_val_0_0_12_fu_250: col_buf_2_val_0_0_11_fu_234);
assign cols_assign_cast1_fu_892_p1 = p_src_cols_V_read;
assign grp_image_filter_borderInterpolate_fu_668_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_668_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_668_p = y_1_2_1_reg_3169;
assign grp_image_filter_borderInterpolate_fu_676_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_676_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_676_p = y_1_2_1_reg_3169;
assign grp_image_filter_borderInterpolate_fu_684_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_684_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_684_p = y_1_2_1_reg_3169;
assign grp_image_filter_borderInterpolate_fu_692_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_692_len = p_src_cols_V_read;
assign grp_image_filter_borderInterpolate_fu_692_p = ImagLoc_x_reg_3193;
assign grp_image_filter_borderInterpolate_fu_700_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_700_len = p_src_cols_V_read;
assign grp_image_filter_borderInterpolate_fu_700_p = ImagLoc_x_reg_3193;
assign grp_image_filter_borderInterpolate_fu_708_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_708_len = p_src_cols_V_read;
assign grp_image_filter_borderInterpolate_fu_708_p = ImagLoc_x_reg_3193;
assign grp_image_filter_borderInterpolate_fu_716_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_716_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_716_p = ImagLoc_y_reg_3118;
assign grp_image_filter_borderInterpolate_fu_724_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_724_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_724_p = y_1_2_reg_3162;
assign grp_image_filter_borderInterpolate_fu_732_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_732_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_732_p = ImagLoc_y_reg_3118;
assign grp_image_filter_borderInterpolate_fu_740_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_740_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_740_p = y_1_2_reg_3162;
assign grp_image_filter_borderInterpolate_fu_748_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_748_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_748_p = ImagLoc_y_reg_3118;
assign grp_image_filter_borderInterpolate_fu_756_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_756_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_756_p = y_1_2_reg_3162;
assign heightloop_fu_932_p2 = (tmp_reg_2745 + ap_const_lv11_5);
assign i_V_fu_982_p2 = (p_012_0_i_i_reg_645 + ap_const_lv11_1);
assign icmp2_fu_1102_p2 = (tmp_80_fu_1092_p4 != ap_const_lv10_0? 1'b1: 1'b0);
assign icmp_fu_1010_p2 = ($signed(tmp_75_fu_1000_p4) > $signed(11'b00000000000)? 1'b1: 1'b0);
assign j_V_fu_1086_p2 = (p_025_0_i_i_reg_656 + ap_const_lv11_1);
assign k_buf_0_val_0_address0 = tmp_35_fu_1287_p1;
assign k_buf_0_val_0_address1 = k_buf_0_val_0_addr_reg_3329;
assign k_buf_0_val_0_d1 = p_src_data_stream_0_V_dout;
assign k_buf_0_val_1_address0 = tmp_35_fu_1287_p1;
assign k_buf_0_val_1_address1 = k_buf_0_val_1_addr_reg_3335;
assign k_buf_0_val_1_d1 = k_buf_0_val_0_q0;
assign k_buf_0_val_2_address0 = tmp_35_fu_1287_p1;
assign k_buf_0_val_2_address1 = k_buf_0_val_2_addr_reg_3341;
assign k_buf_0_val_2_d1 = k_buf_0_val_1_q0;
assign k_buf_1_val_0_address0 = tmp_56_1_fu_1294_p1;
assign k_buf_1_val_0_address1 = tmp_99_1_fu_1516_p1;
assign k_buf_1_val_0_d1 = p_src_data_stream_1_V_dout;
assign k_buf_1_val_1_addr_1_gep_fu_554_p3 = tmp_99_1_fu_1516_p1;
assign k_buf_1_val_1_address0 = tmp_56_1_fu_1294_p1;
assign k_buf_1_val_1_d1 = k_buf_1_val_0_q0;
assign k_buf_1_val_2_address0 = tmp_56_1_fu_1294_p1;
assign k_buf_1_val_2_address1 = tmp_99_1_fu_1516_p1;
assign k_buf_1_val_2_d1 = k_buf_1_val_1_q0;
assign k_buf_2_val_0_address0 = tmp_56_2_fu_1300_p1;
assign k_buf_2_val_0_address1 = tmp_99_2_fu_1702_p1;
assign k_buf_2_val_0_d1 = p_src_data_stream_2_V_dout;
assign k_buf_2_val_1_addr_1_gep_fu_594_p3 = tmp_99_2_fu_1702_p1;
assign k_buf_2_val_1_address0 = tmp_56_2_fu_1300_p1;
assign k_buf_2_val_1_d1 = k_buf_2_val_0_q0;
assign k_buf_2_val_2_address0 = tmp_56_2_fu_1300_p1;
assign k_buf_2_val_2_address1 = tmp_99_2_fu_1702_p1;
assign k_buf_2_val_2_d1 = k_buf_2_val_1_q0;
assign locy_0_1_t_fu_1846_p2 = (tmp_79_reg_3155 - tmp_86_reg_3403);
assign locy_0_2_t_fu_1272_p2 = (tmp_79_reg_3155 - tmp_87_reg_3276);
assign locy_1_0_t_fu_1993_p2 = (tmp_32_reg_3135 - tmp_90_reg_3435);
assign locy_1_1_t_fu_2025_p2 = (tmp_32_reg_3135 - tmp_91_reg_3441);
assign locy_1_2_t_fu_1276_p2 = (tmp_32_reg_3135 - tmp_92_reg_3281);
assign locy_2_0_t_fu_2159_p2 = (tmp_32_reg_3135 - tmp_99_reg_3494);
assign locy_2_1_t_fu_2191_p2 = (tmp_32_reg_3135 - tmp_100_reg_3500);
assign locy_2_2_t_fu_1280_p2 = (tmp_32_reg_3135 - tmp_101_reg_3286);
assign locy_fu_1814_p2 = (tmp_78_reg_3149 - tmp_85_reg_3397);
assign or_cond219_i_i_fu_1108_p2 = (tmp_30_reg_3113 & icmp2_fu_1102_p2);
assign or_cond2_1_fu_1173_p2 = (tmp_61_1_fu_1162_p2 & tmp_63_1_fu_1168_p2);
assign or_cond2_2_fu_1212_p2 = (tmp_61_2_fu_1201_p2 & tmp_63_2_fu_1207_p2);
assign or_cond2_fu_1138_p2 = (tmp_36_fu_1127_p2 & tmp_37_fu_1133_p2);
assign or_cond_2_fu_1021_p2 = (icmp_fu_1010_p2 & tmp_58_2_fu_1016_p2);
assign p_dst_data_stream_0_V_din = ((tmp_115_0_2_2_fu_2613_p2)? ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it11: temp_0_i_i_i_057_i_i_1_0_2_1_reg_3737);
assign p_dst_data_stream_1_V_din = ((tmp_115_1_2_2_fu_2624_p2)? ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it11: temp_0_i_i_i_057_i_i_1_1_2_1_reg_3743);
assign p_dst_data_stream_2_V_din = ((tmp_115_2_2_2_fu_2635_p2)? ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it11: temp_0_i_i_i_057_i_i_1_2_2_1_reg_3749);
assign p_i_i_fu_1042_p3 = ((tmp_58_2_fu_1016_p2)? ap_const_lv11_2: ref_reg_3084);
assign p_neg226_i_i_fu_951_p2 = (ap_const_lv12_3 - p_src_cols_V_read);
assign ref_cast_fu_965_p1 = ref_fu_960_p2;
assign ref_fu_960_p2 = ($signed(tmp_reg_2745) + $signed(ap_const_lv11_7FF));
assign right_border_buf_0_val_1_2_19_fu_1391_p3 = ((sel_tmp26_fu_1360_p2)? k_buf_0_val_1_q0: right_border_buf_0_val_1_2_14_fu_334);
assign right_border_buf_0_val_1_2_20_fu_1943_p3 = ((sel_tmp2_fu_1921_p2)? right_border_buf_0_val_1_2_14_fu_334: right_border_buf_0_val_1_2_fu_1935_p3);
assign right_border_buf_0_val_1_2_2_fu_1352_p3 = ((sel_tmp24_fu_1347_p2)? right_border_buf_0_val_1_2_16_fu_342: k_buf_0_val_1_q0);
assign right_border_buf_0_val_1_2_3_fu_1365_p3 = ((sel_tmp26_fu_1360_p2)? right_border_buf_0_val_1_2_16_fu_342: right_border_buf_0_val_1_2_2_fu_1352_p3);
assign right_border_buf_0_val_1_2_4_fu_1374_p3 = ((sel_tmp24_fu_1347_p2)? k_buf_0_val_1_q0: right_border_buf_0_val_1_2_15_fu_338);
assign right_border_buf_0_val_1_2_5_fu_1382_p3 = ((sel_tmp26_fu_1360_p2)? right_border_buf_0_val_1_2_15_fu_338: right_border_buf_0_val_1_2_4_fu_1374_p3);
assign right_border_buf_0_val_1_2_fu_1935_p3 = ((sel_tmp_fu_1908_p2)? right_border_buf_0_val_1_2_15_fu_338: right_border_buf_0_val_1_2_16_fu_342);
assign right_border_buf_1_val_1_2_19_fu_1577_p3 = ((sel_tmp38_fu_1546_p2)? k_buf_1_val_1_q0: right_border_buf_1_val_1_2_12_fu_358);
assign right_border_buf_1_val_1_2_1_fu_2098_p3 = ((tmp_94_reg_3447)? ap_const_lv8_0: right_border_buf_1_val_1_2_fu_2091_p3);
assign right_border_buf_1_val_1_2_3_fu_1538_p3 = ((sel_tmp36_fu_1533_p2)? right_border_buf_1_val_1_2_16_fu_366: k_buf_1_val_1_q0);
assign right_border_buf_1_val_1_2_4_fu_1551_p3 = ((sel_tmp38_fu_1546_p2)? right_border_buf_1_val_1_2_16_fu_366: right_border_buf_1_val_1_2_3_fu_1538_p3);
assign right_border_buf_1_val_1_2_5_fu_1560_p3 = ((sel_tmp36_fu_1533_p2)? k_buf_1_val_1_q0: right_border_buf_1_val_1_2_15_fu_362);
assign right_border_buf_1_val_1_2_6_74_fu_1568_p3 = ((sel_tmp38_fu_1546_p2)? right_border_buf_1_val_1_2_15_fu_362: right_border_buf_1_val_1_2_5_fu_1560_p3);
assign right_border_buf_1_val_1_2_fu_2091_p3 = ((sel_tmp44_reg_3469)? right_border_buf_1_val_1_2_15_fu_362: right_border_buf_1_val_1_2_16_fu_366);
assign right_border_buf_2_val_1_2_1_fu_2264_p3 = ((tmp_103_reg_3506)? ap_const_lv8_0: right_border_buf_2_val_1_2_fu_2257_p3);
assign right_border_buf_2_val_1_2_23_fu_1724_p3 = ((sel_tmp57_fu_1719_p2)? k_buf_2_val_1_q0: right_border_buf_2_val_1_2_20_fu_294);
assign right_border_buf_2_val_1_2_24_fu_1738_p3 = ((sel_tmp58_fu_1733_p2)? k_buf_2_val_1_q0: right_border_buf_2_val_1_2_19_fu_286);
assign right_border_buf_2_val_1_2_25_fu_1746_p3 = ((sel_tmp57_fu_1719_p2)? right_border_buf_2_val_1_2_19_fu_286: right_border_buf_2_val_1_2_24_fu_1738_p3);
assign right_border_buf_2_val_1_2_26_fu_1755_p3 = ((sel_tmp58_fu_1733_p2)? right_border_buf_2_val_1_2_12_fu_270: k_buf_2_val_1_q0);
assign right_border_buf_2_val_1_2_27_fu_1763_p3 = ((sel_tmp57_fu_1719_p2)? right_border_buf_2_val_1_2_12_fu_270: right_border_buf_2_val_1_2_26_fu_1755_p3);
assign right_border_buf_2_val_1_2_fu_2257_p3 = ((sel_tmp56_reg_3528)? right_border_buf_2_val_1_2_19_fu_286: right_border_buf_2_val_1_2_12_fu_270);
assign sel_tmp10_fu_1832_p2 = (locy_fu_1814_p2 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp12_fu_1853_p2 = (tmp_79_reg_3155 == tmp_86_reg_3403? 1'b1: 1'b0);
assign sel_tmp13_fu_1857_p3 = ((sel_tmp12_fu_1853_p2)? col_buf_0_val_0_0_fu_214: src_kernel_win_0_val_2_0_reg_3390);
assign sel_tmp14_fu_1864_p2 = (locy_0_1_t_fu_1846_p2 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp16_fu_2000_p2 = (tmp_32_reg_3135 == tmp_90_reg_3435? 1'b1: 1'b0);
assign sel_tmp17_fu_2004_p3 = ((sel_tmp16_fu_2000_p2)? col_buf_1_val_0_0_fu_218: src_kernel_win_1_val_2_0_reg_3428);
assign sel_tmp18_fu_2011_p2 = (locy_1_0_t_fu_1993_p2 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp20_fu_2032_p2 = (tmp_32_reg_3135 == tmp_91_reg_3441? 1'b1: 1'b0);
assign sel_tmp21_fu_2036_p3 = ((sel_tmp20_fu_2032_p2)? col_buf_1_val_0_0_fu_218: src_kernel_win_1_val_2_0_reg_3428);
assign sel_tmp22_fu_2043_p2 = (locy_1_1_t_fu_2025_p2 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp24_fu_1347_p2 = (ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp26_fu_1360_p2 = (ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_0? 1'b1: 1'b0);
assign sel_tmp2_fu_1921_p2 = (col_assign_3_reg_3409 == ap_const_lv2_0? 1'b1: 1'b0);
assign sel_tmp36_fu_1533_p2 = (ap_reg_ppstg_tmp_96_reg_3264_pp0_it5 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp38_fu_1546_p2 = (ap_reg_ppstg_tmp_96_reg_3264_pp0_it5 == ap_const_lv2_0? 1'b1: 1'b0);
assign sel_tmp39_fu_1455_p2 = (col_assign_3_1_t1_fu_1450_p2 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp40_fu_1469_p2 = (col_assign_3_1_t1_fu_1450_p2 == ap_const_lv2_0? 1'b1: 1'b0);
assign sel_tmp41_fu_2078_p3 = ((tmp_94_reg_3447)? ap_const_lv8_0: col_buf_1_val_0_0_16_reg_3457);
assign sel_tmp42_fu_1483_p2 = (tmp_94_fu_1440_p3 ^ ap_const_lv1_1);
assign sel_tmp43_fu_1489_p2 = (sel_tmp40_fu_1469_p2 & sel_tmp42_fu_1483_p2);
assign sel_tmp44_fu_1495_p2 = (sel_tmp39_fu_1455_p2 & sel_tmp42_fu_1483_p2);
assign sel_tmp45_fu_2166_p2 = (tmp_32_reg_3135 == tmp_99_reg_3494? 1'b1: 1'b0);
assign sel_tmp46_fu_2170_p3 = ((sel_tmp45_fu_2166_p2)? col_buf_2_val_0_0_fu_222: src_kernel_win_2_val_2_0_reg_3487);
assign sel_tmp47_fu_2177_p2 = (locy_2_0_t_fu_2159_p2 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp48_fu_2198_p2 = (tmp_32_reg_3135 == tmp_100_reg_3500? 1'b1: 1'b0);
assign sel_tmp49_fu_2202_p3 = ((sel_tmp48_fu_2198_p2)? col_buf_2_val_0_0_fu_222: src_kernel_win_2_val_2_0_reg_3487);
assign sel_tmp50_fu_2209_p2 = (locy_2_1_t_fu_2191_p2 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp51_fu_1641_p2 = (col_assign_3_2_t1_fu_1636_p2 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp52_fu_1655_p2 = (col_assign_3_2_t1_fu_1636_p2 == ap_const_lv2_0? 1'b1: 1'b0);
assign sel_tmp53_fu_2244_p3 = ((tmp_103_reg_3506)? ap_const_lv8_0: col_buf_2_val_0_0_16_reg_3516);
assign sel_tmp54_fu_1669_p2 = (tmp_103_fu_1626_p3 ^ ap_const_lv1_1);
assign sel_tmp55_fu_1675_p2 = (sel_tmp52_fu_1655_p2 & sel_tmp54_fu_1669_p2);
assign sel_tmp56_fu_1681_p2 = (sel_tmp51_fu_1641_p2 & sel_tmp54_fu_1669_p2);
assign sel_tmp57_fu_1719_p2 = (ap_reg_ppstg_tmp_105_reg_3270_pp0_it5 == ap_const_lv2_0? 1'b1: 1'b0);
assign sel_tmp58_fu_1733_p2 = (ap_reg_ppstg_tmp_105_reg_3270_pp0_it5 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp8_fu_1821_p2 = (tmp_78_reg_3149 == tmp_85_reg_3397? 1'b1: 1'b0);
assign sel_tmp9_fu_1825_p3 = ((sel_tmp8_fu_1821_p2)? col_buf_0_val_0_0_fu_214: src_kernel_win_0_val_2_0_reg_3390);
assign sel_tmp_fu_1908_p2 = (col_assign_3_reg_3409 == ap_const_lv2_1? 1'b1: 1'b0);
assign src_kernel_win_0_val_0_1_9_fu_1838_p3 = ((sel_tmp10_fu_1832_p2)? right_border_buf_0_val_1_0_reg_3382: sel_tmp9_fu_1825_p3);
assign src_kernel_win_0_val_1_1_9_fu_1870_p3 = ((sel_tmp14_fu_1864_p2)? right_border_buf_0_val_1_0_reg_3382: sel_tmp13_fu_1857_p3);
assign src_kernel_win_1_val_0_1_10_fu_2084_p3 = ((sel_tmp43_reg_3463)? col_buf_1_val_0_0_16_reg_3457: sel_tmp41_fu_2078_p3);
assign src_kernel_win_1_val_0_1_9_fu_2017_p3 = ((sel_tmp18_fu_2011_p2)? right_border_buf_1_val_1_0_reg_3420: sel_tmp17_fu_2004_p3);
assign src_kernel_win_1_val_1_1_10_fu_2105_p3 = ((sel_tmp43_reg_3463)? right_border_buf_1_val_1_2_12_fu_358: right_border_buf_1_val_1_2_1_fu_2098_p3);
assign src_kernel_win_1_val_1_1_9_fu_2049_p3 = ((sel_tmp22_fu_2043_p2)? right_border_buf_1_val_1_0_reg_3420: sel_tmp21_fu_2036_p3);
assign src_kernel_win_2_val_0_1_10_fu_2250_p3 = ((sel_tmp55_reg_3522)? col_buf_2_val_0_0_16_reg_3516: sel_tmp53_fu_2244_p3);
assign src_kernel_win_2_val_0_1_9_fu_2183_p3 = ((sel_tmp47_fu_2177_p2)? right_border_buf_2_val_1_0_reg_3479: sel_tmp46_fu_2170_p3);
assign src_kernel_win_2_val_1_1_10_fu_2271_p3 = ((sel_tmp55_reg_3522)? right_border_buf_2_val_1_2_20_fu_294: right_border_buf_2_val_1_2_1_fu_2264_p3);
assign src_kernel_win_2_val_1_1_9_fu_2215_p3 = ((sel_tmp50_fu_2209_p2)? right_border_buf_2_val_1_0_reg_3479: sel_tmp49_fu_2202_p3);
assign temp_0_i_i_i_057_i_i_1_0_0_1_fu_1985_p3 = ((tmp_115_0_0_1_fu_1979_p2)? src_kernel_win_0_val_2_1_fu_238: src_kernel_win_0_val_2_2_fu_254);
assign temp_0_i_i_i_057_i_i_1_0_0_2_fu_2357_p3 = ((tmp_115_0_0_2_fu_2352_p2)? src_kernel_win_0_val_2_1_fu_238: temp_0_i_i_i_057_i_i_1_0_0_1_reg_3575);
assign temp_0_i_i_i_057_i_i_1_0_1_1_fu_2452_p3 = ((tmp_115_0_1_1_fu_2447_p2)? ap_reg_ppstg_src_kernel_win_0_val_1_1_12_reg_3540_pp0_it8: temp_0_i_i_i_057_i_i_1_0_1_fu_2442_p3);
assign temp_0_i_i_i_057_i_i_1_0_1_2_fu_2500_p3 = ((tmp_115_0_1_2_fu_2496_p2)? ap_reg_ppstg_src_kernel_win_0_val_1_1_lo_reg_3599_pp0_it9: temp_0_i_i_i_057_i_i_1_0_1_1_reg_3674);
assign temp_0_i_i_i_057_i_i_1_0_1_fu_2442_p3 = ((tmp_115_0_1_reg_3615)? src_kernel_win_0_val_1_2_lo_reg_3605: temp_0_i_i_i_057_i_i_1_0_0_2_reg_3610);
assign temp_0_i_i_i_057_i_i_1_0_2_1_fu_2572_p3 = ((tmp_115_0_2_1_fu_2567_p2)? ap_reg_ppstg_src_kernel_win_0_val_0_1_12_reg_3533_pp0_it10: temp_0_i_i_i_057_i_i_1_0_2_fu_2562_p3);
assign temp_0_i_i_i_057_i_i_1_0_2_fu_2562_p3 = ((tmp_115_0_2_reg_3702)? src_kernel_win_0_val_0_2_lo_reg_3692: temp_0_i_i_i_057_i_i_1_0_1_2_reg_3697);
assign temp_0_i_i_i_057_i_i_1_1_0_1_fu_2151_p3 = ((tmp_115_1_0_1_fu_2145_p2)? src_kernel_win_1_val_2_1_fu_274: src_kernel_win_1_val_2_2_fu_290);
assign temp_0_i_i_i_057_i_i_1_1_0_2_fu_2387_p3 = ((tmp_115_1_0_2_fu_2382_p2)? src_kernel_win_1_val_2_1_fu_274: temp_0_i_i_i_057_i_i_1_1_0_1_reg_3581);
assign temp_0_i_i_i_057_i_i_1_1_1_1_fu_2469_p3 = ((tmp_115_1_1_1_fu_2464_p2)? ap_reg_ppstg_src_kernel_win_1_val_1_1_12_reg_3554_pp0_it8: temp_0_i_i_i_057_i_i_1_1_1_fu_2459_p3);
assign temp_0_i_i_i_057_i_i_1_1_1_2_fu_2519_p3 = ((tmp_115_1_1_2_fu_2515_p2)? ap_reg_ppstg_src_kernel_win_1_val_1_1_lo_reg_3626_pp0_it9: temp_0_i_i_i_057_i_i_1_1_1_1_reg_3680);
assign temp_0_i_i_i_057_i_i_1_1_1_fu_2459_p3 = ((tmp_115_1_1_reg_3642)? src_kernel_win_1_val_1_2_lo_reg_3632: temp_0_i_i_i_057_i_i_1_1_0_2_reg_3637);
assign temp_0_i_i_i_057_i_i_1_1_2_1_fu_2589_p3 = ((tmp_115_1_2_1_fu_2584_p2)? ap_reg_ppstg_src_kernel_win_1_val_0_1_12_reg_3547_pp0_it10: temp_0_i_i_i_057_i_i_1_1_2_fu_2579_p3);
assign temp_0_i_i_i_057_i_i_1_1_2_fu_2579_p3 = ((tmp_115_1_2_reg_3717)? src_kernel_win_1_val_0_2_lo_reg_3707: temp_0_i_i_i_057_i_i_1_1_1_2_reg_3712);
assign temp_0_i_i_i_057_i_i_1_2_0_1_fu_2317_p3 = ((tmp_115_2_0_1_fu_2311_p2)? src_kernel_win_2_val_2_1_fu_310: src_kernel_win_2_val_2_2_fu_326);
assign temp_0_i_i_i_057_i_i_1_2_0_2_fu_2417_p3 = ((tmp_115_2_0_2_fu_2412_p2)? src_kernel_win_2_val_2_1_fu_310: temp_0_i_i_i_057_i_i_1_2_0_1_reg_3587);
assign temp_0_i_i_i_057_i_i_1_2_1_1_fu_2486_p3 = ((tmp_115_2_1_1_fu_2481_p2)? ap_reg_ppstg_src_kernel_win_2_val_1_1_12_reg_3568_pp0_it8: temp_0_i_i_i_057_i_i_1_2_1_fu_2476_p3);
assign temp_0_i_i_i_057_i_i_1_2_1_2_fu_2538_p3 = ((tmp_115_2_1_2_fu_2534_p2)? ap_reg_ppstg_src_kernel_win_2_val_1_1_lo_reg_3653_pp0_it9: temp_0_i_i_i_057_i_i_1_2_1_1_reg_3686);
assign temp_0_i_i_i_057_i_i_1_2_1_fu_2476_p3 = ((tmp_115_2_1_reg_3669)? src_kernel_win_2_val_1_2_lo_reg_3659: temp_0_i_i_i_057_i_i_1_2_0_2_reg_3664);
assign temp_0_i_i_i_057_i_i_1_2_2_1_fu_2606_p3 = ((tmp_115_2_2_1_fu_2601_p2)? ap_reg_ppstg_src_kernel_win_2_val_0_1_12_reg_3561_pp0_it10: temp_0_i_i_i_057_i_i_1_2_2_fu_2596_p3);
assign temp_0_i_i_i_057_i_i_1_2_2_fu_2596_p3 = ((tmp_115_2_2_reg_3732)? src_kernel_win_2_val_0_2_lo_reg_3722: temp_0_i_i_i_057_i_i_1_2_1_2_reg_3727);
assign tmp_100_fu_1613_p1 = grp_image_filter_borderInterpolate_fu_756_ap_return[1:0];
assign tmp_101_fu_1264_p1 = grp_image_filter_borderInterpolate_fu_684_ap_return[1:0];
assign tmp_102_fu_1236_p1 = col_assign_s_fu_1231_p2[1:0];
assign tmp_103_fu_1626_p3 = ap_reg_ppstg_x_2_reg_3317_pp0_it5[ap_const_lv32_E];
assign tmp_104_fu_1633_p1 = ap_reg_ppstg_x_2_reg_3317_pp0_it5[1:0];
assign tmp_105_fu_1252_p1 = col_assign_4_2_fu_1248_p2[1:0];
assign tmp_115_0_0_1_fu_1979_p2 = (src_kernel_win_0_val_2_1_fu_238 < src_kernel_win_0_val_2_2_fu_254? 1'b1: 1'b0);
assign tmp_115_0_0_2_fu_2352_p2 = (src_kernel_win_0_val_2_1_fu_238 < temp_0_i_i_i_057_i_i_1_0_0_1_reg_3575? 1'b1: 1'b0);
assign tmp_115_0_1_1_fu_2447_p2 = (ap_reg_ppstg_src_kernel_win_0_val_1_1_12_reg_3540_pp0_it8 < temp_0_i_i_i_057_i_i_1_0_1_fu_2442_p3? 1'b1: 1'b0);
assign tmp_115_0_1_2_fu_2496_p2 = (ap_reg_ppstg_src_kernel_win_0_val_1_1_lo_reg_3599_pp0_it9 < temp_0_i_i_i_057_i_i_1_0_1_1_reg_3674? 1'b1: 1'b0);
assign tmp_115_0_1_fu_2364_p2 = (src_kernel_win_0_val_1_2_fu_246 < temp_0_i_i_i_057_i_i_1_0_0_2_fu_2357_p3? 1'b1: 1'b0);
assign tmp_115_0_2_1_fu_2567_p2 = (ap_reg_ppstg_src_kernel_win_0_val_0_1_12_reg_3533_pp0_it10 < temp_0_i_i_i_057_i_i_1_0_2_fu_2562_p3? 1'b1: 1'b0);
assign tmp_115_0_2_2_fu_2613_p2 = (ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it11 < temp_0_i_i_i_057_i_i_1_0_2_1_reg_3737? 1'b1: 1'b0);
assign tmp_115_0_2_fu_2506_p2 = (src_kernel_win_0_val_0_2_fu_230 < temp_0_i_i_i_057_i_i_1_0_1_2_fu_2500_p3? 1'b1: 1'b0);
assign tmp_115_1_0_1_fu_2145_p2 = (src_kernel_win_1_val_2_1_fu_274 < src_kernel_win_1_val_2_2_fu_290? 1'b1: 1'b0);
assign tmp_115_1_0_2_fu_2382_p2 = (src_kernel_win_1_val_2_1_fu_274 < temp_0_i_i_i_057_i_i_1_1_0_1_reg_3581? 1'b1: 1'b0);
assign tmp_115_1_1_1_fu_2464_p2 = (ap_reg_ppstg_src_kernel_win_1_val_1_1_12_reg_3554_pp0_it8 < temp_0_i_i_i_057_i_i_1_1_1_fu_2459_p3? 1'b1: 1'b0);
assign tmp_115_1_1_2_fu_2515_p2 = (ap_reg_ppstg_src_kernel_win_1_val_1_1_lo_reg_3626_pp0_it9 < temp_0_i_i_i_057_i_i_1_1_1_1_reg_3680? 1'b1: 1'b0);
assign tmp_115_1_1_fu_2394_p2 = (src_kernel_win_1_val_1_2_fu_282 < temp_0_i_i_i_057_i_i_1_1_0_2_fu_2387_p3? 1'b1: 1'b0);
assign tmp_115_1_2_1_fu_2584_p2 = (ap_reg_ppstg_src_kernel_win_1_val_0_1_12_reg_3547_pp0_it10 < temp_0_i_i_i_057_i_i_1_1_2_fu_2579_p3? 1'b1: 1'b0);
assign tmp_115_1_2_2_fu_2624_p2 = (ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it11 < temp_0_i_i_i_057_i_i_1_1_2_1_reg_3743? 1'b1: 1'b0);
assign tmp_115_1_2_fu_2525_p2 = (src_kernel_win_1_val_0_2_fu_266 < temp_0_i_i_i_057_i_i_1_1_1_2_fu_2519_p3? 1'b1: 1'b0);
assign tmp_115_2_0_1_fu_2311_p2 = (src_kernel_win_2_val_2_1_fu_310 < src_kernel_win_2_val_2_2_fu_326? 1'b1: 1'b0);
assign tmp_115_2_0_2_fu_2412_p2 = (src_kernel_win_2_val_2_1_fu_310 < temp_0_i_i_i_057_i_i_1_2_0_1_reg_3587? 1'b1: 1'b0);
assign tmp_115_2_1_1_fu_2481_p2 = (ap_reg_ppstg_src_kernel_win_2_val_1_1_12_reg_3568_pp0_it8 < temp_0_i_i_i_057_i_i_1_2_1_fu_2476_p3? 1'b1: 1'b0);
assign tmp_115_2_1_2_fu_2534_p2 = (ap_reg_ppstg_src_kernel_win_2_val_1_1_lo_reg_3653_pp0_it9 < temp_0_i_i_i_057_i_i_1_2_1_1_reg_3686? 1'b1: 1'b0);
assign tmp_115_2_1_fu_2424_p2 = (src_kernel_win_2_val_1_2_fu_318 < temp_0_i_i_i_057_i_i_1_2_0_2_fu_2417_p3? 1'b1: 1'b0);
assign tmp_115_2_2_1_fu_2601_p2 = (ap_reg_ppstg_src_kernel_win_2_val_0_1_12_reg_3561_pp0_it10 < temp_0_i_i_i_057_i_i_1_2_2_fu_2596_p3? 1'b1: 1'b0);
assign tmp_115_2_2_2_fu_2635_p2 = (ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it11 < temp_0_i_i_i_057_i_i_1_2_2_1_reg_3749? 1'b1: 1'b0);
assign tmp_115_2_2_fu_2544_p2 = (src_kernel_win_2_val_0_2_fu_302 < temp_0_i_i_i_057_i_i_1_2_1_2_fu_2538_p3? 1'b1: 1'b0);
assign tmp_16_fu_896_p2 = (tmp_15_reg_612 + ap_const_lv2_1);
assign tmp_19_fu_908_p2 = (tmp_18_reg_623 + ap_const_lv2_1);
assign tmp_20_fu_914_p2 = (tmp_18_reg_623 == ap_const_lv2_2? 1'b1: 1'b0);
assign tmp_22_fu_920_p2 = (tmp_21_reg_634 + ap_const_lv2_1);
assign tmp_23_fu_926_p2 = (tmp_21_reg_634 == ap_const_lv2_2? 1'b1: 1'b0);
assign tmp_27_fu_942_p2 = ($signed(tmp_72_reg_2751) + $signed(ap_const_lv11_7FD));
assign tmp_28_cast_fu_947_p1 = tmp_27_fu_942_p2;
assign tmp_28_fu_977_p2 = (p_012_0_i_i_reg_645 < heightloop_reg_3051? 1'b1: 1'b0);
assign tmp_29_cast_cast3_fu_973_p1 = p_012_0_i_i_reg_645;
assign tmp_30_fu_988_p2 = (p_012_0_i_i_reg_645 > ap_const_lv11_4? 1'b1: 1'b0);
assign tmp_31_fu_1057_p2 = ($signed(ImagLoc_y_reg_3118) < $signed(12'b111111111111)? 1'b1: 1'b0);
assign tmp_32_fu_1035_p3 = ((tmp_58_2_fu_1016_p2)? ap_const_lv2_2: tmp_74_reg_3094);
assign tmp_33_cast_fu_1077_p1 = p_025_0_i_i_reg_656;
assign tmp_33_fu_1081_p2 = (p_025_0_i_i_reg_656 < widthloop_reg_3056? 1'b1: 1'b0);
assign tmp_35_fu_1287_p1 = $unsigned(x_ext_fu_1284_p1);
assign tmp_36_fu_1127_p2 = (p_025_0_i_i_reg_656 != ap_const_lv11_0? 1'b1: 1'b0);
assign tmp_37_fu_1133_p2 = ($signed(ImagLoc_x_cast2_fu_1123_p1) < $signed(cols_assign_cast1_reg_2757)? 1'b1: 1'b0);
assign tmp_38_fu_1152_p2 = ($signed(ImagLoc_x_fu_1113_p2) < $signed(tmp_28_cast_reg_3061)? 1'b1: 1'b0);
assign tmp_56_1_fu_1294_p1 = $signed(x_1_reg_3305);
assign tmp_56_2_fu_1300_p1 = $signed(x_2_reg_3317);
assign tmp_58_2_fu_1016_p2 = ($signed(ImagLoc_y_fu_994_p2) < $signed(ref_cast_reg_3089)? 1'b1: 1'b0);
assign tmp_61_1_fu_1162_p2 = (p_025_0_i_i_reg_656 != ap_const_lv11_0? 1'b1: 1'b0);
assign tmp_61_2_fu_1201_p2 = (p_025_0_i_i_reg_656 != ap_const_lv11_0? 1'b1: 1'b0);
assign tmp_63_1_fu_1168_p2 = ($signed(ImagLoc_x_cast2_fu_1123_p1) < $signed(cols_assign_cast1_reg_2757)? 1'b1: 1'b0);
assign tmp_63_2_fu_1207_p2 = ($signed(ImagLoc_x_cast2_fu_1123_p1) < $signed(cols_assign_cast1_reg_2757)? 1'b1: 1'b0);
assign tmp_66_1_fu_1187_p2 = ($signed(ImagLoc_x_fu_1113_p2) < $signed(tmp_28_cast_reg_3061)? 1'b1: 1'b0);
assign tmp_66_2_fu_1226_p2 = ($signed(ImagLoc_x_fu_1113_p2) < $signed(tmp_28_cast_reg_3061)? 1'b1: 1'b0);
assign tmp_72_fu_888_p1 = p_src_cols_V_read[10:0];
assign tmp_73_fu_956_p1 = p_neg226_i_i_fu_951_p2[1:0];
assign tmp_74_fu_969_p1 = ref_fu_960_p2[1:0];
assign tmp_75_fu_1000_p4 = {{ImagLoc_y_fu_994_p2[ap_const_lv32_B : ap_const_lv32_1]}};
assign tmp_78_fu_1049_p1 = p_i_i_fu_1042_p3[1:0];
assign tmp_79_fu_1053_p1 = p_i_i_fu_1042_p3[1:0];
assign tmp_80_fu_1092_p4 = {{p_025_0_i_i_reg_656[ap_const_lv32_A : ap_const_lv32_1]}};
assign tmp_82_fu_1119_p1 = ImagLoc_x_fu_1113_p2[1:0];
assign tmp_83_fu_1268_p1 = grp_image_filter_borderInterpolate_fu_692_ap_return[1:0];
assign tmp_85_fu_1311_p1 = grp_image_filter_borderInterpolate_fu_716_ap_return[1:0];
assign tmp_86_fu_1315_p1 = grp_image_filter_borderInterpolate_fu_724_ap_return[1:0];
assign tmp_87_fu_1256_p1 = grp_image_filter_borderInterpolate_fu_668_ap_return[1:0];
assign tmp_90_fu_1423_p1 = grp_image_filter_borderInterpolate_fu_732_ap_return[1:0];
assign tmp_91_fu_1427_p1 = grp_image_filter_borderInterpolate_fu_740_ap_return[1:0];
assign tmp_92_fu_1260_p1 = grp_image_filter_borderInterpolate_fu_676_ap_return[1:0];
assign tmp_93_fu_1197_p1 = col_assign_1_fu_1192_p2[1:0];
assign tmp_94_fu_1440_p3 = ap_reg_ppstg_x_1_reg_3305_pp0_it5[ap_const_lv32_E];
assign tmp_95_fu_1447_p1 = ap_reg_ppstg_x_1_reg_3305_pp0_it5[1:0];
assign tmp_96_fu_1244_p1 = col_assign_4_1_fu_1240_p2[1:0];
assign tmp_99_1_fu_1516_p1 = $unsigned(x_1_ext_fu_1415_p1);
assign tmp_99_2_fu_1702_p1 = $unsigned(x_2_ext_fu_1601_p1);
assign tmp_99_fu_1609_p1 = grp_image_filter_borderInterpolate_fu_748_ap_return[1:0];
assign tmp_fu_884_p1 = p_src_rows_V_read[10:0];
assign tmp_s_fu_902_p2 = (tmp_15_reg_612 == ap_const_lv2_2? 1'b1: 1'b0);
assign widthloop_fu_937_p2 = (tmp_72_reg_2751 + ap_const_lv11_2);
assign x_1_ext_fu_1415_p1 = $signed(ap_reg_ppstg_x_1_reg_3305_pp0_it5);
assign x_2_ext_fu_1601_p1 = $signed(ap_reg_ppstg_x_2_reg_3317_pp0_it5);
assign x_ext_fu_1284_p1 = $signed(x_reg_3291);
assign y_1_2_1_fu_1067_p2 = ($signed(tmp_29_cast_cast3_reg_3099) + $signed(ap_const_lv12_FFA));
assign y_1_2_fu_1062_p2 = ($signed(tmp_29_cast_cast3_reg_3099) + $signed(ap_const_lv12_FFB));
always @ (posedge ap_clk)
begin
cols_assign_cast1_reg_2757[12] <= 1'b0;
tmp_28_cast_reg_3061[11] <= 1'b0;
ref_cast_reg_3089[11] <= 1'b0;
tmp_29_cast_cast3_reg_3099[11] <= 1'b0;
end
endmodule //image_filter_Erode_32_32_1080_1920_s
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